1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[20];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 delim
= get_symbol_name (& name
);
2872 end_name
= input_line_pointer
;
2873 (void) restore_line_pointer (delim
);
2875 if (*input_line_pointer
!= ',')
2878 as_bad (_("expected comma after name \"%s\""), name
);
2880 ignore_rest_of_line ();
2884 input_line_pointer
++;
2887 if (name
[0] == '.' && name
[1] == '\0')
2889 /* XXX - this should not happen to .thumb_set. */
2893 if ((symbolP
= symbol_find (name
)) == NULL
2894 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2897 /* When doing symbol listings, play games with dummy fragments living
2898 outside the normal fragment chain to record the file and line info
2900 if (listing
& LISTING_SYMBOLS
)
2902 extern struct list_info_struct
* listing_tail
;
2903 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2905 memset (dummy_frag
, 0, sizeof (fragS
));
2906 dummy_frag
->fr_type
= rs_fill
;
2907 dummy_frag
->line
= listing_tail
;
2908 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2909 dummy_frag
->fr_symbol
= symbolP
;
2913 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2916 /* "set" symbols are local unless otherwise specified. */
2917 SF_SET_LOCAL (symbolP
);
2918 #endif /* OBJ_COFF */
2919 } /* Make a new symbol. */
2921 symbol_table_insert (symbolP
);
2926 && S_IS_DEFINED (symbolP
)
2927 && S_GET_SEGMENT (symbolP
) != reg_section
)
2928 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2930 pseudo_set (symbolP
);
2932 demand_empty_rest_of_line ();
2934 /* XXX Now we come to the Thumb specific bit of code. */
2936 THUMB_SET_FUNC (symbolP
, 1);
2937 ARM_SET_THUMB (symbolP
, 1);
2938 #if defined OBJ_ELF || defined OBJ_COFF
2939 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2943 /* Directives: Mode selection. */
2945 /* .syntax [unified|divided] - choose the new unified syntax
2946 (same for Arm and Thumb encoding, modulo slight differences in what
2947 can be represented) or the old divergent syntax for each mode. */
2949 s_syntax (int unused ATTRIBUTE_UNUSED
)
2953 delim
= get_symbol_name (& name
);
2955 if (!strcasecmp (name
, "unified"))
2956 unified_syntax
= TRUE
;
2957 else if (!strcasecmp (name
, "divided"))
2958 unified_syntax
= FALSE
;
2961 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2964 (void) restore_line_pointer (delim
);
2965 demand_empty_rest_of_line ();
2968 /* Directives: sectioning and alignment. */
2971 s_bss (int ignore ATTRIBUTE_UNUSED
)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section
, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED
)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg
, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: CodeComposer Studio. */
2997 /* .ref (for CodeComposer Studio syntax only). */
2999 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3001 if (codecomposer_syntax
)
3002 ignore_rest_of_line ();
3004 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3007 /* If name is not NULL, then it is used for marking the beginning of a
3008 function, wherease if it is NULL then it means the function end. */
3010 asmfunc_debug (const char * name
)
3012 static const char * last_name
= NULL
;
3016 gas_assert (last_name
== NULL
);
3019 if (debug_type
== DEBUG_STABS
)
3020 stabs_generate_asm_func (name
, name
);
3024 gas_assert (last_name
!= NULL
);
3026 if (debug_type
== DEBUG_STABS
)
3027 stabs_generate_asm_endfunc (last_name
, last_name
);
3034 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3036 if (codecomposer_syntax
)
3038 switch (asmfunc_state
)
3040 case OUTSIDE_ASMFUNC
:
3041 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3044 case WAITING_ASMFUNC_NAME
:
3045 as_bad (_(".asmfunc repeated."));
3048 case WAITING_ENDASMFUNC
:
3049 as_bad (_(".asmfunc without function."));
3052 demand_empty_rest_of_line ();
3055 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3059 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3061 if (codecomposer_syntax
)
3063 switch (asmfunc_state
)
3065 case OUTSIDE_ASMFUNC
:
3066 as_bad (_(".endasmfunc without a .asmfunc."));
3069 case WAITING_ASMFUNC_NAME
:
3070 as_bad (_(".endasmfunc without function."));
3073 case WAITING_ENDASMFUNC
:
3074 asmfunc_state
= OUTSIDE_ASMFUNC
;
3075 asmfunc_debug (NULL
);
3078 demand_empty_rest_of_line ();
3081 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3085 s_ccs_def (int name
)
3087 if (codecomposer_syntax
)
3090 as_bad (_(".def pseudo-op only available with -mccs flag."));
3093 /* Directives: Literal pools. */
3095 static literal_pool
*
3096 find_literal_pool (void)
3098 literal_pool
* pool
;
3100 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3102 if (pool
->section
== now_seg
3103 && pool
->sub_section
== now_subseg
)
3110 static literal_pool
*
3111 find_or_make_literal_pool (void)
3113 /* Next literal pool ID number. */
3114 static unsigned int latest_pool_num
= 1;
3115 literal_pool
* pool
;
3117 pool
= find_literal_pool ();
3121 /* Create a new pool. */
3122 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3126 pool
->next_free_entry
= 0;
3127 pool
->section
= now_seg
;
3128 pool
->sub_section
= now_subseg
;
3129 pool
->next
= list_of_pools
;
3130 pool
->symbol
= NULL
;
3131 pool
->alignment
= 2;
3133 /* Add it to the list. */
3134 list_of_pools
= pool
;
3137 /* New pools, and emptied pools, will have a NULL symbol. */
3138 if (pool
->symbol
== NULL
)
3140 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3141 (valueT
) 0, &zero_address_frag
);
3142 pool
->id
= latest_pool_num
++;
3149 /* Add the literal in the global 'inst'
3150 structure to the relevant literal pool. */
3153 add_to_lit_pool (unsigned int nbytes
)
3155 #define PADDING_SLOT 0x1
3156 #define LIT_ENTRY_SIZE_MASK 0xFF
3157 literal_pool
* pool
;
3158 unsigned int entry
, pool_size
= 0;
3159 bfd_boolean padding_slot_p
= FALSE
;
3165 imm1
= inst
.operands
[1].imm
;
3166 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3167 : inst
.reloc
.exp
.X_unsigned
? 0
3168 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3169 if (target_big_endian
)
3172 imm2
= inst
.operands
[1].imm
;
3176 pool
= find_or_make_literal_pool ();
3178 /* Check if this literal value is already in the pool. */
3179 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3183 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3184 && (inst
.reloc
.exp
.X_op
== O_constant
)
3185 && (pool
->literals
[entry
].X_add_number
3186 == inst
.reloc
.exp
.X_add_number
)
3187 && (pool
->literals
[entry
].X_md
== nbytes
)
3188 && (pool
->literals
[entry
].X_unsigned
3189 == inst
.reloc
.exp
.X_unsigned
))
3192 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3193 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3194 && (pool
->literals
[entry
].X_add_number
3195 == inst
.reloc
.exp
.X_add_number
)
3196 && (pool
->literals
[entry
].X_add_symbol
3197 == inst
.reloc
.exp
.X_add_symbol
)
3198 && (pool
->literals
[entry
].X_op_symbol
3199 == inst
.reloc
.exp
.X_op_symbol
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
))
3203 else if ((nbytes
== 8)
3204 && !(pool_size
& 0x7)
3205 && ((entry
+ 1) != pool
->next_free_entry
)
3206 && (pool
->literals
[entry
].X_op
== O_constant
)
3207 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3208 && (pool
->literals
[entry
].X_unsigned
3209 == inst
.reloc
.exp
.X_unsigned
)
3210 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3211 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3212 && (pool
->literals
[entry
+ 1].X_unsigned
3213 == inst
.reloc
.exp
.X_unsigned
))
3216 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3217 if (padding_slot_p
&& (nbytes
== 4))
3223 /* Do we need to create a new entry? */
3224 if (entry
== pool
->next_free_entry
)
3226 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3228 inst
.error
= _("literal pool overflow");
3234 /* For 8-byte entries, we align to an 8-byte boundary,
3235 and split it into two 4-byte entries, because on 32-bit
3236 host, 8-byte constants are treated as big num, thus
3237 saved in "generic_bignum" which will be overwritten
3238 by later assignments.
3240 We also need to make sure there is enough space for
3243 We also check to make sure the literal operand is a
3245 if (!(inst
.reloc
.exp
.X_op
== O_constant
3246 || inst
.reloc
.exp
.X_op
== O_big
))
3248 inst
.error
= _("invalid type for literal pool");
3251 else if (pool_size
& 0x7)
3253 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3255 inst
.error
= _("literal pool overflow");
3259 pool
->literals
[entry
] = inst
.reloc
.exp
;
3260 pool
->literals
[entry
].X_add_number
= 0;
3261 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3262 pool
->next_free_entry
+= 1;
3265 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3267 inst
.error
= _("literal pool overflow");
3271 pool
->literals
[entry
] = inst
.reloc
.exp
;
3272 pool
->literals
[entry
].X_op
= O_constant
;
3273 pool
->literals
[entry
].X_add_number
= imm1
;
3274 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3275 pool
->literals
[entry
++].X_md
= 4;
3276 pool
->literals
[entry
] = inst
.reloc
.exp
;
3277 pool
->literals
[entry
].X_op
= O_constant
;
3278 pool
->literals
[entry
].X_add_number
= imm2
;
3279 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3280 pool
->literals
[entry
].X_md
= 4;
3281 pool
->alignment
= 3;
3282 pool
->next_free_entry
+= 1;
3286 pool
->literals
[entry
] = inst
.reloc
.exp
;
3287 pool
->literals
[entry
].X_md
= 4;
3291 /* PR ld/12974: Record the location of the first source line to reference
3292 this entry in the literal pool. If it turns out during linking that the
3293 symbol does not exist we will be able to give an accurate line number for
3294 the (first use of the) missing reference. */
3295 if (debug_type
== DEBUG_DWARF2
)
3296 dwarf2_where (pool
->locs
+ entry
);
3298 pool
->next_free_entry
+= 1;
3300 else if (padding_slot_p
)
3302 pool
->literals
[entry
] = inst
.reloc
.exp
;
3303 pool
->literals
[entry
].X_md
= nbytes
;
3306 inst
.reloc
.exp
.X_op
= O_symbol
;
3307 inst
.reloc
.exp
.X_add_number
= pool_size
;
3308 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3314 tc_start_label_without_colon (void)
3316 bfd_boolean ret
= TRUE
;
3318 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3320 const char *label
= input_line_pointer
;
3322 while (!is_end_of_line
[(int) label
[-1]])
3327 as_bad (_("Invalid label '%s'"), label
);
3331 asmfunc_debug (label
);
3333 asmfunc_state
= WAITING_ENDASMFUNC
;
3339 /* Can't use symbol_new here, so have to create a symbol and then at
3340 a later date assign it a value. Thats what these functions do. */
3343 symbol_locate (symbolS
* symbolP
,
3344 const char * name
, /* It is copied, the caller can modify. */
3345 segT segment
, /* Segment identifier (SEG_<something>). */
3346 valueT valu
, /* Symbol value. */
3347 fragS
* frag
) /* Associated fragment. */
3350 char * preserved_copy_of_name
;
3352 name_length
= strlen (name
) + 1; /* +1 for \0. */
3353 obstack_grow (¬es
, name
, name_length
);
3354 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3356 #ifdef tc_canonicalize_symbol_name
3357 preserved_copy_of_name
=
3358 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3361 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3363 S_SET_SEGMENT (symbolP
, segment
);
3364 S_SET_VALUE (symbolP
, valu
);
3365 symbol_clear_list_pointers (symbolP
);
3367 symbol_set_frag (symbolP
, frag
);
3369 /* Link to end of symbol chain. */
3371 extern int symbol_table_frozen
;
3373 if (symbol_table_frozen
)
3377 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3379 obj_symbol_new_hook (symbolP
);
3381 #ifdef tc_symbol_new_hook
3382 tc_symbol_new_hook (symbolP
);
3386 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3387 #endif /* DEBUG_SYMS */
3391 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3394 literal_pool
* pool
;
3397 pool
= find_literal_pool ();
3399 || pool
->symbol
== NULL
3400 || pool
->next_free_entry
== 0)
3403 /* Align pool as you have word accesses.
3404 Only make a frag if we have to. */
3406 frag_align (pool
->alignment
, 0, 0);
3408 record_alignment (now_seg
, 2);
3411 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3412 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3414 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3416 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3417 (valueT
) frag_now_fix (), frag_now
);
3418 symbol_table_insert (pool
->symbol
);
3420 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3422 #if defined OBJ_COFF || defined OBJ_ELF
3423 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3426 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3429 if (debug_type
== DEBUG_DWARF2
)
3430 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3432 /* First output the expression in the instruction to the pool. */
3433 emit_expr (&(pool
->literals
[entry
]),
3434 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3437 /* Mark the pool as empty. */
3438 pool
->next_free_entry
= 0;
3439 pool
->symbol
= NULL
;
3443 /* Forward declarations for functions below, in the MD interface
3445 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3446 static valueT
create_unwind_entry (int);
3447 static void start_unwind_section (const segT
, int);
3448 static void add_unwind_opcode (valueT
, int);
3449 static void flush_pending_unwind (void);
3451 /* Directives: Data. */
3454 s_arm_elf_cons (int nbytes
)
3458 #ifdef md_flush_pending_output
3459 md_flush_pending_output ();
3462 if (is_it_end_of_statement ())
3464 demand_empty_rest_of_line ();
3468 #ifdef md_cons_align
3469 md_cons_align (nbytes
);
3472 mapping_state (MAP_DATA
);
3476 char *base
= input_line_pointer
;
3480 if (exp
.X_op
!= O_symbol
)
3481 emit_expr (&exp
, (unsigned int) nbytes
);
3484 char *before_reloc
= input_line_pointer
;
3485 reloc
= parse_reloc (&input_line_pointer
);
3488 as_bad (_("unrecognized relocation suffix"));
3489 ignore_rest_of_line ();
3492 else if (reloc
== BFD_RELOC_UNUSED
)
3493 emit_expr (&exp
, (unsigned int) nbytes
);
3496 reloc_howto_type
*howto
= (reloc_howto_type
*)
3497 bfd_reloc_type_lookup (stdoutput
,
3498 (bfd_reloc_code_real_type
) reloc
);
3499 int size
= bfd_get_reloc_size (howto
);
3501 if (reloc
== BFD_RELOC_ARM_PLT32
)
3503 as_bad (_("(plt) is only valid on branch targets"));
3504 reloc
= BFD_RELOC_UNUSED
;
3509 as_bad (_("%s relocations do not fit in %d bytes"),
3510 howto
->name
, nbytes
);
3513 /* We've parsed an expression stopping at O_symbol.
3514 But there may be more expression left now that we
3515 have parsed the relocation marker. Parse it again.
3516 XXX Surely there is a cleaner way to do this. */
3517 char *p
= input_line_pointer
;
3519 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3520 memcpy (save_buf
, base
, input_line_pointer
- base
);
3521 memmove (base
+ (input_line_pointer
- before_reloc
),
3522 base
, before_reloc
- base
);
3524 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3526 memcpy (base
, save_buf
, p
- base
);
3528 offset
= nbytes
- size
;
3529 p
= frag_more (nbytes
);
3530 memset (p
, 0, nbytes
);
3531 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3532 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3537 while (*input_line_pointer
++ == ',');
3539 /* Put terminator back into stream. */
3540 input_line_pointer
--;
3541 demand_empty_rest_of_line ();
3544 /* Emit an expression containing a 32-bit thumb instruction.
3545 Implementation based on put_thumb32_insn. */
3548 emit_thumb32_expr (expressionS
* exp
)
3550 expressionS exp_high
= *exp
;
3552 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3553 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3554 exp
->X_add_number
&= 0xffff;
3555 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3558 /* Guess the instruction size based on the opcode. */
3561 thumb_insn_size (int opcode
)
3563 if ((unsigned int) opcode
< 0xe800u
)
3565 else if ((unsigned int) opcode
>= 0xe8000000u
)
3572 emit_insn (expressionS
*exp
, int nbytes
)
3576 if (exp
->X_op
== O_constant
)
3581 size
= thumb_insn_size (exp
->X_add_number
);
3585 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3587 as_bad (_(".inst.n operand too big. "\
3588 "Use .inst.w instead"));
3593 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3594 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3596 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3598 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3599 emit_thumb32_expr (exp
);
3601 emit_expr (exp
, (unsigned int) size
);
3603 it_fsm_post_encode ();
3607 as_bad (_("cannot determine Thumb instruction size. " \
3608 "Use .inst.n/.inst.w instead"));
3611 as_bad (_("constant expression required"));
3616 /* Like s_arm_elf_cons but do not use md_cons_align and
3617 set the mapping state to MAP_ARM/MAP_THUMB. */
3620 s_arm_elf_inst (int nbytes
)
3622 if (is_it_end_of_statement ())
3624 demand_empty_rest_of_line ();
3628 /* Calling mapping_state () here will not change ARM/THUMB,
3629 but will ensure not to be in DATA state. */
3632 mapping_state (MAP_THUMB
);
3637 as_bad (_("width suffixes are invalid in ARM mode"));
3638 ignore_rest_of_line ();
3644 mapping_state (MAP_ARM
);
3653 if (! emit_insn (& exp
, nbytes
))
3655 ignore_rest_of_line ();
3659 while (*input_line_pointer
++ == ',');
3661 /* Put terminator back into stream. */
3662 input_line_pointer
--;
3663 demand_empty_rest_of_line ();
3666 /* Parse a .rel31 directive. */
3669 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3676 if (*input_line_pointer
== '1')
3677 highbit
= 0x80000000;
3678 else if (*input_line_pointer
!= '0')
3679 as_bad (_("expected 0 or 1"));
3681 input_line_pointer
++;
3682 if (*input_line_pointer
!= ',')
3683 as_bad (_("missing comma"));
3684 input_line_pointer
++;
3686 #ifdef md_flush_pending_output
3687 md_flush_pending_output ();
3690 #ifdef md_cons_align
3694 mapping_state (MAP_DATA
);
3699 md_number_to_chars (p
, highbit
, 4);
3700 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3701 BFD_RELOC_ARM_PREL31
);
3703 demand_empty_rest_of_line ();
3706 /* Directives: AEABI stack-unwind tables. */
3708 /* Parse an unwind_fnstart directive. Simply records the current location. */
3711 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3713 demand_empty_rest_of_line ();
3714 if (unwind
.proc_start
)
3716 as_bad (_("duplicate .fnstart directive"));
3720 /* Mark the start of the function. */
3721 unwind
.proc_start
= expr_build_dot ();
3723 /* Reset the rest of the unwind info. */
3724 unwind
.opcode_count
= 0;
3725 unwind
.table_entry
= NULL
;
3726 unwind
.personality_routine
= NULL
;
3727 unwind
.personality_index
= -1;
3728 unwind
.frame_size
= 0;
3729 unwind
.fp_offset
= 0;
3730 unwind
.fp_reg
= REG_SP
;
3732 unwind
.sp_restored
= 0;
3736 /* Parse a handlerdata directive. Creates the exception handling table entry
3737 for the function. */
3740 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3742 demand_empty_rest_of_line ();
3743 if (!unwind
.proc_start
)
3744 as_bad (MISSING_FNSTART
);
3746 if (unwind
.table_entry
)
3747 as_bad (_("duplicate .handlerdata directive"));
3749 create_unwind_entry (1);
3752 /* Parse an unwind_fnend directive. Generates the index table entry. */
3755 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3760 unsigned int marked_pr_dependency
;
3762 demand_empty_rest_of_line ();
3764 if (!unwind
.proc_start
)
3766 as_bad (_(".fnend directive without .fnstart"));
3770 /* Add eh table entry. */
3771 if (unwind
.table_entry
== NULL
)
3772 val
= create_unwind_entry (0);
3776 /* Add index table entry. This is two words. */
3777 start_unwind_section (unwind
.saved_seg
, 1);
3778 frag_align (2, 0, 0);
3779 record_alignment (now_seg
, 2);
3781 ptr
= frag_more (8);
3783 where
= frag_now_fix () - 8;
3785 /* Self relative offset of the function start. */
3786 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3787 BFD_RELOC_ARM_PREL31
);
3789 /* Indicate dependency on EHABI-defined personality routines to the
3790 linker, if it hasn't been done already. */
3791 marked_pr_dependency
3792 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3793 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3794 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3796 static const char *const name
[] =
3798 "__aeabi_unwind_cpp_pr0",
3799 "__aeabi_unwind_cpp_pr1",
3800 "__aeabi_unwind_cpp_pr2"
3802 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3803 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3804 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3805 |= 1 << unwind
.personality_index
;
3809 /* Inline exception table entry. */
3810 md_number_to_chars (ptr
+ 4, val
, 4);
3812 /* Self relative offset of the table entry. */
3813 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3814 BFD_RELOC_ARM_PREL31
);
3816 /* Restore the original section. */
3817 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3819 unwind
.proc_start
= NULL
;
3823 /* Parse an unwind_cantunwind directive. */
3826 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3828 demand_empty_rest_of_line ();
3829 if (!unwind
.proc_start
)
3830 as_bad (MISSING_FNSTART
);
3832 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3833 as_bad (_("personality routine specified for cantunwind frame"));
3835 unwind
.personality_index
= -2;
3839 /* Parse a personalityindex directive. */
3842 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3846 if (!unwind
.proc_start
)
3847 as_bad (MISSING_FNSTART
);
3849 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3850 as_bad (_("duplicate .personalityindex directive"));
3854 if (exp
.X_op
!= O_constant
3855 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3857 as_bad (_("bad personality routine number"));
3858 ignore_rest_of_line ();
3862 unwind
.personality_index
= exp
.X_add_number
;
3864 demand_empty_rest_of_line ();
3868 /* Parse a personality directive. */
3871 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3875 if (!unwind
.proc_start
)
3876 as_bad (MISSING_FNSTART
);
3878 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3879 as_bad (_("duplicate .personality directive"));
3881 c
= get_symbol_name (& name
);
3882 p
= input_line_pointer
;
3884 ++ input_line_pointer
;
3885 unwind
.personality_routine
= symbol_find_or_make (name
);
3887 demand_empty_rest_of_line ();
3891 /* Parse a directive saving core registers. */
3894 s_arm_unwind_save_core (void)
3900 range
= parse_reg_list (&input_line_pointer
);
3903 as_bad (_("expected register list"));
3904 ignore_rest_of_line ();
3908 demand_empty_rest_of_line ();
3910 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3911 into .unwind_save {..., sp...}. We aren't bothered about the value of
3912 ip because it is clobbered by calls. */
3913 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3914 && (range
& 0x3000) == 0x1000)
3916 unwind
.opcode_count
--;
3917 unwind
.sp_restored
= 0;
3918 range
= (range
| 0x2000) & ~0x1000;
3919 unwind
.pending_offset
= 0;
3925 /* See if we can use the short opcodes. These pop a block of up to 8
3926 registers starting with r4, plus maybe r14. */
3927 for (n
= 0; n
< 8; n
++)
3929 /* Break at the first non-saved register. */
3930 if ((range
& (1 << (n
+ 4))) == 0)
3933 /* See if there are any other bits set. */
3934 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3936 /* Use the long form. */
3937 op
= 0x8000 | ((range
>> 4) & 0xfff);
3938 add_unwind_opcode (op
, 2);
3942 /* Use the short form. */
3944 op
= 0xa8; /* Pop r14. */
3946 op
= 0xa0; /* Do not pop r14. */
3948 add_unwind_opcode (op
, 1);
3955 op
= 0xb100 | (range
& 0xf);
3956 add_unwind_opcode (op
, 2);
3959 /* Record the number of bytes pushed. */
3960 for (n
= 0; n
< 16; n
++)
3962 if (range
& (1 << n
))
3963 unwind
.frame_size
+= 4;
3968 /* Parse a directive saving FPA registers. */
3971 s_arm_unwind_save_fpa (int reg
)
3977 /* Get Number of registers to transfer. */
3978 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3981 exp
.X_op
= O_illegal
;
3983 if (exp
.X_op
!= O_constant
)
3985 as_bad (_("expected , <constant>"));
3986 ignore_rest_of_line ();
3990 num_regs
= exp
.X_add_number
;
3992 if (num_regs
< 1 || num_regs
> 4)
3994 as_bad (_("number of registers must be in the range [1:4]"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4004 op
= 0xb4 | (num_regs
- 1);
4005 add_unwind_opcode (op
, 1);
4010 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4011 add_unwind_opcode (op
, 2);
4013 unwind
.frame_size
+= num_regs
* 12;
4017 /* Parse a directive saving VFP registers for ARMv6 and above. */
4020 s_arm_unwind_save_vfp_armv6 (void)
4025 int num_vfpv3_regs
= 0;
4026 int num_regs_below_16
;
4028 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4031 as_bad (_("expected register list"));
4032 ignore_rest_of_line ();
4036 demand_empty_rest_of_line ();
4038 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4039 than FSTMX/FLDMX-style ones). */
4041 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4043 num_vfpv3_regs
= count
;
4044 else if (start
+ count
> 16)
4045 num_vfpv3_regs
= start
+ count
- 16;
4047 if (num_vfpv3_regs
> 0)
4049 int start_offset
= start
> 16 ? start
- 16 : 0;
4050 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4051 add_unwind_opcode (op
, 2);
4054 /* Generate opcode for registers numbered in the range 0 .. 15. */
4055 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4056 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4057 if (num_regs_below_16
> 0)
4059 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4060 add_unwind_opcode (op
, 2);
4063 unwind
.frame_size
+= count
* 8;
4067 /* Parse a directive saving VFP registers for pre-ARMv6. */
4070 s_arm_unwind_save_vfp (void)
4076 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4089 op
= 0xb8 | (count
- 1);
4090 add_unwind_opcode (op
, 1);
4095 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4096 add_unwind_opcode (op
, 2);
4098 unwind
.frame_size
+= count
* 8 + 4;
4102 /* Parse a directive saving iWMMXt data registers. */
4105 s_arm_unwind_save_mmxwr (void)
4113 if (*input_line_pointer
== '{')
4114 input_line_pointer
++;
4118 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4122 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4127 as_tsktsk (_("register list not in ascending order"));
4130 if (*input_line_pointer
== '-')
4132 input_line_pointer
++;
4133 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4136 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4139 else if (reg
>= hi_reg
)
4141 as_bad (_("bad register range"));
4144 for (; reg
< hi_reg
; reg
++)
4148 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4150 skip_past_char (&input_line_pointer
, '}');
4152 demand_empty_rest_of_line ();
4154 /* Generate any deferred opcodes because we're going to be looking at
4156 flush_pending_unwind ();
4158 for (i
= 0; i
< 16; i
++)
4160 if (mask
& (1 << i
))
4161 unwind
.frame_size
+= 8;
4164 /* Attempt to combine with a previous opcode. We do this because gcc
4165 likes to output separate unwind directives for a single block of
4167 if (unwind
.opcode_count
> 0)
4169 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4170 if ((i
& 0xf8) == 0xc0)
4173 /* Only merge if the blocks are contiguous. */
4176 if ((mask
& 0xfe00) == (1 << 9))
4178 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4179 unwind
.opcode_count
--;
4182 else if (i
== 6 && unwind
.opcode_count
>= 2)
4184 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4188 op
= 0xffff << (reg
- 1);
4190 && ((mask
& op
) == (1u << (reg
- 1))))
4192 op
= (1 << (reg
+ i
+ 1)) - 1;
4193 op
&= ~((1 << reg
) - 1);
4195 unwind
.opcode_count
-= 2;
4202 /* We want to generate opcodes in the order the registers have been
4203 saved, ie. descending order. */
4204 for (reg
= 15; reg
>= -1; reg
--)
4206 /* Save registers in blocks. */
4208 || !(mask
& (1 << reg
)))
4210 /* We found an unsaved reg. Generate opcodes to save the
4217 op
= 0xc0 | (hi_reg
- 10);
4218 add_unwind_opcode (op
, 1);
4223 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4224 add_unwind_opcode (op
, 2);
4233 ignore_rest_of_line ();
4237 s_arm_unwind_save_mmxwcg (void)
4244 if (*input_line_pointer
== '{')
4245 input_line_pointer
++;
4247 skip_whitespace (input_line_pointer
);
4251 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4255 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4261 as_tsktsk (_("register list not in ascending order"));
4264 if (*input_line_pointer
== '-')
4266 input_line_pointer
++;
4267 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4270 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4273 else if (reg
>= hi_reg
)
4275 as_bad (_("bad register range"));
4278 for (; reg
< hi_reg
; reg
++)
4282 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4284 skip_past_char (&input_line_pointer
, '}');
4286 demand_empty_rest_of_line ();
4288 /* Generate any deferred opcodes because we're going to be looking at
4290 flush_pending_unwind ();
4292 for (reg
= 0; reg
< 16; reg
++)
4294 if (mask
& (1 << reg
))
4295 unwind
.frame_size
+= 4;
4298 add_unwind_opcode (op
, 2);
4301 ignore_rest_of_line ();
4305 /* Parse an unwind_save directive.
4306 If the argument is non-zero, this is a .vsave directive. */
4309 s_arm_unwind_save (int arch_v6
)
4312 struct reg_entry
*reg
;
4313 bfd_boolean had_brace
= FALSE
;
4315 if (!unwind
.proc_start
)
4316 as_bad (MISSING_FNSTART
);
4318 /* Figure out what sort of save we have. */
4319 peek
= input_line_pointer
;
4327 reg
= arm_reg_parse_multi (&peek
);
4331 as_bad (_("register expected"));
4332 ignore_rest_of_line ();
4341 as_bad (_("FPA .unwind_save does not take a register list"));
4342 ignore_rest_of_line ();
4345 input_line_pointer
= peek
;
4346 s_arm_unwind_save_fpa (reg
->number
);
4350 s_arm_unwind_save_core ();
4355 s_arm_unwind_save_vfp_armv6 ();
4357 s_arm_unwind_save_vfp ();
4360 case REG_TYPE_MMXWR
:
4361 s_arm_unwind_save_mmxwr ();
4364 case REG_TYPE_MMXWCG
:
4365 s_arm_unwind_save_mmxwcg ();
4369 as_bad (_(".unwind_save does not support this kind of register"));
4370 ignore_rest_of_line ();
4375 /* Parse an unwind_movsp directive. */
4378 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4384 if (!unwind
.proc_start
)
4385 as_bad (MISSING_FNSTART
);
4387 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4390 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4391 ignore_rest_of_line ();
4395 /* Optional constant. */
4396 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4398 if (immediate_for_directive (&offset
) == FAIL
)
4404 demand_empty_rest_of_line ();
4406 if (reg
== REG_SP
|| reg
== REG_PC
)
4408 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4412 if (unwind
.fp_reg
!= REG_SP
)
4413 as_bad (_("unexpected .unwind_movsp directive"));
4415 /* Generate opcode to restore the value. */
4417 add_unwind_opcode (op
, 1);
4419 /* Record the information for later. */
4420 unwind
.fp_reg
= reg
;
4421 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4422 unwind
.sp_restored
= 1;
4425 /* Parse an unwind_pad directive. */
4428 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 if (immediate_for_directive (&offset
) == FAIL
)
4440 as_bad (_("stack increment must be multiple of 4"));
4441 ignore_rest_of_line ();
4445 /* Don't generate any opcodes, just record the details for later. */
4446 unwind
.frame_size
+= offset
;
4447 unwind
.pending_offset
+= offset
;
4449 demand_empty_rest_of_line ();
4452 /* Parse an unwind_setfp directive. */
4455 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4461 if (!unwind
.proc_start
)
4462 as_bad (MISSING_FNSTART
);
4464 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4465 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4468 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4472 as_bad (_("expected <reg>, <reg>"));
4473 ignore_rest_of_line ();
4477 /* Optional constant. */
4478 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4480 if (immediate_for_directive (&offset
) == FAIL
)
4486 demand_empty_rest_of_line ();
4488 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4490 as_bad (_("register must be either sp or set by a previous"
4491 "unwind_movsp directive"));
4495 /* Don't generate any opcodes, just record the information for later. */
4496 unwind
.fp_reg
= fp_reg
;
4498 if (sp_reg
== REG_SP
)
4499 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4501 unwind
.fp_offset
-= offset
;
4504 /* Parse an unwind_raw directive. */
4507 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4510 /* This is an arbitrary limit. */
4511 unsigned char op
[16];
4514 if (!unwind
.proc_start
)
4515 as_bad (MISSING_FNSTART
);
4518 if (exp
.X_op
== O_constant
4519 && skip_past_comma (&input_line_pointer
) != FAIL
)
4521 unwind
.frame_size
+= exp
.X_add_number
;
4525 exp
.X_op
= O_illegal
;
4527 if (exp
.X_op
!= O_constant
)
4529 as_bad (_("expected <offset>, <opcode>"));
4530 ignore_rest_of_line ();
4536 /* Parse the opcode. */
4541 as_bad (_("unwind opcode too long"));
4542 ignore_rest_of_line ();
4544 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4546 as_bad (_("invalid unwind opcode"));
4547 ignore_rest_of_line ();
4550 op
[count
++] = exp
.X_add_number
;
4552 /* Parse the next byte. */
4553 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 /* Add the opcode bytes in reverse order. */
4561 add_unwind_opcode (op
[count
], 1);
4563 demand_empty_rest_of_line ();
4567 /* Parse a .eabi_attribute directive. */
4570 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4572 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4574 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4575 attributes_set_explicitly
[tag
] = 1;
4578 /* Emit a tls fix for the symbol. */
4581 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4585 #ifdef md_flush_pending_output
4586 md_flush_pending_output ();
4589 #ifdef md_cons_align
4593 /* Since we're just labelling the code, there's no need to define a
4596 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4597 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4598 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4599 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4601 #endif /* OBJ_ELF */
4603 static void s_arm_arch (int);
4604 static void s_arm_object_arch (int);
4605 static void s_arm_cpu (int);
4606 static void s_arm_fpu (int);
4607 static void s_arm_arch_extension (int);
4612 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4619 if (exp
.X_op
== O_symbol
)
4620 exp
.X_op
= O_secrel
;
4622 emit_expr (&exp
, 4);
4624 while (*input_line_pointer
++ == ',');
4626 input_line_pointer
--;
4627 demand_empty_rest_of_line ();
4631 /* This table describes all the machine specific pseudo-ops the assembler
4632 has to support. The fields are:
4633 pseudo-op name without dot
4634 function to call to execute this pseudo-op
4635 Integer arg to pass to the function. */
4637 const pseudo_typeS md_pseudo_table
[] =
4639 /* Never called because '.req' does not start a line. */
4640 { "req", s_req
, 0 },
4641 /* Following two are likewise never called. */
4644 { "unreq", s_unreq
, 0 },
4645 { "bss", s_bss
, 0 },
4646 { "align", s_align_ptwo
, 2 },
4647 { "arm", s_arm
, 0 },
4648 { "thumb", s_thumb
, 0 },
4649 { "code", s_code
, 0 },
4650 { "force_thumb", s_force_thumb
, 0 },
4651 { "thumb_func", s_thumb_func
, 0 },
4652 { "thumb_set", s_thumb_set
, 0 },
4653 { "even", s_even
, 0 },
4654 { "ltorg", s_ltorg
, 0 },
4655 { "pool", s_ltorg
, 0 },
4656 { "syntax", s_syntax
, 0 },
4657 { "cpu", s_arm_cpu
, 0 },
4658 { "arch", s_arm_arch
, 0 },
4659 { "object_arch", s_arm_object_arch
, 0 },
4660 { "fpu", s_arm_fpu
, 0 },
4661 { "arch_extension", s_arm_arch_extension
, 0 },
4663 { "word", s_arm_elf_cons
, 4 },
4664 { "long", s_arm_elf_cons
, 4 },
4665 { "inst.n", s_arm_elf_inst
, 2 },
4666 { "inst.w", s_arm_elf_inst
, 4 },
4667 { "inst", s_arm_elf_inst
, 0 },
4668 { "rel31", s_arm_rel31
, 0 },
4669 { "fnstart", s_arm_unwind_fnstart
, 0 },
4670 { "fnend", s_arm_unwind_fnend
, 0 },
4671 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4672 { "personality", s_arm_unwind_personality
, 0 },
4673 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4674 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4675 { "save", s_arm_unwind_save
, 0 },
4676 { "vsave", s_arm_unwind_save
, 1 },
4677 { "movsp", s_arm_unwind_movsp
, 0 },
4678 { "pad", s_arm_unwind_pad
, 0 },
4679 { "setfp", s_arm_unwind_setfp
, 0 },
4680 { "unwind_raw", s_arm_unwind_raw
, 0 },
4681 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4682 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4686 /* These are used for dwarf. */
4690 /* These are used for dwarf2. */
4691 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4692 { "loc", dwarf2_directive_loc
, 0 },
4693 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4695 { "extend", float_cons
, 'x' },
4696 { "ldouble", float_cons
, 'x' },
4697 { "packed", float_cons
, 'p' },
4699 {"secrel32", pe_directive_secrel
, 0},
4702 /* These are for compatibility with CodeComposer Studio. */
4703 {"ref", s_ccs_ref
, 0},
4704 {"def", s_ccs_def
, 0},
4705 {"asmfunc", s_ccs_asmfunc
, 0},
4706 {"endasmfunc", s_ccs_endasmfunc
, 0},
4711 /* Parser functions used exclusively in instruction operands. */
4713 /* Generic immediate-value read function for use in insn parsing.
4714 STR points to the beginning of the immediate (the leading #);
4715 VAL receives the value; if the value is outside [MIN, MAX]
4716 issue an error. PREFIX_OPT is true if the immediate prefix is
4720 parse_immediate (char **str
, int *val
, int min
, int max
,
4721 bfd_boolean prefix_opt
)
4724 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4725 if (exp
.X_op
!= O_constant
)
4727 inst
.error
= _("constant expression required");
4731 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4733 inst
.error
= _("immediate value out of range");
4737 *val
= exp
.X_add_number
;
4741 /* Less-generic immediate-value read function with the possibility of loading a
4742 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4743 instructions. Puts the result directly in inst.operands[i]. */
4746 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4747 bfd_boolean allow_symbol_p
)
4750 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4753 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4755 if (exp_p
->X_op
== O_constant
)
4757 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4758 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4759 O_constant. We have to be careful not to break compilation for
4760 32-bit X_add_number, though. */
4761 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4763 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4764 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4766 inst
.operands
[i
].regisimm
= 1;
4769 else if (exp_p
->X_op
== O_big
4770 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4772 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4774 /* Bignums have their least significant bits in
4775 generic_bignum[0]. Make sure we put 32 bits in imm and
4776 32 bits in reg, in a (hopefully) portable way. */
4777 gas_assert (parts
!= 0);
4779 /* Make sure that the number is not too big.
4780 PR 11972: Bignums can now be sign-extended to the
4781 size of a .octa so check that the out of range bits
4782 are all zero or all one. */
4783 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4785 LITTLENUM_TYPE m
= -1;
4787 if (generic_bignum
[parts
* 2] != 0
4788 && generic_bignum
[parts
* 2] != m
)
4791 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4792 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4796 inst
.operands
[i
].imm
= 0;
4797 for (j
= 0; j
< parts
; j
++, idx
++)
4798 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4799 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4800 inst
.operands
[i
].reg
= 0;
4801 for (j
= 0; j
< parts
; j
++, idx
++)
4802 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4803 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4804 inst
.operands
[i
].regisimm
= 1;
4806 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4814 /* Returns the pseudo-register number of an FPA immediate constant,
4815 or FAIL if there isn't a valid constant here. */
4818 parse_fpa_immediate (char ** str
)
4820 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4826 /* First try and match exact strings, this is to guarantee
4827 that some formats will work even for cross assembly. */
4829 for (i
= 0; fp_const
[i
]; i
++)
4831 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4835 *str
+= strlen (fp_const
[i
]);
4836 if (is_end_of_line
[(unsigned char) **str
])
4842 /* Just because we didn't get a match doesn't mean that the constant
4843 isn't valid, just that it is in a format that we don't
4844 automatically recognize. Try parsing it with the standard
4845 expression routines. */
4847 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4849 /* Look for a raw floating point number. */
4850 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4851 && is_end_of_line
[(unsigned char) *save_in
])
4853 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4855 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4857 if (words
[j
] != fp_values
[i
][j
])
4861 if (j
== MAX_LITTLENUMS
)
4869 /* Try and parse a more complex expression, this will probably fail
4870 unless the code uses a floating point prefix (eg "0f"). */
4871 save_in
= input_line_pointer
;
4872 input_line_pointer
= *str
;
4873 if (expression (&exp
) == absolute_section
4874 && exp
.X_op
== O_big
4875 && exp
.X_add_number
< 0)
4877 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4879 #define X_PRECISION 5
4880 #define E_PRECISION 15L
4881 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4885 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4887 if (words
[j
] != fp_values
[i
][j
])
4891 if (j
== MAX_LITTLENUMS
)
4893 *str
= input_line_pointer
;
4894 input_line_pointer
= save_in
;
4901 *str
= input_line_pointer
;
4902 input_line_pointer
= save_in
;
4903 inst
.error
= _("invalid FPA immediate expression");
4907 /* Returns 1 if a number has "quarter-precision" float format
4908 0baBbbbbbc defgh000 00000000 00000000. */
4911 is_quarter_float (unsigned imm
)
4913 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4914 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4918 /* Detect the presence of a floating point or integer zero constant,
4922 parse_ifimm_zero (char **in
)
4926 if (!is_immediate_prefix (**in
))
4931 /* Accept #0x0 as a synonym for #0. */
4932 if (strncmp (*in
, "0x", 2) == 0)
4935 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4940 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4941 &generic_floating_point_number
);
4944 && generic_floating_point_number
.sign
== '+'
4945 && (generic_floating_point_number
.low
4946 > generic_floating_point_number
.leader
))
4952 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4953 0baBbbbbbc defgh000 00000000 00000000.
4954 The zero and minus-zero cases need special handling, since they can't be
4955 encoded in the "quarter-precision" float format, but can nonetheless be
4956 loaded as integer constants. */
4959 parse_qfloat_immediate (char **ccp
, int *immed
)
4963 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4964 int found_fpchar
= 0;
4966 skip_past_char (&str
, '#');
4968 /* We must not accidentally parse an integer as a floating-point number. Make
4969 sure that the value we parse is not an integer by checking for special
4970 characters '.' or 'e'.
4971 FIXME: This is a horrible hack, but doing better is tricky because type
4972 information isn't in a very usable state at parse time. */
4974 skip_whitespace (fpnum
);
4976 if (strncmp (fpnum
, "0x", 2) == 0)
4980 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4981 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4991 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4993 unsigned fpword
= 0;
4996 /* Our FP word must be 32 bits (single-precision FP). */
4997 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4999 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5003 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5016 /* Shift operands. */
5019 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5022 struct asm_shift_name
5025 enum shift_kind kind
;
5028 /* Third argument to parse_shift. */
5029 enum parse_shift_mode
5031 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5032 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5033 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5034 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5035 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5038 /* Parse a <shift> specifier on an ARM data processing instruction.
5039 This has three forms:
5041 (LSL|LSR|ASL|ASR|ROR) Rs
5042 (LSL|LSR|ASL|ASR|ROR) #imm
5045 Note that ASL is assimilated to LSL in the instruction encoding, and
5046 RRX to ROR #0 (which cannot be written as such). */
5049 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5051 const struct asm_shift_name
*shift_name
;
5052 enum shift_kind shift
;
5057 for (p
= *str
; ISALPHA (*p
); p
++)
5062 inst
.error
= _("shift expression expected");
5066 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5069 if (shift_name
== NULL
)
5071 inst
.error
= _("shift expression expected");
5075 shift
= shift_name
->kind
;
5079 case NO_SHIFT_RESTRICT
:
5080 case SHIFT_IMMEDIATE
: break;
5082 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5083 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5085 inst
.error
= _("'LSL' or 'ASR' required");
5090 case SHIFT_LSL_IMMEDIATE
:
5091 if (shift
!= SHIFT_LSL
)
5093 inst
.error
= _("'LSL' required");
5098 case SHIFT_ASR_IMMEDIATE
:
5099 if (shift
!= SHIFT_ASR
)
5101 inst
.error
= _("'ASR' required");
5109 if (shift
!= SHIFT_RRX
)
5111 /* Whitespace can appear here if the next thing is a bare digit. */
5112 skip_whitespace (p
);
5114 if (mode
== NO_SHIFT_RESTRICT
5115 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5117 inst
.operands
[i
].imm
= reg
;
5118 inst
.operands
[i
].immisreg
= 1;
5120 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5123 inst
.operands
[i
].shift_kind
= shift
;
5124 inst
.operands
[i
].shifted
= 1;
5129 /* Parse a <shifter_operand> for an ARM data processing instruction:
5132 #<immediate>, <rotate>
5136 where <shift> is defined by parse_shift above, and <rotate> is a
5137 multiple of 2 between 0 and 30. Validation of immediate operands
5138 is deferred to md_apply_fix. */
5141 parse_shifter_operand (char **str
, int i
)
5146 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5148 inst
.operands
[i
].reg
= value
;
5149 inst
.operands
[i
].isreg
= 1;
5151 /* parse_shift will override this if appropriate */
5152 inst
.reloc
.exp
.X_op
= O_constant
;
5153 inst
.reloc
.exp
.X_add_number
= 0;
5155 if (skip_past_comma (str
) == FAIL
)
5158 /* Shift operation on register. */
5159 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5162 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5165 if (skip_past_comma (str
) == SUCCESS
)
5167 /* #x, y -- ie explicit rotation by Y. */
5168 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5171 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5173 inst
.error
= _("constant expression expected");
5177 value
= exp
.X_add_number
;
5178 if (value
< 0 || value
> 30 || value
% 2 != 0)
5180 inst
.error
= _("invalid rotation");
5183 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5185 inst
.error
= _("invalid constant");
5189 /* Encode as specified. */
5190 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5194 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5195 inst
.reloc
.pc_rel
= 0;
5199 /* Group relocation information. Each entry in the table contains the
5200 textual name of the relocation as may appear in assembler source
5201 and must end with a colon.
5202 Along with this textual name are the relocation codes to be used if
5203 the corresponding instruction is an ALU instruction (ADD or SUB only),
5204 an LDR, an LDRS, or an LDC. */
5206 struct group_reloc_table_entry
5217 /* Varieties of non-ALU group relocation. */
5224 static struct group_reloc_table_entry group_reloc_table
[] =
5225 { /* Program counter relative: */
5227 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5232 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5233 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5234 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5235 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5237 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5242 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5243 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5244 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5245 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5247 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5248 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5249 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5250 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5251 /* Section base relative */
5253 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5258 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5259 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5260 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5261 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5263 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5268 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5269 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5270 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5271 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5273 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5274 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5277 /* Absolute thumb alu relocations. */
5279 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5284 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5289 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5294 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5299 /* Given the address of a pointer pointing to the textual name of a group
5300 relocation as may appear in assembler source, attempt to find its details
5301 in group_reloc_table. The pointer will be updated to the character after
5302 the trailing colon. On failure, FAIL will be returned; SUCCESS
5303 otherwise. On success, *entry will be updated to point at the relevant
5304 group_reloc_table entry. */
5307 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5310 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5312 int length
= strlen (group_reloc_table
[i
].name
);
5314 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5315 && (*str
)[length
] == ':')
5317 *out
= &group_reloc_table
[i
];
5318 *str
+= (length
+ 1);
5326 /* Parse a <shifter_operand> for an ARM data processing instruction
5327 (as for parse_shifter_operand) where group relocations are allowed:
5330 #<immediate>, <rotate>
5331 #:<group_reloc>:<expression>
5335 where <group_reloc> is one of the strings defined in group_reloc_table.
5336 The hashes are optional.
5338 Everything else is as for parse_shifter_operand. */
5340 static parse_operand_result
5341 parse_shifter_operand_group_reloc (char **str
, int i
)
5343 /* Determine if we have the sequence of characters #: or just :
5344 coming next. If we do, then we check for a group relocation.
5345 If we don't, punt the whole lot to parse_shifter_operand. */
5347 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5348 || (*str
)[0] == ':')
5350 struct group_reloc_table_entry
*entry
;
5352 if ((*str
)[0] == '#')
5357 /* Try to parse a group relocation. Anything else is an error. */
5358 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5360 inst
.error
= _("unknown group relocation");
5361 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5364 /* We now have the group relocation table entry corresponding to
5365 the name in the assembler source. Next, we parse the expression. */
5366 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5367 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5369 /* Record the relocation type (always the ALU variant here). */
5370 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5371 gas_assert (inst
.reloc
.type
!= 0);
5373 return PARSE_OPERAND_SUCCESS
;
5376 return parse_shifter_operand (str
, i
) == SUCCESS
5377 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5379 /* Never reached. */
5382 /* Parse a Neon alignment expression. Information is written to
5383 inst.operands[i]. We assume the initial ':' has been skipped.
5385 align .imm = align << 8, .immisalign=1, .preind=0 */
5386 static parse_operand_result
5387 parse_neon_alignment (char **str
, int i
)
5392 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5394 if (exp
.X_op
!= O_constant
)
5396 inst
.error
= _("alignment must be constant");
5397 return PARSE_OPERAND_FAIL
;
5400 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5401 inst
.operands
[i
].immisalign
= 1;
5402 /* Alignments are not pre-indexes. */
5403 inst
.operands
[i
].preind
= 0;
5406 return PARSE_OPERAND_SUCCESS
;
5409 /* Parse all forms of an ARM address expression. Information is written
5410 to inst.operands[i] and/or inst.reloc.
5412 Preindexed addressing (.preind=1):
5414 [Rn, #offset] .reg=Rn .reloc.exp=offset
5415 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5416 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5417 .shift_kind=shift .reloc.exp=shift_imm
5419 These three may have a trailing ! which causes .writeback to be set also.
5421 Postindexed addressing (.postind=1, .writeback=1):
5423 [Rn], #offset .reg=Rn .reloc.exp=offset
5424 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5425 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5426 .shift_kind=shift .reloc.exp=shift_imm
5428 Unindexed addressing (.preind=0, .postind=0):
5430 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5434 [Rn]{!} shorthand for [Rn,#0]{!}
5435 =immediate .isreg=0 .reloc.exp=immediate
5436 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5438 It is the caller's responsibility to check for addressing modes not
5439 supported by the instruction, and to set inst.reloc.type. */
5441 static parse_operand_result
5442 parse_address_main (char **str
, int i
, int group_relocations
,
5443 group_reloc_type group_type
)
5448 if (skip_past_char (&p
, '[') == FAIL
)
5450 if (skip_past_char (&p
, '=') == FAIL
)
5452 /* Bare address - translate to PC-relative offset. */
5453 inst
.reloc
.pc_rel
= 1;
5454 inst
.operands
[i
].reg
= REG_PC
;
5455 inst
.operands
[i
].isreg
= 1;
5456 inst
.operands
[i
].preind
= 1;
5458 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5459 return PARSE_OPERAND_FAIL
;
5461 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5462 /*allow_symbol_p=*/TRUE
))
5463 return PARSE_OPERAND_FAIL
;
5466 return PARSE_OPERAND_SUCCESS
;
5469 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5470 skip_whitespace (p
);
5472 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5474 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5475 return PARSE_OPERAND_FAIL
;
5477 inst
.operands
[i
].reg
= reg
;
5478 inst
.operands
[i
].isreg
= 1;
5480 if (skip_past_comma (&p
) == SUCCESS
)
5482 inst
.operands
[i
].preind
= 1;
5485 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5487 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5489 inst
.operands
[i
].imm
= reg
;
5490 inst
.operands
[i
].immisreg
= 1;
5492 if (skip_past_comma (&p
) == SUCCESS
)
5493 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5494 return PARSE_OPERAND_FAIL
;
5496 else if (skip_past_char (&p
, ':') == SUCCESS
)
5498 /* FIXME: '@' should be used here, but it's filtered out by generic
5499 code before we get to see it here. This may be subject to
5501 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5503 if (result
!= PARSE_OPERAND_SUCCESS
)
5508 if (inst
.operands
[i
].negative
)
5510 inst
.operands
[i
].negative
= 0;
5514 if (group_relocations
5515 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5517 struct group_reloc_table_entry
*entry
;
5519 /* Skip over the #: or : sequence. */
5525 /* Try to parse a group relocation. Anything else is an
5527 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5529 inst
.error
= _("unknown group relocation");
5530 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5533 /* We now have the group relocation table entry corresponding to
5534 the name in the assembler source. Next, we parse the
5536 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5537 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5539 /* Record the relocation type. */
5543 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5547 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5551 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5558 if (inst
.reloc
.type
== 0)
5560 inst
.error
= _("this group relocation is not allowed on this instruction");
5561 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5567 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5568 return PARSE_OPERAND_FAIL
;
5569 /* If the offset is 0, find out if it's a +0 or -0. */
5570 if (inst
.reloc
.exp
.X_op
== O_constant
5571 && inst
.reloc
.exp
.X_add_number
== 0)
5573 skip_whitespace (q
);
5577 skip_whitespace (q
);
5580 inst
.operands
[i
].negative
= 1;
5585 else if (skip_past_char (&p
, ':') == SUCCESS
)
5587 /* FIXME: '@' should be used here, but it's filtered out by generic code
5588 before we get to see it here. This may be subject to change. */
5589 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5591 if (result
!= PARSE_OPERAND_SUCCESS
)
5595 if (skip_past_char (&p
, ']') == FAIL
)
5597 inst
.error
= _("']' expected");
5598 return PARSE_OPERAND_FAIL
;
5601 if (skip_past_char (&p
, '!') == SUCCESS
)
5602 inst
.operands
[i
].writeback
= 1;
5604 else if (skip_past_comma (&p
) == SUCCESS
)
5606 if (skip_past_char (&p
, '{') == SUCCESS
)
5608 /* [Rn], {expr} - unindexed, with option */
5609 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5610 0, 255, TRUE
) == FAIL
)
5611 return PARSE_OPERAND_FAIL
;
5613 if (skip_past_char (&p
, '}') == FAIL
)
5615 inst
.error
= _("'}' expected at end of 'option' field");
5616 return PARSE_OPERAND_FAIL
;
5618 if (inst
.operands
[i
].preind
)
5620 inst
.error
= _("cannot combine index with option");
5621 return PARSE_OPERAND_FAIL
;
5624 return PARSE_OPERAND_SUCCESS
;
5628 inst
.operands
[i
].postind
= 1;
5629 inst
.operands
[i
].writeback
= 1;
5631 if (inst
.operands
[i
].preind
)
5633 inst
.error
= _("cannot combine pre- and post-indexing");
5634 return PARSE_OPERAND_FAIL
;
5638 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5640 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5642 /* We might be using the immediate for alignment already. If we
5643 are, OR the register number into the low-order bits. */
5644 if (inst
.operands
[i
].immisalign
)
5645 inst
.operands
[i
].imm
|= reg
;
5647 inst
.operands
[i
].imm
= reg
;
5648 inst
.operands
[i
].immisreg
= 1;
5650 if (skip_past_comma (&p
) == SUCCESS
)
5651 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5652 return PARSE_OPERAND_FAIL
;
5657 if (inst
.operands
[i
].negative
)
5659 inst
.operands
[i
].negative
= 0;
5662 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5663 return PARSE_OPERAND_FAIL
;
5664 /* If the offset is 0, find out if it's a +0 or -0. */
5665 if (inst
.reloc
.exp
.X_op
== O_constant
5666 && inst
.reloc
.exp
.X_add_number
== 0)
5668 skip_whitespace (q
);
5672 skip_whitespace (q
);
5675 inst
.operands
[i
].negative
= 1;
5681 /* If at this point neither .preind nor .postind is set, we have a
5682 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5683 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5685 inst
.operands
[i
].preind
= 1;
5686 inst
.reloc
.exp
.X_op
= O_constant
;
5687 inst
.reloc
.exp
.X_add_number
= 0;
5690 return PARSE_OPERAND_SUCCESS
;
5694 parse_address (char **str
, int i
)
5696 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5700 static parse_operand_result
5701 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5703 return parse_address_main (str
, i
, 1, type
);
5706 /* Parse an operand for a MOVW or MOVT instruction. */
5708 parse_half (char **str
)
5713 skip_past_char (&p
, '#');
5714 if (strncasecmp (p
, ":lower16:", 9) == 0)
5715 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5716 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5717 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5719 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5722 skip_whitespace (p
);
5725 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5728 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5730 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5732 inst
.error
= _("constant expression expected");
5735 if (inst
.reloc
.exp
.X_add_number
< 0
5736 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5738 inst
.error
= _("immediate value out of range");
5746 /* Miscellaneous. */
5748 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5749 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5751 parse_psr (char **str
, bfd_boolean lhs
)
5754 unsigned long psr_field
;
5755 const struct asm_psr
*psr
;
5757 bfd_boolean is_apsr
= FALSE
;
5758 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5760 /* PR gas/12698: If the user has specified -march=all then m_profile will
5761 be TRUE, but we want to ignore it in this case as we are building for any
5762 CPU type, including non-m variants. */
5763 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5766 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5767 feature for ease of use and backwards compatibility. */
5769 if (strncasecmp (p
, "SPSR", 4) == 0)
5772 goto unsupported_psr
;
5774 psr_field
= SPSR_BIT
;
5776 else if (strncasecmp (p
, "CPSR", 4) == 0)
5779 goto unsupported_psr
;
5783 else if (strncasecmp (p
, "APSR", 4) == 0)
5785 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5786 and ARMv7-R architecture CPUs. */
5795 while (ISALNUM (*p
) || *p
== '_');
5797 if (strncasecmp (start
, "iapsr", 5) == 0
5798 || strncasecmp (start
, "eapsr", 5) == 0
5799 || strncasecmp (start
, "xpsr", 4) == 0
5800 || strncasecmp (start
, "psr", 3) == 0)
5801 p
= start
+ strcspn (start
, "rR") + 1;
5803 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5809 /* If APSR is being written, a bitfield may be specified. Note that
5810 APSR itself is handled above. */
5811 if (psr
->field
<= 3)
5813 psr_field
= psr
->field
;
5819 /* M-profile MSR instructions have the mask field set to "10", except
5820 *PSR variants which modify APSR, which may use a different mask (and
5821 have been handled already). Do that by setting the PSR_f field
5823 return psr
->field
| (lhs
? PSR_f
: 0);
5826 goto unsupported_psr
;
5832 /* A suffix follows. */
5838 while (ISALNUM (*p
) || *p
== '_');
5842 /* APSR uses a notation for bits, rather than fields. */
5843 unsigned int nzcvq_bits
= 0;
5844 unsigned int g_bit
= 0;
5847 for (bit
= start
; bit
!= p
; bit
++)
5849 switch (TOLOWER (*bit
))
5852 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5856 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5860 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5864 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5868 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5872 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5876 inst
.error
= _("unexpected bit specified after APSR");
5881 if (nzcvq_bits
== 0x1f)
5886 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5888 inst
.error
= _("selected processor does not "
5889 "support DSP extension");
5896 if ((nzcvq_bits
& 0x20) != 0
5897 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5898 || (g_bit
& 0x2) != 0)
5900 inst
.error
= _("bad bitmask specified after APSR");
5906 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5911 psr_field
|= psr
->field
;
5917 goto error
; /* Garbage after "[CS]PSR". */
5919 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5920 is deprecated, but allow it anyway. */
5924 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5927 else if (!m_profile
)
5928 /* These bits are never right for M-profile devices: don't set them
5929 (only code paths which read/write APSR reach here). */
5930 psr_field
|= (PSR_c
| PSR_f
);
5936 inst
.error
= _("selected processor does not support requested special "
5937 "purpose register");
5941 inst
.error
= _("flag for {c}psr instruction expected");
5945 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5946 value suitable for splatting into the AIF field of the instruction. */
5949 parse_cps_flags (char **str
)
5958 case '\0': case ',':
5961 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5962 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5963 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5966 inst
.error
= _("unrecognized CPS flag");
5971 if (saw_a_flag
== 0)
5973 inst
.error
= _("missing CPS flags");
5981 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5982 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5985 parse_endian_specifier (char **str
)
5990 if (strncasecmp (s
, "BE", 2))
5992 else if (strncasecmp (s
, "LE", 2))
5996 inst
.error
= _("valid endian specifiers are be or le");
6000 if (ISALNUM (s
[2]) || s
[2] == '_')
6002 inst
.error
= _("valid endian specifiers are be or le");
6007 return little_endian
;
6010 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6011 value suitable for poking into the rotate field of an sxt or sxta
6012 instruction, or FAIL on error. */
6015 parse_ror (char **str
)
6020 if (strncasecmp (s
, "ROR", 3) == 0)
6024 inst
.error
= _("missing rotation field after comma");
6028 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6033 case 0: *str
= s
; return 0x0;
6034 case 8: *str
= s
; return 0x1;
6035 case 16: *str
= s
; return 0x2;
6036 case 24: *str
= s
; return 0x3;
6039 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6044 /* Parse a conditional code (from conds[] below). The value returned is in the
6045 range 0 .. 14, or FAIL. */
6047 parse_cond (char **str
)
6050 const struct asm_cond
*c
;
6052 /* Condition codes are always 2 characters, so matching up to
6053 3 characters is sufficient. */
6058 while (ISALPHA (*q
) && n
< 3)
6060 cond
[n
] = TOLOWER (*q
);
6065 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6068 inst
.error
= _("condition required");
6076 /* If the given feature available in the selected CPU, mark it as used.
6077 Returns TRUE iff feature is available. */
6079 mark_feature_used (const arm_feature_set
*feature
)
6081 /* Ensure the option is valid on the current architecture. */
6082 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6085 /* Add the appropriate architecture feature for the barrier option used.
6088 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6090 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6095 /* Parse an option for a barrier instruction. Returns the encoding for the
6098 parse_barrier (char **str
)
6101 const struct asm_barrier_opt
*o
;
6104 while (ISALPHA (*q
))
6107 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6112 if (!mark_feature_used (&o
->arch
))
6119 /* Parse the operands of a table branch instruction. Similar to a memory
6122 parse_tb (char **str
)
6127 if (skip_past_char (&p
, '[') == FAIL
)
6129 inst
.error
= _("'[' expected");
6133 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6135 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6138 inst
.operands
[0].reg
= reg
;
6140 if (skip_past_comma (&p
) == FAIL
)
6142 inst
.error
= _("',' expected");
6146 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6148 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6151 inst
.operands
[0].imm
= reg
;
6153 if (skip_past_comma (&p
) == SUCCESS
)
6155 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6157 if (inst
.reloc
.exp
.X_add_number
!= 1)
6159 inst
.error
= _("invalid shift");
6162 inst
.operands
[0].shifted
= 1;
6165 if (skip_past_char (&p
, ']') == FAIL
)
6167 inst
.error
= _("']' expected");
6174 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6175 information on the types the operands can take and how they are encoded.
6176 Up to four operands may be read; this function handles setting the
6177 ".present" field for each read operand itself.
6178 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6179 else returns FAIL. */
6182 parse_neon_mov (char **str
, int *which_operand
)
6184 int i
= *which_operand
, val
;
6185 enum arm_reg_type rtype
;
6187 struct neon_type_el optype
;
6189 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6191 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6192 inst
.operands
[i
].reg
= val
;
6193 inst
.operands
[i
].isscalar
= 1;
6194 inst
.operands
[i
].vectype
= optype
;
6195 inst
.operands
[i
++].present
= 1;
6197 if (skip_past_comma (&ptr
) == FAIL
)
6200 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6203 inst
.operands
[i
].reg
= val
;
6204 inst
.operands
[i
].isreg
= 1;
6205 inst
.operands
[i
].present
= 1;
6207 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6210 /* Cases 0, 1, 2, 3, 5 (D only). */
6211 if (skip_past_comma (&ptr
) == FAIL
)
6214 inst
.operands
[i
].reg
= val
;
6215 inst
.operands
[i
].isreg
= 1;
6216 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6217 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6218 inst
.operands
[i
].isvec
= 1;
6219 inst
.operands
[i
].vectype
= optype
;
6220 inst
.operands
[i
++].present
= 1;
6222 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6224 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6225 Case 13: VMOV <Sd>, <Rm> */
6226 inst
.operands
[i
].reg
= val
;
6227 inst
.operands
[i
].isreg
= 1;
6228 inst
.operands
[i
].present
= 1;
6230 if (rtype
== REG_TYPE_NQ
)
6232 first_error (_("can't use Neon quad register here"));
6235 else if (rtype
!= REG_TYPE_VFS
)
6238 if (skip_past_comma (&ptr
) == FAIL
)
6240 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6242 inst
.operands
[i
].reg
= val
;
6243 inst
.operands
[i
].isreg
= 1;
6244 inst
.operands
[i
].present
= 1;
6247 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6250 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6251 Case 1: VMOV<c><q> <Dd>, <Dm>
6252 Case 8: VMOV.F32 <Sd>, <Sm>
6253 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6255 inst
.operands
[i
].reg
= val
;
6256 inst
.operands
[i
].isreg
= 1;
6257 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6258 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6259 inst
.operands
[i
].isvec
= 1;
6260 inst
.operands
[i
].vectype
= optype
;
6261 inst
.operands
[i
].present
= 1;
6263 if (skip_past_comma (&ptr
) == SUCCESS
)
6268 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6271 inst
.operands
[i
].reg
= val
;
6272 inst
.operands
[i
].isreg
= 1;
6273 inst
.operands
[i
++].present
= 1;
6275 if (skip_past_comma (&ptr
) == FAIL
)
6278 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6281 inst
.operands
[i
].reg
= val
;
6282 inst
.operands
[i
].isreg
= 1;
6283 inst
.operands
[i
].present
= 1;
6286 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6287 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6288 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6289 Case 10: VMOV.F32 <Sd>, #<imm>
6290 Case 11: VMOV.F64 <Dd>, #<imm> */
6291 inst
.operands
[i
].immisfloat
= 1;
6292 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6294 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6295 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6299 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6303 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6306 inst
.operands
[i
].reg
= val
;
6307 inst
.operands
[i
].isreg
= 1;
6308 inst
.operands
[i
++].present
= 1;
6310 if (skip_past_comma (&ptr
) == FAIL
)
6313 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6315 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6316 inst
.operands
[i
].reg
= val
;
6317 inst
.operands
[i
].isscalar
= 1;
6318 inst
.operands
[i
].present
= 1;
6319 inst
.operands
[i
].vectype
= optype
;
6321 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6323 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6324 inst
.operands
[i
].reg
= val
;
6325 inst
.operands
[i
].isreg
= 1;
6326 inst
.operands
[i
++].present
= 1;
6328 if (skip_past_comma (&ptr
) == FAIL
)
6331 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6334 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6338 inst
.operands
[i
].reg
= val
;
6339 inst
.operands
[i
].isreg
= 1;
6340 inst
.operands
[i
].isvec
= 1;
6341 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6342 inst
.operands
[i
].vectype
= optype
;
6343 inst
.operands
[i
].present
= 1;
6345 if (rtype
== REG_TYPE_VFS
)
6349 if (skip_past_comma (&ptr
) == FAIL
)
6351 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6354 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6357 inst
.operands
[i
].reg
= val
;
6358 inst
.operands
[i
].isreg
= 1;
6359 inst
.operands
[i
].isvec
= 1;
6360 inst
.operands
[i
].issingle
= 1;
6361 inst
.operands
[i
].vectype
= optype
;
6362 inst
.operands
[i
].present
= 1;
6365 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6369 inst
.operands
[i
].reg
= val
;
6370 inst
.operands
[i
].isreg
= 1;
6371 inst
.operands
[i
].isvec
= 1;
6372 inst
.operands
[i
].issingle
= 1;
6373 inst
.operands
[i
].vectype
= optype
;
6374 inst
.operands
[i
].present
= 1;
6379 first_error (_("parse error"));
6383 /* Successfully parsed the operands. Update args. */
6389 first_error (_("expected comma"));
6393 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6397 /* Use this macro when the operand constraints are different
6398 for ARM and THUMB (e.g. ldrd). */
6399 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6400 ((arm_operand) | ((thumb_operand) << 16))
6402 /* Matcher codes for parse_operands. */
6403 enum operand_parse_code
6405 OP_stop
, /* end of line */
6407 OP_RR
, /* ARM register */
6408 OP_RRnpc
, /* ARM register, not r15 */
6409 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6410 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6411 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6412 optional trailing ! */
6413 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6414 OP_RCP
, /* Coprocessor number */
6415 OP_RCN
, /* Coprocessor register */
6416 OP_RF
, /* FPA register */
6417 OP_RVS
, /* VFP single precision register */
6418 OP_RVD
, /* VFP double precision register (0..15) */
6419 OP_RND
, /* Neon double precision register (0..31) */
6420 OP_RNQ
, /* Neon quad precision register */
6421 OP_RVSD
, /* VFP single or double precision register */
6422 OP_RNDQ
, /* Neon double or quad precision register */
6423 OP_RNSDQ
, /* Neon single, double or quad precision register */
6424 OP_RNSC
, /* Neon scalar D[X] */
6425 OP_RVC
, /* VFP control register */
6426 OP_RMF
, /* Maverick F register */
6427 OP_RMD
, /* Maverick D register */
6428 OP_RMFX
, /* Maverick FX register */
6429 OP_RMDX
, /* Maverick DX register */
6430 OP_RMAX
, /* Maverick AX register */
6431 OP_RMDS
, /* Maverick DSPSC register */
6432 OP_RIWR
, /* iWMMXt wR register */
6433 OP_RIWC
, /* iWMMXt wC register */
6434 OP_RIWG
, /* iWMMXt wCG register */
6435 OP_RXA
, /* XScale accumulator register */
6437 OP_REGLST
, /* ARM register list */
6438 OP_VRSLST
, /* VFP single-precision register list */
6439 OP_VRDLST
, /* VFP double-precision register list */
6440 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6441 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6442 OP_NSTRLST
, /* Neon element/structure list */
6444 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6445 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6446 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6447 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6448 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6449 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6450 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6451 OP_VMOV
, /* Neon VMOV operands. */
6452 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6453 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6454 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6456 OP_I0
, /* immediate zero */
6457 OP_I7
, /* immediate value 0 .. 7 */
6458 OP_I15
, /* 0 .. 15 */
6459 OP_I16
, /* 1 .. 16 */
6460 OP_I16z
, /* 0 .. 16 */
6461 OP_I31
, /* 0 .. 31 */
6462 OP_I31w
, /* 0 .. 31, optional trailing ! */
6463 OP_I32
, /* 1 .. 32 */
6464 OP_I32z
, /* 0 .. 32 */
6465 OP_I63
, /* 0 .. 63 */
6466 OP_I63s
, /* -64 .. 63 */
6467 OP_I64
, /* 1 .. 64 */
6468 OP_I64z
, /* 0 .. 64 */
6469 OP_I255
, /* 0 .. 255 */
6471 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6472 OP_I7b
, /* 0 .. 7 */
6473 OP_I15b
, /* 0 .. 15 */
6474 OP_I31b
, /* 0 .. 31 */
6476 OP_SH
, /* shifter operand */
6477 OP_SHG
, /* shifter operand with possible group relocation */
6478 OP_ADDR
, /* Memory address expression (any mode) */
6479 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6480 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6481 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6482 OP_EXP
, /* arbitrary expression */
6483 OP_EXPi
, /* same, with optional immediate prefix */
6484 OP_EXPr
, /* same, with optional relocation suffix */
6485 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6487 OP_CPSF
, /* CPS flags */
6488 OP_ENDI
, /* Endianness specifier */
6489 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6490 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6491 OP_COND
, /* conditional code */
6492 OP_TB
, /* Table branch. */
6494 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6496 OP_RRnpc_I0
, /* ARM register or literal 0 */
6497 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6498 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6499 OP_RF_IF
, /* FPA register or immediate */
6500 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6501 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6503 /* Optional operands. */
6504 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6505 OP_oI31b
, /* 0 .. 31 */
6506 OP_oI32b
, /* 1 .. 32 */
6507 OP_oI32z
, /* 0 .. 32 */
6508 OP_oIffffb
, /* 0 .. 65535 */
6509 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6511 OP_oRR
, /* ARM register */
6512 OP_oRRnpc
, /* ARM register, not the PC */
6513 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6514 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6515 OP_oRND
, /* Optional Neon double precision register */
6516 OP_oRNQ
, /* Optional Neon quad precision register */
6517 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6518 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6519 OP_oSHll
, /* LSL immediate */
6520 OP_oSHar
, /* ASR immediate */
6521 OP_oSHllar
, /* LSL or ASR immediate */
6522 OP_oROR
, /* ROR 0/8/16/24 */
6523 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6525 /* Some pre-defined mixed (ARM/THUMB) operands. */
6526 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6527 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6528 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6530 OP_FIRST_OPTIONAL
= OP_oI7b
6533 /* Generic instruction operand parser. This does no encoding and no
6534 semantic validation; it merely squirrels values away in the inst
6535 structure. Returns SUCCESS or FAIL depending on whether the
6536 specified grammar matched. */
6538 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6540 unsigned const int *upat
= pattern
;
6541 char *backtrack_pos
= 0;
6542 const char *backtrack_error
= 0;
6543 int i
, val
= 0, backtrack_index
= 0;
6544 enum arm_reg_type rtype
;
6545 parse_operand_result result
;
6546 unsigned int op_parse_code
;
6548 #define po_char_or_fail(chr) \
6551 if (skip_past_char (&str, chr) == FAIL) \
6556 #define po_reg_or_fail(regtype) \
6559 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6560 & inst.operands[i].vectype); \
6563 first_error (_(reg_expected_msgs[regtype])); \
6566 inst.operands[i].reg = val; \
6567 inst.operands[i].isreg = 1; \
6568 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6569 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6570 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6571 || rtype == REG_TYPE_VFD \
6572 || rtype == REG_TYPE_NQ); \
6576 #define po_reg_or_goto(regtype, label) \
6579 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6580 & inst.operands[i].vectype); \
6584 inst.operands[i].reg = val; \
6585 inst.operands[i].isreg = 1; \
6586 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6587 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6588 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6589 || rtype == REG_TYPE_VFD \
6590 || rtype == REG_TYPE_NQ); \
6594 #define po_imm_or_fail(min, max, popt) \
6597 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6599 inst.operands[i].imm = val; \
6603 #define po_scalar_or_goto(elsz, label) \
6606 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6609 inst.operands[i].reg = val; \
6610 inst.operands[i].isscalar = 1; \
6614 #define po_misc_or_fail(expr) \
6622 #define po_misc_or_fail_no_backtrack(expr) \
6626 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6627 backtrack_pos = 0; \
6628 if (result != PARSE_OPERAND_SUCCESS) \
6633 #define po_barrier_or_imm(str) \
6636 val = parse_barrier (&str); \
6637 if (val == FAIL && ! ISALPHA (*str)) \
6640 /* ISB can only take SY as an option. */ \
6641 || ((inst.instruction & 0xf0) == 0x60 \
6644 inst.error = _("invalid barrier type"); \
6645 backtrack_pos = 0; \
6651 skip_whitespace (str
);
6653 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6655 op_parse_code
= upat
[i
];
6656 if (op_parse_code
>= 1<<16)
6657 op_parse_code
= thumb
? (op_parse_code
>> 16)
6658 : (op_parse_code
& ((1<<16)-1));
6660 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6662 /* Remember where we are in case we need to backtrack. */
6663 gas_assert (!backtrack_pos
);
6664 backtrack_pos
= str
;
6665 backtrack_error
= inst
.error
;
6666 backtrack_index
= i
;
6669 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6670 po_char_or_fail (',');
6672 switch (op_parse_code
)
6680 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6681 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6682 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6683 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6684 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6685 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6687 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6689 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6691 /* Also accept generic coprocessor regs for unknown registers. */
6693 po_reg_or_fail (REG_TYPE_CN
);
6695 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6696 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6697 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6698 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6699 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6700 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6701 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6702 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6703 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6704 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6706 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6708 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6709 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6711 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6713 /* Neon scalar. Using an element size of 8 means that some invalid
6714 scalars are accepted here, so deal with those in later code. */
6715 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6719 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6722 po_imm_or_fail (0, 0, TRUE
);
6727 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6732 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6735 if (parse_ifimm_zero (&str
))
6736 inst
.operands
[i
].imm
= 0;
6740 = _("only floating point zero is allowed as immediate value");
6748 po_scalar_or_goto (8, try_rr
);
6751 po_reg_or_fail (REG_TYPE_RN
);
6757 po_scalar_or_goto (8, try_nsdq
);
6760 po_reg_or_fail (REG_TYPE_NSDQ
);
6766 po_scalar_or_goto (8, try_ndq
);
6769 po_reg_or_fail (REG_TYPE_NDQ
);
6775 po_scalar_or_goto (8, try_vfd
);
6778 po_reg_or_fail (REG_TYPE_VFD
);
6783 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6784 not careful then bad things might happen. */
6785 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6790 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6793 /* There's a possibility of getting a 64-bit immediate here, so
6794 we need special handling. */
6795 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6798 inst
.error
= _("immediate value is out of range");
6806 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6809 po_imm_or_fail (0, 63, TRUE
);
6814 po_char_or_fail ('[');
6815 po_reg_or_fail (REG_TYPE_RN
);
6816 po_char_or_fail (']');
6822 po_reg_or_fail (REG_TYPE_RN
);
6823 if (skip_past_char (&str
, '!') == SUCCESS
)
6824 inst
.operands
[i
].writeback
= 1;
6828 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6829 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6830 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6831 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6832 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6833 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6834 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6835 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6836 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6837 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6838 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6839 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6841 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6843 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6844 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6846 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6847 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6848 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6849 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6851 /* Immediate variants */
6853 po_char_or_fail ('{');
6854 po_imm_or_fail (0, 255, TRUE
);
6855 po_char_or_fail ('}');
6859 /* The expression parser chokes on a trailing !, so we have
6860 to find it first and zap it. */
6863 while (*s
&& *s
!= ',')
6868 inst
.operands
[i
].writeback
= 1;
6870 po_imm_or_fail (0, 31, TRUE
);
6878 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6883 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6888 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6890 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6892 val
= parse_reloc (&str
);
6895 inst
.error
= _("unrecognized relocation suffix");
6898 else if (val
!= BFD_RELOC_UNUSED
)
6900 inst
.operands
[i
].imm
= val
;
6901 inst
.operands
[i
].hasreloc
= 1;
6906 /* Operand for MOVW or MOVT. */
6908 po_misc_or_fail (parse_half (&str
));
6911 /* Register or expression. */
6912 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6913 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6915 /* Register or immediate. */
6916 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6917 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6919 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6921 if (!is_immediate_prefix (*str
))
6924 val
= parse_fpa_immediate (&str
);
6927 /* FPA immediates are encoded as registers 8-15.
6928 parse_fpa_immediate has already applied the offset. */
6929 inst
.operands
[i
].reg
= val
;
6930 inst
.operands
[i
].isreg
= 1;
6933 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6934 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6936 /* Two kinds of register. */
6939 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6941 || (rege
->type
!= REG_TYPE_MMXWR
6942 && rege
->type
!= REG_TYPE_MMXWC
6943 && rege
->type
!= REG_TYPE_MMXWCG
))
6945 inst
.error
= _("iWMMXt data or control register expected");
6948 inst
.operands
[i
].reg
= rege
->number
;
6949 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6955 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6957 || (rege
->type
!= REG_TYPE_MMXWC
6958 && rege
->type
!= REG_TYPE_MMXWCG
))
6960 inst
.error
= _("iWMMXt control register expected");
6963 inst
.operands
[i
].reg
= rege
->number
;
6964 inst
.operands
[i
].isreg
= 1;
6969 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6970 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6971 case OP_oROR
: val
= parse_ror (&str
); break;
6972 case OP_COND
: val
= parse_cond (&str
); break;
6973 case OP_oBARRIER_I15
:
6974 po_barrier_or_imm (str
); break;
6976 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6982 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6983 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6985 inst
.error
= _("Banked registers are not available with this "
6991 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6995 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6998 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7000 if (strncasecmp (str
, "APSR_", 5) == 0)
7007 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7008 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7009 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7010 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7011 default: found
= 16;
7015 inst
.operands
[i
].isvec
= 1;
7016 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7017 inst
.operands
[i
].reg
= REG_PC
;
7024 po_misc_or_fail (parse_tb (&str
));
7027 /* Register lists. */
7029 val
= parse_reg_list (&str
);
7032 inst
.operands
[i
].writeback
= 1;
7038 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7042 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7046 /* Allow Q registers too. */
7047 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7052 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7054 inst
.operands
[i
].issingle
= 1;
7059 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7064 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7065 &inst
.operands
[i
].vectype
);
7068 /* Addressing modes */
7070 po_misc_or_fail (parse_address (&str
, i
));
7074 po_misc_or_fail_no_backtrack (
7075 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7079 po_misc_or_fail_no_backtrack (
7080 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7084 po_misc_or_fail_no_backtrack (
7085 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7089 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7093 po_misc_or_fail_no_backtrack (
7094 parse_shifter_operand_group_reloc (&str
, i
));
7098 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7102 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7106 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7110 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7113 /* Various value-based sanity checks and shared operations. We
7114 do not signal immediate failures for the register constraints;
7115 this allows a syntax error to take precedence. */
7116 switch (op_parse_code
)
7124 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7125 inst
.error
= BAD_PC
;
7130 if (inst
.operands
[i
].isreg
)
7132 if (inst
.operands
[i
].reg
== REG_PC
)
7133 inst
.error
= BAD_PC
;
7134 else if (inst
.operands
[i
].reg
== REG_SP
)
7135 inst
.error
= BAD_SP
;
7140 if (inst
.operands
[i
].isreg
7141 && inst
.operands
[i
].reg
== REG_PC
7142 && (inst
.operands
[i
].writeback
|| thumb
))
7143 inst
.error
= BAD_PC
;
7152 case OP_oBARRIER_I15
:
7161 inst
.operands
[i
].imm
= val
;
7168 /* If we get here, this operand was successfully parsed. */
7169 inst
.operands
[i
].present
= 1;
7173 inst
.error
= BAD_ARGS
;
7178 /* The parse routine should already have set inst.error, but set a
7179 default here just in case. */
7181 inst
.error
= _("syntax error");
7185 /* Do not backtrack over a trailing optional argument that
7186 absorbed some text. We will only fail again, with the
7187 'garbage following instruction' error message, which is
7188 probably less helpful than the current one. */
7189 if (backtrack_index
== i
&& backtrack_pos
!= str
7190 && upat
[i
+1] == OP_stop
)
7193 inst
.error
= _("syntax error");
7197 /* Try again, skipping the optional argument at backtrack_pos. */
7198 str
= backtrack_pos
;
7199 inst
.error
= backtrack_error
;
7200 inst
.operands
[backtrack_index
].present
= 0;
7201 i
= backtrack_index
;
7205 /* Check that we have parsed all the arguments. */
7206 if (*str
!= '\0' && !inst
.error
)
7207 inst
.error
= _("garbage following instruction");
7209 return inst
.error
? FAIL
: SUCCESS
;
7212 #undef po_char_or_fail
7213 #undef po_reg_or_fail
7214 #undef po_reg_or_goto
7215 #undef po_imm_or_fail
7216 #undef po_scalar_or_fail
7217 #undef po_barrier_or_imm
7219 /* Shorthand macro for instruction encoding functions issuing errors. */
7220 #define constraint(expr, err) \
7231 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7232 instructions are unpredictable if these registers are used. This
7233 is the BadReg predicate in ARM's Thumb-2 documentation. */
7234 #define reject_bad_reg(reg) \
7236 if (reg == REG_SP || reg == REG_PC) \
7238 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7243 /* If REG is R13 (the stack pointer), warn that its use is
7245 #define warn_deprecated_sp(reg) \
7247 if (warn_on_deprecated && reg == REG_SP) \
7248 as_tsktsk (_("use of r13 is deprecated")); \
7251 /* Functions for operand encoding. ARM, then Thumb. */
7253 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7255 /* If VAL can be encoded in the immediate field of an ARM instruction,
7256 return the encoded form. Otherwise, return FAIL. */
7259 encode_arm_immediate (unsigned int val
)
7263 for (i
= 0; i
< 32; i
+= 2)
7264 if ((a
= rotate_left (val
, i
)) <= 0xff)
7265 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7270 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7271 return the encoded form. Otherwise, return FAIL. */
7273 encode_thumb32_immediate (unsigned int val
)
7280 for (i
= 1; i
<= 24; i
++)
7283 if ((val
& ~(0xff << i
)) == 0)
7284 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7288 if (val
== ((a
<< 16) | a
))
7290 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7294 if (val
== ((a
<< 16) | a
))
7295 return 0x200 | (a
>> 8);
7299 /* Encode a VFP SP or DP register number into inst.instruction. */
7302 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7304 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7307 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7310 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7313 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7318 first_error (_("D register out of range for selected VFP version"));
7326 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7330 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7334 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7338 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7342 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7346 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7354 /* Encode a <shift> in an ARM-format instruction. The immediate,
7355 if any, is handled by md_apply_fix. */
7357 encode_arm_shift (int i
)
7359 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7360 inst
.instruction
|= SHIFT_ROR
<< 5;
7363 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7364 if (inst
.operands
[i
].immisreg
)
7366 inst
.instruction
|= SHIFT_BY_REG
;
7367 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7370 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7375 encode_arm_shifter_operand (int i
)
7377 if (inst
.operands
[i
].isreg
)
7379 inst
.instruction
|= inst
.operands
[i
].reg
;
7380 encode_arm_shift (i
);
7384 inst
.instruction
|= INST_IMMEDIATE
;
7385 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7386 inst
.instruction
|= inst
.operands
[i
].imm
;
7390 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7392 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7395 Generate an error if the operand is not a register. */
7396 constraint (!inst
.operands
[i
].isreg
,
7397 _("Instruction does not support =N addresses"));
7399 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7401 if (inst
.operands
[i
].preind
)
7405 inst
.error
= _("instruction does not accept preindexed addressing");
7408 inst
.instruction
|= PRE_INDEX
;
7409 if (inst
.operands
[i
].writeback
)
7410 inst
.instruction
|= WRITE_BACK
;
7413 else if (inst
.operands
[i
].postind
)
7415 gas_assert (inst
.operands
[i
].writeback
);
7417 inst
.instruction
|= WRITE_BACK
;
7419 else /* unindexed - only for coprocessor */
7421 inst
.error
= _("instruction does not accept unindexed addressing");
7425 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7426 && (((inst
.instruction
& 0x000f0000) >> 16)
7427 == ((inst
.instruction
& 0x0000f000) >> 12)))
7428 as_warn ((inst
.instruction
& LOAD_BIT
)
7429 ? _("destination register same as write-back base")
7430 : _("source register same as write-back base"));
7433 /* inst.operands[i] was set up by parse_address. Encode it into an
7434 ARM-format mode 2 load or store instruction. If is_t is true,
7435 reject forms that cannot be used with a T instruction (i.e. not
7438 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7440 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7442 encode_arm_addr_mode_common (i
, is_t
);
7444 if (inst
.operands
[i
].immisreg
)
7446 constraint ((inst
.operands
[i
].imm
== REG_PC
7447 || (is_pc
&& inst
.operands
[i
].writeback
)),
7449 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7450 inst
.instruction
|= inst
.operands
[i
].imm
;
7451 if (!inst
.operands
[i
].negative
)
7452 inst
.instruction
|= INDEX_UP
;
7453 if (inst
.operands
[i
].shifted
)
7455 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7456 inst
.instruction
|= SHIFT_ROR
<< 5;
7459 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7460 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7464 else /* immediate offset in inst.reloc */
7466 if (is_pc
&& !inst
.reloc
.pc_rel
)
7468 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7470 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7471 cannot use PC in addressing.
7472 PC cannot be used in writeback addressing, either. */
7473 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7476 /* Use of PC in str is deprecated for ARMv7. */
7477 if (warn_on_deprecated
7479 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7480 as_tsktsk (_("use of PC in this instruction is deprecated"));
7483 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7485 /* Prefer + for zero encoded value. */
7486 if (!inst
.operands
[i
].negative
)
7487 inst
.instruction
|= INDEX_UP
;
7488 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7493 /* inst.operands[i] was set up by parse_address. Encode it into an
7494 ARM-format mode 3 load or store instruction. Reject forms that
7495 cannot be used with such instructions. If is_t is true, reject
7496 forms that cannot be used with a T instruction (i.e. not
7499 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7501 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7503 inst
.error
= _("instruction does not accept scaled register index");
7507 encode_arm_addr_mode_common (i
, is_t
);
7509 if (inst
.operands
[i
].immisreg
)
7511 constraint ((inst
.operands
[i
].imm
== REG_PC
7512 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7514 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7516 inst
.instruction
|= inst
.operands
[i
].imm
;
7517 if (!inst
.operands
[i
].negative
)
7518 inst
.instruction
|= INDEX_UP
;
7520 else /* immediate offset in inst.reloc */
7522 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7523 && inst
.operands
[i
].writeback
),
7525 inst
.instruction
|= HWOFFSET_IMM
;
7526 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7528 /* Prefer + for zero encoded value. */
7529 if (!inst
.operands
[i
].negative
)
7530 inst
.instruction
|= INDEX_UP
;
7532 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7537 /* Write immediate bits [7:0] to the following locations:
7539 |28/24|23 19|18 16|15 4|3 0|
7540 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7542 This function is used by VMOV/VMVN/VORR/VBIC. */
7545 neon_write_immbits (unsigned immbits
)
7547 inst
.instruction
|= immbits
& 0xf;
7548 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7549 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7552 /* Invert low-order SIZE bits of XHI:XLO. */
7555 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7557 unsigned immlo
= xlo
? *xlo
: 0;
7558 unsigned immhi
= xhi
? *xhi
: 0;
7563 immlo
= (~immlo
) & 0xff;
7567 immlo
= (~immlo
) & 0xffff;
7571 immhi
= (~immhi
) & 0xffffffff;
7575 immlo
= (~immlo
) & 0xffffffff;
7589 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7593 neon_bits_same_in_bytes (unsigned imm
)
7595 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7596 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7597 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7598 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7601 /* For immediate of above form, return 0bABCD. */
7604 neon_squash_bits (unsigned imm
)
7606 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7607 | ((imm
& 0x01000000) >> 21);
7610 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7613 neon_qfloat_bits (unsigned imm
)
7615 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7618 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7619 the instruction. *OP is passed as the initial value of the op field, and
7620 may be set to a different value depending on the constant (i.e.
7621 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7622 MVN). If the immediate looks like a repeated pattern then also
7623 try smaller element sizes. */
7626 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7627 unsigned *immbits
, int *op
, int size
,
7628 enum neon_el_type type
)
7630 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7632 if (type
== NT_float
&& !float_p
)
7635 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7637 if (size
!= 32 || *op
== 1)
7639 *immbits
= neon_qfloat_bits (immlo
);
7645 if (neon_bits_same_in_bytes (immhi
)
7646 && neon_bits_same_in_bytes (immlo
))
7650 *immbits
= (neon_squash_bits (immhi
) << 4)
7651 | neon_squash_bits (immlo
);
7662 if (immlo
== (immlo
& 0x000000ff))
7667 else if (immlo
== (immlo
& 0x0000ff00))
7669 *immbits
= immlo
>> 8;
7672 else if (immlo
== (immlo
& 0x00ff0000))
7674 *immbits
= immlo
>> 16;
7677 else if (immlo
== (immlo
& 0xff000000))
7679 *immbits
= immlo
>> 24;
7682 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7684 *immbits
= (immlo
>> 8) & 0xff;
7687 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7689 *immbits
= (immlo
>> 16) & 0xff;
7693 if ((immlo
& 0xffff) != (immlo
>> 16))
7700 if (immlo
== (immlo
& 0x000000ff))
7705 else if (immlo
== (immlo
& 0x0000ff00))
7707 *immbits
= immlo
>> 8;
7711 if ((immlo
& 0xff) != (immlo
>> 8))
7716 if (immlo
== (immlo
& 0x000000ff))
7718 /* Don't allow MVN with 8-bit immediate. */
7728 #if defined BFD_HOST_64_BIT
7729 /* Returns TRUE if double precision value V may be cast
7730 to single precision without loss of accuracy. */
7733 is_double_a_single (bfd_int64_t v
)
7735 int exp
= (int)((v
>> 52) & 0x7FF);
7736 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7738 return (exp
== 0 || exp
== 0x7FF
7739 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7740 && (mantissa
& 0x1FFFFFFFl
) == 0;
7743 /* Returns a double precision value casted to single precision
7744 (ignoring the least significant bits in exponent and mantissa). */
7747 double_to_single (bfd_int64_t v
)
7749 int sign
= (int) ((v
>> 63) & 1l);
7750 int exp
= (int) ((v
>> 52) & 0x7FF);
7751 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7757 exp
= exp
- 1023 + 127;
7766 /* No denormalized numbers. */
7772 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7774 #endif /* BFD_HOST_64_BIT */
7783 static void do_vfp_nsyn_opcode (const char *);
7785 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7786 Determine whether it can be performed with a move instruction; if
7787 it can, convert inst.instruction to that move instruction and
7788 return TRUE; if it can't, convert inst.instruction to a literal-pool
7789 load and return FALSE. If this is not a valid thing to do in the
7790 current context, set inst.error and return TRUE.
7792 inst.operands[i] describes the destination register. */
7795 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7798 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7799 bfd_boolean arm_p
= (t
== CONST_ARM
);
7802 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7806 if ((inst
.instruction
& tbit
) == 0)
7808 inst
.error
= _("invalid pseudo operation");
7812 if (inst
.reloc
.exp
.X_op
!= O_constant
7813 && inst
.reloc
.exp
.X_op
!= O_symbol
7814 && inst
.reloc
.exp
.X_op
!= O_big
)
7816 inst
.error
= _("constant expression expected");
7820 if (inst
.reloc
.exp
.X_op
== O_constant
7821 || inst
.reloc
.exp
.X_op
== O_big
)
7823 #if defined BFD_HOST_64_BIT
7828 if (inst
.reloc
.exp
.X_op
== O_big
)
7830 LITTLENUM_TYPE w
[X_PRECISION
];
7833 if (inst
.reloc
.exp
.X_add_number
== -1)
7835 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7837 /* FIXME: Should we check words w[2..5] ? */
7842 #if defined BFD_HOST_64_BIT
7844 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7845 << LITTLENUM_NUMBER_OF_BITS
)
7846 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7847 << LITTLENUM_NUMBER_OF_BITS
)
7848 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7849 << LITTLENUM_NUMBER_OF_BITS
)
7850 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7852 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7853 | (l
[0] & LITTLENUM_MASK
);
7857 v
= inst
.reloc
.exp
.X_add_number
;
7859 if (!inst
.operands
[i
].issingle
)
7863 /* This can be encoded only for a low register. */
7864 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7866 /* This can be done with a mov(1) instruction. */
7867 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7868 inst
.instruction
|= v
;
7872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7874 /* Check if on thumb2 it can be done with a mov.w, mvn or
7875 movw instruction. */
7876 unsigned int newimm
;
7877 bfd_boolean isNegated
;
7879 newimm
= encode_thumb32_immediate (v
);
7880 if (newimm
!= (unsigned int) FAIL
)
7884 newimm
= encode_thumb32_immediate (~v
);
7885 if (newimm
!= (unsigned int) FAIL
)
7889 /* The number can be loaded with a mov.w or mvn
7891 if (newimm
!= (unsigned int) FAIL
)
7893 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7894 | (inst
.operands
[i
].reg
<< 8));
7895 /* Change to MOVN. */
7896 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7897 inst
.instruction
|= (newimm
& 0x800) << 15;
7898 inst
.instruction
|= (newimm
& 0x700) << 4;
7899 inst
.instruction
|= (newimm
& 0x0ff);
7902 /* The number can be loaded with a movw instruction. */
7903 else if ((v
& ~0xFFFF) == 0)
7905 int imm
= v
& 0xFFFF;
7907 inst
.instruction
= 0xf2400000; /* MOVW. */
7908 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7909 inst
.instruction
|= (imm
& 0xf000) << 4;
7910 inst
.instruction
|= (imm
& 0x0800) << 15;
7911 inst
.instruction
|= (imm
& 0x0700) << 4;
7912 inst
.instruction
|= (imm
& 0x00ff);
7919 int value
= encode_arm_immediate (v
);
7923 /* This can be done with a mov instruction. */
7924 inst
.instruction
&= LITERAL_MASK
;
7925 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7926 inst
.instruction
|= value
& 0xfff;
7930 value
= encode_arm_immediate (~ v
);
7933 /* This can be done with a mvn instruction. */
7934 inst
.instruction
&= LITERAL_MASK
;
7935 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7936 inst
.instruction
|= value
& 0xfff;
7940 else if (t
== CONST_VEC
)
7943 unsigned immbits
= 0;
7944 unsigned immlo
= inst
.operands
[1].imm
;
7945 unsigned immhi
= inst
.operands
[1].regisimm
7946 ? inst
.operands
[1].reg
7947 : inst
.reloc
.exp
.X_unsigned
7949 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7950 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7951 &op
, 64, NT_invtype
);
7955 neon_invert_size (&immlo
, &immhi
, 64);
7957 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7958 &op
, 64, NT_invtype
);
7963 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7969 /* Fill other bits in vmov encoding for both thumb and arm. */
7971 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
7973 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
7974 neon_write_immbits (immbits
);
7982 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7983 if (inst
.operands
[i
].issingle
7984 && is_quarter_float (inst
.operands
[1].imm
)
7985 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
7987 inst
.operands
[1].imm
=
7988 neon_qfloat_bits (v
);
7989 do_vfp_nsyn_opcode ("fconsts");
7993 /* If our host does not support a 64-bit type then we cannot perform
7994 the following optimization. This mean that there will be a
7995 discrepancy between the output produced by an assembler built for
7996 a 32-bit-only host and the output produced from a 64-bit host, but
7997 this cannot be helped. */
7998 #if defined BFD_HOST_64_BIT
7999 else if (!inst
.operands
[1].issingle
8000 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8002 if (is_double_a_single (v
)
8003 && is_quarter_float (double_to_single (v
)))
8005 inst
.operands
[1].imm
=
8006 neon_qfloat_bits (double_to_single (v
));
8007 do_vfp_nsyn_opcode ("fconstd");
8015 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8016 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8019 inst
.operands
[1].reg
= REG_PC
;
8020 inst
.operands
[1].isreg
= 1;
8021 inst
.operands
[1].preind
= 1;
8022 inst
.reloc
.pc_rel
= 1;
8023 inst
.reloc
.type
= (thumb_p
8024 ? BFD_RELOC_ARM_THUMB_OFFSET
8026 ? BFD_RELOC_ARM_HWLITERAL
8027 : BFD_RELOC_ARM_LITERAL
));
8031 /* inst.operands[i] was set up by parse_address. Encode it into an
8032 ARM-format instruction. Reject all forms which cannot be encoded
8033 into a coprocessor load/store instruction. If wb_ok is false,
8034 reject use of writeback; if unind_ok is false, reject use of
8035 unindexed addressing. If reloc_override is not 0, use it instead
8036 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8037 (in which case it is preserved). */
8040 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8042 if (!inst
.operands
[i
].isreg
)
8045 if (! inst
.operands
[0].isvec
)
8047 inst
.error
= _("invalid co-processor operand");
8050 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8054 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8056 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8058 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8060 gas_assert (!inst
.operands
[i
].writeback
);
8063 inst
.error
= _("instruction does not support unindexed addressing");
8066 inst
.instruction
|= inst
.operands
[i
].imm
;
8067 inst
.instruction
|= INDEX_UP
;
8071 if (inst
.operands
[i
].preind
)
8072 inst
.instruction
|= PRE_INDEX
;
8074 if (inst
.operands
[i
].writeback
)
8076 if (inst
.operands
[i
].reg
== REG_PC
)
8078 inst
.error
= _("pc may not be used with write-back");
8083 inst
.error
= _("instruction does not support writeback");
8086 inst
.instruction
|= WRITE_BACK
;
8090 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8091 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8092 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8093 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8096 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8098 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8101 /* Prefer + for zero encoded value. */
8102 if (!inst
.operands
[i
].negative
)
8103 inst
.instruction
|= INDEX_UP
;
8108 /* Functions for instruction encoding, sorted by sub-architecture.
8109 First some generics; their names are taken from the conventional
8110 bit positions for register arguments in ARM format instructions. */
8120 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8127 inst
.instruction
|= inst
.operands
[1].reg
;
8133 inst
.instruction
|= inst
.operands
[0].reg
;
8134 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8141 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8147 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8148 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8152 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8154 if (ARM_CPU_IS_ANY (cpu_variant
))
8156 as_tsktsk ("%s", msg
);
8159 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8171 unsigned Rn
= inst
.operands
[2].reg
;
8172 /* Enforce restrictions on SWP instruction. */
8173 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8175 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8176 _("Rn must not overlap other operands"));
8178 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8180 if (!check_obsolete (&arm_ext_v8
,
8181 _("swp{b} use is obsoleted for ARMv8 and later"))
8182 && warn_on_deprecated
8183 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8184 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8188 inst
.instruction
|= inst
.operands
[1].reg
;
8189 inst
.instruction
|= Rn
<< 16;
8195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8196 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8197 inst
.instruction
|= inst
.operands
[2].reg
;
8203 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8204 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8205 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8206 || inst
.reloc
.exp
.X_add_number
!= 0),
8208 inst
.instruction
|= inst
.operands
[0].reg
;
8209 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8210 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8216 inst
.instruction
|= inst
.operands
[0].imm
;
8222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8223 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8226 /* ARM instructions, in alphabetical order by function name (except
8227 that wrapper functions appear immediately after the function they
8230 /* This is a pseudo-op of the form "adr rd, label" to be converted
8231 into a relative address of the form "add rd, pc, #label-.-8". */
8236 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8238 /* Frag hacking will turn this into a sub instruction if the offset turns
8239 out to be negative. */
8240 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8241 inst
.reloc
.pc_rel
= 1;
8242 inst
.reloc
.exp
.X_add_number
-= 8;
8245 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8246 into a relative address of the form:
8247 add rd, pc, #low(label-.-8)"
8248 add rd, rd, #high(label-.-8)" */
8253 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8255 /* Frag hacking will turn this into a sub instruction if the offset turns
8256 out to be negative. */
8257 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8258 inst
.reloc
.pc_rel
= 1;
8259 inst
.size
= INSN_SIZE
* 2;
8260 inst
.reloc
.exp
.X_add_number
-= 8;
8266 if (!inst
.operands
[1].present
)
8267 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8269 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8270 encode_arm_shifter_operand (2);
8276 if (inst
.operands
[0].present
)
8277 inst
.instruction
|= inst
.operands
[0].imm
;
8279 inst
.instruction
|= 0xf;
8285 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8286 constraint (msb
> 32, _("bit-field extends past end of register"));
8287 /* The instruction encoding stores the LSB and MSB,
8288 not the LSB and width. */
8289 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8290 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8291 inst
.instruction
|= (msb
- 1) << 16;
8299 /* #0 in second position is alternative syntax for bfc, which is
8300 the same instruction but with REG_PC in the Rm field. */
8301 if (!inst
.operands
[1].isreg
)
8302 inst
.operands
[1].reg
= REG_PC
;
8304 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8305 constraint (msb
> 32, _("bit-field extends past end of register"));
8306 /* The instruction encoding stores the LSB and MSB,
8307 not the LSB and width. */
8308 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8309 inst
.instruction
|= inst
.operands
[1].reg
;
8310 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8311 inst
.instruction
|= (msb
- 1) << 16;
8317 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8318 _("bit-field extends past end of register"));
8319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8320 inst
.instruction
|= inst
.operands
[1].reg
;
8321 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8322 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8325 /* ARM V5 breakpoint instruction (argument parse)
8326 BKPT <16 bit unsigned immediate>
8327 Instruction is not conditional.
8328 The bit pattern given in insns[] has the COND_ALWAYS condition,
8329 and it is an error if the caller tried to override that. */
8334 /* Top 12 of 16 bits to bits 19:8. */
8335 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8337 /* Bottom 4 of 16 bits to bits 3:0. */
8338 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8342 encode_branch (int default_reloc
)
8344 if (inst
.operands
[0].hasreloc
)
8346 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8347 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8348 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8349 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8350 ? BFD_RELOC_ARM_PLT32
8351 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8354 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8355 inst
.reloc
.pc_rel
= 1;
8362 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8363 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8366 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8373 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8375 if (inst
.cond
== COND_ALWAYS
)
8376 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8378 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8382 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8385 /* ARM V5 branch-link-exchange instruction (argument parse)
8386 BLX <target_addr> ie BLX(1)
8387 BLX{<condition>} <Rm> ie BLX(2)
8388 Unfortunately, there are two different opcodes for this mnemonic.
8389 So, the insns[].value is not used, and the code here zaps values
8390 into inst.instruction.
8391 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8396 if (inst
.operands
[0].isreg
)
8398 /* Arg is a register; the opcode provided by insns[] is correct.
8399 It is not illegal to do "blx pc", just useless. */
8400 if (inst
.operands
[0].reg
== REG_PC
)
8401 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8403 inst
.instruction
|= inst
.operands
[0].reg
;
8407 /* Arg is an address; this instruction cannot be executed
8408 conditionally, and the opcode must be adjusted.
8409 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8410 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8411 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8412 inst
.instruction
= 0xfa000000;
8413 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8420 bfd_boolean want_reloc
;
8422 if (inst
.operands
[0].reg
== REG_PC
)
8423 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8425 inst
.instruction
|= inst
.operands
[0].reg
;
8426 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8427 it is for ARMv4t or earlier. */
8428 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8429 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8433 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8438 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8442 /* ARM v5TEJ. Jump to Jazelle code. */
8447 if (inst
.operands
[0].reg
== REG_PC
)
8448 as_tsktsk (_("use of r15 in bxj is not really useful"));
8450 inst
.instruction
|= inst
.operands
[0].reg
;
8453 /* Co-processor data operation:
8454 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8455 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8459 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8460 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8461 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8462 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8463 inst
.instruction
|= inst
.operands
[4].reg
;
8464 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8470 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8471 encode_arm_shifter_operand (1);
8474 /* Transfer between coprocessor and ARM registers.
8475 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8480 No special properties. */
8482 struct deprecated_coproc_regs_s
8489 arm_feature_set deprecated
;
8490 arm_feature_set obsoleted
;
8491 const char *dep_msg
;
8492 const char *obs_msg
;
8495 #define DEPR_ACCESS_V8 \
8496 N_("This coprocessor register access is deprecated in ARMv8")
8498 /* Table of all deprecated coprocessor registers. */
8499 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8501 {15, 0, 7, 10, 5, /* CP15DMB. */
8502 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8503 DEPR_ACCESS_V8
, NULL
},
8504 {15, 0, 7, 10, 4, /* CP15DSB. */
8505 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8506 DEPR_ACCESS_V8
, NULL
},
8507 {15, 0, 7, 5, 4, /* CP15ISB. */
8508 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8509 DEPR_ACCESS_V8
, NULL
},
8510 {14, 6, 1, 0, 0, /* TEEHBR. */
8511 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8512 DEPR_ACCESS_V8
, NULL
},
8513 {14, 6, 0, 0, 0, /* TEECR. */
8514 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8515 DEPR_ACCESS_V8
, NULL
},
8518 #undef DEPR_ACCESS_V8
8520 static const size_t deprecated_coproc_reg_count
=
8521 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8529 Rd
= inst
.operands
[2].reg
;
8532 if (inst
.instruction
== 0xee000010
8533 || inst
.instruction
== 0xfe000010)
8535 reject_bad_reg (Rd
);
8538 constraint (Rd
== REG_SP
, BAD_SP
);
8543 if (inst
.instruction
== 0xe000010)
8544 constraint (Rd
== REG_PC
, BAD_PC
);
8547 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8549 const struct deprecated_coproc_regs_s
*r
=
8550 deprecated_coproc_regs
+ i
;
8552 if (inst
.operands
[0].reg
== r
->cp
8553 && inst
.operands
[1].imm
== r
->opc1
8554 && inst
.operands
[3].reg
== r
->crn
8555 && inst
.operands
[4].reg
== r
->crm
8556 && inst
.operands
[5].imm
== r
->opc2
)
8558 if (! ARM_CPU_IS_ANY (cpu_variant
)
8559 && warn_on_deprecated
8560 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8561 as_tsktsk ("%s", r
->dep_msg
);
8565 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8566 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8567 inst
.instruction
|= Rd
<< 12;
8568 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8569 inst
.instruction
|= inst
.operands
[4].reg
;
8570 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8573 /* Transfer between coprocessor register and pair of ARM registers.
8574 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8579 Two XScale instructions are special cases of these:
8581 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8582 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8584 Result unpredictable if Rd or Rn is R15. */
8591 Rd
= inst
.operands
[2].reg
;
8592 Rn
= inst
.operands
[3].reg
;
8596 reject_bad_reg (Rd
);
8597 reject_bad_reg (Rn
);
8601 constraint (Rd
== REG_PC
, BAD_PC
);
8602 constraint (Rn
== REG_PC
, BAD_PC
);
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8606 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8607 inst
.instruction
|= Rd
<< 12;
8608 inst
.instruction
|= Rn
<< 16;
8609 inst
.instruction
|= inst
.operands
[4].reg
;
8615 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8616 if (inst
.operands
[1].present
)
8618 inst
.instruction
|= CPSI_MMOD
;
8619 inst
.instruction
|= inst
.operands
[1].imm
;
8626 inst
.instruction
|= inst
.operands
[0].imm
;
8632 unsigned Rd
, Rn
, Rm
;
8634 Rd
= inst
.operands
[0].reg
;
8635 Rn
= (inst
.operands
[1].present
8636 ? inst
.operands
[1].reg
: Rd
);
8637 Rm
= inst
.operands
[2].reg
;
8639 constraint ((Rd
== REG_PC
), BAD_PC
);
8640 constraint ((Rn
== REG_PC
), BAD_PC
);
8641 constraint ((Rm
== REG_PC
), BAD_PC
);
8643 inst
.instruction
|= Rd
<< 16;
8644 inst
.instruction
|= Rn
<< 0;
8645 inst
.instruction
|= Rm
<< 8;
8651 /* There is no IT instruction in ARM mode. We
8652 process it to do the validation as if in
8653 thumb mode, just in case the code gets
8654 assembled for thumb using the unified syntax. */
8659 set_it_insn_type (IT_INSN
);
8660 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8661 now_it
.cc
= inst
.operands
[0].imm
;
8665 /* If there is only one register in the register list,
8666 then return its register number. Otherwise return -1. */
8668 only_one_reg_in_list (int range
)
8670 int i
= ffs (range
) - 1;
8671 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8675 encode_ldmstm(int from_push_pop_mnem
)
8677 int base_reg
= inst
.operands
[0].reg
;
8678 int range
= inst
.operands
[1].imm
;
8681 inst
.instruction
|= base_reg
<< 16;
8682 inst
.instruction
|= range
;
8684 if (inst
.operands
[1].writeback
)
8685 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8687 if (inst
.operands
[0].writeback
)
8689 inst
.instruction
|= WRITE_BACK
;
8690 /* Check for unpredictable uses of writeback. */
8691 if (inst
.instruction
& LOAD_BIT
)
8693 /* Not allowed in LDM type 2. */
8694 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8695 && ((range
& (1 << REG_PC
)) == 0))
8696 as_warn (_("writeback of base register is UNPREDICTABLE"));
8697 /* Only allowed if base reg not in list for other types. */
8698 else if (range
& (1 << base_reg
))
8699 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8703 /* Not allowed for type 2. */
8704 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8705 as_warn (_("writeback of base register is UNPREDICTABLE"));
8706 /* Only allowed if base reg not in list, or first in list. */
8707 else if ((range
& (1 << base_reg
))
8708 && (range
& ((1 << base_reg
) - 1)))
8709 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8713 /* If PUSH/POP has only one register, then use the A2 encoding. */
8714 one_reg
= only_one_reg_in_list (range
);
8715 if (from_push_pop_mnem
&& one_reg
>= 0)
8717 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8719 inst
.instruction
&= A_COND_MASK
;
8720 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8721 inst
.instruction
|= one_reg
<< 12;
8728 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8731 /* ARMv5TE load-consecutive (argument parse)
8740 constraint (inst
.operands
[0].reg
% 2 != 0,
8741 _("first transfer register must be even"));
8742 constraint (inst
.operands
[1].present
8743 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8744 _("can only transfer two consecutive registers"));
8745 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8746 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8748 if (!inst
.operands
[1].present
)
8749 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8751 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8752 register and the first register written; we have to diagnose
8753 overlap between the base and the second register written here. */
8755 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8756 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8757 as_warn (_("base register written back, and overlaps "
8758 "second transfer register"));
8760 if (!(inst
.instruction
& V4_STR_BIT
))
8762 /* For an index-register load, the index register must not overlap the
8763 destination (even if not write-back). */
8764 if (inst
.operands
[2].immisreg
8765 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8766 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8767 as_warn (_("index register overlaps transfer register"));
8769 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8770 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8776 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8777 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8778 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8779 || inst
.operands
[1].negative
8780 /* This can arise if the programmer has written
8782 or if they have mistakenly used a register name as the last
8785 It is very difficult to distinguish between these two cases
8786 because "rX" might actually be a label. ie the register
8787 name has been occluded by a symbol of the same name. So we
8788 just generate a general 'bad addressing mode' type error
8789 message and leave it up to the programmer to discover the
8790 true cause and fix their mistake. */
8791 || (inst
.operands
[1].reg
== REG_PC
),
8794 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8795 || inst
.reloc
.exp
.X_add_number
!= 0,
8796 _("offset must be zero in ARM encoding"));
8798 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8801 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8802 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8808 constraint (inst
.operands
[0].reg
% 2 != 0,
8809 _("even register required"));
8810 constraint (inst
.operands
[1].present
8811 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8812 _("can only load two consecutive registers"));
8813 /* If op 1 were present and equal to PC, this function wouldn't
8814 have been called in the first place. */
8815 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8817 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8818 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8821 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8822 which is not a multiple of four is UNPREDICTABLE. */
8824 check_ldr_r15_aligned (void)
8826 constraint (!(inst
.operands
[1].immisreg
)
8827 && (inst
.operands
[0].reg
== REG_PC
8828 && inst
.operands
[1].reg
== REG_PC
8829 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8830 _("ldr to register 15 must be 4-byte alligned"));
8836 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8837 if (!inst
.operands
[1].isreg
)
8838 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8840 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8841 check_ldr_r15_aligned ();
8847 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8849 if (inst
.operands
[1].preind
)
8851 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8852 || inst
.reloc
.exp
.X_add_number
!= 0,
8853 _("this instruction requires a post-indexed address"));
8855 inst
.operands
[1].preind
= 0;
8856 inst
.operands
[1].postind
= 1;
8857 inst
.operands
[1].writeback
= 1;
8859 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8860 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8863 /* Halfword and signed-byte load/store operations. */
8868 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8869 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8870 if (!inst
.operands
[1].isreg
)
8871 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8873 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8879 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8881 if (inst
.operands
[1].preind
)
8883 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8884 || inst
.reloc
.exp
.X_add_number
!= 0,
8885 _("this instruction requires a post-indexed address"));
8887 inst
.operands
[1].preind
= 0;
8888 inst
.operands
[1].postind
= 1;
8889 inst
.operands
[1].writeback
= 1;
8891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8892 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8895 /* Co-processor register load/store.
8896 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8900 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8901 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8902 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8908 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8909 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8910 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8911 && !(inst
.instruction
& 0x00400000))
8912 as_tsktsk (_("Rd and Rm should be different in mla"));
8914 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8915 inst
.instruction
|= inst
.operands
[1].reg
;
8916 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8917 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 encode_arm_shifter_operand (1);
8927 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8934 top
= (inst
.instruction
& 0x00400000) != 0;
8935 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8936 _(":lower16: not allowed this instruction"));
8937 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8938 _(":upper16: not allowed instruction"));
8939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8940 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8942 imm
= inst
.reloc
.exp
.X_add_number
;
8943 /* The value is in two pieces: 0:11, 16:19. */
8944 inst
.instruction
|= (imm
& 0x00000fff);
8945 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8950 do_vfp_nsyn_mrs (void)
8952 if (inst
.operands
[0].isvec
)
8954 if (inst
.operands
[1].reg
!= 1)
8955 first_error (_("operand 1 must be FPSCR"));
8956 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8957 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8958 do_vfp_nsyn_opcode ("fmstat");
8960 else if (inst
.operands
[1].isvec
)
8961 do_vfp_nsyn_opcode ("fmrx");
8969 do_vfp_nsyn_msr (void)
8971 if (inst
.operands
[0].isvec
)
8972 do_vfp_nsyn_opcode ("fmxr");
8982 unsigned Rt
= inst
.operands
[0].reg
;
8984 if (thumb_mode
&& Rt
== REG_SP
)
8986 inst
.error
= BAD_SP
;
8990 /* APSR_ sets isvec. All other refs to PC are illegal. */
8991 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8993 inst
.error
= BAD_PC
;
8997 /* If we get through parsing the register name, we just insert the number
8998 generated into the instruction without further validation. */
8999 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9000 inst
.instruction
|= (Rt
<< 12);
9006 unsigned Rt
= inst
.operands
[1].reg
;
9009 reject_bad_reg (Rt
);
9010 else if (Rt
== REG_PC
)
9012 inst
.error
= BAD_PC
;
9016 /* If we get through parsing the register name, we just insert the number
9017 generated into the instruction without further validation. */
9018 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9019 inst
.instruction
|= (Rt
<< 12);
9027 if (do_vfp_nsyn_mrs () == SUCCESS
)
9030 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9033 if (inst
.operands
[1].isreg
)
9035 br
= inst
.operands
[1].reg
;
9036 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9037 as_bad (_("bad register for mrs"));
9041 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9042 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9044 _("'APSR', 'CPSR' or 'SPSR' expected"));
9045 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9048 inst
.instruction
|= br
;
9051 /* Two possible forms:
9052 "{C|S}PSR_<field>, Rm",
9053 "{C|S}PSR_f, #expression". */
9058 if (do_vfp_nsyn_msr () == SUCCESS
)
9061 inst
.instruction
|= inst
.operands
[0].imm
;
9062 if (inst
.operands
[1].isreg
)
9063 inst
.instruction
|= inst
.operands
[1].reg
;
9066 inst
.instruction
|= INST_IMMEDIATE
;
9067 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9068 inst
.reloc
.pc_rel
= 0;
9075 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9077 if (!inst
.operands
[2].present
)
9078 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9079 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9080 inst
.instruction
|= inst
.operands
[1].reg
;
9081 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9083 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9084 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9085 as_tsktsk (_("Rd and Rm should be different in mul"));
9088 /* Long Multiply Parser
9089 UMULL RdLo, RdHi, Rm, Rs
9090 SMULL RdLo, RdHi, Rm, Rs
9091 UMLAL RdLo, RdHi, Rm, Rs
9092 SMLAL RdLo, RdHi, Rm, Rs. */
9097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9098 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9099 inst
.instruction
|= inst
.operands
[2].reg
;
9100 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9102 /* rdhi and rdlo must be different. */
9103 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9104 as_tsktsk (_("rdhi and rdlo must be different"));
9106 /* rdhi, rdlo and rm must all be different before armv6. */
9107 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9108 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9109 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9110 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9116 if (inst
.operands
[0].present
9117 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9119 /* Architectural NOP hints are CPSR sets with no bits selected. */
9120 inst
.instruction
&= 0xf0000000;
9121 inst
.instruction
|= 0x0320f000;
9122 if (inst
.operands
[0].present
)
9123 inst
.instruction
|= inst
.operands
[0].imm
;
9127 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9128 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9129 Condition defaults to COND_ALWAYS.
9130 Error if Rd, Rn or Rm are R15. */
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9137 inst
.instruction
|= inst
.operands
[2].reg
;
9138 if (inst
.operands
[3].present
)
9139 encode_arm_shift (3);
9142 /* ARM V6 PKHTB (Argument Parse). */
9147 if (!inst
.operands
[3].present
)
9149 /* If the shift specifier is omitted, turn the instruction
9150 into pkhbt rd, rm, rn. */
9151 inst
.instruction
&= 0xfff00010;
9152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9153 inst
.instruction
|= inst
.operands
[1].reg
;
9154 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9159 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9160 inst
.instruction
|= inst
.operands
[2].reg
;
9161 encode_arm_shift (3);
9165 /* ARMv5TE: Preload-Cache
9166 MP Extensions: Preload for write
9170 Syntactically, like LDR with B=1, W=0, L=1. */
9175 constraint (!inst
.operands
[0].isreg
,
9176 _("'[' expected after PLD mnemonic"));
9177 constraint (inst
.operands
[0].postind
,
9178 _("post-indexed expression used in preload instruction"));
9179 constraint (inst
.operands
[0].writeback
,
9180 _("writeback used in preload instruction"));
9181 constraint (!inst
.operands
[0].preind
,
9182 _("unindexed addressing used in preload instruction"));
9183 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9186 /* ARMv7: PLI <addr_mode> */
9190 constraint (!inst
.operands
[0].isreg
,
9191 _("'[' expected after PLI mnemonic"));
9192 constraint (inst
.operands
[0].postind
,
9193 _("post-indexed expression used in preload instruction"));
9194 constraint (inst
.operands
[0].writeback
,
9195 _("writeback used in preload instruction"));
9196 constraint (!inst
.operands
[0].preind
,
9197 _("unindexed addressing used in preload instruction"));
9198 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9199 inst
.instruction
&= ~PRE_INDEX
;
9205 constraint (inst
.operands
[0].writeback
,
9206 _("push/pop do not support {reglist}^"));
9207 inst
.operands
[1] = inst
.operands
[0];
9208 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9209 inst
.operands
[0].isreg
= 1;
9210 inst
.operands
[0].writeback
= 1;
9211 inst
.operands
[0].reg
= REG_SP
;
9212 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9215 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9216 word at the specified address and the following word
9218 Unconditionally executed.
9219 Error if Rn is R15. */
9224 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9225 if (inst
.operands
[0].writeback
)
9226 inst
.instruction
|= WRITE_BACK
;
9229 /* ARM V6 ssat (argument parse). */
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9235 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9236 inst
.instruction
|= inst
.operands
[2].reg
;
9238 if (inst
.operands
[3].present
)
9239 encode_arm_shift (3);
9242 /* ARM V6 usat (argument parse). */
9247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9248 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9249 inst
.instruction
|= inst
.operands
[2].reg
;
9251 if (inst
.operands
[3].present
)
9252 encode_arm_shift (3);
9255 /* ARM V6 ssat16 (argument parse). */
9260 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9261 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9262 inst
.instruction
|= inst
.operands
[2].reg
;
9268 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9269 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9270 inst
.instruction
|= inst
.operands
[2].reg
;
9273 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9274 preserving the other bits.
9276 setend <endian_specifier>, where <endian_specifier> is either
9282 if (warn_on_deprecated
9283 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9284 as_tsktsk (_("setend use is deprecated for ARMv8"));
9286 if (inst
.operands
[0].imm
)
9287 inst
.instruction
|= 0x200;
9293 unsigned int Rm
= (inst
.operands
[1].present
9294 ? inst
.operands
[1].reg
9295 : inst
.operands
[0].reg
);
9297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9298 inst
.instruction
|= Rm
;
9299 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9301 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9302 inst
.instruction
|= SHIFT_BY_REG
;
9303 /* PR 12854: Error on extraneous shifts. */
9304 constraint (inst
.operands
[2].shifted
,
9305 _("extraneous shift as part of operand to shift insn"));
9308 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9314 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9315 inst
.reloc
.pc_rel
= 0;
9321 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9322 inst
.reloc
.pc_rel
= 0;
9328 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9329 inst
.reloc
.pc_rel
= 0;
9335 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9336 _("selected processor does not support SETPAN instruction"));
9338 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9345 _("selected processor does not support SETPAN instruction"));
9347 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9350 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9351 SMLAxy{cond} Rd,Rm,Rs,Rn
9352 SMLAWy{cond} Rd,Rm,Rs,Rn
9353 Error if any register is R15. */
9358 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9359 inst
.instruction
|= inst
.operands
[1].reg
;
9360 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9361 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9364 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9365 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9366 Error if any register is R15.
9367 Warning if Rdlo == Rdhi. */
9372 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9373 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9374 inst
.instruction
|= inst
.operands
[2].reg
;
9375 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9377 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9378 as_tsktsk (_("rdhi and rdlo must be different"));
9381 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9382 SMULxy{cond} Rd,Rm,Rs
9383 Error if any register is R15. */
9388 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9389 inst
.instruction
|= inst
.operands
[1].reg
;
9390 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9393 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9394 the same for both ARM and Thumb-2. */
9401 if (inst
.operands
[0].present
)
9403 reg
= inst
.operands
[0].reg
;
9404 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9409 inst
.instruction
|= reg
<< 16;
9410 inst
.instruction
|= inst
.operands
[1].imm
;
9411 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9412 inst
.instruction
|= WRITE_BACK
;
9415 /* ARM V6 strex (argument parse). */
9420 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9421 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9422 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9423 || inst
.operands
[2].negative
9424 /* See comment in do_ldrex(). */
9425 || (inst
.operands
[2].reg
== REG_PC
),
9428 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9429 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9431 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9432 || inst
.reloc
.exp
.X_add_number
!= 0,
9433 _("offset must be zero in ARM encoding"));
9435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9436 inst
.instruction
|= inst
.operands
[1].reg
;
9437 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9438 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9444 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9445 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9446 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9447 || inst
.operands
[2].negative
,
9450 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9451 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9459 constraint (inst
.operands
[1].reg
% 2 != 0,
9460 _("even register required"));
9461 constraint (inst
.operands
[2].present
9462 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9463 _("can only store two consecutive registers"));
9464 /* If op 2 were present and equal to PC, this function wouldn't
9465 have been called in the first place. */
9466 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9468 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9469 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9470 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9474 inst
.instruction
|= inst
.operands
[1].reg
;
9475 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9482 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9483 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9491 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9492 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9497 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9498 extends it to 32-bits, and adds the result to a value in another
9499 register. You can specify a rotation by 0, 8, 16, or 24 bits
9500 before extracting the 16-bit value.
9501 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9502 Condition defaults to COND_ALWAYS.
9503 Error if any register uses R15. */
9508 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9509 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9510 inst
.instruction
|= inst
.operands
[2].reg
;
9511 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9516 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9517 Condition defaults to COND_ALWAYS.
9518 Error if any register uses R15. */
9523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9524 inst
.instruction
|= inst
.operands
[1].reg
;
9525 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9528 /* VFP instructions. In a logical order: SP variant first, monad
9529 before dyad, arithmetic then move then load/store. */
9532 do_vfp_sp_monadic (void)
9534 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9535 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9539 do_vfp_sp_dyadic (void)
9541 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9542 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9543 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9547 do_vfp_sp_compare_z (void)
9549 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9553 do_vfp_dp_sp_cvt (void)
9555 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9556 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9560 do_vfp_sp_dp_cvt (void)
9562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9563 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9567 do_vfp_reg_from_sp (void)
9569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9570 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9574 do_vfp_reg2_from_sp2 (void)
9576 constraint (inst
.operands
[2].imm
!= 2,
9577 _("only two consecutive VFP SP registers allowed here"));
9578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9579 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9580 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9584 do_vfp_sp_from_reg (void)
9586 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9587 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9591 do_vfp_sp2_from_reg2 (void)
9593 constraint (inst
.operands
[0].imm
!= 2,
9594 _("only two consecutive VFP SP registers allowed here"));
9595 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9596 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9597 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9601 do_vfp_sp_ldst (void)
9603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9604 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9608 do_vfp_dp_ldst (void)
9610 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9611 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9616 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9618 if (inst
.operands
[0].writeback
)
9619 inst
.instruction
|= WRITE_BACK
;
9621 constraint (ldstm_type
!= VFP_LDSTMIA
,
9622 _("this addressing mode requires base-register writeback"));
9623 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9624 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9625 inst
.instruction
|= inst
.operands
[1].imm
;
9629 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9633 if (inst
.operands
[0].writeback
)
9634 inst
.instruction
|= WRITE_BACK
;
9636 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9637 _("this addressing mode requires base-register writeback"));
9639 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9640 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9642 count
= inst
.operands
[1].imm
<< 1;
9643 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9646 inst
.instruction
|= count
;
9650 do_vfp_sp_ldstmia (void)
9652 vfp_sp_ldstm (VFP_LDSTMIA
);
9656 do_vfp_sp_ldstmdb (void)
9658 vfp_sp_ldstm (VFP_LDSTMDB
);
9662 do_vfp_dp_ldstmia (void)
9664 vfp_dp_ldstm (VFP_LDSTMIA
);
9668 do_vfp_dp_ldstmdb (void)
9670 vfp_dp_ldstm (VFP_LDSTMDB
);
9674 do_vfp_xp_ldstmia (void)
9676 vfp_dp_ldstm (VFP_LDSTMIAX
);
9680 do_vfp_xp_ldstmdb (void)
9682 vfp_dp_ldstm (VFP_LDSTMDBX
);
9686 do_vfp_dp_rd_rm (void)
9688 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9689 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9693 do_vfp_dp_rn_rd (void)
9695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9696 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9700 do_vfp_dp_rd_rn (void)
9702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9703 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9707 do_vfp_dp_rd_rn_rm (void)
9709 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9710 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9711 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9721 do_vfp_dp_rm_rd_rn (void)
9723 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9724 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9725 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9728 /* VFPv3 instructions. */
9730 do_vfp_sp_const (void)
9732 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9733 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9734 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9738 do_vfp_dp_const (void)
9740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9741 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9742 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9746 vfp_conv (int srcsize
)
9748 int immbits
= srcsize
- inst
.operands
[1].imm
;
9750 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9752 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9753 i.e. immbits must be in range 0 - 16. */
9754 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9757 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9759 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9760 i.e. immbits must be in range 0 - 31. */
9761 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9765 inst
.instruction
|= (immbits
& 1) << 5;
9766 inst
.instruction
|= (immbits
>> 1);
9770 do_vfp_sp_conv_16 (void)
9772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9777 do_vfp_dp_conv_16 (void)
9779 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9784 do_vfp_sp_conv_32 (void)
9786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9791 do_vfp_dp_conv_32 (void)
9793 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9797 /* FPA instructions. Also in a logical order. */
9802 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9803 inst
.instruction
|= inst
.operands
[1].reg
;
9807 do_fpa_ldmstm (void)
9809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9810 switch (inst
.operands
[1].imm
)
9812 case 1: inst
.instruction
|= CP_T_X
; break;
9813 case 2: inst
.instruction
|= CP_T_Y
; break;
9814 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9819 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9821 /* The instruction specified "ea" or "fd", so we can only accept
9822 [Rn]{!}. The instruction does not really support stacking or
9823 unstacking, so we have to emulate these by setting appropriate
9824 bits and offsets. */
9825 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9826 || inst
.reloc
.exp
.X_add_number
!= 0,
9827 _("this instruction does not support indexing"));
9829 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9830 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9832 if (!(inst
.instruction
& INDEX_UP
))
9833 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9835 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9837 inst
.operands
[2].preind
= 0;
9838 inst
.operands
[2].postind
= 1;
9842 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9845 /* iWMMXt instructions: strictly in alphabetical order. */
9848 do_iwmmxt_tandorc (void)
9850 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9854 do_iwmmxt_textrc (void)
9856 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9857 inst
.instruction
|= inst
.operands
[1].imm
;
9861 do_iwmmxt_textrm (void)
9863 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9864 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9865 inst
.instruction
|= inst
.operands
[2].imm
;
9869 do_iwmmxt_tinsr (void)
9871 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9872 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9873 inst
.instruction
|= inst
.operands
[2].imm
;
9877 do_iwmmxt_tmia (void)
9879 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9880 inst
.instruction
|= inst
.operands
[1].reg
;
9881 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9885 do_iwmmxt_waligni (void)
9887 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9888 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9889 inst
.instruction
|= inst
.operands
[2].reg
;
9890 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9894 do_iwmmxt_wmerge (void)
9896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9897 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9898 inst
.instruction
|= inst
.operands
[2].reg
;
9899 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9903 do_iwmmxt_wmov (void)
9905 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9907 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9908 inst
.instruction
|= inst
.operands
[1].reg
;
9912 do_iwmmxt_wldstbh (void)
9915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9917 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9919 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9920 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9924 do_iwmmxt_wldstw (void)
9926 /* RIWR_RIWC clears .isreg for a control register. */
9927 if (!inst
.operands
[0].isreg
)
9929 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9930 inst
.instruction
|= 0xf0000000;
9933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9934 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9938 do_iwmmxt_wldstd (void)
9940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9941 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9942 && inst
.operands
[1].immisreg
)
9944 inst
.instruction
&= ~0x1a000ff;
9945 inst
.instruction
|= (0xfU
<< 28);
9946 if (inst
.operands
[1].preind
)
9947 inst
.instruction
|= PRE_INDEX
;
9948 if (!inst
.operands
[1].negative
)
9949 inst
.instruction
|= INDEX_UP
;
9950 if (inst
.operands
[1].writeback
)
9951 inst
.instruction
|= WRITE_BACK
;
9952 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9953 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9954 inst
.instruction
|= inst
.operands
[1].imm
;
9957 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9961 do_iwmmxt_wshufh (void)
9963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9964 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9965 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9966 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9970 do_iwmmxt_wzero (void)
9972 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9973 inst
.instruction
|= inst
.operands
[0].reg
;
9974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9975 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9979 do_iwmmxt_wrwrwr_or_imm5 (void)
9981 if (inst
.operands
[2].isreg
)
9984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9985 _("immediate operand requires iWMMXt2"));
9987 if (inst
.operands
[2].imm
== 0)
9989 switch ((inst
.instruction
>> 20) & 0xf)
9995 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9996 inst
.operands
[2].imm
= 16;
9997 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10003 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10004 inst
.operands
[2].imm
= 32;
10005 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10012 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10014 wrn
= (inst
.instruction
>> 16) & 0xf;
10015 inst
.instruction
&= 0xff0fff0f;
10016 inst
.instruction
|= wrn
;
10017 /* Bail out here; the instruction is now assembled. */
10022 /* Map 32 -> 0, etc. */
10023 inst
.operands
[2].imm
&= 0x1f;
10024 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10028 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10029 operations first, then control, shift, and load/store. */
10031 /* Insns like "foo X,Y,Z". */
10034 do_mav_triple (void)
10036 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10037 inst
.instruction
|= inst
.operands
[1].reg
;
10038 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10041 /* Insns like "foo W,X,Y,Z".
10042 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10047 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10048 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10049 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10050 inst
.instruction
|= inst
.operands
[3].reg
;
10053 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10055 do_mav_dspsc (void)
10057 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10060 /* Maverick shift immediate instructions.
10061 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10062 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10065 do_mav_shift (void)
10067 int imm
= inst
.operands
[2].imm
;
10069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10070 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10072 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10073 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10074 Bit 4 should be 0. */
10075 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10077 inst
.instruction
|= imm
;
10080 /* XScale instructions. Also sorted arithmetic before move. */
10082 /* Xscale multiply-accumulate (argument parse)
10085 MIAxycc acc0,Rm,Rs. */
10090 inst
.instruction
|= inst
.operands
[1].reg
;
10091 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10094 /* Xscale move-accumulator-register (argument parse)
10096 MARcc acc0,RdLo,RdHi. */
10101 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10102 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10105 /* Xscale move-register-accumulator (argument parse)
10107 MRAcc RdLo,RdHi,acc0. */
10112 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10114 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10117 /* Encoding functions relevant only to Thumb. */
10119 /* inst.operands[i] is a shifted-register operand; encode
10120 it into inst.instruction in the format used by Thumb32. */
10123 encode_thumb32_shifted_operand (int i
)
10125 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10126 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10128 constraint (inst
.operands
[i
].immisreg
,
10129 _("shift by register not allowed in thumb mode"));
10130 inst
.instruction
|= inst
.operands
[i
].reg
;
10131 if (shift
== SHIFT_RRX
)
10132 inst
.instruction
|= SHIFT_ROR
<< 4;
10135 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10136 _("expression too complex"));
10138 constraint (value
> 32
10139 || (value
== 32 && (shift
== SHIFT_LSL
10140 || shift
== SHIFT_ROR
)),
10141 _("shift expression is too large"));
10145 else if (value
== 32)
10148 inst
.instruction
|= shift
<< 4;
10149 inst
.instruction
|= (value
& 0x1c) << 10;
10150 inst
.instruction
|= (value
& 0x03) << 6;
10155 /* inst.operands[i] was set up by parse_address. Encode it into a
10156 Thumb32 format load or store instruction. Reject forms that cannot
10157 be used with such instructions. If is_t is true, reject forms that
10158 cannot be used with a T instruction; if is_d is true, reject forms
10159 that cannot be used with a D instruction. If it is a store insn,
10160 reject PC in Rn. */
10163 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10165 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10167 constraint (!inst
.operands
[i
].isreg
,
10168 _("Instruction does not support =N addresses"));
10170 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10171 if (inst
.operands
[i
].immisreg
)
10173 constraint (is_pc
, BAD_PC_ADDRESSING
);
10174 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10175 constraint (inst
.operands
[i
].negative
,
10176 _("Thumb does not support negative register indexing"));
10177 constraint (inst
.operands
[i
].postind
,
10178 _("Thumb does not support register post-indexing"));
10179 constraint (inst
.operands
[i
].writeback
,
10180 _("Thumb does not support register indexing with writeback"));
10181 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10182 _("Thumb supports only LSL in shifted register indexing"));
10184 inst
.instruction
|= inst
.operands
[i
].imm
;
10185 if (inst
.operands
[i
].shifted
)
10187 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10188 _("expression too complex"));
10189 constraint (inst
.reloc
.exp
.X_add_number
< 0
10190 || inst
.reloc
.exp
.X_add_number
> 3,
10191 _("shift out of range"));
10192 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10194 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10196 else if (inst
.operands
[i
].preind
)
10198 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10199 constraint (is_t
&& inst
.operands
[i
].writeback
,
10200 _("cannot use writeback with this instruction"));
10201 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10202 BAD_PC_ADDRESSING
);
10206 inst
.instruction
|= 0x01000000;
10207 if (inst
.operands
[i
].writeback
)
10208 inst
.instruction
|= 0x00200000;
10212 inst
.instruction
|= 0x00000c00;
10213 if (inst
.operands
[i
].writeback
)
10214 inst
.instruction
|= 0x00000100;
10216 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10218 else if (inst
.operands
[i
].postind
)
10220 gas_assert (inst
.operands
[i
].writeback
);
10221 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10222 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10225 inst
.instruction
|= 0x00200000;
10227 inst
.instruction
|= 0x00000900;
10228 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10230 else /* unindexed - only for coprocessor */
10231 inst
.error
= _("instruction does not accept unindexed addressing");
10234 /* Table of Thumb instructions which exist in both 16- and 32-bit
10235 encodings (the latter only in post-V6T2 cores). The index is the
10236 value used in the insns table below. When there is more than one
10237 possible 16-bit encoding for the instruction, this table always
10239 Also contains several pseudo-instructions used during relaxation. */
10240 #define T16_32_TAB \
10241 X(_adc, 4140, eb400000), \
10242 X(_adcs, 4140, eb500000), \
10243 X(_add, 1c00, eb000000), \
10244 X(_adds, 1c00, eb100000), \
10245 X(_addi, 0000, f1000000), \
10246 X(_addis, 0000, f1100000), \
10247 X(_add_pc,000f, f20f0000), \
10248 X(_add_sp,000d, f10d0000), \
10249 X(_adr, 000f, f20f0000), \
10250 X(_and, 4000, ea000000), \
10251 X(_ands, 4000, ea100000), \
10252 X(_asr, 1000, fa40f000), \
10253 X(_asrs, 1000, fa50f000), \
10254 X(_b, e000, f000b000), \
10255 X(_bcond, d000, f0008000), \
10256 X(_bic, 4380, ea200000), \
10257 X(_bics, 4380, ea300000), \
10258 X(_cmn, 42c0, eb100f00), \
10259 X(_cmp, 2800, ebb00f00), \
10260 X(_cpsie, b660, f3af8400), \
10261 X(_cpsid, b670, f3af8600), \
10262 X(_cpy, 4600, ea4f0000), \
10263 X(_dec_sp,80dd, f1ad0d00), \
10264 X(_eor, 4040, ea800000), \
10265 X(_eors, 4040, ea900000), \
10266 X(_inc_sp,00dd, f10d0d00), \
10267 X(_ldmia, c800, e8900000), \
10268 X(_ldr, 6800, f8500000), \
10269 X(_ldrb, 7800, f8100000), \
10270 X(_ldrh, 8800, f8300000), \
10271 X(_ldrsb, 5600, f9100000), \
10272 X(_ldrsh, 5e00, f9300000), \
10273 X(_ldr_pc,4800, f85f0000), \
10274 X(_ldr_pc2,4800, f85f0000), \
10275 X(_ldr_sp,9800, f85d0000), \
10276 X(_lsl, 0000, fa00f000), \
10277 X(_lsls, 0000, fa10f000), \
10278 X(_lsr, 0800, fa20f000), \
10279 X(_lsrs, 0800, fa30f000), \
10280 X(_mov, 2000, ea4f0000), \
10281 X(_movs, 2000, ea5f0000), \
10282 X(_mul, 4340, fb00f000), \
10283 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10284 X(_mvn, 43c0, ea6f0000), \
10285 X(_mvns, 43c0, ea7f0000), \
10286 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10287 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10288 X(_orr, 4300, ea400000), \
10289 X(_orrs, 4300, ea500000), \
10290 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10291 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10292 X(_rev, ba00, fa90f080), \
10293 X(_rev16, ba40, fa90f090), \
10294 X(_revsh, bac0, fa90f0b0), \
10295 X(_ror, 41c0, fa60f000), \
10296 X(_rors, 41c0, fa70f000), \
10297 X(_sbc, 4180, eb600000), \
10298 X(_sbcs, 4180, eb700000), \
10299 X(_stmia, c000, e8800000), \
10300 X(_str, 6000, f8400000), \
10301 X(_strb, 7000, f8000000), \
10302 X(_strh, 8000, f8200000), \
10303 X(_str_sp,9000, f84d0000), \
10304 X(_sub, 1e00, eba00000), \
10305 X(_subs, 1e00, ebb00000), \
10306 X(_subi, 8000, f1a00000), \
10307 X(_subis, 8000, f1b00000), \
10308 X(_sxtb, b240, fa4ff080), \
10309 X(_sxth, b200, fa0ff080), \
10310 X(_tst, 4200, ea100f00), \
10311 X(_uxtb, b2c0, fa5ff080), \
10312 X(_uxth, b280, fa1ff080), \
10313 X(_nop, bf00, f3af8000), \
10314 X(_yield, bf10, f3af8001), \
10315 X(_wfe, bf20, f3af8002), \
10316 X(_wfi, bf30, f3af8003), \
10317 X(_sev, bf40, f3af8004), \
10318 X(_sevl, bf50, f3af8005), \
10319 X(_udf, de00, f7f0a000)
10321 /* To catch errors in encoding functions, the codes are all offset by
10322 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10323 as 16-bit instructions. */
10324 #define X(a,b,c) T_MNEM##a
10325 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10328 #define X(a,b,c) 0x##b
10329 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10330 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10333 #define X(a,b,c) 0x##c
10334 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10335 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10336 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10340 /* Thumb instruction encoders, in alphabetical order. */
10342 /* ADDW or SUBW. */
10345 do_t_add_sub_w (void)
10349 Rd
= inst
.operands
[0].reg
;
10350 Rn
= inst
.operands
[1].reg
;
10352 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10353 is the SP-{plus,minus}-immediate form of the instruction. */
10355 constraint (Rd
== REG_PC
, BAD_PC
);
10357 reject_bad_reg (Rd
);
10359 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10360 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10363 /* Parse an add or subtract instruction. We get here with inst.instruction
10364 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10367 do_t_add_sub (void)
10371 Rd
= inst
.operands
[0].reg
;
10372 Rs
= (inst
.operands
[1].present
10373 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10374 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10377 set_it_insn_type_last ();
10379 if (unified_syntax
)
10382 bfd_boolean narrow
;
10385 flags
= (inst
.instruction
== T_MNEM_adds
10386 || inst
.instruction
== T_MNEM_subs
);
10388 narrow
= !in_it_block ();
10390 narrow
= in_it_block ();
10391 if (!inst
.operands
[2].isreg
)
10395 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10397 add
= (inst
.instruction
== T_MNEM_add
10398 || inst
.instruction
== T_MNEM_adds
);
10400 if (inst
.size_req
!= 4)
10402 /* Attempt to use a narrow opcode, with relaxation if
10404 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10405 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10406 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10407 opcode
= T_MNEM_add_sp
;
10408 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10409 opcode
= T_MNEM_add_pc
;
10410 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10413 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10415 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10419 inst
.instruction
= THUMB_OP16(opcode
);
10420 inst
.instruction
|= (Rd
<< 4) | Rs
;
10421 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10422 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10423 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10424 if (inst
.size_req
!= 2)
10425 inst
.relax
= opcode
;
10428 constraint (inst
.size_req
== 2, BAD_HIREG
);
10430 if (inst
.size_req
== 4
10431 || (inst
.size_req
!= 2 && !opcode
))
10435 constraint (add
, BAD_PC
);
10436 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10437 _("only SUBS PC, LR, #const allowed"));
10438 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10439 _("expression too complex"));
10440 constraint (inst
.reloc
.exp
.X_add_number
< 0
10441 || inst
.reloc
.exp
.X_add_number
> 0xff,
10442 _("immediate value out of range"));
10443 inst
.instruction
= T2_SUBS_PC_LR
10444 | inst
.reloc
.exp
.X_add_number
;
10445 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10448 else if (Rs
== REG_PC
)
10450 /* Always use addw/subw. */
10451 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10452 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10456 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10457 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10460 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10462 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10464 inst
.instruction
|= Rd
<< 8;
10465 inst
.instruction
|= Rs
<< 16;
10470 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10471 unsigned int shift
= inst
.operands
[2].shift_kind
;
10473 Rn
= inst
.operands
[2].reg
;
10474 /* See if we can do this with a 16-bit instruction. */
10475 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10477 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10482 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10483 || inst
.instruction
== T_MNEM_add
)
10485 : T_OPCODE_SUB_R3
);
10486 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10490 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10492 /* Thumb-1 cores (except v6-M) require at least one high
10493 register in a narrow non flag setting add. */
10494 if (Rd
> 7 || Rn
> 7
10495 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10496 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10503 inst
.instruction
= T_OPCODE_ADD_HI
;
10504 inst
.instruction
|= (Rd
& 8) << 4;
10505 inst
.instruction
|= (Rd
& 7);
10506 inst
.instruction
|= Rn
<< 3;
10512 constraint (Rd
== REG_PC
, BAD_PC
);
10513 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10514 constraint (Rs
== REG_PC
, BAD_PC
);
10515 reject_bad_reg (Rn
);
10517 /* If we get here, it can't be done in 16 bits. */
10518 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10519 _("shift must be constant"));
10520 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10521 inst
.instruction
|= Rd
<< 8;
10522 inst
.instruction
|= Rs
<< 16;
10523 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10524 _("shift value over 3 not allowed in thumb mode"));
10525 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10526 _("only LSL shift allowed in thumb mode"));
10527 encode_thumb32_shifted_operand (2);
10532 constraint (inst
.instruction
== T_MNEM_adds
10533 || inst
.instruction
== T_MNEM_subs
,
10536 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10538 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10539 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10542 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10543 ? 0x0000 : 0x8000);
10544 inst
.instruction
|= (Rd
<< 4) | Rs
;
10545 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10549 Rn
= inst
.operands
[2].reg
;
10550 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10552 /* We now have Rd, Rs, and Rn set to registers. */
10553 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10555 /* Can't do this for SUB. */
10556 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10557 inst
.instruction
= T_OPCODE_ADD_HI
;
10558 inst
.instruction
|= (Rd
& 8) << 4;
10559 inst
.instruction
|= (Rd
& 7);
10561 inst
.instruction
|= Rn
<< 3;
10563 inst
.instruction
|= Rs
<< 3;
10565 constraint (1, _("dest must overlap one source register"));
10569 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10570 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10571 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10581 Rd
= inst
.operands
[0].reg
;
10582 reject_bad_reg (Rd
);
10584 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10586 /* Defer to section relaxation. */
10587 inst
.relax
= inst
.instruction
;
10588 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10589 inst
.instruction
|= Rd
<< 4;
10591 else if (unified_syntax
&& inst
.size_req
!= 2)
10593 /* Generate a 32-bit opcode. */
10594 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10595 inst
.instruction
|= Rd
<< 8;
10596 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10597 inst
.reloc
.pc_rel
= 1;
10601 /* Generate a 16-bit opcode. */
10602 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10603 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10604 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10605 inst
.reloc
.pc_rel
= 1;
10607 inst
.instruction
|= Rd
<< 4;
10611 /* Arithmetic instructions for which there is just one 16-bit
10612 instruction encoding, and it allows only two low registers.
10613 For maximal compatibility with ARM syntax, we allow three register
10614 operands even when Thumb-32 instructions are not available, as long
10615 as the first two are identical. For instance, both "sbc r0,r1" and
10616 "sbc r0,r0,r1" are allowed. */
10622 Rd
= inst
.operands
[0].reg
;
10623 Rs
= (inst
.operands
[1].present
10624 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10625 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10626 Rn
= inst
.operands
[2].reg
;
10628 reject_bad_reg (Rd
);
10629 reject_bad_reg (Rs
);
10630 if (inst
.operands
[2].isreg
)
10631 reject_bad_reg (Rn
);
10633 if (unified_syntax
)
10635 if (!inst
.operands
[2].isreg
)
10637 /* For an immediate, we always generate a 32-bit opcode;
10638 section relaxation will shrink it later if possible. */
10639 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10640 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10641 inst
.instruction
|= Rd
<< 8;
10642 inst
.instruction
|= Rs
<< 16;
10643 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10647 bfd_boolean narrow
;
10649 /* See if we can do this with a 16-bit instruction. */
10650 if (THUMB_SETS_FLAGS (inst
.instruction
))
10651 narrow
= !in_it_block ();
10653 narrow
= in_it_block ();
10655 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10657 if (inst
.operands
[2].shifted
)
10659 if (inst
.size_req
== 4)
10665 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10666 inst
.instruction
|= Rd
;
10667 inst
.instruction
|= Rn
<< 3;
10671 /* If we get here, it can't be done in 16 bits. */
10672 constraint (inst
.operands
[2].shifted
10673 && inst
.operands
[2].immisreg
,
10674 _("shift must be constant"));
10675 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10676 inst
.instruction
|= Rd
<< 8;
10677 inst
.instruction
|= Rs
<< 16;
10678 encode_thumb32_shifted_operand (2);
10683 /* On its face this is a lie - the instruction does set the
10684 flags. However, the only supported mnemonic in this mode
10685 says it doesn't. */
10686 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10688 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10689 _("unshifted register required"));
10690 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10691 constraint (Rd
!= Rs
,
10692 _("dest and source1 must be the same register"));
10694 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10695 inst
.instruction
|= Rd
;
10696 inst
.instruction
|= Rn
<< 3;
10700 /* Similarly, but for instructions where the arithmetic operation is
10701 commutative, so we can allow either of them to be different from
10702 the destination operand in a 16-bit instruction. For instance, all
10703 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10710 Rd
= inst
.operands
[0].reg
;
10711 Rs
= (inst
.operands
[1].present
10712 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10713 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10714 Rn
= inst
.operands
[2].reg
;
10716 reject_bad_reg (Rd
);
10717 reject_bad_reg (Rs
);
10718 if (inst
.operands
[2].isreg
)
10719 reject_bad_reg (Rn
);
10721 if (unified_syntax
)
10723 if (!inst
.operands
[2].isreg
)
10725 /* For an immediate, we always generate a 32-bit opcode;
10726 section relaxation will shrink it later if possible. */
10727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10728 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10729 inst
.instruction
|= Rd
<< 8;
10730 inst
.instruction
|= Rs
<< 16;
10731 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10735 bfd_boolean narrow
;
10737 /* See if we can do this with a 16-bit instruction. */
10738 if (THUMB_SETS_FLAGS (inst
.instruction
))
10739 narrow
= !in_it_block ();
10741 narrow
= in_it_block ();
10743 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10745 if (inst
.operands
[2].shifted
)
10747 if (inst
.size_req
== 4)
10754 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10755 inst
.instruction
|= Rd
;
10756 inst
.instruction
|= Rn
<< 3;
10761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10762 inst
.instruction
|= Rd
;
10763 inst
.instruction
|= Rs
<< 3;
10768 /* If we get here, it can't be done in 16 bits. */
10769 constraint (inst
.operands
[2].shifted
10770 && inst
.operands
[2].immisreg
,
10771 _("shift must be constant"));
10772 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10773 inst
.instruction
|= Rd
<< 8;
10774 inst
.instruction
|= Rs
<< 16;
10775 encode_thumb32_shifted_operand (2);
10780 /* On its face this is a lie - the instruction does set the
10781 flags. However, the only supported mnemonic in this mode
10782 says it doesn't. */
10783 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10785 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10786 _("unshifted register required"));
10787 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10789 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10790 inst
.instruction
|= Rd
;
10793 inst
.instruction
|= Rn
<< 3;
10795 inst
.instruction
|= Rs
<< 3;
10797 constraint (1, _("dest must overlap one source register"));
10805 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10806 constraint (msb
> 32, _("bit-field extends past end of register"));
10807 /* The instruction encoding stores the LSB and MSB,
10808 not the LSB and width. */
10809 Rd
= inst
.operands
[0].reg
;
10810 reject_bad_reg (Rd
);
10811 inst
.instruction
|= Rd
<< 8;
10812 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10813 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10814 inst
.instruction
|= msb
- 1;
10823 Rd
= inst
.operands
[0].reg
;
10824 reject_bad_reg (Rd
);
10826 /* #0 in second position is alternative syntax for bfc, which is
10827 the same instruction but with REG_PC in the Rm field. */
10828 if (!inst
.operands
[1].isreg
)
10832 Rn
= inst
.operands
[1].reg
;
10833 reject_bad_reg (Rn
);
10836 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10837 constraint (msb
> 32, _("bit-field extends past end of register"));
10838 /* The instruction encoding stores the LSB and MSB,
10839 not the LSB and width. */
10840 inst
.instruction
|= Rd
<< 8;
10841 inst
.instruction
|= Rn
<< 16;
10842 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10843 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10844 inst
.instruction
|= msb
- 1;
10852 Rd
= inst
.operands
[0].reg
;
10853 Rn
= inst
.operands
[1].reg
;
10855 reject_bad_reg (Rd
);
10856 reject_bad_reg (Rn
);
10858 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10859 _("bit-field extends past end of register"));
10860 inst
.instruction
|= Rd
<< 8;
10861 inst
.instruction
|= Rn
<< 16;
10862 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10863 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10864 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10867 /* ARM V5 Thumb BLX (argument parse)
10868 BLX <target_addr> which is BLX(1)
10869 BLX <Rm> which is BLX(2)
10870 Unfortunately, there are two different opcodes for this mnemonic.
10871 So, the insns[].value is not used, and the code here zaps values
10872 into inst.instruction.
10874 ??? How to take advantage of the additional two bits of displacement
10875 available in Thumb32 mode? Need new relocation? */
10880 set_it_insn_type_last ();
10882 if (inst
.operands
[0].isreg
)
10884 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10885 /* We have a register, so this is BLX(2). */
10886 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10890 /* No register. This must be BLX(1). */
10891 inst
.instruction
= 0xf000e800;
10892 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10904 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10906 if (in_it_block ())
10908 /* Conditional branches inside IT blocks are encoded as unconditional
10910 cond
= COND_ALWAYS
;
10915 if (cond
!= COND_ALWAYS
)
10916 opcode
= T_MNEM_bcond
;
10918 opcode
= inst
.instruction
;
10921 && (inst
.size_req
== 4
10922 || (inst
.size_req
!= 2
10923 && (inst
.operands
[0].hasreloc
10924 || inst
.reloc
.exp
.X_op
== O_constant
))))
10926 inst
.instruction
= THUMB_OP32(opcode
);
10927 if (cond
== COND_ALWAYS
)
10928 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10931 gas_assert (cond
!= 0xF);
10932 inst
.instruction
|= cond
<< 22;
10933 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10938 inst
.instruction
= THUMB_OP16(opcode
);
10939 if (cond
== COND_ALWAYS
)
10940 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10943 inst
.instruction
|= cond
<< 8;
10944 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10946 /* Allow section relaxation. */
10947 if (unified_syntax
&& inst
.size_req
!= 2)
10948 inst
.relax
= opcode
;
10950 inst
.reloc
.type
= reloc
;
10951 inst
.reloc
.pc_rel
= 1;
10954 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10955 between the two is the maximum immediate allowed - which is passed in
10958 do_t_bkpt_hlt1 (int range
)
10960 constraint (inst
.cond
!= COND_ALWAYS
,
10961 _("instruction is always unconditional"));
10962 if (inst
.operands
[0].present
)
10964 constraint (inst
.operands
[0].imm
> range
,
10965 _("immediate value out of range"));
10966 inst
.instruction
|= inst
.operands
[0].imm
;
10969 set_it_insn_type (NEUTRAL_IT_INSN
);
10975 do_t_bkpt_hlt1 (63);
10981 do_t_bkpt_hlt1 (255);
10985 do_t_branch23 (void)
10987 set_it_insn_type_last ();
10988 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10990 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10991 this file. We used to simply ignore the PLT reloc type here --
10992 the branch encoding is now needed to deal with TLSCALL relocs.
10993 So if we see a PLT reloc now, put it back to how it used to be to
10994 keep the preexisting behaviour. */
10995 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10996 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10998 #if defined(OBJ_COFF)
10999 /* If the destination of the branch is a defined symbol which does not have
11000 the THUMB_FUNC attribute, then we must be calling a function which has
11001 the (interfacearm) attribute. We look for the Thumb entry point to that
11002 function and change the branch to refer to that function instead. */
11003 if ( inst
.reloc
.exp
.X_op
== O_symbol
11004 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11005 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11006 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11007 inst
.reloc
.exp
.X_add_symbol
=
11008 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11015 set_it_insn_type_last ();
11016 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11017 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11018 should cause the alignment to be checked once it is known. This is
11019 because BX PC only works if the instruction is word aligned. */
11027 set_it_insn_type_last ();
11028 Rm
= inst
.operands
[0].reg
;
11029 reject_bad_reg (Rm
);
11030 inst
.instruction
|= Rm
<< 16;
11039 Rd
= inst
.operands
[0].reg
;
11040 Rm
= inst
.operands
[1].reg
;
11042 reject_bad_reg (Rd
);
11043 reject_bad_reg (Rm
);
11045 inst
.instruction
|= Rd
<< 8;
11046 inst
.instruction
|= Rm
<< 16;
11047 inst
.instruction
|= Rm
;
11053 set_it_insn_type (OUTSIDE_IT_INSN
);
11054 inst
.instruction
|= inst
.operands
[0].imm
;
11060 set_it_insn_type (OUTSIDE_IT_INSN
);
11062 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11063 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11065 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11066 inst
.instruction
= 0xf3af8000;
11067 inst
.instruction
|= imod
<< 9;
11068 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11069 if (inst
.operands
[1].present
)
11070 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11074 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11075 && (inst
.operands
[0].imm
& 4),
11076 _("selected processor does not support 'A' form "
11077 "of this instruction"));
11078 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11079 _("Thumb does not support the 2-argument "
11080 "form of this instruction"));
11081 inst
.instruction
|= inst
.operands
[0].imm
;
11085 /* THUMB CPY instruction (argument parse). */
11090 if (inst
.size_req
== 4)
11092 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11093 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11094 inst
.instruction
|= inst
.operands
[1].reg
;
11098 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11099 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11100 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11107 set_it_insn_type (OUTSIDE_IT_INSN
);
11108 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11109 inst
.instruction
|= inst
.operands
[0].reg
;
11110 inst
.reloc
.pc_rel
= 1;
11111 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11117 inst
.instruction
|= inst
.operands
[0].imm
;
11123 unsigned Rd
, Rn
, Rm
;
11125 Rd
= inst
.operands
[0].reg
;
11126 Rn
= (inst
.operands
[1].present
11127 ? inst
.operands
[1].reg
: Rd
);
11128 Rm
= inst
.operands
[2].reg
;
11130 reject_bad_reg (Rd
);
11131 reject_bad_reg (Rn
);
11132 reject_bad_reg (Rm
);
11134 inst
.instruction
|= Rd
<< 8;
11135 inst
.instruction
|= Rn
<< 16;
11136 inst
.instruction
|= Rm
;
11142 if (unified_syntax
&& inst
.size_req
== 4)
11143 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11145 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11151 unsigned int cond
= inst
.operands
[0].imm
;
11153 set_it_insn_type (IT_INSN
);
11154 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11156 now_it
.warn_deprecated
= FALSE
;
11158 /* If the condition is a negative condition, invert the mask. */
11159 if ((cond
& 0x1) == 0x0)
11161 unsigned int mask
= inst
.instruction
& 0x000f;
11163 if ((mask
& 0x7) == 0)
11165 /* No conversion needed. */
11166 now_it
.block_length
= 1;
11168 else if ((mask
& 0x3) == 0)
11171 now_it
.block_length
= 2;
11173 else if ((mask
& 0x1) == 0)
11176 now_it
.block_length
= 3;
11181 now_it
.block_length
= 4;
11184 inst
.instruction
&= 0xfff0;
11185 inst
.instruction
|= mask
;
11188 inst
.instruction
|= cond
<< 4;
11191 /* Helper function used for both push/pop and ldm/stm. */
11193 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11197 load
= (inst
.instruction
& (1 << 20)) != 0;
11199 if (mask
& (1 << 13))
11200 inst
.error
= _("SP not allowed in register list");
11202 if ((mask
& (1 << base
)) != 0
11204 inst
.error
= _("having the base register in the register list when "
11205 "using write back is UNPREDICTABLE");
11209 if (mask
& (1 << 15))
11211 if (mask
& (1 << 14))
11212 inst
.error
= _("LR and PC should not both be in register list");
11214 set_it_insn_type_last ();
11219 if (mask
& (1 << 15))
11220 inst
.error
= _("PC not allowed in register list");
11223 if ((mask
& (mask
- 1)) == 0)
11225 /* Single register transfers implemented as str/ldr. */
11228 if (inst
.instruction
& (1 << 23))
11229 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11231 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11235 if (inst
.instruction
& (1 << 23))
11236 inst
.instruction
= 0x00800000; /* ia -> [base] */
11238 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11241 inst
.instruction
|= 0xf8400000;
11243 inst
.instruction
|= 0x00100000;
11245 mask
= ffs (mask
) - 1;
11248 else if (writeback
)
11249 inst
.instruction
|= WRITE_BACK
;
11251 inst
.instruction
|= mask
;
11252 inst
.instruction
|= base
<< 16;
11258 /* This really doesn't seem worth it. */
11259 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11260 _("expression too complex"));
11261 constraint (inst
.operands
[1].writeback
,
11262 _("Thumb load/store multiple does not support {reglist}^"));
11264 if (unified_syntax
)
11266 bfd_boolean narrow
;
11270 /* See if we can use a 16-bit instruction. */
11271 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11272 && inst
.size_req
!= 4
11273 && !(inst
.operands
[1].imm
& ~0xff))
11275 mask
= 1 << inst
.operands
[0].reg
;
11277 if (inst
.operands
[0].reg
<= 7)
11279 if (inst
.instruction
== T_MNEM_stmia
11280 ? inst
.operands
[0].writeback
11281 : (inst
.operands
[0].writeback
11282 == !(inst
.operands
[1].imm
& mask
)))
11284 if (inst
.instruction
== T_MNEM_stmia
11285 && (inst
.operands
[1].imm
& mask
)
11286 && (inst
.operands
[1].imm
& (mask
- 1)))
11287 as_warn (_("value stored for r%d is UNKNOWN"),
11288 inst
.operands
[0].reg
);
11290 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11291 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11292 inst
.instruction
|= inst
.operands
[1].imm
;
11295 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11297 /* This means 1 register in reg list one of 3 situations:
11298 1. Instruction is stmia, but without writeback.
11299 2. lmdia without writeback, but with Rn not in
11301 3. ldmia with writeback, but with Rn in reglist.
11302 Case 3 is UNPREDICTABLE behaviour, so we handle
11303 case 1 and 2 which can be converted into a 16-bit
11304 str or ldr. The SP cases are handled below. */
11305 unsigned long opcode
;
11306 /* First, record an error for Case 3. */
11307 if (inst
.operands
[1].imm
& mask
11308 && inst
.operands
[0].writeback
)
11310 _("having the base register in the register list when "
11311 "using write back is UNPREDICTABLE");
11313 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11315 inst
.instruction
= THUMB_OP16 (opcode
);
11316 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11317 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11321 else if (inst
.operands
[0] .reg
== REG_SP
)
11323 if (inst
.operands
[0].writeback
)
11326 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11327 ? T_MNEM_push
: T_MNEM_pop
);
11328 inst
.instruction
|= inst
.operands
[1].imm
;
11331 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11334 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11335 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11336 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11344 if (inst
.instruction
< 0xffff)
11345 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11347 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11348 inst
.operands
[0].writeback
);
11353 constraint (inst
.operands
[0].reg
> 7
11354 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11355 constraint (inst
.instruction
!= T_MNEM_ldmia
11356 && inst
.instruction
!= T_MNEM_stmia
,
11357 _("Thumb-2 instruction only valid in unified syntax"));
11358 if (inst
.instruction
== T_MNEM_stmia
)
11360 if (!inst
.operands
[0].writeback
)
11361 as_warn (_("this instruction will write back the base register"));
11362 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11363 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11364 as_warn (_("value stored for r%d is UNKNOWN"),
11365 inst
.operands
[0].reg
);
11369 if (!inst
.operands
[0].writeback
11370 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11371 as_warn (_("this instruction will write back the base register"));
11372 else if (inst
.operands
[0].writeback
11373 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11374 as_warn (_("this instruction will not write back the base register"));
11377 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11378 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11379 inst
.instruction
|= inst
.operands
[1].imm
;
11386 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11387 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11388 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11389 || inst
.operands
[1].negative
,
11392 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11395 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11396 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11402 if (!inst
.operands
[1].present
)
11404 constraint (inst
.operands
[0].reg
== REG_LR
,
11405 _("r14 not allowed as first register "
11406 "when second register is omitted"));
11407 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11409 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11412 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11413 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11414 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11420 unsigned long opcode
;
11423 if (inst
.operands
[0].isreg
11424 && !inst
.operands
[0].preind
11425 && inst
.operands
[0].reg
== REG_PC
)
11426 set_it_insn_type_last ();
11428 opcode
= inst
.instruction
;
11429 if (unified_syntax
)
11431 if (!inst
.operands
[1].isreg
)
11433 if (opcode
<= 0xffff)
11434 inst
.instruction
= THUMB_OP32 (opcode
);
11435 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11438 if (inst
.operands
[1].isreg
11439 && !inst
.operands
[1].writeback
11440 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11441 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11442 && opcode
<= 0xffff
11443 && inst
.size_req
!= 4)
11445 /* Insn may have a 16-bit form. */
11446 Rn
= inst
.operands
[1].reg
;
11447 if (inst
.operands
[1].immisreg
)
11449 inst
.instruction
= THUMB_OP16 (opcode
);
11451 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11453 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11454 reject_bad_reg (inst
.operands
[1].imm
);
11456 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11457 && opcode
!= T_MNEM_ldrsb
)
11458 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11459 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11466 if (inst
.reloc
.pc_rel
)
11467 opcode
= T_MNEM_ldr_pc2
;
11469 opcode
= T_MNEM_ldr_pc
;
11473 if (opcode
== T_MNEM_ldr
)
11474 opcode
= T_MNEM_ldr_sp
;
11476 opcode
= T_MNEM_str_sp
;
11478 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11482 inst
.instruction
= inst
.operands
[0].reg
;
11483 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11485 inst
.instruction
|= THUMB_OP16 (opcode
);
11486 if (inst
.size_req
== 2)
11487 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11489 inst
.relax
= opcode
;
11493 /* Definitely a 32-bit variant. */
11495 /* Warning for Erratum 752419. */
11496 if (opcode
== T_MNEM_ldr
11497 && inst
.operands
[0].reg
== REG_SP
11498 && inst
.operands
[1].writeback
== 1
11499 && !inst
.operands
[1].immisreg
)
11501 if (no_cpu_selected ()
11502 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11503 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11504 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11505 as_warn (_("This instruction may be unpredictable "
11506 "if executed on M-profile cores "
11507 "with interrupts enabled."));
11510 /* Do some validations regarding addressing modes. */
11511 if (inst
.operands
[1].immisreg
)
11512 reject_bad_reg (inst
.operands
[1].imm
);
11514 constraint (inst
.operands
[1].writeback
== 1
11515 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11518 inst
.instruction
= THUMB_OP32 (opcode
);
11519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11520 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11521 check_ldr_r15_aligned ();
11525 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11527 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11529 /* Only [Rn,Rm] is acceptable. */
11530 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11531 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11532 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11533 || inst
.operands
[1].negative
,
11534 _("Thumb does not support this addressing mode"));
11535 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11540 if (!inst
.operands
[1].isreg
)
11541 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11544 constraint (!inst
.operands
[1].preind
11545 || inst
.operands
[1].shifted
11546 || inst
.operands
[1].writeback
,
11547 _("Thumb does not support this addressing mode"));
11548 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11550 constraint (inst
.instruction
& 0x0600,
11551 _("byte or halfword not valid for base register"));
11552 constraint (inst
.operands
[1].reg
== REG_PC
11553 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11554 _("r15 based store not allowed"));
11555 constraint (inst
.operands
[1].immisreg
,
11556 _("invalid base register for register offset"));
11558 if (inst
.operands
[1].reg
== REG_PC
)
11559 inst
.instruction
= T_OPCODE_LDR_PC
;
11560 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11561 inst
.instruction
= T_OPCODE_LDR_SP
;
11563 inst
.instruction
= T_OPCODE_STR_SP
;
11565 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11566 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11570 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11571 if (!inst
.operands
[1].immisreg
)
11573 /* Immediate offset. */
11574 inst
.instruction
|= inst
.operands
[0].reg
;
11575 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11576 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11580 /* Register offset. */
11581 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11582 constraint (inst
.operands
[1].negative
,
11583 _("Thumb does not support this addressing mode"));
11586 switch (inst
.instruction
)
11588 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11589 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11590 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11591 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11592 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11593 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11594 case 0x5600 /* ldrsb */:
11595 case 0x5e00 /* ldrsh */: break;
11599 inst
.instruction
|= inst
.operands
[0].reg
;
11600 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11601 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11607 if (!inst
.operands
[1].present
)
11609 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11610 constraint (inst
.operands
[0].reg
== REG_LR
,
11611 _("r14 not allowed here"));
11612 constraint (inst
.operands
[0].reg
== REG_R12
,
11613 _("r12 not allowed here"));
11616 if (inst
.operands
[2].writeback
11617 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11618 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11619 as_warn (_("base register written back, and overlaps "
11620 "one of transfer registers"));
11622 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11623 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11624 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11631 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11637 unsigned Rd
, Rn
, Rm
, Ra
;
11639 Rd
= inst
.operands
[0].reg
;
11640 Rn
= inst
.operands
[1].reg
;
11641 Rm
= inst
.operands
[2].reg
;
11642 Ra
= inst
.operands
[3].reg
;
11644 reject_bad_reg (Rd
);
11645 reject_bad_reg (Rn
);
11646 reject_bad_reg (Rm
);
11647 reject_bad_reg (Ra
);
11649 inst
.instruction
|= Rd
<< 8;
11650 inst
.instruction
|= Rn
<< 16;
11651 inst
.instruction
|= Rm
;
11652 inst
.instruction
|= Ra
<< 12;
11658 unsigned RdLo
, RdHi
, Rn
, Rm
;
11660 RdLo
= inst
.operands
[0].reg
;
11661 RdHi
= inst
.operands
[1].reg
;
11662 Rn
= inst
.operands
[2].reg
;
11663 Rm
= inst
.operands
[3].reg
;
11665 reject_bad_reg (RdLo
);
11666 reject_bad_reg (RdHi
);
11667 reject_bad_reg (Rn
);
11668 reject_bad_reg (Rm
);
11670 inst
.instruction
|= RdLo
<< 12;
11671 inst
.instruction
|= RdHi
<< 8;
11672 inst
.instruction
|= Rn
<< 16;
11673 inst
.instruction
|= Rm
;
11677 do_t_mov_cmp (void)
11681 Rn
= inst
.operands
[0].reg
;
11682 Rm
= inst
.operands
[1].reg
;
11685 set_it_insn_type_last ();
11687 if (unified_syntax
)
11689 int r0off
= (inst
.instruction
== T_MNEM_mov
11690 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11691 unsigned long opcode
;
11692 bfd_boolean narrow
;
11693 bfd_boolean low_regs
;
11695 low_regs
= (Rn
<= 7 && Rm
<= 7);
11696 opcode
= inst
.instruction
;
11697 if (in_it_block ())
11698 narrow
= opcode
!= T_MNEM_movs
;
11700 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11701 if (inst
.size_req
== 4
11702 || inst
.operands
[1].shifted
)
11705 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11706 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11707 && !inst
.operands
[1].shifted
11711 inst
.instruction
= T2_SUBS_PC_LR
;
11715 if (opcode
== T_MNEM_cmp
)
11717 constraint (Rn
== REG_PC
, BAD_PC
);
11720 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11722 warn_deprecated_sp (Rm
);
11723 /* R15 was documented as a valid choice for Rm in ARMv6,
11724 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11725 tools reject R15, so we do too. */
11726 constraint (Rm
== REG_PC
, BAD_PC
);
11729 reject_bad_reg (Rm
);
11731 else if (opcode
== T_MNEM_mov
11732 || opcode
== T_MNEM_movs
)
11734 if (inst
.operands
[1].isreg
)
11736 if (opcode
== T_MNEM_movs
)
11738 reject_bad_reg (Rn
);
11739 reject_bad_reg (Rm
);
11743 /* This is mov.n. */
11744 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11745 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11747 as_tsktsk (_("Use of r%u as a source register is "
11748 "deprecated when r%u is the destination "
11749 "register."), Rm
, Rn
);
11754 /* This is mov.w. */
11755 constraint (Rn
== REG_PC
, BAD_PC
);
11756 constraint (Rm
== REG_PC
, BAD_PC
);
11757 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11761 reject_bad_reg (Rn
);
11764 if (!inst
.operands
[1].isreg
)
11766 /* Immediate operand. */
11767 if (!in_it_block () && opcode
== T_MNEM_mov
)
11769 if (low_regs
&& narrow
)
11771 inst
.instruction
= THUMB_OP16 (opcode
);
11772 inst
.instruction
|= Rn
<< 8;
11773 if (inst
.size_req
== 2)
11775 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11776 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11777 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11780 inst
.relax
= opcode
;
11784 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11785 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11786 inst
.instruction
|= Rn
<< r0off
;
11787 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11790 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11791 && (inst
.instruction
== T_MNEM_mov
11792 || inst
.instruction
== T_MNEM_movs
))
11794 /* Register shifts are encoded as separate shift instructions. */
11795 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11797 if (in_it_block ())
11802 if (inst
.size_req
== 4)
11805 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11811 switch (inst
.operands
[1].shift_kind
)
11814 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11817 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11820 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11823 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11829 inst
.instruction
= opcode
;
11832 inst
.instruction
|= Rn
;
11833 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11838 inst
.instruction
|= CONDS_BIT
;
11840 inst
.instruction
|= Rn
<< 8;
11841 inst
.instruction
|= Rm
<< 16;
11842 inst
.instruction
|= inst
.operands
[1].imm
;
11847 /* Some mov with immediate shift have narrow variants.
11848 Register shifts are handled above. */
11849 if (low_regs
&& inst
.operands
[1].shifted
11850 && (inst
.instruction
== T_MNEM_mov
11851 || inst
.instruction
== T_MNEM_movs
))
11853 if (in_it_block ())
11854 narrow
= (inst
.instruction
== T_MNEM_mov
);
11856 narrow
= (inst
.instruction
== T_MNEM_movs
);
11861 switch (inst
.operands
[1].shift_kind
)
11863 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11864 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11865 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11866 default: narrow
= FALSE
; break;
11872 inst
.instruction
|= Rn
;
11873 inst
.instruction
|= Rm
<< 3;
11874 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11878 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11879 inst
.instruction
|= Rn
<< r0off
;
11880 encode_thumb32_shifted_operand (1);
11884 switch (inst
.instruction
)
11887 /* In v4t or v5t a move of two lowregs produces unpredictable
11888 results. Don't allow this. */
11891 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11892 "MOV Rd, Rs with two low registers is not "
11893 "permitted on this architecture");
11894 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11898 inst
.instruction
= T_OPCODE_MOV_HR
;
11899 inst
.instruction
|= (Rn
& 0x8) << 4;
11900 inst
.instruction
|= (Rn
& 0x7);
11901 inst
.instruction
|= Rm
<< 3;
11905 /* We know we have low registers at this point.
11906 Generate LSLS Rd, Rs, #0. */
11907 inst
.instruction
= T_OPCODE_LSL_I
;
11908 inst
.instruction
|= Rn
;
11909 inst
.instruction
|= Rm
<< 3;
11915 inst
.instruction
= T_OPCODE_CMP_LR
;
11916 inst
.instruction
|= Rn
;
11917 inst
.instruction
|= Rm
<< 3;
11921 inst
.instruction
= T_OPCODE_CMP_HR
;
11922 inst
.instruction
|= (Rn
& 0x8) << 4;
11923 inst
.instruction
|= (Rn
& 0x7);
11924 inst
.instruction
|= Rm
<< 3;
11931 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11933 /* PR 10443: Do not silently ignore shifted operands. */
11934 constraint (inst
.operands
[1].shifted
,
11935 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11937 if (inst
.operands
[1].isreg
)
11939 if (Rn
< 8 && Rm
< 8)
11941 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11942 since a MOV instruction produces unpredictable results. */
11943 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11944 inst
.instruction
= T_OPCODE_ADD_I3
;
11946 inst
.instruction
= T_OPCODE_CMP_LR
;
11948 inst
.instruction
|= Rn
;
11949 inst
.instruction
|= Rm
<< 3;
11953 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11954 inst
.instruction
= T_OPCODE_MOV_HR
;
11956 inst
.instruction
= T_OPCODE_CMP_HR
;
11962 constraint (Rn
> 7,
11963 _("only lo regs allowed with immediate"));
11964 inst
.instruction
|= Rn
<< 8;
11965 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11976 top
= (inst
.instruction
& 0x00800000) != 0;
11977 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11979 constraint (top
, _(":lower16: not allowed this instruction"));
11980 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11982 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11984 constraint (!top
, _(":upper16: not allowed this instruction"));
11985 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11988 Rd
= inst
.operands
[0].reg
;
11989 reject_bad_reg (Rd
);
11991 inst
.instruction
|= Rd
<< 8;
11992 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11994 imm
= inst
.reloc
.exp
.X_add_number
;
11995 inst
.instruction
|= (imm
& 0xf000) << 4;
11996 inst
.instruction
|= (imm
& 0x0800) << 15;
11997 inst
.instruction
|= (imm
& 0x0700) << 4;
11998 inst
.instruction
|= (imm
& 0x00ff);
12003 do_t_mvn_tst (void)
12007 Rn
= inst
.operands
[0].reg
;
12008 Rm
= inst
.operands
[1].reg
;
12010 if (inst
.instruction
== T_MNEM_cmp
12011 || inst
.instruction
== T_MNEM_cmn
)
12012 constraint (Rn
== REG_PC
, BAD_PC
);
12014 reject_bad_reg (Rn
);
12015 reject_bad_reg (Rm
);
12017 if (unified_syntax
)
12019 int r0off
= (inst
.instruction
== T_MNEM_mvn
12020 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12021 bfd_boolean narrow
;
12023 if (inst
.size_req
== 4
12024 || inst
.instruction
> 0xffff
12025 || inst
.operands
[1].shifted
12026 || Rn
> 7 || Rm
> 7)
12028 else if (inst
.instruction
== T_MNEM_cmn
12029 || inst
.instruction
== T_MNEM_tst
)
12031 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12032 narrow
= !in_it_block ();
12034 narrow
= in_it_block ();
12036 if (!inst
.operands
[1].isreg
)
12038 /* For an immediate, we always generate a 32-bit opcode;
12039 section relaxation will shrink it later if possible. */
12040 if (inst
.instruction
< 0xffff)
12041 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12042 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12043 inst
.instruction
|= Rn
<< r0off
;
12044 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12048 /* See if we can do this with a 16-bit instruction. */
12051 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12052 inst
.instruction
|= Rn
;
12053 inst
.instruction
|= Rm
<< 3;
12057 constraint (inst
.operands
[1].shifted
12058 && inst
.operands
[1].immisreg
,
12059 _("shift must be constant"));
12060 if (inst
.instruction
< 0xffff)
12061 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12062 inst
.instruction
|= Rn
<< r0off
;
12063 encode_thumb32_shifted_operand (1);
12069 constraint (inst
.instruction
> 0xffff
12070 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12071 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12072 _("unshifted register required"));
12073 constraint (Rn
> 7 || Rm
> 7,
12076 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12077 inst
.instruction
|= Rn
;
12078 inst
.instruction
|= Rm
<< 3;
12087 if (do_vfp_nsyn_mrs () == SUCCESS
)
12090 Rd
= inst
.operands
[0].reg
;
12091 reject_bad_reg (Rd
);
12092 inst
.instruction
|= Rd
<< 8;
12094 if (inst
.operands
[1].isreg
)
12096 unsigned br
= inst
.operands
[1].reg
;
12097 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12098 as_bad (_("bad register for mrs"));
12100 inst
.instruction
|= br
& (0xf << 16);
12101 inst
.instruction
|= (br
& 0x300) >> 4;
12102 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12106 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12108 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12110 /* PR gas/12698: The constraint is only applied for m_profile.
12111 If the user has specified -march=all, we want to ignore it as
12112 we are building for any CPU type, including non-m variants. */
12113 bfd_boolean m_profile
=
12114 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12115 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12116 "not support requested special purpose register"));
12119 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12121 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12122 _("'APSR', 'CPSR' or 'SPSR' expected"));
12124 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12125 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12126 inst
.instruction
|= 0xf0000;
12136 if (do_vfp_nsyn_msr () == SUCCESS
)
12139 constraint (!inst
.operands
[1].isreg
,
12140 _("Thumb encoding does not support an immediate here"));
12142 if (inst
.operands
[0].isreg
)
12143 flags
= (int)(inst
.operands
[0].reg
);
12145 flags
= inst
.operands
[0].imm
;
12147 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12149 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12151 /* PR gas/12698: The constraint is only applied for m_profile.
12152 If the user has specified -march=all, we want to ignore it as
12153 we are building for any CPU type, including non-m variants. */
12154 bfd_boolean m_profile
=
12155 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12156 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12157 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12158 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12159 && bits
!= PSR_f
)) && m_profile
,
12160 _("selected processor does not support requested special "
12161 "purpose register"));
12164 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12165 "requested special purpose register"));
12167 Rn
= inst
.operands
[1].reg
;
12168 reject_bad_reg (Rn
);
12170 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12171 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12172 inst
.instruction
|= (flags
& 0x300) >> 4;
12173 inst
.instruction
|= (flags
& 0xff);
12174 inst
.instruction
|= Rn
<< 16;
12180 bfd_boolean narrow
;
12181 unsigned Rd
, Rn
, Rm
;
12183 if (!inst
.operands
[2].present
)
12184 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12186 Rd
= inst
.operands
[0].reg
;
12187 Rn
= inst
.operands
[1].reg
;
12188 Rm
= inst
.operands
[2].reg
;
12190 if (unified_syntax
)
12192 if (inst
.size_req
== 4
12198 else if (inst
.instruction
== T_MNEM_muls
)
12199 narrow
= !in_it_block ();
12201 narrow
= in_it_block ();
12205 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12206 constraint (Rn
> 7 || Rm
> 7,
12213 /* 16-bit MULS/Conditional MUL. */
12214 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12215 inst
.instruction
|= Rd
;
12218 inst
.instruction
|= Rm
<< 3;
12220 inst
.instruction
|= Rn
<< 3;
12222 constraint (1, _("dest must overlap one source register"));
12226 constraint (inst
.instruction
!= T_MNEM_mul
,
12227 _("Thumb-2 MUL must not set flags"));
12229 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12230 inst
.instruction
|= Rd
<< 8;
12231 inst
.instruction
|= Rn
<< 16;
12232 inst
.instruction
|= Rm
<< 0;
12234 reject_bad_reg (Rd
);
12235 reject_bad_reg (Rn
);
12236 reject_bad_reg (Rm
);
12243 unsigned RdLo
, RdHi
, Rn
, Rm
;
12245 RdLo
= inst
.operands
[0].reg
;
12246 RdHi
= inst
.operands
[1].reg
;
12247 Rn
= inst
.operands
[2].reg
;
12248 Rm
= inst
.operands
[3].reg
;
12250 reject_bad_reg (RdLo
);
12251 reject_bad_reg (RdHi
);
12252 reject_bad_reg (Rn
);
12253 reject_bad_reg (Rm
);
12255 inst
.instruction
|= RdLo
<< 12;
12256 inst
.instruction
|= RdHi
<< 8;
12257 inst
.instruction
|= Rn
<< 16;
12258 inst
.instruction
|= Rm
;
12261 as_tsktsk (_("rdhi and rdlo must be different"));
12267 set_it_insn_type (NEUTRAL_IT_INSN
);
12269 if (unified_syntax
)
12271 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12273 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12274 inst
.instruction
|= inst
.operands
[0].imm
;
12278 /* PR9722: Check for Thumb2 availability before
12279 generating a thumb2 nop instruction. */
12280 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12282 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12283 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12286 inst
.instruction
= 0x46c0;
12291 constraint (inst
.operands
[0].present
,
12292 _("Thumb does not support NOP with hints"));
12293 inst
.instruction
= 0x46c0;
12300 if (unified_syntax
)
12302 bfd_boolean narrow
;
12304 if (THUMB_SETS_FLAGS (inst
.instruction
))
12305 narrow
= !in_it_block ();
12307 narrow
= in_it_block ();
12308 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12310 if (inst
.size_req
== 4)
12315 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12316 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12317 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12321 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12322 inst
.instruction
|= inst
.operands
[0].reg
;
12323 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12328 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12330 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12332 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12333 inst
.instruction
|= inst
.operands
[0].reg
;
12334 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12343 Rd
= inst
.operands
[0].reg
;
12344 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12346 reject_bad_reg (Rd
);
12347 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12348 reject_bad_reg (Rn
);
12350 inst
.instruction
|= Rd
<< 8;
12351 inst
.instruction
|= Rn
<< 16;
12353 if (!inst
.operands
[2].isreg
)
12355 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12356 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12362 Rm
= inst
.operands
[2].reg
;
12363 reject_bad_reg (Rm
);
12365 constraint (inst
.operands
[2].shifted
12366 && inst
.operands
[2].immisreg
,
12367 _("shift must be constant"));
12368 encode_thumb32_shifted_operand (2);
12375 unsigned Rd
, Rn
, Rm
;
12377 Rd
= inst
.operands
[0].reg
;
12378 Rn
= inst
.operands
[1].reg
;
12379 Rm
= inst
.operands
[2].reg
;
12381 reject_bad_reg (Rd
);
12382 reject_bad_reg (Rn
);
12383 reject_bad_reg (Rm
);
12385 inst
.instruction
|= Rd
<< 8;
12386 inst
.instruction
|= Rn
<< 16;
12387 inst
.instruction
|= Rm
;
12388 if (inst
.operands
[3].present
)
12390 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12391 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12392 _("expression too complex"));
12393 inst
.instruction
|= (val
& 0x1c) << 10;
12394 inst
.instruction
|= (val
& 0x03) << 6;
12401 if (!inst
.operands
[3].present
)
12405 inst
.instruction
&= ~0x00000020;
12407 /* PR 10168. Swap the Rm and Rn registers. */
12408 Rtmp
= inst
.operands
[1].reg
;
12409 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12410 inst
.operands
[2].reg
= Rtmp
;
12418 if (inst
.operands
[0].immisreg
)
12419 reject_bad_reg (inst
.operands
[0].imm
);
12421 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12425 do_t_push_pop (void)
12429 constraint (inst
.operands
[0].writeback
,
12430 _("push/pop do not support {reglist}^"));
12431 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12432 _("expression too complex"));
12434 mask
= inst
.operands
[0].imm
;
12435 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12436 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12437 else if (inst
.size_req
!= 4
12438 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12439 ? REG_LR
: REG_PC
)))
12441 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12442 inst
.instruction
|= THUMB_PP_PC_LR
;
12443 inst
.instruction
|= mask
& 0xff;
12445 else if (unified_syntax
)
12447 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12448 encode_thumb2_ldmstm (13, mask
, TRUE
);
12452 inst
.error
= _("invalid register list to push/pop instruction");
12462 Rd
= inst
.operands
[0].reg
;
12463 Rm
= inst
.operands
[1].reg
;
12465 reject_bad_reg (Rd
);
12466 reject_bad_reg (Rm
);
12468 inst
.instruction
|= Rd
<< 8;
12469 inst
.instruction
|= Rm
<< 16;
12470 inst
.instruction
|= Rm
;
12478 Rd
= inst
.operands
[0].reg
;
12479 Rm
= inst
.operands
[1].reg
;
12481 reject_bad_reg (Rd
);
12482 reject_bad_reg (Rm
);
12484 if (Rd
<= 7 && Rm
<= 7
12485 && inst
.size_req
!= 4)
12487 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12488 inst
.instruction
|= Rd
;
12489 inst
.instruction
|= Rm
<< 3;
12491 else if (unified_syntax
)
12493 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12494 inst
.instruction
|= Rd
<< 8;
12495 inst
.instruction
|= Rm
<< 16;
12496 inst
.instruction
|= Rm
;
12499 inst
.error
= BAD_HIREG
;
12507 Rd
= inst
.operands
[0].reg
;
12508 Rm
= inst
.operands
[1].reg
;
12510 reject_bad_reg (Rd
);
12511 reject_bad_reg (Rm
);
12513 inst
.instruction
|= Rd
<< 8;
12514 inst
.instruction
|= Rm
;
12522 Rd
= inst
.operands
[0].reg
;
12523 Rs
= (inst
.operands
[1].present
12524 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12525 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12527 reject_bad_reg (Rd
);
12528 reject_bad_reg (Rs
);
12529 if (inst
.operands
[2].isreg
)
12530 reject_bad_reg (inst
.operands
[2].reg
);
12532 inst
.instruction
|= Rd
<< 8;
12533 inst
.instruction
|= Rs
<< 16;
12534 if (!inst
.operands
[2].isreg
)
12536 bfd_boolean narrow
;
12538 if ((inst
.instruction
& 0x00100000) != 0)
12539 narrow
= !in_it_block ();
12541 narrow
= in_it_block ();
12543 if (Rd
> 7 || Rs
> 7)
12546 if (inst
.size_req
== 4 || !unified_syntax
)
12549 if (inst
.reloc
.exp
.X_op
!= O_constant
12550 || inst
.reloc
.exp
.X_add_number
!= 0)
12553 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12554 relaxation, but it doesn't seem worth the hassle. */
12557 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12558 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12559 inst
.instruction
|= Rs
<< 3;
12560 inst
.instruction
|= Rd
;
12564 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12565 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12569 encode_thumb32_shifted_operand (2);
12575 if (warn_on_deprecated
12576 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12577 as_tsktsk (_("setend use is deprecated for ARMv8"));
12579 set_it_insn_type (OUTSIDE_IT_INSN
);
12580 if (inst
.operands
[0].imm
)
12581 inst
.instruction
|= 0x8;
12587 if (!inst
.operands
[1].present
)
12588 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12590 if (unified_syntax
)
12592 bfd_boolean narrow
;
12595 switch (inst
.instruction
)
12598 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12600 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12602 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12604 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12608 if (THUMB_SETS_FLAGS (inst
.instruction
))
12609 narrow
= !in_it_block ();
12611 narrow
= in_it_block ();
12612 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12614 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12616 if (inst
.operands
[2].isreg
12617 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12618 || inst
.operands
[2].reg
> 7))
12620 if (inst
.size_req
== 4)
12623 reject_bad_reg (inst
.operands
[0].reg
);
12624 reject_bad_reg (inst
.operands
[1].reg
);
12628 if (inst
.operands
[2].isreg
)
12630 reject_bad_reg (inst
.operands
[2].reg
);
12631 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12632 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12633 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12634 inst
.instruction
|= inst
.operands
[2].reg
;
12636 /* PR 12854: Error on extraneous shifts. */
12637 constraint (inst
.operands
[2].shifted
,
12638 _("extraneous shift as part of operand to shift insn"));
12642 inst
.operands
[1].shifted
= 1;
12643 inst
.operands
[1].shift_kind
= shift_kind
;
12644 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12645 ? T_MNEM_movs
: T_MNEM_mov
);
12646 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12647 encode_thumb32_shifted_operand (1);
12648 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12649 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12654 if (inst
.operands
[2].isreg
)
12656 switch (shift_kind
)
12658 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12659 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12660 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12661 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12665 inst
.instruction
|= inst
.operands
[0].reg
;
12666 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12668 /* PR 12854: Error on extraneous shifts. */
12669 constraint (inst
.operands
[2].shifted
,
12670 _("extraneous shift as part of operand to shift insn"));
12674 switch (shift_kind
)
12676 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12677 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12678 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12681 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12682 inst
.instruction
|= inst
.operands
[0].reg
;
12683 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12689 constraint (inst
.operands
[0].reg
> 7
12690 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12691 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12693 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12695 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12696 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12697 _("source1 and dest must be same register"));
12699 switch (inst
.instruction
)
12701 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12702 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12703 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12704 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12708 inst
.instruction
|= inst
.operands
[0].reg
;
12709 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12711 /* PR 12854: Error on extraneous shifts. */
12712 constraint (inst
.operands
[2].shifted
,
12713 _("extraneous shift as part of operand to shift insn"));
12717 switch (inst
.instruction
)
12719 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12720 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12721 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12722 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12725 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12726 inst
.instruction
|= inst
.operands
[0].reg
;
12727 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12735 unsigned Rd
, Rn
, Rm
;
12737 Rd
= inst
.operands
[0].reg
;
12738 Rn
= inst
.operands
[1].reg
;
12739 Rm
= inst
.operands
[2].reg
;
12741 reject_bad_reg (Rd
);
12742 reject_bad_reg (Rn
);
12743 reject_bad_reg (Rm
);
12745 inst
.instruction
|= Rd
<< 8;
12746 inst
.instruction
|= Rn
<< 16;
12747 inst
.instruction
|= Rm
;
12753 unsigned Rd
, Rn
, Rm
;
12755 Rd
= inst
.operands
[0].reg
;
12756 Rm
= inst
.operands
[1].reg
;
12757 Rn
= inst
.operands
[2].reg
;
12759 reject_bad_reg (Rd
);
12760 reject_bad_reg (Rn
);
12761 reject_bad_reg (Rm
);
12763 inst
.instruction
|= Rd
<< 8;
12764 inst
.instruction
|= Rn
<< 16;
12765 inst
.instruction
|= Rm
;
12771 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12772 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12773 _("SMC is not permitted on this architecture"));
12774 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12775 _("expression too complex"));
12776 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12777 inst
.instruction
|= (value
& 0xf000) >> 12;
12778 inst
.instruction
|= (value
& 0x0ff0);
12779 inst
.instruction
|= (value
& 0x000f) << 16;
12780 /* PR gas/15623: SMC instructions must be last in an IT block. */
12781 set_it_insn_type_last ();
12787 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12789 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12790 inst
.instruction
|= (value
& 0x0fff);
12791 inst
.instruction
|= (value
& 0xf000) << 4;
12795 do_t_ssat_usat (int bias
)
12799 Rd
= inst
.operands
[0].reg
;
12800 Rn
= inst
.operands
[2].reg
;
12802 reject_bad_reg (Rd
);
12803 reject_bad_reg (Rn
);
12805 inst
.instruction
|= Rd
<< 8;
12806 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12807 inst
.instruction
|= Rn
<< 16;
12809 if (inst
.operands
[3].present
)
12811 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12813 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12815 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12816 _("expression too complex"));
12818 if (shift_amount
!= 0)
12820 constraint (shift_amount
> 31,
12821 _("shift expression is too large"));
12823 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12824 inst
.instruction
|= 0x00200000; /* sh bit. */
12826 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12827 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12835 do_t_ssat_usat (1);
12843 Rd
= inst
.operands
[0].reg
;
12844 Rn
= inst
.operands
[2].reg
;
12846 reject_bad_reg (Rd
);
12847 reject_bad_reg (Rn
);
12849 inst
.instruction
|= Rd
<< 8;
12850 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12851 inst
.instruction
|= Rn
<< 16;
12857 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12858 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12859 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12860 || inst
.operands
[2].negative
,
12863 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12865 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12866 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12867 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12868 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12874 if (!inst
.operands
[2].present
)
12875 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12877 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12878 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12879 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12882 inst
.instruction
|= inst
.operands
[0].reg
;
12883 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12884 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12885 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12891 unsigned Rd
, Rn
, Rm
;
12893 Rd
= inst
.operands
[0].reg
;
12894 Rn
= inst
.operands
[1].reg
;
12895 Rm
= inst
.operands
[2].reg
;
12897 reject_bad_reg (Rd
);
12898 reject_bad_reg (Rn
);
12899 reject_bad_reg (Rm
);
12901 inst
.instruction
|= Rd
<< 8;
12902 inst
.instruction
|= Rn
<< 16;
12903 inst
.instruction
|= Rm
;
12904 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12912 Rd
= inst
.operands
[0].reg
;
12913 Rm
= inst
.operands
[1].reg
;
12915 reject_bad_reg (Rd
);
12916 reject_bad_reg (Rm
);
12918 if (inst
.instruction
<= 0xffff
12919 && inst
.size_req
!= 4
12920 && Rd
<= 7 && Rm
<= 7
12921 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12923 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12924 inst
.instruction
|= Rd
;
12925 inst
.instruction
|= Rm
<< 3;
12927 else if (unified_syntax
)
12929 if (inst
.instruction
<= 0xffff)
12930 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12931 inst
.instruction
|= Rd
<< 8;
12932 inst
.instruction
|= Rm
;
12933 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12937 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12938 _("Thumb encoding does not support rotation"));
12939 constraint (1, BAD_HIREG
);
12946 /* We have to do the following check manually as ARM_EXT_OS only applies
12948 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12950 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12951 /* This only applies to the v6m howver, not later architectures. */
12952 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12953 as_bad (_("SVC is not permitted on this architecture"));
12954 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12957 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12966 half
= (inst
.instruction
& 0x10) != 0;
12967 set_it_insn_type_last ();
12968 constraint (inst
.operands
[0].immisreg
,
12969 _("instruction requires register index"));
12971 Rn
= inst
.operands
[0].reg
;
12972 Rm
= inst
.operands
[0].imm
;
12974 constraint (Rn
== REG_SP
, BAD_SP
);
12975 reject_bad_reg (Rm
);
12977 constraint (!half
&& inst
.operands
[0].shifted
,
12978 _("instruction does not allow shifted index"));
12979 inst
.instruction
|= (Rn
<< 16) | Rm
;
12985 if (!inst
.operands
[0].present
)
12986 inst
.operands
[0].imm
= 0;
12988 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12990 constraint (inst
.size_req
== 2,
12991 _("immediate value out of range"));
12992 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12993 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12994 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12998 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12999 inst
.instruction
|= inst
.operands
[0].imm
;
13002 set_it_insn_type (NEUTRAL_IT_INSN
);
13009 do_t_ssat_usat (0);
13017 Rd
= inst
.operands
[0].reg
;
13018 Rn
= inst
.operands
[2].reg
;
13020 reject_bad_reg (Rd
);
13021 reject_bad_reg (Rn
);
13023 inst
.instruction
|= Rd
<< 8;
13024 inst
.instruction
|= inst
.operands
[1].imm
;
13025 inst
.instruction
|= Rn
<< 16;
13028 /* Neon instruction encoder helpers. */
13030 /* Encodings for the different types for various Neon opcodes. */
13032 /* An "invalid" code for the following tables. */
13035 struct neon_tab_entry
13038 unsigned float_or_poly
;
13039 unsigned scalar_or_imm
;
13042 /* Map overloaded Neon opcodes to their respective encodings. */
13043 #define NEON_ENC_TAB \
13044 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13045 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13046 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13047 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13048 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13049 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13050 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13051 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13052 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13053 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13054 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13055 /* Register variants of the following two instructions are encoded as
13056 vcge / vcgt with the operands reversed. */ \
13057 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13058 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13059 X(vfma, N_INV, 0x0000c10, N_INV), \
13060 X(vfms, N_INV, 0x0200c10, N_INV), \
13061 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13062 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13063 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13064 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13065 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13066 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13067 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13068 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13069 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13070 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13071 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13072 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13073 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13074 X(vshl, 0x0000400, N_INV, 0x0800510), \
13075 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13076 X(vand, 0x0000110, N_INV, 0x0800030), \
13077 X(vbic, 0x0100110, N_INV, 0x0800030), \
13078 X(veor, 0x1000110, N_INV, N_INV), \
13079 X(vorn, 0x0300110, N_INV, 0x0800010), \
13080 X(vorr, 0x0200110, N_INV, 0x0800010), \
13081 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13082 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13083 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13084 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13085 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13086 X(vst1, 0x0000000, 0x0800000, N_INV), \
13087 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13088 X(vst2, 0x0000100, 0x0800100, N_INV), \
13089 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13090 X(vst3, 0x0000200, 0x0800200, N_INV), \
13091 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13092 X(vst4, 0x0000300, 0x0800300, N_INV), \
13093 X(vmovn, 0x1b20200, N_INV, N_INV), \
13094 X(vtrn, 0x1b20080, N_INV, N_INV), \
13095 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13096 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13097 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13098 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13099 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13100 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13101 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13102 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13103 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13104 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13105 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13106 X(vseleq, 0xe000a00, N_INV, N_INV), \
13107 X(vselvs, 0xe100a00, N_INV, N_INV), \
13108 X(vselge, 0xe200a00, N_INV, N_INV), \
13109 X(vselgt, 0xe300a00, N_INV, N_INV), \
13110 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13111 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13112 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13113 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13114 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13115 X(aes, 0x3b00300, N_INV, N_INV), \
13116 X(sha3op, 0x2000c00, N_INV, N_INV), \
13117 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13118 X(sha2op, 0x3ba0380, N_INV, N_INV)
13122 #define X(OPC,I,F,S) N_MNEM_##OPC
13127 static const struct neon_tab_entry neon_enc_tab
[] =
13129 #define X(OPC,I,F,S) { (I), (F), (S) }
13134 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13135 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13136 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13137 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13138 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13139 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13140 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13141 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13142 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13143 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13144 #define NEON_ENC_SINGLE_(X) \
13145 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13146 #define NEON_ENC_DOUBLE_(X) \
13147 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13148 #define NEON_ENC_FPV8_(X) \
13149 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13151 #define NEON_ENCODE(type, inst) \
13154 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13155 inst.is_neon = 1; \
13159 #define check_neon_suffixes \
13162 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13164 as_bad (_("invalid neon suffix for non neon instruction")); \
13170 /* Define shapes for instruction operands. The following mnemonic characters
13171 are used in this table:
13173 F - VFP S<n> register
13174 D - Neon D<n> register
13175 Q - Neon Q<n> register
13179 L - D<n> register list
13181 This table is used to generate various data:
13182 - enumerations of the form NS_DDR to be used as arguments to
13184 - a table classifying shapes into single, double, quad, mixed.
13185 - a table used to drive neon_select_shape. */
13187 #define NEON_SHAPE_DEF \
13188 X(3, (D, D, D), DOUBLE), \
13189 X(3, (Q, Q, Q), QUAD), \
13190 X(3, (D, D, I), DOUBLE), \
13191 X(3, (Q, Q, I), QUAD), \
13192 X(3, (D, D, S), DOUBLE), \
13193 X(3, (Q, Q, S), QUAD), \
13194 X(2, (D, D), DOUBLE), \
13195 X(2, (Q, Q), QUAD), \
13196 X(2, (D, S), DOUBLE), \
13197 X(2, (Q, S), QUAD), \
13198 X(2, (D, R), DOUBLE), \
13199 X(2, (Q, R), QUAD), \
13200 X(2, (D, I), DOUBLE), \
13201 X(2, (Q, I), QUAD), \
13202 X(3, (D, L, D), DOUBLE), \
13203 X(2, (D, Q), MIXED), \
13204 X(2, (Q, D), MIXED), \
13205 X(3, (D, Q, I), MIXED), \
13206 X(3, (Q, D, I), MIXED), \
13207 X(3, (Q, D, D), MIXED), \
13208 X(3, (D, Q, Q), MIXED), \
13209 X(3, (Q, Q, D), MIXED), \
13210 X(3, (Q, D, S), MIXED), \
13211 X(3, (D, Q, S), MIXED), \
13212 X(4, (D, D, D, I), DOUBLE), \
13213 X(4, (Q, Q, Q, I), QUAD), \
13214 X(2, (F, F), SINGLE), \
13215 X(3, (F, F, F), SINGLE), \
13216 X(2, (F, I), SINGLE), \
13217 X(2, (F, D), MIXED), \
13218 X(2, (D, F), MIXED), \
13219 X(3, (F, F, I), MIXED), \
13220 X(4, (R, R, F, F), SINGLE), \
13221 X(4, (F, F, R, R), SINGLE), \
13222 X(3, (D, R, R), DOUBLE), \
13223 X(3, (R, R, D), DOUBLE), \
13224 X(2, (S, R), SINGLE), \
13225 X(2, (R, S), SINGLE), \
13226 X(2, (F, R), SINGLE), \
13227 X(2, (R, F), SINGLE)
13229 #define S2(A,B) NS_##A##B
13230 #define S3(A,B,C) NS_##A##B##C
13231 #define S4(A,B,C,D) NS_##A##B##C##D
13233 #define X(N, L, C) S##N L
13246 enum neon_shape_class
13254 #define X(N, L, C) SC_##C
13256 static enum neon_shape_class neon_shape_class
[] =
13274 /* Register widths of above. */
13275 static unsigned neon_shape_el_size
[] =
13286 struct neon_shape_info
13289 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13292 #define S2(A,B) { SE_##A, SE_##B }
13293 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13294 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13296 #define X(N, L, C) { N, S##N L }
13298 static struct neon_shape_info neon_shape_tab
[] =
13308 /* Bit masks used in type checking given instructions.
13309 'N_EQK' means the type must be the same as (or based on in some way) the key
13310 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13311 set, various other bits can be set as well in order to modify the meaning of
13312 the type constraint. */
13314 enum neon_type_mask
13338 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13339 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13340 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13341 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13342 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13343 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13344 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13345 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13346 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13347 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13348 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13350 N_MAX_NONSPECIAL
= N_P64
13353 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13355 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13356 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13357 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13358 #define N_SUF_32 (N_SU_32 | N_F32)
13359 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13360 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13362 /* Pass this as the first type argument to neon_check_type to ignore types
13364 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13366 /* Select a "shape" for the current instruction (describing register types or
13367 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13368 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13369 function of operand parsing, so this function doesn't need to be called.
13370 Shapes should be listed in order of decreasing length. */
13372 static enum neon_shape
13373 neon_select_shape (enum neon_shape shape
, ...)
13376 enum neon_shape first_shape
= shape
;
13378 /* Fix missing optional operands. FIXME: we don't know at this point how
13379 many arguments we should have, so this makes the assumption that we have
13380 > 1. This is true of all current Neon opcodes, I think, but may not be
13381 true in the future. */
13382 if (!inst
.operands
[1].present
)
13383 inst
.operands
[1] = inst
.operands
[0];
13385 va_start (ap
, shape
);
13387 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13392 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13394 if (!inst
.operands
[j
].present
)
13400 switch (neon_shape_tab
[shape
].el
[j
])
13403 if (!(inst
.operands
[j
].isreg
13404 && inst
.operands
[j
].isvec
13405 && inst
.operands
[j
].issingle
13406 && !inst
.operands
[j
].isquad
))
13411 if (!(inst
.operands
[j
].isreg
13412 && inst
.operands
[j
].isvec
13413 && !inst
.operands
[j
].isquad
13414 && !inst
.operands
[j
].issingle
))
13419 if (!(inst
.operands
[j
].isreg
13420 && !inst
.operands
[j
].isvec
))
13425 if (!(inst
.operands
[j
].isreg
13426 && inst
.operands
[j
].isvec
13427 && inst
.operands
[j
].isquad
13428 && !inst
.operands
[j
].issingle
))
13433 if (!(!inst
.operands
[j
].isreg
13434 && !inst
.operands
[j
].isscalar
))
13439 if (!(!inst
.operands
[j
].isreg
13440 && inst
.operands
[j
].isscalar
))
13450 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13451 /* We've matched all the entries in the shape table, and we don't
13452 have any left over operands which have not been matched. */
13458 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13459 first_error (_("invalid instruction shape"));
13464 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13465 means the Q bit should be set). */
13468 neon_quad (enum neon_shape shape
)
13470 return neon_shape_class
[shape
] == SC_QUAD
;
13474 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13477 /* Allow modification to be made to types which are constrained to be
13478 based on the key element, based on bits set alongside N_EQK. */
13479 if ((typebits
& N_EQK
) != 0)
13481 if ((typebits
& N_HLF
) != 0)
13483 else if ((typebits
& N_DBL
) != 0)
13485 if ((typebits
& N_SGN
) != 0)
13486 *g_type
= NT_signed
;
13487 else if ((typebits
& N_UNS
) != 0)
13488 *g_type
= NT_unsigned
;
13489 else if ((typebits
& N_INT
) != 0)
13490 *g_type
= NT_integer
;
13491 else if ((typebits
& N_FLT
) != 0)
13492 *g_type
= NT_float
;
13493 else if ((typebits
& N_SIZ
) != 0)
13494 *g_type
= NT_untyped
;
13498 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13499 operand type, i.e. the single type specified in a Neon instruction when it
13500 is the only one given. */
13502 static struct neon_type_el
13503 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13505 struct neon_type_el dest
= *key
;
13507 gas_assert ((thisarg
& N_EQK
) != 0);
13509 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13514 /* Convert Neon type and size into compact bitmask representation. */
13516 static enum neon_type_mask
13517 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13524 case 8: return N_8
;
13525 case 16: return N_16
;
13526 case 32: return N_32
;
13527 case 64: return N_64
;
13535 case 8: return N_I8
;
13536 case 16: return N_I16
;
13537 case 32: return N_I32
;
13538 case 64: return N_I64
;
13546 case 16: return N_F16
;
13547 case 32: return N_F32
;
13548 case 64: return N_F64
;
13556 case 8: return N_P8
;
13557 case 16: return N_P16
;
13558 case 64: return N_P64
;
13566 case 8: return N_S8
;
13567 case 16: return N_S16
;
13568 case 32: return N_S32
;
13569 case 64: return N_S64
;
13577 case 8: return N_U8
;
13578 case 16: return N_U16
;
13579 case 32: return N_U32
;
13580 case 64: return N_U64
;
13591 /* Convert compact Neon bitmask type representation to a type and size. Only
13592 handles the case where a single bit is set in the mask. */
13595 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13596 enum neon_type_mask mask
)
13598 if ((mask
& N_EQK
) != 0)
13601 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13603 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13605 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13607 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13612 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13614 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13615 *type
= NT_unsigned
;
13616 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13617 *type
= NT_integer
;
13618 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13619 *type
= NT_untyped
;
13620 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13622 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13630 /* Modify a bitmask of allowed types. This is only needed for type
13634 modify_types_allowed (unsigned allowed
, unsigned mods
)
13637 enum neon_el_type type
;
13643 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13645 if (el_type_of_type_chk (&type
, &size
,
13646 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13648 neon_modify_type_size (mods
, &type
, &size
);
13649 destmask
|= type_chk_of_el_type (type
, size
);
13656 /* Check type and return type classification.
13657 The manual states (paraphrase): If one datatype is given, it indicates the
13659 - the second operand, if there is one
13660 - the operand, if there is no second operand
13661 - the result, if there are no operands.
13662 This isn't quite good enough though, so we use a concept of a "key" datatype
13663 which is set on a per-instruction basis, which is the one which matters when
13664 only one data type is written.
13665 Note: this function has side-effects (e.g. filling in missing operands). All
13666 Neon instructions should call it before performing bit encoding. */
13668 static struct neon_type_el
13669 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13672 unsigned i
, pass
, key_el
= 0;
13673 unsigned types
[NEON_MAX_TYPE_ELS
];
13674 enum neon_el_type k_type
= NT_invtype
;
13675 unsigned k_size
= -1u;
13676 struct neon_type_el badtype
= {NT_invtype
, -1};
13677 unsigned key_allowed
= 0;
13679 /* Optional registers in Neon instructions are always (not) in operand 1.
13680 Fill in the missing operand here, if it was omitted. */
13681 if (els
> 1 && !inst
.operands
[1].present
)
13682 inst
.operands
[1] = inst
.operands
[0];
13684 /* Suck up all the varargs. */
13686 for (i
= 0; i
< els
; i
++)
13688 unsigned thisarg
= va_arg (ap
, unsigned);
13689 if (thisarg
== N_IGNORE_TYPE
)
13694 types
[i
] = thisarg
;
13695 if ((thisarg
& N_KEY
) != 0)
13700 if (inst
.vectype
.elems
> 0)
13701 for (i
= 0; i
< els
; i
++)
13702 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13704 first_error (_("types specified in both the mnemonic and operands"));
13708 /* Duplicate inst.vectype elements here as necessary.
13709 FIXME: No idea if this is exactly the same as the ARM assembler,
13710 particularly when an insn takes one register and one non-register
13712 if (inst
.vectype
.elems
== 1 && els
> 1)
13715 inst
.vectype
.elems
= els
;
13716 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13717 for (j
= 0; j
< els
; j
++)
13719 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13722 else if (inst
.vectype
.elems
== 0 && els
> 0)
13725 /* No types were given after the mnemonic, so look for types specified
13726 after each operand. We allow some flexibility here; as long as the
13727 "key" operand has a type, we can infer the others. */
13728 for (j
= 0; j
< els
; j
++)
13729 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13730 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13732 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13734 for (j
= 0; j
< els
; j
++)
13735 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13736 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13741 first_error (_("operand types can't be inferred"));
13745 else if (inst
.vectype
.elems
!= els
)
13747 first_error (_("type specifier has the wrong number of parts"));
13751 for (pass
= 0; pass
< 2; pass
++)
13753 for (i
= 0; i
< els
; i
++)
13755 unsigned thisarg
= types
[i
];
13756 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13757 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13758 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13759 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13761 /* Decay more-specific signed & unsigned types to sign-insensitive
13762 integer types if sign-specific variants are unavailable. */
13763 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13764 && (types_allowed
& N_SU_ALL
) == 0)
13765 g_type
= NT_integer
;
13767 /* If only untyped args are allowed, decay any more specific types to
13768 them. Some instructions only care about signs for some element
13769 sizes, so handle that properly. */
13770 if (((types_allowed
& N_UNT
) == 0)
13771 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13772 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13773 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13774 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13775 g_type
= NT_untyped
;
13779 if ((thisarg
& N_KEY
) != 0)
13783 key_allowed
= thisarg
& ~N_KEY
;
13788 if ((thisarg
& N_VFP
) != 0)
13790 enum neon_shape_el regshape
;
13791 unsigned regwidth
, match
;
13793 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13796 first_error (_("invalid instruction shape"));
13799 regshape
= neon_shape_tab
[ns
].el
[i
];
13800 regwidth
= neon_shape_el_size
[regshape
];
13802 /* In VFP mode, operands must match register widths. If we
13803 have a key operand, use its width, else use the width of
13804 the current operand. */
13810 if (regwidth
!= match
)
13812 first_error (_("operand size must match register width"));
13817 if ((thisarg
& N_EQK
) == 0)
13819 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13821 if ((given_type
& types_allowed
) == 0)
13823 first_error (_("bad type in Neon instruction"));
13829 enum neon_el_type mod_k_type
= k_type
;
13830 unsigned mod_k_size
= k_size
;
13831 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13832 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13834 first_error (_("inconsistent types in Neon instruction"));
13842 return inst
.vectype
.el
[key_el
];
13845 /* Neon-style VFP instruction forwarding. */
13847 /* Thumb VFP instructions have 0xE in the condition field. */
13850 do_vfp_cond_or_thumb (void)
13855 inst
.instruction
|= 0xe0000000;
13857 inst
.instruction
|= inst
.cond
<< 28;
13860 /* Look up and encode a simple mnemonic, for use as a helper function for the
13861 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13862 etc. It is assumed that operand parsing has already been done, and that the
13863 operands are in the form expected by the given opcode (this isn't necessarily
13864 the same as the form in which they were parsed, hence some massaging must
13865 take place before this function is called).
13866 Checks current arch version against that in the looked-up opcode. */
13869 do_vfp_nsyn_opcode (const char *opname
)
13871 const struct asm_opcode
*opcode
;
13873 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13879 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13886 inst
.instruction
= opcode
->tvalue
;
13887 opcode
->tencode ();
13891 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13892 opcode
->aencode ();
13897 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13899 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13904 do_vfp_nsyn_opcode ("fadds");
13906 do_vfp_nsyn_opcode ("fsubs");
13911 do_vfp_nsyn_opcode ("faddd");
13913 do_vfp_nsyn_opcode ("fsubd");
13917 /* Check operand types to see if this is a VFP instruction, and if so call
13921 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13923 enum neon_shape rs
;
13924 struct neon_type_el et
;
13929 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13930 et
= neon_check_type (2, rs
,
13931 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13935 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13936 et
= neon_check_type (3, rs
,
13937 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13944 if (et
.type
!= NT_invtype
)
13955 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13957 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13962 do_vfp_nsyn_opcode ("fmacs");
13964 do_vfp_nsyn_opcode ("fnmacs");
13969 do_vfp_nsyn_opcode ("fmacd");
13971 do_vfp_nsyn_opcode ("fnmacd");
13976 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13978 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13983 do_vfp_nsyn_opcode ("ffmas");
13985 do_vfp_nsyn_opcode ("ffnmas");
13990 do_vfp_nsyn_opcode ("ffmad");
13992 do_vfp_nsyn_opcode ("ffnmad");
13997 do_vfp_nsyn_mul (enum neon_shape rs
)
14000 do_vfp_nsyn_opcode ("fmuls");
14002 do_vfp_nsyn_opcode ("fmuld");
14006 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14008 int is_neg
= (inst
.instruction
& 0x80) != 0;
14009 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
14014 do_vfp_nsyn_opcode ("fnegs");
14016 do_vfp_nsyn_opcode ("fabss");
14021 do_vfp_nsyn_opcode ("fnegd");
14023 do_vfp_nsyn_opcode ("fabsd");
14027 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14028 insns belong to Neon, and are handled elsewhere. */
14031 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14033 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14037 do_vfp_nsyn_opcode ("fldmdbs");
14039 do_vfp_nsyn_opcode ("fldmias");
14044 do_vfp_nsyn_opcode ("fstmdbs");
14046 do_vfp_nsyn_opcode ("fstmias");
14051 do_vfp_nsyn_sqrt (void)
14053 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14054 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14057 do_vfp_nsyn_opcode ("fsqrts");
14059 do_vfp_nsyn_opcode ("fsqrtd");
14063 do_vfp_nsyn_div (void)
14065 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14066 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14067 N_F32
| N_F64
| N_KEY
| N_VFP
);
14070 do_vfp_nsyn_opcode ("fdivs");
14072 do_vfp_nsyn_opcode ("fdivd");
14076 do_vfp_nsyn_nmul (void)
14078 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14079 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14080 N_F32
| N_F64
| N_KEY
| N_VFP
);
14084 NEON_ENCODE (SINGLE
, inst
);
14085 do_vfp_sp_dyadic ();
14089 NEON_ENCODE (DOUBLE
, inst
);
14090 do_vfp_dp_rd_rn_rm ();
14092 do_vfp_cond_or_thumb ();
14096 do_vfp_nsyn_cmp (void)
14098 if (inst
.operands
[1].isreg
)
14100 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14101 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14105 NEON_ENCODE (SINGLE
, inst
);
14106 do_vfp_sp_monadic ();
14110 NEON_ENCODE (DOUBLE
, inst
);
14111 do_vfp_dp_rd_rm ();
14116 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14117 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14119 switch (inst
.instruction
& 0x0fffffff)
14122 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14125 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14133 NEON_ENCODE (SINGLE
, inst
);
14134 do_vfp_sp_compare_z ();
14138 NEON_ENCODE (DOUBLE
, inst
);
14142 do_vfp_cond_or_thumb ();
14146 nsyn_insert_sp (void)
14148 inst
.operands
[1] = inst
.operands
[0];
14149 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14150 inst
.operands
[0].reg
= REG_SP
;
14151 inst
.operands
[0].isreg
= 1;
14152 inst
.operands
[0].writeback
= 1;
14153 inst
.operands
[0].present
= 1;
14157 do_vfp_nsyn_push (void)
14160 if (inst
.operands
[1].issingle
)
14161 do_vfp_nsyn_opcode ("fstmdbs");
14163 do_vfp_nsyn_opcode ("fstmdbd");
14167 do_vfp_nsyn_pop (void)
14170 if (inst
.operands
[1].issingle
)
14171 do_vfp_nsyn_opcode ("fldmias");
14173 do_vfp_nsyn_opcode ("fldmiad");
14176 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14177 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14180 neon_dp_fixup (struct arm_it
* insn
)
14182 unsigned int i
= insn
->instruction
;
14187 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14198 insn
->instruction
= i
;
14201 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14205 neon_logbits (unsigned x
)
14207 return ffs (x
) - 4;
14210 #define LOW4(R) ((R) & 0xf)
14211 #define HI1(R) (((R) >> 4) & 1)
14213 /* Encode insns with bit pattern:
14215 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14216 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14218 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14219 different meaning for some instruction. */
14222 neon_three_same (int isquad
, int ubit
, int size
)
14224 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14225 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14226 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14227 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14228 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14229 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14230 inst
.instruction
|= (isquad
!= 0) << 6;
14231 inst
.instruction
|= (ubit
!= 0) << 24;
14233 inst
.instruction
|= neon_logbits (size
) << 20;
14235 neon_dp_fixup (&inst
);
14238 /* Encode instructions of the form:
14240 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14241 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14243 Don't write size if SIZE == -1. */
14246 neon_two_same (int qbit
, int ubit
, int size
)
14248 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14249 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14250 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14251 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14252 inst
.instruction
|= (qbit
!= 0) << 6;
14253 inst
.instruction
|= (ubit
!= 0) << 24;
14256 inst
.instruction
|= neon_logbits (size
) << 18;
14258 neon_dp_fixup (&inst
);
14261 /* Neon instruction encoders, in approximate order of appearance. */
14264 do_neon_dyadic_i_su (void)
14266 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14267 struct neon_type_el et
= neon_check_type (3, rs
,
14268 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14269 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14273 do_neon_dyadic_i64_su (void)
14275 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14276 struct neon_type_el et
= neon_check_type (3, rs
,
14277 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14278 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14282 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14285 unsigned size
= et
.size
>> 3;
14286 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14287 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14288 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14289 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14290 inst
.instruction
|= (isquad
!= 0) << 6;
14291 inst
.instruction
|= immbits
<< 16;
14292 inst
.instruction
|= (size
>> 3) << 7;
14293 inst
.instruction
|= (size
& 0x7) << 19;
14295 inst
.instruction
|= (uval
!= 0) << 24;
14297 neon_dp_fixup (&inst
);
14301 do_neon_shl_imm (void)
14303 if (!inst
.operands
[2].isreg
)
14305 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14306 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14307 int imm
= inst
.operands
[2].imm
;
14309 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14310 _("immediate out of range for shift"));
14311 NEON_ENCODE (IMMED
, inst
);
14312 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14316 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14317 struct neon_type_el et
= neon_check_type (3, rs
,
14318 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14321 /* VSHL/VQSHL 3-register variants have syntax such as:
14323 whereas other 3-register operations encoded by neon_three_same have
14326 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14328 tmp
= inst
.operands
[2].reg
;
14329 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14330 inst
.operands
[1].reg
= tmp
;
14331 NEON_ENCODE (INTEGER
, inst
);
14332 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14337 do_neon_qshl_imm (void)
14339 if (!inst
.operands
[2].isreg
)
14341 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14342 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14343 int imm
= inst
.operands
[2].imm
;
14345 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14346 _("immediate out of range for shift"));
14347 NEON_ENCODE (IMMED
, inst
);
14348 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14352 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14353 struct neon_type_el et
= neon_check_type (3, rs
,
14354 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14357 /* See note in do_neon_shl_imm. */
14358 tmp
= inst
.operands
[2].reg
;
14359 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14360 inst
.operands
[1].reg
= tmp
;
14361 NEON_ENCODE (INTEGER
, inst
);
14362 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14367 do_neon_rshl (void)
14369 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14370 struct neon_type_el et
= neon_check_type (3, rs
,
14371 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14374 tmp
= inst
.operands
[2].reg
;
14375 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14376 inst
.operands
[1].reg
= tmp
;
14377 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14381 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14383 /* Handle .I8 pseudo-instructions. */
14386 /* Unfortunately, this will make everything apart from zero out-of-range.
14387 FIXME is this the intended semantics? There doesn't seem much point in
14388 accepting .I8 if so. */
14389 immediate
|= immediate
<< 8;
14395 if (immediate
== (immediate
& 0x000000ff))
14397 *immbits
= immediate
;
14400 else if (immediate
== (immediate
& 0x0000ff00))
14402 *immbits
= immediate
>> 8;
14405 else if (immediate
== (immediate
& 0x00ff0000))
14407 *immbits
= immediate
>> 16;
14410 else if (immediate
== (immediate
& 0xff000000))
14412 *immbits
= immediate
>> 24;
14415 if ((immediate
& 0xffff) != (immediate
>> 16))
14416 goto bad_immediate
;
14417 immediate
&= 0xffff;
14420 if (immediate
== (immediate
& 0x000000ff))
14422 *immbits
= immediate
;
14425 else if (immediate
== (immediate
& 0x0000ff00))
14427 *immbits
= immediate
>> 8;
14432 first_error (_("immediate value out of range"));
14437 do_neon_logic (void)
14439 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14441 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14442 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14443 /* U bit and size field were set as part of the bitmask. */
14444 NEON_ENCODE (INTEGER
, inst
);
14445 neon_three_same (neon_quad (rs
), 0, -1);
14449 const int three_ops_form
= (inst
.operands
[2].present
14450 && !inst
.operands
[2].isreg
);
14451 const int immoperand
= (three_ops_form
? 2 : 1);
14452 enum neon_shape rs
= (three_ops_form
14453 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14454 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14455 struct neon_type_el et
= neon_check_type (2, rs
,
14456 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14457 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14461 if (et
.type
== NT_invtype
)
14464 if (three_ops_form
)
14465 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14466 _("first and second operands shall be the same register"));
14468 NEON_ENCODE (IMMED
, inst
);
14470 immbits
= inst
.operands
[immoperand
].imm
;
14473 /* .i64 is a pseudo-op, so the immediate must be a repeating
14475 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14476 inst
.operands
[immoperand
].reg
: 0))
14478 /* Set immbits to an invalid constant. */
14479 immbits
= 0xdeadbeef;
14486 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14490 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14494 /* Pseudo-instruction for VBIC. */
14495 neon_invert_size (&immbits
, 0, et
.size
);
14496 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14500 /* Pseudo-instruction for VORR. */
14501 neon_invert_size (&immbits
, 0, et
.size
);
14502 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14512 inst
.instruction
|= neon_quad (rs
) << 6;
14513 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14514 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14515 inst
.instruction
|= cmode
<< 8;
14516 neon_write_immbits (immbits
);
14518 neon_dp_fixup (&inst
);
14523 do_neon_bitfield (void)
14525 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14526 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14527 neon_three_same (neon_quad (rs
), 0, -1);
14531 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14534 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14535 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14537 if (et
.type
== NT_float
)
14539 NEON_ENCODE (FLOAT
, inst
);
14540 neon_three_same (neon_quad (rs
), 0, -1);
14544 NEON_ENCODE (INTEGER
, inst
);
14545 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14550 do_neon_dyadic_if_su (void)
14552 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14556 do_neon_dyadic_if_su_d (void)
14558 /* This version only allow D registers, but that constraint is enforced during
14559 operand parsing so we don't need to do anything extra here. */
14560 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14564 do_neon_dyadic_if_i_d (void)
14566 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14567 affected if we specify unsigned args. */
14568 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14571 enum vfp_or_neon_is_neon_bits
14574 NEON_CHECK_ARCH
= 2,
14575 NEON_CHECK_ARCH8
= 4
14578 /* Call this function if an instruction which may have belonged to the VFP or
14579 Neon instruction sets, but turned out to be a Neon instruction (due to the
14580 operand types involved, etc.). We have to check and/or fix-up a couple of
14583 - Make sure the user hasn't attempted to make a Neon instruction
14585 - Alter the value in the condition code field if necessary.
14586 - Make sure that the arch supports Neon instructions.
14588 Which of these operations take place depends on bits from enum
14589 vfp_or_neon_is_neon_bits.
14591 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14592 current instruction's condition is COND_ALWAYS, the condition field is
14593 changed to inst.uncond_value. This is necessary because instructions shared
14594 between VFP and Neon may be conditional for the VFP variants only, and the
14595 unconditional Neon version must have, e.g., 0xF in the condition field. */
14598 vfp_or_neon_is_neon (unsigned check
)
14600 /* Conditions are always legal in Thumb mode (IT blocks). */
14601 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14603 if (inst
.cond
!= COND_ALWAYS
)
14605 first_error (_(BAD_COND
));
14608 if (inst
.uncond_value
!= -1)
14609 inst
.instruction
|= inst
.uncond_value
<< 28;
14612 if ((check
& NEON_CHECK_ARCH
)
14613 && !mark_feature_used (&fpu_neon_ext_v1
))
14615 first_error (_(BAD_FPU
));
14619 if ((check
& NEON_CHECK_ARCH8
)
14620 && !mark_feature_used (&fpu_neon_ext_armv8
))
14622 first_error (_(BAD_FPU
));
14630 do_neon_addsub_if_i (void)
14632 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14635 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14638 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14639 affected if we specify unsigned args. */
14640 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14643 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14645 V<op> A,B (A is operand 0, B is operand 2)
14650 so handle that case specially. */
14653 neon_exchange_operands (void)
14655 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14656 if (inst
.operands
[1].present
)
14658 /* Swap operands[1] and operands[2]. */
14659 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14660 inst
.operands
[1] = inst
.operands
[2];
14661 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14665 inst
.operands
[1] = inst
.operands
[2];
14666 inst
.operands
[2] = inst
.operands
[0];
14671 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14673 if (inst
.operands
[2].isreg
)
14676 neon_exchange_operands ();
14677 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14681 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14682 struct neon_type_el et
= neon_check_type (2, rs
,
14683 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14685 NEON_ENCODE (IMMED
, inst
);
14686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14687 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14688 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14689 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14690 inst
.instruction
|= neon_quad (rs
) << 6;
14691 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14692 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14694 neon_dp_fixup (&inst
);
14701 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14705 do_neon_cmp_inv (void)
14707 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14713 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14716 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14717 scalars, which are encoded in 5 bits, M : Rm.
14718 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14719 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14723 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14725 unsigned regno
= NEON_SCALAR_REG (scalar
);
14726 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14731 if (regno
> 7 || elno
> 3)
14733 return regno
| (elno
<< 3);
14736 if (regno
> 15 || elno
> 1)
14738 return regno
| (elno
<< 4);
14742 first_error (_("scalar out of range for multiply instruction"));
14748 /* Encode multiply / multiply-accumulate scalar instructions. */
14751 neon_mul_mac (struct neon_type_el et
, int ubit
)
14755 /* Give a more helpful error message if we have an invalid type. */
14756 if (et
.type
== NT_invtype
)
14759 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14762 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14764 inst
.instruction
|= LOW4 (scalar
);
14765 inst
.instruction
|= HI1 (scalar
) << 5;
14766 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14767 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14768 inst
.instruction
|= (ubit
!= 0) << 24;
14770 neon_dp_fixup (&inst
);
14774 do_neon_mac_maybe_scalar (void)
14776 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14779 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14782 if (inst
.operands
[2].isscalar
)
14784 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14785 struct neon_type_el et
= neon_check_type (3, rs
,
14786 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14787 NEON_ENCODE (SCALAR
, inst
);
14788 neon_mul_mac (et
, neon_quad (rs
));
14792 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14793 affected if we specify unsigned args. */
14794 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14799 do_neon_fmac (void)
14801 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14804 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14807 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14813 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14814 struct neon_type_el et
= neon_check_type (3, rs
,
14815 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14816 neon_three_same (neon_quad (rs
), 0, et
.size
);
14819 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14820 same types as the MAC equivalents. The polynomial type for this instruction
14821 is encoded the same as the integer type. */
14826 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14829 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14832 if (inst
.operands
[2].isscalar
)
14833 do_neon_mac_maybe_scalar ();
14835 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14839 do_neon_qdmulh (void)
14841 if (inst
.operands
[2].isscalar
)
14843 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14844 struct neon_type_el et
= neon_check_type (3, rs
,
14845 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14846 NEON_ENCODE (SCALAR
, inst
);
14847 neon_mul_mac (et
, neon_quad (rs
));
14851 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14852 struct neon_type_el et
= neon_check_type (3, rs
,
14853 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14854 NEON_ENCODE (INTEGER
, inst
);
14855 /* The U bit (rounding) comes from bit mask. */
14856 neon_three_same (neon_quad (rs
), 0, et
.size
);
14861 do_neon_fcmp_absolute (void)
14863 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14864 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14865 /* Size field comes from bit mask. */
14866 neon_three_same (neon_quad (rs
), 1, -1);
14870 do_neon_fcmp_absolute_inv (void)
14872 neon_exchange_operands ();
14873 do_neon_fcmp_absolute ();
14877 do_neon_step (void)
14879 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14880 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14881 neon_three_same (neon_quad (rs
), 0, -1);
14885 do_neon_abs_neg (void)
14887 enum neon_shape rs
;
14888 struct neon_type_el et
;
14890 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14893 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14896 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14897 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14899 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14900 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14901 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14902 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14903 inst
.instruction
|= neon_quad (rs
) << 6;
14904 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14905 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14907 neon_dp_fixup (&inst
);
14913 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14914 struct neon_type_el et
= neon_check_type (2, rs
,
14915 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14916 int imm
= inst
.operands
[2].imm
;
14917 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14918 _("immediate out of range for insert"));
14919 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14925 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14926 struct neon_type_el et
= neon_check_type (2, rs
,
14927 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14928 int imm
= inst
.operands
[2].imm
;
14929 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14930 _("immediate out of range for insert"));
14931 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14935 do_neon_qshlu_imm (void)
14937 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14938 struct neon_type_el et
= neon_check_type (2, rs
,
14939 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14940 int imm
= inst
.operands
[2].imm
;
14941 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14942 _("immediate out of range for shift"));
14943 /* Only encodes the 'U present' variant of the instruction.
14944 In this case, signed types have OP (bit 8) set to 0.
14945 Unsigned types have OP set to 1. */
14946 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14947 /* The rest of the bits are the same as other immediate shifts. */
14948 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14952 do_neon_qmovn (void)
14954 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14955 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14956 /* Saturating move where operands can be signed or unsigned, and the
14957 destination has the same signedness. */
14958 NEON_ENCODE (INTEGER
, inst
);
14959 if (et
.type
== NT_unsigned
)
14960 inst
.instruction
|= 0xc0;
14962 inst
.instruction
|= 0x80;
14963 neon_two_same (0, 1, et
.size
/ 2);
14967 do_neon_qmovun (void)
14969 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14970 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14971 /* Saturating move with unsigned results. Operands must be signed. */
14972 NEON_ENCODE (INTEGER
, inst
);
14973 neon_two_same (0, 1, et
.size
/ 2);
14977 do_neon_rshift_sat_narrow (void)
14979 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14980 or unsigned. If operands are unsigned, results must also be unsigned. */
14981 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14982 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14983 int imm
= inst
.operands
[2].imm
;
14984 /* This gets the bounds check, size encoding and immediate bits calculation
14988 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14989 VQMOVN.I<size> <Dd>, <Qm>. */
14992 inst
.operands
[2].present
= 0;
14993 inst
.instruction
= N_MNEM_vqmovn
;
14998 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14999 _("immediate out of range"));
15000 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15004 do_neon_rshift_sat_narrow_u (void)
15006 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15007 or unsigned. If operands are unsigned, results must also be unsigned. */
15008 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15009 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15010 int imm
= inst
.operands
[2].imm
;
15011 /* This gets the bounds check, size encoding and immediate bits calculation
15015 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15016 VQMOVUN.I<size> <Dd>, <Qm>. */
15019 inst
.operands
[2].present
= 0;
15020 inst
.instruction
= N_MNEM_vqmovun
;
15025 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15026 _("immediate out of range"));
15027 /* FIXME: The manual is kind of unclear about what value U should have in
15028 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15030 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15034 do_neon_movn (void)
15036 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15037 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15038 NEON_ENCODE (INTEGER
, inst
);
15039 neon_two_same (0, 1, et
.size
/ 2);
15043 do_neon_rshift_narrow (void)
15045 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15046 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15047 int imm
= inst
.operands
[2].imm
;
15048 /* This gets the bounds check, size encoding and immediate bits calculation
15052 /* If immediate is zero then we are a pseudo-instruction for
15053 VMOVN.I<size> <Dd>, <Qm> */
15056 inst
.operands
[2].present
= 0;
15057 inst
.instruction
= N_MNEM_vmovn
;
15062 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15063 _("immediate out of range for narrowing operation"));
15064 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15068 do_neon_shll (void)
15070 /* FIXME: Type checking when lengthening. */
15071 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15072 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15073 unsigned imm
= inst
.operands
[2].imm
;
15075 if (imm
== et
.size
)
15077 /* Maximum shift variant. */
15078 NEON_ENCODE (INTEGER
, inst
);
15079 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15080 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15081 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15082 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15083 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15085 neon_dp_fixup (&inst
);
15089 /* A more-specific type check for non-max versions. */
15090 et
= neon_check_type (2, NS_QDI
,
15091 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15092 NEON_ENCODE (IMMED
, inst
);
15093 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15097 /* Check the various types for the VCVT instruction, and return which version
15098 the current instruction is. */
15100 #define CVT_FLAVOUR_VAR \
15101 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15102 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15103 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15104 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15105 /* Half-precision conversions. */ \
15106 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15107 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15108 /* VFP instructions. */ \
15109 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15110 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15111 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15112 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15113 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15114 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15115 /* VFP instructions with bitshift. */ \
15116 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15117 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15118 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15119 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15120 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15121 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15122 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15123 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15125 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15126 neon_cvt_flavour_##C,
15128 /* The different types of conversions we can do. */
15129 enum neon_cvt_flavour
15132 neon_cvt_flavour_invalid
,
15133 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15138 static enum neon_cvt_flavour
15139 get_neon_cvt_flavour (enum neon_shape rs
)
15141 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15142 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15143 if (et.type != NT_invtype) \
15145 inst.error = NULL; \
15146 return (neon_cvt_flavour_##C); \
15149 struct neon_type_el et
;
15150 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15151 || rs
== NS_FF
) ? N_VFP
: 0;
15152 /* The instruction versions which take an immediate take one register
15153 argument, which is extended to the width of the full register. Thus the
15154 "source" and "destination" registers must have the same width. Hack that
15155 here by making the size equal to the key (wider, in this case) operand. */
15156 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15160 return neon_cvt_flavour_invalid
;
15175 /* Neon-syntax VFP conversions. */
15178 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15180 const char *opname
= 0;
15182 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15184 /* Conversions with immediate bitshift. */
15185 const char *enc
[] =
15187 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15193 if (flavour
< (int) ARRAY_SIZE (enc
))
15195 opname
= enc
[flavour
];
15196 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15197 _("operands 0 and 1 must be the same register"));
15198 inst
.operands
[1] = inst
.operands
[2];
15199 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15204 /* Conversions without bitshift. */
15205 const char *enc
[] =
15207 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15213 if (flavour
< (int) ARRAY_SIZE (enc
))
15214 opname
= enc
[flavour
];
15218 do_vfp_nsyn_opcode (opname
);
15222 do_vfp_nsyn_cvtz (void)
15224 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15225 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15226 const char *enc
[] =
15228 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15234 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15235 do_vfp_nsyn_opcode (enc
[flavour
]);
15239 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15240 enum neon_cvt_mode mode
)
15245 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15246 D register operands. */
15247 if (flavour
== neon_cvt_flavour_s32_f64
15248 || flavour
== neon_cvt_flavour_u32_f64
)
15249 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15252 set_it_insn_type (OUTSIDE_IT_INSN
);
15256 case neon_cvt_flavour_s32_f64
:
15260 case neon_cvt_flavour_s32_f32
:
15264 case neon_cvt_flavour_u32_f64
:
15268 case neon_cvt_flavour_u32_f32
:
15273 first_error (_("invalid instruction shape"));
15279 case neon_cvt_mode_a
: rm
= 0; break;
15280 case neon_cvt_mode_n
: rm
= 1; break;
15281 case neon_cvt_mode_p
: rm
= 2; break;
15282 case neon_cvt_mode_m
: rm
= 3; break;
15283 default: first_error (_("invalid rounding mode")); return;
15286 NEON_ENCODE (FPV8
, inst
);
15287 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15288 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15289 inst
.instruction
|= sz
<< 8;
15290 inst
.instruction
|= op
<< 7;
15291 inst
.instruction
|= rm
<< 16;
15292 inst
.instruction
|= 0xf0000000;
15293 inst
.is_neon
= TRUE
;
15297 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15299 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15300 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15301 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15303 /* PR11109: Handle round-to-zero for VCVT conversions. */
15304 if (mode
== neon_cvt_mode_z
15305 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15306 && (flavour
== neon_cvt_flavour_s32_f32
15307 || flavour
== neon_cvt_flavour_u32_f32
15308 || flavour
== neon_cvt_flavour_s32_f64
15309 || flavour
== neon_cvt_flavour_u32_f64
)
15310 && (rs
== NS_FD
|| rs
== NS_FF
))
15312 do_vfp_nsyn_cvtz ();
15316 /* VFP rather than Neon conversions. */
15317 if (flavour
>= neon_cvt_flavour_first_fp
)
15319 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15320 do_vfp_nsyn_cvt (rs
, flavour
);
15322 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15333 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15335 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15338 /* Fixed-point conversion with #0 immediate is encoded as an
15339 integer conversion. */
15340 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15342 immbits
= 32 - inst
.operands
[2].imm
;
15343 NEON_ENCODE (IMMED
, inst
);
15344 if (flavour
!= neon_cvt_flavour_invalid
)
15345 inst
.instruction
|= enctab
[flavour
];
15346 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15347 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15348 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15349 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15350 inst
.instruction
|= neon_quad (rs
) << 6;
15351 inst
.instruction
|= 1 << 21;
15352 inst
.instruction
|= immbits
<< 16;
15354 neon_dp_fixup (&inst
);
15360 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15362 NEON_ENCODE (FLOAT
, inst
);
15363 set_it_insn_type (OUTSIDE_IT_INSN
);
15365 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15368 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15369 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15370 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15371 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15372 inst
.instruction
|= neon_quad (rs
) << 6;
15373 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15374 inst
.instruction
|= mode
<< 8;
15376 inst
.instruction
|= 0xfc000000;
15378 inst
.instruction
|= 0xf0000000;
15384 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15386 NEON_ENCODE (INTEGER
, inst
);
15388 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15391 if (flavour
!= neon_cvt_flavour_invalid
)
15392 inst
.instruction
|= enctab
[flavour
];
15394 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15395 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15396 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15397 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15398 inst
.instruction
|= neon_quad (rs
) << 6;
15399 inst
.instruction
|= 2 << 18;
15401 neon_dp_fixup (&inst
);
15406 /* Half-precision conversions for Advanced SIMD -- neon. */
15411 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15413 as_bad (_("operand size must match register width"));
15418 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15420 as_bad (_("operand size must match register width"));
15425 inst
.instruction
= 0x3b60600;
15427 inst
.instruction
= 0x3b60700;
15429 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15430 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15431 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15432 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15433 neon_dp_fixup (&inst
);
15437 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15438 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15439 do_vfp_nsyn_cvt (rs
, flavour
);
15441 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15446 do_neon_cvtr (void)
15448 do_neon_cvt_1 (neon_cvt_mode_x
);
15454 do_neon_cvt_1 (neon_cvt_mode_z
);
15458 do_neon_cvta (void)
15460 do_neon_cvt_1 (neon_cvt_mode_a
);
15464 do_neon_cvtn (void)
15466 do_neon_cvt_1 (neon_cvt_mode_n
);
15470 do_neon_cvtp (void)
15472 do_neon_cvt_1 (neon_cvt_mode_p
);
15476 do_neon_cvtm (void)
15478 do_neon_cvt_1 (neon_cvt_mode_m
);
15482 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15485 mark_feature_used (&fpu_vfp_ext_armv8
);
15487 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15488 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15489 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15490 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15491 inst
.instruction
|= to
? 0x10000 : 0;
15492 inst
.instruction
|= t
? 0x80 : 0;
15493 inst
.instruction
|= is_double
? 0x100 : 0;
15494 do_vfp_cond_or_thumb ();
15498 do_neon_cvttb_1 (bfd_boolean t
)
15500 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15504 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15507 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15509 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15512 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15514 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15516 /* The VCVTB and VCVTT instructions with D-register operands
15517 don't work for SP only targets. */
15518 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15522 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15524 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15526 /* The VCVTB and VCVTT instructions with D-register operands
15527 don't work for SP only targets. */
15528 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15532 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15539 do_neon_cvtb (void)
15541 do_neon_cvttb_1 (FALSE
);
15546 do_neon_cvtt (void)
15548 do_neon_cvttb_1 (TRUE
);
15552 neon_move_immediate (void)
15554 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15555 struct neon_type_el et
= neon_check_type (2, rs
,
15556 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15557 unsigned immlo
, immhi
= 0, immbits
;
15558 int op
, cmode
, float_p
;
15560 constraint (et
.type
== NT_invtype
,
15561 _("operand size must be specified for immediate VMOV"));
15563 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15564 op
= (inst
.instruction
& (1 << 5)) != 0;
15566 immlo
= inst
.operands
[1].imm
;
15567 if (inst
.operands
[1].regisimm
)
15568 immhi
= inst
.operands
[1].reg
;
15570 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15571 _("immediate has bits set outside the operand size"));
15573 float_p
= inst
.operands
[1].immisfloat
;
15575 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15576 et
.size
, et
.type
)) == FAIL
)
15578 /* Invert relevant bits only. */
15579 neon_invert_size (&immlo
, &immhi
, et
.size
);
15580 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15581 with one or the other; those cases are caught by
15582 neon_cmode_for_move_imm. */
15584 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15585 &op
, et
.size
, et
.type
)) == FAIL
)
15587 first_error (_("immediate out of range"));
15592 inst
.instruction
&= ~(1 << 5);
15593 inst
.instruction
|= op
<< 5;
15595 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15596 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15597 inst
.instruction
|= neon_quad (rs
) << 6;
15598 inst
.instruction
|= cmode
<< 8;
15600 neon_write_immbits (immbits
);
15606 if (inst
.operands
[1].isreg
)
15608 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15610 NEON_ENCODE (INTEGER
, inst
);
15611 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15612 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15613 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15614 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15615 inst
.instruction
|= neon_quad (rs
) << 6;
15619 NEON_ENCODE (IMMED
, inst
);
15620 neon_move_immediate ();
15623 neon_dp_fixup (&inst
);
15626 /* Encode instructions of form:
15628 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15629 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15632 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15634 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15635 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15636 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15637 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15638 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15639 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15640 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15641 inst
.instruction
|= neon_logbits (size
) << 20;
15643 neon_dp_fixup (&inst
);
15647 do_neon_dyadic_long (void)
15649 /* FIXME: Type checking for lengthening op. */
15650 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15651 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15652 neon_mixed_length (et
, et
.size
);
15656 do_neon_abal (void)
15658 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15659 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15660 neon_mixed_length (et
, et
.size
);
15664 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15666 if (inst
.operands
[2].isscalar
)
15668 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15669 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15670 NEON_ENCODE (SCALAR
, inst
);
15671 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15675 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15676 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15677 NEON_ENCODE (INTEGER
, inst
);
15678 neon_mixed_length (et
, et
.size
);
15683 do_neon_mac_maybe_scalar_long (void)
15685 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15689 do_neon_dyadic_wide (void)
15691 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15692 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15693 neon_mixed_length (et
, et
.size
);
15697 do_neon_dyadic_narrow (void)
15699 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15700 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15701 /* Operand sign is unimportant, and the U bit is part of the opcode,
15702 so force the operand type to integer. */
15703 et
.type
= NT_integer
;
15704 neon_mixed_length (et
, et
.size
/ 2);
15708 do_neon_mul_sat_scalar_long (void)
15710 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15714 do_neon_vmull (void)
15716 if (inst
.operands
[2].isscalar
)
15717 do_neon_mac_maybe_scalar_long ();
15720 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15721 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15723 if (et
.type
== NT_poly
)
15724 NEON_ENCODE (POLY
, inst
);
15726 NEON_ENCODE (INTEGER
, inst
);
15728 /* For polynomial encoding the U bit must be zero, and the size must
15729 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15730 obviously, as 0b10). */
15733 /* Check we're on the correct architecture. */
15734 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15736 _("Instruction form not available on this architecture.");
15741 neon_mixed_length (et
, et
.size
);
15748 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15749 struct neon_type_el et
= neon_check_type (3, rs
,
15750 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15751 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15753 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15754 _("shift out of range"));
15755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15757 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15758 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15759 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15760 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15761 inst
.instruction
|= neon_quad (rs
) << 6;
15762 inst
.instruction
|= imm
<< 8;
15764 neon_dp_fixup (&inst
);
15770 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15771 struct neon_type_el et
= neon_check_type (2, rs
,
15772 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15773 unsigned op
= (inst
.instruction
>> 7) & 3;
15774 /* N (width of reversed regions) is encoded as part of the bitmask. We
15775 extract it here to check the elements to be reversed are smaller.
15776 Otherwise we'd get a reserved instruction. */
15777 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15778 gas_assert (elsize
!= 0);
15779 constraint (et
.size
>= elsize
,
15780 _("elements must be smaller than reversal region"));
15781 neon_two_same (neon_quad (rs
), 1, et
.size
);
15787 if (inst
.operands
[1].isscalar
)
15789 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15790 struct neon_type_el et
= neon_check_type (2, rs
,
15791 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15792 unsigned sizebits
= et
.size
>> 3;
15793 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15794 int logsize
= neon_logbits (et
.size
);
15795 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15797 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15800 NEON_ENCODE (SCALAR
, inst
);
15801 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15802 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15803 inst
.instruction
|= LOW4 (dm
);
15804 inst
.instruction
|= HI1 (dm
) << 5;
15805 inst
.instruction
|= neon_quad (rs
) << 6;
15806 inst
.instruction
|= x
<< 17;
15807 inst
.instruction
|= sizebits
<< 16;
15809 neon_dp_fixup (&inst
);
15813 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15814 struct neon_type_el et
= neon_check_type (2, rs
,
15815 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15816 /* Duplicate ARM register to lanes of vector. */
15817 NEON_ENCODE (ARMREG
, inst
);
15820 case 8: inst
.instruction
|= 0x400000; break;
15821 case 16: inst
.instruction
|= 0x000020; break;
15822 case 32: inst
.instruction
|= 0x000000; break;
15825 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15826 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15827 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15828 inst
.instruction
|= neon_quad (rs
) << 21;
15829 /* The encoding for this instruction is identical for the ARM and Thumb
15830 variants, except for the condition field. */
15831 do_vfp_cond_or_thumb ();
15835 /* VMOV has particularly many variations. It can be one of:
15836 0. VMOV<c><q> <Qd>, <Qm>
15837 1. VMOV<c><q> <Dd>, <Dm>
15838 (Register operations, which are VORR with Rm = Rn.)
15839 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15840 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15842 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15843 (ARM register to scalar.)
15844 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15845 (Two ARM registers to vector.)
15846 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15847 (Scalar to ARM register.)
15848 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15849 (Vector to two ARM registers.)
15850 8. VMOV.F32 <Sd>, <Sm>
15851 9. VMOV.F64 <Dd>, <Dm>
15852 (VFP register moves.)
15853 10. VMOV.F32 <Sd>, #imm
15854 11. VMOV.F64 <Dd>, #imm
15855 (VFP float immediate load.)
15856 12. VMOV <Rd>, <Sm>
15857 (VFP single to ARM reg.)
15858 13. VMOV <Sd>, <Rm>
15859 (ARM reg to VFP single.)
15860 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15861 (Two ARM regs to two VFP singles.)
15862 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15863 (Two VFP singles to two ARM regs.)
15865 These cases can be disambiguated using neon_select_shape, except cases 1/9
15866 and 3/11 which depend on the operand type too.
15868 All the encoded bits are hardcoded by this function.
15870 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15871 Cases 5, 7 may be used with VFPv2 and above.
15873 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15874 can specify a type where it doesn't make sense to, and is ignored). */
15879 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15880 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15882 struct neon_type_el et
;
15883 const char *ldconst
= 0;
15887 case NS_DD
: /* case 1/9. */
15888 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15889 /* It is not an error here if no type is given. */
15891 if (et
.type
== NT_float
&& et
.size
== 64)
15893 do_vfp_nsyn_opcode ("fcpyd");
15896 /* fall through. */
15898 case NS_QQ
: /* case 0/1. */
15900 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15902 /* The architecture manual I have doesn't explicitly state which
15903 value the U bit should have for register->register moves, but
15904 the equivalent VORR instruction has U = 0, so do that. */
15905 inst
.instruction
= 0x0200110;
15906 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15907 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15908 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15909 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15910 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15911 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15912 inst
.instruction
|= neon_quad (rs
) << 6;
15914 neon_dp_fixup (&inst
);
15918 case NS_DI
: /* case 3/11. */
15919 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15921 if (et
.type
== NT_float
&& et
.size
== 64)
15923 /* case 11 (fconstd). */
15924 ldconst
= "fconstd";
15925 goto encode_fconstd
;
15927 /* fall through. */
15929 case NS_QI
: /* case 2/3. */
15930 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15932 inst
.instruction
= 0x0800010;
15933 neon_move_immediate ();
15934 neon_dp_fixup (&inst
);
15937 case NS_SR
: /* case 4. */
15939 unsigned bcdebits
= 0;
15941 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15942 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15944 /* .<size> is optional here, defaulting to .32. */
15945 if (inst
.vectype
.elems
== 0
15946 && inst
.operands
[0].vectype
.type
== NT_invtype
15947 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15949 inst
.vectype
.el
[0].type
= NT_untyped
;
15950 inst
.vectype
.el
[0].size
= 32;
15951 inst
.vectype
.elems
= 1;
15954 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15955 logsize
= neon_logbits (et
.size
);
15957 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15960 && et
.size
!= 32, _(BAD_FPU
));
15961 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15962 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15966 case 8: bcdebits
= 0x8; break;
15967 case 16: bcdebits
= 0x1; break;
15968 case 32: bcdebits
= 0x0; break;
15972 bcdebits
|= x
<< logsize
;
15974 inst
.instruction
= 0xe000b10;
15975 do_vfp_cond_or_thumb ();
15976 inst
.instruction
|= LOW4 (dn
) << 16;
15977 inst
.instruction
|= HI1 (dn
) << 7;
15978 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15979 inst
.instruction
|= (bcdebits
& 3) << 5;
15980 inst
.instruction
|= (bcdebits
>> 2) << 21;
15984 case NS_DRR
: /* case 5 (fmdrr). */
15985 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15988 inst
.instruction
= 0xc400b10;
15989 do_vfp_cond_or_thumb ();
15990 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15991 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15992 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15993 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15996 case NS_RS
: /* case 6. */
15999 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16000 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16001 unsigned abcdebits
= 0;
16003 /* .<dt> is optional here, defaulting to .32. */
16004 if (inst
.vectype
.elems
== 0
16005 && inst
.operands
[0].vectype
.type
== NT_invtype
16006 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16008 inst
.vectype
.el
[0].type
= NT_untyped
;
16009 inst
.vectype
.el
[0].size
= 32;
16010 inst
.vectype
.elems
= 1;
16013 et
= neon_check_type (2, NS_NULL
,
16014 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16015 logsize
= neon_logbits (et
.size
);
16017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16020 && et
.size
!= 32, _(BAD_FPU
));
16021 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16022 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16026 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16027 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16028 case 32: abcdebits
= 0x00; break;
16032 abcdebits
|= x
<< logsize
;
16033 inst
.instruction
= 0xe100b10;
16034 do_vfp_cond_or_thumb ();
16035 inst
.instruction
|= LOW4 (dn
) << 16;
16036 inst
.instruction
|= HI1 (dn
) << 7;
16037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16038 inst
.instruction
|= (abcdebits
& 3) << 5;
16039 inst
.instruction
|= (abcdebits
>> 2) << 21;
16043 case NS_RRD
: /* case 7 (fmrrd). */
16044 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16047 inst
.instruction
= 0xc500b10;
16048 do_vfp_cond_or_thumb ();
16049 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16051 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16052 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16055 case NS_FF
: /* case 8 (fcpys). */
16056 do_vfp_nsyn_opcode ("fcpys");
16059 case NS_FI
: /* case 10 (fconsts). */
16060 ldconst
= "fconsts";
16062 if (is_quarter_float (inst
.operands
[1].imm
))
16064 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16065 do_vfp_nsyn_opcode (ldconst
);
16068 first_error (_("immediate out of range"));
16071 case NS_RF
: /* case 12 (fmrs). */
16072 do_vfp_nsyn_opcode ("fmrs");
16075 case NS_FR
: /* case 13 (fmsr). */
16076 do_vfp_nsyn_opcode ("fmsr");
16079 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16080 (one of which is a list), but we have parsed four. Do some fiddling to
16081 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16083 case NS_RRFF
: /* case 14 (fmrrs). */
16084 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16085 _("VFP registers must be adjacent"));
16086 inst
.operands
[2].imm
= 2;
16087 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16088 do_vfp_nsyn_opcode ("fmrrs");
16091 case NS_FFRR
: /* case 15 (fmsrr). */
16092 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16093 _("VFP registers must be adjacent"));
16094 inst
.operands
[1] = inst
.operands
[2];
16095 inst
.operands
[2] = inst
.operands
[3];
16096 inst
.operands
[0].imm
= 2;
16097 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16098 do_vfp_nsyn_opcode ("fmsrr");
16102 /* neon_select_shape has determined that the instruction
16103 shape is wrong and has already set the error message. */
16112 do_neon_rshift_round_imm (void)
16114 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16115 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16116 int imm
= inst
.operands
[2].imm
;
16118 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16121 inst
.operands
[2].present
= 0;
16126 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16127 _("immediate out of range for shift"));
16128 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16133 do_neon_movl (void)
16135 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16136 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16137 unsigned sizebits
= et
.size
>> 3;
16138 inst
.instruction
|= sizebits
<< 19;
16139 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16145 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16146 struct neon_type_el et
= neon_check_type (2, rs
,
16147 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16148 NEON_ENCODE (INTEGER
, inst
);
16149 neon_two_same (neon_quad (rs
), 1, et
.size
);
16153 do_neon_zip_uzp (void)
16155 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16156 struct neon_type_el et
= neon_check_type (2, rs
,
16157 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16158 if (rs
== NS_DD
&& et
.size
== 32)
16160 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16161 inst
.instruction
= N_MNEM_vtrn
;
16165 neon_two_same (neon_quad (rs
), 1, et
.size
);
16169 do_neon_sat_abs_neg (void)
16171 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16172 struct neon_type_el et
= neon_check_type (2, rs
,
16173 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16174 neon_two_same (neon_quad (rs
), 1, et
.size
);
16178 do_neon_pair_long (void)
16180 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16181 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16182 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16183 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16184 neon_two_same (neon_quad (rs
), 1, et
.size
);
16188 do_neon_recip_est (void)
16190 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16191 struct neon_type_el et
= neon_check_type (2, rs
,
16192 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16193 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16194 neon_two_same (neon_quad (rs
), 1, et
.size
);
16200 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16201 struct neon_type_el et
= neon_check_type (2, rs
,
16202 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16203 neon_two_same (neon_quad (rs
), 1, et
.size
);
16209 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16210 struct neon_type_el et
= neon_check_type (2, rs
,
16211 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16212 neon_two_same (neon_quad (rs
), 1, et
.size
);
16218 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16219 struct neon_type_el et
= neon_check_type (2, rs
,
16220 N_EQK
| N_INT
, N_8
| N_KEY
);
16221 neon_two_same (neon_quad (rs
), 1, et
.size
);
16227 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16228 neon_two_same (neon_quad (rs
), 1, -1);
16232 do_neon_tbl_tbx (void)
16234 unsigned listlenbits
;
16235 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16237 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16239 first_error (_("bad list length for table lookup"));
16243 listlenbits
= inst
.operands
[1].imm
- 1;
16244 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16246 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16247 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16248 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16249 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16250 inst
.instruction
|= listlenbits
<< 8;
16252 neon_dp_fixup (&inst
);
16256 do_neon_ldm_stm (void)
16258 /* P, U and L bits are part of bitmask. */
16259 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16260 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16262 if (inst
.operands
[1].issingle
)
16264 do_vfp_nsyn_ldm_stm (is_dbmode
);
16268 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16269 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16271 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16272 _("register list must contain at least 1 and at most 16 "
16275 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16276 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16277 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16278 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16280 inst
.instruction
|= offsetbits
;
16282 do_vfp_cond_or_thumb ();
16286 do_neon_ldr_str (void)
16288 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16290 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16291 And is UNPREDICTABLE in thumb mode. */
16293 && inst
.operands
[1].reg
== REG_PC
16294 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16297 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16298 else if (warn_on_deprecated
)
16299 as_tsktsk (_("Use of PC here is deprecated"));
16302 if (inst
.operands
[0].issingle
)
16305 do_vfp_nsyn_opcode ("flds");
16307 do_vfp_nsyn_opcode ("fsts");
16312 do_vfp_nsyn_opcode ("fldd");
16314 do_vfp_nsyn_opcode ("fstd");
16318 /* "interleave" version also handles non-interleaving register VLD1/VST1
16322 do_neon_ld_st_interleave (void)
16324 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16325 N_8
| N_16
| N_32
| N_64
);
16326 unsigned alignbits
= 0;
16328 /* The bits in this table go:
16329 0: register stride of one (0) or two (1)
16330 1,2: register list length, minus one (1, 2, 3, 4).
16331 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16332 We use -1 for invalid entries. */
16333 const int typetable
[] =
16335 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16336 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16337 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16338 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16342 if (et
.type
== NT_invtype
)
16345 if (inst
.operands
[1].immisalign
)
16346 switch (inst
.operands
[1].imm
>> 8)
16348 case 64: alignbits
= 1; break;
16350 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16351 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16352 goto bad_alignment
;
16356 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16357 goto bad_alignment
;
16362 first_error (_("bad alignment"));
16366 inst
.instruction
|= alignbits
<< 4;
16367 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16369 /* Bits [4:6] of the immediate in a list specifier encode register stride
16370 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16371 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16372 up the right value for "type" in a table based on this value and the given
16373 list style, then stick it back. */
16374 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16375 | (((inst
.instruction
>> 8) & 3) << 3);
16377 typebits
= typetable
[idx
];
16379 constraint (typebits
== -1, _("bad list type for instruction"));
16380 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16381 _("bad element type for instruction"));
16383 inst
.instruction
&= ~0xf00;
16384 inst
.instruction
|= typebits
<< 8;
16387 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16388 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16389 otherwise. The variable arguments are a list of pairs of legal (size, align)
16390 values, terminated with -1. */
16393 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16396 int result
= FAIL
, thissize
, thisalign
;
16398 if (!inst
.operands
[1].immisalign
)
16404 va_start (ap
, do_align
);
16408 thissize
= va_arg (ap
, int);
16409 if (thissize
== -1)
16411 thisalign
= va_arg (ap
, int);
16413 if (size
== thissize
&& align
== thisalign
)
16416 while (result
!= SUCCESS
);
16420 if (result
== SUCCESS
)
16423 first_error (_("unsupported alignment for instruction"));
16429 do_neon_ld_st_lane (void)
16431 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16432 int align_good
, do_align
= 0;
16433 int logsize
= neon_logbits (et
.size
);
16434 int align
= inst
.operands
[1].imm
>> 8;
16435 int n
= (inst
.instruction
>> 8) & 3;
16436 int max_el
= 64 / et
.size
;
16438 if (et
.type
== NT_invtype
)
16441 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16442 _("bad list length"));
16443 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16444 _("scalar index out of range"));
16445 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16447 _("stride of 2 unavailable when element size is 8"));
16451 case 0: /* VLD1 / VST1. */
16452 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16454 if (align_good
== FAIL
)
16458 unsigned alignbits
= 0;
16461 case 16: alignbits
= 0x1; break;
16462 case 32: alignbits
= 0x3; break;
16465 inst
.instruction
|= alignbits
<< 4;
16469 case 1: /* VLD2 / VST2. */
16470 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16472 if (align_good
== FAIL
)
16475 inst
.instruction
|= 1 << 4;
16478 case 2: /* VLD3 / VST3. */
16479 constraint (inst
.operands
[1].immisalign
,
16480 _("can't use alignment with this instruction"));
16483 case 3: /* VLD4 / VST4. */
16484 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16485 16, 64, 32, 64, 32, 128, -1);
16486 if (align_good
== FAIL
)
16490 unsigned alignbits
= 0;
16493 case 8: alignbits
= 0x1; break;
16494 case 16: alignbits
= 0x1; break;
16495 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16498 inst
.instruction
|= alignbits
<< 4;
16505 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16506 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16507 inst
.instruction
|= 1 << (4 + logsize
);
16509 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16510 inst
.instruction
|= logsize
<< 10;
16513 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16516 do_neon_ld_dup (void)
16518 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16519 int align_good
, do_align
= 0;
16521 if (et
.type
== NT_invtype
)
16524 switch ((inst
.instruction
>> 8) & 3)
16526 case 0: /* VLD1. */
16527 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16528 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16529 &do_align
, 16, 16, 32, 32, -1);
16530 if (align_good
== FAIL
)
16532 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16535 case 2: inst
.instruction
|= 1 << 5; break;
16536 default: first_error (_("bad list length")); return;
16538 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16541 case 1: /* VLD2. */
16542 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16543 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16544 if (align_good
== FAIL
)
16546 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16547 _("bad list length"));
16548 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16549 inst
.instruction
|= 1 << 5;
16550 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16553 case 2: /* VLD3. */
16554 constraint (inst
.operands
[1].immisalign
,
16555 _("can't use alignment with this instruction"));
16556 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16557 _("bad list length"));
16558 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16559 inst
.instruction
|= 1 << 5;
16560 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16563 case 3: /* VLD4. */
16565 int align
= inst
.operands
[1].imm
>> 8;
16566 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16567 16, 64, 32, 64, 32, 128, -1);
16568 if (align_good
== FAIL
)
16570 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16571 _("bad list length"));
16572 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16573 inst
.instruction
|= 1 << 5;
16574 if (et
.size
== 32 && align
== 128)
16575 inst
.instruction
|= 0x3 << 6;
16577 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16584 inst
.instruction
|= do_align
<< 4;
16587 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16588 apart from bits [11:4]. */
16591 do_neon_ldx_stx (void)
16593 if (inst
.operands
[1].isreg
)
16594 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16596 switch (NEON_LANE (inst
.operands
[0].imm
))
16598 case NEON_INTERLEAVE_LANES
:
16599 NEON_ENCODE (INTERLV
, inst
);
16600 do_neon_ld_st_interleave ();
16603 case NEON_ALL_LANES
:
16604 NEON_ENCODE (DUP
, inst
);
16605 if (inst
.instruction
== N_INV
)
16607 first_error ("only loads support such operands");
16614 NEON_ENCODE (LANE
, inst
);
16615 do_neon_ld_st_lane ();
16618 /* L bit comes from bit mask. */
16619 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16620 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16621 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16623 if (inst
.operands
[1].postind
)
16625 int postreg
= inst
.operands
[1].imm
& 0xf;
16626 constraint (!inst
.operands
[1].immisreg
,
16627 _("post-index must be a register"));
16628 constraint (postreg
== 0xd || postreg
== 0xf,
16629 _("bad register for post-index"));
16630 inst
.instruction
|= postreg
;
16634 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16635 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16636 || inst
.reloc
.exp
.X_add_number
!= 0,
16639 if (inst
.operands
[1].writeback
)
16641 inst
.instruction
|= 0xd;
16644 inst
.instruction
|= 0xf;
16648 inst
.instruction
|= 0xf9000000;
16650 inst
.instruction
|= 0xf4000000;
16655 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16657 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16658 D register operands. */
16659 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16660 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16663 NEON_ENCODE (FPV8
, inst
);
16666 do_vfp_sp_dyadic ();
16668 do_vfp_dp_rd_rn_rm ();
16671 inst
.instruction
|= 0x100;
16673 inst
.instruction
|= 0xf0000000;
16679 set_it_insn_type (OUTSIDE_IT_INSN
);
16681 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16682 first_error (_("invalid instruction shape"));
16688 set_it_insn_type (OUTSIDE_IT_INSN
);
16690 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16693 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16696 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16700 do_vrint_1 (enum neon_cvt_mode mode
)
16702 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16703 struct neon_type_el et
;
16708 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16709 D register operands. */
16710 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16711 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16714 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16715 if (et
.type
!= NT_invtype
)
16717 /* VFP encodings. */
16718 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16719 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16720 set_it_insn_type (OUTSIDE_IT_INSN
);
16722 NEON_ENCODE (FPV8
, inst
);
16724 do_vfp_sp_monadic ();
16726 do_vfp_dp_rd_rm ();
16730 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16731 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16732 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16733 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16734 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16735 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16736 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16740 inst
.instruction
|= (rs
== NS_DD
) << 8;
16741 do_vfp_cond_or_thumb ();
16745 /* Neon encodings (or something broken...). */
16747 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16749 if (et
.type
== NT_invtype
)
16752 set_it_insn_type (OUTSIDE_IT_INSN
);
16753 NEON_ENCODE (FLOAT
, inst
);
16755 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16758 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16759 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16760 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16761 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16762 inst
.instruction
|= neon_quad (rs
) << 6;
16765 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16766 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16767 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16768 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16769 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16770 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16771 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16776 inst
.instruction
|= 0xfc000000;
16778 inst
.instruction
|= 0xf0000000;
16785 do_vrint_1 (neon_cvt_mode_x
);
16791 do_vrint_1 (neon_cvt_mode_z
);
16797 do_vrint_1 (neon_cvt_mode_r
);
16803 do_vrint_1 (neon_cvt_mode_a
);
16809 do_vrint_1 (neon_cvt_mode_n
);
16815 do_vrint_1 (neon_cvt_mode_p
);
16821 do_vrint_1 (neon_cvt_mode_m
);
16824 /* Crypto v1 instructions. */
16826 do_crypto_2op_1 (unsigned elttype
, int op
)
16828 set_it_insn_type (OUTSIDE_IT_INSN
);
16830 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16836 NEON_ENCODE (INTEGER
, inst
);
16837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16842 inst
.instruction
|= op
<< 6;
16845 inst
.instruction
|= 0xfc000000;
16847 inst
.instruction
|= 0xf0000000;
16851 do_crypto_3op_1 (int u
, int op
)
16853 set_it_insn_type (OUTSIDE_IT_INSN
);
16855 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16856 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16861 NEON_ENCODE (INTEGER
, inst
);
16862 neon_three_same (1, u
, 8 << op
);
16868 do_crypto_2op_1 (N_8
, 0);
16874 do_crypto_2op_1 (N_8
, 1);
16880 do_crypto_2op_1 (N_8
, 2);
16886 do_crypto_2op_1 (N_8
, 3);
16892 do_crypto_3op_1 (0, 0);
16898 do_crypto_3op_1 (0, 1);
16904 do_crypto_3op_1 (0, 2);
16910 do_crypto_3op_1 (0, 3);
16916 do_crypto_3op_1 (1, 0);
16922 do_crypto_3op_1 (1, 1);
16926 do_sha256su1 (void)
16928 do_crypto_3op_1 (1, 2);
16934 do_crypto_2op_1 (N_32
, -1);
16940 do_crypto_2op_1 (N_32
, 0);
16944 do_sha256su0 (void)
16946 do_crypto_2op_1 (N_32
, 1);
16950 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16952 unsigned int Rd
= inst
.operands
[0].reg
;
16953 unsigned int Rn
= inst
.operands
[1].reg
;
16954 unsigned int Rm
= inst
.operands
[2].reg
;
16956 set_it_insn_type (OUTSIDE_IT_INSN
);
16957 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16958 inst
.instruction
|= LOW4 (Rn
) << 16;
16959 inst
.instruction
|= LOW4 (Rm
);
16960 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16961 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16963 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16964 as_warn (UNPRED_REG ("r15"));
16965 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16966 as_warn (UNPRED_REG ("r13"));
17006 /* Overall per-instruction processing. */
17008 /* We need to be able to fix up arbitrary expressions in some statements.
17009 This is so that we can handle symbols that are an arbitrary distance from
17010 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17011 which returns part of an address in a form which will be valid for
17012 a data instruction. We do this by pushing the expression into a symbol
17013 in the expr_section, and creating a fix for that. */
17016 fix_new_arm (fragS
* frag
,
17030 /* Create an absolute valued symbol, so we have something to
17031 refer to in the object file. Unfortunately for us, gas's
17032 generic expression parsing will already have folded out
17033 any use of .set foo/.type foo %function that may have
17034 been used to set type information of the target location,
17035 that's being specified symbolically. We have to presume
17036 the user knows what they are doing. */
17040 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17042 symbol
= symbol_find_or_make (name
);
17043 S_SET_SEGMENT (symbol
, absolute_section
);
17044 symbol_set_frag (symbol
, &zero_address_frag
);
17045 S_SET_VALUE (symbol
, exp
->X_add_number
);
17046 exp
->X_op
= O_symbol
;
17047 exp
->X_add_symbol
= symbol
;
17048 exp
->X_add_number
= 0;
17054 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17055 (enum bfd_reloc_code_real
) reloc
);
17059 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17060 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17064 /* Mark whether the fix is to a THUMB instruction, or an ARM
17066 new_fix
->tc_fix_data
= thumb_mode
;
17069 /* Create a frg for an instruction requiring relaxation. */
17071 output_relax_insn (void)
17077 /* The size of the instruction is unknown, so tie the debug info to the
17078 start of the instruction. */
17079 dwarf2_emit_insn (0);
17081 switch (inst
.reloc
.exp
.X_op
)
17084 sym
= inst
.reloc
.exp
.X_add_symbol
;
17085 offset
= inst
.reloc
.exp
.X_add_number
;
17089 offset
= inst
.reloc
.exp
.X_add_number
;
17092 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17096 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17097 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17098 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17101 /* Write a 32-bit thumb instruction to buf. */
17103 put_thumb32_insn (char * buf
, unsigned long insn
)
17105 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17106 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17110 output_inst (const char * str
)
17116 as_bad ("%s -- `%s'", inst
.error
, str
);
17121 output_relax_insn ();
17124 if (inst
.size
== 0)
17127 to
= frag_more (inst
.size
);
17128 /* PR 9814: Record the thumb mode into the current frag so that we know
17129 what type of NOP padding to use, if necessary. We override any previous
17130 setting so that if the mode has changed then the NOPS that we use will
17131 match the encoding of the last instruction in the frag. */
17132 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17134 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17136 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17137 put_thumb32_insn (to
, inst
.instruction
);
17139 else if (inst
.size
> INSN_SIZE
)
17141 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17142 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17143 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17146 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17148 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17149 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17150 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17153 dwarf2_emit_insn (inst
.size
);
17157 output_it_inst (int cond
, int mask
, char * to
)
17159 unsigned long instruction
= 0xbf00;
17162 instruction
|= mask
;
17163 instruction
|= cond
<< 4;
17167 to
= frag_more (2);
17169 dwarf2_emit_insn (2);
17173 md_number_to_chars (to
, instruction
, 2);
17178 /* Tag values used in struct asm_opcode's tag field. */
17181 OT_unconditional
, /* Instruction cannot be conditionalized.
17182 The ARM condition field is still 0xE. */
17183 OT_unconditionalF
, /* Instruction cannot be conditionalized
17184 and carries 0xF in its ARM condition field. */
17185 OT_csuffix
, /* Instruction takes a conditional suffix. */
17186 OT_csuffixF
, /* Some forms of the instruction take a conditional
17187 suffix, others place 0xF where the condition field
17189 OT_cinfix3
, /* Instruction takes a conditional infix,
17190 beginning at character index 3. (In
17191 unified mode, it becomes a suffix.) */
17192 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17193 tsts, cmps, cmns, and teqs. */
17194 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17195 character index 3, even in unified mode. Used for
17196 legacy instructions where suffix and infix forms
17197 may be ambiguous. */
17198 OT_csuf_or_in3
, /* Instruction takes either a conditional
17199 suffix or an infix at character index 3. */
17200 OT_odd_infix_unc
, /* This is the unconditional variant of an
17201 instruction that takes a conditional infix
17202 at an unusual position. In unified mode,
17203 this variant will accept a suffix. */
17204 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17205 are the conditional variants of instructions that
17206 take conditional infixes in unusual positions.
17207 The infix appears at character index
17208 (tag - OT_odd_infix_0). These are not accepted
17209 in unified mode. */
17212 /* Subroutine of md_assemble, responsible for looking up the primary
17213 opcode from the mnemonic the user wrote. STR points to the
17214 beginning of the mnemonic.
17216 This is not simply a hash table lookup, because of conditional
17217 variants. Most instructions have conditional variants, which are
17218 expressed with a _conditional affix_ to the mnemonic. If we were
17219 to encode each conditional variant as a literal string in the opcode
17220 table, it would have approximately 20,000 entries.
17222 Most mnemonics take this affix as a suffix, and in unified syntax,
17223 'most' is upgraded to 'all'. However, in the divided syntax, some
17224 instructions take the affix as an infix, notably the s-variants of
17225 the arithmetic instructions. Of those instructions, all but six
17226 have the infix appear after the third character of the mnemonic.
17228 Accordingly, the algorithm for looking up primary opcodes given
17231 1. Look up the identifier in the opcode table.
17232 If we find a match, go to step U.
17234 2. Look up the last two characters of the identifier in the
17235 conditions table. If we find a match, look up the first N-2
17236 characters of the identifier in the opcode table. If we
17237 find a match, go to step CE.
17239 3. Look up the fourth and fifth characters of the identifier in
17240 the conditions table. If we find a match, extract those
17241 characters from the identifier, and look up the remaining
17242 characters in the opcode table. If we find a match, go
17247 U. Examine the tag field of the opcode structure, in case this is
17248 one of the six instructions with its conditional infix in an
17249 unusual place. If it is, the tag tells us where to find the
17250 infix; look it up in the conditions table and set inst.cond
17251 accordingly. Otherwise, this is an unconditional instruction.
17252 Again set inst.cond accordingly. Return the opcode structure.
17254 CE. Examine the tag field to make sure this is an instruction that
17255 should receive a conditional suffix. If it is not, fail.
17256 Otherwise, set inst.cond from the suffix we already looked up,
17257 and return the opcode structure.
17259 CM. Examine the tag field to make sure this is an instruction that
17260 should receive a conditional infix after the third character.
17261 If it is not, fail. Otherwise, undo the edits to the current
17262 line of input and proceed as for case CE. */
17264 static const struct asm_opcode
*
17265 opcode_lookup (char **str
)
17269 const struct asm_opcode
*opcode
;
17270 const struct asm_cond
*cond
;
17273 /* Scan up to the end of the mnemonic, which must end in white space,
17274 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17275 for (base
= end
= *str
; *end
!= '\0'; end
++)
17276 if (*end
== ' ' || *end
== '.')
17282 /* Handle a possible width suffix and/or Neon type suffix. */
17287 /* The .w and .n suffixes are only valid if the unified syntax is in
17289 if (unified_syntax
&& end
[1] == 'w')
17291 else if (unified_syntax
&& end
[1] == 'n')
17296 inst
.vectype
.elems
= 0;
17298 *str
= end
+ offset
;
17300 if (end
[offset
] == '.')
17302 /* See if we have a Neon type suffix (possible in either unified or
17303 non-unified ARM syntax mode). */
17304 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17307 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17313 /* Look for unaffixed or special-case affixed mnemonic. */
17314 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17319 if (opcode
->tag
< OT_odd_infix_0
)
17321 inst
.cond
= COND_ALWAYS
;
17325 if (warn_on_deprecated
&& unified_syntax
)
17326 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17327 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17328 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17331 inst
.cond
= cond
->value
;
17335 /* Cannot have a conditional suffix on a mnemonic of less than two
17337 if (end
- base
< 3)
17340 /* Look for suffixed mnemonic. */
17342 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17343 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17345 if (opcode
&& cond
)
17348 switch (opcode
->tag
)
17350 case OT_cinfix3_legacy
:
17351 /* Ignore conditional suffixes matched on infix only mnemonics. */
17355 case OT_cinfix3_deprecated
:
17356 case OT_odd_infix_unc
:
17357 if (!unified_syntax
)
17359 /* else fall through */
17363 case OT_csuf_or_in3
:
17364 inst
.cond
= cond
->value
;
17367 case OT_unconditional
:
17368 case OT_unconditionalF
:
17370 inst
.cond
= cond
->value
;
17373 /* Delayed diagnostic. */
17374 inst
.error
= BAD_COND
;
17375 inst
.cond
= COND_ALWAYS
;
17384 /* Cannot have a usual-position infix on a mnemonic of less than
17385 six characters (five would be a suffix). */
17386 if (end
- base
< 6)
17389 /* Look for infixed mnemonic in the usual position. */
17391 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17395 memcpy (save
, affix
, 2);
17396 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17397 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17399 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17400 memcpy (affix
, save
, 2);
17403 && (opcode
->tag
== OT_cinfix3
17404 || opcode
->tag
== OT_cinfix3_deprecated
17405 || opcode
->tag
== OT_csuf_or_in3
17406 || opcode
->tag
== OT_cinfix3_legacy
))
17409 if (warn_on_deprecated
&& unified_syntax
17410 && (opcode
->tag
== OT_cinfix3
17411 || opcode
->tag
== OT_cinfix3_deprecated
))
17412 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17414 inst
.cond
= cond
->value
;
17421 /* This function generates an initial IT instruction, leaving its block
17422 virtually open for the new instructions. Eventually,
17423 the mask will be updated by now_it_add_mask () each time
17424 a new instruction needs to be included in the IT block.
17425 Finally, the block is closed with close_automatic_it_block ().
17426 The block closure can be requested either from md_assemble (),
17427 a tencode (), or due to a label hook. */
17430 new_automatic_it_block (int cond
)
17432 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17433 now_it
.mask
= 0x18;
17435 now_it
.block_length
= 1;
17436 mapping_state (MAP_THUMB
);
17437 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17438 now_it
.warn_deprecated
= FALSE
;
17439 now_it
.insn_cond
= TRUE
;
17442 /* Close an automatic IT block.
17443 See comments in new_automatic_it_block (). */
17446 close_automatic_it_block (void)
17448 now_it
.mask
= 0x10;
17449 now_it
.block_length
= 0;
17452 /* Update the mask of the current automatically-generated IT
17453 instruction. See comments in new_automatic_it_block (). */
17456 now_it_add_mask (int cond
)
17458 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17459 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17460 | ((bitvalue) << (nbit)))
17461 const int resulting_bit
= (cond
& 1);
17463 now_it
.mask
&= 0xf;
17464 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17466 (5 - now_it
.block_length
));
17467 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17469 ((5 - now_it
.block_length
) - 1) );
17470 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17473 #undef SET_BIT_VALUE
17476 /* The IT blocks handling machinery is accessed through the these functions:
17477 it_fsm_pre_encode () from md_assemble ()
17478 set_it_insn_type () optional, from the tencode functions
17479 set_it_insn_type_last () ditto
17480 in_it_block () ditto
17481 it_fsm_post_encode () from md_assemble ()
17482 force_automatic_it_block_close () from label habdling functions
17485 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17486 initializing the IT insn type with a generic initial value depending
17487 on the inst.condition.
17488 2) During the tencode function, two things may happen:
17489 a) The tencode function overrides the IT insn type by
17490 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17491 b) The tencode function queries the IT block state by
17492 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17494 Both set_it_insn_type and in_it_block run the internal FSM state
17495 handling function (handle_it_state), because: a) setting the IT insn
17496 type may incur in an invalid state (exiting the function),
17497 and b) querying the state requires the FSM to be updated.
17498 Specifically we want to avoid creating an IT block for conditional
17499 branches, so it_fsm_pre_encode is actually a guess and we can't
17500 determine whether an IT block is required until the tencode () routine
17501 has decided what type of instruction this actually it.
17502 Because of this, if set_it_insn_type and in_it_block have to be used,
17503 set_it_insn_type has to be called first.
17505 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17506 determines the insn IT type depending on the inst.cond code.
17507 When a tencode () routine encodes an instruction that can be
17508 either outside an IT block, or, in the case of being inside, has to be
17509 the last one, set_it_insn_type_last () will determine the proper
17510 IT instruction type based on the inst.cond code. Otherwise,
17511 set_it_insn_type can be called for overriding that logic or
17512 for covering other cases.
17514 Calling handle_it_state () may not transition the IT block state to
17515 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17516 still queried. Instead, if the FSM determines that the state should
17517 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17518 after the tencode () function: that's what it_fsm_post_encode () does.
17520 Since in_it_block () calls the state handling function to get an
17521 updated state, an error may occur (due to invalid insns combination).
17522 In that case, inst.error is set.
17523 Therefore, inst.error has to be checked after the execution of
17524 the tencode () routine.
17526 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17527 any pending state change (if any) that didn't take place in
17528 handle_it_state () as explained above. */
17531 it_fsm_pre_encode (void)
17533 if (inst
.cond
!= COND_ALWAYS
)
17534 inst
.it_insn_type
= INSIDE_IT_INSN
;
17536 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17538 now_it
.state_handled
= 0;
17541 /* IT state FSM handling function. */
17544 handle_it_state (void)
17546 now_it
.state_handled
= 1;
17547 now_it
.insn_cond
= FALSE
;
17549 switch (now_it
.state
)
17551 case OUTSIDE_IT_BLOCK
:
17552 switch (inst
.it_insn_type
)
17554 case OUTSIDE_IT_INSN
:
17557 case INSIDE_IT_INSN
:
17558 case INSIDE_IT_LAST_INSN
:
17559 if (thumb_mode
== 0)
17562 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17563 as_tsktsk (_("Warning: conditional outside an IT block"\
17568 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17569 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17571 /* Automatically generate the IT instruction. */
17572 new_automatic_it_block (inst
.cond
);
17573 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17574 close_automatic_it_block ();
17578 inst
.error
= BAD_OUT_IT
;
17584 case IF_INSIDE_IT_LAST_INSN
:
17585 case NEUTRAL_IT_INSN
:
17589 now_it
.state
= MANUAL_IT_BLOCK
;
17590 now_it
.block_length
= 0;
17595 case AUTOMATIC_IT_BLOCK
:
17596 /* Three things may happen now:
17597 a) We should increment current it block size;
17598 b) We should close current it block (closing insn or 4 insns);
17599 c) We should close current it block and start a new one (due
17600 to incompatible conditions or
17601 4 insns-length block reached). */
17603 switch (inst
.it_insn_type
)
17605 case OUTSIDE_IT_INSN
:
17606 /* The closure of the block shall happen immediatelly,
17607 so any in_it_block () call reports the block as closed. */
17608 force_automatic_it_block_close ();
17611 case INSIDE_IT_INSN
:
17612 case INSIDE_IT_LAST_INSN
:
17613 case IF_INSIDE_IT_LAST_INSN
:
17614 now_it
.block_length
++;
17616 if (now_it
.block_length
> 4
17617 || !now_it_compatible (inst
.cond
))
17619 force_automatic_it_block_close ();
17620 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17621 new_automatic_it_block (inst
.cond
);
17625 now_it
.insn_cond
= TRUE
;
17626 now_it_add_mask (inst
.cond
);
17629 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17630 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17631 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17632 close_automatic_it_block ();
17635 case NEUTRAL_IT_INSN
:
17636 now_it
.block_length
++;
17637 now_it
.insn_cond
= TRUE
;
17639 if (now_it
.block_length
> 4)
17640 force_automatic_it_block_close ();
17642 now_it_add_mask (now_it
.cc
& 1);
17646 close_automatic_it_block ();
17647 now_it
.state
= MANUAL_IT_BLOCK
;
17652 case MANUAL_IT_BLOCK
:
17654 /* Check conditional suffixes. */
17655 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17658 now_it
.mask
&= 0x1f;
17659 is_last
= (now_it
.mask
== 0x10);
17660 now_it
.insn_cond
= TRUE
;
17662 switch (inst
.it_insn_type
)
17664 case OUTSIDE_IT_INSN
:
17665 inst
.error
= BAD_NOT_IT
;
17668 case INSIDE_IT_INSN
:
17669 if (cond
!= inst
.cond
)
17671 inst
.error
= BAD_IT_COND
;
17676 case INSIDE_IT_LAST_INSN
:
17677 case IF_INSIDE_IT_LAST_INSN
:
17678 if (cond
!= inst
.cond
)
17680 inst
.error
= BAD_IT_COND
;
17685 inst
.error
= BAD_BRANCH
;
17690 case NEUTRAL_IT_INSN
:
17691 /* The BKPT instruction is unconditional even in an IT block. */
17695 inst
.error
= BAD_IT_IT
;
17705 struct depr_insn_mask
17707 unsigned long pattern
;
17708 unsigned long mask
;
17709 const char* description
;
17712 /* List of 16-bit instruction patterns deprecated in an IT block in
17714 static const struct depr_insn_mask depr_it_insns
[] = {
17715 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17716 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17717 { 0xa000, 0xb800, N_("ADR") },
17718 { 0x4800, 0xf800, N_("Literal loads") },
17719 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17720 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17721 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17722 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17723 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17728 it_fsm_post_encode (void)
17732 if (!now_it
.state_handled
)
17733 handle_it_state ();
17735 if (now_it
.insn_cond
17736 && !now_it
.warn_deprecated
17737 && warn_on_deprecated
17738 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17740 if (inst
.instruction
>= 0x10000)
17742 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17743 "deprecated in ARMv8"));
17744 now_it
.warn_deprecated
= TRUE
;
17748 const struct depr_insn_mask
*p
= depr_it_insns
;
17750 while (p
->mask
!= 0)
17752 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17754 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17755 "of the following class are deprecated in ARMv8: "
17756 "%s"), p
->description
);
17757 now_it
.warn_deprecated
= TRUE
;
17765 if (now_it
.block_length
> 1)
17767 as_tsktsk (_("IT blocks containing more than one conditional "
17768 "instruction are deprecated in ARMv8"));
17769 now_it
.warn_deprecated
= TRUE
;
17773 is_last
= (now_it
.mask
== 0x10);
17776 now_it
.state
= OUTSIDE_IT_BLOCK
;
17782 force_automatic_it_block_close (void)
17784 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17786 close_automatic_it_block ();
17787 now_it
.state
= OUTSIDE_IT_BLOCK
;
17795 if (!now_it
.state_handled
)
17796 handle_it_state ();
17798 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17801 /* Whether OPCODE only has T32 encoding and makes build attribute
17802 Tag_THUMB_ISA_use be set to 1 if assembled without any cpu or arch info. */
17805 t1_isa_t32_only_insn (const struct asm_opcode
*opcode
)
17807 /* Original Thumb-1 wide instruction. */
17808 if (opcode
->tencode
== do_t_blx
17809 || opcode
->tencode
== do_t_branch23
17810 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17811 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
17818 md_assemble (char *str
)
17821 const struct asm_opcode
* opcode
;
17823 /* Align the previous label if needed. */
17824 if (last_label_seen
!= NULL
)
17826 symbol_set_frag (last_label_seen
, frag_now
);
17827 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17828 S_SET_SEGMENT (last_label_seen
, now_seg
);
17831 memset (&inst
, '\0', sizeof (inst
));
17832 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17834 opcode
= opcode_lookup (&p
);
17837 /* It wasn't an instruction, but it might be a register alias of
17838 the form alias .req reg, or a Neon .dn/.qn directive. */
17839 if (! create_register_alias (str
, p
)
17840 && ! create_neon_reg_alias (str
, p
))
17841 as_bad (_("bad instruction `%s'"), str
);
17846 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17847 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17849 /* The value which unconditional instructions should have in place of the
17850 condition field. */
17851 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17855 arm_feature_set variant
;
17857 variant
= cpu_variant
;
17858 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17859 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17860 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17861 /* Check that this instruction is supported for this CPU. */
17862 if (!opcode
->tvariant
17863 || (thumb_mode
== 1
17864 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17866 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
17869 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17870 && opcode
->tencode
!= do_t_branch
)
17872 as_bad (_("Thumb does not support conditional execution"));
17876 /* Two things are addressed here:
17877 1) Implicit require narrow instructions on Thumb-1.
17878 This avoids relaxation accidentally introducing Thumb-2
17880 2) Reject wide instructions in non Thumb-2 cores.
17882 Only instructions with narrow and wide variants need to be handled
17883 but selecting all non wide-only instructions is easier. */
17884 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
17885 && !t1_isa_t32_only_insn (opcode
))
17887 if (inst
.size_req
== 0)
17889 else if (inst
.size_req
== 4)
17891 as_bad (_("selected processor does not support `%s' in Thumb-2 "
17897 inst
.instruction
= opcode
->tvalue
;
17899 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17901 /* Prepare the it_insn_type for those encodings that don't set
17903 it_fsm_pre_encode ();
17905 opcode
->tencode ();
17907 it_fsm_post_encode ();
17910 if (!(inst
.error
|| inst
.relax
))
17912 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17913 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17914 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17916 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17921 /* Something has gone badly wrong if we try to relax a fixed size
17923 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17925 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17926 *opcode
->tvariant
);
17927 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17928 set those bits when Thumb-2 32-bit instructions are seen. The impact
17929 of relaxable instructions will be considered later after we finish all
17931 if (inst
.size
== 4 && !t1_isa_t32_only_insn (opcode
))
17932 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17935 check_neon_suffixes
;
17939 mapping_state (MAP_THUMB
);
17942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17946 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17947 is_bx
= (opcode
->aencode
== do_bx
);
17949 /* Check that this instruction is supported for this CPU. */
17950 if (!(is_bx
&& fix_v4bx
)
17951 && !(opcode
->avariant
&&
17952 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17954 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
17959 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17963 inst
.instruction
= opcode
->avalue
;
17964 if (opcode
->tag
== OT_unconditionalF
)
17965 inst
.instruction
|= 0xFU
<< 28;
17967 inst
.instruction
|= inst
.cond
<< 28;
17968 inst
.size
= INSN_SIZE
;
17969 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17971 it_fsm_pre_encode ();
17972 opcode
->aencode ();
17973 it_fsm_post_encode ();
17975 /* Arm mode bx is marked as both v4T and v5 because it's still required
17976 on a hypothetical non-thumb v5 core. */
17978 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17980 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17981 *opcode
->avariant
);
17983 check_neon_suffixes
;
17987 mapping_state (MAP_ARM
);
17992 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18000 check_it_blocks_finished (void)
18005 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18006 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18007 == MANUAL_IT_BLOCK
)
18009 as_warn (_("section '%s' finished with an open IT block."),
18013 if (now_it
.state
== MANUAL_IT_BLOCK
)
18014 as_warn (_("file finished with an open IT block."));
18018 /* Various frobbings of labels and their addresses. */
18021 arm_start_line_hook (void)
18023 last_label_seen
= NULL
;
18027 arm_frob_label (symbolS
* sym
)
18029 last_label_seen
= sym
;
18031 ARM_SET_THUMB (sym
, thumb_mode
);
18033 #if defined OBJ_COFF || defined OBJ_ELF
18034 ARM_SET_INTERWORK (sym
, support_interwork
);
18037 force_automatic_it_block_close ();
18039 /* Note - do not allow local symbols (.Lxxx) to be labelled
18040 as Thumb functions. This is because these labels, whilst
18041 they exist inside Thumb code, are not the entry points for
18042 possible ARM->Thumb calls. Also, these labels can be used
18043 as part of a computed goto or switch statement. eg gcc
18044 can generate code that looks like this:
18046 ldr r2, [pc, .Laaa]
18056 The first instruction loads the address of the jump table.
18057 The second instruction converts a table index into a byte offset.
18058 The third instruction gets the jump address out of the table.
18059 The fourth instruction performs the jump.
18061 If the address stored at .Laaa is that of a symbol which has the
18062 Thumb_Func bit set, then the linker will arrange for this address
18063 to have the bottom bit set, which in turn would mean that the
18064 address computation performed by the third instruction would end
18065 up with the bottom bit set. Since the ARM is capable of unaligned
18066 word loads, the instruction would then load the incorrect address
18067 out of the jump table, and chaos would ensue. */
18068 if (label_is_thumb_function_name
18069 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18070 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18072 /* When the address of a Thumb function is taken the bottom
18073 bit of that address should be set. This will allow
18074 interworking between Arm and Thumb functions to work
18077 THUMB_SET_FUNC (sym
, 1);
18079 label_is_thumb_function_name
= FALSE
;
18082 dwarf2_emit_label (sym
);
18086 arm_data_in_code (void)
18088 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18090 *input_line_pointer
= '/';
18091 input_line_pointer
+= 5;
18092 *input_line_pointer
= 0;
18100 arm_canonicalize_symbol_name (char * name
)
18104 if (thumb_mode
&& (len
= strlen (name
)) > 5
18105 && streq (name
+ len
- 5, "/data"))
18106 *(name
+ len
- 5) = 0;
18111 /* Table of all register names defined by default. The user can
18112 define additional names with .req. Note that all register names
18113 should appear in both upper and lowercase variants. Some registers
18114 also have mixed-case names. */
18116 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18117 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18118 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18119 #define REGSET(p,t) \
18120 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18121 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18122 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18123 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18124 #define REGSETH(p,t) \
18125 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18126 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18127 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18128 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18129 #define REGSET2(p,t) \
18130 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18131 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18132 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18133 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18134 #define SPLRBANK(base,bank,t) \
18135 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18136 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18137 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18138 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18139 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18140 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18142 static const struct reg_entry reg_names
[] =
18144 /* ARM integer registers. */
18145 REGSET(r
, RN
), REGSET(R
, RN
),
18147 /* ATPCS synonyms. */
18148 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18149 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18150 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18152 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18153 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18154 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18156 /* Well-known aliases. */
18157 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18158 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18160 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18161 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18163 /* Coprocessor numbers. */
18164 REGSET(p
, CP
), REGSET(P
, CP
),
18166 /* Coprocessor register numbers. The "cr" variants are for backward
18168 REGSET(c
, CN
), REGSET(C
, CN
),
18169 REGSET(cr
, CN
), REGSET(CR
, CN
),
18171 /* ARM banked registers. */
18172 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18173 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18174 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18175 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18176 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18177 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18178 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18180 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18181 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18182 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18183 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18184 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18185 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18186 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18187 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18189 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18190 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18191 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18192 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18193 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18194 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18195 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18196 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18197 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18199 /* FPA registers. */
18200 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18201 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18203 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18204 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18206 /* VFP SP registers. */
18207 REGSET(s
,VFS
), REGSET(S
,VFS
),
18208 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18210 /* VFP DP Registers. */
18211 REGSET(d
,VFD
), REGSET(D
,VFD
),
18212 /* Extra Neon DP registers. */
18213 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18215 /* Neon QP registers. */
18216 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18218 /* VFP control registers. */
18219 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18220 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18221 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18222 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18223 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18224 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18226 /* Maverick DSP coprocessor registers. */
18227 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18228 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18230 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18231 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18232 REGDEF(dspsc
,0,DSPSC
),
18234 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18235 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18236 REGDEF(DSPSC
,0,DSPSC
),
18238 /* iWMMXt data registers - p0, c0-15. */
18239 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18241 /* iWMMXt control registers - p1, c0-3. */
18242 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18243 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18244 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18245 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18247 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18248 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18249 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18250 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18251 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18253 /* XScale accumulator registers. */
18254 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18260 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18261 within psr_required_here. */
18262 static const struct asm_psr psrs
[] =
18264 /* Backward compatibility notation. Note that "all" is no longer
18265 truly all possible PSR bits. */
18266 {"all", PSR_c
| PSR_f
},
18270 /* Individual flags. */
18276 /* Combinations of flags. */
18277 {"fs", PSR_f
| PSR_s
},
18278 {"fx", PSR_f
| PSR_x
},
18279 {"fc", PSR_f
| PSR_c
},
18280 {"sf", PSR_s
| PSR_f
},
18281 {"sx", PSR_s
| PSR_x
},
18282 {"sc", PSR_s
| PSR_c
},
18283 {"xf", PSR_x
| PSR_f
},
18284 {"xs", PSR_x
| PSR_s
},
18285 {"xc", PSR_x
| PSR_c
},
18286 {"cf", PSR_c
| PSR_f
},
18287 {"cs", PSR_c
| PSR_s
},
18288 {"cx", PSR_c
| PSR_x
},
18289 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18290 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18291 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18292 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18293 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18294 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18295 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18296 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18297 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18298 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18299 {"scf", PSR_s
| PSR_c
| PSR_f
},
18300 {"scx", PSR_s
| PSR_c
| PSR_x
},
18301 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18302 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18303 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18304 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18305 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18306 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18307 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18308 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18309 {"csf", PSR_c
| PSR_s
| PSR_f
},
18310 {"csx", PSR_c
| PSR_s
| PSR_x
},
18311 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18312 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18313 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18314 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18315 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18316 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18317 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18318 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18319 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18320 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18321 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18322 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18323 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18324 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18325 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18326 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18327 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18328 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18329 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18330 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18331 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18332 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18333 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18334 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18335 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18336 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18339 /* Table of V7M psr names. */
18340 static const struct asm_psr v7m_psrs
[] =
18342 {"apsr", 0 }, {"APSR", 0 },
18343 {"iapsr", 1 }, {"IAPSR", 1 },
18344 {"eapsr", 2 }, {"EAPSR", 2 },
18345 {"psr", 3 }, {"PSR", 3 },
18346 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18347 {"ipsr", 5 }, {"IPSR", 5 },
18348 {"epsr", 6 }, {"EPSR", 6 },
18349 {"iepsr", 7 }, {"IEPSR", 7 },
18350 {"msp", 8 }, {"MSP", 8 },
18351 {"psp", 9 }, {"PSP", 9 },
18352 {"primask", 16}, {"PRIMASK", 16},
18353 {"basepri", 17}, {"BASEPRI", 17},
18354 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18355 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18356 {"faultmask", 19}, {"FAULTMASK", 19},
18357 {"control", 20}, {"CONTROL", 20}
18360 /* Table of all shift-in-operand names. */
18361 static const struct asm_shift_name shift_names
[] =
18363 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18364 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18365 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18366 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18367 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18368 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18371 /* Table of all explicit relocation names. */
18373 static struct reloc_entry reloc_names
[] =
18375 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18376 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18377 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18378 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18379 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18380 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18381 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18382 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18383 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18384 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18385 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18386 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18387 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18388 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18389 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18390 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18391 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18392 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18396 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18397 static const struct asm_cond conds
[] =
18401 {"cs", 0x2}, {"hs", 0x2},
18402 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18416 #define UL_BARRIER(L,U,CODE,FEAT) \
18417 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18418 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18420 static struct asm_barrier_opt barrier_opt_names
[] =
18422 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18423 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18424 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18425 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18426 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18427 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18428 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18429 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18430 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18431 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18432 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18433 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18434 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18435 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18436 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18437 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18442 /* Table of ARM-format instructions. */
18444 /* Macros for gluing together operand strings. N.B. In all cases
18445 other than OPS0, the trailing OP_stop comes from default
18446 zero-initialization of the unspecified elements of the array. */
18447 #define OPS0() { OP_stop, }
18448 #define OPS1(a) { OP_##a, }
18449 #define OPS2(a,b) { OP_##a,OP_##b, }
18450 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18451 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18452 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18453 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18455 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18456 This is useful when mixing operands for ARM and THUMB, i.e. using the
18457 MIX_ARM_THUMB_OPERANDS macro.
18458 In order to use these macros, prefix the number of operands with _
18460 #define OPS_1(a) { a, }
18461 #define OPS_2(a,b) { a,b, }
18462 #define OPS_3(a,b,c) { a,b,c, }
18463 #define OPS_4(a,b,c,d) { a,b,c,d, }
18464 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18465 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18467 /* These macros abstract out the exact format of the mnemonic table and
18468 save some repeated characters. */
18470 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18471 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18472 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18473 THUMB_VARIANT, do_##ae, do_##te }
18475 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18476 a T_MNEM_xyz enumerator. */
18477 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18478 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18479 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18480 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18482 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18483 infix after the third character. */
18484 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18485 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18486 THUMB_VARIANT, do_##ae, do_##te }
18487 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18488 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18489 THUMB_VARIANT, do_##ae, do_##te }
18490 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18491 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18492 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18493 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18494 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18495 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18496 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18497 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18499 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18500 field is still 0xE. Many of the Thumb variants can be executed
18501 conditionally, so this is checked separately. */
18502 #define TUE(mnem, op, top, nops, ops, ae, te) \
18503 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18504 THUMB_VARIANT, do_##ae, do_##te }
18506 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18507 Used by mnemonics that have very minimal differences in the encoding for
18508 ARM and Thumb variants and can be handled in a common function. */
18509 #define TUEc(mnem, op, top, nops, ops, en) \
18510 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18511 THUMB_VARIANT, do_##en, do_##en }
18513 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18514 condition code field. */
18515 #define TUF(mnem, op, top, nops, ops, ae, te) \
18516 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18517 THUMB_VARIANT, do_##ae, do_##te }
18519 /* ARM-only variants of all the above. */
18520 #define CE(mnem, op, nops, ops, ae) \
18521 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18523 #define C3(mnem, op, nops, ops, ae) \
18524 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18526 /* Legacy mnemonics that always have conditional infix after the third
18528 #define CL(mnem, op, nops, ops, ae) \
18529 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18530 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18532 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18533 #define cCE(mnem, op, nops, ops, ae) \
18534 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18536 /* Legacy coprocessor instructions where conditional infix and conditional
18537 suffix are ambiguous. For consistency this includes all FPA instructions,
18538 not just the potentially ambiguous ones. */
18539 #define cCL(mnem, op, nops, ops, ae) \
18540 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18541 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18543 /* Coprocessor, takes either a suffix or a position-3 infix
18544 (for an FPA corner case). */
18545 #define C3E(mnem, op, nops, ops, ae) \
18546 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18547 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18549 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18550 { m1 #m2 m3, OPS##nops ops, \
18551 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18552 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18554 #define CM(m1, m2, op, nops, ops, ae) \
18555 xCM_ (m1, , m2, op, nops, ops, ae), \
18556 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18557 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18558 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18559 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18560 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18561 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18562 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18563 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18564 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18565 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18566 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18567 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18568 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18569 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18570 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18571 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18572 xCM_ (m1, le, m2, op, nops, ops, ae), \
18573 xCM_ (m1, al, m2, op, nops, ops, ae)
18575 #define UE(mnem, op, nops, ops, ae) \
18576 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18578 #define UF(mnem, op, nops, ops, ae) \
18579 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18581 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18582 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18583 use the same encoding function for each. */
18584 #define NUF(mnem, op, nops, ops, enc) \
18585 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18586 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18588 /* Neon data processing, version which indirects through neon_enc_tab for
18589 the various overloaded versions of opcodes. */
18590 #define nUF(mnem, op, nops, ops, enc) \
18591 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18592 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18594 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18596 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18597 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18598 THUMB_VARIANT, do_##enc, do_##enc }
18600 #define NCE(mnem, op, nops, ops, enc) \
18601 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18603 #define NCEF(mnem, op, nops, ops, enc) \
18604 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18606 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18607 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18608 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18609 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18611 #define nCE(mnem, op, nops, ops, enc) \
18612 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18614 #define nCEF(mnem, op, nops, ops, enc) \
18615 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18619 static const struct asm_opcode insns
[] =
18621 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18622 #define THUMB_VARIANT & arm_ext_v4t
18623 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18624 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18625 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18626 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18627 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18628 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18629 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18630 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18631 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18632 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18633 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18634 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18635 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18636 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18637 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18638 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18640 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18641 for setting PSR flag bits. They are obsolete in V6 and do not
18642 have Thumb equivalents. */
18643 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18644 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18645 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18646 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18647 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18648 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18649 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18650 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18651 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18653 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18654 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
18655 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18656 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18658 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18659 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18660 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18662 OP_ADDRGLDR
),ldst
, t_ldst
),
18663 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18665 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18666 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18667 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18668 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18669 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18670 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18672 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18673 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18674 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18675 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18678 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18679 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18680 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18681 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18683 /* Thumb-compatibility pseudo ops. */
18684 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18685 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18686 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18687 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18688 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18689 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18690 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18691 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18692 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18693 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18694 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18695 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18697 /* These may simplify to neg. */
18698 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18699 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18701 #undef THUMB_VARIANT
18702 #define THUMB_VARIANT & arm_ext_v6
18704 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18706 /* V1 instructions with no Thumb analogue prior to V6T2. */
18707 #undef THUMB_VARIANT
18708 #define THUMB_VARIANT & arm_ext_v6t2
18710 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18711 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18712 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18714 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18715 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18716 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18717 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18719 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18720 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18722 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18723 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18725 /* V1 instructions with no Thumb analogue at all. */
18726 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18727 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18729 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18730 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18731 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18732 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18733 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18734 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18735 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18736 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18739 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18740 #undef THUMB_VARIANT
18741 #define THUMB_VARIANT & arm_ext_v4t
18743 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18744 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18746 #undef THUMB_VARIANT
18747 #define THUMB_VARIANT & arm_ext_v6t2
18749 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18750 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18752 /* Generic coprocessor instructions. */
18753 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18754 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18755 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18756 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18757 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18758 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18759 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18762 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18764 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18765 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18768 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18769 #undef THUMB_VARIANT
18770 #define THUMB_VARIANT & arm_ext_msr
18772 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18773 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18776 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18777 #undef THUMB_VARIANT
18778 #define THUMB_VARIANT & arm_ext_v6t2
18780 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18781 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18782 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18783 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18784 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18785 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18786 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18787 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18790 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18791 #undef THUMB_VARIANT
18792 #define THUMB_VARIANT & arm_ext_v4t
18794 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18795 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18796 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18797 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18798 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18799 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18802 #define ARM_VARIANT & arm_ext_v4t_5
18804 /* ARM Architecture 4T. */
18805 /* Note: bx (and blx) are required on V5, even if the processor does
18806 not support Thumb. */
18807 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18810 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18811 #undef THUMB_VARIANT
18812 #define THUMB_VARIANT & arm_ext_v5t
18814 /* Note: blx has 2 variants; the .value coded here is for
18815 BLX(2). Only this variant has conditional execution. */
18816 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18817 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18819 #undef THUMB_VARIANT
18820 #define THUMB_VARIANT & arm_ext_v6t2
18822 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18823 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18824 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18825 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18826 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18827 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18828 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18829 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18832 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18833 #undef THUMB_VARIANT
18834 #define THUMB_VARIANT & arm_ext_v5exp
18836 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18837 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18838 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18839 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18841 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18842 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18844 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18845 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18846 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18847 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18849 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18850 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18851 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18852 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18854 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18855 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18857 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18858 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18859 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18860 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18863 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18864 #undef THUMB_VARIANT
18865 #define THUMB_VARIANT & arm_ext_v6t2
18867 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18868 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18870 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18871 ADDRGLDRS
), ldrd
, t_ldstd
),
18873 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18874 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18877 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18879 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18882 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18883 #undef THUMB_VARIANT
18884 #define THUMB_VARIANT & arm_ext_v6
18886 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18887 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18888 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18889 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18890 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18891 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18892 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18893 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18894 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18895 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18897 #undef THUMB_VARIANT
18898 #define THUMB_VARIANT & arm_ext_v6t2
18900 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18901 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18903 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18904 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18906 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18907 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18909 /* ARM V6 not included in V7M. */
18910 #undef THUMB_VARIANT
18911 #define THUMB_VARIANT & arm_ext_v6_notm
18912 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18913 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18914 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18915 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18916 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18917 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18918 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18919 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18920 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18921 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18922 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18923 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18924 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18925 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18926 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18927 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18928 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18929 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18930 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18932 /* ARM V6 not included in V7M (eg. integer SIMD). */
18933 #undef THUMB_VARIANT
18934 #define THUMB_VARIANT & arm_ext_v6_dsp
18935 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18936 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18937 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18940 /* Old name for QASX. */
18941 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18942 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18943 /* Old name for QSAX. */
18944 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18945 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18946 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18948 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 /* Old name for SASX. */
18951 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18952 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18954 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18955 /* Old name for SHASX. */
18956 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18957 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18958 /* Old name for SHSAX. */
18959 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18960 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18961 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18962 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18963 /* Old name for SSAX. */
18964 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18965 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18966 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18967 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18968 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18969 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18970 /* Old name for UASX. */
18971 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18972 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18973 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18974 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18975 /* Old name for UHASX. */
18976 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18977 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18978 /* Old name for UHSAX. */
18979 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18980 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18981 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18982 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18983 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18984 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18985 /* Old name for UQASX. */
18986 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18987 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18988 /* Old name for UQSAX. */
18989 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18990 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18991 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18992 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18993 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18994 /* Old name for USAX. */
18995 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18996 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18997 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18998 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18999 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19000 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19001 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19002 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19003 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19004 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19005 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19006 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19007 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19008 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19009 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19010 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19011 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19012 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19013 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19014 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19015 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19016 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19017 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19018 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19019 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19020 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19021 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19022 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19023 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19024 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19025 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19026 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19027 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19028 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19031 #define ARM_VARIANT & arm_ext_v6k
19032 #undef THUMB_VARIANT
19033 #define THUMB_VARIANT & arm_ext_v6k
19035 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19036 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19037 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19038 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19040 #undef THUMB_VARIANT
19041 #define THUMB_VARIANT & arm_ext_v6_notm
19042 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19044 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19045 RRnpcb
), strexd
, t_strexd
),
19047 #undef THUMB_VARIANT
19048 #define THUMB_VARIANT & arm_ext_v6t2
19049 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19051 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19053 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19055 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19057 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19060 #define ARM_VARIANT & arm_ext_sec
19061 #undef THUMB_VARIANT
19062 #define THUMB_VARIANT & arm_ext_sec
19064 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19067 #define ARM_VARIANT & arm_ext_virt
19068 #undef THUMB_VARIANT
19069 #define THUMB_VARIANT & arm_ext_virt
19071 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19072 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19075 #define ARM_VARIANT & arm_ext_pan
19076 #undef THUMB_VARIANT
19077 #define THUMB_VARIANT & arm_ext_pan
19079 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19082 #define ARM_VARIANT & arm_ext_v6t2
19083 #undef THUMB_VARIANT
19084 #define THUMB_VARIANT & arm_ext_v6t2
19086 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19087 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19088 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19089 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19091 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19092 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19093 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19094 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19096 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19097 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19098 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19099 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19101 /* Thumb-only instructions. */
19103 #define ARM_VARIANT NULL
19104 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19105 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19107 /* ARM does not really have an IT instruction, so always allow it.
19108 The opcode is copied from Thumb in order to allow warnings in
19109 -mimplicit-it=[never | arm] modes. */
19111 #define ARM_VARIANT & arm_ext_v1
19113 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19114 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19115 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19116 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19117 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19118 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19119 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19120 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19121 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19122 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19123 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19124 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19125 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19126 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19127 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19128 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19129 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19130 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19132 /* Thumb2 only instructions. */
19134 #define ARM_VARIANT NULL
19136 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19137 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19138 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19139 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19140 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19141 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19143 /* Hardware division instructions. */
19145 #define ARM_VARIANT & arm_ext_adiv
19146 #undef THUMB_VARIANT
19147 #define THUMB_VARIANT & arm_ext_div
19149 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19150 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19152 /* ARM V6M/V7 instructions. */
19154 #define ARM_VARIANT & arm_ext_barrier
19155 #undef THUMB_VARIANT
19156 #define THUMB_VARIANT & arm_ext_barrier
19158 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19159 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19160 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19162 /* ARM V7 instructions. */
19164 #define ARM_VARIANT & arm_ext_v7
19165 #undef THUMB_VARIANT
19166 #define THUMB_VARIANT & arm_ext_v7
19168 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19169 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19172 #define ARM_VARIANT & arm_ext_mp
19173 #undef THUMB_VARIANT
19174 #define THUMB_VARIANT & arm_ext_mp
19176 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19178 /* AArchv8 instructions. */
19180 #define ARM_VARIANT & arm_ext_v8
19181 #undef THUMB_VARIANT
19182 #define THUMB_VARIANT & arm_ext_v8
19184 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19185 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19186 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19187 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19189 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19190 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19191 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19193 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19195 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19197 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19199 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19200 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19201 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19202 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19203 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19204 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19206 /* ARMv8 T32 only. */
19208 #define ARM_VARIANT NULL
19209 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19210 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19211 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19213 /* FP for ARMv8. */
19215 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19216 #undef THUMB_VARIANT
19217 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19219 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19220 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19221 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19222 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19223 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19224 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19225 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19226 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19227 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19228 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19229 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19230 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19231 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19232 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19233 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19234 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19235 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19237 /* Crypto v1 extensions. */
19239 #define ARM_VARIANT & fpu_crypto_ext_armv8
19240 #undef THUMB_VARIANT
19241 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19243 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19244 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19245 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19246 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19247 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19248 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19249 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19250 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19251 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19252 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19253 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19254 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19255 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19256 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19259 #define ARM_VARIANT & crc_ext_armv8
19260 #undef THUMB_VARIANT
19261 #define THUMB_VARIANT & crc_ext_armv8
19262 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19263 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19264 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19265 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19266 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19267 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19270 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19271 #undef THUMB_VARIANT
19272 #define THUMB_VARIANT NULL
19274 cCE("wfs", e200110
, 1, (RR
), rd
),
19275 cCE("rfs", e300110
, 1, (RR
), rd
),
19276 cCE("wfc", e400110
, 1, (RR
), rd
),
19277 cCE("rfc", e500110
, 1, (RR
), rd
),
19279 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19280 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19281 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19282 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19284 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19285 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19286 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19287 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19289 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19297 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19310 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19323 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19336 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19349 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19362 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19375 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19388 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19401 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19414 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19427 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19440 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19453 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19454 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19455 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19456 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19458 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19459 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19460 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19461 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19462 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19463 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19464 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19465 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19466 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19467 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19468 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19469 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19471 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19472 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19473 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19474 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19475 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19476 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19477 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19478 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19479 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19480 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19481 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19482 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19484 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19485 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19486 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19487 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19488 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19489 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19490 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19491 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19492 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19493 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19494 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19495 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19497 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19500 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19501 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19504 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19505 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19506 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19518 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19531 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19544 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19557 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19570 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19583 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19596 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19609 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19622 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19623 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19624 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19625 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19627 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19628 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19629 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19630 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19631 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19632 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19633 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19634 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19635 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19636 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19637 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19638 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19640 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19641 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19642 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19643 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19644 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19645 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19646 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19647 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19648 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19649 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19650 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19651 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19653 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19654 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19655 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19656 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19657 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19658 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19659 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19660 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19661 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19662 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19663 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19664 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19666 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19667 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19668 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19669 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19671 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19672 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19673 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19674 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19675 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19676 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19677 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19678 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19679 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19680 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19681 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19682 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19684 /* The implementation of the FIX instruction is broken on some
19685 assemblers, in that it accepts a precision specifier as well as a
19686 rounding specifier, despite the fact that this is meaningless.
19687 To be more compatible, we accept it as well, though of course it
19688 does not set any bits. */
19689 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19690 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19691 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19692 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19693 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19694 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19695 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19696 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19697 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19698 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19699 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19700 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19701 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19703 /* Instructions that were new with the real FPA, call them V2. */
19705 #define ARM_VARIANT & fpu_fpa_ext_v2
19707 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19708 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19709 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19710 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19711 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19712 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19715 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19717 /* Moves and type conversions. */
19718 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19719 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19720 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19721 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19722 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19723 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19724 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19725 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19726 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19727 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19728 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19729 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19730 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19731 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19733 /* Memory operations. */
19734 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19735 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19736 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19737 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19738 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19739 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19740 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19741 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19742 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19743 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19744 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19745 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19746 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19747 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19748 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19749 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19750 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19751 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19753 /* Monadic operations. */
19754 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19755 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19756 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19758 /* Dyadic operations. */
19759 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19760 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19761 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19762 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19763 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19764 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19765 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19766 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19767 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19770 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19771 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19772 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19773 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19775 /* Double precision load/store are still present on single precision
19776 implementations. */
19777 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19778 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19779 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19780 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19781 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19782 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19783 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19784 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19785 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19786 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19789 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19791 /* Moves and type conversions. */
19792 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19793 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19794 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19795 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19796 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19797 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19798 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19799 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19800 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19801 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19802 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19803 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19804 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19806 /* Monadic operations. */
19807 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19808 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19809 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19811 /* Dyadic operations. */
19812 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19813 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19814 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19815 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19816 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19817 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19818 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19819 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19820 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19823 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19824 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19825 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19826 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19829 #define ARM_VARIANT & fpu_vfp_ext_v2
19831 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19832 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19833 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19834 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19836 /* Instructions which may belong to either the Neon or VFP instruction sets.
19837 Individual encoder functions perform additional architecture checks. */
19839 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19840 #undef THUMB_VARIANT
19841 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19843 /* These mnemonics are unique to VFP. */
19844 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19845 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19846 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19847 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19848 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19849 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19850 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19851 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19852 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19853 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19855 /* Mnemonics shared by Neon and VFP. */
19856 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19857 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19858 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19860 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19861 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19863 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19864 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19866 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19867 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19868 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19869 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19870 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19871 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19872 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19873 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19875 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19876 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19877 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19878 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19881 /* NOTE: All VMOV encoding is special-cased! */
19882 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19883 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19885 #undef THUMB_VARIANT
19886 #define THUMB_VARIANT & fpu_neon_ext_v1
19888 #define ARM_VARIANT & fpu_neon_ext_v1
19890 /* Data processing with three registers of the same length. */
19891 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19892 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19893 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19894 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19895 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19896 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19897 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19898 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19899 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19900 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19901 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19902 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19903 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19904 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19905 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19906 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19907 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19908 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19909 /* If not immediate, fall back to neon_dyadic_i64_su.
19910 shl_imm should accept I8 I16 I32 I64,
19911 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19912 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19913 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19914 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19915 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19916 /* Logic ops, types optional & ignored. */
19917 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19918 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19919 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19920 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19921 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19922 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19923 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19924 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19925 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19926 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19927 /* Bitfield ops, untyped. */
19928 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19929 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19930 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19931 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19932 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19933 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19934 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19935 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19936 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19937 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19938 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19939 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19940 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19941 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19942 back to neon_dyadic_if_su. */
19943 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19944 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19945 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19946 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19947 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19948 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19949 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19950 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19951 /* Comparison. Type I8 I16 I32 F32. */
19952 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19953 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19954 /* As above, D registers only. */
19955 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19956 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19957 /* Int and float variants, signedness unimportant. */
19958 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19959 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19960 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19961 /* Add/sub take types I8 I16 I32 I64 F32. */
19962 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19963 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19964 /* vtst takes sizes 8, 16, 32. */
19965 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19966 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19967 /* VMUL takes I8 I16 I32 F32 P8. */
19968 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19969 /* VQD{R}MULH takes S16 S32. */
19970 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19971 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19972 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19973 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19974 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19975 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19976 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19977 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19978 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19979 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19980 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19981 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19982 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19983 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19984 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19985 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19986 /* ARM v8.1 extension. */
19987 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19988 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19989 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19990 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19992 /* Two address, int/float. Types S8 S16 S32 F32. */
19993 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19994 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19996 /* Data processing with two registers and a shift amount. */
19997 /* Right shifts, and variants with rounding.
19998 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19999 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20000 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20001 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20002 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20003 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20004 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20005 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20006 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20007 /* Shift and insert. Sizes accepted 8 16 32 64. */
20008 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20009 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20010 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20011 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20012 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20013 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20014 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20015 /* Right shift immediate, saturating & narrowing, with rounding variants.
20016 Types accepted S16 S32 S64 U16 U32 U64. */
20017 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20018 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20019 /* As above, unsigned. Types accepted S16 S32 S64. */
20020 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20021 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20022 /* Right shift narrowing. Types accepted I16 I32 I64. */
20023 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20024 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20025 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20026 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20027 /* CVT with optional immediate for fixed-point variant. */
20028 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20030 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20031 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20033 /* Data processing, three registers of different lengths. */
20034 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20035 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20036 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20037 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20038 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20039 /* If not scalar, fall back to neon_dyadic_long.
20040 Vector types as above, scalar types S16 S32 U16 U32. */
20041 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20042 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20043 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20044 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20045 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20046 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20047 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20048 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20049 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20050 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20051 /* Saturating doubling multiplies. Types S16 S32. */
20052 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20053 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20054 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20055 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20056 S16 S32 U16 U32. */
20057 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20059 /* Extract. Size 8. */
20060 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20061 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20063 /* Two registers, miscellaneous. */
20064 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20065 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20066 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20067 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20068 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20069 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20070 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20071 /* Vector replicate. Sizes 8 16 32. */
20072 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20073 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20074 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20075 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20076 /* VMOVN. Types I16 I32 I64. */
20077 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20078 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20079 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20080 /* VQMOVUN. Types S16 S32 S64. */
20081 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20082 /* VZIP / VUZP. Sizes 8 16 32. */
20083 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20084 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20085 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20086 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20087 /* VQABS / VQNEG. Types S8 S16 S32. */
20088 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20089 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20090 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20091 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20092 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20093 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20094 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20095 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20096 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20097 /* Reciprocal estimates. Types U32 F32. */
20098 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20099 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20100 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20101 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20102 /* VCLS. Types S8 S16 S32. */
20103 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20104 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20105 /* VCLZ. Types I8 I16 I32. */
20106 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20107 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20108 /* VCNT. Size 8. */
20109 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20110 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20111 /* Two address, untyped. */
20112 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20113 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20114 /* VTRN. Sizes 8 16 32. */
20115 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20116 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20118 /* Table lookup. Size 8. */
20119 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20120 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20122 #undef THUMB_VARIANT
20123 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20125 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20127 /* Neon element/structure load/store. */
20128 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20129 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20130 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20131 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20132 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20133 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20134 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20135 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20137 #undef THUMB_VARIANT
20138 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20140 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20141 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20142 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20143 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20144 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20145 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20146 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20147 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20148 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20149 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20151 #undef THUMB_VARIANT
20152 #define THUMB_VARIANT & fpu_vfp_ext_v3
20154 #define ARM_VARIANT & fpu_vfp_ext_v3
20156 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20157 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20158 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20159 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20160 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20161 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20162 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20163 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20164 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20167 #define ARM_VARIANT & fpu_vfp_ext_fma
20168 #undef THUMB_VARIANT
20169 #define THUMB_VARIANT & fpu_vfp_ext_fma
20170 /* Mnemonics shared by Neon and VFP. These are included in the
20171 VFP FMA variant; NEON and VFP FMA always includes the NEON
20172 FMA instructions. */
20173 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20174 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20175 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20176 the v form should always be used. */
20177 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20178 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20179 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20180 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20181 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20182 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20184 #undef THUMB_VARIANT
20186 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20188 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20189 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20190 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20191 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20192 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20193 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20194 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20195 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20198 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20200 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20201 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20202 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20203 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20204 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20205 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20206 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20207 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20208 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20209 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20210 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20211 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20212 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20213 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20214 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20215 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20216 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20217 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20218 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20219 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20220 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20221 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20222 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20223 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20224 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20225 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20226 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20227 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20228 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20229 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20230 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20231 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20232 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20233 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20234 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20235 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20236 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20237 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20246 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20247 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20254 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20257 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20258 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20259 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20260 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20261 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20262 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20263 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20267 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20268 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20269 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20270 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20271 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20272 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20273 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20274 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20275 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20276 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20277 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20278 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20279 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20280 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20281 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20282 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20283 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20284 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20285 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20286 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20287 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20288 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20289 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20290 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20291 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20292 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20293 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20294 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20295 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20296 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20297 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20298 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20299 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20300 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20301 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20302 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20303 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20304 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20305 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20306 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20307 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20308 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20309 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20310 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20311 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20312 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20313 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20314 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20315 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20316 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20317 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20318 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20319 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20320 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20321 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20322 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20323 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20324 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20325 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20326 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20327 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20328 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20329 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20330 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20331 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20332 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20333 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20334 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20335 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20336 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20337 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20338 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20339 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20340 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20341 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20342 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20343 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20344 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20345 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20346 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20347 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20348 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20351 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20352 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20353 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20354 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20355 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20356 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20357 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20358 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20359 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20360 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20361 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20364 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20366 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20367 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20368 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20369 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20370 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20371 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20372 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20376 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20379 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20380 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20381 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20382 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20383 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20384 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20385 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20386 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20387 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20388 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20389 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20390 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20391 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20392 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20393 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20394 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20395 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20396 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20397 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20398 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20399 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20400 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20401 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20402 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20403 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20404 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20405 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20406 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20407 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20408 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20409 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20410 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20411 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20412 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20413 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20414 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20415 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20416 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20417 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20418 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20419 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20420 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20421 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20422 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20425 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20427 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20428 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20429 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20430 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20431 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20432 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20433 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20434 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20435 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20436 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20437 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20438 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20439 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20440 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20441 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20442 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20443 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20444 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20445 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20446 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20447 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20448 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20449 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20450 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20451 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20452 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20453 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20454 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20455 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20456 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20457 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20458 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20459 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20460 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20461 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20462 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20463 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20464 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20465 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20466 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20467 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20468 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20469 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20470 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20471 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20472 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20473 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20474 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20475 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20476 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20477 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20478 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20479 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20480 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20481 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20482 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20483 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20484 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20485 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20486 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20487 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20488 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20489 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20490 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20491 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20492 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20493 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20494 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20495 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20496 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20497 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20498 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20499 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20500 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20501 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20502 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20505 #undef THUMB_VARIANT
20531 /* MD interface: bits in the object file. */
20533 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20534 for use in the a.out file, and stores them in the array pointed to by buf.
20535 This knows about the endian-ness of the target machine and does
20536 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20537 2 (short) and 4 (long) Floating numbers are put out as a series of
20538 LITTLENUMS (shorts, here at least). */
20541 md_number_to_chars (char * buf
, valueT val
, int n
)
20543 if (target_big_endian
)
20544 number_to_chars_bigendian (buf
, val
, n
);
20546 number_to_chars_littleendian (buf
, val
, n
);
20550 md_chars_to_number (char * buf
, int n
)
20553 unsigned char * where
= (unsigned char *) buf
;
20555 if (target_big_endian
)
20560 result
|= (*where
++ & 255);
20568 result
|= (where
[n
] & 255);
20575 /* MD interface: Sections. */
20577 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20578 that an rs_machine_dependent frag may reach. */
20581 arm_frag_max_var (fragS
*fragp
)
20583 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20584 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20586 Note that we generate relaxable instructions even for cases that don't
20587 really need it, like an immediate that's a trivial constant. So we're
20588 overestimating the instruction size for some of those cases. Rather
20589 than putting more intelligence here, it would probably be better to
20590 avoid generating a relaxation frag in the first place when it can be
20591 determined up front that a short instruction will suffice. */
20593 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20597 /* Estimate the size of a frag before relaxing. Assume everything fits in
20601 md_estimate_size_before_relax (fragS
* fragp
,
20602 segT segtype ATTRIBUTE_UNUSED
)
20608 /* Convert a machine dependent frag. */
20611 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20613 unsigned long insn
;
20614 unsigned long old_op
;
20622 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20624 old_op
= bfd_get_16(abfd
, buf
);
20625 if (fragp
->fr_symbol
)
20627 exp
.X_op
= O_symbol
;
20628 exp
.X_add_symbol
= fragp
->fr_symbol
;
20632 exp
.X_op
= O_constant
;
20634 exp
.X_add_number
= fragp
->fr_offset
;
20635 opcode
= fragp
->fr_subtype
;
20638 case T_MNEM_ldr_pc
:
20639 case T_MNEM_ldr_pc2
:
20640 case T_MNEM_ldr_sp
:
20641 case T_MNEM_str_sp
:
20648 if (fragp
->fr_var
== 4)
20650 insn
= THUMB_OP32 (opcode
);
20651 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20653 insn
|= (old_op
& 0x700) << 4;
20657 insn
|= (old_op
& 7) << 12;
20658 insn
|= (old_op
& 0x38) << 13;
20660 insn
|= 0x00000c00;
20661 put_thumb32_insn (buf
, insn
);
20662 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20666 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20668 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20671 if (fragp
->fr_var
== 4)
20673 insn
= THUMB_OP32 (opcode
);
20674 insn
|= (old_op
& 0xf0) << 4;
20675 put_thumb32_insn (buf
, insn
);
20676 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20680 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20681 exp
.X_add_number
-= 4;
20689 if (fragp
->fr_var
== 4)
20691 int r0off
= (opcode
== T_MNEM_mov
20692 || opcode
== T_MNEM_movs
) ? 0 : 8;
20693 insn
= THUMB_OP32 (opcode
);
20694 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20695 insn
|= (old_op
& 0x700) << r0off
;
20696 put_thumb32_insn (buf
, insn
);
20697 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20701 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20706 if (fragp
->fr_var
== 4)
20708 insn
= THUMB_OP32(opcode
);
20709 put_thumb32_insn (buf
, insn
);
20710 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20713 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20717 if (fragp
->fr_var
== 4)
20719 insn
= THUMB_OP32(opcode
);
20720 insn
|= (old_op
& 0xf00) << 14;
20721 put_thumb32_insn (buf
, insn
);
20722 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20725 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20728 case T_MNEM_add_sp
:
20729 case T_MNEM_add_pc
:
20730 case T_MNEM_inc_sp
:
20731 case T_MNEM_dec_sp
:
20732 if (fragp
->fr_var
== 4)
20734 /* ??? Choose between add and addw. */
20735 insn
= THUMB_OP32 (opcode
);
20736 insn
|= (old_op
& 0xf0) << 4;
20737 put_thumb32_insn (buf
, insn
);
20738 if (opcode
== T_MNEM_add_pc
)
20739 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20741 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20744 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20752 if (fragp
->fr_var
== 4)
20754 insn
= THUMB_OP32 (opcode
);
20755 insn
|= (old_op
& 0xf0) << 4;
20756 insn
|= (old_op
& 0xf) << 16;
20757 put_thumb32_insn (buf
, insn
);
20758 if (insn
& (1 << 20))
20759 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20761 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20764 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20770 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20771 (enum bfd_reloc_code_real
) reloc_type
);
20772 fixp
->fx_file
= fragp
->fr_file
;
20773 fixp
->fx_line
= fragp
->fr_line
;
20774 fragp
->fr_fix
+= fragp
->fr_var
;
20776 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20777 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20778 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20779 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20782 /* Return the size of a relaxable immediate operand instruction.
20783 SHIFT and SIZE specify the form of the allowable immediate. */
20785 relax_immediate (fragS
*fragp
, int size
, int shift
)
20791 /* ??? Should be able to do better than this. */
20792 if (fragp
->fr_symbol
)
20795 low
= (1 << shift
) - 1;
20796 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20797 offset
= fragp
->fr_offset
;
20798 /* Force misaligned offsets to 32-bit variant. */
20801 if (offset
& ~mask
)
20806 /* Get the address of a symbol during relaxation. */
20808 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20814 sym
= fragp
->fr_symbol
;
20815 sym_frag
= symbol_get_frag (sym
);
20816 know (S_GET_SEGMENT (sym
) != absolute_section
20817 || sym_frag
== &zero_address_frag
);
20818 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20820 /* If frag has yet to be reached on this pass, assume it will
20821 move by STRETCH just as we did. If this is not so, it will
20822 be because some frag between grows, and that will force
20826 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20830 /* Adjust stretch for any alignment frag. Note that if have
20831 been expanding the earlier code, the symbol may be
20832 defined in what appears to be an earlier frag. FIXME:
20833 This doesn't handle the fr_subtype field, which specifies
20834 a maximum number of bytes to skip when doing an
20836 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20838 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20841 stretch
= - ((- stretch
)
20842 & ~ ((1 << (int) f
->fr_offset
) - 1));
20844 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20856 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20859 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20864 /* Assume worst case for symbols not known to be in the same section. */
20865 if (fragp
->fr_symbol
== NULL
20866 || !S_IS_DEFINED (fragp
->fr_symbol
)
20867 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20868 || S_IS_WEAK (fragp
->fr_symbol
))
20871 val
= relaxed_symbol_addr (fragp
, stretch
);
20872 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20873 addr
= (addr
+ 4) & ~3;
20874 /* Force misaligned targets to 32-bit variant. */
20878 if (val
< 0 || val
> 1020)
20883 /* Return the size of a relaxable add/sub immediate instruction. */
20885 relax_addsub (fragS
*fragp
, asection
*sec
)
20890 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20891 op
= bfd_get_16(sec
->owner
, buf
);
20892 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20893 return relax_immediate (fragp
, 8, 0);
20895 return relax_immediate (fragp
, 3, 0);
20898 /* Return TRUE iff the definition of symbol S could be pre-empted
20899 (overridden) at link or load time. */
20901 symbol_preemptible (symbolS
*s
)
20903 /* Weak symbols can always be pre-empted. */
20907 /* Non-global symbols cannot be pre-empted. */
20908 if (! S_IS_EXTERNAL (s
))
20912 /* In ELF, a global symbol can be marked protected, or private. In that
20913 case it can't be pre-empted (other definitions in the same link unit
20914 would violate the ODR). */
20915 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20919 /* Other global symbols might be pre-empted. */
20923 /* Return the size of a relaxable branch instruction. BITS is the
20924 size of the offset field in the narrow instruction. */
20927 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20933 /* Assume worst case for symbols not known to be in the same section. */
20934 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20935 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20936 || S_IS_WEAK (fragp
->fr_symbol
))
20940 /* A branch to a function in ARM state will require interworking. */
20941 if (S_IS_DEFINED (fragp
->fr_symbol
)
20942 && ARM_IS_FUNC (fragp
->fr_symbol
))
20946 if (symbol_preemptible (fragp
->fr_symbol
))
20949 val
= relaxed_symbol_addr (fragp
, stretch
);
20950 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20953 /* Offset is a signed value *2 */
20955 if (val
>= limit
|| val
< -limit
)
20961 /* Relax a machine dependent frag. This returns the amount by which
20962 the current size of the frag should change. */
20965 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20970 oldsize
= fragp
->fr_var
;
20971 switch (fragp
->fr_subtype
)
20973 case T_MNEM_ldr_pc2
:
20974 newsize
= relax_adr (fragp
, sec
, stretch
);
20976 case T_MNEM_ldr_pc
:
20977 case T_MNEM_ldr_sp
:
20978 case T_MNEM_str_sp
:
20979 newsize
= relax_immediate (fragp
, 8, 2);
20983 newsize
= relax_immediate (fragp
, 5, 2);
20987 newsize
= relax_immediate (fragp
, 5, 1);
20991 newsize
= relax_immediate (fragp
, 5, 0);
20994 newsize
= relax_adr (fragp
, sec
, stretch
);
21000 newsize
= relax_immediate (fragp
, 8, 0);
21003 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21006 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21008 case T_MNEM_add_sp
:
21009 case T_MNEM_add_pc
:
21010 newsize
= relax_immediate (fragp
, 8, 2);
21012 case T_MNEM_inc_sp
:
21013 case T_MNEM_dec_sp
:
21014 newsize
= relax_immediate (fragp
, 7, 2);
21020 newsize
= relax_addsub (fragp
, sec
);
21026 fragp
->fr_var
= newsize
;
21027 /* Freeze wide instructions that are at or before the same location as
21028 in the previous pass. This avoids infinite loops.
21029 Don't freeze them unconditionally because targets may be artificially
21030 misaligned by the expansion of preceding frags. */
21031 if (stretch
<= 0 && newsize
> 2)
21033 md_convert_frag (sec
->owner
, sec
, fragp
);
21037 return newsize
- oldsize
;
21040 /* Round up a section size to the appropriate boundary. */
21043 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21046 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21047 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21049 /* For a.out, force the section size to be aligned. If we don't do
21050 this, BFD will align it for us, but it will not write out the
21051 final bytes of the section. This may be a bug in BFD, but it is
21052 easier to fix it here since that is how the other a.out targets
21056 align
= bfd_get_section_alignment (stdoutput
, segment
);
21057 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21064 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21065 of an rs_align_code fragment. */
21068 arm_handle_align (fragS
* fragP
)
21070 static char const arm_noop
[2][2][4] =
21073 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21074 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21077 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21078 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21081 static char const thumb_noop
[2][2][2] =
21084 {0xc0, 0x46}, /* LE */
21085 {0x46, 0xc0}, /* BE */
21088 {0x00, 0xbf}, /* LE */
21089 {0xbf, 0x00} /* BE */
21092 static char const wide_thumb_noop
[2][4] =
21093 { /* Wide Thumb-2 */
21094 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21095 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21098 unsigned bytes
, fix
, noop_size
;
21101 const char *narrow_noop
= NULL
;
21106 if (fragP
->fr_type
!= rs_align_code
)
21109 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21110 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21113 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21114 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21116 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21118 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21120 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21121 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21123 narrow_noop
= thumb_noop
[1][target_big_endian
];
21124 noop
= wide_thumb_noop
[target_big_endian
];
21127 noop
= thumb_noop
[0][target_big_endian
];
21135 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21136 ? selected_cpu
: arm_arch_none
,
21138 [target_big_endian
];
21145 fragP
->fr_var
= noop_size
;
21147 if (bytes
& (noop_size
- 1))
21149 fix
= bytes
& (noop_size
- 1);
21151 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21153 memset (p
, 0, fix
);
21160 if (bytes
& noop_size
)
21162 /* Insert a narrow noop. */
21163 memcpy (p
, narrow_noop
, noop_size
);
21165 bytes
-= noop_size
;
21169 /* Use wide noops for the remainder */
21173 while (bytes
>= noop_size
)
21175 memcpy (p
, noop
, noop_size
);
21177 bytes
-= noop_size
;
21181 fragP
->fr_fix
+= fix
;
21184 /* Called from md_do_align. Used to create an alignment
21185 frag in a code section. */
21188 arm_frag_align_code (int n
, int max
)
21192 /* We assume that there will never be a requirement
21193 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21194 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21199 _("alignments greater than %d bytes not supported in .text sections."),
21200 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21201 as_fatal ("%s", err_msg
);
21204 p
= frag_var (rs_align_code
,
21205 MAX_MEM_FOR_RS_ALIGN_CODE
,
21207 (relax_substateT
) max
,
21214 /* Perform target specific initialisation of a frag.
21215 Note - despite the name this initialisation is not done when the frag
21216 is created, but only when its type is assigned. A frag can be created
21217 and used a long time before its type is set, so beware of assuming that
21218 this initialisationis performed first. */
21222 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21224 /* Record whether this frag is in an ARM or a THUMB area. */
21225 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21228 #else /* OBJ_ELF is defined. */
21230 arm_init_frag (fragS
* fragP
, int max_chars
)
21232 int frag_thumb_mode
;
21234 /* If the current ARM vs THUMB mode has not already
21235 been recorded into this frag then do so now. */
21236 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21237 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21239 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21241 /* Record a mapping symbol for alignment frags. We will delete this
21242 later if the alignment ends up empty. */
21243 switch (fragP
->fr_type
)
21246 case rs_align_test
:
21248 mapping_state_2 (MAP_DATA
, max_chars
);
21250 case rs_align_code
:
21251 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21258 /* When we change sections we need to issue a new mapping symbol. */
21261 arm_elf_change_section (void)
21263 /* Link an unlinked unwind index table section to the .text section. */
21264 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21265 && elf_linked_to_section (now_seg
) == NULL
)
21266 elf_linked_to_section (now_seg
) = text_section
;
21270 arm_elf_section_type (const char * str
, size_t len
)
21272 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21273 return SHT_ARM_EXIDX
;
21278 /* Code to deal with unwinding tables. */
21280 static void add_unwind_adjustsp (offsetT
);
21282 /* Generate any deferred unwind frame offset. */
21285 flush_pending_unwind (void)
21289 offset
= unwind
.pending_offset
;
21290 unwind
.pending_offset
= 0;
21292 add_unwind_adjustsp (offset
);
21295 /* Add an opcode to this list for this function. Two-byte opcodes should
21296 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21300 add_unwind_opcode (valueT op
, int length
)
21302 /* Add any deferred stack adjustment. */
21303 if (unwind
.pending_offset
)
21304 flush_pending_unwind ();
21306 unwind
.sp_restored
= 0;
21308 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21310 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21311 if (unwind
.opcodes
)
21312 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21313 unwind
.opcode_alloc
);
21315 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21320 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21322 unwind
.opcode_count
++;
21326 /* Add unwind opcodes to adjust the stack pointer. */
21329 add_unwind_adjustsp (offsetT offset
)
21333 if (offset
> 0x200)
21335 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21340 /* Long form: 0xb2, uleb128. */
21341 /* This might not fit in a word so add the individual bytes,
21342 remembering the list is built in reverse order. */
21343 o
= (valueT
) ((offset
- 0x204) >> 2);
21345 add_unwind_opcode (0, 1);
21347 /* Calculate the uleb128 encoding of the offset. */
21351 bytes
[n
] = o
& 0x7f;
21357 /* Add the insn. */
21359 add_unwind_opcode (bytes
[n
- 1], 1);
21360 add_unwind_opcode (0xb2, 1);
21362 else if (offset
> 0x100)
21364 /* Two short opcodes. */
21365 add_unwind_opcode (0x3f, 1);
21366 op
= (offset
- 0x104) >> 2;
21367 add_unwind_opcode (op
, 1);
21369 else if (offset
> 0)
21371 /* Short opcode. */
21372 op
= (offset
- 4) >> 2;
21373 add_unwind_opcode (op
, 1);
21375 else if (offset
< 0)
21378 while (offset
> 0x100)
21380 add_unwind_opcode (0x7f, 1);
21383 op
= ((offset
- 4) >> 2) | 0x40;
21384 add_unwind_opcode (op
, 1);
21388 /* Finish the list of unwind opcodes for this function. */
21390 finish_unwind_opcodes (void)
21394 if (unwind
.fp_used
)
21396 /* Adjust sp as necessary. */
21397 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21398 flush_pending_unwind ();
21400 /* After restoring sp from the frame pointer. */
21401 op
= 0x90 | unwind
.fp_reg
;
21402 add_unwind_opcode (op
, 1);
21405 flush_pending_unwind ();
21409 /* Start an exception table entry. If idx is nonzero this is an index table
21413 start_unwind_section (const segT text_seg
, int idx
)
21415 const char * text_name
;
21416 const char * prefix
;
21417 const char * prefix_once
;
21418 const char * group_name
;
21422 size_t sec_name_len
;
21429 prefix
= ELF_STRING_ARM_unwind
;
21430 prefix_once
= ELF_STRING_ARM_unwind_once
;
21431 type
= SHT_ARM_EXIDX
;
21435 prefix
= ELF_STRING_ARM_unwind_info
;
21436 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21437 type
= SHT_PROGBITS
;
21440 text_name
= segment_name (text_seg
);
21441 if (streq (text_name
, ".text"))
21444 if (strncmp (text_name
, ".gnu.linkonce.t.",
21445 strlen (".gnu.linkonce.t.")) == 0)
21447 prefix
= prefix_once
;
21448 text_name
+= strlen (".gnu.linkonce.t.");
21451 prefix_len
= strlen (prefix
);
21452 text_len
= strlen (text_name
);
21453 sec_name_len
= prefix_len
+ text_len
;
21454 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21455 memcpy (sec_name
, prefix
, prefix_len
);
21456 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21457 sec_name
[prefix_len
+ text_len
] = '\0';
21463 /* Handle COMDAT group. */
21464 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21466 group_name
= elf_group_name (text_seg
);
21467 if (group_name
== NULL
)
21469 as_bad (_("Group section `%s' has no group signature"),
21470 segment_name (text_seg
));
21471 ignore_rest_of_line ();
21474 flags
|= SHF_GROUP
;
21478 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21480 /* Set the section link for index tables. */
21482 elf_linked_to_section (now_seg
) = text_seg
;
21486 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21487 personality routine data. Returns zero, or the index table value for
21488 an inline entry. */
21491 create_unwind_entry (int have_data
)
21496 /* The current word of data. */
21498 /* The number of bytes left in this word. */
21501 finish_unwind_opcodes ();
21503 /* Remember the current text section. */
21504 unwind
.saved_seg
= now_seg
;
21505 unwind
.saved_subseg
= now_subseg
;
21507 start_unwind_section (now_seg
, 0);
21509 if (unwind
.personality_routine
== NULL
)
21511 if (unwind
.personality_index
== -2)
21514 as_bad (_("handlerdata in cantunwind frame"));
21515 return 1; /* EXIDX_CANTUNWIND. */
21518 /* Use a default personality routine if none is specified. */
21519 if (unwind
.personality_index
== -1)
21521 if (unwind
.opcode_count
> 3)
21522 unwind
.personality_index
= 1;
21524 unwind
.personality_index
= 0;
21527 /* Space for the personality routine entry. */
21528 if (unwind
.personality_index
== 0)
21530 if (unwind
.opcode_count
> 3)
21531 as_bad (_("too many unwind opcodes for personality routine 0"));
21535 /* All the data is inline in the index table. */
21538 while (unwind
.opcode_count
> 0)
21540 unwind
.opcode_count
--;
21541 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21545 /* Pad with "finish" opcodes. */
21547 data
= (data
<< 8) | 0xb0;
21554 /* We get two opcodes "free" in the first word. */
21555 size
= unwind
.opcode_count
- 2;
21559 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21560 if (unwind
.personality_index
!= -1)
21562 as_bad (_("attempt to recreate an unwind entry"));
21566 /* An extra byte is required for the opcode count. */
21567 size
= unwind
.opcode_count
+ 1;
21570 size
= (size
+ 3) >> 2;
21572 as_bad (_("too many unwind opcodes"));
21574 frag_align (2, 0, 0);
21575 record_alignment (now_seg
, 2);
21576 unwind
.table_entry
= expr_build_dot ();
21578 /* Allocate the table entry. */
21579 ptr
= frag_more ((size
<< 2) + 4);
21580 /* PR 13449: Zero the table entries in case some of them are not used. */
21581 memset (ptr
, 0, (size
<< 2) + 4);
21582 where
= frag_now_fix () - ((size
<< 2) + 4);
21584 switch (unwind
.personality_index
)
21587 /* ??? Should this be a PLT generating relocation? */
21588 /* Custom personality routine. */
21589 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21590 BFD_RELOC_ARM_PREL31
);
21595 /* Set the first byte to the number of additional words. */
21596 data
= size
> 0 ? size
- 1 : 0;
21600 /* ABI defined personality routines. */
21602 /* Three opcodes bytes are packed into the first word. */
21609 /* The size and first two opcode bytes go in the first word. */
21610 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21615 /* Should never happen. */
21619 /* Pack the opcodes into words (MSB first), reversing the list at the same
21621 while (unwind
.opcode_count
> 0)
21625 md_number_to_chars (ptr
, data
, 4);
21630 unwind
.opcode_count
--;
21632 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21635 /* Finish off the last word. */
21638 /* Pad with "finish" opcodes. */
21640 data
= (data
<< 8) | 0xb0;
21642 md_number_to_chars (ptr
, data
, 4);
21647 /* Add an empty descriptor if there is no user-specified data. */
21648 ptr
= frag_more (4);
21649 md_number_to_chars (ptr
, 0, 4);
21656 /* Initialize the DWARF-2 unwind information for this procedure. */
21659 tc_arm_frame_initial_instructions (void)
21661 cfi_add_CFA_def_cfa (REG_SP
, 0);
21663 #endif /* OBJ_ELF */
21665 /* Convert REGNAME to a DWARF-2 register number. */
21668 tc_arm_regname_to_dw2regnum (char *regname
)
21670 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21674 /* PR 16694: Allow VFP registers as well. */
21675 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21679 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21688 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21692 exp
.X_op
= O_secrel
;
21693 exp
.X_add_symbol
= symbol
;
21694 exp
.X_add_number
= 0;
21695 emit_expr (&exp
, size
);
21699 /* MD interface: Symbol and relocation handling. */
21701 /* Return the address within the segment that a PC-relative fixup is
21702 relative to. For ARM, PC-relative fixups applied to instructions
21703 are generally relative to the location of the fixup plus 8 bytes.
21704 Thumb branches are offset by 4, and Thumb loads relative to PC
21705 require special handling. */
21708 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21710 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21712 /* If this is pc-relative and we are going to emit a relocation
21713 then we just want to put out any pipeline compensation that the linker
21714 will need. Otherwise we want to use the calculated base.
21715 For WinCE we skip the bias for externals as well, since this
21716 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21718 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21719 || (arm_force_relocation (fixP
)
21721 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21727 switch (fixP
->fx_r_type
)
21729 /* PC relative addressing on the Thumb is slightly odd as the
21730 bottom two bits of the PC are forced to zero for the
21731 calculation. This happens *after* application of the
21732 pipeline offset. However, Thumb adrl already adjusts for
21733 this, so we need not do it again. */
21734 case BFD_RELOC_ARM_THUMB_ADD
:
21737 case BFD_RELOC_ARM_THUMB_OFFSET
:
21738 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21739 case BFD_RELOC_ARM_T32_ADD_PC12
:
21740 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21741 return (base
+ 4) & ~3;
21743 /* Thumb branches are simply offset by +4. */
21744 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21745 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21746 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21747 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21748 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21751 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21753 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21754 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21755 && ARM_IS_FUNC (fixP
->fx_addsy
)
21756 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21757 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21760 /* BLX is like branches above, but forces the low two bits of PC to
21762 case BFD_RELOC_THUMB_PCREL_BLX
:
21764 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21765 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21766 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21767 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21768 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21769 return (base
+ 4) & ~3;
21771 /* ARM mode branches are offset by +8. However, the Windows CE
21772 loader expects the relocation not to take this into account. */
21773 case BFD_RELOC_ARM_PCREL_BLX
:
21775 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21776 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21777 && ARM_IS_FUNC (fixP
->fx_addsy
)
21778 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21779 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21782 case BFD_RELOC_ARM_PCREL_CALL
:
21784 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21785 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21786 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21787 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21788 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21791 case BFD_RELOC_ARM_PCREL_BRANCH
:
21792 case BFD_RELOC_ARM_PCREL_JUMP
:
21793 case BFD_RELOC_ARM_PLT32
:
21795 /* When handling fixups immediately, because we have already
21796 discovered the value of a symbol, or the address of the frag involved
21797 we must account for the offset by +8, as the OS loader will never see the reloc.
21798 see fixup_segment() in write.c
21799 The S_IS_EXTERNAL test handles the case of global symbols.
21800 Those need the calculated base, not just the pipe compensation the linker will need. */
21802 && fixP
->fx_addsy
!= NULL
21803 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21804 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21812 /* ARM mode loads relative to PC are also offset by +8. Unlike
21813 branches, the Windows CE loader *does* expect the relocation
21814 to take this into account. */
21815 case BFD_RELOC_ARM_OFFSET_IMM
:
21816 case BFD_RELOC_ARM_OFFSET_IMM8
:
21817 case BFD_RELOC_ARM_HWLITERAL
:
21818 case BFD_RELOC_ARM_LITERAL
:
21819 case BFD_RELOC_ARM_CP_OFF_IMM
:
21823 /* Other PC-relative relocations are un-offset. */
21829 static bfd_boolean flag_warn_syms
= TRUE
;
21832 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21834 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21835 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21836 does mean that the resulting code might be very confusing to the reader.
21837 Also this warning can be triggered if the user omits an operand before
21838 an immediate address, eg:
21842 GAS treats this as an assignment of the value of the symbol foo to a
21843 symbol LDR, and so (without this code) it will not issue any kind of
21844 warning or error message.
21846 Note - ARM instructions are case-insensitive but the strings in the hash
21847 table are all stored in lower case, so we must first ensure that name is
21849 if (flag_warn_syms
&& arm_ops_hsh
)
21851 char * nbuf
= strdup (name
);
21854 for (p
= nbuf
; *p
; p
++)
21856 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21858 static struct hash_control
* already_warned
= NULL
;
21860 if (already_warned
== NULL
)
21861 already_warned
= hash_new ();
21862 /* Only warn about the symbol once. To keep the code
21863 simple we let hash_insert do the lookup for us. */
21864 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21865 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21874 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21875 Otherwise we have no need to default values of symbols. */
21878 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21881 if (name
[0] == '_' && name
[1] == 'G'
21882 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21886 if (symbol_find (name
))
21887 as_bad (_("GOT already in the symbol table"));
21889 GOT_symbol
= symbol_new (name
, undefined_section
,
21890 (valueT
) 0, & zero_address_frag
);
21900 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21901 computed as two separate immediate values, added together. We
21902 already know that this value cannot be computed by just one ARM
21905 static unsigned int
21906 validate_immediate_twopart (unsigned int val
,
21907 unsigned int * highpart
)
21912 for (i
= 0; i
< 32; i
+= 2)
21913 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21919 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21921 else if (a
& 0xff0000)
21923 if (a
& 0xff000000)
21925 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21929 gas_assert (a
& 0xff000000);
21930 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21933 return (a
& 0xff) | (i
<< 7);
21940 validate_offset_imm (unsigned int val
, int hwse
)
21942 if ((hwse
&& val
> 255) || val
> 4095)
21947 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21948 negative immediate constant by altering the instruction. A bit of
21953 by inverting the second operand, and
21956 by negating the second operand. */
21959 negate_data_op (unsigned long * instruction
,
21960 unsigned long value
)
21963 unsigned long negated
, inverted
;
21965 negated
= encode_arm_immediate (-value
);
21966 inverted
= encode_arm_immediate (~value
);
21968 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21971 /* First negates. */
21972 case OPCODE_SUB
: /* ADD <-> SUB */
21973 new_inst
= OPCODE_ADD
;
21978 new_inst
= OPCODE_SUB
;
21982 case OPCODE_CMP
: /* CMP <-> CMN */
21983 new_inst
= OPCODE_CMN
;
21988 new_inst
= OPCODE_CMP
;
21992 /* Now Inverted ops. */
21993 case OPCODE_MOV
: /* MOV <-> MVN */
21994 new_inst
= OPCODE_MVN
;
21999 new_inst
= OPCODE_MOV
;
22003 case OPCODE_AND
: /* AND <-> BIC */
22004 new_inst
= OPCODE_BIC
;
22009 new_inst
= OPCODE_AND
;
22013 case OPCODE_ADC
: /* ADC <-> SBC */
22014 new_inst
= OPCODE_SBC
;
22019 new_inst
= OPCODE_ADC
;
22023 /* We cannot do anything. */
22028 if (value
== (unsigned) FAIL
)
22031 *instruction
&= OPCODE_MASK
;
22032 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22036 /* Like negate_data_op, but for Thumb-2. */
22038 static unsigned int
22039 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22043 unsigned int negated
, inverted
;
22045 negated
= encode_thumb32_immediate (-value
);
22046 inverted
= encode_thumb32_immediate (~value
);
22048 rd
= (*instruction
>> 8) & 0xf;
22049 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22052 /* ADD <-> SUB. Includes CMP <-> CMN. */
22053 case T2_OPCODE_SUB
:
22054 new_inst
= T2_OPCODE_ADD
;
22058 case T2_OPCODE_ADD
:
22059 new_inst
= T2_OPCODE_SUB
;
22063 /* ORR <-> ORN. Includes MOV <-> MVN. */
22064 case T2_OPCODE_ORR
:
22065 new_inst
= T2_OPCODE_ORN
;
22069 case T2_OPCODE_ORN
:
22070 new_inst
= T2_OPCODE_ORR
;
22074 /* AND <-> BIC. TST has no inverted equivalent. */
22075 case T2_OPCODE_AND
:
22076 new_inst
= T2_OPCODE_BIC
;
22083 case T2_OPCODE_BIC
:
22084 new_inst
= T2_OPCODE_AND
;
22089 case T2_OPCODE_ADC
:
22090 new_inst
= T2_OPCODE_SBC
;
22094 case T2_OPCODE_SBC
:
22095 new_inst
= T2_OPCODE_ADC
;
22099 /* We cannot do anything. */
22104 if (value
== (unsigned int)FAIL
)
22107 *instruction
&= T2_OPCODE_MASK
;
22108 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22112 /* Read a 32-bit thumb instruction from buf. */
22113 static unsigned long
22114 get_thumb32_insn (char * buf
)
22116 unsigned long insn
;
22117 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22118 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22124 /* We usually want to set the low bit on the address of thumb function
22125 symbols. In particular .word foo - . should have the low bit set.
22126 Generic code tries to fold the difference of two symbols to
22127 a constant. Prevent this and force a relocation when the first symbols
22128 is a thumb function. */
22131 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22133 if (op
== O_subtract
22134 && l
->X_op
== O_symbol
22135 && r
->X_op
== O_symbol
22136 && THUMB_IS_FUNC (l
->X_add_symbol
))
22138 l
->X_op
= O_subtract
;
22139 l
->X_op_symbol
= r
->X_add_symbol
;
22140 l
->X_add_number
-= r
->X_add_number
;
22144 /* Process as normal. */
22148 /* Encode Thumb2 unconditional branches and calls. The encoding
22149 for the 2 are identical for the immediate values. */
22152 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22154 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22157 addressT S
, I1
, I2
, lo
, hi
;
22159 S
= (value
>> 24) & 0x01;
22160 I1
= (value
>> 23) & 0x01;
22161 I2
= (value
>> 22) & 0x01;
22162 hi
= (value
>> 12) & 0x3ff;
22163 lo
= (value
>> 1) & 0x7ff;
22164 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22165 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22166 newval
|= (S
<< 10) | hi
;
22167 newval2
&= ~T2I1I2MASK
;
22168 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22170 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22174 md_apply_fix (fixS
* fixP
,
22178 offsetT value
= * valP
;
22180 unsigned int newimm
;
22181 unsigned long temp
;
22183 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22185 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22187 /* Note whether this will delete the relocation. */
22189 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22192 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22193 consistency with the behaviour on 32-bit hosts. Remember value
22195 value
&= 0xffffffff;
22196 value
^= 0x80000000;
22197 value
-= 0x80000000;
22200 fixP
->fx_addnumber
= value
;
22202 /* Same treatment for fixP->fx_offset. */
22203 fixP
->fx_offset
&= 0xffffffff;
22204 fixP
->fx_offset
^= 0x80000000;
22205 fixP
->fx_offset
-= 0x80000000;
22207 switch (fixP
->fx_r_type
)
22209 case BFD_RELOC_NONE
:
22210 /* This will need to go in the object file. */
22214 case BFD_RELOC_ARM_IMMEDIATE
:
22215 /* We claim that this fixup has been processed here,
22216 even if in fact we generate an error because we do
22217 not have a reloc for it, so tc_gen_reloc will reject it. */
22220 if (fixP
->fx_addsy
)
22222 const char *msg
= 0;
22224 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22225 msg
= _("undefined symbol %s used as an immediate value");
22226 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22227 msg
= _("symbol %s is in a different section");
22228 else if (S_IS_WEAK (fixP
->fx_addsy
))
22229 msg
= _("symbol %s is weak and may be overridden later");
22233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22234 msg
, S_GET_NAME (fixP
->fx_addsy
));
22239 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22241 /* If the offset is negative, we should use encoding A2 for ADR. */
22242 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22243 newimm
= negate_data_op (&temp
, value
);
22246 newimm
= encode_arm_immediate (value
);
22248 /* If the instruction will fail, see if we can fix things up by
22249 changing the opcode. */
22250 if (newimm
== (unsigned int) FAIL
)
22251 newimm
= negate_data_op (&temp
, value
);
22254 if (newimm
== (unsigned int) FAIL
)
22256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22257 _("invalid constant (%lx) after fixup"),
22258 (unsigned long) value
);
22262 newimm
|= (temp
& 0xfffff000);
22263 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22266 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22268 unsigned int highpart
= 0;
22269 unsigned int newinsn
= 0xe1a00000; /* nop. */
22271 if (fixP
->fx_addsy
)
22273 const char *msg
= 0;
22275 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22276 msg
= _("undefined symbol %s used as an immediate value");
22277 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22278 msg
= _("symbol %s is in a different section");
22279 else if (S_IS_WEAK (fixP
->fx_addsy
))
22280 msg
= _("symbol %s is weak and may be overridden later");
22284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22285 msg
, S_GET_NAME (fixP
->fx_addsy
));
22290 newimm
= encode_arm_immediate (value
);
22291 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22293 /* If the instruction will fail, see if we can fix things up by
22294 changing the opcode. */
22295 if (newimm
== (unsigned int) FAIL
22296 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22298 /* No ? OK - try using two ADD instructions to generate
22300 newimm
= validate_immediate_twopart (value
, & highpart
);
22302 /* Yes - then make sure that the second instruction is
22304 if (newimm
!= (unsigned int) FAIL
)
22306 /* Still No ? Try using a negated value. */
22307 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22308 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22309 /* Otherwise - give up. */
22312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22313 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22318 /* Replace the first operand in the 2nd instruction (which
22319 is the PC) with the destination register. We have
22320 already added in the PC in the first instruction and we
22321 do not want to do it again. */
22322 newinsn
&= ~ 0xf0000;
22323 newinsn
|= ((newinsn
& 0x0f000) << 4);
22326 newimm
|= (temp
& 0xfffff000);
22327 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22329 highpart
|= (newinsn
& 0xfffff000);
22330 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22334 case BFD_RELOC_ARM_OFFSET_IMM
:
22335 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22338 case BFD_RELOC_ARM_LITERAL
:
22344 if (validate_offset_imm (value
, 0) == FAIL
)
22346 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22348 _("invalid literal constant: pool needs to be closer"));
22350 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22351 _("bad immediate value for offset (%ld)"),
22356 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22358 newval
&= 0xfffff000;
22361 newval
&= 0xff7ff000;
22362 newval
|= value
| (sign
? INDEX_UP
: 0);
22364 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22367 case BFD_RELOC_ARM_OFFSET_IMM8
:
22368 case BFD_RELOC_ARM_HWLITERAL
:
22374 if (validate_offset_imm (value
, 1) == FAIL
)
22376 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22378 _("invalid literal constant: pool needs to be closer"));
22380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22381 _("bad immediate value for 8-bit offset (%ld)"),
22386 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22388 newval
&= 0xfffff0f0;
22391 newval
&= 0xff7ff0f0;
22392 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22394 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22397 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22398 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22400 _("bad immediate value for offset (%ld)"), (long) value
);
22403 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22405 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22408 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22409 /* This is a complicated relocation used for all varieties of Thumb32
22410 load/store instruction with immediate offset:
22412 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22413 *4, optional writeback(W)
22414 (doubleword load/store)
22416 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22417 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22418 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22419 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22420 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22422 Uppercase letters indicate bits that are already encoded at
22423 this point. Lowercase letters are our problem. For the
22424 second block of instructions, the secondary opcode nybble
22425 (bits 8..11) is present, and bit 23 is zero, even if this is
22426 a PC-relative operation. */
22427 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22429 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22431 if ((newval
& 0xf0000000) == 0xe0000000)
22433 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22435 newval
|= (1 << 23);
22438 if (value
% 4 != 0)
22440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22441 _("offset not a multiple of 4"));
22447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22448 _("offset out of range"));
22453 else if ((newval
& 0x000f0000) == 0x000f0000)
22455 /* PC-relative, 12-bit offset. */
22457 newval
|= (1 << 23);
22462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22463 _("offset out of range"));
22468 else if ((newval
& 0x00000100) == 0x00000100)
22470 /* Writeback: 8-bit, +/- offset. */
22472 newval
|= (1 << 9);
22477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22478 _("offset out of range"));
22483 else if ((newval
& 0x00000f00) == 0x00000e00)
22485 /* T-instruction: positive 8-bit offset. */
22486 if (value
< 0 || value
> 0xff)
22488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22489 _("offset out of range"));
22497 /* Positive 12-bit or negative 8-bit offset. */
22501 newval
|= (1 << 23);
22511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22512 _("offset out of range"));
22519 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22520 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22523 case BFD_RELOC_ARM_SHIFT_IMM
:
22524 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22525 if (((unsigned long) value
) > 32
22527 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22529 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22530 _("shift expression is too large"));
22535 /* Shifts of zero must be done as lsl. */
22537 else if (value
== 32)
22539 newval
&= 0xfffff07f;
22540 newval
|= (value
& 0x1f) << 7;
22541 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22544 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22545 case BFD_RELOC_ARM_T32_ADD_IMM
:
22546 case BFD_RELOC_ARM_T32_IMM12
:
22547 case BFD_RELOC_ARM_T32_ADD_PC12
:
22548 /* We claim that this fixup has been processed here,
22549 even if in fact we generate an error because we do
22550 not have a reloc for it, so tc_gen_reloc will reject it. */
22554 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22557 _("undefined symbol %s used as an immediate value"),
22558 S_GET_NAME (fixP
->fx_addsy
));
22562 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22564 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22567 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22568 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22570 newimm
= encode_thumb32_immediate (value
);
22571 if (newimm
== (unsigned int) FAIL
)
22572 newimm
= thumb32_negate_data_op (&newval
, value
);
22574 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22575 && newimm
== (unsigned int) FAIL
)
22577 /* Turn add/sum into addw/subw. */
22578 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22579 newval
= (newval
& 0xfeffffff) | 0x02000000;
22580 /* No flat 12-bit imm encoding for addsw/subsw. */
22581 if ((newval
& 0x00100000) == 0)
22583 /* 12 bit immediate for addw/subw. */
22587 newval
^= 0x00a00000;
22590 newimm
= (unsigned int) FAIL
;
22596 if (newimm
== (unsigned int)FAIL
)
22598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22599 _("invalid constant (%lx) after fixup"),
22600 (unsigned long) value
);
22604 newval
|= (newimm
& 0x800) << 15;
22605 newval
|= (newimm
& 0x700) << 4;
22606 newval
|= (newimm
& 0x0ff);
22608 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22609 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22612 case BFD_RELOC_ARM_SMC
:
22613 if (((unsigned long) value
) > 0xffff)
22614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22615 _("invalid smc expression"));
22616 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22617 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22618 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22621 case BFD_RELOC_ARM_HVC
:
22622 if (((unsigned long) value
) > 0xffff)
22623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22624 _("invalid hvc expression"));
22625 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22626 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22627 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22630 case BFD_RELOC_ARM_SWI
:
22631 if (fixP
->tc_fix_data
!= 0)
22633 if (((unsigned long) value
) > 0xff)
22634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22635 _("invalid swi expression"));
22636 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22638 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22642 if (((unsigned long) value
) > 0x00ffffff)
22643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22644 _("invalid swi expression"));
22645 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22647 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22651 case BFD_RELOC_ARM_MULTI
:
22652 if (((unsigned long) value
) > 0xffff)
22653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22654 _("invalid expression in load/store multiple"));
22655 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22656 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22660 case BFD_RELOC_ARM_PCREL_CALL
:
22662 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22664 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22665 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22666 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22667 /* Flip the bl to blx. This is a simple flip
22668 bit here because we generate PCREL_CALL for
22669 unconditional bls. */
22671 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22672 newval
= newval
| 0x10000000;
22673 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22679 goto arm_branch_common
;
22681 case BFD_RELOC_ARM_PCREL_JUMP
:
22682 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22684 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22685 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22686 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22688 /* This would map to a bl<cond>, b<cond>,
22689 b<always> to a Thumb function. We
22690 need to force a relocation for this particular
22692 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22696 case BFD_RELOC_ARM_PLT32
:
22698 case BFD_RELOC_ARM_PCREL_BRANCH
:
22700 goto arm_branch_common
;
22702 case BFD_RELOC_ARM_PCREL_BLX
:
22705 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22707 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22708 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22709 && ARM_IS_FUNC (fixP
->fx_addsy
))
22711 /* Flip the blx to a bl and warn. */
22712 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22713 newval
= 0xeb000000;
22714 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22715 _("blx to '%s' an ARM ISA state function changed to bl"),
22717 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22723 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22724 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22728 /* We are going to store value (shifted right by two) in the
22729 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22730 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22731 also be be clear. */
22733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22734 _("misaligned branch destination"));
22735 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22736 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22739 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22741 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22742 newval
|= (value
>> 2) & 0x00ffffff;
22743 /* Set the H bit on BLX instructions. */
22747 newval
|= 0x01000000;
22749 newval
&= ~0x01000000;
22751 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22755 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22756 /* CBZ can only branch forward. */
22758 /* Attempts to use CBZ to branch to the next instruction
22759 (which, strictly speaking, are prohibited) will be turned into
22762 FIXME: It may be better to remove the instruction completely and
22763 perform relaxation. */
22766 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22767 newval
= 0xbf00; /* NOP encoding T1 */
22768 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22775 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22777 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22778 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22779 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22784 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22785 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22788 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22790 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22791 newval
|= (value
& 0x1ff) >> 1;
22792 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22796 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22797 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22800 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22802 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22803 newval
|= (value
& 0xfff) >> 1;
22804 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22808 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22810 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22811 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22812 && ARM_IS_FUNC (fixP
->fx_addsy
)
22813 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22815 /* Force a relocation for a branch 20 bits wide. */
22818 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22820 _("conditional branch out of range"));
22822 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22825 addressT S
, J1
, J2
, lo
, hi
;
22827 S
= (value
& 0x00100000) >> 20;
22828 J2
= (value
& 0x00080000) >> 19;
22829 J1
= (value
& 0x00040000) >> 18;
22830 hi
= (value
& 0x0003f000) >> 12;
22831 lo
= (value
& 0x00000ffe) >> 1;
22833 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22834 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22835 newval
|= (S
<< 10) | hi
;
22836 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22838 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22842 case BFD_RELOC_THUMB_PCREL_BLX
:
22843 /* If there is a blx from a thumb state function to
22844 another thumb function flip this to a bl and warn
22848 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22849 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22850 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22852 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22853 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22854 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22856 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22857 newval
= newval
| 0x1000;
22858 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22859 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22864 goto thumb_bl_common
;
22866 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22867 /* A bl from Thumb state ISA to an internal ARM state function
22868 is converted to a blx. */
22870 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22871 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22872 && ARM_IS_FUNC (fixP
->fx_addsy
)
22873 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22875 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22876 newval
= newval
& ~0x1000;
22877 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22878 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22884 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22885 /* For a BLX instruction, make sure that the relocation is rounded up
22886 to a word boundary. This follows the semantics of the instruction
22887 which specifies that bit 1 of the target address will come from bit
22888 1 of the base address. */
22889 value
= (value
+ 3) & ~ 3;
22892 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22893 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22894 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22897 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22899 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
22900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22901 else if ((value
& ~0x1ffffff)
22902 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22904 _("Thumb2 branch out of range"));
22907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22908 encode_thumb2_b_bl_offset (buf
, value
);
22912 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22913 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22916 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22917 encode_thumb2_b_bl_offset (buf
, value
);
22922 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22927 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22928 md_number_to_chars (buf
, value
, 2);
22932 case BFD_RELOC_ARM_TLS_CALL
:
22933 case BFD_RELOC_ARM_THM_TLS_CALL
:
22934 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22935 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22936 case BFD_RELOC_ARM_TLS_GOTDESC
:
22937 case BFD_RELOC_ARM_TLS_GD32
:
22938 case BFD_RELOC_ARM_TLS_LE32
:
22939 case BFD_RELOC_ARM_TLS_IE32
:
22940 case BFD_RELOC_ARM_TLS_LDM32
:
22941 case BFD_RELOC_ARM_TLS_LDO32
:
22942 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22945 case BFD_RELOC_ARM_GOT32
:
22946 case BFD_RELOC_ARM_GOTOFF
:
22949 case BFD_RELOC_ARM_GOT_PREL
:
22950 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22951 md_number_to_chars (buf
, value
, 4);
22954 case BFD_RELOC_ARM_TARGET2
:
22955 /* TARGET2 is not partial-inplace, so we need to write the
22956 addend here for REL targets, because it won't be written out
22957 during reloc processing later. */
22958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22959 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22963 case BFD_RELOC_RVA
:
22965 case BFD_RELOC_ARM_TARGET1
:
22966 case BFD_RELOC_ARM_ROSEGREL32
:
22967 case BFD_RELOC_ARM_SBREL32
:
22968 case BFD_RELOC_32_PCREL
:
22970 case BFD_RELOC_32_SECREL
:
22972 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22974 /* For WinCE we only do this for pcrel fixups. */
22975 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22977 md_number_to_chars (buf
, value
, 4);
22981 case BFD_RELOC_ARM_PREL31
:
22982 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22984 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22985 if ((value
^ (value
>> 1)) & 0x40000000)
22987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22988 _("rel31 relocation overflow"));
22990 newval
|= value
& 0x7fffffff;
22991 md_number_to_chars (buf
, newval
, 4);
22996 case BFD_RELOC_ARM_CP_OFF_IMM
:
22997 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22998 if (value
< -1023 || value
> 1023 || (value
& 3))
22999 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23000 _("co-processor offset out of range"));
23005 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23006 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23007 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23009 newval
= get_thumb32_insn (buf
);
23011 newval
&= 0xffffff00;
23014 newval
&= 0xff7fff00;
23015 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23017 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23018 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23019 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23021 put_thumb32_insn (buf
, newval
);
23024 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23025 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23026 if (value
< -255 || value
> 255)
23027 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23028 _("co-processor offset out of range"));
23030 goto cp_off_common
;
23032 case BFD_RELOC_ARM_THUMB_OFFSET
:
23033 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23034 /* Exactly what ranges, and where the offset is inserted depends
23035 on the type of instruction, we can establish this from the
23037 switch (newval
>> 12)
23039 case 4: /* PC load. */
23040 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23041 forced to zero for these loads; md_pcrel_from has already
23042 compensated for this. */
23044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23045 _("invalid offset, target not word aligned (0x%08lX)"),
23046 (((unsigned long) fixP
->fx_frag
->fr_address
23047 + (unsigned long) fixP
->fx_where
) & ~3)
23048 + (unsigned long) value
);
23050 if (value
& ~0x3fc)
23051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23052 _("invalid offset, value too big (0x%08lX)"),
23055 newval
|= value
>> 2;
23058 case 9: /* SP load/store. */
23059 if (value
& ~0x3fc)
23060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23061 _("invalid offset, value too big (0x%08lX)"),
23063 newval
|= value
>> 2;
23066 case 6: /* Word load/store. */
23068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23069 _("invalid offset, value too big (0x%08lX)"),
23071 newval
|= value
<< 4; /* 6 - 2. */
23074 case 7: /* Byte load/store. */
23076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23077 _("invalid offset, value too big (0x%08lX)"),
23079 newval
|= value
<< 6;
23082 case 8: /* Halfword load/store. */
23084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23085 _("invalid offset, value too big (0x%08lX)"),
23087 newval
|= value
<< 5; /* 6 - 1. */
23091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23092 "Unable to process relocation for thumb opcode: %lx",
23093 (unsigned long) newval
);
23096 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23099 case BFD_RELOC_ARM_THUMB_ADD
:
23100 /* This is a complicated relocation, since we use it for all of
23101 the following immediate relocations:
23105 9bit ADD/SUB SP word-aligned
23106 10bit ADD PC/SP word-aligned
23108 The type of instruction being processed is encoded in the
23115 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23117 int rd
= (newval
>> 4) & 0xf;
23118 int rs
= newval
& 0xf;
23119 int subtract
= !!(newval
& 0x8000);
23121 /* Check for HI regs, only very restricted cases allowed:
23122 Adjusting SP, and using PC or SP to get an address. */
23123 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23124 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23126 _("invalid Hi register with immediate"));
23128 /* If value is negative, choose the opposite instruction. */
23132 subtract
= !subtract
;
23134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23135 _("immediate value out of range"));
23140 if (value
& ~0x1fc)
23141 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23142 _("invalid immediate for stack address calculation"));
23143 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23144 newval
|= value
>> 2;
23146 else if (rs
== REG_PC
|| rs
== REG_SP
)
23148 /* PR gas/18541. If the addition is for a defined symbol
23149 within range of an ADR instruction then accept it. */
23152 && fixP
->fx_addsy
!= NULL
)
23156 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23157 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23158 || S_IS_WEAK (fixP
->fx_addsy
))
23160 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23161 _("address calculation needs a strongly defined nearby symbol"));
23165 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23167 /* Round up to the next 4-byte boundary. */
23172 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23177 _("symbol too far away"));
23187 if (subtract
|| value
& ~0x3fc)
23188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23189 _("invalid immediate for address calculation (value = 0x%08lX)"),
23190 (unsigned long) (subtract
? - value
: value
));
23191 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23193 newval
|= value
>> 2;
23198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23199 _("immediate value out of range"));
23200 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23201 newval
|= (rd
<< 8) | value
;
23206 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23207 _("immediate value out of range"));
23208 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23209 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23212 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23215 case BFD_RELOC_ARM_THUMB_IMM
:
23216 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23217 if (value
< 0 || value
> 255)
23218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23219 _("invalid immediate: %ld is out of range"),
23222 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23225 case BFD_RELOC_ARM_THUMB_SHIFT
:
23226 /* 5bit shift value (0..32). LSL cannot take 32. */
23227 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23228 temp
= newval
& 0xf800;
23229 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23231 _("invalid shift value: %ld"), (long) value
);
23232 /* Shifts of zero must be encoded as LSL. */
23234 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23235 /* Shifts of 32 are encoded as zero. */
23236 else if (value
== 32)
23238 newval
|= value
<< 6;
23239 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23242 case BFD_RELOC_VTABLE_INHERIT
:
23243 case BFD_RELOC_VTABLE_ENTRY
:
23247 case BFD_RELOC_ARM_MOVW
:
23248 case BFD_RELOC_ARM_MOVT
:
23249 case BFD_RELOC_ARM_THUMB_MOVW
:
23250 case BFD_RELOC_ARM_THUMB_MOVT
:
23251 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23253 /* REL format relocations are limited to a 16-bit addend. */
23254 if (!fixP
->fx_done
)
23256 if (value
< -0x8000 || value
> 0x7fff)
23257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23258 _("offset out of range"));
23260 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23261 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23266 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23267 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23269 newval
= get_thumb32_insn (buf
);
23270 newval
&= 0xfbf08f00;
23271 newval
|= (value
& 0xf000) << 4;
23272 newval
|= (value
& 0x0800) << 15;
23273 newval
|= (value
& 0x0700) << 4;
23274 newval
|= (value
& 0x00ff);
23275 put_thumb32_insn (buf
, newval
);
23279 newval
= md_chars_to_number (buf
, 4);
23280 newval
&= 0xfff0f000;
23281 newval
|= value
& 0x0fff;
23282 newval
|= (value
& 0xf000) << 4;
23283 md_number_to_chars (buf
, newval
, 4);
23288 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23289 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23290 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23291 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23292 gas_assert (!fixP
->fx_done
);
23295 bfd_boolean is_mov
;
23296 bfd_vma encoded_addend
= value
;
23298 /* Check that addend can be encoded in instruction. */
23299 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23300 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23301 _("the offset 0x%08lX is not representable"),
23302 (unsigned long) encoded_addend
);
23304 /* Extract the instruction. */
23305 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23306 is_mov
= (insn
& 0xf800) == 0x2000;
23311 if (!seg
->use_rela_p
)
23312 insn
|= encoded_addend
;
23318 /* Extract the instruction. */
23319 /* Encoding is the following
23324 /* The following conditions must be true :
23329 rd
= (insn
>> 4) & 0xf;
23331 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23333 _("Unable to process relocation for thumb opcode: %lx"),
23334 (unsigned long) insn
);
23336 /* Encode as ADD immediate8 thumb 1 code. */
23337 insn
= 0x3000 | (rd
<< 8);
23339 /* Place the encoded addend into the first 8 bits of the
23341 if (!seg
->use_rela_p
)
23342 insn
|= encoded_addend
;
23345 /* Update the instruction. */
23346 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23350 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23351 case BFD_RELOC_ARM_ALU_PC_G0
:
23352 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23353 case BFD_RELOC_ARM_ALU_PC_G1
:
23354 case BFD_RELOC_ARM_ALU_PC_G2
:
23355 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23356 case BFD_RELOC_ARM_ALU_SB_G0
:
23357 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23358 case BFD_RELOC_ARM_ALU_SB_G1
:
23359 case BFD_RELOC_ARM_ALU_SB_G2
:
23360 gas_assert (!fixP
->fx_done
);
23361 if (!seg
->use_rela_p
)
23364 bfd_vma encoded_addend
;
23365 bfd_vma addend_abs
= abs (value
);
23367 /* Check that the absolute value of the addend can be
23368 expressed as an 8-bit constant plus a rotation. */
23369 encoded_addend
= encode_arm_immediate (addend_abs
);
23370 if (encoded_addend
== (unsigned int) FAIL
)
23371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23372 _("the offset 0x%08lX is not representable"),
23373 (unsigned long) addend_abs
);
23375 /* Extract the instruction. */
23376 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23378 /* If the addend is positive, use an ADD instruction.
23379 Otherwise use a SUB. Take care not to destroy the S bit. */
23380 insn
&= 0xff1fffff;
23386 /* Place the encoded addend into the first 12 bits of the
23388 insn
&= 0xfffff000;
23389 insn
|= encoded_addend
;
23391 /* Update the instruction. */
23392 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23396 case BFD_RELOC_ARM_LDR_PC_G0
:
23397 case BFD_RELOC_ARM_LDR_PC_G1
:
23398 case BFD_RELOC_ARM_LDR_PC_G2
:
23399 case BFD_RELOC_ARM_LDR_SB_G0
:
23400 case BFD_RELOC_ARM_LDR_SB_G1
:
23401 case BFD_RELOC_ARM_LDR_SB_G2
:
23402 gas_assert (!fixP
->fx_done
);
23403 if (!seg
->use_rela_p
)
23406 bfd_vma addend_abs
= abs (value
);
23408 /* Check that the absolute value of the addend can be
23409 encoded in 12 bits. */
23410 if (addend_abs
>= 0x1000)
23411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23412 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23413 (unsigned long) addend_abs
);
23415 /* Extract the instruction. */
23416 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23418 /* If the addend is negative, clear bit 23 of the instruction.
23419 Otherwise set it. */
23421 insn
&= ~(1 << 23);
23425 /* Place the absolute value of the addend into the first 12 bits
23426 of the instruction. */
23427 insn
&= 0xfffff000;
23428 insn
|= addend_abs
;
23430 /* Update the instruction. */
23431 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23435 case BFD_RELOC_ARM_LDRS_PC_G0
:
23436 case BFD_RELOC_ARM_LDRS_PC_G1
:
23437 case BFD_RELOC_ARM_LDRS_PC_G2
:
23438 case BFD_RELOC_ARM_LDRS_SB_G0
:
23439 case BFD_RELOC_ARM_LDRS_SB_G1
:
23440 case BFD_RELOC_ARM_LDRS_SB_G2
:
23441 gas_assert (!fixP
->fx_done
);
23442 if (!seg
->use_rela_p
)
23445 bfd_vma addend_abs
= abs (value
);
23447 /* Check that the absolute value of the addend can be
23448 encoded in 8 bits. */
23449 if (addend_abs
>= 0x100)
23450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23451 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23452 (unsigned long) addend_abs
);
23454 /* Extract the instruction. */
23455 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23457 /* If the addend is negative, clear bit 23 of the instruction.
23458 Otherwise set it. */
23460 insn
&= ~(1 << 23);
23464 /* Place the first four bits of the absolute value of the addend
23465 into the first 4 bits of the instruction, and the remaining
23466 four into bits 8 .. 11. */
23467 insn
&= 0xfffff0f0;
23468 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23470 /* Update the instruction. */
23471 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23475 case BFD_RELOC_ARM_LDC_PC_G0
:
23476 case BFD_RELOC_ARM_LDC_PC_G1
:
23477 case BFD_RELOC_ARM_LDC_PC_G2
:
23478 case BFD_RELOC_ARM_LDC_SB_G0
:
23479 case BFD_RELOC_ARM_LDC_SB_G1
:
23480 case BFD_RELOC_ARM_LDC_SB_G2
:
23481 gas_assert (!fixP
->fx_done
);
23482 if (!seg
->use_rela_p
)
23485 bfd_vma addend_abs
= abs (value
);
23487 /* Check that the absolute value of the addend is a multiple of
23488 four and, when divided by four, fits in 8 bits. */
23489 if (addend_abs
& 0x3)
23490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23491 _("bad offset 0x%08lX (must be word-aligned)"),
23492 (unsigned long) addend_abs
);
23494 if ((addend_abs
>> 2) > 0xff)
23495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23496 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23497 (unsigned long) addend_abs
);
23499 /* Extract the instruction. */
23500 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23502 /* If the addend is negative, clear bit 23 of the instruction.
23503 Otherwise set it. */
23505 insn
&= ~(1 << 23);
23509 /* Place the addend (divided by four) into the first eight
23510 bits of the instruction. */
23511 insn
&= 0xfffffff0;
23512 insn
|= addend_abs
>> 2;
23514 /* Update the instruction. */
23515 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23519 case BFD_RELOC_ARM_V4BX
:
23520 /* This will need to go in the object file. */
23524 case BFD_RELOC_UNUSED
:
23526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23527 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23531 /* Translate internal representation of relocation info to BFD target
23535 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23538 bfd_reloc_code_real_type code
;
23540 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23542 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23543 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23544 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23546 if (fixp
->fx_pcrel
)
23548 if (section
->use_rela_p
)
23549 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23551 fixp
->fx_offset
= reloc
->address
;
23553 reloc
->addend
= fixp
->fx_offset
;
23555 switch (fixp
->fx_r_type
)
23558 if (fixp
->fx_pcrel
)
23560 code
= BFD_RELOC_8_PCREL
;
23565 if (fixp
->fx_pcrel
)
23567 code
= BFD_RELOC_16_PCREL
;
23572 if (fixp
->fx_pcrel
)
23574 code
= BFD_RELOC_32_PCREL
;
23578 case BFD_RELOC_ARM_MOVW
:
23579 if (fixp
->fx_pcrel
)
23581 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23585 case BFD_RELOC_ARM_MOVT
:
23586 if (fixp
->fx_pcrel
)
23588 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23592 case BFD_RELOC_ARM_THUMB_MOVW
:
23593 if (fixp
->fx_pcrel
)
23595 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23599 case BFD_RELOC_ARM_THUMB_MOVT
:
23600 if (fixp
->fx_pcrel
)
23602 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23606 case BFD_RELOC_NONE
:
23607 case BFD_RELOC_ARM_PCREL_BRANCH
:
23608 case BFD_RELOC_ARM_PCREL_BLX
:
23609 case BFD_RELOC_RVA
:
23610 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23611 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23612 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23613 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23614 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23615 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23616 case BFD_RELOC_VTABLE_ENTRY
:
23617 case BFD_RELOC_VTABLE_INHERIT
:
23619 case BFD_RELOC_32_SECREL
:
23621 code
= fixp
->fx_r_type
;
23624 case BFD_RELOC_THUMB_PCREL_BLX
:
23626 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23627 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23630 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23633 case BFD_RELOC_ARM_LITERAL
:
23634 case BFD_RELOC_ARM_HWLITERAL
:
23635 /* If this is called then the a literal has
23636 been referenced across a section boundary. */
23637 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23638 _("literal referenced across section boundary"));
23642 case BFD_RELOC_ARM_TLS_CALL
:
23643 case BFD_RELOC_ARM_THM_TLS_CALL
:
23644 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23645 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23646 case BFD_RELOC_ARM_GOT32
:
23647 case BFD_RELOC_ARM_GOTOFF
:
23648 case BFD_RELOC_ARM_GOT_PREL
:
23649 case BFD_RELOC_ARM_PLT32
:
23650 case BFD_RELOC_ARM_TARGET1
:
23651 case BFD_RELOC_ARM_ROSEGREL32
:
23652 case BFD_RELOC_ARM_SBREL32
:
23653 case BFD_RELOC_ARM_PREL31
:
23654 case BFD_RELOC_ARM_TARGET2
:
23655 case BFD_RELOC_ARM_TLS_LDO32
:
23656 case BFD_RELOC_ARM_PCREL_CALL
:
23657 case BFD_RELOC_ARM_PCREL_JUMP
:
23658 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23659 case BFD_RELOC_ARM_ALU_PC_G0
:
23660 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23661 case BFD_RELOC_ARM_ALU_PC_G1
:
23662 case BFD_RELOC_ARM_ALU_PC_G2
:
23663 case BFD_RELOC_ARM_LDR_PC_G0
:
23664 case BFD_RELOC_ARM_LDR_PC_G1
:
23665 case BFD_RELOC_ARM_LDR_PC_G2
:
23666 case BFD_RELOC_ARM_LDRS_PC_G0
:
23667 case BFD_RELOC_ARM_LDRS_PC_G1
:
23668 case BFD_RELOC_ARM_LDRS_PC_G2
:
23669 case BFD_RELOC_ARM_LDC_PC_G0
:
23670 case BFD_RELOC_ARM_LDC_PC_G1
:
23671 case BFD_RELOC_ARM_LDC_PC_G2
:
23672 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23673 case BFD_RELOC_ARM_ALU_SB_G0
:
23674 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23675 case BFD_RELOC_ARM_ALU_SB_G1
:
23676 case BFD_RELOC_ARM_ALU_SB_G2
:
23677 case BFD_RELOC_ARM_LDR_SB_G0
:
23678 case BFD_RELOC_ARM_LDR_SB_G1
:
23679 case BFD_RELOC_ARM_LDR_SB_G2
:
23680 case BFD_RELOC_ARM_LDRS_SB_G0
:
23681 case BFD_RELOC_ARM_LDRS_SB_G1
:
23682 case BFD_RELOC_ARM_LDRS_SB_G2
:
23683 case BFD_RELOC_ARM_LDC_SB_G0
:
23684 case BFD_RELOC_ARM_LDC_SB_G1
:
23685 case BFD_RELOC_ARM_LDC_SB_G2
:
23686 case BFD_RELOC_ARM_V4BX
:
23687 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23688 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23689 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23690 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23691 code
= fixp
->fx_r_type
;
23694 case BFD_RELOC_ARM_TLS_GOTDESC
:
23695 case BFD_RELOC_ARM_TLS_GD32
:
23696 case BFD_RELOC_ARM_TLS_LE32
:
23697 case BFD_RELOC_ARM_TLS_IE32
:
23698 case BFD_RELOC_ARM_TLS_LDM32
:
23699 /* BFD will include the symbol's address in the addend.
23700 But we don't want that, so subtract it out again here. */
23701 if (!S_IS_COMMON (fixp
->fx_addsy
))
23702 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23703 code
= fixp
->fx_r_type
;
23707 case BFD_RELOC_ARM_IMMEDIATE
:
23708 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23709 _("internal relocation (type: IMMEDIATE) not fixed up"));
23712 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23713 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23714 _("ADRL used for a symbol not defined in the same file"));
23717 case BFD_RELOC_ARM_OFFSET_IMM
:
23718 if (section
->use_rela_p
)
23720 code
= fixp
->fx_r_type
;
23724 if (fixp
->fx_addsy
!= NULL
23725 && !S_IS_DEFINED (fixp
->fx_addsy
)
23726 && S_IS_LOCAL (fixp
->fx_addsy
))
23728 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23729 _("undefined local label `%s'"),
23730 S_GET_NAME (fixp
->fx_addsy
));
23734 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23735 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23742 switch (fixp
->fx_r_type
)
23744 case BFD_RELOC_NONE
: type
= "NONE"; break;
23745 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23746 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23747 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23748 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23749 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23750 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23751 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23752 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23753 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23754 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23755 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23756 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23757 default: type
= _("<unknown>"); break;
23759 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23760 _("cannot represent %s relocation in this object file format"),
23767 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23769 && fixp
->fx_addsy
== GOT_symbol
)
23771 code
= BFD_RELOC_ARM_GOTPC
;
23772 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23776 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23778 if (reloc
->howto
== NULL
)
23780 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23781 _("cannot represent %s relocation in this object file format"),
23782 bfd_get_reloc_code_name (code
));
23786 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23787 vtable entry to be used in the relocation's section offset. */
23788 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23789 reloc
->address
= fixp
->fx_offset
;
23794 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23797 cons_fix_new_arm (fragS
* frag
,
23801 bfd_reloc_code_real_type reloc
)
23806 FIXME: @@ Should look at CPU word size. */
23810 reloc
= BFD_RELOC_8
;
23813 reloc
= BFD_RELOC_16
;
23817 reloc
= BFD_RELOC_32
;
23820 reloc
= BFD_RELOC_64
;
23825 if (exp
->X_op
== O_secrel
)
23827 exp
->X_op
= O_symbol
;
23828 reloc
= BFD_RELOC_32_SECREL
;
23832 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23835 #if defined (OBJ_COFF)
23837 arm_validate_fix (fixS
* fixP
)
23839 /* If the destination of the branch is a defined symbol which does not have
23840 the THUMB_FUNC attribute, then we must be calling a function which has
23841 the (interfacearm) attribute. We look for the Thumb entry point to that
23842 function and change the branch to refer to that function instead. */
23843 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23844 && fixP
->fx_addsy
!= NULL
23845 && S_IS_DEFINED (fixP
->fx_addsy
)
23846 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23848 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23855 arm_force_relocation (struct fix
* fixp
)
23857 #if defined (OBJ_COFF) && defined (TE_PE)
23858 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23862 /* In case we have a call or a branch to a function in ARM ISA mode from
23863 a thumb function or vice-versa force the relocation. These relocations
23864 are cleared off for some cores that might have blx and simple transformations
23868 switch (fixp
->fx_r_type
)
23870 case BFD_RELOC_ARM_PCREL_JUMP
:
23871 case BFD_RELOC_ARM_PCREL_CALL
:
23872 case BFD_RELOC_THUMB_PCREL_BLX
:
23873 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23877 case BFD_RELOC_ARM_PCREL_BLX
:
23878 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23879 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23880 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23881 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23890 /* Resolve these relocations even if the symbol is extern or weak.
23891 Technically this is probably wrong due to symbol preemption.
23892 In practice these relocations do not have enough range to be useful
23893 at dynamic link time, and some code (e.g. in the Linux kernel)
23894 expects these references to be resolved. */
23895 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23896 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23897 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23898 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23899 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23900 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23901 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23902 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23903 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23904 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23905 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23906 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23907 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23908 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23911 /* Always leave these relocations for the linker. */
23912 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23913 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23914 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23917 /* Always generate relocations against function symbols. */
23918 if (fixp
->fx_r_type
== BFD_RELOC_32
23920 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23923 return generic_force_reloc (fixp
);
23926 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23927 /* Relocations against function names must be left unadjusted,
23928 so that the linker can use this information to generate interworking
23929 stubs. The MIPS version of this function
23930 also prevents relocations that are mips-16 specific, but I do not
23931 know why it does this.
23934 There is one other problem that ought to be addressed here, but
23935 which currently is not: Taking the address of a label (rather
23936 than a function) and then later jumping to that address. Such
23937 addresses also ought to have their bottom bit set (assuming that
23938 they reside in Thumb code), but at the moment they will not. */
23941 arm_fix_adjustable (fixS
* fixP
)
23943 if (fixP
->fx_addsy
== NULL
)
23946 /* Preserve relocations against symbols with function type. */
23947 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23950 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23951 && fixP
->fx_subsy
== NULL
)
23954 /* We need the symbol name for the VTABLE entries. */
23955 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23956 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23959 /* Don't allow symbols to be discarded on GOT related relocs. */
23960 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23961 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23962 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23963 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23964 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23965 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23966 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23967 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23968 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23969 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23970 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23971 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23972 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23973 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23976 /* Similarly for group relocations. */
23977 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23978 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23979 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23982 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23983 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23984 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23985 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23986 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23987 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23988 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23989 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23990 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23993 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
23994 offsets, so keep these symbols. */
23995 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
23996 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24001 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24006 elf32_arm_target_format (void)
24009 return (target_big_endian
24010 ? "elf32-bigarm-symbian"
24011 : "elf32-littlearm-symbian");
24012 #elif defined (TE_VXWORKS)
24013 return (target_big_endian
24014 ? "elf32-bigarm-vxworks"
24015 : "elf32-littlearm-vxworks");
24016 #elif defined (TE_NACL)
24017 return (target_big_endian
24018 ? "elf32-bigarm-nacl"
24019 : "elf32-littlearm-nacl");
24021 if (target_big_endian
)
24022 return "elf32-bigarm";
24024 return "elf32-littlearm";
24029 armelf_frob_symbol (symbolS
* symp
,
24032 elf_frob_symbol (symp
, puntp
);
24036 /* MD interface: Finalization. */
24041 literal_pool
* pool
;
24043 /* Ensure that all the IT blocks are properly closed. */
24044 check_it_blocks_finished ();
24046 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24048 /* Put it at the end of the relevant section. */
24049 subseg_set (pool
->section
, pool
->sub_section
);
24051 arm_elf_change_section ();
24058 /* Remove any excess mapping symbols generated for alignment frags in
24059 SEC. We may have created a mapping symbol before a zero byte
24060 alignment; remove it if there's a mapping symbol after the
24063 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24064 void *dummy ATTRIBUTE_UNUSED
)
24066 segment_info_type
*seginfo
= seg_info (sec
);
24069 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24072 for (fragp
= seginfo
->frchainP
->frch_root
;
24074 fragp
= fragp
->fr_next
)
24076 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24077 fragS
*next
= fragp
->fr_next
;
24079 /* Variable-sized frags have been converted to fixed size by
24080 this point. But if this was variable-sized to start with,
24081 there will be a fixed-size frag after it. So don't handle
24083 if (sym
== NULL
|| next
== NULL
)
24086 if (S_GET_VALUE (sym
) < next
->fr_address
)
24087 /* Not at the end of this frag. */
24089 know (S_GET_VALUE (sym
) == next
->fr_address
);
24093 if (next
->tc_frag_data
.first_map
!= NULL
)
24095 /* Next frag starts with a mapping symbol. Discard this
24097 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24101 if (next
->fr_next
== NULL
)
24103 /* This mapping symbol is at the end of the section. Discard
24105 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24106 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24110 /* As long as we have empty frags without any mapping symbols,
24112 /* If the next frag is non-empty and does not start with a
24113 mapping symbol, then this mapping symbol is required. */
24114 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24117 next
= next
->fr_next
;
24119 while (next
!= NULL
);
24124 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24128 arm_adjust_symtab (void)
24133 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24135 if (ARM_IS_THUMB (sym
))
24137 if (THUMB_IS_FUNC (sym
))
24139 /* Mark the symbol as a Thumb function. */
24140 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24141 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24142 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24144 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24145 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24147 as_bad (_("%s: unexpected function type: %d"),
24148 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24150 else switch (S_GET_STORAGE_CLASS (sym
))
24153 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24156 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24159 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24167 if (ARM_IS_INTERWORK (sym
))
24168 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24175 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24177 if (ARM_IS_THUMB (sym
))
24179 elf_symbol_type
* elf_sym
;
24181 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24182 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24184 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24185 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24187 /* If it's a .thumb_func, declare it as so,
24188 otherwise tag label as .code 16. */
24189 if (THUMB_IS_FUNC (sym
))
24190 elf_sym
->internal_elf_sym
.st_target_internal
24191 = ST_BRANCH_TO_THUMB
;
24192 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24193 elf_sym
->internal_elf_sym
.st_info
=
24194 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24199 /* Remove any overlapping mapping symbols generated by alignment frags. */
24200 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24201 /* Now do generic ELF adjustments. */
24202 elf_adjust_symtab ();
24206 /* MD interface: Initialization. */
24209 set_constant_flonums (void)
24213 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24214 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24218 /* Auto-select Thumb mode if it's the only available instruction set for the
24219 given architecture. */
24222 autoselect_thumb_from_cpu_variant (void)
24224 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24225 opcode_select (16);
24234 if ( (arm_ops_hsh
= hash_new ()) == NULL
24235 || (arm_cond_hsh
= hash_new ()) == NULL
24236 || (arm_shift_hsh
= hash_new ()) == NULL
24237 || (arm_psr_hsh
= hash_new ()) == NULL
24238 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24239 || (arm_reg_hsh
= hash_new ()) == NULL
24240 || (arm_reloc_hsh
= hash_new ()) == NULL
24241 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24242 as_fatal (_("virtual memory exhausted"));
24244 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24245 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24246 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24247 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24248 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24249 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24250 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24251 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24252 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24253 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24254 (void *) (v7m_psrs
+ i
));
24255 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24256 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24258 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24260 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24261 (void *) (barrier_opt_names
+ i
));
24263 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24265 struct reloc_entry
* entry
= reloc_names
+ i
;
24267 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24268 /* This makes encode_branch() use the EABI versions of this relocation. */
24269 entry
->reloc
= BFD_RELOC_UNUSED
;
24271 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24275 set_constant_flonums ();
24277 /* Set the cpu variant based on the command-line options. We prefer
24278 -mcpu= over -march= if both are set (as for GCC); and we prefer
24279 -mfpu= over any other way of setting the floating point unit.
24280 Use of legacy options with new options are faulted. */
24283 if (mcpu_cpu_opt
|| march_cpu_opt
)
24284 as_bad (_("use of old and new-style options to set CPU type"));
24286 mcpu_cpu_opt
= legacy_cpu
;
24288 else if (!mcpu_cpu_opt
)
24289 mcpu_cpu_opt
= march_cpu_opt
;
24294 as_bad (_("use of old and new-style options to set FPU type"));
24296 mfpu_opt
= legacy_fpu
;
24298 else if (!mfpu_opt
)
24300 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24301 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24302 /* Some environments specify a default FPU. If they don't, infer it
24303 from the processor. */
24305 mfpu_opt
= mcpu_fpu_opt
;
24307 mfpu_opt
= march_fpu_opt
;
24309 mfpu_opt
= &fpu_default
;
24315 if (mcpu_cpu_opt
!= NULL
)
24316 mfpu_opt
= &fpu_default
;
24317 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24318 mfpu_opt
= &fpu_arch_vfp_v2
;
24320 mfpu_opt
= &fpu_arch_fpa
;
24326 mcpu_cpu_opt
= &cpu_default
;
24327 selected_cpu
= cpu_default
;
24329 else if (no_cpu_selected ())
24330 selected_cpu
= cpu_default
;
24333 selected_cpu
= *mcpu_cpu_opt
;
24335 mcpu_cpu_opt
= &arm_arch_any
;
24338 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24340 autoselect_thumb_from_cpu_variant ();
24342 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24344 #if defined OBJ_COFF || defined OBJ_ELF
24346 unsigned int flags
= 0;
24348 #if defined OBJ_ELF
24349 flags
= meabi_flags
;
24351 switch (meabi_flags
)
24353 case EF_ARM_EABI_UNKNOWN
:
24355 /* Set the flags in the private structure. */
24356 if (uses_apcs_26
) flags
|= F_APCS26
;
24357 if (support_interwork
) flags
|= F_INTERWORK
;
24358 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24359 if (pic_code
) flags
|= F_PIC
;
24360 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24361 flags
|= F_SOFT_FLOAT
;
24363 switch (mfloat_abi_opt
)
24365 case ARM_FLOAT_ABI_SOFT
:
24366 case ARM_FLOAT_ABI_SOFTFP
:
24367 flags
|= F_SOFT_FLOAT
;
24370 case ARM_FLOAT_ABI_HARD
:
24371 if (flags
& F_SOFT_FLOAT
)
24372 as_bad (_("hard-float conflicts with specified fpu"));
24376 /* Using pure-endian doubles (even if soft-float). */
24377 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24378 flags
|= F_VFP_FLOAT
;
24380 #if defined OBJ_ELF
24381 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24382 flags
|= EF_ARM_MAVERICK_FLOAT
;
24385 case EF_ARM_EABI_VER4
:
24386 case EF_ARM_EABI_VER5
:
24387 /* No additional flags to set. */
24394 bfd_set_private_flags (stdoutput
, flags
);
24396 /* We have run out flags in the COFF header to encode the
24397 status of ATPCS support, so instead we create a dummy,
24398 empty, debug section called .arm.atpcs. */
24403 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24407 bfd_set_section_flags
24408 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24409 bfd_set_section_size (stdoutput
, sec
, 0);
24410 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24416 /* Record the CPU type as well. */
24417 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24418 mach
= bfd_mach_arm_iWMMXt2
;
24419 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24420 mach
= bfd_mach_arm_iWMMXt
;
24421 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24422 mach
= bfd_mach_arm_XScale
;
24423 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24424 mach
= bfd_mach_arm_ep9312
;
24425 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24426 mach
= bfd_mach_arm_5TE
;
24427 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24429 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24430 mach
= bfd_mach_arm_5T
;
24432 mach
= bfd_mach_arm_5
;
24434 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24436 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24437 mach
= bfd_mach_arm_4T
;
24439 mach
= bfd_mach_arm_4
;
24441 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24442 mach
= bfd_mach_arm_3M
;
24443 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24444 mach
= bfd_mach_arm_3
;
24445 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24446 mach
= bfd_mach_arm_2a
;
24447 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24448 mach
= bfd_mach_arm_2
;
24450 mach
= bfd_mach_arm_unknown
;
24452 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24455 /* Command line processing. */
24458 Invocation line includes a switch not recognized by the base assembler.
24459 See if it's a processor-specific option.
24461 This routine is somewhat complicated by the need for backwards
24462 compatibility (since older releases of gcc can't be changed).
24463 The new options try to make the interface as compatible as
24466 New options (supported) are:
24468 -mcpu=<cpu name> Assemble for selected processor
24469 -march=<architecture name> Assemble for selected architecture
24470 -mfpu=<fpu architecture> Assemble for selected FPU.
24471 -EB/-mbig-endian Big-endian
24472 -EL/-mlittle-endian Little-endian
24473 -k Generate PIC code
24474 -mthumb Start in Thumb mode
24475 -mthumb-interwork Code supports ARM/Thumb interworking
24477 -m[no-]warn-deprecated Warn about deprecated features
24478 -m[no-]warn-syms Warn when symbols match instructions
24480 For now we will also provide support for:
24482 -mapcs-32 32-bit Program counter
24483 -mapcs-26 26-bit Program counter
24484 -macps-float Floats passed in FP registers
24485 -mapcs-reentrant Reentrant code
24487 (sometime these will probably be replaced with -mapcs=<list of options>
24488 and -matpcs=<list of options>)
24490 The remaining options are only supported for back-wards compatibility.
24491 Cpu variants, the arm part is optional:
24492 -m[arm]1 Currently not supported.
24493 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24494 -m[arm]3 Arm 3 processor
24495 -m[arm]6[xx], Arm 6 processors
24496 -m[arm]7[xx][t][[d]m] Arm 7 processors
24497 -m[arm]8[10] Arm 8 processors
24498 -m[arm]9[20][tdmi] Arm 9 processors
24499 -mstrongarm[110[0]] StrongARM processors
24500 -mxscale XScale processors
24501 -m[arm]v[2345[t[e]]] Arm architectures
24502 -mall All (except the ARM1)
24504 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24505 -mfpe-old (No float load/store multiples)
24506 -mvfpxd VFP Single precision
24508 -mno-fpu Disable all floating point instructions
24510 The following CPU names are recognized:
24511 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24512 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24513 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24514 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24515 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24516 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24517 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24521 const char * md_shortopts
= "m:k";
24523 #ifdef ARM_BI_ENDIAN
24524 #define OPTION_EB (OPTION_MD_BASE + 0)
24525 #define OPTION_EL (OPTION_MD_BASE + 1)
24527 #if TARGET_BYTES_BIG_ENDIAN
24528 #define OPTION_EB (OPTION_MD_BASE + 0)
24530 #define OPTION_EL (OPTION_MD_BASE + 1)
24533 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24535 struct option md_longopts
[] =
24538 {"EB", no_argument
, NULL
, OPTION_EB
},
24541 {"EL", no_argument
, NULL
, OPTION_EL
},
24543 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24544 {NULL
, no_argument
, NULL
, 0}
24548 size_t md_longopts_size
= sizeof (md_longopts
);
24550 struct arm_option_table
24552 char *option
; /* Option name to match. */
24553 char *help
; /* Help information. */
24554 int *var
; /* Variable to change. */
24555 int value
; /* What to change it to. */
24556 char *deprecated
; /* If non-null, print this message. */
24559 struct arm_option_table arm_opts
[] =
24561 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24562 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24563 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24564 &support_interwork
, 1, NULL
},
24565 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24566 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24567 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24569 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24570 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24571 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24572 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24575 /* These are recognized by the assembler, but have no affect on code. */
24576 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24577 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24579 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24580 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24581 &warn_on_deprecated
, 0, NULL
},
24582 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24583 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24584 {NULL
, NULL
, NULL
, 0, NULL
}
24587 struct arm_legacy_option_table
24589 char *option
; /* Option name to match. */
24590 const arm_feature_set
**var
; /* Variable to change. */
24591 const arm_feature_set value
; /* What to change it to. */
24592 char *deprecated
; /* If non-null, print this message. */
24595 const struct arm_legacy_option_table arm_legacy_opts
[] =
24597 /* DON'T add any new processors to this list -- we want the whole list
24598 to go away... Add them to the processors table instead. */
24599 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24600 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24601 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24602 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24603 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24604 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24605 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24606 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24607 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24608 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24609 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24610 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24611 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24612 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24613 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24614 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24615 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24616 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24617 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24618 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24619 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24620 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24621 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24622 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24623 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24624 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24625 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24626 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24627 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24628 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24629 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24630 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24631 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24632 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24633 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24634 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24635 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24636 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24637 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24638 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24639 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24640 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24641 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24642 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24643 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24644 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24645 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24646 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24647 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24648 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24649 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24650 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24651 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24652 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24653 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24654 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24655 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24656 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24657 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24658 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24659 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24660 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24661 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24662 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24663 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24664 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24665 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24666 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24667 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24668 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24669 N_("use -mcpu=strongarm110")},
24670 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24671 N_("use -mcpu=strongarm1100")},
24672 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24673 N_("use -mcpu=strongarm1110")},
24674 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24675 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24676 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24678 /* Architecture variants -- don't add any more to this list either. */
24679 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24680 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24681 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24682 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24683 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24684 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24685 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24686 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24687 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24688 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24689 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24690 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24691 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24692 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24693 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24694 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24695 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24696 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24698 /* Floating point variants -- don't add any more to this list either. */
24699 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24700 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24701 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24702 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24703 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24705 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24708 struct arm_cpu_option_table
24712 const arm_feature_set value
;
24713 /* For some CPUs we assume an FPU unless the user explicitly sets
24715 const arm_feature_set default_fpu
;
24716 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24718 const char *canonical_name
;
24721 /* This list should, at a minimum, contain all the cpu names
24722 recognized by GCC. */
24723 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24724 static const struct arm_cpu_option_table arm_cpus
[] =
24726 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24727 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24728 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24729 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24730 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24731 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24732 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24733 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24734 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24735 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24736 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24737 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24738 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24739 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24740 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24741 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24742 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24743 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24744 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24745 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24746 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24747 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24748 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24749 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24750 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24751 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24752 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24753 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24754 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24755 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24756 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24757 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24758 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24759 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24760 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24761 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24762 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24763 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24764 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24765 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24766 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24767 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24768 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24769 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24770 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24771 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24772 /* For V5 or later processors we default to using VFP; but the user
24773 should really set the FPU type explicitly. */
24774 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24775 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24776 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24777 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24778 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24779 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24780 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24781 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24782 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24783 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24784 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24785 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24786 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24787 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24788 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24789 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24790 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24791 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24792 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24793 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24795 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24796 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24797 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24798 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24799 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24800 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24801 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24802 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24803 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24805 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24806 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24807 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24808 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24809 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24810 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
24811 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
24812 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24813 FPU_NONE
, "Cortex-A5"),
24814 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24816 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24817 ARM_FEATURE_COPROC (FPU_VFP_V3
24818 | FPU_NEON_EXT_V1
),
24820 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24821 ARM_FEATURE_COPROC (FPU_VFP_V3
24822 | FPU_NEON_EXT_V1
),
24824 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24826 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24828 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24830 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24832 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24834 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24836 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24838 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24839 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24841 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24842 FPU_NONE
, "Cortex-R5"),
24843 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24844 FPU_ARCH_VFP_V3D16
,
24846 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24847 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24848 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24849 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24850 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24851 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24852 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24855 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24859 /* ??? XSCALE is really an architecture. */
24860 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24861 /* ??? iwmmxt is not a processor. */
24862 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24863 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24864 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24866 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24867 FPU_ARCH_MAVERICK
, "ARM920T"),
24868 /* Marvell processors. */
24869 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24871 FPU_ARCH_VFP_V3D16
, NULL
),
24872 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24874 FPU_ARCH_NEON_VFP_V4
, NULL
),
24875 /* APM X-Gene family. */
24876 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24878 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24881 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24885 struct arm_arch_option_table
24889 const arm_feature_set value
;
24890 const arm_feature_set default_fpu
;
24893 /* This list should, at a minimum, contain all the architecture names
24894 recognized by GCC. */
24895 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24896 static const struct arm_arch_option_table arm_archs
[] =
24898 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24899 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24900 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24901 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24902 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24903 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24904 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24905 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24906 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24907 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24908 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24909 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24910 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24911 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24912 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24913 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24914 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24915 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24916 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24917 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24918 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24919 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
24920 kept to preserve existing behaviour. */
24921 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24922 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24923 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24924 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24925 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24926 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
24927 kept to preserve existing behaviour. */
24928 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24929 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24930 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24931 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24932 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24933 /* The official spelling of the ARMv7 profile variants is the dashed form.
24934 Accept the non-dashed form for compatibility with old toolchains. */
24935 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24936 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24937 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24938 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24939 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24940 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24941 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24942 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24943 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24944 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24945 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
24946 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24947 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24948 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24949 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24951 #undef ARM_ARCH_OPT
24953 /* ISA extensions in the co-processor and main instruction set space. */
24954 struct arm_option_extension_value_table
24958 const arm_feature_set merge_value
;
24959 const arm_feature_set clear_value
;
24960 const arm_feature_set allowed_archs
;
24963 /* The following table must be in alphabetical order with a NULL last entry.
24965 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24966 static const struct arm_option_extension_value_table arm_extensions
[] =
24968 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24969 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24970 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24971 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24972 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24973 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24974 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24975 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24976 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24977 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24978 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24979 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24980 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24981 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24982 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24983 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24984 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24985 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24986 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24987 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24988 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24989 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24990 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24991 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24992 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24993 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24994 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24995 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24996 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24997 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24998 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24999 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25001 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25002 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25003 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
25004 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25005 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25006 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25007 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
25008 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25012 /* ISA floating-point and Advanced SIMD extensions. */
25013 struct arm_option_fpu_value_table
25016 const arm_feature_set value
;
25019 /* This list should, at a minimum, contain all the fpu names
25020 recognized by GCC. */
25021 static const struct arm_option_fpu_value_table arm_fpus
[] =
25023 {"softfpa", FPU_NONE
},
25024 {"fpe", FPU_ARCH_FPE
},
25025 {"fpe2", FPU_ARCH_FPE
},
25026 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25027 {"fpa", FPU_ARCH_FPA
},
25028 {"fpa10", FPU_ARCH_FPA
},
25029 {"fpa11", FPU_ARCH_FPA
},
25030 {"arm7500fe", FPU_ARCH_FPA
},
25031 {"softvfp", FPU_ARCH_VFP
},
25032 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25033 {"vfp", FPU_ARCH_VFP_V2
},
25034 {"vfp9", FPU_ARCH_VFP_V2
},
25035 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25036 {"vfp10", FPU_ARCH_VFP_V2
},
25037 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25038 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25039 {"vfpv2", FPU_ARCH_VFP_V2
},
25040 {"vfpv3", FPU_ARCH_VFP_V3
},
25041 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25042 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25043 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25044 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25045 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25046 {"arm1020t", FPU_ARCH_VFP_V1
},
25047 {"arm1020e", FPU_ARCH_VFP_V2
},
25048 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25049 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25050 {"maverick", FPU_ARCH_MAVERICK
},
25051 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25052 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25053 {"vfpv4", FPU_ARCH_VFP_V4
},
25054 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25055 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25056 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25057 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25058 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25059 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25060 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25061 {"crypto-neon-fp-armv8",
25062 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25063 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25064 {"crypto-neon-fp-armv8.1",
25065 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25066 {NULL
, ARM_ARCH_NONE
}
25069 struct arm_option_value_table
25075 static const struct arm_option_value_table arm_float_abis
[] =
25077 {"hard", ARM_FLOAT_ABI_HARD
},
25078 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25079 {"soft", ARM_FLOAT_ABI_SOFT
},
25084 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25085 static const struct arm_option_value_table arm_eabis
[] =
25087 {"gnu", EF_ARM_EABI_UNKNOWN
},
25088 {"4", EF_ARM_EABI_VER4
},
25089 {"5", EF_ARM_EABI_VER5
},
25094 struct arm_long_option_table
25096 char * option
; /* Substring to match. */
25097 char * help
; /* Help information. */
25098 int (* func
) (char * subopt
); /* Function to decode sub-option. */
25099 char * deprecated
; /* If non-null, print this message. */
25103 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
25105 arm_feature_set
*ext_set
= (arm_feature_set
*)
25106 xmalloc (sizeof (arm_feature_set
));
25108 /* We insist on extensions being specified in alphabetical order, and with
25109 extensions being added before being removed. We achieve this by having
25110 the global ARM_EXTENSIONS table in alphabetical order, and using the
25111 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25112 or removing it (0) and only allowing it to change in the order
25114 const struct arm_option_extension_value_table
* opt
= NULL
;
25115 int adding_value
= -1;
25117 /* Copy the feature set, so that we can modify it. */
25118 *ext_set
= **opt_p
;
25121 while (str
!= NULL
&& *str
!= 0)
25128 as_bad (_("invalid architectural extension"));
25133 ext
= strchr (str
, '+');
25138 len
= strlen (str
);
25140 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25142 if (adding_value
!= 0)
25145 opt
= arm_extensions
;
25153 if (adding_value
== -1)
25156 opt
= arm_extensions
;
25158 else if (adding_value
!= 1)
25160 as_bad (_("must specify extensions to add before specifying "
25161 "those to remove"));
25168 as_bad (_("missing architectural extension"));
25172 gas_assert (adding_value
!= -1);
25173 gas_assert (opt
!= NULL
);
25175 /* Scan over the options table trying to find an exact match. */
25176 for (; opt
->name
!= NULL
; opt
++)
25177 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25179 /* Check we can apply the extension to this architecture. */
25180 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25182 as_bad (_("extension does not apply to the base architecture"));
25186 /* Add or remove the extension. */
25188 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25190 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25195 if (opt
->name
== NULL
)
25197 /* Did we fail to find an extension because it wasn't specified in
25198 alphabetical order, or because it does not exist? */
25200 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25201 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25204 if (opt
->name
== NULL
)
25205 as_bad (_("unknown architectural extension `%s'"), str
);
25207 as_bad (_("architectural extensions must be specified in "
25208 "alphabetical order"));
25214 /* We should skip the extension we've just matched the next time
25226 arm_parse_cpu (char *str
)
25228 const struct arm_cpu_option_table
*opt
;
25229 char *ext
= strchr (str
, '+');
25235 len
= strlen (str
);
25239 as_bad (_("missing cpu name `%s'"), str
);
25243 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25244 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25246 mcpu_cpu_opt
= &opt
->value
;
25247 mcpu_fpu_opt
= &opt
->default_fpu
;
25248 if (opt
->canonical_name
)
25250 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25251 strcpy (selected_cpu_name
, opt
->canonical_name
);
25257 if (len
>= sizeof selected_cpu_name
)
25258 len
= (sizeof selected_cpu_name
) - 1;
25260 for (i
= 0; i
< len
; i
++)
25261 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25262 selected_cpu_name
[i
] = 0;
25266 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25271 as_bad (_("unknown cpu `%s'"), str
);
25276 arm_parse_arch (char *str
)
25278 const struct arm_arch_option_table
*opt
;
25279 char *ext
= strchr (str
, '+');
25285 len
= strlen (str
);
25289 as_bad (_("missing architecture name `%s'"), str
);
25293 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25294 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25296 march_cpu_opt
= &opt
->value
;
25297 march_fpu_opt
= &opt
->default_fpu
;
25298 strcpy (selected_cpu_name
, opt
->name
);
25301 return arm_parse_extension (ext
, &march_cpu_opt
);
25306 as_bad (_("unknown architecture `%s'\n"), str
);
25311 arm_parse_fpu (char * str
)
25313 const struct arm_option_fpu_value_table
* opt
;
25315 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25316 if (streq (opt
->name
, str
))
25318 mfpu_opt
= &opt
->value
;
25322 as_bad (_("unknown floating point format `%s'\n"), str
);
25327 arm_parse_float_abi (char * str
)
25329 const struct arm_option_value_table
* opt
;
25331 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25332 if (streq (opt
->name
, str
))
25334 mfloat_abi_opt
= opt
->value
;
25338 as_bad (_("unknown floating point abi `%s'\n"), str
);
25344 arm_parse_eabi (char * str
)
25346 const struct arm_option_value_table
*opt
;
25348 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25349 if (streq (opt
->name
, str
))
25351 meabi_flags
= opt
->value
;
25354 as_bad (_("unknown EABI `%s'\n"), str
);
25360 arm_parse_it_mode (char * str
)
25362 bfd_boolean ret
= TRUE
;
25364 if (streq ("arm", str
))
25365 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25366 else if (streq ("thumb", str
))
25367 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25368 else if (streq ("always", str
))
25369 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25370 else if (streq ("never", str
))
25371 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25374 as_bad (_("unknown implicit IT mode `%s', should be "\
25375 "arm, thumb, always, or never."), str
);
25383 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25385 codecomposer_syntax
= TRUE
;
25386 arm_comment_chars
[0] = ';';
25387 arm_line_separator_chars
[0] = 0;
25391 struct arm_long_option_table arm_long_opts
[] =
25393 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25394 arm_parse_cpu
, NULL
},
25395 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25396 arm_parse_arch
, NULL
},
25397 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25398 arm_parse_fpu
, NULL
},
25399 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25400 arm_parse_float_abi
, NULL
},
25402 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25403 arm_parse_eabi
, NULL
},
25405 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25406 arm_parse_it_mode
, NULL
},
25407 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25408 arm_ccs_mode
, NULL
},
25409 {NULL
, NULL
, 0, NULL
}
25413 md_parse_option (int c
, char * arg
)
25415 struct arm_option_table
*opt
;
25416 const struct arm_legacy_option_table
*fopt
;
25417 struct arm_long_option_table
*lopt
;
25423 target_big_endian
= 1;
25429 target_big_endian
= 0;
25433 case OPTION_FIX_V4BX
:
25438 /* Listing option. Just ignore these, we don't support additional
25443 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25445 if (c
== opt
->option
[0]
25446 && ((arg
== NULL
&& opt
->option
[1] == 0)
25447 || streq (arg
, opt
->option
+ 1)))
25449 /* If the option is deprecated, tell the user. */
25450 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25451 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25452 arg
? arg
: "", _(opt
->deprecated
));
25454 if (opt
->var
!= NULL
)
25455 *opt
->var
= opt
->value
;
25461 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25463 if (c
== fopt
->option
[0]
25464 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25465 || streq (arg
, fopt
->option
+ 1)))
25467 /* If the option is deprecated, tell the user. */
25468 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25469 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25470 arg
? arg
: "", _(fopt
->deprecated
));
25472 if (fopt
->var
!= NULL
)
25473 *fopt
->var
= &fopt
->value
;
25479 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25481 /* These options are expected to have an argument. */
25482 if (c
== lopt
->option
[0]
25484 && strncmp (arg
, lopt
->option
+ 1,
25485 strlen (lopt
->option
+ 1)) == 0)
25487 /* If the option is deprecated, tell the user. */
25488 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25489 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25490 _(lopt
->deprecated
));
25492 /* Call the sup-option parser. */
25493 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25504 md_show_usage (FILE * fp
)
25506 struct arm_option_table
*opt
;
25507 struct arm_long_option_table
*lopt
;
25509 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25511 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25512 if (opt
->help
!= NULL
)
25513 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25515 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25516 if (lopt
->help
!= NULL
)
25517 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25521 -EB assemble code for a big-endian cpu\n"));
25526 -EL assemble code for a little-endian cpu\n"));
25530 --fix-v4bx Allow BX in ARMv4 code\n"));
25538 arm_feature_set flags
;
25539 } cpu_arch_ver_table
;
25541 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25542 least features first. */
25543 static const cpu_arch_ver_table cpu_arch_ver
[] =
25549 {4, ARM_ARCH_V5TE
},
25550 {5, ARM_ARCH_V5TEJ
},
25554 {11, ARM_ARCH_V6M
},
25555 {12, ARM_ARCH_V6SM
},
25556 {8, ARM_ARCH_V6T2
},
25557 {10, ARM_ARCH_V7VE
},
25558 {10, ARM_ARCH_V7R
},
25559 {10, ARM_ARCH_V7M
},
25560 {14, ARM_ARCH_V8A
},
25564 /* Set an attribute if it has not already been set by the user. */
25566 aeabi_set_attribute_int (int tag
, int value
)
25569 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25570 || !attributes_set_explicitly
[tag
])
25571 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25575 aeabi_set_attribute_string (int tag
, const char *value
)
25578 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25579 || !attributes_set_explicitly
[tag
])
25580 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25583 /* Set the public EABI object attributes. */
25585 aeabi_set_public_attributes (void)
25590 int fp16_optional
= 0;
25591 arm_feature_set flags
;
25592 arm_feature_set tmp
;
25593 const cpu_arch_ver_table
*p
;
25595 /* Choose the architecture based on the capabilities of the requested cpu
25596 (if any) and/or the instructions actually used. */
25597 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25598 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25599 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25601 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25602 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25604 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25605 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25607 selected_cpu
= flags
;
25609 /* Allow the user to override the reported architecture. */
25612 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25613 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25616 /* We need to make sure that the attributes do not identify us as v6S-M
25617 when the only v6S-M feature in use is the Operating System Extensions. */
25618 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25619 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25620 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25624 for (p
= cpu_arch_ver
; p
->val
; p
++)
25626 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25629 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25633 /* The table lookup above finds the last architecture to contribute
25634 a new feature. Unfortunately, Tag13 is a subset of the union of
25635 v6T2 and v7-M, so it is never seen as contributing a new feature.
25636 We can not search for the last entry which is entirely used,
25637 because if no CPU is specified we build up only those flags
25638 actually used. Perhaps we should separate out the specified
25639 and implicit cases. Avoid taking this path for -march=all by
25640 checking for contradictory v7-A / v7-M features. */
25642 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25643 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25644 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25647 /* Tag_CPU_name. */
25648 if (selected_cpu_name
[0])
25652 q
= selected_cpu_name
;
25653 if (strncmp (q
, "armv", 4) == 0)
25658 for (i
= 0; q
[i
]; i
++)
25659 q
[i
] = TOUPPER (q
[i
]);
25661 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25664 /* Tag_CPU_arch. */
25665 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25667 /* Tag_CPU_arch_profile. */
25668 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25669 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25671 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25673 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25678 if (profile
!= '\0')
25679 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25681 /* Tag_ARM_ISA_use. */
25682 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25684 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25686 /* Tag_THUMB_ISA_use. */
25687 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25689 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25690 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25692 /* Tag_VFP_arch. */
25693 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25694 aeabi_set_attribute_int (Tag_VFP_arch
,
25695 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25697 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25698 aeabi_set_attribute_int (Tag_VFP_arch
,
25699 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25701 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25704 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25706 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25708 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25711 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25712 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25713 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25714 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25715 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25717 /* Tag_ABI_HardFP_use. */
25718 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25719 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25720 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25722 /* Tag_WMMX_arch. */
25723 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25724 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25725 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25726 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25728 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25729 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25730 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25731 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25733 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25735 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25739 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25744 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25745 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25746 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25750 We set Tag_DIV_use to two when integer divide instructions have been used
25751 in ARM state, or when Thumb integer divide instructions have been used,
25752 but we have no architecture profile set, nor have we any ARM instructions.
25754 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25757 For new architectures we will have to check these tests. */
25758 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25759 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25760 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25761 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25762 || (profile
== '\0'
25763 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25764 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25765 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25767 /* Tag_MP_extension_use. */
25768 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25769 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25771 /* Tag Virtualization_use. */
25772 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25774 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25777 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25780 /* Add the default contents for the .ARM.attributes section. */
25784 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25787 aeabi_set_public_attributes ();
25789 #endif /* OBJ_ELF */
25792 /* Parse a .cpu directive. */
25795 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25797 const struct arm_cpu_option_table
*opt
;
25801 name
= input_line_pointer
;
25802 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25803 input_line_pointer
++;
25804 saved_char
= *input_line_pointer
;
25805 *input_line_pointer
= 0;
25807 /* Skip the first "all" entry. */
25808 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25809 if (streq (opt
->name
, name
))
25811 mcpu_cpu_opt
= &opt
->value
;
25812 selected_cpu
= opt
->value
;
25813 if (opt
->canonical_name
)
25814 strcpy (selected_cpu_name
, opt
->canonical_name
);
25818 for (i
= 0; opt
->name
[i
]; i
++)
25819 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25821 selected_cpu_name
[i
] = 0;
25823 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25824 *input_line_pointer
= saved_char
;
25825 demand_empty_rest_of_line ();
25828 as_bad (_("unknown cpu `%s'"), name
);
25829 *input_line_pointer
= saved_char
;
25830 ignore_rest_of_line ();
25834 /* Parse a .arch directive. */
25837 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25839 const struct arm_arch_option_table
*opt
;
25843 name
= input_line_pointer
;
25844 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25845 input_line_pointer
++;
25846 saved_char
= *input_line_pointer
;
25847 *input_line_pointer
= 0;
25849 /* Skip the first "all" entry. */
25850 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25851 if (streq (opt
->name
, name
))
25853 mcpu_cpu_opt
= &opt
->value
;
25854 selected_cpu
= opt
->value
;
25855 strcpy (selected_cpu_name
, opt
->name
);
25856 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25857 *input_line_pointer
= saved_char
;
25858 demand_empty_rest_of_line ();
25862 as_bad (_("unknown architecture `%s'\n"), name
);
25863 *input_line_pointer
= saved_char
;
25864 ignore_rest_of_line ();
25868 /* Parse a .object_arch directive. */
25871 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25873 const struct arm_arch_option_table
*opt
;
25877 name
= input_line_pointer
;
25878 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25879 input_line_pointer
++;
25880 saved_char
= *input_line_pointer
;
25881 *input_line_pointer
= 0;
25883 /* Skip the first "all" entry. */
25884 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25885 if (streq (opt
->name
, name
))
25887 object_arch
= &opt
->value
;
25888 *input_line_pointer
= saved_char
;
25889 demand_empty_rest_of_line ();
25893 as_bad (_("unknown architecture `%s'\n"), name
);
25894 *input_line_pointer
= saved_char
;
25895 ignore_rest_of_line ();
25898 /* Parse a .arch_extension directive. */
25901 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25903 const struct arm_option_extension_value_table
*opt
;
25906 int adding_value
= 1;
25908 name
= input_line_pointer
;
25909 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25910 input_line_pointer
++;
25911 saved_char
= *input_line_pointer
;
25912 *input_line_pointer
= 0;
25914 if (strlen (name
) >= 2
25915 && strncmp (name
, "no", 2) == 0)
25921 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25922 if (streq (opt
->name
, name
))
25924 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25926 as_bad (_("architectural extension `%s' is not allowed for the "
25927 "current base architecture"), name
);
25932 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25935 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25937 mcpu_cpu_opt
= &selected_cpu
;
25938 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25939 *input_line_pointer
= saved_char
;
25940 demand_empty_rest_of_line ();
25944 if (opt
->name
== NULL
)
25945 as_bad (_("unknown architecture extension `%s'\n"), name
);
25947 *input_line_pointer
= saved_char
;
25948 ignore_rest_of_line ();
25951 /* Parse a .fpu directive. */
25954 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25956 const struct arm_option_fpu_value_table
*opt
;
25960 name
= input_line_pointer
;
25961 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25962 input_line_pointer
++;
25963 saved_char
= *input_line_pointer
;
25964 *input_line_pointer
= 0;
25966 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25967 if (streq (opt
->name
, name
))
25969 mfpu_opt
= &opt
->value
;
25970 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25971 *input_line_pointer
= saved_char
;
25972 demand_empty_rest_of_line ();
25976 as_bad (_("unknown floating point format `%s'\n"), name
);
25977 *input_line_pointer
= saved_char
;
25978 ignore_rest_of_line ();
25981 /* Copy symbol information. */
25984 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25986 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25990 /* Given a symbolic attribute NAME, return the proper integer value.
25991 Returns -1 if the attribute is not known. */
25994 arm_convert_symbolic_attribute (const char *name
)
25996 static const struct
26001 attribute_table
[] =
26003 /* When you modify this table you should
26004 also modify the list in doc/c-arm.texi. */
26005 #define T(tag) {#tag, tag}
26006 T (Tag_CPU_raw_name
),
26009 T (Tag_CPU_arch_profile
),
26010 T (Tag_ARM_ISA_use
),
26011 T (Tag_THUMB_ISA_use
),
26015 T (Tag_Advanced_SIMD_arch
),
26016 T (Tag_PCS_config
),
26017 T (Tag_ABI_PCS_R9_use
),
26018 T (Tag_ABI_PCS_RW_data
),
26019 T (Tag_ABI_PCS_RO_data
),
26020 T (Tag_ABI_PCS_GOT_use
),
26021 T (Tag_ABI_PCS_wchar_t
),
26022 T (Tag_ABI_FP_rounding
),
26023 T (Tag_ABI_FP_denormal
),
26024 T (Tag_ABI_FP_exceptions
),
26025 T (Tag_ABI_FP_user_exceptions
),
26026 T (Tag_ABI_FP_number_model
),
26027 T (Tag_ABI_align_needed
),
26028 T (Tag_ABI_align8_needed
),
26029 T (Tag_ABI_align_preserved
),
26030 T (Tag_ABI_align8_preserved
),
26031 T (Tag_ABI_enum_size
),
26032 T (Tag_ABI_HardFP_use
),
26033 T (Tag_ABI_VFP_args
),
26034 T (Tag_ABI_WMMX_args
),
26035 T (Tag_ABI_optimization_goals
),
26036 T (Tag_ABI_FP_optimization_goals
),
26037 T (Tag_compatibility
),
26038 T (Tag_CPU_unaligned_access
),
26039 T (Tag_FP_HP_extension
),
26040 T (Tag_VFP_HP_extension
),
26041 T (Tag_ABI_FP_16bit_format
),
26042 T (Tag_MPextension_use
),
26044 T (Tag_nodefaults
),
26045 T (Tag_also_compatible_with
),
26046 T (Tag_conformance
),
26048 T (Tag_Virtualization_use
),
26049 /* We deliberately do not include Tag_MPextension_use_legacy. */
26057 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26058 if (streq (name
, attribute_table
[i
].name
))
26059 return attribute_table
[i
].tag
;
26065 /* Apply sym value for relocations only in the case that they are for
26066 local symbols in the same segment as the fixup and you have the
26067 respective architectural feature for blx and simple switches. */
26069 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26072 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26073 /* PR 17444: If the local symbol is in a different section then a reloc
26074 will always be generated for it, so applying the symbol value now
26075 will result in a double offset being stored in the relocation. */
26076 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26077 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26079 switch (fixP
->fx_r_type
)
26081 case BFD_RELOC_ARM_PCREL_BLX
:
26082 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26083 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26087 case BFD_RELOC_ARM_PCREL_CALL
:
26088 case BFD_RELOC_THUMB_PCREL_BLX
:
26089 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26100 #endif /* OBJ_ELF */