1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright (C) 1999-2018 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "struc-symbol.h"
27 #include "dwarf2dbg.h"
28 #include "dw2gencfi.h"
30 #include "elf32-avr.h"
32 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
33 struct avr_property_record_link
35 struct avr_property_record record
;
36 struct avr_property_record_link
*next
;
42 const char * constraints
;
44 int insn_size
; /* In words. */
46 unsigned int bin_opcode
;
49 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
50 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
52 struct avr_opcodes_s avr_opcodes
[] =
54 #include "opcode/avr.h"
55 {NULL
, NULL
, NULL
, 0, 0, 0}
59 /* Stuff for the `__gcc_isr' pseudo instruction.
61 Purpose of the pseudo instruction is to emit more efficient ISR prologues
62 and epilogues than GCC currently does. GCC has no explicit (on RTL level)
63 modelling of SREG, TMP_REG or ZERO_REG. These regs are used implicitly
64 during instruction printing. That doesn't hurt too much for ordinary
65 functions, however for small ISRs there might be some overhead.
67 As implementing http://gcc.gnu.org/PR20296 would imply an almost complete
68 rewite of GCC's AVR back-end (which might pop up less optimized code in
69 other places), we provide a pseudo-instruction which is resolved by GAS
70 into ISR prologue / epilogue as expected by GCC.
72 Using GAS for this purpose has the additional benefit that it can scan
73 code emit by inline asm which is opaque to GCC.
75 The pseudo-instruction is only supposed to handle the starting of
76 prologue and the ending of epilogues (without RETI) which deal with
77 SREG, TMP_REG and ZERO_REG and one additional, optional general purpose
80 __gcc_isr consists of 3 different "chunks":
83 Chunk 1 (ISR_CHUNK_Prologue)
84 Start the ISR code. Will be replaced by ISR prologue by next Done chunk.
85 Must be the 1st chunk in a file or follow a Done chunk from previous
86 ISR (which has been patched already).
88 It will finish the current frag and emit a new frag of
89 type rs_machine_dependent, subtype ISR_CHUNK_Prologue.
92 Chunk 2 (ISR_CHUNK_Epilogue)
93 Will be replaced by ISR epilogue by next Done chunk. Must follow
94 chunk 1 (Prologue) or chunk 2 (Epilogue). Functions might come
95 without epilogue or with more than one epilogue, and even code
96 located statically after the last epilogue might belong to a function.
98 It will finish the current frag and emit a new frag of
99 type rs_machine_dependent, subtype ISR_CHUNK_Epilogue.
102 Chunk 0 (ISR_CHUNK_Done)
103 Must follow chunk 1 (Prologue) or chunk 2 (Epilogue) and finishes
104 the ISR code. Only GCC can know where a function's code ends.
106 It triggers the patch-up of all rs_machine_dependent frags in the
107 current frag chain and turns them into ordinary rs_fill code frags.
109 If Rx is a register > ZERO_REG then GCC also wants to push / pop Rx.
110 If neither TMP_REG nor ZERO_REG are needed, Rx will be used in
111 the push / pop sequence avoiding the need for TMP_REG / ZERO_REG.
112 If Rx <= ZERO_REG then GCC doesn't assume anything about Rx.
116 o GCC takes care of code that is opaque to GAS like tail calls
119 o Using SEI / CLI does not count as clobbering SREG. This is
120 because a final RETI will restore the I-flag.
122 o Using OUT or ST* is supposed not to clobber SREG. Sequences like
124 IN-SREG + CLI + Atomic-Code + OUT-SREG
126 will still work as expected because the scan will reveal any
127 clobber of SREG other than I-flag and emit PUSH / POP of SREG.
133 ISR_CHUNK_Prologue
= 1,
134 ISR_CHUNK_Epilogue
= 2
139 /* Previous __gcc_isr chunk (one of the enums above)
140 and it's location for diagnostics. */
144 /* Replacer for __gcc_isr.n_pushed once we know how many regs are
145 pushed by the Prologue chunk. */
146 symbolS
*sym_n_pushed
;
148 /* Set and used during parse from chunk 1 (Prologue) up to chunk 0 (Done).
149 Set by `avr_update_gccisr' and used by `avr_patch_gccisr_frag'. */
155 static void avr_gccisr_operands (struct avr_opcodes_s
*, char**);
156 static void avr_update_gccisr (struct avr_opcodes_s
*, int, int);
157 static struct avr_opcodes_s
*avr_gccisr_opcode
;
159 const char comment_chars
[] = ";";
160 const char line_comment_chars
[] = "#";
161 const char line_separator_chars
[] = "$";
163 const char *md_shortopts
= "m:";
171 /* XXX - devices that don't seem to exist (renamed, replaced with larger
172 ones, or planned but never produced), left here for compatibility. */
174 static struct mcu_type_s mcu_types
[] =
176 {"avr1", AVR_ISA_AVR1
, bfd_mach_avr1
},
177 /* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
178 but set to AVR_ISA_AVR25 for some following version
179 of GCC (from 4.3) for backward compatibility. */
180 {"avr2", AVR_ISA_AVR25
, bfd_mach_avr2
},
181 {"avr25", AVR_ISA_AVR25
, bfd_mach_avr25
},
182 /* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
183 but set to AVR_ISA_AVR3_ALL for some following version
184 of GCC (from 4.3) for backward compatibility. */
185 {"avr3", AVR_ISA_AVR3_ALL
, bfd_mach_avr3
},
186 {"avr31", AVR_ISA_AVR31
, bfd_mach_avr31
},
187 {"avr35", AVR_ISA_AVR35
, bfd_mach_avr35
},
188 {"avr4", AVR_ISA_AVR4
, bfd_mach_avr4
},
189 /* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
190 but set to AVR_ISA_AVR51 for some following version
191 of GCC (from 4.3) for backward compatibility. */
192 {"avr5", AVR_ISA_AVR51
, bfd_mach_avr5
},
193 {"avr51", AVR_ISA_AVR51
, bfd_mach_avr51
},
194 {"avr6", AVR_ISA_AVR6
, bfd_mach_avr6
},
195 {"avrxmega1", AVR_ISA_XMEGA
, bfd_mach_avrxmega1
},
196 {"avrxmega2", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
197 {"avrxmega3", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
198 {"avrxmega4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
199 {"avrxmega5", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
200 {"avrxmega6", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
201 {"avrxmega7", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
202 {"avrtiny", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
203 {"at90s1200", AVR_ISA_1200
, bfd_mach_avr1
},
204 {"attiny11", AVR_ISA_AVR1
, bfd_mach_avr1
},
205 {"attiny12", AVR_ISA_AVR1
, bfd_mach_avr1
},
206 {"attiny15", AVR_ISA_AVR1
, bfd_mach_avr1
},
207 {"attiny28", AVR_ISA_AVR1
, bfd_mach_avr1
},
208 {"at90s2313", AVR_ISA_AVR2
, bfd_mach_avr2
},
209 {"at90s2323", AVR_ISA_AVR2
, bfd_mach_avr2
},
210 {"at90s2333", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 4433 */
211 {"at90s2343", AVR_ISA_AVR2
, bfd_mach_avr2
},
212 {"attiny22", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 2343 */
213 {"attiny26", AVR_ISA_2xxe
, bfd_mach_avr2
},
214 {"at90s4414", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8515 */
215 {"at90s4433", AVR_ISA_AVR2
, bfd_mach_avr2
},
216 {"at90s4434", AVR_ISA_AVR2
, bfd_mach_avr2
}, /* XXX -> 8535 */
217 {"at90s8515", AVR_ISA_AVR2
, bfd_mach_avr2
},
218 {"at90c8534", AVR_ISA_AVR2
, bfd_mach_avr2
},
219 {"at90s8535", AVR_ISA_AVR2
, bfd_mach_avr2
},
220 {"ata5272", AVR_ISA_AVR25
, bfd_mach_avr25
},
221 {"attiny13", AVR_ISA_AVR25
, bfd_mach_avr25
},
222 {"attiny13a", AVR_ISA_AVR25
, bfd_mach_avr25
},
223 {"attiny2313", AVR_ISA_AVR25
, bfd_mach_avr25
},
224 {"attiny2313a",AVR_ISA_AVR25
, bfd_mach_avr25
},
225 {"attiny24", AVR_ISA_AVR25
, bfd_mach_avr25
},
226 {"attiny24a", AVR_ISA_AVR25
, bfd_mach_avr25
},
227 {"attiny4313", AVR_ISA_AVR25
, bfd_mach_avr25
},
228 {"attiny44", AVR_ISA_AVR25
, bfd_mach_avr25
},
229 {"attiny44a", AVR_ISA_AVR25
, bfd_mach_avr25
},
230 {"attiny84", AVR_ISA_AVR25
, bfd_mach_avr25
},
231 {"attiny84a", AVR_ISA_AVR25
, bfd_mach_avr25
},
232 {"attiny25", AVR_ISA_AVR25
, bfd_mach_avr25
},
233 {"attiny45", AVR_ISA_AVR25
, bfd_mach_avr25
},
234 {"attiny85", AVR_ISA_AVR25
, bfd_mach_avr25
},
235 {"attiny261", AVR_ISA_AVR25
, bfd_mach_avr25
},
236 {"attiny261a", AVR_ISA_AVR25
, bfd_mach_avr25
},
237 {"attiny461", AVR_ISA_AVR25
, bfd_mach_avr25
},
238 {"attiny461a", AVR_ISA_AVR25
, bfd_mach_avr25
},
239 {"attiny861", AVR_ISA_AVR25
, bfd_mach_avr25
},
240 {"attiny861a", AVR_ISA_AVR25
, bfd_mach_avr25
},
241 {"attiny87", AVR_ISA_AVR25
, bfd_mach_avr25
},
242 {"attiny43u", AVR_ISA_AVR25
, bfd_mach_avr25
},
243 {"attiny48", AVR_ISA_AVR25
, bfd_mach_avr25
},
244 {"attiny88", AVR_ISA_AVR25
, bfd_mach_avr25
},
245 {"attiny828", AVR_ISA_AVR25
, bfd_mach_avr25
},
246 {"at86rf401", AVR_ISA_RF401
, bfd_mach_avr25
},
247 {"at43usb355", AVR_ISA_AVR3
, bfd_mach_avr3
},
248 {"at76c711", AVR_ISA_AVR3
, bfd_mach_avr3
},
249 {"atmega103", AVR_ISA_AVR31
, bfd_mach_avr31
},
250 {"at43usb320", AVR_ISA_AVR31
, bfd_mach_avr31
},
251 {"attiny167", AVR_ISA_AVR35
, bfd_mach_avr35
},
252 {"at90usb82", AVR_ISA_AVR35
, bfd_mach_avr35
},
253 {"at90usb162", AVR_ISA_AVR35
, bfd_mach_avr35
},
254 {"ata5505", AVR_ISA_AVR35
, bfd_mach_avr35
},
255 {"atmega8u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
256 {"atmega16u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
257 {"atmega32u2", AVR_ISA_AVR35
, bfd_mach_avr35
},
258 {"attiny1634", AVR_ISA_AVR35
, bfd_mach_avr35
},
259 {"atmega8", AVR_ISA_M8
, bfd_mach_avr4
},
260 {"ata6289", AVR_ISA_AVR4
, bfd_mach_avr4
},
261 {"atmega8a", AVR_ISA_M8
, bfd_mach_avr4
},
262 {"ata6285", AVR_ISA_AVR4
, bfd_mach_avr4
},
263 {"ata6286", AVR_ISA_AVR4
, bfd_mach_avr4
},
264 {"atmega48", AVR_ISA_AVR4
, bfd_mach_avr4
},
265 {"atmega48a", AVR_ISA_AVR4
, bfd_mach_avr4
},
266 {"atmega48pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
267 {"atmega48p", AVR_ISA_AVR4
, bfd_mach_avr4
},
268 {"atmega88", AVR_ISA_AVR4
, bfd_mach_avr4
},
269 {"atmega88a", AVR_ISA_AVR4
, bfd_mach_avr4
},
270 {"atmega88p", AVR_ISA_AVR4
, bfd_mach_avr4
},
271 {"atmega88pa", AVR_ISA_AVR4
, bfd_mach_avr4
},
272 {"atmega8515", AVR_ISA_M8
, bfd_mach_avr4
},
273 {"atmega8535", AVR_ISA_M8
, bfd_mach_avr4
},
274 {"atmega8hva", AVR_ISA_AVR4
, bfd_mach_avr4
},
275 {"at90pwm1", AVR_ISA_AVR4
, bfd_mach_avr4
},
276 {"at90pwm2", AVR_ISA_AVR4
, bfd_mach_avr4
},
277 {"at90pwm2b", AVR_ISA_AVR4
, bfd_mach_avr4
},
278 {"at90pwm3", AVR_ISA_AVR4
, bfd_mach_avr4
},
279 {"at90pwm3b", AVR_ISA_AVR4
, bfd_mach_avr4
},
280 {"at90pwm81", AVR_ISA_AVR4
, bfd_mach_avr4
},
281 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
282 {"ata5790", AVR_ISA_AVR5
, bfd_mach_avr5
},
283 {"ata5795", AVR_ISA_AVR5
, bfd_mach_avr5
},
284 {"atmega16", AVR_ISA_AVR5
, bfd_mach_avr5
},
285 {"atmega16a", AVR_ISA_AVR5
, bfd_mach_avr5
},
286 {"atmega161", AVR_ISA_M161
, bfd_mach_avr5
},
287 {"atmega162", AVR_ISA_AVR5
, bfd_mach_avr5
},
288 {"atmega163", AVR_ISA_M161
, bfd_mach_avr5
},
289 {"atmega164a", AVR_ISA_AVR5
, bfd_mach_avr5
},
290 {"atmega164p", AVR_ISA_AVR5
, bfd_mach_avr5
},
291 {"atmega164pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
292 {"atmega165", AVR_ISA_AVR5
, bfd_mach_avr5
},
293 {"atmega165a", AVR_ISA_AVR5
, bfd_mach_avr5
},
294 {"atmega165p", AVR_ISA_AVR5
, bfd_mach_avr5
},
295 {"atmega165pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
296 {"atmega168", AVR_ISA_AVR5
, bfd_mach_avr5
},
297 {"atmega168a", AVR_ISA_AVR5
, bfd_mach_avr5
},
298 {"atmega168p", AVR_ISA_AVR5
, bfd_mach_avr5
},
299 {"atmega168pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
300 {"atmega169", AVR_ISA_AVR5
, bfd_mach_avr5
},
301 {"atmega169a", AVR_ISA_AVR5
, bfd_mach_avr5
},
302 {"atmega169p", AVR_ISA_AVR5
, bfd_mach_avr5
},
303 {"atmega169pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
304 {"atmega32", AVR_ISA_AVR5
, bfd_mach_avr5
},
305 {"atmega32a", AVR_ISA_AVR5
, bfd_mach_avr5
},
306 {"atmega323", AVR_ISA_AVR5
, bfd_mach_avr5
},
307 {"atmega324a", AVR_ISA_AVR5
, bfd_mach_avr5
},
308 {"atmega324p", AVR_ISA_AVR5
, bfd_mach_avr5
},
309 {"atmega324pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
310 {"atmega325", AVR_ISA_AVR5
, bfd_mach_avr5
},
311 {"atmega325a", AVR_ISA_AVR5
, bfd_mach_avr5
},
312 {"atmega325p", AVR_ISA_AVR5
, bfd_mach_avr5
},
313 {"atmega325pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
314 {"atmega3250", AVR_ISA_AVR5
, bfd_mach_avr5
},
315 {"atmega3250a",AVR_ISA_AVR5
, bfd_mach_avr5
},
316 {"atmega3250p",AVR_ISA_AVR5
, bfd_mach_avr5
},
317 {"atmega3250pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
318 {"atmega328", AVR_ISA_AVR5
, bfd_mach_avr5
},
319 {"atmega328p", AVR_ISA_AVR5
, bfd_mach_avr5
},
320 {"atmega329", AVR_ISA_AVR5
, bfd_mach_avr5
},
321 {"atmega329a", AVR_ISA_AVR5
, bfd_mach_avr5
},
322 {"atmega329p", AVR_ISA_AVR5
, bfd_mach_avr5
},
323 {"atmega329pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
324 {"atmega3290", AVR_ISA_AVR5
, bfd_mach_avr5
},
325 {"atmega3290a",AVR_ISA_AVR5
, bfd_mach_avr5
},
326 {"atmega3290p",AVR_ISA_AVR5
, bfd_mach_avr5
},
327 {"atmega3290pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
328 {"atmega406", AVR_ISA_AVR5
, bfd_mach_avr5
},
329 {"atmega64rfr2", AVR_ISA_AVR5
, bfd_mach_avr5
},
330 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
331 {"atmega64", AVR_ISA_AVR5
, bfd_mach_avr5
},
332 {"atmega64a", AVR_ISA_AVR5
, bfd_mach_avr5
},
333 {"atmega640", AVR_ISA_AVR5
, bfd_mach_avr5
},
334 {"atmega644", AVR_ISA_AVR5
, bfd_mach_avr5
},
335 {"atmega644a", AVR_ISA_AVR5
, bfd_mach_avr5
},
336 {"atmega644p", AVR_ISA_AVR5
, bfd_mach_avr5
},
337 {"atmega644pa",AVR_ISA_AVR5
, bfd_mach_avr5
},
338 {"atmega645", AVR_ISA_AVR5
, bfd_mach_avr5
},
339 {"atmega645a", AVR_ISA_AVR5
, bfd_mach_avr5
},
340 {"atmega645p", AVR_ISA_AVR5
, bfd_mach_avr5
},
341 {"atmega649", AVR_ISA_AVR5
, bfd_mach_avr5
},
342 {"atmega649a", AVR_ISA_AVR5
, bfd_mach_avr5
},
343 {"atmega649p", AVR_ISA_AVR5
, bfd_mach_avr5
},
344 {"atmega6450", AVR_ISA_AVR5
, bfd_mach_avr5
},
345 {"atmega6450a",AVR_ISA_AVR5
, bfd_mach_avr5
},
346 {"atmega6450p",AVR_ISA_AVR5
, bfd_mach_avr5
},
347 {"atmega6490", AVR_ISA_AVR5
, bfd_mach_avr5
},
348 {"atmega6490a",AVR_ISA_AVR5
, bfd_mach_avr5
},
349 {"atmega6490p",AVR_ISA_AVR5
, bfd_mach_avr5
},
350 {"atmega64rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
351 {"atmega644rfr2",AVR_ISA_AVR5
, bfd_mach_avr5
},
352 {"atmega16hva",AVR_ISA_AVR5
, bfd_mach_avr5
},
353 {"atmega16hva2",AVR_ISA_AVR5
, bfd_mach_avr5
},
354 {"atmega16hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
355 {"atmega16hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
356 {"atmega32hvb",AVR_ISA_AVR5
, bfd_mach_avr5
},
357 {"atmega32hvbrevb",AVR_ISA_AVR5
,bfd_mach_avr5
},
358 {"atmega64hve",AVR_ISA_AVR5
, bfd_mach_avr5
},
359 {"at90can32" , AVR_ISA_AVR5
, bfd_mach_avr5
},
360 {"at90can64" , AVR_ISA_AVR5
, bfd_mach_avr5
},
361 {"at90pwm161", AVR_ISA_AVR5
, bfd_mach_avr5
},
362 {"at90pwm216", AVR_ISA_AVR5
, bfd_mach_avr5
},
363 {"at90pwm316", AVR_ISA_AVR5
, bfd_mach_avr5
},
364 {"atmega32c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
365 {"atmega64c1", AVR_ISA_AVR5
, bfd_mach_avr5
},
366 {"atmega16m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
367 {"atmega32m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
368 {"atmega64m1", AVR_ISA_AVR5
, bfd_mach_avr5
},
369 {"atmega16u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
370 {"atmega32u4", AVR_ISA_AVR5
, bfd_mach_avr5
},
371 {"atmega32u6", AVR_ISA_AVR5
, bfd_mach_avr5
},
372 {"at90usb646", AVR_ISA_AVR5
, bfd_mach_avr5
},
373 {"at90usb647", AVR_ISA_AVR5
, bfd_mach_avr5
},
374 {"at90scr100", AVR_ISA_AVR5
, bfd_mach_avr5
},
375 {"at94k", AVR_ISA_94K
, bfd_mach_avr5
},
376 {"m3000", AVR_ISA_AVR5
, bfd_mach_avr5
},
377 {"atmega128", AVR_ISA_AVR51
, bfd_mach_avr51
},
378 {"atmega128a", AVR_ISA_AVR51
, bfd_mach_avr51
},
379 {"atmega1280", AVR_ISA_AVR51
, bfd_mach_avr51
},
380 {"atmega1281", AVR_ISA_AVR51
, bfd_mach_avr51
},
381 {"atmega1284", AVR_ISA_AVR51
, bfd_mach_avr51
},
382 {"atmega1284p",AVR_ISA_AVR51
, bfd_mach_avr51
},
383 {"atmega128rfa1",AVR_ISA_AVR51
, bfd_mach_avr51
},
384 {"atmega128rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
385 {"atmega1284rfr2",AVR_ISA_AVR51
, bfd_mach_avr51
},
386 {"at90can128", AVR_ISA_AVR51
, bfd_mach_avr51
},
387 {"at90usb1286",AVR_ISA_AVR51
, bfd_mach_avr51
},
388 {"at90usb1287",AVR_ISA_AVR51
, bfd_mach_avr51
},
389 {"atmega2560", AVR_ISA_AVR6
, bfd_mach_avr6
},
390 {"atmega2561", AVR_ISA_AVR6
, bfd_mach_avr6
},
391 {"atmega256rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
392 {"atmega2564rfr2", AVR_ISA_AVR6
, bfd_mach_avr6
},
393 {"atxmega16a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
394 {"atxmega16a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
395 {"atxmega16c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
396 {"atxmega16d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
397 {"atxmega32a4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
398 {"atxmega32a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
399 {"atxmega32c4", AVR_ISA_XMEGAU
, bfd_mach_avrxmega2
},
400 {"atxmega32d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
401 {"atxmega32e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
402 {"atxmega16e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
403 {"atxmega8e5", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
404 {"atxmega32x1", AVR_ISA_XMEGA
, bfd_mach_avrxmega2
},
405 {"attiny212", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
406 {"attiny214", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
407 {"attiny412", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
408 {"attiny414", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
409 {"attiny416", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
410 {"attiny417", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
411 {"attiny814", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
412 {"attiny816", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
413 {"attiny817", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
414 {"attiny1614", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
415 {"attiny1616", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
416 {"attiny1617", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
417 {"attiny3214", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
418 {"attiny3216", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
419 {"attiny3217", AVR_ISA_XMEGA
, bfd_mach_avrxmega3
},
420 {"atxmega64a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
421 {"atxmega64a3u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
422 {"atxmega64a4u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
423 {"atxmega64b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
424 {"atxmega64b3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
425 {"atxmega64c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega4
},
426 {"atxmega64d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
427 {"atxmega64d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega4
},
428 {"atxmega64a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega5
},
429 {"atxmega64a1u",AVR_ISA_XMEGAU
, bfd_mach_avrxmega5
},
430 {"atxmega128a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
431 {"atxmega128a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
432 {"atxmega128b1", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
433 {"atxmega128b3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
434 {"atxmega128c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
435 {"atxmega128d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
436 {"atxmega128d4", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
437 {"atxmega192a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
438 {"atxmega192a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
439 {"atxmega192c3", AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
440 {"atxmega192d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
441 {"atxmega256a3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
442 {"atxmega256a3u",AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
443 {"atxmega256a3b",AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
444 {"atxmega256a3bu",AVR_ISA_XMEGAU
, bfd_mach_avrxmega6
},
445 {"atxmega256c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
446 {"atxmega256d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
447 {"atxmega384c3", AVR_ISA_XMEGAU
,bfd_mach_avrxmega6
},
448 {"atxmega384d3", AVR_ISA_XMEGA
, bfd_mach_avrxmega6
},
449 {"atxmega128a1", AVR_ISA_XMEGA
, bfd_mach_avrxmega7
},
450 {"atxmega128a1u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
451 {"atxmega128a4u", AVR_ISA_XMEGAU
, bfd_mach_avrxmega7
},
452 {"attiny4", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
453 {"attiny5", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
454 {"attiny9", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
455 {"attiny10", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
456 {"attiny20", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
457 {"attiny40", AVR_ISA_AVRTINY
, bfd_mach_avrtiny
},
462 /* Current MCU type. */
463 static struct mcu_type_s default_mcu
= {"avr2", AVR_ISA_AVR2
, bfd_mach_avr2
};
464 static struct mcu_type_s specified_mcu
;
465 static struct mcu_type_s
* avr_mcu
= & default_mcu
;
467 /* AVR target-specific switches. */
470 int all_opcodes
; /* -mall-opcodes: accept all known AVR opcodes. */
471 int no_skip_bug
; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
472 int no_wrap
; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
473 int no_link_relax
; /* -mno-link-relax / -mlink-relax: generate (or not)
474 relocations for linker relaxation. */
475 int have_gccisr
; /* Whether "__gcc_isr" is a known (pseudo) insn. */
478 static struct avr_opt_s avr_opt
= { 0, 0, 0, 0, 0 };
480 const char EXP_CHARS
[] = "eE";
481 const char FLT_CHARS
[] = "dD";
483 static void avr_set_arch (int);
484 static void avr_set_section (int);
486 /* The target specific pseudo-ops which we support. */
487 const pseudo_typeS md_pseudo_table
[] =
489 {"arch", avr_set_arch
, 0},
490 {"section", avr_set_section
, 0},
494 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
496 #define EXP_MOD_NAME(i) exp_mod[i].name
497 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
498 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
499 #define HAVE_PM_P(i) exp_mod[i].have_pm
504 bfd_reloc_code_real_type reloc
;
505 bfd_reloc_code_real_type neg_reloc
;
509 static struct exp_mod_s exp_mod
[] =
511 {"hh8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 1},
512 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM
, BFD_RELOC_AVR_HH8_LDI_PM_NEG
, 0},
513 {"hi8", BFD_RELOC_AVR_HI8_LDI
, BFD_RELOC_AVR_HI8_LDI_NEG
, 1},
514 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM
, BFD_RELOC_AVR_HI8_LDI_PM_NEG
, 0},
515 {"lo8", BFD_RELOC_AVR_LO8_LDI
, BFD_RELOC_AVR_LO8_LDI_NEG
, 1},
516 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM
, BFD_RELOC_AVR_LO8_LDI_PM_NEG
, 0},
517 {"hlo8", BFD_RELOC_AVR_HH8_LDI
, BFD_RELOC_AVR_HH8_LDI_NEG
, 0},
518 {"hhi8", BFD_RELOC_AVR_MS8_LDI
, BFD_RELOC_AVR_MS8_LDI_NEG
, 0},
521 /* A union used to store indices into the exp_mod[] array
522 in a hash table which expects void * data types. */
529 /* Opcode hash table. */
530 static struct hash_control
*avr_hash
;
532 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
533 static struct hash_control
*avr_mod_hash
;
535 /* Whether some opcode does not change SREG. */
536 static struct hash_control
*avr_no_sreg_hash
;
538 static const char* const avr_no_sreg
[] =
541 "ldi", "swap", "mov", "movw",
542 /* Special instructions. I-Flag will be restored by RETI, and we don't
543 consider I-Flag as being clobbered when changed. */
544 "sei", "cli", "reti", "brie", "brid",
545 "nop", "wdr", "sleep",
547 "ld", "ldd", "lds", "pop", "in", "lpm", "elpm",
548 "st", "std", "sts", "push", "out",
549 /* Jumps and Calls. Calls might call code that changes SREG.
550 GCC has to filter out ABI calls. The non-ABI transparent calls
551 must use [R]CALL and are filtered out now by not mentioning them. */
552 "rjmp", "jmp", "ijmp", "ret",
553 /* Skipping. Branches need SREG to be set, hence we regard them
554 as if they changed SREG and don't list them here. */
555 "sbrc", "sbrs", "sbic", "sbis", "cpse",
556 /* I/O Manipulation */
558 /* Read-Modify-Write */
559 "lac", "las", "lat", "xch"
562 #define OPTION_MMCU 'm'
565 OPTION_ALL_OPCODES
= OPTION_MD_BASE
+ 1,
570 OPTION_NO_LINK_RELAX
,
574 struct option md_longopts
[] =
576 { "mmcu", required_argument
, NULL
, OPTION_MMCU
},
577 { "mall-opcodes", no_argument
, NULL
, OPTION_ALL_OPCODES
},
578 { "mno-skip-bug", no_argument
, NULL
, OPTION_NO_SKIP_BUG
},
579 { "mno-wrap", no_argument
, NULL
, OPTION_NO_WRAP
},
580 { "mrmw", no_argument
, NULL
, OPTION_ISA_RMW
},
581 { "mlink-relax", no_argument
, NULL
, OPTION_LINK_RELAX
},
582 { "mno-link-relax", no_argument
, NULL
, OPTION_NO_LINK_RELAX
},
583 { "mgcc-isr", no_argument
, NULL
, OPTION_HAVE_GCCISR
},
584 { NULL
, no_argument
, NULL
, 0 }
587 size_t md_longopts_size
= sizeof (md_longopts
);
589 /* Display nicely formatted list of known MCU names. */
592 show_mcu_list (FILE *stream
)
596 fprintf (stream
, _("Known MCU names:"));
599 for (i
= 0; mcu_types
[i
].name
; i
++)
601 int len
= strlen (mcu_types
[i
].name
);
606 fprintf (stream
, " %s", mcu_types
[i
].name
);
609 fprintf (stream
, "\n %s", mcu_types
[i
].name
);
614 fprintf (stream
, "\n");
620 while (*s
== ' ' || *s
== '\t')
625 /* Extract one word from FROM and copy it to TO. */
628 extract_word (char *from
, char *to
, int limit
)
633 /* Drop leading whitespace. */
634 from
= skip_space (from
);
637 /* Find the op code end. */
638 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
640 to
[size
++] = *op_end
++;
641 if (size
+ 1 >= limit
)
650 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
651 asection
*seg ATTRIBUTE_UNUSED
)
658 md_show_usage (FILE *stream
)
661 _("AVR Assembler options:\n"
662 " -mmcu=[avr-name] select microcontroller variant\n"
663 " [avr-name] can be:\n"
664 " avr1 - classic AVR core without data RAM\n"
665 " avr2 - classic AVR core with up to 8K program memory\n"
666 " avr25 - classic AVR core with up to 8K program memory\n"
667 " plus the MOVW instruction\n"
668 " avr3 - classic AVR core with up to 64K program memory\n"
669 " avr31 - classic AVR core with up to 128K program memory\n"
670 " avr35 - classic AVR core with up to 64K program memory\n"
671 " plus the MOVW instruction\n"
672 " avr4 - enhanced AVR core with up to 8K program memory\n"
673 " avr5 - enhanced AVR core with up to 64K program memory\n"
674 " avr51 - enhanced AVR core with up to 128K program memory\n"
675 " avr6 - enhanced AVR core with up to 256K program memory\n"
676 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
677 " avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM\n"
678 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
679 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
680 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
681 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
682 " avrtiny - AVR Tiny core with 16 gp registers\n"));
684 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
685 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
686 " (default for avr4, avr5)\n"
687 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
688 " (default for avr3, avr5)\n"
689 " -mrmw accept Read-Modify-Write instructions\n"
690 " -mlink-relax generate relocations for linker relaxation (default)\n"
691 " -mno-link-relax don't generate relocations for linker relaxation.\n"
692 " -mgcc-isr accept the __gcc_isr pseudo-instruction.\n"
694 show_mcu_list (stream
);
698 avr_set_arch (int dummy ATTRIBUTE_UNUSED
)
702 input_line_pointer
= extract_word (input_line_pointer
, str
, 20);
703 md_parse_option (OPTION_MMCU
, str
);
704 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
708 avr_set_section (int push
)
710 obj_elf_section (push
);
712 /* PR 23570. The .noinit section needs to be explicitly
713 set to the NOBITS type. */
714 if (seg_info (now_seg
)->bss
== 0
715 && strcmp (bfd_get_section_name (stdoutput
, now_seg
), ".noinit") == 0)
717 bfd_set_section_flags (stdoutput
, now_seg
, SEC_ALLOC
| SEC_RELOC
);
718 seg_info (now_seg
)->bss
= 1;
719 elf_section_type (now_seg
) = SHT_NOBITS
;
720 elf_section_flags (now_seg
) = SHF_ALLOC
| SHF_WRITE
;
725 md_parse_option (int c
, const char *arg
)
733 for (i
= 0; mcu_types
[i
].name
; ++i
)
734 if (strcasecmp (mcu_types
[i
].name
, arg
) == 0)
737 if (!mcu_types
[i
].name
)
739 show_mcu_list (stderr
);
740 as_fatal (_("unknown MCU: %s\n"), arg
);
743 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
744 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
745 as .arch ... in the asm output at the same time. */
746 if (avr_mcu
== &default_mcu
|| avr_mcu
->mach
== mcu_types
[i
].mach
)
748 specified_mcu
.name
= mcu_types
[i
].name
;
749 specified_mcu
.isa
|= mcu_types
[i
].isa
;
750 specified_mcu
.mach
= mcu_types
[i
].mach
;
751 avr_mcu
= &specified_mcu
;
754 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
755 avr_mcu
->name
, mcu_types
[i
].name
);
758 case OPTION_ALL_OPCODES
:
759 avr_opt
.all_opcodes
= 1;
761 case OPTION_NO_SKIP_BUG
:
762 avr_opt
.no_skip_bug
= 1;
768 specified_mcu
.isa
|= AVR_ISA_RMW
;
770 case OPTION_LINK_RELAX
:
771 avr_opt
.no_link_relax
= 0;
773 case OPTION_NO_LINK_RELAX
:
774 avr_opt
.no_link_relax
= 1;
776 case OPTION_HAVE_GCCISR
:
777 avr_opt
.have_gccisr
= 1;
785 /* Implement `md_undefined_symbol' */
786 /* If we are in `__gcc_isr' chunk, pop up `__gcc_isr.n_pushed.<NUM>'
787 instead of `__gcc_isr.n_pushed'. This will be resolved by the Done
788 chunk in `avr_patch_gccisr_frag' to the number of PUSHes produced by
789 the Prologue chunk. */
792 avr_undefined_symbol (char *name
)
794 if (ISR_CHUNK_Done
!= avr_isr
.prev_chunk
795 && 0 == strcmp (name
, "__gcc_isr.n_pushed"))
797 if (!avr_isr
.sym_n_pushed
)
799 static unsigned suffix
;
801 sprintf (xname
, "%s.%03u", name
, (++suffix
) % 1000);
802 avr_isr
.sym_n_pushed
= symbol_new (xname
, undefined_section
,
803 (valueT
) 0, &zero_address_frag
);
805 return avr_isr
.sym_n_pushed
;
812 md_atof (int type
, char *litP
, int *sizeP
)
814 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
818 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
819 asection
*sec ATTRIBUTE_UNUSED
,
820 fragS
*fragP ATTRIBUTE_UNUSED
)
829 struct avr_opcodes_s
*opcode
;
831 avr_hash
= hash_new ();
833 /* Insert unique names into hash table. This hash table then provides a
834 quick index to the first opcode with a particular name in the opcode
836 for (opcode
= avr_opcodes
; opcode
->name
; opcode
++)
837 hash_insert (avr_hash
, opcode
->name
, (char *) opcode
);
839 avr_mod_hash
= hash_new ();
841 for (i
= 0; i
< ARRAY_SIZE (exp_mod
); ++i
)
846 hash_insert (avr_mod_hash
, EXP_MOD_NAME (i
), m
.ptr
);
849 avr_no_sreg_hash
= hash_new ();
851 for (i
= 0; i
< ARRAY_SIZE (avr_no_sreg
); ++i
)
853 gas_assert (hash_find (avr_hash
, avr_no_sreg
[i
]));
854 hash_insert (avr_no_sreg_hash
, avr_no_sreg
[i
], (char*) 4 /* dummy */);
857 avr_gccisr_opcode
= (struct avr_opcodes_s
*) hash_find (avr_hash
, "__gcc_isr");
858 gas_assert (avr_gccisr_opcode
);
860 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, avr_mcu
->mach
);
861 linkrelax
= !avr_opt
.no_link_relax
;
864 /* Resolve STR as a constant expression and return the result.
865 If result greater than MAX then error. */
868 avr_get_constant (char *str
, int max
)
872 str
= skip_space (str
);
873 input_line_pointer
= str
;
876 if (ex
.X_op
!= O_constant
)
877 as_bad (_("constant value required"));
879 if (ex
.X_add_number
> max
|| ex
.X_add_number
< 0)
880 as_bad (_("number must be positive and less than %d"), max
+ 1);
882 return ex
.X_add_number
;
885 /* Parse for ldd/std offset. */
888 avr_offset_expression (expressionS
*exp
)
890 char *str
= input_line_pointer
;
895 str
= extract_word (str
, op
, sizeof (op
));
897 input_line_pointer
= tmp
;
900 /* Warn about expressions that fail to use lo8 (). */
901 if (exp
->X_op
== O_constant
)
903 int x
= exp
->X_add_number
;
905 if (x
< -255 || x
> 255)
906 as_warn (_("constant out of 8-bit range: %d"), x
);
910 /* Parse ordinary expression. */
913 parse_exp (char *s
, expressionS
*op
)
915 input_line_pointer
= s
;
917 if (op
->X_op
== O_absent
)
918 as_bad (_("missing operand"));
919 return input_line_pointer
;
922 /* Parse special expressions (needed for LDI command):
927 where xx is: hh, hi, lo. */
929 static bfd_reloc_code_real_type
930 avr_ldi_expression (expressionS
*exp
)
932 char *str
= input_line_pointer
;
936 int linker_stubs_should_be_generated
= 0;
940 str
= extract_word (str
, op
, sizeof (op
));
946 m
.ptr
= hash_find (avr_mod_hash
, op
);
954 str
= skip_space (str
);
958 bfd_reloc_code_real_type reloc_to_return
;
963 if (strncmp ("pm(", str
, 3) == 0
964 || strncmp ("gs(",str
,3) == 0
965 || strncmp ("-(gs(",str
,5) == 0
966 || strncmp ("-(pm(", str
, 5) == 0)
974 as_bad (_("illegal expression"));
976 if (str
[0] == 'g' || str
[2] == 'g')
977 linker_stubs_should_be_generated
= 1;
989 if (*str
== '-' && *(str
+ 1) == '(')
996 input_line_pointer
= str
;
1001 if (*input_line_pointer
!= ')')
1003 as_bad (_("`)' required"));
1006 input_line_pointer
++;
1011 neg_p
? EXP_MOD_NEG_RELOC (mod
) : EXP_MOD_RELOC (mod
);
1012 if (linker_stubs_should_be_generated
)
1014 switch (reloc_to_return
)
1016 case BFD_RELOC_AVR_LO8_LDI_PM
:
1017 reloc_to_return
= BFD_RELOC_AVR_LO8_LDI_GS
;
1019 case BFD_RELOC_AVR_HI8_LDI_PM
:
1020 reloc_to_return
= BFD_RELOC_AVR_HI8_LDI_GS
;
1024 /* PR 5523: Do not generate a warning here,
1025 legitimate code can trigger this case. */
1029 return reloc_to_return
;
1034 input_line_pointer
= tmp
;
1037 /* Warn about expressions that fail to use lo8 (). */
1038 if (exp
->X_op
== O_constant
)
1040 int x
= exp
->X_add_number
;
1042 if (x
< -255 || x
> 255)
1043 as_warn (_("constant out of 8-bit range: %d"), x
);
1046 return BFD_RELOC_AVR_LDI
;
1049 /* Parse one instruction operand.
1050 Return operand bitmask. Also fixups can be generated. */
1053 avr_operand (struct avr_opcodes_s
*opcode
,
1059 expressionS op_expr
;
1060 unsigned int op_mask
= 0;
1061 char *str
= skip_space (*line
);
1065 /* Any register operand. */
1072 char * old_str
= str
;
1076 str
= extract_word (str
, r_name
, sizeof (r_name
));
1077 for (lower
= r_name
; *lower
; ++lower
)
1079 if (*lower
>= 'A' && *lower
<= 'Z')
1080 *lower
+= 'a' - 'A';
1083 if (r_name
[0] == 'r' && ISDIGIT (r_name
[1]) && r_name
[2] == 0)
1084 /* Single-digit register number, ie r0-r9. */
1085 op_mask
= r_name
[1] - '0';
1086 else if (r_name
[0] == 'r' && ISDIGIT (r_name
[1])
1087 && ISDIGIT (r_name
[2]) && r_name
[3] == 0)
1088 /* Double-digit register number, ie r10 - r32. */
1089 op_mask
= (r_name
[1] - '0') * 10 + r_name
[2] - '0';
1090 else if (r_name
[0] >= 'x' && r_name
[0] <= 'z'
1091 && (r_name
[1] == 'l' || r_name
[1] == 'h') && r_name
[2] == 0)
1092 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
1093 op_mask
= (r_name
[0] - 'x') * 2 + (r_name
[1] == 'h') + 26;
1094 else if ((*op
== 'v' || *op
== 'w')
1095 && r_name
[0] >= 'x' && r_name
[0] <= 'z' && r_name
[1] == 0)
1096 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
1097 op_mask
= (r_name
[0] - 'x') * 2 + 26;
1100 /* Numeric or symbolic constant register number. */
1101 op_mask
= avr_get_constant (old_str
, 31);
1102 str
= input_line_pointer
;
1109 if (avr_mcu
->mach
== bfd_mach_avrtiny
)
1111 if (op_mask
< 16 || op_mask
> 31)
1113 as_bad (_("register name or number from 16 to 31 required"));
1117 else if (op_mask
> 31)
1119 as_bad (_("register name or number from 0 to 31 required"));
1126 if (op_mask
< 16 || op_mask
> 23)
1127 as_bad (_("register r16-r23 required"));
1133 as_bad (_("register number above 15 required"));
1139 as_bad (_("even register number required"));
1144 if ((op_mask
& 1) || op_mask
< 24)
1145 as_bad (_("register r24, r26, r28 or r30 required"));
1146 op_mask
= (op_mask
- 24) >> 1;
1157 str
= skip_space (str
+ 1);
1166 as_bad (_("pointer register (X, Y or Z) required"));
1168 str
= skip_space (str
+ 1);
1173 as_bad (_("cannot both predecrement and postincrement"));
1177 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
1178 registers, no predecrement, no postincrement. */
1179 if (!avr_opt
.all_opcodes
&& (op_mask
& 0x100F)
1180 && !(avr_mcu
->isa
& AVR_ISA_SRAM
))
1181 as_bad (_("addressing mode not supported"));
1187 as_bad (_("can't predecrement"));
1189 if (! (*str
== 'z' || *str
== 'Z'))
1190 as_bad (_("pointer register Z required"));
1192 str
= skip_space (str
+ 1);
1198 for (s
= opcode
->opcode
; *s
; ++s
)
1201 op_mask
|= (1 << (15 - (s
- opcode
->opcode
)));
1205 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1206 if (!avr_opt
.all_opcodes
1207 && (op_mask
& 0x0001)
1208 && !(avr_mcu
->isa
& AVR_ISA_MOVW
))
1209 as_bad (_("postincrement not supported"));
1214 char c
= TOLOWER (*str
++);
1219 as_bad (_("pointer register (Y or Z) required"));
1220 str
= skip_space (str
);
1223 input_line_pointer
= str
;
1224 avr_offset_expression (& op_expr
);
1225 str
= input_line_pointer
;
1226 fix_new_exp (frag_now
, where
, 3,
1227 &op_expr
, FALSE
, BFD_RELOC_AVR_6
);
1233 str
= parse_exp (str
, &op_expr
);
1234 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1235 &op_expr
, FALSE
, BFD_RELOC_AVR_CALL
);
1239 str
= parse_exp (str
, &op_expr
);
1240 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1241 &op_expr
, TRUE
, BFD_RELOC_AVR_13_PCREL
);
1245 str
= parse_exp (str
, &op_expr
);
1246 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1247 &op_expr
, TRUE
, BFD_RELOC_AVR_7_PCREL
);
1251 str
= parse_exp (str
, &op_expr
);
1252 fix_new_exp (frag_now
, where
+ 2, opcode
->insn_size
* 2,
1253 &op_expr
, FALSE
, BFD_RELOC_16
);
1257 str
= parse_exp (str
, &op_expr
);
1258 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1259 &op_expr
, FALSE
, BFD_RELOC_AVR_LDS_STS_16
);
1264 bfd_reloc_code_real_type r_type
;
1266 input_line_pointer
= str
;
1267 r_type
= avr_ldi_expression (&op_expr
);
1268 str
= input_line_pointer
;
1269 fix_new_exp (frag_now
, where
, 3,
1270 &op_expr
, FALSE
, r_type
);
1278 x
= ~avr_get_constant (str
, 255);
1279 str
= input_line_pointer
;
1280 op_mask
|= (x
& 0xf) | ((x
<< 4) & 0xf00);
1288 x
= avr_get_constant (str
, 255);
1289 str
= input_line_pointer
;
1295 input_line_pointer
= str
;
1296 avr_offset_expression (& op_expr
);
1297 str
= input_line_pointer
;
1298 fix_new_exp (frag_now
, where
, 3,
1299 & op_expr
, FALSE
, BFD_RELOC_AVR_6_ADIW
);
1307 x
= avr_get_constant (str
, 7);
1308 str
= input_line_pointer
;
1316 str
= parse_exp (str
, &op_expr
);
1317 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1318 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT6
);
1322 str
= parse_exp (str
, &op_expr
);
1323 fix_new_exp (frag_now
, where
, opcode
->insn_size
* 2,
1324 &op_expr
, FALSE
, BFD_RELOC_AVR_PORT5
);
1331 x
= avr_get_constant (str
, 15);
1332 str
= input_line_pointer
;
1333 op_mask
|= (x
<< 4);
1341 as_bad (_("unknown constraint `%c'"), *op
);
1348 /* TC_FRAG_INIT hook */
1351 avr_frag_init (fragS
*frag
)
1353 memset (& frag
->tc_frag_data
, 0, sizeof frag
->tc_frag_data
);
1357 /* Parse instruction operands.
1358 Return binary opcode. */
1361 avr_operands (struct avr_opcodes_s
*opcode
, char **line
)
1363 const char *op
= opcode
->constraints
;
1364 unsigned int bin
= opcode
->bin_opcode
;
1365 char *frag
= frag_more (opcode
->insn_size
* 2);
1367 int where
= frag
- frag_now
->fr_literal
;
1371 /* Opcode have operands. */
1374 unsigned int reg1
= 0;
1375 unsigned int reg2
= 0;
1376 int reg1_present
= 0;
1377 int reg2_present
= 0;
1379 /* Parse first operand. */
1380 if (REGISTER_P (*op
))
1382 reg1
= avr_operand (opcode
, where
, op
, &str
, ®no1
);
1385 /* Parse second operand. */
1399 if (REGISTER_P (*op
))
1402 str
= skip_space (str
);
1404 as_bad (_("`,' required"));
1405 str
= skip_space (str
);
1407 reg2
= avr_operand (opcode
, where
, op
, &str
, ®no2
);
1410 if (reg1_present
&& reg2_present
)
1411 reg2
= (reg2
& 0xf) | ((reg2
<< 5) & 0x200);
1412 else if (reg2_present
)
1420 if (avr_opt
.have_gccisr
)
1421 avr_update_gccisr (opcode
, regno1
, regno2
);
1423 /* Detect undefined combinations (like ld r31,Z+). */
1424 if (!avr_opt
.all_opcodes
&& AVR_UNDEF_P (bin
))
1425 as_warn (_("undefined combination of operands"));
1427 if (opcode
->insn_size
== 2)
1429 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1430 (AVR core bug, fixed in the newer devices). */
1431 if (!(avr_opt
.no_skip_bug
||
1432 (avr_mcu
->isa
& (AVR_ISA_MUL
| AVR_ISA_MOVW
)))
1433 && AVR_SKIP_P (frag_now
->tc_frag_data
.prev_opcode
))
1434 as_warn (_("skipping two-word instruction"));
1436 bfd_putl32 ((bfd_vma
) bin
, frag
);
1439 bfd_putl16 ((bfd_vma
) bin
, frag
);
1441 frag_now
->tc_frag_data
.prev_opcode
= bin
;
1446 /* GAS will call this function for each section at the end of the assembly,
1447 to permit the CPU backend to adjust the alignment of a section. */
1450 md_section_align (asection
*seg
, valueT addr
)
1452 int align
= bfd_get_section_alignment (stdoutput
, seg
);
1453 return ((addr
+ (1 << align
) - 1) & (-1UL << align
));
1456 /* If you define this macro, it should return the offset between the
1457 address of a PC relative fixup and the position from which the PC
1458 relative adjustment should be made. On many processors, the base
1459 of a PC relative instruction is the next instruction, so this
1460 macro would return the length of an instruction. */
1463 md_pcrel_from_section (fixS
*fixp
, segT sec
)
1465 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1466 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1467 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1470 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1474 relaxable_section (asection
*sec
)
1476 return ((sec
->flags
& SEC_DEBUGGING
) == 0
1477 && (sec
->flags
& SEC_CODE
) != 0
1478 && (sec
->flags
& SEC_ALLOC
) != 0);
1481 /* Does whatever the xtensa port does. */
1483 avr_validate_fix_sub (fixS
*fix
)
1485 segT add_symbol_segment
, sub_symbol_segment
;
1487 /* The difference of two symbols should be resolved by the assembler when
1488 linkrelax is not set. If the linker may relax the section containing
1489 the symbols, then an Xtensa DIFF relocation must be generated so that
1490 the linker knows to adjust the difference value. */
1491 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
1494 /* Make sure both symbols are in the same segment, and that segment is
1495 "normal" and relaxable. If the segment is not "normal", then the
1496 fix is not valid. If the segment is not "relaxable", then the fix
1497 should have been handled earlier. */
1498 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
1499 if (! SEG_NORMAL (add_symbol_segment
) ||
1500 ! relaxable_section (add_symbol_segment
))
1503 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
1504 return (sub_symbol_segment
== add_symbol_segment
);
1507 /* TC_FORCE_RELOCATION hook */
1509 /* If linkrelax is turned on, and the symbol to relocate
1510 against is in a relaxable segment, don't compute the value -
1511 generate a relocation instead. */
1513 avr_force_relocation (fixS
*fix
)
1515 if (linkrelax
&& fix
->fx_addsy
1516 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
1519 return generic_force_reloc (fix
);
1522 /* GAS will call this for each fixup. It should store the correct
1523 value in the object file. */
1526 md_apply_fix (fixS
*fixP
, valueT
* valP
, segT seg
)
1528 unsigned char *where
;
1532 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1535 else if (fixP
->fx_pcrel
)
1537 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
1539 if (s
== seg
|| s
== absolute_section
)
1541 value
+= S_GET_VALUE (fixP
->fx_addsy
);
1545 else if (linkrelax
&& fixP
->fx_subsy
)
1547 /* For a subtraction relocation expression, generate one
1548 of the DIFF relocs, with the value being the difference.
1549 Note that a sym1 - sym2 expression is adjusted into a
1550 section_start_sym + sym4_offset_from_section_start - sym1
1551 expression. fixP->fx_addsy holds the section start symbol,
1552 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1553 holds sym1. Calculate the current difference and write value,
1554 but leave fx_offset as is - during relaxation,
1555 fx_offset - value gives sym1's value. */
1557 switch (fixP
->fx_r_type
)
1560 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF8
;
1563 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF16
;
1566 fixP
->fx_r_type
= BFD_RELOC_AVR_DIFF32
;
1569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1573 value
= S_GET_VALUE (fixP
->fx_addsy
) +
1574 fixP
->fx_offset
- S_GET_VALUE (fixP
->fx_subsy
);
1577 fixP
->fx_subsy
= NULL
;
1579 /* We don't actually support subtracting a symbol. */
1580 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
1583 /* For the DIFF relocs, write the value into the object file while still
1584 keeping fx_done FALSE, as both the difference (recorded in the object file)
1585 and the sym offset (part of fixP) are needed at link relax time. */
1586 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1587 switch (fixP
->fx_r_type
)
1590 fixP
->fx_no_overflow
= 1;
1592 case BFD_RELOC_AVR_7_PCREL
:
1593 case BFD_RELOC_AVR_13_PCREL
:
1597 case BFD_RELOC_AVR_DIFF8
:
1600 case BFD_RELOC_AVR_DIFF16
:
1601 bfd_putl16 ((bfd_vma
) value
, where
);
1603 case BFD_RELOC_AVR_DIFF32
:
1604 bfd_putl32 ((bfd_vma
) value
, where
);
1606 case BFD_RELOC_AVR_CALL
:
1612 /* Fetch the instruction, insert the fully resolved operand
1613 value, and stuff the instruction back again. */
1614 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1615 insn
= bfd_getl16 (where
);
1617 switch (fixP
->fx_r_type
)
1619 case BFD_RELOC_AVR_7_PCREL
:
1621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1622 _("odd address operand: %ld"), value
);
1624 /* Instruction addresses are always right-shifted by 1. */
1626 --value
; /* Correct PC. */
1628 if (value
< -64 || value
> 63)
1629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1630 _("operand out of range: %ld"), value
);
1631 value
= (value
<< 3) & 0x3f8;
1632 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1635 case BFD_RELOC_AVR_13_PCREL
:
1637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1638 _("odd address operand: %ld"), value
);
1640 /* Instruction addresses are always right-shifted by 1. */
1642 --value
; /* Correct PC. */
1644 if (value
< -2048 || value
> 2047)
1646 /* No wrap for devices with >8K of program memory. */
1647 if ((avr_mcu
->isa
& AVR_ISA_MEGA
) || avr_opt
.no_wrap
)
1648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1649 _("operand out of range: %ld"), value
);
1653 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
1657 bfd_putl32 ((bfd_vma
) value
, where
);
1661 bfd_putl16 ((bfd_vma
) value
, where
);
1665 if (value
> 255 || value
< -128)
1666 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1667 _("operand out of range: %ld"), value
);
1671 case BFD_RELOC_AVR_16_PM
:
1672 bfd_putl16 ((bfd_vma
) (value
>> 1), where
);
1675 case BFD_RELOC_AVR_LDI
:
1677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1678 _("operand out of range: %ld"), value
);
1679 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1682 case BFD_RELOC_AVR_LDS_STS_16
:
1683 if ((value
< 0x40) || (value
> 0xBF))
1684 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
1685 _("operand out of range: 0x%lx"),
1686 (unsigned long)value
);
1687 insn
|= ((value
& 0xF) | ((value
& 0x30) << 5) | ((value
& 0x40) << 2));
1688 bfd_putl16 ((bfd_vma
) insn
, where
);
1691 case BFD_RELOC_AVR_6
:
1692 if ((value
> 63) || (value
< 0))
1693 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1694 _("operand out of range: %ld"), value
);
1695 bfd_putl16 ((bfd_vma
) insn
| ((value
& 7) | ((value
& (3 << 3)) << 7)
1696 | ((value
& (1 << 5)) << 8)), where
);
1699 case BFD_RELOC_AVR_6_ADIW
:
1700 if ((value
> 63) || (value
< 0))
1701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1702 _("operand out of range: %ld"), value
);
1703 bfd_putl16 ((bfd_vma
) insn
| (value
& 0xf) | ((value
& 0x30) << 2), where
);
1706 case BFD_RELOC_AVR_LO8_LDI
:
1707 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
), where
);
1710 case BFD_RELOC_AVR_HI8_LDI
:
1711 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 8), where
);
1714 case BFD_RELOC_AVR_MS8_LDI
:
1715 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 24), where
);
1718 case BFD_RELOC_AVR_HH8_LDI
:
1719 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 16), where
);
1722 case BFD_RELOC_AVR_LO8_LDI_NEG
:
1723 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
), where
);
1726 case BFD_RELOC_AVR_HI8_LDI_NEG
:
1727 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 8), where
);
1730 case BFD_RELOC_AVR_MS8_LDI_NEG
:
1731 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 24), where
);
1734 case BFD_RELOC_AVR_HH8_LDI_NEG
:
1735 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 16), where
);
1738 case BFD_RELOC_AVR_LO8_LDI_PM
:
1739 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 1), where
);
1742 case BFD_RELOC_AVR_HI8_LDI_PM
:
1743 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 9), where
);
1746 case BFD_RELOC_AVR_HH8_LDI_PM
:
1747 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (value
>> 17), where
);
1750 case BFD_RELOC_AVR_LO8_LDI_PM_NEG
:
1751 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 1), where
);
1754 case BFD_RELOC_AVR_HI8_LDI_PM_NEG
:
1755 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 9), where
);
1758 case BFD_RELOC_AVR_HH8_LDI_PM_NEG
:
1759 bfd_putl16 ((bfd_vma
) insn
| LDI_IMMEDIATE (-value
>> 17), where
);
1762 case BFD_RELOC_AVR_CALL
:
1766 x
= bfd_getl16 (where
);
1768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1769 _("odd address operand: %ld"), value
);
1771 x
|= ((value
& 0x10000) | ((value
<< 3) & 0x1f00000)) >> 16;
1772 bfd_putl16 ((bfd_vma
) x
, where
);
1773 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
1777 case BFD_RELOC_AVR_8_LO
:
1778 *where
= 0xff & value
;
1781 case BFD_RELOC_AVR_8_HI
:
1782 *where
= 0xff & (value
>> 8);
1785 case BFD_RELOC_AVR_8_HLO
:
1786 *where
= 0xff & (value
>> 16);
1790 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1791 fixP
->fx_line
, fixP
->fx_r_type
);
1794 case BFD_RELOC_AVR_PORT6
:
1796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1797 _("operand out of range: %ld"), value
);
1798 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x30) << 5) | (value
& 0x0f), where
);
1801 case BFD_RELOC_AVR_PORT5
:
1803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1804 _("operand out of range: %ld"), value
);
1805 bfd_putl16 ((bfd_vma
) insn
| ((value
& 0x1f) << 3), where
);
1811 switch ((int) fixP
->fx_r_type
)
1813 case -BFD_RELOC_AVR_HI8_LDI_NEG
:
1814 case -BFD_RELOC_AVR_HI8_LDI
:
1815 case -BFD_RELOC_AVR_LO8_LDI_NEG
:
1816 case -BFD_RELOC_AVR_LO8_LDI
:
1817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1818 _("only constant expression allowed"));
1827 /* GAS will call this to generate a reloc, passing the resulting reloc
1828 to `bfd_install_relocation'. This currently works poorly, as
1829 `bfd_install_relocation' often does the wrong thing, and instances of
1830 `tc_gen_reloc' have been written to work around the problems, which
1831 in turns makes it difficult to fix `bfd_install_relocation'. */
1833 /* If while processing a fixup, a reloc really needs to be created
1834 then it is done here. */
1837 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
,
1841 bfd_reloc_code_real_type code
= fixp
->fx_r_type
;
1843 if (fixp
->fx_subsy
!= NULL
)
1845 as_bad_where (fixp
->fx_file
, fixp
->fx_line
, _("expression too complex"));
1849 reloc
= XNEW (arelent
);
1851 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
1852 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1854 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1856 if ((fixp
->fx_r_type
== BFD_RELOC_32
) && (fixp
->fx_pcrel
))
1858 if (seg
->use_rela_p
)
1859 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, seg
);
1861 fixp
->fx_offset
= reloc
->address
;
1863 code
= BFD_RELOC_32_PCREL
;
1866 reloc
->addend
= fixp
->fx_offset
;
1868 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1870 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1872 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1873 _("reloc %d not supported by object file format"),
1874 (int) fixp
->fx_r_type
);
1878 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1879 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1880 reloc
->address
= fixp
->fx_offset
;
1887 md_assemble (char *str
)
1889 struct avr_opcodes_s
*opcode
;
1892 str
= skip_space (extract_word (str
, op
, sizeof (op
)));
1895 as_bad (_("can't find opcode "));
1897 opcode
= (struct avr_opcodes_s
*) hash_find (avr_hash
, op
);
1899 if (opcode
&& !avr_opt
.all_opcodes
)
1901 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1902 specified by the user. If not look for other instructions
1903 specifications with same mnemonic who's ISA bits matches.
1905 This requires include/opcode/avr.h to have the instructions with
1906 same mnemonic to be specified in sequence. */
1908 while ((opcode
->isa
& avr_mcu
->isa
) != opcode
->isa
)
1912 if (opcode
->name
&& strcmp(op
, opcode
->name
))
1914 as_bad (_("illegal opcode %s for mcu %s"),
1915 opcode
->name
, avr_mcu
->name
);
1923 as_bad (_("unknown opcode `%s'"), op
);
1927 if (opcode
== avr_gccisr_opcode
1928 && !avr_opt
.have_gccisr
)
1930 as_bad (_("pseudo instruction `%s' not supported"), op
);
1934 /* Special case for opcodes with optional operands (lpm, elpm) -
1935 version with operands exists in avr_opcodes[] in the next entry. */
1937 if (*str
&& *opcode
->constraints
== '?')
1940 dwarf2_emit_insn (0);
1942 /* We used to set input_line_pointer to the result of get_operands,
1943 but that is wrong. Our caller assumes we don't change it. */
1945 char *t
= input_line_pointer
;
1947 if (opcode
== avr_gccisr_opcode
)
1948 avr_gccisr_operands (opcode
, &str
);
1950 avr_operands (opcode
, &str
);
1951 if (*skip_space (str
))
1952 as_bad (_("garbage at end of line"));
1953 input_line_pointer
= t
;
1957 const exp_mod_data_t exp_mod_data
[] =
1959 /* Default, must be first. */
1960 { "", 0, BFD_RELOC_16
, "" },
1961 /* Divides by 2 to get word address. Generate Stub. */
1962 { "gs", 2, BFD_RELOC_AVR_16_PM
, "`gs' " },
1963 { "pm", 2, BFD_RELOC_AVR_16_PM
, "`pm' " },
1964 /* The following are used together with avr-gcc's __memx address space
1965 in order to initialize a 24-bit pointer variable with a 24-bit address.
1966 For address in flash, hlo8 will contain the flash segment if the
1967 symbol is located in flash. If the symbol is located in RAM; hlo8
1968 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1969 addresses linearize address space. */
1970 { "lo8", 1, BFD_RELOC_AVR_8_LO
, "`lo8' " },
1971 { "hi8", 1, BFD_RELOC_AVR_8_HI
, "`hi8' " },
1972 { "hlo8", 1, BFD_RELOC_AVR_8_HLO
, "`hlo8' " },
1973 { "hh8", 1, BFD_RELOC_AVR_8_HLO
, "`hh8' " },
1976 /* Parse special CONS expression: pm (expression) or alternatively
1977 gs (expression). These are used for addressing program memory. Moreover,
1978 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1980 const exp_mod_data_t
*
1981 avr_parse_cons_expression (expressionS
*exp
, int nbytes
)
1986 tmp
= input_line_pointer
= skip_space (input_line_pointer
);
1988 /* The first entry of exp_mod_data[] contains an entry if no
1989 expression modifier is present. Skip it. */
1991 for (i
= 0; i
< ARRAY_SIZE (exp_mod_data
); i
++)
1993 const exp_mod_data_t
*pexp
= &exp_mod_data
[i
];
1994 int len
= strlen (pexp
->name
);
1996 if (nbytes
== pexp
->nbytes
1997 && strncasecmp (input_line_pointer
, pexp
->name
, len
) == 0)
1999 input_line_pointer
= skip_space (input_line_pointer
+ len
);
2001 if (*input_line_pointer
== '(')
2003 input_line_pointer
= skip_space (input_line_pointer
+ 1);
2006 if (*input_line_pointer
== ')')
2008 ++input_line_pointer
;
2013 as_bad (_("`)' required"));
2014 return &exp_mod_data
[0];
2018 input_line_pointer
= tmp
;
2025 return &exp_mod_data
[0];
2029 avr_cons_fix_new (fragS
*frag
,
2033 const exp_mod_data_t
*pexp_mod_data
)
2037 switch (pexp_mod_data
->reloc
)
2041 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_8
);
2042 else if (nbytes
== 2)
2043 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_16
);
2044 else if (nbytes
== 4)
2045 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, BFD_RELOC_32
);
2050 case BFD_RELOC_AVR_16_PM
:
2051 case BFD_RELOC_AVR_8_LO
:
2052 case BFD_RELOC_AVR_8_HI
:
2053 case BFD_RELOC_AVR_8_HLO
:
2054 if (nbytes
== pexp_mod_data
->nbytes
)
2055 fix_new_exp (frag
, where
, nbytes
, exp
, FALSE
, pexp_mod_data
->reloc
);
2062 as_bad (_("illegal %s relocation size: %d"), pexp_mod_data
->error
, nbytes
);
2066 mcu_has_3_byte_pc (void)
2068 int mach
= avr_mcu
->mach
;
2070 return mach
== bfd_mach_avr6
2071 || mach
== bfd_mach_avrxmega6
2072 || mach
== bfd_mach_avrxmega7
;
2076 tc_cfi_frame_initial_instructions (void)
2078 /* AVR6 pushes 3 bytes for calls. */
2079 int return_size
= (mcu_has_3_byte_pc () ? 3 : 2);
2081 /* The CFA is the caller's stack location before the call insn. */
2082 /* Note that the stack pointer is dwarf register number 32. */
2083 cfi_add_CFA_def_cfa (32, return_size
);
2085 /* Note that AVR consistently uses post-decrement, which means that things
2086 do not line up the same way as for targets that use pre-decrement. */
2087 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, 1-return_size
);
2091 avr_allow_local_subtract (expressionS
* left
,
2092 expressionS
* right
,
2095 /* If we are not in relaxation mode, subtraction is OK. */
2099 /* If the symbols are not in a code section then they are OK. */
2100 if ((section
->flags
& SEC_CODE
) == 0)
2103 if (left
->X_add_symbol
== right
->X_add_symbol
)
2106 /* We have to assume that there may be instructions between the
2107 two symbols and that relaxation may increase the distance between
2113 avr_elf_final_processing (void)
2116 elf_elfheader (stdoutput
)->e_flags
|= EF_AVR_LINKRELAX_PREPARED
;
2119 /* Write out the header of a .avr.prop section into the area pointed to by
2120 DATA. The RECORD_COUNT will be placed in the header as the number of
2121 records that are to follow.
2122 The area DATA must be big enough the receive the header, which is
2123 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
2126 avr_output_property_section_header (char *data
,
2127 unsigned int record_count
)
2129 char *orig_data
= data
;
2131 md_number_to_chars (data
, AVR_PROPERTY_RECORDS_VERSION
, 1);
2133 /* There's space for a single byte flags field, but right now there's
2134 nothing to go in here, so just set the value to zero. */
2135 md_number_to_chars (data
, 0, 1);
2137 md_number_to_chars (data
, record_count
, 2);
2140 gas_assert (data
- orig_data
== AVR_PROPERTY_SECTION_HEADER_SIZE
);
2145 /* Return the number of bytes required to store RECORD into the .avr.prop
2146 section. The size returned is the compressed size that corresponds to
2147 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
2150 avr_record_size (const struct avr_property_record
*record
)
2152 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
2156 switch (record
->type
)
2159 size
+= 0; /* No extra information. */
2162 case RECORD_ORG_AND_FILL
:
2163 size
+= 4; /* A 4-byte fill value. */
2167 size
+= 4; /* A 4-byte alignment value. */
2170 case RECORD_ALIGN_AND_FILL
:
2171 size
+= 8; /* A 4-byte alignment, and 4-byte fill value. */
2175 as_fatal (_("unknown record type %d (in %s)"),
2176 record
->type
, __PRETTY_FUNCTION__
);
2182 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
2183 to hold all of the .avr.prop content, FRAG_PTR points to the next
2184 writable location. The data area must be big enough to hold all of the
2185 records. The size of the data written out for this RECORD must match
2186 the size from AVR_RECORD_SIZE. */
2189 avr_output_property_record (char * const frag_base
, char *frag_ptr
,
2190 const struct avr_property_record
*record
)
2194 char *init_frag_ptr
= frag_ptr
;
2196 where
= frag_ptr
- frag_base
;
2197 fix
= fix_new (frag_now
, where
, 4,
2198 section_symbol (record
->section
),
2199 record
->offset
, FALSE
, BFD_RELOC_32
);
2200 fix
->fx_file
= "<internal>";
2204 md_number_to_chars (frag_ptr
, (bfd_byte
) record
->type
, 1);
2207 /* Write out the rest of the data. */
2208 switch (record
->type
)
2213 case RECORD_ORG_AND_FILL
:
2214 md_number_to_chars (frag_ptr
, record
->data
.org
.fill
, 4);
2219 md_number_to_chars (frag_ptr
, record
->data
.align
.bytes
, 4);
2223 case RECORD_ALIGN_AND_FILL
:
2224 md_number_to_chars (frag_ptr
, record
->data
.align
.bytes
, 4);
2225 md_number_to_chars (frag_ptr
+ 4, record
->data
.align
.fill
, 4);
2230 as_fatal (_("unknown record type %d (in %s)"),
2231 record
->type
, __PRETTY_FUNCTION__
);
2234 gas_assert (frag_ptr
- init_frag_ptr
== avr_record_size (record
));
2239 /* Create the section to hold the AVR property information. Return the
2243 avr_create_property_section (void)
2246 flagword flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
);
2247 const char *section_name
= AVR_PROPERTY_RECORD_SECTION_NAME
;
2249 sec
= bfd_make_section (stdoutput
, section_name
);
2251 as_fatal (_("Failed to create property section `%s'\n"), section_name
);
2252 bfd_set_section_flags (stdoutput
, sec
, flags
);
2253 sec
->output_section
= sec
;
2257 /* This hook is called when alignment is performed, and allows us to
2258 capture the details of both .org and .align directives. */
2261 avr_handle_align (fragS
*fragP
)
2265 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2266 start of a section, and will be handled by the standard section
2267 alignment mechanism. */
2268 if ((fragP
->fr_type
== rs_align
2269 || fragP
->fr_type
== rs_align_code
)
2270 && fragP
->fr_offset
> 0)
2272 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2274 fragP
->tc_frag_data
.is_align
= TRUE
;
2275 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
2276 fragP
->tc_frag_data
.fill
= *p
;
2277 fragP
->tc_frag_data
.has_fill
= (fragP
->tc_frag_data
.fill
!= 0);
2280 if (fragP
->fr_type
== rs_org
&& fragP
->fr_offset
> 0)
2282 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2284 fragP
->tc_frag_data
.is_org
= TRUE
;
2285 fragP
->tc_frag_data
.fill
= *p
;
2286 fragP
->tc_frag_data
.has_fill
= (fragP
->tc_frag_data
.fill
!= 0);
2291 /* Return TRUE if this section is not one for which we need to record
2292 information in the avr property section. */
2295 exclude_section_from_property_tables (segT sec
)
2297 /* Only generate property information for sections on which linker
2298 relaxation could be performed. */
2299 return !relaxable_section (sec
);
2302 /* Create a property record for fragment FRAGP from section SEC and place
2303 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2304 into a linked list by the caller. */
2306 static struct avr_property_record_link
*
2307 create_record_for_frag (segT sec
, fragS
*fragP
)
2309 struct avr_property_record_link
*prop_rec_link
;
2311 prop_rec_link
= XCNEW (struct avr_property_record_link
);
2312 gas_assert (fragP
->fr_next
!= NULL
);
2314 if (fragP
->tc_frag_data
.is_org
)
2316 prop_rec_link
->record
.offset
= fragP
->fr_next
->fr_address
;
2317 prop_rec_link
->record
.section
= sec
;
2319 if (fragP
->tc_frag_data
.has_fill
)
2321 prop_rec_link
->record
.data
.org
.fill
= fragP
->tc_frag_data
.fill
;
2322 prop_rec_link
->record
.type
= RECORD_ORG_AND_FILL
;
2325 prop_rec_link
->record
.type
= RECORD_ORG
;
2329 prop_rec_link
->record
.offset
= fragP
->fr_next
->fr_address
;
2330 prop_rec_link
->record
.section
= sec
;
2332 gas_assert (fragP
->tc_frag_data
.is_align
);
2333 if (fragP
->tc_frag_data
.has_fill
)
2335 prop_rec_link
->record
.data
.align
.fill
= fragP
->tc_frag_data
.fill
;
2336 prop_rec_link
->record
.type
= RECORD_ALIGN_AND_FILL
;
2339 prop_rec_link
->record
.type
= RECORD_ALIGN
;
2340 prop_rec_link
->record
.data
.align
.bytes
= fragP
->tc_frag_data
.alignment
;
2343 return prop_rec_link
;
2346 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2347 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2348 the last list item created. */
2350 static struct avr_property_record_link
**
2351 append_records_for_section (segT sec
,
2352 struct avr_property_record_link
**next_ptr
)
2354 segment_info_type
*seginfo
= seg_info (sec
);
2357 if (seginfo
&& seginfo
->frchainP
)
2359 for (fragP
= seginfo
->frchainP
->frch_root
;
2361 fragP
= fragP
->fr_next
)
2363 if (fragP
->tc_frag_data
.is_align
2364 || fragP
->tc_frag_data
.is_org
)
2366 /* Create a single new entry. */
2367 struct avr_property_record_link
*new_link
2368 = create_record_for_frag (sec
, fragP
);
2370 *next_ptr
= new_link
;
2371 next_ptr
= &new_link
->next
;
2379 /* Create the AVR property section and fill it with records of .org and
2380 .align directives that were used. The section is only created if it
2381 will actually have any content. */
2384 avr_create_and_fill_property_section (void)
2388 struct avr_property_record_link
*r_list
, **next_ptr
;
2389 char *frag_ptr
, *frag_base
;
2390 bfd_size_type sec_size
;
2391 struct avr_property_record_link
*rec
;
2392 unsigned int record_count
;
2394 /* First walk over all sections. For sections on which linker
2395 relaxation could be applied, extend the record list. The record list
2396 holds information that the linker will need to know. */
2401 for (seclist
= &stdoutput
->sections
;
2402 seclist
&& *seclist
;
2403 seclist
= &(*seclist
)->next
)
2405 segT sec
= *seclist
;
2407 if (exclude_section_from_property_tables (sec
))
2410 next_ptr
= append_records_for_section (sec
, next_ptr
);
2413 /* Create property section and ensure the size is correct. We've already
2414 passed the point where gas could size this for us. */
2415 sec_size
= AVR_PROPERTY_SECTION_HEADER_SIZE
;
2417 for (rec
= r_list
; rec
!= NULL
; rec
= rec
->next
)
2420 sec_size
+= avr_record_size (&rec
->record
);
2423 if (record_count
== 0)
2426 prop_sec
= avr_create_property_section ();
2427 bfd_set_section_size (stdoutput
, prop_sec
, sec_size
);
2429 subseg_set (prop_sec
, 0);
2430 frag_base
= frag_more (sec_size
);
2433 avr_output_property_section_header (frag_base
, record_count
);
2435 for (rec
= r_list
; rec
!= NULL
; rec
= rec
->next
)
2436 frag_ptr
= avr_output_property_record (frag_base
, frag_ptr
, &rec
->record
);
2438 frag_wane (frag_now
);
2440 frag_wane (frag_now
);
2443 /* We're using this hook to build up the AVR property section. It's called
2444 late in the assembly process which suits our needs. */
2446 avr_post_relax_hook (void)
2448 avr_create_and_fill_property_section ();
2452 /* Accumulate information about instruction sequence to `avr_isr':
2453 wheter TMP_REG, ZERO_REG and SREG might be touched. Used during parse.
2454 REG1 is either -1 or a register number used by the instruction as input
2455 or output operand. Similar for REG2. */
2458 avr_update_gccisr (struct avr_opcodes_s
*opcode
, int reg1
, int reg2
)
2460 const int tiny_p
= avr_mcu
->mach
== bfd_mach_avrtiny
;
2461 const int reg_tmp
= tiny_p
? 16 : 0;
2462 const int reg_zero
= 1 + reg_tmp
;
2464 if (ISR_CHUNK_Done
== avr_isr
.prev_chunk
2465 || (avr_isr
.need_sreg
2466 && avr_isr
.need_reg_tmp
2467 && avr_isr
.need_reg_zero
))
2469 /* Nothing (more) to do */
2473 /* SREG: Look up instructions that don't clobber SREG. */
2475 if (!avr_isr
.need_sreg
2476 && !hash_find (avr_no_sreg_hash
, opcode
->name
))
2478 avr_isr
.need_sreg
= 1;
2481 /* Handle explicit register operands. Record *any* use as clobber.
2482 This is because TMP_REG and ZERO_REG are not global and using
2483 them makes no sense without a previous set. */
2485 avr_isr
.need_reg_tmp
|= reg1
== reg_tmp
|| reg2
== reg_tmp
;
2486 avr_isr
.need_reg_zero
|= reg1
== reg_zero
|| reg2
== reg_zero
;
2488 /* Handle implicit register operands and some opaque stuff. */
2490 if (strstr (opcode
->name
, "lpm")
2491 && '?' == *opcode
->constraints
)
2493 avr_isr
.need_reg_tmp
= 1;
2496 if (strstr (opcode
->name
, "call")
2497 || strstr (opcode
->name
, "mul")
2498 || 0 == strcmp (opcode
->name
, "des")
2499 || (0 == strcmp (opcode
->name
, "movw")
2500 && (reg1
== reg_tmp
|| reg2
== reg_tmp
)))
2502 avr_isr
.need_reg_tmp
= 1;
2503 avr_isr
.need_reg_zero
= 1;
2508 /* Emit some 1-word instruction to **PWHERE and advance *PWHERE by the number
2509 of octets written. INSN specifies the desired instruction and REG is the
2510 register used by it. This function is only used with restricted subset of
2511 instructions as might be emit by `__gcc_isr'. IN / OUT will use SREG
2515 avr_emit_insn (const char *insn
, int reg
, char **pwhere
)
2517 const int sreg
= 0x3f;
2519 const struct avr_opcodes_s
*op
2520 = (struct avr_opcodes_s
*) hash_find (avr_hash
, insn
);
2522 /* We only have to deal with: IN, OUT, PUSH, POP, CLR, LDI 0. All of
2523 these deal with at least one Reg and are 1-word instructions. */
2525 gas_assert (op
&& 1 == op
->insn_size
);
2526 gas_assert (reg
>= 0 && reg
<= 31);
2528 if (strchr (op
->constraints
, 'r'))
2530 bin
= op
->bin_opcode
| (reg
<< 4);
2532 else if (strchr (op
->constraints
, 'd'))
2534 gas_assert (reg
>= 16);
2535 bin
= op
->bin_opcode
| ((reg
& 0xf) << 4);
2540 if (strchr (op
->constraints
, 'P'))
2542 bin
|= ((sreg
& 0x30) << 5) | (sreg
& 0x0f);
2544 else if (0 == strcmp ("r=r", op
->constraints
))
2546 bin
|= ((reg
& 0x10) << 5) | (reg
& 0x0f);
2549 gas_assert (0 == strcmp ("r", op
->constraints
)
2550 || 0 == strcmp ("ldi", op
->name
));
2552 bfd_putl16 ((bfd_vma
) bin
, *pwhere
);
2553 (*pwhere
) += 2 * op
->insn_size
;
2557 /* Turn rs_machine_dependent frag *FR into an ordinary rs_fill code frag,
2558 using information gathered in `avr_isr'. REG is the register number as
2559 supplied by Done chunk "__gcc_isr 0,REG". */
2562 avr_patch_gccisr_frag (fragS
*fr
, int reg
)
2566 char *where
= fr
->fr_literal
;
2567 const int tiny_p
= avr_mcu
->mach
== bfd_mach_avrtiny
;
2568 const int reg_tmp
= tiny_p
? 16 : 0;
2569 const int reg_zero
= 1 + reg_tmp
;
2571 /* Clearing ZERO_REG on non-Tiny needs CLR which clobbers SREG. */
2573 avr_isr
.need_sreg
|= !tiny_p
&& avr_isr
.need_reg_zero
;
2575 /* A working register to PUSH / POP the SREG. We might use the register
2576 as supplied by ISR_CHUNK_Done for that purpose as GCC wants to push
2577 it anyways. If GCC passes ZERO_REG or TMP_REG, it has no clue (and
2578 no additional regs to safe) and we use that reg. */
2581 = avr_isr
.need_reg_tmp
? reg_tmp
2582 : avr_isr
.need_reg_zero
? reg_zero
2583 : avr_isr
.need_sreg
? reg
2584 : reg
> reg_zero
? reg
2589 /* Non-empty prologue / epilogue */
2591 if (ISR_CHUNK_Prologue
== fr
->fr_subtype
)
2593 avr_emit_insn ("push", treg
, &where
);
2596 if (avr_isr
.need_sreg
)
2598 avr_emit_insn ("in", treg
, &where
);
2599 avr_emit_insn ("push", treg
, &where
);
2603 if (avr_isr
.need_reg_zero
)
2605 if (reg_zero
!= treg
)
2607 avr_emit_insn ("push", reg_zero
, &where
);
2610 avr_emit_insn (tiny_p
? "ldi" : "clr", reg_zero
, &where
);
2613 if (reg
> reg_zero
&& reg
!= treg
)
2615 avr_emit_insn ("push", reg
, &where
);
2619 else if (ISR_CHUNK_Epilogue
== fr
->fr_subtype
)
2621 /* Same logic as in Prologue but in reverse order and with counter
2622 parts of either instruction: POP instead of PUSH and OUT instead
2623 of IN. Clearing ZERO_REG has no couter part. */
2625 if (reg
> reg_zero
&& reg
!= treg
)
2626 avr_emit_insn ("pop", reg
, &where
);
2628 if (avr_isr
.need_reg_zero
2629 && reg_zero
!= treg
)
2630 avr_emit_insn ("pop", reg_zero
, &where
);
2632 if (avr_isr
.need_sreg
)
2634 avr_emit_insn ("pop", treg
, &where
);
2635 avr_emit_insn ("out", treg
, &where
);
2638 avr_emit_insn ("pop", treg
, &where
);
2644 if (ISR_CHUNK_Prologue
== fr
->fr_subtype
2645 && avr_isr
.sym_n_pushed
)
2647 symbolS
*sy
= avr_isr
.sym_n_pushed
;
2648 /* Turn magic `__gcc_isr.n_pushed' into its now known value. */
2650 sy
->sy_value
.X_op
= O_constant
;
2651 sy
->sy_value
.X_add_number
= n_pushed
;
2652 S_SET_SEGMENT (sy
, expr_section
);
2653 avr_isr
.sym_n_pushed
= NULL
;
2656 /* Turn frag into ordinary code frag of now known size. */
2659 fr
->fr_fix
= (offsetT
) (where
- fr
->fr_literal
);
2660 gas_assert (fr
->fr_fix
<= fr
->fr_offset
);
2662 fr
->fr_type
= rs_fill
;
2667 /* Implements `__gcc_isr' pseudo-instruction. For Prologue and Epilogue
2668 chunks, emit a new rs_machine_dependent frag. For Done chunks, traverse
2669 the current segment and patch all rs_machine_dependent frags to become
2670 appropriate rs_fill code frags. If chunks are seen in an odd ordering,
2671 throw an error instead. */
2674 avr_gccisr_operands (struct avr_opcodes_s
*opcode
, char **line
)
2680 gas_assert (avr_opt
.have_gccisr
);
2682 /* We only use operands "N" and "r" which don't pop new fix-ups. */
2684 /* 1st operand: Which chunk of __gcc_isr: 0...2. */
2686 chunk
= avr_operand (opcode
, -1, "N", &str
, NULL
);
2687 if (chunk
< 0 || chunk
> 2)
2688 as_bad (_("%s requires value 0-2 as operand 1"), opcode
->name
);
2690 if (ISR_CHUNK_Done
== chunk
)
2692 /* 2nd operand: A register to push / pop. */
2694 str
= skip_space (str
);
2695 if (*str
== '\0' || *str
++ != ',')
2696 as_bad (_("`,' required"));
2698 avr_operand (opcode
, -1, "r", &str
, ®
);
2703 /* Chunks must follow in a specific order:
2704 - Prologue: Exactly one
2705 - Epilogue: Any number
2706 - Done: Exactly one. */
2707 bad
|= ISR_CHUNK_Prologue
== chunk
&& avr_isr
.prev_chunk
!= ISR_CHUNK_Done
;
2708 bad
|= ISR_CHUNK_Epilogue
== chunk
&& avr_isr
.prev_chunk
== ISR_CHUNK_Done
;
2709 bad
|= ISR_CHUNK_Done
== chunk
&& avr_isr
.prev_chunk
== ISR_CHUNK_Done
;
2713 as_bad (_("`%s %d' after `%s %d' from %s:%u"), opcode
->name
, chunk
,
2714 opcode
->name
, avr_isr
.prev_chunk
, avr_isr
.file
, avr_isr
.line
);
2716 as_bad (_("`%s %d' but no chunk open yet"), opcode
->name
, chunk
);
2721 /* The longest sequence (prologue) might have up to 6 insns (words):
2730 unsigned int size
= 2 * 6;
2735 case ISR_CHUNK_Prologue
:
2736 avr_isr
.need_reg_tmp
= 0;
2737 avr_isr
.need_reg_zero
= 0;
2738 avr_isr
.need_sreg
= 0;
2739 avr_isr
.sym_n_pushed
= NULL
;
2742 case ISR_CHUNK_Epilogue
:
2743 /* Emit a new rs_machine_dependent fragment into the fragment chain.
2744 It will be patched and cleaned up once we see the matching
2746 frag_wane (frag_now
);
2750 frag_now
->fr_var
= 1;
2751 frag_now
->fr_offset
= size
;
2752 frag_now
->fr_fix
= 0;
2753 frag_now
->fr_type
= rs_machine_dependent
;
2754 frag_now
->fr_subtype
= chunk
;
2758 case ISR_CHUNK_Done
:
2759 /* Traverse all frags of the current subseg and turn ones of type
2760 rs_machine_dependent into ordinary code as expected by GCC. */
2762 for (fr
= frchain_now
->frch_root
; fr
; fr
= fr
->fr_next
)
2763 if (fr
->fr_type
== rs_machine_dependent
)
2764 avr_patch_gccisr_frag (fr
, reg
);
2773 avr_isr
.prev_chunk
= chunk
;
2774 avr_isr
.file
= as_where (&avr_isr
.line
);
2778 /* Callback used by the function below. Diagnose any dangling stuff from
2779 `__gcc_isr', i.e. frags of type rs_machine_dependent. Such frags should
2780 have been resolved during parse by ISR_CHUNK_Done. If such a frag is
2781 seen, report an error and turn it into something harmless. */
2784 avr_check_gccisr_done (bfd
*abfd ATTRIBUTE_UNUSED
,
2786 void *xxx ATTRIBUTE_UNUSED
)
2788 segment_info_type
*info
= seg_info (section
);
2790 if (SEG_NORMAL (section
)
2791 /* BFD may have introduced its own sections without using
2792 subseg_new, so it is possible that seg_info is NULL. */
2798 for (frch
= info
->frchainP
; frch
; frch
= frch
->frch_next
)
2799 for (fr
= frch
->frch_root
; fr
; fr
= fr
->fr_next
)
2800 if (fr
->fr_type
== rs_machine_dependent
)
2803 as_bad_where (avr_isr
.file
, avr_isr
.line
,
2804 _("dangling `__gcc_isr %d'"), avr_isr
.prev_chunk
);
2805 else if (!had_errors())
2806 as_bad (_("dangling `__gcc_isr'"));
2808 avr_isr
.file
= NULL
;
2810 /* Avoid Internal errors due to rs_machine_dependent in the
2811 remainder: Turn frag into something harmless. */
2815 fr
->fr_type
= rs_fill
;
2822 /* Implement `md_pre_output_hook' */
2823 /* Run over all relevant sections and diagnose any dangling `__gcc_isr'.
2824 This runs after parsing all inputs but before relaxing and writing. */
2827 avr_pre_output_hook (void)
2829 if (avr_opt
.have_gccisr
)
2830 bfd_map_over_sections (stdoutput
, avr_check_gccisr_done
, NULL
);