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Define DIFF_EXPR_OK for avr target to allow PC relative difference relocation.
[deliverable/binutils-gdb.git] / gas / config / tc-avr.c
1 /* tc-avr.c -- Assembler code for the ATMEL AVR
2
3 Copyright (C) 1999-2015 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "elf/avr.h"
29 #include "elf32-avr.h"
30
31 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
32 struct avr_property_record_link
33 {
34 struct avr_property_record record;
35 struct avr_property_record_link *next;
36 };
37
38 struct avr_opcodes_s
39 {
40 char * name;
41 char * constraints;
42 char * opcode;
43 int insn_size; /* In words. */
44 int isa;
45 unsigned int bin_opcode;
46 };
47
48 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
49 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
50
51 struct avr_opcodes_s avr_opcodes[] =
52 {
53 #include "opcode/avr.h"
54 {NULL, NULL, NULL, 0, 0, 0}
55 };
56
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "$";
60
61 const char *md_shortopts = "m:";
62 struct mcu_type_s
63 {
64 char *name;
65 int isa;
66 int mach;
67 };
68
69 /* XXX - devices that don't seem to exist (renamed, replaced with larger
70 ones, or planned but never produced), left here for compatibility. */
71
72 static struct mcu_type_s mcu_types[] =
73 {
74 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
75 /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
76 but set to AVR_ISA_AVR25 for some following version
77 of GCC (from 4.3) for backward compatibility. */
78 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
79 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
80 /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
81 but set to AVR_ISA_AVR3_ALL for some following version
82 of GCC (from 4.3) for backward compatibility. */
83 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
84 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
85 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
86 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
87 /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
88 but set to AVR_ISA_AVR51 for some following version
89 of GCC (from 4.3) for backward compatibility. */
90 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
91 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
92 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
93 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
94 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
95 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
96 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
97 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
98 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
99 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
100 {"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
101 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
102 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
103 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
104 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
105 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
106 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
107 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
108 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
109 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
110 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
111 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
112 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
113 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
114 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
115 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
116 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
117 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
118 {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25},
119 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
120 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
121 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
122 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
123 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
124 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
125 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
126 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
127 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
128 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
129 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
130 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
131 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
132 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
133 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
134 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
135 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
136 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
137 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
138 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
139 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
140 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
141 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
142 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
143 {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25},
144 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
145 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
146 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
147 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
148 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
149 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
150 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
151 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
152 {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35},
153 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
154 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
155 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
156 {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35},
157 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
158 {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4},
159 {"atmega8a", AVR_ISA_M8, bfd_mach_avr4},
160 {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4},
161 {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4},
162 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
163 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
164 {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4},
165 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
166 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
167 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
168 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
169 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
170 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
171 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
172 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
173 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
174 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
175 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
176 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
177 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
178 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
179 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
180 {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5},
181 {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5},
182 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
183 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
184 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
185 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
186 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
187 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
188 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
189 {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5},
190 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
191 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
192 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
193 {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5},
194 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
195 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
196 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
197 {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5},
198 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
199 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
200 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
201 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
202 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
203 {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5},
204 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
205 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
206 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
207 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
208 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
209 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
210 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
211 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
212 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
213 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
214 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
215 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
216 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
217 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
218 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
219 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
220 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
221 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
222 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
223 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
224 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
225 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
226 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
227 {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5},
228 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
229 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
230 {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5},
231 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
232 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
233 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
234 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
235 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
236 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
237 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
238 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
239 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
240 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
241 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
242 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
243 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
244 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
245 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
246 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
247 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
248 {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
249 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
250 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
251 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
252 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
253 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
254 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
255 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
256 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
257 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
258 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
259 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
260 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
261 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
262 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
263 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
264 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
265 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
266 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
267 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
268 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
269 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
270 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
271 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
272 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
273 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
274 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
275 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
276 {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51},
277 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
278 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
279 {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51},
280 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
281 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
282 {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
283 {"atmega1284rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
284 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
285 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
286 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
287 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
288 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
289 {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
290 {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
291 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
292 {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
293 {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
294 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
295 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
296 {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
297 {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
298 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
299 {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
300 {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
301 {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
302 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
303 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
304 {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
305 {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
306 {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
307 {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
308 {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
309 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
310 {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
311 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
312 {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5},
313 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
314 {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
315 {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
316 {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
317 {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
318 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
319 {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
320 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
321 {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
322 {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
323 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
324 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
325 {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
326 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
327 {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
328 {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
329 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
330 {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
331 {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
332 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
333 {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
334 {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
335 {"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
336 {"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
337 {"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
338 {"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
339 {"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
340 {"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
341 {NULL, 0, 0}
342 };
343
344
345 /* Current MCU type. */
346 static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
347 static struct mcu_type_s specified_mcu;
348 static struct mcu_type_s * avr_mcu = & default_mcu;
349
350 /* AVR target-specific switches. */
351 struct avr_opt_s
352 {
353 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
354 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
355 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
356 int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not)
357 relocations for linker relaxation. */
358 };
359
360 static struct avr_opt_s avr_opt = { 0, 0, 0, 0 };
361
362 const char EXP_CHARS[] = "eE";
363 const char FLT_CHARS[] = "dD";
364
365 static void avr_set_arch (int);
366
367 /* The target specific pseudo-ops which we support. */
368 const pseudo_typeS md_pseudo_table[] =
369 {
370 {"arch", avr_set_arch, 0},
371 { NULL, NULL, 0}
372 };
373
374 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
375
376 #define EXP_MOD_NAME(i) exp_mod[i].name
377 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
378 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
379 #define HAVE_PM_P(i) exp_mod[i].have_pm
380
381 struct exp_mod_s
382 {
383 char * name;
384 bfd_reloc_code_real_type reloc;
385 bfd_reloc_code_real_type neg_reloc;
386 int have_pm;
387 };
388
389 static struct exp_mod_s exp_mod[] =
390 {
391 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
392 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
393 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
394 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
395 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
396 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
397 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
398 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
399 };
400
401 /* A union used to store indicies into the exp_mod[] array
402 in a hash table which expects void * data types. */
403 typedef union
404 {
405 void * ptr;
406 int index;
407 } mod_index;
408
409 /* Opcode hash table. */
410 static struct hash_control *avr_hash;
411
412 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
413 static struct hash_control *avr_mod_hash;
414
415 #define OPTION_MMCU 'm'
416 enum options
417 {
418 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
419 OPTION_NO_SKIP_BUG,
420 OPTION_NO_WRAP,
421 OPTION_ISA_RMW,
422 OPTION_LINK_RELAX,
423 OPTION_NO_LINK_RELAX
424 };
425
426 struct option md_longopts[] =
427 {
428 { "mmcu", required_argument, NULL, OPTION_MMCU },
429 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
430 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
431 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
432 { "mrmw", no_argument, NULL, OPTION_ISA_RMW },
433 { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX },
434 { "mno-link-relax", no_argument, NULL, OPTION_NO_LINK_RELAX },
435 { NULL, no_argument, NULL, 0 }
436 };
437
438 size_t md_longopts_size = sizeof (md_longopts);
439
440 /* Display nicely formatted list of known MCU names. */
441
442 static void
443 show_mcu_list (FILE *stream)
444 {
445 int i, x;
446
447 fprintf (stream, _("Known MCU names:"));
448 x = 1000;
449
450 for (i = 0; mcu_types[i].name; i++)
451 {
452 int len = strlen (mcu_types[i].name);
453
454 x += len + 1;
455
456 if (x < 75)
457 fprintf (stream, " %s", mcu_types[i].name);
458 else
459 {
460 fprintf (stream, "\n %s", mcu_types[i].name);
461 x = len + 2;
462 }
463 }
464
465 fprintf (stream, "\n");
466 }
467
468 static inline char *
469 skip_space (char *s)
470 {
471 while (*s == ' ' || *s == '\t')
472 ++s;
473 return s;
474 }
475
476 /* Extract one word from FROM and copy it to TO. */
477
478 static char *
479 extract_word (char *from, char *to, int limit)
480 {
481 char *op_end;
482 int size = 0;
483
484 /* Drop leading whitespace. */
485 from = skip_space (from);
486 *to = 0;
487
488 /* Find the op code end. */
489 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
490 {
491 to[size++] = *op_end++;
492 if (size + 1 >= limit)
493 break;
494 }
495
496 to[size] = 0;
497 return op_end;
498 }
499
500 int
501 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
502 asection *seg ATTRIBUTE_UNUSED)
503 {
504 abort ();
505 return 0;
506 }
507
508 void
509 md_show_usage (FILE *stream)
510 {
511 fprintf (stream,
512 _("AVR Assembler options:\n"
513 " -mmcu=[avr-name] select microcontroller variant\n"
514 " [avr-name] can be:\n"
515 " avr1 - classic AVR core without data RAM\n"
516 " avr2 - classic AVR core with up to 8K program memory\n"
517 " avr25 - classic AVR core with up to 8K program memory\n"
518 " plus the MOVW instruction\n"
519 " avr3 - classic AVR core with up to 64K program memory\n"
520 " avr31 - classic AVR core with up to 128K program memory\n"
521 " avr35 - classic AVR core with up to 64K program memory\n"
522 " plus the MOVW instruction\n"
523 " avr4 - enhanced AVR core with up to 8K program memory\n"
524 " avr5 - enhanced AVR core with up to 64K program memory\n"
525 " avr51 - enhanced AVR core with up to 128K program memory\n"
526 " avr6 - enhanced AVR core with up to 256K program memory\n"
527 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
528 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
529 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
530 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
531 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
532 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
533 " avrtiny - AVR Tiny core with 16 gp registers\n"));
534 fprintf (stream,
535 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
536 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
537 " (default for avr4, avr5)\n"
538 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
539 " (default for avr3, avr5)\n"
540 " -mrmw accept Read-Modify-Write instructions\n"
541 " -mlink-relax generate relocations for linker relaxation (default)\n"
542 " -mno-link-relax don't generate relocations for linker relaxation.\n"
543 ));
544 show_mcu_list (stream);
545 }
546
547 static void
548 avr_set_arch (int dummy ATTRIBUTE_UNUSED)
549 {
550 char str[20];
551
552 input_line_pointer = extract_word (input_line_pointer, str, 20);
553 md_parse_option (OPTION_MMCU, str);
554 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
555 }
556
557 int
558 md_parse_option (int c, char *arg)
559 {
560 switch (c)
561 {
562 case OPTION_MMCU:
563 {
564 int i;
565 char *s = alloca (strlen (arg) + 1);
566
567 {
568 char *t = s;
569 char *arg1 = arg;
570
571 do
572 *t = TOLOWER (*arg1++);
573 while (*t++);
574 }
575
576 for (i = 0; mcu_types[i].name; ++i)
577 if (strcmp (mcu_types[i].name, s) == 0)
578 break;
579
580 if (!mcu_types[i].name)
581 {
582 show_mcu_list (stderr);
583 as_fatal (_("unknown MCU: %s\n"), arg);
584 }
585
586 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
587 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
588 as .arch ... in the asm output at the same time. */
589 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
590 {
591 specified_mcu.name = mcu_types[i].name;
592 specified_mcu.isa |= mcu_types[i].isa;
593 specified_mcu.mach = mcu_types[i].mach;
594 avr_mcu = &specified_mcu;
595 }
596 else
597 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
598 avr_mcu->name, mcu_types[i].name);
599 return 1;
600 }
601 case OPTION_ALL_OPCODES:
602 avr_opt.all_opcodes = 1;
603 return 1;
604 case OPTION_NO_SKIP_BUG:
605 avr_opt.no_skip_bug = 1;
606 return 1;
607 case OPTION_NO_WRAP:
608 avr_opt.no_wrap = 1;
609 return 1;
610 case OPTION_ISA_RMW:
611 specified_mcu.isa |= AVR_ISA_RMW;
612 return 1;
613 case OPTION_LINK_RELAX:
614 avr_opt.no_link_relax = 0;
615 return 1;
616 case OPTION_NO_LINK_RELAX:
617 avr_opt.no_link_relax = 1;
618 return 1;
619 }
620
621 return 0;
622 }
623
624 symbolS *
625 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
626 {
627 return NULL;
628 }
629
630 char *
631 md_atof (int type, char *litP, int *sizeP)
632 {
633 return ieee_md_atof (type, litP, sizeP, FALSE);
634 }
635
636 void
637 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
638 asection *sec ATTRIBUTE_UNUSED,
639 fragS *fragP ATTRIBUTE_UNUSED)
640 {
641 abort ();
642 }
643
644 void
645 md_begin (void)
646 {
647 unsigned int i;
648 struct avr_opcodes_s *opcode;
649
650 avr_hash = hash_new ();
651
652 /* Insert unique names into hash table. This hash table then provides a
653 quick index to the first opcode with a particular name in the opcode
654 table. */
655 for (opcode = avr_opcodes; opcode->name; opcode++)
656 hash_insert (avr_hash, opcode->name, (char *) opcode);
657
658 avr_mod_hash = hash_new ();
659
660 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
661 {
662 mod_index m;
663
664 m.index = i + 10;
665 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
666 }
667
668 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
669 linkrelax = !avr_opt.no_link_relax;
670 }
671
672 /* Resolve STR as a constant expression and return the result.
673 If result greater than MAX then error. */
674
675 static unsigned int
676 avr_get_constant (char *str, int max)
677 {
678 expressionS ex;
679
680 str = skip_space (str);
681 input_line_pointer = str;
682 expression (& ex);
683
684 if (ex.X_op != O_constant)
685 as_bad (_("constant value required"));
686
687 if (ex.X_add_number > max || ex.X_add_number < 0)
688 as_bad (_("number must be positive and less than %d"), max + 1);
689
690 return ex.X_add_number;
691 }
692
693 /* Parse for ldd/std offset. */
694
695 static void
696 avr_offset_expression (expressionS *exp)
697 {
698 char *str = input_line_pointer;
699 char *tmp;
700 char op[8];
701
702 tmp = str;
703 str = extract_word (str, op, sizeof (op));
704
705 input_line_pointer = tmp;
706 expression (exp);
707
708 /* Warn about expressions that fail to use lo8 (). */
709 if (exp->X_op == O_constant)
710 {
711 int x = exp->X_add_number;
712
713 if (x < -255 || x > 255)
714 as_warn (_("constant out of 8-bit range: %d"), x);
715 }
716 }
717
718 /* Parse ordinary expression. */
719
720 static char *
721 parse_exp (char *s, expressionS *op)
722 {
723 input_line_pointer = s;
724 expression (op);
725 if (op->X_op == O_absent)
726 as_bad (_("missing operand"));
727 return input_line_pointer;
728 }
729
730 /* Parse special expressions (needed for LDI command):
731 xx8 (address)
732 xx8 (-address)
733 pm_xx8 (address)
734 pm_xx8 (-address)
735 where xx is: hh, hi, lo. */
736
737 static bfd_reloc_code_real_type
738 avr_ldi_expression (expressionS *exp)
739 {
740 char *str = input_line_pointer;
741 char *tmp;
742 char op[8];
743 int mod;
744 int linker_stubs_should_be_generated = 0;
745
746 tmp = str;
747
748 str = extract_word (str, op, sizeof (op));
749
750 if (op[0])
751 {
752 mod_index m;
753
754 m.ptr = hash_find (avr_mod_hash, op);
755 mod = m.index;
756
757 if (mod)
758 {
759 int closes = 0;
760
761 mod -= 10;
762 str = skip_space (str);
763
764 if (*str == '(')
765 {
766 bfd_reloc_code_real_type reloc_to_return;
767 int neg_p = 0;
768
769 ++str;
770
771 if (strncmp ("pm(", str, 3) == 0
772 || strncmp ("gs(",str,3) == 0
773 || strncmp ("-(gs(",str,5) == 0
774 || strncmp ("-(pm(", str, 5) == 0)
775 {
776 if (HAVE_PM_P (mod))
777 {
778 ++mod;
779 ++closes;
780 }
781 else
782 as_bad (_("illegal expression"));
783
784 if (str[0] == 'g' || str[2] == 'g')
785 linker_stubs_should_be_generated = 1;
786
787 if (*str == '-')
788 {
789 neg_p = 1;
790 ++closes;
791 str += 5;
792 }
793 else
794 str += 3;
795 }
796
797 if (*str == '-' && *(str + 1) == '(')
798 {
799 neg_p ^= 1;
800 ++closes;
801 str += 2;
802 }
803
804 input_line_pointer = str;
805 expression (exp);
806
807 do
808 {
809 if (*input_line_pointer != ')')
810 {
811 as_bad (_("`)' required"));
812 break;
813 }
814 input_line_pointer++;
815 }
816 while (closes--);
817
818 reloc_to_return =
819 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
820 if (linker_stubs_should_be_generated)
821 {
822 switch (reloc_to_return)
823 {
824 case BFD_RELOC_AVR_LO8_LDI_PM:
825 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
826 break;
827 case BFD_RELOC_AVR_HI8_LDI_PM:
828 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
829 break;
830
831 default:
832 /* PR 5523: Do not generate a warning here,
833 legitimate code can trigger this case. */
834 break;
835 }
836 }
837 return reloc_to_return;
838 }
839 }
840 }
841
842 input_line_pointer = tmp;
843 expression (exp);
844
845 /* Warn about expressions that fail to use lo8 (). */
846 if (exp->X_op == O_constant)
847 {
848 int x = exp->X_add_number;
849
850 if (x < -255 || x > 255)
851 as_warn (_("constant out of 8-bit range: %d"), x);
852 }
853
854 return BFD_RELOC_AVR_LDI;
855 }
856
857 /* Parse one instruction operand.
858 Return operand bitmask. Also fixups can be generated. */
859
860 static unsigned int
861 avr_operand (struct avr_opcodes_s *opcode,
862 int where,
863 char *op,
864 char **line)
865 {
866 expressionS op_expr;
867 unsigned int op_mask = 0;
868 char *str = skip_space (*line);
869
870 switch (*op)
871 {
872 /* Any register operand. */
873 case 'w':
874 case 'd':
875 case 'r':
876 case 'a':
877 case 'v':
878 {
879 char * old_str = str;
880 char *lower;
881 char r_name[20];
882
883 str = extract_word (str, r_name, sizeof (r_name));
884 for (lower = r_name; *lower; ++lower)
885 {
886 if (*lower >= 'A' && *lower <= 'Z')
887 *lower += 'a' - 'A';
888 }
889
890 if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0)
891 /* Single-digit register number, ie r0-r9. */
892 op_mask = r_name[1] - '0';
893 else if (r_name[0] == 'r' && ISDIGIT (r_name[1])
894 && ISDIGIT (r_name[2]) && r_name[3] == 0)
895 /* Double-digit register number, ie r10 - r32. */
896 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
897 else if (r_name[0] >= 'x' && r_name[0] <= 'z'
898 && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0)
899 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
900 op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26;
901 else if ((*op == 'v' || *op == 'w')
902 && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0)
903 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
904 op_mask = (r_name[0] - 'x') * 2 + 26;
905 else
906 {
907 /* Numeric or symbolic constant register number. */
908 op_mask = avr_get_constant (old_str, 31);
909 str = input_line_pointer;
910 }
911 }
912
913 if (avr_mcu->mach == bfd_mach_avrtiny)
914 {
915 if (op_mask < 16 || op_mask > 31)
916 {
917 as_bad (_("register name or number from 16 to 31 required"));
918 break;
919 }
920 }
921 else if (op_mask > 31)
922 {
923 as_bad (_("register name or number from 0 to 31 required"));
924 break;
925 }
926
927 switch (*op)
928 {
929 case 'a':
930 if (op_mask < 16 || op_mask > 23)
931 as_bad (_("register r16-r23 required"));
932 op_mask -= 16;
933 break;
934
935 case 'd':
936 if (op_mask < 16)
937 as_bad (_("register number above 15 required"));
938 op_mask -= 16;
939 break;
940
941 case 'v':
942 if (op_mask & 1)
943 as_bad (_("even register number required"));
944 op_mask >>= 1;
945 break;
946
947 case 'w':
948 if ((op_mask & 1) || op_mask < 24)
949 as_bad (_("register r24, r26, r28 or r30 required"));
950 op_mask = (op_mask - 24) >> 1;
951 break;
952 }
953 break;
954
955 case 'e':
956 {
957 char c;
958
959 if (*str == '-')
960 {
961 str = skip_space (str + 1);
962 op_mask = 0x1002;
963 }
964 c = TOLOWER (*str);
965 if (c == 'x')
966 op_mask |= 0x100c;
967 else if (c == 'y')
968 op_mask |= 0x8;
969 else if (c != 'z')
970 as_bad (_("pointer register (X, Y or Z) required"));
971
972 str = skip_space (str + 1);
973 if (*str == '+')
974 {
975 ++str;
976 if (op_mask & 2)
977 as_bad (_("cannot both predecrement and postincrement"));
978 op_mask |= 0x1001;
979 }
980
981 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
982 registers, no predecrement, no postincrement. */
983 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
984 && !(avr_mcu->isa & AVR_ISA_SRAM))
985 as_bad (_("addressing mode not supported"));
986 }
987 break;
988
989 case 'z':
990 if (*str == '-')
991 as_bad (_("can't predecrement"));
992
993 if (! (*str == 'z' || *str == 'Z'))
994 as_bad (_("pointer register Z required"));
995
996 str = skip_space (str + 1);
997
998 if (*str == '+')
999 {
1000 ++str;
1001 char *s;
1002 for (s = opcode->opcode; *s; ++s)
1003 {
1004 if (*s == '+')
1005 op_mask |= (1 << (15 - (s - opcode->opcode)));
1006 }
1007 }
1008
1009 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1010 if (!avr_opt.all_opcodes
1011 && (op_mask & 0x0001)
1012 && !(avr_mcu->isa & AVR_ISA_MOVW))
1013 as_bad (_("postincrement not supported"));
1014 break;
1015
1016 case 'b':
1017 {
1018 char c = TOLOWER (*str++);
1019
1020 if (c == 'y')
1021 op_mask |= 0x8;
1022 else if (c != 'z')
1023 as_bad (_("pointer register (Y or Z) required"));
1024 str = skip_space (str);
1025 if (*str++ == '+')
1026 {
1027 input_line_pointer = str;
1028 avr_offset_expression (& op_expr);
1029 str = input_line_pointer;
1030 fix_new_exp (frag_now, where, 3,
1031 &op_expr, FALSE, BFD_RELOC_AVR_6);
1032 }
1033 }
1034 break;
1035
1036 case 'h':
1037 str = parse_exp (str, &op_expr);
1038 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1039 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
1040 break;
1041
1042 case 'L':
1043 str = parse_exp (str, &op_expr);
1044 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1045 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
1046 break;
1047
1048 case 'l':
1049 str = parse_exp (str, &op_expr);
1050 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1051 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
1052 break;
1053
1054 case 'i':
1055 str = parse_exp (str, &op_expr);
1056 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
1057 &op_expr, FALSE, BFD_RELOC_16);
1058 break;
1059
1060 case 'j':
1061 str = parse_exp (str, &op_expr);
1062 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1063 &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
1064 break;
1065
1066 case 'M':
1067 {
1068 bfd_reloc_code_real_type r_type;
1069
1070 input_line_pointer = str;
1071 r_type = avr_ldi_expression (&op_expr);
1072 str = input_line_pointer;
1073 fix_new_exp (frag_now, where, 3,
1074 &op_expr, FALSE, r_type);
1075 }
1076 break;
1077
1078 case 'n':
1079 {
1080 unsigned int x;
1081
1082 x = ~avr_get_constant (str, 255);
1083 str = input_line_pointer;
1084 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
1085 }
1086 break;
1087
1088 case 'K':
1089 input_line_pointer = str;
1090 avr_offset_expression (& op_expr);
1091 str = input_line_pointer;
1092 fix_new_exp (frag_now, where, 3,
1093 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
1094 break;
1095
1096 case 'S':
1097 case 's':
1098 {
1099 unsigned int x;
1100
1101 x = avr_get_constant (str, 7);
1102 str = input_line_pointer;
1103 if (*op == 'S')
1104 x <<= 4;
1105 op_mask |= x;
1106 }
1107 break;
1108
1109 case 'P':
1110 str = parse_exp (str, &op_expr);
1111 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1112 &op_expr, FALSE, BFD_RELOC_AVR_PORT6);
1113 break;
1114
1115 case 'p':
1116 str = parse_exp (str, &op_expr);
1117 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1118 &op_expr, FALSE, BFD_RELOC_AVR_PORT5);
1119 break;
1120
1121 case 'E':
1122 {
1123 unsigned int x;
1124
1125 x = avr_get_constant (str, 15);
1126 str = input_line_pointer;
1127 op_mask |= (x << 4);
1128 }
1129 break;
1130
1131 case '?':
1132 break;
1133
1134 default:
1135 as_bad (_("unknown constraint `%c'"), *op);
1136 }
1137
1138 *line = str;
1139 return op_mask;
1140 }
1141
1142 /* Parse instruction operands.
1143 Return binary opcode. */
1144
1145 static unsigned int
1146 avr_operands (struct avr_opcodes_s *opcode, char **line)
1147 {
1148 char *op = opcode->constraints;
1149 unsigned int bin = opcode->bin_opcode;
1150 char *frag = frag_more (opcode->insn_size * 2);
1151 char *str = *line;
1152 int where = frag - frag_now->fr_literal;
1153 static unsigned int prev = 0; /* Previous opcode. */
1154
1155 /* Opcode have operands. */
1156 if (*op)
1157 {
1158 unsigned int reg1 = 0;
1159 unsigned int reg2 = 0;
1160 int reg1_present = 0;
1161 int reg2_present = 0;
1162
1163 /* Parse first operand. */
1164 if (REGISTER_P (*op))
1165 reg1_present = 1;
1166 reg1 = avr_operand (opcode, where, op, &str);
1167 ++op;
1168
1169 /* Parse second operand. */
1170 if (*op)
1171 {
1172 if (*op == ',')
1173 ++op;
1174
1175 if (*op == '=')
1176 {
1177 reg2 = reg1;
1178 reg2_present = 1;
1179 }
1180 else
1181 {
1182 if (REGISTER_P (*op))
1183 reg2_present = 1;
1184
1185 str = skip_space (str);
1186 if (*str++ != ',')
1187 as_bad (_("`,' required"));
1188 str = skip_space (str);
1189
1190 reg2 = avr_operand (opcode, where, op, &str);
1191 }
1192
1193 if (reg1_present && reg2_present)
1194 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1195 else if (reg2_present)
1196 reg2 <<= 4;
1197 }
1198 if (reg1_present)
1199 reg1 <<= 4;
1200 bin |= reg1 | reg2;
1201 }
1202
1203 /* Detect undefined combinations (like ld r31,Z+). */
1204 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1205 as_warn (_("undefined combination of operands"));
1206
1207 if (opcode->insn_size == 2)
1208 {
1209 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1210 (AVR core bug, fixed in the newer devices). */
1211 if (!(avr_opt.no_skip_bug ||
1212 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
1213 && AVR_SKIP_P (prev))
1214 as_warn (_("skipping two-word instruction"));
1215
1216 bfd_putl32 ((bfd_vma) bin, frag);
1217 }
1218 else
1219 bfd_putl16 ((bfd_vma) bin, frag);
1220
1221 prev = bin;
1222 *line = str;
1223 return bin;
1224 }
1225
1226 /* GAS will call this function for each section at the end of the assembly,
1227 to permit the CPU backend to adjust the alignment of a section. */
1228
1229 valueT
1230 md_section_align (asection *seg, valueT addr)
1231 {
1232 int align = bfd_get_section_alignment (stdoutput, seg);
1233 return ((addr + (1 << align) - 1) & (-1 << align));
1234 }
1235
1236 /* If you define this macro, it should return the offset between the
1237 address of a PC relative fixup and the position from which the PC
1238 relative adjustment should be made. On many processors, the base
1239 of a PC relative instruction is the next instruction, so this
1240 macro would return the length of an instruction. */
1241
1242 long
1243 md_pcrel_from_section (fixS *fixp, segT sec)
1244 {
1245 if (fixp->fx_addsy != (symbolS *) NULL
1246 && (!S_IS_DEFINED (fixp->fx_addsy)
1247 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1248 return 0;
1249
1250 return fixp->fx_frag->fr_address + fixp->fx_where;
1251 }
1252
1253 static bfd_boolean
1254 relaxable_section (asection *sec)
1255 {
1256 return ((sec->flags & SEC_DEBUGGING) == 0
1257 && (sec->flags & SEC_CODE) != 0
1258 && (sec->flags & SEC_ALLOC) != 0);
1259 }
1260
1261 /* Does whatever the xtensa port does. */
1262 int
1263 avr_validate_fix_sub (fixS *fix)
1264 {
1265 segT add_symbol_segment, sub_symbol_segment;
1266
1267 /* The difference of two symbols should be resolved by the assembler when
1268 linkrelax is not set. If the linker may relax the section containing
1269 the symbols, then an Xtensa DIFF relocation must be generated so that
1270 the linker knows to adjust the difference value. */
1271 if (!linkrelax || fix->fx_addsy == NULL)
1272 return 0;
1273
1274 /* Make sure both symbols are in the same segment, and that segment is
1275 "normal" and relaxable. If the segment is not "normal", then the
1276 fix is not valid. If the segment is not "relaxable", then the fix
1277 should have been handled earlier. */
1278 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
1279 if (! SEG_NORMAL (add_symbol_segment) ||
1280 ! relaxable_section (add_symbol_segment))
1281 return 0;
1282
1283 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
1284 return (sub_symbol_segment == add_symbol_segment);
1285 }
1286
1287 /* TC_FORCE_RELOCATION hook */
1288
1289 /* If linkrelax is turned on, and the symbol to relocate
1290 against is in a relaxable segment, don't compute the value -
1291 generate a relocation instead. */
1292 int
1293 avr_force_relocation (fixS *fix)
1294 {
1295 if (linkrelax && fix->fx_addsy
1296 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
1297 return 1;
1298
1299 return generic_force_reloc (fix);
1300 }
1301
1302 /* GAS will call this for each fixup. It should store the correct
1303 value in the object file. */
1304
1305 void
1306 md_apply_fix (fixS *fixP, valueT * valP, segT seg)
1307 {
1308 unsigned char *where;
1309 unsigned long insn;
1310 long value = *valP;
1311
1312 if (fixP->fx_addsy == (symbolS *) NULL)
1313 fixP->fx_done = 1;
1314
1315 else if (fixP->fx_pcrel)
1316 {
1317 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1318
1319 if (s == seg || s == absolute_section)
1320 {
1321 value += S_GET_VALUE (fixP->fx_addsy);
1322 fixP->fx_done = 1;
1323 }
1324 }
1325 else if (linkrelax && fixP->fx_subsy)
1326 {
1327 /* For a subtraction relocation expression, generate one
1328 of the DIFF relocs, with the value being the difference.
1329 Note that a sym1 - sym2 expression is adjusted into a
1330 section_start_sym + sym4_offset_from_section_start - sym1
1331 expression. fixP->fx_addsy holds the section start symbol,
1332 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1333 holds sym1. Calculate the current difference and write value,
1334 but leave fx_offset as is - during relaxation,
1335 fx_offset - value gives sym1's value. */
1336
1337 switch (fixP->fx_r_type)
1338 {
1339 case BFD_RELOC_8:
1340 fixP->fx_r_type = BFD_RELOC_AVR_DIFF8;
1341 break;
1342 case BFD_RELOC_16:
1343 fixP->fx_r_type = BFD_RELOC_AVR_DIFF16;
1344 break;
1345 case BFD_RELOC_32:
1346 fixP->fx_r_type = BFD_RELOC_AVR_DIFF32;
1347 break;
1348 default:
1349 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1350 break;
1351 }
1352
1353 value = S_GET_VALUE (fixP->fx_addsy) +
1354 fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy);
1355 *valP = value;
1356
1357 fixP->fx_subsy = NULL;
1358 }
1359 /* We don't actually support subtracting a symbol. */
1360 if (fixP->fx_subsy != (symbolS *) NULL)
1361 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1362
1363 /* For the DIFF relocs, write the value into the object file while still
1364 keeping fx_done FALSE, as both the difference (recorded in the object file)
1365 and the sym offset (part of fixP) are needed at link relax time. */
1366 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1367 switch (fixP->fx_r_type)
1368 {
1369 default:
1370 fixP->fx_no_overflow = 1;
1371 break;
1372 case BFD_RELOC_AVR_7_PCREL:
1373 case BFD_RELOC_AVR_13_PCREL:
1374 case BFD_RELOC_32:
1375 case BFD_RELOC_16:
1376 break;
1377 case BFD_RELOC_AVR_DIFF8:
1378 *where = value;
1379 break;
1380 case BFD_RELOC_AVR_DIFF16:
1381 bfd_putl16 ((bfd_vma) value, where);
1382 break;
1383 case BFD_RELOC_AVR_DIFF32:
1384 bfd_putl32 ((bfd_vma) value, where);
1385 break;
1386 case BFD_RELOC_AVR_CALL:
1387 break;
1388 }
1389
1390 if (fixP->fx_done)
1391 {
1392 /* Fetch the instruction, insert the fully resolved operand
1393 value, and stuff the instruction back again. */
1394 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1395 insn = bfd_getl16 (where);
1396
1397 switch (fixP->fx_r_type)
1398 {
1399 case BFD_RELOC_AVR_7_PCREL:
1400 if (value & 1)
1401 as_bad_where (fixP->fx_file, fixP->fx_line,
1402 _("odd address operand: %ld"), value);
1403
1404 /* Instruction addresses are always right-shifted by 1. */
1405 value >>= 1;
1406 --value; /* Correct PC. */
1407
1408 if (value < -64 || value > 63)
1409 as_bad_where (fixP->fx_file, fixP->fx_line,
1410 _("operand out of range: %ld"), value);
1411 value = (value << 3) & 0x3f8;
1412 bfd_putl16 ((bfd_vma) (value | insn), where);
1413 break;
1414
1415 case BFD_RELOC_AVR_13_PCREL:
1416 if (value & 1)
1417 as_bad_where (fixP->fx_file, fixP->fx_line,
1418 _("odd address operand: %ld"), value);
1419
1420 /* Instruction addresses are always right-shifted by 1. */
1421 value >>= 1;
1422 --value; /* Correct PC. */
1423
1424 if (value < -2048 || value > 2047)
1425 {
1426 /* No wrap for devices with >8K of program memory. */
1427 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
1428 as_bad_where (fixP->fx_file, fixP->fx_line,
1429 _("operand out of range: %ld"), value);
1430 }
1431
1432 value &= 0xfff;
1433 bfd_putl16 ((bfd_vma) (value | insn), where);
1434 break;
1435
1436 case BFD_RELOC_32:
1437 bfd_putl32 ((bfd_vma) value, where);
1438 break;
1439
1440 case BFD_RELOC_16:
1441 bfd_putl16 ((bfd_vma) value, where);
1442 break;
1443
1444 case BFD_RELOC_8:
1445 if (value > 255 || value < -128)
1446 as_warn_where (fixP->fx_file, fixP->fx_line,
1447 _("operand out of range: %ld"), value);
1448 *where = value;
1449 break;
1450
1451 case BFD_RELOC_AVR_16_PM:
1452 bfd_putl16 ((bfd_vma) (value >> 1), where);
1453 break;
1454
1455 case BFD_RELOC_AVR_LDI:
1456 if (value > 255)
1457 as_bad_where (fixP->fx_file, fixP->fx_line,
1458 _("operand out of range: %ld"), value);
1459 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1460 break;
1461
1462 case BFD_RELOC_AVR_LDS_STS_16:
1463 if ((value < 0x40) || (value > 0xBF))
1464 as_warn_where (fixP->fx_file, fixP->fx_line,
1465 _("operand out of range: 0x%lx"),
1466 (unsigned long)value);
1467 insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2));
1468 bfd_putl16 ((bfd_vma) insn, where);
1469 break;
1470
1471 case BFD_RELOC_AVR_6:
1472 if ((value > 63) || (value < 0))
1473 as_bad_where (fixP->fx_file, fixP->fx_line,
1474 _("operand out of range: %ld"), value);
1475 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7)
1476 | ((value & (1 << 5)) << 8)), where);
1477 break;
1478
1479 case BFD_RELOC_AVR_6_ADIW:
1480 if ((value > 63) || (value < 0))
1481 as_bad_where (fixP->fx_file, fixP->fx_line,
1482 _("operand out of range: %ld"), value);
1483 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1484 break;
1485
1486 case BFD_RELOC_AVR_LO8_LDI:
1487 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1488 break;
1489
1490 case BFD_RELOC_AVR_HI8_LDI:
1491 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1492 break;
1493
1494 case BFD_RELOC_AVR_MS8_LDI:
1495 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1496 break;
1497
1498 case BFD_RELOC_AVR_HH8_LDI:
1499 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1500 break;
1501
1502 case BFD_RELOC_AVR_LO8_LDI_NEG:
1503 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1504 break;
1505
1506 case BFD_RELOC_AVR_HI8_LDI_NEG:
1507 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1508 break;
1509
1510 case BFD_RELOC_AVR_MS8_LDI_NEG:
1511 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1512 break;
1513
1514 case BFD_RELOC_AVR_HH8_LDI_NEG:
1515 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1516 break;
1517
1518 case BFD_RELOC_AVR_LO8_LDI_PM:
1519 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1520 break;
1521
1522 case BFD_RELOC_AVR_HI8_LDI_PM:
1523 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1524 break;
1525
1526 case BFD_RELOC_AVR_HH8_LDI_PM:
1527 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1528 break;
1529
1530 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1531 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1532 break;
1533
1534 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1535 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1536 break;
1537
1538 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1539 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1540 break;
1541
1542 case BFD_RELOC_AVR_CALL:
1543 {
1544 unsigned long x;
1545
1546 x = bfd_getl16 (where);
1547 if (value & 1)
1548 as_bad_where (fixP->fx_file, fixP->fx_line,
1549 _("odd address operand: %ld"), value);
1550 value >>= 1;
1551 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1552 bfd_putl16 ((bfd_vma) x, where);
1553 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
1554 }
1555 break;
1556
1557 case BFD_RELOC_AVR_8_LO:
1558 *where = 0xff & value;
1559 break;
1560
1561 case BFD_RELOC_AVR_8_HI:
1562 *where = 0xff & (value >> 8);
1563 break;
1564
1565 case BFD_RELOC_AVR_8_HLO:
1566 *where = 0xff & (value >> 16);
1567 break;
1568
1569 default:
1570 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1571 fixP->fx_line, fixP->fx_r_type);
1572 break;
1573
1574 case BFD_RELOC_AVR_PORT6:
1575 if (value > 63)
1576 as_bad_where (fixP->fx_file, fixP->fx_line,
1577 _("operand out of range: %ld"), value);
1578 bfd_putl16 ((bfd_vma) insn | ((value & 0x30) << 5) | (value & 0x0f), where);
1579 break;
1580
1581 case BFD_RELOC_AVR_PORT5:
1582 if (value > 31)
1583 as_bad_where (fixP->fx_file, fixP->fx_line,
1584 _("operand out of range: %ld"), value);
1585 bfd_putl16 ((bfd_vma) insn | ((value & 0x1f) << 3), where);
1586 break;
1587 }
1588 }
1589 else
1590 {
1591 switch ((int) fixP->fx_r_type)
1592 {
1593 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1594 case -BFD_RELOC_AVR_HI8_LDI:
1595 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1596 case -BFD_RELOC_AVR_LO8_LDI:
1597 as_bad_where (fixP->fx_file, fixP->fx_line,
1598 _("only constant expression allowed"));
1599 fixP->fx_done = 1;
1600 break;
1601 default:
1602 break;
1603 }
1604 }
1605 }
1606
1607 /* GAS will call this to generate a reloc, passing the resulting reloc
1608 to `bfd_install_relocation'. This currently works poorly, as
1609 `bfd_install_relocation' often does the wrong thing, and instances of
1610 `tc_gen_reloc' have been written to work around the problems, which
1611 in turns makes it difficult to fix `bfd_install_relocation'. */
1612
1613 /* If while processing a fixup, a reloc really needs to be created
1614 then it is done here. */
1615
1616 arelent *
1617 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1618 fixS *fixp)
1619 {
1620 arelent *reloc;
1621 bfd_reloc_code_real_type code = fixp->fx_r_type;
1622
1623 if (fixp->fx_subsy != NULL)
1624 {
1625 as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex"));
1626 return NULL;
1627 }
1628
1629 reloc = xmalloc (sizeof (arelent));
1630
1631 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1632 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1633
1634 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1635
1636 if ((fixp->fx_r_type == BFD_RELOC_32) && (fixp->fx_pcrel))
1637 {
1638 if (seg->use_rela_p)
1639 fixp->fx_offset -= md_pcrel_from_section (fixp, seg);
1640 else
1641 fixp->fx_offset = reloc->address;
1642
1643 code = BFD_RELOC_32_PCREL;
1644 }
1645
1646 reloc->addend = fixp->fx_offset;
1647
1648 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1649
1650 if (reloc->howto == (reloc_howto_type *) NULL)
1651 {
1652 as_bad_where (fixp->fx_file, fixp->fx_line,
1653 _("reloc %d not supported by object file format"),
1654 (int) fixp->fx_r_type);
1655 return NULL;
1656 }
1657
1658 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1659 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1660 reloc->address = fixp->fx_offset;
1661
1662
1663 return reloc;
1664 }
1665
1666 void
1667 md_assemble (char *str)
1668 {
1669 struct avr_opcodes_s *opcode;
1670 char op[11];
1671
1672 str = skip_space (extract_word (str, op, sizeof (op)));
1673
1674 if (!op[0])
1675 as_bad (_("can't find opcode "));
1676
1677 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1678
1679 if (opcode && !avr_opt.all_opcodes)
1680 {
1681 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1682 specified by the user. If not look for other instructions
1683 specifications with same mnemonic who's ISA bits matches.
1684
1685 This requires include/opcode/avr.h to have the instructions with
1686 same mnenomic to be specified in sequence. */
1687
1688 while ((opcode->isa & avr_mcu->isa) != opcode->isa)
1689 {
1690 opcode++;
1691
1692 if (opcode->name && strcmp(op, opcode->name))
1693 {
1694 as_bad (_("illegal opcode %s for mcu %s"),
1695 opcode->name, avr_mcu->name);
1696 return;
1697 }
1698 }
1699 }
1700
1701 if (opcode == NULL)
1702 {
1703 as_bad (_("unknown opcode `%s'"), op);
1704 return;
1705 }
1706
1707 /* Special case for opcodes with optional operands (lpm, elpm) -
1708 version with operands exists in avr_opcodes[] in the next entry. */
1709
1710 if (*str && *opcode->constraints == '?')
1711 ++opcode;
1712
1713 dwarf2_emit_insn (0);
1714
1715 /* We used to set input_line_pointer to the result of get_operands,
1716 but that is wrong. Our caller assumes we don't change it. */
1717 {
1718 char *t = input_line_pointer;
1719
1720 avr_operands (opcode, &str);
1721 if (*skip_space (str))
1722 as_bad (_("garbage at end of line"));
1723 input_line_pointer = t;
1724 }
1725 }
1726
1727 const exp_mod_data_t exp_mod_data[] =
1728 {
1729 /* Default, must be first. */
1730 { "", 0, BFD_RELOC_16, "" },
1731 /* Divides by 2 to get word address. Generate Stub. */
1732 { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " },
1733 { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " },
1734 /* The following are used together with avr-gcc's __memx address space
1735 in order to initialize a 24-bit pointer variable with a 24-bit address.
1736 For address in flash, hlo8 will contain the flash segment if the
1737 symbol is located in flash. If the symbol is located in RAM; hlo8
1738 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1739 addresses linearize address space. */
1740 { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " },
1741 { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " },
1742 { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " },
1743 { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " },
1744 /* End of list. */
1745 { NULL, 0, 0, NULL }
1746 };
1747
1748 /* Parse special CONS expression: pm (expression) or alternatively
1749 gs (expression). These are used for addressing program memory. Moreover,
1750 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1751
1752 const exp_mod_data_t *
1753 avr_parse_cons_expression (expressionS *exp, int nbytes)
1754 {
1755 const exp_mod_data_t *pexp = &exp_mod_data[0];
1756 char *tmp;
1757
1758 tmp = input_line_pointer = skip_space (input_line_pointer);
1759
1760 /* The first entry of exp_mod_data[] contains an entry if no
1761 expression modifier is present. Skip it. */
1762
1763 for (pexp++; pexp->name; pexp++)
1764 {
1765 int len = strlen (pexp->name);
1766
1767 if (nbytes == pexp->nbytes
1768 && strncasecmp (input_line_pointer, pexp->name, len) == 0)
1769 {
1770 input_line_pointer = skip_space (input_line_pointer + len);
1771
1772 if (*input_line_pointer == '(')
1773 {
1774 input_line_pointer = skip_space (input_line_pointer + 1);
1775 expression (exp);
1776
1777 if (*input_line_pointer == ')')
1778 {
1779 ++input_line_pointer;
1780 return pexp;
1781 }
1782 else
1783 {
1784 as_bad (_("`)' required"));
1785 return &exp_mod_data[0];
1786 }
1787 }
1788
1789 input_line_pointer = tmp;
1790
1791 break;
1792 }
1793 }
1794
1795 expression (exp);
1796 return &exp_mod_data[0];
1797 }
1798
1799 void
1800 avr_cons_fix_new (fragS *frag,
1801 int where,
1802 int nbytes,
1803 expressionS *exp,
1804 const exp_mod_data_t *pexp_mod_data)
1805 {
1806 int bad = 0;
1807
1808 switch (pexp_mod_data->reloc)
1809 {
1810 default:
1811 if (nbytes == 1)
1812 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
1813 else if (nbytes == 2)
1814 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
1815 else if (nbytes == 4)
1816 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
1817 else
1818 bad = 1;
1819 break;
1820
1821 case BFD_RELOC_AVR_16_PM:
1822 case BFD_RELOC_AVR_8_LO:
1823 case BFD_RELOC_AVR_8_HI:
1824 case BFD_RELOC_AVR_8_HLO:
1825 if (nbytes == pexp_mod_data->nbytes)
1826 fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
1827 else
1828 bad = 1;
1829 break;
1830 }
1831
1832 if (bad)
1833 as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes);
1834 }
1835
1836 static bfd_boolean
1837 mcu_has_3_byte_pc (void)
1838 {
1839 int mach = avr_mcu->mach;
1840
1841 return mach == bfd_mach_avr6
1842 || mach == bfd_mach_avrxmega6
1843 || mach == bfd_mach_avrxmega7;
1844 }
1845
1846 void
1847 tc_cfi_frame_initial_instructions (void)
1848 {
1849 /* AVR6 pushes 3 bytes for calls. */
1850 int return_size = (mcu_has_3_byte_pc () ? 3 : 2);
1851
1852 /* The CFA is the caller's stack location before the call insn. */
1853 /* Note that the stack pointer is dwarf register number 32. */
1854 cfi_add_CFA_def_cfa (32, return_size);
1855
1856 /* Note that AVR consistently uses post-decrement, which means that things
1857 do not line up the same way as for targers that use pre-decrement. */
1858 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
1859 }
1860
1861 bfd_boolean
1862 avr_allow_local_subtract (expressionS * left,
1863 expressionS * right,
1864 segT section)
1865 {
1866 /* If we are not in relaxation mode, subtraction is OK. */
1867 if (!linkrelax)
1868 return TRUE;
1869
1870 /* If the symbols are not in a code section then they are OK. */
1871 if ((section->flags & SEC_CODE) == 0)
1872 return TRUE;
1873
1874 if (left->X_add_symbol == right->X_add_symbol)
1875 return TRUE;
1876
1877 /* We have to assume that there may be instructions between the
1878 two symbols and that relaxation may increase the distance between
1879 them. */
1880 return FALSE;
1881 }
1882
1883 void
1884 avr_elf_final_processing (void)
1885 {
1886 if (linkrelax)
1887 elf_elfheader (stdoutput)->e_flags |= EF_AVR_LINKRELAX_PREPARED;
1888 }
1889
1890 /* Write out the header of a .avr.prop section into the area pointed to by
1891 DATA. The RECORD_COUNT will be placed in the header as the number of
1892 records that are to follow.
1893 The area DATA must be big enough the receive the header, which is
1894 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
1895
1896 static char *
1897 avr_output_property_section_header (char *data,
1898 unsigned int record_count)
1899 {
1900 char *orig_data = data;
1901
1902 md_number_to_chars (data, AVR_PROPERTY_RECORDS_VERSION, 1);
1903 data++;
1904 /* There's space for a single byte flags field, but right now there's
1905 nothing to go in here, so just set the value to zero. */
1906 md_number_to_chars (data, 0, 1);
1907 data++;
1908 md_number_to_chars (data, record_count, 2);
1909 data+=2;
1910
1911 gas_assert (data - orig_data == AVR_PROPERTY_SECTION_HEADER_SIZE);
1912
1913 return data;
1914 }
1915
1916 /* Return the number of bytes required to store RECORD into the .avr.prop
1917 section. The size returned is the compressed size that corresponds to
1918 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
1919
1920 static int
1921 avr_record_size (const struct avr_property_record *record)
1922 {
1923 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
1924 identifier. */
1925 int size = 5;
1926
1927 switch (record->type)
1928 {
1929 case RECORD_ORG:
1930 size += 0; /* No extra information. */
1931 break;
1932
1933 case RECORD_ORG_AND_FILL:
1934 size += 4; /* A 4-byte fill value. */
1935 break;
1936
1937 case RECORD_ALIGN:
1938 size += 4; /* A 4-byte alignment value. */
1939 break;
1940
1941 case RECORD_ALIGN_AND_FILL:
1942 size += 8; /* A 4-byte alignment, and 4-byte fill value. */
1943 break;
1944
1945 default:
1946 as_fatal (_("unknown record type %d (in %s)"),
1947 record->type, __PRETTY_FUNCTION__);
1948 }
1949
1950 return size;
1951 }
1952
1953 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
1954 to hold all of the .avr.prop content, FRAG_PTR points to the next
1955 writable location. The data area must be big enough to hold all of the
1956 records. The size of the data written out for this RECORD must match
1957 the size from AVR_RECORD_SIZE. */
1958
1959 static char *
1960 avr_output_property_record (char * const frag_base, char *frag_ptr,
1961 const struct avr_property_record *record)
1962 {
1963 fixS *fix;
1964 int where;
1965 char *init_frag_ptr = frag_ptr;
1966
1967 where = frag_ptr - frag_base;
1968 fix = fix_new (frag_now, where, 4,
1969 section_symbol (record->section),
1970 record->offset, FALSE, BFD_RELOC_32);
1971 fix->fx_file = "<internal>";
1972 fix->fx_line = 0;
1973 frag_ptr += 4;
1974
1975 md_number_to_chars (frag_ptr, (bfd_byte) record->type, 1);
1976 frag_ptr += 1;
1977
1978 /* Write out the rest of the data. */
1979 switch (record->type)
1980 {
1981 case RECORD_ORG:
1982 break;
1983
1984 case RECORD_ORG_AND_FILL:
1985 md_number_to_chars (frag_ptr, record->data.org.fill, 4);
1986 frag_ptr += 4;
1987 break;
1988
1989 case RECORD_ALIGN:
1990 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
1991 frag_ptr += 4;
1992 break;
1993
1994 case RECORD_ALIGN_AND_FILL:
1995 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
1996 md_number_to_chars (frag_ptr, record->data.align.fill, 4);
1997 frag_ptr += 8;
1998 break;
1999
2000 default:
2001 as_fatal (_("unknown record type %d (in %s)"),
2002 record->type, __PRETTY_FUNCTION__);
2003 }
2004
2005 gas_assert (frag_ptr - init_frag_ptr == avr_record_size (record));
2006
2007 return frag_ptr;
2008 }
2009
2010 /* Create the section to hold the AVR property information. Return the
2011 section. */
2012
2013 static asection *
2014 avr_create_property_section (void)
2015 {
2016 asection *sec;
2017 flagword flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY);
2018 const char *section_name = AVR_PROPERTY_RECORD_SECTION_NAME;
2019
2020 sec = bfd_make_section (stdoutput, section_name);
2021 if (sec == NULL)
2022 as_fatal (_("Failed to create property section `%s'\n"), section_name);
2023 bfd_set_section_flags (stdoutput, sec, flags);
2024 sec->output_section = sec;
2025 return sec;
2026 }
2027
2028 /* This hook is called when alignment is performed, and allows us to
2029 capture the details of both .org and .align directives. */
2030
2031 void
2032 avr_handle_align (fragS *fragP)
2033 {
2034 if (linkrelax)
2035 {
2036 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2037 start of a section, and will be handled by the standard section
2038 alignment mechanism. */
2039 if ((fragP->fr_type == rs_align
2040 || fragP->fr_type == rs_align_code)
2041 && fragP->fr_address > 0
2042 && fragP->fr_offset > 0)
2043 {
2044 fragP->tc_frag_data.is_align = TRUE;
2045 fragP->tc_frag_data.alignment = fragP->fr_offset;
2046 }
2047
2048 if (fragP->fr_type == rs_org && fragP->fr_offset > 0)
2049 {
2050 char *p = fragP->fr_literal + fragP->fr_fix;
2051
2052 fragP->tc_frag_data.is_org = TRUE;
2053 fragP->tc_frag_data.fill = *p;
2054 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2055 }
2056 }
2057 }
2058
2059 /* Return TRUE if this section is not one for which we need to record
2060 information in the avr property section. */
2061
2062 static bfd_boolean
2063 exclude_section_from_property_tables (segT sec)
2064 {
2065 /* Only generate property information for sections on which linker
2066 relaxation could be performed. */
2067 return !relaxable_section (sec);
2068 }
2069
2070 /* Create a property record for fragment FRAGP from section SEC and place
2071 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2072 into a linked list by the caller. */
2073
2074 static struct avr_property_record_link *
2075 create_record_for_frag (segT sec, fragS *fragP)
2076 {
2077 struct avr_property_record_link *prop_rec_link;
2078
2079 prop_rec_link = xmalloc (sizeof (struct avr_property_record_link));
2080 memset (prop_rec_link, 0, sizeof (*prop_rec_link));
2081
2082 if (fragP->tc_frag_data.is_org)
2083 {
2084 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2085 prop_rec_link->record.section = sec;
2086
2087 if (fragP->tc_frag_data.has_fill)
2088 {
2089 prop_rec_link->record.data.org.fill = fragP->tc_frag_data.fill;
2090 prop_rec_link->record.type = RECORD_ORG_AND_FILL;
2091 }
2092 else
2093 prop_rec_link->record.type = RECORD_ORG;
2094 }
2095 else
2096 {
2097 prop_rec_link->record.offset = fragP->fr_address;
2098 prop_rec_link->record.section = sec;
2099
2100 gas_assert (fragP->tc_frag_data.is_align);
2101 if (fragP->tc_frag_data.has_fill)
2102 {
2103 prop_rec_link->record.data.align.fill = fragP->tc_frag_data.fill;
2104 prop_rec_link->record.type = RECORD_ALIGN_AND_FILL;
2105 }
2106 else
2107 prop_rec_link->record.type = RECORD_ALIGN;
2108 prop_rec_link->record.data.align.bytes = fragP->tc_frag_data.alignment;
2109 }
2110
2111 return prop_rec_link;
2112 }
2113
2114 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2115 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2116 the last list item created. */
2117
2118 static struct avr_property_record_link **
2119 append_records_for_section (segT sec,
2120 struct avr_property_record_link **next_ptr)
2121 {
2122 segment_info_type *seginfo = seg_info (sec);
2123 fragS *fragP;
2124
2125 if (seginfo && seginfo->frchainP)
2126 {
2127 for (fragP = seginfo->frchainP->frch_root;
2128 fragP;
2129 fragP = fragP->fr_next)
2130 {
2131 if (fragP->tc_frag_data.is_align
2132 || fragP->tc_frag_data.is_org)
2133 {
2134 /* Create a single new entry. */
2135 struct avr_property_record_link *new_link
2136 = create_record_for_frag (sec, fragP);
2137
2138 *next_ptr = new_link;
2139 next_ptr = &new_link->next;
2140 }
2141 }
2142 }
2143
2144 return next_ptr;
2145 }
2146
2147 /* Create the AVR property section and fill it with records of .org and
2148 .align directives that were used. The section is only created if it
2149 will actually have any content. */
2150
2151 static void
2152 avr_create_and_fill_property_section (void)
2153 {
2154 segT *seclist;
2155 asection *prop_sec;
2156 struct avr_property_record_link *r_list, **next_ptr;
2157 char *frag_ptr, *frag_base;
2158 bfd_size_type sec_size;
2159 struct avr_property_record_link *rec;
2160 unsigned int record_count;
2161
2162 /* First walk over all sections. For sections on which linker
2163 relaxation could be applied, extend the record list. The record list
2164 holds information that the linker will need to know. */
2165
2166 prop_sec = NULL;
2167 r_list = NULL;
2168 next_ptr = &r_list;
2169 for (seclist = &stdoutput->sections;
2170 seclist && *seclist;
2171 seclist = &(*seclist)->next)
2172 {
2173 segT sec = *seclist;
2174
2175 if (exclude_section_from_property_tables (sec))
2176 continue;
2177
2178 next_ptr = append_records_for_section (sec, next_ptr);
2179 }
2180
2181 /* Create property section and ensure the size is correct. We've already
2182 passed the point where gas could size this for us. */
2183 sec_size = AVR_PROPERTY_SECTION_HEADER_SIZE;
2184 record_count = 0;
2185 for (rec = r_list; rec != NULL; rec = rec->next)
2186 {
2187 record_count++;
2188 sec_size += avr_record_size (&rec->record);
2189 }
2190
2191 if (record_count == 0)
2192 return;
2193
2194 prop_sec = avr_create_property_section ();
2195 bfd_set_section_size (stdoutput, prop_sec, sec_size);
2196
2197 subseg_set (prop_sec, 0);
2198 frag_base = frag_more (sec_size);
2199
2200 frag_ptr =
2201 avr_output_property_section_header (frag_base, record_count);
2202
2203 for (rec = r_list; rec != NULL; rec = rec->next)
2204 frag_ptr = avr_output_property_record (frag_base, frag_ptr, &rec->record);
2205
2206 frag_wane (frag_now);
2207 frag_new (0);
2208 frag_wane (frag_now);
2209 }
2210
2211 /* We're using this hook to build up the AVR property section. It's called
2212 late in the assembly process which suits our needs. */
2213 void
2214 avr_post_relax_hook (void)
2215 {
2216 avr_create_and_fill_property_section ();
2217 }
GDB Binutils - Deliverables
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