1 /* tc-bfin.c -- Assembler for the ADI Blackfin.
2 Copyright 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "struc-symbol.h"
24 #include "bfin-defs.h"
26 #include "safe-ctype.h"
28 #include "dwarf2dbg.h"
31 #include "elf/common.h"
34 extern int yyparse (void);
35 struct yy_buffer_state
;
36 typedef struct yy_buffer_state
*YY_BUFFER_STATE
;
37 extern YY_BUFFER_STATE
yy_scan_string (const char *yy_str
);
38 extern void yy_delete_buffer (YY_BUFFER_STATE b
);
39 static parse_state
parse (char *line
);
41 /* Global variables. */
42 struct bfin_insn
*insn
;
45 extern struct obstack mempool
;
48 /* Flags to set in the elf header */
49 #define DEFAULT_FLAGS 0
52 # define DEFAULT_FDPIC EF_BFIN_FDPIC
54 # define DEFAULT_FDPIC 0
57 static flagword bfin_flags
= DEFAULT_FLAGS
| DEFAULT_FDPIC
;
58 static const char *bfin_pic_flag
= DEFAULT_FDPIC
? "-mfdpic" : (const char *)0;
60 /* Blackfin specific function to handle FD-PIC pointer initializations. */
63 bfin_pic_ptr (int nbytes
)
71 #ifdef md_flush_pending_output
72 md_flush_pending_output ();
75 if (is_it_end_of_statement ())
77 demand_empty_rest_of_line ();
82 md_cons_align (nbytes
);
87 bfd_reloc_code_real_type reloc_type
= BFD_RELOC_BFIN_FUNCDESC
;
89 if (strncasecmp (input_line_pointer
, "funcdesc(", 9) == 0)
91 input_line_pointer
+= 9;
93 if (*input_line_pointer
== ')')
96 as_bad (_("missing ')'"));
99 error ("missing funcdesc in picptr");
103 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
106 while (*input_line_pointer
++ == ',');
108 input_line_pointer
--; /* Put terminator back into stream. */
109 demand_empty_rest_of_line ();
113 bfin_s_bss (int ignore ATTRIBUTE_UNUSED
)
117 temp
= get_absolute_expression ();
118 subseg_set (bss_section
, (subsegT
) temp
);
119 demand_empty_rest_of_line ();
122 const pseudo_typeS md_pseudo_table
[] = {
123 {"align", s_align_bytes
, 0},
126 {"picptr", bfin_pic_ptr
, 4},
127 {"code", obj_elf_section
, 0},
132 {"pdata", s_ignore
, 0},
133 {"var", s_ignore
, 0},
134 {"bss", bfin_s_bss
, 0},
138 /* Characters that are used to denote comments and line separators. */
139 const char comment_chars
[] = "";
140 const char line_comment_chars
[] = "#";
141 const char line_separator_chars
[] = ";";
143 /* Characters that can be used to separate the mantissa from the
144 exponent in floating point numbers. */
145 const char EXP_CHARS
[] = "eE";
147 /* Characters that mean this number is a floating point constant.
148 As in 0f12.456 or 0d1.2345e12. */
149 const char FLT_CHARS
[] = "fFdDxX";
151 typedef enum bfin_cpu_type
185 bfin_cpu_t bfin_cpu_type
= BFIN_CPU_UNKNOWN
;
186 /* -msi-revision support. There are three special values:
187 -1 -msi-revision=none.
188 0xffff -msi-revision=any. */
189 int bfin_si_revision
;
191 unsigned int bfin_anomaly_checks
= 0;
198 unsigned int anomaly_checks
;
201 struct bfin_cpu bfin_cpus
[] =
203 {"bf512", BFIN_CPU_BF512
, 0x0001, AC_05000074
},
204 {"bf512", BFIN_CPU_BF512
, 0x0000, AC_05000074
},
206 {"bf514", BFIN_CPU_BF514
, 0x0001, AC_05000074
},
207 {"bf514", BFIN_CPU_BF514
, 0x0000, AC_05000074
},
209 {"bf516", BFIN_CPU_BF516
, 0x0001, AC_05000074
},
210 {"bf516", BFIN_CPU_BF516
, 0x0000, AC_05000074
},
212 {"bf518", BFIN_CPU_BF518
, 0x0001, AC_05000074
},
213 {"bf518", BFIN_CPU_BF518
, 0x0000, AC_05000074
},
215 {"bf522", BFIN_CPU_BF522
, 0x0002, AC_05000074
},
216 {"bf522", BFIN_CPU_BF522
, 0x0001, AC_05000074
},
217 {"bf522", BFIN_CPU_BF522
, 0x0000, AC_05000074
},
219 {"bf523", BFIN_CPU_BF523
, 0x0002, AC_05000074
},
220 {"bf523", BFIN_CPU_BF523
, 0x0001, AC_05000074
},
221 {"bf523", BFIN_CPU_BF523
, 0x0000, AC_05000074
},
223 {"bf524", BFIN_CPU_BF524
, 0x0002, AC_05000074
},
224 {"bf524", BFIN_CPU_BF524
, 0x0001, AC_05000074
},
225 {"bf524", BFIN_CPU_BF524
, 0x0000, AC_05000074
},
227 {"bf525", BFIN_CPU_BF525
, 0x0002, AC_05000074
},
228 {"bf525", BFIN_CPU_BF525
, 0x0001, AC_05000074
},
229 {"bf525", BFIN_CPU_BF525
, 0x0000, AC_05000074
},
231 {"bf526", BFIN_CPU_BF526
, 0x0002, AC_05000074
},
232 {"bf526", BFIN_CPU_BF526
, 0x0001, AC_05000074
},
233 {"bf526", BFIN_CPU_BF526
, 0x0000, AC_05000074
},
235 {"bf527", BFIN_CPU_BF527
, 0x0002, AC_05000074
},
236 {"bf527", BFIN_CPU_BF527
, 0x0001, AC_05000074
},
237 {"bf527", BFIN_CPU_BF527
, 0x0000, AC_05000074
},
239 {"bf531", BFIN_CPU_BF531
, 0x0006, AC_05000074
},
240 {"bf531", BFIN_CPU_BF531
, 0x0005, AC_05000074
},
241 {"bf531", BFIN_CPU_BF531
, 0x0004, AC_05000074
},
242 {"bf531", BFIN_CPU_BF531
, 0x0003, AC_05000074
},
244 {"bf532", BFIN_CPU_BF532
, 0x0006, AC_05000074
},
245 {"bf532", BFIN_CPU_BF532
, 0x0005, AC_05000074
},
246 {"bf532", BFIN_CPU_BF532
, 0x0004, AC_05000074
},
247 {"bf532", BFIN_CPU_BF532
, 0x0003, AC_05000074
},
249 {"bf533", BFIN_CPU_BF533
, 0x0006, AC_05000074
},
250 {"bf533", BFIN_CPU_BF533
, 0x0005, AC_05000074
},
251 {"bf533", BFIN_CPU_BF533
, 0x0004, AC_05000074
},
252 {"bf533", BFIN_CPU_BF533
, 0x0003, AC_05000074
},
254 {"bf534", BFIN_CPU_BF534
, 0x0003, AC_05000074
},
255 {"bf534", BFIN_CPU_BF534
, 0x0002, AC_05000074
},
256 {"bf534", BFIN_CPU_BF534
, 0x0001, AC_05000074
},
258 {"bf536", BFIN_CPU_BF536
, 0x0003, AC_05000074
},
259 {"bf536", BFIN_CPU_BF536
, 0x0002, AC_05000074
},
260 {"bf536", BFIN_CPU_BF536
, 0x0001, AC_05000074
},
262 {"bf537", BFIN_CPU_BF537
, 0x0003, AC_05000074
},
263 {"bf537", BFIN_CPU_BF537
, 0x0002, AC_05000074
},
264 {"bf537", BFIN_CPU_BF537
, 0x0001, AC_05000074
},
266 {"bf538", BFIN_CPU_BF538
, 0x0005, AC_05000074
},
267 {"bf538", BFIN_CPU_BF538
, 0x0004, AC_05000074
},
268 {"bf538", BFIN_CPU_BF538
, 0x0003, AC_05000074
},
269 {"bf538", BFIN_CPU_BF538
, 0x0002, AC_05000074
},
271 {"bf539", BFIN_CPU_BF539
, 0x0005, AC_05000074
},
272 {"bf539", BFIN_CPU_BF539
, 0x0004, AC_05000074
},
273 {"bf539", BFIN_CPU_BF539
, 0x0003, AC_05000074
},
274 {"bf539", BFIN_CPU_BF539
, 0x0002, AC_05000074
},
276 {"bf542m", BFIN_CPU_BF542M
, 0x0003, AC_05000074
},
278 {"bf542", BFIN_CPU_BF542
, 0x0002, AC_05000074
},
279 {"bf542", BFIN_CPU_BF542
, 0x0001, AC_05000074
},
280 {"bf542", BFIN_CPU_BF542
, 0x0000, AC_05000074
},
282 {"bf544m", BFIN_CPU_BF544M
, 0x0003, AC_05000074
},
284 {"bf544", BFIN_CPU_BF544
, 0x0002, AC_05000074
},
285 {"bf544", BFIN_CPU_BF544
, 0x0001, AC_05000074
},
286 {"bf544", BFIN_CPU_BF544
, 0x0000, AC_05000074
},
288 {"bf547m", BFIN_CPU_BF547M
, 0x0003, AC_05000074
},
290 {"bf547", BFIN_CPU_BF547
, 0x0002, AC_05000074
},
291 {"bf547", BFIN_CPU_BF547
, 0x0001, AC_05000074
},
292 {"bf547", BFIN_CPU_BF547
, 0x0000, AC_05000074
},
294 {"bf548m", BFIN_CPU_BF548M
, 0x0003, AC_05000074
},
296 {"bf548", BFIN_CPU_BF548
, 0x0002, AC_05000074
},
297 {"bf548", BFIN_CPU_BF548
, 0x0001, AC_05000074
},
298 {"bf548", BFIN_CPU_BF548
, 0x0000, AC_05000074
},
300 {"bf549m", BFIN_CPU_BF549M
, 0x0003, AC_05000074
},
302 {"bf549", BFIN_CPU_BF549
, 0x0002, AC_05000074
},
303 {"bf549", BFIN_CPU_BF549
, 0x0001, AC_05000074
},
304 {"bf549", BFIN_CPU_BF549
, 0x0000, AC_05000074
},
306 {"bf561", BFIN_CPU_BF561
, 0x0005, AC_05000074
},
307 {"bf561", BFIN_CPU_BF561
, 0x0003, AC_05000074
},
308 {"bf561", BFIN_CPU_BF561
, 0x0002, AC_05000074
},
313 /* Define bfin-specific command-line options (there are none). */
314 const char *md_shortopts
= "";
316 #define OPTION_FDPIC (OPTION_MD_BASE)
317 #define OPTION_NOPIC (OPTION_MD_BASE + 1)
318 #define OPTION_MCPU (OPTION_MD_BASE + 2)
320 struct option md_longopts
[] =
322 { "mcpu", required_argument
, NULL
, OPTION_MCPU
},
323 { "mfdpic", no_argument
, NULL
, OPTION_FDPIC
},
324 { "mnopic", no_argument
, NULL
, OPTION_NOPIC
},
325 { "mno-fdpic", no_argument
, NULL
, OPTION_NOPIC
},
326 { NULL
, no_argument
, NULL
, 0 },
329 size_t md_longopts_size
= sizeof (md_longopts
);
333 md_parse_option (int c ATTRIBUTE_UNUSED
, char *arg ATTRIBUTE_UNUSED
)
346 while ((p
= bfin_cpus
[i
].name
) != NULL
)
348 if (strncmp (arg
, p
, strlen (p
)) == 0)
355 error ("-mcpu=%s is not valid", arg
);
359 bfin_cpu_type
= bfin_cpus
[i
].type
;
361 q
= arg
+ strlen (p
);
365 bfin_si_revision
= bfin_cpus
[i
].si_revision
;
366 bfin_anomaly_checks
|= bfin_cpus
[i
].anomaly_checks
;
368 else if (strcmp (q
, "-none") == 0)
369 bfin_si_revision
= -1;
370 else if (strcmp (q
, "-any") == 0)
372 bfin_si_revision
= 0xffff;
373 while (bfin_cpus
[i
].type
== bfin_cpu_type
)
375 bfin_anomaly_checks
|= bfin_cpus
[i
].anomaly_checks
;
381 unsigned int si_major
, si_minor
;
384 rev_len
= strlen (q
);
386 if (sscanf (q
, "-%u.%u%n", &si_major
, &si_minor
, &n
) != 2
388 || si_major
> 0xff || si_minor
> 0xff)
390 invalid_silicon_revision
:
391 error ("-mcpu=%s has invalid silicon revision", arg
);
395 bfin_si_revision
= (si_major
<< 8) | si_minor
;
397 while (bfin_cpus
[i
].type
== bfin_cpu_type
398 && bfin_cpus
[i
].si_revision
!= bfin_si_revision
)
401 if (bfin_cpus
[i
].type
!= bfin_cpu_type
)
402 goto invalid_silicon_revision
;
404 bfin_anomaly_checks
|= bfin_cpus
[i
].anomaly_checks
;
411 bfin_flags
|= EF_BFIN_FDPIC
;
412 bfin_pic_flag
= "-mfdpic";
416 bfin_flags
&= ~(EF_BFIN_FDPIC
);
425 md_show_usage (FILE * stream ATTRIBUTE_UNUSED
)
427 fprintf (stream
, _(" BFIN specific command line options:\n"));
430 /* Perform machine-specific initializations. */
434 /* Set the ELF flags if desired. */
436 bfd_set_private_flags (stdoutput
, bfin_flags
);
438 /* Set the default machine type. */
439 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_bfin
, 0))
440 as_warn (_("Could not set architecture and machine."));
442 /* Ensure that lines can begin with '(', for multiple
443 register stack pops. */
444 lex_type
['('] = LEX_BEGIN_NAME
;
447 record_alignment (text_section
, 2);
448 record_alignment (data_section
, 2);
449 record_alignment (bss_section
, 2);
453 obstack_init (&mempool
);
456 extern int debug_codeselection
;
457 debug_codeselection
= 1;
463 /* Perform the main parsing, and assembly of the input here. Also,
464 call the required routines for alignment and fixups here.
465 This is called for every line that contains real assembly code. */
468 md_assemble (char *line
)
471 extern char *current_inputline
;
473 struct bfin_insn
*tmp_insn
;
475 static size_t buffer_len
= 0;
479 if (len
+ 2 > buffer_len
)
482 free (current_inputline
);
483 buffer_len
= len
+ 40;
484 current_inputline
= xmalloc (buffer_len
);
486 memcpy (current_inputline
, line
, len
);
487 current_inputline
[len
] = ';';
488 current_inputline
[len
+ 1] = '\0';
490 state
= parse (current_inputline
);
491 if (state
== NO_INSN_GENERATED
)
494 for (insn_size
= 0, tmp_insn
= insn
; tmp_insn
; tmp_insn
= tmp_insn
->next
)
495 if (!tmp_insn
->reloc
|| !tmp_insn
->exp
->symbol
)
499 toP
= frag_more (insn_size
);
501 last_insn_size
= insn_size
;
508 if (insn
->reloc
&& insn
->exp
->symbol
)
510 char *prev_toP
= toP
- 2;
513 case BFD_RELOC_BFIN_24_PCREL_JUMP_L
:
514 case BFD_RELOC_24_PCREL
:
515 case BFD_RELOC_BFIN_16_LOW
:
516 case BFD_RELOC_BFIN_16_HIGH
:
523 /* Following if condition checks for the arithmetic relocations.
524 If the case then it doesn't required to generate the code.
525 It has been assumed that, their ID will be contiguous. */
526 if ((BFD_ARELOC_BFIN_PUSH
<= insn
->reloc
527 && BFD_ARELOC_BFIN_COMP
>= insn
->reloc
)
528 || insn
->reloc
== BFD_RELOC_BFIN_16_IMM
)
532 if (insn
->reloc
== BFD_ARELOC_BFIN_CONST
533 || insn
->reloc
== BFD_ARELOC_BFIN_PUSH
)
537 (prev_toP
- frag_now
->fr_literal
),
538 size
, insn
->exp
->symbol
, insn
->exp
->value
,
539 insn
->pcrel
, insn
->reloc
);
543 md_number_to_chars (toP
, insn
->value
, 2);
549 printf (" %02x%02x", ((unsigned char *) &insn
->value
)[0],
550 ((unsigned char *) &insn
->value
)[1]);
556 dwarf2_emit_insn (insn_size
);
559 while (*line
++ != '\0')
561 bump_line_counters ();
564 /* Parse one line of instructions, and generate opcode for it.
565 To parse the line, YACC and LEX are used, because the instruction set
566 syntax doesn't confirm to the AT&T assembly syntax.
567 To call a YACC & LEX generated parser, we must provide the input via
568 a FILE stream, otherwise stdin is used by default. Below the input
569 to the function will be put into a temporary file, then the generated
570 parser uses the temporary file for parsing. */
576 YY_BUFFER_STATE buffstate
;
578 buffstate
= yy_scan_string (line
);
580 /* our lex requires setting the start state to keyword
581 every line as the first word may be a keyword.
582 Fixes a bug where we could not have keywords as labels. */
585 /* Call yyparse here. */
587 if (state
== SEMANTIC_ERROR
)
589 as_bad (_("Parse failed."));
593 yy_delete_buffer (buffstate
);
597 /* We need to handle various expressions properly.
598 Such as, [SP--] = 34, concerned by md_assemble(). */
601 md_operand (expressionS
* expressionP
)
603 if (*input_line_pointer
== '[')
605 as_tsktsk ("We found a '['!");
606 input_line_pointer
++;
607 expression (expressionP
);
611 /* Handle undefined symbols. */
613 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
615 return (symbolS
*) 0;
619 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
620 segT segment ATTRIBUTE_UNUSED
)
625 /* Convert from target byte order to host byte order. */
628 md_chars_to_number (char *val
, int n
)
632 for (retval
= 0; n
--;)
641 md_apply_fix (fixS
*fixP
, valueT
*valueP
, segT seg ATTRIBUTE_UNUSED
)
643 char *where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
645 long value
= *valueP
;
648 switch (fixP
->fx_r_type
)
650 case BFD_RELOC_BFIN_GOT
:
651 case BFD_RELOC_BFIN_GOT17M4
:
652 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4
:
653 fixP
->fx_no_overflow
= 1;
654 newval
= md_chars_to_number (where
, 2);
655 newval
|= 0x0 & 0x7f;
656 md_number_to_chars (where
, newval
, 2);
659 case BFD_RELOC_BFIN_10_PCREL
:
662 if (value
< -1024 || value
> 1022)
663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
664 _("pcrel too far BFD_RELOC_BFIN_10"));
666 /* 11 bit offset even numbered, so we remove right bit. */
668 newval
= md_chars_to_number (where
, 2);
669 newval
|= value
& 0x03ff;
670 md_number_to_chars (where
, newval
, 2);
673 case BFD_RELOC_BFIN_12_PCREL_JUMP
:
674 case BFD_RELOC_BFIN_12_PCREL_JUMP_S
:
675 case BFD_RELOC_12_PCREL
:
679 if (value
< -4096 || value
> 4094)
680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_12"));
681 /* 13 bit offset even numbered, so we remove right bit. */
683 newval
= md_chars_to_number (where
, 2);
684 newval
|= value
& 0xfff;
685 md_number_to_chars (where
, newval
, 2);
688 case BFD_RELOC_BFIN_16_LOW
:
689 case BFD_RELOC_BFIN_16_HIGH
:
690 fixP
->fx_done
= FALSE
;
693 case BFD_RELOC_BFIN_24_PCREL_JUMP_L
:
694 case BFD_RELOC_BFIN_24_PCREL_CALL_X
:
695 case BFD_RELOC_24_PCREL
:
699 if (value
< -16777216 || value
> 16777214)
700 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_24"));
702 /* 25 bit offset even numbered, so we remove right bit. */
706 md_number_to_chars (where
- 2, value
>> 16, 1);
707 md_number_to_chars (where
, value
, 1);
708 md_number_to_chars (where
+ 1, value
>> 8, 1);
711 case BFD_RELOC_BFIN_5_PCREL
: /* LSETUP (a, b) : "a" */
714 if (value
< 4 || value
> 30)
715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_5"));
717 newval
= md_chars_to_number (where
, 1);
718 newval
= (newval
& 0xf0) | (value
& 0xf);
719 md_number_to_chars (where
, newval
, 1);
722 case BFD_RELOC_BFIN_11_PCREL
: /* LSETUP (a, b) : "b" */
726 if (value
< 4 || value
> 2046)
727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far BFD_RELOC_BFIN_11_PCREL"));
728 /* 11 bit unsigned even, so we remove right bit. */
730 newval
= md_chars_to_number (where
, 2);
731 newval
|= value
& 0x03ff;
732 md_number_to_chars (where
, newval
, 2);
736 if (value
< -0x80 || value
>= 0x7f)
737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("rel too far BFD_RELOC_8"));
738 md_number_to_chars (where
, value
, 1);
741 case BFD_RELOC_BFIN_16_IMM
:
743 if (value
< -0x8000 || value
>= 0x7fff)
744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("rel too far BFD_RELOC_16"));
745 md_number_to_chars (where
, value
, 2);
749 md_number_to_chars (where
, value
, 4);
752 case BFD_RELOC_BFIN_PLTPC
:
753 md_number_to_chars (where
, value
, 2);
756 case BFD_RELOC_BFIN_FUNCDESC
:
757 case BFD_RELOC_VTABLE_INHERIT
:
758 case BFD_RELOC_VTABLE_ENTRY
:
759 fixP
->fx_done
= FALSE
;
763 if ((BFD_ARELOC_BFIN_PUSH
> fixP
->fx_r_type
) || (BFD_ARELOC_BFIN_COMP
< fixP
->fx_r_type
))
765 fprintf (stderr
, "Relocation %d not handled in gas." " Contact support.\n", fixP
->fx_r_type
);
771 fixP
->fx_done
= TRUE
;
775 /* Round up a section size to the appropriate boundary. */
777 md_section_align (segment
, size
)
781 int boundary
= bfd_get_section_alignment (stdoutput
, segment
);
782 return ((size
+ (1 << boundary
) - 1) & (-1 << boundary
));
787 md_atof (int type
, char * litP
, int * sizeP
)
789 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
793 /* If while processing a fixup, a reloc really needs to be created
794 then it is done here. */
797 tc_gen_reloc (seg
, fixp
)
798 asection
*seg ATTRIBUTE_UNUSED
;
803 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
804 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
805 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
806 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
808 reloc
->addend
= fixp
->fx_offset
;
809 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
811 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
813 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
814 /* xgettext:c-format. */
815 _("reloc %d not supported by object file format"),
816 (int) fixp
->fx_r_type
);
826 /* The location from which a PC relative jump should be calculated,
827 given a PC relative reloc. */
830 md_pcrel_from_section (fixP
, sec
)
834 if (fixP
->fx_addsy
!= (symbolS
*) NULL
835 && (!S_IS_DEFINED (fixP
->fx_addsy
)
836 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
838 /* The symbol is undefined (or is defined but not in this section).
839 Let the linker figure it out. */
842 return fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
845 /* Return true if the fix can be handled by GAS, false if it must
846 be passed through to the linker. */
849 bfin_fix_adjustable (fixS
*fixP
)
851 switch (fixP
->fx_r_type
)
853 /* Adjust_reloc_syms doesn't know about the GOT. */
854 case BFD_RELOC_BFIN_GOT
:
855 case BFD_RELOC_BFIN_PLTPC
:
856 /* We need the symbol name for the VTABLE entries. */
857 case BFD_RELOC_VTABLE_INHERIT
:
858 case BFD_RELOC_VTABLE_ENTRY
:
866 /* Special extra functions that help bfin-parse.y perform its job. */
868 struct obstack mempool
;
871 conscode (INSTR_T head
, INSTR_T tail
)
880 conctcode (INSTR_T head
, INSTR_T tail
)
882 INSTR_T temp
= (head
);
893 note_reloc (INSTR_T code
, Expr_Node
* symbol
, int reloc
, int pcrel
)
895 /* Assert that the symbol is not an operator. */
896 gas_assert (symbol
->type
== Expr_Node_Reloc
);
898 return note_reloc1 (code
, symbol
->value
.s_value
, reloc
, pcrel
);
903 note_reloc1 (INSTR_T code
, const char *symbol
, int reloc
, int pcrel
)
906 code
->exp
= mkexpr (0, symbol_find_or_make (symbol
));
912 note_reloc2 (INSTR_T code
, const char *symbol
, int reloc
, int value
, int pcrel
)
915 code
->exp
= mkexpr (value
, symbol_find_or_make (symbol
));
921 gencode (unsigned long x
)
923 INSTR_T cell
= obstack_alloc (&mempool
, sizeof (struct bfin_insn
));
924 memset (cell
, 0, sizeof (struct bfin_insn
));
936 return obstack_alloc (&mempool
, n
);
940 Expr_Node_Create (Expr_Node_Type type
,
941 Expr_Node_Value value
,
942 Expr_Node
*Left_Child
,
943 Expr_Node
*Right_Child
)
947 Expr_Node
*node
= (Expr_Node
*) allocate (sizeof (Expr_Node
));
950 node
->Left_Child
= Left_Child
;
951 node
->Right_Child
= Right_Child
;
955 static const char *con
= ".__constant";
956 static const char *op
= ".__operator";
957 static INSTR_T
Expr_Node_Gen_Reloc_R (Expr_Node
* head
);
958 INSTR_T
Expr_Node_Gen_Reloc (Expr_Node
*head
, int parent_reloc
);
961 Expr_Node_Gen_Reloc (Expr_Node
* head
, int parent_reloc
)
963 /* Top level reloction expression generator VDSP style.
964 If the relocation is just by itself, generate one item
965 else generate this convoluted expression. */
967 INSTR_T note
= NULL_CODE
;
968 INSTR_T note1
= NULL_CODE
;
969 int pcrel
= 1; /* Is the parent reloc pcrelative?
970 This calculation here and HOWTO should match. */
974 /* If it's 32 bit quantity then 16bit code needs to be added. */
977 if (head
->type
== Expr_Node_Constant
)
979 /* If note1 is not null code, we have to generate a right
980 aligned value for the constant. Otherwise the reloc is
981 a part of the basic command and the yacc file
983 value
= head
->value
.i_value
;
985 switch (parent_reloc
)
987 /* Some relocations will need to allocate extra words. */
988 case BFD_RELOC_BFIN_16_IMM
:
989 case BFD_RELOC_BFIN_16_LOW
:
990 case BFD_RELOC_BFIN_16_HIGH
:
991 note1
= conscode (gencode (value
), NULL_CODE
);
994 case BFD_RELOC_BFIN_PLTPC
:
995 note1
= conscode (gencode (value
), NULL_CODE
);
999 case BFD_RELOC_BFIN_GOT
:
1000 case BFD_RELOC_BFIN_GOT17M4
:
1001 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4
:
1002 note1
= conscode (gencode (value
), NULL_CODE
);
1005 case BFD_RELOC_24_PCREL
:
1006 case BFD_RELOC_BFIN_24_PCREL_JUMP_L
:
1007 case BFD_RELOC_BFIN_24_PCREL_CALL_X
:
1008 /* These offsets are even numbered pcrel. */
1009 note1
= conscode (gencode (value
>> 1), NULL_CODE
);
1015 if (head
->type
== Expr_Node_Constant
)
1017 else if (head
->type
== Expr_Node_Reloc
)
1019 note
= note_reloc1 (gencode (0), head
->value
.s_value
, parent_reloc
, pcrel
);
1020 if (note1
!= NULL_CODE
)
1021 note
= conscode (note1
, note
);
1023 else if (head
->type
== Expr_Node_Binop
1024 && (head
->value
.op_value
== Expr_Op_Type_Add
1025 || head
->value
.op_value
== Expr_Op_Type_Sub
)
1026 && head
->Left_Child
->type
== Expr_Node_Reloc
1027 && head
->Right_Child
->type
== Expr_Node_Constant
)
1029 int val
= head
->Right_Child
->value
.i_value
;
1030 if (head
->value
.op_value
== Expr_Op_Type_Sub
)
1032 note
= conscode (note_reloc2 (gencode (0), head
->Left_Child
->value
.s_value
,
1033 parent_reloc
, val
, 0),
1035 if (note1
!= NULL_CODE
)
1036 note
= conscode (note1
, note
);
1040 /* Call the recursive function. */
1041 note
= note_reloc1 (gencode (0), op
, parent_reloc
, pcrel
);
1042 if (note1
!= NULL_CODE
)
1043 note
= conscode (note1
, note
);
1044 note
= conctcode (Expr_Node_Gen_Reloc_R (head
), note
);
1050 Expr_Node_Gen_Reloc_R (Expr_Node
* head
)
1058 case Expr_Node_Constant
:
1059 note
= conscode (note_reloc2 (gencode (0), con
, BFD_ARELOC_BFIN_CONST
, head
->value
.i_value
, 0), NULL_CODE
);
1061 case Expr_Node_Reloc
:
1062 note
= conscode (note_reloc (gencode (0), head
, BFD_ARELOC_BFIN_PUSH
, 0), NULL_CODE
);
1064 case Expr_Node_Binop
:
1065 note1
= conctcode (Expr_Node_Gen_Reloc_R (head
->Left_Child
), Expr_Node_Gen_Reloc_R (head
->Right_Child
));
1066 switch (head
->value
.op_value
)
1068 case Expr_Op_Type_Add
:
1069 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_ADD
, 0), NULL_CODE
));
1071 case Expr_Op_Type_Sub
:
1072 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_SUB
, 0), NULL_CODE
));
1074 case Expr_Op_Type_Mult
:
1075 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_MULT
, 0), NULL_CODE
));
1077 case Expr_Op_Type_Div
:
1078 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_DIV
, 0), NULL_CODE
));
1080 case Expr_Op_Type_Mod
:
1081 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_MOD
, 0), NULL_CODE
));
1083 case Expr_Op_Type_Lshift
:
1084 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_LSHIFT
, 0), NULL_CODE
));
1086 case Expr_Op_Type_Rshift
:
1087 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_RSHIFT
, 0), NULL_CODE
));
1089 case Expr_Op_Type_BAND
:
1090 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_AND
, 0), NULL_CODE
));
1092 case Expr_Op_Type_BOR
:
1093 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_OR
, 0), NULL_CODE
));
1095 case Expr_Op_Type_BXOR
:
1096 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_XOR
, 0), NULL_CODE
));
1098 case Expr_Op_Type_LAND
:
1099 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_LAND
, 0), NULL_CODE
));
1101 case Expr_Op_Type_LOR
:
1102 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_LOR
, 0), NULL_CODE
));
1105 fprintf (stderr
, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__
, __LINE__
);
1110 case Expr_Node_Unop
:
1111 note1
= conscode (Expr_Node_Gen_Reloc_R (head
->Left_Child
), NULL_CODE
);
1112 switch (head
->value
.op_value
)
1114 case Expr_Op_Type_NEG
:
1115 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_NEG
, 0), NULL_CODE
));
1117 case Expr_Op_Type_COMP
:
1118 note
= conctcode (note1
, conscode (note_reloc1 (gencode (0), op
, BFD_ARELOC_BFIN_COMP
, 0), NULL_CODE
));
1121 fprintf (stderr
, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__
, __LINE__
);
1125 fprintf (stderr
, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__
, __LINE__
);
1130 /* Blackfin opcode generation. */
1132 /* These functions are called by the generated parser
1133 (from bfin-parse.y), the register type classification
1134 happens in bfin-lex.l. */
1136 #include "bfin-aux.h"
1137 #include "opcode/bfin.h"
1139 #define INIT(t) t c_code = init_##t
1140 #define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
1141 #define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
1143 #define HI(x) ((x >> 16) & 0xffff)
1144 #define LO(x) ((x ) & 0xffff)
1146 #define GROUP(x) ((x->regno & CLASS_MASK) >> 4)
1148 #define GEN_OPCODE32() \
1149 conscode (gencode (HI (c_code.opcode)), \
1150 conscode (gencode (LO (c_code.opcode)), NULL_CODE))
1152 #define GEN_OPCODE16() \
1153 conscode (gencode (c_code.opcode), NULL_CODE)
1156 /* 32 BIT INSTRUCTIONS. */
1159 /* DSP32 instruction generation. */
1162 bfin_gen_dsp32mac (int op1
, int MM
, int mmod
, int w1
, int P
,
1163 int h01
, int h11
, int h00
, int h10
, int op0
,
1164 REG_T dst
, REG_T src0
, REG_T src1
, int w0
)
1180 /* If we have full reg assignments, mask out LSB to encode
1181 single or simultaneous even/odd register moves. */
1191 return GEN_OPCODE32 ();
1195 bfin_gen_dsp32mult (int op1
, int MM
, int mmod
, int w1
, int P
,
1196 int h01
, int h11
, int h00
, int h10
, int op0
,
1197 REG_T dst
, REG_T src0
, REG_T src1
, int w0
)
1222 return GEN_OPCODE32 ();
1226 bfin_gen_dsp32alu (int HL
, int aopcde
, int aop
, int s
, int x
,
1227 REG_T dst0
, REG_T dst1
, REG_T src0
, REG_T src1
)
1241 return GEN_OPCODE32 ();
1245 bfin_gen_dsp32shift (int sopcde
, REG_T dst0
, REG_T src0
,
1246 REG_T src1
, int sop
, int HLs
)
1258 return GEN_OPCODE32 ();
1262 bfin_gen_dsp32shiftimm (int sopcde
, REG_T dst0
, int immag
,
1263 REG_T src1
, int sop
, int HLs
)
1265 INIT (DSP32ShiftImm
);
1275 return GEN_OPCODE32 ();
1281 bfin_gen_loopsetup (Expr_Node
* psoffset
, REG_T c
, int rop
,
1282 Expr_Node
* peoffset
, REG_T reg
)
1284 int soffset
, eoffset
;
1287 soffset
= (EXPR_VALUE (psoffset
) >> 1);
1289 eoffset
= (EXPR_VALUE (peoffset
) >> 1);
1296 conscode (gencode (HI (c_code
.opcode
)),
1297 conctcode (Expr_Node_Gen_Reloc (psoffset
, BFD_RELOC_BFIN_5_PCREL
),
1298 conctcode (gencode (LO (c_code
.opcode
)), Expr_Node_Gen_Reloc (peoffset
, BFD_RELOC_BFIN_11_PCREL
))));
1305 bfin_gen_calla (Expr_Node
* addr
, int S
)
1313 case 0 : reloc
= BFD_RELOC_BFIN_24_PCREL_JUMP_L
; break;
1314 case 1 : reloc
= BFD_RELOC_24_PCREL
; break;
1315 case 2 : reloc
= BFD_RELOC_BFIN_PLTPC
; break;
1321 val
= EXPR_VALUE (addr
) >> 1;
1322 high_val
= val
>> 16;
1324 return conscode (gencode (HI (c_code
.opcode
) | (high_val
& 0xff)),
1325 Expr_Node_Gen_Reloc (addr
, reloc
));
1329 bfin_gen_linkage (int R
, int framesize
)
1336 return GEN_OPCODE32 ();
1340 /* Load and Store. */
1343 bfin_gen_ldimmhalf (REG_T reg
, int H
, int S
, int Z
, Expr_Node
* phword
, int reloc
)
1346 unsigned val
= EXPR_VALUE (phword
);
1354 grp
= (GROUP (reg
));
1358 return conscode (gencode (HI (c_code
.opcode
)), Expr_Node_Gen_Reloc (phword
, BFD_RELOC_BFIN_16_IMM
));
1360 else if (reloc
== 1)
1362 return conscode (gencode (HI (c_code
.opcode
)), Expr_Node_Gen_Reloc (phword
, IS_H (*reg
) ? BFD_RELOC_BFIN_16_HIGH
: BFD_RELOC_BFIN_16_LOW
));
1369 return GEN_OPCODE32 ();
1373 bfin_gen_ldstidxi (REG_T ptr
, REG_T reg
, int W
, int sz
, int Z
, Expr_Node
* poffset
)
1377 if (!IS_PREG (*ptr
) || (!IS_DREG (*reg
) && !Z
))
1379 fprintf (stderr
, "Warning: possible mixup of Preg/Dreg\n");
1390 if (poffset
->type
!= Expr_Node_Constant
)
1392 /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
1393 /* distinguish between R0 = [P5 + symbol@GOT] and
1394 P5 = [P5 + _current_shared_library_p5_offset_]
1396 if (poffset
->type
== Expr_Node_Reloc
1397 && !strcmp (poffset
->value
.s_value
,
1398 "_current_shared_library_p5_offset_"))
1400 return conscode (gencode (HI (c_code
.opcode
)),
1401 Expr_Node_Gen_Reloc(poffset
, BFD_RELOC_16
));
1403 else if (poffset
->type
!= Expr_Node_GOT_Reloc
)
1406 return conscode (gencode (HI (c_code
.opcode
)),
1407 Expr_Node_Gen_Reloc(poffset
->Left_Child
,
1408 poffset
->value
.i_value
));
1414 { /* load/store access size */
1415 case 0: /* 32 bit */
1416 value
= EXPR_VALUE (poffset
) >> 2;
1418 case 1: /* 16 bit */
1419 value
= EXPR_VALUE (poffset
) >> 1;
1422 value
= EXPR_VALUE (poffset
);
1428 offset
= (value
& 0xffff);
1430 return GEN_OPCODE32 ();
1436 bfin_gen_ldst (REG_T ptr
, REG_T reg
, int aop
, int sz
, int Z
, int W
)
1440 if (!IS_PREG (*ptr
) || (!IS_DREG (*reg
) && !Z
))
1442 fprintf (stderr
, "Warning: possible mixup of Preg/Dreg\n");
1453 return GEN_OPCODE16 ();
1457 bfin_gen_ldstii (REG_T ptr
, REG_T reg
, Expr_Node
* poffset
, int W
, int op
)
1464 if (!IS_PREG (*ptr
))
1466 fprintf (stderr
, "Warning: possible mixup of Preg/Dreg\n");
1474 value
= EXPR_VALUE (poffset
) >> 1;
1478 value
= EXPR_VALUE (poffset
) >> 2;
1490 return GEN_OPCODE16 ();
1494 bfin_gen_ldstiifp (REG_T sreg
, Expr_Node
* poffset
, int W
)
1496 /* Set bit 4 if it's a Preg. */
1497 int reg
= (sreg
->regno
& CODE_MASK
) | (IS_PREG (*sreg
) ? 0x8 : 0x0);
1498 int offset
= ((~(EXPR_VALUE (poffset
) >> 2)) & 0x1f) + 1;
1504 return GEN_OPCODE16 ();
1508 bfin_gen_ldstpmod (REG_T ptr
, REG_T reg
, int aop
, int W
, REG_T idx
)
1518 return GEN_OPCODE16 ();
1522 bfin_gen_dspldst (REG_T i
, REG_T reg
, int aop
, int W
, int m
)
1532 return GEN_OPCODE16 ();
1536 bfin_gen_logi2op (int opc
, int src
, int dst
)
1544 return GEN_OPCODE16 ();
1548 bfin_gen_brcc (int T
, int B
, Expr_Node
* poffset
)
1555 offset
= ((EXPR_VALUE (poffset
) >> 1));
1557 return conscode (gencode (c_code
.opcode
), Expr_Node_Gen_Reloc (poffset
, BFD_RELOC_BFIN_10_PCREL
));
1561 bfin_gen_ujump (Expr_Node
* poffset
)
1566 offset
= ((EXPR_VALUE (poffset
) >> 1));
1569 return conscode (gencode (c_code
.opcode
),
1570 Expr_Node_Gen_Reloc (
1571 poffset
, BFD_RELOC_BFIN_12_PCREL_JUMP_S
));
1575 bfin_gen_alu2op (REG_T dst
, REG_T src
, int opc
)
1583 return GEN_OPCODE16 ();
1587 bfin_gen_compi2opd (REG_T dst
, int src
, int op
)
1595 return GEN_OPCODE16 ();
1599 bfin_gen_compi2opp (REG_T dst
, int src
, int op
)
1607 return GEN_OPCODE16 ();
1611 bfin_gen_dagmodik (REG_T i
, int op
)
1618 return GEN_OPCODE16 ();
1622 bfin_gen_dagmodim (REG_T i
, REG_T m
, int op
, int br
)
1631 return GEN_OPCODE16 ();
1635 bfin_gen_ptr2op (REG_T dst
, REG_T src
, int opc
)
1643 return GEN_OPCODE16 ();
1647 bfin_gen_comp3op (REG_T src0
, REG_T src1
, REG_T dst
, int opc
)
1656 return GEN_OPCODE16 ();
1660 bfin_gen_ccflag (REG_T x
, int y
, int opc
, int I
, int G
)
1670 return GEN_OPCODE16 ();
1674 bfin_gen_ccmv (REG_T src
, REG_T dst
, int T
)
1687 return GEN_OPCODE16 ();
1691 bfin_gen_cc2stat (int cbit
, int op
, int D
)
1699 return GEN_OPCODE16 ();
1703 bfin_gen_regmv (REG_T src
, REG_T dst
)
1716 return GEN_OPCODE16 ();
1720 bfin_gen_cc2dreg (int op
, REG_T reg
)
1727 return GEN_OPCODE16 ();
1731 bfin_gen_progctrl (int prgfunc
, int poprnd
)
1738 return GEN_OPCODE16 ();
1742 bfin_gen_cactrl (REG_T reg
, int a
, int op
)
1750 return GEN_OPCODE16 ();
1754 bfin_gen_pushpopmultiple (int dr
, int pr
, int d
, int p
, int W
)
1756 INIT (PushPopMultiple
);
1764 return GEN_OPCODE16 ();
1768 bfin_gen_pushpopreg (REG_T reg
, int W
)
1774 grp
= (GROUP (reg
));
1778 return GEN_OPCODE16 ();
1781 /* Pseudo Debugging Support. */
1784 bfin_gen_pseudodbg (int fn
, int reg
, int grp
)
1792 return GEN_OPCODE16 ();
1796 bfin_gen_pseudodbg_assert (int dbgop
, REG_T regtest
, int expected
)
1798 INIT (PseudoDbg_Assert
);
1804 return GEN_OPCODE32 ();
1807 /* Multiple instruction generation. */
1810 bfin_gen_multi_instr (INSTR_T dsp32
, INSTR_T dsp16_grp1
, INSTR_T dsp16_grp2
)
1814 /* If it's a 0, convert into MNOP. */
1818 SET_MULTI_INSTRUCTION_BIT (dsp32
);
1822 dsp32
= gencode (0xc803);
1823 walk
= gencode (0x1800);
1829 dsp16_grp1
= gencode (0x0000);
1834 dsp16_grp2
= gencode (0x0000);
1837 walk
->next
= dsp16_grp1
;
1838 dsp16_grp1
->next
= dsp16_grp2
;
1839 dsp16_grp2
->next
= NULL_CODE
;
1845 bfin_gen_loop (Expr_Node
*expr
, REG_T reg
, int rop
, REG_T preg
)
1847 const char *loopsym
;
1848 char *lbeginsym
, *lendsym
;
1849 Expr_Node_Value lbeginval
, lendval
;
1850 Expr_Node
*lbegin
, *lend
;
1852 loopsym
= expr
->value
.s_value
;
1853 lbeginsym
= (char *) xmalloc (strlen (loopsym
) + strlen ("__BEGIN") + 5);
1854 lendsym
= (char *) xmalloc (strlen (loopsym
) + strlen ("__END") + 5);
1859 strcat (lbeginsym
, "L$L$");
1860 strcat (lbeginsym
, loopsym
);
1861 strcat (lbeginsym
, "__BEGIN");
1863 strcat (lendsym
, "L$L$");
1864 strcat (lendsym
, loopsym
);
1865 strcat (lendsym
, "__END");
1867 lbeginval
.s_value
= lbeginsym
;
1868 lendval
.s_value
= lendsym
;
1870 lbegin
= Expr_Node_Create (Expr_Node_Reloc
, lbeginval
, NULL
, NULL
);
1871 lend
= Expr_Node_Create (Expr_Node_Reloc
, lendval
, NULL
, NULL
);
1873 symbol_remove (symbol_find (loopsym
), &symbol_rootP
, &symbol_lastP
);
1875 return bfin_gen_loopsetup(lbegin
, reg
, rop
, lend
, preg
);
1879 bfin_loop_beginend (Expr_Node
*expr
, int begin
)
1881 const char *loopsym
;
1883 symbolS
*line_label
;
1884 const char *suffix
= begin
? "__BEGIN" : "__END";
1886 loopsym
= expr
->value
.s_value
;
1887 label_name
= (char *) xmalloc (strlen (loopsym
) + strlen (suffix
) + 5);
1891 strcat (label_name
, "L$L$");
1892 strcat (label_name
, loopsym
);
1893 strcat (label_name
, suffix
);
1895 line_label
= colon (label_name
);
1897 /* LOOP_END follows the last instruction in the loop.
1898 Adjust label address. */
1900 ((struct local_symbol
*) line_label
)->lsy_value
-= last_insn_size
;
1904 bfin_eol_in_insn (char *line
)
1906 /* Allow a new-line to appear in the middle of a multi-issue instruction. */
1913 /* A semi-colon followed by a newline is always the end of a line. */
1914 if (line
[-1] == ';')
1917 if (line
[-1] == '|')
1920 /* If the || is on the next line, there might be leading whitespace. */
1922 while (*temp
== ' ' || *temp
== '\t') temp
++;
1931 bfin_start_label (char *s
, char *ptr
)
1935 if (*s
== '(' || *s
== '[')
1944 bfin_force_relocation (struct fix
*fixp
)
1946 if (fixp
->fx_r_type
==BFD_RELOC_BFIN_16_LOW
1947 || fixp
->fx_r_type
== BFD_RELOC_BFIN_16_HIGH
)
1950 return generic_force_reloc (fixp
);
1953 /* This is a stripped down version of the disassembler. The only thing it
1954 does is return a mask of registers modified by an instruction. Only
1955 instructions that can occur in a parallel-issue bundle are handled, and
1956 only the registers that can cause a conflict are recorded. */
1958 #define DREG_MASK(n) (0x101 << (n))
1959 #define DREGH_MASK(n) (0x100 << (n))
1960 #define DREGL_MASK(n) (0x001 << (n))
1961 #define IREG_MASK(n) (1 << ((n) + 16))
1964 decode_ProgCtrl_0 (int iw0
)
1972 decode_LDSTpmod_0 (int iw0
)
1975 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1976 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1977 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1978 int W
= ((iw0
>> LDSTpmod_W_bits
) & LDSTpmod_W_mask
);
1979 int aop
= ((iw0
>> LDSTpmod_aop_bits
) & LDSTpmod_aop_mask
);
1980 int idx
= ((iw0
>> LDSTpmod_idx_bits
) & LDSTpmod_idx_mask
);
1981 int ptr
= ((iw0
>> LDSTpmod_ptr_bits
) & LDSTpmod_ptr_mask
);
1982 int reg
= ((iw0
>> LDSTpmod_reg_bits
) & LDSTpmod_reg_mask
);
1984 if (aop
== 1 && W
== 0 && idx
== ptr
)
1985 return DREGL_MASK (reg
);
1986 else if (aop
== 2 && W
== 0 && idx
== ptr
)
1987 return DREGH_MASK (reg
);
1988 else if (aop
== 1 && W
== 1 && idx
== ptr
)
1990 else if (aop
== 2 && W
== 1 && idx
== ptr
)
1992 else if (aop
== 0 && W
== 0)
1993 return DREG_MASK (reg
);
1994 else if (aop
== 1 && W
== 0)
1995 return DREGL_MASK (reg
);
1996 else if (aop
== 2 && W
== 0)
1997 return DREGH_MASK (reg
);
1998 else if (aop
== 3 && W
== 0)
1999 return DREG_MASK (reg
);
2000 else if (aop
== 3 && W
== 1)
2001 return DREG_MASK (reg
);
2002 else if (aop
== 0 && W
== 1)
2004 else if (aop
== 1 && W
== 1)
2006 else if (aop
== 2 && W
== 1)
2015 decode_dagMODim_0 (int iw0
)
2018 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2019 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2020 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2021 int i
= ((iw0
>> DagMODim_i_bits
) & DagMODim_i_mask
);
2022 int op
= ((iw0
>> DagMODim_op_bits
) & DagMODim_op_mask
);
2024 if (op
== 0 || op
== 1)
2025 return IREG_MASK (i
);
2033 decode_dagMODik_0 (int iw0
)
2036 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2037 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2038 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2039 int i
= ((iw0
>> DagMODik_i_bits
) & DagMODik_i_mask
);
2040 return IREG_MASK (i
);
2045 decode_dspLDST_0 (int iw0
)
2048 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2049 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2050 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2051 int i
= ((iw0
>> DspLDST_i_bits
) & DspLDST_i_mask
);
2052 int m
= ((iw0
>> DspLDST_m_bits
) & DspLDST_m_mask
);
2053 int W
= ((iw0
>> DspLDST_W_bits
) & DspLDST_W_mask
);
2054 int aop
= ((iw0
>> DspLDST_aop_bits
) & DspLDST_aop_mask
);
2055 int reg
= ((iw0
>> DspLDST_reg_bits
) & DspLDST_reg_mask
);
2057 if (aop
== 0 && W
== 0 && m
== 0)
2058 return DREG_MASK (reg
) | IREG_MASK (i
);
2059 else if (aop
== 0 && W
== 0 && m
== 1)
2060 return DREGL_MASK (reg
) | IREG_MASK (i
);
2061 else if (aop
== 0 && W
== 0 && m
== 2)
2062 return DREGH_MASK (reg
) | IREG_MASK (i
);
2063 else if (aop
== 1 && W
== 0 && m
== 0)
2064 return DREG_MASK (reg
) | IREG_MASK (i
);
2065 else if (aop
== 1 && W
== 0 && m
== 1)
2066 return DREGL_MASK (reg
) | IREG_MASK (i
);
2067 else if (aop
== 1 && W
== 0 && m
== 2)
2068 return DREGH_MASK (reg
) | IREG_MASK (i
);
2069 else if (aop
== 2 && W
== 0 && m
== 0)
2070 return DREG_MASK (reg
);
2071 else if (aop
== 2 && W
== 0 && m
== 1)
2072 return DREGL_MASK (reg
);
2073 else if (aop
== 2 && W
== 0 && m
== 2)
2074 return DREGH_MASK (reg
);
2075 else if (aop
== 0 && W
== 1 && m
== 0)
2076 return IREG_MASK (i
);
2077 else if (aop
== 0 && W
== 1 && m
== 1)
2078 return IREG_MASK (i
);
2079 else if (aop
== 0 && W
== 1 && m
== 2)
2080 return IREG_MASK (i
);
2081 else if (aop
== 1 && W
== 1 && m
== 0)
2082 return IREG_MASK (i
);
2083 else if (aop
== 1 && W
== 1 && m
== 1)
2084 return IREG_MASK (i
);
2085 else if (aop
== 1 && W
== 1 && m
== 2)
2086 return IREG_MASK (i
);
2087 else if (aop
== 2 && W
== 1 && m
== 0)
2089 else if (aop
== 2 && W
== 1 && m
== 1)
2091 else if (aop
== 2 && W
== 1 && m
== 2)
2093 else if (aop
== 3 && W
== 0)
2094 return DREG_MASK (reg
) | IREG_MASK (i
);
2095 else if (aop
== 3 && W
== 1)
2096 return IREG_MASK (i
);
2103 decode_LDST_0 (int iw0
)
2106 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2107 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2108 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2109 int Z
= ((iw0
>> LDST_Z_bits
) & LDST_Z_mask
);
2110 int W
= ((iw0
>> LDST_W_bits
) & LDST_W_mask
);
2111 int sz
= ((iw0
>> LDST_sz_bits
) & LDST_sz_mask
);
2112 int aop
= ((iw0
>> LDST_aop_bits
) & LDST_aop_mask
);
2113 int reg
= ((iw0
>> LDST_reg_bits
) & LDST_reg_mask
);
2115 if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 0)
2116 return DREG_MASK (reg
);
2117 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 0)
2119 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 0)
2120 return DREG_MASK (reg
);
2121 else if (aop
== 0 && sz
== 1 && Z
== 1 && W
== 0)
2122 return DREG_MASK (reg
);
2123 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 0)
2124 return DREG_MASK (reg
);
2125 else if (aop
== 0 && sz
== 2 && Z
== 1 && W
== 0)
2126 return DREG_MASK (reg
);
2127 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 0)
2128 return DREG_MASK (reg
);
2129 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 0)
2131 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 0)
2132 return DREG_MASK (reg
);
2133 else if (aop
== 1 && sz
== 1 && Z
== 1 && W
== 0)
2134 return DREG_MASK (reg
);
2135 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 0)
2136 return DREG_MASK (reg
);
2137 else if (aop
== 1 && sz
== 2 && Z
== 1 && W
== 0)
2138 return DREG_MASK (reg
);
2139 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 0)
2140 return DREG_MASK (reg
);
2141 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 0)
2143 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 0)
2144 return DREG_MASK (reg
);
2145 else if (aop
== 2 && sz
== 1 && Z
== 1 && W
== 0)
2146 return DREG_MASK (reg
);
2147 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 0)
2148 return DREG_MASK (reg
);
2149 else if (aop
== 2 && sz
== 2 && Z
== 1 && W
== 0)
2150 return DREG_MASK (reg
);
2151 else if (aop
== 0 && sz
== 0 && Z
== 0 && W
== 1)
2153 else if (aop
== 0 && sz
== 0 && Z
== 1 && W
== 1)
2155 else if (aop
== 0 && sz
== 1 && Z
== 0 && W
== 1)
2157 else if (aop
== 0 && sz
== 2 && Z
== 0 && W
== 1)
2159 else if (aop
== 1 && sz
== 0 && Z
== 0 && W
== 1)
2161 else if (aop
== 1 && sz
== 0 && Z
== 1 && W
== 1)
2163 else if (aop
== 1 && sz
== 1 && Z
== 0 && W
== 1)
2165 else if (aop
== 1 && sz
== 2 && Z
== 0 && W
== 1)
2167 else if (aop
== 2 && sz
== 0 && Z
== 0 && W
== 1)
2169 else if (aop
== 2 && sz
== 0 && Z
== 1 && W
== 1)
2171 else if (aop
== 2 && sz
== 1 && Z
== 0 && W
== 1)
2173 else if (aop
== 2 && sz
== 2 && Z
== 0 && W
== 1)
2180 decode_LDSTiiFP_0 (int iw0
)
2183 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2184 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2185 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2186 int reg
= ((iw0
>> LDSTiiFP_reg_bits
) & LDSTiiFP_reg_mask
);
2187 int W
= ((iw0
>> LDSTiiFP_W_bits
) & LDSTiiFP_W_mask
);
2190 return reg
< 8 ? DREG_MASK (reg
) : 0;
2196 decode_LDSTii_0 (int iw0
)
2199 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2200 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2201 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2202 int reg
= ((iw0
>> LDSTii_reg_bit
) & LDSTii_reg_mask
);
2203 int op
= ((iw0
>> LDSTii_op_bit
) & LDSTii_op_mask
);
2204 int W
= ((iw0
>> LDSTii_W_bit
) & LDSTii_W_mask
);
2206 if (W
== 0 && op
!= 3)
2207 return DREG_MASK (reg
);
2208 else if (W
== 0 && op
== 3)
2210 else if (W
== 1 && op
== 0)
2212 else if (W
== 1 && op
== 1)
2214 else if (W
== 1 && op
== 3)
2221 decode_dsp32mac_0 (int iw0
, int iw1
)
2225 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2226 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2227 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2228 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2229 int op1
= ((iw0
>> (DSP32Mac_op1_bits
- 16)) & DSP32Mac_op1_mask
);
2230 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
2231 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
2232 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
2233 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
2234 int MM
= ((iw1
>> DSP32Mac_MM_bits
) & DSP32Mac_MM_mask
);
2235 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
2236 int op0
= ((iw1
>> DSP32Mac_op0_bits
) & DSP32Mac_op0_mask
);
2238 if (w0
== 0 && w1
== 0 && op1
== 3 && op0
== 3)
2244 if ((w1
|| w0
) && mmod
== M_W32
)
2247 if (((1 << mmod
) & (P
? 0x131b : 0x1b5f)) == 0)
2250 if (w1
== 1 || op1
!= 3)
2255 return DREG_MASK (dst
+ 1);
2257 return DREGH_MASK (dst
);
2261 if (w0
== 1 || op0
!= 3)
2266 return DREG_MASK (dst
);
2268 return DREGL_MASK (dst
);
2276 decode_dsp32mult_0 (int iw0
, int iw1
)
2279 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2280 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2281 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2282 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2283 int w1
= ((iw0
>> (DSP32Mac_w1_bits
- 16)) & DSP32Mac_w1_mask
);
2284 int P
= ((iw0
>> (DSP32Mac_p_bits
- 16)) & DSP32Mac_p_mask
);
2285 int mmod
= ((iw0
>> (DSP32Mac_mmod_bits
- 16)) & DSP32Mac_mmod_mask
);
2286 int w0
= ((iw1
>> DSP32Mac_w0_bits
) & DSP32Mac_w0_mask
);
2287 int dst
= ((iw1
>> DSP32Mac_dst_bits
) & DSP32Mac_dst_mask
);
2290 if (w1
== 0 && w0
== 0)
2293 if (((1 << mmod
) & (P
? 0x313 : 0x1b57)) == 0)
2299 return DREG_MASK (dst
| 1);
2301 return DREGH_MASK (dst
);
2307 return DREG_MASK (dst
);
2309 return DREGL_MASK (dst
);
2316 decode_dsp32alu_0 (int iw0
, int iw1
)
2319 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2320 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
2321 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2322 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2323 int s
= ((iw1
>> DSP32Alu_s_bits
) & DSP32Alu_s_mask
);
2324 int x
= ((iw1
>> DSP32Alu_x_bits
) & DSP32Alu_x_mask
);
2325 int aop
= ((iw1
>> DSP32Alu_aop_bits
) & DSP32Alu_aop_mask
);
2326 int dst0
= ((iw1
>> DSP32Alu_dst0_bits
) & DSP32Alu_dst0_mask
);
2327 int dst1
= ((iw1
>> DSP32Alu_dst1_bits
) & DSP32Alu_dst1_mask
);
2328 int HL
= ((iw0
>> (DSP32Alu_HL_bits
- 16)) & DSP32Alu_HL_mask
);
2329 int aopcde
= ((iw0
>> (DSP32Alu_aopcde_bits
- 16)) & DSP32Alu_aopcde_mask
);
2331 if (aop
== 0 && aopcde
== 9 && s
== 0)
2333 else if (aop
== 2 && aopcde
== 9 && HL
== 0 && s
== 0)
2335 else if (aop
>= x
* 2 && aopcde
== 5)
2336 return HL
? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2337 else if (HL
== 0 && aopcde
== 2)
2338 return DREGL_MASK (dst0
);
2339 else if (HL
== 1 && aopcde
== 2)
2340 return DREGH_MASK (dst0
);
2341 else if (HL
== 0 && aopcde
== 3)
2342 return DREGL_MASK (dst0
);
2343 else if (HL
== 1 && aopcde
== 3)
2344 return DREGH_MASK (dst0
);
2346 else if (aop
== 0 && aopcde
== 9 && s
== 1)
2348 else if (aop
== 1 && aopcde
== 9 && s
== 0)
2350 else if (aop
== 2 && aopcde
== 9 && s
== 1)
2352 else if (aop
== 3 && aopcde
== 9 && s
== 0)
2354 else if (aopcde
== 8)
2356 else if (aop
== 0 && aopcde
== 11)
2357 return DREG_MASK (dst0
);
2358 else if (aop
== 1 && aopcde
== 11)
2359 return HL
? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2360 else if (aopcde
== 11)
2362 else if (aopcde
== 22)
2363 return DREG_MASK (dst0
);
2365 else if ((aop
== 0 || aop
== 1) && aopcde
== 14)
2367 else if (aop
== 3 && HL
== 0 && aopcde
== 14)
2370 else if (aop
== 3 && HL
== 0 && aopcde
== 15)
2371 return DREG_MASK (dst0
);
2373 else if (aop
== 1 && aopcde
== 16)
2376 else if (aop
== 0 && aopcde
== 16)
2379 else if (aop
== 3 && HL
== 0 && aopcde
== 16)
2382 else if (aop
== 3 && HL
== 0 && aopcde
== 7)
2383 return DREG_MASK (dst0
);
2384 else if ((aop
== 0 || aop
== 1 || aop
== 2) && aopcde
== 7)
2385 return DREG_MASK (dst0
);
2387 else if (aop
== 0 && aopcde
== 12)
2388 return DREG_MASK (dst0
);
2389 else if (aop
== 1 && aopcde
== 12)
2390 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2391 else if (aop
== 3 && aopcde
== 12)
2392 return HL
? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2394 else if (aopcde
== 0)
2395 return DREG_MASK (dst0
);
2396 else if (aopcde
== 1)
2397 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2399 else if (aop
== 0 && aopcde
== 10)
2400 return DREGL_MASK (dst0
);
2401 else if (aop
== 1 && aopcde
== 10)
2402 return DREGL_MASK (dst0
);
2404 else if ((aop
== 1 || aop
== 0) && aopcde
== 4)
2405 return DREG_MASK (dst0
);
2406 else if (aop
== 2 && aopcde
== 4)
2407 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2409 else if (aop
== 0 && aopcde
== 17)
2410 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2411 else if (aop
== 1 && aopcde
== 17)
2412 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2413 else if (aop
== 0 && aopcde
== 18)
2415 else if (aop
== 3 && aopcde
== 18)
2418 else if ((aop
== 0 || aop
== 1 || aop
== 2) && aopcde
== 6)
2419 return DREG_MASK (dst0
);
2421 else if ((aop
== 0 || aop
== 1) && aopcde
== 20)
2422 return DREG_MASK (dst0
);
2424 else if ((aop
== 0 || aop
== 1) && aopcde
== 21)
2425 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2427 else if (aop
== 0 && aopcde
== 23 && HL
== 1)
2428 return DREG_MASK (dst0
);
2429 else if (aop
== 0 && aopcde
== 23 && HL
== 0)
2430 return DREG_MASK (dst0
);
2432 else if (aop
== 0 && aopcde
== 24)
2433 return DREG_MASK (dst0
);
2434 else if (aop
== 1 && aopcde
== 24)
2435 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2436 else if (aopcde
== 13)
2437 return DREG_MASK (dst0
) | DREG_MASK (dst1
);
2445 decode_dsp32shift_0 (int iw0
, int iw1
)
2448 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2449 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
2450 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
2451 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2452 int HLs
= ((iw1
>> DSP32Shift_HLs_bits
) & DSP32Shift_HLs_mask
);
2453 int sop
= ((iw1
>> DSP32Shift_sop_bits
) & DSP32Shift_sop_mask
);
2454 int src0
= ((iw1
>> DSP32Shift_src0_bits
) & DSP32Shift_src0_mask
);
2455 int src1
= ((iw1
>> DSP32Shift_src1_bits
) & DSP32Shift_src1_mask
);
2456 int dst0
= ((iw1
>> DSP32Shift_dst0_bits
) & DSP32Shift_dst0_mask
);
2457 int sopcde
= ((iw0
>> (DSP32Shift_sopcde_bits
- 16)) & DSP32Shift_sopcde_mask
);
2459 if (sop
== 0 && sopcde
== 0)
2460 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2461 else if (sop
== 1 && sopcde
== 0)
2462 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2463 else if (sop
== 2 && sopcde
== 0)
2464 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2465 else if (sop
== 0 && sopcde
== 3)
2467 else if (sop
== 1 && sopcde
== 3)
2469 else if (sop
== 2 && sopcde
== 3)
2471 else if (sop
== 3 && sopcde
== 3)
2472 return DREG_MASK (dst0
);
2473 else if (sop
== 0 && sopcde
== 1)
2474 return DREG_MASK (dst0
);
2475 else if (sop
== 1 && sopcde
== 1)
2476 return DREG_MASK (dst0
);
2477 else if (sop
== 2 && sopcde
== 1)
2478 return DREG_MASK (dst0
);
2479 else if (sopcde
== 2)
2480 return DREG_MASK (dst0
);
2481 else if (sopcde
== 4)
2482 return DREG_MASK (dst0
);
2483 else if (sop
== 0 && sopcde
== 5)
2484 return DREGL_MASK (dst0
);
2485 else if (sop
== 1 && sopcde
== 5)
2486 return DREGL_MASK (dst0
);
2487 else if (sop
== 2 && sopcde
== 5)
2488 return DREGL_MASK (dst0
);
2489 else if (sop
== 0 && sopcde
== 6)
2490 return DREGL_MASK (dst0
);
2491 else if (sop
== 1 && sopcde
== 6)
2492 return DREGL_MASK (dst0
);
2493 else if (sop
== 3 && sopcde
== 6)
2494 return DREGL_MASK (dst0
);
2495 else if (sop
== 0 && sopcde
== 7)
2496 return DREGL_MASK (dst0
);
2497 else if (sop
== 1 && sopcde
== 7)
2498 return DREGL_MASK (dst0
);
2499 else if (sop
== 2 && sopcde
== 7)
2500 return DREGL_MASK (dst0
);
2501 else if (sop
== 3 && sopcde
== 7)
2502 return DREGL_MASK (dst0
);
2503 else if (sop
== 0 && sopcde
== 8)
2504 return DREG_MASK (src0
) | DREG_MASK (src1
);
2507 OUTS (outf
, "BITMUX (");
2508 OUTS (outf
, dregs (src0
));
2510 OUTS (outf
, dregs (src1
));
2511 OUTS (outf
, ", A0) (ASR)");
2514 else if (sop
== 1 && sopcde
== 8)
2515 return DREG_MASK (src0
) | DREG_MASK (src1
);
2518 OUTS (outf
, "BITMUX (");
2519 OUTS (outf
, dregs (src0
));
2521 OUTS (outf
, dregs (src1
));
2522 OUTS (outf
, ", A0) (ASL)");
2525 else if (sopcde
== 9)
2526 return sop
< 2 ? DREGL_MASK (dst0
) : DREG_MASK (dst0
);
2527 else if (sopcde
== 10)
2528 return DREG_MASK (dst0
);
2529 else if (sop
== 0 && sopcde
== 11)
2530 return DREGL_MASK (dst0
);
2531 else if (sop
== 1 && sopcde
== 11)
2532 return DREGL_MASK (dst0
);
2533 else if (sop
== 0 && sopcde
== 12)
2535 else if (sop
== 1 && sopcde
== 12)
2536 return DREGL_MASK (dst0
);
2537 else if (sop
== 0 && sopcde
== 13)
2538 return DREG_MASK (dst0
);
2539 else if (sop
== 1 && sopcde
== 13)
2540 return DREG_MASK (dst0
);
2541 else if (sop
== 2 && sopcde
== 13)
2542 return DREG_MASK (dst0
);
2548 decode_dsp32shiftimm_0 (int iw0
, int iw1
)
2551 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2552 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
2553 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
2554 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2555 int sop
= ((iw1
>> DSP32ShiftImm_sop_bits
) & DSP32ShiftImm_sop_mask
);
2556 int bit8
= ((iw1
>> 8) & 0x1);
2557 int dst0
= ((iw1
>> DSP32ShiftImm_dst0_bits
) & DSP32ShiftImm_dst0_mask
);
2558 int sopcde
= ((iw0
>> (DSP32ShiftImm_sopcde_bits
- 16)) & DSP32ShiftImm_sopcde_mask
);
2559 int HLs
= ((iw1
>> DSP32ShiftImm_HLs_bits
) & DSP32ShiftImm_HLs_mask
);
2562 if (sop
== 0 && sopcde
== 0)
2563 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2564 else if (sop
== 1 && sopcde
== 0 && bit8
== 0)
2565 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2566 else if (sop
== 1 && sopcde
== 0 && bit8
== 1)
2567 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2568 else if (sop
== 2 && sopcde
== 0 && bit8
== 0)
2569 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2570 else if (sop
== 2 && sopcde
== 0 && bit8
== 1)
2571 return HLs
& 2 ? DREGH_MASK (dst0
) : DREGL_MASK (dst0
);
2572 else if (sop
== 2 && sopcde
== 3 && HLs
== 1)
2574 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 0)
2576 else if (sop
== 0 && sopcde
== 3 && HLs
== 0 && bit8
== 1)
2578 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 0)
2580 else if (sop
== 0 && sopcde
== 3 && HLs
== 1 && bit8
== 1)
2582 else if (sop
== 1 && sopcde
== 3 && HLs
== 0)
2584 else if (sop
== 1 && sopcde
== 3 && HLs
== 1)
2586 else if (sop
== 2 && sopcde
== 3 && HLs
== 0)
2588 else if (sop
== 1 && sopcde
== 1 && bit8
== 0)
2589 return DREG_MASK (dst0
);
2590 else if (sop
== 1 && sopcde
== 1 && bit8
== 1)
2591 return DREG_MASK (dst0
);
2592 else if (sop
== 2 && sopcde
== 1 && bit8
== 1)
2593 return DREG_MASK (dst0
);
2594 else if (sop
== 2 && sopcde
== 1 && bit8
== 0)
2595 return DREG_MASK (dst0
);
2596 else if (sop
== 0 && sopcde
== 1)
2597 return DREG_MASK (dst0
);
2598 else if (sop
== 1 && sopcde
== 2)
2599 return DREG_MASK (dst0
);
2600 else if (sop
== 2 && sopcde
== 2 && bit8
== 1)
2601 return DREG_MASK (dst0
);
2602 else if (sop
== 2 && sopcde
== 2 && bit8
== 0)
2603 return DREG_MASK (dst0
);
2604 else if (sop
== 3 && sopcde
== 2)
2605 return DREG_MASK (dst0
);
2606 else if (sop
== 0 && sopcde
== 2)
2607 return DREG_MASK (dst0
);
2613 insn_regmask (int iw0
, int iw1
)
2615 if ((iw0
& 0xf7ff) == 0xc003 && iw1
== 0x1800)
2616 return 0; /* MNOP */
2617 else if ((iw0
& 0xff00) == 0x0000)
2618 return decode_ProgCtrl_0 (iw0
);
2619 else if ((iw0
& 0xffc0) == 0x0240)
2621 else if ((iw0
& 0xff80) == 0x0100)
2623 else if ((iw0
& 0xfe00) == 0x0400)
2625 else if ((iw0
& 0xfe00) == 0x0600)
2627 else if ((iw0
& 0xf800) == 0x0800)
2629 else if ((iw0
& 0xffe0) == 0x0200)
2631 else if ((iw0
& 0xff00) == 0x0300)
2633 else if ((iw0
& 0xf000) == 0x1000)
2635 else if ((iw0
& 0xf000) == 0x2000)
2637 else if ((iw0
& 0xf000) == 0x3000)
2639 else if ((iw0
& 0xfc00) == 0x4000)
2641 else if ((iw0
& 0xfe00) == 0x4400)
2643 else if ((iw0
& 0xf800) == 0x4800)
2645 else if ((iw0
& 0xf000) == 0x5000)
2647 else if ((iw0
& 0xf800) == 0x6000)
2649 else if ((iw0
& 0xf800) == 0x6800)
2651 else if ((iw0
& 0xf000) == 0x8000)
2652 return decode_LDSTpmod_0 (iw0
);
2653 else if ((iw0
& 0xff60) == 0x9e60)
2654 return decode_dagMODim_0 (iw0
);
2655 else if ((iw0
& 0xfff0) == 0x9f60)
2656 return decode_dagMODik_0 (iw0
);
2657 else if ((iw0
& 0xfc00) == 0x9c00)
2658 return decode_dspLDST_0 (iw0
);
2659 else if ((iw0
& 0xf000) == 0x9000)
2660 return decode_LDST_0 (iw0
);
2661 else if ((iw0
& 0xfc00) == 0xb800)
2662 return decode_LDSTiiFP_0 (iw0
);
2663 else if ((iw0
& 0xe000) == 0xA000)
2664 return decode_LDSTii_0 (iw0
);
2665 else if ((iw0
& 0xff80) == 0xe080 && (iw1
& 0x0C00) == 0x0000)
2667 else if ((iw0
& 0xff00) == 0xe100 && (iw1
& 0x0000) == 0x0000)
2669 else if ((iw0
& 0xfe00) == 0xe200 && (iw1
& 0x0000) == 0x0000)
2671 else if ((iw0
& 0xfc00) == 0xe400 && (iw1
& 0x0000) == 0x0000)
2673 else if ((iw0
& 0xfffe) == 0xe800 && (iw1
& 0x0000) == 0x0000)
2675 else if ((iw0
& 0xf600) == 0xc000 && (iw1
& 0x0000) == 0x0000)
2676 return decode_dsp32mac_0 (iw0
, iw1
);
2677 else if ((iw0
& 0xf600) == 0xc200 && (iw1
& 0x0000) == 0x0000)
2678 return decode_dsp32mult_0 (iw0
, iw1
);
2679 else if ((iw0
& 0xf7c0) == 0xc400 && (iw1
& 0x0000) == 0x0000)
2680 return decode_dsp32alu_0 (iw0
, iw1
);
2681 else if ((iw0
& 0xf780) == 0xc600 && (iw1
& 0x01c0) == 0x0000)
2682 return decode_dsp32shift_0 (iw0
, iw1
);
2683 else if ((iw0
& 0xf780) == 0xc680 && (iw1
& 0x0000) == 0x0000)
2684 return decode_dsp32shiftimm_0 (iw0
, iw1
);
2685 else if ((iw0
& 0xff00) == 0xf800)
2687 else if ((iw0
& 0xFFC0) == 0xf000 && (iw1
& 0x0000) == 0x0000)