1 /* tc-cr16.c -- Assembler code for the CR16 CPU core.
2 Copyright 2007 Free Software Foundation, Inc.
4 Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
26 #include "opcode/cr16.h"
30 /* Word is considered here as a 16-bit unsigned short int. */
33 /* Register is 2-byte size. */
36 /* Maximum size of a single instruction (in words). */
37 #define INSN_MAX_SIZE 3
39 /* Maximum bits which may be set in a `mask16' operand. */
40 #define MAX_REGS_IN_MASK16 8
42 /* Assign a number NUM, shifted by SHIFT bytes, into a location
43 pointed by index BYTE of array 'output_opcode'. */
44 #define CR16_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT)
49 OP_LEGAL
= 0, /* Legal operand. */
50 OP_OUT_OF_RANGE
, /* Operand not within permitted range. */
51 OP_NOT_EVEN
/* Operand is Odd number, should be even. */
55 /* Opcode mnemonics hash table. */
56 static struct hash_control
*cr16_inst_hash
;
57 /* CR16 registers hash table. */
58 static struct hash_control
*reg_hash
;
59 /* CR16 register pair hash table. */
60 static struct hash_control
*regp_hash
;
61 /* CR16 processor registers hash table. */
62 static struct hash_control
*preg_hash
;
63 /* CR16 processor registers 32 bit hash table. */
64 static struct hash_control
*pregp_hash
;
65 /* Current instruction we're assembling. */
66 const inst
*instruction
;
69 static int code_label
= 0;
71 /* Global variables. */
73 /* Array to hold an instruction encoding. */
74 long output_opcode
[2];
76 /* Nonzero means a relocatable symbol. */
79 /* A copy of the original instruction (used in error messages). */
80 char ins_parse
[MAX_INST_LEN
];
82 /* The current processed argument number. */
85 /* Generic assembler global variables which must be defined by all targets. */
87 /* Characters which always start a comment. */
88 const char comment_chars
[] = "#";
90 /* Characters which start a comment at the beginning of a line. */
91 const char line_comment_chars
[] = "#";
93 /* This array holds machine specific line separator characters. */
94 const char line_separator_chars
[] = ";";
96 /* Chars that can be used to separate mant from exp in floating point nums. */
97 const char EXP_CHARS
[] = "eE";
99 /* Chars that mean this number is a floating point constant as in 0f12.456 */
100 const char FLT_CHARS
[] = "f'";
102 /* Target-specific multicharacter options, not const-declared at usage. */
103 const char *md_shortopts
= "";
104 struct option md_longopts
[] =
106 {NULL
, no_argument
, NULL
, 0}
108 size_t md_longopts_size
= sizeof (md_longopts
);
116 #ifdef md_flush_pending_output
117 md_flush_pending_output ();
120 if (is_it_end_of_statement ())
122 demand_empty_rest_of_line ();
126 #ifdef TC_ADDRESS_BYTES
128 nbytes
= TC_ADDRESS_BYTES ();
132 md_cons_align (nbytes
);
138 unsigned int bits_available
= BITS_PER_CHAR
* nbytes
;
139 char *hold
= input_line_pointer
;
143 if (*input_line_pointer
== ':')
152 if (*input_line_pointer
!= ':')
154 input_line_pointer
= hold
;
157 if (exp
.X_op
== O_absent
)
159 as_warn (_("using a bit field width of zero"));
160 exp
.X_add_number
= 0;
161 exp
.X_op
= O_constant
;
164 if (exp
.X_op
!= O_constant
)
166 *input_line_pointer
= '\0';
167 as_bad (_("field width \"%s\" too complex for a bitfield"), hold
);
168 *input_line_pointer
= ':';
169 demand_empty_rest_of_line ();
173 if ((width
= exp
.X_add_number
) >
174 (unsigned int)(BITS_PER_CHAR
* nbytes
))
176 as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width
, nbytes
, (BITS_PER_CHAR
* nbytes
));
177 width
= BITS_PER_CHAR
* nbytes
;
181 if (width
> bits_available
)
183 /* FIXME-SOMEDAY: backing up and reparsing is wasteful. */
184 input_line_pointer
= hold
;
185 exp
.X_add_number
= value
;
190 hold
= ++input_line_pointer
;
193 if (exp
.X_op
!= O_constant
)
195 char cache
= *input_line_pointer
;
197 *input_line_pointer
= '\0';
198 as_bad (_("field value \"%s\" too complex for a bitfield"), hold
);
199 *input_line_pointer
= cache
;
200 demand_empty_rest_of_line ();
204 value
|= ((~(-1 << width
) & exp
.X_add_number
)
205 << ((BITS_PER_CHAR
* nbytes
) - bits_available
));
207 if ((bits_available
-= width
) == 0
208 || is_it_end_of_statement ()
209 || *input_line_pointer
!= ',')
212 hold
= ++input_line_pointer
;
216 exp
.X_add_number
= value
;
217 exp
.X_op
= O_constant
;
221 if ((*(input_line_pointer
) == '@') && (*(input_line_pointer
+1) == 'c'))
223 emit_expr (&exp
, (unsigned int) nbytes
);
225 if ((*(input_line_pointer
) == '@') && (*(input_line_pointer
+1) == 'c'))
227 input_line_pointer
+=3;
231 while ((*input_line_pointer
++ == ','));
233 /* Put terminator back into stream. */
234 input_line_pointer
--;
236 demand_empty_rest_of_line ();
240 /* This table describes all the machine specific pseudo-ops
241 the assembler has to support. The fields are:
242 *** Pseudo-op name without dot.
243 *** Function to call to execute this pseudo-op.
244 *** Integer arg to pass to the function. */
246 const pseudo_typeS md_pseudo_table
[] =
248 /* In CR16 machine, align is in bytes (not a ptwo boundary). */
249 {"align", s_align_bytes
, 0},
250 {"long", l_cons
, 4 },
254 /* CR16 relaxation table. */
255 const relax_typeS md_relax_table
[] =
258 {0xfa, -0x100, 2, 1}, /* 8 */
259 {0xfffe, -0x10000, 4, 2}, /* 16 */
260 {0xfffffe, -0x1000000, 6, 0}, /* 24 */
263 /* Return the bit size for a given operand. */
266 get_opbits (operand_type op
)
269 return cr16_optab
[op
].bit_size
;
274 /* Return the argument type of a given operand. */
277 get_optype (operand_type op
)
280 return cr16_optab
[op
].arg_type
;
285 /* Return the flags of a given operand. */
288 get_opflags (operand_type op
)
291 return cr16_optab
[op
].flags
;
296 /* Get the cc code. */
299 get_cc (char *cc_name
)
303 for (i
= 0; i
< cr16_num_cc
; i
++)
304 if (strcmp (cc_name
, cr16_b_cond_tab
[i
]) == 0)
310 /* Get the core processor register 'reg_name'. */
313 get_register (char *reg_name
)
315 const reg_entry
*reg
;
317 reg
= (const reg_entry
*) hash_find (reg_hash
, reg_name
);
320 return reg
->value
.reg_val
;
324 /* Get the core processor register-pair 'reg_name'. */
327 get_register_pair (char *reg_name
)
329 const reg_entry
*reg
;
330 char tmp_rp
[16]="\0";
332 /* Add '(' and ')' to the reg pair, if its not present. */
333 if (reg_name
[0] != '(')
336 strcat (tmp_rp
, reg_name
);
338 reg
= (const reg_entry
*) hash_find (regp_hash
, tmp_rp
);
341 reg
= (const reg_entry
*) hash_find (regp_hash
, reg_name
);
344 return reg
->value
.reg_val
;
349 /* Get the index register 'reg_name'. */
352 get_index_register (char *reg_name
)
354 const reg_entry
*reg
;
356 reg
= (const reg_entry
*) hash_find (reg_hash
, reg_name
);
359 && ((reg
->value
.reg_val
== 12) || (reg
->value
.reg_val
== 13)))
360 return reg
->value
.reg_val
;
364 /* Get the core processor index register-pair 'reg_name'. */
367 get_index_register_pair (char *reg_name
)
369 const reg_entry
*reg
;
371 reg
= (const reg_entry
*) hash_find (regp_hash
, reg_name
);
375 if ((reg
->value
.reg_val
!= 1) || (reg
->value
.reg_val
!= 7)
376 || (reg
->value
.reg_val
!= 9) || (reg
->value
.reg_val
> 10))
377 return reg
->value
.reg_val
;
379 as_bad (_("Unknown register pair - index relative mode: `%d'"), reg
->value
.reg_val
);
385 /* Get the processor register 'preg_name'. */
388 get_pregister (char *preg_name
)
390 const reg_entry
*preg
;
392 preg
= (const reg_entry
*) hash_find (preg_hash
, preg_name
);
395 return preg
->value
.preg_val
;
397 return nullpregister
;
400 /* Get the processor register 'preg_name 32 bit'. */
403 get_pregisterp (char *preg_name
)
405 const reg_entry
*preg
;
407 preg
= (const reg_entry
*) hash_find (pregp_hash
, preg_name
);
410 return preg
->value
.preg_val
;
412 return nullpregister
;
416 /* Round up a section size to the appropriate boundary. */
419 md_section_align (segT seg
, valueT val
)
421 /* Round .text section to a multiple of 2. */
422 if (seg
== text_section
)
423 return (val
+ 1) & ~1;
427 /* Parse an operand that is machine-specific (remove '*'). */
430 md_operand (expressionS
* exp
)
432 char c
= *input_line_pointer
;
437 input_line_pointer
++;
445 /* Reset global variables before parsing a new instruction. */
448 reset_vars (char *op
)
450 cur_arg_num
= relocatable
= 0;
451 memset (& output_opcode
, '\0', sizeof (output_opcode
));
453 /* Save a copy of the original OP (used in error messages). */
454 strncpy (ins_parse
, op
, sizeof ins_parse
- 1);
455 ins_parse
[sizeof ins_parse
- 1] = 0;
458 /* This macro decides whether a particular reloc is an entry in a
459 switch table. It is used when relaxing, because the linker needs
460 to know about all such entries so that it can adjust them if
463 #define SWITCH_TABLE(fix) \
464 ( (fix)->fx_addsy != NULL \
465 && (fix)->fx_subsy != NULL \
466 && S_GET_SEGMENT ((fix)->fx_addsy) == \
467 S_GET_SEGMENT ((fix)->fx_subsy) \
468 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \
469 && ( (fix)->fx_r_type == BFD_RELOC_CR16_NUM8 \
470 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16 \
471 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32 \
472 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a))
474 /* See whether we need to force a relocation into the output file.
475 This is used to force out switch and PC relative relocations when
479 cr16_force_relocation (fixS
*fix
)
481 if (generic_force_reloc (fix
) || SWITCH_TABLE (fix
))
487 /* Record a fixup for a cons expression. */
490 cr16_cons_fix_new (fragS
*frag
, int offset
, int len
, expressionS
*exp
)
495 default: rtype
= BFD_RELOC_NONE
; break;
496 case 1: rtype
= BFD_RELOC_CR16_NUM8
; break;
497 case 2: rtype
= BFD_RELOC_CR16_NUM16
; break;
501 rtype
= BFD_RELOC_CR16_NUM32a
;
505 rtype
= BFD_RELOC_CR16_NUM32
;
509 fix_new_exp (frag
, offset
, len
, exp
, 0, rtype
);
512 /* Generate a relocation entry for a fixup. */
515 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
* fixP
)
519 reloc
= xmalloc (sizeof (arelent
));
520 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
521 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixP
->fx_addsy
);
522 reloc
->address
= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
523 reloc
->addend
= fixP
->fx_offset
;
525 if (fixP
->fx_subsy
!= NULL
)
527 if (SWITCH_TABLE (fixP
))
529 /* Keep the current difference in the addend. */
530 reloc
->addend
= (S_GET_VALUE (fixP
->fx_addsy
)
531 - S_GET_VALUE (fixP
->fx_subsy
) + fixP
->fx_offset
);
533 switch (fixP
->fx_r_type
)
535 case BFD_RELOC_CR16_NUM8
:
536 fixP
->fx_r_type
= BFD_RELOC_CR16_SWITCH8
;
538 case BFD_RELOC_CR16_NUM16
:
539 fixP
->fx_r_type
= BFD_RELOC_CR16_SWITCH16
;
541 case BFD_RELOC_CR16_NUM32
:
542 fixP
->fx_r_type
= BFD_RELOC_CR16_SWITCH32
;
544 case BFD_RELOC_CR16_NUM32a
:
545 fixP
->fx_r_type
= BFD_RELOC_CR16_NUM32a
;
554 /* We only resolve difference expressions in the same section. */
555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
556 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
557 fixP
->fx_addsy
? S_GET_NAME (fixP
->fx_addsy
) : "0",
558 segment_name (fixP
->fx_addsy
559 ? S_GET_SEGMENT (fixP
->fx_addsy
)
561 S_GET_NAME (fixP
->fx_subsy
),
562 segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)));
566 assert ((int) fixP
->fx_r_type
> 0);
567 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
569 if (reloc
->howto
== NULL
)
571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
572 _("internal error: reloc %d (`%s') not supported by object file format"),
574 bfd_get_reloc_code_name (fixP
->fx_r_type
));
577 assert (!fixP
->fx_pcrel
== !reloc
->howto
->pc_relative
);
582 /* Prepare machine-dependent frags for relaxation. */
585 md_estimate_size_before_relax (fragS
*fragp
, asection
*seg
)
587 /* If symbol is undefined or located in a different section,
588 select the largest supported relocation. */
589 relax_substateT subtype
;
590 relax_substateT rlx_state
[] = {0, 2};
592 for (subtype
= 0; subtype
< ARRAY_SIZE (rlx_state
); subtype
+= 2)
594 if (fragp
->fr_subtype
== rlx_state
[subtype
]
595 && (!S_IS_DEFINED (fragp
->fr_symbol
)
596 || seg
!= S_GET_SEGMENT (fragp
->fr_symbol
)))
598 fragp
->fr_subtype
= rlx_state
[subtype
+ 1];
603 if (fragp
->fr_subtype
>= ARRAY_SIZE (md_relax_table
))
606 return md_relax_table
[fragp
->fr_subtype
].rlx_length
;
610 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, fragS
*fragP
)
612 /* 'opcode' points to the start of the instruction, whether
613 we need to change the instruction's fixed encoding. */
614 char *opcode
= fragP
->fr_literal
+ fragP
->fr_fix
;
615 bfd_reloc_code_real_type reloc
;
617 subseg_change (sec
, 0);
619 switch (fragP
->fr_subtype
)
622 reloc
= BFD_RELOC_CR16_DISP8
;
625 /* If the subtype is not changed due to :m operand qualifier,
626 then no need to update the opcode value. */
627 if ((int)opcode
[1] != 0x18)
629 opcode
[0] = (opcode
[0] & 0xf0);
632 reloc
= BFD_RELOC_CR16_DISP16
;
635 /* If the subtype is not changed due to :l operand qualifier,
636 then no need to update the opcode value. */
637 if ((int)opcode
[1] != 0)
639 opcode
[2] = opcode
[0];
640 opcode
[0] = opcode
[1];
643 reloc
= BFD_RELOC_CR16_DISP24
;
649 fix_new (fragP
, fragP
->fr_fix
,
650 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput
, reloc
)),
651 fragP
->fr_symbol
, fragP
->fr_offset
, 1, reloc
);
653 fragP
->fr_fix
+= md_relax_table
[fragP
->fr_subtype
].rlx_length
;
656 /* Process machine-dependent command line options. Called once for
657 each option on the command line that the machine-independent part of
658 GAS does not understand. */
661 md_parse_option (int c ATTRIBUTE_UNUSED
, char *arg ATTRIBUTE_UNUSED
)
666 /* Machine-dependent usage-output. */
669 md_show_usage (FILE *stream ATTRIBUTE_UNUSED
)
674 /* Turn a string in input_line_pointer into a floating point constant
675 of type TYPE, and store the appropriate bytes in *LITP. The number
676 of LITTLENUMS emitted is stored in *SIZEP. An error message is
677 returned, or NULL on OK. */
680 md_atof (int type
, char *litP
, int *sizeP
)
684 LITTLENUM_TYPE words
[4];
699 return _("bad call to md_atof");
702 t
= atof_ieee (input_line_pointer
, type
, words
);
704 input_line_pointer
= t
;
708 if (! target_big_endian
)
710 for (i
= prec
- 1; i
>= 0; i
--)
712 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
718 for (i
= 0; i
< prec
; i
++)
720 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
728 /* Apply a fixS (fixup of an instruction or data that we didn't have
729 enough info to complete immediately) to the data in a frag.
730 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
731 relaxation of debug sections, this function is called only when
732 fixuping relocations of debug sections. */
735 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
738 char *buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
741 switch (fixP
->fx_r_type
)
743 case BFD_RELOC_CR16_NUM8
:
744 bfd_put_8 (stdoutput
, (unsigned char) val
, buf
);
746 case BFD_RELOC_CR16_NUM16
:
747 bfd_put_16 (stdoutput
, val
, buf
);
749 case BFD_RELOC_CR16_NUM32
:
750 bfd_put_32 (stdoutput
, val
, buf
);
752 case BFD_RELOC_CR16_NUM32a
:
753 bfd_put_32 (stdoutput
, val
, buf
);
756 /* We shouldn't ever get here because linkrelax is nonzero. */
763 if (fixP
->fx_addsy
== NULL
764 && fixP
->fx_pcrel
== 0)
767 if (fixP
->fx_pcrel
== 1
768 && fixP
->fx_addsy
!= NULL
769 && S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
773 /* The location from which a PC relative jump should be calculated,
774 given a PC relative reloc. */
777 md_pcrel_from (fixS
*fixp
)
779 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
783 initialise_reg_hash_table (struct hash_control
** hash_table
,
784 const reg_entry
* register_table
,
785 const unsigned int num_entries
)
787 const reg_entry
* reg
;
790 if ((* hash_table
= hash_new ()) == NULL
)
791 as_fatal (_("Virtual memory exhausted"));
793 for (reg
= register_table
;
794 reg
< (register_table
+ num_entries
);
797 hashret
= hash_insert (* hash_table
, reg
->name
, (char *) reg
);
799 as_fatal (_("Internal Error: Can't hash %s: %s"),
804 /* This function is called once, at assembler startup time. This should
805 set up all the tables, etc that the MD part of the assembler needs. */
812 /* Set up a hash table for the instructions. */
813 if ((cr16_inst_hash
= hash_new ()) == NULL
)
814 as_fatal (_("Virtual memory exhausted"));
816 while (cr16_instruction
[i
].mnemonic
!= NULL
)
819 const char *mnemonic
= cr16_instruction
[i
].mnemonic
;
821 hashret
= hash_insert (cr16_inst_hash
, mnemonic
,
822 (char *)(cr16_instruction
+ i
));
824 if (hashret
!= NULL
&& *hashret
!= '\0')
825 as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction
[i
].mnemonic
,
826 *hashret
== 0 ? _("(unknown reason)") : hashret
);
828 /* Insert unique names into hash table. The CR16 instruction set
829 has many identical opcode names that have different opcodes based
830 on the operands. This hash table then provides a quick index to
831 the first opcode with a particular name in the opcode table. */
836 while (cr16_instruction
[i
].mnemonic
!= NULL
837 && streq (cr16_instruction
[i
].mnemonic
, mnemonic
));
840 /* Initialize reg_hash hash table. */
841 initialise_reg_hash_table (& reg_hash
, cr16_regtab
, NUMREGS
);
842 /* Initialize regp_hash hash table. */
843 initialise_reg_hash_table (& regp_hash
, cr16_regptab
, NUMREGPS
);
844 /* Initialize preg_hash hash table. */
845 initialise_reg_hash_table (& preg_hash
, cr16_pregtab
, NUMPREGS
);
846 /* Initialize pregp_hash hash table. */
847 initialise_reg_hash_table (& pregp_hash
, cr16_pregptab
, NUMPREGPS
);
849 /* Set linkrelax here to avoid fixups in most sections. */
853 /* Process constants (immediate/absolute)
854 and labels (jump targets/Memory locations). */
857 process_label_constant (char *str
, ins
* cr16_ins
)
859 char *saved_input_line_pointer
;
860 int symbol_with_at
= 0;
861 int symbol_with_s
= 0;
862 int symbol_with_m
= 0;
863 int symbol_with_l
= 0;
864 argument
*cur_arg
= cr16_ins
->arg
+ cur_arg_num
; /* Current argument. */
866 saved_input_line_pointer
= input_line_pointer
;
867 input_line_pointer
= str
;
869 expression (&cr16_ins
->exp
);
871 switch (cr16_ins
->exp
.X_op
)
875 /* Missing or bad expr becomes absolute 0. */
876 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
878 cr16_ins
->exp
.X_op
= O_constant
;
879 cr16_ins
->exp
.X_add_number
= 0;
880 cr16_ins
->exp
.X_add_symbol
= NULL
;
881 cr16_ins
->exp
.X_op_symbol
= NULL
;
885 cur_arg
->X_op
= O_constant
;
886 cur_arg
->constant
= cr16_ins
->exp
.X_add_number
;
892 cur_arg
->X_op
= O_symbol
;
893 cr16_ins
->rtype
= BFD_RELOC_NONE
;
896 if (strneq (input_line_pointer
, "@c", 2))
899 if (strneq (input_line_pointer
, "@l", 2)
900 || strneq (input_line_pointer
, ":l", 2))
903 if (strneq (input_line_pointer
, "@m", 2)
904 || strneq (input_line_pointer
, ":m", 2))
907 if (strneq (input_line_pointer
, "@s", 2)
908 || strneq (input_line_pointer
, ":s", 2))
911 switch (cur_arg
->type
)
914 if (IS_INSN_TYPE (LD_STOR_INS
) || IS_INSN_TYPE (CSTBIT_INS
))
916 if (cur_arg
->size
== 20)
917 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL20
;
919 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL20a
;
924 if (IS_INSN_TYPE (LD_STOR_INS
) || IS_INSN_TYPE (CSTBIT_INS
))
925 switch (instruction
->size
)
928 switch (cur_arg
->size
)
931 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL0
;
934 if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb"))
935 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL4
;
937 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL4a
;
943 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL16
;
946 if (cur_arg
->size
== 20)
947 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL20
;
949 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL20a
;
957 if (IS_INSN_TYPE (LD_STOR_INS
) || IS_INSN_TYPE (CSTBIT_INS
))
958 cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL20
;
962 if (IS_INSN_TYPE (LD_STOR_INS
) || IS_INSN_TYPE (CSTBIT_INS
))
963 switch (instruction
->size
)
965 case 1: cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL0
; break;
966 case 2: cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL14
; break;
967 case 3: cr16_ins
->rtype
= BFD_RELOC_CR16_REGREL20
; break;
973 if (IS_INSN_MNEMONIC ("bal"))
974 cr16_ins
->rtype
= BFD_RELOC_CR16_DISP24
;
975 else if (IS_INSN_TYPE (BRANCH_INS
))
978 cr16_ins
->rtype
= BFD_RELOC_CR16_DISP24
;
979 else if (symbol_with_m
)
980 cr16_ins
->rtype
= BFD_RELOC_CR16_DISP16
;
982 cr16_ins
->rtype
= BFD_RELOC_CR16_DISP8
;
984 else if (IS_INSN_TYPE (STOR_IMM_INS
) || IS_INSN_TYPE (LD_STOR_INS
)
985 || IS_INSN_TYPE (CSTBIT_INS
))
988 as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num
+ 1, str
);
990 cr16_ins
->rtype
= BFD_RELOC_CR16_ABS20
;
991 else /* Default to (symbol_with_l) */
992 cr16_ins
->rtype
= BFD_RELOC_CR16_ABS24
;
994 else if (IS_INSN_TYPE (BRANCH_NEQ_INS
))
995 cr16_ins
->rtype
= BFD_RELOC_CR16_DISP4
;
999 if (IS_INSN_TYPE (ARITH_INS
))
1002 cr16_ins
->rtype
= BFD_RELOC_CR16_IMM4
;
1003 else if (symbol_with_m
)
1004 cr16_ins
->rtype
= BFD_RELOC_CR16_IMM20
;
1005 else if (symbol_with_at
)
1006 cr16_ins
->rtype
= BFD_RELOC_CR16_IMM32a
;
1007 else /* Default to (symbol_with_l) */
1008 cr16_ins
->rtype
= BFD_RELOC_CR16_IMM32
;
1010 else if (IS_INSN_TYPE (ARITH_BYTE_INS
))
1012 cr16_ins
->rtype
= BFD_RELOC_CR16_IMM16
;
1021 cur_arg
->X_op
= cr16_ins
->exp
.X_op
;
1025 input_line_pointer
= saved_input_line_pointer
;
1029 /* Retrieve the opcode image of a given register.
1030 If the register is illegal for the current instruction,
1034 getreg_image (reg r
)
1036 const reg_entry
*reg
;
1038 int is_procreg
= 0; /* Nonzero means argument should be processor reg. */
1040 /* Check whether the register is in registers table. */
1042 reg
= cr16_regtab
+ r
;
1043 else /* Register not found. */
1045 as_bad (_("Unknown register: `%d'"), r
);
1049 reg_name
= reg
->name
;
1051 /* Issue a error message when register is illegal. */
1053 as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
1054 reg_name, ins_parse); \
1059 case CR16_R_REGTYPE
:
1065 case CR16_P_REGTYPE
:
1076 /* Parsing different types of operands
1077 -> constants Immediate/Absolute/Relative numbers
1078 -> Labels Relocatable symbols
1079 -> (reg pair base) Register pair base
1080 -> (rbase) Register base
1081 -> disp(rbase) Register relative
1082 -> [rinx]disp(reg pair) Register index with reg pair mode
1083 -> disp(rbase,ridx,scl) Register index mode. */
1086 set_operand (char *operand
, ins
* cr16_ins
)
1088 char *operandS
; /* Pointer to start of sub-opearand. */
1089 char *operandE
; /* Pointer to end of sub-opearand. */
1091 argument
*cur_arg
= &cr16_ins
->arg
[cur_arg_num
]; /* Current argument. */
1093 /* Initialize pointers. */
1094 operandS
= operandE
= operand
;
1096 switch (cur_arg
->type
)
1098 case arg_ic
: /* Case $0x18. */
1100 case arg_c
: /* Case 0x18. */
1102 process_label_constant (operandS
, cr16_ins
);
1104 if (cur_arg
->type
!= arg_ic
)
1105 cur_arg
->type
= arg_c
;
1108 case arg_icr
: /* Case $0x18(r1). */
1110 case arg_cr
: /* Case 0x18(r1). */
1111 /* Set displacement constant. */
1112 while (*operandE
!= '(')
1115 process_label_constant (operandS
, cr16_ins
);
1116 operandS
= operandE
;
1117 case arg_rbase
: /* Case (r1) or (r1,r0). */
1119 /* Set register base. */
1120 while (*operandE
!= ')')
1123 if ((cur_arg
->r
= get_register (operandS
)) == nullregister
)
1124 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1125 operandS
, ins_parse
);
1127 /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */
1128 if ((cur_arg
->type
!= arg_rbase
)
1129 && ((getreg_image (cur_arg
->r
) == 12)
1130 || (getreg_image (cur_arg
->r
) == 13)
1131 || (getreg_image (cur_arg
->r
) == 14)
1132 || (getreg_image (cur_arg
->r
) == 15)))
1134 cur_arg
->type
= arg_crp
;
1135 cur_arg
->rp
= cur_arg
->r
;
1139 case arg_crp
: /* Case 0x18(r1,r0). */
1140 /* Set displacement constant. */
1141 while (*operandE
!= '(')
1144 process_label_constant (operandS
, cr16_ins
);
1145 operandS
= operandE
;
1147 /* Set register pair base. */
1148 while (*operandE
!= ')')
1151 if ((cur_arg
->rp
= get_register_pair (operandS
)) == nullregister
)
1152 as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
1153 operandS
, ins_parse
);
1157 /* Set register pair base. */
1158 if ((strchr (operandS
,'(') != NULL
))
1160 while ((*operandE
!= '(') && (! ISSPACE (*operandE
)))
1162 if ((cur_arg
->rp
= get_index_register_pair (operandE
)) == nullregister
)
1163 as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
1164 operandS
, ins_parse
);
1166 cur_arg
->type
= arg_idxrp
;
1171 operandE
= operandS
;
1172 /* Set displacement constant. */
1173 while (*operandE
!= ']')
1175 process_label_constant (++operandE
, cr16_ins
);
1177 operandE
= operandS
;
1179 /* Set index register . */
1180 operandS
= strchr (operandE
,'[');
1181 if (operandS
!= NULL
)
1182 { /* Eliminate '[', detach from rest of operand. */
1185 operandE
= strchr (operandS
, ']');
1187 if (operandE
== NULL
)
1188 as_bad (_("unmatched '['"));
1190 { /* Eliminate ']' and make sure it was the last thing
1193 if (*(operandE
+ 1) != '\0')
1194 as_bad (_("garbage after index spec ignored"));
1198 if ((cur_arg
->i_r
= get_index_register (operandS
)) == nullregister
)
1199 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1200 operandS
, ins_parse
);
1210 /* Parse a single operand.
1211 operand - Current operand to parse.
1212 cr16_ins - Current assembled instruction. */
1215 parse_operand (char *operand
, ins
* cr16_ins
)
1218 argument
*cur_arg
= cr16_ins
->arg
+ cur_arg_num
; /* Current argument. */
1220 /* Initialize the type to NULL before parsing. */
1221 cur_arg
->type
= nullargs
;
1223 /* Check whether this is a condition code . */
1224 if ((IS_INSN_MNEMONIC ("b")) && ((ret_val
= get_cc (operand
)) != -1))
1226 cur_arg
->type
= arg_cc
;
1227 cur_arg
->cc
= ret_val
;
1228 cur_arg
->X_op
= O_register
;
1232 /* Check whether this is a general processor register. */
1233 if ((ret_val
= get_register (operand
)) != nullregister
)
1235 cur_arg
->type
= arg_r
;
1236 cur_arg
->r
= ret_val
;
1241 /* Check whether this is a general processor register pair. */
1242 if ((operand
[0] == '(')
1243 && ((ret_val
= get_register_pair (operand
)) != nullregister
))
1245 cur_arg
->type
= arg_rp
;
1246 cur_arg
->rp
= ret_val
;
1247 cur_arg
->X_op
= O_register
;
1251 /* Check whether the operand is a processor register.
1252 For "lprd" and "sprd" instruction, only 32 bit
1253 processor registers used. */
1254 if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd")))
1255 && ((ret_val
= get_pregister (operand
)) != nullpregister
))
1257 cur_arg
->type
= arg_pr
;
1258 cur_arg
->pr
= ret_val
;
1259 cur_arg
->X_op
= O_register
;
1263 /* Check whether this is a processor register - 32 bit. */
1264 if ((ret_val
= get_pregisterp (operand
)) != nullpregister
)
1266 cur_arg
->type
= arg_prp
;
1267 cur_arg
->prp
= ret_val
;
1268 cur_arg
->X_op
= O_register
;
1272 /* Deal with special characters. */
1276 if (strchr (operand
, '(') != NULL
)
1277 cur_arg
->type
= arg_icr
;
1279 cur_arg
->type
= arg_ic
;
1284 cur_arg
->type
= arg_rbase
;
1289 cur_arg
->type
= arg_idxr
;
1297 if (strchr (operand
, '(') != NULL
)
1299 if (strchr (operand
, ',') != NULL
1300 && (strchr (operand
, ',') > strchr (operand
, '(')))
1301 cur_arg
->type
= arg_crp
;
1303 cur_arg
->type
= arg_cr
;
1306 cur_arg
->type
= arg_c
;
1308 /* Parse an operand according to its type. */
1310 cur_arg
->constant
= 0;
1311 set_operand (operand
, cr16_ins
);
1314 /* Parse the various operands. Each operand is then analyzed to fillup
1315 the fields in the cr16_ins data structure. */
1318 parse_operands (ins
* cr16_ins
, char *operands
)
1320 char *operandS
; /* Operands string. */
1321 char *operandH
, *operandT
; /* Single operand head/tail pointers. */
1322 int allocated
= 0; /* Indicates a new operands string was allocated.*/
1323 char *operand
[MAX_OPERANDS
];/* Separating the operands. */
1324 int op_num
= 0; /* Current operand number we are parsing. */
1325 int bracket_flag
= 0; /* Indicates a bracket '(' was found. */
1326 int sq_bracket_flag
= 0; /* Indicates a square bracket '[' was found. */
1328 /* Preprocess the list of registers, if necessary. */
1329 operandS
= operandH
= operandT
= operands
;
1331 while (*operandT
!= '\0')
1333 if (*operandT
== ',' && bracket_flag
!= 1 && sq_bracket_flag
!= 1)
1336 operand
[op_num
++] = strdup (operandH
);
1337 operandH
= operandT
;
1341 if (*operandT
== ' ')
1342 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse
);
1344 if (*operandT
== '(')
1346 else if (*operandT
== '[')
1347 sq_bracket_flag
= 1;
1349 if (*operandT
== ')')
1354 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
1356 else if (*operandT
== ']')
1358 if (sq_bracket_flag
)
1359 sq_bracket_flag
= 0;
1361 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
1364 if (bracket_flag
== 1 && *operandT
== ')')
1366 else if (sq_bracket_flag
== 1 && *operandT
== ']')
1367 sq_bracket_flag
= 0;
1372 /* Adding the last operand. */
1373 operand
[op_num
++] = strdup (operandH
);
1374 cr16_ins
->nargs
= op_num
;
1376 /* Verifying correct syntax of operands (all brackets should be closed). */
1377 if (bracket_flag
|| sq_bracket_flag
)
1378 as_fatal (_("Missing matching brackets : `%s'"), ins_parse
);
1380 /* Now we parse each operand separately. */
1381 for (op_num
= 0; op_num
< cr16_ins
->nargs
; op_num
++)
1383 cur_arg_num
= op_num
;
1384 parse_operand (operand
[op_num
], cr16_ins
);
1385 free (operand
[op_num
]);
1392 /* Get the trap index in dispatch table, given its name.
1393 This routine is used by assembling the 'excp' instruction. */
1398 const trap_entry
*trap
;
1400 for (trap
= cr16_traps
; trap
< (cr16_traps
+ NUMTRAPS
); trap
++)
1401 if (strcasecmp (trap
->name
, s
) == 0)
1404 /* To make compatable with CR16 4.1 tools, the below 3-lines of
1405 * code added. Refer: Development Tracker item #123 */
1406 for (trap
= cr16_traps
; trap
< (cr16_traps
+ NUMTRAPS
); trap
++)
1407 if (trap
->entry
== (unsigned int) atoi (s
))
1410 as_bad (_("Unknown exception: `%s'"), s
);
1414 /* Top level module where instruction parsing starts.
1415 cr16_ins - data structure holds some information.
1416 operands - holds the operands part of the whole instruction. */
1419 parse_insn (ins
*insn
, char *operands
)
1423 /* Handle instructions with no operands. */
1424 for (i
= 0; cr16_no_op_insn
[i
] != NULL
; i
++)
1426 if (streq (cr16_no_op_insn
[i
], instruction
->mnemonic
))
1433 /* Handle 'excp' instructions. */
1434 if (IS_INSN_MNEMONIC ("excp"))
1437 insn
->arg
[0].type
= arg_ic
;
1438 insn
->arg
[0].constant
= gettrap (operands
);
1439 insn
->arg
[0].X_op
= O_constant
;
1443 if (operands
!= NULL
)
1444 parse_operands (insn
, operands
);
1447 /* bCC instruction requires special handling. */
1449 get_b_cc (char * op
)
1454 for (i
= 1; i
< strlen (op
); i
++)
1459 for (i
= 0; i
< cr16_num_cc
; i
++)
1460 if (streq (op1
, cr16_b_cond_tab
[i
]))
1461 return (char *) cr16_b_cond_tab
[i
];
1466 /* bCC instruction requires special handling. */
1468 is_bcc_insn (char * op
)
1470 if (!(streq (op
, "bal") || streq (op
, "beq0b") || streq (op
, "bnq0b")
1471 || streq (op
, "beq0w") || streq (op
, "bnq0w")))
1472 if ((op
[0] == 'b') && (get_b_cc (op
) != NULL
))
1477 /* Cinv instruction requires special handling. */
1480 check_cinv_options (char * operand
)
1483 int i_used
= 0, u_used
= 0, d_used
= 0;
1487 if (*p
== ',' || *p
== ' ')
1497 as_bad (_("Illegal `cinv' parameter: `%c'"), *p
);
1503 /* Retrieve the opcode image of a given register pair.
1504 If the register is illegal for the current instruction,
1508 getregp_image (reg r
)
1510 const reg_entry
*reg
;
1513 /* Check whether the register is in registers table. */
1515 reg
= cr16_regptab
+ r
;
1516 /* Register not found. */
1519 as_bad (_("Unknown register pair: `%d'"), r
);
1523 reg_name
= reg
->name
;
1525 /* Issue a error message when register pair is illegal. */
1526 #define RPAIR_IMAGE_ERR \
1527 as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \
1528 reg_name, ins_parse); \
1533 case CR16_RP_REGTYPE
:
1542 /* Retrieve the opcode image of a given index register pair.
1543 If the register is illegal for the current instruction,
1547 getidxregp_image (reg r
)
1549 const reg_entry
*reg
;
1552 /* Check whether the register is in registers table. */
1554 reg
= cr16_regptab
+ r
;
1555 /* Register not found. */
1558 as_bad (_("Unknown register pair: `%d'"), r
);
1562 reg_name
= reg
->name
;
1564 /* Issue a error message when register pair is illegal. */
1565 #define IDX_RPAIR_IMAGE_ERR \
1566 as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \
1567 reg_name, ins_parse); \
1569 if (reg->type == CR16_RP_REGTYPE)
1573 case 0: return 0; break;
1574 case 2: return 1; break;
1575 case 4: return 2; break;
1576 case 6: return 3; break;
1577 case 8: return 4; break;
1578 case 10: return 5; break;
1579 case 3: return 6; break;
1580 case 5: return 7; break;
1586 IDX_RPAIR_IMAGE_ERR
;
1590 /* Retrieve the opcode image of a given processort register.
1591 If the register is illegal for the current instruction,
1594 getprocreg_image (reg r
)
1596 const reg_entry
*reg
;
1599 /* Check whether the register is in registers table. */
1601 reg
= &cr16_pregtab
[r
- MAX_REG
];
1602 /* Register not found. */
1605 as_bad (_("Unknown processor register : `%d'"), r
);
1609 reg_name
= reg
->name
;
1611 /* Issue a error message when register pair is illegal. */
1612 #define PROCREG_IMAGE_ERR \
1613 as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \
1614 reg_name, ins_parse); \
1619 case CR16_P_REGTYPE
:
1628 /* Retrieve the opcode image of a given processort register.
1629 If the register is illegal for the current instruction,
1632 getprocregp_image (reg r
)
1634 const reg_entry
*reg
;
1636 int pregptab_disp
= 0;
1638 /* Check whether the register is in registers table. */
1644 case 4: pregptab_disp
= 1; break;
1645 case 6: pregptab_disp
= 2; break;
1649 pregptab_disp
= 3; break;
1651 pregptab_disp
= 4; break;
1653 pregptab_disp
= 5; break;
1656 reg
= &cr16_pregptab
[r
- pregptab_disp
];
1658 /* Register not found. */
1661 as_bad (_("Unknown processor register (32 bit) : `%d'"), r
);
1665 reg_name
= reg
->name
;
1667 /* Issue a error message when register pair is illegal. */
1668 #define PROCREGP_IMAGE_ERR \
1669 as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\
1670 reg_name, ins_parse); \
1675 case CR16_P_REGTYPE
:
1684 /* Routine used to represent integer X using NBITS bits. */
1687 getconstant (long x
, int nbits
)
1689 /* The following expression avoids overflow if
1690 'nbits' is the number of bits in 'bfd_vma'. */
1691 return (x
& ((((1 << (nbits
- 1)) - 1) << 1) | 1));
1694 /* Print a constant value to 'output_opcode':
1695 ARG holds the operand's type and value.
1696 SHIFT represents the location of the operand to be print into.
1697 NBITS determines the size (in bits) of the constant. */
1700 print_constant (int nbits
, int shift
, argument
*arg
)
1702 unsigned long mask
= 0;
1704 long constant
= getconstant (arg
->constant
, nbits
);
1710 /* mask the upper part of the constant, that is, the bits
1711 going to the lowest byte of output_opcode[0].
1712 The upper part of output_opcode[1] is always filled,
1713 therefore it is always masked with 0xFFFF. */
1714 mask
= (1 << (nbits
- 16)) - 1;
1715 /* Divide the constant between two consecutive words :
1717 +---------+---------+---------+---------+
1718 | | X X X X | x X x X | |
1719 +---------+---------+---------+---------+
1720 output_opcode[0] output_opcode[1] */
1722 CR16_PRINT (0, (constant
>> WORD_SHIFT
) & mask
, 0);
1723 CR16_PRINT (1, (constant
& 0xFFFF), WORD_SHIFT
);
1727 if ((nbits
== 21) && (IS_INSN_TYPE (LD_STOR_INS
))) nbits
= 20;
1731 /* mask the upper part of the constant, that is, the bits
1732 going to the lowest byte of output_opcode[0].
1733 The upper part of output_opcode[1] is always filled,
1734 therefore it is always masked with 0xFFFF. */
1735 mask
= (1 << (nbits
- 16)) - 1;
1736 /* Divide the constant between two consecutive words :
1738 +---------+---------+---------+---------+
1739 | | X X X X | - X - X | |
1740 +---------+---------+---------+---------+
1741 output_opcode[0] output_opcode[1] */
1743 if ((instruction
->size
> 2) && (shift
== WORD_SHIFT
))
1745 if (arg
->type
== arg_idxrp
)
1747 CR16_PRINT (0, ((constant
>> WORD_SHIFT
) & mask
) << 8, 0);
1748 CR16_PRINT (1, (constant
& 0xFFFF), WORD_SHIFT
);
1752 CR16_PRINT (0, (((((constant
>> WORD_SHIFT
) & mask
) << 8) & 0x0f00) | ((((constant
>> WORD_SHIFT
) & mask
) >> 4) & 0xf)),0);
1753 CR16_PRINT (1, (constant
& 0xFFFF), WORD_SHIFT
);
1757 CR16_PRINT (0, constant
, shift
);
1761 if (arg
->type
== arg_idxrp
)
1763 if (instruction
->size
== 2)
1765 CR16_PRINT (0, ((constant
) & 0xf), shift
); /* 0-3 bits. */
1766 CR16_PRINT (0, ((constant
>> 4) & 0x3), (shift
+ 20)); /* 4-5 bits. */
1767 CR16_PRINT (0, ((constant
>> 6) & 0x3), (shift
+ 14)); /* 6-7 bits. */
1768 CR16_PRINT (0, ((constant
>> 8) & 0x3f), (shift
+ 8)); /* 8-13 bits. */
1771 CR16_PRINT (0, constant
, shift
);
1777 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
1778 always filling the upper part of output_opcode[1]. If we mistakenly
1779 write it to output_opcode[0], the constant prefix (that is, 'match')
1782 +---------+---------+---------+---------+
1783 | 'match' | | X X X X | |
1784 +---------+---------+---------+---------+
1785 output_opcode[0] output_opcode[1] */
1787 if ((instruction
->size
> 2) && (shift
== WORD_SHIFT
))
1788 CR16_PRINT (1, constant
, WORD_SHIFT
);
1790 CR16_PRINT (0, constant
, shift
);
1794 CR16_PRINT (0, ((constant
/ 2) & 0xf), shift
);
1795 CR16_PRINT (0, ((constant
/ 2) >> 4), (shift
+ 8));
1799 CR16_PRINT (0, constant
, shift
);
1804 /* Print an operand to 'output_opcode', which later on will be
1805 printed to the object file:
1806 ARG holds the operand's type, size and value.
1807 SHIFT represents the printing location of operand.
1808 NBITS determines the size (in bits) of a constant operand. */
1811 print_operand (int nbits
, int shift
, argument
*arg
)
1816 CR16_PRINT (0, arg
->cc
, shift
);
1820 CR16_PRINT (0, getreg_image (arg
->r
), shift
);
1824 CR16_PRINT (0, getregp_image (arg
->rp
), shift
);
1828 CR16_PRINT (0, getprocreg_image (arg
->pr
), shift
);
1832 CR16_PRINT (0, getprocregp_image (arg
->prp
), shift
);
1837 +-----------------------------+
1838 | r_index | disp | rp_base |
1839 +-----------------------------+ */
1841 if (instruction
->size
== 3)
1843 CR16_PRINT (0, getidxregp_image (arg
->rp
), 0);
1844 if (getreg_image (arg
->i_r
) == 12)
1845 CR16_PRINT (0, 0, 3);
1847 CR16_PRINT (0, 1, 3);
1851 CR16_PRINT (0, getidxregp_image (arg
->rp
), 16);
1852 if (getreg_image (arg
->i_r
) == 12)
1853 CR16_PRINT (0, 0, 19);
1855 CR16_PRINT (0, 1, 19);
1857 print_constant (nbits
, shift
, arg
);
1861 if (getreg_image (arg
->i_r
) == 12)
1862 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
1863 || IS_INSN_MNEMONIC ("tbitb"))
1864 CR16_PRINT (0, 0, 23);
1865 else CR16_PRINT (0, 0, 24);
1867 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
1868 || IS_INSN_MNEMONIC ("tbitb"))
1869 CR16_PRINT (0, 1, 23);
1870 else CR16_PRINT (0, 1, 24);
1872 print_constant (nbits
, shift
, arg
);
1877 print_constant (nbits
, shift
, arg
);
1881 CR16_PRINT (0, getreg_image (arg
->r
), shift
);
1885 print_constant (nbits
, shift
, arg
);
1886 /* Add the register argument to the output_opcode. */
1887 CR16_PRINT (0, getreg_image (arg
->r
), (shift
+16));
1891 print_constant (nbits
, shift
, arg
);
1892 if (instruction
->size
> 1)
1893 CR16_PRINT (0, getregp_image (arg
->rp
), (shift
+ 16));
1894 else if (IS_INSN_TYPE (LD_STOR_INS
) || (IS_INSN_TYPE (CSTBIT_INS
)))
1896 if (instruction
->size
== 2)
1897 CR16_PRINT (0, getregp_image (arg
->rp
), (shift
- 8));
1898 else if (instruction
->size
== 1)
1899 CR16_PRINT (0, getregp_image (arg
->rp
), 16);
1902 CR16_PRINT (0, getregp_image (arg
->rp
), shift
);
1910 /* Retrieve the number of operands for the current assembled instruction. */
1913 get_number_of_operands (void)
1917 for (i
= 0; instruction
->operands
[i
].op_type
&& i
< MAX_OPERANDS
; i
++)
1922 /* Verify that the number NUM can be represented in BITS bits (that is,
1923 within its permitted range), based on the instruction's FLAGS.
1924 If UPDATE is nonzero, update the value of NUM if necessary.
1925 Return OP_LEGAL upon success, actual error type upon failure. */
1928 check_range (long *num
, int bits
, int unsigned flags
, int update
)
1931 int retval
= OP_LEGAL
;
1934 if (bits
== 0 && value
> 0) return OP_OUT_OF_RANGE
;
1936 /* For hosts witah longs bigger than 32-bits make sure that the top
1937 bits of a 32-bit negative value read in by the parser are set,
1938 so that the correct comparisons are made. */
1939 if (value
& 0x80000000)
1940 value
|= (-1L << 31);
1943 /* Verify operand value is even. */
1944 if (flags
& OP_EVEN
)
1957 if (flags
& OP_SHIFT
)
1963 else if (flags
& OP_SHIFT_DEC
)
1965 value
= (value
>> 1) - 1;
1970 if (flags
& OP_ABS20
)
1972 if (value
> 0xEFFFF)
1973 return OP_OUT_OF_RANGE
;
1978 if (value
== 0xB || value
== 0x9)
1979 return OP_OUT_OF_RANGE
;
1980 else if (value
== -1)
1988 if (flags
& OP_ESC1
)
1991 return OP_OUT_OF_RANGE
;
1994 if (flags
& OP_SIGNED
)
1996 max
= (1 << (bits
- 1)) - 1;
1997 min
= - (1 << (bits
- 1));
1998 if ((value
> max
) || (value
< min
))
1999 retval
= OP_OUT_OF_RANGE
;
2001 else if (flags
& OP_UNSIGNED
)
2003 max
= ((((1 << (bits
- 1)) - 1) << 1) | 1);
2005 if (((unsigned long) value
> (unsigned long) max
)
2006 || ((unsigned long) value
< (unsigned long) min
))
2007 retval
= OP_OUT_OF_RANGE
;
2009 else if (flags
& OP_NEG
)
2012 min
= - ((1 << (bits
- 1)) - 1);
2013 if ((value
> max
) || (value
< min
))
2014 retval
= OP_OUT_OF_RANGE
;
2019 /* Bunch of error checkings.
2020 The checks are made after a matching instruction was found. */
2023 warn_if_needed (ins
*insn
)
2025 /* If the post-increment address mode is used and the load/store
2026 source register is the same as rbase, the result of the
2027 instruction is undefined. */
2028 if (IS_INSN_TYPE (LD_STOR_INS_INC
))
2030 /* Enough to verify that one of the arguments is a simple reg. */
2031 if ((insn
->arg
[0].type
== arg_r
) || (insn
->arg
[1].type
== arg_r
))
2032 if (insn
->arg
[0].r
== insn
->arg
[1].r
)
2033 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn
->arg
[0].r
);
2036 if (IS_INSN_MNEMONIC ("pop")
2037 || IS_INSN_MNEMONIC ("push")
2038 || IS_INSN_MNEMONIC ("popret"))
2040 unsigned int count
= insn
->arg
[0].constant
, reg_val
;
2042 /* Check if count operand caused to save/retrive the RA twice
2043 to generate warning message. */
2044 if (insn
->nargs
> 2)
2046 reg_val
= getreg_image (insn
->arg
[1].r
);
2048 if ( ((reg_val
== 9) && (count
> 7))
2049 || ((reg_val
== 10) && (count
> 6))
2050 || ((reg_val
== 11) && (count
> 5))
2051 || ((reg_val
== 12) && (count
> 4))
2052 || ((reg_val
== 13) && (count
> 2))
2053 || ((reg_val
== 14) && (count
> 0)))
2054 as_warn (_("RA register is saved twice."));
2056 /* Check if the third operand is "RA" or "ra" */
2057 if (!(((insn
->arg
[2].r
) == ra
) || ((insn
->arg
[2].r
) == RA
)))
2058 as_bad (_("`%s' Illegal use of registers."), ins_parse
);
2061 if (insn
->nargs
> 1)
2063 reg_val
= getreg_image (insn
->arg
[1].r
);
2065 /* If register is a register pair ie r12/r13/r14 in operand1, then
2066 the count constant should be validated. */
2067 if (((reg_val
== 11) && (count
> 7))
2068 || ((reg_val
== 12) && (count
> 6))
2069 || ((reg_val
== 13) && (count
> 4))
2070 || ((reg_val
== 14) && (count
> 2))
2071 || ((reg_val
== 15) && (count
> 0)))
2072 as_bad (_("`%s' Illegal count-register combination."), ins_parse
);
2076 /* Check if the operand is "RA" or "ra" */
2077 if (!(((insn
->arg
[0].r
) == ra
) || ((insn
->arg
[0].r
) == RA
)))
2078 as_bad (_("`%s' Illegal use of register."), ins_parse
);
2082 /* Some instruction assume the stack pointer as rptr operand.
2083 Issue an error when the register to be loaded is also SP. */
2084 if (instruction
->flags
& NO_SP
)
2086 if (getreg_image (insn
->arg
[1].r
) == getreg_image (sp
))
2087 as_bad (_("`%s' has undefined result"), ins_parse
);
2090 /* If the rptr register is specified as one of the registers to be loaded,
2091 the final contents of rptr are undefined. Thus, we issue an error. */
2092 if (instruction
->flags
& NO_RPTR
)
2094 if ((1 << getreg_image (insn
->arg
[0].r
)) & insn
->arg
[1].constant
)
2095 as_bad (_("Same src/dest register is used (`r%d'),result is undefined"),
2096 getreg_image (insn
->arg
[0].r
));
2100 /* In some cases, we need to adjust the instruction pointer although a
2101 match was already found. Here, we gather all these cases.
2102 Returns 1 if instruction pointer was adjusted, otherwise 0. */
2105 adjust_if_needed (ins
*insn ATTRIBUTE_UNUSED
)
2109 if ((IS_INSN_TYPE (CSTBIT_INS
)) || (IS_INSN_TYPE (LD_STOR_INS
)))
2111 if ((instruction
->operands
[0].op_type
== abs24
)
2112 && ((insn
->arg
[0].constant
) > 0xF00000))
2114 insn
->arg
[0].constant
&= 0xFFFFF;
2123 /* Assemble a single instruction:
2124 INSN is already parsed (that is, all operand values and types are set).
2125 For instruction to be assembled, we need to find an appropriate template in
2126 the instruction table, meeting the following conditions:
2127 1: Has the same number of operands.
2128 2: Has the same operand types.
2129 3: Each operand size is sufficient to represent the instruction's values.
2130 Returns 1 upon success, 0 upon failure. */
2133 assemble_insn (char *mnemonic
, ins
*insn
)
2135 /* Type of each operand in the current template. */
2136 argtype cur_type
[MAX_OPERANDS
];
2137 /* Size (in bits) of each operand in the current template. */
2138 unsigned int cur_size
[MAX_OPERANDS
];
2139 /* Flags of each operand in the current template. */
2140 unsigned int cur_flags
[MAX_OPERANDS
];
2141 /* Instruction type to match. */
2142 unsigned int ins_type
;
2143 /* Boolean flag to mark whether a match was found. */
2146 /* Nonzero if an instruction with same number of operands was found. */
2147 int found_same_number_of_operands
= 0;
2148 /* Nonzero if an instruction with same argument types was found. */
2149 int found_same_argument_types
= 0;
2150 /* Nonzero if a constant was found within the required range. */
2151 int found_const_within_range
= 0;
2152 /* Argument number of an operand with invalid type. */
2153 int invalid_optype
= -1;
2154 /* Argument number of an operand with invalid constant value. */
2155 int invalid_const
= -1;
2156 /* Operand error (used for issuing various constant error messages). */
2157 op_err op_error
, const_err
= OP_LEGAL
;
2159 /* Retrieve data (based on FUNC) for each operand of a given instruction. */
2160 #define GET_CURRENT_DATA(FUNC, ARRAY) \
2161 for (i = 0; i < insn->nargs; i++) \
2162 ARRAY[i] = FUNC (instruction->operands[i].op_type)
2164 #define GET_CURRENT_TYPE GET_CURRENT_DATA (get_optype, cur_type)
2165 #define GET_CURRENT_SIZE GET_CURRENT_DATA (get_opbits, cur_size)
2166 #define GET_CURRENT_FLAGS GET_CURRENT_DATA (get_opflags, cur_flags)
2168 /* Instruction has no operands -> only copy the constant opcode. */
2169 if (insn
->nargs
== 0)
2171 output_opcode
[0] = BIN (instruction
->match
, instruction
->match_bits
);
2175 /* In some case, same mnemonic can appear with different instruction types.
2176 For example, 'storb' is supported with 3 different types :
2177 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
2178 We assume that when reaching this point, the instruction type was
2179 pre-determined. We need to make sure that the type stays the same
2180 during a search for matching instruction. */
2181 ins_type
= CR16_INS_TYPE (instruction
->flags
);
2183 while (/* Check that match is still not found. */
2185 /* Check we didn't get to end of table. */
2186 && instruction
->mnemonic
!= NULL
2187 /* Check that the actual mnemonic is still available. */
2188 && IS_INSN_MNEMONIC (mnemonic
)
2189 /* Check that the instruction type wasn't changed. */
2190 && IS_INSN_TYPE (ins_type
))
2192 /* Check whether number of arguments is legal. */
2193 if (get_number_of_operands () != insn
->nargs
)
2195 found_same_number_of_operands
= 1;
2197 /* Initialize arrays with data of each operand in current template. */
2202 /* Check for type compatibility. */
2203 for (i
= 0; i
< insn
->nargs
; i
++)
2205 if (cur_type
[i
] != insn
->arg
[i
].type
)
2207 if (invalid_optype
== -1)
2208 invalid_optype
= i
+ 1;
2212 found_same_argument_types
= 1;
2214 for (i
= 0; i
< insn
->nargs
; i
++)
2216 /* If 'bal' instruction size is '2' and reg operand is not 'ra'
2217 then goto next instruction. */
2218 if (IS_INSN_MNEMONIC ("bal") && (i
== 0)
2219 && (instruction
->size
== 2) && (insn
->arg
[i
].rp
!= 14))
2222 /* If 'storb' instruction with 'sp' reg and 16-bit disp of
2223 * reg-pair, leads to undifined trap, so this should use
2224 * 20-bit disp of reg-pair. */
2225 if (IS_INSN_MNEMONIC ("storb") && (instruction
->size
== 2)
2226 && (insn
->arg
[i
].r
== 15) && (insn
->arg
[i
+ 1].type
== arg_crp
))
2229 /* Only check range - don't update the constant's value, since the
2230 current instruction may not be the last we try to match.
2231 The constant's value will be updated later, right before printing
2232 it to the object file. */
2233 if ((insn
->arg
[i
].X_op
== O_constant
)
2234 && (op_error
= check_range (&insn
->arg
[i
].constant
, cur_size
[i
],
2237 if (invalid_const
== -1)
2239 invalid_const
= i
+ 1;
2240 const_err
= op_error
;
2244 /* For symbols, we make sure the relocation size (which was already
2245 determined) is sufficient. */
2246 else if ((insn
->arg
[i
].X_op
== O_symbol
)
2247 && ((bfd_reloc_type_lookup (stdoutput
, insn
->rtype
))->bitsize
2251 found_const_within_range
= 1;
2253 /* If we got till here -> Full match is found. */
2257 /* Try again with next instruction. */
2264 /* We haven't found a match - instruction can't be assembled. */
2265 if (!found_same_number_of_operands
)
2266 as_bad (_("Incorrect number of operands"));
2267 else if (!found_same_argument_types
)
2268 as_bad (_("Illegal type of operand (arg %d)"), invalid_optype
);
2269 else if (!found_const_within_range
)
2273 case OP_OUT_OF_RANGE
:
2274 as_bad (_("Operand out of range (arg %d)"), invalid_const
);
2277 as_bad (_("Operand has odd displacement (arg %d)"), invalid_const
);
2280 as_bad (_("Illegal operand (arg %d)"), invalid_const
);
2288 /* Full match - print the encoding to output file. */
2290 /* Make further checkings (such that couldn't be made earlier).
2291 Warn the user if necessary. */
2292 warn_if_needed (insn
);
2294 /* Check whether we need to adjust the instruction pointer. */
2295 if (adjust_if_needed (insn
))
2296 /* If instruction pointer was adjusted, we need to update
2297 the size of the current template operands. */
2300 for (i
= 0; i
< insn
->nargs
; i
++)
2302 int j
= instruction
->flags
& REVERSE_MATCH
?
2307 /* This time, update constant value before printing it. */
2308 if ((insn
->arg
[j
].X_op
== O_constant
)
2309 && (check_range (&insn
->arg
[j
].constant
, cur_size
[j
],
2310 cur_flags
[j
], 1) != OP_LEGAL
))
2311 as_fatal (_("Illegal operand (arg %d)"), j
+1);
2314 /* First, copy the instruction's opcode. */
2315 output_opcode
[0] = BIN (instruction
->match
, instruction
->match_bits
);
2317 for (i
= 0; i
< insn
->nargs
; i
++)
2319 /* For BAL (ra),disp17 instuction only. And also set the
2320 DISP24a relocation type. */
2321 if (IS_INSN_MNEMONIC ("bal") && (instruction
->size
== 2) && i
== 0)
2323 insn
->rtype
= BFD_RELOC_CR16_DISP24a
;
2327 print_operand (cur_size
[i
], instruction
->operands
[i
].shift
,
2335 /* Print the instruction.
2336 Handle also cases where the instruction is relaxable/relocatable. */
2339 print_insn (ins
*insn
)
2341 unsigned int i
, j
, insn_size
;
2343 unsigned short words
[4];
2346 /* Arrange the insn encodings in a WORD size array. */
2347 for (i
= 0, j
= 0; i
< 2; i
++)
2349 words
[j
++] = (output_opcode
[i
] >> 16) & 0xFFFF;
2350 words
[j
++] = output_opcode
[i
] & 0xFFFF;
2353 /* Handle relocation. */
2354 if ((instruction
->flags
& RELAXABLE
) && relocatable
)
2357 /* Write the maximal instruction size supported. */
2358 insn_size
= INSN_MAX_SIZE
;
2360 if (IS_INSN_TYPE (BRANCH_INS
))
2362 switch (insn
->rtype
)
2364 case BFD_RELOC_CR16_DISP24
:
2367 case BFD_RELOC_CR16_DISP16
:
2378 this_frag
= frag_var (rs_machine_dependent
, insn_size
*2,
2380 insn
->exp
.X_add_symbol
,
2381 insn
->exp
.X_add_number
,
2386 insn_size
= instruction
->size
;
2387 this_frag
= frag_more (insn_size
* 2);
2389 if ((relocatable
) && (insn
->rtype
!= BFD_RELOC_NONE
))
2391 reloc_howto_type
*reloc_howto
;
2394 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, insn
->rtype
);
2399 size
= bfd_get_reloc_size (reloc_howto
);
2401 if (size
< 1 || size
> 4)
2404 fix_new_exp (frag_now
, this_frag
- frag_now
->fr_literal
,
2405 size
, &insn
->exp
, reloc_howto
->pc_relative
,
2410 /* Verify a 2-byte code alignment. */
2411 addr_mod
= frag_now_fix () & 1;
2412 if (frag_now
->has_code
&& frag_now
->insn_addr
!= addr_mod
)
2413 as_bad (_("instruction address is not a multiple of 2"));
2414 frag_now
->insn_addr
= addr_mod
;
2415 frag_now
->has_code
= 1;
2417 /* Write the instruction encoding to frag. */
2418 for (i
= 0; i
< insn_size
; i
++)
2420 md_number_to_chars (this_frag
, (valueT
) words
[i
], 2);
2425 /* This is the guts of the machine-dependent assembler. OP points to a
2426 machine dependent instruction. This function is supposed to emit
2427 the frags/bytes it assembles to. */
2430 md_assemble (char *op
)
2433 char *param
, param1
[32];
2436 /* Reset global variables for a new instruction. */
2439 /* Strip the mnemonic. */
2440 for (param
= op
; *param
!= 0 && !ISSPACE (*param
); param
++)
2445 /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */
2446 if (is_bcc_insn (op
))
2448 strcpy (param1
, get_b_cc (op
));
2450 strcat (param1
,",");
2451 strcat (param1
, param
);
2452 param
= (char *) ¶m1
;
2455 /* Checking the cinv options and adjust the mnemonic by removing the
2456 extra white spaces. */
2457 if (streq ("cinv", op
))
2459 /* Validate the cinv options. */
2460 check_cinv_options (param
);
2464 /* MAPPING - SHIFT INSN, if imm4/imm16 positive values
2465 lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
2466 as CR16 core doesn't support lsh[b/w] right shift operaions. */
2467 if ((streq ("lshb", op
) || streq ("lshw", op
) || streq ("lshd", op
))
2468 && (param
[0] == '$'))
2470 strcpy (param1
, param
);
2471 /* Find the instruction. */
2472 instruction
= (const inst
*) hash_find (cr16_inst_hash
, op
);
2473 parse_operands (&cr16_ins
, param1
);
2474 if (((&cr16_ins
)->arg
[0].type
== arg_ic
)
2475 && ((&cr16_ins
)->arg
[0].constant
>= 0))
2477 if (streq ("lshb", op
))
2479 else if (streq ("lshd", op
))
2486 /* Find the instruction. */
2487 instruction
= (const inst
*) hash_find (cr16_inst_hash
, op
);
2488 if (instruction
== NULL
)
2490 as_bad (_("Unknown opcode: `%s'"), op
);
2494 /* Tie dwarf2 debug info to the address at the start of the insn. */
2495 dwarf2_emit_insn (0);
2497 /* Parse the instruction's operands. */
2498 parse_insn (&cr16_ins
, param
);
2500 /* Assemble the instruction - return upon failure. */
2501 if (assemble_insn (op
, &cr16_ins
) == 0)
2504 /* Print the instruction. */
2505 print_insn (&cr16_ins
);