gas/config/tc-d10v.c

   1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
   2
   3    Copyright (C) 1996 Free Software Foundation.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include <ctype.h>
  24 #include "as.h"
  25 #include "subsegs.h"
  26 #include "opcode/d10v.h"
  27 #include "elf/ppc.h"
  28
  29 const char comment_chars[] = ";";
  30 const char line_comment_chars[] = "#";
  31 const char line_separator_chars[] = "";
  32 const char *md_shortopts = "O";
  33 const char EXP_CHARS[] = "eE";
  34 const char FLT_CHARS[] = "dD";
  35
  36 int Optimizing = 0;
  37
  38 #define AT_WORD (-1)
  39
  40 /* fixups */
  41 #define MAX_INSN_FIXUPS (5)
  42 struct d10v_fixup
  43 {
  44   expressionS exp;
  45   int operand;
  46   int pcrel;
  47   int size;
  48   bfd_reloc_code_real_type reloc;
  49 };
  50
  51 typedef struct _fixups
  52 {
  53   int fc;
  54   struct d10v_fixup fix[MAX_INSN_FIXUPS];
  55   struct _fixups *next;
  56 } Fixups;
  57
  58 static Fixups FixUps[2];
  59 static Fixups *fixups;
  60
  61 /* local functions */
  62 static int reg_name_search PARAMS ((char *name));
  63 static int register_name PARAMS ((expressionS *expressionP));
  64 static int check_range PARAMS ((unsigned long num, int bits, int flags));
  65 static int postfix PARAMS ((char *p));
  66 static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
  67 static int get_operands PARAMS ((expressionS exp[]));
  68 static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
  69 static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
  70 static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
  71 static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
  72 static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
  73                                   struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx));
  74 static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
  75 static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
  76                                                    offsetT value, int left, fixS *fix));
  77 static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
  78                                   struct d10v_opcode *opcode2, unsigned long insn2));
  79
  80
  81 struct option md_longopts[] = {
  82   {NULL, no_argument, NULL, 0}
  83 };
  84 size_t md_longopts_size = sizeof(md_longopts);
  85
  86 static void d10v_dot_word PARAMS ((int));
  87
  88 /* The target specific pseudo-ops which we support.  */
  89 const pseudo_typeS md_pseudo_table[] =
  90 {
  91   { "word",     d10v_dot_word,  2 },
  92   { NULL,       NULL,           0 }
  93 };
  94
  95 /* Opcode hash table.  */
  96 static struct hash_control *d10v_hash;
  97
  98 /* reg_name_search does a binary search of the pre_defined_registers
  99    array to see if "name" is a valid regiter name.  Returns the register
 100    number from the array on success, or -1 on failure. */
 101
 102 static int
 103 reg_name_search (name)
 104      char *name;
 105 {
 106   int middle, low, high;
 107   int cmp;
 108
 109   low = 0;
 110   high = reg_name_cnt() - 1;
 111
 112   do
 113     {
 114       middle = (low + high) / 2;
 115       cmp = strcasecmp (name, pre_defined_registers[middle].name);
 116       if (cmp < 0)
 117         high = middle - 1;
 118       else if (cmp > 0)
 119         low = middle + 1;
 120       else
 121           return pre_defined_registers[middle].value;
 122     }
 123   while (low <= high);
 124   return -1;
 125 }
 126
 127 /* register_name() checks the string at input_line_pointer
 128    to see if it is a valid register name */
 129
 130 static int
 131 register_name (expressionP)
 132      expressionS *expressionP;
 133 {
 134   int reg_number;
 135   char c, *p = input_line_pointer;
 136
 137   while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
 138     p++;
 139
 140   c = *p;
 141   if (c)
 142     *p++ = 0;
 143
 144   /* look to see if it's in the register table */
 145   reg_number = reg_name_search (input_line_pointer);
 146   if (reg_number >= 0)
 147     {
 148       expressionP->X_op = O_register;
 149       /* temporarily store a pointer to the string here */
 150       expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
 151       expressionP->X_add_number = reg_number;
 152       input_line_pointer = p;
 153       return 1;
 154     }
 155   if (c)
 156     *(p-1) = c;
 157   return 0;
 158 }
 159
 160
 161 static int
 162 check_range (num, bits, flags)
 163      unsigned long num;
 164      int bits;
 165      int flags;
 166 {
 167   long min, max, bit1;
 168   int retval=0;
 169
 170   /* don't bother checking 16-bit values */
 171   if (bits == 16)
 172     return 0;
 173
 174   if (flags & OPERAND_SHIFT)
 175     {
 176       /* all special shift operands are unsigned */
 177       /* and <= 16.  We allow 0 for now. */
 178       if (num>16)
 179         return 1;
 180       else
 181         return 0;
 182     }
 183
 184   if (flags & OPERAND_SIGNED)
 185     {
 186       max = (1 << (bits - 1))-1;
 187       min = - (1 << (bits - 1));
 188       if (((long)num > max) || ((long)num < min))
 189         retval = 1;
 190     }
 191   else
 192     {
 193       max = (1 << bits) - 1;
 194       min = 0;
 195       if ((num > max) || (num < min))
 196         retval = 1;
 197     }
 198   return retval;
 199 }
 200
 201
 202 void
 203 md_show_usage (stream)
 204   FILE *stream;
 205 {
 206   fprintf(stream, "D10V options:\n\
 207 -O                      optimize.  Will do some operations in parallel.\n");
 208 }
 209
 210 int
 211 md_parse_option (c, arg)
 212      int c;
 213      char *arg;
 214 {
 215   switch (c)
 216     {
 217     case 'O':
 218       /* Optimize. Will attempt to parallelize operations */
 219       Optimizing = 1;
 220       break;
 221     default:
 222       return 0;
 223     }
 224   return 1;
 225 }
 226
 227 symbolS *
 228 md_undefined_symbol (name)
 229   char *name;
 230 {
 231   return 0;
 232 }
 233
 234 /* Turn a string in input_line_pointer into a floating point constant of type
 235    type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
 236    emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
 237  */
 238 char *
 239 md_atof (type, litP, sizeP)
 240      int type;
 241      char *litP;
 242      int *sizeP;
 243 {
 244   int prec;
 245   LITTLENUM_TYPE words[4];
 246   char *t;
 247   int i;
 248
 249   switch (type)
 250     {
 251     case 'f':
 252       prec = 2;
 253       break;
 254     case 'd':
 255       prec = 4;
 256       break;
 257     default:
 258       *sizeP = 0;
 259       return "bad call to md_atof";
 260     }
 261
 262   t = atof_ieee (input_line_pointer, type, words);
 263   if (t)
 264     input_line_pointer = t;
 265
 266   *sizeP = prec * 2;
 267
 268   for (i = 0; i < prec; i++)
 269     {
 270       md_number_to_chars (litP, (valueT) words[i], 2);
 271           litP += 2;
 272     }
 273   return NULL;
 274 }
 275
 276 void
 277 md_convert_frag (abfd, sec, fragP)
 278   bfd *abfd;
 279   asection *sec;
 280   fragS *fragP;
 281 {
 282   printf ("call to md_convert_frag \n");
 283   abort ();
 284 }
 285
 286 valueT
 287 md_section_align (seg, addr)
 288      asection *seg;
 289      valueT addr;
 290 {
 291   int align = bfd_get_section_alignment (stdoutput, seg);
 292   return ((addr + (1 << align) - 1) & (-1 << align));
 293 }
 294
 295
 296 void
 297 md_begin ()
 298 {
 299   char *prev_name = "";
 300   struct d10v_opcode *opcode;
 301   d10v_hash = hash_new();
 302
 303   /* Insert unique names into hash table.  The D10v instruction set
 304      has many identical opcode names that have different opcodes based
 305      on the operands.  This hash table then provides a quick index to
 306      the first opcode with a particular name in the opcode table.  */
 307
 308   for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
 309     {
 310       if (strcmp (prev_name, opcode->name))
 311         {
 312           prev_name = (char *)opcode->name;
 313           hash_insert (d10v_hash, opcode->name, (char *) opcode);
 314         }
 315     }
 316
 317   fixups = &FixUps[0];
 318   FixUps[0].next = &FixUps[1];
 319   FixUps[1].next = &FixUps[0];
 320 }
 321
 322
 323 /* this function removes the postincrement or postdecrement
 324    operator ( '+' or '-' ) from an expression */
 325
 326 static int postfix (p)
 327      char *p;
 328 {
 329   while (*p != '-' && *p != '+')
 330     {
 331       if (*p==0 || *p=='\n' || *p=='\r')
 332         break;
 333       p++;
 334     }
 335
 336   if (*p == '-')
 337     {
 338       *p = ' ';
 339       return (-1);
 340     }
 341   if (*p == '+')
 342     {
 343       *p = ' ';
 344       return (1);
 345     }
 346
 347   return (0);
 348 }
 349
 350
 351 static bfd_reloc_code_real_type
 352 get_reloc (op)
 353      struct d10v_operand *op;
 354 {
 355   int bits = op->bits;
 356
 357   /*  printf("get_reloc:  bits=%d  address=%d\n",bits,op->flags & OPERAND_ADDR);   */
 358   if (bits <= 4)
 359     return (0);
 360
 361   if (op->flags & OPERAND_ADDR)
 362     {
 363       if (bits == 8)
 364         return (BFD_RELOC_D10V_10_PCREL_R);
 365       else
 366         return (BFD_RELOC_D10V_18_PCREL);
 367     }
 368
 369   return (BFD_RELOC_16);
 370 }
 371
 372
 373 /* get_operands parses a string of operands and returns
 374    an array of expressions */
 375
 376 static int
 377 get_operands (exp)
 378      expressionS exp[];
 379 {
 380   char *p = input_line_pointer;
 381   int numops = 0;
 382   int post = 0;
 383
 384   while (*p)
 385     {
 386       while (*p == ' ' || *p == '\t' || *p == ',')
 387         p++;
 388       if (*p==0 || *p=='\n' || *p=='\r')
 389         break;
 390
 391       if (*p == '@')
 392         {
 393           p++;
 394           exp[numops].X_op = O_absent;
 395           if (*p == '(')
 396             {
 397               p++;
 398               exp[numops].X_add_number = OPERAND_ATPAR;
 399             }
 400           else if (*p == '-')
 401             {
 402               p++;
 403               exp[numops].X_add_number = OPERAND_ATMINUS;
 404             }
 405           else
 406             {
 407               exp[numops].X_add_number = OPERAND_ATSIGN;
 408               post = postfix (p);
 409             }
 410           numops++;
 411           continue;
 412         }
 413
 414       if (*p == ')')
 415         {
 416           /* just skip the trailing paren */
 417           p++;
 418           continue;
 419         }
 420
 421       input_line_pointer = p;
 422
 423       /* check to see if it might be a register name */
 424       if (!register_name (&exp[numops]))
 425         {
 426           /* parse as an expression */
 427           expression (&exp[numops]);
 428         }
 429
 430       if (!strncasecmp (input_line_pointer, "@word", 5))
 431         {
 432           if (exp[numops].X_op == O_register)
 433             {
 434               /* if it looked like a register name but was followed by "@word" */
 435               /* then it was really a symbol, so change it to one */
 436               exp[numops].X_op = O_symbol;
 437               exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol);
 438               exp[numops].X_op_symbol = NULL;
 439             }
 440           exp[numops].X_add_number = AT_WORD;
 441           input_line_pointer += 5;
 442         }
 443
 444       if (exp[numops].X_op == O_illegal)
 445         as_bad ("illegal operand");
 446       else if (exp[numops].X_op == O_absent)
 447         as_bad ("missing operand");
 448
 449       numops++;
 450       p = input_line_pointer;
 451     }
 452
 453   switch (post)
 454     {
 455     case -1:    /* postdecrement mode */
 456       exp[numops].X_op = O_absent;
 457       exp[numops++].X_add_number = OPERAND_MINUS;
 458       break;
 459     case 1:     /* postincrement mode */
 460       exp[numops].X_op = O_absent;
 461       exp[numops++].X_add_number = OPERAND_PLUS;
 462       break;
 463     }
 464
 465   exp[numops].X_op = 0;
 466   return (numops);
 467 }
 468
 469 static unsigned long
 470 d10v_insert_operand (insn, op_type, value, left, fix)
 471      unsigned long insn;
 472      int op_type;
 473      offsetT value;
 474      int left;
 475      fixS *fix;
 476 {
 477   int shift, bits;
 478
 479   shift = d10v_operands[op_type].shift;
 480   if (left)
 481     shift += 15;
 482
 483   bits = d10v_operands[op_type].bits;
 484
 485   /* truncate to the proper number of bits */
 486   if (check_range (value, bits, d10v_operands[op_type].flags))
 487     as_bad_where (fix->fx_file, fix->fx_line, "operand out of range: %d", value);
 488
 489   value &= 0x7FFFFFFF >> (31 - bits);
 490   insn |= (value << shift);
 491
 492   return insn;
 493 }
 494
 495
 496 /* build_insn takes a pointer to the opcode entry in the opcode table
 497    and the array of operand expressions and returns the instruction */
 498
 499 static unsigned long
 500 build_insn (opcode, opers, insn)
 501      struct d10v_opcode *opcode;
 502      expressionS *opers;
 503      unsigned long insn;
 504 {
 505   int i, bits, shift, flags, format;
 506   unsigned int number;
 507
 508   /* the insn argument is only used for the DIVS kludge */
 509   if (insn)
 510     format = LONG_R;
 511   else
 512     {
 513       insn = opcode->opcode;
 514       format = opcode->format;
 515     }
 516
 517   for (i=0;opcode->operands[i];i++)
 518     {
 519       flags = d10v_operands[opcode->operands[i]].flags;
 520       bits = d10v_operands[opcode->operands[i]].bits;
 521       shift = d10v_operands[opcode->operands[i]].shift;
 522       number = opers[i].X_add_number;
 523
 524       if (flags & OPERAND_REG)
 525         {
 526           number &= REGISTER_MASK;
 527           if (format == LONG_L)
 528             shift += 15;
 529         }
 530
 531       if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
 532         {
 533           /* now create a fixup */
 534
 535           /*
 536           printf("need a fixup: ");
 537           print_expr_1(stdout,&opers[i]);
 538           printf("\n");
 539           */
 540
 541           if (fixups->fc >= MAX_INSN_FIXUPS)
 542             as_fatal ("too many fixups");
 543
 544           if (opers[i].X_op == O_symbol && number == AT_WORD)
 545             {
 546               number = opers[i].X_add_number = 0;
 547               fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
 548             } else
 549               fixups->fix[fixups->fc].reloc =
 550                 get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]);
 551
 552           if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
 553               fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
 554             fixups->fix[fixups->fc].size = 2;
 555           else
 556             fixups->fix[fixups->fc].size = 4;
 557
 558           fixups->fix[fixups->fc].exp = opers[i];
 559           fixups->fix[fixups->fc].operand = opcode->operands[i];
 560           fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
 561           (fixups->fc)++;
 562         }
 563
 564       /* truncate to the proper number of bits */
 565       if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
 566         as_bad("operand out of range: %d",number);
 567       number &= 0x7FFFFFFF >> (31 - bits);
 568       insn = insn | (number << shift);
 569     }
 570
 571   /* kludge: for DIVS, we need to put the operands in twice */
 572   /* on the second pass, format is changed to LONG_R to force */
 573   /* the second set of operands to not be shifted over 15 */
 574   if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
 575     insn = build_insn (opcode, opers, insn);
 576
 577   return insn;
 578 }
 579
 580 /* write out a long form instruction */
 581 static void
 582 write_long (opcode, insn, fx)
 583      struct d10v_opcode *opcode;
 584      unsigned long insn;
 585      Fixups *fx;
 586 {
 587   int i, where;
 588   char *f = frag_more(4);
 589
 590   insn |= FM11;
 591   /* printf("INSN: %08x\n",insn); */
 592   number_to_chars_bigendian (f, insn, 4);
 593
 594   for (i=0; i < fx->fc; i++)
 595     {
 596       if (fx->fix[i].reloc)
 597         {
 598           where = f - frag_now->fr_literal;
 599           if (fx->fix[i].size == 2)
 600             where += 2;
 601           /*
 602           printf("fix_new_exp: where:%x size:%d\n    ",where,fx->fix[i].size);
 603           print_expr_1(stdout,&(fx->fix[i].exp));
 604           printf("\n");
 605           */
 606
 607           if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
 608             fx->fix[i].operand |= 4096;
 609
 610           fix_new_exp (frag_now,
 611                        where,
 612                        fx->fix[i].size,
 613                        &(fx->fix[i].exp),
 614                        fx->fix[i].pcrel,
 615                        fx->fix[i].operand|2048);
 616         }
 617     }
 618   fx->fc = 0;
 619 }
 620
 621
 622 /* write out a short form instruction by itself */
 623 static void
 624 write_1_short (opcode, insn, fx)
 625      struct d10v_opcode *opcode;
 626      unsigned long insn;
 627      Fixups *fx;
 628 {
 629   char *f = frag_more(4);
 630   int i, where;
 631
 632   if (opcode->exec_type & PARONLY)
 633     as_fatal ("Instruction must be executed in parallel with another instruction.");
 634
 635   /* the other container needs to be NOP */
 636   /* according to 4.3.1: for FM=00, sub-instructions performed only
 637      by IU cannot be encoded in L-container. */
 638   if (opcode->unit == IU)
 639     insn |= FM00 | (NOP << 15);         /* right container */
 640   else
 641     insn = FM00 | (insn << 15) | NOP;   /* left container */
 642
 643   /*  printf("INSN: %08x\n",insn);  */
 644   number_to_chars_bigendian (f, insn, 4);
 645   for (i=0; i < fx->fc; i++)
 646     {
 647       if (fx->fix[i].reloc)
 648         {
 649           where = f - frag_now->fr_literal;
 650           if (fx->fix[i].size == 2)
 651             where += 2;
 652
 653           /*
 654           printf("fix_new_exp: where:%x size:%d\n    ",where, fx->fix[i].size);
 655           print_expr_1(stdout,&(fx->fix[i].exp));
 656           printf("\n");
 657           */
 658
 659           if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
 660             fx->fix[i].operand |= 4096;
 661
 662           /* if it's an R reloc, we may have to switch it to L */
 663           if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
 664             fx->fix[i].operand |= 1024;
 665
 666           fix_new_exp (frag_now,
 667                        where,
 668                        fx->fix[i].size,
 669                        &(fx->fix[i].exp),
 670                        fx->fix[i].pcrel,
 671                        fx->fix[i].operand|2048);
 672         }
 673     }
 674   fx->fc = 0;
 675 }
 676
 677 /* write out a short form instruction if possible */
 678 /* return number of instructions not written out */
 679 static int
 680 write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
 681      struct d10v_opcode *opcode1, *opcode2;
 682      unsigned long insn1, insn2;
 683      int exec_type;
 684      Fixups *fx;
 685 {
 686   unsigned long insn;
 687   char *f;
 688   int i,j, where;
 689
 690   if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY)
 691                         || (opcode2->exec_type & PARONLY)))
 692     as_fatal("Instruction must be executed in parallel");
 693
 694   if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
 695     as_fatal ("Long instructions may not be combined.");
 696
 697   if(opcode1->exec_type & BRANCH_LINK)
 698     {
 699       /* subroutines must be called from 32-bit boundaries */
 700       /* so the return address will be correct */
 701       write_1_short (opcode1, insn1, fx->next);
 702       return (1);
 703     }
 704
 705   switch (exec_type)
 706     {
 707     case 0:     /* order not specified */
 708       if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2))
 709         {
 710           /* parallel */
 711           if (opcode1->unit == IU)
 712             insn = FM00 | (insn2 << 15) | insn1;
 713           else if (opcode2->unit == MU)
 714             insn = FM00 | (insn2 << 15) | insn1;
 715           else
 716             {
 717               insn = FM00 | (insn1 << 15) | insn2;
 718               fx = fx->next;
 719             }
 720         }
 721       else if (opcode1->unit == IU)
 722         {
 723           /* reverse sequential */
 724           insn = FM10 | (insn2 << 15) | insn1;
 725         }
 726       else
 727         {
 728           /* sequential */
 729           insn = FM01 | (insn1 << 15) | insn2;
 730           fx = fx->next;
 731         }
 732       break;
 733     case 1:     /* parallel */
 734       if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
 735         as_fatal ("One of these instructions may not be executed in parallel.");
 736
 737       if (opcode1->unit == IU)
 738         {
 739           if (opcode2->unit == IU)
 740             as_fatal ("Two IU instructions may not be executed in parallel");
 741           as_warn ("Swapping instruction order");
 742           insn = FM00 | (insn2 << 15) | insn1;
 743         }
 744       else if (opcode2->unit == MU)
 745         {
 746           if (opcode1->unit == MU)
 747             as_fatal ("Two MU instructions may not be executed in parallel");
 748           as_warn ("Swapping instruction order");
 749           insn = FM00 | (insn2 << 15) | insn1;
 750         }
 751       else
 752         {
 753           insn = FM00 | (insn1 << 15) | insn2;
 754           fx = fx->next;
 755         }
 756       break;
 757     case 2:     /* sequential */
 758       if (opcode1->unit == IU)
 759         as_fatal ("IU instruction may not be in the left container");
 760       insn = FM01 | (insn1 << 15) | insn2;
 761       fx = fx->next;
 762       break;
 763     case 3:     /* reverse sequential */
 764       if (opcode2->unit == MU)
 765         as_fatal ("MU instruction may not be in the right container");
 766       insn = FM10 | (insn1 << 15) | insn2;
 767       fx = fx->next;
 768       break;
 769     default:
 770       as_fatal("unknown execution type passed to write_2_short()");
 771     }
 772
 773   /*  printf("INSN: %08x\n",insn); */
 774   f = frag_more(4);
 775   number_to_chars_bigendian (f, insn, 4);
 776
 777   for (j=0; j<2; j++)
 778     {
 779       for (i=0; i < fx->fc; i++)
 780         {
 781           if (fx->fix[i].reloc)
 782             {
 783               where = f - frag_now->fr_literal;
 784               if (fx->fix[i].size == 2)
 785                 where += 2;
 786
 787               if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
 788                 fx->fix[i].operand |= 1024;
 789
 790               if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
 791                 fx->fix[i].operand |= 4096;
 792
 793               /*
 794                 printf("fix_new_exp: where:%x reloc:%d\n    ",where,fx->fix[i].operand);
 795                 print_expr_1(stdout,&(fx->fix[i].exp));
 796                 printf("\n");
 797                 */
 798
 799               fix_new_exp (frag_now,
 800                            where,
 801                            fx->fix[i].size,
 802                            &(fx->fix[i].exp),
 803                            fx->fix[i].pcrel,
 804                            fx->fix[i].operand|2048);
 805             }
 806         }
 807       fx->fc = 0;
 808       fx = fx->next;
 809     }
 810   return (0);
 811 }
 812
 813
 814 /* Check 2 instructions and determine if they can be safely */
 815 /* executed in parallel.  Returns 1 if they can be.         */
 816 static int
 817 parallel_ok (op1, insn1, op2, insn2)
 818      struct d10v_opcode *op1, *op2;
 819      unsigned long insn1, insn2;
 820 {
 821   int i, j, flags, mask, shift, regno;
 822   unsigned long ins, mod[2], used[2];
 823   struct d10v_opcode *op;
 824
 825   if (op1->exec_type & SEQ || op2->exec_type & SEQ)
 826     return 0;
 827
 828   /* The idea here is to create two sets of bitmasks (mod and used) */
 829   /* which indicate which registers are modified or used by each instruction. */
 830   /* The operation can only be done in parallel if instruction 1 and instruction 2 */
 831   /* modify different registers, and neither instruction modifies any registers */
 832   /* the other is using.  Accesses to control registers, PSW, and memory are treated */
 833   /* as accesses to a single register.  So if both instructions write memory or one */
 834   /* instruction writes memory and the other reads, then they cannot be done in parallel. */
 835   /* Likewise, if one instruction mucks with the psw and the other reads the PSW */
 836   /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
 837
 838   /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
 839   /* r0-r15       0-15  */
 840   /* a0-a1        16-17 */
 841   /* cr (not psw) 18    */
 842   /* psw          19    */
 843   /* mem          20    */
 844
 845   for (j=0;j<2;j++)
 846     {
 847       if (j == 0)
 848         {
 849           op = op1;
 850           ins = insn1;
 851         }
 852       else
 853         {
 854           op = op2;
 855           ins = insn2;
 856         }
 857       mod[j] = used[j] = 0;
 858       for (i = 0; op->operands[i]; i++)
 859         {
 860           flags = d10v_operands[op->operands[i]].flags;
 861           shift = d10v_operands[op->operands[i]].shift;
 862           mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
 863           if (flags & OPERAND_REG)
 864             {
 865               regno = (ins >> shift) & mask;
 866               if (flags & OPERAND_ACC)
 867                 regno += 16;
 868               else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
 869                 {
 870                   if (regno == 0)
 871                     regno = 19;
 872                   else
 873                     regno = 18;
 874                 }
 875               else if (flags & OPERAND_FLAG)
 876                 regno = 19;
 877
 878               if ( flags & OPERAND_DEST )
 879                 {
 880                   mod[j] |= 1 << regno;
 881                   if (flags & OPERAND_EVEN)
 882                     mod[j] |= 1 << (regno + 1);
 883                 }
 884               else
 885                 {
 886                   used[j] |= 1 << regno ;
 887                   if (flags & OPERAND_EVEN)
 888                     used[j] |= 1 << (regno + 1);
 889                 }
 890             }
 891         }
 892       if (op->exec_type & RMEM)
 893         used[j] |= 1 << 20;
 894       else if (op->exec_type & WMEM)
 895         mod[j] |= 1 << 20;
 896       else if (op->exec_type & RF0)
 897         used[j] |= 1 << 19;
 898       else if (op->exec_type & WF0)
 899         mod[j] |= 1 << 19;
 900       else if (op->exec_type & WCAR)
 901         mod[j] |= 1 << 19;
 902     }
 903   if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0)
 904     return 1;
 905   return 0;
 906 }
 907
 908
 909 /* This is the main entry point for the machine-dependent assembler.  str points to a
 910    machine-dependent instruction.  This function is supposed to emit the frags/bytes
 911    it assembles to.  For the D10V, it mostly handles the special VLIW parsing and packing
 912    and leaves the difficult stuff to do_assemble().
 913  */
 914
 915 static unsigned long prev_insn;
 916 static struct d10v_opcode *prev_opcode = 0;
 917 static subsegT prev_subseg;
 918 static segT prev_seg;
 919
 920 void
 921 md_assemble (str)
 922      char *str;
 923 {
 924   struct d10v_opcode *opcode;
 925   unsigned long insn;
 926   int extype=0;                 /* execution type; parallel, etc */
 927   static int etype=0;           /* saved extype.  used for multiline instructions */
 928   char *str2;
 929
 930   /*  printf("md_assemble: str=%s\n",str); */
 931
 932   if (etype == 0)
 933     {
 934       /* look for the special multiple instruction separators */
 935       str2 = strstr (str, "||");
 936       if (str2)
 937         extype = 1;
 938       else
 939         {
 940           str2 = strstr (str, "->");
 941           if (str2)
 942             extype = 2;
 943           else
 944             {
 945               str2 = strstr (str, "<-");
 946               if (str2)
 947                 extype = 3;
 948             }
 949         }
 950       /* str2 points to the separator, if one */
 951       if (str2)
 952         {
 953           *str2 = 0;
 954
 955           /* if two instructions are present and we already have one saved
 956              then first write it out */
 957           if (prev_opcode)
 958             write_1_short (prev_opcode, prev_insn, fixups->next);
 959
 960           /* assemble first instruction and save it */
 961           prev_insn = do_assemble (str, &prev_opcode);
 962           if (prev_insn == -1)
 963             as_fatal ("can't find opcode ");
 964           fixups = fixups->next;
 965           str = str2 + 2;
 966         }
 967     }
 968
 969   insn = do_assemble (str, &opcode);
 970   if (insn == -1)
 971     {
 972       if (extype)
 973         {
 974           etype = extype;
 975           return;
 976         }
 977       as_fatal ("can't find opcode ");
 978     }
 979
 980   if (etype)
 981     {
 982       extype = etype;
 983       etype = 0;
 984     }
 985
 986   /* if this is a long instruction, write it and any previous short instruction */
 987   if (opcode->format & LONG_OPCODE)
 988     {
 989       if (extype)
 990         as_fatal("Unable to mix instructions as specified");
 991       if (prev_opcode)
 992         {
 993           write_1_short (prev_opcode, prev_insn, fixups->next);
 994           prev_opcode = NULL;
 995         }
 996       write_long (opcode, insn, fixups);
 997       prev_opcode = NULL;
 998       return;
 999     }
1000
1001   if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
1002     {
1003       /* no instructions saved */
1004       prev_opcode = NULL;
1005     }
1006   else
1007     {
1008       if (extype)
1009         as_fatal("Unable to mix instructions as specified");
1010       /* save off last instruction so it may be packed on next pass */
1011       prev_opcode = opcode;
1012       prev_insn = insn;
1013       prev_seg = now_seg;
1014       prev_subseg = now_subseg;
1015       fixups = fixups->next;
1016     }
1017 }
1018
1019
1020 /* do_assemble assembles a single instruction and returns an opcode */
1021 /* it returns -1 (an invalid opcode) on error */
1022
1023 static unsigned long
1024 do_assemble (str, opcode)
1025      char *str;
1026      struct d10v_opcode **opcode;
1027 {
1028   unsigned char *op_start, *save;
1029   unsigned char *op_end;
1030   char name[20];
1031   int nlen = 0;
1032   expressionS myops[6];
1033   unsigned long insn;
1034
1035   /* printf("do_assemble: str=%s\n",str); */
1036
1037   /* Drop leading whitespace */
1038   while (*str == ' ')
1039     str++;
1040
1041   /* find the opcode end */
1042   for (op_start = op_end = (unsigned char *) (str);
1043        *op_end
1044        && nlen < 20
1045        && !is_end_of_line[*op_end] && *op_end != ' ';
1046        op_end++)
1047     {
1048       name[nlen] = op_start[nlen];
1049       nlen++;
1050     }
1051   name[nlen] = 0;
1052
1053   if (nlen == 0)
1054     return (-1);
1055
1056   /* find the first opcode with the proper name */
1057   *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
1058   if (*opcode == NULL)
1059       as_fatal ("unknown opcode: %s",name);
1060
1061   save = input_line_pointer;
1062   input_line_pointer = op_end;
1063   *opcode = find_opcode (*opcode, myops);
1064   if (*opcode == 0)
1065     return -1;
1066   input_line_pointer = save;
1067
1068   insn = build_insn ((*opcode), myops, 0);
1069   /* printf("sub-insn = %lx\n",insn);  */
1070   return (insn);
1071 }
1072
1073 /* find_opcode() gets a pointer to an entry in the opcode table.       */
1074 /* It must look at all opcodes with the same name and use the operands */
1075 /* to choose the correct opcode. */
1076
1077 static struct d10v_opcode *
1078 find_opcode (opcode, myops)
1079      struct d10v_opcode *opcode;
1080      expressionS myops[];
1081 {
1082   int i, match, done, numops;
1083   struct d10v_opcode *next_opcode;
1084
1085   /* get all the operands and save them as expressions */
1086   numops = get_operands (myops);
1087
1088   /* now see if the operand is a fake.  If so, find the correct size */
1089   /* instruction, if possible */
1090   if (opcode->format == OPCODE_FAKE)
1091     {
1092       int opnum = opcode->operands[0];
1093
1094       if (myops[opnum].X_op == O_register)
1095         {
1096           myops[opnum].X_op = O_symbol;
1097           myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
1098           myops[opnum].X_add_number = 0;
1099           myops[opnum].X_op_symbol = NULL;
1100         }
1101
1102       if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol &&
1103           S_IS_DEFINED(myops[opnum].X_add_symbol) &&
1104           (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg)))
1105         {
1106           next_opcode=opcode+1;
1107           for (i=0; opcode->operands[i+1]; i++)
1108             {
1109               int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1110               int flags = d10v_operands[next_opcode->operands[opnum]].flags;
1111               if (flags & OPERAND_ADDR)
1112                 bits += 2;
1113               if (myops[opnum].X_op == O_constant)
1114                 {
1115                   if (!check_range (myops[opnum].X_add_number, bits, flags))
1116                     return next_opcode;
1117                 }
1118               else
1119                 {
1120                   fragS *f;
1121                   long value;
1122                   /* calculate the current address by running through the previous frags */
1123                   /* and adding our current offset */
1124                   for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next)
1125                     value += f->fr_fix;
1126
1127                   if (flags & OPERAND_ADDR)
1128                     value = S_GET_VALUE(myops[opnum].X_add_symbol) - value -
1129                       (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal);
1130                   else
1131                     value = S_GET_VALUE(myops[opnum].X_add_symbol);
1132
1133                   if (myops[opnum].X_add_number == AT_WORD)
1134                     {
1135                       if (bits > 4)
1136                         {
1137                           bits += 2;
1138                           if (!check_range (value, bits, flags))
1139                             return next_opcode;
1140                         }
1141                     }
1142                   else if (!check_range (value, bits, flags))
1143                     return next_opcode;
1144                 }
1145               next_opcode++;
1146             }
1147           as_fatal ("value out of range");
1148         }
1149       else
1150         {
1151           /* not a constant, so use a long instruction */
1152           return opcode+2;
1153         }
1154     }
1155   else
1156     {
1157       match = 0;
1158       /* now search the opcode table table for one with operands */
1159       /* that matches what we've got */
1160       while (!match)
1161         {
1162           match = 1;
1163           for (i = 0; opcode->operands[i]; i++)
1164             {
1165               int flags = d10v_operands[opcode->operands[i]].flags;
1166               int X_op = myops[i].X_op;
1167               int num = myops[i].X_add_number;
1168
1169               if (X_op==0)
1170                 {
1171                   match=0;
1172                   break;
1173                 }
1174
1175               if (flags & OPERAND_REG)
1176                 {
1177                   if ((X_op != O_register) ||
1178                       ((flags & OPERAND_ACC) != (num & OPERAND_ACC)) ||
1179                       ((flags & OPERAND_FLAG) != (num & OPERAND_FLAG)) ||
1180                       ((flags & OPERAND_CONTROL) != (num & OPERAND_CONTROL)))
1181                     {
1182                       match=0;
1183                       break;
1184                     }
1185                 }
1186
1187               if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1188                   ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1189                   ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1190                   ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1191                   ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
1192                 {
1193                   match=0;
1194                   break;
1195                 }
1196             }
1197           /* we're only done if the operands matched so far AND there
1198              are no more to check */
1199           if (match && myops[i].X_op==0)
1200             break;
1201           else
1202             match = 0;
1203
1204           next_opcode = opcode+1;
1205           if (next_opcode->opcode == 0)
1206             break;
1207           if (strcmp(next_opcode->name, opcode->name))
1208             break;
1209           opcode = next_opcode;
1210         }
1211     }
1212
1213   if (!match)
1214     {
1215       as_bad ("bad opcode or operands");
1216       return (0);
1217     }
1218
1219   /* Check that all registers that are required to be even are. */
1220   /* Also, if any operands were marked as registers, but were really symbols */
1221   /* fix that here. */
1222   for (i=0; opcode->operands[i]; i++)
1223     {
1224       if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1225           (myops[i].X_add_number & 1))
1226         as_fatal("Register number must be EVEN");
1227       if (myops[i].X_op == O_register)
1228         {
1229           if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1230             {
1231               myops[i].X_op = O_symbol;
1232               myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
1233               myops[i].X_add_number = 0;
1234               myops[i].X_op_symbol = NULL;
1235             }
1236         }
1237     }
1238   return opcode;
1239 }
1240
1241 /* if while processing a fixup, a reloc really needs to be created */
1242 /* then it is done here */
1243
1244 arelent *
1245 tc_gen_reloc (seg, fixp)
1246      asection *seg;
1247      fixS *fixp;
1248 {
1249   arelent *reloc;
1250   reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1251   reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1252   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1253   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1254   if (reloc->howto == (reloc_howto_type *) NULL)
1255     {
1256       as_bad_where (fixp->fx_file, fixp->fx_line,
1257                     "reloc %d not supported by object file format", (int)fixp->fx_r_type);
1258       return NULL;
1259     }
1260   reloc->addend = fixp->fx_addnumber;
1261   /* printf("tc_gen_reloc: addr=%x  addend=%x\n", reloc->address, reloc->addend); */
1262   return reloc;
1263 }
1264
1265 int
1266 md_estimate_size_before_relax (fragp, seg)
1267      fragS *fragp;
1268      asection *seg;
1269 {
1270   abort ();
1271   return 0;
1272 }
1273
1274 long
1275 md_pcrel_from_section (fixp, sec)
1276      fixS *fixp;
1277      segT sec;
1278 {
1279   if (fixp->fx_addsy != (symbolS *)NULL && !S_IS_DEFINED (fixp->fx_addsy))
1280     return 0;
1281   /* printf("pcrel_from_section: %x\n", fixp->fx_frag->fr_address + fixp->fx_where); */
1282   return fixp->fx_frag->fr_address + fixp->fx_where;
1283 }
1284
1285 int
1286 md_apply_fix3 (fixp, valuep, seg)
1287      fixS *fixp;
1288      valueT *valuep;
1289      segT seg;
1290 {
1291   char *where;
1292   unsigned long insn;
1293   long value;
1294   int op_type;
1295   int left=0;
1296
1297   if (fixp->fx_addsy == (symbolS *) NULL)
1298     {
1299       value = *valuep;
1300       fixp->fx_done = 1;
1301     }
1302   else if (fixp->fx_pcrel)
1303     value = *valuep;
1304   else
1305     {
1306       value = fixp->fx_offset;
1307       if (fixp->fx_subsy != (symbolS *) NULL)
1308         {
1309           if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
1310             value -= S_GET_VALUE (fixp->fx_subsy);
1311           else
1312             {
1313               /* We don't actually support subtracting a symbol.  */
1314               as_bad_where (fixp->fx_file, fixp->fx_line,
1315                             "expression too complex");
1316             }
1317         }
1318     }
1319
1320   /* printf("md_apply_fix: value=0x%x  type=0x%x  where=0x%x size=%d line=%d\n", value, fixp->fx_r_type,fixp->fx_where,fixp->fx_size, fixp->fx_line); */
1321
1322   op_type = fixp->fx_r_type;
1323   if (op_type & 2048)
1324     {
1325       op_type -= 2048;
1326       if (op_type & 1024)
1327         {
1328           op_type -= 1024;
1329           fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1330           left = 1;
1331         }
1332       else if (op_type & 4096)
1333         {
1334           op_type -= 4096;
1335           fixp->fx_r_type = BFD_RELOC_D10V_18;
1336         }
1337       else
1338         fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
1339     }
1340
1341   /* Fetch the instruction, insert the fully resolved operand
1342      value, and stuff the instruction back again.  */
1343   where = fixp->fx_frag->fr_literal + fixp->fx_where;
1344   insn = bfd_getb32 ((unsigned char *) where);
1345
1346   switch (fixp->fx_r_type)
1347     {
1348     case BFD_RELOC_D10V_10_PCREL_L:
1349     case BFD_RELOC_D10V_10_PCREL_R:
1350     case BFD_RELOC_D10V_18_PCREL:
1351     case BFD_RELOC_D10V_18:
1352       /* instruction addresses are always right-shifted by 2 */
1353       value >>= 2;
1354       if (fixp->fx_size == 2)
1355         bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1356       else
1357         {
1358           /* printf("   insn=%x  value=%x where=%x  pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */
1359           insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp);
1360           /* printf("   new insn=%x\n",insn); */
1361           bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1362         }
1363       break;
1364     case BFD_RELOC_32:
1365       bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1366       break;
1367     case BFD_RELOC_16:
1368       bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1369       break;
1370     default:
1371       as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type);
1372     }
1373   return 0;
1374 }
1375
1376
1377 /* d10v_cleanup() is called after the assembler has finished parsing the input
1378    file or after a label is defined.  Because the D10V assembler sometimes saves short
1379    instructions to see if it can package them with the next instruction, there may
1380    be a short instruction that still needs written.  */
1381 int
1382 d10v_cleanup (done)
1383      int done;
1384 {
1385   segT seg;
1386   subsegT subseg;
1387
1388   if ( prev_opcode && (done  || (now_seg == prev_seg) && (now_subseg == prev_subseg)))
1389     {
1390       seg = now_seg;
1391       subseg = now_subseg;
1392       subseg_set (prev_seg, prev_subseg);
1393       write_1_short (prev_opcode, prev_insn, fixups->next);
1394       subseg_set (seg, subseg);
1395       prev_opcode = NULL;
1396     }
1397   return 1;
1398 }
1399
1400 /* Like normal .word, except support @word */
1401 /* clobbers input_line_pointer, checks end-of-line. */
1402 static void
1403 d10v_dot_word (nbytes)
1404      register int nbytes;       /* 1=.byte, 2=.word, 4=.long */
1405 {
1406   expressionS exp;
1407   bfd_reloc_code_real_type reloc;
1408   char *p;
1409   int offset;
1410
1411   if (is_it_end_of_statement ())
1412     {
1413       demand_empty_rest_of_line ();
1414       return;
1415     }
1416
1417   do
1418     {
1419       expression (&exp);
1420       if (!strncasecmp (input_line_pointer, "@word", 5))
1421         {
1422           exp.X_add_number = 0;
1423           input_line_pointer += 5;
1424
1425           p = frag_more (2);
1426           fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1427                        &exp, 0, BFD_RELOC_D10V_18);
1428         }
1429       else
1430         emit_expr (&exp, 2);
1431     }
1432   while (*input_line_pointer++ == ',');
1433
1434   input_line_pointer--;         /* Put terminator back into stream. */
1435   demand_empty_rest_of_line ();
1436 }
1437
1438
1439 /* Mitsubishi asked that we support some old syntax that apparently */
1440 /* had immediate operands starting with '#'.  This is in some of their */
1441 /* sample code but is not documented (although it appears in some  */
1442 /* examples in their assembler manual). For now, we'll solve this */
1443 /* compatibility problem by simply ignoring any '#' at the beginning */
1444 /* of an operand. */
1445
1446 /* operands that begin with '#' should fall through to here */
1447 /* from expr.c */
1448
1449 void
1450 md_operand (expressionP)
1451      expressionS *expressionP;
1452 {
1453   if (*input_line_pointer == '#')
1454     {
1455       input_line_pointer++;
1456       expression (expressionP);
1457     }
1458 }
1459