1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/d10v.h"
30 const char comment_chars
[] = ";";
31 const char line_comment_chars
[] = "#";
32 const char line_separator_chars
[] = "";
33 const char *md_shortopts
= "O";
34 const char EXP_CHARS
[] = "eE";
35 const char FLT_CHARS
[] = "dD";
39 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
40 && (X)->X_op_symbol != NULL \
41 && symbol_constant_p ((X)->X_op_symbol) \
42 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
43 #define AT_WORD_RIGHT_SHIFT 2
46 #define MAX_INSN_FIXUPS (5)
53 bfd_reloc_code_real_type reloc
;
56 typedef struct _fixups
59 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
63 static Fixups FixUps
[2];
64 static Fixups
*fixups
;
66 static int do_not_ignore_hash
= 0;
68 typedef int packing_type
;
69 #define PACK_UNSPEC (0) /* Packing order not specified. */
70 #define PACK_PARALLEL (1) /* "||" */
71 #define PACK_LEFT_RIGHT (2) /* "->" */
72 #define PACK_RIGHT_LEFT (3) /* "<-" */
73 static packing_type etype
= PACK_UNSPEC
; /* Used by d10v_cleanup. */
75 /* True if instruction swapping warnings should be inhibited.
77 static boolean flag_warn_suppress_instructionswap
;
79 /* True if instruction packing should be performed when --gstabs is specified.
80 --gstabs-packing, --no-gstabs-packing. */
81 static boolean flag_allow_gstabs_packing
= 1;
83 /* Local functions. */
84 static int reg_name_search
PARAMS ((char *name
));
85 static int register_name
PARAMS ((expressionS
*expressionP
));
86 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
87 static int postfix
PARAMS ((char *p
));
88 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
89 static int get_operands
PARAMS ((expressionS exp
[]));
90 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
91 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
92 static void write_long
PARAMS ((unsigned long insn
, Fixups
*fx
));
93 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
94 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
95 struct d10v_opcode
*opcode2
, unsigned long insn2
, packing_type exec_type
, Fixups
*fx
));
96 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
97 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
98 offsetT value
, int left
, fixS
*fix
));
99 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
100 struct d10v_opcode
*opcode2
, unsigned long insn2
,
101 packing_type exec_type
));
102 static symbolS
* find_symbol_matching_register
PARAMS ((expressionS
*));
104 struct option md_longopts
[] =
106 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
107 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
108 #define OPTION_GSTABSPACKING (OPTION_MD_BASE + 1)
109 {"gstabspacking", no_argument
, NULL
, OPTION_GSTABSPACKING
},
110 {"gstabs-packing", no_argument
, NULL
, OPTION_GSTABSPACKING
},
111 #define OPTION_NOGSTABSPACKING (OPTION_MD_BASE + 2)
112 {"nogstabspacking", no_argument
, NULL
, OPTION_NOGSTABSPACKING
},
113 {"no-gstabs-packing", no_argument
, NULL
, OPTION_NOGSTABSPACKING
},
114 {NULL
, no_argument
, NULL
, 0}
117 size_t md_longopts_size
= sizeof (md_longopts
);
119 static void d10v_dot_word
PARAMS ((int));
121 /* The target specific pseudo-ops which we support. */
122 const pseudo_typeS md_pseudo_table
[] =
124 { "word", d10v_dot_word
, 2 },
128 /* Opcode hash table. */
129 static struct hash_control
*d10v_hash
;
131 /* Do a binary search of the d10v_predefined_registers array to see if
132 NAME is a valid regiter name. Return the register number from the
133 array on success, or -1 on failure. */
136 reg_name_search (name
)
139 int middle
, low
, high
;
143 high
= d10v_reg_name_cnt () - 1;
147 middle
= (low
+ high
) / 2;
148 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
154 return d10v_predefined_registers
[middle
].value
;
160 /* Check the string at input_line_pointer
161 to see if it is a valid register name. */
164 register_name (expressionP
)
165 expressionS
*expressionP
;
168 char c
, *p
= input_line_pointer
;
171 && *p
!= '\n' && *p
!= '\r' && *p
!= ',' && *p
!= ' ' && *p
!= ')')
178 /* Look to see if it's in the register table. */
179 reg_number
= reg_name_search (input_line_pointer
);
182 expressionP
->X_op
= O_register
;
183 /* Temporarily store a pointer to the string here. */
184 expressionP
->X_op_symbol
= (symbolS
*) input_line_pointer
;
185 expressionP
->X_add_number
= reg_number
;
186 input_line_pointer
= p
;
195 check_range (num
, bits
, flags
)
203 /* Don't bother checking 16-bit values. */
207 if (flags
& OPERAND_SHIFT
)
209 /* All special shift operands are unsigned and <= 16.
210 We allow 0 for now. */
217 if (flags
& OPERAND_SIGNED
)
219 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
220 if (flags
& RESTRICTED_NUM3
)
222 if ((long) num
< -2 || (long) num
> 3)
227 max
= (1 << (bits
- 1)) - 1;
228 min
= - (1 << (bits
- 1));
229 if (((long) num
> max
) || ((long) num
< min
))
235 max
= (1 << bits
) - 1;
237 if (((long) num
> max
) || ((long) num
< min
))
244 md_show_usage (stream
)
247 fprintf (stream
, _("D10V options:\n\
248 -O Optimize. Will do some operations in parallel.\n\
249 --gstabs-packing Pack adjacent short instructions together even\n\
250 when --gstabs is specified. On by default.\n\
251 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
252 instructions together.\n"));
256 md_parse_option (c
, arg
)
258 char *arg ATTRIBUTE_UNUSED
;
263 /* Optimize. Will attempt to parallelize operations. */
266 case OPTION_NOWARNSWAP
:
267 flag_warn_suppress_instructionswap
= 1;
269 case OPTION_GSTABSPACKING
:
270 flag_allow_gstabs_packing
= 1;
272 case OPTION_NOGSTABSPACKING
:
273 flag_allow_gstabs_packing
= 0;
282 md_undefined_symbol (name
)
283 char *name ATTRIBUTE_UNUSED
;
288 /* Turn a string in input_line_pointer into a floating point constant
289 of type TYPE, and store the appropriate bytes in *LITP. The number
290 of LITTLENUMS emitted is stored in *SIZEP. An error message is
291 returned, or NULL on OK. */
294 md_atof (type
, litP
, sizeP
)
300 LITTLENUM_TYPE words
[4];
314 return _("bad call to md_atof");
317 t
= atof_ieee (input_line_pointer
, type
, words
);
319 input_line_pointer
= t
;
323 for (i
= 0; i
< prec
; i
++)
325 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
332 md_convert_frag (abfd
, sec
, fragP
)
333 bfd
*abfd ATTRIBUTE_UNUSED
;
334 asection
*sec ATTRIBUTE_UNUSED
;
335 fragS
*fragP ATTRIBUTE_UNUSED
;
341 md_section_align (seg
, addr
)
345 int align
= bfd_get_section_alignment (stdoutput
, seg
);
346 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
352 char *prev_name
= "";
353 struct d10v_opcode
*opcode
;
354 d10v_hash
= hash_new ();
356 /* Insert unique names into hash table. The D10v instruction set
357 has many identical opcode names that have different opcodes based
358 on the operands. This hash table then provides a quick index to
359 the first opcode with a particular name in the opcode table. */
361 for (opcode
= (struct d10v_opcode
*) d10v_opcodes
; opcode
->name
; opcode
++)
363 if (strcmp (prev_name
, opcode
->name
))
365 prev_name
= (char *) opcode
->name
;
366 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
371 FixUps
[0].next
= &FixUps
[1];
372 FixUps
[1].next
= &FixUps
[0];
375 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
376 from an expression. */
382 while (*p
!= '-' && *p
!= '+')
384 if (*p
== 0 || *p
== '\n' || *p
== '\r')
403 static bfd_reloc_code_real_type
405 struct d10v_operand
*op
;
412 if (op
->flags
& OPERAND_ADDR
)
415 return (BFD_RELOC_D10V_10_PCREL_R
);
417 return (BFD_RELOC_D10V_18_PCREL
);
420 return (BFD_RELOC_16
);
423 /* Parse a string of operands. Return an array of expressions. */
429 char *p
= input_line_pointer
;
436 while (*p
== ' ' || *p
== '\t' || *p
== ',')
438 if (*p
== 0 || *p
== '\n' || *p
== '\r')
446 exp
[numops
].X_op
= O_absent
;
450 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
455 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
459 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
462 exp
[++numops
].X_add_number
= OPERAND_PLUS
;
473 /* Just skip the trailing paren. */
478 input_line_pointer
= p
;
480 /* Check to see if it might be a register name. */
481 if (!register_name (&exp
[numops
]))
483 /* Parse as an expression. */
486 /* Any expression that involves the indirect addressing
487 cannot also involve immediate addressing. Therefore
488 the use of the hash character is illegal. */
489 int save
= do_not_ignore_hash
;
490 do_not_ignore_hash
= 1;
492 expression (&exp
[numops
]);
494 do_not_ignore_hash
= save
;
497 expression (&exp
[numops
]);
500 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
502 input_line_pointer
+= 5;
503 if (exp
[numops
].X_op
== O_register
)
505 /* If it looked like a register name but was followed by
506 "@word" then it was really a symbol, so change it to
508 exp
[numops
].X_op
= O_symbol
;
509 exp
[numops
].X_add_symbol
=
510 symbol_find_or_make ((char *) exp
[numops
].X_op_symbol
);
513 /* Check for identifier@word+constant. */
514 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
517 expression (&new_exp
);
518 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
521 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
524 memset (&new_exp
, 0, sizeof new_exp
);
525 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
526 new_exp
.X_op
= O_constant
;
527 new_exp
.X_unsigned
= 1;
528 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
529 exp
[numops
].X_op
= O_right_shift
;
532 know (AT_WORD_P (&exp
[numops
]));
535 if (exp
[numops
].X_op
== O_illegal
)
536 as_bad (_("illegal operand"));
537 else if (exp
[numops
].X_op
== O_absent
)
538 as_bad (_("missing operand"));
541 p
= input_line_pointer
;
546 case -1: /* Postdecrement mode. */
547 exp
[numops
].X_op
= O_absent
;
548 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
550 case 1: /* Postincrement mode. */
551 exp
[numops
].X_op
= O_absent
;
552 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
556 exp
[numops
].X_op
= 0;
561 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
570 shift
= d10v_operands
[op_type
].shift
;
574 bits
= d10v_operands
[op_type
].bits
;
576 /* Truncate to the proper number of bits. */
577 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
578 as_bad_where (fix
->fx_file
, fix
->fx_line
,
579 _("operand out of range: %d"), value
);
581 value
&= 0x7FFFFFFF >> (31 - bits
);
582 insn
|= (value
<< shift
);
587 /* Take a pointer to the opcode entry in the opcode table and the
588 array of operand expressions. Return the instruction. */
591 build_insn (opcode
, opers
, insn
)
592 struct d10v_opcode
*opcode
;
596 int i
, bits
, shift
, flags
, format
;
597 unsigned long number
;
599 /* The insn argument is only used for the DIVS kludge. */
604 insn
= opcode
->opcode
;
605 format
= opcode
->format
;
608 for (i
= 0; opcode
->operands
[i
]; i
++)
610 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
611 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
612 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
613 number
= opers
[i
].X_add_number
;
615 if (flags
& OPERAND_REG
)
617 number
&= REGISTER_MASK
;
618 if (format
== LONG_L
)
622 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
624 /* Now create a fixup. */
626 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
627 as_fatal (_("too many fixups"));
629 if (AT_WORD_P (&opers
[i
]))
631 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
632 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
633 opers
[i
].X_op
= O_symbol
;
634 opers
[i
].X_op_symbol
= NULL
; /* Should free it. */
635 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
636 that, it is aligned with the symbol's value. Later,
637 BFD_RELOC_D10V_18 will right shift (symbol_value +
639 number
<<= AT_WORD_RIGHT_SHIFT
;
640 opers
[i
].X_add_number
= number
;
643 fixups
->fix
[fixups
->fc
].reloc
=
644 get_reloc ((struct d10v_operand
*) &d10v_operands
[opcode
->operands
[i
]]);
646 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
647 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
648 fixups
->fix
[fixups
->fc
].size
= 2;
650 fixups
->fix
[fixups
->fc
].size
= 4;
652 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
653 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
654 fixups
->fix
[fixups
->fc
].pcrel
=
655 (flags
& OPERAND_ADDR
) ? true : false;
659 /* Truncate to the proper number of bits. */
660 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
661 as_bad (_("operand out of range: %d"), number
);
662 number
&= 0x7FFFFFFF >> (31 - bits
);
663 insn
= insn
| (number
<< shift
);
666 /* kludge: for DIVS, we need to put the operands in twice */
667 /* on the second pass, format is changed to LONG_R to force
668 the second set of operands to not be shifted over 15. */
669 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
== LONG_L
))
670 insn
= build_insn (opcode
, opers
, insn
);
675 /* Write out a long form instruction. */
678 write_long (insn
, fx
)
683 char *f
= frag_more (4);
686 number_to_chars_bigendian (f
, insn
, 4);
688 for (i
= 0; i
< fx
->fc
; i
++)
690 if (fx
->fix
[i
].reloc
)
692 where
= f
- frag_now
->fr_literal
;
693 if (fx
->fix
[i
].size
== 2)
696 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
697 fx
->fix
[i
].operand
|= 4096;
699 fix_new_exp (frag_now
,
704 fx
->fix
[i
].operand
|2048);
710 /* Write out a short form instruction by itself. */
713 write_1_short (opcode
, insn
, fx
)
714 struct d10v_opcode
*opcode
;
718 char *f
= frag_more (4);
721 if (opcode
->exec_type
& PARONLY
)
722 as_fatal (_("Instruction must be executed in parallel with another instruction."));
724 /* The other container needs to be NOP. */
725 /* According to 4.3.1: for FM=00, sub-instructions performed only
726 by IU cannot be encoded in L-container. */
727 if (opcode
->unit
== IU
)
728 insn
|= FM00
| (NOP
<< 15); /* Right container. */
730 insn
= FM00
| (insn
<< 15) | NOP
; /* Left container. */
732 number_to_chars_bigendian (f
, insn
, 4);
733 for (i
= 0; i
< fx
->fc
; i
++)
735 if (fx
->fix
[i
].reloc
)
737 where
= f
- frag_now
->fr_literal
;
738 if (fx
->fix
[i
].size
== 2)
741 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
742 fx
->fix
[i
].operand
|= 4096;
744 /* If it's an R reloc, we may have to switch it to L. */
745 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
)
746 && (opcode
->unit
!= IU
))
747 fx
->fix
[i
].operand
|= 1024;
749 fix_new_exp (frag_now
,
754 fx
->fix
[i
].operand
|2048);
760 /* Expects two short instructions.
761 If possible, writes out both as a single packed instruction.
762 Otherwise, writes out the first one, packed with a NOP.
763 Returns number of instructions not written out. */
766 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
767 struct d10v_opcode
*opcode1
, *opcode2
;
768 unsigned long insn1
, insn2
;
769 packing_type exec_type
;
776 if ((exec_type
!= PACK_PARALLEL
)
777 && ((opcode1
->exec_type
& PARONLY
) || (opcode2
->exec_type
& PARONLY
)))
778 as_fatal (_("Instruction must be executed in parallel"));
780 if ((opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
781 as_fatal (_("Long instructions may not be combined."));
785 case PACK_UNSPEC
: /* Order not specified. */
786 if (opcode1
->exec_type
& ALONE
)
788 /* Case of a short branch on a separate GAS line.
790 write_1_short (opcode1
, insn1
, fx
->next
);
794 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
797 if (opcode1
->unit
== IU
)
798 insn
= FM00
| (insn2
<< 15) | insn1
;
799 else if (opcode2
->unit
== MU
)
800 insn
= FM00
| (insn2
<< 15) | insn1
;
803 insn
= FM00
| (insn1
<< 15) | insn2
;
804 /* Advance over dummy fixup since packed insn1 in L. */
808 else if (opcode1
->unit
== IU
)
809 /* Reverse sequential with IU opcode1 on right and done first. */
810 insn
= FM10
| (insn2
<< 15) | insn1
;
813 /* Sequential with non-IU opcode1 on left and done first. */
814 insn
= FM01
| (insn1
<< 15) | insn2
;
815 /* Advance over dummy fixup since packed insn1 in L. */
821 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
823 (_("One of these instructions may not be executed in parallel."));
824 if (opcode1
->unit
== IU
)
826 if (opcode2
->unit
== IU
)
827 as_fatal (_("Two IU instructions may not be executed in parallel"));
828 if (!flag_warn_suppress_instructionswap
)
829 as_warn (_("Swapping instruction order"));
830 insn
= FM00
| (insn2
<< 15) | insn1
;
832 else if (opcode2
->unit
== MU
)
834 if (opcode1
->unit
== MU
)
835 as_fatal (_("Two MU instructions may not be executed in parallel"));
836 if (!flag_warn_suppress_instructionswap
)
837 as_warn (_("Swapping instruction order"));
838 insn
= FM00
| (insn2
<< 15) | insn1
;
842 insn
= FM00
| (insn1
<< 15) | insn2
;
843 /* Advance over dummy fixup since packed insn1 in L. */
848 case PACK_LEFT_RIGHT
:
849 if (opcode1
->unit
!= IU
)
850 insn
= FM01
| (insn1
<< 15) | insn2
;
851 else if (opcode2
->unit
== MU
|| opcode2
->unit
== EITHER
)
853 if (!flag_warn_suppress_instructionswap
)
854 as_warn (_("Swapping instruction order"));
855 insn
= FM10
| (insn2
<< 15) | insn1
;
858 as_fatal (_("IU instruction may not be in the left container"));
859 if (opcode1
->exec_type
& ALONE
)
860 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
861 /* Advance over dummy fixup. */
865 case PACK_RIGHT_LEFT
:
866 if (opcode2
->unit
!= MU
)
867 insn
= FM10
| (insn1
<< 15) | insn2
;
868 else if (opcode1
->unit
== IU
|| opcode1
->unit
== EITHER
)
870 if (!flag_warn_suppress_instructionswap
)
871 as_warn (_("Swapping instruction order"));
872 insn
= FM01
| (insn2
<< 15) | insn1
;
875 as_fatal (_("MU instruction may not be in the right container"));
876 if (opcode2
->exec_type
& ALONE
)
877 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
878 /* Advance over dummy fixup. */
883 as_fatal (_("unknown execution type passed to write_2_short()"));
887 number_to_chars_bigendian (f
, insn
, 4);
889 /* Process fixup chains.
890 Note that the packing code above advanced fx conditionally.
891 dlindsay@cygnus.com: There's something subtle going on here involving
892 _dummy_first_bfd_reloc_code_real. This is related to the
893 difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether
894 a fixup is done in the L or R container. A bug in this code
895 can pass Plum Hall fine, yet still affect hand-written assembler. */
897 for (j
= 0; j
< 2; j
++)
899 for (i
= 0; i
< fx
->fc
; i
++)
901 if (fx
->fix
[i
].reloc
)
903 where
= f
- frag_now
->fr_literal
;
904 if (fx
->fix
[i
].size
== 2)
907 if ((fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0))
908 fx
->fix
[i
].operand
|= 1024;
910 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
911 fx
->fix
[i
].operand
|= 4096;
913 fix_new_exp (frag_now
,
918 fx
->fix
[i
].operand
|2048);
927 /* Check 2 instructions and determine if they can be safely
928 executed in parallel. Return 1 if they can be. */
931 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
932 struct d10v_opcode
*op1
, *op2
;
933 unsigned long insn1
, insn2
;
934 packing_type exec_type
;
936 int i
, j
, flags
, mask
, shift
, regno
;
937 unsigned long ins
, mod
[2], used
[2];
938 struct d10v_opcode
*op
;
940 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
941 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
942 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
943 || (op1
->unit
== IU
&& op2
->unit
== IU
)
944 || (op1
->unit
== MU
&& op2
->unit
== MU
))
947 /* If this is auto parallization, and either instruction is a branch,
949 if (exec_type
== PACK_UNSPEC
950 && (op1
->exec_type
& ALONE
|| op2
->exec_type
& ALONE
))
953 /* The idea here is to create two sets of bitmasks (mod and used)
954 which indicate which registers are modified or used by each
955 instruction. The operation can only be done in parallel if
956 instruction 1 and instruction 2 modify different registers, and
957 the first instruction does not modify registers that the second
958 is using (The second instruction can modify registers that the
959 first is using as they are only written back after the first
960 instruction has completed). Accesses to control registers, PSW,
961 and memory are treated as accesses to a single register. So if
962 both instructions write memory or if the first instruction writes
963 memory and the second reads, then they cannot be done in
964 parallel. Likewise, if the first instruction mucks with the psw
965 and the second reads the PSW (which includes C, F0, and F1), then
966 they cannot operate safely in parallel. */
968 /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
971 /* cr (not psw) 18 */
975 for (j
= 0; j
< 2; j
++)
987 mod
[j
] = used
[j
] = 0;
988 if (op
->exec_type
& BRANCH_LINK
)
991 for (i
= 0; op
->operands
[i
]; i
++)
993 flags
= d10v_operands
[op
->operands
[i
]].flags
;
994 shift
= d10v_operands
[op
->operands
[i
]].shift
;
995 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
996 if (flags
& OPERAND_REG
)
998 regno
= (ins
>> shift
) & mask
;
999 if (flags
& (OPERAND_ACC0
| OPERAND_ACC1
))
1001 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc. */
1008 else if (flags
& (OPERAND_FFLAG
| OPERAND_CFLAG
))
1011 if (flags
& OPERAND_DEST
)
1013 mod
[j
] |= 1 << regno
;
1014 if (flags
& OPERAND_EVEN
)
1015 mod
[j
] |= 1 << (regno
+ 1);
1019 used
[j
] |= 1 << regno
;
1020 if (flags
& OPERAND_EVEN
)
1021 used
[j
] |= 1 << (regno
+ 1);
1023 /* Auto inc/dec also modifies the register. */
1024 if (op
->operands
[i
+ 1] != 0
1025 && (d10v_operands
[op
->operands
[i
+ 1]].flags
1026 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
1027 mod
[j
] |= 1 << regno
;
1030 else if (flags
& OPERAND_ATMINUS
)
1032 /* SP implicitly used/modified. */
1037 if (op
->exec_type
& RMEM
)
1039 else if (op
->exec_type
& WMEM
)
1041 else if (op
->exec_type
& RF0
)
1043 else if (op
->exec_type
& WF0
)
1045 else if (op
->exec_type
& WCAR
)
1048 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
1053 /* This is the main entry point for the machine-dependent assembler.
1054 STR points to a machine-dependent instruction. This function is
1055 supposed to emit the frags/bytes it assembles to. For the D10V, it
1056 mostly handles the special VLIW parsing and packing and leaves the
1057 difficult stuff to do_assemble(). */
1059 static unsigned long prev_insn
;
1060 static struct d10v_opcode
*prev_opcode
= 0;
1061 static subsegT prev_subseg
;
1062 static segT prev_seg
= 0;;
1068 /* etype is saved extype. For multi-line instructions. */
1070 packing_type extype
= PACK_UNSPEC
; /* Parallel, etc. */
1072 struct d10v_opcode
*opcode
;
1076 if (etype
== PACK_UNSPEC
)
1078 /* Look for the special multiple instruction separators. */
1079 str2
= strstr (str
, "||");
1081 extype
= PACK_PARALLEL
;
1084 str2
= strstr (str
, "->");
1086 extype
= PACK_LEFT_RIGHT
;
1089 str2
= strstr (str
, "<-");
1091 extype
= PACK_RIGHT_LEFT
;
1094 /* STR2 points to the separator, if there is one. */
1099 /* If two instructions are present and we already have one saved,
1100 then first write out the saved one. */
1103 /* Assemble first instruction and save it. */
1104 prev_insn
= do_assemble (str
, &prev_opcode
);
1106 prev_subseg
= now_subseg
;
1107 if (prev_insn
== (unsigned long) -1)
1108 as_fatal (_("can't find opcode "));
1109 fixups
= fixups
->next
;
1114 insn
= do_assemble (str
, &opcode
);
1115 if (insn
== (unsigned long) -1)
1117 if (extype
!= PACK_UNSPEC
)
1122 as_fatal (_("can't find opcode "));
1125 if (etype
!= PACK_UNSPEC
)
1128 etype
= PACK_UNSPEC
;
1131 /* If this is a long instruction, write it and any previous short
1133 if (opcode
->format
& LONG_OPCODE
)
1135 if (extype
!= PACK_UNSPEC
)
1136 as_fatal (_("Unable to mix instructions as specified"));
1138 write_long (insn
, fixups
);
1145 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1149 && (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1151 /* No instructions saved. */
1156 if (extype
!= PACK_UNSPEC
)
1157 as_fatal (_("Unable to mix instructions as specified"));
1158 /* Save last instruction so it may be packed on next pass. */
1159 prev_opcode
= opcode
;
1162 prev_subseg
= now_subseg
;
1163 fixups
= fixups
->next
;
1167 /* Assemble a single instruction.
1168 Return an opcode, or -1 (an invalid opcode) on error. */
1170 static unsigned long
1171 do_assemble (str
, opcode
)
1173 struct d10v_opcode
**opcode
;
1175 unsigned char *op_start
, *save
;
1176 unsigned char *op_end
;
1179 expressionS myops
[6];
1182 /* Drop leading whitespace. */
1186 /* Find the opcode end. */
1187 for (op_start
= op_end
= (unsigned char *) (str
);
1190 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1193 name
[nlen
] = TOLOWER (op_start
[nlen
]);
1201 /* Find the first opcode with the proper name. */
1202 *opcode
= (struct d10v_opcode
*) hash_find (d10v_hash
, name
);
1203 if (*opcode
== NULL
)
1204 as_fatal (_("unknown opcode: %s"), name
);
1206 save
= input_line_pointer
;
1207 input_line_pointer
= op_end
;
1208 *opcode
= find_opcode (*opcode
, myops
);
1211 input_line_pointer
= save
;
1213 insn
= build_insn ((*opcode
), myops
, 0);
1217 /* Find the symbol which has the same name as the register in EXP. */
1220 find_symbol_matching_register (exp
)
1225 if (exp
->X_op
!= O_register
)
1228 /* Find the name of the register. */
1229 for (i
= d10v_reg_name_cnt (); i
--;)
1230 if (d10v_predefined_registers
[i
].value
== exp
->X_add_number
)
1236 /* Now see if a symbol has been defined with the same name. */
1237 return symbol_find (d10v_predefined_registers
[i
].name
);
1240 /* Get a pointer to an entry in the opcode table.
1241 The function must look at all opcodes with the same name and use
1242 the operands to choose the correct opcode. */
1244 static struct d10v_opcode
*
1245 find_opcode (opcode
, myops
)
1246 struct d10v_opcode
*opcode
;
1247 expressionS myops
[];
1250 struct d10v_opcode
*next_opcode
;
1252 /* Get all the operands and save them as expressions. */
1253 get_operands (myops
);
1255 /* Now see if the operand is a fake. If so, find the correct size
1256 instruction, if possible. */
1257 if (opcode
->format
== OPCODE_FAKE
)
1259 int opnum
= opcode
->operands
[0];
1262 if (myops
[opnum
].X_op
== O_register
)
1264 myops
[opnum
].X_op
= O_symbol
;
1265 myops
[opnum
].X_add_symbol
=
1266 symbol_find_or_make ((char *) myops
[opnum
].X_op_symbol
);
1267 myops
[opnum
].X_add_number
= 0;
1268 myops
[opnum
].X_op_symbol
= NULL
;
1271 next_opcode
= opcode
+ 1;
1273 /* If the first operand is supposed to be a register, make sure
1274 we got a valid one. */
1275 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1276 if (flags
& OPERAND_REG
)
1278 int X_op
= myops
[0].X_op
;
1279 int num
= myops
[0].X_add_number
;
1281 if (X_op
!= O_register
1283 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1284 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
))
1285 || ((flags
& OPERAND_SP
) && ! (num
& OPERAND_SP
)))
1287 as_bad (_("bad opcode or operands"));
1292 if (myops
[opnum
].X_op
== O_constant
1293 || (myops
[opnum
].X_op
== O_symbol
1294 && S_IS_DEFINED (myops
[opnum
].X_add_symbol
)
1295 && (S_GET_SEGMENT (myops
[opnum
].X_add_symbol
) == now_seg
)))
1297 for (i
= 0; opcode
->operands
[i
+ 1]; i
++)
1299 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1300 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1301 if (flags
& OPERAND_ADDR
)
1304 if (myops
[opnum
].X_op
== O_constant
)
1306 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1313 unsigned long current_position
;
1314 unsigned long symbol_position
;
1315 unsigned long value
;
1316 boolean found_symbol
;
1318 /* Calculate the address of the current instruction
1319 and the address of the symbol. Do this by summing
1320 the offsets of previous frags until we reach the
1321 frag containing the symbol, and the current frag. */
1322 sym_frag
= symbol_get_frag (myops
[opnum
].X_add_symbol
);
1323 found_symbol
= false;
1326 obstack_next_free (&frchain_now
->frch_obstack
)
1327 - frag_now
->fr_literal
;
1328 symbol_position
= S_GET_VALUE (myops
[opnum
].X_add_symbol
);
1330 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1332 current_position
+= f
->fr_fix
+ f
->fr_offset
;
1335 found_symbol
= true;
1338 symbol_position
+= f
->fr_fix
+ f
->fr_offset
;
1341 value
= symbol_position
;
1343 if (flags
& OPERAND_ADDR
)
1344 value
-= current_position
;
1346 if (AT_WORD_P (&myops
[opnum
]))
1351 if (!check_range (value
, bits
, flags
))
1355 else if (!check_range (value
, bits
, flags
))
1360 as_fatal (_("value out of range"));
1364 /* Not a constant, so use a long instruction. */
1371 /* Now search the opcode table table for one with operands
1372 that matches what we've got. */
1376 for (i
= 0; opcode
->operands
[i
]; i
++)
1378 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1379 int X_op
= myops
[i
].X_op
;
1380 int num
= myops
[i
].X_add_number
;
1388 if (flags
& OPERAND_REG
)
1390 if ((X_op
!= O_register
)
1392 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1393 | OPERAND_FFLAG
| OPERAND_CFLAG
1395 || ((flags
& OPERAND_SP
) && ! (num
& OPERAND_SP
)))
1402 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1403 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1404 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1405 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1406 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || ((num
!= OPERAND_ATSIGN
) && (num
!= OPERAND_ATPAR
)))))
1412 /* Unfortunatly, for the indirect operand in
1413 instructions such as ``ldb r1, @(c,r14)'' this
1414 function can be passed X_op == O_register (because
1415 'c' is a valid register name). However we cannot
1416 just ignore the case when X_op == O_register but
1417 flags & OPERAND_REG is null, so we check to see if a
1418 symbol of the same name as the register exists. If
1419 the symbol does exist, then the parser was unable to
1420 distinguish the two cases and we fix things here.
1423 if (!(flags
& OPERAND_REG
) && (X_op
== O_register
))
1425 symbolS
*sym
= find_symbol_matching_register (&myops
[i
]);
1429 myops
[i
].X_op
= X_op
= O_symbol
;
1430 myops
[i
].X_add_symbol
= sym
;
1434 (_("illegal operand - register name found where none expected"));
1438 /* We're only done if the operands matched so far AND there
1439 are no more to check. */
1440 if (match
&& myops
[i
].X_op
== 0)
1445 next_opcode
= opcode
+ 1;
1447 if (next_opcode
->opcode
== 0)
1450 if (strcmp (next_opcode
->name
, opcode
->name
))
1453 opcode
= next_opcode
;
1459 as_bad (_("bad opcode or operands"));
1463 /* Check that all registers that are required to be even are.
1464 Also, if any operands were marked as registers, but were really symbols,
1466 for (i
= 0; opcode
->operands
[i
]; i
++)
1468 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1469 (myops
[i
].X_add_number
& 1))
1470 as_fatal (_("Register number must be EVEN"));
1471 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_NOSP
)
1472 && (myops
[i
].X_add_number
& OPERAND_SP
))
1473 as_bad (_("Unsupported use of sp"));
1474 if (myops
[i
].X_op
== O_register
)
1476 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1478 myops
[i
].X_op
= O_symbol
;
1479 myops
[i
].X_add_symbol
=
1480 symbol_find_or_make ((char *) myops
[i
].X_op_symbol
);
1481 myops
[i
].X_add_number
= 0;
1482 myops
[i
].X_op_symbol
= NULL
;
1489 /* If while processing a fixup, a reloc really needs to be created.
1490 Then it is done here. */
1493 tc_gen_reloc (seg
, fixp
)
1494 asection
*seg ATTRIBUTE_UNUSED
;
1498 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1499 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1500 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1501 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1502 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1503 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1505 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1506 _("reloc %d not supported by object file format"),
1507 (int) fixp
->fx_r_type
);
1511 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1512 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1513 reloc
->address
= fixp
->fx_offset
;
1515 reloc
->addend
= fixp
->fx_addnumber
;
1521 md_estimate_size_before_relax (fragp
, seg
)
1522 fragS
*fragp ATTRIBUTE_UNUSED
;
1523 asection
*seg ATTRIBUTE_UNUSED
;
1530 md_pcrel_from_section (fixp
, sec
)
1534 if (fixp
->fx_addsy
!= (symbolS
*) NULL
1535 && (!S_IS_DEFINED (fixp
->fx_addsy
)
1536 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1538 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1542 md_apply_fix3 (fixP
, valP
, seg
)
1545 segT seg ATTRIBUTE_UNUSED
;
1549 long value
= * (long *) valP
;
1553 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
1556 else if (fixP
->fx_pcrel
)
1561 value
= fixP
->fx_offset
;
1563 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
1565 if (S_GET_SEGMENT (fixP
->fx_subsy
) == absolute_section
)
1566 value
-= S_GET_VALUE (fixP
->fx_subsy
);
1569 /* We don't actually support subtracting a symbol. */
1570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1571 _("expression too complex"));
1576 op_type
= fixP
->fx_r_type
;
1583 fixP
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1586 else if (op_type
& 4096)
1589 fixP
->fx_r_type
= BFD_RELOC_D10V_18
;
1593 get_reloc ((struct d10v_operand
*) &d10v_operands
[op_type
]);
1596 /* Fetch the instruction, insert the fully resolved operand
1597 value, and stuff the instruction back again. */
1598 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
1599 insn
= bfd_getb32 ((unsigned char *) where
);
1601 switch (fixP
->fx_r_type
)
1603 case BFD_RELOC_D10V_10_PCREL_L
:
1604 case BFD_RELOC_D10V_10_PCREL_R
:
1605 case BFD_RELOC_D10V_18_PCREL
:
1606 case BFD_RELOC_D10V_18
:
1607 /* Instruction addresses are always right-shifted by 2. */
1608 value
>>= AT_WORD_RIGHT_SHIFT
;
1609 if (fixP
->fx_size
== 2)
1610 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1613 struct d10v_opcode
*rep
, *repi
;
1615 rep
= (struct d10v_opcode
*) hash_find (d10v_hash
, "rep");
1616 repi
= (struct d10v_opcode
*) hash_find (d10v_hash
, "repi");
1617 if ((insn
& FM11
) == FM11
1618 && ( (repi
!= NULL
&& (insn
& repi
->mask
) == (unsigned) repi
->opcode
)
1619 || (rep
!= NULL
&& (insn
& rep
->mask
) == (unsigned) rep
->opcode
))
1622 (_("line %d: rep or repi must include at least 4 instructions"),
1625 d10v_insert_operand (insn
, op_type
, (offsetT
) value
, left
, fixP
);
1626 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1630 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1633 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1636 case BFD_RELOC_VTABLE_INHERIT
:
1637 case BFD_RELOC_VTABLE_ENTRY
:
1642 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1643 fixP
->fx_line
, fixP
->fx_r_type
);
1647 /* d10v_cleanup() is called after the assembler has finished parsing
1648 the input file, when a label is read from the input file, or when a
1649 stab directive is output. Because the D10V assembler sometimes
1650 saves short instructions to see if it can package them with the
1651 next instruction, there may be a short instruction that still needs
1654 NOTE: accesses a global, etype.
1655 NOTE: invoked by various macros such as md_cleanup: see. */
1663 /* If cleanup was invoked because the assembler encountered, e.g., a
1664 user label, we write out the pending instruction, if any. If it
1665 was invoked because the assembler is outputting a piece of line
1666 debugging information, though, we write out the pending
1667 instruction only if the --no-gstabs-packing command line switch
1668 has been specified. */
1670 && etype
== PACK_UNSPEC
1671 && (! outputting_stabs_line_debug
|| ! flag_allow_gstabs_packing
))
1674 subseg
= now_subseg
;
1677 subseg_set (prev_seg
, prev_subseg
);
1679 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1681 subseg_set (seg
, subseg
);
1687 /* Like normal .word, except support @word. */
1688 /* Clobbers input_line_pointer, checks end-of-line. */
1691 d10v_dot_word (dummy
)
1692 int dummy ATTRIBUTE_UNUSED
;
1697 if (is_it_end_of_statement ())
1699 demand_empty_rest_of_line ();
1706 if (!strncasecmp (input_line_pointer
, "@word", 5))
1708 exp
.X_add_number
= 0;
1709 input_line_pointer
+= 5;
1712 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1713 &exp
, 0, BFD_RELOC_D10V_18
);
1716 emit_expr (&exp
, 2);
1718 while (*input_line_pointer
++ == ',');
1720 input_line_pointer
--; /* Put terminator back into stream. */
1721 demand_empty_rest_of_line ();
1724 /* Mitsubishi asked that we support some old syntax that apparently
1725 had immediate operands starting with '#'. This is in some of their
1726 sample code but is not documented (although it appears in some
1727 examples in their assembler manual). For now, we'll solve this
1728 compatibility problem by simply ignoring any '#' at the beginning
1731 /* Operands that begin with '#' should fall through to here. */
1735 md_operand (expressionP
)
1736 expressionS
*expressionP
;
1738 if (*input_line_pointer
== '#' && ! do_not_ignore_hash
)
1740 input_line_pointer
++;
1741 expression (expressionP
);
1746 d10v_fix_adjustable (fixP
)
1749 if (fixP
->fx_addsy
== NULL
)
1752 /* Prevent all adjustments to global symbols. */
1753 if (S_IS_EXTERN (fixP
->fx_addsy
))
1755 if (S_IS_WEAK (fixP
->fx_addsy
))
1758 /* We need the symbol name for the VTABLE entries. */
1759 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1760 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1767 d10v_force_relocation (fixp
)
1770 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1771 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)