gas/config/tc-d10v.c

   1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
   2
   3    Copyright (C) 1996 Free Software Foundation.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include <ctype.h>
  24 #include "as.h"
  25 #include "subsegs.h"
  26 #include "opcode/d10v.h"
  27 #include "elf/ppc.h"
  28
  29 const char comment_chars[] = "#;";
  30 const char line_comment_chars[] = "#";
  31 const char line_separator_chars[] = "";
  32 const char *md_shortopts = "O";
  33 const char EXP_CHARS[] = "eE";
  34 const char FLT_CHARS[] = "dD";
  35
  36 int Optimizing = 0;
  37
  38 /* fixups */
  39 #define MAX_INSN_FIXUPS (5)
  40 struct d10v_fixup
  41 {
  42   expressionS exp;
  43   int operand;
  44   int pcrel;
  45 };
  46
  47 typedef struct _fixups
  48 {
  49   int fc;
  50   struct d10v_fixup fix[MAX_INSN_FIXUPS];
  51   struct _fixups *next;
  52 } Fixups;
  53
  54 static Fixups FixUps[2];
  55 static Fixups *fixups;
  56
  57 /* local functions */
  58 static int reg_name_search PARAMS ((char *name));
  59 static int register_name PARAMS ((expressionS *expressionP));
  60 static int check_range PARAMS ((unsigned long num, int bits, int flags));
  61 static int postfix PARAMS ((char *p));
  62 static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
  63 static int get_operands PARAMS ((expressionS exp[]));
  64 static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
  65 static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
  66 static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
  67 static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
  68 static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
  69                                   struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx));
  70 static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
  71 static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
  72                                                    offsetT value, int left));
  73 static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
  74                                   struct d10v_opcode *opcode2, unsigned long insn2));
  75
  76
  77 struct option md_longopts[] = {
  78   {NULL, no_argument, NULL, 0}
  79 };
  80 size_t md_longopts_size = sizeof(md_longopts);
  81
  82 /* The target specific pseudo-ops which we support.  */
  83 const pseudo_typeS md_pseudo_table[] =
  84 {
  85   { NULL,       NULL,           0 }
  86 };
  87
  88 /* Opcode hash table.  */
  89 static struct hash_control *d10v_hash;
  90
  91 /* reg_name_search does a binary search of the pre_defined_registers
  92    array to see if "name" is a valid regiter name.  Returns the register
  93    number from the array on success, or -1 on failure. */
  94
  95 static int
  96 reg_name_search (name)
  97      char *name;
  98 {
  99   int middle, low, high;
 100   int cmp;
 101
 102   low = 0;
 103   high = reg_name_cnt() - 1;
 104
 105   do
 106     {
 107       middle = (low + high) / 2;
 108       cmp = strcasecmp (name, pre_defined_registers[middle].name);
 109       if (cmp < 0)
 110         high = middle - 1;
 111       else if (cmp > 0)
 112         low = middle + 1;
 113       else
 114           return pre_defined_registers[middle].value;
 115     }
 116   while (low <= high);
 117   return -1;
 118 }
 119
 120 /* register_name() checks the string at input_line_pointer
 121    to see if it is a valid register name */
 122
 123 static int
 124 register_name (expressionP)
 125      expressionS *expressionP;
 126 {
 127   int reg_number;
 128   char c, *p = input_line_pointer;
 129
 130   while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
 131     p++;
 132
 133   c = *p;
 134   if (c)
 135     *p++ = 0;
 136
 137   /* look to see if it's in the register table */
 138   reg_number = reg_name_search (input_line_pointer);
 139   if (reg_number >= 0)
 140     {
 141       expressionP->X_op = O_register;
 142       /* temporarily store a pointer to the string here */
 143       expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
 144       expressionP->X_add_number = reg_number;
 145       input_line_pointer = p;
 146       return 1;
 147     }
 148   if (c)
 149     *(p-1) = c;
 150   return 0;
 151 }
 152
 153
 154 static int
 155 check_range (num, bits, flags)
 156      unsigned long num;
 157      int bits;
 158      int flags;
 159 {
 160   long min, max, bit1;
 161   int retval=0;
 162
 163   /* don't bother checking 16-bit values */
 164   if (bits == 16)
 165     return 0;
 166
 167   if (flags & OPERAND_SHIFT)
 168     {
 169       /* all special shift operands are unsigned */
 170       /* and <= 16.  We allow 0 for now. */
 171       if (num>16)
 172         return 1;
 173       else
 174         return 0;
 175     }
 176
 177   if (flags & OPERAND_SIGNED)
 178     {
 179       max = (1 << (bits - 1))-1;
 180       min = - (1 << (bits - 1));
 181       if (((long)num > max) || ((long)num < min))
 182         retval = 1;
 183     }
 184   else
 185     {
 186       max = (1 << bits) - 1;
 187       min = 0;
 188       if ((num > max) || (num < min))
 189         retval = 1;
 190     }
 191   return retval;
 192 }
 193
 194
 195 void
 196 md_show_usage (stream)
 197   FILE *stream;
 198 {
 199   fprintf(stream, "D10V options:\n\
 200 -O                      optimize.  Will do some operations in parallel.\n");
 201 }
 202
 203 int
 204 md_parse_option (c, arg)
 205      int c;
 206      char *arg;
 207 {
 208   switch (c)
 209     {
 210     case 'O':
 211       /* Optimize. Will attempt to parallelize operations */
 212       Optimizing = 1;
 213       break;
 214     default:
 215       return 0;
 216     }
 217   return 1;
 218 }
 219
 220 symbolS *
 221 md_undefined_symbol (name)
 222   char *name;
 223 {
 224   return 0;
 225 }
 226
 227 /* Turn a string in input_line_pointer into a floating point constant of type
 228    type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
 229    emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
 230  */
 231 char *
 232 md_atof (type, litP, sizeP)
 233      int type;
 234      char *litP;
 235      int *sizeP;
 236 {
 237   int prec;
 238   LITTLENUM_TYPE words[4];
 239   char *t;
 240   int i;
 241
 242   switch (type)
 243     {
 244     case 'f':
 245       prec = 2;
 246       break;
 247     case 'd':
 248       prec = 4;
 249       break;
 250     default:
 251       *sizeP = 0;
 252       return "bad call to md_atof";
 253     }
 254
 255   t = atof_ieee (input_line_pointer, type, words);
 256   if (t)
 257     input_line_pointer = t;
 258
 259   *sizeP = prec * 2;
 260
 261   for (i = 0; i < prec; i++)
 262     {
 263       md_number_to_chars (litP, (valueT) words[i], 2);
 264           litP += 2;
 265     }
 266   return NULL;
 267 }
 268
 269 void
 270 md_convert_frag (abfd, sec, fragP)
 271   bfd *abfd;
 272   asection *sec;
 273   fragS *fragP;
 274 {
 275   printf ("call to md_convert_frag \n");
 276   abort ();
 277 }
 278
 279 valueT
 280 md_section_align (seg, addr)
 281      asection *seg;
 282      valueT addr;
 283 {
 284   int align = bfd_get_section_alignment (stdoutput, seg);
 285   return ((addr + (1 << align) - 1) & (-1 << align));
 286 }
 287
 288
 289 void
 290 md_begin ()
 291 {
 292   char *prev_name = "";
 293   struct d10v_opcode *opcode;
 294   d10v_hash = hash_new();
 295
 296   /* Insert unique names into hash table.  The D10v instruction set
 297      has many identical opcode names that have different opcodes based
 298      on the operands.  This hash table then provides a quick index to
 299      the first opcode with a particular name in the opcode table.  */
 300
 301   for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
 302     {
 303       if (strcmp (prev_name, opcode->name))
 304         {
 305           prev_name = (char *)opcode->name;
 306           hash_insert (d10v_hash, opcode->name, (char *) opcode);
 307         }
 308     }
 309
 310   fixups = &FixUps[0];
 311   FixUps[0].next = &FixUps[1];
 312   FixUps[1].next = &FixUps[0];
 313 }
 314
 315
 316 /* this function removes the postincrement or postdecrement
 317    operator ( '+' or '-' ) from an expression */
 318
 319 static int postfix (p)
 320      char *p;
 321 {
 322   while (*p != '-' && *p != '+')
 323     {
 324       if (*p==0 || *p=='\n' || *p=='\r')
 325         break;
 326       p++;
 327     }
 328
 329   if (*p == '-')
 330     {
 331       *p = ' ';
 332       return (-1);
 333     }
 334   if (*p == '+')
 335     {
 336       *p = ' ';
 337       return (1);
 338     }
 339
 340   return (0);
 341 }
 342
 343
 344 static bfd_reloc_code_real_type
 345 get_reloc (op)
 346      struct d10v_operand *op;
 347 {
 348   int bits = op->bits;
 349
 350   /*  printf("get_reloc:  bits=%d  address=%d\n",bits,op->flags & OPERAND_ADDR);   */
 351   if (bits <= 4)
 352     return (0);
 353
 354   if (op->flags & OPERAND_ADDR)
 355     {
 356       if (bits == 8)
 357         return (BFD_RELOC_D10V_10_PCREL_R);
 358       else
 359         return (BFD_RELOC_D10V_18_PCREL);
 360     }
 361
 362   return (BFD_RELOC_16);
 363 }
 364
 365 /* get_operands parses a string of operands and returns
 366    an array of expressions */
 367
 368 static int
 369 get_operands (exp)
 370      expressionS exp[];
 371 {
 372   char *p = input_line_pointer;
 373   int numops = 0;
 374   int post = 0;
 375
 376   while (*p)
 377     {
 378       while (*p == ' ' || *p == '\t' || *p == ',')
 379         p++;
 380       if (*p==0 || *p=='\n' || *p=='\r')
 381         break;
 382
 383       if (*p == '@')
 384         {
 385           p++;
 386           exp[numops].X_op = O_absent;
 387           if (*p == '(')
 388             {
 389               p++;
 390               exp[numops].X_add_number = OPERAND_ATPAR;
 391             }
 392           else if (*p == '-')
 393             {
 394               p++;
 395               exp[numops].X_add_number = OPERAND_ATMINUS;
 396             }
 397           else
 398             {
 399               exp[numops].X_add_number = OPERAND_ATSIGN;
 400               post = postfix (p);
 401             }
 402           numops++;
 403           continue;
 404         }
 405
 406       if (*p == ')')
 407         {
 408           /* just skip the trailing paren */
 409           p++;
 410           continue;
 411         }
 412
 413       input_line_pointer = p;
 414
 415
 416       /* check to see if it might be a register name */
 417       if (!register_name (&exp[numops]))
 418         {
 419           /* parse as an expression */
 420           expression (&exp[numops]);
 421         }
 422
 423       if (exp[numops].X_op == O_illegal)
 424         as_bad ("illegal operand");
 425       else if (exp[numops].X_op == O_absent)
 426         as_bad ("missing operand");
 427
 428       numops++;
 429       p = input_line_pointer;
 430     }
 431
 432   switch (post)
 433     {
 434     case -1:    /* postdecrement mode */
 435       exp[numops].X_op = O_absent;
 436       exp[numops++].X_add_number = OPERAND_MINUS;
 437       break;
 438     case 1:     /* postincrement mode */
 439       exp[numops].X_op = O_absent;
 440       exp[numops++].X_add_number = OPERAND_PLUS;
 441       break;
 442     }
 443
 444   exp[numops].X_op = 0;
 445   return (numops);
 446 }
 447
 448 static unsigned long
 449 d10v_insert_operand (insn, op_type, value, left)
 450      unsigned long insn;
 451      int op_type;
 452      offsetT value;
 453      int left;
 454 {
 455   int shift, bits;
 456
 457   shift = d10v_operands[op_type].shift;
 458   if (left)
 459     shift += 15;
 460
 461   bits = d10v_operands[op_type].bits;
 462
 463   /* truncate to the proper number of bits */
 464   if (check_range (value, bits, d10v_operands[op_type].flags))
 465     as_bad("operand out of range: %d",value);
 466
 467   value &= 0x7FFFFFFF >> (31 - bits);
 468   insn |= (value << shift);
 469
 470   return insn;
 471 }
 472
 473
 474 /* build_insn takes a pointer to the opcode entry in the opcode table
 475    and the array of operand expressions and returns the instruction */
 476
 477 static unsigned long
 478 build_insn (opcode, opers, insn)
 479      struct d10v_opcode *opcode;
 480      expressionS *opers;
 481      unsigned long insn;
 482 {
 483   int i, bits, shift, flags, format;
 484   unsigned int number;
 485
 486   /* the insn argument is only used for the DIVS kludge */
 487   if (insn)
 488     format = LONG_R;
 489   else
 490     {
 491       insn = opcode->opcode;
 492       format = opcode->format;
 493     }
 494
 495   for (i=0;opcode->operands[i];i++)
 496     {
 497       flags = d10v_operands[opcode->operands[i]].flags;
 498       bits = d10v_operands[opcode->operands[i]].bits;
 499       shift = d10v_operands[opcode->operands[i]].shift;
 500       number = opers[i].X_add_number;
 501
 502       if (flags & OPERAND_REG)
 503         {
 504           number &= REGISTER_MASK;
 505           if (format == LONG_L)
 506             shift += 15;
 507         }
 508
 509       if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
 510         {
 511           /* now create a fixup */
 512
 513           /*
 514           printf("need a fixup: ");
 515           print_expr_1(stdout,&opers[i]);
 516           printf("\n");
 517           */
 518
 519           if (fixups->fc >= MAX_INSN_FIXUPS)
 520             as_fatal ("too many fixups");
 521           fixups->fix[fixups->fc].exp = opers[i];
 522           fixups->fix[fixups->fc].operand = opcode->operands[i];
 523           fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
 524           (fixups->fc)++;
 525         }
 526
 527       /* truncate to the proper number of bits */
 528       if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
 529         as_bad("operand out of range: %d",number);
 530       number &= 0x7FFFFFFF >> (31 - bits);
 531       insn = insn | (number << shift);
 532     }
 533
 534   /* kludge: for DIVS, we need to put the operands in twice */
 535   /* on the second pass, format is changed to LONG_R to force */
 536   /* the second set of operands to not be shifted over 15 */
 537   if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
 538     insn = build_insn (opcode, opers, insn);
 539
 540   return insn;
 541 }
 542
 543 /* write out a long form instruction */
 544 static void
 545 write_long (opcode, insn, fx)
 546      struct d10v_opcode *opcode;
 547      unsigned long insn;
 548      Fixups *fx;
 549 {
 550   int i;
 551   char *f = frag_more(4);
 552
 553   insn |= FM11;
 554   /* printf("INSN: %08x\n",insn); */
 555   number_to_chars_bigendian (f, insn, 4);
 556
 557   for (i=0; i < fx->fc; i++)
 558     {
 559       if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].operand]))
 560         {
 561           /*
 562           printf("fix_new_exp: where:%x size:4\n    ",f - frag_now->fr_literal);
 563           print_expr_1(stdout,&(fx->fix[i].exp));
 564           printf("\n");
 565           */
 566
 567           fix_new_exp (frag_now,
 568                        f - frag_now->fr_literal,
 569                        4,
 570                        &(fx->fix[i].exp),
 571                        fx->fix[i].pcrel,
 572                        fx->fix[i].operand|2048);
 573         }
 574     }
 575   fx->fc = 0;
 576 }
 577
 578
 579 /* write out a short form instruction by itself */
 580 static void
 581 write_1_short (opcode, insn, fx)
 582      struct d10v_opcode *opcode;
 583      unsigned long insn;
 584      Fixups *fx;
 585 {
 586   char *f = frag_more(4);
 587   int i;
 588
 589   if (opcode->exec_type & PARONLY)
 590     as_fatal ("Instruction must be executed in parallel with another instruction.");
 591
 592   /* the other container needs to be NOP */
 593   /* according to 4.3.1: for FM=00, sub-instructions performed only
 594      by IU cannot be encoded in L-container. */
 595   if (opcode->unit == IU)
 596     insn |= FM00 | (NOP << 15);         /* right container */
 597   else
 598     insn = FM00 | (insn << 15) | NOP;   /* left container */
 599
 600   /*  printf("INSN: %08x\n",insn);  */
 601   number_to_chars_bigendian (f, insn, 4);
 602   for (i=0; i < fx->fc; i++)
 603     {
 604       bfd_reloc_code_real_type reloc;
 605       reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].operand]);
 606       if (reloc)
 607         {
 608           /*
 609           printf("fix_new_exp: where:%x size:4\n    ",f - frag_now->fr_literal);
 610           print_expr_1(stdout,&(fx->fix[i].exp));
 611           printf("\n");
 612           */
 613
 614           /* if it's an R reloc, we may have to switch it to L */
 615           if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
 616             fx->fix[i].operand |= 1024;
 617
 618           fix_new_exp (frag_now,
 619                        f - frag_now->fr_literal,
 620                        4,
 621                        &(fx->fix[i].exp),
 622                        fx->fix[i].pcrel,
 623                        fx->fix[i].operand|2048);
 624         }
 625     }
 626   fx->fc = 0;
 627 }
 628
 629 /* write out a short form instruction if possible */
 630 /* return number of instructions not written out */
 631 static int
 632 write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
 633      struct d10v_opcode *opcode1, *opcode2;
 634      unsigned long insn1, insn2;
 635      int exec_type;
 636      Fixups *fx;
 637 {
 638   unsigned long insn;
 639   char *f;
 640   int i,j;
 641
 642   if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY)
 643                         || (opcode2->exec_type & PARONLY)))
 644     as_fatal("Instruction must be executed in parallel");
 645
 646   if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
 647     as_fatal ("Long instructions may not be combined.");
 648
 649   if(opcode1->exec_type & BRANCH_LINK)
 650     {
 651       /* subroutines must be called from 32-bit boundaries */
 652       /* so the return address will be correct */
 653       write_1_short (opcode1, insn1, fx->next);
 654       return (1);
 655     }
 656
 657   switch (exec_type)
 658     {
 659     case 0:     /* order not specified */
 660       if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2))
 661         {
 662           /* parallel */
 663           if (opcode1->unit == IU)
 664             insn = FM00 | (insn2 << 15) | insn1;
 665           else if (opcode2->unit == MU)
 666             insn = FM00 | (insn2 << 15) | insn1;
 667           else
 668             {
 669               insn = FM00 | (insn1 << 15) | insn2;
 670               fx = fx->next;
 671             }
 672         }
 673       else if (opcode1->unit == IU)
 674         {
 675           /* reverse sequential */
 676           insn = FM10 | (insn2 << 15) | insn1;
 677         }
 678       else
 679         {
 680           /* sequential */
 681           insn = FM01 | (insn1 << 15) | insn2;
 682           fx = fx->next;
 683         }
 684       break;
 685     case 1:     /* parallel */
 686       if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
 687         as_fatal ("One of these instructions may not be executed in parallel.");
 688
 689       if (opcode1->unit == IU)
 690         {
 691           if (opcode2->unit == IU)
 692             as_fatal ("Two IU instructions may not be executed in parallel");
 693           as_warn ("Swapping instruction order");
 694           insn = FM00 | (insn2 << 15) | insn1;
 695         }
 696       else if (opcode2->unit == MU)
 697         {
 698           if (opcode1->unit == MU)
 699             as_fatal ("Two MU instructions may not be executed in parallel");
 700           as_warn ("Swapping instruction order");
 701           insn = FM00 | (insn2 << 15) | insn1;
 702         }
 703       else
 704         {
 705           insn = FM00 | (insn1 << 15) | insn2;
 706           fx = fx->next;
 707         }
 708       break;
 709     case 2:     /* sequential */
 710       if (opcode1->unit == IU)
 711         as_fatal ("IU instruction may not be in the left container");
 712       insn = FM01 | (insn1 << 15) | insn2;
 713       fx = fx->next;
 714       break;
 715     case 3:     /* reverse sequential */
 716       if (opcode2->unit == MU)
 717         as_fatal ("MU instruction may not be in the right container");
 718       insn = FM10 | (insn1 << 15) | insn2;
 719       fx = fx->next;
 720       break;
 721     default:
 722       as_fatal("unknown execution type passed to write_2_short()");
 723     }
 724
 725   /*  printf("INSN: %08x\n",insn); */
 726   f = frag_more(4);
 727   number_to_chars_bigendian (f, insn, 4);
 728
 729   for (j=0; j<2; j++)
 730     {
 731       bfd_reloc_code_real_type reloc;
 732       for (i=0; i < fx->fc; i++)
 733         {
 734           reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].operand]);
 735           if (reloc)
 736             {
 737               if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
 738                 fx->fix[i].operand |= 1024;
 739
 740               /*
 741                 printf("fix_new_exp: where:%x reloc:%d\n    ",f - frag_now->fr_literal,fx->fix[i].operand);
 742                 print_expr_1(stdout,&(fx->fix[i].exp));
 743                 printf("\n");
 744                 */
 745               fix_new_exp (frag_now,
 746                            f - frag_now->fr_literal,
 747                            4,
 748                            &(fx->fix[i].exp),
 749                            fx->fix[i].pcrel,
 750                            fx->fix[i].operand|2048);
 751             }
 752         }
 753       fx->fc = 0;
 754       fx = fx->next;
 755     }
 756   return (0);
 757 }
 758
 759
 760 /* Check 2 instructions and determine if they can be safely */
 761 /* executed in parallel.  Returns 1 if they can be.         */
 762 static int
 763 parallel_ok (op1, insn1, op2, insn2)
 764      struct d10v_opcode *op1, *op2;
 765      unsigned long insn1, insn2;
 766 {
 767   int i, j, flags, mask, shift, regno;
 768   unsigned long ins, mod[2], used[2];
 769   struct d10v_opcode *op;
 770
 771   if (op1->exec_type & SEQ || op2->exec_type & SEQ)
 772     return 0;
 773
 774   /* The idea here is to create two sets of bitmasks (mod and used) */
 775   /* which indicate which registers are modified or used by each instruction. */
 776   /* The operation can only be done in parallel if instruction 1 and instruction 2 */
 777   /* modify different registers, and neither instruction modifies any registers */
 778   /* the other is using.  Accesses to control registers, PSW, and memory are treated */
 779   /* as accesses to a single register.  So if both instructions write memory or one */
 780   /* instruction writes memory and the other reads, then they cannot be done in parallel. */
 781   /* Likewise, if one instruction mucks with the psw and the other reads the PSW */
 782   /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
 783
 784   /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
 785   /* r0-r15       0-15  */
 786   /* a0-a1        16-17 */
 787   /* cr (not psw) 18    */
 788   /* psw          19    */
 789   /* mem          20    */
 790
 791   for (j=0;j<2;j++)
 792     {
 793       if (j == 0)
 794         {
 795           op = op1;
 796           ins = insn1;
 797         }
 798       else
 799         {
 800           op = op2;
 801           ins = insn2;
 802         }
 803       mod[j] = used[j] = 0;
 804       for (i = 0; op1->operands[i]; i++)
 805         {
 806           flags = d10v_operands[op->operands[i]].flags;
 807           shift = d10v_operands[op->operands[i]].shift;
 808           mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
 809           if (flags & OPERAND_REG)
 810             {
 811               regno = (ins >> shift) & mask;
 812               if (flags & OPERAND_ACC)
 813                 regno += 16;
 814               else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
 815                 {
 816                   if (regno == 0)
 817                     regno = 19;
 818                   else
 819                     regno = 18;
 820                 }
 821               else if (flags & OPERAND_FLAG)
 822                 regno = 19;
 823
 824               if ( flags & OPERAND_DEST )
 825                 {
 826                   mod[j] |= 1 << regno;
 827                   if (flags & OPERAND_EVEN)
 828                     mod[j] |= 1 << (regno + 1);
 829                 }
 830               else
 831                 {
 832                   used[j] |= 1 << regno ;
 833                   if (flags & OPERAND_EVEN)
 834                     used[j] |= 1 << (regno + 1);
 835                 }
 836             }
 837           else if (op->exec_type & RMEM)
 838             used[j] |= 1 << 20;
 839           else if (op->exec_type & WMEM)
 840             mod[j] |= 1 << 20;
 841           else if (op->exec_type & RF0)
 842             used[j] |= 1 << 19;
 843           else if (op->exec_type & WF0)
 844             mod[j] |= 1 << 19;
 845           else if (op->exec_type & WCAR)
 846             mod[j] |= 1 << 19;
 847         }
 848     }
 849   if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0)
 850     return 1;
 851   return 0;
 852 }
 853
 854
 855 /* This is the main entry point for the machine-dependent assembler.  str points to a
 856    machine-dependent instruction.  This function is supposed to emit the frags/bytes
 857    it assembles to.  For the D10V, it mostly handles the special VLIW parsing and packing
 858    and leaves the difficult stuff to do_assemble().
 859  */
 860
 861 static unsigned long prev_insn;
 862 static struct d10v_opcode *prev_opcode = 0;
 863 static subsegT prev_subseg;
 864 static segT prev_seg;
 865
 866 void
 867 md_assemble (str)
 868      char *str;
 869 {
 870   struct d10v_opcode *opcode;
 871   unsigned long insn;
 872   int extype=0;                 /* execution type; parallel, etc */
 873   static int etype=0;           /* saved extype.  used for multiline instructions */
 874   char *str2;
 875
 876   /*  printf("md_assemble: str=%s\n",str); */
 877
 878   if (etype == 0)
 879     {
 880       /* look for the special multiple instruction separators */
 881       str2 = strstr (str, "||");
 882       if (str2)
 883         extype = 1;
 884       else
 885         {
 886           str2 = strstr (str, "->");
 887           if (str2)
 888             extype = 2;
 889           else
 890             {
 891               str2 = strstr (str, "<-");
 892               if (str2)
 893                 extype = 3;
 894             }
 895         }
 896       /* str2 points to the separator, if one */
 897       if (str2)
 898         {
 899           *str2 = 0;
 900
 901           /* if two instructions are present and we already have one saved
 902              then first write it out */
 903           if (prev_opcode)
 904             write_1_short (prev_opcode, prev_insn, fixups->next);
 905
 906           /* assemble first instruction and save it */
 907           prev_insn = do_assemble (str, &prev_opcode);
 908           if (prev_insn == -1)
 909             as_fatal ("can't find opcode ");
 910           fixups = fixups->next;
 911           str = str2 + 2;
 912         }
 913     }
 914
 915   insn = do_assemble (str, &opcode);
 916   if (insn == -1)
 917     {
 918       if (extype)
 919         {
 920           etype = extype;
 921           return;
 922         }
 923       as_fatal ("can't find opcode ");
 924     }
 925
 926   if (etype)
 927     {
 928       extype = etype;
 929       etype = 0;
 930     }
 931
 932   /* if this is a long instruction, write it and any previous short instruction */
 933   if (opcode->format & LONG_OPCODE)
 934     {
 935       if (extype)
 936         as_fatal("Unable to mix instructions as specified");
 937       if (prev_opcode)
 938         {
 939           write_1_short (prev_opcode, prev_insn, fixups->next);
 940           prev_opcode = NULL;
 941         }
 942       write_long (opcode, insn, fixups);
 943       prev_opcode = NULL;
 944       return;
 945     }
 946
 947   if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
 948     {
 949       /* no instructions saved */
 950       prev_opcode = NULL;
 951     }
 952   else
 953     {
 954       if (extype)
 955         as_fatal("Unable to mix instructions as specified");
 956       /* save off last instruction so it may be packed on next pass */
 957       prev_opcode = opcode;
 958       prev_insn = insn;
 959       prev_seg = now_seg;
 960       prev_subseg = now_subseg;
 961       fixups = fixups->next;
 962     }
 963 }
 964
 965
 966 /* do_assemble assembles a single instruction and returns an opcode */
 967 /* it returns -1 (an invalid opcode) on error */
 968
 969 static unsigned long
 970 do_assemble (str, opcode)
 971      char *str;
 972      struct d10v_opcode **opcode;
 973 {
 974   unsigned char *op_start, *save;
 975   unsigned char *op_end;
 976   char name[20];
 977   int nlen = 0;
 978   expressionS myops[6];
 979   unsigned long insn;
 980
 981   /* printf("do_assemble: str=%s\n",str); */
 982
 983   /* Drop leading whitespace */
 984   while (*str == ' ')
 985     str++;
 986
 987   /* find the opcode end */
 988   for (op_start = op_end = (unsigned char *) (str);
 989        *op_end
 990        && nlen < 20
 991        && !is_end_of_line[*op_end] && *op_end != ' ';
 992        op_end++)
 993     {
 994       name[nlen] = op_start[nlen];
 995       nlen++;
 996     }
 997   name[nlen] = 0;
 998
 999   if (nlen == 0)
1000     return (-1);
1001
1002   /* find the first opcode with the proper name */
1003   *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
1004   if (*opcode == NULL)
1005       as_fatal ("unknown opcode: %s",name);
1006
1007   save = input_line_pointer;
1008   input_line_pointer = op_end;
1009   *opcode = find_opcode (*opcode, myops);
1010   if (*opcode == 0)
1011     return -1;
1012   input_line_pointer = save;
1013
1014   insn = build_insn ((*opcode), myops, 0);
1015   /* printf("sub-insn = %lx\n",insn); */
1016   return (insn);
1017 }
1018
1019 /* find_opcode() gets a pointer to an entry in the opcode table.       */
1020 /* It must look at all opcodes with the same name and use the operands */
1021 /* to choose the correct opcode. */
1022
1023 static struct d10v_opcode *
1024 find_opcode (opcode, myops)
1025      struct d10v_opcode *opcode;
1026      expressionS myops[];
1027 {
1028   int i, match, done, numops;
1029   struct d10v_opcode *next_opcode;
1030
1031   /* get all the operands and save them as expressions */
1032   numops = get_operands (myops);
1033
1034   /* now see if the operand is a fake.  If so, find the correct size */
1035   /* instruction, if possible */
1036   if (opcode->format == OPCODE_FAKE)
1037     {
1038       int opnum = opcode->operands[0];
1039
1040       if (myops[opnum].X_op == O_register)
1041         {
1042           myops[opnum].X_op = O_symbol;
1043           myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
1044           myops[opnum].X_add_number = 0;
1045           myops[opnum].X_op_symbol = NULL;
1046         }
1047
1048       if (myops[opnum].X_op == O_constant || S_IS_DEFINED(myops[opnum].X_add_symbol))
1049         {
1050           next_opcode=opcode+1;
1051           for (i=0; opcode->operands[i+1]; i++)
1052             {
1053               int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1054               int flags = d10v_operands[next_opcode->operands[opnum]].flags;
1055               if (!check_range (myops[opnum].X_add_number, bits, flags))
1056                   return next_opcode;
1057               next_opcode++;
1058             }
1059           as_fatal ("value out of range");
1060         }
1061       else
1062         {
1063           /* not a constant, so use a long instruction */
1064           return opcode+2;
1065         }
1066     }
1067   else
1068     {
1069       match = 0;
1070       /* now search the opcode table table for one with operands */
1071       /* that matches what we've got */
1072       while (!match)
1073         {
1074           match = 1;
1075           for (i = 0; opcode->operands[i]; i++)
1076             {
1077               int flags = d10v_operands[opcode->operands[i]].flags;
1078               int X_op = myops[i].X_op;
1079               int num = myops[i].X_add_number;
1080
1081               if (X_op==0)
1082                 {
1083                   match=0;
1084                   break;
1085                 }
1086
1087               if (flags & OPERAND_REG)
1088                 {
1089                   if ((X_op != O_register) ||
1090                       ((flags & OPERAND_ACC) != (num & OPERAND_ACC)) ||
1091                       ((flags & OPERAND_FLAG) != (num & OPERAND_FLAG)) ||
1092                       ((flags & OPERAND_CONTROL) != (num & OPERAND_CONTROL)))
1093                     {
1094                       match=0;
1095                       break;
1096                     }
1097                 }
1098
1099               if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1100                   ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1101                   ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1102                   ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1103                   ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
1104                 {
1105                   match=0;
1106                   break;
1107                 }
1108             }
1109
1110           /* we're only done if the operands matched so far AND there
1111              are no more to check */
1112           if (match && myops[i].X_op==0)
1113             break;
1114
1115           next_opcode = opcode+1;
1116           if (next_opcode->opcode == 0)
1117             break;
1118           if (strcmp(next_opcode->name, opcode->name))
1119             break;
1120           opcode = next_opcode;
1121         }
1122     }
1123
1124   if (!match)
1125     {
1126       as_bad ("bad opcode or operands");
1127       return (0);
1128     }
1129
1130   /* Check that all registers that are required to be even are. */
1131   /* Also, if any operands were marked as registers, but were really symbols */
1132   /* fix that here. */
1133   for (i=0; opcode->operands[i]; i++)
1134     {
1135       if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1136           (myops[i].X_add_number & 1))
1137         as_fatal("Register number must be EVEN");
1138       if (myops[i].X_op == O_register)
1139         {
1140           if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1141             {
1142               myops[i].X_op = O_symbol;
1143               myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
1144               myops[i].X_add_number = 0;
1145               myops[i].X_op_symbol = NULL;
1146             }
1147         }
1148     }
1149   return opcode;
1150 }
1151
1152 /* if while processing a fixup, a reloc really needs to be created */
1153 /* then it is done here */
1154
1155 arelent *
1156 tc_gen_reloc (seg, fixp)
1157      asection *seg;
1158      fixS *fixp;
1159 {
1160   arelent *reloc;
1161   reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1162   reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1163   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1164   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1165   if (reloc->howto == (reloc_howto_type *) NULL)
1166     {
1167       as_bad_where (fixp->fx_file, fixp->fx_line,
1168                     "reloc %d not supported by object file format", (int)fixp->fx_r_type);
1169       return NULL;
1170     }
1171   reloc->addend = fixp->fx_addnumber;
1172   /* printf("tc_gen_reloc: addr=%x  addend=%x\n", reloc->address, reloc->addend); */
1173   return reloc;
1174 }
1175
1176 int
1177 md_estimate_size_before_relax (fragp, seg)
1178      fragS *fragp;
1179      asection *seg;
1180 {
1181   abort ();
1182   return 0;
1183 }
1184
1185 long
1186 md_pcrel_from_section (fixp, sec)
1187      fixS *fixp;
1188      segT sec;
1189 {
1190   if (fixp->fx_addsy != (symbolS *)NULL && !S_IS_DEFINED (fixp->fx_addsy))
1191     return 0;
1192   /* printf("pcrel_from_section: %x\n", fixp->fx_frag->fr_address + fixp->fx_where); */
1193   return fixp->fx_frag->fr_address + fixp->fx_where;
1194 }
1195
1196 int
1197 md_apply_fix3 (fixp, valuep, seg)
1198      fixS *fixp;
1199      valueT *valuep;
1200      segT seg;
1201 {
1202   char *where;
1203   unsigned long insn;
1204   long value;
1205   int op_type;
1206   int left=0;
1207
1208   if (fixp->fx_addsy == (symbolS *) NULL)
1209     {
1210       value = *valuep;
1211       fixp->fx_done = 1;
1212     }
1213   else if (fixp->fx_pcrel)
1214     value = *valuep;
1215   else
1216     {
1217       value = fixp->fx_offset;
1218       if (fixp->fx_subsy != (symbolS *) NULL)
1219         {
1220           if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
1221             value -= S_GET_VALUE (fixp->fx_subsy);
1222           else
1223             {
1224               /* We don't actually support subtracting a symbol.  */
1225               as_bad_where (fixp->fx_file, fixp->fx_line,
1226                             "expression too complex");
1227             }
1228         }
1229     }
1230
1231   /* printf("md_apply_fix: value=0x%x  type=0x%x  where=0x%x\n",  value, fixp->fx_r_type,fixp->fx_where); */
1232
1233   op_type = fixp->fx_r_type;
1234   if (op_type & 2048)
1235     {
1236       op_type -= 2048;
1237       if (op_type & 1024)
1238         {
1239           op_type -= 1024;
1240           fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1241           left = 1;
1242         }
1243       else
1244         fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
1245     }
1246
1247   /* Fetch the instruction, insert the fully resolved operand
1248      value, and stuff the instruction back again.  */
1249   where = fixp->fx_frag->fr_literal + fixp->fx_where;
1250   insn = bfd_getb32 ((unsigned char *) where);
1251
1252   switch (fixp->fx_r_type)
1253     {
1254     case BFD_RELOC_D10V_10_PCREL_L:
1255     case BFD_RELOC_D10V_10_PCREL_R:
1256     case BFD_RELOC_D10V_18_PCREL:
1257       /* instruction addresses are always right-shifted by 2 */
1258       value >>= 2;
1259       break;
1260     case BFD_RELOC_32:
1261       bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1262       return 1;
1263     default:
1264       break;
1265     }
1266
1267   /* printf("   insn=%x  value=%x where=%x  pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */
1268   insn = d10v_insert_operand (insn, op_type, (offsetT)value, left);
1269   /* printf("   new insn=%x\n",insn); */
1270
1271   bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1272
1273   if (fixp->fx_done)
1274     return 1;
1275
1276   fixp->fx_addnumber = value;
1277   return 1;
1278 }
1279
1280
1281 /* d10v_cleanup() is called after the assembler has finished parsing the input
1282    file or after a label is defined.  Because the D10V assembler sometimes saves short
1283    instructions to see if it can package them with the next instruction, there may
1284    be a short instruction that still needs written.  */
1285 int
1286 d10v_cleanup (done)
1287      int done;
1288 {
1289   segT seg;
1290   subsegT subseg;
1291
1292   if ( prev_opcode && (done  || (now_seg == prev_seg) && (now_subseg == prev_subseg)))
1293     {
1294       seg = now_seg;
1295       subseg = now_subseg;
1296       subseg_set (prev_seg, prev_subseg);
1297       write_1_short (prev_opcode, prev_insn, fixups);
1298       subseg_set (seg, subseg);
1299       prev_opcode = NULL;
1300     }
1301   return 1;
1302 }