1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars
[] = ";";
30 const char line_comment_chars
[] = "#";
31 const char line_separator_chars
[] = "";
32 const char *md_shortopts
= "O";
33 const char EXP_CHARS
[] = "eE";
34 const char FLT_CHARS
[] = "dD";
38 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
39 && (X)->X_op_symbol != NULL \
40 && (X)->X_op_symbol->sy_value.X_op == O_constant \
41 && (X)->X_op_symbol->sy_value.X_add_number == AT_WORD_RIGHT_SHIFT)
42 #define AT_WORD_RIGHT_SHIFT 2
46 #define MAX_INSN_FIXUPS (5)
53 bfd_reloc_code_real_type reloc
;
56 typedef struct _fixups
59 struct d10v_fixup fix
[MAX_INSN_FIXUPS
];
63 static Fixups FixUps
[2];
64 static Fixups
*fixups
;
67 static int reg_name_search
PARAMS ((char *name
));
68 static int register_name
PARAMS ((expressionS
*expressionP
));
69 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
70 static int postfix
PARAMS ((char *p
));
71 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d10v_operand
*op
));
72 static int get_operands
PARAMS ((expressionS exp
[]));
73 static struct d10v_opcode
*find_opcode
PARAMS ((struct d10v_opcode
*opcode
, expressionS ops
[]));
74 static unsigned long build_insn
PARAMS ((struct d10v_opcode
*opcode
, expressionS
*opers
, unsigned long insn
));
75 static void write_long
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
76 static void write_1_short
PARAMS ((struct d10v_opcode
*opcode
, unsigned long insn
, Fixups
*fx
));
77 static int write_2_short
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
78 struct d10v_opcode
*opcode2
, unsigned long insn2
, int exec_type
, Fixups
*fx
));
79 static unsigned long do_assemble
PARAMS ((char *str
, struct d10v_opcode
**opcode
));
80 static unsigned long d10v_insert_operand
PARAMS (( unsigned long insn
, int op_type
,
81 offsetT value
, int left
, fixS
*fix
));
82 static int parallel_ok
PARAMS ((struct d10v_opcode
*opcode1
, unsigned long insn1
,
83 struct d10v_opcode
*opcode2
, unsigned long insn2
,
86 struct option md_longopts
[] = {
87 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
88 {"nowarnswap", no_argument
, NULL
, OPTION_NOWARNSWAP
},
89 {NULL
, no_argument
, NULL
, 0}
91 size_t md_longopts_size
= sizeof(md_longopts
);
93 static void d10v_dot_word
PARAMS ((int));
95 /* The target specific pseudo-ops which we support. */
96 const pseudo_typeS md_pseudo_table
[] =
98 { "word", d10v_dot_word
, 2 },
102 /* Opcode hash table. */
103 static struct hash_control
*d10v_hash
;
105 /* reg_name_search does a binary search of the d10v_predefined_registers
106 array to see if "name" is a valid regiter name. Returns the register
107 number from the array on success, or -1 on failure. */
110 reg_name_search (name
)
113 int middle
, low
, high
;
117 high
= d10v_reg_name_cnt() - 1;
121 middle
= (low
+ high
) / 2;
122 cmp
= strcasecmp (name
, d10v_predefined_registers
[middle
].name
);
128 return d10v_predefined_registers
[middle
].value
;
134 /* register_name() checks the string at input_line_pointer
135 to see if it is a valid register name */
138 register_name (expressionP
)
139 expressionS
*expressionP
;
142 char c
, *p
= input_line_pointer
;
144 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
151 /* look to see if it's in the register table */
152 reg_number
= reg_name_search (input_line_pointer
);
155 expressionP
->X_op
= O_register
;
156 /* temporarily store a pointer to the string here */
157 expressionP
->X_op_symbol
= (struct symbol
*)input_line_pointer
;
158 expressionP
->X_add_number
= reg_number
;
159 input_line_pointer
= p
;
169 check_range (num
, bits
, flags
)
177 /* don't bother checking 16-bit values */
181 if (flags
& OPERAND_SHIFT
)
183 /* all special shift operands are unsigned */
184 /* and <= 16. We allow 0 for now. */
191 if (flags
& OPERAND_SIGNED
)
193 max
= (1 << (bits
- 1))-1;
194 min
= - (1 << (bits
- 1));
195 if (((long)num
> max
) || ((long)num
< min
))
200 max
= (1 << bits
) - 1;
202 if ((num
> max
) || (num
< min
))
210 md_show_usage (stream
)
213 fprintf(stream
, "D10V options:\n\
214 -O optimize. Will do some operations in parallel.\n");
218 md_parse_option (c
, arg
)
225 /* Optimize. Will attempt to parallelize operations */
228 case OPTION_NOWARNSWAP
:
229 flag_warn_suppress_instructionswap
= 1;
238 md_undefined_symbol (name
)
244 /* Turn a string in input_line_pointer into a floating point constant of type
245 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
246 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
249 md_atof (type
, litP
, sizeP
)
255 LITTLENUM_TYPE words
[4];
269 return "bad call to md_atof";
272 t
= atof_ieee (input_line_pointer
, type
, words
);
274 input_line_pointer
= t
;
278 for (i
= 0; i
< prec
; i
++)
280 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
287 md_convert_frag (abfd
, sec
, fragP
)
296 md_section_align (seg
, addr
)
300 int align
= bfd_get_section_alignment (stdoutput
, seg
);
301 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
308 char *prev_name
= "";
309 struct d10v_opcode
*opcode
;
310 d10v_hash
= hash_new();
312 /* Insert unique names into hash table. The D10v instruction set
313 has many identical opcode names that have different opcodes based
314 on the operands. This hash table then provides a quick index to
315 the first opcode with a particular name in the opcode table. */
317 for (opcode
= (struct d10v_opcode
*)d10v_opcodes
; opcode
->name
; opcode
++)
319 if (strcmp (prev_name
, opcode
->name
))
321 prev_name
= (char *)opcode
->name
;
322 hash_insert (d10v_hash
, opcode
->name
, (char *) opcode
);
327 FixUps
[0].next
= &FixUps
[1];
328 FixUps
[1].next
= &FixUps
[0];
332 /* this function removes the postincrement or postdecrement
333 operator ( '+' or '-' ) from an expression */
335 static int postfix (p
)
338 while (*p
!= '-' && *p
!= '+')
340 if (*p
==0 || *p
=='\n' || *p
=='\r')
360 static bfd_reloc_code_real_type
362 struct d10v_operand
*op
;
369 if (op
->flags
& OPERAND_ADDR
)
372 return (BFD_RELOC_D10V_10_PCREL_R
);
374 return (BFD_RELOC_D10V_18_PCREL
);
377 return (BFD_RELOC_16
);
381 /* get_operands parses a string of operands and returns
382 an array of expressions */
388 char *p
= input_line_pointer
;
394 while (*p
== ' ' || *p
== '\t' || *p
== ',')
396 if (*p
==0 || *p
=='\n' || *p
=='\r')
402 exp
[numops
].X_op
= O_absent
;
406 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
411 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
415 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
424 /* just skip the trailing paren */
429 input_line_pointer
= p
;
431 /* check to see if it might be a register name */
432 if (!register_name (&exp
[numops
]))
434 /* parse as an expression */
435 expression (&exp
[numops
]);
438 if (strncasecmp (input_line_pointer
, "@word", 5) == 0)
440 input_line_pointer
+= 5;
441 if (exp
[numops
].X_op
== O_register
)
443 /* if it looked like a register name but was followed by
444 "@word" then it was really a symbol, so change it to
446 exp
[numops
].X_op
= O_symbol
;
447 exp
[numops
].X_add_symbol
= symbol_find_or_make ((char *)exp
[numops
].X_op_symbol
);
450 /* check for identifier@word+constant */
451 if (*input_line_pointer
== '-' || *input_line_pointer
== '+')
453 char *orig_line
= input_line_pointer
;
455 expression (&new_exp
);
456 exp
[numops
].X_add_number
= new_exp
.X_add_number
;
459 /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
462 memset (&new_exp
, 0, sizeof new_exp
);
463 new_exp
.X_add_number
= AT_WORD_RIGHT_SHIFT
;
464 new_exp
.X_op
= O_constant
;
465 new_exp
.X_unsigned
= 1;
466 exp
[numops
].X_op_symbol
= make_expr_symbol (&new_exp
);
467 exp
[numops
].X_op
= O_right_shift
;
470 know (AT_WORD_P (&exp
[numops
]));
473 if (exp
[numops
].X_op
== O_illegal
)
474 as_bad ("illegal operand");
475 else if (exp
[numops
].X_op
== O_absent
)
476 as_bad ("missing operand");
479 p
= input_line_pointer
;
484 case -1: /* postdecrement mode */
485 exp
[numops
].X_op
= O_absent
;
486 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
488 case 1: /* postincrement mode */
489 exp
[numops
].X_op
= O_absent
;
490 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
494 exp
[numops
].X_op
= 0;
499 d10v_insert_operand (insn
, op_type
, value
, left
, fix
)
508 shift
= d10v_operands
[op_type
].shift
;
512 bits
= d10v_operands
[op_type
].bits
;
514 /* truncate to the proper number of bits */
515 if (check_range (value
, bits
, d10v_operands
[op_type
].flags
))
516 as_bad_where (fix
->fx_file
, fix
->fx_line
, "operand out of range: %d", value
);
518 value
&= 0x7FFFFFFF >> (31 - bits
);
519 insn
|= (value
<< shift
);
525 /* build_insn takes a pointer to the opcode entry in the opcode table
526 and the array of operand expressions and returns the instruction */
529 build_insn (opcode
, opers
, insn
)
530 struct d10v_opcode
*opcode
;
534 int i
, bits
, shift
, flags
, format
;
535 unsigned long number
;
537 /* the insn argument is only used for the DIVS kludge */
542 insn
= opcode
->opcode
;
543 format
= opcode
->format
;
546 for (i
=0;opcode
->operands
[i
];i
++)
548 flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
549 bits
= d10v_operands
[opcode
->operands
[i
]].bits
;
550 shift
= d10v_operands
[opcode
->operands
[i
]].shift
;
551 number
= opers
[i
].X_add_number
;
553 if (flags
& OPERAND_REG
)
555 number
&= REGISTER_MASK
;
556 if (format
== LONG_L
)
560 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
)
562 /* now create a fixup */
564 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
565 as_fatal ("too many fixups");
567 if (AT_WORD_P (&opers
[i
]))
569 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
570 fixups
->fix
[fixups
->fc
].reloc
= BFD_RELOC_D10V_18
;
571 opers
[i
].X_op
= O_symbol
;
572 opers
[i
].X_op_symbol
= NULL
; /* Should free it */
573 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
574 that, it is aligned with the symbol's value. Later,
575 BFD_RELOC_D10V_18 will right shift (symbol_value +
577 number
<<= AT_WORD_RIGHT_SHIFT
;
578 opers
[i
].X_add_number
= number
;
581 fixups
->fix
[fixups
->fc
].reloc
=
582 get_reloc((struct d10v_operand
*)&d10v_operands
[opcode
->operands
[i
]]);
584 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_16
||
585 fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D10V_18
)
586 fixups
->fix
[fixups
->fc
].size
= 2;
588 fixups
->fix
[fixups
->fc
].size
= 4;
590 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
591 fixups
->fix
[fixups
->fc
].operand
= opcode
->operands
[i
];
592 fixups
->fix
[fixups
->fc
].pcrel
= (flags
& OPERAND_ADDR
) ? true : false;
596 /* truncate to the proper number of bits */
597 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
598 as_bad("operand out of range: %d",number
);
599 number
&= 0x7FFFFFFF >> (31 - bits
);
600 insn
= insn
| (number
<< shift
);
603 /* kludge: for DIVS, we need to put the operands in twice */
604 /* on the second pass, format is changed to LONG_R to force */
605 /* the second set of operands to not be shifted over 15 */
606 if ((opcode
->opcode
== OPCODE_DIVS
) && (format
==LONG_L
))
607 insn
= build_insn (opcode
, opers
, insn
);
612 /* write out a long form instruction */
614 write_long (opcode
, insn
, fx
)
615 struct d10v_opcode
*opcode
;
620 char *f
= frag_more(4);
623 number_to_chars_bigendian (f
, insn
, 4);
625 for (i
=0; i
< fx
->fc
; i
++)
627 if (fx
->fix
[i
].reloc
)
629 where
= f
- frag_now
->fr_literal
;
630 if (fx
->fix
[i
].size
== 2)
633 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
634 fx
->fix
[i
].operand
|= 4096;
636 fix_new_exp (frag_now
,
641 fx
->fix
[i
].operand
|2048);
648 /* write out a short form instruction by itself */
650 write_1_short (opcode
, insn
, fx
)
651 struct d10v_opcode
*opcode
;
655 char *f
= frag_more(4);
658 if (opcode
->exec_type
& PARONLY
)
659 as_fatal ("Instruction must be executed in parallel with another instruction.");
661 /* the other container needs to be NOP */
662 /* according to 4.3.1: for FM=00, sub-instructions performed only
663 by IU cannot be encoded in L-container. */
664 if (opcode
->unit
== IU
)
665 insn
|= FM00
| (NOP
<< 15); /* right container */
667 insn
= FM00
| (insn
<< 15) | NOP
; /* left container */
669 number_to_chars_bigendian (f
, insn
, 4);
670 for (i
=0; i
< fx
->fc
; i
++)
672 if (fx
->fix
[i
].reloc
)
674 where
= f
- frag_now
->fr_literal
;
675 if (fx
->fix
[i
].size
== 2)
678 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
679 fx
->fix
[i
].operand
|= 4096;
681 /* if it's an R reloc, we may have to switch it to L */
682 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (opcode
->unit
!= IU
) )
683 fx
->fix
[i
].operand
|= 1024;
685 fix_new_exp (frag_now
,
690 fx
->fix
[i
].operand
|2048);
696 /* write out a short form instruction if possible */
697 /* return number of instructions not written out */
699 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
700 struct d10v_opcode
*opcode1
, *opcode2
;
701 unsigned long insn1
, insn2
;
709 if ( (exec_type
!= 1) && ((opcode1
->exec_type
& PARONLY
)
710 || (opcode2
->exec_type
& PARONLY
)))
711 as_fatal("Instruction must be executed in parallel");
713 if ( (opcode1
->format
& LONG_OPCODE
) || (opcode2
->format
& LONG_OPCODE
))
714 as_fatal ("Long instructions may not be combined.");
716 if(opcode1
->exec_type
& BRANCH_LINK
&& exec_type
== 0)
718 /* Instructions paired with a subroutine call are executed before the
719 subroutine, so don't do these pairings unless explicitly requested. */
720 write_1_short (opcode1
, insn1
, fx
->next
);
726 case 0: /* order not specified */
727 if ( Optimizing
&& parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
730 if (opcode1
->unit
== IU
)
731 insn
= FM00
| (insn2
<< 15) | insn1
;
732 else if (opcode2
->unit
== MU
)
733 insn
= FM00
| (insn2
<< 15) | insn1
;
736 insn
= FM00
| (insn1
<< 15) | insn2
;
740 else if (opcode1
->unit
== IU
)
742 /* reverse sequential */
743 insn
= FM10
| (insn2
<< 15) | insn1
;
748 insn
= FM01
| (insn1
<< 15) | insn2
;
752 case 1: /* parallel */
753 if (opcode1
->exec_type
& SEQ
|| opcode2
->exec_type
& SEQ
)
754 as_fatal ("One of these instructions may not be executed in parallel.");
756 if (opcode1
->unit
== IU
)
758 if (opcode2
->unit
== IU
)
759 as_fatal ("Two IU instructions may not be executed in parallel");
760 if (!flag_warn_suppress_instructionswap
)
761 as_warn ("Swapping instruction order");
762 insn
= FM00
| (insn2
<< 15) | insn1
;
764 else if (opcode2
->unit
== MU
)
766 if (opcode1
->unit
== MU
)
767 as_fatal ("Two MU instructions may not be executed in parallel");
768 if (!flag_warn_suppress_instructionswap
)
769 as_warn ("Swapping instruction order");
770 insn
= FM00
| (insn2
<< 15) | insn1
;
774 insn
= FM00
| (insn1
<< 15) | insn2
;
778 case 2: /* sequential */
779 if (opcode1
->unit
== IU
)
780 as_fatal ("IU instruction may not be in the left container");
781 insn
= FM01
| (insn1
<< 15) | insn2
;
784 case 3: /* reverse sequential */
785 if (opcode2
->unit
== MU
)
786 as_fatal ("MU instruction may not be in the right container");
787 insn
= FM10
| (insn1
<< 15) | insn2
;
791 as_fatal("unknown execution type passed to write_2_short()");
795 number_to_chars_bigendian (f
, insn
, 4);
799 for (i
=0; i
< fx
->fc
; i
++)
801 if (fx
->fix
[i
].reloc
)
803 where
= f
- frag_now
->fr_literal
;
804 if (fx
->fix
[i
].size
== 2)
807 if ( (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_10_PCREL_R
) && (j
== 0) )
808 fx
->fix
[i
].operand
|= 1024;
810 if (fx
->fix
[i
].reloc
== BFD_RELOC_D10V_18
)
811 fx
->fix
[i
].operand
|= 4096;
813 fix_new_exp (frag_now
,
818 fx
->fix
[i
].operand
|2048);
828 /* Check 2 instructions and determine if they can be safely */
829 /* executed in parallel. Returns 1 if they can be. */
831 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
832 struct d10v_opcode
*op1
, *op2
;
833 unsigned long insn1
, insn2
;
836 int i
, j
, flags
, mask
, shift
, regno
;
837 unsigned long ins
, mod
[2], used
[2];
838 struct d10v_opcode
*op
;
840 if ((op1
->exec_type
& SEQ
) != 0 || (op2
->exec_type
& SEQ
) != 0
841 || (op1
->exec_type
& PAR
) == 0 || (op2
->exec_type
& PAR
) == 0
842 || (op1
->unit
== BOTH
) || (op2
->unit
== BOTH
)
843 || (op1
->unit
== IU
&& op2
->unit
== IU
)
844 || (op1
->unit
== MU
&& op2
->unit
== MU
))
847 /* If the first instruction is a branch and this is auto parallazation,
848 don't combine with any second instruction. */
849 if (exec_type
== 0 && (op1
->exec_type
& BRANCH
) != 0)
852 /* The idea here is to create two sets of bitmasks (mod and used)
853 which indicate which registers are modified or used by each
854 instruction. The operation can only be done in parallel if
855 instruction 1 and instruction 2 modify different registers, and
856 the first instruction does not modify registers that the second
857 is using (The second instruction can modify registers that the
858 first is using as they are only written back after the first
859 instruction has completed). Accesses to control registers, PSW,
860 and memory are treated as accesses to a single register. So if
861 both instructions write memory or if the first instruction writes
862 memory and the second reads, then they cannot be done in
863 parallel. Likewise, if the first instruction mucks with the psw
864 and the second reads the PSW (which includes C, F0, and F1), then
865 they cannot operate safely in parallel. */
867 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
870 /* cr (not psw) 18 */
886 mod
[j
] = used
[j
] = 0;
887 if (op
->exec_type
& BRANCH_LINK
)
890 for (i
= 0; op
->operands
[i
]; i
++)
892 flags
= d10v_operands
[op
->operands
[i
]].flags
;
893 shift
= d10v_operands
[op
->operands
[i
]].shift
;
894 mask
= 0x7FFFFFFF >> (31 - d10v_operands
[op
->operands
[i
]].bits
);
895 if (flags
& OPERAND_REG
)
897 regno
= (ins
>> shift
) & mask
;
898 if (flags
& (OPERAND_ACC0
|OPERAND_ACC1
))
900 else if (flags
& OPERAND_CONTROL
) /* mvtc or mvfc */
907 else if (flags
& (OPERAND_FFLAG
|OPERAND_CFLAG
))
910 if ( flags
& OPERAND_DEST
)
912 mod
[j
] |= 1 << regno
;
913 if (flags
& OPERAND_EVEN
)
914 mod
[j
] |= 1 << (regno
+ 1);
918 used
[j
] |= 1 << regno
;
919 if (flags
& OPERAND_EVEN
)
920 used
[j
] |= 1 << (regno
+ 1);
922 /* Auto inc/dec also modifies the register. */
923 if (op
->operands
[i
+1] != 0
924 && (d10v_operands
[op
->operands
[i
+1]].flags
925 & (OPERAND_PLUS
| OPERAND_MINUS
)) != 0)
926 mod
[j
] |= 1 << regno
;
929 else if (flags
& OPERAND_ATMINUS
)
931 /* SP implicitly used/modified */
936 if (op
->exec_type
& RMEM
)
938 else if (op
->exec_type
& WMEM
)
940 else if (op
->exec_type
& RF0
)
942 else if (op
->exec_type
& WF0
)
944 else if (op
->exec_type
& WCAR
)
947 if ((mod
[0] & mod
[1]) == 0 && (mod
[0] & used
[1]) == 0)
953 /* This is the main entry point for the machine-dependent assembler. str points to a
954 machine-dependent instruction. This function is supposed to emit the frags/bytes
955 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
956 and leaves the difficult stuff to do_assemble().
959 static unsigned long prev_insn
;
960 static struct d10v_opcode
*prev_opcode
= 0;
961 static subsegT prev_subseg
;
962 static segT prev_seg
= 0;;
968 struct d10v_opcode
*opcode
;
970 int extype
=0; /* execution type; parallel, etc */
971 static int etype
=0; /* saved extype. used for multiline instructions */
976 /* look for the special multiple instruction separators */
977 str2
= strstr (str
, "||");
982 str2
= strstr (str
, "->");
987 str2
= strstr (str
, "<-");
992 /* str2 points to the separator, if one */
997 /* if two instructions are present and we already have one saved
998 then first write it out */
1001 /* assemble first instruction and save it */
1002 prev_insn
= do_assemble (str
, &prev_opcode
);
1003 if (prev_insn
== -1)
1004 as_fatal ("can't find opcode ");
1005 fixups
= fixups
->next
;
1010 insn
= do_assemble (str
, &opcode
);
1018 as_fatal ("can't find opcode ");
1027 /* if this is a long instruction, write it and any previous short instruction */
1028 if (opcode
->format
& LONG_OPCODE
)
1031 as_fatal("Unable to mix instructions as specified");
1033 write_long (opcode
, insn
, fixups
);
1038 if (prev_opcode
&& prev_seg
&& ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1041 if (prev_opcode
&& (write_2_short (prev_opcode
, prev_insn
, opcode
, insn
, extype
, fixups
) == 0))
1043 /* no instructions saved */
1049 as_fatal("Unable to mix instructions as specified");
1050 /* save off last instruction so it may be packed on next pass */
1051 prev_opcode
= opcode
;
1054 prev_subseg
= now_subseg
;
1055 fixups
= fixups
->next
;
1060 /* do_assemble assembles a single instruction and returns an opcode */
1061 /* it returns -1 (an invalid opcode) on error */
1063 static unsigned long
1064 do_assemble (str
, opcode
)
1066 struct d10v_opcode
**opcode
;
1068 unsigned char *op_start
, *save
;
1069 unsigned char *op_end
;
1072 expressionS myops
[6];
1075 /* Drop leading whitespace */
1079 /* find the opcode end */
1080 for (op_start
= op_end
= (unsigned char *) (str
);
1083 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1086 name
[nlen
] = tolower(op_start
[nlen
]);
1094 /* find the first opcode with the proper name */
1095 *opcode
= (struct d10v_opcode
*)hash_find (d10v_hash
, name
);
1096 if (*opcode
== NULL
)
1097 as_fatal ("unknown opcode: %s",name
);
1099 save
= input_line_pointer
;
1100 input_line_pointer
= op_end
;
1101 *opcode
= find_opcode (*opcode
, myops
);
1104 input_line_pointer
= save
;
1106 insn
= build_insn ((*opcode
), myops
, 0);
1110 /* find_opcode() gets a pointer to an entry in the opcode table. */
1111 /* It must look at all opcodes with the same name and use the operands */
1112 /* to choose the correct opcode. */
1114 static struct d10v_opcode
*
1115 find_opcode (opcode
, myops
)
1116 struct d10v_opcode
*opcode
;
1117 expressionS myops
[];
1120 struct d10v_opcode
*next_opcode
;
1122 /* get all the operands and save them as expressions */
1123 get_operands (myops
);
1125 /* now see if the operand is a fake. If so, find the correct size */
1126 /* instruction, if possible */
1127 if (opcode
->format
== OPCODE_FAKE
)
1129 int opnum
= opcode
->operands
[0];
1132 if (myops
[opnum
].X_op
== O_register
)
1134 myops
[opnum
].X_op
= O_symbol
;
1135 myops
[opnum
].X_add_symbol
= symbol_find_or_make ((char *)myops
[opnum
].X_op_symbol
);
1136 myops
[opnum
].X_add_number
= 0;
1137 myops
[opnum
].X_op_symbol
= NULL
;
1140 next_opcode
=opcode
+1;
1142 /* If the first operand is supposed to be a register, make sure
1143 we got a valid one. */
1144 flags
= d10v_operands
[next_opcode
->operands
[0]].flags
;
1145 if (flags
& OPERAND_REG
)
1147 int X_op
= myops
[0].X_op
;
1148 int num
= myops
[0].X_add_number
;
1150 if (X_op
!= O_register
1152 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1153 | OPERAND_FFLAG
| OPERAND_CFLAG
| OPERAND_CONTROL
)))
1155 as_bad ("bad opcode or operands");
1160 if (myops
[opnum
].X_op
== O_constant
|| (myops
[opnum
].X_op
== O_symbol
&&
1161 S_IS_DEFINED(myops
[opnum
].X_add_symbol
) &&
1162 (S_GET_SEGMENT(myops
[opnum
].X_add_symbol
) == now_seg
)))
1164 for (i
=0; opcode
->operands
[i
+1]; i
++)
1166 int bits
= d10v_operands
[next_opcode
->operands
[opnum
]].bits
;
1167 int flags
= d10v_operands
[next_opcode
->operands
[opnum
]].flags
;
1168 if (flags
& OPERAND_ADDR
)
1170 if (myops
[opnum
].X_op
== O_constant
)
1172 if (!check_range (myops
[opnum
].X_add_number
, bits
, flags
))
1179 /* calculate the current address by running through the previous frags */
1180 /* and adding our current offset */
1181 for (value
= 0, f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1182 value
+= f
->fr_fix
+ f
->fr_offset
;
1184 if (flags
& OPERAND_ADDR
)
1185 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
) - value
-
1186 (obstack_next_free(&frchain_now
->frch_obstack
) - frag_now
->fr_literal
);
1188 value
= S_GET_VALUE(myops
[opnum
].X_add_symbol
);
1190 if (AT_WORD_P (&myops
[opnum
]))
1195 if (!check_range (value
, bits
, flags
))
1199 else if (!check_range (value
, bits
, flags
))
1204 as_fatal ("value out of range");
1208 /* not a constant, so use a long instruction */
1215 /* now search the opcode table table for one with operands */
1216 /* that matches what we've got */
1220 for (i
= 0; opcode
->operands
[i
]; i
++)
1222 int flags
= d10v_operands
[opcode
->operands
[i
]].flags
;
1223 int X_op
= myops
[i
].X_op
;
1224 int num
= myops
[i
].X_add_number
;
1232 if (flags
& OPERAND_REG
)
1234 if ((X_op
!= O_register
)
1236 & (OPERAND_GPR
| OPERAND_ACC0
| OPERAND_ACC1
1237 | OPERAND_FFLAG
| OPERAND_CFLAG
1238 | OPERAND_CONTROL
)))
1245 if (((flags
& OPERAND_MINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_MINUS
))) ||
1246 ((flags
& OPERAND_PLUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_PLUS
))) ||
1247 ((flags
& OPERAND_ATMINUS
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATMINUS
))) ||
1248 ((flags
& OPERAND_ATPAR
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATPAR
))) ||
1249 ((flags
& OPERAND_ATSIGN
) && ((X_op
!= O_absent
) || (num
!= OPERAND_ATSIGN
))))
1255 /* we're only done if the operands matched so far AND there
1256 are no more to check */
1257 if (match
&& myops
[i
].X_op
==0)
1262 next_opcode
= opcode
+1;
1263 if (next_opcode
->opcode
== 0)
1265 if (strcmp(next_opcode
->name
, opcode
->name
))
1267 opcode
= next_opcode
;
1273 as_bad ("bad opcode or operands");
1277 /* Check that all registers that are required to be even are. */
1278 /* Also, if any operands were marked as registers, but were really symbols */
1279 /* fix that here. */
1280 for (i
=0; opcode
->operands
[i
]; i
++)
1282 if ((d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_EVEN
) &&
1283 (myops
[i
].X_add_number
& 1))
1284 as_fatal("Register number must be EVEN");
1285 if (myops
[i
].X_op
== O_register
)
1287 if (!(d10v_operands
[opcode
->operands
[i
]].flags
& OPERAND_REG
))
1289 myops
[i
].X_op
= O_symbol
;
1290 myops
[i
].X_add_symbol
= symbol_find_or_make ((char *)myops
[i
].X_op_symbol
);
1291 myops
[i
].X_add_number
= 0;
1292 myops
[i
].X_op_symbol
= NULL
;
1299 /* if while processing a fixup, a reloc really needs to be created */
1300 /* then it is done here */
1303 tc_gen_reloc (seg
, fixp
)
1308 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1309 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1310 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1311 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1312 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1314 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1315 "reloc %d not supported by object file format", (int)fixp
->fx_r_type
);
1318 reloc
->addend
= fixp
->fx_addnumber
;
1323 md_estimate_size_before_relax (fragp
, seg
)
1332 md_pcrel_from_section (fixp
, sec
)
1336 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1337 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1339 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1343 md_apply_fix3 (fixp
, valuep
, seg
)
1354 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1359 else if (fixp
->fx_pcrel
)
1363 value
= fixp
->fx_offset
;
1364 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1366 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1367 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1370 /* We don't actually support subtracting a symbol. */
1371 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1372 "expression too complex");
1377 op_type
= fixp
->fx_r_type
;
1384 fixp
->fx_r_type
= BFD_RELOC_D10V_10_PCREL_L
;
1387 else if (op_type
& 4096)
1390 fixp
->fx_r_type
= BFD_RELOC_D10V_18
;
1393 fixp
->fx_r_type
= get_reloc((struct d10v_operand
*)&d10v_operands
[op_type
]);
1396 /* Fetch the instruction, insert the fully resolved operand
1397 value, and stuff the instruction back again. */
1398 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1399 insn
= bfd_getb32 ((unsigned char *) where
);
1401 switch (fixp
->fx_r_type
)
1403 case BFD_RELOC_D10V_10_PCREL_L
:
1404 case BFD_RELOC_D10V_10_PCREL_R
:
1405 case BFD_RELOC_D10V_18_PCREL
:
1406 case BFD_RELOC_D10V_18
:
1407 /* instruction addresses are always right-shifted by 2 */
1408 value
>>= AT_WORD_RIGHT_SHIFT
;
1409 if (fixp
->fx_size
== 2)
1410 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1413 insn
= d10v_insert_operand (insn
, op_type
, (offsetT
)value
, left
, fixp
);
1414 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1418 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1421 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1424 as_fatal ("line %d: unknown relocation type: 0x%x",fixp
->fx_line
,fixp
->fx_r_type
);
1429 /* d10v_cleanup() is called after the assembler has finished parsing the input
1430 file or after a label is defined. Because the D10V assembler sometimes saves short
1431 instructions to see if it can package them with the next instruction, there may
1432 be a short instruction that still needs written. */
1442 subseg
= now_subseg
;
1443 subseg_set (prev_seg
, prev_subseg
);
1444 write_1_short (prev_opcode
, prev_insn
, fixups
->next
);
1445 subseg_set (seg
, subseg
);
1451 /* Like normal .word, except support @word */
1452 /* clobbers input_line_pointer, checks end-of-line. */
1454 d10v_dot_word (nbytes
)
1455 register int nbytes
; /* 1=.byte, 2=.word, 4=.long */
1458 bfd_reloc_code_real_type reloc
;
1462 if (is_it_end_of_statement ())
1464 demand_empty_rest_of_line ();
1471 if (!strncasecmp (input_line_pointer
, "@word", 5))
1473 exp
.X_add_number
= 0;
1474 input_line_pointer
+= 5;
1477 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
1478 &exp
, 0, BFD_RELOC_D10V_18
);
1481 emit_expr (&exp
, 2);
1483 while (*input_line_pointer
++ == ',');
1485 input_line_pointer
--; /* Put terminator back into stream. */
1486 demand_empty_rest_of_line ();
1490 /* Mitsubishi asked that we support some old syntax that apparently */
1491 /* had immediate operands starting with '#'. This is in some of their */
1492 /* sample code but is not documented (although it appears in some */
1493 /* examples in their assembler manual). For now, we'll solve this */
1494 /* compatibility problem by simply ignoring any '#' at the beginning */
1495 /* of an operand. */
1497 /* operands that begin with '#' should fall through to here */
1501 md_operand (expressionP
)
1502 expressionS
*expressionP
;
1504 if (*input_line_pointer
== '#')
1506 input_line_pointer
++;
1507 expression (expressionP
);