1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2 Copyright (C) 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "opcode/d30v.h"
27 const char comment_chars
[] = ";";
28 const char line_comment_chars
[] = "#";
29 const char line_separator_chars
[] = "";
30 const char *md_shortopts
= "OnNcC";
31 const char EXP_CHARS
[] = "eE";
32 const char FLT_CHARS
[] = "dD";
34 #define NOP_MULTIPLY 1
36 static int warn_nops
= 0;
37 static int Optimizing
= 0;
38 static int warn_register_name_conflicts
= 1;
44 typedef enum _exec_type
46 EXEC_UNKNOWN
, /* no order specified */
47 EXEC_PARALLEL
, /* done in parallel (FM=00) */
48 EXEC_SEQ
, /* sequential (FM=01) */
49 EXEC_REVSEQ
/* reverse sequential (FM=10) */
53 #define MAX_INSN_FIXUPS (5)
60 bfd_reloc_code_real_type reloc
;
63 typedef struct _fixups
66 struct d30v_fixup fix
[MAX_INSN_FIXUPS
];
70 static Fixups FixUps
[2];
71 static Fixups
*fixups
;
73 /* Whether current and previous instruction are word multiply insns. */
74 static int cur_mul32_p
= 0;
75 static int prev_mul32_p
= 0;
77 /* The flag_explicitly_parallel is true iff the instruction being assembled
78 has been explicitly written as a parallel short-instruction pair by the
79 human programmer. It is used in parallel_ok() to distinguish between
80 those dangerous parallelizations attempted by the human, which are to be
81 allowed, and those attempted by the assembler, which are not. It is set
82 from md_assemble(). */
83 static int flag_explicitly_parallel
= 0;
84 static int flag_xp_state
= 0;
86 /* Whether current and previous left sub-instruction disables
87 execution of right sub-instruction. */
88 static int cur_left_kills_right_p
= 0;
89 static int prev_left_kills_right_p
= 0;
91 /* The known current alignment of the current section. */
92 static int d30v_current_align
;
93 static segT d30v_current_align_seg
;
95 /* The last seen label in the current section. This is used to auto-align
96 labels preceeding instructions. */
97 static symbolS
*d30v_last_label
;
100 #define NOP_LEFT ((long long) NOP << 32)
101 #define NOP_RIGHT ((long long) NOP)
102 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
104 /* local functions */
105 static int reg_name_search
PARAMS ((char *name
));
106 static int register_name
PARAMS ((expressionS
*expressionP
));
107 static int check_range
PARAMS ((unsigned long num
, int bits
, int flags
));
108 static int postfix
PARAMS ((char *p
));
109 static bfd_reloc_code_real_type get_reloc
PARAMS ((struct d30v_operand
*op
, int rel_flag
));
110 static int get_operands
PARAMS ((expressionS exp
[], int cmp_hack
));
111 static struct d30v_format
*find_format
PARAMS ((struct d30v_opcode
*opcode
,
112 expressionS ops
[],int fsize
, int cmp_hack
));
113 static long long build_insn
PARAMS ((struct d30v_insn
*opcode
, expressionS
*opers
));
114 static void write_long
PARAMS ((struct d30v_insn
*opcode
, long long insn
, Fixups
*fx
));
115 static void write_1_short
PARAMS ((struct d30v_insn
*opcode
, long long insn
,
116 Fixups
*fx
, int use_sequential
));
117 static int write_2_short
PARAMS ((struct d30v_insn
*opcode1
, long long insn1
,
118 struct d30v_insn
*opcode2
, long long insn2
, exec_type_enum exec_type
, Fixups
*fx
));
119 static long long do_assemble
PARAMS ((char *str
, struct d30v_insn
*opcode
,
120 int shortp
, int is_parallel
));
121 static int parallel_ok
PARAMS ((struct d30v_insn
*opcode1
, unsigned long insn1
,
122 struct d30v_insn
*opcode2
, unsigned long insn2
,
123 exec_type_enum exec_type
));
124 static void d30v_number_to_chars
PARAMS ((char *buf
, long long value
, int nbytes
));
125 static void check_size
PARAMS ((long value
, int bits
, char *file
, int line
));
126 static void d30v_align
PARAMS ((int, char *, symbolS
*));
127 static void s_d30v_align
PARAMS ((int));
128 static void s_d30v_text
PARAMS ((int));
129 static void s_d30v_data
PARAMS ((int));
130 static void s_d30v_section
PARAMS ((int));
132 struct option md_longopts
[] = {
133 {NULL
, no_argument
, NULL
, 0}
135 size_t md_longopts_size
= sizeof(md_longopts
);
138 /* The target specific pseudo-ops which we support. */
139 const pseudo_typeS md_pseudo_table
[] =
142 { "hword", cons
, 2 },
143 { "align", s_d30v_align
, 0 },
144 { "text", s_d30v_text
, 0 },
145 { "data", s_d30v_data
, 0 },
146 { "section", s_d30v_section
, 0 },
147 { "section.s", s_d30v_section
, 0 },
148 { "sect", s_d30v_section
, 0 },
149 { "sect.s", s_d30v_section
, 0 },
153 /* Opcode hash table. */
154 static struct hash_control
*d30v_hash
;
156 /* reg_name_search does a binary search of the pre_defined_registers
157 array to see if "name" is a valid regiter name. Returns the register
158 number from the array on success, or -1 on failure. */
161 reg_name_search (name
)
164 int middle
, low
, high
;
168 high
= reg_name_cnt () - 1;
172 middle
= (low
+ high
) / 2;
173 cmp
= strcasecmp (name
, pre_defined_registers
[middle
].name
);
180 if (symbol_find (name
) != NULL
)
182 if (warn_register_name_conflicts
)
183 as_warn (_("Register name %s conflicts with symbol of the same name"),
187 return pre_defined_registers
[middle
].value
;
195 /* register_name() checks the string at input_line_pointer
196 to see if it is a valid register name. */
199 register_name (expressionP
)
200 expressionS
*expressionP
;
203 char c
, *p
= input_line_pointer
;
205 while (*p
&& *p
!='\n' && *p
!='\r' && *p
!=',' && *p
!=' ' && *p
!=')')
212 /* look to see if it's in the register table */
213 reg_number
= reg_name_search (input_line_pointer
);
216 expressionP
->X_op
= O_register
;
217 /* temporarily store a pointer to the string here */
218 expressionP
->X_op_symbol
= (symbolS
*)input_line_pointer
;
219 expressionP
->X_add_number
= reg_number
;
220 input_line_pointer
= p
;
230 check_range (num
, bits
, flags
)
238 /* don't bother checking 32-bit values */
242 if (flags
& OPERAND_SHIFT
)
244 /* We know that all shifts are right by three bits.... */
246 if (flags
& OPERAND_SIGNED
)
247 num
= (unsigned long) (((/*signed*/ long) num
) >> 3);
252 if (flags
& OPERAND_SIGNED
)
254 max
= (1 << (bits
- 1))-1;
255 min
= - (1 << (bits
- 1));
256 if (((long)num
> max
) || ((long)num
< min
))
261 max
= (1 << bits
) - 1;
263 if ((num
> max
) || (num
< min
))
272 md_show_usage (stream
)
275 fprintf (stream
, _("\nD30V options:\n\
276 -O Make adjacent short instructions parallel if possible.\n\
277 -n Warn about all NOPs inserted by the assembler.\n\
278 -N Warn about NOPs inserted after word multiplies.\n\
279 -c Warn about symbols whoes names match register names.\n\
280 -C Opposite of -C. -c is the default.\n"));
284 md_parse_option (c
, arg
)
290 /* Optimize. Will attempt to parallelize operations */
295 /* Warn about all NOPS that the assembler inserts. */
300 /* Warn about the NOPS that the assembler inserts because of the
303 warn_nops
= NOP_MULTIPLY
;
307 warn_register_name_conflicts
= 1;
311 warn_register_name_conflicts
= 0;
321 md_undefined_symbol (name
)
327 /* Turn a string in input_line_pointer into a floating point constant of type
328 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
329 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
332 md_atof (type
, litP
, sizeP
)
338 LITTLENUM_TYPE words
[4];
352 return _("bad call to md_atof");
355 t
= atof_ieee (input_line_pointer
, type
, words
);
357 input_line_pointer
= t
;
361 for (i
= 0; i
< prec
; i
++)
363 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
370 md_convert_frag (abfd
, sec
, fragP
)
379 md_section_align (seg
, addr
)
383 int align
= bfd_get_section_alignment (stdoutput
, seg
);
384 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
391 struct d30v_opcode
* opcode
;
392 d30v_hash
= hash_new ();
394 /* Insert opcode names into a hash table. */
395 for (opcode
= (struct d30v_opcode
*)d30v_opcode_table
; opcode
->name
; opcode
++)
396 hash_insert (d30v_hash
, opcode
->name
, (char *) opcode
);
399 FixUps
[0].next
= &FixUps
[1];
400 FixUps
[1].next
= &FixUps
[0];
402 d30v_current_align_seg
= now_seg
;
406 /* this function removes the postincrement or postdecrement
407 operator ( '+' or '-' ) from an expression */
409 static int postfix (p
)
412 while (*p
!= '-' && *p
!= '+')
414 if (*p
==0 || *p
=='\n' || *p
=='\r' || *p
==' ' || *p
==',')
434 static bfd_reloc_code_real_type
435 get_reloc (op
, rel_flag
)
436 struct d30v_operand
*op
;
442 if (op
->flags
& OPERAND_SHIFT
)
443 return BFD_RELOC_D30V_9_PCREL
;
445 return BFD_RELOC_D30V_6
;
448 if (!(op
->flags
& OPERAND_SHIFT
))
449 as_warn (_("unexpected 12-bit reloc type"));
450 if (rel_flag
== RELOC_PCREL
)
451 return BFD_RELOC_D30V_15_PCREL
;
453 return BFD_RELOC_D30V_15
;
455 if (!(op
->flags
& OPERAND_SHIFT
))
456 as_warn (_("unexpected 18-bit reloc type"));
457 if (rel_flag
== RELOC_PCREL
)
458 return BFD_RELOC_D30V_21_PCREL
;
460 return BFD_RELOC_D30V_21
;
462 if (rel_flag
== RELOC_PCREL
)
463 return BFD_RELOC_D30V_32_PCREL
;
465 return BFD_RELOC_D30V_32
;
471 /* get_operands parses a string of operands and returns
472 an array of expressions */
475 get_operands (exp
, cmp_hack
)
479 char *p
= input_line_pointer
;
485 exp
[numops
].X_op
= O_absent
;
486 exp
[numops
++].X_add_number
= cmp_hack
- 1;
491 while (*p
== ' ' || *p
== '\t' || *p
== ',')
493 if (*p
==0 || *p
=='\n' || *p
=='\r')
499 exp
[numops
].X_op
= O_absent
;
503 exp
[numops
].X_add_number
= OPERAND_ATPAR
;
509 exp
[numops
].X_add_number
= OPERAND_ATMINUS
;
513 exp
[numops
].X_add_number
= OPERAND_ATSIGN
;
522 /* just skip the trailing paren */
527 input_line_pointer
= p
;
529 /* check to see if it might be a register name */
530 if (!register_name (&exp
[numops
]))
532 /* parse as an expression */
533 expression (&exp
[numops
]);
536 if (exp
[numops
].X_op
== O_illegal
)
537 as_bad (_("illegal operand"));
538 else if (exp
[numops
].X_op
== O_absent
)
539 as_bad (_("missing operand"));
542 p
= input_line_pointer
;
546 case -1: /* postdecrement mode */
547 exp
[numops
].X_op
= O_absent
;
548 exp
[numops
++].X_add_number
= OPERAND_MINUS
;
550 case 1: /* postincrement mode */
551 exp
[numops
].X_op
= O_absent
;
552 exp
[numops
++].X_add_number
= OPERAND_PLUS
;
558 exp
[numops
].X_op
= 0;
562 /* build_insn generates the instruction. It does everything */
563 /* but write the FM bits. */
566 build_insn (opcode
, opers
)
567 struct d30v_insn
*opcode
;
570 int i
, length
, bits
, shift
, flags
;
571 unsigned int number
, id
=0;
573 struct d30v_opcode
*op
= opcode
->op
;
574 struct d30v_format
*form
= opcode
->form
;
576 insn
= opcode
->ecc
<< 28 | op
->op1
<< 25 | op
->op2
<< 20 | form
->modifier
<< 18;
578 for (i
=0; form
->operands
[i
]; i
++)
580 flags
= d30v_operand_table
[form
->operands
[i
]].flags
;
582 /* must be a register or number */
583 if (!(flags
& OPERAND_REG
) && !(flags
& OPERAND_NUM
) &&
584 !(flags
& OPERAND_NAME
) && !(flags
& OPERAND_SPECIAL
))
587 bits
= d30v_operand_table
[form
->operands
[i
]].bits
;
588 if (flags
& OPERAND_SHIFT
)
591 length
= d30v_operand_table
[form
->operands
[i
]].length
;
592 shift
= 12 - d30v_operand_table
[form
->operands
[i
]].position
;
593 if (opers
[i
].X_op
!= O_symbol
)
594 number
= opers
[i
].X_add_number
;
597 if (flags
& OPERAND_REG
)
599 /* check for mvfsys or mvtsys control registers */
600 if (flags
& OPERAND_CONTROL
&& (number
& 0x7f) > MAX_CONTROL_REG
)
603 id
= (number
& 0x7f) - MAX_CONTROL_REG
;
606 else if (number
& OPERAND_FLAG
)
608 id
= 3; /* number is a flag register */
612 else if (flags
& OPERAND_SPECIAL
)
617 if (opers
[i
].X_op
!= O_register
&& opers
[i
].X_op
!= O_constant
&& !(flags
& OPERAND_NAME
))
619 /* now create a fixup */
621 if (fixups
->fc
>= MAX_INSN_FIXUPS
)
622 as_fatal (_("too many fixups"));
624 fixups
->fix
[fixups
->fc
].reloc
=
625 get_reloc ((struct d30v_operand
*)&d30v_operand_table
[form
->operands
[i
]], op
->reloc_flag
);
626 fixups
->fix
[fixups
->fc
].size
= 4;
627 fixups
->fix
[fixups
->fc
].exp
= opers
[i
];
628 fixups
->fix
[fixups
->fc
].operand
= form
->operands
[i
];
629 if (fixups
->fix
[fixups
->fc
].reloc
== BFD_RELOC_D30V_9_PCREL
)
630 fixups
->fix
[fixups
->fc
].pcrel
= RELOC_PCREL
;
632 fixups
->fix
[fixups
->fc
].pcrel
= op
->reloc_flag
;
636 /* truncate to the proper number of bits */
637 if ((opers
[i
].X_op
== O_constant
) && check_range (number
, bits
, flags
))
638 as_bad (_("operand out of range: %d"),number
);
640 number
&= 0x7FFFFFFF >> (31 - bits
);
641 if (flags
& OPERAND_SHIFT
)
645 /* it's a LONG instruction */
646 insn
|= (number
>> 26); /* top 6 bits */
647 insn
<<= 32; /* shift the first word over */
648 insn
|= ((number
& 0x03FC0000) << 2); /* next 8 bits */
649 insn
|= number
& 0x0003FFFF; /* bottom 18 bits */
652 insn
|= number
<< shift
;
658 /* write out a long form instruction */
660 write_long (opcode
, insn
, fx
)
661 struct d30v_insn
*opcode
;
666 char *f
= frag_more (8);
669 d30v_number_to_chars (f
, insn
, 8);
671 for (i
=0; i
< fx
->fc
; i
++)
673 if (fx
->fix
[i
].reloc
)
675 where
= f
- frag_now
->fr_literal
;
676 fix_new_exp (frag_now
,
688 /* Write out a short form instruction by itself. */
690 write_1_short (opcode
, insn
, fx
, use_sequential
)
691 struct d30v_insn
*opcode
;
696 char *f
= frag_more (8);
699 if (warn_nops
== NOP_ALL
)
700 as_warn (_("%s NOP inserted"), use_sequential
?
701 _("sequential") : _("parallel"));
703 /* The other container needs to be NOP. */
706 /* Use a sequential NOP rather than a parallel one,
707 as the current instruction is a FLAG_MUL32 type one
708 and the next instruction is a load. */
710 /* According to 4.3.1: for FM=01, sub-instructions performed
711 only by IU cannot be encoded in L-container. */
713 if (opcode
->op
->unit
== IU
)
714 insn
|= FM10
| NOP_LEFT
; /* right then left */
716 insn
= FM01
| (insn
<< 32) | NOP_RIGHT
; /* left then right */
720 /* According to 4.3.1: for FM=00, sub-instructions performed
721 only by IU cannot be encoded in L-container. */
723 if (opcode
->op
->unit
== IU
)
724 insn
|= FM00
| NOP_LEFT
; /* right container */
726 insn
= FM00
| (insn
<< 32) | NOP_RIGHT
; /* left container */
729 d30v_number_to_chars (f
, insn
, 8);
731 for (i
=0; i
< fx
->fc
; i
++)
733 if (fx
->fix
[i
].reloc
)
735 where
= f
- frag_now
->fr_literal
;
736 fix_new_exp (frag_now
,
747 /* Write out a short form instruction if possible.
748 Return number of instructions not written out. */
750 write_2_short (opcode1
, insn1
, opcode2
, insn2
, exec_type
, fx
)
751 struct d30v_insn
*opcode1
, *opcode2
;
752 long long insn1
, insn2
;
753 exec_type_enum exec_type
;
756 long long insn
= NOP2
;
760 if (exec_type
== EXEC_SEQ
761 && (opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
))
762 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
763 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
765 /* Unconditional, non-delayed branches kill instructions in
766 the right bin. Conditional branches don't always but if
767 we are not optimizing, then we have been asked to produce
768 an error about such constructs. For the purposes of this
769 test, subroutine calls are considered to be branches. */
770 write_1_short (opcode1
, insn1
, fx
->next
, false);
774 /* Note: we do not have to worry about subroutine calls occuring
775 in the right hand container. The return address is always
776 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
780 case EXEC_UNKNOWN
: /* Order not specified. */
782 && parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
)
783 && ! ( (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
784 || opcode1
->op
->unit
== MU
)
786 ( opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
787 || opcode2
->op
->unit
== MU
)))
790 exec_type
= EXEC_PARALLEL
;
792 if (opcode1
->op
->unit
== IU
793 || opcode2
->op
->unit
== MU
794 || opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
795 insn
= FM00
| (insn2
<< 32) | insn1
;
798 insn
= FM00
| (insn1
<< 32) | insn2
;
802 else if ((opcode1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)
803 && ((opcode1
->op
->flags_used
& FLAG_DELAY
) == 0)
804 && ((opcode1
->ecc
== ECC_AL
) || ! Optimizing
))
805 || opcode1
->op
->flags_used
& FLAG_RP
)
807 /* We must emit (non-delayed) branch type instructions
808 on their own with nothing in the right container. */
809 /* We must treat repeat instructions likewise, since the
810 following instruction has to be separate from the repeat
811 in order to be repeated. */
812 write_1_short (opcode1
, insn1
, fx
->next
, false);
815 else if (prev_left_kills_right_p
)
817 /* The left instruction kils the right slot, so we
818 must leave it empty. */
819 write_1_short (opcode1
, insn1
, fx
->next
, false);
822 else if (opcode1
->op
->unit
== IU
823 || (opcode1
->op
->unit
== EITHER
824 && opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
))
826 /* reverse sequential */
827 insn
= FM10
| (insn2
<< 32) | insn1
;
828 exec_type
= EXEC_REVSEQ
;
833 insn
= FM01
| (insn1
<< 32) | insn2
;
835 exec_type
= EXEC_SEQ
;
839 case EXEC_PARALLEL
: /* parallel */
840 flag_explicitly_parallel
= flag_xp_state
;
841 if (! parallel_ok (opcode1
, insn1
, opcode2
, insn2
, exec_type
))
842 as_bad (_("Instructions may not be executed in parallel"));
843 else if (opcode1
->op
->unit
== IU
)
845 if (opcode2
->op
->unit
== IU
)
846 as_bad (_("Two IU instructions may not be executed in parallel"));
847 as_warn (_("Swapping instruction order"));
848 insn
= FM00
| (insn2
<< 32) | insn1
;
850 else if (opcode2
->op
->unit
== MU
)
852 if (opcode1
->op
->unit
== MU
)
853 as_bad (_("Two MU instructions may not be executed in parallel"));
854 else if (opcode1
->op
->unit
== EITHER_BUT_PREFER_MU
)
855 as_warn (_("Executing %s in IU may not work"), opcode1
->op
->name
);
856 as_warn (_("Swapping instruction order"));
857 insn
= FM00
| (insn2
<< 32) | insn1
;
861 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
862 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
864 insn
= FM00
| (insn1
<< 32) | insn2
;
867 flag_explicitly_parallel
= 0;
870 case EXEC_SEQ
: /* sequential */
871 if (opcode1
->op
->unit
== IU
)
872 as_bad (_("IU instruction may not be in the left container"));
873 if (prev_left_kills_right_p
)
874 as_bad (_("special left instruction `%s' kills instruction "
875 "`%s' in right container"),
876 opcode1
->op
->name
, opcode2
->op
->name
);
877 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
878 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
879 insn
= FM01
| (insn1
<< 32) | insn2
;
883 case EXEC_REVSEQ
: /* reverse sequential */
884 if (opcode2
->op
->unit
== MU
)
885 as_bad (_("MU instruction may not be in the right container"));
886 if (opcode2
->op
->unit
== EITHER_BUT_PREFER_MU
)
887 as_warn (_("Executing %s in IU may not work"), opcode2
->op
->name
);
888 insn
= FM10
| (insn1
<< 32) | insn2
;
893 as_fatal (_("unknown execution type passed to write_2_short()"));
896 /* printf ("writing out %llx\n",insn); */
898 d30v_number_to_chars (f
, insn
, 8);
900 /* If the previous instruction was a 32-bit multiply but it is put into a
901 parallel container, mark the current instruction as being a 32-bit
903 if (prev_mul32_p
&& exec_type
== EXEC_PARALLEL
)
908 for (i
=0; i
< fx
->fc
; i
++)
910 if (fx
->fix
[i
].reloc
)
912 where
= (f
- frag_now
->fr_literal
) + 4*j
;
914 fix_new_exp (frag_now
,
931 /* Check 2 instructions and determine if they can be safely */
932 /* executed in parallel. Returns 1 if they can be. */
934 parallel_ok (op1
, insn1
, op2
, insn2
, exec_type
)
935 struct d30v_insn
*op1
, *op2
;
936 unsigned long insn1
, insn2
;
937 exec_type_enum exec_type
;
939 int i
, j
, shift
, regno
, bits
, ecc
;
940 unsigned long flags
, mask
, flags_set1
, flags_set2
, flags_used1
, flags_used2
;
941 unsigned long ins
, mod_reg
[2][3], used_reg
[2][3], flag_reg
[2];
942 struct d30v_format
*f
;
943 struct d30v_opcode
*op
;
945 /* section 4.3: both instructions must not be IU or MU only */
946 if ((op1
->op
->unit
== IU
&& op2
->op
->unit
== IU
)
947 || (op1
->op
->unit
== MU
&& op2
->op
->unit
== MU
))
950 /* first instruction must not be a jump to safely optimize, unless this
951 is an explicit parallel operation. */
952 if (exec_type
!= EXEC_PARALLEL
953 && (op1
->op
->flags_used
& (FLAG_JMP
| FLAG_JSR
)))
956 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
957 then it is safe to allow the two to be done as parallel ops, since only
958 one will ever be executed at a time. */
959 if ((op1
->ecc
== ECC_TX
&& op2
->ecc
== ECC_FX
)
960 || (op1
->ecc
== ECC_FX
&& op2
->ecc
== ECC_TX
)
961 || (op1
->ecc
== ECC_XT
&& op2
->ecc
== ECC_XF
)
962 || (op1
->ecc
== ECC_XF
&& op2
->ecc
== ECC_XT
))
967 [2] a0, a1, flag registers */
969 for (j
= 0; j
< 2; j
++)
986 mod_reg
[j
][0] = mod_reg
[j
][1] = 0;
987 used_reg
[j
][0] = used_reg
[j
][1] = 0;
989 if (flag_explicitly_parallel
)
991 /* For human specified parallel instructions we have been asked
992 to ignore the possibility that both instructions could modify
993 bits in the PSW, so we initialise the mod & used arrays to 0.
994 We have been asked, however, to refuse to allow parallel
995 instructions which explicitly set the same flag register,
996 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
997 for the use of a flag register and set a bit in the mod or used
998 array appropriately. */
1005 mod_reg
[j
][2] = (op
->flags_set
& FLAG_ALL
);
1006 used_reg
[j
][2] = (op
->flags_used
& FLAG_ALL
);
1009 /* BSR/JSR always sets R62 */
1010 if (op
->flags_used
& FLAG_JSR
)
1011 mod_reg
[j
][1] = (1L << (62-32));
1013 /* conditional execution affects the flags_used */
1018 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_0
;
1023 used_reg
[j
][2] |= flag_reg
[j
] = FLAG_1
;
1028 used_reg
[j
][2] |= flag_reg
[j
] = (FLAG_0
| FLAG_1
);
1032 for (i
= 0; f
->operands
[i
]; i
++)
1034 flags
= d30v_operand_table
[f
->operands
[i
]].flags
;
1035 shift
= 12 - d30v_operand_table
[f
->operands
[i
]].position
;
1036 bits
= d30v_operand_table
[f
->operands
[i
]].bits
;
1040 mask
= 0x7FFFFFFF >> (31 - bits
);
1042 if ((flags
& OPERAND_PLUS
) || (flags
& OPERAND_MINUS
))
1044 /* this is a post-increment or post-decrement */
1045 /* the previous register needs to be marked as modified */
1047 shift
= 12 - d30v_operand_table
[f
->operands
[i
-1]].position
;
1048 regno
= (ins
>> shift
) & 0x3f;
1050 mod_reg
[j
][1] |= 1L << (regno
- 32);
1052 mod_reg
[j
][0] |= 1L << regno
;
1054 else if (flags
& OPERAND_REG
)
1056 regno
= (ins
>> shift
) & mask
;
1057 /* the memory write functions don't have a destination register */
1058 if ((flags
& OPERAND_DEST
) && !(op
->flags_set
& FLAG_MEM
))
1060 /* MODIFIED registers and flags */
1061 if (flags
& OPERAND_ACC
)
1064 mod_reg
[j
][2] |= FLAG_A0
;
1065 else if (regno
== 1)
1066 mod_reg
[j
][2] |= FLAG_A1
;
1070 else if (flags
& OPERAND_FLAG
)
1071 mod_reg
[j
][2] |= 1L << regno
;
1072 else if (!(flags
& OPERAND_CONTROL
))
1076 /* need to check if there are two destination */
1077 /* registers, for example ld2w */
1078 if (flags
& OPERAND_2REG
)
1083 for (r
= regno
; r
<= regno
+ z
; r
++)
1086 mod_reg
[j
][1] |= 1L << (r
- 32);
1088 mod_reg
[j
][0] |= 1L << r
;
1094 /* USED, but not modified registers and flags */
1095 if (flags
& OPERAND_ACC
)
1098 used_reg
[j
][2] |= FLAG_A0
;
1099 else if (regno
== 1)
1100 used_reg
[j
][2] |= FLAG_A1
;
1104 else if (flags
& OPERAND_FLAG
)
1105 used_reg
[j
][2] |= 1L << regno
;
1106 else if (!(flags
& OPERAND_CONTROL
))
1110 /* need to check if there are two source */
1111 /* registers, for example st2w */
1112 if (flags
& OPERAND_2REG
)
1117 for (r
= regno
; r
<= regno
+ z
; r
++)
1120 used_reg
[j
][1] |= 1L << (r
- 32);
1122 used_reg
[j
][0] |= 1L << r
;
1130 flags_set1
= op1
->op
->flags_set
;
1131 flags_set2
= op2
->op
->flags_set
;
1132 flags_used1
= op1
->op
->flags_used
;
1133 flags_used2
= op2
->op
->flags_used
;
1135 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
1136 if (((flags_set1
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1137 && (flags_used2
& FLAG_ADDSUBppp
) != 0)
1138 || ((flags_set2
& (FLAG_MEM
| FLAG_2WORD
)) == (FLAG_MEM
| FLAG_2WORD
)
1139 && (flags_used1
& FLAG_ADDSUBppp
) != 0))
1142 /* Load instruction combined with half-word multiply is illegal. */
1143 if (((flags_used1
& FLAG_MEM
) != 0 && (flags_used2
& FLAG_MUL16
))
1144 || ((flags_used2
& FLAG_MEM
) != 0 && (flags_used1
& FLAG_MUL16
)))
1147 /* Specifically allow add || add by removing carry, overflow bits dependency.
1148 This is safe, even if an addc follows since the IU takes the argument in
1149 the right container, and it writes its results last.
1150 However, don't paralellize add followed by addc or sub followed by
1153 if (mod_reg
[0][2] == FLAG_CVVA
&& mod_reg
[1][2] == FLAG_CVVA
1154 && (used_reg
[0][2] & ~flag_reg
[0]) == 0
1155 && (used_reg
[1][2] & ~flag_reg
[1]) == 0
1156 && op1
->op
->unit
== EITHER
&& op2
->op
->unit
== EITHER
)
1158 mod_reg
[0][2] = mod_reg
[1][2] = 0;
1161 for (j
= 0; j
< 3; j
++)
1163 /* If the second instruction depends on the first, we obviously
1164 cannot parallelize. Note, the mod flag implies use, so
1165 check that as well. */
1166 /* If flag_explicitly_parallel is set, then the case of the
1167 second instruction using a register the first instruction
1168 modifies is assumed to be okay; we trust the human. We
1169 don't trust the human if both instructions modify the same
1170 register but we do trust the human if they modify the same
1172 /* We have now been requested not to trust the human if the
1173 instructions modify the same flag registers either. */
1174 if (flag_explicitly_parallel
)
1176 if ((mod_reg
[0][j
] & mod_reg
[1][j
]) != 0)
1180 if ((mod_reg
[0][j
] & (mod_reg
[1][j
] | used_reg
[1][j
])) != 0)
1188 /* This is the main entry point for the machine-dependent assembler. str points to a
1189 machine-dependent instruction. This function is supposed to emit the frags/bytes
1190 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1191 and leaves the difficult stuff to do_assemble(). */
1193 static long long prev_insn
= -1;
1194 static struct d30v_insn prev_opcode
;
1195 static subsegT prev_subseg
;
1196 static segT prev_seg
= 0;
1202 struct d30v_insn opcode
;
1204 exec_type_enum extype
= EXEC_UNKNOWN
; /* execution type; parallel, etc */
1205 static exec_type_enum etype
= EXEC_UNKNOWN
; /* saved extype. used for multiline instructions */
1208 if ((prev_insn
!= -1) && prev_seg
1209 && ((prev_seg
!= now_seg
) || (prev_subseg
!= now_subseg
)))
1210 d30v_cleanup (false);
1212 if (d30v_current_align
< 3)
1213 d30v_align (3, NULL
, d30v_last_label
);
1214 else if (d30v_current_align
> 3)
1215 d30v_current_align
= 3;
1216 d30v_last_label
= NULL
;
1218 flag_explicitly_parallel
= 0;
1220 if (etype
== EXEC_UNKNOWN
)
1222 /* look for the special multiple instruction separators */
1223 str2
= strstr (str
, "||");
1226 extype
= EXEC_PARALLEL
;
1231 str2
= strstr (str
, "->");
1236 str2
= strstr (str
, "<-");
1238 extype
= EXEC_REVSEQ
;
1241 /* str2 points to the separator, if one */
1246 /* if two instructions are present and we already have one saved
1247 then first write it out */
1248 d30v_cleanup (false);
1250 /* Assemble first instruction and save it. */
1251 prev_insn
= do_assemble (str
, &prev_opcode
, 1, 0);
1252 if (prev_insn
== -1)
1253 as_bad (_("Cannot assemble instruction"));
1254 if (prev_opcode
.form
!= NULL
&& prev_opcode
.form
->form
>= LONG
)
1255 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1256 fixups
= fixups
->next
;
1259 prev_subseg
= now_subseg
;
1263 insn
= do_assemble (str
, &opcode
,
1264 (extype
!= EXEC_UNKNOWN
|| etype
!= EXEC_UNKNOWN
),
1265 extype
== EXEC_PARALLEL
);
1268 if (extype
!= EXEC_UNKNOWN
)
1270 as_bad (_("Cannot assemble instruction"));
1274 if (etype
!= EXEC_UNKNOWN
)
1277 etype
= EXEC_UNKNOWN
;
1280 /* Word multiply instructions must not be followed by either a load or a
1281 16-bit multiply instruction in the next cycle. */
1282 if ( (extype
!= EXEC_REVSEQ
)
1284 && (opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1286 /* However, load and multiply should able to be combined in a parallel
1287 operation, so check for that first. */
1289 && (opcode
.op
->flags_used
& FLAG_MEM
)
1290 && opcode
.form
->form
< LONG
1291 && (extype
== EXEC_PARALLEL
|| (Optimizing
&& extype
== EXEC_UNKNOWN
))
1292 && parallel_ok (&prev_opcode
, (long)prev_insn
,
1293 &opcode
, (long)insn
, extype
)
1294 && write_2_short (&prev_opcode
, (long)prev_insn
,
1295 &opcode
, (long)insn
, extype
, fixups
) == 0)
1297 /* no instructions saved */
1303 /* Can't parallelize, flush previous instruction and emit a word of NOPS,
1304 unless the previous instruction is a NOP, in which case just flush it,
1305 as this will generate a word of NOPs for us. */
1307 if (prev_insn
!= -1 && (strcmp (prev_opcode
.op
->name
, "nop") == 0))
1308 d30v_cleanup (false);
1313 if (prev_insn
!= -1)
1314 d30v_cleanup (true);
1318 d30v_number_to_chars (f
, NOP2
, 8);
1320 if (warn_nops
== NOP_ALL
|| warn_nops
== NOP_MULTIPLY
)
1322 if (opcode
.op
->flags_used
& FLAG_MEM
)
1323 as_warn (_("word of NOPs added between word multiply and load"));
1325 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1330 extype
= EXEC_UNKNOWN
;
1333 else if ( (extype
== EXEC_REVSEQ
)
1335 && (prev_opcode
.op
->flags_used
& (FLAG_MEM
| FLAG_MUL16
)))
1337 /* Can't parallelize, flush current instruction and add a sequential NOP. */
1338 write_1_short (& opcode
, (long) insn
, fixups
->next
->next
, true);
1340 /* Make the previous instruction the current one. */
1341 extype
= EXEC_UNKNOWN
;
1344 now_subseg
= prev_subseg
;
1346 cur_mul32_p
= prev_mul32_p
;
1348 memcpy (&opcode
, &prev_opcode
, sizeof (prev_opcode
));
1351 /* If this is a long instruction, write it and any previous short instruction. */
1352 if (opcode
.form
->form
>= LONG
)
1354 if (extype
!= EXEC_UNKNOWN
)
1355 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1356 d30v_cleanup (false);
1357 write_long (& opcode
, insn
, fixups
);
1360 else if ((prev_insn
!= -1)
1362 (& prev_opcode
, (long) prev_insn
, & opcode
,
1363 (long) insn
, extype
, fixups
) == 0))
1365 /* No instructions saved. */
1370 if (extype
!= EXEC_UNKNOWN
)
1371 as_bad (_("Unable to mix instructions as specified"));
1373 /* Save off last instruction so it may be packed on next pass. */
1374 memcpy (&prev_opcode
, &opcode
, sizeof (prev_opcode
));
1377 prev_subseg
= now_subseg
;
1378 fixups
= fixups
->next
;
1379 prev_mul32_p
= cur_mul32_p
;
1384 /* do_assemble assembles a single instruction and returns an opcode */
1385 /* it returns -1 (an invalid opcode) on error */
1387 #define NAME_BUF_LEN 20
1390 do_assemble (str
, opcode
, shortp
, is_parallel
)
1392 struct d30v_insn
*opcode
;
1396 unsigned char * op_start
;
1397 unsigned char * save
;
1398 unsigned char * op_end
;
1399 char name
[NAME_BUF_LEN
];
1402 int fsize
= (shortp
? FORCE_SHORT
: 0);
1403 expressionS myops
[6];
1406 /* Drop leading whitespace */
1407 while (* str
== ' ')
1410 /* find the opcode end */
1411 for (op_start
= op_end
= (unsigned char *) (str
);
1413 && nlen
< (NAME_BUF_LEN
- 1)
1415 && !is_end_of_line
[*op_end
] && *op_end
!= ' ';
1418 name
[nlen
] = tolower (op_start
[nlen
]);
1427 /* if there is an execution condition code, handle it */
1431 while ( (i
< ECC_MAX
) && strncasecmp (d30v_ecc_names
[i
], op_end
+ 1, 2))
1437 strncpy (tmp
, op_end
+ 1, 2);
1439 as_bad (_("unknown condition code: %s"),tmp
);
1442 /* printf ("condition code=%d\n",i); */
1447 opcode
->ecc
= ECC_AL
;
1450 /* CMP and CMPU change their name based on condition codes */
1451 if (!strncmp (name
, "cmp", 3))
1454 char **str
= (char **)d30v_cc_names
;
1460 for (i
=1; *str
&& strncmp (*str
, & name
[p
], 2); i
++, str
++)
1463 /* cmpu only supports some condition codes */
1469 as_bad (_("cmpu doesn't support condition code %s"),&name
[p
]);
1476 as_bad (_("unknown condition code: %s"),&name
[p
]);
1485 /* printf("cmp_hack=%d\n",cmp_hack); */
1487 /* need to look for .s or .l */
1488 if (name
[nlen
-2] == '.')
1490 switch (name
[nlen
-1])
1493 fsize
= FORCE_SHORT
;
1502 /* find the first opcode with the proper name */
1503 opcode
->op
= (struct d30v_opcode
*)hash_find (d30v_hash
, name
);
1504 if (opcode
->op
== NULL
)
1506 as_bad (_("unknown opcode: %s"),name
);
1510 save
= input_line_pointer
;
1511 input_line_pointer
= op_end
;
1512 while (!(opcode
->form
= find_format (opcode
->op
, myops
, fsize
, cmp_hack
)))
1515 if (opcode
->op
->name
== NULL
|| strcmp (opcode
->op
->name
, name
))
1517 as_bad (_("operands for opcode `%s' do not match any valid format"), name
);
1521 input_line_pointer
= save
;
1523 insn
= build_insn (opcode
, myops
);
1525 /* Propigate multiply status */
1528 if (is_parallel
&& prev_mul32_p
)
1532 prev_mul32_p
= cur_mul32_p
;
1533 cur_mul32_p
= (opcode
->op
->flags_used
& FLAG_MUL32
) != 0;
1537 /* Propagate left_kills_right status */
1540 prev_left_kills_right_p
= cur_left_kills_right_p
;
1542 if (opcode
->op
->flags_set
& FLAG_LKR
)
1544 cur_left_kills_right_p
= 1;
1546 if (strcmp (opcode
->op
->name
, "mvtsys") == 0)
1548 /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */
1549 if ((myops
[0].X_op
== O_register
) &&
1550 ((myops
[0].X_add_number
== OPERAND_CONTROL
) || /* psw */
1551 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+2) || /* pswh */
1552 (myops
[0].X_add_number
== OPERAND_CONTROL
+MAX_CONTROL_REG
+1) || /* pswl */
1553 (myops
[0].X_add_number
== OPERAND_FLAG
+0) || /* f0 */
1554 (myops
[0].X_add_number
== OPERAND_FLAG
+1) || /* f1 */
1555 (myops
[0].X_add_number
== OPERAND_FLAG
+2) || /* f2 */
1556 (myops
[0].X_add_number
== OPERAND_FLAG
+3) || /* f3 */
1557 (myops
[0].X_add_number
== OPERAND_FLAG
+4) || /* f4 */
1558 (myops
[0].X_add_number
== OPERAND_FLAG
+5) || /* f5 */
1559 (myops
[0].X_add_number
== OPERAND_FLAG
+6) || /* f6 */
1560 (myops
[0].X_add_number
== OPERAND_FLAG
+7))) /* f7 */
1562 cur_left_kills_right_p
= 1;
1566 /* Other mvtsys target registers don't kill right instruction. */
1567 cur_left_kills_right_p
= 0;
1572 cur_left_kills_right_p
= 0;
1579 /* find_format() gets a pointer to an entry in the format table.
1580 It must look at all formats for an opcode and use the operands
1581 to choose the correct one. Returns NULL on error. */
1583 static struct d30v_format
*
1584 find_format (opcode
, myops
, fsize
, cmp_hack
)
1585 struct d30v_opcode
*opcode
;
1586 expressionS myops
[];
1590 int numops
, match
, index
, i
=0, j
, k
;
1591 struct d30v_format
*fm
;
1596 /* Get all the operands and save them as expressions. */
1597 numops
= get_operands (myops
, cmp_hack
);
1599 while ((index
= opcode
->format
[i
++]) != 0)
1601 if (fsize
== FORCE_SHORT
&& index
>= LONG
)
1604 if (fsize
== FORCE_LONG
&& index
< LONG
)
1607 fm
= (struct d30v_format
*)&d30v_format_table
[index
];
1609 while (fm
->form
== index
)
1612 /* Now check the operands for compatibility. */
1613 for (j
= 0; match
&& fm
->operands
[j
]; j
++)
1615 int flags
= d30v_operand_table
[fm
->operands
[j
]].flags
;
1616 int bits
= d30v_operand_table
[fm
->operands
[j
]].bits
;
1617 int X_op
= myops
[j
].X_op
;
1618 int num
= myops
[j
].X_add_number
;
1620 if (flags
& OPERAND_SPECIAL
)
1622 else if (X_op
== O_illegal
)
1624 else if (flags
& OPERAND_REG
)
1626 if (X_op
!= O_register
1627 || ((flags
& OPERAND_ACC
) && !(num
& OPERAND_ACC
))
1628 || (!(flags
& OPERAND_ACC
) && (num
& OPERAND_ACC
))
1629 || ((flags
& OPERAND_FLAG
) && !(num
& OPERAND_FLAG
))
1630 || (!(flags
& (OPERAND_FLAG
| OPERAND_CONTROL
)) && (num
& OPERAND_FLAG
))
1631 || ((flags
& OPERAND_CONTROL
)
1632 && !(num
& (OPERAND_CONTROL
| OPERAND_FLAG
))))
1637 else if (((flags
& OPERAND_MINUS
)
1638 && (X_op
!= O_absent
|| num
!= OPERAND_MINUS
))
1639 || ((flags
& OPERAND_PLUS
)
1640 && (X_op
!= O_absent
|| num
!= OPERAND_PLUS
))
1641 || ((flags
& OPERAND_ATMINUS
)
1642 && (X_op
!= O_absent
|| num
!= OPERAND_ATMINUS
))
1643 || ((flags
& OPERAND_ATPAR
)
1644 && (X_op
!= O_absent
|| num
!= OPERAND_ATPAR
))
1645 || ((flags
& OPERAND_ATSIGN
)
1646 && (X_op
!= O_absent
|| num
!= OPERAND_ATSIGN
)))
1650 else if (flags
& OPERAND_NUM
)
1652 /* A number can be a constant or symbol expression. */
1654 /* If we have found a register name, but that name also
1655 matches a symbol, then re-parse the name as an expression. */
1656 if (X_op
== O_register
1657 && symbol_find ((char *) myops
[j
].X_op_symbol
))
1659 input_line_pointer
= (char *) myops
[j
].X_op_symbol
;
1660 expression (& myops
[j
]);
1663 /* Turn an expression into a symbol for later resolution. */
1664 if (X_op
!= O_absent
&& X_op
!= O_constant
1665 && X_op
!= O_symbol
&& X_op
!= O_register
1668 symbolS
*sym
= make_expr_symbol (&myops
[j
]);
1669 myops
[j
].X_op
= X_op
= O_symbol
;
1670 myops
[j
].X_add_symbol
= sym
;
1671 myops
[j
].X_add_number
= num
= 0;
1674 if (fm
->form
>= LONG
)
1676 /* If we're testing for a LONG format, either fits. */
1677 if (X_op
!= O_constant
&& X_op
!= O_symbol
)
1680 else if (fm
->form
< LONG
1681 && ((fsize
== FORCE_SHORT
&& X_op
== O_symbol
)
1682 || (fm
->form
== SHORT_D2
&& j
== 0)))
1684 /* This is the tricky part. Will the constant or symbol
1685 fit into the space in the current format? */
1686 else if (X_op
== O_constant
)
1688 if (check_range (num
, bits
, flags
))
1691 else if (X_op
== O_symbol
1692 && S_IS_DEFINED (myops
[j
].X_add_symbol
)
1693 && S_GET_SEGMENT (myops
[j
].X_add_symbol
) == now_seg
1694 && opcode
->reloc_flag
== RELOC_PCREL
)
1696 /* If the symbol is defined, see if the value will fit
1697 into the form we're considering. */
1701 /* Calculate the current address by running through the
1702 previous frags and adding our current offset. */
1704 for (f
= frchain_now
->frch_root
; f
; f
= f
->fr_next
)
1705 value
+= f
->fr_fix
+ f
->fr_offset
;
1706 value
= (S_GET_VALUE (myops
[j
].X_add_symbol
) - value
1707 - (obstack_next_free (&frchain_now
->frch_obstack
)
1708 - frag_now
->fr_literal
));
1709 if (check_range (value
, bits
, flags
))
1716 /* printf("through the loop: match=%d\n",match); */
1717 /* We're only done if the operands matched so far AND there
1718 are no more to check. */
1719 if (match
&& myops
[j
].X_op
== 0)
1721 /* Final check - issue a warning if an odd numbered register
1722 is used as the first register in an instruction that reads
1723 or writes 2 registers. */
1725 for (j
= 0; fm
->operands
[j
]; j
++)
1726 if (myops
[j
].X_op
== O_register
1727 && (myops
[j
].X_add_number
& 1)
1728 && (d30v_operand_table
[fm
->operands
[j
]].flags
& OPERAND_2REG
))
1730 _("Odd numbered register used as target of multi-register instruction"));
1734 fm
= (struct d30v_format
*)&d30v_format_table
[++k
];
1736 /* printf("trying another format: i=%d\n",i); */
1741 /* if while processing a fixup, a reloc really needs to be created */
1742 /* then it is done here */
1745 tc_gen_reloc (seg
, fixp
)
1750 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
1751 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
1752 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1753 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1754 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
1755 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
1757 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1758 _("reloc %d not supported by object file format"), (int)fixp
->fx_r_type
);
1761 reloc
->addend
= fixp
->fx_addnumber
;
1766 md_estimate_size_before_relax (fragp
, seg
)
1775 md_pcrel_from_section (fixp
, sec
)
1779 if (fixp
->fx_addsy
!= (symbolS
*)NULL
&& (!S_IS_DEFINED (fixp
->fx_addsy
) ||
1780 (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
1782 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1786 md_apply_fix3 (fixp
, valuep
, seg
)
1792 unsigned long insn
, insn2
;
1795 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
1800 else if (fixp
->fx_pcrel
)
1804 value
= fixp
->fx_offset
;
1806 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
1808 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
1809 value
-= S_GET_VALUE (fixp
->fx_subsy
);
1812 /* We don't actually support subtracting a symbol. */
1813 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1814 _("expression too complex"));
1819 /* Fetch the instruction, insert the fully resolved operand
1820 value, and stuff the instruction back again. */
1821 where
= fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
1822 insn
= bfd_getb32 ((unsigned char *) where
);
1824 switch (fixp
->fx_r_type
)
1826 case BFD_RELOC_8
: /* Check for a bad .byte directive. */
1827 if (fixp
->fx_addsy
!= NULL
)
1828 as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1829 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1830 else if (((unsigned)value
) > 0xff)
1831 as_bad (_("line %d: unable to place value %x into a byte"),
1832 fixp
->fx_line
, value
);
1834 * (unsigned char *) where
= value
;
1837 case BFD_RELOC_16
: /* Check for a bad .short directive. */
1838 if (fixp
->fx_addsy
!= NULL
)
1839 as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1840 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1841 else if (((unsigned)value
) > 0xffff)
1842 as_bad (_("line %d: unable to place value %x into a short"),
1843 fixp
->fx_line
, value
);
1845 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
1848 case BFD_RELOC_64
: /* Check for a bad .quad directive. */
1849 if (fixp
->fx_addsy
!= NULL
)
1850 as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1851 fixp
->fx_line
, S_GET_NAME (fixp
->fx_addsy
));
1854 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1855 bfd_putb32 (0, ((unsigned char *) where
) + 4);
1859 case BFD_RELOC_D30V_6
:
1860 check_size (value
, 6, fixp
->fx_file
, fixp
->fx_line
);
1861 insn
|= value
& 0x3F;
1862 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1865 case BFD_RELOC_D30V_9_PCREL
:
1866 if (fixp
->fx_where
& 0x7)
1871 fixp
->fx_r_type
= BFD_RELOC_D30V_9_PCREL_R
;
1873 check_size (value
, 9, fixp
->fx_file
, fixp
->fx_line
);
1874 insn
|= ((value
>> 3) & 0x3F) << 12;
1875 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1878 case BFD_RELOC_D30V_15
:
1879 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1880 insn
|= (value
>> 3) & 0xFFF;
1881 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1884 case BFD_RELOC_D30V_15_PCREL
:
1885 if (fixp
->fx_where
& 0x7)
1890 fixp
->fx_r_type
= BFD_RELOC_D30V_15_PCREL_R
;
1892 check_size (value
, 15, fixp
->fx_file
, fixp
->fx_line
);
1893 insn
|= (value
>> 3) & 0xFFF;
1894 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1897 case BFD_RELOC_D30V_21
:
1898 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1899 insn
|= (value
>> 3) & 0x3FFFF;
1900 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1903 case BFD_RELOC_D30V_21_PCREL
:
1904 if (fixp
->fx_where
& 0x7)
1909 fixp
->fx_r_type
= BFD_RELOC_D30V_21_PCREL_R
;
1911 check_size (value
, 21, fixp
->fx_file
, fixp
->fx_line
);
1912 insn
|= (value
>> 3) & 0x3FFFF;
1913 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1916 case BFD_RELOC_D30V_32
:
1917 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1918 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1919 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1920 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1921 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1922 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1925 case BFD_RELOC_D30V_32_PCREL
:
1926 insn2
= bfd_getb32 ((unsigned char *) where
+ 4);
1927 insn
|= (value
>> 26) & 0x3F; /* top 6 bits */
1928 insn2
|= ((value
& 0x03FC0000) << 2); /* next 8 bits */
1929 insn2
|= value
& 0x0003FFFF; /* bottom 18 bits */
1930 bfd_putb32 ((bfd_vma
) insn
, (unsigned char *) where
);
1931 bfd_putb32 ((bfd_vma
) insn2
, (unsigned char *) where
+ 4);
1935 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
1939 as_bad (_("line %d: unknown relocation type: 0x%x"),
1940 fixp
->fx_line
,fixp
->fx_r_type
);
1947 /* d30v_cleanup() is called after the assembler has finished parsing the input
1948 file or after a label is defined. Because the D30V assembler sometimes saves short
1949 instructions to see if it can package them with the next instruction, there may
1950 be a short instruction that still needs written. */
1952 d30v_cleanup (use_sequential
)
1958 if (prev_insn
!= -1)
1961 subseg
= now_subseg
;
1962 subseg_set (prev_seg
, prev_subseg
);
1963 write_1_short (&prev_opcode
, (long)prev_insn
, fixups
->next
, use_sequential
);
1964 subseg_set (seg
, subseg
);
1967 prev_mul32_p
= false;
1973 d30v_number_to_chars (buf
, value
, n
)
1974 char *buf
; /* Return 'nbytes' of chars here. */
1975 long long value
; /* The value of the bits. */
1976 int n
; /* Number of bytes in the output. */
1980 buf
[n
] = value
& 0xff;
1986 /* This function is called at the start of every line. */
1987 /* it checks to see if the first character is a '.' */
1988 /* which indicates the start of a pseudo-op. If it is, */
1989 /* then write out any unwritten instructions */
1994 char *c
= input_line_pointer
;
1996 while (isspace (*c
))
2000 d30v_cleanup (false);
2004 check_size (value
, bits
, file
, line
)
2017 max
= (1 << (bits
- 1)) - 1;
2020 as_bad_where (file
, line
, _("value too large to fit in %d bits"), bits
);
2025 /* d30v_frob_label() is called when after a label is recognized. */
2028 d30v_frob_label (lab
)
2031 /* Emit any pending instructions. */
2032 d30v_cleanup (false);
2034 /* Update the label's address with the current output pointer. */
2035 symbol_set_frag (lab
, frag_now
);
2036 S_SET_VALUE (lab
, (valueT
) frag_now_fix ());
2038 /* Record this label for future adjustment after we find out what
2039 kind of data it references, and the required alignment therewith. */
2040 d30v_last_label
= lab
;
2043 /* Hook into cons for capturing alignment changes. */
2046 d30v_cons_align (size
)
2052 while ((size
>>= 1) != 0)
2055 if (d30v_current_align
< log_size
)
2056 d30v_align (log_size
, (char *) NULL
, NULL
);
2057 else if (d30v_current_align
> log_size
)
2058 d30v_current_align
= log_size
;
2059 d30v_last_label
= NULL
;
2062 /* Called internally to handle all alignment needs. This takes care
2063 of eliding calls to frag_align if'n the cached current alignment
2064 says we've already got it, as well as taking care of the auto-aligning
2068 d30v_align (n
, pfill
, label
)
2073 /* The front end is prone to changing segments out from under us
2074 temporarily when -g is in effect. */
2075 int switched_seg_p
= (d30v_current_align_seg
!= now_seg
);
2077 /* Do not assume that if 'd30v_current_align >= n' and
2078 '! switched_seg_p' that it is safe to avoid performing
2079 this alignement request. The alignment of the current frag
2080 can be changed under our feet, for example by a .ascii
2081 directive in the source code. cf testsuite/gas/d30v/reloc.s */
2083 d30v_cleanup (false);
2088 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
2090 static char const nop
[4] = { 0x00, 0xf0, 0x00, 0x00 };
2092 /* First, make sure we're on a four-byte boundary, in case
2093 someone has been putting .byte values the text section. */
2094 if (d30v_current_align
< 2 || switched_seg_p
)
2095 frag_align (2, 0, 0);
2096 frag_align_pattern (n
, nop
, sizeof nop
, 0);
2099 frag_align (n
, 0, 0);
2102 frag_align (n
, *pfill
, 0);
2104 if (!switched_seg_p
)
2105 d30v_current_align
= n
;
2110 int label_seen
= false;
2111 struct frag
* old_frag
;
2115 assert (S_GET_SEGMENT (label
) == now_seg
);
2117 old_frag
= symbol_get_frag (label
);
2118 old_value
= S_GET_VALUE (label
);
2119 new_value
= (valueT
) frag_now_fix ();
2121 /* It is possible to have more than one label at a particular
2122 address, especially if debugging is enabled, so we must
2123 take care to adjust all the labels at this address in this
2124 fragment. To save time we search from the end of the symbol
2125 list, backwards, since the symbols we are interested in are
2126 almost certainly the ones that were most recently added.
2127 Also to save time we stop searching once we have seen at least
2128 one matching label, and we encounter a label that is no longer
2129 in the target fragment. Note, this search is guaranteed to
2130 find at least one match when sym == label, so no special case
2131 code is necessary. */
2132 for (sym
= symbol_lastP
; sym
!= NULL
; sym
= symbol_previous (sym
))
2134 if (symbol_get_frag (sym
) == old_frag
2135 && S_GET_VALUE (sym
) == old_value
)
2138 symbol_set_frag (sym
, frag_now
);
2139 S_SET_VALUE (sym
, new_value
);
2141 else if (label_seen
&& symbol_get_frag (sym
) != old_frag
)
2146 record_alignment (now_seg
, n
);
2149 /* Handle the .align pseudo-op. This aligns to a power of two. We
2150 hook here to latch the current alignment. */
2153 s_d30v_align (ignore
)
2157 char fill
, *pfill
= NULL
;
2158 long max_alignment
= 15;
2160 align
= get_absolute_expression ();
2161 if (align
> max_alignment
)
2163 align
= max_alignment
;
2164 as_warn (_("Alignment too large: %d assumed"), align
);
2168 as_warn (_("Alignment negative: 0 assumed"));
2172 if (*input_line_pointer
== ',')
2174 input_line_pointer
++;
2175 fill
= get_absolute_expression ();
2179 d30v_last_label
= NULL
;
2180 d30v_align (align
, pfill
, NULL
);
2182 demand_empty_rest_of_line ();
2185 /* Handle the .text pseudo-op. This is like the usual one, but it
2186 clears the saved last label and resets known alignment. */
2194 d30v_last_label
= NULL
;
2195 d30v_current_align
= 0;
2196 d30v_current_align_seg
= now_seg
;
2199 /* Handle the .data pseudo-op. This is like the usual one, but it
2200 clears the saved last label and resets known alignment. */
2207 d30v_last_label
= NULL
;
2208 d30v_current_align
= 0;
2209 d30v_current_align_seg
= now_seg
;
2212 /* Handle the .section pseudo-op. This is like the usual one, but it
2213 clears the saved last label and resets known alignment. */
2216 s_d30v_section (ignore
)
2219 obj_elf_section (ignore
);
2220 d30v_last_label
= NULL
;
2221 d30v_current_align
= 0;
2222 d30v_current_align_seg
= now_seg
;