1 /* tc-h8300.c -- Assemble code for the Renesas H8/300
2 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 /* Written By Steve Chamberlain <sac@cygnus.com>. */
26 #include "dwarf2dbg.h"
29 #define h8_opcodes ops
30 #include "opcode/h8300.h"
31 #include "safe-ctype.h"
37 const char comment_chars
[] = ";";
38 const char line_comment_chars
[] = "#";
39 const char line_separator_chars
[] = "";
41 static void sbranch (int);
42 static void h8300hmode (int);
43 static void h8300smode (int);
44 static void h8300hnmode (int);
45 static void h8300snmode (int);
46 static void h8300sxmode (int);
47 static void h8300sxnmode (int);
48 static void pint (int);
55 #define PSIZE (Hmode && !Nmode ? L_32 : L_16)
57 static int bsize
= L_8
; /* Default branch displacement. */
65 const struct h8_opcode
*opcode
;
68 static struct h8_instruction
*h8_instructions
;
71 h8300hmode (int arg ATTRIBUTE_UNUSED
)
75 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300h
))
76 as_warn (_("could not set architecture and machine"));
80 h8300smode (int arg ATTRIBUTE_UNUSED
)
84 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300s
))
85 as_warn (_("could not set architecture and machine"));
89 h8300hnmode (int arg ATTRIBUTE_UNUSED
)
94 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300hn
))
95 as_warn (_("could not set architecture and machine"));
99 h8300snmode (int arg ATTRIBUTE_UNUSED
)
104 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sn
))
105 as_warn (_("could not set architecture and machine"));
109 h8300sxmode (int arg ATTRIBUTE_UNUSED
)
114 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sx
))
115 as_warn (_("could not set architecture and machine"));
119 h8300sxnmode (int arg ATTRIBUTE_UNUSED
)
125 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sxn
))
126 as_warn (_("could not set architecture and machine"));
136 pint (int arg ATTRIBUTE_UNUSED
)
138 cons (Hmode
? 4 : 2);
141 /* This table describes all the machine specific pseudo-ops the assembler
142 has to support. The fields are:
143 pseudo-op name without dot
144 function to call to execute this pseudo-op
145 Integer arg to pass to the function. */
147 const pseudo_typeS md_pseudo_table
[] =
149 {"h8300h", h8300hmode
, 0},
150 {"h8300hn", h8300hnmode
, 0},
151 {"h8300s", h8300smode
, 0},
152 {"h8300sn", h8300snmode
, 0},
153 {"h8300sx", h8300sxmode
, 0},
154 {"h8300sxn", h8300sxnmode
, 0},
155 {"sbranch", sbranch
, L_8
},
156 {"lbranch", sbranch
, L_16
},
162 {"form", listing_psize
, 0},
163 {"heading", listing_title
, 0},
164 {"import", s_ignore
, 0},
165 {"page", listing_eject
, 0},
166 {"program", s_ignore
, 0},
170 const char EXP_CHARS
[] = "eE";
172 /* Chars that mean this number is a floating point constant
175 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
177 static struct hash_control
*opcode_hash_control
; /* Opcode mnemonics. */
179 /* This function is called once, at assembler startup time. This
180 should set up all the tables, etc. that the MD part of the assembler
186 unsigned int nopcodes
;
187 struct h8_opcode
*p
, *p1
;
188 struct h8_instruction
*pi
;
189 char prev_buffer
[100];
192 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300
))
193 as_warn (_("could not set architecture and machine"));
195 opcode_hash_control
= hash_new ();
198 nopcodes
= sizeof (h8_opcodes
) / sizeof (struct h8_opcode
);
200 h8_instructions
= (struct h8_instruction
*)
201 xmalloc (nopcodes
* sizeof (struct h8_instruction
));
203 pi
= h8_instructions
;
205 /* We do a minimum amount of sorting on the opcode table; this is to
206 make it easy to describe the mova instructions without unnecessary
208 Sorting only takes place inside blocks of instructions of the form
209 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */
212 struct h8_opcode
*first_skipped
= 0;
214 char *src
= p1
->name
;
219 /* Strip off any . part when inserting the opcode and only enter
220 unique codes into the hash table. */
221 dst
= buffer
= malloc (strlen (src
) + 1);
230 cmplen
= src
- p1
->name
+ 1;
237 hash_insert (opcode_hash_control
, buffer
, (char *) pi
);
238 strcpy (prev_buffer
, buffer
);
241 for (p
= p1
; p
->name
; p
++)
243 /* A negative TIME is used to indicate that we've added this opcode
247 if (strncmp (p
->name
, buffer
, cmplen
) != 0
248 || (p
->name
[cmplen
] != '\0' && p
->name
[cmplen
] != '.'
249 && p
->name
[cmplen
- 1] != '/'))
251 if (first_skipped
== 0)
255 if (strncmp (p
->name
, buffer
, len
) != 0)
257 if (first_skipped
== 0)
263 pi
->size
= p
->name
[len
] == '.' ? p
->name
[len
+ 1] : 0;
266 /* Find the number of operands. */
268 while (pi
->noperands
< 3 && p
->args
.nib
[pi
->noperands
] != (op_type
) E
)
271 /* Find the length of the opcode in bytes. */
273 while (p
->data
.nib
[pi
->length
* 2] != (op_type
) E
)
282 /* Add entry for the NULL vector terminator. */
299 static void clever_message (const struct h8_instruction
*, struct h8_op
*);
300 static void fix_operand_size (struct h8_op
*, int);
301 static void build_bytes (const struct h8_instruction
*, struct h8_op
*);
302 static void do_a_fix_imm (int, int, struct h8_op
*, int, const struct h8_instruction
*);
303 static void check_operand (struct h8_op
*, unsigned int, char *);
304 static const struct h8_instruction
* get_specific (const struct h8_instruction
*, struct h8_op
*, int) ;
305 static char *get_operands (unsigned, char *, struct h8_op
*);
306 static void get_operand (char **, struct h8_op
*, int);
307 static int parse_reg (char *, op_type
*, unsigned *, int);
308 static char *skip_colonthing (char *, int *);
309 static char *parse_exp (char *, struct h8_op
*);
311 static int constant_fits_width_p (struct h8_op
*, unsigned int);
312 static int constant_fits_size_p (struct h8_op
*, int, int);
316 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
325 /* Try to parse a reg name. Return the number of chars consumed. */
328 parse_reg (char *src
, op_type
*mode
, unsigned int *reg
, int direction
)
333 /* Cribbed from get_symbol_end. */
334 if (!is_name_beginner (*src
) || *src
== '\001')
337 while ((is_part_of_name (*end
) && *end
!= '.') || *end
== '\001')
341 if (len
== 2 && TOLOWER (src
[0]) == 's' && TOLOWER (src
[1]) == 'p')
343 *mode
= PSIZE
| REG
| direction
;
348 TOLOWER (src
[0]) == 'c' &&
349 TOLOWER (src
[1]) == 'c' &&
350 TOLOWER (src
[2]) == 'r')
357 TOLOWER (src
[0]) == 'e' &&
358 TOLOWER (src
[1]) == 'x' &&
359 TOLOWER (src
[2]) == 'r')
366 TOLOWER (src
[0]) == 'v' &&
367 TOLOWER (src
[1]) == 'b' &&
368 TOLOWER (src
[2]) == 'r')
375 TOLOWER (src
[0]) == 's' &&
376 TOLOWER (src
[1]) == 'b' &&
377 TOLOWER (src
[2]) == 'r')
383 if (len
== 2 && TOLOWER (src
[0]) == 'f' && TOLOWER (src
[1]) == 'p')
385 *mode
= PSIZE
| REG
| direction
;
389 if (len
== 3 && TOLOWER (src
[0]) == 'e' && TOLOWER (src
[1]) == 'r' &&
390 src
[2] >= '0' && src
[2] <= '7')
392 *mode
= L_32
| REG
| direction
;
395 as_warn (_("Reg not valid for H8/300"));
398 if (len
== 2 && TOLOWER (src
[0]) == 'e' && src
[1] >= '0' && src
[1] <= '7')
400 *mode
= L_16
| REG
| direction
;
401 *reg
= src
[1] - '0' + 8;
403 as_warn (_("Reg not valid for H8/300"));
407 if (TOLOWER (src
[0]) == 'r')
409 if (src
[1] >= '0' && src
[1] <= '7')
411 if (len
== 3 && TOLOWER (src
[2]) == 'l')
413 *mode
= L_8
| REG
| direction
;
414 *reg
= (src
[1] - '0') + 8;
417 if (len
== 3 && TOLOWER (src
[2]) == 'h')
419 *mode
= L_8
| REG
| direction
;
420 *reg
= (src
[1] - '0');
425 *mode
= L_16
| REG
| direction
;
426 *reg
= (src
[1] - '0');
436 /* Parse an immediate or address-related constant and store it in OP.
437 If the user also specifies the operand's size, store that size
438 in OP->MODE, otherwise leave it for later code to decide. */
441 parse_exp (char *src
, struct h8_op
*op
)
445 save
= input_line_pointer
;
446 input_line_pointer
= src
;
447 expression (&op
->exp
);
448 if (op
->exp
.X_op
== O_absent
)
449 as_bad (_("missing operand"));
450 src
= input_line_pointer
;
451 input_line_pointer
= save
;
453 return skip_colonthing (src
, &op
->mode
);
457 /* If SRC starts with an explicit operand size, skip it and store the size
458 in *MODE. Leave *MODE unchanged otherwise. */
461 skip_colonthing (char *src
, int *mode
)
467 if (src
[0] == '8' && !ISDIGIT (src
[1]))
469 else if (src
[0] == '2' && !ISDIGIT (src
[1]))
471 else if (src
[0] == '3' && !ISDIGIT (src
[1]))
473 else if (src
[0] == '4' && !ISDIGIT (src
[1]))
475 else if (src
[0] == '5' && !ISDIGIT (src
[1]))
477 else if (src
[0] == '2' && src
[1] == '4' && !ISDIGIT (src
[2]))
479 else if (src
[0] == '3' && src
[1] == '2' && !ISDIGIT (src
[2]))
481 else if (src
[0] == '1' && src
[1] == '6' && !ISDIGIT (src
[2]))
484 as_bad (_("invalid operand size requested"));
486 while (ISDIGIT (*src
))
492 /* The many forms of operand:
495 @Rn Register indirect
496 @(exp[:16], Rn) Register indirect with displacement
500 @aa:16 absolute 16 bit
503 #xx[:size] immediate data
504 @(exp:[8], pc) pc rel
505 @@aa[:8] memory indirect. */
508 constant_fits_width_p (struct h8_op
*operand
, unsigned int width
)
510 return ((operand
->exp
.X_add_number
& ~width
) == 0
511 || (operand
->exp
.X_add_number
| width
) == (unsigned)(~0));
515 constant_fits_size_p (struct h8_op
*operand
, int size
, int no_symbols
)
517 offsetT num
= operand
->exp
.X_add_number
;
519 && (operand
->exp
.X_add_symbol
!= 0 || operand
->exp
.X_op_symbol
!= 0))
524 return (num
& ~3) == 0;
526 return (num
& ~7) == 0;
528 return num
>= 1 && num
< 8;
530 return (num
& ~15) == 0;
532 return num
>= 1 && num
< 32;
534 return (num
& ~0xFF) == 0 || ((unsigned)num
| 0x7F) == ~0u;
536 return (num
& ~0xFF) == 0;
538 return (num
& ~0xFFFF) == 0 || ((unsigned)num
| 0x7FFF) == ~0u;
540 return (num
& ~0xFFFF) == 0;
549 get_operand (char **ptr
, struct h8_op
*op
, int direction
)
558 /* Check for '(' and ')' for instructions ldm and stm. */
559 if (src
[0] == '(' && src
[8] == ')')
562 /* Gross. Gross. ldm and stm have a format not easily handled
563 by get_operand. We deal with it explicitly here. */
564 if (TOLOWER (src
[0]) == 'e' && TOLOWER (src
[1]) == 'r' &&
565 ISDIGIT (src
[2]) && src
[3] == '-' &&
566 TOLOWER (src
[4]) == 'e' && TOLOWER (src
[5]) == 'r' && ISDIGIT (src
[6]))
573 /* Check register pair's validity as per tech note TN-H8*-193A/E
574 from Renesas for H8S and H8SX hardware manual. */
575 if ( !(low
== 0 && (high
== 1 || high
== 2 || high
== 3))
576 && !(low
== 1 && (high
== 2 || high
== 3 || high
== 4) && SXmode
)
577 && !(low
== 2 && (high
== 3 || ((high
== 4 || high
== 5) && SXmode
)))
578 && !(low
== 3 && (high
== 4 || high
== 5 || high
== 6) && SXmode
)
579 && !(low
== 4 && (high
== 5 || high
== 6))
580 && !(low
== 4 && high
== 7 && SXmode
)
581 && !(low
== 5 && (high
== 6 || high
== 7) && SXmode
)
582 && !(low
== 6 && high
== 7 && SXmode
))
583 as_bad (_("Invalid register list for ldm/stm\n"));
585 /* Even sicker. We encode two registers into op->reg. One
586 for the low register to save, the other for the high
587 register to save; we also set the high bit in op->reg
588 so we know this is "very special". */
589 op
->reg
= 0x80000000 | (high
<< 8) | low
;
598 len
= parse_reg (src
, &op
->mode
, &op
->reg
, direction
);
604 int size
= op
->mode
& SIZE
;
609 as_warn (_("mismatch between register and suffix"));
610 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
613 if (size
!= L_32
&& size
!= L_16
)
614 as_warn (_("mismatch between register and suffix"));
615 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
616 op
->mode
= (op
->mode
& ~SIZE
) | L_16
;
619 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
620 if (size
!= L_32
&& size
!= L_8
)
621 as_warn (_("mismatch between register and suffix"));
622 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
623 op
->mode
= (op
->mode
& ~SIZE
) | L_8
;
626 as_warn ("invalid suffix after register.");
640 *ptr
= parse_exp (src
+ 1, op
);
641 if (op
->exp
.X_add_number
>= 0x100)
646 /* FIXME : 2? or 4? */
647 if (op
->exp
.X_add_number
>= 0x400)
648 as_bad (_("address too high for vector table jmp/jsr"));
649 else if (op
->exp
.X_add_number
>= 0x200)
654 op
->exp
.X_add_number
= op
->exp
.X_add_number
/ divisor
- 0x80;
661 if (*src
== '-' || *src
== '+')
663 len
= parse_reg (src
+ 1, &mode
, &num
, direction
);
666 /* Oops, not a reg after all, must be ordinary exp. */
667 op
->mode
= ABS
| direction
;
668 *ptr
= parse_exp (src
, op
);
672 if (((mode
& SIZE
) != PSIZE
)
673 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
674 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
675 as_bad (_("Wrong size pointer register for architecture."));
677 op
->mode
= src
[0] == '-' ? RDPREDEC
: RDPREINC
;
679 *ptr
= src
+ 1 + len
;
686 /* See if this is @(ERn.x, PC). */
687 len
= parse_reg (src
, &mode
, &op
->reg
, direction
);
688 if (len
!= 0 && (mode
& MODE
) == REG
&& src
[len
] == '.')
690 switch (TOLOWER (src
[len
+ 1]))
693 mode
= PCIDXB
| direction
;
696 mode
= PCIDXW
| direction
;
699 mode
= PCIDXL
| direction
;
706 && src
[len
+ 2] == ','
707 && TOLOWER (src
[len
+ 3]) != 'p'
708 && TOLOWER (src
[len
+ 4]) != 'c'
709 && src
[len
+ 5] != ')')
711 *ptr
= src
+ len
+ 6;
715 /* Fall through into disp case - the grammar is somewhat
716 ambiguous, so we should try whether it's a DISP operand
717 after all ("ER3.L" might be a poorly named label...). */
722 /* Start off assuming a 16 bit offset. */
724 src
= parse_exp (src
, op
);
727 op
->mode
|= ABS
| direction
;
734 as_bad (_("expected @(exp, reg16)"));
739 len
= parse_reg (src
, &mode
, &op
->reg
, direction
);
740 if (len
== 0 || (mode
& MODE
) != REG
)
742 as_bad (_("expected @(exp, reg16)"));
748 switch (TOLOWER (src
[1]))
751 op
->mode
|= INDEXB
| direction
;
754 op
->mode
|= INDEXW
| direction
;
757 op
->mode
|= INDEXL
| direction
;
760 as_bad (_("expected .L, .W or .B for register in indexed addressing mode"));
766 op
->mode
|= DISP
| direction
;
767 src
= skip_colonthing (src
, &op
->mode
);
769 if (*src
!= ')' && '(')
771 as_bad (_("expected @(exp, reg16)"));
777 len
= parse_reg (src
, &mode
, &num
, direction
);
782 if (*src
== '+' || *src
== '-')
784 if (((mode
& SIZE
) != PSIZE
)
785 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
786 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
787 as_bad (_("Wrong size pointer register for architecture."));
788 op
->mode
= *src
== '+' ? RSPOSTINC
: RSPOSTDEC
;
794 if (((mode
& SIZE
) != PSIZE
)
795 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
796 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
797 as_bad (_("Wrong size pointer register for architecture."));
799 op
->mode
= direction
| IND
| PSIZE
;
807 /* must be a symbol */
809 op
->mode
= ABS
| direction
;
810 *ptr
= parse_exp (src
, op
);
818 *ptr
= parse_exp (src
+ 1, op
);
821 else if (strncmp (src
, "mach", 4) == 0 ||
822 strncmp (src
, "macl", 4) == 0 ||
823 strncmp (src
, "MACH", 4) == 0 ||
824 strncmp (src
, "MACL", 4) == 0)
826 op
->reg
= TOLOWER (src
[3]) == 'l';
834 *ptr
= parse_exp (src
, op
);
839 get_operands (unsigned int noperands
, char *op_end
, struct h8_op
*operand
)
850 get_operand (&ptr
, operand
+ 0, SRC
);
854 get_operand (&ptr
, operand
+ 1, DST
);
860 get_operand (&ptr
, operand
+ 0, SRC
);
863 get_operand (&ptr
, operand
+ 1, DST
);
868 get_operand (&ptr
, operand
+ 0, SRC
);
871 get_operand (&ptr
, operand
+ 1, DST
);
874 get_operand (&ptr
, operand
+ 2, OP3
);
884 /* MOVA has special requirements. Rather than adding twice the amount of
885 addressing modes, we simply special case it a bit. */
887 get_mova_operands (char *op_end
, struct h8_op
*operand
)
891 if (ptr
[1] != '@' || ptr
[2] != '(')
895 ptr
= parse_exp (ptr
, &operand
[0]);
900 get_operand (&ptr
, operand
+ 1, DST
);
908 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXB
;
911 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXW
;
914 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXL
;
920 else if ((operand
[1].mode
& MODE
) == LOWREG
)
922 switch (operand
[1].mode
& SIZE
)
925 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXB
;
928 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXW
;
931 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXL
;
940 if (*ptr
++ != ')' || *ptr
++ != ',')
942 get_operand (&ptr
, operand
+ 2, OP3
);
943 /* See if we can use the short form of MOVA. */
944 if (((operand
[1].mode
& MODE
) == REG
|| (operand
[1].mode
& MODE
) == LOWREG
)
945 && (operand
[2].mode
& MODE
) == REG
946 && (operand
[1].reg
& 7) == (operand
[2].reg
& 7))
948 operand
[1].mode
= operand
[2].mode
= 0;
949 operand
[0].reg
= operand
[2].reg
& 7;
954 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""));
958 get_rtsl_operands (char *ptr
, struct h8_op
*operand
)
960 int mode
, len
, type
= 0;
961 unsigned int num
, num2
;
969 len
= parse_reg (ptr
, &mode
, &num
, SRC
);
970 if (len
== 0 || (mode
& MODE
) != REG
)
972 as_bad (_("expected register"));
978 len
= parse_reg (++ptr
, &mode
, &num2
, SRC
);
979 if (len
== 0 || (mode
& MODE
) != REG
)
981 as_bad (_("expected register"));
985 /* CONST_xxx are used as placeholders in the opcode table. */
989 as_bad (_("invalid register list"));
995 if (type
== 1 && *ptr
++ != ')')
997 as_bad (_("expected closing paren"));
1000 operand
[0].mode
= RS32
;
1001 operand
[1].mode
= RD32
;
1002 operand
[0].reg
= num
;
1003 operand
[1].reg
= num2
;
1006 /* Passed a pointer to a list of opcodes which use different
1007 addressing modes, return the opcode which matches the opcodes
1010 static const struct h8_instruction
*
1011 get_specific (const struct h8_instruction
*instruction
,
1012 struct h8_op
*operands
, int size
)
1014 const struct h8_instruction
*this_try
= instruction
;
1015 const struct h8_instruction
*found_other
= 0, *found_mismatched
= 0;
1017 int this_index
= instruction
->idx
;
1020 /* There's only one ldm/stm and it's easier to just
1021 get out quick for them. */
1022 if (OP_KIND (instruction
->opcode
->how
) == O_LDM
1023 || OP_KIND (instruction
->opcode
->how
) == O_STM
)
1026 while (noperands
< 3 && operands
[noperands
].mode
!= 0)
1029 while (this_index
== instruction
->idx
&& !found
)
1034 this_try
= instruction
++;
1035 this_size
= this_try
->opcode
->how
& SN
;
1037 if (this_try
->noperands
!= noperands
)
1039 else if (this_try
->noperands
> 0)
1043 for (i
= 0; i
< this_try
->noperands
&& found
; i
++)
1045 op_type op
= this_try
->opcode
->args
.nib
[i
];
1046 int op_mode
= op
& MODE
;
1047 int op_size
= op
& SIZE
;
1048 int x
= operands
[i
].mode
;
1049 int x_mode
= x
& MODE
;
1050 int x_size
= x
& SIZE
;
1052 if (op_mode
== LOWREG
&& (x_mode
== REG
|| x_mode
== LOWREG
))
1054 if ((x_size
== L_8
&& (operands
[i
].reg
& 8) == 0)
1055 || (x_size
== L_16
&& (operands
[i
].reg
& 8) == 8))
1056 as_warn (_("can't use high part of register in operand %d"), i
);
1058 if (x_size
!= op_size
)
1061 else if (op_mode
== REG
)
1063 if (x_mode
== LOWREG
)
1069 x_size
= (Hmode
? L_32
: L_16
);
1071 op_size
= (Hmode
? L_32
: L_16
);
1073 /* The size of the reg is v important. */
1074 if (op_size
!= x_size
)
1077 else if (op_mode
& CTRL
) /* control register */
1079 if (!(x_mode
& CTRL
))
1085 if (op_mode
!= CCR
&&
1086 op_mode
!= CCR_EXR
&&
1087 op_mode
!= CC_EX_VB_SB
)
1091 if (op_mode
!= EXR
&&
1092 op_mode
!= CCR_EXR
&&
1093 op_mode
!= CC_EX_VB_SB
)
1097 if (op_mode
!= MACH
&&
1102 if (op_mode
!= MACL
&&
1107 if (op_mode
!= VBR
&&
1108 op_mode
!= VBR_SBR
&&
1109 op_mode
!= CC_EX_VB_SB
)
1113 if (op_mode
!= SBR
&&
1114 op_mode
!= VBR_SBR
&&
1115 op_mode
!= CC_EX_VB_SB
)
1120 else if ((op
& ABSJMP
) && (x_mode
== ABS
|| x_mode
== PCREL
))
1122 operands
[i
].mode
&= ~MODE
;
1123 operands
[i
].mode
|= ABSJMP
;
1124 /* But it may not be 24 bits long. */
1125 if (x_mode
== ABS
&& !Hmode
)
1127 operands
[i
].mode
&= ~SIZE
;
1128 operands
[i
].mode
|= L_16
;
1130 if ((operands
[i
].mode
& SIZE
) == L_32
1131 && (op_mode
& SIZE
) != L_32
)
1134 else if (x_mode
== IMM
&& op_mode
!= IMM
)
1136 offsetT num
= operands
[i
].exp
.X_add_number
;
1137 if (op_mode
== KBIT
|| op_mode
== DBIT
)
1138 /* This is ok if the immediate value is sensible. */;
1139 else if (op_mode
== CONST_2
)
1141 else if (op_mode
== CONST_4
)
1143 else if (op_mode
== CONST_8
)
1145 else if (op_mode
== CONST_16
)
1150 else if (op_mode
== PCREL
&& op_mode
== x_mode
)
1152 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour:
1153 If x_size is L_8, promote it. */
1154 if (OP_KIND (this_try
->opcode
->how
) == O_MOVSD
1155 || OP_KIND (this_try
->opcode
->how
) == O_BSRBC
1156 || OP_KIND (this_try
->opcode
->how
) == O_BSRBS
)
1160 /* The size of the displacement is important. */
1161 if (op_size
!= x_size
)
1164 else if ((op_mode
== DISP
|| op_mode
== IMM
|| op_mode
== ABS
1165 || op_mode
== INDEXB
|| op_mode
== INDEXW
1166 || op_mode
== INDEXL
)
1167 && op_mode
== x_mode
)
1169 /* Promote a L_24 to L_32 if it makes us match. */
1170 if (x_size
== L_24
&& op_size
== L_32
)
1176 if (((x_size
== L_16
&& op_size
== L_16U
)
1177 || (x_size
== L_8
&& op_size
== L_8U
)
1178 || (x_size
== L_3
&& op_size
== L_3NZ
))
1179 /* We're deliberately more permissive for ABS modes. */
1181 || constant_fits_size_p (operands
+ i
, op_size
,
1185 if (x_size
!= 0 && op_size
!= x_size
)
1187 else if (x_size
== 0
1188 && ! constant_fits_size_p (operands
+ i
, op_size
,
1192 else if (op_mode
!= x_mode
)
1200 if ((this_try
->opcode
->available
== AV_H8SX
&& ! SXmode
)
1201 || (this_try
->opcode
->available
== AV_H8S
&& ! Smode
)
1202 || (this_try
->opcode
->available
== AV_H8H
&& ! Hmode
))
1203 found
= 0, found_other
= this_try
;
1204 else if (this_size
!= size
&& (this_size
!= SN
&& size
!= SN
))
1205 found_mismatched
= this_try
, found
= 0;
1213 as_warn (_("Opcode `%s' with these operand types not available in %s mode"),
1214 found_other
->opcode
->name
,
1215 (! Hmode
&& ! Smode
? "H8/300"
1220 else if (found_mismatched
)
1222 as_warn (_("mismatch between opcode size and operand size"));
1223 return found_mismatched
;
1229 check_operand (struct h8_op
*operand
, unsigned int width
, char *string
)
1231 if (operand
->exp
.X_add_symbol
== 0
1232 && operand
->exp
.X_op_symbol
== 0)
1234 /* No symbol involved, let's look at offset, it's dangerous if
1235 any of the high bits are not 0 or ff's, find out by oring or
1236 anding with the width and seeing if the answer is 0 or all
1239 if (! constant_fits_width_p (operand
, width
))
1242 && (operand
->exp
.X_add_number
& 0xff00) == 0xff00)
1244 /* Just ignore this one - which happens when trying to
1245 fit a 16 bit address truncated into an 8 bit address
1246 of something like bset. */
1248 else if (strcmp (string
, "@") == 0
1250 && (operand
->exp
.X_add_number
& 0xff8000) == 0xff8000)
1252 /* Just ignore this one - which happens when trying to
1253 fit a 24 bit address truncated into a 16 bit address
1254 of something like mov.w. */
1258 as_warn (_("operand %s0x%lx out of range."), string
,
1259 (unsigned long) operand
->exp
.X_add_number
);
1265 /* RELAXMODE has one of 3 values:
1267 0 Output a "normal" reloc, no relaxing possible for this insn/reloc
1269 1 Output a relaxable 24bit absolute mov.w address relocation
1270 (may relax into a 16bit absolute address).
1272 2 Output a relaxable 16/24 absolute mov.b address relocation
1273 (may relax into an 8bit absolute address). */
1276 do_a_fix_imm (int offset
, int nibble
, struct h8_op
*operand
, int relaxmode
, const struct h8_instruction
*this_try
)
1281 char *bytes
= frag_now
->fr_literal
+ offset
;
1283 char *t
= ((operand
->mode
& MODE
) == IMM
) ? "#" : "@";
1285 if (operand
->exp
.X_add_symbol
== 0)
1287 switch (operand
->mode
& SIZE
)
1290 check_operand (operand
, 0x3, t
);
1291 bytes
[0] |= (operand
->exp
.X_add_number
& 3) << (nibble
? 0 : 4);
1295 check_operand (operand
, 0x7, t
);
1296 bytes
[0] |= (operand
->exp
.X_add_number
& 7) << (nibble
? 0 : 4);
1299 check_operand (operand
, 0xF, t
);
1300 bytes
[0] |= (operand
->exp
.X_add_number
& 15) << (nibble
? 0 : 4);
1303 check_operand (operand
, 0x1F, t
);
1304 bytes
[0] |= operand
->exp
.X_add_number
& 31;
1308 check_operand (operand
, 0xff, t
);
1309 bytes
[0] |= operand
->exp
.X_add_number
;
1313 check_operand (operand
, 0xffff, t
);
1314 bytes
[0] |= operand
->exp
.X_add_number
>> 8;
1315 bytes
[1] |= operand
->exp
.X_add_number
>> 0;
1317 /* MOVA needs both relocs to relax the second operand properly. */
1319 && (OP_KIND(this_try
->opcode
->how
) == O_MOVAB
1320 || OP_KIND(this_try
->opcode
->how
) == O_MOVAW
1321 || OP_KIND(this_try
->opcode
->how
) == O_MOVAL
))
1324 fix_new_exp (frag_now
, offset
, 2, &operand
->exp
, 0, idx
);
1329 check_operand (operand
, 0xffffff, t
);
1330 bytes
[0] |= operand
->exp
.X_add_number
>> 16;
1331 bytes
[1] |= operand
->exp
.X_add_number
>> 8;
1332 bytes
[2] |= operand
->exp
.X_add_number
>> 0;
1336 /* This should be done with bfd. */
1337 bytes
[0] |= operand
->exp
.X_add_number
>> 24;
1338 bytes
[1] |= operand
->exp
.X_add_number
>> 16;
1339 bytes
[2] |= operand
->exp
.X_add_number
>> 8;
1340 bytes
[3] |= operand
->exp
.X_add_number
>> 0;
1343 idx
= (relaxmode
== 2) ? R_MOV24B1
: R_MOVL1
;
1344 fix_new_exp (frag_now
, offset
, 4, &operand
->exp
, 0, idx
);
1351 switch (operand
->mode
& SIZE
)
1356 where
= (operand
->mode
& SIZE
) == L_24
? -1 : 0;
1359 else if (relaxmode
== 1)
1365 as_bad (_("Can't work out size of operand.\n"));
1374 operand
->exp
.X_add_number
=
1375 ((operand
->exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1376 operand
->exp
.X_add_number
|= (bytes
[0] << 8) | bytes
[1];
1382 operand
->exp
.X_add_number
=
1383 ((operand
->exp
.X_add_number
& 0xff) ^ 0x80) - 0x80;
1384 operand
->exp
.X_add_number
|= bytes
[0];
1387 fix_new_exp (frag_now
,
1396 /* Now we know what sort of opcodes it is, let's build the bytes. */
1399 build_bytes (const struct h8_instruction
*this_try
, struct h8_op
*operand
)
1402 char *output
= frag_more (this_try
->length
);
1403 const op_type
*nibble_ptr
= this_try
->opcode
->data
.nib
;
1405 unsigned int nibble_count
= 0;
1409 char asnibbles
[100];
1410 char *p
= asnibbles
;
1413 if (!Hmode
&& this_try
->opcode
->available
!= AV_H8
)
1414 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
1415 this_try
->opcode
->name
);
1417 && this_try
->opcode
->available
!= AV_H8
1418 && this_try
->opcode
->available
!= AV_H8H
)
1419 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
1420 this_try
->opcode
->name
);
1422 && this_try
->opcode
->available
!= AV_H8
1423 && this_try
->opcode
->available
!= AV_H8H
1424 && this_try
->opcode
->available
!= AV_H8S
)
1425 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"),
1426 this_try
->opcode
->name
);
1428 while (*nibble_ptr
!= (op_type
) E
)
1435 d
= (c
& OP3
) == OP3
? 2 : (c
& DST
) == DST
? 1 : 0;
1443 if (c2
== REG
|| c2
== LOWREG
1444 || c2
== IND
|| c2
== PREINC
|| c2
== PREDEC
1445 || c2
== POSTINC
|| c2
== POSTDEC
)
1447 nib
= operand
[d
].reg
;
1452 else if (c
& CTRL
) /* Control reg operand. */
1453 nib
= operand
[d
].reg
;
1455 else if ((c
& DISPREG
) == (DISPREG
))
1457 nib
= operand
[d
].reg
;
1461 operand
[d
].mode
= c
;
1462 op_at
[d
] = nibble_count
;
1465 else if (c2
== IMM
|| c2
== PCREL
|| c2
== ABS
1466 || (c
& ABSJMP
) || c2
== DISP
)
1468 operand
[d
].mode
= c
;
1469 op_at
[d
] = nibble_count
;
1472 else if ((c
& IGNORE
) || (c
& DATA
))
1475 else if (c2
== DBIT
)
1477 switch (operand
[0].exp
.X_add_number
)
1486 as_bad (_("Need #1 or #2 here"));
1489 else if (c2
== KBIT
)
1491 switch (operand
[0].exp
.X_add_number
)
1501 as_warn (_("#4 not valid on H8/300."));
1506 as_bad (_("Need #1 or #2 here"));
1509 /* Stop it making a fix. */
1510 operand
[0].mode
= 0;
1514 operand
[d
].mode
|= MEMRELAX
;
1530 if (operand
[0].mode
== MACREG
)
1531 /* stmac has mac[hl] as the first operand. */
1532 nib
= 2 + operand
[0].reg
;
1534 /* ldmac has mac[hl] as the second operand. */
1535 nib
= 2 + operand
[1].reg
;
1543 /* Disgusting. Why, oh why didn't someone ask us for advice
1544 on the assembler format. */
1545 if (OP_KIND (this_try
->opcode
->how
) == O_LDM
)
1547 high
= (operand
[1].reg
>> 8) & 0xf;
1548 low
= (operand
[1].reg
) & 0xf;
1549 asnibbles
[2] = high
- low
;
1550 asnibbles
[7] = high
;
1552 else if (OP_KIND (this_try
->opcode
->how
) == O_STM
)
1554 high
= (operand
[0].reg
>> 8) & 0xf;
1555 low
= (operand
[0].reg
) & 0xf;
1556 asnibbles
[2] = high
- low
;
1560 for (i
= 0; i
< this_try
->length
; i
++)
1561 output
[i
] = (asnibbles
[i
* 2] << 4) | asnibbles
[i
* 2 + 1];
1563 /* Note if this is a movb or a bit manipulation instruction
1564 there is a special relaxation which only applies. */
1565 if ( this_try
->opcode
->how
== O (O_MOV
, SB
)
1566 || this_try
->opcode
->how
== O (O_BCLR
, SB
)
1567 || this_try
->opcode
->how
== O (O_BAND
, SB
)
1568 || this_try
->opcode
->how
== O (O_BIAND
, SB
)
1569 || this_try
->opcode
->how
== O (O_BILD
, SB
)
1570 || this_try
->opcode
->how
== O (O_BIOR
, SB
)
1571 || this_try
->opcode
->how
== O (O_BIST
, SB
)
1572 || this_try
->opcode
->how
== O (O_BIXOR
, SB
)
1573 || this_try
->opcode
->how
== O (O_BLD
, SB
)
1574 || this_try
->opcode
->how
== O (O_BNOT
, SB
)
1575 || this_try
->opcode
->how
== O (O_BOR
, SB
)
1576 || this_try
->opcode
->how
== O (O_BSET
, SB
)
1577 || this_try
->opcode
->how
== O (O_BST
, SB
)
1578 || this_try
->opcode
->how
== O (O_BTST
, SB
)
1579 || this_try
->opcode
->how
== O (O_BXOR
, SB
))
1582 /* Output any fixes. */
1583 for (i
= 0; i
< this_try
->noperands
; i
++)
1585 int x
= operand
[i
].mode
;
1586 int x_mode
= x
& MODE
;
1588 if (x_mode
== IMM
|| x_mode
== DISP
)
1589 do_a_fix_imm (output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1590 op_at
[i
] & 1, operand
+ i
, (x
& MEMRELAX
) != 0,
1593 else if (x_mode
== ABS
)
1594 do_a_fix_imm (output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1595 op_at
[i
] & 1, operand
+ i
,
1596 (x
& MEMRELAX
) ? movb
+ 1 : 0,
1599 else if (x_mode
== PCREL
)
1601 int size16
= (x
& SIZE
) == L_16
;
1602 int size
= size16
? 2 : 1;
1603 int type
= size16
? R_PCRWORD
: R_PCRBYTE
;
1606 check_operand (operand
+ i
, size16
? 0x7fff : 0x7f, "@");
1608 if (operand
[i
].exp
.X_add_number
& 1)
1609 as_warn (_("branch operand has odd offset (%lx)\n"),
1610 (unsigned long) operand
->exp
.X_add_number
);
1612 /* The COFF port has always been off by one, changing it
1613 now would be an incompatible change, so we leave it as-is.
1615 We don't want to do this for ELF as we want to be
1616 compatible with the proposed ELF format from Hitachi. */
1617 operand
[i
].exp
.X_add_number
-= 1;
1621 operand
[i
].exp
.X_add_number
=
1622 ((operand
[i
].exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1626 operand
[i
].exp
.X_add_number
=
1627 ((operand
[i
].exp
.X_add_number
& 0xff) ^ 0x80) - 0x80;
1632 operand
[i
].exp
.X_add_number
|= output
[op_at
[i
] / 2];
1634 fixP
= fix_new_exp (frag_now
,
1635 output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1640 fixP
->fx_signed
= 1;
1642 else if (x_mode
== MEMIND
)
1644 check_operand (operand
+ i
, 0xff, "@@");
1645 fix_new_exp (frag_now
,
1646 output
- frag_now
->fr_literal
+ 1,
1652 else if (x_mode
== VECIND
)
1654 check_operand (operand
+ i
, 0x7f, "@@");
1655 /* FIXME: approximating the effect of "B31" here...
1656 This is very hackish, and ought to be done a better way. */
1657 operand
[i
].exp
.X_add_number
|= 0x80;
1658 fix_new_exp (frag_now
,
1659 output
- frag_now
->fr_literal
+ 1,
1665 else if (x
& ABSJMP
)
1668 bfd_reloc_code_real_type reloc_type
= R_JMPL1
;
1671 /* To be compatible with the proposed H8 ELF format, we
1672 want the relocation's offset to point to the first byte
1673 that will be modified, not to the start of the instruction. */
1675 if ((operand
->mode
& SIZE
) == L_32
)
1678 reloc_type
= R_RELLONG
;
1684 /* This jmp may be a jump or a branch. */
1686 check_operand (operand
+ i
,
1687 SXmode
? 0xffffffff : Hmode
? 0xffffff : 0xffff,
1690 if (operand
[i
].exp
.X_add_number
& 1)
1691 as_warn (_("branch operand has odd offset (%lx)\n"),
1692 (unsigned long) operand
->exp
.X_add_number
);
1695 operand
[i
].exp
.X_add_number
=
1696 ((operand
[i
].exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1697 fix_new_exp (frag_now
,
1698 output
- frag_now
->fr_literal
+ where
,
1707 /* Try to give an intelligent error message for common and simple to
1711 clever_message (const struct h8_instruction
*instruction
,
1712 struct h8_op
*operand
)
1714 /* Find out if there was more than one possible opcode. */
1716 if ((instruction
+ 1)->idx
!= instruction
->idx
)
1720 /* Only one opcode of this flavour, try to guess which operand
1722 for (argn
= 0; argn
< instruction
->noperands
; argn
++)
1724 switch (instruction
->opcode
->args
.nib
[argn
])
1727 if (operand
[argn
].mode
!= RD16
)
1729 as_bad (_("destination operand must be 16 bit register"));
1736 if (operand
[argn
].mode
!= RS8
)
1738 as_bad (_("source operand must be 8 bit register"));
1744 if (operand
[argn
].mode
!= ABS16DST
)
1746 as_bad (_("destination operand must be 16bit absolute address"));
1751 if (operand
[argn
].mode
!= RD8
)
1753 as_bad (_("destination operand must be 8 bit register"));
1759 if (operand
[argn
].mode
!= ABS16SRC
)
1761 as_bad (_("source operand must be 16bit absolute address"));
1769 as_bad (_("invalid operands"));
1773 /* If OPERAND is part of an address, adjust its size and value given
1774 that it addresses SIZE bytes.
1776 This function decides how big non-immediate constants are when no
1777 size was explicitly given. It also scales down the assembly-level
1778 displacement in an @(d:2,ERn) operand. */
1781 fix_operand_size (struct h8_op
*operand
, int size
)
1783 if (SXmode
&& (operand
->mode
& MODE
) == DISP
)
1785 /* If the user didn't specify an operand width, see if we
1786 can use @(d:2,ERn). */
1787 if ((operand
->mode
& SIZE
) == 0
1788 && operand
->exp
.X_add_symbol
== 0
1789 && operand
->exp
.X_op_symbol
== 0
1790 && (operand
->exp
.X_add_number
== size
1791 || operand
->exp
.X_add_number
== size
* 2
1792 || operand
->exp
.X_add_number
== size
* 3))
1793 operand
->mode
|= L_2
;
1795 /* Scale down the displacement in an @(d:2,ERn) operand.
1796 X_add_number then contains the desired field value. */
1797 if ((operand
->mode
& SIZE
) == L_2
)
1799 if (operand
->exp
.X_add_number
% size
!= 0)
1800 as_warn (_("operand/size mis-match"));
1801 operand
->exp
.X_add_number
/= size
;
1805 if ((operand
->mode
& SIZE
) == 0)
1806 switch (operand
->mode
& MODE
)
1813 /* Pick a 24-bit address unless we know that a 16-bit address
1814 is safe. get_specific() will relax L_24 into L_32 where
1818 && (operand
->exp
.X_add_number
< -32768
1819 || operand
->exp
.X_add_number
> 32767
1820 || operand
->exp
.X_add_symbol
!= 0
1821 || operand
->exp
.X_op_symbol
!= 0))
1822 operand
->mode
|= L_24
;
1824 operand
->mode
|= L_16
;
1828 /* This condition is long standing, though somewhat suspect. */
1829 if (operand
->exp
.X_add_number
> -128
1830 && operand
->exp
.X_add_number
< 127)
1832 if (operand
->exp
.X_add_symbol
!= NULL
)
1833 operand
->mode
|= bsize
;
1835 operand
->mode
|= L_8
;
1838 operand
->mode
|= L_16
;
1844 /* This is the guts of the machine-dependent assembler. STR points to
1845 a machine dependent instruction. This function is supposed to emit
1846 the frags/bytes it assembles. */
1849 md_assemble (char *str
)
1853 struct h8_op operand
[3];
1854 const struct h8_instruction
*instruction
;
1855 const struct h8_instruction
*prev_instruction
;
1862 /* Drop leading whitespace. */
1866 /* Find the op code end. */
1867 for (op_start
= op_end
= str
;
1868 *op_end
!= 0 && *op_end
!= ' ';
1878 else if (*op_end
== '/' && ! slash
)
1882 if (op_end
== op_start
)
1884 as_bad (_("can't find opcode "));
1890 /* The assembler stops scanning the opcode at slashes, so it fails
1891 to make characters following them lower case. Fix them. */
1894 *slash
= TOLOWER (*slash
);
1896 instruction
= (const struct h8_instruction
*)
1897 hash_find (opcode_hash_control
, op_start
);
1899 if (instruction
== NULL
)
1901 as_bad (_("unknown opcode"));
1905 /* We used to set input_line_pointer to the result of get_operands,
1906 but that is wrong. Our caller assumes we don't change it. */
1908 operand
[0].mode
= 0;
1909 operand
[1].mode
= 0;
1910 operand
[2].mode
= 0;
1912 if (OP_KIND (instruction
->opcode
->how
) == O_MOVAB
1913 || OP_KIND (instruction
->opcode
->how
) == O_MOVAW
1914 || OP_KIND (instruction
->opcode
->how
) == O_MOVAL
)
1915 get_mova_operands (op_end
, operand
);
1916 else if (OP_KIND (instruction
->opcode
->how
) == O_RTEL
1917 || OP_KIND (instruction
->opcode
->how
) == O_RTSL
)
1918 get_rtsl_operands (op_end
, operand
);
1920 get_operands (instruction
->noperands
, op_end
, operand
);
1923 prev_instruction
= instruction
;
1925 /* Now we have operands from instruction.
1926 Let's check them out for ldm and stm. */
1927 if (OP_KIND (instruction
->opcode
->how
) == O_LDM
)
1929 /* The first operand must be @er7+, and the
1930 second operand must be a register pair. */
1931 if ((operand
[0].mode
!= RSINC
)
1932 || (operand
[0].reg
!= 7)
1933 || ((operand
[1].reg
& 0x80000000) == 0))
1934 as_bad (_("invalid operand in ldm"));
1936 else if (OP_KIND (instruction
->opcode
->how
) == O_STM
)
1938 /* The first operand must be a register pair,
1939 and the second operand must be @-er7. */
1940 if (((operand
[0].reg
& 0x80000000) == 0)
1941 || (operand
[1].mode
!= RDDEC
)
1942 || (operand
[1].reg
!= 7))
1943 as_bad (_("invalid operand in stm"));
1949 switch (TOLOWER (*dot
))
1964 if (OP_KIND (instruction
->opcode
->how
) == O_MOVAB
||
1965 OP_KIND (instruction
->opcode
->how
) == O_MOVAW
||
1966 OP_KIND (instruction
->opcode
->how
) == O_MOVAL
)
1968 switch (operand
[0].mode
& MODE
)
1972 fix_operand_size (&operand
[1], 1);
1975 fix_operand_size (&operand
[1], 2);
1978 fix_operand_size (&operand
[1], 4);
1984 for (i
= 0; i
< 3 && operand
[i
].mode
!= 0; i
++)
1990 fix_operand_size (&operand
[i
], 1);
1993 fix_operand_size (&operand
[i
], 2);
1996 fix_operand_size (&operand
[i
], 4);
2001 instruction
= get_specific (instruction
, operand
, size
);
2003 if (instruction
== 0)
2005 /* Couldn't find an opcode which matched the operands. */
2006 char *where
= frag_more (2);
2010 clever_message (prev_instruction
, operand
);
2015 build_bytes (instruction
, operand
);
2017 dwarf2_emit_insn (instruction
->length
);
2021 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
2026 /* Various routines to kill one day. */
2029 md_atof (int type
, char *litP
, int *sizeP
)
2031 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
2034 #define OPTION_H_TICK_HEX (OPTION_MD_BASE)
2036 const char *md_shortopts
= "";
2037 struct option md_longopts
[] = {
2038 { "h-tick-hex", no_argument
, NULL
, OPTION_H_TICK_HEX
},
2039 {NULL
, no_argument
, NULL
, 0}
2042 size_t md_longopts_size
= sizeof (md_longopts
);
2045 md_parse_option (int c ATTRIBUTE_UNUSED
, char *arg ATTRIBUTE_UNUSED
)
2049 case OPTION_H_TICK_HEX
:
2050 enable_h_tick_hex
= 1;
2060 md_show_usage (FILE *stream ATTRIBUTE_UNUSED
)
2064 void tc_aout_fix_to_chars (void);
2067 tc_aout_fix_to_chars (void)
2069 printf (_("call to tc_aout_fix_to_chars \n"));
2074 md_convert_frag (bfd
*headers ATTRIBUTE_UNUSED
,
2075 segT seg ATTRIBUTE_UNUSED
,
2076 fragS
*fragP ATTRIBUTE_UNUSED
)
2078 printf (_("call to md_convert_frag \n"));
2083 md_section_align (segT segment
, valueT size
)
2085 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2086 return ((size
+ (1 << align
) - 1) & (-1 << align
));
2090 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2092 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2095 switch (fixP
->fx_size
)
2101 *buf
++ = (val
>> 8);
2105 *buf
++ = (val
>> 24);
2106 *buf
++ = (val
>> 16);
2107 *buf
++ = (val
>> 8);
2111 /* This can arise when the .quad or .8byte pseudo-ops are used.
2112 Returning here (without setting fx_done) will cause the code
2113 to attempt to generate a reloc which will then fail with the
2114 slightly more helpful error message: "Cannot represent
2115 relocation type BFD_RELOC_64". */
2121 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
2126 md_estimate_size_before_relax (fragS
*fragP ATTRIBUTE_UNUSED
,
2127 segT segment_type ATTRIBUTE_UNUSED
)
2129 printf (_("call to md_estimate_size_before_relax \n"));
2133 /* Put number into target byte order. */
2135 md_number_to_chars (char *ptr
, valueT use
, int nbytes
)
2137 number_to_chars_bigendian (ptr
, use
, nbytes
);
2141 md_pcrel_from (fixS
*fixP ATTRIBUTE_UNUSED
)
2147 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2150 bfd_reloc_code_real_type r_type
;
2152 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
2154 if ((S_GET_SEGMENT (fixp
->fx_addsy
) != S_GET_SEGMENT (fixp
->fx_subsy
))
2155 || S_GET_SEGMENT (fixp
->fx_addsy
) == undefined_section
)
2157 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2158 _("Difference of symbols in different sections is not supported"));
2163 rel
= xmalloc (sizeof (arelent
));
2164 rel
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
2165 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2166 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2167 rel
->addend
= fixp
->fx_offset
;
2169 r_type
= fixp
->fx_r_type
;
2173 fprintf (stderr
, "%s\n", bfd_get_reloc_code_name (r_type
));
2176 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, r_type
);
2177 if (rel
->howto
== NULL
)
2179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2180 _("Cannot represent relocation type %s"),
2181 bfd_get_reloc_code_name (r_type
));