1 /* tc-h8300.c -- Assemble code for the Renesas H8/300
2 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Written By Steve Chamberlain <sac@cygnus.com>. */
30 #include "dwarf2dbg.h"
34 #define h8_opcodes ops
35 #include "opcode/h8300.h"
36 #include "safe-ctype.h"
42 const char comment_chars
[] = ";";
43 const char line_comment_chars
[] = "#";
44 const char line_separator_chars
[] = "";
46 static void sbranch (int);
47 static void h8300hmode (int);
48 static void h8300smode (int);
49 static void h8300hnmode (int);
50 static void h8300snmode (int);
51 static void h8300sxmode (int);
52 static void h8300sxnmode (int);
53 static void pint (int);
60 #define PSIZE (Hmode && !Nmode ? L_32 : L_16)
62 static int bsize
= L_8
; /* Default branch displacement. */
70 const struct h8_opcode
*opcode
;
73 static struct h8_instruction
*h8_instructions
;
76 h8300hmode (int arg ATTRIBUTE_UNUSED
)
81 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300h
))
82 as_warn (_("could not set architecture and machine"));
87 h8300smode (int arg ATTRIBUTE_UNUSED
)
92 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300s
))
93 as_warn (_("could not set architecture and machine"));
98 h8300hnmode (int arg ATTRIBUTE_UNUSED
)
104 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300hn
))
105 as_warn (_("could not set architecture and machine"));
110 h8300snmode (int arg ATTRIBUTE_UNUSED
)
116 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sn
))
117 as_warn (_("could not set architecture and machine"));
122 h8300sxmode (int arg ATTRIBUTE_UNUSED
)
128 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sx
))
129 as_warn (_("could not set architecture and machine"));
134 h8300sxnmode (int arg ATTRIBUTE_UNUSED
)
141 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300sxn
))
142 as_warn (_("could not set architecture and machine"));
153 pint (int arg ATTRIBUTE_UNUSED
)
155 cons (Hmode
? 4 : 2);
158 /* This table describes all the machine specific pseudo-ops the assembler
159 has to support. The fields are:
160 pseudo-op name without dot
161 function to call to execute this pseudo-op
162 Integer arg to pass to the function. */
164 const pseudo_typeS md_pseudo_table
[] =
166 {"h8300h", h8300hmode
, 0},
167 {"h8300hn", h8300hnmode
, 0},
168 {"h8300s", h8300smode
, 0},
169 {"h8300sn", h8300snmode
, 0},
170 {"h8300sx", h8300sxmode
, 0},
171 {"h8300sxn", h8300sxnmode
, 0},
172 {"sbranch", sbranch
, L_8
},
173 {"lbranch", sbranch
, L_16
},
179 {"form", listing_psize
, 0},
180 {"heading", listing_title
, 0},
181 {"import", s_ignore
, 0},
182 {"page", listing_eject
, 0},
183 {"program", s_ignore
, 0},
187 const int md_reloc_size
;
189 const char EXP_CHARS
[] = "eE";
191 /* Chars that mean this number is a floating point constant
194 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
196 static struct hash_control
*opcode_hash_control
; /* Opcode mnemonics. */
198 /* This function is called once, at assembler startup time. This
199 should set up all the tables, etc. that the MD part of the assembler
205 unsigned int nopcodes
;
206 struct h8_opcode
*p
, *p1
;
207 struct h8_instruction
*pi
;
208 char prev_buffer
[100];
212 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_h8300
, bfd_mach_h8300
))
213 as_warn (_("could not set architecture and machine"));
216 opcode_hash_control
= hash_new ();
219 nopcodes
= sizeof (h8_opcodes
) / sizeof (struct h8_opcode
);
221 h8_instructions
= (struct h8_instruction
*)
222 xmalloc (nopcodes
* sizeof (struct h8_instruction
));
224 pi
= h8_instructions
;
226 /* We do a minimum amount of sorting on the opcode table; this is to
227 make it easy to describe the mova instructions without unnecessary
229 Sorting only takes place inside blocks of instructions of the form
230 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */
233 struct h8_opcode
*first_skipped
= 0;
235 char *src
= p1
->name
;
240 /* Strip off any . part when inserting the opcode and only enter
241 unique codes into the hash table. */
242 dst
= buffer
= malloc (strlen (src
) + 1);
251 cmplen
= src
- p1
->name
+ 1;
258 hash_insert (opcode_hash_control
, buffer
, (char *) pi
);
259 strcpy (prev_buffer
, buffer
);
262 for (p
= p1
; p
->name
; p
++)
264 /* A negative TIME is used to indicate that we've added this opcode
268 if (strncmp (p
->name
, buffer
, cmplen
) != 0
269 || (p
->name
[cmplen
] != '\0' && p
->name
[cmplen
] != '.'
270 && p
->name
[cmplen
- 1] != '/'))
272 if (first_skipped
== 0)
276 if (strncmp (p
->name
, buffer
, len
) != 0)
278 if (first_skipped
== 0)
284 pi
->size
= p
->name
[len
] == '.' ? p
->name
[len
+ 1] : 0;
287 /* Find the number of operands. */
289 while (pi
->noperands
< 3 && p
->args
.nib
[pi
->noperands
] != (op_type
) E
)
292 /* Find the length of the opcode in bytes. */
294 while (p
->data
.nib
[pi
->length
* 2] != (op_type
) E
)
303 /* Add entry for the NULL vector terminator. */
320 static void clever_message (const struct h8_instruction
*, struct h8_op
*);
321 static void fix_operand_size (struct h8_op
*, int);
322 static void build_bytes (const struct h8_instruction
*, struct h8_op
*);
323 static void do_a_fix_imm (int, int, struct h8_op
*, int);
324 static void check_operand (struct h8_op
*, unsigned int, char *);
325 static const struct h8_instruction
* get_specific (const struct h8_instruction
*, struct h8_op
*, int) ;
326 static char *get_operands (unsigned, char *, struct h8_op
*);
327 static void get_operand (char **, struct h8_op
*, int);
328 static int parse_reg (char *, op_type
*, unsigned *, int);
329 static char *skip_colonthing (char *, int *);
330 static char *parse_exp (char *, struct h8_op
*);
332 static int constant_fits_width_p (struct h8_op
*, unsigned int);
333 static int constant_fits_size_p (struct h8_op
*, int, int);
337 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
346 /* Try to parse a reg name. Return the number of chars consumed. */
349 parse_reg (char *src
, op_type
*mode
, unsigned int *reg
, int direction
)
354 /* Cribbed from get_symbol_end. */
355 if (!is_name_beginner (*src
) || *src
== '\001')
358 while ((is_part_of_name (*end
) && *end
!= '.') || *end
== '\001')
362 if (len
== 2 && TOLOWER (src
[0]) == 's' && TOLOWER (src
[1]) == 'p')
364 *mode
= PSIZE
| REG
| direction
;
369 TOLOWER (src
[0]) == 'c' &&
370 TOLOWER (src
[1]) == 'c' &&
371 TOLOWER (src
[2]) == 'r')
378 TOLOWER (src
[0]) == 'e' &&
379 TOLOWER (src
[1]) == 'x' &&
380 TOLOWER (src
[2]) == 'r')
387 TOLOWER (src
[0]) == 'v' &&
388 TOLOWER (src
[1]) == 'b' &&
389 TOLOWER (src
[2]) == 'r')
396 TOLOWER (src
[0]) == 's' &&
397 TOLOWER (src
[1]) == 'b' &&
398 TOLOWER (src
[2]) == 'r')
404 if (len
== 2 && TOLOWER (src
[0]) == 'f' && TOLOWER (src
[1]) == 'p')
406 *mode
= PSIZE
| REG
| direction
;
410 if (len
== 3 && TOLOWER (src
[0]) == 'e' && TOLOWER (src
[1]) == 'r' &&
411 src
[2] >= '0' && src
[2] <= '7')
413 *mode
= L_32
| REG
| direction
;
416 as_warn (_("Reg not valid for H8/300"));
419 if (len
== 2 && TOLOWER (src
[0]) == 'e' && src
[1] >= '0' && src
[1] <= '7')
421 *mode
= L_16
| REG
| direction
;
422 *reg
= src
[1] - '0' + 8;
424 as_warn (_("Reg not valid for H8/300"));
428 if (TOLOWER (src
[0]) == 'r')
430 if (src
[1] >= '0' && src
[1] <= '7')
432 if (len
== 3 && TOLOWER (src
[2]) == 'l')
434 *mode
= L_8
| REG
| direction
;
435 *reg
= (src
[1] - '0') + 8;
438 if (len
== 3 && TOLOWER (src
[2]) == 'h')
440 *mode
= L_8
| REG
| direction
;
441 *reg
= (src
[1] - '0');
446 *mode
= L_16
| REG
| direction
;
447 *reg
= (src
[1] - '0');
457 /* Parse an immediate or address-related constant and store it in OP.
458 If the user also specifies the operand's size, store that size
459 in OP->MODE, otherwise leave it for later code to decide. */
462 parse_exp (char *src
, struct h8_op
*op
)
466 save
= input_line_pointer
;
467 input_line_pointer
= src
;
468 expression (&op
->exp
);
469 if (op
->exp
.X_op
== O_absent
)
470 as_bad (_("missing operand"));
471 src
= input_line_pointer
;
472 input_line_pointer
= save
;
474 return skip_colonthing (src
, &op
->mode
);
478 /* If SRC starts with an explicit operand size, skip it and store the size
479 in *MODE. Leave *MODE unchanged otherwise. */
482 skip_colonthing (char *src
, int *mode
)
488 if (src
[0] == '8' && !ISDIGIT (src
[1]))
490 else if (src
[0] == '2' && !ISDIGIT (src
[1]))
492 else if (src
[0] == '3' && !ISDIGIT (src
[1]))
494 else if (src
[0] == '4' && !ISDIGIT (src
[1]))
496 else if (src
[0] == '5' && !ISDIGIT (src
[1]))
498 else if (src
[0] == '2' && src
[1] == '4' && !ISDIGIT (src
[2]))
500 else if (src
[0] == '3' && src
[1] == '2' && !ISDIGIT (src
[2]))
502 else if (src
[0] == '1' && src
[1] == '6' && !ISDIGIT (src
[2]))
505 as_bad (_("invalid operand size requested"));
507 while (ISDIGIT (*src
))
513 /* The many forms of operand:
516 @Rn Register indirect
517 @(exp[:16], Rn) Register indirect with displacement
521 @aa:16 absolute 16 bit
524 #xx[:size] immediate data
525 @(exp:[8], pc) pc rel
526 @@aa[:8] memory indirect. */
529 constant_fits_width_p (struct h8_op
*operand
, unsigned int width
)
531 return ((operand
->exp
.X_add_number
& ~width
) == 0
532 || (operand
->exp
.X_add_number
| width
) == (unsigned)(~0));
536 constant_fits_size_p (struct h8_op
*operand
, int size
, int no_symbols
)
538 offsetT num
= operand
->exp
.X_add_number
;
540 && (operand
->exp
.X_add_symbol
!= 0 || operand
->exp
.X_op_symbol
!= 0))
545 return (num
& ~3) == 0;
547 return (num
& ~7) == 0;
549 return num
>= 1 && num
< 8;
551 return (num
& ~15) == 0;
553 return num
>= 1 && num
< 32;
555 return (num
& ~0xFF) == 0 || ((unsigned)num
| 0x7F) == ~0u;
557 return (num
& ~0xFF) == 0;
559 return (num
& ~0xFFFF) == 0 || ((unsigned)num
| 0x7FFF) == ~0u;
561 return (num
& ~0xFFFF) == 0;
570 get_operand (char **ptr
, struct h8_op
*op
, int direction
)
579 /* Check for '(' and ')' for instructions ldm and stm. */
580 if (src
[0] == '(' && src
[8] == ')')
583 /* Gross. Gross. ldm and stm have a format not easily handled
584 by get_operand. We deal with it explicitly here. */
585 if (TOLOWER (src
[0]) == 'e' && TOLOWER (src
[1]) == 'r' &&
586 ISDIGIT (src
[2]) && src
[3] == '-' &&
587 TOLOWER (src
[4]) == 'e' && TOLOWER (src
[5]) == 'r' && ISDIGIT (src
[6]))
594 /* Check register pair's validity as per tech note TN-H8*-193A/E
595 from Renesas for H8S and H8SX hardware manual. */
596 if ( !(low
== 0 && (high
== 1 || high
== 2 || high
== 3))
597 && !(low
== 1 && (high
== 2 || high
== 3 || high
== 4) && SXmode
)
598 && !(low
== 2 && (high
== 3 || ((high
== 4 || high
== 5) && SXmode
)))
599 && !(low
== 3 && (high
== 4 || high
== 5 || high
== 6) && SXmode
)
600 && !(low
== 4 && (high
== 5 || high
== 6))
601 && !(low
== 4 && high
== 7 && SXmode
)
602 && !(low
== 5 && (high
== 6 || high
== 7) && SXmode
)
603 && !(low
== 6 && high
== 7 && SXmode
))
604 as_bad (_("Invalid register list for ldm/stm\n"));
606 /* Even sicker. We encode two registers into op->reg. One
607 for the low register to save, the other for the high
608 register to save; we also set the high bit in op->reg
609 so we know this is "very special". */
610 op
->reg
= 0x80000000 | (high
<< 8) | low
;
619 len
= parse_reg (src
, &op
->mode
, &op
->reg
, direction
);
625 int size
= op
->mode
& SIZE
;
630 as_warn (_("mismatch between register and suffix"));
631 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
634 if (size
!= L_32
&& size
!= L_16
)
635 as_warn (_("mismatch between register and suffix"));
636 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
637 op
->mode
= (op
->mode
& ~SIZE
) | L_16
;
640 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
641 if (size
!= L_32
&& size
!= L_8
)
642 as_warn (_("mismatch between register and suffix"));
643 op
->mode
= (op
->mode
& ~MODE
) | LOWREG
;
644 op
->mode
= (op
->mode
& ~SIZE
) | L_8
;
647 as_warn ("invalid suffix after register.");
661 *ptr
= parse_exp (src
+ 1, op
);
662 if (op
->exp
.X_add_number
>= 0x100)
667 /* FIXME : 2? or 4? */
668 if (op
->exp
.X_add_number
>= 0x400)
669 as_bad (_("address too high for vector table jmp/jsr"));
670 else if (op
->exp
.X_add_number
>= 0x200)
675 op
->exp
.X_add_number
= op
->exp
.X_add_number
/ divisor
- 0x80;
682 if (*src
== '-' || *src
== '+')
684 len
= parse_reg (src
+ 1, &mode
, &num
, direction
);
687 /* Oops, not a reg after all, must be ordinary exp. */
688 op
->mode
= ABS
| direction
;
689 *ptr
= parse_exp (src
, op
);
693 if (((mode
& SIZE
) != PSIZE
)
694 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
695 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
696 as_bad (_("Wrong size pointer register for architecture."));
698 op
->mode
= src
[0] == '-' ? RDPREDEC
: RDPREINC
;
700 *ptr
= src
+ 1 + len
;
707 /* See if this is @(ERn.x, PC). */
708 len
= parse_reg (src
, &mode
, &op
->reg
, direction
);
709 if (len
!= 0 && (mode
& MODE
) == REG
&& src
[len
] == '.')
711 switch (TOLOWER (src
[len
+ 1]))
714 mode
= PCIDXB
| direction
;
717 mode
= PCIDXW
| direction
;
720 mode
= PCIDXL
| direction
;
727 && src
[len
+ 2] == ','
728 && TOLOWER (src
[len
+ 3]) != 'p'
729 && TOLOWER (src
[len
+ 4]) != 'c'
730 && src
[len
+ 5] != ')')
732 *ptr
= src
+ len
+ 6;
736 /* Fall through into disp case - the grammar is somewhat
737 ambiguous, so we should try whether it's a DISP operand
738 after all ("ER3.L" might be a poorly named label...). */
743 /* Start off assuming a 16 bit offset. */
745 src
= parse_exp (src
, op
);
748 op
->mode
|= ABS
| direction
;
755 as_bad (_("expected @(exp, reg16)"));
760 len
= parse_reg (src
, &mode
, &op
->reg
, direction
);
761 if (len
== 0 || (mode
& MODE
) != REG
)
763 as_bad (_("expected @(exp, reg16)"));
769 switch (TOLOWER (src
[1]))
772 op
->mode
|= INDEXB
| direction
;
775 op
->mode
|= INDEXW
| direction
;
778 op
->mode
|= INDEXL
| direction
;
781 as_bad (_("expected .L, .W or .B for register in indexed addressing mode"));
787 op
->mode
|= DISP
| direction
;
788 src
= skip_colonthing (src
, &op
->mode
);
790 if (*src
!= ')' && '(')
792 as_bad (_("expected @(exp, reg16)"));
798 len
= parse_reg (src
, &mode
, &num
, direction
);
803 if (*src
== '+' || *src
== '-')
805 if (((mode
& SIZE
) != PSIZE
)
806 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
807 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
808 as_bad (_("Wrong size pointer register for architecture."));
809 op
->mode
= *src
== '+' ? RSPOSTINC
: RSPOSTDEC
;
815 if (((mode
& SIZE
) != PSIZE
)
816 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
817 && (!Nmode
|| ((mode
& SIZE
) != L_32
)))
818 as_bad (_("Wrong size pointer register for architecture."));
820 op
->mode
= direction
| IND
| PSIZE
;
828 /* must be a symbol */
830 op
->mode
= ABS
| direction
;
831 *ptr
= parse_exp (src
, op
);
839 *ptr
= parse_exp (src
+ 1, op
);
842 else if (strncmp (src
, "mach", 4) == 0 ||
843 strncmp (src
, "macl", 4) == 0 ||
844 strncmp (src
, "MACH", 4) == 0 ||
845 strncmp (src
, "MACL", 4) == 0)
847 op
->reg
= TOLOWER (src
[3]) == 'l';
855 *ptr
= parse_exp (src
, op
);
860 get_operands (unsigned int noperands
, char *op_end
, struct h8_op
*operand
)
871 get_operand (&ptr
, operand
+ 0, SRC
);
875 get_operand (&ptr
, operand
+ 1, DST
);
881 get_operand (&ptr
, operand
+ 0, SRC
);
884 get_operand (&ptr
, operand
+ 1, DST
);
889 get_operand (&ptr
, operand
+ 0, SRC
);
892 get_operand (&ptr
, operand
+ 1, DST
);
895 get_operand (&ptr
, operand
+ 2, OP3
);
905 /* MOVA has special requirements. Rather than adding twice the amount of
906 addressing modes, we simply special case it a bit. */
908 get_mova_operands (char *op_end
, struct h8_op
*operand
)
912 if (ptr
[1] != '@' || ptr
[2] != '(')
916 ptr
= parse_exp (ptr
, &operand
[0]);
921 get_operand (&ptr
, operand
+ 1, DST
);
929 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXB
;
932 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXW
;
935 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXL
;
941 else if ((operand
[1].mode
& MODE
) == LOWREG
)
943 switch (operand
[1].mode
& SIZE
)
946 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXB
;
949 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXW
;
952 operand
[0].mode
= (operand
[0].mode
& ~MODE
) | INDEXL
;
961 if (*ptr
++ != ')' || *ptr
++ != ',')
963 get_operand (&ptr
, operand
+ 2, OP3
);
964 /* See if we can use the short form of MOVA. */
965 if (((operand
[1].mode
& MODE
) == REG
|| (operand
[1].mode
& MODE
) == LOWREG
)
966 && (operand
[2].mode
& MODE
) == REG
967 && (operand
[1].reg
& 7) == (operand
[2].reg
& 7))
969 operand
[1].mode
= operand
[2].mode
= 0;
970 operand
[0].reg
= operand
[2].reg
& 7;
975 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""));
979 get_rtsl_operands (char *ptr
, struct h8_op
*operand
)
981 int mode
, num
, num2
, len
, type
= 0;
989 len
= parse_reg (ptr
, &mode
, &num
, SRC
);
990 if (len
== 0 || (mode
& MODE
) != REG
)
992 as_bad (_("expected register"));
998 len
= parse_reg (++ptr
, &mode
, &num2
, SRC
);
999 if (len
== 0 || (mode
& MODE
) != REG
)
1001 as_bad (_("expected register"));
1005 /* CONST_xxx are used as placeholders in the opcode table. */
1007 if (num
< 0 || num
> 3)
1009 as_bad (_("invalid register list"));
1014 num2
= num
, num
= 0;
1015 if (type
== 1 && *ptr
++ != ')')
1017 as_bad (_("expected closing paren"));
1020 operand
[0].mode
= RS32
;
1021 operand
[1].mode
= RD32
;
1022 operand
[0].reg
= num
;
1023 operand
[1].reg
= num2
;
1026 /* Passed a pointer to a list of opcodes which use different
1027 addressing modes, return the opcode which matches the opcodes
1030 static const struct h8_instruction
*
1031 get_specific (const struct h8_instruction
*instruction
,
1032 struct h8_op
*operands
, int size
)
1034 const struct h8_instruction
*this_try
= instruction
;
1035 const struct h8_instruction
*found_other
= 0, *found_mismatched
= 0;
1037 int this_index
= instruction
->idx
;
1040 /* There's only one ldm/stm and it's easier to just
1041 get out quick for them. */
1042 if (OP_KIND (instruction
->opcode
->how
) == O_LDM
1043 || OP_KIND (instruction
->opcode
->how
) == O_STM
)
1046 while (noperands
< 3 && operands
[noperands
].mode
!= 0)
1049 while (this_index
== instruction
->idx
&& !found
)
1054 this_try
= instruction
++;
1055 this_size
= this_try
->opcode
->how
& SN
;
1057 if (this_try
->noperands
!= noperands
)
1059 else if (this_try
->noperands
> 0)
1063 for (i
= 0; i
< this_try
->noperands
&& found
; i
++)
1065 op_type op
= this_try
->opcode
->args
.nib
[i
];
1066 int op_mode
= op
& MODE
;
1067 int op_size
= op
& SIZE
;
1068 int x
= operands
[i
].mode
;
1069 int x_mode
= x
& MODE
;
1070 int x_size
= x
& SIZE
;
1072 if (op_mode
== LOWREG
&& (x_mode
== REG
|| x_mode
== LOWREG
))
1074 if ((x_size
== L_8
&& (operands
[i
].reg
& 8) == 0)
1075 || (x_size
== L_16
&& (operands
[i
].reg
& 8) == 8))
1076 as_warn (_("can't use high part of register in operand %d"), i
);
1078 if (x_size
!= op_size
)
1081 else if (op_mode
== REG
)
1083 if (x_mode
== LOWREG
)
1089 x_size
= (Hmode
? L_32
: L_16
);
1091 op_size
= (Hmode
? L_32
: L_16
);
1093 /* The size of the reg is v important. */
1094 if (op_size
!= x_size
)
1097 else if (op_mode
& CTRL
) /* control register */
1099 if (!(x_mode
& CTRL
))
1105 if (op_mode
!= CCR
&&
1106 op_mode
!= CCR_EXR
&&
1107 op_mode
!= CC_EX_VB_SB
)
1111 if (op_mode
!= EXR
&&
1112 op_mode
!= CCR_EXR
&&
1113 op_mode
!= CC_EX_VB_SB
)
1117 if (op_mode
!= MACH
&&
1122 if (op_mode
!= MACL
&&
1127 if (op_mode
!= VBR
&&
1128 op_mode
!= VBR_SBR
&&
1129 op_mode
!= CC_EX_VB_SB
)
1133 if (op_mode
!= SBR
&&
1134 op_mode
!= VBR_SBR
&&
1135 op_mode
!= CC_EX_VB_SB
)
1140 else if ((op
& ABSJMP
) && (x_mode
== ABS
|| x_mode
== PCREL
))
1142 operands
[i
].mode
&= ~MODE
;
1143 operands
[i
].mode
|= ABSJMP
;
1144 /* But it may not be 24 bits long. */
1145 if (x_mode
== ABS
&& !Hmode
)
1147 operands
[i
].mode
&= ~SIZE
;
1148 operands
[i
].mode
|= L_16
;
1150 if ((operands
[i
].mode
& SIZE
) == L_32
1151 && (op_mode
& SIZE
) != L_32
)
1154 else if (x_mode
== IMM
&& op_mode
!= IMM
)
1156 offsetT num
= operands
[i
].exp
.X_add_number
;
1157 if (op_mode
== KBIT
|| op_mode
== DBIT
)
1158 /* This is ok if the immediate value is sensible. */;
1159 else if (op_mode
== CONST_2
)
1161 else if (op_mode
== CONST_4
)
1163 else if (op_mode
== CONST_8
)
1165 else if (op_mode
== CONST_16
)
1170 else if (op_mode
== PCREL
&& op_mode
== x_mode
)
1172 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour:
1173 If x_size is L_8, promote it. */
1174 if (OP_KIND (this_try
->opcode
->how
) == O_MOVSD
1175 || OP_KIND (this_try
->opcode
->how
) == O_BSRBC
1176 || OP_KIND (this_try
->opcode
->how
) == O_BSRBS
)
1180 /* The size of the displacement is important. */
1181 if (op_size
!= x_size
)
1184 else if ((op_mode
== DISP
|| op_mode
== IMM
|| op_mode
== ABS
1185 || op_mode
== INDEXB
|| op_mode
== INDEXW
1186 || op_mode
== INDEXL
)
1187 && op_mode
== x_mode
)
1189 /* Promote a L_24 to L_32 if it makes us match. */
1190 if (x_size
== L_24
&& op_size
== L_32
)
1196 if (((x_size
== L_16
&& op_size
== L_16U
)
1197 || (x_size
== L_8
&& op_size
== L_8U
)
1198 || (x_size
== L_3
&& op_size
== L_3NZ
))
1199 /* We're deliberately more permissive for ABS modes. */
1201 || constant_fits_size_p (operands
+ i
, op_size
,
1205 if (x_size
!= 0 && op_size
!= x_size
)
1207 else if (x_size
== 0
1208 && ! constant_fits_size_p (operands
+ i
, op_size
,
1212 else if (op_mode
!= x_mode
)
1220 if ((this_try
->opcode
->available
== AV_H8SX
&& ! SXmode
)
1221 || (this_try
->opcode
->available
== AV_H8S
&& ! Smode
)
1222 || (this_try
->opcode
->available
== AV_H8H
&& ! Hmode
))
1223 found
= 0, found_other
= this_try
;
1224 else if (this_size
!= size
&& (this_size
!= SN
&& size
!= SN
))
1225 found_mismatched
= this_try
, found
= 0;
1233 as_warn (_("Opcode `%s' with these operand types not available in %s mode"),
1234 found_other
->opcode
->name
,
1235 (! Hmode
&& ! Smode
? "H8/300"
1240 else if (found_mismatched
)
1242 as_warn (_("mismatch between opcode size and operand size"));
1243 return found_mismatched
;
1249 check_operand (struct h8_op
*operand
, unsigned int width
, char *string
)
1251 if (operand
->exp
.X_add_symbol
== 0
1252 && operand
->exp
.X_op_symbol
== 0)
1254 /* No symbol involved, let's look at offset, it's dangerous if
1255 any of the high bits are not 0 or ff's, find out by oring or
1256 anding with the width and seeing if the answer is 0 or all
1259 if (! constant_fits_width_p (operand
, width
))
1262 && (operand
->exp
.X_add_number
& 0xff00) == 0xff00)
1264 /* Just ignore this one - which happens when trying to
1265 fit a 16 bit address truncated into an 8 bit address
1266 of something like bset. */
1268 else if (strcmp (string
, "@") == 0
1270 && (operand
->exp
.X_add_number
& 0xff8000) == 0xff8000)
1272 /* Just ignore this one - which happens when trying to
1273 fit a 24 bit address truncated into a 16 bit address
1274 of something like mov.w. */
1278 as_warn (_("operand %s0x%lx out of range."), string
,
1279 (unsigned long) operand
->exp
.X_add_number
);
1285 /* RELAXMODE has one of 3 values:
1287 0 Output a "normal" reloc, no relaxing possible for this insn/reloc
1289 1 Output a relaxable 24bit absolute mov.w address relocation
1290 (may relax into a 16bit absolute address).
1292 2 Output a relaxable 16/24 absolute mov.b address relocation
1293 (may relax into an 8bit absolute address). */
1296 do_a_fix_imm (int offset
, int nibble
, struct h8_op
*operand
, int relaxmode
)
1301 char *bytes
= frag_now
->fr_literal
+ offset
;
1303 char *t
= ((operand
->mode
& MODE
) == IMM
) ? "#" : "@";
1305 if (operand
->exp
.X_add_symbol
== 0)
1307 switch (operand
->mode
& SIZE
)
1310 check_operand (operand
, 0x3, t
);
1311 bytes
[0] |= (operand
->exp
.X_add_number
& 3) << (nibble
? 0 : 4);
1315 check_operand (operand
, 0x7, t
);
1316 bytes
[0] |= (operand
->exp
.X_add_number
& 7) << (nibble
? 0 : 4);
1319 check_operand (operand
, 0xF, t
);
1320 bytes
[0] |= (operand
->exp
.X_add_number
& 15) << (nibble
? 0 : 4);
1323 check_operand (operand
, 0x1F, t
);
1324 bytes
[0] |= operand
->exp
.X_add_number
& 31;
1328 check_operand (operand
, 0xff, t
);
1329 bytes
[0] |= operand
->exp
.X_add_number
;
1333 check_operand (operand
, 0xffff, t
);
1334 bytes
[0] |= operand
->exp
.X_add_number
>> 8;
1335 bytes
[1] |= operand
->exp
.X_add_number
>> 0;
1338 check_operand (operand
, 0xffffff, t
);
1339 bytes
[0] |= operand
->exp
.X_add_number
>> 16;
1340 bytes
[1] |= operand
->exp
.X_add_number
>> 8;
1341 bytes
[2] |= operand
->exp
.X_add_number
>> 0;
1345 /* This should be done with bfd. */
1346 bytes
[0] |= operand
->exp
.X_add_number
>> 24;
1347 bytes
[1] |= operand
->exp
.X_add_number
>> 16;
1348 bytes
[2] |= operand
->exp
.X_add_number
>> 8;
1349 bytes
[3] |= operand
->exp
.X_add_number
>> 0;
1352 idx
= (relaxmode
== 2) ? R_MOV24B1
: R_MOVL1
;
1353 fix_new_exp (frag_now
, offset
, 4, &operand
->exp
, 0, idx
);
1360 switch (operand
->mode
& SIZE
)
1365 where
= (operand
->mode
& SIZE
) == L_24
? -1 : 0;
1368 else if (relaxmode
== 1)
1374 as_bad (_("Can't work out size of operand.\n"));
1383 operand
->exp
.X_add_number
=
1384 ((operand
->exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1385 operand
->exp
.X_add_number
|= (bytes
[0] << 8) | bytes
[1];
1391 operand
->exp
.X_add_number
=
1392 ((operand
->exp
.X_add_number
& 0xff) ^ 0x80) - 0x80;
1393 operand
->exp
.X_add_number
|= bytes
[0];
1396 fix_new_exp (frag_now
,
1405 /* Now we know what sort of opcodes it is, let's build the bytes. */
1408 build_bytes (const struct h8_instruction
*this_try
, struct h8_op
*operand
)
1411 char *output
= frag_more (this_try
->length
);
1412 op_type
*nibble_ptr
= this_try
->opcode
->data
.nib
;
1414 unsigned int nibble_count
= 0;
1418 char asnibbles
[100];
1419 char *p
= asnibbles
;
1422 if (!Hmode
&& this_try
->opcode
->available
!= AV_H8
)
1423 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
1424 this_try
->opcode
->name
);
1426 && this_try
->opcode
->available
!= AV_H8
1427 && this_try
->opcode
->available
!= AV_H8H
)
1428 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
1429 this_try
->opcode
->name
);
1431 && this_try
->opcode
->available
!= AV_H8
1432 && this_try
->opcode
->available
!= AV_H8H
1433 && this_try
->opcode
->available
!= AV_H8S
)
1434 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"),
1435 this_try
->opcode
->name
);
1437 while (*nibble_ptr
!= (op_type
) E
)
1444 d
= (c
& OP3
) == OP3
? 2 : (c
& DST
) == DST
? 1 : 0;
1452 if (c2
== REG
|| c2
== LOWREG
1453 || c2
== IND
|| c2
== PREINC
|| c2
== PREDEC
1454 || c2
== POSTINC
|| c2
== POSTDEC
)
1456 nib
= operand
[d
].reg
;
1461 else if (c
& CTRL
) /* Control reg operand. */
1462 nib
= operand
[d
].reg
;
1464 else if ((c
& DISPREG
) == (DISPREG
))
1466 nib
= operand
[d
].reg
;
1470 operand
[d
].mode
= c
;
1471 op_at
[d
] = nibble_count
;
1474 else if (c2
== IMM
|| c2
== PCREL
|| c2
== ABS
1475 || (c
& ABSJMP
) || c2
== DISP
)
1477 operand
[d
].mode
= c
;
1478 op_at
[d
] = nibble_count
;
1481 else if ((c
& IGNORE
) || (c
& DATA
))
1484 else if (c2
== DBIT
)
1486 switch (operand
[0].exp
.X_add_number
)
1495 as_bad (_("Need #1 or #2 here"));
1498 else if (c2
== KBIT
)
1500 switch (operand
[0].exp
.X_add_number
)
1510 as_warn (_("#4 not valid on H8/300."));
1515 as_bad (_("Need #1 or #2 here"));
1518 /* Stop it making a fix. */
1519 operand
[0].mode
= 0;
1523 operand
[d
].mode
|= MEMRELAX
;
1539 if (operand
[0].mode
== MACREG
)
1540 /* stmac has mac[hl] as the first operand. */
1541 nib
= 2 + operand
[0].reg
;
1543 /* ldmac has mac[hl] as the second operand. */
1544 nib
= 2 + operand
[1].reg
;
1552 /* Disgusting. Why, oh why didn't someone ask us for advice
1553 on the assembler format. */
1554 if (OP_KIND (this_try
->opcode
->how
) == O_LDM
)
1556 high
= (operand
[1].reg
>> 8) & 0xf;
1557 low
= (operand
[1].reg
) & 0xf;
1558 asnibbles
[2] = high
- low
;
1559 asnibbles
[7] = high
;
1561 else if (OP_KIND (this_try
->opcode
->how
) == O_STM
)
1563 high
= (operand
[0].reg
>> 8) & 0xf;
1564 low
= (operand
[0].reg
) & 0xf;
1565 asnibbles
[2] = high
- low
;
1569 for (i
= 0; i
< this_try
->length
; i
++)
1570 output
[i
] = (asnibbles
[i
* 2] << 4) | asnibbles
[i
* 2 + 1];
1572 /* Note if this is a movb or a bit manipulation instruction
1573 there is a special relaxation which only applies. */
1574 if ( this_try
->opcode
->how
== O (O_MOV
, SB
)
1575 || this_try
->opcode
->how
== O (O_BCLR
, SB
)
1576 || this_try
->opcode
->how
== O (O_BAND
, SB
)
1577 || this_try
->opcode
->how
== O (O_BIAND
, SB
)
1578 || this_try
->opcode
->how
== O (O_BILD
, SB
)
1579 || this_try
->opcode
->how
== O (O_BIOR
, SB
)
1580 || this_try
->opcode
->how
== O (O_BIST
, SB
)
1581 || this_try
->opcode
->how
== O (O_BIXOR
, SB
)
1582 || this_try
->opcode
->how
== O (O_BLD
, SB
)
1583 || this_try
->opcode
->how
== O (O_BNOT
, SB
)
1584 || this_try
->opcode
->how
== O (O_BOR
, SB
)
1585 || this_try
->opcode
->how
== O (O_BSET
, SB
)
1586 || this_try
->opcode
->how
== O (O_BST
, SB
)
1587 || this_try
->opcode
->how
== O (O_BTST
, SB
)
1588 || this_try
->opcode
->how
== O (O_BXOR
, SB
))
1591 /* Output any fixes. */
1592 for (i
= 0; i
< this_try
->noperands
; i
++)
1594 int x
= operand
[i
].mode
;
1595 int x_mode
= x
& MODE
;
1597 if (x_mode
== IMM
|| x_mode
== DISP
)
1598 do_a_fix_imm (output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1599 op_at
[i
] & 1, operand
+ i
, (x
& MEMRELAX
) != 0);
1601 else if (x_mode
== ABS
)
1602 do_a_fix_imm (output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1603 op_at
[i
] & 1, operand
+ i
,
1604 (x
& MEMRELAX
) ? movb
+ 1 : 0);
1606 else if (x_mode
== PCREL
)
1608 int size16
= (x
& SIZE
) == L_16
;
1609 int size
= size16
? 2 : 1;
1610 int type
= size16
? R_PCRWORD
: R_PCRBYTE
;
1613 check_operand (operand
+ i
, size16
? 0x7fff : 0x7f, "@");
1615 if (operand
[i
].exp
.X_add_number
& 1)
1616 as_warn (_("branch operand has odd offset (%lx)\n"),
1617 (unsigned long) operand
->exp
.X_add_number
);
1619 /* The COFF port has always been off by one, changing it
1620 now would be an incompatible change, so we leave it as-is.
1622 We don't want to do this for ELF as we want to be
1623 compatible with the proposed ELF format from Hitachi. */
1624 operand
[i
].exp
.X_add_number
-= 1;
1628 operand
[i
].exp
.X_add_number
=
1629 ((operand
[i
].exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1633 operand
[i
].exp
.X_add_number
=
1634 ((operand
[i
].exp
.X_add_number
& 0xff) ^ 0x80) - 0x80;
1639 operand
[i
].exp
.X_add_number
|= output
[op_at
[i
] / 2];
1641 fixP
= fix_new_exp (frag_now
,
1642 output
- frag_now
->fr_literal
+ op_at
[i
] / 2,
1647 fixP
->fx_signed
= 1;
1649 else if (x_mode
== MEMIND
)
1651 check_operand (operand
+ i
, 0xff, "@@");
1652 fix_new_exp (frag_now
,
1653 output
- frag_now
->fr_literal
+ 1,
1659 else if (x_mode
== VECIND
)
1661 check_operand (operand
+ i
, 0x7f, "@@");
1662 /* FIXME: approximating the effect of "B31" here...
1663 This is very hackish, and ought to be done a better way. */
1664 operand
[i
].exp
.X_add_number
|= 0x80;
1665 fix_new_exp (frag_now
,
1666 output
- frag_now
->fr_literal
+ 1,
1672 else if (x
& ABSJMP
)
1675 bfd_reloc_code_real_type reloc_type
= R_JMPL1
;
1678 /* To be compatible with the proposed H8 ELF format, we
1679 want the relocation's offset to point to the first byte
1680 that will be modified, not to the start of the instruction. */
1682 if ((operand
->mode
& SIZE
) == L_32
)
1685 reloc_type
= R_RELLONG
;
1691 /* This jmp may be a jump or a branch. */
1693 check_operand (operand
+ i
,
1694 SXmode
? 0xffffffff : Hmode
? 0xffffff : 0xffff,
1697 if (operand
[i
].exp
.X_add_number
& 1)
1698 as_warn (_("branch operand has odd offset (%lx)\n"),
1699 (unsigned long) operand
->exp
.X_add_number
);
1702 operand
[i
].exp
.X_add_number
=
1703 ((operand
[i
].exp
.X_add_number
& 0xffff) ^ 0x8000) - 0x8000;
1704 fix_new_exp (frag_now
,
1705 output
- frag_now
->fr_literal
+ where
,
1714 /* Try to give an intelligent error message for common and simple to
1718 clever_message (const struct h8_instruction
*instruction
,
1719 struct h8_op
*operand
)
1721 /* Find out if there was more than one possible opcode. */
1723 if ((instruction
+ 1)->idx
!= instruction
->idx
)
1727 /* Only one opcode of this flavour, try to guess which operand
1729 for (argn
= 0; argn
< instruction
->noperands
; argn
++)
1731 switch (instruction
->opcode
->args
.nib
[argn
])
1734 if (operand
[argn
].mode
!= RD16
)
1736 as_bad (_("destination operand must be 16 bit register"));
1743 if (operand
[argn
].mode
!= RS8
)
1745 as_bad (_("source operand must be 8 bit register"));
1751 if (operand
[argn
].mode
!= ABS16DST
)
1753 as_bad (_("destination operand must be 16bit absolute address"));
1758 if (operand
[argn
].mode
!= RD8
)
1760 as_bad (_("destination operand must be 8 bit register"));
1766 if (operand
[argn
].mode
!= ABS16SRC
)
1768 as_bad (_("source operand must be 16bit absolute address"));
1776 as_bad (_("invalid operands"));
1780 /* If OPERAND is part of an address, adjust its size and value given
1781 that it addresses SIZE bytes.
1783 This function decides how big non-immediate constants are when no
1784 size was explicitly given. It also scales down the assembly-level
1785 displacement in an @(d:2,ERn) operand. */
1788 fix_operand_size (struct h8_op
*operand
, int size
)
1790 if (SXmode
&& (operand
->mode
& MODE
) == DISP
)
1792 /* If the user didn't specify an operand width, see if we
1793 can use @(d:2,ERn). */
1794 if ((operand
->mode
& SIZE
) == 0
1795 && operand
->exp
.X_add_symbol
== 0
1796 && operand
->exp
.X_op_symbol
== 0
1797 && (operand
->exp
.X_add_number
== size
1798 || operand
->exp
.X_add_number
== size
* 2
1799 || operand
->exp
.X_add_number
== size
* 3))
1800 operand
->mode
|= L_2
;
1802 /* Scale down the displacement in an @(d:2,ERn) operand.
1803 X_add_number then contains the desired field value. */
1804 if ((operand
->mode
& SIZE
) == L_2
)
1806 if (operand
->exp
.X_add_number
% size
!= 0)
1807 as_warn (_("operand/size mis-match"));
1808 operand
->exp
.X_add_number
/= size
;
1812 if ((operand
->mode
& SIZE
) == 0)
1813 switch (operand
->mode
& MODE
)
1820 /* Pick a 24-bit address unless we know that a 16-bit address
1821 is safe. get_specific() will relax L_24 into L_32 where
1825 && (operand
->exp
.X_add_number
< -32768
1826 || operand
->exp
.X_add_number
> 32767
1827 || operand
->exp
.X_add_symbol
!= 0
1828 || operand
->exp
.X_op_symbol
!= 0))
1829 operand
->mode
|= L_24
;
1831 operand
->mode
|= L_16
;
1835 /* This condition is long standing, though somewhat suspect. */
1836 if (operand
->exp
.X_add_number
> -128
1837 && operand
->exp
.X_add_number
< 127)
1838 operand
->mode
|= L_8
;
1840 operand
->mode
|= L_16
;
1846 /* This is the guts of the machine-dependent assembler. STR points to
1847 a machine dependent instruction. This function is supposed to emit
1848 the frags/bytes it assembles. */
1851 md_assemble (char *str
)
1855 struct h8_op operand
[3];
1856 const struct h8_instruction
*instruction
;
1857 const struct h8_instruction
*prev_instruction
;
1864 /* Drop leading whitespace. */
1868 /* Find the op code end. */
1869 for (op_start
= op_end
= str
;
1870 *op_end
!= 0 && *op_end
!= ' ';
1880 else if (*op_end
== '/' && ! slash
)
1884 if (op_end
== op_start
)
1886 as_bad (_("can't find opcode "));
1892 /* The assembler stops scanning the opcode at slashes, so it fails
1893 to make characters following them lower case. Fix them. */
1896 *slash
= TOLOWER (*slash
);
1898 instruction
= (const struct h8_instruction
*)
1899 hash_find (opcode_hash_control
, op_start
);
1901 if (instruction
== NULL
)
1903 as_bad (_("unknown opcode"));
1907 /* We used to set input_line_pointer to the result of get_operands,
1908 but that is wrong. Our caller assumes we don't change it. */
1910 operand
[0].mode
= 0;
1911 operand
[1].mode
= 0;
1912 operand
[2].mode
= 0;
1914 if (OP_KIND (instruction
->opcode
->how
) == O_MOVAB
1915 || OP_KIND (instruction
->opcode
->how
) == O_MOVAW
1916 || OP_KIND (instruction
->opcode
->how
) == O_MOVAL
)
1917 get_mova_operands (op_end
, operand
);
1918 else if (OP_KIND (instruction
->opcode
->how
) == O_RTEL
1919 || OP_KIND (instruction
->opcode
->how
) == O_RTSL
)
1920 get_rtsl_operands (op_end
, operand
);
1922 get_operands (instruction
->noperands
, op_end
, operand
);
1925 prev_instruction
= instruction
;
1927 /* Now we have operands from instruction.
1928 Let's check them out for ldm and stm. */
1929 if (OP_KIND (instruction
->opcode
->how
) == O_LDM
)
1931 /* The first operand must be @er7+, and the
1932 second operand must be a register pair. */
1933 if ((operand
[0].mode
!= RSINC
)
1934 || (operand
[0].reg
!= 7)
1935 || ((operand
[1].reg
& 0x80000000) == 0))
1936 as_bad (_("invalid operand in ldm"));
1938 else if (OP_KIND (instruction
->opcode
->how
) == O_STM
)
1940 /* The first operand must be a register pair,
1941 and the second operand must be @-er7. */
1942 if (((operand
[0].reg
& 0x80000000) == 0)
1943 || (operand
[1].mode
!= RDDEC
)
1944 || (operand
[1].reg
!= 7))
1945 as_bad (_("invalid operand in stm"));
1951 switch (TOLOWER (*dot
))
1966 if (OP_KIND (instruction
->opcode
->how
) == O_MOVAB
||
1967 OP_KIND (instruction
->opcode
->how
) == O_MOVAW
||
1968 OP_KIND (instruction
->opcode
->how
) == O_MOVAL
)
1970 switch (operand
[0].mode
& MODE
)
1974 fix_operand_size (&operand
[1], 1);
1977 fix_operand_size (&operand
[1], 2);
1980 fix_operand_size (&operand
[1], 4);
1986 for (i
= 0; i
< 3 && operand
[i
].mode
!= 0; i
++)
1992 fix_operand_size (&operand
[i
], 1);
1995 fix_operand_size (&operand
[i
], 2);
1998 fix_operand_size (&operand
[i
], 4);
2003 instruction
= get_specific (instruction
, operand
, size
);
2005 if (instruction
== 0)
2007 /* Couldn't find an opcode which matched the operands. */
2008 char *where
= frag_more (2);
2012 clever_message (prev_instruction
, operand
);
2017 build_bytes (instruction
, operand
);
2019 #ifdef BFD_ASSEMBLER
2020 dwarf2_emit_insn (instruction
->length
);
2024 #ifndef BFD_ASSEMBLER
2026 tc_crawl_symbol_chain (object_headers
*headers ATTRIBUTE_UNUSED
)
2028 printf (_("call to tc_crawl_symbol_chain \n"));
2033 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
2038 #ifndef BFD_ASSEMBLER
2040 tc_headers_hook (object_headers
*headers ATTRIBUTE_UNUSED
)
2042 printf (_("call to tc_headers_hook \n"));
2046 /* Various routines to kill one day */
2047 /* Equal to MAX_PRECISION in atof-ieee.c */
2048 #define MAX_LITTLENUMS 6
2050 /* Turn a string in input_line_pointer into a floating point constant
2051 of type TYPE, and store the appropriate bytes in *LITP. The number
2052 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2053 returned, or NULL on OK. */
2056 md_atof (int type
, char *litP
, int *sizeP
)
2059 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2060 LITTLENUM_TYPE
*wordP
;
2091 return _("Bad call to MD_ATOF()");
2093 t
= atof_ieee (input_line_pointer
, type
, words
);
2095 input_line_pointer
= t
;
2097 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2098 for (wordP
= words
; prec
--;)
2100 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
2101 litP
+= sizeof (LITTLENUM_TYPE
);
2106 const char *md_shortopts
= "";
2107 struct option md_longopts
[] = {
2108 {NULL
, no_argument
, NULL
, 0}
2111 size_t md_longopts_size
= sizeof (md_longopts
);
2114 md_parse_option (int c ATTRIBUTE_UNUSED
, char *arg ATTRIBUTE_UNUSED
)
2120 md_show_usage (FILE *stream ATTRIBUTE_UNUSED
)
2124 void tc_aout_fix_to_chars (void);
2127 tc_aout_fix_to_chars (void)
2129 printf (_("call to tc_aout_fix_to_chars \n"));
2135 #ifdef BFD_ASSEMBLER
2136 bfd
*headers ATTRIBUTE_UNUSED
,
2138 object_headers
*headers ATTRIBUTE_UNUSED
,
2140 segT seg ATTRIBUTE_UNUSED
,
2141 fragS
*fragP ATTRIBUTE_UNUSED
)
2143 printf (_("call to md_convert_frag \n"));
2147 #ifdef BFD_ASSEMBLER
2149 md_section_align (segT segment
, valueT size
)
2151 int align
= bfd_get_section_alignment (stdoutput
, segment
);
2152 return ((size
+ (1 << align
) - 1) & (-1 << align
));
2156 md_section_align (segT seg
, valueT size
)
2158 return ((size
+ (1 << section_alignment
[(int) seg
]) - 1)
2159 & (-1 << section_alignment
[(int) seg
]));
2165 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2167 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2170 switch (fixP
->fx_size
)
2176 *buf
++ = (val
>> 8);
2180 *buf
++ = (val
>> 24);
2181 *buf
++ = (val
>> 16);
2182 *buf
++ = (val
>> 8);
2189 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
2194 md_estimate_size_before_relax (register fragS
*fragP ATTRIBUTE_UNUSED
,
2195 register segT segment_type ATTRIBUTE_UNUSED
)
2197 printf (_("call tomd_estimate_size_before_relax \n"));
2201 /* Put number into target byte order. */
2203 md_number_to_chars (char *ptr
, valueT use
, int nbytes
)
2205 number_to_chars_bigendian (ptr
, use
, nbytes
);
2209 md_pcrel_from (fixS
*fixP ATTRIBUTE_UNUSED
)
2214 #ifndef BFD_ASSEMBLER
2216 tc_reloc_mangle (fixS
*fix_ptr
, struct internal_reloc
*intr
, bfd_vma base
)
2218 symbolS
*symbol_ptr
;
2220 symbol_ptr
= fix_ptr
->fx_addsy
;
2222 /* If this relocation is attached to a symbol then it's ok
2224 if (fix_ptr
->fx_r_type
== TC_CONS_RELOC
)
2226 /* cons likes to create reloc32's whatever the size of the reloc..
2228 switch (fix_ptr
->fx_size
)
2231 intr
->r_type
= R_RELLONG
;
2234 intr
->r_type
= R_RELWORD
;
2237 intr
->r_type
= R_RELBYTE
;
2245 intr
->r_type
= fix_ptr
->fx_r_type
;
2248 intr
->r_vaddr
= fix_ptr
->fx_frag
->fr_address
+ fix_ptr
->fx_where
+ base
;
2249 intr
->r_offset
= fix_ptr
->fx_offset
;
2253 if (symbol_ptr
->sy_number
!= -1)
2254 intr
->r_symndx
= symbol_ptr
->sy_number
;
2259 /* This case arises when a reference is made to `.'. */
2260 segsym
= seg_info (S_GET_SEGMENT (symbol_ptr
))->dot
;
2262 intr
->r_symndx
= -1;
2265 intr
->r_symndx
= segsym
->sy_number
;
2266 intr
->r_offset
+= S_GET_VALUE (symbol_ptr
);
2271 intr
->r_symndx
= -1;
2273 #else /* BFD_ASSEMBLER */
2275 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2278 bfd_reloc_code_real_type r_type
;
2280 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
2282 if ((S_GET_SEGMENT (fixp
->fx_addsy
) != S_GET_SEGMENT (fixp
->fx_subsy
))
2283 || S_GET_SEGMENT (fixp
->fx_addsy
) == undefined_section
)
2285 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2286 "Difference of symbols in different sections is not supported");
2291 rel
= (arelent
*) xmalloc (sizeof (arelent
));
2292 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2293 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2294 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2295 rel
->addend
= fixp
->fx_offset
;
2297 r_type
= fixp
->fx_r_type
;
2301 fprintf (stderr
, "%s\n", bfd_get_reloc_code_name (r_type
));
2304 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, r_type
);
2305 if (rel
->howto
== NULL
)
2307 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2308 _("Cannot represent relocation type %s"),
2309 bfd_get_reloc_code_name (r_type
));