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x86: fold a few XOP templates
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88 #define END_OF_INSN '\0'
89
90 /*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97 typedef struct
98 {
99 const insn_template *start;
100 const insn_template *end;
101 }
102 templates;
103
104 /* 386 operand encoding bytes: see 386 book for details of this. */
105 typedef struct
106 {
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110 }
111 modrm_byte;
112
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
115
116 /* 386 opcode byte to code indirect addressing. */
117 typedef struct
118 {
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122 }
123 sib_byte;
124
125 /* x86 arch names, types and features */
126 typedef struct
127 {
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
133 }
134 arch_entry;
135
136 /* Used to turn off indicated flags. */
137 typedef struct
138 {
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142 }
143 noarch_entry;
144
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
153 #ifdef TE_PE
154 static void pe_directive_secrel (int);
155 #endif
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
186 #ifndef I386COFF
187 static void s_bss (int);
188 #endif
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
191 #endif
192
193 static const char *default_arch = DEFAULT_ARCH;
194
195 /* This struct describes rounding control and SAE in the instruction. */
196 struct RC_Operation
197 {
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207 };
208
209 static struct RC_Operation rc_op;
210
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
215 {
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220 };
221
222 static struct Mask_Operation mask_op;
223
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226 struct Broadcast_Operation
227 {
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233 };
234
235 static struct Broadcast_Operation broadcast_op;
236
237 /* VEX prefix. */
238 typedef struct
239 {
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245 } vex_prefix;
246
247 /* 'md_assemble ()' gathers together information and puts it into a
248 i386_insn. */
249
250 union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
257 enum i386_error
258 {
259 operand_size_mismatch,
260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
267 unsupported,
268 invalid_vsib_address,
269 invalid_vector_register_set,
270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
280 };
281
282 struct _i386_insn
283 {
284 /* TM holds the template for the insn were currently assembling. */
285 insn_template tm;
286
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
289 char suffix;
290
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
296 operands. */
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
302
303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
306
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
310
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
313
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
323
324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
334 modrm_byte rm;
335 rex_byte rex;
336 rex_byte vrex;
337 sib_byte sib;
338 vex_prefix vex;
339
340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
359
360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
367
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
383 /* REP prefix. */
384 const char *rep_prefix;
385
386 /* HLE prefix. */
387 const char *hle_prefix;
388
389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
395 /* Error message. */
396 enum i386_error error;
397 };
398
399 typedef struct _i386_insn i386_insn;
400
401 /* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403 struct RC_name
404 {
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408 };
409
410 static const struct RC_name RC_NamesTable[] =
411 {
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417 };
418
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars[] = "*%-([{}"
422 #ifdef LEX_AT
423 "@"
424 #endif
425 #ifdef LEX_QM
426 "?"
427 #endif
428 ;
429
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_NETWARE) \
436 && !defined (TE_FreeBSD) \
437 && !defined (TE_DragonFly) \
438 && !defined (TE_NetBSD)))
439 /* This array holds the chars that always start a comment. If the
440 pre-processor is disabled, these aren't very useful. The option
441 --divide will remove '/' from this list. */
442 const char *i386_comment_chars = "#/";
443 #define SVR4_COMMENT_CHARS 1
444 #define PREFIX_SEPARATOR '\\'
445
446 #else
447 const char *i386_comment_chars = "#";
448 #define PREFIX_SEPARATOR '/'
449 #endif
450
451 /* This array holds the chars that only start a comment at the beginning of
452 a line. If the line seems to have the form '# 123 filename'
453 .line and .file directives will appear in the pre-processed output.
454 Note that input_file.c hand checks for '#' at the beginning of the
455 first line of the input file. This is because the compiler outputs
456 #NO_APP at the beginning of its output.
457 Also note that comments started like this one will always work if
458 '/' isn't otherwise defined. */
459 const char line_comment_chars[] = "#/";
460
461 const char line_separator_chars[] = ";";
462
463 /* Chars that can be used to separate mant from exp in floating point
464 nums. */
465 const char EXP_CHARS[] = "eE";
466
467 /* Chars that mean this number is a floating point constant
468 As in 0f12.456
469 or 0d1.2345e12. */
470 const char FLT_CHARS[] = "fFdDxX";
471
472 /* Tables for lexical analysis. */
473 static char mnemonic_chars[256];
474 static char register_chars[256];
475 static char operand_chars[256];
476 static char identifier_chars[256];
477 static char digit_chars[256];
478
479 /* Lexical macros. */
480 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
481 #define is_operand_char(x) (operand_chars[(unsigned char) x])
482 #define is_register_char(x) (register_chars[(unsigned char) x])
483 #define is_space_char(x) ((x) == ' ')
484 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
485 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486
487 /* All non-digit non-letter characters that may occur in an operand. */
488 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
489
490 /* md_assemble() always leaves the strings it's passed unaltered. To
491 effect this we maintain a stack of saved characters that we've smashed
492 with '\0's (indicating end of strings for various sub-fields of the
493 assembler instruction). */
494 static char save_stack[32];
495 static char *save_stack_p;
496 #define END_STRING_AND_SAVE(s) \
497 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
498 #define RESTORE_END_STRING(s) \
499 do { *(s) = *--save_stack_p; } while (0)
500
501 /* The instruction we're assembling. */
502 static i386_insn i;
503
504 /* Possible templates for current insn. */
505 static const templates *current_templates;
506
507 /* Per instruction expressionS buffers: max displacements & immediates. */
508 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
509 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
510
511 /* Current operand we are working on. */
512 static int this_operand = -1;
513
514 /* We support four different modes. FLAG_CODE variable is used to distinguish
515 these. */
516
517 enum flag_code {
518 CODE_32BIT,
519 CODE_16BIT,
520 CODE_64BIT };
521
522 static enum flag_code flag_code;
523 static unsigned int object_64bit;
524 static unsigned int disallow_64bit_reloc;
525 static int use_rela_relocations = 0;
526
527 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
528 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
529 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530
531 /* The ELF ABI to use. */
532 enum x86_elf_abi
533 {
534 I386_ABI,
535 X86_64_ABI,
536 X86_64_X32_ABI
537 };
538
539 static enum x86_elf_abi x86_elf_abi = I386_ABI;
540 #endif
541
542 #if defined (TE_PE) || defined (TE_PEP)
543 /* Use big object file format. */
544 static int use_big_obj = 0;
545 #endif
546
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 /* 1 if generating code for a shared library. */
549 static int shared = 0;
550 #endif
551
552 /* 1 for intel syntax,
553 0 if att syntax. */
554 static int intel_syntax = 0;
555
556 /* 1 for Intel64 ISA,
557 0 if AMD64 ISA. */
558 static int intel64;
559
560 /* 1 for intel mnemonic,
561 0 if att mnemonic. */
562 static int intel_mnemonic = !SYSV386_COMPAT;
563
564 /* 1 if pseudo registers are permitted. */
565 static int allow_pseudo_reg = 0;
566
567 /* 1 if register prefix % not required. */
568 static int allow_naked_reg = 0;
569
570 /* 1 if the assembler should add BND prefix for all control-transferring
571 instructions supporting it, even if this prefix wasn't specified
572 explicitly. */
573 static int add_bnd_prefix = 0;
574
575 /* 1 if pseudo index register, eiz/riz, is allowed . */
576 static int allow_index_reg = 0;
577
578 /* 1 if the assembler should ignore LOCK prefix, even if it was
579 specified explicitly. */
580 static int omit_lock_prefix = 0;
581
582 /* 1 if the assembler should encode lfence, mfence, and sfence as
583 "lock addl $0, (%{re}sp)". */
584 static int avoid_fence = 0;
585
586 /* 1 if the assembler should generate relax relocations. */
587
588 static int generate_relax_relocations
589 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
590
591 static enum check_kind
592 {
593 check_none = 0,
594 check_warning,
595 check_error
596 }
597 sse_check, operand_check = check_warning;
598
599 /* Optimization:
600 1. Clear the REX_W bit with register operand if possible.
601 2. Above plus use 128bit vector instruction to clear the full vector
602 register.
603 */
604 static int optimize = 0;
605
606 /* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
611 "testb $imm7,%r8".
612 */
613 static int optimize_for_space = 0;
614
615 /* Register prefix used for error message. */
616 static const char *register_prefix = "%";
617
618 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
619 leave, push, and pop instructions so that gcc has the same stack
620 frame as in 32 bit mode. */
621 static char stackop_size = '\0';
622
623 /* Non-zero to optimize code alignment. */
624 int optimize_align_code = 1;
625
626 /* Non-zero to quieten some warnings. */
627 static int quiet_warnings = 0;
628
629 /* CPU name. */
630 static const char *cpu_arch_name = NULL;
631 static char *cpu_sub_arch_name = NULL;
632
633 /* CPU feature flags. */
634 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
635
636 /* If we have selected a cpu we are generating instructions for. */
637 static int cpu_arch_tune_set = 0;
638
639 /* Cpu we are generating instructions for. */
640 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
641
642 /* CPU feature flags of cpu we are generating instructions for. */
643 static i386_cpu_flags cpu_arch_tune_flags;
644
645 /* CPU instruction set architecture used. */
646 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
647
648 /* CPU feature flags of instruction set architecture used. */
649 i386_cpu_flags cpu_arch_isa_flags;
650
651 /* If set, conditional jumps are not automatically promoted to handle
652 larger than a byte offset. */
653 static unsigned int no_cond_jump_promotion = 0;
654
655 /* Encode SSE instructions with VEX prefix. */
656 static unsigned int sse2avx;
657
658 /* Encode scalar AVX instructions with specific vector length. */
659 static enum
660 {
661 vex128 = 0,
662 vex256
663 } avxscalar;
664
665 /* Encode scalar EVEX LIG instructions with specific vector length. */
666 static enum
667 {
668 evexl128 = 0,
669 evexl256,
670 evexl512
671 } evexlig;
672
673 /* Encode EVEX WIG instructions with specific evex.w. */
674 static enum
675 {
676 evexw0 = 0,
677 evexw1
678 } evexwig;
679
680 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
681 static enum rc_type evexrcig = rne;
682
683 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
684 static symbolS *GOT_symbol;
685
686 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
687 unsigned int x86_dwarf2_return_column;
688
689 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
690 int x86_cie_data_alignment;
691
692 /* Interface to relax_segment.
693 There are 3 major relax states for 386 jump insns because the
694 different types of jumps add different sizes to frags when we're
695 figuring out what sort of jump to choose to reach a given label. */
696
697 /* Types. */
698 #define UNCOND_JUMP 0
699 #define COND_JUMP 1
700 #define COND_JUMP86 2
701
702 /* Sizes. */
703 #define CODE16 1
704 #define SMALL 0
705 #define SMALL16 (SMALL | CODE16)
706 #define BIG 2
707 #define BIG16 (BIG | CODE16)
708
709 #ifndef INLINE
710 #ifdef __GNUC__
711 #define INLINE __inline__
712 #else
713 #define INLINE
714 #endif
715 #endif
716
717 #define ENCODE_RELAX_STATE(type, size) \
718 ((relax_substateT) (((type) << 2) | (size)))
719 #define TYPE_FROM_RELAX_STATE(s) \
720 ((s) >> 2)
721 #define DISP_SIZE_FROM_RELAX_STATE(s) \
722 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723
724 /* This table is used by relax_frag to promote short jumps to long
725 ones where necessary. SMALL (short) jumps may be promoted to BIG
726 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
727 don't allow a short jump in a 32 bit code segment to be promoted to
728 a 16 bit offset jump because it's slower (requires data size
729 prefix), and doesn't work, unless the destination is in the bottom
730 64k of the code segment (The top 16 bits of eip are zeroed). */
731
732 const relax_typeS md_relax_table[] =
733 {
734 /* The fields are:
735 1) most positive reach of this state,
736 2) most negative reach of this state,
737 3) how many bytes this mode will have in the variable part of the frag
738 4) which index into the table to try if we can't fit into this one. */
739
740 /* UNCOND_JUMP states. */
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
742 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
743 /* dword jmp adds 4 bytes to frag:
744 0 extra opcode bytes, 4 displacement bytes. */
745 {0, 0, 4, 0},
746 /* word jmp adds 2 byte2 to frag:
747 0 extra opcode bytes, 2 displacement bytes. */
748 {0, 0, 2, 0},
749
750 /* COND_JUMP states. */
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
752 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
753 /* dword conditionals adds 5 bytes to frag:
754 1 extra opcode byte, 4 displacement bytes. */
755 {0, 0, 5, 0},
756 /* word conditionals add 3 bytes to frag:
757 1 extra opcode byte, 2 displacement bytes. */
758 {0, 0, 3, 0},
759
760 /* COND_JUMP86 states. */
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
763 /* dword conditionals adds 5 bytes to frag:
764 1 extra opcode byte, 4 displacement bytes. */
765 {0, 0, 5, 0},
766 /* word conditionals add 4 bytes to frag:
767 1 displacement byte and a 3 byte long branch insn. */
768 {0, 0, 4, 0}
769 };
770
771 static const arch_entry cpu_arch[] =
772 {
773 /* Do not replace the first two entries - i386_target_format()
774 relies on them being there in this order. */
775 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
776 CPU_GENERIC32_FLAGS, 0 },
777 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
778 CPU_GENERIC64_FLAGS, 0 },
779 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
780 CPU_NONE_FLAGS, 0 },
781 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
782 CPU_I186_FLAGS, 0 },
783 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
784 CPU_I286_FLAGS, 0 },
785 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
786 CPU_I386_FLAGS, 0 },
787 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
788 CPU_I486_FLAGS, 0 },
789 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
790 CPU_I586_FLAGS, 0 },
791 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
792 CPU_I686_FLAGS, 0 },
793 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
794 CPU_I586_FLAGS, 0 },
795 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
796 CPU_PENTIUMPRO_FLAGS, 0 },
797 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
798 CPU_P2_FLAGS, 0 },
799 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
800 CPU_P3_FLAGS, 0 },
801 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
802 CPU_P4_FLAGS, 0 },
803 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
804 CPU_CORE_FLAGS, 0 },
805 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
806 CPU_NOCONA_FLAGS, 0 },
807 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
808 CPU_CORE_FLAGS, 1 },
809 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
810 CPU_CORE_FLAGS, 0 },
811 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
812 CPU_CORE2_FLAGS, 1 },
813 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
814 CPU_CORE2_FLAGS, 0 },
815 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
816 CPU_COREI7_FLAGS, 0 },
817 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
818 CPU_L1OM_FLAGS, 0 },
819 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
820 CPU_K1OM_FLAGS, 0 },
821 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
822 CPU_IAMCU_FLAGS, 0 },
823 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
824 CPU_K6_FLAGS, 0 },
825 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
826 CPU_K6_2_FLAGS, 0 },
827 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
828 CPU_ATHLON_FLAGS, 0 },
829 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
830 CPU_K8_FLAGS, 1 },
831 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
832 CPU_K8_FLAGS, 0 },
833 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
834 CPU_K8_FLAGS, 0 },
835 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
836 CPU_AMDFAM10_FLAGS, 0 },
837 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
838 CPU_BDVER1_FLAGS, 0 },
839 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
840 CPU_BDVER2_FLAGS, 0 },
841 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
842 CPU_BDVER3_FLAGS, 0 },
843 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
844 CPU_BDVER4_FLAGS, 0 },
845 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
846 CPU_ZNVER1_FLAGS, 0 },
847 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
848 CPU_BTVER1_FLAGS, 0 },
849 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
850 CPU_BTVER2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
852 CPU_8087_FLAGS, 0 },
853 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
854 CPU_287_FLAGS, 0 },
855 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
856 CPU_387_FLAGS, 0 },
857 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
858 CPU_687_FLAGS, 0 },
859 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
860 CPU_MMX_FLAGS, 0 },
861 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
862 CPU_SSE_FLAGS, 0 },
863 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
864 CPU_SSE2_FLAGS, 0 },
865 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
866 CPU_SSE3_FLAGS, 0 },
867 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
868 CPU_SSSE3_FLAGS, 0 },
869 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
870 CPU_SSE4_1_FLAGS, 0 },
871 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
872 CPU_SSE4_2_FLAGS, 0 },
873 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
874 CPU_SSE4_2_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
876 CPU_AVX_FLAGS, 0 },
877 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
878 CPU_AVX2_FLAGS, 0 },
879 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
880 CPU_AVX512F_FLAGS, 0 },
881 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
882 CPU_AVX512CD_FLAGS, 0 },
883 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
884 CPU_AVX512ER_FLAGS, 0 },
885 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
886 CPU_AVX512PF_FLAGS, 0 },
887 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
888 CPU_AVX512DQ_FLAGS, 0 },
889 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
890 CPU_AVX512BW_FLAGS, 0 },
891 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
892 CPU_AVX512VL_FLAGS, 0 },
893 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
894 CPU_VMX_FLAGS, 0 },
895 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
896 CPU_VMFUNC_FLAGS, 0 },
897 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
898 CPU_SMX_FLAGS, 0 },
899 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
900 CPU_XSAVE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
902 CPU_XSAVEOPT_FLAGS, 0 },
903 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
904 CPU_XSAVEC_FLAGS, 0 },
905 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
906 CPU_XSAVES_FLAGS, 0 },
907 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
908 CPU_AES_FLAGS, 0 },
909 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
910 CPU_PCLMUL_FLAGS, 0 },
911 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
912 CPU_PCLMUL_FLAGS, 1 },
913 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
914 CPU_FSGSBASE_FLAGS, 0 },
915 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
916 CPU_RDRND_FLAGS, 0 },
917 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
918 CPU_F16C_FLAGS, 0 },
919 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
920 CPU_BMI2_FLAGS, 0 },
921 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
922 CPU_FMA_FLAGS, 0 },
923 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
924 CPU_FMA4_FLAGS, 0 },
925 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
926 CPU_XOP_FLAGS, 0 },
927 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
928 CPU_LWP_FLAGS, 0 },
929 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
930 CPU_MOVBE_FLAGS, 0 },
931 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
932 CPU_CX16_FLAGS, 0 },
933 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
934 CPU_EPT_FLAGS, 0 },
935 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
936 CPU_LZCNT_FLAGS, 0 },
937 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
938 CPU_HLE_FLAGS, 0 },
939 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
940 CPU_RTM_FLAGS, 0 },
941 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
942 CPU_INVPCID_FLAGS, 0 },
943 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
944 CPU_CLFLUSH_FLAGS, 0 },
945 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
946 CPU_NOP_FLAGS, 0 },
947 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
948 CPU_SYSCALL_FLAGS, 0 },
949 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
950 CPU_RDTSCP_FLAGS, 0 },
951 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
952 CPU_3DNOW_FLAGS, 0 },
953 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
954 CPU_3DNOWA_FLAGS, 0 },
955 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
956 CPU_PADLOCK_FLAGS, 0 },
957 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
958 CPU_SVME_FLAGS, 1 },
959 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
960 CPU_SVME_FLAGS, 0 },
961 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
962 CPU_SSE4A_FLAGS, 0 },
963 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
964 CPU_ABM_FLAGS, 0 },
965 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
966 CPU_BMI_FLAGS, 0 },
967 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
968 CPU_TBM_FLAGS, 0 },
969 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
970 CPU_ADX_FLAGS, 0 },
971 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
972 CPU_RDSEED_FLAGS, 0 },
973 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
974 CPU_PRFCHW_FLAGS, 0 },
975 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
976 CPU_SMAP_FLAGS, 0 },
977 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
978 CPU_MPX_FLAGS, 0 },
979 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
980 CPU_SHA_FLAGS, 0 },
981 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
982 CPU_CLFLUSHOPT_FLAGS, 0 },
983 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
984 CPU_PREFETCHWT1_FLAGS, 0 },
985 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
986 CPU_SE1_FLAGS, 0 },
987 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
988 CPU_CLWB_FLAGS, 0 },
989 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
990 CPU_AVX512IFMA_FLAGS, 0 },
991 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
992 CPU_AVX512VBMI_FLAGS, 0 },
993 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
994 CPU_AVX512_4FMAPS_FLAGS, 0 },
995 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
996 CPU_AVX512_4VNNIW_FLAGS, 0 },
997 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
998 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
999 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1000 CPU_AVX512_VBMI2_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1002 CPU_AVX512_VNNI_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1004 CPU_AVX512_BITALG_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1006 CPU_CLZERO_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1008 CPU_MWAITX_FLAGS, 0 },
1009 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1010 CPU_OSPKE_FLAGS, 0 },
1011 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1012 CPU_RDPID_FLAGS, 0 },
1013 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1014 CPU_PTWRITE_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1016 CPU_IBT_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1018 CPU_SHSTK_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1020 CPU_GFNI_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1022 CPU_VAES_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1024 CPU_VPCLMULQDQ_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1026 CPU_WBNOINVD_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1028 CPU_PCONFIG_FLAGS, 0 },
1029 };
1030
1031 static const noarch_entry cpu_noarch[] =
1032 {
1033 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1034 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1035 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1036 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1037 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1038 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1039 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1040 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1041 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1042 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1043 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1044 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1045 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1046 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1047 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1048 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1049 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1050 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1062 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1063 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1064 };
1065
1066 #ifdef I386COFF
1067 /* Like s_lcomm_internal in gas/read.c but the alignment string
1068 is allowed to be optional. */
1069
1070 static symbolS *
1071 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1072 {
1073 addressT align = 0;
1074
1075 SKIP_WHITESPACE ();
1076
1077 if (needs_align
1078 && *input_line_pointer == ',')
1079 {
1080 align = parse_align (needs_align - 1);
1081
1082 if (align == (addressT) -1)
1083 return NULL;
1084 }
1085 else
1086 {
1087 if (size >= 8)
1088 align = 3;
1089 else if (size >= 4)
1090 align = 2;
1091 else if (size >= 2)
1092 align = 1;
1093 else
1094 align = 0;
1095 }
1096
1097 bss_alloc (symbolP, size, align);
1098 return symbolP;
1099 }
1100
1101 static void
1102 pe_lcomm (int needs_align)
1103 {
1104 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1105 }
1106 #endif
1107
1108 const pseudo_typeS md_pseudo_table[] =
1109 {
1110 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1111 {"align", s_align_bytes, 0},
1112 #else
1113 {"align", s_align_ptwo, 0},
1114 #endif
1115 {"arch", set_cpu_arch, 0},
1116 #ifndef I386COFF
1117 {"bss", s_bss, 0},
1118 #else
1119 {"lcomm", pe_lcomm, 1},
1120 #endif
1121 {"ffloat", float_cons, 'f'},
1122 {"dfloat", float_cons, 'd'},
1123 {"tfloat", float_cons, 'x'},
1124 {"value", cons, 2},
1125 {"slong", signed_cons, 4},
1126 {"noopt", s_ignore, 0},
1127 {"optim", s_ignore, 0},
1128 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1129 {"code16", set_code_flag, CODE_16BIT},
1130 {"code32", set_code_flag, CODE_32BIT},
1131 #ifdef BFD64
1132 {"code64", set_code_flag, CODE_64BIT},
1133 #endif
1134 {"intel_syntax", set_intel_syntax, 1},
1135 {"att_syntax", set_intel_syntax, 0},
1136 {"intel_mnemonic", set_intel_mnemonic, 1},
1137 {"att_mnemonic", set_intel_mnemonic, 0},
1138 {"allow_index_reg", set_allow_index_reg, 1},
1139 {"disallow_index_reg", set_allow_index_reg, 0},
1140 {"sse_check", set_check, 0},
1141 {"operand_check", set_check, 1},
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 {"largecomm", handle_large_common, 0},
1144 #else
1145 {"file", dwarf2_directive_file, 0},
1146 {"loc", dwarf2_directive_loc, 0},
1147 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1148 #endif
1149 #ifdef TE_PE
1150 {"secrel32", pe_directive_secrel, 0},
1151 #endif
1152 {0, 0, 0}
1153 };
1154
1155 /* For interface with expression (). */
1156 extern char *input_line_pointer;
1157
1158 /* Hash table for instruction mnemonic lookup. */
1159 static struct hash_control *op_hash;
1160
1161 /* Hash table for register lookup. */
1162 static struct hash_control *reg_hash;
1163 \f
1164 /* Various efficient no-op patterns for aligning code labels.
1165 Note: Don't try to assemble the instructions in the comments.
1166 0L and 0w are not legal. */
1167 static const unsigned char f32_1[] =
1168 {0x90}; /* nop */
1169 static const unsigned char f32_2[] =
1170 {0x66,0x90}; /* xchg %ax,%ax */
1171 static const unsigned char f32_3[] =
1172 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1173 static const unsigned char f32_4[] =
1174 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1175 static const unsigned char f32_6[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1177 static const unsigned char f32_7[] =
1178 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1179 static const unsigned char f16_3[] =
1180 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1181 static const unsigned char f16_4[] =
1182 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1183 static const unsigned char jump_disp8[] =
1184 {0xeb}; /* jmp disp8 */
1185 static const unsigned char jump32_disp32[] =
1186 {0xe9}; /* jmp disp32 */
1187 static const unsigned char jump16_disp32[] =
1188 {0x66,0xe9}; /* jmp disp32 */
1189 /* 32-bit NOPs patterns. */
1190 static const unsigned char *const f32_patt[] = {
1191 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1192 };
1193 /* 16-bit NOPs patterns. */
1194 static const unsigned char *const f16_patt[] = {
1195 f32_1, f32_2, f16_3, f16_4
1196 };
1197 /* nopl (%[re]ax) */
1198 static const unsigned char alt_3[] =
1199 {0x0f,0x1f,0x00};
1200 /* nopl 0(%[re]ax) */
1201 static const unsigned char alt_4[] =
1202 {0x0f,0x1f,0x40,0x00};
1203 /* nopl 0(%[re]ax,%[re]ax,1) */
1204 static const unsigned char alt_5[] =
1205 {0x0f,0x1f,0x44,0x00,0x00};
1206 /* nopw 0(%[re]ax,%[re]ax,1) */
1207 static const unsigned char alt_6[] =
1208 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1209 /* nopl 0L(%[re]ax) */
1210 static const unsigned char alt_7[] =
1211 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1212 /* nopl 0L(%[re]ax,%[re]ax,1) */
1213 static const unsigned char alt_8[] =
1214 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1215 /* nopw 0L(%[re]ax,%[re]ax,1) */
1216 static const unsigned char alt_9[] =
1217 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_10[] =
1220 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221 /* data16 nopw %cs:0L(%eax,%eax,1) */
1222 static const unsigned char alt_11[] =
1223 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1224 /* 32-bit and 64-bit NOPs patterns. */
1225 static const unsigned char *const alt_patt[] = {
1226 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1227 alt_9, alt_10, alt_11
1228 };
1229
1230 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1231 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1232
1233 static void
1234 i386_output_nops (char *where, const unsigned char *const *patt,
1235 int count, int max_single_nop_size)
1236
1237 {
1238 /* Place the longer NOP first. */
1239 int last;
1240 int offset;
1241 const unsigned char *nops = patt[max_single_nop_size - 1];
1242
1243 /* Use the smaller one if the requsted one isn't available. */
1244 if (nops == NULL)
1245 {
1246 max_single_nop_size--;
1247 nops = patt[max_single_nop_size - 1];
1248 }
1249
1250 last = count % max_single_nop_size;
1251
1252 count -= last;
1253 for (offset = 0; offset < count; offset += max_single_nop_size)
1254 memcpy (where + offset, nops, max_single_nop_size);
1255
1256 if (last)
1257 {
1258 nops = patt[last - 1];
1259 if (nops == NULL)
1260 {
1261 /* Use the smaller one plus one-byte NOP if the needed one
1262 isn't available. */
1263 last--;
1264 nops = patt[last - 1];
1265 memcpy (where + offset, nops, last);
1266 where[offset + last] = *patt[0];
1267 }
1268 else
1269 memcpy (where + offset, nops, last);
1270 }
1271 }
1272
1273 static INLINE int
1274 fits_in_imm7 (offsetT num)
1275 {
1276 return (num & 0x7f) == num;
1277 }
1278
1279 static INLINE int
1280 fits_in_imm31 (offsetT num)
1281 {
1282 return (num & 0x7fffffff) == num;
1283 }
1284
1285 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1286 single NOP instruction LIMIT. */
1287
1288 void
1289 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1290 {
1291 const unsigned char *const *patt = NULL;
1292 int max_single_nop_size;
1293 /* Maximum number of NOPs before switching to jump over NOPs. */
1294 int max_number_of_nops;
1295
1296 switch (fragP->fr_type)
1297 {
1298 case rs_fill_nop:
1299 case rs_align_code:
1300 break;
1301 default:
1302 return;
1303 }
1304
1305 /* We need to decide which NOP sequence to use for 32bit and
1306 64bit. When -mtune= is used:
1307
1308 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1309 PROCESSOR_GENERIC32, f32_patt will be used.
1310 2. For the rest, alt_patt will be used.
1311
1312 When -mtune= isn't used, alt_patt will be used if
1313 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1314 be used.
1315
1316 When -march= or .arch is used, we can't use anything beyond
1317 cpu_arch_isa_flags. */
1318
1319 if (flag_code == CODE_16BIT)
1320 {
1321 patt = f16_patt;
1322 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1323 /* Limit number of NOPs to 2 in 16-bit mode. */
1324 max_number_of_nops = 2;
1325 }
1326 else
1327 {
1328 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1329 {
1330 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1331 switch (cpu_arch_tune)
1332 {
1333 case PROCESSOR_UNKNOWN:
1334 /* We use cpu_arch_isa_flags to check if we SHOULD
1335 optimize with nops. */
1336 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1337 patt = alt_patt;
1338 else
1339 patt = f32_patt;
1340 break;
1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
1343 case PROCESSOR_CORE:
1344 case PROCESSOR_CORE2:
1345 case PROCESSOR_COREI7:
1346 case PROCESSOR_L1OM:
1347 case PROCESSOR_K1OM:
1348 case PROCESSOR_GENERIC64:
1349 case PROCESSOR_K6:
1350 case PROCESSOR_ATHLON:
1351 case PROCESSOR_K8:
1352 case PROCESSOR_AMDFAM10:
1353 case PROCESSOR_BD:
1354 case PROCESSOR_ZNVER:
1355 case PROCESSOR_BT:
1356 patt = alt_patt;
1357 break;
1358 case PROCESSOR_I386:
1359 case PROCESSOR_I486:
1360 case PROCESSOR_PENTIUM:
1361 case PROCESSOR_PENTIUMPRO:
1362 case PROCESSOR_IAMCU:
1363 case PROCESSOR_GENERIC32:
1364 patt = f32_patt;
1365 break;
1366 }
1367 }
1368 else
1369 {
1370 switch (fragP->tc_frag_data.tune)
1371 {
1372 case PROCESSOR_UNKNOWN:
1373 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1374 PROCESSOR_UNKNOWN. */
1375 abort ();
1376 break;
1377
1378 case PROCESSOR_I386:
1379 case PROCESSOR_I486:
1380 case PROCESSOR_PENTIUM:
1381 case PROCESSOR_IAMCU:
1382 case PROCESSOR_K6:
1383 case PROCESSOR_ATHLON:
1384 case PROCESSOR_K8:
1385 case PROCESSOR_AMDFAM10:
1386 case PROCESSOR_BD:
1387 case PROCESSOR_ZNVER:
1388 case PROCESSOR_BT:
1389 case PROCESSOR_GENERIC32:
1390 /* We use cpu_arch_isa_flags to check if we CAN optimize
1391 with nops. */
1392 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1393 patt = alt_patt;
1394 else
1395 patt = f32_patt;
1396 break;
1397 case PROCESSOR_PENTIUMPRO:
1398 case PROCESSOR_PENTIUM4:
1399 case PROCESSOR_NOCONA:
1400 case PROCESSOR_CORE:
1401 case PROCESSOR_CORE2:
1402 case PROCESSOR_COREI7:
1403 case PROCESSOR_L1OM:
1404 case PROCESSOR_K1OM:
1405 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1406 patt = alt_patt;
1407 else
1408 patt = f32_patt;
1409 break;
1410 case PROCESSOR_GENERIC64:
1411 patt = alt_patt;
1412 break;
1413 }
1414 }
1415
1416 if (patt == f32_patt)
1417 {
1418 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1419 /* Limit number of NOPs to 2 for older processors. */
1420 max_number_of_nops = 2;
1421 }
1422 else
1423 {
1424 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1425 /* Limit number of NOPs to 7 for newer processors. */
1426 max_number_of_nops = 7;
1427 }
1428 }
1429
1430 if (limit == 0)
1431 limit = max_single_nop_size;
1432
1433 if (fragP->fr_type == rs_fill_nop)
1434 {
1435 /* Output NOPs for .nop directive. */
1436 if (limit > max_single_nop_size)
1437 {
1438 as_bad_where (fragP->fr_file, fragP->fr_line,
1439 _("invalid single nop size: %d "
1440 "(expect within [0, %d])"),
1441 limit, max_single_nop_size);
1442 return;
1443 }
1444 }
1445 else
1446 fragP->fr_var = count;
1447
1448 if ((count / max_single_nop_size) > max_number_of_nops)
1449 {
1450 /* Generate jump over NOPs. */
1451 offsetT disp = count - 2;
1452 if (fits_in_imm7 (disp))
1453 {
1454 /* Use "jmp disp8" if possible. */
1455 count = disp;
1456 where[0] = jump_disp8[0];
1457 where[1] = count;
1458 where += 2;
1459 }
1460 else
1461 {
1462 unsigned int size_of_jump;
1463
1464 if (flag_code == CODE_16BIT)
1465 {
1466 where[0] = jump16_disp32[0];
1467 where[1] = jump16_disp32[1];
1468 size_of_jump = 2;
1469 }
1470 else
1471 {
1472 where[0] = jump32_disp32[0];
1473 size_of_jump = 1;
1474 }
1475
1476 count -= size_of_jump + 4;
1477 if (!fits_in_imm31 (count))
1478 {
1479 as_bad_where (fragP->fr_file, fragP->fr_line,
1480 _("jump over nop padding out of range"));
1481 return;
1482 }
1483
1484 md_number_to_chars (where + size_of_jump, count, 4);
1485 where += size_of_jump + 4;
1486 }
1487 }
1488
1489 /* Generate multiple NOPs. */
1490 i386_output_nops (where, patt, count, limit);
1491 }
1492
1493 static INLINE int
1494 operand_type_all_zero (const union i386_operand_type *x)
1495 {
1496 switch (ARRAY_SIZE(x->array))
1497 {
1498 case 3:
1499 if (x->array[2])
1500 return 0;
1501 /* Fall through. */
1502 case 2:
1503 if (x->array[1])
1504 return 0;
1505 /* Fall through. */
1506 case 1:
1507 return !x->array[0];
1508 default:
1509 abort ();
1510 }
1511 }
1512
1513 static INLINE void
1514 operand_type_set (union i386_operand_type *x, unsigned int v)
1515 {
1516 switch (ARRAY_SIZE(x->array))
1517 {
1518 case 3:
1519 x->array[2] = v;
1520 /* Fall through. */
1521 case 2:
1522 x->array[1] = v;
1523 /* Fall through. */
1524 case 1:
1525 x->array[0] = v;
1526 /* Fall through. */
1527 break;
1528 default:
1529 abort ();
1530 }
1531 }
1532
1533 static INLINE int
1534 operand_type_equal (const union i386_operand_type *x,
1535 const union i386_operand_type *y)
1536 {
1537 switch (ARRAY_SIZE(x->array))
1538 {
1539 case 3:
1540 if (x->array[2] != y->array[2])
1541 return 0;
1542 /* Fall through. */
1543 case 2:
1544 if (x->array[1] != y->array[1])
1545 return 0;
1546 /* Fall through. */
1547 case 1:
1548 return x->array[0] == y->array[0];
1549 break;
1550 default:
1551 abort ();
1552 }
1553 }
1554
1555 static INLINE int
1556 cpu_flags_all_zero (const union i386_cpu_flags *x)
1557 {
1558 switch (ARRAY_SIZE(x->array))
1559 {
1560 case 4:
1561 if (x->array[3])
1562 return 0;
1563 /* Fall through. */
1564 case 3:
1565 if (x->array[2])
1566 return 0;
1567 /* Fall through. */
1568 case 2:
1569 if (x->array[1])
1570 return 0;
1571 /* Fall through. */
1572 case 1:
1573 return !x->array[0];
1574 default:
1575 abort ();
1576 }
1577 }
1578
1579 static INLINE int
1580 cpu_flags_equal (const union i386_cpu_flags *x,
1581 const union i386_cpu_flags *y)
1582 {
1583 switch (ARRAY_SIZE(x->array))
1584 {
1585 case 4:
1586 if (x->array[3] != y->array[3])
1587 return 0;
1588 /* Fall through. */
1589 case 3:
1590 if (x->array[2] != y->array[2])
1591 return 0;
1592 /* Fall through. */
1593 case 2:
1594 if (x->array[1] != y->array[1])
1595 return 0;
1596 /* Fall through. */
1597 case 1:
1598 return x->array[0] == y->array[0];
1599 break;
1600 default:
1601 abort ();
1602 }
1603 }
1604
1605 static INLINE int
1606 cpu_flags_check_cpu64 (i386_cpu_flags f)
1607 {
1608 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1609 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1610 }
1611
1612 static INLINE i386_cpu_flags
1613 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1614 {
1615 switch (ARRAY_SIZE (x.array))
1616 {
1617 case 4:
1618 x.array [3] &= y.array [3];
1619 /* Fall through. */
1620 case 3:
1621 x.array [2] &= y.array [2];
1622 /* Fall through. */
1623 case 2:
1624 x.array [1] &= y.array [1];
1625 /* Fall through. */
1626 case 1:
1627 x.array [0] &= y.array [0];
1628 break;
1629 default:
1630 abort ();
1631 }
1632 return x;
1633 }
1634
1635 static INLINE i386_cpu_flags
1636 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1637 {
1638 switch (ARRAY_SIZE (x.array))
1639 {
1640 case 4:
1641 x.array [3] |= y.array [3];
1642 /* Fall through. */
1643 case 3:
1644 x.array [2] |= y.array [2];
1645 /* Fall through. */
1646 case 2:
1647 x.array [1] |= y.array [1];
1648 /* Fall through. */
1649 case 1:
1650 x.array [0] |= y.array [0];
1651 break;
1652 default:
1653 abort ();
1654 }
1655 return x;
1656 }
1657
1658 static INLINE i386_cpu_flags
1659 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1660 {
1661 switch (ARRAY_SIZE (x.array))
1662 {
1663 case 4:
1664 x.array [3] &= ~y.array [3];
1665 /* Fall through. */
1666 case 3:
1667 x.array [2] &= ~y.array [2];
1668 /* Fall through. */
1669 case 2:
1670 x.array [1] &= ~y.array [1];
1671 /* Fall through. */
1672 case 1:
1673 x.array [0] &= ~y.array [0];
1674 break;
1675 default:
1676 abort ();
1677 }
1678 return x;
1679 }
1680
1681 #define CPU_FLAGS_ARCH_MATCH 0x1
1682 #define CPU_FLAGS_64BIT_MATCH 0x2
1683
1684 #define CPU_FLAGS_PERFECT_MATCH \
1685 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1686
1687 /* Return CPU flags match bits. */
1688
1689 static int
1690 cpu_flags_match (const insn_template *t)
1691 {
1692 i386_cpu_flags x = t->cpu_flags;
1693 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1694
1695 x.bitfield.cpu64 = 0;
1696 x.bitfield.cpuno64 = 0;
1697
1698 if (cpu_flags_all_zero (&x))
1699 {
1700 /* This instruction is available on all archs. */
1701 match |= CPU_FLAGS_ARCH_MATCH;
1702 }
1703 else
1704 {
1705 /* This instruction is available only on some archs. */
1706 i386_cpu_flags cpu = cpu_arch_flags;
1707
1708 /* AVX512VL is no standalone feature - match it and then strip it. */
1709 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1710 return match;
1711 x.bitfield.cpuavx512vl = 0;
1712
1713 cpu = cpu_flags_and (x, cpu);
1714 if (!cpu_flags_all_zero (&cpu))
1715 {
1716 if (x.bitfield.cpuavx)
1717 {
1718 /* We need to check a few extra flags with AVX. */
1719 if (cpu.bitfield.cpuavx
1720 && (!t->opcode_modifier.sse2avx || sse2avx)
1721 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1722 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1723 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1724 match |= CPU_FLAGS_ARCH_MATCH;
1725 }
1726 else if (x.bitfield.cpuavx512f)
1727 {
1728 /* We need to check a few extra flags with AVX512F. */
1729 if (cpu.bitfield.cpuavx512f
1730 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1731 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1732 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1733 match |= CPU_FLAGS_ARCH_MATCH;
1734 }
1735 else
1736 match |= CPU_FLAGS_ARCH_MATCH;
1737 }
1738 }
1739 return match;
1740 }
1741
1742 static INLINE i386_operand_type
1743 operand_type_and (i386_operand_type x, i386_operand_type y)
1744 {
1745 switch (ARRAY_SIZE (x.array))
1746 {
1747 case 3:
1748 x.array [2] &= y.array [2];
1749 /* Fall through. */
1750 case 2:
1751 x.array [1] &= y.array [1];
1752 /* Fall through. */
1753 case 1:
1754 x.array [0] &= y.array [0];
1755 break;
1756 default:
1757 abort ();
1758 }
1759 return x;
1760 }
1761
1762 static INLINE i386_operand_type
1763 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1764 {
1765 switch (ARRAY_SIZE (x.array))
1766 {
1767 case 3:
1768 x.array [2] &= ~y.array [2];
1769 /* Fall through. */
1770 case 2:
1771 x.array [1] &= ~y.array [1];
1772 /* Fall through. */
1773 case 1:
1774 x.array [0] &= ~y.array [0];
1775 break;
1776 default:
1777 abort ();
1778 }
1779 return x;
1780 }
1781
1782 static INLINE i386_operand_type
1783 operand_type_or (i386_operand_type x, i386_operand_type y)
1784 {
1785 switch (ARRAY_SIZE (x.array))
1786 {
1787 case 3:
1788 x.array [2] |= y.array [2];
1789 /* Fall through. */
1790 case 2:
1791 x.array [1] |= y.array [1];
1792 /* Fall through. */
1793 case 1:
1794 x.array [0] |= y.array [0];
1795 break;
1796 default:
1797 abort ();
1798 }
1799 return x;
1800 }
1801
1802 static INLINE i386_operand_type
1803 operand_type_xor (i386_operand_type x, i386_operand_type y)
1804 {
1805 switch (ARRAY_SIZE (x.array))
1806 {
1807 case 3:
1808 x.array [2] ^= y.array [2];
1809 /* Fall through. */
1810 case 2:
1811 x.array [1] ^= y.array [1];
1812 /* Fall through. */
1813 case 1:
1814 x.array [0] ^= y.array [0];
1815 break;
1816 default:
1817 abort ();
1818 }
1819 return x;
1820 }
1821
1822 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1823 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1824 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1825 static const i386_operand_type inoutportreg
1826 = OPERAND_TYPE_INOUTPORTREG;
1827 static const i386_operand_type reg16_inoutportreg
1828 = OPERAND_TYPE_REG16_INOUTPORTREG;
1829 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1830 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1831 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1832 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1833 static const i386_operand_type anydisp
1834 = OPERAND_TYPE_ANYDISP;
1835 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1836 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1837 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1838 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1839 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1840 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1841 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1842 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1843 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1844 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1845 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1846 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1847
1848 enum operand_type
1849 {
1850 reg,
1851 imm,
1852 disp,
1853 anymem
1854 };
1855
1856 static INLINE int
1857 operand_type_check (i386_operand_type t, enum operand_type c)
1858 {
1859 switch (c)
1860 {
1861 case reg:
1862 return t.bitfield.reg;
1863
1864 case imm:
1865 return (t.bitfield.imm8
1866 || t.bitfield.imm8s
1867 || t.bitfield.imm16
1868 || t.bitfield.imm32
1869 || t.bitfield.imm32s
1870 || t.bitfield.imm64);
1871
1872 case disp:
1873 return (t.bitfield.disp8
1874 || t.bitfield.disp16
1875 || t.bitfield.disp32
1876 || t.bitfield.disp32s
1877 || t.bitfield.disp64);
1878
1879 case anymem:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64
1885 || t.bitfield.baseindex);
1886
1887 default:
1888 abort ();
1889 }
1890
1891 return 0;
1892 }
1893
1894 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1895 operand J for instruction template T. */
1896
1897 static INLINE int
1898 match_reg_size (const insn_template *t, unsigned int j)
1899 {
1900 return !((i.types[j].bitfield.byte
1901 && !t->operand_types[j].bitfield.byte)
1902 || (i.types[j].bitfield.word
1903 && !t->operand_types[j].bitfield.word)
1904 || (i.types[j].bitfield.dword
1905 && !t->operand_types[j].bitfield.dword)
1906 || (i.types[j].bitfield.qword
1907 && !t->operand_types[j].bitfield.qword)
1908 || (i.types[j].bitfield.tbyte
1909 && !t->operand_types[j].bitfield.tbyte));
1910 }
1911
1912 /* Return 1 if there is no conflict in SIMD register on
1913 operand J for instruction template T. */
1914
1915 static INLINE int
1916 match_simd_size (const insn_template *t, unsigned int j)
1917 {
1918 return !((i.types[j].bitfield.xmmword
1919 && !t->operand_types[j].bitfield.xmmword)
1920 || (i.types[j].bitfield.ymmword
1921 && !t->operand_types[j].bitfield.ymmword)
1922 || (i.types[j].bitfield.zmmword
1923 && !t->operand_types[j].bitfield.zmmword));
1924 }
1925
1926 /* Return 1 if there is no conflict in any size on operand J for
1927 instruction template T. */
1928
1929 static INLINE int
1930 match_mem_size (const insn_template *t, unsigned int j)
1931 {
1932 return (match_reg_size (t, j)
1933 && !((i.types[j].bitfield.unspecified
1934 && !i.broadcast
1935 && !t->operand_types[j].bitfield.unspecified)
1936 || (i.types[j].bitfield.fword
1937 && !t->operand_types[j].bitfield.fword)
1938 /* For scalar opcode templates to allow register and memory
1939 operands at the same time, some special casing is needed
1940 here. */
1941 || ((t->operand_types[j].bitfield.regsimd
1942 && !t->opcode_modifier.broadcast
1943 && (t->operand_types[j].bitfield.dword
1944 || t->operand_types[j].bitfield.qword))
1945 ? (i.types[j].bitfield.xmmword
1946 || i.types[j].bitfield.ymmword
1947 || i.types[j].bitfield.zmmword)
1948 : !match_simd_size(t, j))));
1949 }
1950
1951 /* Return 1 if there is no size conflict on any operands for
1952 instruction template T. */
1953
1954 static INLINE int
1955 operand_size_match (const insn_template *t)
1956 {
1957 unsigned int j;
1958 int match = 1;
1959
1960 /* Don't check jump instructions. */
1961 if (t->opcode_modifier.jump
1962 || t->opcode_modifier.jumpbyte
1963 || t->opcode_modifier.jumpdword
1964 || t->opcode_modifier.jumpintersegment)
1965 return match;
1966
1967 /* Check memory and accumulator operand size. */
1968 for (j = 0; j < i.operands; j++)
1969 {
1970 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1971 && t->operand_types[j].bitfield.anysize)
1972 continue;
1973
1974 if (t->operand_types[j].bitfield.reg
1975 && !match_reg_size (t, j))
1976 {
1977 match = 0;
1978 break;
1979 }
1980
1981 if (t->operand_types[j].bitfield.regsimd
1982 && !match_simd_size (t, j))
1983 {
1984 match = 0;
1985 break;
1986 }
1987
1988 if (t->operand_types[j].bitfield.acc
1989 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1990 {
1991 match = 0;
1992 break;
1993 }
1994
1995 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1996 {
1997 match = 0;
1998 break;
1999 }
2000 }
2001
2002 if (match)
2003 return match;
2004 else if (!t->opcode_modifier.d)
2005 {
2006 mismatch:
2007 i.error = operand_size_mismatch;
2008 return 0;
2009 }
2010
2011 /* Check reverse. */
2012 gas_assert (i.operands == 2);
2013
2014 match = 1;
2015 for (j = 0; j < 2; j++)
2016 {
2017 if ((t->operand_types[j].bitfield.reg
2018 || t->operand_types[j].bitfield.acc)
2019 && !match_reg_size (t, j ? 0 : 1))
2020 goto mismatch;
2021
2022 if (i.types[j].bitfield.mem
2023 && !match_mem_size (t, j ? 0 : 1))
2024 goto mismatch;
2025 }
2026
2027 return match;
2028 }
2029
2030 static INLINE int
2031 operand_type_match (i386_operand_type overlap,
2032 i386_operand_type given)
2033 {
2034 i386_operand_type temp = overlap;
2035
2036 temp.bitfield.jumpabsolute = 0;
2037 temp.bitfield.unspecified = 0;
2038 temp.bitfield.byte = 0;
2039 temp.bitfield.word = 0;
2040 temp.bitfield.dword = 0;
2041 temp.bitfield.fword = 0;
2042 temp.bitfield.qword = 0;
2043 temp.bitfield.tbyte = 0;
2044 temp.bitfield.xmmword = 0;
2045 temp.bitfield.ymmword = 0;
2046 temp.bitfield.zmmword = 0;
2047 if (operand_type_all_zero (&temp))
2048 goto mismatch;
2049
2050 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2051 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2052 return 1;
2053
2054 mismatch:
2055 i.error = operand_type_mismatch;
2056 return 0;
2057 }
2058
2059 /* If given types g0 and g1 are registers they must be of the same type
2060 unless the expected operand type register overlap is null.
2061 Memory operand size of certain SIMD instructions is also being checked
2062 here. */
2063
2064 static INLINE int
2065 operand_type_register_match (i386_operand_type g0,
2066 i386_operand_type t0,
2067 i386_operand_type g1,
2068 i386_operand_type t1)
2069 {
2070 if (!g0.bitfield.reg
2071 && !g0.bitfield.regsimd
2072 && (!operand_type_check (g0, anymem)
2073 || g0.bitfield.unspecified
2074 || !t0.bitfield.regsimd))
2075 return 1;
2076
2077 if (!g1.bitfield.reg
2078 && !g1.bitfield.regsimd
2079 && (!operand_type_check (g1, anymem)
2080 || g1.bitfield.unspecified
2081 || !t1.bitfield.regsimd))
2082 return 1;
2083
2084 if (g0.bitfield.byte == g1.bitfield.byte
2085 && g0.bitfield.word == g1.bitfield.word
2086 && g0.bitfield.dword == g1.bitfield.dword
2087 && g0.bitfield.qword == g1.bitfield.qword
2088 && g0.bitfield.xmmword == g1.bitfield.xmmword
2089 && g0.bitfield.ymmword == g1.bitfield.ymmword
2090 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2091 return 1;
2092
2093 if (!(t0.bitfield.byte & t1.bitfield.byte)
2094 && !(t0.bitfield.word & t1.bitfield.word)
2095 && !(t0.bitfield.dword & t1.bitfield.dword)
2096 && !(t0.bitfield.qword & t1.bitfield.qword)
2097 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2098 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2099 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2100 return 1;
2101
2102 i.error = register_type_mismatch;
2103
2104 return 0;
2105 }
2106
2107 static INLINE unsigned int
2108 register_number (const reg_entry *r)
2109 {
2110 unsigned int nr = r->reg_num;
2111
2112 if (r->reg_flags & RegRex)
2113 nr += 8;
2114
2115 if (r->reg_flags & RegVRex)
2116 nr += 16;
2117
2118 return nr;
2119 }
2120
2121 static INLINE unsigned int
2122 mode_from_disp_size (i386_operand_type t)
2123 {
2124 if (t.bitfield.disp8)
2125 return 1;
2126 else if (t.bitfield.disp16
2127 || t.bitfield.disp32
2128 || t.bitfield.disp32s)
2129 return 2;
2130 else
2131 return 0;
2132 }
2133
2134 static INLINE int
2135 fits_in_signed_byte (addressT num)
2136 {
2137 return num + 0x80 <= 0xff;
2138 }
2139
2140 static INLINE int
2141 fits_in_unsigned_byte (addressT num)
2142 {
2143 return num <= 0xff;
2144 }
2145
2146 static INLINE int
2147 fits_in_unsigned_word (addressT num)
2148 {
2149 return num <= 0xffff;
2150 }
2151
2152 static INLINE int
2153 fits_in_signed_word (addressT num)
2154 {
2155 return num + 0x8000 <= 0xffff;
2156 }
2157
2158 static INLINE int
2159 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2160 {
2161 #ifndef BFD64
2162 return 1;
2163 #else
2164 return num + 0x80000000 <= 0xffffffff;
2165 #endif
2166 } /* fits_in_signed_long() */
2167
2168 static INLINE int
2169 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2170 {
2171 #ifndef BFD64
2172 return 1;
2173 #else
2174 return num <= 0xffffffff;
2175 #endif
2176 } /* fits_in_unsigned_long() */
2177
2178 static INLINE int
2179 fits_in_disp8 (offsetT num)
2180 {
2181 int shift = i.memshift;
2182 unsigned int mask;
2183
2184 if (shift == -1)
2185 abort ();
2186
2187 mask = (1 << shift) - 1;
2188
2189 /* Return 0 if NUM isn't properly aligned. */
2190 if ((num & mask))
2191 return 0;
2192
2193 /* Check if NUM will fit in 8bit after shift. */
2194 return fits_in_signed_byte (num >> shift);
2195 }
2196
2197 static INLINE int
2198 fits_in_imm4 (offsetT num)
2199 {
2200 return (num & 0xf) == num;
2201 }
2202
2203 static i386_operand_type
2204 smallest_imm_type (offsetT num)
2205 {
2206 i386_operand_type t;
2207
2208 operand_type_set (&t, 0);
2209 t.bitfield.imm64 = 1;
2210
2211 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2212 {
2213 /* This code is disabled on the 486 because all the Imm1 forms
2214 in the opcode table are slower on the i486. They're the
2215 versions with the implicitly specified single-position
2216 displacement, which has another syntax if you really want to
2217 use that form. */
2218 t.bitfield.imm1 = 1;
2219 t.bitfield.imm8 = 1;
2220 t.bitfield.imm8s = 1;
2221 t.bitfield.imm16 = 1;
2222 t.bitfield.imm32 = 1;
2223 t.bitfield.imm32s = 1;
2224 }
2225 else if (fits_in_signed_byte (num))
2226 {
2227 t.bitfield.imm8 = 1;
2228 t.bitfield.imm8s = 1;
2229 t.bitfield.imm16 = 1;
2230 t.bitfield.imm32 = 1;
2231 t.bitfield.imm32s = 1;
2232 }
2233 else if (fits_in_unsigned_byte (num))
2234 {
2235 t.bitfield.imm8 = 1;
2236 t.bitfield.imm16 = 1;
2237 t.bitfield.imm32 = 1;
2238 t.bitfield.imm32s = 1;
2239 }
2240 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2241 {
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2245 }
2246 else if (fits_in_signed_long (num))
2247 {
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2250 }
2251 else if (fits_in_unsigned_long (num))
2252 t.bitfield.imm32 = 1;
2253
2254 return t;
2255 }
2256
2257 static offsetT
2258 offset_in_range (offsetT val, int size)
2259 {
2260 addressT mask;
2261
2262 switch (size)
2263 {
2264 case 1: mask = ((addressT) 1 << 8) - 1; break;
2265 case 2: mask = ((addressT) 1 << 16) - 1; break;
2266 case 4: mask = ((addressT) 2 << 31) - 1; break;
2267 #ifdef BFD64
2268 case 8: mask = ((addressT) 2 << 63) - 1; break;
2269 #endif
2270 default: abort ();
2271 }
2272
2273 #ifdef BFD64
2274 /* If BFD64, sign extend val for 32bit address mode. */
2275 if (flag_code != CODE_64BIT
2276 || i.prefix[ADDR_PREFIX])
2277 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2278 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2279 #endif
2280
2281 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2282 {
2283 char buf1[40], buf2[40];
2284
2285 sprint_value (buf1, val);
2286 sprint_value (buf2, val & mask);
2287 as_warn (_("%s shortened to %s"), buf1, buf2);
2288 }
2289 return val & mask;
2290 }
2291
2292 enum PREFIX_GROUP
2293 {
2294 PREFIX_EXIST = 0,
2295 PREFIX_LOCK,
2296 PREFIX_REP,
2297 PREFIX_DS,
2298 PREFIX_OTHER
2299 };
2300
2301 /* Returns
2302 a. PREFIX_EXIST if attempting to add a prefix where one from the
2303 same class already exists.
2304 b. PREFIX_LOCK if lock prefix is added.
2305 c. PREFIX_REP if rep/repne prefix is added.
2306 d. PREFIX_DS if ds prefix is added.
2307 e. PREFIX_OTHER if other prefix is added.
2308 */
2309
2310 static enum PREFIX_GROUP
2311 add_prefix (unsigned int prefix)
2312 {
2313 enum PREFIX_GROUP ret = PREFIX_OTHER;
2314 unsigned int q;
2315
2316 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2317 && flag_code == CODE_64BIT)
2318 {
2319 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2320 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2321 && (prefix & (REX_R | REX_X | REX_B))))
2322 ret = PREFIX_EXIST;
2323 q = REX_PREFIX;
2324 }
2325 else
2326 {
2327 switch (prefix)
2328 {
2329 default:
2330 abort ();
2331
2332 case DS_PREFIX_OPCODE:
2333 ret = PREFIX_DS;
2334 /* Fall through. */
2335 case CS_PREFIX_OPCODE:
2336 case ES_PREFIX_OPCODE:
2337 case FS_PREFIX_OPCODE:
2338 case GS_PREFIX_OPCODE:
2339 case SS_PREFIX_OPCODE:
2340 q = SEG_PREFIX;
2341 break;
2342
2343 case REPNE_PREFIX_OPCODE:
2344 case REPE_PREFIX_OPCODE:
2345 q = REP_PREFIX;
2346 ret = PREFIX_REP;
2347 break;
2348
2349 case LOCK_PREFIX_OPCODE:
2350 q = LOCK_PREFIX;
2351 ret = PREFIX_LOCK;
2352 break;
2353
2354 case FWAIT_OPCODE:
2355 q = WAIT_PREFIX;
2356 break;
2357
2358 case ADDR_PREFIX_OPCODE:
2359 q = ADDR_PREFIX;
2360 break;
2361
2362 case DATA_PREFIX_OPCODE:
2363 q = DATA_PREFIX;
2364 break;
2365 }
2366 if (i.prefix[q] != 0)
2367 ret = PREFIX_EXIST;
2368 }
2369
2370 if (ret)
2371 {
2372 if (!i.prefix[q])
2373 ++i.prefixes;
2374 i.prefix[q] |= prefix;
2375 }
2376 else
2377 as_bad (_("same type of prefix used twice"));
2378
2379 return ret;
2380 }
2381
2382 static void
2383 update_code_flag (int value, int check)
2384 {
2385 PRINTF_LIKE ((*as_error));
2386
2387 flag_code = (enum flag_code) value;
2388 if (flag_code == CODE_64BIT)
2389 {
2390 cpu_arch_flags.bitfield.cpu64 = 1;
2391 cpu_arch_flags.bitfield.cpuno64 = 0;
2392 }
2393 else
2394 {
2395 cpu_arch_flags.bitfield.cpu64 = 0;
2396 cpu_arch_flags.bitfield.cpuno64 = 1;
2397 }
2398 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2399 {
2400 if (check)
2401 as_error = as_fatal;
2402 else
2403 as_error = as_bad;
2404 (*as_error) (_("64bit mode not supported on `%s'."),
2405 cpu_arch_name ? cpu_arch_name : default_arch);
2406 }
2407 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2408 {
2409 if (check)
2410 as_error = as_fatal;
2411 else
2412 as_error = as_bad;
2413 (*as_error) (_("32bit mode not supported on `%s'."),
2414 cpu_arch_name ? cpu_arch_name : default_arch);
2415 }
2416 stackop_size = '\0';
2417 }
2418
2419 static void
2420 set_code_flag (int value)
2421 {
2422 update_code_flag (value, 0);
2423 }
2424
2425 static void
2426 set_16bit_gcc_code_flag (int new_code_flag)
2427 {
2428 flag_code = (enum flag_code) new_code_flag;
2429 if (flag_code != CODE_16BIT)
2430 abort ();
2431 cpu_arch_flags.bitfield.cpu64 = 0;
2432 cpu_arch_flags.bitfield.cpuno64 = 1;
2433 stackop_size = LONG_MNEM_SUFFIX;
2434 }
2435
2436 static void
2437 set_intel_syntax (int syntax_flag)
2438 {
2439 /* Find out if register prefixing is specified. */
2440 int ask_naked_reg = 0;
2441
2442 SKIP_WHITESPACE ();
2443 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2444 {
2445 char *string;
2446 int e = get_symbol_name (&string);
2447
2448 if (strcmp (string, "prefix") == 0)
2449 ask_naked_reg = 1;
2450 else if (strcmp (string, "noprefix") == 0)
2451 ask_naked_reg = -1;
2452 else
2453 as_bad (_("bad argument to syntax directive."));
2454 (void) restore_line_pointer (e);
2455 }
2456 demand_empty_rest_of_line ();
2457
2458 intel_syntax = syntax_flag;
2459
2460 if (ask_naked_reg == 0)
2461 allow_naked_reg = (intel_syntax
2462 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2463 else
2464 allow_naked_reg = (ask_naked_reg < 0);
2465
2466 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2467
2468 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2469 identifier_chars['$'] = intel_syntax ? '$' : 0;
2470 register_prefix = allow_naked_reg ? "" : "%";
2471 }
2472
2473 static void
2474 set_intel_mnemonic (int mnemonic_flag)
2475 {
2476 intel_mnemonic = mnemonic_flag;
2477 }
2478
2479 static void
2480 set_allow_index_reg (int flag)
2481 {
2482 allow_index_reg = flag;
2483 }
2484
2485 static void
2486 set_check (int what)
2487 {
2488 enum check_kind *kind;
2489 const char *str;
2490
2491 if (what)
2492 {
2493 kind = &operand_check;
2494 str = "operand";
2495 }
2496 else
2497 {
2498 kind = &sse_check;
2499 str = "sse";
2500 }
2501
2502 SKIP_WHITESPACE ();
2503
2504 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2505 {
2506 char *string;
2507 int e = get_symbol_name (&string);
2508
2509 if (strcmp (string, "none") == 0)
2510 *kind = check_none;
2511 else if (strcmp (string, "warning") == 0)
2512 *kind = check_warning;
2513 else if (strcmp (string, "error") == 0)
2514 *kind = check_error;
2515 else
2516 as_bad (_("bad argument to %s_check directive."), str);
2517 (void) restore_line_pointer (e);
2518 }
2519 else
2520 as_bad (_("missing argument for %s_check directive"), str);
2521
2522 demand_empty_rest_of_line ();
2523 }
2524
2525 static void
2526 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2527 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2528 {
2529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2530 static const char *arch;
2531
2532 /* Intel LIOM is only supported on ELF. */
2533 if (!IS_ELF)
2534 return;
2535
2536 if (!arch)
2537 {
2538 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2539 use default_arch. */
2540 arch = cpu_arch_name;
2541 if (!arch)
2542 arch = default_arch;
2543 }
2544
2545 /* If we are targeting Intel MCU, we must enable it. */
2546 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2547 || new_flag.bitfield.cpuiamcu)
2548 return;
2549
2550 /* If we are targeting Intel L1OM, we must enable it. */
2551 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2552 || new_flag.bitfield.cpul1om)
2553 return;
2554
2555 /* If we are targeting Intel K1OM, we must enable it. */
2556 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2557 || new_flag.bitfield.cpuk1om)
2558 return;
2559
2560 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2561 #endif
2562 }
2563
2564 static void
2565 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2566 {
2567 SKIP_WHITESPACE ();
2568
2569 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2570 {
2571 char *string;
2572 int e = get_symbol_name (&string);
2573 unsigned int j;
2574 i386_cpu_flags flags;
2575
2576 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2577 {
2578 if (strcmp (string, cpu_arch[j].name) == 0)
2579 {
2580 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2581
2582 if (*string != '.')
2583 {
2584 cpu_arch_name = cpu_arch[j].name;
2585 cpu_sub_arch_name = NULL;
2586 cpu_arch_flags = cpu_arch[j].flags;
2587 if (flag_code == CODE_64BIT)
2588 {
2589 cpu_arch_flags.bitfield.cpu64 = 1;
2590 cpu_arch_flags.bitfield.cpuno64 = 0;
2591 }
2592 else
2593 {
2594 cpu_arch_flags.bitfield.cpu64 = 0;
2595 cpu_arch_flags.bitfield.cpuno64 = 1;
2596 }
2597 cpu_arch_isa = cpu_arch[j].type;
2598 cpu_arch_isa_flags = cpu_arch[j].flags;
2599 if (!cpu_arch_tune_set)
2600 {
2601 cpu_arch_tune = cpu_arch_isa;
2602 cpu_arch_tune_flags = cpu_arch_isa_flags;
2603 }
2604 break;
2605 }
2606
2607 flags = cpu_flags_or (cpu_arch_flags,
2608 cpu_arch[j].flags);
2609
2610 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2611 {
2612 if (cpu_sub_arch_name)
2613 {
2614 char *name = cpu_sub_arch_name;
2615 cpu_sub_arch_name = concat (name,
2616 cpu_arch[j].name,
2617 (const char *) NULL);
2618 free (name);
2619 }
2620 else
2621 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2622 cpu_arch_flags = flags;
2623 cpu_arch_isa_flags = flags;
2624 }
2625 else
2626 cpu_arch_isa_flags
2627 = cpu_flags_or (cpu_arch_isa_flags,
2628 cpu_arch[j].flags);
2629 (void) restore_line_pointer (e);
2630 demand_empty_rest_of_line ();
2631 return;
2632 }
2633 }
2634
2635 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2636 {
2637 /* Disable an ISA extension. */
2638 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2639 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2640 {
2641 flags = cpu_flags_and_not (cpu_arch_flags,
2642 cpu_noarch[j].flags);
2643 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2644 {
2645 if (cpu_sub_arch_name)
2646 {
2647 char *name = cpu_sub_arch_name;
2648 cpu_sub_arch_name = concat (name, string,
2649 (const char *) NULL);
2650 free (name);
2651 }
2652 else
2653 cpu_sub_arch_name = xstrdup (string);
2654 cpu_arch_flags = flags;
2655 cpu_arch_isa_flags = flags;
2656 }
2657 (void) restore_line_pointer (e);
2658 demand_empty_rest_of_line ();
2659 return;
2660 }
2661
2662 j = ARRAY_SIZE (cpu_arch);
2663 }
2664
2665 if (j >= ARRAY_SIZE (cpu_arch))
2666 as_bad (_("no such architecture: `%s'"), string);
2667
2668 *input_line_pointer = e;
2669 }
2670 else
2671 as_bad (_("missing cpu architecture"));
2672
2673 no_cond_jump_promotion = 0;
2674 if (*input_line_pointer == ','
2675 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2676 {
2677 char *string;
2678 char e;
2679
2680 ++input_line_pointer;
2681 e = get_symbol_name (&string);
2682
2683 if (strcmp (string, "nojumps") == 0)
2684 no_cond_jump_promotion = 1;
2685 else if (strcmp (string, "jumps") == 0)
2686 ;
2687 else
2688 as_bad (_("no such architecture modifier: `%s'"), string);
2689
2690 (void) restore_line_pointer (e);
2691 }
2692
2693 demand_empty_rest_of_line ();
2694 }
2695
2696 enum bfd_architecture
2697 i386_arch (void)
2698 {
2699 if (cpu_arch_isa == PROCESSOR_L1OM)
2700 {
2701 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2702 || flag_code != CODE_64BIT)
2703 as_fatal (_("Intel L1OM is 64bit ELF only"));
2704 return bfd_arch_l1om;
2705 }
2706 else if (cpu_arch_isa == PROCESSOR_K1OM)
2707 {
2708 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2709 || flag_code != CODE_64BIT)
2710 as_fatal (_("Intel K1OM is 64bit ELF only"));
2711 return bfd_arch_k1om;
2712 }
2713 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2714 {
2715 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2716 || flag_code == CODE_64BIT)
2717 as_fatal (_("Intel MCU is 32bit ELF only"));
2718 return bfd_arch_iamcu;
2719 }
2720 else
2721 return bfd_arch_i386;
2722 }
2723
2724 unsigned long
2725 i386_mach (void)
2726 {
2727 if (!strncmp (default_arch, "x86_64", 6))
2728 {
2729 if (cpu_arch_isa == PROCESSOR_L1OM)
2730 {
2731 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2732 || default_arch[6] != '\0')
2733 as_fatal (_("Intel L1OM is 64bit ELF only"));
2734 return bfd_mach_l1om;
2735 }
2736 else if (cpu_arch_isa == PROCESSOR_K1OM)
2737 {
2738 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2739 || default_arch[6] != '\0')
2740 as_fatal (_("Intel K1OM is 64bit ELF only"));
2741 return bfd_mach_k1om;
2742 }
2743 else if (default_arch[6] == '\0')
2744 return bfd_mach_x86_64;
2745 else
2746 return bfd_mach_x64_32;
2747 }
2748 else if (!strcmp (default_arch, "i386")
2749 || !strcmp (default_arch, "iamcu"))
2750 {
2751 if (cpu_arch_isa == PROCESSOR_IAMCU)
2752 {
2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2754 as_fatal (_("Intel MCU is 32bit ELF only"));
2755 return bfd_mach_i386_iamcu;
2756 }
2757 else
2758 return bfd_mach_i386_i386;
2759 }
2760 else
2761 as_fatal (_("unknown architecture"));
2762 }
2763 \f
2764 void
2765 md_begin (void)
2766 {
2767 const char *hash_err;
2768
2769 /* Support pseudo prefixes like {disp32}. */
2770 lex_type ['{'] = LEX_BEGIN_NAME;
2771
2772 /* Initialize op_hash hash table. */
2773 op_hash = hash_new ();
2774
2775 {
2776 const insn_template *optab;
2777 templates *core_optab;
2778
2779 /* Setup for loop. */
2780 optab = i386_optab;
2781 core_optab = XNEW (templates);
2782 core_optab->start = optab;
2783
2784 while (1)
2785 {
2786 ++optab;
2787 if (optab->name == NULL
2788 || strcmp (optab->name, (optab - 1)->name) != 0)
2789 {
2790 /* different name --> ship out current template list;
2791 add to hash table; & begin anew. */
2792 core_optab->end = optab;
2793 hash_err = hash_insert (op_hash,
2794 (optab - 1)->name,
2795 (void *) core_optab);
2796 if (hash_err)
2797 {
2798 as_fatal (_("can't hash %s: %s"),
2799 (optab - 1)->name,
2800 hash_err);
2801 }
2802 if (optab->name == NULL)
2803 break;
2804 core_optab = XNEW (templates);
2805 core_optab->start = optab;
2806 }
2807 }
2808 }
2809
2810 /* Initialize reg_hash hash table. */
2811 reg_hash = hash_new ();
2812 {
2813 const reg_entry *regtab;
2814 unsigned int regtab_size = i386_regtab_size;
2815
2816 for (regtab = i386_regtab; regtab_size--; regtab++)
2817 {
2818 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2819 if (hash_err)
2820 as_fatal (_("can't hash %s: %s"),
2821 regtab->reg_name,
2822 hash_err);
2823 }
2824 }
2825
2826 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2827 {
2828 int c;
2829 char *p;
2830
2831 for (c = 0; c < 256; c++)
2832 {
2833 if (ISDIGIT (c))
2834 {
2835 digit_chars[c] = c;
2836 mnemonic_chars[c] = c;
2837 register_chars[c] = c;
2838 operand_chars[c] = c;
2839 }
2840 else if (ISLOWER (c))
2841 {
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2845 }
2846 else if (ISUPPER (c))
2847 {
2848 mnemonic_chars[c] = TOLOWER (c);
2849 register_chars[c] = mnemonic_chars[c];
2850 operand_chars[c] = c;
2851 }
2852 else if (c == '{' || c == '}')
2853 {
2854 mnemonic_chars[c] = c;
2855 operand_chars[c] = c;
2856 }
2857
2858 if (ISALPHA (c) || ISDIGIT (c))
2859 identifier_chars[c] = c;
2860 else if (c >= 128)
2861 {
2862 identifier_chars[c] = c;
2863 operand_chars[c] = c;
2864 }
2865 }
2866
2867 #ifdef LEX_AT
2868 identifier_chars['@'] = '@';
2869 #endif
2870 #ifdef LEX_QM
2871 identifier_chars['?'] = '?';
2872 operand_chars['?'] = '?';
2873 #endif
2874 digit_chars['-'] = '-';
2875 mnemonic_chars['_'] = '_';
2876 mnemonic_chars['-'] = '-';
2877 mnemonic_chars['.'] = '.';
2878 identifier_chars['_'] = '_';
2879 identifier_chars['.'] = '.';
2880
2881 for (p = operand_special_chars; *p != '\0'; p++)
2882 operand_chars[(unsigned char) *p] = *p;
2883 }
2884
2885 if (flag_code == CODE_64BIT)
2886 {
2887 #if defined (OBJ_COFF) && defined (TE_PE)
2888 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2889 ? 32 : 16);
2890 #else
2891 x86_dwarf2_return_column = 16;
2892 #endif
2893 x86_cie_data_alignment = -8;
2894 }
2895 else
2896 {
2897 x86_dwarf2_return_column = 8;
2898 x86_cie_data_alignment = -4;
2899 }
2900 }
2901
2902 void
2903 i386_print_statistics (FILE *file)
2904 {
2905 hash_print_statistics (file, "i386 opcode", op_hash);
2906 hash_print_statistics (file, "i386 register", reg_hash);
2907 }
2908 \f
2909 #ifdef DEBUG386
2910
2911 /* Debugging routines for md_assemble. */
2912 static void pte (insn_template *);
2913 static void pt (i386_operand_type);
2914 static void pe (expressionS *);
2915 static void ps (symbolS *);
2916
2917 static void
2918 pi (char *line, i386_insn *x)
2919 {
2920 unsigned int j;
2921
2922 fprintf (stdout, "%s: template ", line);
2923 pte (&x->tm);
2924 fprintf (stdout, " address: base %s index %s scale %x\n",
2925 x->base_reg ? x->base_reg->reg_name : "none",
2926 x->index_reg ? x->index_reg->reg_name : "none",
2927 x->log2_scale_factor);
2928 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2929 x->rm.mode, x->rm.reg, x->rm.regmem);
2930 fprintf (stdout, " sib: base %x index %x scale %x\n",
2931 x->sib.base, x->sib.index, x->sib.scale);
2932 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2933 (x->rex & REX_W) != 0,
2934 (x->rex & REX_R) != 0,
2935 (x->rex & REX_X) != 0,
2936 (x->rex & REX_B) != 0);
2937 for (j = 0; j < x->operands; j++)
2938 {
2939 fprintf (stdout, " #%d: ", j + 1);
2940 pt (x->types[j]);
2941 fprintf (stdout, "\n");
2942 if (x->types[j].bitfield.reg
2943 || x->types[j].bitfield.regmmx
2944 || x->types[j].bitfield.regsimd
2945 || x->types[j].bitfield.sreg2
2946 || x->types[j].bitfield.sreg3
2947 || x->types[j].bitfield.control
2948 || x->types[j].bitfield.debug
2949 || x->types[j].bitfield.test)
2950 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2951 if (operand_type_check (x->types[j], imm))
2952 pe (x->op[j].imms);
2953 if (operand_type_check (x->types[j], disp))
2954 pe (x->op[j].disps);
2955 }
2956 }
2957
2958 static void
2959 pte (insn_template *t)
2960 {
2961 unsigned int j;
2962 fprintf (stdout, " %d operands ", t->operands);
2963 fprintf (stdout, "opcode %x ", t->base_opcode);
2964 if (t->extension_opcode != None)
2965 fprintf (stdout, "ext %x ", t->extension_opcode);
2966 if (t->opcode_modifier.d)
2967 fprintf (stdout, "D");
2968 if (t->opcode_modifier.w)
2969 fprintf (stdout, "W");
2970 fprintf (stdout, "\n");
2971 for (j = 0; j < t->operands; j++)
2972 {
2973 fprintf (stdout, " #%d type ", j + 1);
2974 pt (t->operand_types[j]);
2975 fprintf (stdout, "\n");
2976 }
2977 }
2978
2979 static void
2980 pe (expressionS *e)
2981 {
2982 fprintf (stdout, " operation %d\n", e->X_op);
2983 fprintf (stdout, " add_number %ld (%lx)\n",
2984 (long) e->X_add_number, (long) e->X_add_number);
2985 if (e->X_add_symbol)
2986 {
2987 fprintf (stdout, " add_symbol ");
2988 ps (e->X_add_symbol);
2989 fprintf (stdout, "\n");
2990 }
2991 if (e->X_op_symbol)
2992 {
2993 fprintf (stdout, " op_symbol ");
2994 ps (e->X_op_symbol);
2995 fprintf (stdout, "\n");
2996 }
2997 }
2998
2999 static void
3000 ps (symbolS *s)
3001 {
3002 fprintf (stdout, "%s type %s%s",
3003 S_GET_NAME (s),
3004 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3005 segment_name (S_GET_SEGMENT (s)));
3006 }
3007
3008 static struct type_name
3009 {
3010 i386_operand_type mask;
3011 const char *name;
3012 }
3013 const type_names[] =
3014 {
3015 { OPERAND_TYPE_REG8, "r8" },
3016 { OPERAND_TYPE_REG16, "r16" },
3017 { OPERAND_TYPE_REG32, "r32" },
3018 { OPERAND_TYPE_REG64, "r64" },
3019 { OPERAND_TYPE_IMM8, "i8" },
3020 { OPERAND_TYPE_IMM8, "i8s" },
3021 { OPERAND_TYPE_IMM16, "i16" },
3022 { OPERAND_TYPE_IMM32, "i32" },
3023 { OPERAND_TYPE_IMM32S, "i32s" },
3024 { OPERAND_TYPE_IMM64, "i64" },
3025 { OPERAND_TYPE_IMM1, "i1" },
3026 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3027 { OPERAND_TYPE_DISP8, "d8" },
3028 { OPERAND_TYPE_DISP16, "d16" },
3029 { OPERAND_TYPE_DISP32, "d32" },
3030 { OPERAND_TYPE_DISP32S, "d32s" },
3031 { OPERAND_TYPE_DISP64, "d64" },
3032 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3033 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3034 { OPERAND_TYPE_CONTROL, "control reg" },
3035 { OPERAND_TYPE_TEST, "test reg" },
3036 { OPERAND_TYPE_DEBUG, "debug reg" },
3037 { OPERAND_TYPE_FLOATREG, "FReg" },
3038 { OPERAND_TYPE_FLOATACC, "FAcc" },
3039 { OPERAND_TYPE_SREG2, "SReg2" },
3040 { OPERAND_TYPE_SREG3, "SReg3" },
3041 { OPERAND_TYPE_ACC, "Acc" },
3042 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3043 { OPERAND_TYPE_REGMMX, "rMMX" },
3044 { OPERAND_TYPE_REGXMM, "rXMM" },
3045 { OPERAND_TYPE_REGYMM, "rYMM" },
3046 { OPERAND_TYPE_REGZMM, "rZMM" },
3047 { OPERAND_TYPE_REGMASK, "Mask reg" },
3048 { OPERAND_TYPE_ESSEG, "es" },
3049 };
3050
3051 static void
3052 pt (i386_operand_type t)
3053 {
3054 unsigned int j;
3055 i386_operand_type a;
3056
3057 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3058 {
3059 a = operand_type_and (t, type_names[j].mask);
3060 if (!operand_type_all_zero (&a))
3061 fprintf (stdout, "%s, ", type_names[j].name);
3062 }
3063 fflush (stdout);
3064 }
3065
3066 #endif /* DEBUG386 */
3067 \f
3068 static bfd_reloc_code_real_type
3069 reloc (unsigned int size,
3070 int pcrel,
3071 int sign,
3072 bfd_reloc_code_real_type other)
3073 {
3074 if (other != NO_RELOC)
3075 {
3076 reloc_howto_type *rel;
3077
3078 if (size == 8)
3079 switch (other)
3080 {
3081 case BFD_RELOC_X86_64_GOT32:
3082 return BFD_RELOC_X86_64_GOT64;
3083 break;
3084 case BFD_RELOC_X86_64_GOTPLT64:
3085 return BFD_RELOC_X86_64_GOTPLT64;
3086 break;
3087 case BFD_RELOC_X86_64_PLTOFF64:
3088 return BFD_RELOC_X86_64_PLTOFF64;
3089 break;
3090 case BFD_RELOC_X86_64_GOTPC32:
3091 other = BFD_RELOC_X86_64_GOTPC64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPCREL:
3094 other = BFD_RELOC_X86_64_GOTPCREL64;
3095 break;
3096 case BFD_RELOC_X86_64_TPOFF32:
3097 other = BFD_RELOC_X86_64_TPOFF64;
3098 break;
3099 case BFD_RELOC_X86_64_DTPOFF32:
3100 other = BFD_RELOC_X86_64_DTPOFF64;
3101 break;
3102 default:
3103 break;
3104 }
3105
3106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3107 if (other == BFD_RELOC_SIZE32)
3108 {
3109 if (size == 8)
3110 other = BFD_RELOC_SIZE64;
3111 if (pcrel)
3112 {
3113 as_bad (_("there are no pc-relative size relocations"));
3114 return NO_RELOC;
3115 }
3116 }
3117 #endif
3118
3119 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3120 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3121 sign = -1;
3122
3123 rel = bfd_reloc_type_lookup (stdoutput, other);
3124 if (!rel)
3125 as_bad (_("unknown relocation (%u)"), other);
3126 else if (size != bfd_get_reloc_size (rel))
3127 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3128 bfd_get_reloc_size (rel),
3129 size);
3130 else if (pcrel && !rel->pc_relative)
3131 as_bad (_("non-pc-relative relocation for pc-relative field"));
3132 else if ((rel->complain_on_overflow == complain_overflow_signed
3133 && !sign)
3134 || (rel->complain_on_overflow == complain_overflow_unsigned
3135 && sign > 0))
3136 as_bad (_("relocated field and relocation type differ in signedness"));
3137 else
3138 return other;
3139 return NO_RELOC;
3140 }
3141
3142 if (pcrel)
3143 {
3144 if (!sign)
3145 as_bad (_("there are no unsigned pc-relative relocations"));
3146 switch (size)
3147 {
3148 case 1: return BFD_RELOC_8_PCREL;
3149 case 2: return BFD_RELOC_16_PCREL;
3150 case 4: return BFD_RELOC_32_PCREL;
3151 case 8: return BFD_RELOC_64_PCREL;
3152 }
3153 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3154 }
3155 else
3156 {
3157 if (sign > 0)
3158 switch (size)
3159 {
3160 case 4: return BFD_RELOC_X86_64_32S;
3161 }
3162 else
3163 switch (size)
3164 {
3165 case 1: return BFD_RELOC_8;
3166 case 2: return BFD_RELOC_16;
3167 case 4: return BFD_RELOC_32;
3168 case 8: return BFD_RELOC_64;
3169 }
3170 as_bad (_("cannot do %s %u byte relocation"),
3171 sign > 0 ? "signed" : "unsigned", size);
3172 }
3173
3174 return NO_RELOC;
3175 }
3176
3177 /* Here we decide which fixups can be adjusted to make them relative to
3178 the beginning of the section instead of the symbol. Basically we need
3179 to make sure that the dynamic relocations are done correctly, so in
3180 some cases we force the original symbol to be used. */
3181
3182 int
3183 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3184 {
3185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3186 if (!IS_ELF)
3187 return 1;
3188
3189 /* Don't adjust pc-relative references to merge sections in 64-bit
3190 mode. */
3191 if (use_rela_relocations
3192 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3193 && fixP->fx_pcrel)
3194 return 0;
3195
3196 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3197 and changed later by validate_fix. */
3198 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3199 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3200 return 0;
3201
3202 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3203 for size relocations. */
3204 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3205 || fixP->fx_r_type == BFD_RELOC_SIZE64
3206 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3207 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3208 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3209 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3210 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3211 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3212 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3220 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3221 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3222 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3235 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3236 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3237 return 0;
3238 #endif
3239 return 1;
3240 }
3241
3242 static int
3243 intel_float_operand (const char *mnemonic)
3244 {
3245 /* Note that the value returned is meaningful only for opcodes with (memory)
3246 operands, hence the code here is free to improperly handle opcodes that
3247 have no operands (for better performance and smaller code). */
3248
3249 if (mnemonic[0] != 'f')
3250 return 0; /* non-math */
3251
3252 switch (mnemonic[1])
3253 {
3254 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3255 the fs segment override prefix not currently handled because no
3256 call path can make opcodes without operands get here */
3257 case 'i':
3258 return 2 /* integer op */;
3259 case 'l':
3260 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3261 return 3; /* fldcw/fldenv */
3262 break;
3263 case 'n':
3264 if (mnemonic[2] != 'o' /* fnop */)
3265 return 3; /* non-waiting control op */
3266 break;
3267 case 'r':
3268 if (mnemonic[2] == 's')
3269 return 3; /* frstor/frstpm */
3270 break;
3271 case 's':
3272 if (mnemonic[2] == 'a')
3273 return 3; /* fsave */
3274 if (mnemonic[2] == 't')
3275 {
3276 switch (mnemonic[3])
3277 {
3278 case 'c': /* fstcw */
3279 case 'd': /* fstdw */
3280 case 'e': /* fstenv */
3281 case 's': /* fsts[gw] */
3282 return 3;
3283 }
3284 }
3285 break;
3286 case 'x':
3287 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3288 return 0; /* fxsave/fxrstor are not really math ops */
3289 break;
3290 }
3291
3292 return 1;
3293 }
3294
3295 /* Build the VEX prefix. */
3296
3297 static void
3298 build_vex_prefix (const insn_template *t)
3299 {
3300 unsigned int register_specifier;
3301 unsigned int implied_prefix;
3302 unsigned int vector_length;
3303
3304 /* Check register specifier. */
3305 if (i.vex.register_specifier)
3306 {
3307 register_specifier =
3308 ~register_number (i.vex.register_specifier) & 0xf;
3309 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3310 }
3311 else
3312 register_specifier = 0xf;
3313
3314 /* Use 2-byte VEX prefix by swapping destination and source
3315 operand. */
3316 if (i.vec_encoding != vex_encoding_vex3
3317 && i.dir_encoding == dir_encoding_default
3318 && i.operands == i.reg_operands
3319 && i.tm.opcode_modifier.vexopcode == VEX0F
3320 && i.tm.opcode_modifier.load
3321 && i.rex == REX_B)
3322 {
3323 unsigned int xchg = i.operands - 1;
3324 union i386_op temp_op;
3325 i386_operand_type temp_type;
3326
3327 temp_type = i.types[xchg];
3328 i.types[xchg] = i.types[0];
3329 i.types[0] = temp_type;
3330 temp_op = i.op[xchg];
3331 i.op[xchg] = i.op[0];
3332 i.op[0] = temp_op;
3333
3334 gas_assert (i.rm.mode == 3);
3335
3336 i.rex = REX_R;
3337 xchg = i.rm.regmem;
3338 i.rm.regmem = i.rm.reg;
3339 i.rm.reg = xchg;
3340
3341 /* Use the next insn. */
3342 i.tm = t[1];
3343 }
3344
3345 if (i.tm.opcode_modifier.vex == VEXScalar)
3346 vector_length = avxscalar;
3347 else if (i.tm.opcode_modifier.vex == VEX256)
3348 vector_length = 1;
3349 else
3350 {
3351 unsigned int op;
3352
3353 vector_length = 0;
3354 for (op = 0; op < t->operands; ++op)
3355 if (t->operand_types[op].bitfield.xmmword
3356 && t->operand_types[op].bitfield.ymmword
3357 && i.types[op].bitfield.ymmword)
3358 {
3359 vector_length = 1;
3360 break;
3361 }
3362 }
3363
3364 switch ((i.tm.base_opcode >> 8) & 0xff)
3365 {
3366 case 0:
3367 implied_prefix = 0;
3368 break;
3369 case DATA_PREFIX_OPCODE:
3370 implied_prefix = 1;
3371 break;
3372 case REPE_PREFIX_OPCODE:
3373 implied_prefix = 2;
3374 break;
3375 case REPNE_PREFIX_OPCODE:
3376 implied_prefix = 3;
3377 break;
3378 default:
3379 abort ();
3380 }
3381
3382 /* Use 2-byte VEX prefix if possible. */
3383 if (i.vec_encoding != vex_encoding_vex3
3384 && i.tm.opcode_modifier.vexopcode == VEX0F
3385 && i.tm.opcode_modifier.vexw != VEXW1
3386 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3387 {
3388 /* 2-byte VEX prefix. */
3389 unsigned int r;
3390
3391 i.vex.length = 2;
3392 i.vex.bytes[0] = 0xc5;
3393
3394 /* Check the REX.R bit. */
3395 r = (i.rex & REX_R) ? 0 : 1;
3396 i.vex.bytes[1] = (r << 7
3397 | register_specifier << 3
3398 | vector_length << 2
3399 | implied_prefix);
3400 }
3401 else
3402 {
3403 /* 3-byte VEX prefix. */
3404 unsigned int m, w;
3405
3406 i.vex.length = 3;
3407
3408 switch (i.tm.opcode_modifier.vexopcode)
3409 {
3410 case VEX0F:
3411 m = 0x1;
3412 i.vex.bytes[0] = 0xc4;
3413 break;
3414 case VEX0F38:
3415 m = 0x2;
3416 i.vex.bytes[0] = 0xc4;
3417 break;
3418 case VEX0F3A:
3419 m = 0x3;
3420 i.vex.bytes[0] = 0xc4;
3421 break;
3422 case XOP08:
3423 m = 0x8;
3424 i.vex.bytes[0] = 0x8f;
3425 break;
3426 case XOP09:
3427 m = 0x9;
3428 i.vex.bytes[0] = 0x8f;
3429 break;
3430 case XOP0A:
3431 m = 0xa;
3432 i.vex.bytes[0] = 0x8f;
3433 break;
3434 default:
3435 abort ();
3436 }
3437
3438 /* The high 3 bits of the second VEX byte are 1's compliment
3439 of RXB bits from REX. */
3440 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3441
3442 /* Check the REX.W bit. */
3443 w = (i.rex & REX_W) ? 1 : 0;
3444 if (i.tm.opcode_modifier.vexw == VEXW1)
3445 w = 1;
3446
3447 i.vex.bytes[2] = (w << 7
3448 | register_specifier << 3
3449 | vector_length << 2
3450 | implied_prefix);
3451 }
3452 }
3453
3454 static INLINE bfd_boolean
3455 is_evex_encoding (const insn_template *t)
3456 {
3457 return t->opcode_modifier.evex
3458 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3459 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3460 }
3461
3462 /* Build the EVEX prefix. */
3463
3464 static void
3465 build_evex_prefix (void)
3466 {
3467 unsigned int register_specifier;
3468 unsigned int implied_prefix;
3469 unsigned int m, w;
3470 rex_byte vrex_used = 0;
3471
3472 /* Check register specifier. */
3473 if (i.vex.register_specifier)
3474 {
3475 gas_assert ((i.vrex & REX_X) == 0);
3476
3477 register_specifier = i.vex.register_specifier->reg_num;
3478 if ((i.vex.register_specifier->reg_flags & RegRex))
3479 register_specifier += 8;
3480 /* The upper 16 registers are encoded in the fourth byte of the
3481 EVEX prefix. */
3482 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3483 i.vex.bytes[3] = 0x8;
3484 register_specifier = ~register_specifier & 0xf;
3485 }
3486 else
3487 {
3488 register_specifier = 0xf;
3489
3490 /* Encode upper 16 vector index register in the fourth byte of
3491 the EVEX prefix. */
3492 if (!(i.vrex & REX_X))
3493 i.vex.bytes[3] = 0x8;
3494 else
3495 vrex_used |= REX_X;
3496 }
3497
3498 switch ((i.tm.base_opcode >> 8) & 0xff)
3499 {
3500 case 0:
3501 implied_prefix = 0;
3502 break;
3503 case DATA_PREFIX_OPCODE:
3504 implied_prefix = 1;
3505 break;
3506 case REPE_PREFIX_OPCODE:
3507 implied_prefix = 2;
3508 break;
3509 case REPNE_PREFIX_OPCODE:
3510 implied_prefix = 3;
3511 break;
3512 default:
3513 abort ();
3514 }
3515
3516 /* 4 byte EVEX prefix. */
3517 i.vex.length = 4;
3518 i.vex.bytes[0] = 0x62;
3519
3520 /* mmmm bits. */
3521 switch (i.tm.opcode_modifier.vexopcode)
3522 {
3523 case VEX0F:
3524 m = 1;
3525 break;
3526 case VEX0F38:
3527 m = 2;
3528 break;
3529 case VEX0F3A:
3530 m = 3;
3531 break;
3532 default:
3533 abort ();
3534 break;
3535 }
3536
3537 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3538 bits from REX. */
3539 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3540
3541 /* The fifth bit of the second EVEX byte is 1's compliment of the
3542 REX_R bit in VREX. */
3543 if (!(i.vrex & REX_R))
3544 i.vex.bytes[1] |= 0x10;
3545 else
3546 vrex_used |= REX_R;
3547
3548 if ((i.reg_operands + i.imm_operands) == i.operands)
3549 {
3550 /* When all operands are registers, the REX_X bit in REX is not
3551 used. We reuse it to encode the upper 16 registers, which is
3552 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3553 as 1's compliment. */
3554 if ((i.vrex & REX_B))
3555 {
3556 vrex_used |= REX_B;
3557 i.vex.bytes[1] &= ~0x40;
3558 }
3559 }
3560
3561 /* EVEX instructions shouldn't need the REX prefix. */
3562 i.vrex &= ~vrex_used;
3563 gas_assert (i.vrex == 0);
3564
3565 /* Check the REX.W bit. */
3566 w = (i.rex & REX_W) ? 1 : 0;
3567 if (i.tm.opcode_modifier.vexw)
3568 {
3569 if (i.tm.opcode_modifier.vexw == VEXW1)
3570 w = 1;
3571 }
3572 /* If w is not set it means we are dealing with WIG instruction. */
3573 else if (!w)
3574 {
3575 if (evexwig == evexw1)
3576 w = 1;
3577 }
3578
3579 /* Encode the U bit. */
3580 implied_prefix |= 0x4;
3581
3582 /* The third byte of the EVEX prefix. */
3583 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3584
3585 /* The fourth byte of the EVEX prefix. */
3586 /* The zeroing-masking bit. */
3587 if (i.mask && i.mask->zeroing)
3588 i.vex.bytes[3] |= 0x80;
3589
3590 /* Don't always set the broadcast bit if there is no RC. */
3591 if (!i.rounding)
3592 {
3593 /* Encode the vector length. */
3594 unsigned int vec_length;
3595
3596 if (!i.tm.opcode_modifier.evex
3597 || i.tm.opcode_modifier.evex == EVEXDYN)
3598 {
3599 unsigned int op;
3600
3601 vec_length = 0;
3602 for (op = 0; op < i.tm.operands; ++op)
3603 if (i.tm.operand_types[op].bitfield.xmmword
3604 + i.tm.operand_types[op].bitfield.ymmword
3605 + i.tm.operand_types[op].bitfield.zmmword > 1)
3606 {
3607 if (i.types[op].bitfield.zmmword)
3608 i.tm.opcode_modifier.evex = EVEX512;
3609 else if (i.types[op].bitfield.ymmword)
3610 i.tm.opcode_modifier.evex = EVEX256;
3611 else if (i.types[op].bitfield.xmmword)
3612 i.tm.opcode_modifier.evex = EVEX128;
3613 else
3614 continue;
3615 break;
3616 }
3617 }
3618
3619 switch (i.tm.opcode_modifier.evex)
3620 {
3621 case EVEXLIG: /* LL' is ignored */
3622 vec_length = evexlig << 5;
3623 break;
3624 case EVEX128:
3625 vec_length = 0 << 5;
3626 break;
3627 case EVEX256:
3628 vec_length = 1 << 5;
3629 break;
3630 case EVEX512:
3631 vec_length = 2 << 5;
3632 break;
3633 default:
3634 abort ();
3635 break;
3636 }
3637 i.vex.bytes[3] |= vec_length;
3638 /* Encode the broadcast bit. */
3639 if (i.broadcast)
3640 i.vex.bytes[3] |= 0x10;
3641 }
3642 else
3643 {
3644 if (i.rounding->type != saeonly)
3645 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3646 else
3647 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3648 }
3649
3650 if (i.mask && i.mask->mask)
3651 i.vex.bytes[3] |= i.mask->mask->reg_num;
3652 }
3653
3654 static void
3655 process_immext (void)
3656 {
3657 expressionS *exp;
3658
3659 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3660 && i.operands > 0)
3661 {
3662 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3663 with an opcode suffix which is coded in the same place as an
3664 8-bit immediate field would be.
3665 Here we check those operands and remove them afterwards. */
3666 unsigned int x;
3667
3668 for (x = 0; x < i.operands; x++)
3669 if (register_number (i.op[x].regs) != x)
3670 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3671 register_prefix, i.op[x].regs->reg_name, x + 1,
3672 i.tm.name);
3673
3674 i.operands = 0;
3675 }
3676
3677 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3678 {
3679 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3680 suffix which is coded in the same place as an 8-bit immediate
3681 field would be.
3682 Here we check those operands and remove them afterwards. */
3683 unsigned int x;
3684
3685 if (i.operands != 3)
3686 abort();
3687
3688 for (x = 0; x < 2; x++)
3689 if (register_number (i.op[x].regs) != x)
3690 goto bad_register_operand;
3691
3692 /* Check for third operand for mwaitx/monitorx insn. */
3693 if (register_number (i.op[x].regs)
3694 != (x + (i.tm.extension_opcode == 0xfb)))
3695 {
3696 bad_register_operand:
3697 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3698 register_prefix, i.op[x].regs->reg_name, x+1,
3699 i.tm.name);
3700 }
3701
3702 i.operands = 0;
3703 }
3704
3705 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3706 which is coded in the same place as an 8-bit immediate field
3707 would be. Here we fake an 8-bit immediate operand from the
3708 opcode suffix stored in tm.extension_opcode.
3709
3710 AVX instructions also use this encoding, for some of
3711 3 argument instructions. */
3712
3713 gas_assert (i.imm_operands <= 1
3714 && (i.operands <= 2
3715 || ((i.tm.opcode_modifier.vex
3716 || i.tm.opcode_modifier.vexopcode
3717 || is_evex_encoding (&i.tm))
3718 && i.operands <= 4)));
3719
3720 exp = &im_expressions[i.imm_operands++];
3721 i.op[i.operands].imms = exp;
3722 i.types[i.operands] = imm8;
3723 i.operands++;
3724 exp->X_op = O_constant;
3725 exp->X_add_number = i.tm.extension_opcode;
3726 i.tm.extension_opcode = None;
3727 }
3728
3729
3730 static int
3731 check_hle (void)
3732 {
3733 switch (i.tm.opcode_modifier.hleprefixok)
3734 {
3735 default:
3736 abort ();
3737 case HLEPrefixNone:
3738 as_bad (_("invalid instruction `%s' after `%s'"),
3739 i.tm.name, i.hle_prefix);
3740 return 0;
3741 case HLEPrefixLock:
3742 if (i.prefix[LOCK_PREFIX])
3743 return 1;
3744 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3745 return 0;
3746 case HLEPrefixAny:
3747 return 1;
3748 case HLEPrefixRelease:
3749 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3750 {
3751 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3752 i.tm.name);
3753 return 0;
3754 }
3755 if (i.mem_operands == 0
3756 || !operand_type_check (i.types[i.operands - 1], anymem))
3757 {
3758 as_bad (_("memory destination needed for instruction `%s'"
3759 " after `xrelease'"), i.tm.name);
3760 return 0;
3761 }
3762 return 1;
3763 }
3764 }
3765
3766 /* Try the shortest encoding by shortening operand size. */
3767
3768 static void
3769 optimize_encoding (void)
3770 {
3771 int j;
3772
3773 if (optimize_for_space
3774 && i.reg_operands == 1
3775 && i.imm_operands == 1
3776 && !i.types[1].bitfield.byte
3777 && i.op[0].imms->X_op == O_constant
3778 && fits_in_imm7 (i.op[0].imms->X_add_number)
3779 && ((i.tm.base_opcode == 0xa8
3780 && i.tm.extension_opcode == None)
3781 || (i.tm.base_opcode == 0xf6
3782 && i.tm.extension_opcode == 0x0)))
3783 {
3784 /* Optimize: -Os:
3785 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3786 */
3787 unsigned int base_regnum = i.op[1].regs->reg_num;
3788 if (flag_code == CODE_64BIT || base_regnum < 4)
3789 {
3790 i.types[1].bitfield.byte = 1;
3791 /* Ignore the suffix. */
3792 i.suffix = 0;
3793 if (base_regnum >= 4
3794 && !(i.op[1].regs->reg_flags & RegRex))
3795 {
3796 /* Handle SP, BP, SI and DI registers. */
3797 if (i.types[1].bitfield.word)
3798 j = 16;
3799 else if (i.types[1].bitfield.dword)
3800 j = 32;
3801 else
3802 j = 48;
3803 i.op[1].regs -= j;
3804 }
3805 }
3806 }
3807 else if (flag_code == CODE_64BIT
3808 && ((i.types[1].bitfield.qword
3809 && i.reg_operands == 1
3810 && i.imm_operands == 1
3811 && i.op[0].imms->X_op == O_constant
3812 && ((i.tm.base_opcode == 0xb0
3813 && i.tm.extension_opcode == None
3814 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3815 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3816 && (((i.tm.base_opcode == 0x24
3817 || i.tm.base_opcode == 0xa8)
3818 && i.tm.extension_opcode == None)
3819 || (i.tm.base_opcode == 0x80
3820 && i.tm.extension_opcode == 0x4)
3821 || ((i.tm.base_opcode == 0xf6
3822 || i.tm.base_opcode == 0xc6)
3823 && i.tm.extension_opcode == 0x0)))))
3824 || (i.types[0].bitfield.qword
3825 && ((i.reg_operands == 2
3826 && i.op[0].regs == i.op[1].regs
3827 && ((i.tm.base_opcode == 0x30
3828 || i.tm.base_opcode == 0x28)
3829 && i.tm.extension_opcode == None))
3830 || (i.reg_operands == 1
3831 && i.operands == 1
3832 && i.tm.base_opcode == 0x30
3833 && i.tm.extension_opcode == None)))))
3834 {
3835 /* Optimize: -O:
3836 andq $imm31, %r64 -> andl $imm31, %r32
3837 testq $imm31, %r64 -> testl $imm31, %r32
3838 xorq %r64, %r64 -> xorl %r32, %r32
3839 subq %r64, %r64 -> subl %r32, %r32
3840 movq $imm31, %r64 -> movl $imm31, %r32
3841 movq $imm32, %r64 -> movl $imm32, %r32
3842 */
3843 i.tm.opcode_modifier.norex64 = 1;
3844 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3845 {
3846 /* Handle
3847 movq $imm31, %r64 -> movl $imm31, %r32
3848 movq $imm32, %r64 -> movl $imm32, %r32
3849 */
3850 i.tm.operand_types[0].bitfield.imm32 = 1;
3851 i.tm.operand_types[0].bitfield.imm32s = 0;
3852 i.tm.operand_types[0].bitfield.imm64 = 0;
3853 i.types[0].bitfield.imm32 = 1;
3854 i.types[0].bitfield.imm32s = 0;
3855 i.types[0].bitfield.imm64 = 0;
3856 i.types[1].bitfield.dword = 1;
3857 i.types[1].bitfield.qword = 0;
3858 if (i.tm.base_opcode == 0xc6)
3859 {
3860 /* Handle
3861 movq $imm31, %r64 -> movl $imm31, %r32
3862 */
3863 i.tm.base_opcode = 0xb0;
3864 i.tm.extension_opcode = None;
3865 i.tm.opcode_modifier.shortform = 1;
3866 i.tm.opcode_modifier.modrm = 0;
3867 }
3868 }
3869 }
3870 else if (optimize > 1
3871 && i.reg_operands == 3
3872 && i.op[0].regs == i.op[1].regs
3873 && !i.types[2].bitfield.xmmword
3874 && (i.tm.opcode_modifier.vex
3875 || (!i.mask
3876 && !i.rounding
3877 && is_evex_encoding (&i.tm)
3878 && (i.vec_encoding != vex_encoding_evex
3879 || i.tm.cpu_flags.bitfield.cpuavx512vl
3880 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3881 && ((i.tm.base_opcode == 0x55
3882 || i.tm.base_opcode == 0x6655
3883 || i.tm.base_opcode == 0x66df
3884 || i.tm.base_opcode == 0x57
3885 || i.tm.base_opcode == 0x6657
3886 || i.tm.base_opcode == 0x66ef
3887 || i.tm.base_opcode == 0x66f8
3888 || i.tm.base_opcode == 0x66f9
3889 || i.tm.base_opcode == 0x66fa
3890 || i.tm.base_opcode == 0x66fb)
3891 && i.tm.extension_opcode == None))
3892 {
3893 /* Optimize: -O2:
3894 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3895 vpsubq and vpsubw:
3896 EVEX VOP %zmmM, %zmmM, %zmmN
3897 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3898 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3899 EVEX VOP %ymmM, %ymmM, %ymmN
3900 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3901 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3902 VEX VOP %ymmM, %ymmM, %ymmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN
3904 VOP, one of vpandn and vpxor:
3905 VEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN
3907 VOP, one of vpandnd and vpandnq:
3908 EVEX VOP %zmmM, %zmmM, %zmmN
3909 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3910 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3911 EVEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3913 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3914 VOP, one of vpxord and vpxorq:
3915 EVEX VOP %zmmM, %zmmM, %zmmN
3916 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3917 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3918 EVEX VOP %ymmM, %ymmM, %ymmN
3919 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3920 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3921 */
3922 if (is_evex_encoding (&i.tm))
3923 {
3924 if (i.vec_encoding == vex_encoding_evex)
3925 i.tm.opcode_modifier.evex = EVEX128;
3926 else
3927 {
3928 i.tm.opcode_modifier.vex = VEX128;
3929 i.tm.opcode_modifier.vexw = VEXW0;
3930 i.tm.opcode_modifier.evex = 0;
3931 }
3932 }
3933 else
3934 i.tm.opcode_modifier.vex = VEX128;
3935
3936 if (i.tm.opcode_modifier.vex)
3937 for (j = 0; j < 3; j++)
3938 {
3939 i.types[j].bitfield.xmmword = 1;
3940 i.types[j].bitfield.ymmword = 0;
3941 }
3942 }
3943 }
3944
3945 /* This is the guts of the machine-dependent assembler. LINE points to a
3946 machine dependent instruction. This function is supposed to emit
3947 the frags/bytes it assembles to. */
3948
3949 void
3950 md_assemble (char *line)
3951 {
3952 unsigned int j;
3953 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3954 const insn_template *t;
3955
3956 /* Initialize globals. */
3957 memset (&i, '\0', sizeof (i));
3958 for (j = 0; j < MAX_OPERANDS; j++)
3959 i.reloc[j] = NO_RELOC;
3960 memset (disp_expressions, '\0', sizeof (disp_expressions));
3961 memset (im_expressions, '\0', sizeof (im_expressions));
3962 save_stack_p = save_stack;
3963
3964 /* First parse an instruction mnemonic & call i386_operand for the operands.
3965 We assume that the scrubber has arranged it so that line[0] is the valid
3966 start of a (possibly prefixed) mnemonic. */
3967
3968 line = parse_insn (line, mnemonic);
3969 if (line == NULL)
3970 return;
3971 mnem_suffix = i.suffix;
3972
3973 line = parse_operands (line, mnemonic);
3974 this_operand = -1;
3975 xfree (i.memop1_string);
3976 i.memop1_string = NULL;
3977 if (line == NULL)
3978 return;
3979
3980 /* Now we've parsed the mnemonic into a set of templates, and have the
3981 operands at hand. */
3982
3983 /* All intel opcodes have reversed operands except for "bound" and
3984 "enter". We also don't reverse intersegment "jmp" and "call"
3985 instructions with 2 immediate operands so that the immediate segment
3986 precedes the offset, as it does when in AT&T mode. */
3987 if (intel_syntax
3988 && i.operands > 1
3989 && (strcmp (mnemonic, "bound") != 0)
3990 && (strcmp (mnemonic, "invlpga") != 0)
3991 && !(operand_type_check (i.types[0], imm)
3992 && operand_type_check (i.types[1], imm)))
3993 swap_operands ();
3994
3995 /* The order of the immediates should be reversed
3996 for 2 immediates extrq and insertq instructions */
3997 if (i.imm_operands == 2
3998 && (strcmp (mnemonic, "extrq") == 0
3999 || strcmp (mnemonic, "insertq") == 0))
4000 swap_2_operands (0, 1);
4001
4002 if (i.imm_operands)
4003 optimize_imm ();
4004
4005 /* Don't optimize displacement for movabs since it only takes 64bit
4006 displacement. */
4007 if (i.disp_operands
4008 && i.disp_encoding != disp_encoding_32bit
4009 && (flag_code != CODE_64BIT
4010 || strcmp (mnemonic, "movabs") != 0))
4011 optimize_disp ();
4012
4013 /* Next, we find a template that matches the given insn,
4014 making sure the overlap of the given operands types is consistent
4015 with the template operand types. */
4016
4017 if (!(t = match_template (mnem_suffix)))
4018 return;
4019
4020 if (sse_check != check_none
4021 && !i.tm.opcode_modifier.noavx
4022 && !i.tm.cpu_flags.bitfield.cpuavx
4023 && (i.tm.cpu_flags.bitfield.cpusse
4024 || i.tm.cpu_flags.bitfield.cpusse2
4025 || i.tm.cpu_flags.bitfield.cpusse3
4026 || i.tm.cpu_flags.bitfield.cpussse3
4027 || i.tm.cpu_flags.bitfield.cpusse4_1
4028 || i.tm.cpu_flags.bitfield.cpusse4_2
4029 || i.tm.cpu_flags.bitfield.cpupclmul
4030 || i.tm.cpu_flags.bitfield.cpuaes
4031 || i.tm.cpu_flags.bitfield.cpugfni))
4032 {
4033 (sse_check == check_warning
4034 ? as_warn
4035 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4036 }
4037
4038 /* Zap movzx and movsx suffix. The suffix has been set from
4039 "word ptr" or "byte ptr" on the source operand in Intel syntax
4040 or extracted from mnemonic in AT&T syntax. But we'll use
4041 the destination register to choose the suffix for encoding. */
4042 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4043 {
4044 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4045 there is no suffix, the default will be byte extension. */
4046 if (i.reg_operands != 2
4047 && !i.suffix
4048 && intel_syntax)
4049 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4050
4051 i.suffix = 0;
4052 }
4053
4054 if (i.tm.opcode_modifier.fwait)
4055 if (!add_prefix (FWAIT_OPCODE))
4056 return;
4057
4058 /* Check if REP prefix is OK. */
4059 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4060 {
4061 as_bad (_("invalid instruction `%s' after `%s'"),
4062 i.tm.name, i.rep_prefix);
4063 return;
4064 }
4065
4066 /* Check for lock without a lockable instruction. Destination operand
4067 must be memory unless it is xchg (0x86). */
4068 if (i.prefix[LOCK_PREFIX]
4069 && (!i.tm.opcode_modifier.islockable
4070 || i.mem_operands == 0
4071 || (i.tm.base_opcode != 0x86
4072 && !operand_type_check (i.types[i.operands - 1], anymem))))
4073 {
4074 as_bad (_("expecting lockable instruction after `lock'"));
4075 return;
4076 }
4077
4078 /* Check if HLE prefix is OK. */
4079 if (i.hle_prefix && !check_hle ())
4080 return;
4081
4082 /* Check BND prefix. */
4083 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4084 as_bad (_("expecting valid branch instruction after `bnd'"));
4085
4086 /* Check NOTRACK prefix. */
4087 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4088 as_bad (_("expecting indirect branch instruction after `notrack'"));
4089
4090 if (i.tm.cpu_flags.bitfield.cpumpx)
4091 {
4092 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4093 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4094 else if (flag_code != CODE_16BIT
4095 ? i.prefix[ADDR_PREFIX]
4096 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4097 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4098 }
4099
4100 /* Insert BND prefix. */
4101 if (add_bnd_prefix
4102 && i.tm.opcode_modifier.bndprefixok
4103 && !i.prefix[BND_PREFIX])
4104 add_prefix (BND_PREFIX_OPCODE);
4105
4106 /* Check string instruction segment overrides. */
4107 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4108 {
4109 if (!check_string ())
4110 return;
4111 i.disp_operands = 0;
4112 }
4113
4114 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4115 optimize_encoding ();
4116
4117 if (!process_suffix ())
4118 return;
4119
4120 /* Update operand types. */
4121 for (j = 0; j < i.operands; j++)
4122 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4123
4124 /* Make still unresolved immediate matches conform to size of immediate
4125 given in i.suffix. */
4126 if (!finalize_imm ())
4127 return;
4128
4129 if (i.types[0].bitfield.imm1)
4130 i.imm_operands = 0; /* kludge for shift insns. */
4131
4132 /* We only need to check those implicit registers for instructions
4133 with 3 operands or less. */
4134 if (i.operands <= 3)
4135 for (j = 0; j < i.operands; j++)
4136 if (i.types[j].bitfield.inoutportreg
4137 || i.types[j].bitfield.shiftcount
4138 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4139 i.reg_operands--;
4140
4141 /* ImmExt should be processed after SSE2AVX. */
4142 if (!i.tm.opcode_modifier.sse2avx
4143 && i.tm.opcode_modifier.immext)
4144 process_immext ();
4145
4146 /* For insns with operands there are more diddles to do to the opcode. */
4147 if (i.operands)
4148 {
4149 if (!process_operands ())
4150 return;
4151 }
4152 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4153 {
4154 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4155 as_warn (_("translating to `%sp'"), i.tm.name);
4156 }
4157
4158 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4159 || is_evex_encoding (&i.tm))
4160 {
4161 if (flag_code == CODE_16BIT)
4162 {
4163 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4164 i.tm.name);
4165 return;
4166 }
4167
4168 if (i.tm.opcode_modifier.vex)
4169 build_vex_prefix (t);
4170 else
4171 build_evex_prefix ();
4172 }
4173
4174 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4175 instructions may define INT_OPCODE as well, so avoid this corner
4176 case for those instructions that use MODRM. */
4177 if (i.tm.base_opcode == INT_OPCODE
4178 && !i.tm.opcode_modifier.modrm
4179 && i.op[0].imms->X_add_number == 3)
4180 {
4181 i.tm.base_opcode = INT3_OPCODE;
4182 i.imm_operands = 0;
4183 }
4184
4185 if ((i.tm.opcode_modifier.jump
4186 || i.tm.opcode_modifier.jumpbyte
4187 || i.tm.opcode_modifier.jumpdword)
4188 && i.op[0].disps->X_op == O_constant)
4189 {
4190 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4191 the absolute address given by the constant. Since ix86 jumps and
4192 calls are pc relative, we need to generate a reloc. */
4193 i.op[0].disps->X_add_symbol = &abs_symbol;
4194 i.op[0].disps->X_op = O_symbol;
4195 }
4196
4197 if (i.tm.opcode_modifier.rex64)
4198 i.rex |= REX_W;
4199
4200 /* For 8 bit registers we need an empty rex prefix. Also if the
4201 instruction already has a prefix, we need to convert old
4202 registers to new ones. */
4203
4204 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4205 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4206 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4207 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4208 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4209 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4210 && i.rex != 0))
4211 {
4212 int x;
4213
4214 i.rex |= REX_OPCODE;
4215 for (x = 0; x < 2; x++)
4216 {
4217 /* Look for 8 bit operand that uses old registers. */
4218 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4219 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4220 {
4221 /* In case it is "hi" register, give up. */
4222 if (i.op[x].regs->reg_num > 3)
4223 as_bad (_("can't encode register '%s%s' in an "
4224 "instruction requiring REX prefix."),
4225 register_prefix, i.op[x].regs->reg_name);
4226
4227 /* Otherwise it is equivalent to the extended register.
4228 Since the encoding doesn't change this is merely
4229 cosmetic cleanup for debug output. */
4230
4231 i.op[x].regs = i.op[x].regs + 8;
4232 }
4233 }
4234 }
4235
4236 if (i.rex == 0 && i.rex_encoding)
4237 {
4238 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4239 that uses legacy register. If it is "hi" register, don't add
4240 the REX_OPCODE byte. */
4241 int x;
4242 for (x = 0; x < 2; x++)
4243 if (i.types[x].bitfield.reg
4244 && i.types[x].bitfield.byte
4245 && (i.op[x].regs->reg_flags & RegRex64) == 0
4246 && i.op[x].regs->reg_num > 3)
4247 {
4248 i.rex_encoding = FALSE;
4249 break;
4250 }
4251
4252 if (i.rex_encoding)
4253 i.rex = REX_OPCODE;
4254 }
4255
4256 if (i.rex != 0)
4257 add_prefix (REX_OPCODE | i.rex);
4258
4259 /* We are ready to output the insn. */
4260 output_insn ();
4261 }
4262
4263 static char *
4264 parse_insn (char *line, char *mnemonic)
4265 {
4266 char *l = line;
4267 char *token_start = l;
4268 char *mnem_p;
4269 int supported;
4270 const insn_template *t;
4271 char *dot_p = NULL;
4272
4273 while (1)
4274 {
4275 mnem_p = mnemonic;
4276 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4277 {
4278 if (*mnem_p == '.')
4279 dot_p = mnem_p;
4280 mnem_p++;
4281 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4282 {
4283 as_bad (_("no such instruction: `%s'"), token_start);
4284 return NULL;
4285 }
4286 l++;
4287 }
4288 if (!is_space_char (*l)
4289 && *l != END_OF_INSN
4290 && (intel_syntax
4291 || (*l != PREFIX_SEPARATOR
4292 && *l != ',')))
4293 {
4294 as_bad (_("invalid character %s in mnemonic"),
4295 output_invalid (*l));
4296 return NULL;
4297 }
4298 if (token_start == l)
4299 {
4300 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4301 as_bad (_("expecting prefix; got nothing"));
4302 else
4303 as_bad (_("expecting mnemonic; got nothing"));
4304 return NULL;
4305 }
4306
4307 /* Look up instruction (or prefix) via hash table. */
4308 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4309
4310 if (*l != END_OF_INSN
4311 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4312 && current_templates
4313 && current_templates->start->opcode_modifier.isprefix)
4314 {
4315 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4316 {
4317 as_bad ((flag_code != CODE_64BIT
4318 ? _("`%s' is only supported in 64-bit mode")
4319 : _("`%s' is not supported in 64-bit mode")),
4320 current_templates->start->name);
4321 return NULL;
4322 }
4323 /* If we are in 16-bit mode, do not allow addr16 or data16.
4324 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4325 if ((current_templates->start->opcode_modifier.size16
4326 || current_templates->start->opcode_modifier.size32)
4327 && flag_code != CODE_64BIT
4328 && (current_templates->start->opcode_modifier.size32
4329 ^ (flag_code == CODE_16BIT)))
4330 {
4331 as_bad (_("redundant %s prefix"),
4332 current_templates->start->name);
4333 return NULL;
4334 }
4335 if (current_templates->start->opcode_length == 0)
4336 {
4337 /* Handle pseudo prefixes. */
4338 switch (current_templates->start->base_opcode)
4339 {
4340 case 0x0:
4341 /* {disp8} */
4342 i.disp_encoding = disp_encoding_8bit;
4343 break;
4344 case 0x1:
4345 /* {disp32} */
4346 i.disp_encoding = disp_encoding_32bit;
4347 break;
4348 case 0x2:
4349 /* {load} */
4350 i.dir_encoding = dir_encoding_load;
4351 break;
4352 case 0x3:
4353 /* {store} */
4354 i.dir_encoding = dir_encoding_store;
4355 break;
4356 case 0x4:
4357 /* {vex2} */
4358 i.vec_encoding = vex_encoding_vex2;
4359 break;
4360 case 0x5:
4361 /* {vex3} */
4362 i.vec_encoding = vex_encoding_vex3;
4363 break;
4364 case 0x6:
4365 /* {evex} */
4366 i.vec_encoding = vex_encoding_evex;
4367 break;
4368 case 0x7:
4369 /* {rex} */
4370 i.rex_encoding = TRUE;
4371 break;
4372 case 0x8:
4373 /* {nooptimize} */
4374 i.no_optimize = TRUE;
4375 break;
4376 default:
4377 abort ();
4378 }
4379 }
4380 else
4381 {
4382 /* Add prefix, checking for repeated prefixes. */
4383 switch (add_prefix (current_templates->start->base_opcode))
4384 {
4385 case PREFIX_EXIST:
4386 return NULL;
4387 case PREFIX_DS:
4388 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4389 i.notrack_prefix = current_templates->start->name;
4390 break;
4391 case PREFIX_REP:
4392 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4393 i.hle_prefix = current_templates->start->name;
4394 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4395 i.bnd_prefix = current_templates->start->name;
4396 else
4397 i.rep_prefix = current_templates->start->name;
4398 break;
4399 default:
4400 break;
4401 }
4402 }
4403 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4404 token_start = ++l;
4405 }
4406 else
4407 break;
4408 }
4409
4410 if (!current_templates)
4411 {
4412 /* Check if we should swap operand or force 32bit displacement in
4413 encoding. */
4414 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4415 i.dir_encoding = dir_encoding_store;
4416 else if (mnem_p - 3 == dot_p
4417 && dot_p[1] == 'd'
4418 && dot_p[2] == '8')
4419 i.disp_encoding = disp_encoding_8bit;
4420 else if (mnem_p - 4 == dot_p
4421 && dot_p[1] == 'd'
4422 && dot_p[2] == '3'
4423 && dot_p[3] == '2')
4424 i.disp_encoding = disp_encoding_32bit;
4425 else
4426 goto check_suffix;
4427 mnem_p = dot_p;
4428 *dot_p = '\0';
4429 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4430 }
4431
4432 if (!current_templates)
4433 {
4434 check_suffix:
4435 /* See if we can get a match by trimming off a suffix. */
4436 switch (mnem_p[-1])
4437 {
4438 case WORD_MNEM_SUFFIX:
4439 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4440 i.suffix = SHORT_MNEM_SUFFIX;
4441 else
4442 /* Fall through. */
4443 case BYTE_MNEM_SUFFIX:
4444 case QWORD_MNEM_SUFFIX:
4445 i.suffix = mnem_p[-1];
4446 mnem_p[-1] = '\0';
4447 current_templates = (const templates *) hash_find (op_hash,
4448 mnemonic);
4449 break;
4450 case SHORT_MNEM_SUFFIX:
4451 case LONG_MNEM_SUFFIX:
4452 if (!intel_syntax)
4453 {
4454 i.suffix = mnem_p[-1];
4455 mnem_p[-1] = '\0';
4456 current_templates = (const templates *) hash_find (op_hash,
4457 mnemonic);
4458 }
4459 break;
4460
4461 /* Intel Syntax. */
4462 case 'd':
4463 if (intel_syntax)
4464 {
4465 if (intel_float_operand (mnemonic) == 1)
4466 i.suffix = SHORT_MNEM_SUFFIX;
4467 else
4468 i.suffix = LONG_MNEM_SUFFIX;
4469 mnem_p[-1] = '\0';
4470 current_templates = (const templates *) hash_find (op_hash,
4471 mnemonic);
4472 }
4473 break;
4474 }
4475 if (!current_templates)
4476 {
4477 as_bad (_("no such instruction: `%s'"), token_start);
4478 return NULL;
4479 }
4480 }
4481
4482 if (current_templates->start->opcode_modifier.jump
4483 || current_templates->start->opcode_modifier.jumpbyte)
4484 {
4485 /* Check for a branch hint. We allow ",pt" and ",pn" for
4486 predict taken and predict not taken respectively.
4487 I'm not sure that branch hints actually do anything on loop
4488 and jcxz insns (JumpByte) for current Pentium4 chips. They
4489 may work in the future and it doesn't hurt to accept them
4490 now. */
4491 if (l[0] == ',' && l[1] == 'p')
4492 {
4493 if (l[2] == 't')
4494 {
4495 if (!add_prefix (DS_PREFIX_OPCODE))
4496 return NULL;
4497 l += 3;
4498 }
4499 else if (l[2] == 'n')
4500 {
4501 if (!add_prefix (CS_PREFIX_OPCODE))
4502 return NULL;
4503 l += 3;
4504 }
4505 }
4506 }
4507 /* Any other comma loses. */
4508 if (*l == ',')
4509 {
4510 as_bad (_("invalid character %s in mnemonic"),
4511 output_invalid (*l));
4512 return NULL;
4513 }
4514
4515 /* Check if instruction is supported on specified architecture. */
4516 supported = 0;
4517 for (t = current_templates->start; t < current_templates->end; ++t)
4518 {
4519 supported |= cpu_flags_match (t);
4520 if (supported == CPU_FLAGS_PERFECT_MATCH)
4521 {
4522 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4523 as_warn (_("use .code16 to ensure correct addressing mode"));
4524
4525 return l;
4526 }
4527 }
4528
4529 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4530 as_bad (flag_code == CODE_64BIT
4531 ? _("`%s' is not supported in 64-bit mode")
4532 : _("`%s' is only supported in 64-bit mode"),
4533 current_templates->start->name);
4534 else
4535 as_bad (_("`%s' is not supported on `%s%s'"),
4536 current_templates->start->name,
4537 cpu_arch_name ? cpu_arch_name : default_arch,
4538 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4539
4540 return NULL;
4541 }
4542
4543 static char *
4544 parse_operands (char *l, const char *mnemonic)
4545 {
4546 char *token_start;
4547
4548 /* 1 if operand is pending after ','. */
4549 unsigned int expecting_operand = 0;
4550
4551 /* Non-zero if operand parens not balanced. */
4552 unsigned int paren_not_balanced;
4553
4554 while (*l != END_OF_INSN)
4555 {
4556 /* Skip optional white space before operand. */
4557 if (is_space_char (*l))
4558 ++l;
4559 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4560 {
4561 as_bad (_("invalid character %s before operand %d"),
4562 output_invalid (*l),
4563 i.operands + 1);
4564 return NULL;
4565 }
4566 token_start = l; /* After white space. */
4567 paren_not_balanced = 0;
4568 while (paren_not_balanced || *l != ',')
4569 {
4570 if (*l == END_OF_INSN)
4571 {
4572 if (paren_not_balanced)
4573 {
4574 if (!intel_syntax)
4575 as_bad (_("unbalanced parenthesis in operand %d."),
4576 i.operands + 1);
4577 else
4578 as_bad (_("unbalanced brackets in operand %d."),
4579 i.operands + 1);
4580 return NULL;
4581 }
4582 else
4583 break; /* we are done */
4584 }
4585 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4586 {
4587 as_bad (_("invalid character %s in operand %d"),
4588 output_invalid (*l),
4589 i.operands + 1);
4590 return NULL;
4591 }
4592 if (!intel_syntax)
4593 {
4594 if (*l == '(')
4595 ++paren_not_balanced;
4596 if (*l == ')')
4597 --paren_not_balanced;
4598 }
4599 else
4600 {
4601 if (*l == '[')
4602 ++paren_not_balanced;
4603 if (*l == ']')
4604 --paren_not_balanced;
4605 }
4606 l++;
4607 }
4608 if (l != token_start)
4609 { /* Yes, we've read in another operand. */
4610 unsigned int operand_ok;
4611 this_operand = i.operands++;
4612 if (i.operands > MAX_OPERANDS)
4613 {
4614 as_bad (_("spurious operands; (%d operands/instruction max)"),
4615 MAX_OPERANDS);
4616 return NULL;
4617 }
4618 i.types[this_operand].bitfield.unspecified = 1;
4619 /* Now parse operand adding info to 'i' as we go along. */
4620 END_STRING_AND_SAVE (l);
4621
4622 if (intel_syntax)
4623 operand_ok =
4624 i386_intel_operand (token_start,
4625 intel_float_operand (mnemonic));
4626 else
4627 operand_ok = i386_att_operand (token_start);
4628
4629 RESTORE_END_STRING (l);
4630 if (!operand_ok)
4631 return NULL;
4632 }
4633 else
4634 {
4635 if (expecting_operand)
4636 {
4637 expecting_operand_after_comma:
4638 as_bad (_("expecting operand after ','; got nothing"));
4639 return NULL;
4640 }
4641 if (*l == ',')
4642 {
4643 as_bad (_("expecting operand before ','; got nothing"));
4644 return NULL;
4645 }
4646 }
4647
4648 /* Now *l must be either ',' or END_OF_INSN. */
4649 if (*l == ',')
4650 {
4651 if (*++l == END_OF_INSN)
4652 {
4653 /* Just skip it, if it's \n complain. */
4654 goto expecting_operand_after_comma;
4655 }
4656 expecting_operand = 1;
4657 }
4658 }
4659 return l;
4660 }
4661
4662 static void
4663 swap_2_operands (int xchg1, int xchg2)
4664 {
4665 union i386_op temp_op;
4666 i386_operand_type temp_type;
4667 enum bfd_reloc_code_real temp_reloc;
4668
4669 temp_type = i.types[xchg2];
4670 i.types[xchg2] = i.types[xchg1];
4671 i.types[xchg1] = temp_type;
4672 temp_op = i.op[xchg2];
4673 i.op[xchg2] = i.op[xchg1];
4674 i.op[xchg1] = temp_op;
4675 temp_reloc = i.reloc[xchg2];
4676 i.reloc[xchg2] = i.reloc[xchg1];
4677 i.reloc[xchg1] = temp_reloc;
4678
4679 if (i.mask)
4680 {
4681 if (i.mask->operand == xchg1)
4682 i.mask->operand = xchg2;
4683 else if (i.mask->operand == xchg2)
4684 i.mask->operand = xchg1;
4685 }
4686 if (i.broadcast)
4687 {
4688 if (i.broadcast->operand == xchg1)
4689 i.broadcast->operand = xchg2;
4690 else if (i.broadcast->operand == xchg2)
4691 i.broadcast->operand = xchg1;
4692 }
4693 if (i.rounding)
4694 {
4695 if (i.rounding->operand == xchg1)
4696 i.rounding->operand = xchg2;
4697 else if (i.rounding->operand == xchg2)
4698 i.rounding->operand = xchg1;
4699 }
4700 }
4701
4702 static void
4703 swap_operands (void)
4704 {
4705 switch (i.operands)
4706 {
4707 case 5:
4708 case 4:
4709 swap_2_operands (1, i.operands - 2);
4710 /* Fall through. */
4711 case 3:
4712 case 2:
4713 swap_2_operands (0, i.operands - 1);
4714 break;
4715 default:
4716 abort ();
4717 }
4718
4719 if (i.mem_operands == 2)
4720 {
4721 const seg_entry *temp_seg;
4722 temp_seg = i.seg[0];
4723 i.seg[0] = i.seg[1];
4724 i.seg[1] = temp_seg;
4725 }
4726 }
4727
4728 /* Try to ensure constant immediates are represented in the smallest
4729 opcode possible. */
4730 static void
4731 optimize_imm (void)
4732 {
4733 char guess_suffix = 0;
4734 int op;
4735
4736 if (i.suffix)
4737 guess_suffix = i.suffix;
4738 else if (i.reg_operands)
4739 {
4740 /* Figure out a suffix from the last register operand specified.
4741 We can't do this properly yet, ie. excluding InOutPortReg,
4742 but the following works for instructions with immediates.
4743 In any case, we can't set i.suffix yet. */
4744 for (op = i.operands; --op >= 0;)
4745 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4746 {
4747 guess_suffix = BYTE_MNEM_SUFFIX;
4748 break;
4749 }
4750 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4751 {
4752 guess_suffix = WORD_MNEM_SUFFIX;
4753 break;
4754 }
4755 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4756 {
4757 guess_suffix = LONG_MNEM_SUFFIX;
4758 break;
4759 }
4760 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4761 {
4762 guess_suffix = QWORD_MNEM_SUFFIX;
4763 break;
4764 }
4765 }
4766 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4767 guess_suffix = WORD_MNEM_SUFFIX;
4768
4769 for (op = i.operands; --op >= 0;)
4770 if (operand_type_check (i.types[op], imm))
4771 {
4772 switch (i.op[op].imms->X_op)
4773 {
4774 case O_constant:
4775 /* If a suffix is given, this operand may be shortened. */
4776 switch (guess_suffix)
4777 {
4778 case LONG_MNEM_SUFFIX:
4779 i.types[op].bitfield.imm32 = 1;
4780 i.types[op].bitfield.imm64 = 1;
4781 break;
4782 case WORD_MNEM_SUFFIX:
4783 i.types[op].bitfield.imm16 = 1;
4784 i.types[op].bitfield.imm32 = 1;
4785 i.types[op].bitfield.imm32s = 1;
4786 i.types[op].bitfield.imm64 = 1;
4787 break;
4788 case BYTE_MNEM_SUFFIX:
4789 i.types[op].bitfield.imm8 = 1;
4790 i.types[op].bitfield.imm8s = 1;
4791 i.types[op].bitfield.imm16 = 1;
4792 i.types[op].bitfield.imm32 = 1;
4793 i.types[op].bitfield.imm32s = 1;
4794 i.types[op].bitfield.imm64 = 1;
4795 break;
4796 }
4797
4798 /* If this operand is at most 16 bits, convert it
4799 to a signed 16 bit number before trying to see
4800 whether it will fit in an even smaller size.
4801 This allows a 16-bit operand such as $0xffe0 to
4802 be recognised as within Imm8S range. */
4803 if ((i.types[op].bitfield.imm16)
4804 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4805 {
4806 i.op[op].imms->X_add_number =
4807 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4808 }
4809 #ifdef BFD64
4810 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4811 if ((i.types[op].bitfield.imm32)
4812 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4813 == 0))
4814 {
4815 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4816 ^ ((offsetT) 1 << 31))
4817 - ((offsetT) 1 << 31));
4818 }
4819 #endif
4820 i.types[op]
4821 = operand_type_or (i.types[op],
4822 smallest_imm_type (i.op[op].imms->X_add_number));
4823
4824 /* We must avoid matching of Imm32 templates when 64bit
4825 only immediate is available. */
4826 if (guess_suffix == QWORD_MNEM_SUFFIX)
4827 i.types[op].bitfield.imm32 = 0;
4828 break;
4829
4830 case O_absent:
4831 case O_register:
4832 abort ();
4833
4834 /* Symbols and expressions. */
4835 default:
4836 /* Convert symbolic operand to proper sizes for matching, but don't
4837 prevent matching a set of insns that only supports sizes other
4838 than those matching the insn suffix. */
4839 {
4840 i386_operand_type mask, allowed;
4841 const insn_template *t;
4842
4843 operand_type_set (&mask, 0);
4844 operand_type_set (&allowed, 0);
4845
4846 for (t = current_templates->start;
4847 t < current_templates->end;
4848 ++t)
4849 allowed = operand_type_or (allowed,
4850 t->operand_types[op]);
4851 switch (guess_suffix)
4852 {
4853 case QWORD_MNEM_SUFFIX:
4854 mask.bitfield.imm64 = 1;
4855 mask.bitfield.imm32s = 1;
4856 break;
4857 case LONG_MNEM_SUFFIX:
4858 mask.bitfield.imm32 = 1;
4859 break;
4860 case WORD_MNEM_SUFFIX:
4861 mask.bitfield.imm16 = 1;
4862 break;
4863 case BYTE_MNEM_SUFFIX:
4864 mask.bitfield.imm8 = 1;
4865 break;
4866 default:
4867 break;
4868 }
4869 allowed = operand_type_and (mask, allowed);
4870 if (!operand_type_all_zero (&allowed))
4871 i.types[op] = operand_type_and (i.types[op], mask);
4872 }
4873 break;
4874 }
4875 }
4876 }
4877
4878 /* Try to use the smallest displacement type too. */
4879 static void
4880 optimize_disp (void)
4881 {
4882 int op;
4883
4884 for (op = i.operands; --op >= 0;)
4885 if (operand_type_check (i.types[op], disp))
4886 {
4887 if (i.op[op].disps->X_op == O_constant)
4888 {
4889 offsetT op_disp = i.op[op].disps->X_add_number;
4890
4891 if (i.types[op].bitfield.disp16
4892 && (op_disp & ~(offsetT) 0xffff) == 0)
4893 {
4894 /* If this operand is at most 16 bits, convert
4895 to a signed 16 bit number and don't use 64bit
4896 displacement. */
4897 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4898 i.types[op].bitfield.disp64 = 0;
4899 }
4900 #ifdef BFD64
4901 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4902 if (i.types[op].bitfield.disp32
4903 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4904 {
4905 /* If this operand is at most 32 bits, convert
4906 to a signed 32 bit number and don't use 64bit
4907 displacement. */
4908 op_disp &= (((offsetT) 2 << 31) - 1);
4909 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4910 i.types[op].bitfield.disp64 = 0;
4911 }
4912 #endif
4913 if (!op_disp && i.types[op].bitfield.baseindex)
4914 {
4915 i.types[op].bitfield.disp8 = 0;
4916 i.types[op].bitfield.disp16 = 0;
4917 i.types[op].bitfield.disp32 = 0;
4918 i.types[op].bitfield.disp32s = 0;
4919 i.types[op].bitfield.disp64 = 0;
4920 i.op[op].disps = 0;
4921 i.disp_operands--;
4922 }
4923 else if (flag_code == CODE_64BIT)
4924 {
4925 if (fits_in_signed_long (op_disp))
4926 {
4927 i.types[op].bitfield.disp64 = 0;
4928 i.types[op].bitfield.disp32s = 1;
4929 }
4930 if (i.prefix[ADDR_PREFIX]
4931 && fits_in_unsigned_long (op_disp))
4932 i.types[op].bitfield.disp32 = 1;
4933 }
4934 if ((i.types[op].bitfield.disp32
4935 || i.types[op].bitfield.disp32s
4936 || i.types[op].bitfield.disp16)
4937 && fits_in_disp8 (op_disp))
4938 i.types[op].bitfield.disp8 = 1;
4939 }
4940 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4941 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4942 {
4943 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4944 i.op[op].disps, 0, i.reloc[op]);
4945 i.types[op].bitfield.disp8 = 0;
4946 i.types[op].bitfield.disp16 = 0;
4947 i.types[op].bitfield.disp32 = 0;
4948 i.types[op].bitfield.disp32s = 0;
4949 i.types[op].bitfield.disp64 = 0;
4950 }
4951 else
4952 /* We only support 64bit displacement on constants. */
4953 i.types[op].bitfield.disp64 = 0;
4954 }
4955 }
4956
4957 /* Check if operands are valid for the instruction. */
4958
4959 static int
4960 check_VecOperands (const insn_template *t)
4961 {
4962 unsigned int op;
4963
4964 /* Without VSIB byte, we can't have a vector register for index. */
4965 if (!t->opcode_modifier.vecsib
4966 && i.index_reg
4967 && (i.index_reg->reg_type.bitfield.xmmword
4968 || i.index_reg->reg_type.bitfield.ymmword
4969 || i.index_reg->reg_type.bitfield.zmmword))
4970 {
4971 i.error = unsupported_vector_index_register;
4972 return 1;
4973 }
4974
4975 /* Check if default mask is allowed. */
4976 if (t->opcode_modifier.nodefmask
4977 && (!i.mask || i.mask->mask->reg_num == 0))
4978 {
4979 i.error = no_default_mask;
4980 return 1;
4981 }
4982
4983 /* For VSIB byte, we need a vector register for index, and all vector
4984 registers must be distinct. */
4985 if (t->opcode_modifier.vecsib)
4986 {
4987 if (!i.index_reg
4988 || !((t->opcode_modifier.vecsib == VecSIB128
4989 && i.index_reg->reg_type.bitfield.xmmword)
4990 || (t->opcode_modifier.vecsib == VecSIB256
4991 && i.index_reg->reg_type.bitfield.ymmword)
4992 || (t->opcode_modifier.vecsib == VecSIB512
4993 && i.index_reg->reg_type.bitfield.zmmword)))
4994 {
4995 i.error = invalid_vsib_address;
4996 return 1;
4997 }
4998
4999 gas_assert (i.reg_operands == 2 || i.mask);
5000 if (i.reg_operands == 2 && !i.mask)
5001 {
5002 gas_assert (i.types[0].bitfield.regsimd);
5003 gas_assert (i.types[0].bitfield.xmmword
5004 || i.types[0].bitfield.ymmword);
5005 gas_assert (i.types[2].bitfield.regsimd);
5006 gas_assert (i.types[2].bitfield.xmmword
5007 || i.types[2].bitfield.ymmword);
5008 if (operand_check == check_none)
5009 return 0;
5010 if (register_number (i.op[0].regs)
5011 != register_number (i.index_reg)
5012 && register_number (i.op[2].regs)
5013 != register_number (i.index_reg)
5014 && register_number (i.op[0].regs)
5015 != register_number (i.op[2].regs))
5016 return 0;
5017 if (operand_check == check_error)
5018 {
5019 i.error = invalid_vector_register_set;
5020 return 1;
5021 }
5022 as_warn (_("mask, index, and destination registers should be distinct"));
5023 }
5024 else if (i.reg_operands == 1 && i.mask)
5025 {
5026 if (i.types[1].bitfield.regsimd
5027 && (i.types[1].bitfield.xmmword
5028 || i.types[1].bitfield.ymmword
5029 || i.types[1].bitfield.zmmword)
5030 && (register_number (i.op[1].regs)
5031 == register_number (i.index_reg)))
5032 {
5033 if (operand_check == check_error)
5034 {
5035 i.error = invalid_vector_register_set;
5036 return 1;
5037 }
5038 if (operand_check != check_none)
5039 as_warn (_("index and destination registers should be distinct"));
5040 }
5041 }
5042 }
5043
5044 /* Check if broadcast is supported by the instruction and is applied
5045 to the memory operand. */
5046 if (i.broadcast)
5047 {
5048 int broadcasted_opnd_size;
5049
5050 /* Check if specified broadcast is supported in this instruction,
5051 and it's applied to memory operand of DWORD or QWORD type,
5052 depending on VecESize. */
5053 if (i.broadcast->type != t->opcode_modifier.broadcast
5054 || !i.types[i.broadcast->operand].bitfield.mem
5055 || (t->opcode_modifier.vecesize == 0
5056 && !i.types[i.broadcast->operand].bitfield.dword
5057 && !i.types[i.broadcast->operand].bitfield.unspecified)
5058 || (t->opcode_modifier.vecesize == 1
5059 && !i.types[i.broadcast->operand].bitfield.qword
5060 && !i.types[i.broadcast->operand].bitfield.unspecified))
5061 goto bad_broadcast;
5062
5063 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5064 if (i.broadcast->type == BROADCAST_1TO16)
5065 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5066 else if (i.broadcast->type == BROADCAST_1TO8)
5067 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5068 else if (i.broadcast->type == BROADCAST_1TO4)
5069 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5070 else if (i.broadcast->type == BROADCAST_1TO2)
5071 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5072 else
5073 goto bad_broadcast;
5074
5075 if ((broadcasted_opnd_size == 256
5076 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5077 || (broadcasted_opnd_size == 512
5078 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5079 {
5080 bad_broadcast:
5081 i.error = unsupported_broadcast;
5082 return 1;
5083 }
5084 }
5085 /* If broadcast is supported in this instruction, we need to check if
5086 operand of one-element size isn't specified without broadcast. */
5087 else if (t->opcode_modifier.broadcast && i.mem_operands)
5088 {
5089 /* Find memory operand. */
5090 for (op = 0; op < i.operands; op++)
5091 if (operand_type_check (i.types[op], anymem))
5092 break;
5093 gas_assert (op < i.operands);
5094 /* Check size of the memory operand. */
5095 if ((t->opcode_modifier.vecesize == 0
5096 && i.types[op].bitfield.dword)
5097 || (t->opcode_modifier.vecesize == 1
5098 && i.types[op].bitfield.qword))
5099 {
5100 i.error = broadcast_needed;
5101 return 1;
5102 }
5103 }
5104
5105 /* Check if requested masking is supported. */
5106 if (i.mask
5107 && (!t->opcode_modifier.masking
5108 || (i.mask->zeroing
5109 && t->opcode_modifier.masking == MERGING_MASKING)))
5110 {
5111 i.error = unsupported_masking;
5112 return 1;
5113 }
5114
5115 /* Check if masking is applied to dest operand. */
5116 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5117 {
5118 i.error = mask_not_on_destination;
5119 return 1;
5120 }
5121
5122 /* Check RC/SAE. */
5123 if (i.rounding)
5124 {
5125 if ((i.rounding->type != saeonly
5126 && !t->opcode_modifier.staticrounding)
5127 || (i.rounding->type == saeonly
5128 && (t->opcode_modifier.staticrounding
5129 || !t->opcode_modifier.sae)))
5130 {
5131 i.error = unsupported_rc_sae;
5132 return 1;
5133 }
5134 /* If the instruction has several immediate operands and one of
5135 them is rounding, the rounding operand should be the last
5136 immediate operand. */
5137 if (i.imm_operands > 1
5138 && i.rounding->operand != (int) (i.imm_operands - 1))
5139 {
5140 i.error = rc_sae_operand_not_last_imm;
5141 return 1;
5142 }
5143 }
5144
5145 /* Check vector Disp8 operand. */
5146 if (t->opcode_modifier.disp8memshift
5147 && i.disp_encoding != disp_encoding_32bit)
5148 {
5149 if (i.broadcast)
5150 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5151 else
5152 i.memshift = t->opcode_modifier.disp8memshift;
5153
5154 for (op = 0; op < i.operands; op++)
5155 if (operand_type_check (i.types[op], disp)
5156 && i.op[op].disps->X_op == O_constant)
5157 {
5158 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5159 {
5160 i.types[op].bitfield.disp8 = 1;
5161 return 0;
5162 }
5163 i.types[op].bitfield.disp8 = 0;
5164 }
5165 }
5166
5167 i.memshift = 0;
5168
5169 return 0;
5170 }
5171
5172 /* Check if operands are valid for the instruction. Update VEX
5173 operand types. */
5174
5175 static int
5176 VEX_check_operands (const insn_template *t)
5177 {
5178 if (i.vec_encoding == vex_encoding_evex)
5179 {
5180 /* This instruction must be encoded with EVEX prefix. */
5181 if (!is_evex_encoding (t))
5182 {
5183 i.error = unsupported;
5184 return 1;
5185 }
5186 return 0;
5187 }
5188
5189 if (!t->opcode_modifier.vex)
5190 {
5191 /* This instruction template doesn't have VEX prefix. */
5192 if (i.vec_encoding != vex_encoding_default)
5193 {
5194 i.error = unsupported;
5195 return 1;
5196 }
5197 return 0;
5198 }
5199
5200 /* Only check VEX_Imm4, which must be the first operand. */
5201 if (t->operand_types[0].bitfield.vec_imm4)
5202 {
5203 if (i.op[0].imms->X_op != O_constant
5204 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5205 {
5206 i.error = bad_imm4;
5207 return 1;
5208 }
5209
5210 /* Turn off Imm8 so that update_imm won't complain. */
5211 i.types[0] = vec_imm4;
5212 }
5213
5214 return 0;
5215 }
5216
5217 static const insn_template *
5218 match_template (char mnem_suffix)
5219 {
5220 /* Points to template once we've found it. */
5221 const insn_template *t;
5222 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5223 i386_operand_type overlap4;
5224 unsigned int found_reverse_match;
5225 i386_opcode_modifier suffix_check, mnemsuf_check;
5226 i386_operand_type operand_types [MAX_OPERANDS];
5227 int addr_prefix_disp;
5228 unsigned int j;
5229 unsigned int found_cpu_match;
5230 unsigned int check_register;
5231 enum i386_error specific_error = 0;
5232
5233 #if MAX_OPERANDS != 5
5234 # error "MAX_OPERANDS must be 5."
5235 #endif
5236
5237 found_reverse_match = 0;
5238 addr_prefix_disp = -1;
5239
5240 memset (&suffix_check, 0, sizeof (suffix_check));
5241 if (i.suffix == BYTE_MNEM_SUFFIX)
5242 suffix_check.no_bsuf = 1;
5243 else if (i.suffix == WORD_MNEM_SUFFIX)
5244 suffix_check.no_wsuf = 1;
5245 else if (i.suffix == SHORT_MNEM_SUFFIX)
5246 suffix_check.no_ssuf = 1;
5247 else if (i.suffix == LONG_MNEM_SUFFIX)
5248 suffix_check.no_lsuf = 1;
5249 else if (i.suffix == QWORD_MNEM_SUFFIX)
5250 suffix_check.no_qsuf = 1;
5251 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5252 suffix_check.no_ldsuf = 1;
5253
5254 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5255 if (intel_syntax)
5256 {
5257 switch (mnem_suffix)
5258 {
5259 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5260 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5261 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5262 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5263 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5264 }
5265 }
5266
5267 /* Must have right number of operands. */
5268 i.error = number_of_operands_mismatch;
5269
5270 for (t = current_templates->start; t < current_templates->end; t++)
5271 {
5272 addr_prefix_disp = -1;
5273
5274 if (i.operands != t->operands)
5275 continue;
5276
5277 /* Check processor support. */
5278 i.error = unsupported;
5279 found_cpu_match = (cpu_flags_match (t)
5280 == CPU_FLAGS_PERFECT_MATCH);
5281 if (!found_cpu_match)
5282 continue;
5283
5284 /* Check AT&T mnemonic. */
5285 i.error = unsupported_with_intel_mnemonic;
5286 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5287 continue;
5288
5289 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5290 i.error = unsupported_syntax;
5291 if ((intel_syntax && t->opcode_modifier.attsyntax)
5292 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5293 || (intel64 && t->opcode_modifier.amd64)
5294 || (!intel64 && t->opcode_modifier.intel64))
5295 continue;
5296
5297 /* Check the suffix, except for some instructions in intel mode. */
5298 i.error = invalid_instruction_suffix;
5299 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5300 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5301 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5302 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5303 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5304 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5305 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5306 continue;
5307 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5308 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5309 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5310 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5311 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5312 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5313 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5314 continue;
5315
5316 if (!operand_size_match (t))
5317 continue;
5318
5319 for (j = 0; j < MAX_OPERANDS; j++)
5320 operand_types[j] = t->operand_types[j];
5321
5322 /* In general, don't allow 64-bit operands in 32-bit mode. */
5323 if (i.suffix == QWORD_MNEM_SUFFIX
5324 && flag_code != CODE_64BIT
5325 && (intel_syntax
5326 ? (!t->opcode_modifier.ignoresize
5327 && !intel_float_operand (t->name))
5328 : intel_float_operand (t->name) != 2)
5329 && ((!operand_types[0].bitfield.regmmx
5330 && !operand_types[0].bitfield.regsimd)
5331 || (!operand_types[t->operands > 1].bitfield.regmmx
5332 && !operand_types[t->operands > 1].bitfield.regsimd))
5333 && (t->base_opcode != 0x0fc7
5334 || t->extension_opcode != 1 /* cmpxchg8b */))
5335 continue;
5336
5337 /* In general, don't allow 32-bit operands on pre-386. */
5338 else if (i.suffix == LONG_MNEM_SUFFIX
5339 && !cpu_arch_flags.bitfield.cpui386
5340 && (intel_syntax
5341 ? (!t->opcode_modifier.ignoresize
5342 && !intel_float_operand (t->name))
5343 : intel_float_operand (t->name) != 2)
5344 && ((!operand_types[0].bitfield.regmmx
5345 && !operand_types[0].bitfield.regsimd)
5346 || (!operand_types[t->operands > 1].bitfield.regmmx
5347 && !operand_types[t->operands > 1].bitfield.regsimd)))
5348 continue;
5349
5350 /* Do not verify operands when there are none. */
5351 else
5352 {
5353 if (!t->operands)
5354 /* We've found a match; break out of loop. */
5355 break;
5356 }
5357
5358 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5359 into Disp32/Disp16/Disp32 operand. */
5360 if (i.prefix[ADDR_PREFIX] != 0)
5361 {
5362 /* There should be only one Disp operand. */
5363 switch (flag_code)
5364 {
5365 case CODE_16BIT:
5366 for (j = 0; j < MAX_OPERANDS; j++)
5367 {
5368 if (operand_types[j].bitfield.disp16)
5369 {
5370 addr_prefix_disp = j;
5371 operand_types[j].bitfield.disp32 = 1;
5372 operand_types[j].bitfield.disp16 = 0;
5373 break;
5374 }
5375 }
5376 break;
5377 case CODE_32BIT:
5378 for (j = 0; j < MAX_OPERANDS; j++)
5379 {
5380 if (operand_types[j].bitfield.disp32)
5381 {
5382 addr_prefix_disp = j;
5383 operand_types[j].bitfield.disp32 = 0;
5384 operand_types[j].bitfield.disp16 = 1;
5385 break;
5386 }
5387 }
5388 break;
5389 case CODE_64BIT:
5390 for (j = 0; j < MAX_OPERANDS; j++)
5391 {
5392 if (operand_types[j].bitfield.disp64)
5393 {
5394 addr_prefix_disp = j;
5395 operand_types[j].bitfield.disp64 = 0;
5396 operand_types[j].bitfield.disp32 = 1;
5397 break;
5398 }
5399 }
5400 break;
5401 }
5402 }
5403
5404 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5405 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5406 continue;
5407
5408 /* We check register size if needed. */
5409 check_register = t->opcode_modifier.checkregsize;
5410 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5411 switch (t->operands)
5412 {
5413 case 1:
5414 if (!operand_type_match (overlap0, i.types[0]))
5415 continue;
5416 break;
5417 case 2:
5418 /* xchg %eax, %eax is a special case. It is an alias for nop
5419 only in 32bit mode and we can use opcode 0x90. In 64bit
5420 mode, we can't use 0x90 for xchg %eax, %eax since it should
5421 zero-extend %eax to %rax. */
5422 if (flag_code == CODE_64BIT
5423 && t->base_opcode == 0x90
5424 && operand_type_equal (&i.types [0], &acc32)
5425 && operand_type_equal (&i.types [1], &acc32))
5426 continue;
5427 /* If we want store form, we reverse direction of operands. */
5428 if (i.dir_encoding == dir_encoding_store
5429 && t->opcode_modifier.d)
5430 goto check_reverse;
5431 /* Fall through. */
5432
5433 case 3:
5434 /* If we want store form, we skip the current load. */
5435 if (i.dir_encoding == dir_encoding_store
5436 && i.mem_operands == 0
5437 && t->opcode_modifier.load)
5438 continue;
5439 /* Fall through. */
5440 case 4:
5441 case 5:
5442 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5443 if (!operand_type_match (overlap0, i.types[0])
5444 || !operand_type_match (overlap1, i.types[1])
5445 || (check_register
5446 && !operand_type_register_match (i.types[0],
5447 operand_types[0],
5448 i.types[1],
5449 operand_types[1])))
5450 {
5451 /* Check if other direction is valid ... */
5452 if (!t->opcode_modifier.d)
5453 continue;
5454
5455 check_reverse:
5456 /* Try reversing direction of operands. */
5457 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5458 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5459 if (!operand_type_match (overlap0, i.types[0])
5460 || !operand_type_match (overlap1, i.types[1])
5461 || (check_register
5462 && !operand_type_register_match (i.types[0],
5463 operand_types[1],
5464 i.types[1],
5465 operand_types[0])))
5466 {
5467 /* Does not match either direction. */
5468 continue;
5469 }
5470 /* found_reverse_match holds which of D or FloatR
5471 we've found. */
5472 if (!t->opcode_modifier.d)
5473 found_reverse_match = 0;
5474 else if (operand_types[0].bitfield.tbyte)
5475 found_reverse_match = Opcode_FloatD;
5476 else
5477 found_reverse_match = Opcode_D;
5478 if (t->opcode_modifier.floatr)
5479 found_reverse_match |= Opcode_FloatR;
5480 }
5481 else
5482 {
5483 /* Found a forward 2 operand match here. */
5484 switch (t->operands)
5485 {
5486 case 5:
5487 overlap4 = operand_type_and (i.types[4],
5488 operand_types[4]);
5489 /* Fall through. */
5490 case 4:
5491 overlap3 = operand_type_and (i.types[3],
5492 operand_types[3]);
5493 /* Fall through. */
5494 case 3:
5495 overlap2 = operand_type_and (i.types[2],
5496 operand_types[2]);
5497 break;
5498 }
5499
5500 switch (t->operands)
5501 {
5502 case 5:
5503 if (!operand_type_match (overlap4, i.types[4])
5504 || !operand_type_register_match (i.types[3],
5505 operand_types[3],
5506 i.types[4],
5507 operand_types[4]))
5508 continue;
5509 /* Fall through. */
5510 case 4:
5511 if (!operand_type_match (overlap3, i.types[3])
5512 || (check_register
5513 && (!operand_type_register_match (i.types[1],
5514 operand_types[1],
5515 i.types[3],
5516 operand_types[3])
5517 || !operand_type_register_match (i.types[2],
5518 operand_types[2],
5519 i.types[3],
5520 operand_types[3]))))
5521 continue;
5522 /* Fall through. */
5523 case 3:
5524 /* Here we make use of the fact that there are no
5525 reverse match 3 operand instructions. */
5526 if (!operand_type_match (overlap2, i.types[2])
5527 || (check_register
5528 && (!operand_type_register_match (i.types[0],
5529 operand_types[0],
5530 i.types[2],
5531 operand_types[2])
5532 || !operand_type_register_match (i.types[1],
5533 operand_types[1],
5534 i.types[2],
5535 operand_types[2]))))
5536 continue;
5537 break;
5538 }
5539 }
5540 /* Found either forward/reverse 2, 3 or 4 operand match here:
5541 slip through to break. */
5542 }
5543 if (!found_cpu_match)
5544 {
5545 found_reverse_match = 0;
5546 continue;
5547 }
5548
5549 /* Check if vector and VEX operands are valid. */
5550 if (check_VecOperands (t) || VEX_check_operands (t))
5551 {
5552 specific_error = i.error;
5553 continue;
5554 }
5555
5556 /* We've found a match; break out of loop. */
5557 break;
5558 }
5559
5560 if (t == current_templates->end)
5561 {
5562 /* We found no match. */
5563 const char *err_msg;
5564 switch (specific_error ? specific_error : i.error)
5565 {
5566 default:
5567 abort ();
5568 case operand_size_mismatch:
5569 err_msg = _("operand size mismatch");
5570 break;
5571 case operand_type_mismatch:
5572 err_msg = _("operand type mismatch");
5573 break;
5574 case register_type_mismatch:
5575 err_msg = _("register type mismatch");
5576 break;
5577 case number_of_operands_mismatch:
5578 err_msg = _("number of operands mismatch");
5579 break;
5580 case invalid_instruction_suffix:
5581 err_msg = _("invalid instruction suffix");
5582 break;
5583 case bad_imm4:
5584 err_msg = _("constant doesn't fit in 4 bits");
5585 break;
5586 case unsupported_with_intel_mnemonic:
5587 err_msg = _("unsupported with Intel mnemonic");
5588 break;
5589 case unsupported_syntax:
5590 err_msg = _("unsupported syntax");
5591 break;
5592 case unsupported:
5593 as_bad (_("unsupported instruction `%s'"),
5594 current_templates->start->name);
5595 return NULL;
5596 case invalid_vsib_address:
5597 err_msg = _("invalid VSIB address");
5598 break;
5599 case invalid_vector_register_set:
5600 err_msg = _("mask, index, and destination registers must be distinct");
5601 break;
5602 case unsupported_vector_index_register:
5603 err_msg = _("unsupported vector index register");
5604 break;
5605 case unsupported_broadcast:
5606 err_msg = _("unsupported broadcast");
5607 break;
5608 case broadcast_not_on_src_operand:
5609 err_msg = _("broadcast not on source memory operand");
5610 break;
5611 case broadcast_needed:
5612 err_msg = _("broadcast is needed for operand of such type");
5613 break;
5614 case unsupported_masking:
5615 err_msg = _("unsupported masking");
5616 break;
5617 case mask_not_on_destination:
5618 err_msg = _("mask not on destination operand");
5619 break;
5620 case no_default_mask:
5621 err_msg = _("default mask isn't allowed");
5622 break;
5623 case unsupported_rc_sae:
5624 err_msg = _("unsupported static rounding/sae");
5625 break;
5626 case rc_sae_operand_not_last_imm:
5627 if (intel_syntax)
5628 err_msg = _("RC/SAE operand must precede immediate operands");
5629 else
5630 err_msg = _("RC/SAE operand must follow immediate operands");
5631 break;
5632 case invalid_register_operand:
5633 err_msg = _("invalid register operand");
5634 break;
5635 }
5636 as_bad (_("%s for `%s'"), err_msg,
5637 current_templates->start->name);
5638 return NULL;
5639 }
5640
5641 if (!quiet_warnings)
5642 {
5643 if (!intel_syntax
5644 && (i.types[0].bitfield.jumpabsolute
5645 != operand_types[0].bitfield.jumpabsolute))
5646 {
5647 as_warn (_("indirect %s without `*'"), t->name);
5648 }
5649
5650 if (t->opcode_modifier.isprefix
5651 && t->opcode_modifier.ignoresize)
5652 {
5653 /* Warn them that a data or address size prefix doesn't
5654 affect assembly of the next line of code. */
5655 as_warn (_("stand-alone `%s' prefix"), t->name);
5656 }
5657 }
5658
5659 /* Copy the template we found. */
5660 i.tm = *t;
5661
5662 if (addr_prefix_disp != -1)
5663 i.tm.operand_types[addr_prefix_disp]
5664 = operand_types[addr_prefix_disp];
5665
5666 if (found_reverse_match)
5667 {
5668 /* If we found a reverse match we must alter the opcode
5669 direction bit. found_reverse_match holds bits to change
5670 (different for int & float insns). */
5671
5672 i.tm.base_opcode ^= found_reverse_match;
5673
5674 i.tm.operand_types[0] = operand_types[1];
5675 i.tm.operand_types[1] = operand_types[0];
5676 }
5677
5678 return t;
5679 }
5680
5681 static int
5682 check_string (void)
5683 {
5684 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5685 if (i.tm.operand_types[mem_op].bitfield.esseg)
5686 {
5687 if (i.seg[0] != NULL && i.seg[0] != &es)
5688 {
5689 as_bad (_("`%s' operand %d must use `%ses' segment"),
5690 i.tm.name,
5691 mem_op + 1,
5692 register_prefix);
5693 return 0;
5694 }
5695 /* There's only ever one segment override allowed per instruction.
5696 This instruction possibly has a legal segment override on the
5697 second operand, so copy the segment to where non-string
5698 instructions store it, allowing common code. */
5699 i.seg[0] = i.seg[1];
5700 }
5701 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5702 {
5703 if (i.seg[1] != NULL && i.seg[1] != &es)
5704 {
5705 as_bad (_("`%s' operand %d must use `%ses' segment"),
5706 i.tm.name,
5707 mem_op + 2,
5708 register_prefix);
5709 return 0;
5710 }
5711 }
5712 return 1;
5713 }
5714
5715 static int
5716 process_suffix (void)
5717 {
5718 /* If matched instruction specifies an explicit instruction mnemonic
5719 suffix, use it. */
5720 if (i.tm.opcode_modifier.size16)
5721 i.suffix = WORD_MNEM_SUFFIX;
5722 else if (i.tm.opcode_modifier.size32)
5723 i.suffix = LONG_MNEM_SUFFIX;
5724 else if (i.tm.opcode_modifier.size64)
5725 i.suffix = QWORD_MNEM_SUFFIX;
5726 else if (i.reg_operands)
5727 {
5728 /* If there's no instruction mnemonic suffix we try to invent one
5729 based on register operands. */
5730 if (!i.suffix)
5731 {
5732 /* We take i.suffix from the last register operand specified,
5733 Destination register type is more significant than source
5734 register type. crc32 in SSE4.2 prefers source register
5735 type. */
5736 if (i.tm.base_opcode == 0xf20f38f1)
5737 {
5738 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5739 i.suffix = WORD_MNEM_SUFFIX;
5740 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5741 i.suffix = LONG_MNEM_SUFFIX;
5742 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5743 i.suffix = QWORD_MNEM_SUFFIX;
5744 }
5745 else if (i.tm.base_opcode == 0xf20f38f0)
5746 {
5747 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5748 i.suffix = BYTE_MNEM_SUFFIX;
5749 }
5750
5751 if (!i.suffix)
5752 {
5753 int op;
5754
5755 if (i.tm.base_opcode == 0xf20f38f1
5756 || i.tm.base_opcode == 0xf20f38f0)
5757 {
5758 /* We have to know the operand size for crc32. */
5759 as_bad (_("ambiguous memory operand size for `%s`"),
5760 i.tm.name);
5761 return 0;
5762 }
5763
5764 for (op = i.operands; --op >= 0;)
5765 if (!i.tm.operand_types[op].bitfield.inoutportreg
5766 && !i.tm.operand_types[op].bitfield.shiftcount)
5767 {
5768 if (!i.types[op].bitfield.reg)
5769 continue;
5770 if (i.types[op].bitfield.byte)
5771 i.suffix = BYTE_MNEM_SUFFIX;
5772 else if (i.types[op].bitfield.word)
5773 i.suffix = WORD_MNEM_SUFFIX;
5774 else if (i.types[op].bitfield.dword)
5775 i.suffix = LONG_MNEM_SUFFIX;
5776 else if (i.types[op].bitfield.qword)
5777 i.suffix = QWORD_MNEM_SUFFIX;
5778 else
5779 continue;
5780 break;
5781 }
5782 }
5783 }
5784 else if (i.suffix == BYTE_MNEM_SUFFIX)
5785 {
5786 if (intel_syntax
5787 && i.tm.opcode_modifier.ignoresize
5788 && i.tm.opcode_modifier.no_bsuf)
5789 i.suffix = 0;
5790 else if (!check_byte_reg ())
5791 return 0;
5792 }
5793 else if (i.suffix == LONG_MNEM_SUFFIX)
5794 {
5795 if (intel_syntax
5796 && i.tm.opcode_modifier.ignoresize
5797 && i.tm.opcode_modifier.no_lsuf)
5798 i.suffix = 0;
5799 else if (!check_long_reg ())
5800 return 0;
5801 }
5802 else if (i.suffix == QWORD_MNEM_SUFFIX)
5803 {
5804 if (intel_syntax
5805 && i.tm.opcode_modifier.ignoresize
5806 && i.tm.opcode_modifier.no_qsuf)
5807 i.suffix = 0;
5808 else if (!check_qword_reg ())
5809 return 0;
5810 }
5811 else if (i.suffix == WORD_MNEM_SUFFIX)
5812 {
5813 if (intel_syntax
5814 && i.tm.opcode_modifier.ignoresize
5815 && i.tm.opcode_modifier.no_wsuf)
5816 i.suffix = 0;
5817 else if (!check_word_reg ())
5818 return 0;
5819 }
5820 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5821 /* Do nothing if the instruction is going to ignore the prefix. */
5822 ;
5823 else
5824 abort ();
5825 }
5826 else if (i.tm.opcode_modifier.defaultsize
5827 && !i.suffix
5828 /* exclude fldenv/frstor/fsave/fstenv */
5829 && i.tm.opcode_modifier.no_ssuf)
5830 {
5831 i.suffix = stackop_size;
5832 }
5833 else if (intel_syntax
5834 && !i.suffix
5835 && (i.tm.operand_types[0].bitfield.jumpabsolute
5836 || i.tm.opcode_modifier.jumpbyte
5837 || i.tm.opcode_modifier.jumpintersegment
5838 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5839 && i.tm.extension_opcode <= 3)))
5840 {
5841 switch (flag_code)
5842 {
5843 case CODE_64BIT:
5844 if (!i.tm.opcode_modifier.no_qsuf)
5845 {
5846 i.suffix = QWORD_MNEM_SUFFIX;
5847 break;
5848 }
5849 /* Fall through. */
5850 case CODE_32BIT:
5851 if (!i.tm.opcode_modifier.no_lsuf)
5852 i.suffix = LONG_MNEM_SUFFIX;
5853 break;
5854 case CODE_16BIT:
5855 if (!i.tm.opcode_modifier.no_wsuf)
5856 i.suffix = WORD_MNEM_SUFFIX;
5857 break;
5858 }
5859 }
5860
5861 if (!i.suffix)
5862 {
5863 if (!intel_syntax)
5864 {
5865 if (i.tm.opcode_modifier.w)
5866 {
5867 as_bad (_("no instruction mnemonic suffix given and "
5868 "no register operands; can't size instruction"));
5869 return 0;
5870 }
5871 }
5872 else
5873 {
5874 unsigned int suffixes;
5875
5876 suffixes = !i.tm.opcode_modifier.no_bsuf;
5877 if (!i.tm.opcode_modifier.no_wsuf)
5878 suffixes |= 1 << 1;
5879 if (!i.tm.opcode_modifier.no_lsuf)
5880 suffixes |= 1 << 2;
5881 if (!i.tm.opcode_modifier.no_ldsuf)
5882 suffixes |= 1 << 3;
5883 if (!i.tm.opcode_modifier.no_ssuf)
5884 suffixes |= 1 << 4;
5885 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5886 suffixes |= 1 << 5;
5887
5888 /* There are more than suffix matches. */
5889 if (i.tm.opcode_modifier.w
5890 || ((suffixes & (suffixes - 1))
5891 && !i.tm.opcode_modifier.defaultsize
5892 && !i.tm.opcode_modifier.ignoresize))
5893 {
5894 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5895 return 0;
5896 }
5897 }
5898 }
5899
5900 /* Change the opcode based on the operand size given by i.suffix. */
5901 switch (i.suffix)
5902 {
5903 /* Size floating point instruction. */
5904 case LONG_MNEM_SUFFIX:
5905 if (i.tm.opcode_modifier.floatmf)
5906 {
5907 i.tm.base_opcode ^= 4;
5908 break;
5909 }
5910 /* fall through */
5911 case WORD_MNEM_SUFFIX:
5912 case QWORD_MNEM_SUFFIX:
5913 /* It's not a byte, select word/dword operation. */
5914 if (i.tm.opcode_modifier.w)
5915 {
5916 if (i.tm.opcode_modifier.shortform)
5917 i.tm.base_opcode |= 8;
5918 else
5919 i.tm.base_opcode |= 1;
5920 }
5921 /* fall through */
5922 case SHORT_MNEM_SUFFIX:
5923 /* Now select between word & dword operations via the operand
5924 size prefix, except for instructions that will ignore this
5925 prefix anyway. */
5926 if (i.tm.opcode_modifier.addrprefixop0)
5927 {
5928 /* The address size override prefix changes the size of the
5929 first operand. */
5930 if ((flag_code == CODE_32BIT
5931 && i.op->regs[0].reg_type.bitfield.word)
5932 || (flag_code != CODE_32BIT
5933 && i.op->regs[0].reg_type.bitfield.dword))
5934 if (!add_prefix (ADDR_PREFIX_OPCODE))
5935 return 0;
5936 }
5937 else if (i.suffix != QWORD_MNEM_SUFFIX
5938 && !i.tm.opcode_modifier.ignoresize
5939 && !i.tm.opcode_modifier.floatmf
5940 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5941 || (flag_code == CODE_64BIT
5942 && i.tm.opcode_modifier.jumpbyte)))
5943 {
5944 unsigned int prefix = DATA_PREFIX_OPCODE;
5945
5946 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5947 prefix = ADDR_PREFIX_OPCODE;
5948
5949 if (!add_prefix (prefix))
5950 return 0;
5951 }
5952
5953 /* Set mode64 for an operand. */
5954 if (i.suffix == QWORD_MNEM_SUFFIX
5955 && flag_code == CODE_64BIT
5956 && !i.tm.opcode_modifier.norex64
5957 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5958 need rex64. */
5959 && ! (i.operands == 2
5960 && i.tm.base_opcode == 0x90
5961 && i.tm.extension_opcode == None
5962 && operand_type_equal (&i.types [0], &acc64)
5963 && operand_type_equal (&i.types [1], &acc64)))
5964 i.rex |= REX_W;
5965
5966 break;
5967 }
5968
5969 return 1;
5970 }
5971
5972 static int
5973 check_byte_reg (void)
5974 {
5975 int op;
5976
5977 for (op = i.operands; --op >= 0;)
5978 {
5979 /* Skip non-register operands. */
5980 if (!i.types[op].bitfield.reg)
5981 continue;
5982
5983 /* If this is an eight bit register, it's OK. If it's the 16 or
5984 32 bit version of an eight bit register, we will just use the
5985 low portion, and that's OK too. */
5986 if (i.types[op].bitfield.byte)
5987 continue;
5988
5989 /* I/O port address operands are OK too. */
5990 if (i.tm.operand_types[op].bitfield.inoutportreg)
5991 continue;
5992
5993 /* crc32 doesn't generate this warning. */
5994 if (i.tm.base_opcode == 0xf20f38f0)
5995 continue;
5996
5997 if ((i.types[op].bitfield.word
5998 || i.types[op].bitfield.dword
5999 || i.types[op].bitfield.qword)
6000 && i.op[op].regs->reg_num < 4
6001 /* Prohibit these changes in 64bit mode, since the lowering
6002 would be more complicated. */
6003 && flag_code != CODE_64BIT)
6004 {
6005 #if REGISTER_WARNINGS
6006 if (!quiet_warnings)
6007 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6008 register_prefix,
6009 (i.op[op].regs + (i.types[op].bitfield.word
6010 ? REGNAM_AL - REGNAM_AX
6011 : REGNAM_AL - REGNAM_EAX))->reg_name,
6012 register_prefix,
6013 i.op[op].regs->reg_name,
6014 i.suffix);
6015 #endif
6016 continue;
6017 }
6018 /* Any other register is bad. */
6019 if (i.types[op].bitfield.reg
6020 || i.types[op].bitfield.regmmx
6021 || i.types[op].bitfield.regsimd
6022 || i.types[op].bitfield.sreg2
6023 || i.types[op].bitfield.sreg3
6024 || i.types[op].bitfield.control
6025 || i.types[op].bitfield.debug
6026 || i.types[op].bitfield.test)
6027 {
6028 as_bad (_("`%s%s' not allowed with `%s%c'"),
6029 register_prefix,
6030 i.op[op].regs->reg_name,
6031 i.tm.name,
6032 i.suffix);
6033 return 0;
6034 }
6035 }
6036 return 1;
6037 }
6038
6039 static int
6040 check_long_reg (void)
6041 {
6042 int op;
6043
6044 for (op = i.operands; --op >= 0;)
6045 /* Skip non-register operands. */
6046 if (!i.types[op].bitfield.reg)
6047 continue;
6048 /* Reject eight bit registers, except where the template requires
6049 them. (eg. movzb) */
6050 else if (i.types[op].bitfield.byte
6051 && (i.tm.operand_types[op].bitfield.reg
6052 || i.tm.operand_types[op].bitfield.acc)
6053 && (i.tm.operand_types[op].bitfield.word
6054 || i.tm.operand_types[op].bitfield.dword))
6055 {
6056 as_bad (_("`%s%s' not allowed with `%s%c'"),
6057 register_prefix,
6058 i.op[op].regs->reg_name,
6059 i.tm.name,
6060 i.suffix);
6061 return 0;
6062 }
6063 /* Warn if the e prefix on a general reg is missing. */
6064 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6065 && i.types[op].bitfield.word
6066 && (i.tm.operand_types[op].bitfield.reg
6067 || i.tm.operand_types[op].bitfield.acc)
6068 && i.tm.operand_types[op].bitfield.dword)
6069 {
6070 /* Prohibit these changes in the 64bit mode, since the
6071 lowering is more complicated. */
6072 if (flag_code == CODE_64BIT)
6073 {
6074 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6075 register_prefix, i.op[op].regs->reg_name,
6076 i.suffix);
6077 return 0;
6078 }
6079 #if REGISTER_WARNINGS
6080 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6081 register_prefix,
6082 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6083 register_prefix, i.op[op].regs->reg_name, i.suffix);
6084 #endif
6085 }
6086 /* Warn if the r prefix on a general reg is present. */
6087 else if (i.types[op].bitfield.qword
6088 && (i.tm.operand_types[op].bitfield.reg
6089 || i.tm.operand_types[op].bitfield.acc)
6090 && i.tm.operand_types[op].bitfield.dword)
6091 {
6092 if (intel_syntax
6093 && i.tm.opcode_modifier.toqword
6094 && !i.types[0].bitfield.regsimd)
6095 {
6096 /* Convert to QWORD. We want REX byte. */
6097 i.suffix = QWORD_MNEM_SUFFIX;
6098 }
6099 else
6100 {
6101 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6102 register_prefix, i.op[op].regs->reg_name,
6103 i.suffix);
6104 return 0;
6105 }
6106 }
6107 return 1;
6108 }
6109
6110 static int
6111 check_qword_reg (void)
6112 {
6113 int op;
6114
6115 for (op = i.operands; --op >= 0; )
6116 /* Skip non-register operands. */
6117 if (!i.types[op].bitfield.reg)
6118 continue;
6119 /* Reject eight bit registers, except where the template requires
6120 them. (eg. movzb) */
6121 else if (i.types[op].bitfield.byte
6122 && (i.tm.operand_types[op].bitfield.reg
6123 || i.tm.operand_types[op].bitfield.acc)
6124 && (i.tm.operand_types[op].bitfield.word
6125 || i.tm.operand_types[op].bitfield.dword))
6126 {
6127 as_bad (_("`%s%s' not allowed with `%s%c'"),
6128 register_prefix,
6129 i.op[op].regs->reg_name,
6130 i.tm.name,
6131 i.suffix);
6132 return 0;
6133 }
6134 /* Warn if the r prefix on a general reg is missing. */
6135 else if ((i.types[op].bitfield.word
6136 || i.types[op].bitfield.dword)
6137 && (i.tm.operand_types[op].bitfield.reg
6138 || i.tm.operand_types[op].bitfield.acc)
6139 && i.tm.operand_types[op].bitfield.qword)
6140 {
6141 /* Prohibit these changes in the 64bit mode, since the
6142 lowering is more complicated. */
6143 if (intel_syntax
6144 && i.tm.opcode_modifier.todword
6145 && !i.types[0].bitfield.regsimd)
6146 {
6147 /* Convert to DWORD. We don't want REX byte. */
6148 i.suffix = LONG_MNEM_SUFFIX;
6149 }
6150 else
6151 {
6152 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6153 register_prefix, i.op[op].regs->reg_name,
6154 i.suffix);
6155 return 0;
6156 }
6157 }
6158 return 1;
6159 }
6160
6161 static int
6162 check_word_reg (void)
6163 {
6164 int op;
6165 for (op = i.operands; --op >= 0;)
6166 /* Skip non-register operands. */
6167 if (!i.types[op].bitfield.reg)
6168 continue;
6169 /* Reject eight bit registers, except where the template requires
6170 them. (eg. movzb) */
6171 else if (i.types[op].bitfield.byte
6172 && (i.tm.operand_types[op].bitfield.reg
6173 || i.tm.operand_types[op].bitfield.acc)
6174 && (i.tm.operand_types[op].bitfield.word
6175 || i.tm.operand_types[op].bitfield.dword))
6176 {
6177 as_bad (_("`%s%s' not allowed with `%s%c'"),
6178 register_prefix,
6179 i.op[op].regs->reg_name,
6180 i.tm.name,
6181 i.suffix);
6182 return 0;
6183 }
6184 /* Warn if the e or r prefix on a general reg is present. */
6185 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6186 && (i.types[op].bitfield.dword
6187 || i.types[op].bitfield.qword)
6188 && (i.tm.operand_types[op].bitfield.reg
6189 || i.tm.operand_types[op].bitfield.acc)
6190 && i.tm.operand_types[op].bitfield.word)
6191 {
6192 /* Prohibit these changes in the 64bit mode, since the
6193 lowering is more complicated. */
6194 if (flag_code == CODE_64BIT)
6195 {
6196 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6197 register_prefix, i.op[op].regs->reg_name,
6198 i.suffix);
6199 return 0;
6200 }
6201 #if REGISTER_WARNINGS
6202 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6203 register_prefix,
6204 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6205 register_prefix, i.op[op].regs->reg_name, i.suffix);
6206 #endif
6207 }
6208 return 1;
6209 }
6210
6211 static int
6212 update_imm (unsigned int j)
6213 {
6214 i386_operand_type overlap = i.types[j];
6215 if ((overlap.bitfield.imm8
6216 || overlap.bitfield.imm8s
6217 || overlap.bitfield.imm16
6218 || overlap.bitfield.imm32
6219 || overlap.bitfield.imm32s
6220 || overlap.bitfield.imm64)
6221 && !operand_type_equal (&overlap, &imm8)
6222 && !operand_type_equal (&overlap, &imm8s)
6223 && !operand_type_equal (&overlap, &imm16)
6224 && !operand_type_equal (&overlap, &imm32)
6225 && !operand_type_equal (&overlap, &imm32s)
6226 && !operand_type_equal (&overlap, &imm64))
6227 {
6228 if (i.suffix)
6229 {
6230 i386_operand_type temp;
6231
6232 operand_type_set (&temp, 0);
6233 if (i.suffix == BYTE_MNEM_SUFFIX)
6234 {
6235 temp.bitfield.imm8 = overlap.bitfield.imm8;
6236 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6237 }
6238 else if (i.suffix == WORD_MNEM_SUFFIX)
6239 temp.bitfield.imm16 = overlap.bitfield.imm16;
6240 else if (i.suffix == QWORD_MNEM_SUFFIX)
6241 {
6242 temp.bitfield.imm64 = overlap.bitfield.imm64;
6243 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6244 }
6245 else
6246 temp.bitfield.imm32 = overlap.bitfield.imm32;
6247 overlap = temp;
6248 }
6249 else if (operand_type_equal (&overlap, &imm16_32_32s)
6250 || operand_type_equal (&overlap, &imm16_32)
6251 || operand_type_equal (&overlap, &imm16_32s))
6252 {
6253 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6254 overlap = imm16;
6255 else
6256 overlap = imm32s;
6257 }
6258 if (!operand_type_equal (&overlap, &imm8)
6259 && !operand_type_equal (&overlap, &imm8s)
6260 && !operand_type_equal (&overlap, &imm16)
6261 && !operand_type_equal (&overlap, &imm32)
6262 && !operand_type_equal (&overlap, &imm32s)
6263 && !operand_type_equal (&overlap, &imm64))
6264 {
6265 as_bad (_("no instruction mnemonic suffix given; "
6266 "can't determine immediate size"));
6267 return 0;
6268 }
6269 }
6270 i.types[j] = overlap;
6271
6272 return 1;
6273 }
6274
6275 static int
6276 finalize_imm (void)
6277 {
6278 unsigned int j, n;
6279
6280 /* Update the first 2 immediate operands. */
6281 n = i.operands > 2 ? 2 : i.operands;
6282 if (n)
6283 {
6284 for (j = 0; j < n; j++)
6285 if (update_imm (j) == 0)
6286 return 0;
6287
6288 /* The 3rd operand can't be immediate operand. */
6289 gas_assert (operand_type_check (i.types[2], imm) == 0);
6290 }
6291
6292 return 1;
6293 }
6294
6295 static int
6296 process_operands (void)
6297 {
6298 /* Default segment register this instruction will use for memory
6299 accesses. 0 means unknown. This is only for optimizing out
6300 unnecessary segment overrides. */
6301 const seg_entry *default_seg = 0;
6302
6303 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6304 {
6305 unsigned int dupl = i.operands;
6306 unsigned int dest = dupl - 1;
6307 unsigned int j;
6308
6309 /* The destination must be an xmm register. */
6310 gas_assert (i.reg_operands
6311 && MAX_OPERANDS > dupl
6312 && operand_type_equal (&i.types[dest], &regxmm));
6313
6314 if (i.tm.operand_types[0].bitfield.acc
6315 && i.tm.operand_types[0].bitfield.xmmword)
6316 {
6317 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6318 {
6319 /* Keep xmm0 for instructions with VEX prefix and 3
6320 sources. */
6321 i.tm.operand_types[0].bitfield.acc = 0;
6322 i.tm.operand_types[0].bitfield.regsimd = 1;
6323 goto duplicate;
6324 }
6325 else
6326 {
6327 /* We remove the first xmm0 and keep the number of
6328 operands unchanged, which in fact duplicates the
6329 destination. */
6330 for (j = 1; j < i.operands; j++)
6331 {
6332 i.op[j - 1] = i.op[j];
6333 i.types[j - 1] = i.types[j];
6334 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6335 }
6336 }
6337 }
6338 else if (i.tm.opcode_modifier.implicit1stxmm0)
6339 {
6340 gas_assert ((MAX_OPERANDS - 1) > dupl
6341 && (i.tm.opcode_modifier.vexsources
6342 == VEX3SOURCES));
6343
6344 /* Add the implicit xmm0 for instructions with VEX prefix
6345 and 3 sources. */
6346 for (j = i.operands; j > 0; j--)
6347 {
6348 i.op[j] = i.op[j - 1];
6349 i.types[j] = i.types[j - 1];
6350 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6351 }
6352 i.op[0].regs
6353 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6354 i.types[0] = regxmm;
6355 i.tm.operand_types[0] = regxmm;
6356
6357 i.operands += 2;
6358 i.reg_operands += 2;
6359 i.tm.operands += 2;
6360
6361 dupl++;
6362 dest++;
6363 i.op[dupl] = i.op[dest];
6364 i.types[dupl] = i.types[dest];
6365 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6366 }
6367 else
6368 {
6369 duplicate:
6370 i.operands++;
6371 i.reg_operands++;
6372 i.tm.operands++;
6373
6374 i.op[dupl] = i.op[dest];
6375 i.types[dupl] = i.types[dest];
6376 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6377 }
6378
6379 if (i.tm.opcode_modifier.immext)
6380 process_immext ();
6381 }
6382 else if (i.tm.operand_types[0].bitfield.acc
6383 && i.tm.operand_types[0].bitfield.xmmword)
6384 {
6385 unsigned int j;
6386
6387 for (j = 1; j < i.operands; j++)
6388 {
6389 i.op[j - 1] = i.op[j];
6390 i.types[j - 1] = i.types[j];
6391
6392 /* We need to adjust fields in i.tm since they are used by
6393 build_modrm_byte. */
6394 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6395 }
6396
6397 i.operands--;
6398 i.reg_operands--;
6399 i.tm.operands--;
6400 }
6401 else if (i.tm.opcode_modifier.implicitquadgroup)
6402 {
6403 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6404
6405 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6406 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6407 regnum = register_number (i.op[1].regs);
6408 first_reg_in_group = regnum & ~3;
6409 last_reg_in_group = first_reg_in_group + 3;
6410 if (regnum != first_reg_in_group)
6411 as_warn (_("source register `%s%s' implicitly denotes"
6412 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6413 register_prefix, i.op[1].regs->reg_name,
6414 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6415 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6416 i.tm.name);
6417 }
6418 else if (i.tm.opcode_modifier.regkludge)
6419 {
6420 /* The imul $imm, %reg instruction is converted into
6421 imul $imm, %reg, %reg, and the clr %reg instruction
6422 is converted into xor %reg, %reg. */
6423
6424 unsigned int first_reg_op;
6425
6426 if (operand_type_check (i.types[0], reg))
6427 first_reg_op = 0;
6428 else
6429 first_reg_op = 1;
6430 /* Pretend we saw the extra register operand. */
6431 gas_assert (i.reg_operands == 1
6432 && i.op[first_reg_op + 1].regs == 0);
6433 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6434 i.types[first_reg_op + 1] = i.types[first_reg_op];
6435 i.operands++;
6436 i.reg_operands++;
6437 }
6438
6439 if (i.tm.opcode_modifier.shortform)
6440 {
6441 if (i.types[0].bitfield.sreg2
6442 || i.types[0].bitfield.sreg3)
6443 {
6444 if (i.tm.base_opcode == POP_SEG_SHORT
6445 && i.op[0].regs->reg_num == 1)
6446 {
6447 as_bad (_("you can't `pop %scs'"), register_prefix);
6448 return 0;
6449 }
6450 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6451 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6452 i.rex |= REX_B;
6453 }
6454 else
6455 {
6456 /* The register or float register operand is in operand
6457 0 or 1. */
6458 unsigned int op;
6459
6460 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6461 || operand_type_check (i.types[0], reg))
6462 op = 0;
6463 else
6464 op = 1;
6465 /* Register goes in low 3 bits of opcode. */
6466 i.tm.base_opcode |= i.op[op].regs->reg_num;
6467 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6468 i.rex |= REX_B;
6469 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6470 {
6471 /* Warn about some common errors, but press on regardless.
6472 The first case can be generated by gcc (<= 2.8.1). */
6473 if (i.operands == 2)
6474 {
6475 /* Reversed arguments on faddp, fsubp, etc. */
6476 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6477 register_prefix, i.op[!intel_syntax].regs->reg_name,
6478 register_prefix, i.op[intel_syntax].regs->reg_name);
6479 }
6480 else
6481 {
6482 /* Extraneous `l' suffix on fp insn. */
6483 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6484 register_prefix, i.op[0].regs->reg_name);
6485 }
6486 }
6487 }
6488 }
6489 else if (i.tm.opcode_modifier.modrm)
6490 {
6491 /* The opcode is completed (modulo i.tm.extension_opcode which
6492 must be put into the modrm byte). Now, we make the modrm and
6493 index base bytes based on all the info we've collected. */
6494
6495 default_seg = build_modrm_byte ();
6496 }
6497 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6498 {
6499 default_seg = &ds;
6500 }
6501 else if (i.tm.opcode_modifier.isstring)
6502 {
6503 /* For the string instructions that allow a segment override
6504 on one of their operands, the default segment is ds. */
6505 default_seg = &ds;
6506 }
6507
6508 if (i.tm.base_opcode == 0x8d /* lea */
6509 && i.seg[0]
6510 && !quiet_warnings)
6511 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6512
6513 /* If a segment was explicitly specified, and the specified segment
6514 is not the default, use an opcode prefix to select it. If we
6515 never figured out what the default segment is, then default_seg
6516 will be zero at this point, and the specified segment prefix will
6517 always be used. */
6518 if ((i.seg[0]) && (i.seg[0] != default_seg))
6519 {
6520 if (!add_prefix (i.seg[0]->seg_prefix))
6521 return 0;
6522 }
6523 return 1;
6524 }
6525
6526 static const seg_entry *
6527 build_modrm_byte (void)
6528 {
6529 const seg_entry *default_seg = 0;
6530 unsigned int source, dest;
6531 int vex_3_sources;
6532
6533 /* The first operand of instructions with VEX prefix and 3 sources
6534 must be VEX_Imm4. */
6535 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6536 if (vex_3_sources)
6537 {
6538 unsigned int nds, reg_slot;
6539 expressionS *exp;
6540
6541 if (i.tm.opcode_modifier.veximmext
6542 && i.tm.opcode_modifier.immext)
6543 {
6544 dest = i.operands - 2;
6545 gas_assert (dest == 3);
6546 }
6547 else
6548 dest = i.operands - 1;
6549 nds = dest - 1;
6550
6551 /* There are 2 kinds of instructions:
6552 1. 5 operands: 4 register operands or 3 register operands
6553 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6554 VexW0 or VexW1. The destination must be either XMM, YMM or
6555 ZMM register.
6556 2. 4 operands: 4 register operands or 3 register operands
6557 plus 1 memory operand, VexXDS, and VexImmExt */
6558 gas_assert ((i.reg_operands == 4
6559 || (i.reg_operands == 3 && i.mem_operands == 1))
6560 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6561 && (i.tm.opcode_modifier.veximmext
6562 || (i.imm_operands == 1
6563 && i.types[0].bitfield.vec_imm4
6564 && (i.tm.opcode_modifier.vexw == VEXW0
6565 || i.tm.opcode_modifier.vexw == VEXW1)
6566 && i.tm.operand_types[dest].bitfield.regsimd)));
6567
6568 if (i.imm_operands == 0)
6569 {
6570 /* When there is no immediate operand, generate an 8bit
6571 immediate operand to encode the first operand. */
6572 exp = &im_expressions[i.imm_operands++];
6573 i.op[i.operands].imms = exp;
6574 i.types[i.operands] = imm8;
6575 i.operands++;
6576 /* If VexW1 is set, the first operand is the source and
6577 the second operand is encoded in the immediate operand. */
6578 if (i.tm.opcode_modifier.vexw == VEXW1)
6579 {
6580 source = 0;
6581 reg_slot = 1;
6582 }
6583 else
6584 {
6585 source = 1;
6586 reg_slot = 0;
6587 }
6588
6589 /* FMA swaps REG and NDS. */
6590 if (i.tm.cpu_flags.bitfield.cpufma)
6591 {
6592 unsigned int tmp;
6593 tmp = reg_slot;
6594 reg_slot = nds;
6595 nds = tmp;
6596 }
6597
6598 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6599 exp->X_op = O_constant;
6600 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6601 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6602 }
6603 else
6604 {
6605 unsigned int imm_slot;
6606
6607 if (i.tm.opcode_modifier.vexw == VEXW0)
6608 {
6609 /* If VexW0 is set, the third operand is the source and
6610 the second operand is encoded in the immediate
6611 operand. */
6612 source = 2;
6613 reg_slot = 1;
6614 }
6615 else
6616 {
6617 /* VexW1 is set, the second operand is the source and
6618 the third operand is encoded in the immediate
6619 operand. */
6620 source = 1;
6621 reg_slot = 2;
6622 }
6623
6624 if (i.tm.opcode_modifier.immext)
6625 {
6626 /* When ImmExt is set, the immediate byte is the last
6627 operand. */
6628 imm_slot = i.operands - 1;
6629 source--;
6630 reg_slot--;
6631 }
6632 else
6633 {
6634 imm_slot = 0;
6635
6636 /* Turn on Imm8 so that output_imm will generate it. */
6637 i.types[imm_slot].bitfield.imm8 = 1;
6638 }
6639
6640 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6641 i.op[imm_slot].imms->X_add_number
6642 |= register_number (i.op[reg_slot].regs) << 4;
6643 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6644 }
6645
6646 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6647 i.vex.register_specifier = i.op[nds].regs;
6648 }
6649 else
6650 source = dest = 0;
6651
6652 /* i.reg_operands MUST be the number of real register operands;
6653 implicit registers do not count. If there are 3 register
6654 operands, it must be a instruction with VexNDS. For a
6655 instruction with VexNDD, the destination register is encoded
6656 in VEX prefix. If there are 4 register operands, it must be
6657 a instruction with VEX prefix and 3 sources. */
6658 if (i.mem_operands == 0
6659 && ((i.reg_operands == 2
6660 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6661 || (i.reg_operands == 3
6662 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6663 || (i.reg_operands == 4 && vex_3_sources)))
6664 {
6665 switch (i.operands)
6666 {
6667 case 2:
6668 source = 0;
6669 break;
6670 case 3:
6671 /* When there are 3 operands, one of them may be immediate,
6672 which may be the first or the last operand. Otherwise,
6673 the first operand must be shift count register (cl) or it
6674 is an instruction with VexNDS. */
6675 gas_assert (i.imm_operands == 1
6676 || (i.imm_operands == 0
6677 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6678 || i.types[0].bitfield.shiftcount)));
6679 if (operand_type_check (i.types[0], imm)
6680 || i.types[0].bitfield.shiftcount)
6681 source = 1;
6682 else
6683 source = 0;
6684 break;
6685 case 4:
6686 /* When there are 4 operands, the first two must be 8bit
6687 immediate operands. The source operand will be the 3rd
6688 one.
6689
6690 For instructions with VexNDS, if the first operand
6691 an imm8, the source operand is the 2nd one. If the last
6692 operand is imm8, the source operand is the first one. */
6693 gas_assert ((i.imm_operands == 2
6694 && i.types[0].bitfield.imm8
6695 && i.types[1].bitfield.imm8)
6696 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6697 && i.imm_operands == 1
6698 && (i.types[0].bitfield.imm8
6699 || i.types[i.operands - 1].bitfield.imm8
6700 || i.rounding)));
6701 if (i.imm_operands == 2)
6702 source = 2;
6703 else
6704 {
6705 if (i.types[0].bitfield.imm8)
6706 source = 1;
6707 else
6708 source = 0;
6709 }
6710 break;
6711 case 5:
6712 if (is_evex_encoding (&i.tm))
6713 {
6714 /* For EVEX instructions, when there are 5 operands, the
6715 first one must be immediate operand. If the second one
6716 is immediate operand, the source operand is the 3th
6717 one. If the last one is immediate operand, the source
6718 operand is the 2nd one. */
6719 gas_assert (i.imm_operands == 2
6720 && i.tm.opcode_modifier.sae
6721 && operand_type_check (i.types[0], imm));
6722 if (operand_type_check (i.types[1], imm))
6723 source = 2;
6724 else if (operand_type_check (i.types[4], imm))
6725 source = 1;
6726 else
6727 abort ();
6728 }
6729 break;
6730 default:
6731 abort ();
6732 }
6733
6734 if (!vex_3_sources)
6735 {
6736 dest = source + 1;
6737
6738 /* RC/SAE operand could be between DEST and SRC. That happens
6739 when one operand is GPR and the other one is XMM/YMM/ZMM
6740 register. */
6741 if (i.rounding && i.rounding->operand == (int) dest)
6742 dest++;
6743
6744 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6745 {
6746 /* For instructions with VexNDS, the register-only source
6747 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6748 register. It is encoded in VEX prefix. We need to
6749 clear RegMem bit before calling operand_type_equal. */
6750
6751 i386_operand_type op;
6752 unsigned int vvvv;
6753
6754 /* Check register-only source operand when two source
6755 operands are swapped. */
6756 if (!i.tm.operand_types[source].bitfield.baseindex
6757 && i.tm.operand_types[dest].bitfield.baseindex)
6758 {
6759 vvvv = source;
6760 source = dest;
6761 }
6762 else
6763 vvvv = dest;
6764
6765 op = i.tm.operand_types[vvvv];
6766 op.bitfield.regmem = 0;
6767 if ((dest + 1) >= i.operands
6768 || ((!op.bitfield.reg
6769 || (!op.bitfield.dword && !op.bitfield.qword))
6770 && !op.bitfield.regsimd
6771 && !operand_type_equal (&op, &regmask)))
6772 abort ();
6773 i.vex.register_specifier = i.op[vvvv].regs;
6774 dest++;
6775 }
6776 }
6777
6778 i.rm.mode = 3;
6779 /* One of the register operands will be encoded in the i.tm.reg
6780 field, the other in the combined i.tm.mode and i.tm.regmem
6781 fields. If no form of this instruction supports a memory
6782 destination operand, then we assume the source operand may
6783 sometimes be a memory operand and so we need to store the
6784 destination in the i.rm.reg field. */
6785 if (!i.tm.operand_types[dest].bitfield.regmem
6786 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6787 {
6788 i.rm.reg = i.op[dest].regs->reg_num;
6789 i.rm.regmem = i.op[source].regs->reg_num;
6790 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6791 i.rex |= REX_R;
6792 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6793 i.vrex |= REX_R;
6794 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6795 i.rex |= REX_B;
6796 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6797 i.vrex |= REX_B;
6798 }
6799 else
6800 {
6801 i.rm.reg = i.op[source].regs->reg_num;
6802 i.rm.regmem = i.op[dest].regs->reg_num;
6803 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6804 i.rex |= REX_B;
6805 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6806 i.vrex |= REX_B;
6807 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6808 i.rex |= REX_R;
6809 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6810 i.vrex |= REX_R;
6811 }
6812 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6813 {
6814 if (!i.types[0].bitfield.control
6815 && !i.types[1].bitfield.control)
6816 abort ();
6817 i.rex &= ~(REX_R | REX_B);
6818 add_prefix (LOCK_PREFIX_OPCODE);
6819 }
6820 }
6821 else
6822 { /* If it's not 2 reg operands... */
6823 unsigned int mem;
6824
6825 if (i.mem_operands)
6826 {
6827 unsigned int fake_zero_displacement = 0;
6828 unsigned int op;
6829
6830 for (op = 0; op < i.operands; op++)
6831 if (operand_type_check (i.types[op], anymem))
6832 break;
6833 gas_assert (op < i.operands);
6834
6835 if (i.tm.opcode_modifier.vecsib)
6836 {
6837 if (i.index_reg->reg_num == RegEiz
6838 || i.index_reg->reg_num == RegRiz)
6839 abort ();
6840
6841 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6842 if (!i.base_reg)
6843 {
6844 i.sib.base = NO_BASE_REGISTER;
6845 i.sib.scale = i.log2_scale_factor;
6846 i.types[op].bitfield.disp8 = 0;
6847 i.types[op].bitfield.disp16 = 0;
6848 i.types[op].bitfield.disp64 = 0;
6849 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6850 {
6851 /* Must be 32 bit */
6852 i.types[op].bitfield.disp32 = 1;
6853 i.types[op].bitfield.disp32s = 0;
6854 }
6855 else
6856 {
6857 i.types[op].bitfield.disp32 = 0;
6858 i.types[op].bitfield.disp32s = 1;
6859 }
6860 }
6861 i.sib.index = i.index_reg->reg_num;
6862 if ((i.index_reg->reg_flags & RegRex) != 0)
6863 i.rex |= REX_X;
6864 if ((i.index_reg->reg_flags & RegVRex) != 0)
6865 i.vrex |= REX_X;
6866 }
6867
6868 default_seg = &ds;
6869
6870 if (i.base_reg == 0)
6871 {
6872 i.rm.mode = 0;
6873 if (!i.disp_operands)
6874 fake_zero_displacement = 1;
6875 if (i.index_reg == 0)
6876 {
6877 i386_operand_type newdisp;
6878
6879 gas_assert (!i.tm.opcode_modifier.vecsib);
6880 /* Operand is just <disp> */
6881 if (flag_code == CODE_64BIT)
6882 {
6883 /* 64bit mode overwrites the 32bit absolute
6884 addressing by RIP relative addressing and
6885 absolute addressing is encoded by one of the
6886 redundant SIB forms. */
6887 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6888 i.sib.base = NO_BASE_REGISTER;
6889 i.sib.index = NO_INDEX_REGISTER;
6890 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6891 }
6892 else if ((flag_code == CODE_16BIT)
6893 ^ (i.prefix[ADDR_PREFIX] != 0))
6894 {
6895 i.rm.regmem = NO_BASE_REGISTER_16;
6896 newdisp = disp16;
6897 }
6898 else
6899 {
6900 i.rm.regmem = NO_BASE_REGISTER;
6901 newdisp = disp32;
6902 }
6903 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6904 i.types[op] = operand_type_or (i.types[op], newdisp);
6905 }
6906 else if (!i.tm.opcode_modifier.vecsib)
6907 {
6908 /* !i.base_reg && i.index_reg */
6909 if (i.index_reg->reg_num == RegEiz
6910 || i.index_reg->reg_num == RegRiz)
6911 i.sib.index = NO_INDEX_REGISTER;
6912 else
6913 i.sib.index = i.index_reg->reg_num;
6914 i.sib.base = NO_BASE_REGISTER;
6915 i.sib.scale = i.log2_scale_factor;
6916 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6917 i.types[op].bitfield.disp8 = 0;
6918 i.types[op].bitfield.disp16 = 0;
6919 i.types[op].bitfield.disp64 = 0;
6920 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6921 {
6922 /* Must be 32 bit */
6923 i.types[op].bitfield.disp32 = 1;
6924 i.types[op].bitfield.disp32s = 0;
6925 }
6926 else
6927 {
6928 i.types[op].bitfield.disp32 = 0;
6929 i.types[op].bitfield.disp32s = 1;
6930 }
6931 if ((i.index_reg->reg_flags & RegRex) != 0)
6932 i.rex |= REX_X;
6933 }
6934 }
6935 /* RIP addressing for 64bit mode. */
6936 else if (i.base_reg->reg_num == RegRip ||
6937 i.base_reg->reg_num == RegEip)
6938 {
6939 gas_assert (!i.tm.opcode_modifier.vecsib);
6940 i.rm.regmem = NO_BASE_REGISTER;
6941 i.types[op].bitfield.disp8 = 0;
6942 i.types[op].bitfield.disp16 = 0;
6943 i.types[op].bitfield.disp32 = 0;
6944 i.types[op].bitfield.disp32s = 1;
6945 i.types[op].bitfield.disp64 = 0;
6946 i.flags[op] |= Operand_PCrel;
6947 if (! i.disp_operands)
6948 fake_zero_displacement = 1;
6949 }
6950 else if (i.base_reg->reg_type.bitfield.word)
6951 {
6952 gas_assert (!i.tm.opcode_modifier.vecsib);
6953 switch (i.base_reg->reg_num)
6954 {
6955 case 3: /* (%bx) */
6956 if (i.index_reg == 0)
6957 i.rm.regmem = 7;
6958 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6959 i.rm.regmem = i.index_reg->reg_num - 6;
6960 break;
6961 case 5: /* (%bp) */
6962 default_seg = &ss;
6963 if (i.index_reg == 0)
6964 {
6965 i.rm.regmem = 6;
6966 if (operand_type_check (i.types[op], disp) == 0)
6967 {
6968 /* fake (%bp) into 0(%bp) */
6969 i.types[op].bitfield.disp8 = 1;
6970 fake_zero_displacement = 1;
6971 }
6972 }
6973 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6974 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6975 break;
6976 default: /* (%si) -> 4 or (%di) -> 5 */
6977 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6978 }
6979 i.rm.mode = mode_from_disp_size (i.types[op]);
6980 }
6981 else /* i.base_reg and 32/64 bit mode */
6982 {
6983 if (flag_code == CODE_64BIT
6984 && operand_type_check (i.types[op], disp))
6985 {
6986 i.types[op].bitfield.disp16 = 0;
6987 i.types[op].bitfield.disp64 = 0;
6988 if (i.prefix[ADDR_PREFIX] == 0)
6989 {
6990 i.types[op].bitfield.disp32 = 0;
6991 i.types[op].bitfield.disp32s = 1;
6992 }
6993 else
6994 {
6995 i.types[op].bitfield.disp32 = 1;
6996 i.types[op].bitfield.disp32s = 0;
6997 }
6998 }
6999
7000 if (!i.tm.opcode_modifier.vecsib)
7001 i.rm.regmem = i.base_reg->reg_num;
7002 if ((i.base_reg->reg_flags & RegRex) != 0)
7003 i.rex |= REX_B;
7004 i.sib.base = i.base_reg->reg_num;
7005 /* x86-64 ignores REX prefix bit here to avoid decoder
7006 complications. */
7007 if (!(i.base_reg->reg_flags & RegRex)
7008 && (i.base_reg->reg_num == EBP_REG_NUM
7009 || i.base_reg->reg_num == ESP_REG_NUM))
7010 default_seg = &ss;
7011 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7012 {
7013 fake_zero_displacement = 1;
7014 i.types[op].bitfield.disp8 = 1;
7015 }
7016 i.sib.scale = i.log2_scale_factor;
7017 if (i.index_reg == 0)
7018 {
7019 gas_assert (!i.tm.opcode_modifier.vecsib);
7020 /* <disp>(%esp) becomes two byte modrm with no index
7021 register. We've already stored the code for esp
7022 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7023 Any base register besides %esp will not use the
7024 extra modrm byte. */
7025 i.sib.index = NO_INDEX_REGISTER;
7026 }
7027 else if (!i.tm.opcode_modifier.vecsib)
7028 {
7029 if (i.index_reg->reg_num == RegEiz
7030 || i.index_reg->reg_num == RegRiz)
7031 i.sib.index = NO_INDEX_REGISTER;
7032 else
7033 i.sib.index = i.index_reg->reg_num;
7034 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7035 if ((i.index_reg->reg_flags & RegRex) != 0)
7036 i.rex |= REX_X;
7037 }
7038
7039 if (i.disp_operands
7040 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7041 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7042 i.rm.mode = 0;
7043 else
7044 {
7045 if (!fake_zero_displacement
7046 && !i.disp_operands
7047 && i.disp_encoding)
7048 {
7049 fake_zero_displacement = 1;
7050 if (i.disp_encoding == disp_encoding_8bit)
7051 i.types[op].bitfield.disp8 = 1;
7052 else
7053 i.types[op].bitfield.disp32 = 1;
7054 }
7055 i.rm.mode = mode_from_disp_size (i.types[op]);
7056 }
7057 }
7058
7059 if (fake_zero_displacement)
7060 {
7061 /* Fakes a zero displacement assuming that i.types[op]
7062 holds the correct displacement size. */
7063 expressionS *exp;
7064
7065 gas_assert (i.op[op].disps == 0);
7066 exp = &disp_expressions[i.disp_operands++];
7067 i.op[op].disps = exp;
7068 exp->X_op = O_constant;
7069 exp->X_add_number = 0;
7070 exp->X_add_symbol = (symbolS *) 0;
7071 exp->X_op_symbol = (symbolS *) 0;
7072 }
7073
7074 mem = op;
7075 }
7076 else
7077 mem = ~0;
7078
7079 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7080 {
7081 if (operand_type_check (i.types[0], imm))
7082 i.vex.register_specifier = NULL;
7083 else
7084 {
7085 /* VEX.vvvv encodes one of the sources when the first
7086 operand is not an immediate. */
7087 if (i.tm.opcode_modifier.vexw == VEXW0)
7088 i.vex.register_specifier = i.op[0].regs;
7089 else
7090 i.vex.register_specifier = i.op[1].regs;
7091 }
7092
7093 /* Destination is a XMM register encoded in the ModRM.reg
7094 and VEX.R bit. */
7095 i.rm.reg = i.op[2].regs->reg_num;
7096 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7097 i.rex |= REX_R;
7098
7099 /* ModRM.rm and VEX.B encodes the other source. */
7100 if (!i.mem_operands)
7101 {
7102 i.rm.mode = 3;
7103
7104 if (i.tm.opcode_modifier.vexw == VEXW0)
7105 i.rm.regmem = i.op[1].regs->reg_num;
7106 else
7107 i.rm.regmem = i.op[0].regs->reg_num;
7108
7109 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7110 i.rex |= REX_B;
7111 }
7112 }
7113 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7114 {
7115 i.vex.register_specifier = i.op[2].regs;
7116 if (!i.mem_operands)
7117 {
7118 i.rm.mode = 3;
7119 i.rm.regmem = i.op[1].regs->reg_num;
7120 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7121 i.rex |= REX_B;
7122 }
7123 }
7124 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7125 (if any) based on i.tm.extension_opcode. Again, we must be
7126 careful to make sure that segment/control/debug/test/MMX
7127 registers are coded into the i.rm.reg field. */
7128 else if (i.reg_operands)
7129 {
7130 unsigned int op;
7131 unsigned int vex_reg = ~0;
7132
7133 for (op = 0; op < i.operands; op++)
7134 if (i.types[op].bitfield.reg
7135 || i.types[op].bitfield.regmmx
7136 || i.types[op].bitfield.regsimd
7137 || i.types[op].bitfield.regbnd
7138 || i.types[op].bitfield.regmask
7139 || i.types[op].bitfield.sreg2
7140 || i.types[op].bitfield.sreg3
7141 || i.types[op].bitfield.control
7142 || i.types[op].bitfield.debug
7143 || i.types[op].bitfield.test)
7144 break;
7145
7146 if (vex_3_sources)
7147 op = dest;
7148 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7149 {
7150 /* For instructions with VexNDS, the register-only
7151 source operand is encoded in VEX prefix. */
7152 gas_assert (mem != (unsigned int) ~0);
7153
7154 if (op > mem)
7155 {
7156 vex_reg = op++;
7157 gas_assert (op < i.operands);
7158 }
7159 else
7160 {
7161 /* Check register-only source operand when two source
7162 operands are swapped. */
7163 if (!i.tm.operand_types[op].bitfield.baseindex
7164 && i.tm.operand_types[op + 1].bitfield.baseindex)
7165 {
7166 vex_reg = op;
7167 op += 2;
7168 gas_assert (mem == (vex_reg + 1)
7169 && op < i.operands);
7170 }
7171 else
7172 {
7173 vex_reg = op + 1;
7174 gas_assert (vex_reg < i.operands);
7175 }
7176 }
7177 }
7178 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7179 {
7180 /* For instructions with VexNDD, the register destination
7181 is encoded in VEX prefix. */
7182 if (i.mem_operands == 0)
7183 {
7184 /* There is no memory operand. */
7185 gas_assert ((op + 2) == i.operands);
7186 vex_reg = op + 1;
7187 }
7188 else
7189 {
7190 /* There are only 2 non-immediate operands. */
7191 gas_assert (op < i.imm_operands + 2
7192 && i.operands == i.imm_operands + 2);
7193 vex_reg = i.imm_operands + 1;
7194 }
7195 }
7196 else
7197 gas_assert (op < i.operands);
7198
7199 if (vex_reg != (unsigned int) ~0)
7200 {
7201 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7202
7203 if ((!type->bitfield.reg
7204 || (!type->bitfield.dword && !type->bitfield.qword))
7205 && !type->bitfield.regsimd
7206 && !operand_type_equal (type, &regmask))
7207 abort ();
7208
7209 i.vex.register_specifier = i.op[vex_reg].regs;
7210 }
7211
7212 /* Don't set OP operand twice. */
7213 if (vex_reg != op)
7214 {
7215 /* If there is an extension opcode to put here, the
7216 register number must be put into the regmem field. */
7217 if (i.tm.extension_opcode != None)
7218 {
7219 i.rm.regmem = i.op[op].regs->reg_num;
7220 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7221 i.rex |= REX_B;
7222 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7223 i.vrex |= REX_B;
7224 }
7225 else
7226 {
7227 i.rm.reg = i.op[op].regs->reg_num;
7228 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7229 i.rex |= REX_R;
7230 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7231 i.vrex |= REX_R;
7232 }
7233 }
7234
7235 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7236 must set it to 3 to indicate this is a register operand
7237 in the regmem field. */
7238 if (!i.mem_operands)
7239 i.rm.mode = 3;
7240 }
7241
7242 /* Fill in i.rm.reg field with extension opcode (if any). */
7243 if (i.tm.extension_opcode != None)
7244 i.rm.reg = i.tm.extension_opcode;
7245 }
7246 return default_seg;
7247 }
7248
7249 static void
7250 output_branch (void)
7251 {
7252 char *p;
7253 int size;
7254 int code16;
7255 int prefix;
7256 relax_substateT subtype;
7257 symbolS *sym;
7258 offsetT off;
7259
7260 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7261 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7262
7263 prefix = 0;
7264 if (i.prefix[DATA_PREFIX] != 0)
7265 {
7266 prefix = 1;
7267 i.prefixes -= 1;
7268 code16 ^= CODE16;
7269 }
7270 /* Pentium4 branch hints. */
7271 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7272 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7273 {
7274 prefix++;
7275 i.prefixes--;
7276 }
7277 if (i.prefix[REX_PREFIX] != 0)
7278 {
7279 prefix++;
7280 i.prefixes--;
7281 }
7282
7283 /* BND prefixed jump. */
7284 if (i.prefix[BND_PREFIX] != 0)
7285 {
7286 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7287 i.prefixes -= 1;
7288 }
7289
7290 if (i.prefixes != 0 && !intel_syntax)
7291 as_warn (_("skipping prefixes on this instruction"));
7292
7293 /* It's always a symbol; End frag & setup for relax.
7294 Make sure there is enough room in this frag for the largest
7295 instruction we may generate in md_convert_frag. This is 2
7296 bytes for the opcode and room for the prefix and largest
7297 displacement. */
7298 frag_grow (prefix + 2 + 4);
7299 /* Prefix and 1 opcode byte go in fr_fix. */
7300 p = frag_more (prefix + 1);
7301 if (i.prefix[DATA_PREFIX] != 0)
7302 *p++ = DATA_PREFIX_OPCODE;
7303 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7304 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7305 *p++ = i.prefix[SEG_PREFIX];
7306 if (i.prefix[REX_PREFIX] != 0)
7307 *p++ = i.prefix[REX_PREFIX];
7308 *p = i.tm.base_opcode;
7309
7310 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7311 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7312 else if (cpu_arch_flags.bitfield.cpui386)
7313 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7314 else
7315 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7316 subtype |= code16;
7317
7318 sym = i.op[0].disps->X_add_symbol;
7319 off = i.op[0].disps->X_add_number;
7320
7321 if (i.op[0].disps->X_op != O_constant
7322 && i.op[0].disps->X_op != O_symbol)
7323 {
7324 /* Handle complex expressions. */
7325 sym = make_expr_symbol (i.op[0].disps);
7326 off = 0;
7327 }
7328
7329 /* 1 possible extra opcode + 4 byte displacement go in var part.
7330 Pass reloc in fr_var. */
7331 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7332 }
7333
7334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7335 /* Return TRUE iff PLT32 relocation should be used for branching to
7336 symbol S. */
7337
7338 static bfd_boolean
7339 need_plt32_p (symbolS *s)
7340 {
7341 /* PLT32 relocation is ELF only. */
7342 if (!IS_ELF)
7343 return FALSE;
7344
7345 /* Since there is no need to prepare for PLT branch on x86-64, we
7346 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7347 be used as a marker for 32-bit PC-relative branches. */
7348 if (!object_64bit)
7349 return FALSE;
7350
7351 /* Weak or undefined symbol need PLT32 relocation. */
7352 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7353 return TRUE;
7354
7355 /* Non-global symbol doesn't need PLT32 relocation. */
7356 if (! S_IS_EXTERNAL (s))
7357 return FALSE;
7358
7359 /* Other global symbols need PLT32 relocation. NB: Symbol with
7360 non-default visibilities are treated as normal global symbol
7361 so that PLT32 relocation can be used as a marker for 32-bit
7362 PC-relative branches. It is useful for linker relaxation. */
7363 return TRUE;
7364 }
7365 #endif
7366
7367 static void
7368 output_jump (void)
7369 {
7370 char *p;
7371 int size;
7372 fixS *fixP;
7373 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7374
7375 if (i.tm.opcode_modifier.jumpbyte)
7376 {
7377 /* This is a loop or jecxz type instruction. */
7378 size = 1;
7379 if (i.prefix[ADDR_PREFIX] != 0)
7380 {
7381 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7382 i.prefixes -= 1;
7383 }
7384 /* Pentium4 branch hints. */
7385 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7386 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7387 {
7388 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7389 i.prefixes--;
7390 }
7391 }
7392 else
7393 {
7394 int code16;
7395
7396 code16 = 0;
7397 if (flag_code == CODE_16BIT)
7398 code16 = CODE16;
7399
7400 if (i.prefix[DATA_PREFIX] != 0)
7401 {
7402 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7403 i.prefixes -= 1;
7404 code16 ^= CODE16;
7405 }
7406
7407 size = 4;
7408 if (code16)
7409 size = 2;
7410 }
7411
7412 if (i.prefix[REX_PREFIX] != 0)
7413 {
7414 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7415 i.prefixes -= 1;
7416 }
7417
7418 /* BND prefixed jump. */
7419 if (i.prefix[BND_PREFIX] != 0)
7420 {
7421 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7422 i.prefixes -= 1;
7423 }
7424
7425 if (i.prefixes != 0 && !intel_syntax)
7426 as_warn (_("skipping prefixes on this instruction"));
7427
7428 p = frag_more (i.tm.opcode_length + size);
7429 switch (i.tm.opcode_length)
7430 {
7431 case 2:
7432 *p++ = i.tm.base_opcode >> 8;
7433 /* Fall through. */
7434 case 1:
7435 *p++ = i.tm.base_opcode;
7436 break;
7437 default:
7438 abort ();
7439 }
7440
7441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7442 if (size == 4
7443 && jump_reloc == NO_RELOC
7444 && need_plt32_p (i.op[0].disps->X_add_symbol))
7445 jump_reloc = BFD_RELOC_X86_64_PLT32;
7446 #endif
7447
7448 jump_reloc = reloc (size, 1, 1, jump_reloc);
7449
7450 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7451 i.op[0].disps, 1, jump_reloc);
7452
7453 /* All jumps handled here are signed, but don't use a signed limit
7454 check for 32 and 16 bit jumps as we want to allow wrap around at
7455 4G and 64k respectively. */
7456 if (size == 1)
7457 fixP->fx_signed = 1;
7458 }
7459
7460 static void
7461 output_interseg_jump (void)
7462 {
7463 char *p;
7464 int size;
7465 int prefix;
7466 int code16;
7467
7468 code16 = 0;
7469 if (flag_code == CODE_16BIT)
7470 code16 = CODE16;
7471
7472 prefix = 0;
7473 if (i.prefix[DATA_PREFIX] != 0)
7474 {
7475 prefix = 1;
7476 i.prefixes -= 1;
7477 code16 ^= CODE16;
7478 }
7479 if (i.prefix[REX_PREFIX] != 0)
7480 {
7481 prefix++;
7482 i.prefixes -= 1;
7483 }
7484
7485 size = 4;
7486 if (code16)
7487 size = 2;
7488
7489 if (i.prefixes != 0 && !intel_syntax)
7490 as_warn (_("skipping prefixes on this instruction"));
7491
7492 /* 1 opcode; 2 segment; offset */
7493 p = frag_more (prefix + 1 + 2 + size);
7494
7495 if (i.prefix[DATA_PREFIX] != 0)
7496 *p++ = DATA_PREFIX_OPCODE;
7497
7498 if (i.prefix[REX_PREFIX] != 0)
7499 *p++ = i.prefix[REX_PREFIX];
7500
7501 *p++ = i.tm.base_opcode;
7502 if (i.op[1].imms->X_op == O_constant)
7503 {
7504 offsetT n = i.op[1].imms->X_add_number;
7505
7506 if (size == 2
7507 && !fits_in_unsigned_word (n)
7508 && !fits_in_signed_word (n))
7509 {
7510 as_bad (_("16-bit jump out of range"));
7511 return;
7512 }
7513 md_number_to_chars (p, n, size);
7514 }
7515 else
7516 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7517 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7518 if (i.op[0].imms->X_op != O_constant)
7519 as_bad (_("can't handle non absolute segment in `%s'"),
7520 i.tm.name);
7521 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7522 }
7523
7524 static void
7525 output_insn (void)
7526 {
7527 fragS *insn_start_frag;
7528 offsetT insn_start_off;
7529
7530 /* Tie dwarf2 debug info to the address at the start of the insn.
7531 We can't do this after the insn has been output as the current
7532 frag may have been closed off. eg. by frag_var. */
7533 dwarf2_emit_insn (0);
7534
7535 insn_start_frag = frag_now;
7536 insn_start_off = frag_now_fix ();
7537
7538 /* Output jumps. */
7539 if (i.tm.opcode_modifier.jump)
7540 output_branch ();
7541 else if (i.tm.opcode_modifier.jumpbyte
7542 || i.tm.opcode_modifier.jumpdword)
7543 output_jump ();
7544 else if (i.tm.opcode_modifier.jumpintersegment)
7545 output_interseg_jump ();
7546 else
7547 {
7548 /* Output normal instructions here. */
7549 char *p;
7550 unsigned char *q;
7551 unsigned int j;
7552 unsigned int prefix;
7553
7554 if (avoid_fence
7555 && i.tm.base_opcode == 0xfae
7556 && i.operands == 1
7557 && i.imm_operands == 1
7558 && (i.op[0].imms->X_add_number == 0xe8
7559 || i.op[0].imms->X_add_number == 0xf0
7560 || i.op[0].imms->X_add_number == 0xf8))
7561 {
7562 /* Encode lfence, mfence, and sfence as
7563 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7564 offsetT val = 0x240483f0ULL;
7565 p = frag_more (5);
7566 md_number_to_chars (p, val, 5);
7567 return;
7568 }
7569
7570 /* Some processors fail on LOCK prefix. This options makes
7571 assembler ignore LOCK prefix and serves as a workaround. */
7572 if (omit_lock_prefix)
7573 {
7574 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7575 return;
7576 i.prefix[LOCK_PREFIX] = 0;
7577 }
7578
7579 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7580 don't need the explicit prefix. */
7581 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7582 {
7583 switch (i.tm.opcode_length)
7584 {
7585 case 3:
7586 if (i.tm.base_opcode & 0xff000000)
7587 {
7588 prefix = (i.tm.base_opcode >> 24) & 0xff;
7589 goto check_prefix;
7590 }
7591 break;
7592 case 2:
7593 if ((i.tm.base_opcode & 0xff0000) != 0)
7594 {
7595 prefix = (i.tm.base_opcode >> 16) & 0xff;
7596 if (i.tm.cpu_flags.bitfield.cpupadlock)
7597 {
7598 check_prefix:
7599 if (prefix != REPE_PREFIX_OPCODE
7600 || (i.prefix[REP_PREFIX]
7601 != REPE_PREFIX_OPCODE))
7602 add_prefix (prefix);
7603 }
7604 else
7605 add_prefix (prefix);
7606 }
7607 break;
7608 case 1:
7609 break;
7610 case 0:
7611 /* Check for pseudo prefixes. */
7612 as_bad_where (insn_start_frag->fr_file,
7613 insn_start_frag->fr_line,
7614 _("pseudo prefix without instruction"));
7615 return;
7616 default:
7617 abort ();
7618 }
7619
7620 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7621 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7622 R_X86_64_GOTTPOFF relocation so that linker can safely
7623 perform IE->LE optimization. */
7624 if (x86_elf_abi == X86_64_X32_ABI
7625 && i.operands == 2
7626 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7627 && i.prefix[REX_PREFIX] == 0)
7628 add_prefix (REX_OPCODE);
7629 #endif
7630
7631 /* The prefix bytes. */
7632 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7633 if (*q)
7634 FRAG_APPEND_1_CHAR (*q);
7635 }
7636 else
7637 {
7638 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7639 if (*q)
7640 switch (j)
7641 {
7642 case REX_PREFIX:
7643 /* REX byte is encoded in VEX prefix. */
7644 break;
7645 case SEG_PREFIX:
7646 case ADDR_PREFIX:
7647 FRAG_APPEND_1_CHAR (*q);
7648 break;
7649 default:
7650 /* There should be no other prefixes for instructions
7651 with VEX prefix. */
7652 abort ();
7653 }
7654
7655 /* For EVEX instructions i.vrex should become 0 after
7656 build_evex_prefix. For VEX instructions upper 16 registers
7657 aren't available, so VREX should be 0. */
7658 if (i.vrex)
7659 abort ();
7660 /* Now the VEX prefix. */
7661 p = frag_more (i.vex.length);
7662 for (j = 0; j < i.vex.length; j++)
7663 p[j] = i.vex.bytes[j];
7664 }
7665
7666 /* Now the opcode; be careful about word order here! */
7667 if (i.tm.opcode_length == 1)
7668 {
7669 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7670 }
7671 else
7672 {
7673 switch (i.tm.opcode_length)
7674 {
7675 case 4:
7676 p = frag_more (4);
7677 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7678 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7679 break;
7680 case 3:
7681 p = frag_more (3);
7682 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7683 break;
7684 case 2:
7685 p = frag_more (2);
7686 break;
7687 default:
7688 abort ();
7689 break;
7690 }
7691
7692 /* Put out high byte first: can't use md_number_to_chars! */
7693 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7694 *p = i.tm.base_opcode & 0xff;
7695 }
7696
7697 /* Now the modrm byte and sib byte (if present). */
7698 if (i.tm.opcode_modifier.modrm)
7699 {
7700 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7701 | i.rm.reg << 3
7702 | i.rm.mode << 6));
7703 /* If i.rm.regmem == ESP (4)
7704 && i.rm.mode != (Register mode)
7705 && not 16 bit
7706 ==> need second modrm byte. */
7707 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7708 && i.rm.mode != 3
7709 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7710 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7711 | i.sib.index << 3
7712 | i.sib.scale << 6));
7713 }
7714
7715 if (i.disp_operands)
7716 output_disp (insn_start_frag, insn_start_off);
7717
7718 if (i.imm_operands)
7719 output_imm (insn_start_frag, insn_start_off);
7720 }
7721
7722 #ifdef DEBUG386
7723 if (flag_debug)
7724 {
7725 pi ("" /*line*/, &i);
7726 }
7727 #endif /* DEBUG386 */
7728 }
7729
7730 /* Return the size of the displacement operand N. */
7731
7732 static int
7733 disp_size (unsigned int n)
7734 {
7735 int size = 4;
7736
7737 if (i.types[n].bitfield.disp64)
7738 size = 8;
7739 else if (i.types[n].bitfield.disp8)
7740 size = 1;
7741 else if (i.types[n].bitfield.disp16)
7742 size = 2;
7743 return size;
7744 }
7745
7746 /* Return the size of the immediate operand N. */
7747
7748 static int
7749 imm_size (unsigned int n)
7750 {
7751 int size = 4;
7752 if (i.types[n].bitfield.imm64)
7753 size = 8;
7754 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7755 size = 1;
7756 else if (i.types[n].bitfield.imm16)
7757 size = 2;
7758 return size;
7759 }
7760
7761 static void
7762 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7763 {
7764 char *p;
7765 unsigned int n;
7766
7767 for (n = 0; n < i.operands; n++)
7768 {
7769 if (operand_type_check (i.types[n], disp))
7770 {
7771 if (i.op[n].disps->X_op == O_constant)
7772 {
7773 int size = disp_size (n);
7774 offsetT val = i.op[n].disps->X_add_number;
7775
7776 val = offset_in_range (val >> i.memshift, size);
7777 p = frag_more (size);
7778 md_number_to_chars (p, val, size);
7779 }
7780 else
7781 {
7782 enum bfd_reloc_code_real reloc_type;
7783 int size = disp_size (n);
7784 int sign = i.types[n].bitfield.disp32s;
7785 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7786 fixS *fixP;
7787
7788 /* We can't have 8 bit displacement here. */
7789 gas_assert (!i.types[n].bitfield.disp8);
7790
7791 /* The PC relative address is computed relative
7792 to the instruction boundary, so in case immediate
7793 fields follows, we need to adjust the value. */
7794 if (pcrel && i.imm_operands)
7795 {
7796 unsigned int n1;
7797 int sz = 0;
7798
7799 for (n1 = 0; n1 < i.operands; n1++)
7800 if (operand_type_check (i.types[n1], imm))
7801 {
7802 /* Only one immediate is allowed for PC
7803 relative address. */
7804 gas_assert (sz == 0);
7805 sz = imm_size (n1);
7806 i.op[n].disps->X_add_number -= sz;
7807 }
7808 /* We should find the immediate. */
7809 gas_assert (sz != 0);
7810 }
7811
7812 p = frag_more (size);
7813 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7814 if (GOT_symbol
7815 && GOT_symbol == i.op[n].disps->X_add_symbol
7816 && (((reloc_type == BFD_RELOC_32
7817 || reloc_type == BFD_RELOC_X86_64_32S
7818 || (reloc_type == BFD_RELOC_64
7819 && object_64bit))
7820 && (i.op[n].disps->X_op == O_symbol
7821 || (i.op[n].disps->X_op == O_add
7822 && ((symbol_get_value_expression
7823 (i.op[n].disps->X_op_symbol)->X_op)
7824 == O_subtract))))
7825 || reloc_type == BFD_RELOC_32_PCREL))
7826 {
7827 offsetT add;
7828
7829 if (insn_start_frag == frag_now)
7830 add = (p - frag_now->fr_literal) - insn_start_off;
7831 else
7832 {
7833 fragS *fr;
7834
7835 add = insn_start_frag->fr_fix - insn_start_off;
7836 for (fr = insn_start_frag->fr_next;
7837 fr && fr != frag_now; fr = fr->fr_next)
7838 add += fr->fr_fix;
7839 add += p - frag_now->fr_literal;
7840 }
7841
7842 if (!object_64bit)
7843 {
7844 reloc_type = BFD_RELOC_386_GOTPC;
7845 i.op[n].imms->X_add_number += add;
7846 }
7847 else if (reloc_type == BFD_RELOC_64)
7848 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7849 else
7850 /* Don't do the adjustment for x86-64, as there
7851 the pcrel addressing is relative to the _next_
7852 insn, and that is taken care of in other code. */
7853 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7854 }
7855 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7856 size, i.op[n].disps, pcrel,
7857 reloc_type);
7858 /* Check for "call/jmp *mem", "mov mem, %reg",
7859 "test %reg, mem" and "binop mem, %reg" where binop
7860 is one of adc, add, and, cmp, or, sbb, sub, xor
7861 instructions. Always generate R_386_GOT32X for
7862 "sym*GOT" operand in 32-bit mode. */
7863 if ((generate_relax_relocations
7864 || (!object_64bit
7865 && i.rm.mode == 0
7866 && i.rm.regmem == 5))
7867 && (i.rm.mode == 2
7868 || (i.rm.mode == 0 && i.rm.regmem == 5))
7869 && ((i.operands == 1
7870 && i.tm.base_opcode == 0xff
7871 && (i.rm.reg == 2 || i.rm.reg == 4))
7872 || (i.operands == 2
7873 && (i.tm.base_opcode == 0x8b
7874 || i.tm.base_opcode == 0x85
7875 || (i.tm.base_opcode & 0xc7) == 0x03))))
7876 {
7877 if (object_64bit)
7878 {
7879 fixP->fx_tcbit = i.rex != 0;
7880 if (i.base_reg
7881 && (i.base_reg->reg_num == RegRip
7882 || i.base_reg->reg_num == RegEip))
7883 fixP->fx_tcbit2 = 1;
7884 }
7885 else
7886 fixP->fx_tcbit2 = 1;
7887 }
7888 }
7889 }
7890 }
7891 }
7892
7893 static void
7894 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7895 {
7896 char *p;
7897 unsigned int n;
7898
7899 for (n = 0; n < i.operands; n++)
7900 {
7901 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7902 if (i.rounding && (int) n == i.rounding->operand)
7903 continue;
7904
7905 if (operand_type_check (i.types[n], imm))
7906 {
7907 if (i.op[n].imms->X_op == O_constant)
7908 {
7909 int size = imm_size (n);
7910 offsetT val;
7911
7912 val = offset_in_range (i.op[n].imms->X_add_number,
7913 size);
7914 p = frag_more (size);
7915 md_number_to_chars (p, val, size);
7916 }
7917 else
7918 {
7919 /* Not absolute_section.
7920 Need a 32-bit fixup (don't support 8bit
7921 non-absolute imms). Try to support other
7922 sizes ... */
7923 enum bfd_reloc_code_real reloc_type;
7924 int size = imm_size (n);
7925 int sign;
7926
7927 if (i.types[n].bitfield.imm32s
7928 && (i.suffix == QWORD_MNEM_SUFFIX
7929 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7930 sign = 1;
7931 else
7932 sign = 0;
7933
7934 p = frag_more (size);
7935 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7936
7937 /* This is tough to explain. We end up with this one if we
7938 * have operands that look like
7939 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7940 * obtain the absolute address of the GOT, and it is strongly
7941 * preferable from a performance point of view to avoid using
7942 * a runtime relocation for this. The actual sequence of
7943 * instructions often look something like:
7944 *
7945 * call .L66
7946 * .L66:
7947 * popl %ebx
7948 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7949 *
7950 * The call and pop essentially return the absolute address
7951 * of the label .L66 and store it in %ebx. The linker itself
7952 * will ultimately change the first operand of the addl so
7953 * that %ebx points to the GOT, but to keep things simple, the
7954 * .o file must have this operand set so that it generates not
7955 * the absolute address of .L66, but the absolute address of
7956 * itself. This allows the linker itself simply treat a GOTPC
7957 * relocation as asking for a pcrel offset to the GOT to be
7958 * added in, and the addend of the relocation is stored in the
7959 * operand field for the instruction itself.
7960 *
7961 * Our job here is to fix the operand so that it would add
7962 * the correct offset so that %ebx would point to itself. The
7963 * thing that is tricky is that .-.L66 will point to the
7964 * beginning of the instruction, so we need to further modify
7965 * the operand so that it will point to itself. There are
7966 * other cases where you have something like:
7967 *
7968 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7969 *
7970 * and here no correction would be required. Internally in
7971 * the assembler we treat operands of this form as not being
7972 * pcrel since the '.' is explicitly mentioned, and I wonder
7973 * whether it would simplify matters to do it this way. Who
7974 * knows. In earlier versions of the PIC patches, the
7975 * pcrel_adjust field was used to store the correction, but
7976 * since the expression is not pcrel, I felt it would be
7977 * confusing to do it this way. */
7978
7979 if ((reloc_type == BFD_RELOC_32
7980 || reloc_type == BFD_RELOC_X86_64_32S
7981 || reloc_type == BFD_RELOC_64)
7982 && GOT_symbol
7983 && GOT_symbol == i.op[n].imms->X_add_symbol
7984 && (i.op[n].imms->X_op == O_symbol
7985 || (i.op[n].imms->X_op == O_add
7986 && ((symbol_get_value_expression
7987 (i.op[n].imms->X_op_symbol)->X_op)
7988 == O_subtract))))
7989 {
7990 offsetT add;
7991
7992 if (insn_start_frag == frag_now)
7993 add = (p - frag_now->fr_literal) - insn_start_off;
7994 else
7995 {
7996 fragS *fr;
7997
7998 add = insn_start_frag->fr_fix - insn_start_off;
7999 for (fr = insn_start_frag->fr_next;
8000 fr && fr != frag_now; fr = fr->fr_next)
8001 add += fr->fr_fix;
8002 add += p - frag_now->fr_literal;
8003 }
8004
8005 if (!object_64bit)
8006 reloc_type = BFD_RELOC_386_GOTPC;
8007 else if (size == 4)
8008 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8009 else if (size == 8)
8010 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8011 i.op[n].imms->X_add_number += add;
8012 }
8013 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8014 i.op[n].imms, 0, reloc_type);
8015 }
8016 }
8017 }
8018 }
8019 \f
8020 /* x86_cons_fix_new is called via the expression parsing code when a
8021 reloc is needed. We use this hook to get the correct .got reloc. */
8022 static int cons_sign = -1;
8023
8024 void
8025 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8026 expressionS *exp, bfd_reloc_code_real_type r)
8027 {
8028 r = reloc (len, 0, cons_sign, r);
8029
8030 #ifdef TE_PE
8031 if (exp->X_op == O_secrel)
8032 {
8033 exp->X_op = O_symbol;
8034 r = BFD_RELOC_32_SECREL;
8035 }
8036 #endif
8037
8038 fix_new_exp (frag, off, len, exp, 0, r);
8039 }
8040
8041 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8042 purpose of the `.dc.a' internal pseudo-op. */
8043
8044 int
8045 x86_address_bytes (void)
8046 {
8047 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8048 return 4;
8049 return stdoutput->arch_info->bits_per_address / 8;
8050 }
8051
8052 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8053 || defined (LEX_AT)
8054 # define lex_got(reloc, adjust, types) NULL
8055 #else
8056 /* Parse operands of the form
8057 <symbol>@GOTOFF+<nnn>
8058 and similar .plt or .got references.
8059
8060 If we find one, set up the correct relocation in RELOC and copy the
8061 input string, minus the `@GOTOFF' into a malloc'd buffer for
8062 parsing by the calling routine. Return this buffer, and if ADJUST
8063 is non-null set it to the length of the string we removed from the
8064 input line. Otherwise return NULL. */
8065 static char *
8066 lex_got (enum bfd_reloc_code_real *rel,
8067 int *adjust,
8068 i386_operand_type *types)
8069 {
8070 /* Some of the relocations depend on the size of what field is to
8071 be relocated. But in our callers i386_immediate and i386_displacement
8072 we don't yet know the operand size (this will be set by insn
8073 matching). Hence we record the word32 relocation here,
8074 and adjust the reloc according to the real size in reloc(). */
8075 static const struct {
8076 const char *str;
8077 int len;
8078 const enum bfd_reloc_code_real rel[2];
8079 const i386_operand_type types64;
8080 } gotrel[] = {
8081 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8082 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8083 BFD_RELOC_SIZE32 },
8084 OPERAND_TYPE_IMM32_64 },
8085 #endif
8086 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8087 BFD_RELOC_X86_64_PLTOFF64 },
8088 OPERAND_TYPE_IMM64 },
8089 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8090 BFD_RELOC_X86_64_PLT32 },
8091 OPERAND_TYPE_IMM32_32S_DISP32 },
8092 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8093 BFD_RELOC_X86_64_GOTPLT64 },
8094 OPERAND_TYPE_IMM64_DISP64 },
8095 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8096 BFD_RELOC_X86_64_GOTOFF64 },
8097 OPERAND_TYPE_IMM64_DISP64 },
8098 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8099 BFD_RELOC_X86_64_GOTPCREL },
8100 OPERAND_TYPE_IMM32_32S_DISP32 },
8101 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8102 BFD_RELOC_X86_64_TLSGD },
8103 OPERAND_TYPE_IMM32_32S_DISP32 },
8104 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8105 _dummy_first_bfd_reloc_code_real },
8106 OPERAND_TYPE_NONE },
8107 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8108 BFD_RELOC_X86_64_TLSLD },
8109 OPERAND_TYPE_IMM32_32S_DISP32 },
8110 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8111 BFD_RELOC_X86_64_GOTTPOFF },
8112 OPERAND_TYPE_IMM32_32S_DISP32 },
8113 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8114 BFD_RELOC_X86_64_TPOFF32 },
8115 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8116 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8117 _dummy_first_bfd_reloc_code_real },
8118 OPERAND_TYPE_NONE },
8119 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8120 BFD_RELOC_X86_64_DTPOFF32 },
8121 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8122 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8123 _dummy_first_bfd_reloc_code_real },
8124 OPERAND_TYPE_NONE },
8125 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8126 _dummy_first_bfd_reloc_code_real },
8127 OPERAND_TYPE_NONE },
8128 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8129 BFD_RELOC_X86_64_GOT32 },
8130 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8131 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8132 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8133 OPERAND_TYPE_IMM32_32S_DISP32 },
8134 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8135 BFD_RELOC_X86_64_TLSDESC_CALL },
8136 OPERAND_TYPE_IMM32_32S_DISP32 },
8137 };
8138 char *cp;
8139 unsigned int j;
8140
8141 #if defined (OBJ_MAYBE_ELF)
8142 if (!IS_ELF)
8143 return NULL;
8144 #endif
8145
8146 for (cp = input_line_pointer; *cp != '@'; cp++)
8147 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8148 return NULL;
8149
8150 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8151 {
8152 int len = gotrel[j].len;
8153 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8154 {
8155 if (gotrel[j].rel[object_64bit] != 0)
8156 {
8157 int first, second;
8158 char *tmpbuf, *past_reloc;
8159
8160 *rel = gotrel[j].rel[object_64bit];
8161
8162 if (types)
8163 {
8164 if (flag_code != CODE_64BIT)
8165 {
8166 types->bitfield.imm32 = 1;
8167 types->bitfield.disp32 = 1;
8168 }
8169 else
8170 *types = gotrel[j].types64;
8171 }
8172
8173 if (j != 0 && GOT_symbol == NULL)
8174 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8175
8176 /* The length of the first part of our input line. */
8177 first = cp - input_line_pointer;
8178
8179 /* The second part goes from after the reloc token until
8180 (and including) an end_of_line char or comma. */
8181 past_reloc = cp + 1 + len;
8182 cp = past_reloc;
8183 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8184 ++cp;
8185 second = cp + 1 - past_reloc;
8186
8187 /* Allocate and copy string. The trailing NUL shouldn't
8188 be necessary, but be safe. */
8189 tmpbuf = XNEWVEC (char, first + second + 2);
8190 memcpy (tmpbuf, input_line_pointer, first);
8191 if (second != 0 && *past_reloc != ' ')
8192 /* Replace the relocation token with ' ', so that
8193 errors like foo@GOTOFF1 will be detected. */
8194 tmpbuf[first++] = ' ';
8195 else
8196 /* Increment length by 1 if the relocation token is
8197 removed. */
8198 len++;
8199 if (adjust)
8200 *adjust = len;
8201 memcpy (tmpbuf + first, past_reloc, second);
8202 tmpbuf[first + second] = '\0';
8203 return tmpbuf;
8204 }
8205
8206 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8207 gotrel[j].str, 1 << (5 + object_64bit));
8208 return NULL;
8209 }
8210 }
8211
8212 /* Might be a symbol version string. Don't as_bad here. */
8213 return NULL;
8214 }
8215 #endif
8216
8217 #ifdef TE_PE
8218 #ifdef lex_got
8219 #undef lex_got
8220 #endif
8221 /* Parse operands of the form
8222 <symbol>@SECREL32+<nnn>
8223
8224 If we find one, set up the correct relocation in RELOC and copy the
8225 input string, minus the `@SECREL32' into a malloc'd buffer for
8226 parsing by the calling routine. Return this buffer, and if ADJUST
8227 is non-null set it to the length of the string we removed from the
8228 input line. Otherwise return NULL.
8229
8230 This function is copied from the ELF version above adjusted for PE targets. */
8231
8232 static char *
8233 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8234 int *adjust ATTRIBUTE_UNUSED,
8235 i386_operand_type *types)
8236 {
8237 static const struct
8238 {
8239 const char *str;
8240 int len;
8241 const enum bfd_reloc_code_real rel[2];
8242 const i386_operand_type types64;
8243 }
8244 gotrel[] =
8245 {
8246 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8247 BFD_RELOC_32_SECREL },
8248 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8249 };
8250
8251 char *cp;
8252 unsigned j;
8253
8254 for (cp = input_line_pointer; *cp != '@'; cp++)
8255 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8256 return NULL;
8257
8258 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8259 {
8260 int len = gotrel[j].len;
8261
8262 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8263 {
8264 if (gotrel[j].rel[object_64bit] != 0)
8265 {
8266 int first, second;
8267 char *tmpbuf, *past_reloc;
8268
8269 *rel = gotrel[j].rel[object_64bit];
8270 if (adjust)
8271 *adjust = len;
8272
8273 if (types)
8274 {
8275 if (flag_code != CODE_64BIT)
8276 {
8277 types->bitfield.imm32 = 1;
8278 types->bitfield.disp32 = 1;
8279 }
8280 else
8281 *types = gotrel[j].types64;
8282 }
8283
8284 /* The length of the first part of our input line. */
8285 first = cp - input_line_pointer;
8286
8287 /* The second part goes from after the reloc token until
8288 (and including) an end_of_line char or comma. */
8289 past_reloc = cp + 1 + len;
8290 cp = past_reloc;
8291 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8292 ++cp;
8293 second = cp + 1 - past_reloc;
8294
8295 /* Allocate and copy string. The trailing NUL shouldn't
8296 be necessary, but be safe. */
8297 tmpbuf = XNEWVEC (char, first + second + 2);
8298 memcpy (tmpbuf, input_line_pointer, first);
8299 if (second != 0 && *past_reloc != ' ')
8300 /* Replace the relocation token with ' ', so that
8301 errors like foo@SECLREL321 will be detected. */
8302 tmpbuf[first++] = ' ';
8303 memcpy (tmpbuf + first, past_reloc, second);
8304 tmpbuf[first + second] = '\0';
8305 return tmpbuf;
8306 }
8307
8308 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8309 gotrel[j].str, 1 << (5 + object_64bit));
8310 return NULL;
8311 }
8312 }
8313
8314 /* Might be a symbol version string. Don't as_bad here. */
8315 return NULL;
8316 }
8317
8318 #endif /* TE_PE */
8319
8320 bfd_reloc_code_real_type
8321 x86_cons (expressionS *exp, int size)
8322 {
8323 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8324
8325 intel_syntax = -intel_syntax;
8326
8327 exp->X_md = 0;
8328 if (size == 4 || (object_64bit && size == 8))
8329 {
8330 /* Handle @GOTOFF and the like in an expression. */
8331 char *save;
8332 char *gotfree_input_line;
8333 int adjust = 0;
8334
8335 save = input_line_pointer;
8336 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8337 if (gotfree_input_line)
8338 input_line_pointer = gotfree_input_line;
8339
8340 expression (exp);
8341
8342 if (gotfree_input_line)
8343 {
8344 /* expression () has merrily parsed up to the end of line,
8345 or a comma - in the wrong buffer. Transfer how far
8346 input_line_pointer has moved to the right buffer. */
8347 input_line_pointer = (save
8348 + (input_line_pointer - gotfree_input_line)
8349 + adjust);
8350 free (gotfree_input_line);
8351 if (exp->X_op == O_constant
8352 || exp->X_op == O_absent
8353 || exp->X_op == O_illegal
8354 || exp->X_op == O_register
8355 || exp->X_op == O_big)
8356 {
8357 char c = *input_line_pointer;
8358 *input_line_pointer = 0;
8359 as_bad (_("missing or invalid expression `%s'"), save);
8360 *input_line_pointer = c;
8361 }
8362 }
8363 }
8364 else
8365 expression (exp);
8366
8367 intel_syntax = -intel_syntax;
8368
8369 if (intel_syntax)
8370 i386_intel_simplify (exp);
8371
8372 return got_reloc;
8373 }
8374
8375 static void
8376 signed_cons (int size)
8377 {
8378 if (flag_code == CODE_64BIT)
8379 cons_sign = 1;
8380 cons (size);
8381 cons_sign = -1;
8382 }
8383
8384 #ifdef TE_PE
8385 static void
8386 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8387 {
8388 expressionS exp;
8389
8390 do
8391 {
8392 expression (&exp);
8393 if (exp.X_op == O_symbol)
8394 exp.X_op = O_secrel;
8395
8396 emit_expr (&exp, 4);
8397 }
8398 while (*input_line_pointer++ == ',');
8399
8400 input_line_pointer--;
8401 demand_empty_rest_of_line ();
8402 }
8403 #endif
8404
8405 /* Handle Vector operations. */
8406
8407 static char *
8408 check_VecOperations (char *op_string, char *op_end)
8409 {
8410 const reg_entry *mask;
8411 const char *saved;
8412 char *end_op;
8413
8414 while (*op_string
8415 && (op_end == NULL || op_string < op_end))
8416 {
8417 saved = op_string;
8418 if (*op_string == '{')
8419 {
8420 op_string++;
8421
8422 /* Check broadcasts. */
8423 if (strncmp (op_string, "1to", 3) == 0)
8424 {
8425 int bcst_type;
8426
8427 if (i.broadcast)
8428 goto duplicated_vec_op;
8429
8430 op_string += 3;
8431 if (*op_string == '8')
8432 bcst_type = BROADCAST_1TO8;
8433 else if (*op_string == '4')
8434 bcst_type = BROADCAST_1TO4;
8435 else if (*op_string == '2')
8436 bcst_type = BROADCAST_1TO2;
8437 else if (*op_string == '1'
8438 && *(op_string+1) == '6')
8439 {
8440 bcst_type = BROADCAST_1TO16;
8441 op_string++;
8442 }
8443 else
8444 {
8445 as_bad (_("Unsupported broadcast: `%s'"), saved);
8446 return NULL;
8447 }
8448 op_string++;
8449
8450 broadcast_op.type = bcst_type;
8451 broadcast_op.operand = this_operand;
8452 i.broadcast = &broadcast_op;
8453 }
8454 /* Check masking operation. */
8455 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8456 {
8457 /* k0 can't be used for write mask. */
8458 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8459 {
8460 as_bad (_("`%s%s' can't be used for write mask"),
8461 register_prefix, mask->reg_name);
8462 return NULL;
8463 }
8464
8465 if (!i.mask)
8466 {
8467 mask_op.mask = mask;
8468 mask_op.zeroing = 0;
8469 mask_op.operand = this_operand;
8470 i.mask = &mask_op;
8471 }
8472 else
8473 {
8474 if (i.mask->mask)
8475 goto duplicated_vec_op;
8476
8477 i.mask->mask = mask;
8478
8479 /* Only "{z}" is allowed here. No need to check
8480 zeroing mask explicitly. */
8481 if (i.mask->operand != this_operand)
8482 {
8483 as_bad (_("invalid write mask `%s'"), saved);
8484 return NULL;
8485 }
8486 }
8487
8488 op_string = end_op;
8489 }
8490 /* Check zeroing-flag for masking operation. */
8491 else if (*op_string == 'z')
8492 {
8493 if (!i.mask)
8494 {
8495 mask_op.mask = NULL;
8496 mask_op.zeroing = 1;
8497 mask_op.operand = this_operand;
8498 i.mask = &mask_op;
8499 }
8500 else
8501 {
8502 if (i.mask->zeroing)
8503 {
8504 duplicated_vec_op:
8505 as_bad (_("duplicated `%s'"), saved);
8506 return NULL;
8507 }
8508
8509 i.mask->zeroing = 1;
8510
8511 /* Only "{%k}" is allowed here. No need to check mask
8512 register explicitly. */
8513 if (i.mask->operand != this_operand)
8514 {
8515 as_bad (_("invalid zeroing-masking `%s'"),
8516 saved);
8517 return NULL;
8518 }
8519 }
8520
8521 op_string++;
8522 }
8523 else
8524 goto unknown_vec_op;
8525
8526 if (*op_string != '}')
8527 {
8528 as_bad (_("missing `}' in `%s'"), saved);
8529 return NULL;
8530 }
8531 op_string++;
8532
8533 /* Strip whitespace since the addition of pseudo prefixes
8534 changed how the scrubber treats '{'. */
8535 if (is_space_char (*op_string))
8536 ++op_string;
8537
8538 continue;
8539 }
8540 unknown_vec_op:
8541 /* We don't know this one. */
8542 as_bad (_("unknown vector operation: `%s'"), saved);
8543 return NULL;
8544 }
8545
8546 if (i.mask && i.mask->zeroing && !i.mask->mask)
8547 {
8548 as_bad (_("zeroing-masking only allowed with write mask"));
8549 return NULL;
8550 }
8551
8552 return op_string;
8553 }
8554
8555 static int
8556 i386_immediate (char *imm_start)
8557 {
8558 char *save_input_line_pointer;
8559 char *gotfree_input_line;
8560 segT exp_seg = 0;
8561 expressionS *exp;
8562 i386_operand_type types;
8563
8564 operand_type_set (&types, ~0);
8565
8566 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8567 {
8568 as_bad (_("at most %d immediate operands are allowed"),
8569 MAX_IMMEDIATE_OPERANDS);
8570 return 0;
8571 }
8572
8573 exp = &im_expressions[i.imm_operands++];
8574 i.op[this_operand].imms = exp;
8575
8576 if (is_space_char (*imm_start))
8577 ++imm_start;
8578
8579 save_input_line_pointer = input_line_pointer;
8580 input_line_pointer = imm_start;
8581
8582 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8583 if (gotfree_input_line)
8584 input_line_pointer = gotfree_input_line;
8585
8586 exp_seg = expression (exp);
8587
8588 SKIP_WHITESPACE ();
8589
8590 /* Handle vector operations. */
8591 if (*input_line_pointer == '{')
8592 {
8593 input_line_pointer = check_VecOperations (input_line_pointer,
8594 NULL);
8595 if (input_line_pointer == NULL)
8596 return 0;
8597 }
8598
8599 if (*input_line_pointer)
8600 as_bad (_("junk `%s' after expression"), input_line_pointer);
8601
8602 input_line_pointer = save_input_line_pointer;
8603 if (gotfree_input_line)
8604 {
8605 free (gotfree_input_line);
8606
8607 if (exp->X_op == O_constant || exp->X_op == O_register)
8608 exp->X_op = O_illegal;
8609 }
8610
8611 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8612 }
8613
8614 static int
8615 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8616 i386_operand_type types, const char *imm_start)
8617 {
8618 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8619 {
8620 if (imm_start)
8621 as_bad (_("missing or invalid immediate expression `%s'"),
8622 imm_start);
8623 return 0;
8624 }
8625 else if (exp->X_op == O_constant)
8626 {
8627 /* Size it properly later. */
8628 i.types[this_operand].bitfield.imm64 = 1;
8629 /* If not 64bit, sign extend val. */
8630 if (flag_code != CODE_64BIT
8631 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8632 exp->X_add_number
8633 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8634 }
8635 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8636 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8637 && exp_seg != absolute_section
8638 && exp_seg != text_section
8639 && exp_seg != data_section
8640 && exp_seg != bss_section
8641 && exp_seg != undefined_section
8642 && !bfd_is_com_section (exp_seg))
8643 {
8644 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8645 return 0;
8646 }
8647 #endif
8648 else if (!intel_syntax && exp_seg == reg_section)
8649 {
8650 if (imm_start)
8651 as_bad (_("illegal immediate register operand %s"), imm_start);
8652 return 0;
8653 }
8654 else
8655 {
8656 /* This is an address. The size of the address will be
8657 determined later, depending on destination register,
8658 suffix, or the default for the section. */
8659 i.types[this_operand].bitfield.imm8 = 1;
8660 i.types[this_operand].bitfield.imm16 = 1;
8661 i.types[this_operand].bitfield.imm32 = 1;
8662 i.types[this_operand].bitfield.imm32s = 1;
8663 i.types[this_operand].bitfield.imm64 = 1;
8664 i.types[this_operand] = operand_type_and (i.types[this_operand],
8665 types);
8666 }
8667
8668 return 1;
8669 }
8670
8671 static char *
8672 i386_scale (char *scale)
8673 {
8674 offsetT val;
8675 char *save = input_line_pointer;
8676
8677 input_line_pointer = scale;
8678 val = get_absolute_expression ();
8679
8680 switch (val)
8681 {
8682 case 1:
8683 i.log2_scale_factor = 0;
8684 break;
8685 case 2:
8686 i.log2_scale_factor = 1;
8687 break;
8688 case 4:
8689 i.log2_scale_factor = 2;
8690 break;
8691 case 8:
8692 i.log2_scale_factor = 3;
8693 break;
8694 default:
8695 {
8696 char sep = *input_line_pointer;
8697
8698 *input_line_pointer = '\0';
8699 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8700 scale);
8701 *input_line_pointer = sep;
8702 input_line_pointer = save;
8703 return NULL;
8704 }
8705 }
8706 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8707 {
8708 as_warn (_("scale factor of %d without an index register"),
8709 1 << i.log2_scale_factor);
8710 i.log2_scale_factor = 0;
8711 }
8712 scale = input_line_pointer;
8713 input_line_pointer = save;
8714 return scale;
8715 }
8716
8717 static int
8718 i386_displacement (char *disp_start, char *disp_end)
8719 {
8720 expressionS *exp;
8721 segT exp_seg = 0;
8722 char *save_input_line_pointer;
8723 char *gotfree_input_line;
8724 int override;
8725 i386_operand_type bigdisp, types = anydisp;
8726 int ret;
8727
8728 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8729 {
8730 as_bad (_("at most %d displacement operands are allowed"),
8731 MAX_MEMORY_OPERANDS);
8732 return 0;
8733 }
8734
8735 operand_type_set (&bigdisp, 0);
8736 if ((i.types[this_operand].bitfield.jumpabsolute)
8737 || (!current_templates->start->opcode_modifier.jump
8738 && !current_templates->start->opcode_modifier.jumpdword))
8739 {
8740 bigdisp.bitfield.disp32 = 1;
8741 override = (i.prefix[ADDR_PREFIX] != 0);
8742 if (flag_code == CODE_64BIT)
8743 {
8744 if (!override)
8745 {
8746 bigdisp.bitfield.disp32s = 1;
8747 bigdisp.bitfield.disp64 = 1;
8748 }
8749 }
8750 else if ((flag_code == CODE_16BIT) ^ override)
8751 {
8752 bigdisp.bitfield.disp32 = 0;
8753 bigdisp.bitfield.disp16 = 1;
8754 }
8755 }
8756 else
8757 {
8758 /* For PC-relative branches, the width of the displacement
8759 is dependent upon data size, not address size. */
8760 override = (i.prefix[DATA_PREFIX] != 0);
8761 if (flag_code == CODE_64BIT)
8762 {
8763 if (override || i.suffix == WORD_MNEM_SUFFIX)
8764 bigdisp.bitfield.disp16 = 1;
8765 else
8766 {
8767 bigdisp.bitfield.disp32 = 1;
8768 bigdisp.bitfield.disp32s = 1;
8769 }
8770 }
8771 else
8772 {
8773 if (!override)
8774 override = (i.suffix == (flag_code != CODE_16BIT
8775 ? WORD_MNEM_SUFFIX
8776 : LONG_MNEM_SUFFIX));
8777 bigdisp.bitfield.disp32 = 1;
8778 if ((flag_code == CODE_16BIT) ^ override)
8779 {
8780 bigdisp.bitfield.disp32 = 0;
8781 bigdisp.bitfield.disp16 = 1;
8782 }
8783 }
8784 }
8785 i.types[this_operand] = operand_type_or (i.types[this_operand],
8786 bigdisp);
8787
8788 exp = &disp_expressions[i.disp_operands];
8789 i.op[this_operand].disps = exp;
8790 i.disp_operands++;
8791 save_input_line_pointer = input_line_pointer;
8792 input_line_pointer = disp_start;
8793 END_STRING_AND_SAVE (disp_end);
8794
8795 #ifndef GCC_ASM_O_HACK
8796 #define GCC_ASM_O_HACK 0
8797 #endif
8798 #if GCC_ASM_O_HACK
8799 END_STRING_AND_SAVE (disp_end + 1);
8800 if (i.types[this_operand].bitfield.baseIndex
8801 && displacement_string_end[-1] == '+')
8802 {
8803 /* This hack is to avoid a warning when using the "o"
8804 constraint within gcc asm statements.
8805 For instance:
8806
8807 #define _set_tssldt_desc(n,addr,limit,type) \
8808 __asm__ __volatile__ ( \
8809 "movw %w2,%0\n\t" \
8810 "movw %w1,2+%0\n\t" \
8811 "rorl $16,%1\n\t" \
8812 "movb %b1,4+%0\n\t" \
8813 "movb %4,5+%0\n\t" \
8814 "movb $0,6+%0\n\t" \
8815 "movb %h1,7+%0\n\t" \
8816 "rorl $16,%1" \
8817 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8818
8819 This works great except that the output assembler ends
8820 up looking a bit weird if it turns out that there is
8821 no offset. You end up producing code that looks like:
8822
8823 #APP
8824 movw $235,(%eax)
8825 movw %dx,2+(%eax)
8826 rorl $16,%edx
8827 movb %dl,4+(%eax)
8828 movb $137,5+(%eax)
8829 movb $0,6+(%eax)
8830 movb %dh,7+(%eax)
8831 rorl $16,%edx
8832 #NO_APP
8833
8834 So here we provide the missing zero. */
8835
8836 *displacement_string_end = '0';
8837 }
8838 #endif
8839 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8840 if (gotfree_input_line)
8841 input_line_pointer = gotfree_input_line;
8842
8843 exp_seg = expression (exp);
8844
8845 SKIP_WHITESPACE ();
8846 if (*input_line_pointer)
8847 as_bad (_("junk `%s' after expression"), input_line_pointer);
8848 #if GCC_ASM_O_HACK
8849 RESTORE_END_STRING (disp_end + 1);
8850 #endif
8851 input_line_pointer = save_input_line_pointer;
8852 if (gotfree_input_line)
8853 {
8854 free (gotfree_input_line);
8855
8856 if (exp->X_op == O_constant || exp->X_op == O_register)
8857 exp->X_op = O_illegal;
8858 }
8859
8860 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8861
8862 RESTORE_END_STRING (disp_end);
8863
8864 return ret;
8865 }
8866
8867 static int
8868 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8869 i386_operand_type types, const char *disp_start)
8870 {
8871 i386_operand_type bigdisp;
8872 int ret = 1;
8873
8874 /* We do this to make sure that the section symbol is in
8875 the symbol table. We will ultimately change the relocation
8876 to be relative to the beginning of the section. */
8877 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8878 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8879 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8880 {
8881 if (exp->X_op != O_symbol)
8882 goto inv_disp;
8883
8884 if (S_IS_LOCAL (exp->X_add_symbol)
8885 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8886 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8887 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8888 exp->X_op = O_subtract;
8889 exp->X_op_symbol = GOT_symbol;
8890 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8891 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8892 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8893 i.reloc[this_operand] = BFD_RELOC_64;
8894 else
8895 i.reloc[this_operand] = BFD_RELOC_32;
8896 }
8897
8898 else if (exp->X_op == O_absent
8899 || exp->X_op == O_illegal
8900 || exp->X_op == O_big)
8901 {
8902 inv_disp:
8903 as_bad (_("missing or invalid displacement expression `%s'"),
8904 disp_start);
8905 ret = 0;
8906 }
8907
8908 else if (flag_code == CODE_64BIT
8909 && !i.prefix[ADDR_PREFIX]
8910 && exp->X_op == O_constant)
8911 {
8912 /* Since displacement is signed extended to 64bit, don't allow
8913 disp32 and turn off disp32s if they are out of range. */
8914 i.types[this_operand].bitfield.disp32 = 0;
8915 if (!fits_in_signed_long (exp->X_add_number))
8916 {
8917 i.types[this_operand].bitfield.disp32s = 0;
8918 if (i.types[this_operand].bitfield.baseindex)
8919 {
8920 as_bad (_("0x%lx out range of signed 32bit displacement"),
8921 (long) exp->X_add_number);
8922 ret = 0;
8923 }
8924 }
8925 }
8926
8927 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8928 else if (exp->X_op != O_constant
8929 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8930 && exp_seg != absolute_section
8931 && exp_seg != text_section
8932 && exp_seg != data_section
8933 && exp_seg != bss_section
8934 && exp_seg != undefined_section
8935 && !bfd_is_com_section (exp_seg))
8936 {
8937 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8938 ret = 0;
8939 }
8940 #endif
8941
8942 /* Check if this is a displacement only operand. */
8943 bigdisp = i.types[this_operand];
8944 bigdisp.bitfield.disp8 = 0;
8945 bigdisp.bitfield.disp16 = 0;
8946 bigdisp.bitfield.disp32 = 0;
8947 bigdisp.bitfield.disp32s = 0;
8948 bigdisp.bitfield.disp64 = 0;
8949 if (operand_type_all_zero (&bigdisp))
8950 i.types[this_operand] = operand_type_and (i.types[this_operand],
8951 types);
8952
8953 return ret;
8954 }
8955
8956 /* Return the active addressing mode, taking address override and
8957 registers forming the address into consideration. Update the
8958 address override prefix if necessary. */
8959
8960 static enum flag_code
8961 i386_addressing_mode (void)
8962 {
8963 enum flag_code addr_mode;
8964
8965 if (i.prefix[ADDR_PREFIX])
8966 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8967 else
8968 {
8969 addr_mode = flag_code;
8970
8971 #if INFER_ADDR_PREFIX
8972 if (i.mem_operands == 0)
8973 {
8974 /* Infer address prefix from the first memory operand. */
8975 const reg_entry *addr_reg = i.base_reg;
8976
8977 if (addr_reg == NULL)
8978 addr_reg = i.index_reg;
8979
8980 if (addr_reg)
8981 {
8982 if (addr_reg->reg_num == RegEip
8983 || addr_reg->reg_num == RegEiz
8984 || addr_reg->reg_type.bitfield.dword)
8985 addr_mode = CODE_32BIT;
8986 else if (flag_code != CODE_64BIT
8987 && addr_reg->reg_type.bitfield.word)
8988 addr_mode = CODE_16BIT;
8989
8990 if (addr_mode != flag_code)
8991 {
8992 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8993 i.prefixes += 1;
8994 /* Change the size of any displacement too. At most one
8995 of Disp16 or Disp32 is set.
8996 FIXME. There doesn't seem to be any real need for
8997 separate Disp16 and Disp32 flags. The same goes for
8998 Imm16 and Imm32. Removing them would probably clean
8999 up the code quite a lot. */
9000 if (flag_code != CODE_64BIT
9001 && (i.types[this_operand].bitfield.disp16
9002 || i.types[this_operand].bitfield.disp32))
9003 i.types[this_operand]
9004 = operand_type_xor (i.types[this_operand], disp16_32);
9005 }
9006 }
9007 }
9008 #endif
9009 }
9010
9011 return addr_mode;
9012 }
9013
9014 /* Make sure the memory operand we've been dealt is valid.
9015 Return 1 on success, 0 on a failure. */
9016
9017 static int
9018 i386_index_check (const char *operand_string)
9019 {
9020 const char *kind = "base/index";
9021 enum flag_code addr_mode = i386_addressing_mode ();
9022
9023 if (current_templates->start->opcode_modifier.isstring
9024 && !current_templates->start->opcode_modifier.immext
9025 && (current_templates->end[-1].opcode_modifier.isstring
9026 || i.mem_operands))
9027 {
9028 /* Memory operands of string insns are special in that they only allow
9029 a single register (rDI, rSI, or rBX) as their memory address. */
9030 const reg_entry *expected_reg;
9031 static const char *di_si[][2] =
9032 {
9033 { "esi", "edi" },
9034 { "si", "di" },
9035 { "rsi", "rdi" }
9036 };
9037 static const char *bx[] = { "ebx", "bx", "rbx" };
9038
9039 kind = "string address";
9040
9041 if (current_templates->start->opcode_modifier.repprefixok)
9042 {
9043 i386_operand_type type = current_templates->end[-1].operand_types[0];
9044
9045 if (!type.bitfield.baseindex
9046 || ((!i.mem_operands != !intel_syntax)
9047 && current_templates->end[-1].operand_types[1]
9048 .bitfield.baseindex))
9049 type = current_templates->end[-1].operand_types[1];
9050 expected_reg = hash_find (reg_hash,
9051 di_si[addr_mode][type.bitfield.esseg]);
9052
9053 }
9054 else
9055 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9056
9057 if (i.base_reg != expected_reg
9058 || i.index_reg
9059 || operand_type_check (i.types[this_operand], disp))
9060 {
9061 /* The second memory operand must have the same size as
9062 the first one. */
9063 if (i.mem_operands
9064 && i.base_reg
9065 && !((addr_mode == CODE_64BIT
9066 && i.base_reg->reg_type.bitfield.qword)
9067 || (addr_mode == CODE_32BIT
9068 ? i.base_reg->reg_type.bitfield.dword
9069 : i.base_reg->reg_type.bitfield.word)))
9070 goto bad_address;
9071
9072 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9073 operand_string,
9074 intel_syntax ? '[' : '(',
9075 register_prefix,
9076 expected_reg->reg_name,
9077 intel_syntax ? ']' : ')');
9078 return 1;
9079 }
9080 else
9081 return 1;
9082
9083 bad_address:
9084 as_bad (_("`%s' is not a valid %s expression"),
9085 operand_string, kind);
9086 return 0;
9087 }
9088 else
9089 {
9090 if (addr_mode != CODE_16BIT)
9091 {
9092 /* 32-bit/64-bit checks. */
9093 if ((i.base_reg
9094 && (addr_mode == CODE_64BIT
9095 ? !i.base_reg->reg_type.bitfield.qword
9096 : !i.base_reg->reg_type.bitfield.dword)
9097 && (i.index_reg
9098 || (i.base_reg->reg_num
9099 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9100 || (i.index_reg
9101 && !i.index_reg->reg_type.bitfield.xmmword
9102 && !i.index_reg->reg_type.bitfield.ymmword
9103 && !i.index_reg->reg_type.bitfield.zmmword
9104 && ((addr_mode == CODE_64BIT
9105 ? !(i.index_reg->reg_type.bitfield.qword
9106 || i.index_reg->reg_num == RegRiz)
9107 : !(i.index_reg->reg_type.bitfield.dword
9108 || i.index_reg->reg_num == RegEiz))
9109 || !i.index_reg->reg_type.bitfield.baseindex)))
9110 goto bad_address;
9111
9112 /* bndmk, bndldx, and bndstx have special restrictions. */
9113 if (current_templates->start->base_opcode == 0xf30f1b
9114 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9115 {
9116 /* They cannot use RIP-relative addressing. */
9117 if (i.base_reg && i.base_reg->reg_num == RegRip)
9118 {
9119 as_bad (_("`%s' cannot be used here"), operand_string);
9120 return 0;
9121 }
9122
9123 /* bndldx and bndstx ignore their scale factor. */
9124 if (current_templates->start->base_opcode != 0xf30f1b
9125 && i.log2_scale_factor)
9126 as_warn (_("register scaling is being ignored here"));
9127 }
9128 }
9129 else
9130 {
9131 /* 16-bit checks. */
9132 if ((i.base_reg
9133 && (!i.base_reg->reg_type.bitfield.word
9134 || !i.base_reg->reg_type.bitfield.baseindex))
9135 || (i.index_reg
9136 && (!i.index_reg->reg_type.bitfield.word
9137 || !i.index_reg->reg_type.bitfield.baseindex
9138 || !(i.base_reg
9139 && i.base_reg->reg_num < 6
9140 && i.index_reg->reg_num >= 6
9141 && i.log2_scale_factor == 0))))
9142 goto bad_address;
9143 }
9144 }
9145 return 1;
9146 }
9147
9148 /* Handle vector immediates. */
9149
9150 static int
9151 RC_SAE_immediate (const char *imm_start)
9152 {
9153 unsigned int match_found, j;
9154 const char *pstr = imm_start;
9155 expressionS *exp;
9156
9157 if (*pstr != '{')
9158 return 0;
9159
9160 pstr++;
9161 match_found = 0;
9162 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9163 {
9164 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9165 {
9166 if (!i.rounding)
9167 {
9168 rc_op.type = RC_NamesTable[j].type;
9169 rc_op.operand = this_operand;
9170 i.rounding = &rc_op;
9171 }
9172 else
9173 {
9174 as_bad (_("duplicated `%s'"), imm_start);
9175 return 0;
9176 }
9177 pstr += RC_NamesTable[j].len;
9178 match_found = 1;
9179 break;
9180 }
9181 }
9182 if (!match_found)
9183 return 0;
9184
9185 if (*pstr++ != '}')
9186 {
9187 as_bad (_("Missing '}': '%s'"), imm_start);
9188 return 0;
9189 }
9190 /* RC/SAE immediate string should contain nothing more. */;
9191 if (*pstr != 0)
9192 {
9193 as_bad (_("Junk after '}': '%s'"), imm_start);
9194 return 0;
9195 }
9196
9197 exp = &im_expressions[i.imm_operands++];
9198 i.op[this_operand].imms = exp;
9199
9200 exp->X_op = O_constant;
9201 exp->X_add_number = 0;
9202 exp->X_add_symbol = (symbolS *) 0;
9203 exp->X_op_symbol = (symbolS *) 0;
9204
9205 i.types[this_operand].bitfield.imm8 = 1;
9206 return 1;
9207 }
9208
9209 /* Only string instructions can have a second memory operand, so
9210 reduce current_templates to just those if it contains any. */
9211 static int
9212 maybe_adjust_templates (void)
9213 {
9214 const insn_template *t;
9215
9216 gas_assert (i.mem_operands == 1);
9217
9218 for (t = current_templates->start; t < current_templates->end; ++t)
9219 if (t->opcode_modifier.isstring)
9220 break;
9221
9222 if (t < current_templates->end)
9223 {
9224 static templates aux_templates;
9225 bfd_boolean recheck;
9226
9227 aux_templates.start = t;
9228 for (; t < current_templates->end; ++t)
9229 if (!t->opcode_modifier.isstring)
9230 break;
9231 aux_templates.end = t;
9232
9233 /* Determine whether to re-check the first memory operand. */
9234 recheck = (aux_templates.start != current_templates->start
9235 || t != current_templates->end);
9236
9237 current_templates = &aux_templates;
9238
9239 if (recheck)
9240 {
9241 i.mem_operands = 0;
9242 if (i.memop1_string != NULL
9243 && i386_index_check (i.memop1_string) == 0)
9244 return 0;
9245 i.mem_operands = 1;
9246 }
9247 }
9248
9249 return 1;
9250 }
9251
9252 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9253 on error. */
9254
9255 static int
9256 i386_att_operand (char *operand_string)
9257 {
9258 const reg_entry *r;
9259 char *end_op;
9260 char *op_string = operand_string;
9261
9262 if (is_space_char (*op_string))
9263 ++op_string;
9264
9265 /* We check for an absolute prefix (differentiating,
9266 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9267 if (*op_string == ABSOLUTE_PREFIX)
9268 {
9269 ++op_string;
9270 if (is_space_char (*op_string))
9271 ++op_string;
9272 i.types[this_operand].bitfield.jumpabsolute = 1;
9273 }
9274
9275 /* Check if operand is a register. */
9276 if ((r = parse_register (op_string, &end_op)) != NULL)
9277 {
9278 i386_operand_type temp;
9279
9280 /* Check for a segment override by searching for ':' after a
9281 segment register. */
9282 op_string = end_op;
9283 if (is_space_char (*op_string))
9284 ++op_string;
9285 if (*op_string == ':'
9286 && (r->reg_type.bitfield.sreg2
9287 || r->reg_type.bitfield.sreg3))
9288 {
9289 switch (r->reg_num)
9290 {
9291 case 0:
9292 i.seg[i.mem_operands] = &es;
9293 break;
9294 case 1:
9295 i.seg[i.mem_operands] = &cs;
9296 break;
9297 case 2:
9298 i.seg[i.mem_operands] = &ss;
9299 break;
9300 case 3:
9301 i.seg[i.mem_operands] = &ds;
9302 break;
9303 case 4:
9304 i.seg[i.mem_operands] = &fs;
9305 break;
9306 case 5:
9307 i.seg[i.mem_operands] = &gs;
9308 break;
9309 }
9310
9311 /* Skip the ':' and whitespace. */
9312 ++op_string;
9313 if (is_space_char (*op_string))
9314 ++op_string;
9315
9316 if (!is_digit_char (*op_string)
9317 && !is_identifier_char (*op_string)
9318 && *op_string != '('
9319 && *op_string != ABSOLUTE_PREFIX)
9320 {
9321 as_bad (_("bad memory operand `%s'"), op_string);
9322 return 0;
9323 }
9324 /* Handle case of %es:*foo. */
9325 if (*op_string == ABSOLUTE_PREFIX)
9326 {
9327 ++op_string;
9328 if (is_space_char (*op_string))
9329 ++op_string;
9330 i.types[this_operand].bitfield.jumpabsolute = 1;
9331 }
9332 goto do_memory_reference;
9333 }
9334
9335 /* Handle vector operations. */
9336 if (*op_string == '{')
9337 {
9338 op_string = check_VecOperations (op_string, NULL);
9339 if (op_string == NULL)
9340 return 0;
9341 }
9342
9343 if (*op_string)
9344 {
9345 as_bad (_("junk `%s' after register"), op_string);
9346 return 0;
9347 }
9348 temp = r->reg_type;
9349 temp.bitfield.baseindex = 0;
9350 i.types[this_operand] = operand_type_or (i.types[this_operand],
9351 temp);
9352 i.types[this_operand].bitfield.unspecified = 0;
9353 i.op[this_operand].regs = r;
9354 i.reg_operands++;
9355 }
9356 else if (*op_string == REGISTER_PREFIX)
9357 {
9358 as_bad (_("bad register name `%s'"), op_string);
9359 return 0;
9360 }
9361 else if (*op_string == IMMEDIATE_PREFIX)
9362 {
9363 ++op_string;
9364 if (i.types[this_operand].bitfield.jumpabsolute)
9365 {
9366 as_bad (_("immediate operand illegal with absolute jump"));
9367 return 0;
9368 }
9369 if (!i386_immediate (op_string))
9370 return 0;
9371 }
9372 else if (RC_SAE_immediate (operand_string))
9373 {
9374 /* If it is a RC or SAE immediate, do nothing. */
9375 ;
9376 }
9377 else if (is_digit_char (*op_string)
9378 || is_identifier_char (*op_string)
9379 || *op_string == '"'
9380 || *op_string == '(')
9381 {
9382 /* This is a memory reference of some sort. */
9383 char *base_string;
9384
9385 /* Start and end of displacement string expression (if found). */
9386 char *displacement_string_start;
9387 char *displacement_string_end;
9388 char *vop_start;
9389
9390 do_memory_reference:
9391 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9392 return 0;
9393 if ((i.mem_operands == 1
9394 && !current_templates->start->opcode_modifier.isstring)
9395 || i.mem_operands == 2)
9396 {
9397 as_bad (_("too many memory references for `%s'"),
9398 current_templates->start->name);
9399 return 0;
9400 }
9401
9402 /* Check for base index form. We detect the base index form by
9403 looking for an ')' at the end of the operand, searching
9404 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9405 after the '('. */
9406 base_string = op_string + strlen (op_string);
9407
9408 /* Handle vector operations. */
9409 vop_start = strchr (op_string, '{');
9410 if (vop_start && vop_start < base_string)
9411 {
9412 if (check_VecOperations (vop_start, base_string) == NULL)
9413 return 0;
9414 base_string = vop_start;
9415 }
9416
9417 --base_string;
9418 if (is_space_char (*base_string))
9419 --base_string;
9420
9421 /* If we only have a displacement, set-up for it to be parsed later. */
9422 displacement_string_start = op_string;
9423 displacement_string_end = base_string + 1;
9424
9425 if (*base_string == ')')
9426 {
9427 char *temp_string;
9428 unsigned int parens_balanced = 1;
9429 /* We've already checked that the number of left & right ()'s are
9430 equal, so this loop will not be infinite. */
9431 do
9432 {
9433 base_string--;
9434 if (*base_string == ')')
9435 parens_balanced++;
9436 if (*base_string == '(')
9437 parens_balanced--;
9438 }
9439 while (parens_balanced);
9440
9441 temp_string = base_string;
9442
9443 /* Skip past '(' and whitespace. */
9444 ++base_string;
9445 if (is_space_char (*base_string))
9446 ++base_string;
9447
9448 if (*base_string == ','
9449 || ((i.base_reg = parse_register (base_string, &end_op))
9450 != NULL))
9451 {
9452 displacement_string_end = temp_string;
9453
9454 i.types[this_operand].bitfield.baseindex = 1;
9455
9456 if (i.base_reg)
9457 {
9458 base_string = end_op;
9459 if (is_space_char (*base_string))
9460 ++base_string;
9461 }
9462
9463 /* There may be an index reg or scale factor here. */
9464 if (*base_string == ',')
9465 {
9466 ++base_string;
9467 if (is_space_char (*base_string))
9468 ++base_string;
9469
9470 if ((i.index_reg = parse_register (base_string, &end_op))
9471 != NULL)
9472 {
9473 base_string = end_op;
9474 if (is_space_char (*base_string))
9475 ++base_string;
9476 if (*base_string == ',')
9477 {
9478 ++base_string;
9479 if (is_space_char (*base_string))
9480 ++base_string;
9481 }
9482 else if (*base_string != ')')
9483 {
9484 as_bad (_("expecting `,' or `)' "
9485 "after index register in `%s'"),
9486 operand_string);
9487 return 0;
9488 }
9489 }
9490 else if (*base_string == REGISTER_PREFIX)
9491 {
9492 end_op = strchr (base_string, ',');
9493 if (end_op)
9494 *end_op = '\0';
9495 as_bad (_("bad register name `%s'"), base_string);
9496 return 0;
9497 }
9498
9499 /* Check for scale factor. */
9500 if (*base_string != ')')
9501 {
9502 char *end_scale = i386_scale (base_string);
9503
9504 if (!end_scale)
9505 return 0;
9506
9507 base_string = end_scale;
9508 if (is_space_char (*base_string))
9509 ++base_string;
9510 if (*base_string != ')')
9511 {
9512 as_bad (_("expecting `)' "
9513 "after scale factor in `%s'"),
9514 operand_string);
9515 return 0;
9516 }
9517 }
9518 else if (!i.index_reg)
9519 {
9520 as_bad (_("expecting index register or scale factor "
9521 "after `,'; got '%c'"),
9522 *base_string);
9523 return 0;
9524 }
9525 }
9526 else if (*base_string != ')')
9527 {
9528 as_bad (_("expecting `,' or `)' "
9529 "after base register in `%s'"),
9530 operand_string);
9531 return 0;
9532 }
9533 }
9534 else if (*base_string == REGISTER_PREFIX)
9535 {
9536 end_op = strchr (base_string, ',');
9537 if (end_op)
9538 *end_op = '\0';
9539 as_bad (_("bad register name `%s'"), base_string);
9540 return 0;
9541 }
9542 }
9543
9544 /* If there's an expression beginning the operand, parse it,
9545 assuming displacement_string_start and
9546 displacement_string_end are meaningful. */
9547 if (displacement_string_start != displacement_string_end)
9548 {
9549 if (!i386_displacement (displacement_string_start,
9550 displacement_string_end))
9551 return 0;
9552 }
9553
9554 /* Special case for (%dx) while doing input/output op. */
9555 if (i.base_reg
9556 && operand_type_equal (&i.base_reg->reg_type,
9557 &reg16_inoutportreg)
9558 && i.index_reg == 0
9559 && i.log2_scale_factor == 0
9560 && i.seg[i.mem_operands] == 0
9561 && !operand_type_check (i.types[this_operand], disp))
9562 {
9563 i.types[this_operand] = inoutportreg;
9564 return 1;
9565 }
9566
9567 if (i386_index_check (operand_string) == 0)
9568 return 0;
9569 i.types[this_operand].bitfield.mem = 1;
9570 if (i.mem_operands == 0)
9571 i.memop1_string = xstrdup (operand_string);
9572 i.mem_operands++;
9573 }
9574 else
9575 {
9576 /* It's not a memory operand; argh! */
9577 as_bad (_("invalid char %s beginning operand %d `%s'"),
9578 output_invalid (*op_string),
9579 this_operand + 1,
9580 op_string);
9581 return 0;
9582 }
9583 return 1; /* Normal return. */
9584 }
9585 \f
9586 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9587 that an rs_machine_dependent frag may reach. */
9588
9589 unsigned int
9590 i386_frag_max_var (fragS *frag)
9591 {
9592 /* The only relaxable frags are for jumps.
9593 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9594 gas_assert (frag->fr_type == rs_machine_dependent);
9595 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9596 }
9597
9598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9599 static int
9600 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9601 {
9602 /* STT_GNU_IFUNC symbol must go through PLT. */
9603 if ((symbol_get_bfdsym (fr_symbol)->flags
9604 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9605 return 0;
9606
9607 if (!S_IS_EXTERNAL (fr_symbol))
9608 /* Symbol may be weak or local. */
9609 return !S_IS_WEAK (fr_symbol);
9610
9611 /* Global symbols with non-default visibility can't be preempted. */
9612 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9613 return 1;
9614
9615 if (fr_var != NO_RELOC)
9616 switch ((enum bfd_reloc_code_real) fr_var)
9617 {
9618 case BFD_RELOC_386_PLT32:
9619 case BFD_RELOC_X86_64_PLT32:
9620 /* Symbol with PLT relocation may be preempted. */
9621 return 0;
9622 default:
9623 abort ();
9624 }
9625
9626 /* Global symbols with default visibility in a shared library may be
9627 preempted by another definition. */
9628 return !shared;
9629 }
9630 #endif
9631
9632 /* md_estimate_size_before_relax()
9633
9634 Called just before relax() for rs_machine_dependent frags. The x86
9635 assembler uses these frags to handle variable size jump
9636 instructions.
9637
9638 Any symbol that is now undefined will not become defined.
9639 Return the correct fr_subtype in the frag.
9640 Return the initial "guess for variable size of frag" to caller.
9641 The guess is actually the growth beyond the fixed part. Whatever
9642 we do to grow the fixed or variable part contributes to our
9643 returned value. */
9644
9645 int
9646 md_estimate_size_before_relax (fragS *fragP, segT segment)
9647 {
9648 /* We've already got fragP->fr_subtype right; all we have to do is
9649 check for un-relaxable symbols. On an ELF system, we can't relax
9650 an externally visible symbol, because it may be overridden by a
9651 shared library. */
9652 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9654 || (IS_ELF
9655 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9656 fragP->fr_var))
9657 #endif
9658 #if defined (OBJ_COFF) && defined (TE_PE)
9659 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9660 && S_IS_WEAK (fragP->fr_symbol))
9661 #endif
9662 )
9663 {
9664 /* Symbol is undefined in this segment, or we need to keep a
9665 reloc so that weak symbols can be overridden. */
9666 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9667 enum bfd_reloc_code_real reloc_type;
9668 unsigned char *opcode;
9669 int old_fr_fix;
9670
9671 if (fragP->fr_var != NO_RELOC)
9672 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9673 else if (size == 2)
9674 reloc_type = BFD_RELOC_16_PCREL;
9675 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9676 else if (need_plt32_p (fragP->fr_symbol))
9677 reloc_type = BFD_RELOC_X86_64_PLT32;
9678 #endif
9679 else
9680 reloc_type = BFD_RELOC_32_PCREL;
9681
9682 old_fr_fix = fragP->fr_fix;
9683 opcode = (unsigned char *) fragP->fr_opcode;
9684
9685 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9686 {
9687 case UNCOND_JUMP:
9688 /* Make jmp (0xeb) a (d)word displacement jump. */
9689 opcode[0] = 0xe9;
9690 fragP->fr_fix += size;
9691 fix_new (fragP, old_fr_fix, size,
9692 fragP->fr_symbol,
9693 fragP->fr_offset, 1,
9694 reloc_type);
9695 break;
9696
9697 case COND_JUMP86:
9698 if (size == 2
9699 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9700 {
9701 /* Negate the condition, and branch past an
9702 unconditional jump. */
9703 opcode[0] ^= 1;
9704 opcode[1] = 3;
9705 /* Insert an unconditional jump. */
9706 opcode[2] = 0xe9;
9707 /* We added two extra opcode bytes, and have a two byte
9708 offset. */
9709 fragP->fr_fix += 2 + 2;
9710 fix_new (fragP, old_fr_fix + 2, 2,
9711 fragP->fr_symbol,
9712 fragP->fr_offset, 1,
9713 reloc_type);
9714 break;
9715 }
9716 /* Fall through. */
9717
9718 case COND_JUMP:
9719 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9720 {
9721 fixS *fixP;
9722
9723 fragP->fr_fix += 1;
9724 fixP = fix_new (fragP, old_fr_fix, 1,
9725 fragP->fr_symbol,
9726 fragP->fr_offset, 1,
9727 BFD_RELOC_8_PCREL);
9728 fixP->fx_signed = 1;
9729 break;
9730 }
9731
9732 /* This changes the byte-displacement jump 0x7N
9733 to the (d)word-displacement jump 0x0f,0x8N. */
9734 opcode[1] = opcode[0] + 0x10;
9735 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9736 /* We've added an opcode byte. */
9737 fragP->fr_fix += 1 + size;
9738 fix_new (fragP, old_fr_fix + 1, size,
9739 fragP->fr_symbol,
9740 fragP->fr_offset, 1,
9741 reloc_type);
9742 break;
9743
9744 default:
9745 BAD_CASE (fragP->fr_subtype);
9746 break;
9747 }
9748 frag_wane (fragP);
9749 return fragP->fr_fix - old_fr_fix;
9750 }
9751
9752 /* Guess size depending on current relax state. Initially the relax
9753 state will correspond to a short jump and we return 1, because
9754 the variable part of the frag (the branch offset) is one byte
9755 long. However, we can relax a section more than once and in that
9756 case we must either set fr_subtype back to the unrelaxed state,
9757 or return the value for the appropriate branch. */
9758 return md_relax_table[fragP->fr_subtype].rlx_length;
9759 }
9760
9761 /* Called after relax() is finished.
9762
9763 In: Address of frag.
9764 fr_type == rs_machine_dependent.
9765 fr_subtype is what the address relaxed to.
9766
9767 Out: Any fixSs and constants are set up.
9768 Caller will turn frag into a ".space 0". */
9769
9770 void
9771 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9772 fragS *fragP)
9773 {
9774 unsigned char *opcode;
9775 unsigned char *where_to_put_displacement = NULL;
9776 offsetT target_address;
9777 offsetT opcode_address;
9778 unsigned int extension = 0;
9779 offsetT displacement_from_opcode_start;
9780
9781 opcode = (unsigned char *) fragP->fr_opcode;
9782
9783 /* Address we want to reach in file space. */
9784 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9785
9786 /* Address opcode resides at in file space. */
9787 opcode_address = fragP->fr_address + fragP->fr_fix;
9788
9789 /* Displacement from opcode start to fill into instruction. */
9790 displacement_from_opcode_start = target_address - opcode_address;
9791
9792 if ((fragP->fr_subtype & BIG) == 0)
9793 {
9794 /* Don't have to change opcode. */
9795 extension = 1; /* 1 opcode + 1 displacement */
9796 where_to_put_displacement = &opcode[1];
9797 }
9798 else
9799 {
9800 if (no_cond_jump_promotion
9801 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9802 as_warn_where (fragP->fr_file, fragP->fr_line,
9803 _("long jump required"));
9804
9805 switch (fragP->fr_subtype)
9806 {
9807 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9808 extension = 4; /* 1 opcode + 4 displacement */
9809 opcode[0] = 0xe9;
9810 where_to_put_displacement = &opcode[1];
9811 break;
9812
9813 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9814 extension = 2; /* 1 opcode + 2 displacement */
9815 opcode[0] = 0xe9;
9816 where_to_put_displacement = &opcode[1];
9817 break;
9818
9819 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9820 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9821 extension = 5; /* 2 opcode + 4 displacement */
9822 opcode[1] = opcode[0] + 0x10;
9823 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9824 where_to_put_displacement = &opcode[2];
9825 break;
9826
9827 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9828 extension = 3; /* 2 opcode + 2 displacement */
9829 opcode[1] = opcode[0] + 0x10;
9830 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9831 where_to_put_displacement = &opcode[2];
9832 break;
9833
9834 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9835 extension = 4;
9836 opcode[0] ^= 1;
9837 opcode[1] = 3;
9838 opcode[2] = 0xe9;
9839 where_to_put_displacement = &opcode[3];
9840 break;
9841
9842 default:
9843 BAD_CASE (fragP->fr_subtype);
9844 break;
9845 }
9846 }
9847
9848 /* If size if less then four we are sure that the operand fits,
9849 but if it's 4, then it could be that the displacement is larger
9850 then -/+ 2GB. */
9851 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9852 && object_64bit
9853 && ((addressT) (displacement_from_opcode_start - extension
9854 + ((addressT) 1 << 31))
9855 > (((addressT) 2 << 31) - 1)))
9856 {
9857 as_bad_where (fragP->fr_file, fragP->fr_line,
9858 _("jump target out of range"));
9859 /* Make us emit 0. */
9860 displacement_from_opcode_start = extension;
9861 }
9862 /* Now put displacement after opcode. */
9863 md_number_to_chars ((char *) where_to_put_displacement,
9864 (valueT) (displacement_from_opcode_start - extension),
9865 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9866 fragP->fr_fix += extension;
9867 }
9868 \f
9869 /* Apply a fixup (fixP) to segment data, once it has been determined
9870 by our caller that we have all the info we need to fix it up.
9871
9872 Parameter valP is the pointer to the value of the bits.
9873
9874 On the 386, immediates, displacements, and data pointers are all in
9875 the same (little-endian) format, so we don't need to care about which
9876 we are handling. */
9877
9878 void
9879 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9880 {
9881 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9882 valueT value = *valP;
9883
9884 #if !defined (TE_Mach)
9885 if (fixP->fx_pcrel)
9886 {
9887 switch (fixP->fx_r_type)
9888 {
9889 default:
9890 break;
9891
9892 case BFD_RELOC_64:
9893 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9894 break;
9895 case BFD_RELOC_32:
9896 case BFD_RELOC_X86_64_32S:
9897 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9898 break;
9899 case BFD_RELOC_16:
9900 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9901 break;
9902 case BFD_RELOC_8:
9903 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9904 break;
9905 }
9906 }
9907
9908 if (fixP->fx_addsy != NULL
9909 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9910 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9911 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9912 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9913 && !use_rela_relocations)
9914 {
9915 /* This is a hack. There should be a better way to handle this.
9916 This covers for the fact that bfd_install_relocation will
9917 subtract the current location (for partial_inplace, PC relative
9918 relocations); see more below. */
9919 #ifndef OBJ_AOUT
9920 if (IS_ELF
9921 #ifdef TE_PE
9922 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9923 #endif
9924 )
9925 value += fixP->fx_where + fixP->fx_frag->fr_address;
9926 #endif
9927 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9928 if (IS_ELF)
9929 {
9930 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9931
9932 if ((sym_seg == seg
9933 || (symbol_section_p (fixP->fx_addsy)
9934 && sym_seg != absolute_section))
9935 && !generic_force_reloc (fixP))
9936 {
9937 /* Yes, we add the values in twice. This is because
9938 bfd_install_relocation subtracts them out again. I think
9939 bfd_install_relocation is broken, but I don't dare change
9940 it. FIXME. */
9941 value += fixP->fx_where + fixP->fx_frag->fr_address;
9942 }
9943 }
9944 #endif
9945 #if defined (OBJ_COFF) && defined (TE_PE)
9946 /* For some reason, the PE format does not store a
9947 section address offset for a PC relative symbol. */
9948 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9949 || S_IS_WEAK (fixP->fx_addsy))
9950 value += md_pcrel_from (fixP);
9951 #endif
9952 }
9953 #if defined (OBJ_COFF) && defined (TE_PE)
9954 if (fixP->fx_addsy != NULL
9955 && S_IS_WEAK (fixP->fx_addsy)
9956 /* PR 16858: Do not modify weak function references. */
9957 && ! fixP->fx_pcrel)
9958 {
9959 #if !defined (TE_PEP)
9960 /* For x86 PE weak function symbols are neither PC-relative
9961 nor do they set S_IS_FUNCTION. So the only reliable way
9962 to detect them is to check the flags of their containing
9963 section. */
9964 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9965 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9966 ;
9967 else
9968 #endif
9969 value -= S_GET_VALUE (fixP->fx_addsy);
9970 }
9971 #endif
9972
9973 /* Fix a few things - the dynamic linker expects certain values here,
9974 and we must not disappoint it. */
9975 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9976 if (IS_ELF && fixP->fx_addsy)
9977 switch (fixP->fx_r_type)
9978 {
9979 case BFD_RELOC_386_PLT32:
9980 case BFD_RELOC_X86_64_PLT32:
9981 /* Make the jump instruction point to the address of the operand. At
9982 runtime we merely add the offset to the actual PLT entry. */
9983 value = -4;
9984 break;
9985
9986 case BFD_RELOC_386_TLS_GD:
9987 case BFD_RELOC_386_TLS_LDM:
9988 case BFD_RELOC_386_TLS_IE_32:
9989 case BFD_RELOC_386_TLS_IE:
9990 case BFD_RELOC_386_TLS_GOTIE:
9991 case BFD_RELOC_386_TLS_GOTDESC:
9992 case BFD_RELOC_X86_64_TLSGD:
9993 case BFD_RELOC_X86_64_TLSLD:
9994 case BFD_RELOC_X86_64_GOTTPOFF:
9995 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9996 value = 0; /* Fully resolved at runtime. No addend. */
9997 /* Fallthrough */
9998 case BFD_RELOC_386_TLS_LE:
9999 case BFD_RELOC_386_TLS_LDO_32:
10000 case BFD_RELOC_386_TLS_LE_32:
10001 case BFD_RELOC_X86_64_DTPOFF32:
10002 case BFD_RELOC_X86_64_DTPOFF64:
10003 case BFD_RELOC_X86_64_TPOFF32:
10004 case BFD_RELOC_X86_64_TPOFF64:
10005 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10006 break;
10007
10008 case BFD_RELOC_386_TLS_DESC_CALL:
10009 case BFD_RELOC_X86_64_TLSDESC_CALL:
10010 value = 0; /* Fully resolved at runtime. No addend. */
10011 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10012 fixP->fx_done = 0;
10013 return;
10014
10015 case BFD_RELOC_VTABLE_INHERIT:
10016 case BFD_RELOC_VTABLE_ENTRY:
10017 fixP->fx_done = 0;
10018 return;
10019
10020 default:
10021 break;
10022 }
10023 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10024 *valP = value;
10025 #endif /* !defined (TE_Mach) */
10026
10027 /* Are we finished with this relocation now? */
10028 if (fixP->fx_addsy == NULL)
10029 fixP->fx_done = 1;
10030 #if defined (OBJ_COFF) && defined (TE_PE)
10031 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10032 {
10033 fixP->fx_done = 0;
10034 /* Remember value for tc_gen_reloc. */
10035 fixP->fx_addnumber = value;
10036 /* Clear out the frag for now. */
10037 value = 0;
10038 }
10039 #endif
10040 else if (use_rela_relocations)
10041 {
10042 fixP->fx_no_overflow = 1;
10043 /* Remember value for tc_gen_reloc. */
10044 fixP->fx_addnumber = value;
10045 value = 0;
10046 }
10047
10048 md_number_to_chars (p, value, fixP->fx_size);
10049 }
10050 \f
10051 const char *
10052 md_atof (int type, char *litP, int *sizeP)
10053 {
10054 /* This outputs the LITTLENUMs in REVERSE order;
10055 in accord with the bigendian 386. */
10056 return ieee_md_atof (type, litP, sizeP, FALSE);
10057 }
10058 \f
10059 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10060
10061 static char *
10062 output_invalid (int c)
10063 {
10064 if (ISPRINT (c))
10065 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10066 "'%c'", c);
10067 else
10068 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10069 "(0x%x)", (unsigned char) c);
10070 return output_invalid_buf;
10071 }
10072
10073 /* REG_STRING starts *before* REGISTER_PREFIX. */
10074
10075 static const reg_entry *
10076 parse_real_register (char *reg_string, char **end_op)
10077 {
10078 char *s = reg_string;
10079 char *p;
10080 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10081 const reg_entry *r;
10082
10083 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10084 if (*s == REGISTER_PREFIX)
10085 ++s;
10086
10087 if (is_space_char (*s))
10088 ++s;
10089
10090 p = reg_name_given;
10091 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10092 {
10093 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10094 return (const reg_entry *) NULL;
10095 s++;
10096 }
10097
10098 /* For naked regs, make sure that we are not dealing with an identifier.
10099 This prevents confusing an identifier like `eax_var' with register
10100 `eax'. */
10101 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10102 return (const reg_entry *) NULL;
10103
10104 *end_op = s;
10105
10106 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10107
10108 /* Handle floating point regs, allowing spaces in the (i) part. */
10109 if (r == i386_regtab /* %st is first entry of table */)
10110 {
10111 if (is_space_char (*s))
10112 ++s;
10113 if (*s == '(')
10114 {
10115 ++s;
10116 if (is_space_char (*s))
10117 ++s;
10118 if (*s >= '0' && *s <= '7')
10119 {
10120 int fpr = *s - '0';
10121 ++s;
10122 if (is_space_char (*s))
10123 ++s;
10124 if (*s == ')')
10125 {
10126 *end_op = s + 1;
10127 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10128 know (r);
10129 return r + fpr;
10130 }
10131 }
10132 /* We have "%st(" then garbage. */
10133 return (const reg_entry *) NULL;
10134 }
10135 }
10136
10137 if (r == NULL || allow_pseudo_reg)
10138 return r;
10139
10140 if (operand_type_all_zero (&r->reg_type))
10141 return (const reg_entry *) NULL;
10142
10143 if ((r->reg_type.bitfield.dword
10144 || r->reg_type.bitfield.sreg3
10145 || r->reg_type.bitfield.control
10146 || r->reg_type.bitfield.debug
10147 || r->reg_type.bitfield.test)
10148 && !cpu_arch_flags.bitfield.cpui386)
10149 return (const reg_entry *) NULL;
10150
10151 if (r->reg_type.bitfield.tbyte
10152 && !cpu_arch_flags.bitfield.cpu8087
10153 && !cpu_arch_flags.bitfield.cpu287
10154 && !cpu_arch_flags.bitfield.cpu387)
10155 return (const reg_entry *) NULL;
10156
10157 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10158 return (const reg_entry *) NULL;
10159
10160 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10161 return (const reg_entry *) NULL;
10162
10163 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10164 return (const reg_entry *) NULL;
10165
10166 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10167 return (const reg_entry *) NULL;
10168
10169 if (r->reg_type.bitfield.regmask
10170 && !cpu_arch_flags.bitfield.cpuregmask)
10171 return (const reg_entry *) NULL;
10172
10173 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10174 if (!allow_index_reg
10175 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10176 return (const reg_entry *) NULL;
10177
10178 /* Upper 16 vector register is only available with VREX in 64bit
10179 mode. */
10180 if ((r->reg_flags & RegVRex))
10181 {
10182 if (i.vec_encoding == vex_encoding_default)
10183 i.vec_encoding = vex_encoding_evex;
10184
10185 if (!cpu_arch_flags.bitfield.cpuvrex
10186 || i.vec_encoding != vex_encoding_evex
10187 || flag_code != CODE_64BIT)
10188 return (const reg_entry *) NULL;
10189 }
10190
10191 if (((r->reg_flags & (RegRex64 | RegRex))
10192 || r->reg_type.bitfield.qword)
10193 && (!cpu_arch_flags.bitfield.cpulm
10194 || !operand_type_equal (&r->reg_type, &control))
10195 && flag_code != CODE_64BIT)
10196 return (const reg_entry *) NULL;
10197
10198 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10199 return (const reg_entry *) NULL;
10200
10201 return r;
10202 }
10203
10204 /* REG_STRING starts *before* REGISTER_PREFIX. */
10205
10206 static const reg_entry *
10207 parse_register (char *reg_string, char **end_op)
10208 {
10209 const reg_entry *r;
10210
10211 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10212 r = parse_real_register (reg_string, end_op);
10213 else
10214 r = NULL;
10215 if (!r)
10216 {
10217 char *save = input_line_pointer;
10218 char c;
10219 symbolS *symbolP;
10220
10221 input_line_pointer = reg_string;
10222 c = get_symbol_name (&reg_string);
10223 symbolP = symbol_find (reg_string);
10224 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10225 {
10226 const expressionS *e = symbol_get_value_expression (symbolP);
10227
10228 know (e->X_op == O_register);
10229 know (e->X_add_number >= 0
10230 && (valueT) e->X_add_number < i386_regtab_size);
10231 r = i386_regtab + e->X_add_number;
10232 if ((r->reg_flags & RegVRex))
10233 i.vec_encoding = vex_encoding_evex;
10234 *end_op = input_line_pointer;
10235 }
10236 *input_line_pointer = c;
10237 input_line_pointer = save;
10238 }
10239 return r;
10240 }
10241
10242 int
10243 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10244 {
10245 const reg_entry *r;
10246 char *end = input_line_pointer;
10247
10248 *end = *nextcharP;
10249 r = parse_register (name, &input_line_pointer);
10250 if (r && end <= input_line_pointer)
10251 {
10252 *nextcharP = *input_line_pointer;
10253 *input_line_pointer = 0;
10254 e->X_op = O_register;
10255 e->X_add_number = r - i386_regtab;
10256 return 1;
10257 }
10258 input_line_pointer = end;
10259 *end = 0;
10260 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10261 }
10262
10263 void
10264 md_operand (expressionS *e)
10265 {
10266 char *end;
10267 const reg_entry *r;
10268
10269 switch (*input_line_pointer)
10270 {
10271 case REGISTER_PREFIX:
10272 r = parse_real_register (input_line_pointer, &end);
10273 if (r)
10274 {
10275 e->X_op = O_register;
10276 e->X_add_number = r - i386_regtab;
10277 input_line_pointer = end;
10278 }
10279 break;
10280
10281 case '[':
10282 gas_assert (intel_syntax);
10283 end = input_line_pointer++;
10284 expression (e);
10285 if (*input_line_pointer == ']')
10286 {
10287 ++input_line_pointer;
10288 e->X_op_symbol = make_expr_symbol (e);
10289 e->X_add_symbol = NULL;
10290 e->X_add_number = 0;
10291 e->X_op = O_index;
10292 }
10293 else
10294 {
10295 e->X_op = O_absent;
10296 input_line_pointer = end;
10297 }
10298 break;
10299 }
10300 }
10301
10302 \f
10303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10304 const char *md_shortopts = "kVQ:sqnO::";
10305 #else
10306 const char *md_shortopts = "qnO::";
10307 #endif
10308
10309 #define OPTION_32 (OPTION_MD_BASE + 0)
10310 #define OPTION_64 (OPTION_MD_BASE + 1)
10311 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10312 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10313 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10314 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10315 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10316 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10317 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10318 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10319 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10320 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10321 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10322 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10323 #define OPTION_X32 (OPTION_MD_BASE + 14)
10324 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10325 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10326 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10327 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10328 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10329 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10330 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10331 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10332 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10333 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10334
10335 struct option md_longopts[] =
10336 {
10337 {"32", no_argument, NULL, OPTION_32},
10338 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10339 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10340 {"64", no_argument, NULL, OPTION_64},
10341 #endif
10342 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10343 {"x32", no_argument, NULL, OPTION_X32},
10344 {"mshared", no_argument, NULL, OPTION_MSHARED},
10345 #endif
10346 {"divide", no_argument, NULL, OPTION_DIVIDE},
10347 {"march", required_argument, NULL, OPTION_MARCH},
10348 {"mtune", required_argument, NULL, OPTION_MTUNE},
10349 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10350 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10351 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10352 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10353 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10354 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10355 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10356 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10357 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10358 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10359 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10360 # if defined (TE_PE) || defined (TE_PEP)
10361 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10362 #endif
10363 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10364 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10365 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10366 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10367 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10368 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10369 {NULL, no_argument, NULL, 0}
10370 };
10371 size_t md_longopts_size = sizeof (md_longopts);
10372
10373 int
10374 md_parse_option (int c, const char *arg)
10375 {
10376 unsigned int j;
10377 char *arch, *next, *saved;
10378
10379 switch (c)
10380 {
10381 case 'n':
10382 optimize_align_code = 0;
10383 break;
10384
10385 case 'q':
10386 quiet_warnings = 1;
10387 break;
10388
10389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10390 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10391 should be emitted or not. FIXME: Not implemented. */
10392 case 'Q':
10393 break;
10394
10395 /* -V: SVR4 argument to print version ID. */
10396 case 'V':
10397 print_version_id ();
10398 break;
10399
10400 /* -k: Ignore for FreeBSD compatibility. */
10401 case 'k':
10402 break;
10403
10404 case 's':
10405 /* -s: On i386 Solaris, this tells the native assembler to use
10406 .stab instead of .stab.excl. We always use .stab anyhow. */
10407 break;
10408
10409 case OPTION_MSHARED:
10410 shared = 1;
10411 break;
10412 #endif
10413 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10414 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10415 case OPTION_64:
10416 {
10417 const char **list, **l;
10418
10419 list = bfd_target_list ();
10420 for (l = list; *l != NULL; l++)
10421 if (CONST_STRNEQ (*l, "elf64-x86-64")
10422 || strcmp (*l, "coff-x86-64") == 0
10423 || strcmp (*l, "pe-x86-64") == 0
10424 || strcmp (*l, "pei-x86-64") == 0
10425 || strcmp (*l, "mach-o-x86-64") == 0)
10426 {
10427 default_arch = "x86_64";
10428 break;
10429 }
10430 if (*l == NULL)
10431 as_fatal (_("no compiled in support for x86_64"));
10432 free (list);
10433 }
10434 break;
10435 #endif
10436
10437 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10438 case OPTION_X32:
10439 if (IS_ELF)
10440 {
10441 const char **list, **l;
10442
10443 list = bfd_target_list ();
10444 for (l = list; *l != NULL; l++)
10445 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10446 {
10447 default_arch = "x86_64:32";
10448 break;
10449 }
10450 if (*l == NULL)
10451 as_fatal (_("no compiled in support for 32bit x86_64"));
10452 free (list);
10453 }
10454 else
10455 as_fatal (_("32bit x86_64 is only supported for ELF"));
10456 break;
10457 #endif
10458
10459 case OPTION_32:
10460 default_arch = "i386";
10461 break;
10462
10463 case OPTION_DIVIDE:
10464 #ifdef SVR4_COMMENT_CHARS
10465 {
10466 char *n, *t;
10467 const char *s;
10468
10469 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10470 t = n;
10471 for (s = i386_comment_chars; *s != '\0'; s++)
10472 if (*s != '/')
10473 *t++ = *s;
10474 *t = '\0';
10475 i386_comment_chars = n;
10476 }
10477 #endif
10478 break;
10479
10480 case OPTION_MARCH:
10481 saved = xstrdup (arg);
10482 arch = saved;
10483 /* Allow -march=+nosse. */
10484 if (*arch == '+')
10485 arch++;
10486 do
10487 {
10488 if (*arch == '.')
10489 as_fatal (_("invalid -march= option: `%s'"), arg);
10490 next = strchr (arch, '+');
10491 if (next)
10492 *next++ = '\0';
10493 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10494 {
10495 if (strcmp (arch, cpu_arch [j].name) == 0)
10496 {
10497 /* Processor. */
10498 if (! cpu_arch[j].flags.bitfield.cpui386)
10499 continue;
10500
10501 cpu_arch_name = cpu_arch[j].name;
10502 cpu_sub_arch_name = NULL;
10503 cpu_arch_flags = cpu_arch[j].flags;
10504 cpu_arch_isa = cpu_arch[j].type;
10505 cpu_arch_isa_flags = cpu_arch[j].flags;
10506 if (!cpu_arch_tune_set)
10507 {
10508 cpu_arch_tune = cpu_arch_isa;
10509 cpu_arch_tune_flags = cpu_arch_isa_flags;
10510 }
10511 break;
10512 }
10513 else if (*cpu_arch [j].name == '.'
10514 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10515 {
10516 /* ISA extension. */
10517 i386_cpu_flags flags;
10518
10519 flags = cpu_flags_or (cpu_arch_flags,
10520 cpu_arch[j].flags);
10521
10522 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10523 {
10524 if (cpu_sub_arch_name)
10525 {
10526 char *name = cpu_sub_arch_name;
10527 cpu_sub_arch_name = concat (name,
10528 cpu_arch[j].name,
10529 (const char *) NULL);
10530 free (name);
10531 }
10532 else
10533 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10534 cpu_arch_flags = flags;
10535 cpu_arch_isa_flags = flags;
10536 }
10537 else
10538 cpu_arch_isa_flags
10539 = cpu_flags_or (cpu_arch_isa_flags,
10540 cpu_arch[j].flags);
10541 break;
10542 }
10543 }
10544
10545 if (j >= ARRAY_SIZE (cpu_arch))
10546 {
10547 /* Disable an ISA extension. */
10548 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10549 if (strcmp (arch, cpu_noarch [j].name) == 0)
10550 {
10551 i386_cpu_flags flags;
10552
10553 flags = cpu_flags_and_not (cpu_arch_flags,
10554 cpu_noarch[j].flags);
10555 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10556 {
10557 if (cpu_sub_arch_name)
10558 {
10559 char *name = cpu_sub_arch_name;
10560 cpu_sub_arch_name = concat (arch,
10561 (const char *) NULL);
10562 free (name);
10563 }
10564 else
10565 cpu_sub_arch_name = xstrdup (arch);
10566 cpu_arch_flags = flags;
10567 cpu_arch_isa_flags = flags;
10568 }
10569 break;
10570 }
10571
10572 if (j >= ARRAY_SIZE (cpu_noarch))
10573 j = ARRAY_SIZE (cpu_arch);
10574 }
10575
10576 if (j >= ARRAY_SIZE (cpu_arch))
10577 as_fatal (_("invalid -march= option: `%s'"), arg);
10578
10579 arch = next;
10580 }
10581 while (next != NULL);
10582 free (saved);
10583 break;
10584
10585 case OPTION_MTUNE:
10586 if (*arg == '.')
10587 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10589 {
10590 if (strcmp (arg, cpu_arch [j].name) == 0)
10591 {
10592 cpu_arch_tune_set = 1;
10593 cpu_arch_tune = cpu_arch [j].type;
10594 cpu_arch_tune_flags = cpu_arch[j].flags;
10595 break;
10596 }
10597 }
10598 if (j >= ARRAY_SIZE (cpu_arch))
10599 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10600 break;
10601
10602 case OPTION_MMNEMONIC:
10603 if (strcasecmp (arg, "att") == 0)
10604 intel_mnemonic = 0;
10605 else if (strcasecmp (arg, "intel") == 0)
10606 intel_mnemonic = 1;
10607 else
10608 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10609 break;
10610
10611 case OPTION_MSYNTAX:
10612 if (strcasecmp (arg, "att") == 0)
10613 intel_syntax = 0;
10614 else if (strcasecmp (arg, "intel") == 0)
10615 intel_syntax = 1;
10616 else
10617 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10618 break;
10619
10620 case OPTION_MINDEX_REG:
10621 allow_index_reg = 1;
10622 break;
10623
10624 case OPTION_MNAKED_REG:
10625 allow_naked_reg = 1;
10626 break;
10627
10628 case OPTION_MSSE2AVX:
10629 sse2avx = 1;
10630 break;
10631
10632 case OPTION_MSSE_CHECK:
10633 if (strcasecmp (arg, "error") == 0)
10634 sse_check = check_error;
10635 else if (strcasecmp (arg, "warning") == 0)
10636 sse_check = check_warning;
10637 else if (strcasecmp (arg, "none") == 0)
10638 sse_check = check_none;
10639 else
10640 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10641 break;
10642
10643 case OPTION_MOPERAND_CHECK:
10644 if (strcasecmp (arg, "error") == 0)
10645 operand_check = check_error;
10646 else if (strcasecmp (arg, "warning") == 0)
10647 operand_check = check_warning;
10648 else if (strcasecmp (arg, "none") == 0)
10649 operand_check = check_none;
10650 else
10651 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10652 break;
10653
10654 case OPTION_MAVXSCALAR:
10655 if (strcasecmp (arg, "128") == 0)
10656 avxscalar = vex128;
10657 else if (strcasecmp (arg, "256") == 0)
10658 avxscalar = vex256;
10659 else
10660 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10661 break;
10662
10663 case OPTION_MADD_BND_PREFIX:
10664 add_bnd_prefix = 1;
10665 break;
10666
10667 case OPTION_MEVEXLIG:
10668 if (strcmp (arg, "128") == 0)
10669 evexlig = evexl128;
10670 else if (strcmp (arg, "256") == 0)
10671 evexlig = evexl256;
10672 else if (strcmp (arg, "512") == 0)
10673 evexlig = evexl512;
10674 else
10675 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10676 break;
10677
10678 case OPTION_MEVEXRCIG:
10679 if (strcmp (arg, "rne") == 0)
10680 evexrcig = rne;
10681 else if (strcmp (arg, "rd") == 0)
10682 evexrcig = rd;
10683 else if (strcmp (arg, "ru") == 0)
10684 evexrcig = ru;
10685 else if (strcmp (arg, "rz") == 0)
10686 evexrcig = rz;
10687 else
10688 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10689 break;
10690
10691 case OPTION_MEVEXWIG:
10692 if (strcmp (arg, "0") == 0)
10693 evexwig = evexw0;
10694 else if (strcmp (arg, "1") == 0)
10695 evexwig = evexw1;
10696 else
10697 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10698 break;
10699
10700 # if defined (TE_PE) || defined (TE_PEP)
10701 case OPTION_MBIG_OBJ:
10702 use_big_obj = 1;
10703 break;
10704 #endif
10705
10706 case OPTION_MOMIT_LOCK_PREFIX:
10707 if (strcasecmp (arg, "yes") == 0)
10708 omit_lock_prefix = 1;
10709 else if (strcasecmp (arg, "no") == 0)
10710 omit_lock_prefix = 0;
10711 else
10712 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10713 break;
10714
10715 case OPTION_MFENCE_AS_LOCK_ADD:
10716 if (strcasecmp (arg, "yes") == 0)
10717 avoid_fence = 1;
10718 else if (strcasecmp (arg, "no") == 0)
10719 avoid_fence = 0;
10720 else
10721 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10722 break;
10723
10724 case OPTION_MRELAX_RELOCATIONS:
10725 if (strcasecmp (arg, "yes") == 0)
10726 generate_relax_relocations = 1;
10727 else if (strcasecmp (arg, "no") == 0)
10728 generate_relax_relocations = 0;
10729 else
10730 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10731 break;
10732
10733 case OPTION_MAMD64:
10734 intel64 = 0;
10735 break;
10736
10737 case OPTION_MINTEL64:
10738 intel64 = 1;
10739 break;
10740
10741 case 'O':
10742 if (arg == NULL)
10743 {
10744 optimize = 1;
10745 /* Turn off -Os. */
10746 optimize_for_space = 0;
10747 }
10748 else if (*arg == 's')
10749 {
10750 optimize_for_space = 1;
10751 /* Turn on all encoding optimizations. */
10752 optimize = -1;
10753 }
10754 else
10755 {
10756 optimize = atoi (arg);
10757 /* Turn off -Os. */
10758 optimize_for_space = 0;
10759 }
10760 break;
10761
10762 default:
10763 return 0;
10764 }
10765 return 1;
10766 }
10767
10768 #define MESSAGE_TEMPLATE \
10769 " "
10770
10771 static char *
10772 output_message (FILE *stream, char *p, char *message, char *start,
10773 int *left_p, const char *name, int len)
10774 {
10775 int size = sizeof (MESSAGE_TEMPLATE);
10776 int left = *left_p;
10777
10778 /* Reserve 2 spaces for ", " or ",\0" */
10779 left -= len + 2;
10780
10781 /* Check if there is any room. */
10782 if (left >= 0)
10783 {
10784 if (p != start)
10785 {
10786 *p++ = ',';
10787 *p++ = ' ';
10788 }
10789 p = mempcpy (p, name, len);
10790 }
10791 else
10792 {
10793 /* Output the current message now and start a new one. */
10794 *p++ = ',';
10795 *p = '\0';
10796 fprintf (stream, "%s\n", message);
10797 p = start;
10798 left = size - (start - message) - len - 2;
10799
10800 gas_assert (left >= 0);
10801
10802 p = mempcpy (p, name, len);
10803 }
10804
10805 *left_p = left;
10806 return p;
10807 }
10808
10809 static void
10810 show_arch (FILE *stream, int ext, int check)
10811 {
10812 static char message[] = MESSAGE_TEMPLATE;
10813 char *start = message + 27;
10814 char *p;
10815 int size = sizeof (MESSAGE_TEMPLATE);
10816 int left;
10817 const char *name;
10818 int len;
10819 unsigned int j;
10820
10821 p = start;
10822 left = size - (start - message);
10823 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10824 {
10825 /* Should it be skipped? */
10826 if (cpu_arch [j].skip)
10827 continue;
10828
10829 name = cpu_arch [j].name;
10830 len = cpu_arch [j].len;
10831 if (*name == '.')
10832 {
10833 /* It is an extension. Skip if we aren't asked to show it. */
10834 if (ext)
10835 {
10836 name++;
10837 len--;
10838 }
10839 else
10840 continue;
10841 }
10842 else if (ext)
10843 {
10844 /* It is an processor. Skip if we show only extension. */
10845 continue;
10846 }
10847 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10848 {
10849 /* It is an impossible processor - skip. */
10850 continue;
10851 }
10852
10853 p = output_message (stream, p, message, start, &left, name, len);
10854 }
10855
10856 /* Display disabled extensions. */
10857 if (ext)
10858 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10859 {
10860 name = cpu_noarch [j].name;
10861 len = cpu_noarch [j].len;
10862 p = output_message (stream, p, message, start, &left, name,
10863 len);
10864 }
10865
10866 *p = '\0';
10867 fprintf (stream, "%s\n", message);
10868 }
10869
10870 void
10871 md_show_usage (FILE *stream)
10872 {
10873 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10874 fprintf (stream, _("\
10875 -Q ignored\n\
10876 -V print assembler version number\n\
10877 -k ignored\n"));
10878 #endif
10879 fprintf (stream, _("\
10880 -n Do not optimize code alignment\n\
10881 -q quieten some warnings\n"));
10882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883 fprintf (stream, _("\
10884 -s ignored\n"));
10885 #endif
10886 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10887 || defined (TE_PE) || defined (TE_PEP))
10888 fprintf (stream, _("\
10889 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10890 #endif
10891 #ifdef SVR4_COMMENT_CHARS
10892 fprintf (stream, _("\
10893 --divide do not treat `/' as a comment character\n"));
10894 #else
10895 fprintf (stream, _("\
10896 --divide ignored\n"));
10897 #endif
10898 fprintf (stream, _("\
10899 -march=CPU[,+EXTENSION...]\n\
10900 generate code for CPU and EXTENSION, CPU is one of:\n"));
10901 show_arch (stream, 0, 1);
10902 fprintf (stream, _("\
10903 EXTENSION is combination of:\n"));
10904 show_arch (stream, 1, 0);
10905 fprintf (stream, _("\
10906 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10907 show_arch (stream, 0, 0);
10908 fprintf (stream, _("\
10909 -msse2avx encode SSE instructions with VEX prefix\n"));
10910 fprintf (stream, _("\
10911 -msse-check=[none|error|warning]\n\
10912 check SSE instructions\n"));
10913 fprintf (stream, _("\
10914 -moperand-check=[none|error|warning]\n\
10915 check operand combinations for validity\n"));
10916 fprintf (stream, _("\
10917 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10918 length\n"));
10919 fprintf (stream, _("\
10920 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10921 length\n"));
10922 fprintf (stream, _("\
10923 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10924 for EVEX.W bit ignored instructions\n"));
10925 fprintf (stream, _("\
10926 -mevexrcig=[rne|rd|ru|rz]\n\
10927 encode EVEX instructions with specific EVEX.RC value\n\
10928 for SAE-only ignored instructions\n"));
10929 fprintf (stream, _("\
10930 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10931 fprintf (stream, _("\
10932 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10933 fprintf (stream, _("\
10934 -mindex-reg support pseudo index registers\n"));
10935 fprintf (stream, _("\
10936 -mnaked-reg don't require `%%' prefix for registers\n"));
10937 fprintf (stream, _("\
10938 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10939 fprintf (stream, _("\
10940 -mshared disable branch optimization for shared code\n"));
10941 # if defined (TE_PE) || defined (TE_PEP)
10942 fprintf (stream, _("\
10943 -mbig-obj generate big object files\n"));
10944 #endif
10945 fprintf (stream, _("\
10946 -momit-lock-prefix=[no|yes]\n\
10947 strip all lock prefixes\n"));
10948 fprintf (stream, _("\
10949 -mfence-as-lock-add=[no|yes]\n\
10950 encode lfence, mfence and sfence as\n\
10951 lock addl $0x0, (%%{re}sp)\n"));
10952 fprintf (stream, _("\
10953 -mrelax-relocations=[no|yes]\n\
10954 generate relax relocations\n"));
10955 fprintf (stream, _("\
10956 -mamd64 accept only AMD64 ISA\n"));
10957 fprintf (stream, _("\
10958 -mintel64 accept only Intel64 ISA\n"));
10959 }
10960
10961 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10962 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10963 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10964
10965 /* Pick the target format to use. */
10966
10967 const char *
10968 i386_target_format (void)
10969 {
10970 if (!strncmp (default_arch, "x86_64", 6))
10971 {
10972 update_code_flag (CODE_64BIT, 1);
10973 if (default_arch[6] == '\0')
10974 x86_elf_abi = X86_64_ABI;
10975 else
10976 x86_elf_abi = X86_64_X32_ABI;
10977 }
10978 else if (!strcmp (default_arch, "i386"))
10979 update_code_flag (CODE_32BIT, 1);
10980 else if (!strcmp (default_arch, "iamcu"))
10981 {
10982 update_code_flag (CODE_32BIT, 1);
10983 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10984 {
10985 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10986 cpu_arch_name = "iamcu";
10987 cpu_sub_arch_name = NULL;
10988 cpu_arch_flags = iamcu_flags;
10989 cpu_arch_isa = PROCESSOR_IAMCU;
10990 cpu_arch_isa_flags = iamcu_flags;
10991 if (!cpu_arch_tune_set)
10992 {
10993 cpu_arch_tune = cpu_arch_isa;
10994 cpu_arch_tune_flags = cpu_arch_isa_flags;
10995 }
10996 }
10997 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10998 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10999 cpu_arch_name);
11000 }
11001 else
11002 as_fatal (_("unknown architecture"));
11003
11004 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11005 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11006 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11007 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11008
11009 switch (OUTPUT_FLAVOR)
11010 {
11011 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11012 case bfd_target_aout_flavour:
11013 return AOUT_TARGET_FORMAT;
11014 #endif
11015 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11016 # if defined (TE_PE) || defined (TE_PEP)
11017 case bfd_target_coff_flavour:
11018 if (flag_code == CODE_64BIT)
11019 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11020 else
11021 return "pe-i386";
11022 # elif defined (TE_GO32)
11023 case bfd_target_coff_flavour:
11024 return "coff-go32";
11025 # else
11026 case bfd_target_coff_flavour:
11027 return "coff-i386";
11028 # endif
11029 #endif
11030 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11031 case bfd_target_elf_flavour:
11032 {
11033 const char *format;
11034
11035 switch (x86_elf_abi)
11036 {
11037 default:
11038 format = ELF_TARGET_FORMAT;
11039 break;
11040 case X86_64_ABI:
11041 use_rela_relocations = 1;
11042 object_64bit = 1;
11043 format = ELF_TARGET_FORMAT64;
11044 break;
11045 case X86_64_X32_ABI:
11046 use_rela_relocations = 1;
11047 object_64bit = 1;
11048 disallow_64bit_reloc = 1;
11049 format = ELF_TARGET_FORMAT32;
11050 break;
11051 }
11052 if (cpu_arch_isa == PROCESSOR_L1OM)
11053 {
11054 if (x86_elf_abi != X86_64_ABI)
11055 as_fatal (_("Intel L1OM is 64bit only"));
11056 return ELF_TARGET_L1OM_FORMAT;
11057 }
11058 else if (cpu_arch_isa == PROCESSOR_K1OM)
11059 {
11060 if (x86_elf_abi != X86_64_ABI)
11061 as_fatal (_("Intel K1OM is 64bit only"));
11062 return ELF_TARGET_K1OM_FORMAT;
11063 }
11064 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11065 {
11066 if (x86_elf_abi != I386_ABI)
11067 as_fatal (_("Intel MCU is 32bit only"));
11068 return ELF_TARGET_IAMCU_FORMAT;
11069 }
11070 else
11071 return format;
11072 }
11073 #endif
11074 #if defined (OBJ_MACH_O)
11075 case bfd_target_mach_o_flavour:
11076 if (flag_code == CODE_64BIT)
11077 {
11078 use_rela_relocations = 1;
11079 object_64bit = 1;
11080 return "mach-o-x86-64";
11081 }
11082 else
11083 return "mach-o-i386";
11084 #endif
11085 default:
11086 abort ();
11087 return NULL;
11088 }
11089 }
11090
11091 #endif /* OBJ_MAYBE_ more than one */
11092 \f
11093 symbolS *
11094 md_undefined_symbol (char *name)
11095 {
11096 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11097 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11098 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11099 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11100 {
11101 if (!GOT_symbol)
11102 {
11103 if (symbol_find (name))
11104 as_bad (_("GOT already in symbol table"));
11105 GOT_symbol = symbol_new (name, undefined_section,
11106 (valueT) 0, &zero_address_frag);
11107 };
11108 return GOT_symbol;
11109 }
11110 return 0;
11111 }
11112
11113 /* Round up a section size to the appropriate boundary. */
11114
11115 valueT
11116 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11117 {
11118 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11119 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11120 {
11121 /* For a.out, force the section size to be aligned. If we don't do
11122 this, BFD will align it for us, but it will not write out the
11123 final bytes of the section. This may be a bug in BFD, but it is
11124 easier to fix it here since that is how the other a.out targets
11125 work. */
11126 int align;
11127
11128 align = bfd_get_section_alignment (stdoutput, segment);
11129 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11130 }
11131 #endif
11132
11133 return size;
11134 }
11135
11136 /* On the i386, PC-relative offsets are relative to the start of the
11137 next instruction. That is, the address of the offset, plus its
11138 size, since the offset is always the last part of the insn. */
11139
11140 long
11141 md_pcrel_from (fixS *fixP)
11142 {
11143 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11144 }
11145
11146 #ifndef I386COFF
11147
11148 static void
11149 s_bss (int ignore ATTRIBUTE_UNUSED)
11150 {
11151 int temp;
11152
11153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11154 if (IS_ELF)
11155 obj_elf_section_change_hook ();
11156 #endif
11157 temp = get_absolute_expression ();
11158 subseg_set (bss_section, (subsegT) temp);
11159 demand_empty_rest_of_line ();
11160 }
11161
11162 #endif
11163
11164 void
11165 i386_validate_fix (fixS *fixp)
11166 {
11167 if (fixp->fx_subsy)
11168 {
11169 if (fixp->fx_subsy == GOT_symbol)
11170 {
11171 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11172 {
11173 if (!object_64bit)
11174 abort ();
11175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11176 if (fixp->fx_tcbit2)
11177 fixp->fx_r_type = (fixp->fx_tcbit
11178 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11179 : BFD_RELOC_X86_64_GOTPCRELX);
11180 else
11181 #endif
11182 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11183 }
11184 else
11185 {
11186 if (!object_64bit)
11187 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11188 else
11189 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11190 }
11191 fixp->fx_subsy = 0;
11192 }
11193 }
11194 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11195 else if (!object_64bit)
11196 {
11197 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11198 && fixp->fx_tcbit2)
11199 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11200 }
11201 #endif
11202 }
11203
11204 arelent *
11205 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11206 {
11207 arelent *rel;
11208 bfd_reloc_code_real_type code;
11209
11210 switch (fixp->fx_r_type)
11211 {
11212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11213 case BFD_RELOC_SIZE32:
11214 case BFD_RELOC_SIZE64:
11215 if (S_IS_DEFINED (fixp->fx_addsy)
11216 && !S_IS_EXTERNAL (fixp->fx_addsy))
11217 {
11218 /* Resolve size relocation against local symbol to size of
11219 the symbol plus addend. */
11220 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11221 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11222 && !fits_in_unsigned_long (value))
11223 as_bad_where (fixp->fx_file, fixp->fx_line,
11224 _("symbol size computation overflow"));
11225 fixp->fx_addsy = NULL;
11226 fixp->fx_subsy = NULL;
11227 md_apply_fix (fixp, (valueT *) &value, NULL);
11228 return NULL;
11229 }
11230 #endif
11231 /* Fall through. */
11232
11233 case BFD_RELOC_X86_64_PLT32:
11234 case BFD_RELOC_X86_64_GOT32:
11235 case BFD_RELOC_X86_64_GOTPCREL:
11236 case BFD_RELOC_X86_64_GOTPCRELX:
11237 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11238 case BFD_RELOC_386_PLT32:
11239 case BFD_RELOC_386_GOT32:
11240 case BFD_RELOC_386_GOT32X:
11241 case BFD_RELOC_386_GOTOFF:
11242 case BFD_RELOC_386_GOTPC:
11243 case BFD_RELOC_386_TLS_GD:
11244 case BFD_RELOC_386_TLS_LDM:
11245 case BFD_RELOC_386_TLS_LDO_32:
11246 case BFD_RELOC_386_TLS_IE_32:
11247 case BFD_RELOC_386_TLS_IE:
11248 case BFD_RELOC_386_TLS_GOTIE:
11249 case BFD_RELOC_386_TLS_LE_32:
11250 case BFD_RELOC_386_TLS_LE:
11251 case BFD_RELOC_386_TLS_GOTDESC:
11252 case BFD_RELOC_386_TLS_DESC_CALL:
11253 case BFD_RELOC_X86_64_TLSGD:
11254 case BFD_RELOC_X86_64_TLSLD:
11255 case BFD_RELOC_X86_64_DTPOFF32:
11256 case BFD_RELOC_X86_64_DTPOFF64:
11257 case BFD_RELOC_X86_64_GOTTPOFF:
11258 case BFD_RELOC_X86_64_TPOFF32:
11259 case BFD_RELOC_X86_64_TPOFF64:
11260 case BFD_RELOC_X86_64_GOTOFF64:
11261 case BFD_RELOC_X86_64_GOTPC32:
11262 case BFD_RELOC_X86_64_GOT64:
11263 case BFD_RELOC_X86_64_GOTPCREL64:
11264 case BFD_RELOC_X86_64_GOTPC64:
11265 case BFD_RELOC_X86_64_GOTPLT64:
11266 case BFD_RELOC_X86_64_PLTOFF64:
11267 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11268 case BFD_RELOC_X86_64_TLSDESC_CALL:
11269 case BFD_RELOC_RVA:
11270 case BFD_RELOC_VTABLE_ENTRY:
11271 case BFD_RELOC_VTABLE_INHERIT:
11272 #ifdef TE_PE
11273 case BFD_RELOC_32_SECREL:
11274 #endif
11275 code = fixp->fx_r_type;
11276 break;
11277 case BFD_RELOC_X86_64_32S:
11278 if (!fixp->fx_pcrel)
11279 {
11280 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11281 code = fixp->fx_r_type;
11282 break;
11283 }
11284 /* Fall through. */
11285 default:
11286 if (fixp->fx_pcrel)
11287 {
11288 switch (fixp->fx_size)
11289 {
11290 default:
11291 as_bad_where (fixp->fx_file, fixp->fx_line,
11292 _("can not do %d byte pc-relative relocation"),
11293 fixp->fx_size);
11294 code = BFD_RELOC_32_PCREL;
11295 break;
11296 case 1: code = BFD_RELOC_8_PCREL; break;
11297 case 2: code = BFD_RELOC_16_PCREL; break;
11298 case 4: code = BFD_RELOC_32_PCREL; break;
11299 #ifdef BFD64
11300 case 8: code = BFD_RELOC_64_PCREL; break;
11301 #endif
11302 }
11303 }
11304 else
11305 {
11306 switch (fixp->fx_size)
11307 {
11308 default:
11309 as_bad_where (fixp->fx_file, fixp->fx_line,
11310 _("can not do %d byte relocation"),
11311 fixp->fx_size);
11312 code = BFD_RELOC_32;
11313 break;
11314 case 1: code = BFD_RELOC_8; break;
11315 case 2: code = BFD_RELOC_16; break;
11316 case 4: code = BFD_RELOC_32; break;
11317 #ifdef BFD64
11318 case 8: code = BFD_RELOC_64; break;
11319 #endif
11320 }
11321 }
11322 break;
11323 }
11324
11325 if ((code == BFD_RELOC_32
11326 || code == BFD_RELOC_32_PCREL
11327 || code == BFD_RELOC_X86_64_32S)
11328 && GOT_symbol
11329 && fixp->fx_addsy == GOT_symbol)
11330 {
11331 if (!object_64bit)
11332 code = BFD_RELOC_386_GOTPC;
11333 else
11334 code = BFD_RELOC_X86_64_GOTPC32;
11335 }
11336 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11337 && GOT_symbol
11338 && fixp->fx_addsy == GOT_symbol)
11339 {
11340 code = BFD_RELOC_X86_64_GOTPC64;
11341 }
11342
11343 rel = XNEW (arelent);
11344 rel->sym_ptr_ptr = XNEW (asymbol *);
11345 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11346
11347 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11348
11349 if (!use_rela_relocations)
11350 {
11351 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11352 vtable entry to be used in the relocation's section offset. */
11353 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11354 rel->address = fixp->fx_offset;
11355 #if defined (OBJ_COFF) && defined (TE_PE)
11356 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11357 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11358 else
11359 #endif
11360 rel->addend = 0;
11361 }
11362 /* Use the rela in 64bit mode. */
11363 else
11364 {
11365 if (disallow_64bit_reloc)
11366 switch (code)
11367 {
11368 case BFD_RELOC_X86_64_DTPOFF64:
11369 case BFD_RELOC_X86_64_TPOFF64:
11370 case BFD_RELOC_64_PCREL:
11371 case BFD_RELOC_X86_64_GOTOFF64:
11372 case BFD_RELOC_X86_64_GOT64:
11373 case BFD_RELOC_X86_64_GOTPCREL64:
11374 case BFD_RELOC_X86_64_GOTPC64:
11375 case BFD_RELOC_X86_64_GOTPLT64:
11376 case BFD_RELOC_X86_64_PLTOFF64:
11377 as_bad_where (fixp->fx_file, fixp->fx_line,
11378 _("cannot represent relocation type %s in x32 mode"),
11379 bfd_get_reloc_code_name (code));
11380 break;
11381 default:
11382 break;
11383 }
11384
11385 if (!fixp->fx_pcrel)
11386 rel->addend = fixp->fx_offset;
11387 else
11388 switch (code)
11389 {
11390 case BFD_RELOC_X86_64_PLT32:
11391 case BFD_RELOC_X86_64_GOT32:
11392 case BFD_RELOC_X86_64_GOTPCREL:
11393 case BFD_RELOC_X86_64_GOTPCRELX:
11394 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11395 case BFD_RELOC_X86_64_TLSGD:
11396 case BFD_RELOC_X86_64_TLSLD:
11397 case BFD_RELOC_X86_64_GOTTPOFF:
11398 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11399 case BFD_RELOC_X86_64_TLSDESC_CALL:
11400 rel->addend = fixp->fx_offset - fixp->fx_size;
11401 break;
11402 default:
11403 rel->addend = (section->vma
11404 - fixp->fx_size
11405 + fixp->fx_addnumber
11406 + md_pcrel_from (fixp));
11407 break;
11408 }
11409 }
11410
11411 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11412 if (rel->howto == NULL)
11413 {
11414 as_bad_where (fixp->fx_file, fixp->fx_line,
11415 _("cannot represent relocation type %s"),
11416 bfd_get_reloc_code_name (code));
11417 /* Set howto to a garbage value so that we can keep going. */
11418 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11419 gas_assert (rel->howto != NULL);
11420 }
11421
11422 return rel;
11423 }
11424
11425 #include "tc-i386-intel.c"
11426
11427 void
11428 tc_x86_parse_to_dw2regnum (expressionS *exp)
11429 {
11430 int saved_naked_reg;
11431 char saved_register_dot;
11432
11433 saved_naked_reg = allow_naked_reg;
11434 allow_naked_reg = 1;
11435 saved_register_dot = register_chars['.'];
11436 register_chars['.'] = '.';
11437 allow_pseudo_reg = 1;
11438 expression_and_evaluate (exp);
11439 allow_pseudo_reg = 0;
11440 register_chars['.'] = saved_register_dot;
11441 allow_naked_reg = saved_naked_reg;
11442
11443 if (exp->X_op == O_register && exp->X_add_number >= 0)
11444 {
11445 if ((addressT) exp->X_add_number < i386_regtab_size)
11446 {
11447 exp->X_op = O_constant;
11448 exp->X_add_number = i386_regtab[exp->X_add_number]
11449 .dw2_regnum[flag_code >> 1];
11450 }
11451 else
11452 exp->X_op = O_illegal;
11453 }
11454 }
11455
11456 void
11457 tc_x86_frame_initial_instructions (void)
11458 {
11459 static unsigned int sp_regno[2];
11460
11461 if (!sp_regno[flag_code >> 1])
11462 {
11463 char *saved_input = input_line_pointer;
11464 char sp[][4] = {"esp", "rsp"};
11465 expressionS exp;
11466
11467 input_line_pointer = sp[flag_code >> 1];
11468 tc_x86_parse_to_dw2regnum (&exp);
11469 gas_assert (exp.X_op == O_constant);
11470 sp_regno[flag_code >> 1] = exp.X_add_number;
11471 input_line_pointer = saved_input;
11472 }
11473
11474 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11475 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11476 }
11477
11478 int
11479 x86_dwarf2_addr_size (void)
11480 {
11481 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11482 if (x86_elf_abi == X86_64_X32_ABI)
11483 return 4;
11484 #endif
11485 return bfd_arch_bits_per_address (stdoutput) / 8;
11486 }
11487
11488 int
11489 i386_elf_section_type (const char *str, size_t len)
11490 {
11491 if (flag_code == CODE_64BIT
11492 && len == sizeof ("unwind") - 1
11493 && strncmp (str, "unwind", 6) == 0)
11494 return SHT_X86_64_UNWIND;
11495
11496 return -1;
11497 }
11498
11499 #ifdef TE_SOLARIS
11500 void
11501 i386_solaris_fix_up_eh_frame (segT sec)
11502 {
11503 if (flag_code == CODE_64BIT)
11504 elf_section_type (sec) = SHT_X86_64_UNWIND;
11505 }
11506 #endif
11507
11508 #ifdef TE_PE
11509 void
11510 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11511 {
11512 expressionS exp;
11513
11514 exp.X_op = O_secrel;
11515 exp.X_add_symbol = symbol;
11516 exp.X_add_number = 0;
11517 emit_expr (&exp, size);
11518 }
11519 #endif
11520
11521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11522 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11523
11524 bfd_vma
11525 x86_64_section_letter (int letter, const char **ptr_msg)
11526 {
11527 if (flag_code == CODE_64BIT)
11528 {
11529 if (letter == 'l')
11530 return SHF_X86_64_LARGE;
11531
11532 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11533 }
11534 else
11535 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11536 return -1;
11537 }
11538
11539 bfd_vma
11540 x86_64_section_word (char *str, size_t len)
11541 {
11542 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11543 return SHF_X86_64_LARGE;
11544
11545 return -1;
11546 }
11547
11548 static void
11549 handle_large_common (int small ATTRIBUTE_UNUSED)
11550 {
11551 if (flag_code != CODE_64BIT)
11552 {
11553 s_comm_internal (0, elf_common_parse);
11554 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11555 }
11556 else
11557 {
11558 static segT lbss_section;
11559 asection *saved_com_section_ptr = elf_com_section_ptr;
11560 asection *saved_bss_section = bss_section;
11561
11562 if (lbss_section == NULL)
11563 {
11564 flagword applicable;
11565 segT seg = now_seg;
11566 subsegT subseg = now_subseg;
11567
11568 /* The .lbss section is for local .largecomm symbols. */
11569 lbss_section = subseg_new (".lbss", 0);
11570 applicable = bfd_applicable_section_flags (stdoutput);
11571 bfd_set_section_flags (stdoutput, lbss_section,
11572 applicable & SEC_ALLOC);
11573 seg_info (lbss_section)->bss = 1;
11574
11575 subseg_set (seg, subseg);
11576 }
11577
11578 elf_com_section_ptr = &_bfd_elf_large_com_section;
11579 bss_section = lbss_section;
11580
11581 s_comm_internal (0, elf_common_parse);
11582
11583 elf_com_section_ptr = saved_com_section_ptr;
11584 bss_section = saved_bss_section;
11585 }
11586 }
11587 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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