1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
356 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
357 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
},
362 i386_align_code (fragP
, count
)
366 /* Various efficient no-op patterns for aligning code labels.
367 Note: Don't try to assemble the instructions in the comments.
368 0L and 0w are not legal. */
369 static const char f32_1
[] =
371 static const char f32_2
[] =
372 {0x89,0xf6}; /* movl %esi,%esi */
373 static const char f32_3
[] =
374 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
375 static const char f32_4
[] =
376 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
377 static const char f32_5
[] =
379 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
380 static const char f32_6
[] =
381 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
382 static const char f32_7
[] =
383 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
384 static const char f32_8
[] =
386 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
387 static const char f32_9
[] =
388 {0x89,0xf6, /* movl %esi,%esi */
389 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
390 static const char f32_10
[] =
391 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
392 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
393 static const char f32_11
[] =
394 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
395 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
396 static const char f32_12
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
398 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
399 static const char f32_13
[] =
400 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
401 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
402 static const char f32_14
[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
404 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
405 static const char f32_15
[] =
406 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
407 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
408 static const char f16_3
[] =
409 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
410 static const char f16_4
[] =
411 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
412 static const char f16_5
[] =
414 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
415 static const char f16_6
[] =
416 {0x89,0xf6, /* mov %si,%si */
417 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
418 static const char f16_7
[] =
419 {0x8d,0x74,0x00, /* lea 0(%si),%si */
420 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
421 static const char f16_8
[] =
422 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
423 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
424 static const char *const f32_patt
[] = {
425 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
426 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
428 static const char *const f16_patt
[] = {
429 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
430 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
433 /* ??? We can't use these fillers for x86_64, since they often kills the
434 upper halves. Solve later. */
435 if (flag_code
== CODE_64BIT
)
438 if (count
> 0 && count
<= 15)
440 if (flag_code
== CODE_16BIT
)
442 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
443 f16_patt
[count
- 1], count
);
445 /* Adjust jump offset. */
446 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
449 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
450 f32_patt
[count
- 1], count
);
451 fragP
->fr_var
= count
;
455 static char *output_invalid
PARAMS ((int c
));
456 static int i386_operand
PARAMS ((char *operand_string
));
457 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
458 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
462 static void s_bss
PARAMS ((int));
465 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
467 static INLINE
unsigned int
468 mode_from_disp_size (t
)
471 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
475 fits_in_signed_byte (num
)
478 return (num
>= -128) && (num
<= 127);
482 fits_in_unsigned_byte (num
)
485 return (num
& 0xff) == num
;
489 fits_in_unsigned_word (num
)
492 return (num
& 0xffff) == num
;
496 fits_in_signed_word (num
)
499 return (-32768 <= num
) && (num
<= 32767);
502 fits_in_signed_long (num
)
503 offsetT num ATTRIBUTE_UNUSED
;
508 return (!(((offsetT
) -1 << 31) & num
)
509 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
511 } /* fits_in_signed_long() */
513 fits_in_unsigned_long (num
)
514 offsetT num ATTRIBUTE_UNUSED
;
519 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
521 } /* fits_in_unsigned_long() */
524 smallest_imm_type (num
)
527 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
528 && !(cpu_arch_flags
& (CpuUnknown
)))
530 /* This code is disabled on the 486 because all the Imm1 forms
531 in the opcode table are slower on the i486. They're the
532 versions with the implicitly specified single-position
533 displacement, which has another syntax if you really want to
536 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
538 return (fits_in_signed_byte (num
)
539 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
540 : fits_in_unsigned_byte (num
)
541 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
542 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
543 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
544 : fits_in_signed_long (num
)
545 ? (Imm32
| Imm32S
| Imm64
)
546 : fits_in_unsigned_long (num
)
552 offset_in_range (val
, size
)
560 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
561 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
562 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
564 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
569 /* If BFD64, sign extend val. */
570 if (!use_rela_relocations
)
571 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
572 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
574 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
576 char buf1
[40], buf2
[40];
578 sprint_value (buf1
, val
);
579 sprint_value (buf2
, val
& mask
);
580 as_warn (_("%s shortened to %s"), buf1
, buf2
);
585 /* Returns 0 if attempting to add a prefix where one from the same
586 class already exists, 1 if non rep/repne added, 2 if rep/repne
595 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
603 case CS_PREFIX_OPCODE
:
604 case DS_PREFIX_OPCODE
:
605 case ES_PREFIX_OPCODE
:
606 case FS_PREFIX_OPCODE
:
607 case GS_PREFIX_OPCODE
:
608 case SS_PREFIX_OPCODE
:
612 case REPNE_PREFIX_OPCODE
:
613 case REPE_PREFIX_OPCODE
:
616 case LOCK_PREFIX_OPCODE
:
624 case ADDR_PREFIX_OPCODE
:
628 case DATA_PREFIX_OPCODE
:
635 as_bad (_("same type of prefix used twice"));
640 i
.prefix
[q
] = prefix
;
645 set_code_flag (value
)
649 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
650 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
651 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
653 as_bad (_("64bit mode not supported on this CPU."));
655 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
657 as_bad (_("32bit mode not supported on this CPU."));
663 set_16bit_gcc_code_flag (new_code_flag
)
666 flag_code
= new_code_flag
;
667 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
668 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
673 set_intel_syntax (syntax_flag
)
676 /* Find out if register prefixing is specified. */
677 int ask_naked_reg
= 0;
680 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
682 char *string
= input_line_pointer
;
683 int e
= get_symbol_end ();
685 if (strcmp (string
, "prefix") == 0)
687 else if (strcmp (string
, "noprefix") == 0)
690 as_bad (_("bad argument to syntax directive."));
691 *input_line_pointer
= e
;
693 demand_empty_rest_of_line ();
695 intel_syntax
= syntax_flag
;
697 if (ask_naked_reg
== 0)
700 allow_naked_reg
= (intel_syntax
701 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
703 /* Conservative default. */
708 allow_naked_reg
= (ask_naked_reg
< 0);
713 int dummy ATTRIBUTE_UNUSED
;
717 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
719 char *string
= input_line_pointer
;
720 int e
= get_symbol_end ();
723 for (i
= 0; cpu_arch
[i
].name
; i
++)
725 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
727 cpu_arch_name
= cpu_arch
[i
].name
;
728 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
732 if (!cpu_arch
[i
].name
)
733 as_bad (_("no such architecture: `%s'"), string
);
735 *input_line_pointer
= e
;
738 as_bad (_("missing cpu architecture"));
740 demand_empty_rest_of_line ();
743 const pseudo_typeS md_pseudo_table
[] =
745 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
746 {"align", s_align_bytes
, 0},
748 {"align", s_align_ptwo
, 0},
750 {"arch", set_cpu_arch
, 0},
754 {"ffloat", float_cons
, 'f'},
755 {"dfloat", float_cons
, 'd'},
756 {"tfloat", float_cons
, 'x'},
758 {"noopt", s_ignore
, 0},
759 {"optim", s_ignore
, 0},
760 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
761 {"code16", set_code_flag
, CODE_16BIT
},
762 {"code32", set_code_flag
, CODE_32BIT
},
763 {"code64", set_code_flag
, CODE_64BIT
},
764 {"intel_syntax", set_intel_syntax
, 1},
765 {"att_syntax", set_intel_syntax
, 0},
766 {"file", dwarf2_directive_file
, 0},
767 {"loc", dwarf2_directive_loc
, 0},
771 /* For interface with expression (). */
772 extern char *input_line_pointer
;
774 /* Hash table for instruction mnemonic lookup. */
775 static struct hash_control
*op_hash
;
777 /* Hash table for register lookup. */
778 static struct hash_control
*reg_hash
;
783 const char *hash_err
;
785 /* Initialize op_hash hash table. */
786 op_hash
= hash_new ();
789 register const template *optab
;
790 register templates
*core_optab
;
792 /* Setup for loop. */
794 core_optab
= (templates
*) xmalloc (sizeof (templates
));
795 core_optab
->start
= optab
;
800 if (optab
->name
== NULL
801 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
803 /* different name --> ship out current template list;
804 add to hash table; & begin anew. */
805 core_optab
->end
= optab
;
806 hash_err
= hash_insert (op_hash
,
811 as_fatal (_("Internal Error: Can't hash %s: %s"),
815 if (optab
->name
== NULL
)
817 core_optab
= (templates
*) xmalloc (sizeof (templates
));
818 core_optab
->start
= optab
;
823 /* Initialize reg_hash hash table. */
824 reg_hash
= hash_new ();
826 register const reg_entry
*regtab
;
828 for (regtab
= i386_regtab
;
829 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
832 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
834 as_fatal (_("Internal Error: Can't hash %s: %s"),
840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
845 for (c
= 0; c
< 256; c
++)
850 mnemonic_chars
[c
] = c
;
851 register_chars
[c
] = c
;
852 operand_chars
[c
] = c
;
854 else if (islower (c
))
856 mnemonic_chars
[c
] = c
;
857 register_chars
[c
] = c
;
858 operand_chars
[c
] = c
;
860 else if (isupper (c
))
862 mnemonic_chars
[c
] = tolower (c
);
863 register_chars
[c
] = mnemonic_chars
[c
];
864 operand_chars
[c
] = c
;
867 if (isalpha (c
) || isdigit (c
))
868 identifier_chars
[c
] = c
;
871 identifier_chars
[c
] = c
;
872 operand_chars
[c
] = c
;
877 identifier_chars
['@'] = '@';
879 digit_chars
['-'] = '-';
880 identifier_chars
['_'] = '_';
881 identifier_chars
['.'] = '.';
883 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
884 operand_chars
[(unsigned char) *p
] = *p
;
887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
888 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
890 record_alignment (text_section
, 2);
891 record_alignment (data_section
, 2);
892 record_alignment (bss_section
, 2);
898 i386_print_statistics (file
)
901 hash_print_statistics (file
, "i386 opcode", op_hash
);
902 hash_print_statistics (file
, "i386 register", reg_hash
);
907 /* Debugging routines for md_assemble. */
908 static void pi
PARAMS ((char *, i386_insn
*));
909 static void pte
PARAMS ((template *));
910 static void pt
PARAMS ((unsigned int));
911 static void pe
PARAMS ((expressionS
*));
912 static void ps
PARAMS ((symbolS
*));
919 register template *p
;
922 fprintf (stdout
, "%s: template ", line
);
924 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
925 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
926 fprintf (stdout
, " base %x index %x scale %x\n",
927 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
928 for (i
= 0; i
< x
->operands
; i
++)
930 fprintf (stdout
, " #%d: ", i
+ 1);
932 fprintf (stdout
, "\n");
934 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
935 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
936 if (x
->types
[i
] & Imm
)
938 if (x
->types
[i
] & Disp
)
948 fprintf (stdout
, " %d operands ", t
->operands
);
949 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
950 if (t
->extension_opcode
!= None
)
951 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
952 if (t
->opcode_modifier
& D
)
953 fprintf (stdout
, "D");
954 if (t
->opcode_modifier
& W
)
955 fprintf (stdout
, "W");
956 fprintf (stdout
, "\n");
957 for (i
= 0; i
< t
->operands
; i
++)
959 fprintf (stdout
, " #%d type ", i
+ 1);
960 pt (t
->operand_types
[i
]);
961 fprintf (stdout
, "\n");
969 fprintf (stdout
, " operation %d\n", e
->X_op
);
970 fprintf (stdout
, " add_number %ld (%lx)\n",
971 (long) e
->X_add_number
, (long) e
->X_add_number
);
974 fprintf (stdout
, " add_symbol ");
975 ps (e
->X_add_symbol
);
976 fprintf (stdout
, "\n");
980 fprintf (stdout
, " op_symbol ");
982 fprintf (stdout
, "\n");
990 fprintf (stdout
, "%s type %s%s",
992 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
993 segment_name (S_GET_SEGMENT (s
)));
1012 { BaseIndex
, "BaseIndex" },
1016 { InOutPortReg
, "InOutPortReg" },
1017 { ShiftCount
, "ShiftCount" },
1018 { Control
, "control reg" },
1019 { Test
, "test reg" },
1020 { Debug
, "debug reg" },
1021 { FloatReg
, "FReg" },
1022 { FloatAcc
, "FAcc" },
1026 { JumpAbsolute
, "Jump Absolute" },
1037 register struct type_name
*ty
;
1041 fprintf (stdout
, _("Unknown"));
1045 for (ty
= type_names
; ty
->mask
; ty
++)
1047 fprintf (stdout
, "%s, ", ty
->tname
);
1052 #endif /* DEBUG386 */
1055 tc_i386_force_relocation (fixp
)
1058 #ifdef BFD_ASSEMBLER
1059 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1060 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1065 return fixp
->fx_r_type
== 7;
1069 #ifdef BFD_ASSEMBLER
1071 static bfd_reloc_code_real_type
1072 reloc (size
, pcrel
, sign
, other
)
1076 bfd_reloc_code_real_type other
;
1078 if (other
!= NO_RELOC
)
1084 as_bad(_("There are no unsigned pc-relative relocations"));
1087 case 1: return BFD_RELOC_8_PCREL
;
1088 case 2: return BFD_RELOC_16_PCREL
;
1089 case 4: return BFD_RELOC_32_PCREL
;
1091 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1098 case 4: return BFD_RELOC_X86_64_32S
;
1103 case 1: return BFD_RELOC_8
;
1104 case 2: return BFD_RELOC_16
;
1105 case 4: return BFD_RELOC_32
;
1106 case 8: return BFD_RELOC_64
;
1108 as_bad (_("can not do %s %d byte relocation"),
1109 sign
? "signed" : "unsigned", size
);
1113 return BFD_RELOC_NONE
;
1116 /* Here we decide which fixups can be adjusted to make them relative to
1117 the beginning of the section instead of the symbol. Basically we need
1118 to make sure that the dynamic relocations are done correctly, so in
1119 some cases we force the original symbol to be used. */
1122 tc_i386_fix_adjustable (fixP
)
1125 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1126 /* Prevent all adjustments to global symbols, or else dynamic
1127 linking will not work correctly. */
1128 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1129 || S_IS_WEAK (fixP
->fx_addsy
))
1132 /* adjust_reloc_syms doesn't know about the GOT. */
1133 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1134 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1135 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1136 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1137 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1138 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1139 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1144 #define reloc(SIZE,PCREL,OTHER) 0
1145 #define BFD_RELOC_16 0
1146 #define BFD_RELOC_32 0
1147 #define BFD_RELOC_16_PCREL 0
1148 #define BFD_RELOC_32_PCREL 0
1149 #define BFD_RELOC_386_PLT32 0
1150 #define BFD_RELOC_386_GOT32 0
1151 #define BFD_RELOC_386_GOTOFF 0
1152 #define BFD_RELOC_X86_64_PLT32 0
1153 #define BFD_RELOC_X86_64_GOT32 0
1156 static int intel_float_operand
PARAMS ((char *mnemonic
));
1159 intel_float_operand (mnemonic
)
1162 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1165 if (mnemonic
[0] == 'f')
1171 /* This is the guts of the machine-dependent assembler. LINE points to a
1172 machine dependent instruction. This function is supposed to emit
1173 the frags/bytes it assembles to. */
1179 /* Points to template once we've found it. */
1182 /* Count the size of the instruction generated. */
1187 char mnemonic
[MAX_MNEM_SIZE
];
1189 /* Initialize globals. */
1190 memset (&i
, '\0', sizeof (i
));
1191 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1192 i
.disp_reloc
[j
] = NO_RELOC
;
1193 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1194 memset (im_expressions
, '\0', sizeof (im_expressions
));
1195 save_stack_p
= save_stack
;
1197 /* First parse an instruction mnemonic & call i386_operand for the operands.
1198 We assume that the scrubber has arranged it so that line[0] is the valid
1199 start of a (possibly prefixed) mnemonic. */
1202 char *token_start
= l
;
1205 /* Non-zero if we found a prefix only acceptable with string insns. */
1206 const char *expecting_string_instruction
= NULL
;
1211 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1214 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1216 as_bad (_("no such instruction: `%s'"), token_start
);
1221 if (!is_space_char (*l
)
1222 && *l
!= END_OF_INSN
1223 && *l
!= PREFIX_SEPARATOR
)
1225 as_bad (_("invalid character %s in mnemonic"),
1226 output_invalid (*l
));
1229 if (token_start
== l
)
1231 if (*l
== PREFIX_SEPARATOR
)
1232 as_bad (_("expecting prefix; got nothing"));
1234 as_bad (_("expecting mnemonic; got nothing"));
1238 /* Look up instruction (or prefix) via hash table. */
1239 current_templates
= hash_find (op_hash
, mnemonic
);
1241 if (*l
!= END_OF_INSN
1242 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1243 && current_templates
1244 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1246 /* If we are in 16-bit mode, do not allow addr16 or data16.
1247 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1248 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1249 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1250 ^ (flag_code
== CODE_16BIT
)))
1252 as_bad (_("redundant %s prefix"),
1253 current_templates
->start
->name
);
1256 /* Add prefix, checking for repeated prefixes. */
1257 switch (add_prefix (current_templates
->start
->base_opcode
))
1262 expecting_string_instruction
= current_templates
->start
->name
;
1265 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1272 if (!current_templates
)
1274 /* See if we can get a match by trimming off a suffix. */
1277 case WORD_MNEM_SUFFIX
:
1278 case BYTE_MNEM_SUFFIX
:
1279 case QWORD_MNEM_SUFFIX
:
1280 i
.suffix
= mnem_p
[-1];
1282 current_templates
= hash_find (op_hash
, mnemonic
);
1284 case SHORT_MNEM_SUFFIX
:
1285 case LONG_MNEM_SUFFIX
:
1288 i
.suffix
= mnem_p
[-1];
1290 current_templates
= hash_find (op_hash
, mnemonic
);
1298 if (intel_float_operand (mnemonic
))
1299 i
.suffix
= SHORT_MNEM_SUFFIX
;
1301 i
.suffix
= LONG_MNEM_SUFFIX
;
1303 current_templates
= hash_find (op_hash
, mnemonic
);
1307 if (!current_templates
)
1309 as_bad (_("no such instruction: `%s'"), token_start
);
1314 /* Check if instruction is supported on specified architecture. */
1315 if (cpu_arch_flags
!= 0)
1317 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1318 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1320 as_warn (_("`%s' is not supported on `%s'"),
1321 current_templates
->start
->name
, cpu_arch_name
);
1323 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1325 as_warn (_("use .code16 to ensure correct addressing mode"));
1329 /* Check for rep/repne without a string instruction. */
1330 if (expecting_string_instruction
1331 && !(current_templates
->start
->opcode_modifier
& IsString
))
1333 as_bad (_("expecting string instruction after `%s'"),
1334 expecting_string_instruction
);
1338 /* There may be operands to parse. */
1339 if (*l
!= END_OF_INSN
)
1341 /* 1 if operand is pending after ','. */
1342 unsigned int expecting_operand
= 0;
1344 /* Non-zero if operand parens not balanced. */
1345 unsigned int paren_not_balanced
;
1349 /* Skip optional white space before operand. */
1350 if (is_space_char (*l
))
1352 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1354 as_bad (_("invalid character %s before operand %d"),
1355 output_invalid (*l
),
1359 token_start
= l
; /* after white space */
1360 paren_not_balanced
= 0;
1361 while (paren_not_balanced
|| *l
!= ',')
1363 if (*l
== END_OF_INSN
)
1365 if (paren_not_balanced
)
1368 as_bad (_("unbalanced parenthesis in operand %d."),
1371 as_bad (_("unbalanced brackets in operand %d."),
1376 break; /* we are done */
1378 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1380 as_bad (_("invalid character %s in operand %d"),
1381 output_invalid (*l
),
1388 ++paren_not_balanced
;
1390 --paren_not_balanced
;
1395 ++paren_not_balanced
;
1397 --paren_not_balanced
;
1401 if (l
!= token_start
)
1402 { /* Yes, we've read in another operand. */
1403 unsigned int operand_ok
;
1404 this_operand
= i
.operands
++;
1405 if (i
.operands
> MAX_OPERANDS
)
1407 as_bad (_("spurious operands; (%d operands/instruction max)"),
1411 /* Now parse operand adding info to 'i' as we go along. */
1412 END_STRING_AND_SAVE (l
);
1416 i386_intel_operand (token_start
,
1417 intel_float_operand (mnemonic
));
1419 operand_ok
= i386_operand (token_start
);
1421 RESTORE_END_STRING (l
);
1427 if (expecting_operand
)
1429 expecting_operand_after_comma
:
1430 as_bad (_("expecting operand after ','; got nothing"));
1435 as_bad (_("expecting operand before ','; got nothing"));
1440 /* Now *l must be either ',' or END_OF_INSN. */
1443 if (*++l
== END_OF_INSN
)
1445 /* Just skip it, if it's \n complain. */
1446 goto expecting_operand_after_comma
;
1448 expecting_operand
= 1;
1451 while (*l
!= END_OF_INSN
);
1455 /* Now we've parsed the mnemonic into a set of templates, and have the
1458 Next, we find a template that matches the given insn,
1459 making sure the overlap of the given operands types is consistent
1460 with the template operand types. */
1462 #define MATCH(overlap, given, template) \
1463 ((overlap & ~JumpAbsolute) \
1464 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1466 /* If given types r0 and r1 are registers they must be of the same type
1467 unless the expected operand type register overlap is null.
1468 Note that Acc in a template matches every size of reg. */
1469 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1470 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1471 ((g0) & Reg) == ((g1) & Reg) || \
1472 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1475 register unsigned int overlap0
, overlap1
;
1476 unsigned int overlap2
;
1477 unsigned int found_reverse_match
;
1480 /* All intel opcodes have reversed operands except for "bound" and
1481 "enter". We also don't reverse intersegment "jmp" and "call"
1482 instructions with 2 immediate operands so that the immediate segment
1483 precedes the offset, as it does when in AT&T mode. "enter" and the
1484 intersegment "jmp" and "call" instructions are the only ones that
1485 have two immediate operands. */
1486 if (intel_syntax
&& i
.operands
> 1
1487 && (strcmp (mnemonic
, "bound") != 0)
1488 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1490 union i386_op temp_op
;
1491 unsigned int temp_type
;
1492 #ifdef BFD_ASSEMBLER
1493 enum bfd_reloc_code_real temp_reloc
;
1500 if (i
.operands
== 2)
1505 else if (i
.operands
== 3)
1510 temp_type
= i
.types
[xchg2
];
1511 i
.types
[xchg2
] = i
.types
[xchg1
];
1512 i
.types
[xchg1
] = temp_type
;
1513 temp_op
= i
.op
[xchg2
];
1514 i
.op
[xchg2
] = i
.op
[xchg1
];
1515 i
.op
[xchg1
] = temp_op
;
1516 temp_reloc
= i
.disp_reloc
[xchg2
];
1517 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1518 i
.disp_reloc
[xchg1
] = temp_reloc
;
1520 if (i
.mem_operands
== 2)
1522 const seg_entry
*temp_seg
;
1523 temp_seg
= i
.seg
[0];
1524 i
.seg
[0] = i
.seg
[1];
1525 i
.seg
[1] = temp_seg
;
1531 /* Try to ensure constant immediates are represented in the smallest
1533 char guess_suffix
= 0;
1537 guess_suffix
= i
.suffix
;
1538 else if (i
.reg_operands
)
1540 /* Figure out a suffix from the last register operand specified.
1541 We can't do this properly yet, ie. excluding InOutPortReg,
1542 but the following works for instructions with immediates.
1543 In any case, we can't set i.suffix yet. */
1544 for (op
= i
.operands
; --op
>= 0;)
1545 if (i
.types
[op
] & Reg
)
1547 if (i
.types
[op
] & Reg8
)
1548 guess_suffix
= BYTE_MNEM_SUFFIX
;
1549 else if (i
.types
[op
] & Reg16
)
1550 guess_suffix
= WORD_MNEM_SUFFIX
;
1551 else if (i
.types
[op
] & Reg32
)
1552 guess_suffix
= LONG_MNEM_SUFFIX
;
1553 else if (i
.types
[op
] & Reg64
)
1554 guess_suffix
= QWORD_MNEM_SUFFIX
;
1558 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1559 guess_suffix
= WORD_MNEM_SUFFIX
;
1561 for (op
= i
.operands
; --op
>= 0;)
1562 if (i
.types
[op
] & Imm
)
1564 switch (i
.op
[op
].imms
->X_op
)
1567 /* If a suffix is given, this operand may be shortened. */
1568 switch (guess_suffix
)
1570 case LONG_MNEM_SUFFIX
:
1571 i
.types
[op
] |= Imm32
| Imm64
;
1573 case WORD_MNEM_SUFFIX
:
1574 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1576 case BYTE_MNEM_SUFFIX
:
1577 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1581 /* If this operand is at most 16 bits, convert it to a
1582 signed 16 bit number before trying to see whether it will
1583 fit in an even smaller size. This allows a 16-bit operand
1584 such as $0xffe0 to be recognised as within Imm8S range. */
1585 if ((i
.types
[op
] & Imm16
)
1586 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1588 i
.op
[op
].imms
->X_add_number
=
1589 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1591 if ((i
.types
[op
] & Imm32
)
1592 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1594 i
.op
[op
].imms
->X_add_number
=
1595 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1597 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1598 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1599 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1600 i
.types
[op
] &= ~Imm32
;
1605 /* Symbols and expressions. */
1607 /* Convert symbolic operand to proper sizes for matching. */
1608 switch (guess_suffix
)
1610 case QWORD_MNEM_SUFFIX
:
1611 i
.types
[op
] = Imm64
| Imm32S
;
1613 case LONG_MNEM_SUFFIX
:
1614 i
.types
[op
] = Imm32
| Imm64
;
1616 case WORD_MNEM_SUFFIX
:
1617 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1620 case BYTE_MNEM_SUFFIX
:
1621 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1630 if (i
.disp_operands
)
1632 /* Try to use the smallest displacement type too. */
1635 for (op
= i
.operands
; --op
>= 0;)
1636 if ((i
.types
[op
] & Disp
)
1637 && i
.op
[op
].imms
->X_op
== O_constant
)
1639 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1641 if (i
.types
[op
] & Disp16
)
1643 /* We know this operand is at most 16 bits, so
1644 convert to a signed 16 bit number before trying
1645 to see whether it will fit in an even smaller
1648 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1650 else if (i
.types
[op
] & Disp32
)
1652 /* We know this operand is at most 32 bits, so convert to a
1653 signed 32 bit number before trying to see whether it will
1654 fit in an even smaller size. */
1655 disp
&= (((offsetT
) 2 << 31) - 1);
1656 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1658 if (flag_code
== CODE_64BIT
)
1660 if (fits_in_signed_long (disp
))
1661 i
.types
[op
] |= Disp32S
;
1662 if (fits_in_unsigned_long (disp
))
1663 i
.types
[op
] |= Disp32
;
1665 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1666 && fits_in_signed_byte (disp
))
1667 i
.types
[op
] |= Disp8
;
1674 found_reverse_match
= 0;
1675 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1677 : (i
.suffix
== WORD_MNEM_SUFFIX
1679 : (i
.suffix
== SHORT_MNEM_SUFFIX
1681 : (i
.suffix
== LONG_MNEM_SUFFIX
1683 : (i
.suffix
== QWORD_MNEM_SUFFIX
1685 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1687 for (t
= current_templates
->start
;
1688 t
< current_templates
->end
;
1691 /* Must have right number of operands. */
1692 if (i
.operands
!= t
->operands
)
1695 /* Check the suffix, except for some instructions in intel mode. */
1696 if ((t
->opcode_modifier
& suffix_check
)
1698 && (t
->opcode_modifier
& IgnoreSize
))
1700 && t
->base_opcode
== 0xd9
1701 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1702 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1705 else if (!t
->operands
)
1706 /* 0 operands always matches. */
1709 overlap0
= i
.types
[0] & t
->operand_types
[0];
1710 switch (t
->operands
)
1713 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1718 overlap1
= i
.types
[1] & t
->operand_types
[1];
1719 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1720 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1721 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1722 t
->operand_types
[0],
1723 overlap1
, i
.types
[1],
1724 t
->operand_types
[1]))
1726 /* Check if other direction is valid ... */
1727 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1730 /* Try reversing direction of operands. */
1731 overlap0
= i
.types
[0] & t
->operand_types
[1];
1732 overlap1
= i
.types
[1] & t
->operand_types
[0];
1733 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1734 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1735 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1736 t
->operand_types
[1],
1737 overlap1
, i
.types
[1],
1738 t
->operand_types
[0]))
1740 /* Does not match either direction. */
1743 /* found_reverse_match holds which of D or FloatDR
1745 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1747 /* Found a forward 2 operand match here. */
1748 else if (t
->operands
== 3)
1750 /* Here we make use of the fact that there are no
1751 reverse match 3 operand instructions, and all 3
1752 operand instructions only need to be checked for
1753 register consistency between operands 2 and 3. */
1754 overlap2
= i
.types
[2] & t
->operand_types
[2];
1755 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1756 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1757 t
->operand_types
[1],
1758 overlap2
, i
.types
[2],
1759 t
->operand_types
[2]))
1763 /* Found either forward/reverse 2 or 3 operand match here:
1764 slip through to break. */
1766 if (t
->cpu_flags
& ~cpu_arch_flags
)
1768 found_reverse_match
= 0;
1771 /* We've found a match; break out of loop. */
1774 if (t
== current_templates
->end
)
1776 /* We found no match. */
1777 as_bad (_("suffix or operands invalid for `%s'"),
1778 current_templates
->start
->name
);
1782 if (!quiet_warnings
)
1785 && ((i
.types
[0] & JumpAbsolute
)
1786 != (t
->operand_types
[0] & JumpAbsolute
)))
1788 as_warn (_("indirect %s without `*'"), t
->name
);
1791 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1792 == (IsPrefix
|IgnoreSize
))
1794 /* Warn them that a data or address size prefix doesn't
1795 affect assembly of the next line of code. */
1796 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1800 /* Copy the template we found. */
1802 if (found_reverse_match
)
1804 /* If we found a reverse match we must alter the opcode
1805 direction bit. found_reverse_match holds bits to change
1806 (different for int & float insns). */
1808 i
.tm
.base_opcode
^= found_reverse_match
;
1810 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1811 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1814 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1817 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1818 i
.tm
.base_opcode
^= FloatR
;
1820 if (i
.tm
.opcode_modifier
& FWait
)
1821 if (! add_prefix (FWAIT_OPCODE
))
1824 /* Check string instruction segment overrides. */
1825 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1827 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1828 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1830 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1832 as_bad (_("`%s' operand %d must use `%%es' segment"),
1837 /* There's only ever one segment override allowed per instruction.
1838 This instruction possibly has a legal segment override on the
1839 second operand, so copy the segment to where non-string
1840 instructions store it, allowing common code. */
1841 i
.seg
[0] = i
.seg
[1];
1843 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1845 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1847 as_bad (_("`%s' operand %d must use `%%es' segment"),
1855 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1858 for (op
= i
.operands
; --op
>= 0; )
1859 if ((i
.types
[op
] & Reg
)
1860 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1861 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1862 i
.op
[op
].regs
->reg_name
);
1865 /* If matched instruction specifies an explicit instruction mnemonic
1867 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1869 if (i
.tm
.opcode_modifier
& Size16
)
1870 i
.suffix
= WORD_MNEM_SUFFIX
;
1871 else if (i
.tm
.opcode_modifier
& Size64
)
1872 i
.suffix
= QWORD_MNEM_SUFFIX
;
1874 i
.suffix
= LONG_MNEM_SUFFIX
;
1876 else if (i
.reg_operands
)
1878 /* If there's no instruction mnemonic suffix we try to invent one
1879 based on register operands. */
1882 /* We take i.suffix from the last register operand specified,
1883 Destination register type is more significant than source
1886 for (op
= i
.operands
; --op
>= 0;)
1887 if ((i
.types
[op
] & Reg
)
1888 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1890 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1891 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1892 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1897 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1900 for (op
= i
.operands
; --op
>= 0;)
1902 /* If this is an eight bit register, it's OK. If it's
1903 the 16 or 32 bit version of an eight bit register,
1904 we will just use the low portion, and that's OK too. */
1905 if (i
.types
[op
] & Reg8
)
1908 /* movzx and movsx should not generate this warning. */
1910 && (i
.tm
.base_opcode
== 0xfb7
1911 || i
.tm
.base_opcode
== 0xfb6
1912 || i
.tm
.base_opcode
== 0x63
1913 || i
.tm
.base_opcode
== 0xfbe
1914 || i
.tm
.base_opcode
== 0xfbf))
1917 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1919 /* Check that the template allows eight bit regs
1920 This kills insns such as `orb $1,%edx', which
1921 maybe should be allowed. */
1922 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1926 /* Prohibit these changes in the 64bit mode, since
1927 the lowering is more complicated. */
1928 if (flag_code
== CODE_64BIT
1929 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1930 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1931 i
.op
[op
].regs
->reg_name
,
1933 #if REGISTER_WARNINGS
1935 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1936 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1937 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1938 i
.op
[op
].regs
->reg_name
,
1943 /* Any other register is bad. */
1944 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1946 | Control
| Debug
| Test
1947 | FloatReg
| FloatAcc
))
1949 as_bad (_("`%%%s' not allowed with `%s%c'"),
1950 i
.op
[op
].regs
->reg_name
,
1957 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1961 for (op
= i
.operands
; --op
>= 0;)
1962 /* Reject eight bit registers, except where the template
1963 requires them. (eg. movzb) */
1964 if ((i
.types
[op
] & Reg8
) != 0
1965 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1967 as_bad (_("`%%%s' not allowed with `%s%c'"),
1968 i
.op
[op
].regs
->reg_name
,
1973 /* Warn if the e prefix on a general reg is missing. */
1974 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
1975 && (i
.types
[op
] & Reg16
) != 0
1976 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1978 /* Prohibit these changes in the 64bit mode, since
1979 the lowering is more complicated. */
1980 if (flag_code
== CODE_64BIT
)
1981 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1982 i
.op
[op
].regs
->reg_name
,
1984 #if REGISTER_WARNINGS
1986 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1987 (i
.op
[op
].regs
+ 8)->reg_name
,
1988 i
.op
[op
].regs
->reg_name
,
1992 /* Warn if the r prefix on a general reg is missing. */
1993 else if ((i
.types
[op
] & Reg64
) != 0
1994 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1996 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1997 i
.op
[op
].regs
->reg_name
,
2001 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2004 if (flag_code
< CODE_64BIT
)
2005 as_bad (_("64bit operations available only in 64bit modes."));
2007 for (op
= i
.operands
; --op
>= 0; )
2008 /* Reject eight bit registers, except where the template
2009 requires them. (eg. movzb) */
2010 if ((i
.types
[op
] & Reg8
) != 0
2011 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2013 as_bad (_("`%%%s' not allowed with `%s%c'"),
2014 i
.op
[op
].regs
->reg_name
,
2019 /* Warn if the e prefix on a general reg is missing. */
2020 else if (((i
.types
[op
] & Reg16
) != 0
2021 || (i
.types
[op
] & Reg32
) != 0)
2022 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2024 /* Prohibit these changes in the 64bit mode, since
2025 the lowering is more complicated. */
2026 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2027 i
.op
[op
].regs
->reg_name
,
2031 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2034 for (op
= i
.operands
; --op
>= 0;)
2035 /* Reject eight bit registers, except where the template
2036 requires them. (eg. movzb) */
2037 if ((i
.types
[op
] & Reg8
) != 0
2038 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2040 as_bad (_("`%%%s' not allowed with `%s%c'"),
2041 i
.op
[op
].regs
->reg_name
,
2046 /* Warn if the e prefix on a general reg is present. */
2047 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2048 && (i
.types
[op
] & Reg32
) != 0
2049 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2051 /* Prohibit these changes in the 64bit mode, since
2052 the lowering is more complicated. */
2053 if (flag_code
== CODE_64BIT
)
2054 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2055 i
.op
[op
].regs
->reg_name
,
2058 #if REGISTER_WARNINGS
2059 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2060 (i
.op
[op
].regs
- 8)->reg_name
,
2061 i
.op
[op
].regs
->reg_name
,
2066 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2067 /* Do nothing if the instruction is going to ignore the prefix. */
2072 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2074 i
.suffix
= stackop_size
;
2076 /* Make still unresolved immediate matches conform to size of immediate
2077 given in i.suffix. Note: overlap2 cannot be an immediate! */
2078 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2079 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2080 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2081 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2085 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2086 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2087 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2089 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2090 || overlap0
== (Imm16
| Imm32
)
2091 || overlap0
== (Imm16
| Imm32S
))
2094 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2096 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2097 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2098 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2100 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2104 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2105 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2106 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2107 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2111 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2112 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2113 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2115 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2116 || overlap1
== (Imm16
| Imm32
)
2117 || overlap1
== (Imm16
| Imm32S
))
2120 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2122 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2123 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2124 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2126 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2130 assert ((overlap2
& Imm
) == 0);
2132 i
.types
[0] = overlap0
;
2133 if (overlap0
& ImplicitRegister
)
2135 if (overlap0
& Imm1
)
2136 i
.imm_operands
= 0; /* kludge for shift insns. */
2138 i
.types
[1] = overlap1
;
2139 if (overlap1
& ImplicitRegister
)
2142 i
.types
[2] = overlap2
;
2143 if (overlap2
& ImplicitRegister
)
2146 /* Finalize opcode. First, we change the opcode based on the operand
2147 size given by i.suffix: We need not change things for byte insns. */
2149 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2151 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2155 /* For movzx and movsx, need to check the register type. */
2157 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2158 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2160 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2162 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2163 if (!add_prefix (prefix
))
2167 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2169 /* It's not a byte, select word/dword operation. */
2170 if (i
.tm
.opcode_modifier
& W
)
2172 if (i
.tm
.opcode_modifier
& ShortForm
)
2173 i
.tm
.base_opcode
|= 8;
2175 i
.tm
.base_opcode
|= 1;
2177 /* Now select between word & dword operations via the operand
2178 size prefix, except for instructions that will ignore this
2180 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2181 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2182 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2184 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2185 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2186 prefix
= ADDR_PREFIX_OPCODE
;
2188 if (! add_prefix (prefix
))
2192 /* Set mode64 for an operand. */
2193 if (i
.suffix
== QWORD_MNEM_SUFFIX
2194 && !(i
.tm
.opcode_modifier
& NoRex64
))
2197 /* Size floating point instruction. */
2198 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2200 if (i
.tm
.opcode_modifier
& FloatMF
)
2201 i
.tm
.base_opcode
^= 4;
2205 if (i
.tm
.opcode_modifier
& ImmExt
)
2207 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2208 opcode suffix which is coded in the same place as an 8-bit
2209 immediate field would be. Here we fake an 8-bit immediate
2210 operand from the opcode suffix stored in tm.extension_opcode. */
2214 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2216 exp
= &im_expressions
[i
.imm_operands
++];
2217 i
.op
[i
.operands
].imms
= exp
;
2218 i
.types
[i
.operands
++] = Imm8
;
2219 exp
->X_op
= O_constant
;
2220 exp
->X_add_number
= i
.tm
.extension_opcode
;
2221 i
.tm
.extension_opcode
= None
;
2224 /* For insns with operands there are more diddles to do to the opcode. */
2227 /* Default segment register this instruction will use
2228 for memory accesses. 0 means unknown.
2229 This is only for optimizing out unnecessary segment overrides. */
2230 const seg_entry
*default_seg
= 0;
2232 /* The imul $imm, %reg instruction is converted into
2233 imul $imm, %reg, %reg, and the clr %reg instruction
2234 is converted into xor %reg, %reg. */
2235 if (i
.tm
.opcode_modifier
& regKludge
)
2237 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2238 /* Pretend we saw the extra register operand. */
2239 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2240 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2241 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2245 if (i
.tm
.opcode_modifier
& ShortForm
)
2247 /* The register or float register operand is in operand 0 or 1. */
2248 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2249 /* Register goes in low 3 bits of opcode. */
2250 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2251 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2253 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2255 /* Warn about some common errors, but press on regardless.
2256 The first case can be generated by gcc (<= 2.8.1). */
2257 if (i
.operands
== 2)
2259 /* Reversed arguments on faddp, fsubp, etc. */
2260 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2261 i
.op
[1].regs
->reg_name
,
2262 i
.op
[0].regs
->reg_name
);
2266 /* Extraneous `l' suffix on fp insn. */
2267 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2268 i
.op
[0].regs
->reg_name
);
2272 else if (i
.tm
.opcode_modifier
& Modrm
)
2274 /* The opcode is completed (modulo i.tm.extension_opcode which
2275 must be put into the modrm byte).
2276 Now, we make the modrm & index base bytes based on all the
2277 info we've collected. */
2279 /* i.reg_operands MUST be the number of real register operands;
2280 implicit registers do not count. */
2281 if (i
.reg_operands
== 2)
2283 unsigned int source
, dest
;
2284 source
= ((i
.types
[0]
2285 & (Reg
| RegMMX
| RegXMM
2287 | Control
| Debug
| Test
))
2292 /* One of the register operands will be encoded in the
2293 i.tm.reg field, the other in the combined i.tm.mode
2294 and i.tm.regmem fields. If no form of this
2295 instruction supports a memory destination operand,
2296 then we assume the source operand may sometimes be
2297 a memory operand and so we need to store the
2298 destination in the i.rm.reg field. */
2299 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2301 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2302 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2303 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2305 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2310 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2311 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2312 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2314 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2319 { /* If it's not 2 reg operands... */
2322 unsigned int fake_zero_displacement
= 0;
2323 unsigned int op
= ((i
.types
[0] & AnyMem
)
2325 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2332 if (! i
.disp_operands
)
2333 fake_zero_displacement
= 1;
2336 /* Operand is just <disp> */
2337 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2339 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2340 i
.types
[op
] &= ~Disp
;
2341 i
.types
[op
] |= Disp16
;
2343 else if (flag_code
!= CODE_64BIT
)
2345 i
.rm
.regmem
= NO_BASE_REGISTER
;
2346 i
.types
[op
] &= ~Disp
;
2347 i
.types
[op
] |= Disp32
;
2351 /* 64bit mode overwrites the 32bit absolute addressing
2352 by RIP relative addressing and absolute addressing
2353 is encoded by one of the redundant SIB forms. */
2355 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2356 i
.sib
.base
= NO_BASE_REGISTER
;
2357 i
.sib
.index
= NO_INDEX_REGISTER
;
2358 i
.types
[op
] &= ~Disp
;
2359 i
.types
[op
] |= Disp32S
;
2362 else /* ! i.base_reg && i.index_reg */
2364 i
.sib
.index
= i
.index_reg
->reg_num
;
2365 i
.sib
.base
= NO_BASE_REGISTER
;
2366 i
.sib
.scale
= i
.log2_scale_factor
;
2367 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2368 i
.types
[op
] &= ~Disp
;
2369 if (flag_code
!= CODE_64BIT
)
2370 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2372 i
.types
[op
] |= Disp32S
;
2373 if (i
.index_reg
->reg_flags
& RegRex
)
2377 /* RIP addressing for 64bit mode. */
2378 else if (i
.base_reg
->reg_type
== BaseIndex
)
2380 i
.rm
.regmem
= NO_BASE_REGISTER
;
2381 i
.types
[op
] &= ~Disp
;
2382 i
.types
[op
] |= Disp32S
;
2383 i
.flags
[op
] = Operand_PCrel
;
2385 else if (i
.base_reg
->reg_type
& Reg16
)
2387 switch (i
.base_reg
->reg_num
)
2392 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2393 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2400 if ((i
.types
[op
] & Disp
) == 0)
2402 /* fake (%bp) into 0(%bp) */
2403 i
.types
[op
] |= Disp8
;
2404 fake_zero_displacement
= 1;
2407 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2408 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2410 default: /* (%si) -> 4 or (%di) -> 5 */
2411 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2413 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2415 else /* i.base_reg and 32/64 bit mode */
2417 if (flag_code
== CODE_64BIT
2418 && (i
.types
[op
] & Disp
))
2420 if (i
.types
[op
] & Disp8
)
2421 i
.types
[op
] = Disp8
| Disp32S
;
2423 i
.types
[op
] = Disp32S
;
2425 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2426 if (i
.base_reg
->reg_flags
& RegRex
)
2428 i
.sib
.base
= i
.base_reg
->reg_num
;
2429 /* x86-64 ignores REX prefix bit here to avoid
2430 decoder complications. */
2431 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2434 if (i
.disp_operands
== 0)
2436 fake_zero_displacement
= 1;
2437 i
.types
[op
] |= Disp8
;
2440 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2444 i
.sib
.scale
= i
.log2_scale_factor
;
2447 /* <disp>(%esp) becomes two byte modrm
2448 with no index register. We've already
2449 stored the code for esp in i.rm.regmem
2450 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2451 base register besides %esp will not use
2452 the extra modrm byte. */
2453 i
.sib
.index
= NO_INDEX_REGISTER
;
2454 #if ! SCALE1_WHEN_NO_INDEX
2455 /* Another case where we force the second
2457 if (i
.log2_scale_factor
)
2458 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2463 i
.sib
.index
= i
.index_reg
->reg_num
;
2464 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2465 if (i
.index_reg
->reg_flags
& RegRex
)
2468 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2471 if (fake_zero_displacement
)
2473 /* Fakes a zero displacement assuming that i.types[op]
2474 holds the correct displacement size. */
2477 assert (i
.op
[op
].disps
== 0);
2478 exp
= &disp_expressions
[i
.disp_operands
++];
2479 i
.op
[op
].disps
= exp
;
2480 exp
->X_op
= O_constant
;
2481 exp
->X_add_number
= 0;
2482 exp
->X_add_symbol
= (symbolS
*) 0;
2483 exp
->X_op_symbol
= (symbolS
*) 0;
2487 /* Fill in i.rm.reg or i.rm.regmem field with register
2488 operand (if any) based on i.tm.extension_opcode.
2489 Again, we must be careful to make sure that
2490 segment/control/debug/test/MMX registers are coded
2491 into the i.rm.reg field. */
2496 & (Reg
| RegMMX
| RegXMM
2498 | Control
| Debug
| Test
))
2501 & (Reg
| RegMMX
| RegXMM
2503 | Control
| Debug
| Test
))
2506 /* If there is an extension opcode to put here, the
2507 register number must be put into the regmem field. */
2508 if (i
.tm
.extension_opcode
!= None
)
2510 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2511 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2516 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2517 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2521 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2522 we must set it to 3 to indicate this is a register
2523 operand in the regmem field. */
2524 if (!i
.mem_operands
)
2528 /* Fill in i.rm.reg field with extension opcode (if any). */
2529 if (i
.tm
.extension_opcode
!= None
)
2530 i
.rm
.reg
= i
.tm
.extension_opcode
;
2533 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2535 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2536 && i
.op
[0].regs
->reg_num
== 1)
2538 as_bad (_("you can't `pop %%cs'"));
2541 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2542 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2545 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2549 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2551 /* For the string instructions that allow a segment override
2552 on one of their operands, the default segment is ds. */
2556 /* If a segment was explicitly specified,
2557 and the specified segment is not the default,
2558 use an opcode prefix to select it.
2559 If we never figured out what the default segment is,
2560 then default_seg will be zero at this point,
2561 and the specified segment prefix will always be used. */
2562 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2564 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2568 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2570 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2571 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2575 /* Handle conversion of 'int $3' --> special int3 insn. */
2576 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2578 i
.tm
.base_opcode
= INT3_OPCODE
;
2582 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2583 && i
.op
[0].disps
->X_op
== O_constant
)
2585 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2586 the absolute address given by the constant. Since ix86 jumps and
2587 calls are pc relative, we need to generate a reloc. */
2588 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2589 i
.op
[0].disps
->X_op
= O_symbol
;
2592 if (i
.tm
.opcode_modifier
& Rex64
)
2595 /* For 8bit registers we would need an empty rex prefix.
2596 Also in the case instruction is already having prefix,
2597 we need to convert old registers to new ones. */
2599 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2600 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2601 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2602 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2606 for (x
= 0; x
< 2; x
++)
2608 /* Look for 8bit operand that does use old registers. */
2609 if (i
.types
[x
] & Reg8
2610 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2612 /* In case it is "hi" register, give up. */
2613 if (i
.op
[x
].regs
->reg_num
> 3)
2614 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2615 i
.op
[x
].regs
->reg_name
);
2617 /* Otherwise it is equivalent to the extended register.
2618 Since the encoding don't change this is merely cosmetical
2619 cleanup for debug output. */
2621 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2626 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2628 | (i
.rex
.mode64
? 8 : 0)
2629 | (i
.rex
.extX
? 4 : 0)
2630 | (i
.rex
.extY
? 2 : 0)
2631 | (i
.rex
.extZ
? 1 : 0));
2633 /* We are ready to output the insn. */
2638 if (i
.tm
.opcode_modifier
& Jump
)
2645 if (flag_code
== CODE_16BIT
)
2649 if (i
.prefix
[DATA_PREFIX
])
2655 if (i
.prefix
[REX_PREFIX
])
2665 if (i
.prefixes
!= 0 && !intel_syntax
)
2666 as_warn (_("skipping prefixes on this instruction"));
2668 /* It's always a symbol; End frag & setup for relax.
2669 Make sure there is enough room in this frag for the largest
2670 instruction we may generate in md_convert_frag. This is 2
2671 bytes for the opcode and room for the prefix and largest
2673 frag_grow (prefix
+ 2 + size
);
2674 insn_size
+= prefix
+ 1;
2675 /* Prefix and 1 opcode byte go in fr_fix. */
2676 p
= frag_more (prefix
+ 1);
2677 if (i
.prefix
[DATA_PREFIX
])
2678 *p
++ = DATA_PREFIX_OPCODE
;
2679 if (i
.prefix
[REX_PREFIX
])
2680 *p
++ = i
.prefix
[REX_PREFIX
];
2681 *p
= i
.tm
.base_opcode
;
2682 /* 1 possible extra opcode + displacement go in var part.
2683 Pass reloc in fr_var. */
2684 frag_var (rs_machine_dependent
,
2687 ((unsigned char) *p
== JUMP_PC_RELATIVE
2688 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2689 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2690 i
.op
[0].disps
->X_add_symbol
,
2691 i
.op
[0].disps
->X_add_number
,
2694 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2698 if (i
.tm
.opcode_modifier
& JumpByte
)
2700 /* This is a loop or jecxz type instruction. */
2702 if (i
.prefix
[ADDR_PREFIX
])
2705 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2714 if (flag_code
== CODE_16BIT
)
2717 if (i
.prefix
[DATA_PREFIX
])
2720 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2730 if (i
.prefix
[REX_PREFIX
])
2732 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2737 if (i
.prefixes
!= 0 && !intel_syntax
)
2738 as_warn (_("skipping prefixes on this instruction"));
2740 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2742 insn_size
+= 1 + size
;
2743 p
= frag_more (1 + size
);
2747 /* Opcode can be at most two bytes. */
2748 insn_size
+= 2 + size
;
2749 p
= frag_more (2 + size
);
2750 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2752 *p
++ = i
.tm
.base_opcode
& 0xff;
2754 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2755 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2757 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2764 if (flag_code
== CODE_16BIT
)
2768 if (i
.prefix
[DATA_PREFIX
])
2774 if (i
.prefix
[REX_PREFIX
])
2784 if (i
.prefixes
!= 0 && !intel_syntax
)
2785 as_warn (_("skipping prefixes on this instruction"));
2787 /* 1 opcode; 2 segment; offset */
2788 insn_size
+= prefix
+ 1 + 2 + size
;
2789 p
= frag_more (prefix
+ 1 + 2 + size
);
2791 if (i
.prefix
[DATA_PREFIX
])
2792 *p
++ = DATA_PREFIX_OPCODE
;
2794 if (i
.prefix
[REX_PREFIX
])
2795 *p
++ = i
.prefix
[REX_PREFIX
];
2797 *p
++ = i
.tm
.base_opcode
;
2798 if (i
.op
[1].imms
->X_op
== O_constant
)
2800 offsetT n
= i
.op
[1].imms
->X_add_number
;
2803 && !fits_in_unsigned_word (n
)
2804 && !fits_in_signed_word (n
))
2806 as_bad (_("16-bit jump out of range"));
2809 md_number_to_chars (p
, n
, size
);
2812 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2813 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2814 if (i
.op
[0].imms
->X_op
!= O_constant
)
2815 as_bad (_("can't handle non absolute segment in `%s'"),
2817 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2821 /* Output normal instructions here. */
2824 /* The prefix bytes. */
2826 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2833 md_number_to_chars (p
, (valueT
) *q
, 1);
2837 /* Now the opcode; be careful about word order here! */
2838 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2841 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2843 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2847 /* Put out high byte first: can't use md_number_to_chars! */
2848 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2849 *p
= i
.tm
.base_opcode
& 0xff;
2852 { /* Opcode is either 3 or 4 bytes. */
2853 if (i
.tm
.base_opcode
& 0xff000000)
2857 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2864 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2865 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2866 *p
= (i
.tm
.base_opcode
) & 0xff;
2869 /* Now the modrm byte and sib byte (if present). */
2870 if (i
.tm
.opcode_modifier
& Modrm
)
2874 md_number_to_chars (p
,
2875 (valueT
) (i
.rm
.regmem
<< 0
2879 /* If i.rm.regmem == ESP (4)
2880 && i.rm.mode != (Register mode)
2882 ==> need second modrm byte. */
2883 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2885 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2889 md_number_to_chars (p
,
2890 (valueT
) (i
.sib
.base
<< 0
2892 | i
.sib
.scale
<< 6),
2897 if (i
.disp_operands
)
2899 register unsigned int n
;
2901 for (n
= 0; n
< i
.operands
; n
++)
2903 if (i
.types
[n
] & Disp
)
2905 if (i
.op
[n
].disps
->X_op
== O_constant
)
2911 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2914 if (i
.types
[n
] & Disp8
)
2916 if (i
.types
[n
] & Disp64
)
2919 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2922 p
= frag_more (size
);
2923 md_number_to_chars (p
, val
, size
);
2929 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2931 /* The PC relative address is computed relative
2932 to the instruction boundary, so in case immediate
2933 fields follows, we need to adjust the value. */
2934 if (pcrel
&& i
.imm_operands
)
2937 register unsigned int n1
;
2939 for (n1
= 0; n1
< i
.operands
; n1
++)
2940 if (i
.types
[n1
] & Imm
)
2942 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2945 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2947 if (i
.types
[n1
] & Imm64
)
2952 /* We should find the immediate. */
2953 if (n1
== i
.operands
)
2955 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2958 if (i
.types
[n
] & Disp32S
)
2961 if (i
.types
[n
] & (Disp16
| Disp64
))
2964 if (i
.types
[n
] & Disp64
)
2969 p
= frag_more (size
);
2970 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2971 i
.op
[n
].disps
, pcrel
,
2972 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2978 /* Output immediate. */
2981 register unsigned int n
;
2983 for (n
= 0; n
< i
.operands
; n
++)
2985 if (i
.types
[n
] & Imm
)
2987 if (i
.op
[n
].imms
->X_op
== O_constant
)
2993 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2996 if (i
.types
[n
] & (Imm8
| Imm8S
))
2998 else if (i
.types
[n
] & Imm64
)
3001 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3004 p
= frag_more (size
);
3005 md_number_to_chars (p
, val
, size
);
3009 /* Not absolute_section.
3010 Need a 32-bit fixup (don't support 8bit
3011 non-absolute imms). Try to support other
3013 #ifdef BFD_ASSEMBLER
3014 enum bfd_reloc_code_real reloc_type
;
3021 if ((i
.types
[n
] & (Imm32S
))
3022 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3024 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3027 if (i
.types
[n
] & (Imm8
| Imm8S
))
3029 if (i
.types
[n
] & Imm64
)
3034 p
= frag_more (size
);
3035 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3036 #ifdef BFD_ASSEMBLER
3037 if (reloc_type
== BFD_RELOC_32
3039 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3040 && (i
.op
[n
].imms
->X_op
== O_symbol
3041 || (i
.op
[n
].imms
->X_op
== O_add
3042 && ((symbol_get_value_expression
3043 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3046 /* We don't support dynamic linking on x86-64 yet. */
3047 if (flag_code
== CODE_64BIT
)
3049 reloc_type
= BFD_RELOC_386_GOTPC
;
3050 i
.op
[n
].imms
->X_add_number
+= 3;
3053 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3054 i
.op
[n
].imms
, 0, reloc_type
);
3061 dwarf2_emit_insn (insn_size
);
3068 #endif /* DEBUG386 */
3072 static int i386_immediate
PARAMS ((char *));
3075 i386_immediate (imm_start
)
3078 char *save_input_line_pointer
;
3082 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3084 as_bad (_("only 1 or 2 immediate operands are allowed"));
3088 exp
= &im_expressions
[i
.imm_operands
++];
3089 i
.op
[this_operand
].imms
= exp
;
3091 if (is_space_char (*imm_start
))
3094 save_input_line_pointer
= input_line_pointer
;
3095 input_line_pointer
= imm_start
;
3099 /* We can have operands of the form
3100 <symbol>@GOTOFF+<nnn>
3101 Take the easy way out here and copy everything
3102 into a temporary buffer... */
3105 cp
= strchr (input_line_pointer
, '@');
3112 /* GOT relocations are not supported in 16 bit mode. */
3113 if (flag_code
== CODE_16BIT
)
3114 as_bad (_("GOT relocations not supported in 16 bit mode"));
3116 if (GOT_symbol
== NULL
)
3117 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3119 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3121 if (flag_code
== CODE_64BIT
)
3122 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3124 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3127 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3129 if (flag_code
== CODE_64BIT
)
3130 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3131 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3134 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3136 if (flag_code
== CODE_64BIT
)
3137 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3139 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3142 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3144 if (flag_code
== CODE_64BIT
)
3145 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3147 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3151 as_bad (_("bad reloc specifier in expression"));
3153 /* Replace the relocation token with ' ', so that errors like
3154 foo@GOTOFF1 will be detected. */
3155 first
= cp
- input_line_pointer
;
3156 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3157 memcpy (tmpbuf
, input_line_pointer
, first
);
3158 tmpbuf
[first
] = ' ';
3159 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3160 input_line_pointer
= tmpbuf
;
3165 exp_seg
= expression (exp
);
3168 if (*input_line_pointer
)
3169 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3171 input_line_pointer
= save_input_line_pointer
;
3173 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3175 /* Missing or bad expr becomes absolute 0. */
3176 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3178 exp
->X_op
= O_constant
;
3179 exp
->X_add_number
= 0;
3180 exp
->X_add_symbol
= (symbolS
*) 0;
3181 exp
->X_op_symbol
= (symbolS
*) 0;
3183 else if (exp
->X_op
== O_constant
)
3185 /* Size it properly later. */
3186 i
.types
[this_operand
] |= Imm64
;
3187 /* If BFD64, sign extend val. */
3188 if (!use_rela_relocations
)
3189 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3190 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3192 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3194 #ifdef BFD_ASSEMBLER
3195 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3197 && exp_seg
!= text_section
3198 && exp_seg
!= data_section
3199 && exp_seg
!= bss_section
3200 && exp_seg
!= undefined_section
3201 #ifdef BFD_ASSEMBLER
3202 && !bfd_is_com_section (exp_seg
)
3206 #ifdef BFD_ASSEMBLER
3207 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3209 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3216 /* This is an address. The size of the address will be
3217 determined later, depending on destination register,
3218 suffix, or the default for the section. */
3219 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3225 static int i386_scale
PARAMS ((char *));
3231 if (!isdigit (*scale
))
3238 i
.log2_scale_factor
= 0;
3241 i
.log2_scale_factor
= 1;
3244 i
.log2_scale_factor
= 2;
3247 i
.log2_scale_factor
= 3;
3251 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3255 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3257 as_warn (_("scale factor of %d without an index register"),
3258 1 << i
.log2_scale_factor
);
3259 #if SCALE1_WHEN_NO_INDEX
3260 i
.log2_scale_factor
= 0;
3266 static int i386_displacement
PARAMS ((char *, char *));
3269 i386_displacement (disp_start
, disp_end
)
3273 register expressionS
*exp
;
3275 char *save_input_line_pointer
;
3276 int bigdisp
= Disp32
;
3278 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3280 if (flag_code
== CODE_64BIT
)
3282 i
.types
[this_operand
] |= bigdisp
;
3284 exp
= &disp_expressions
[i
.disp_operands
];
3285 i
.op
[this_operand
].disps
= exp
;
3287 save_input_line_pointer
= input_line_pointer
;
3288 input_line_pointer
= disp_start
;
3289 END_STRING_AND_SAVE (disp_end
);
3291 #ifndef GCC_ASM_O_HACK
3292 #define GCC_ASM_O_HACK 0
3295 END_STRING_AND_SAVE (disp_end
+ 1);
3296 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3297 && displacement_string_end
[-1] == '+')
3299 /* This hack is to avoid a warning when using the "o"
3300 constraint within gcc asm statements.
3303 #define _set_tssldt_desc(n,addr,limit,type) \
3304 __asm__ __volatile__ ( \
3306 "movw %w1,2+%0\n\t" \
3308 "movb %b1,4+%0\n\t" \
3309 "movb %4,5+%0\n\t" \
3310 "movb $0,6+%0\n\t" \
3311 "movb %h1,7+%0\n\t" \
3313 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3315 This works great except that the output assembler ends
3316 up looking a bit weird if it turns out that there is
3317 no offset. You end up producing code that looks like:
3330 So here we provide the missing zero. */
3332 *displacement_string_end
= '0';
3337 /* We can have operands of the form
3338 <symbol>@GOTOFF+<nnn>
3339 Take the easy way out here and copy everything
3340 into a temporary buffer... */
3343 cp
= strchr (input_line_pointer
, '@');
3350 /* GOT relocations are not supported in 16 bit mode. */
3351 if (flag_code
== CODE_16BIT
)
3352 as_bad (_("GOT relocations not supported in 16 bit mode"));
3354 if (GOT_symbol
== NULL
)
3355 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3357 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3359 if (flag_code
== CODE_64BIT
)
3360 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3362 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3365 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3367 if (flag_code
== CODE_64BIT
)
3368 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3369 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3372 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3374 if (flag_code
== CODE_64BIT
)
3375 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3377 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3380 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3382 if (flag_code
!= CODE_64BIT
)
3383 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3384 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3388 as_bad (_("bad reloc specifier in expression"));
3390 /* Replace the relocation token with ' ', so that errors like
3391 foo@GOTOFF1 will be detected. */
3392 first
= cp
- input_line_pointer
;
3393 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3394 memcpy (tmpbuf
, input_line_pointer
, first
);
3395 tmpbuf
[first
] = ' ';
3396 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3397 input_line_pointer
= tmpbuf
;
3402 exp_seg
= expression (exp
);
3404 #ifdef BFD_ASSEMBLER
3405 /* We do this to make sure that the section symbol is in
3406 the symbol table. We will ultimately change the relocation
3407 to be relative to the beginning of the section. */
3408 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3409 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3411 if (S_IS_LOCAL(exp
->X_add_symbol
)
3412 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3413 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3414 assert (exp
->X_op
== O_symbol
);
3415 exp
->X_op
= O_subtract
;
3416 exp
->X_op_symbol
= GOT_symbol
;
3417 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3422 if (*input_line_pointer
)
3423 as_bad (_("ignoring junk `%s' after expression"),
3424 input_line_pointer
);
3426 RESTORE_END_STRING (disp_end
+ 1);
3428 RESTORE_END_STRING (disp_end
);
3429 input_line_pointer
= save_input_line_pointer
;
3431 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3433 /* Missing or bad expr becomes absolute 0. */
3434 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3436 exp
->X_op
= O_constant
;
3437 exp
->X_add_number
= 0;
3438 exp
->X_add_symbol
= (symbolS
*) 0;
3439 exp
->X_op_symbol
= (symbolS
*) 0;
3442 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3443 if (exp
->X_op
!= O_constant
3444 #ifdef BFD_ASSEMBLER
3445 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3447 && exp_seg
!= text_section
3448 && exp_seg
!= data_section
3449 && exp_seg
!= bss_section
3450 && exp_seg
!= undefined_section
)
3452 #ifdef BFD_ASSEMBLER
3453 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3455 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3460 else if (flag_code
== CODE_64BIT
)
3461 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3465 static int i386_index_check
PARAMS((const char *));
3467 /* Make sure the memory operand we've been dealt is valid.
3468 Return 1 on success, 0 on a failure. */
3471 i386_index_check (operand_string
)
3472 const char *operand_string
;
3475 #if INFER_ADDR_PREFIX
3481 if (flag_code
== CODE_64BIT
)
3485 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3486 && (i
.base_reg
->reg_type
!= BaseIndex
3489 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3490 != (Reg64
|BaseIndex
))))
3495 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3499 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3500 != (Reg16
|BaseIndex
)))
3502 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3503 != (Reg16
|BaseIndex
))
3505 && i
.base_reg
->reg_num
< 6
3506 && i
.index_reg
->reg_num
>= 6
3507 && i
.log2_scale_factor
== 0))))
3514 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3516 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3517 != (Reg32
|BaseIndex
))))
3523 #if INFER_ADDR_PREFIX
3524 if (flag_code
!= CODE_64BIT
3525 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3527 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3529 /* Change the size of any displacement too. At most one of
3530 Disp16 or Disp32 is set.
3531 FIXME. There doesn't seem to be any real need for separate
3532 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3533 Removing them would probably clean up the code quite a lot. */
3534 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3535 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3540 as_bad (_("`%s' is not a valid base/index expression"),
3544 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3546 flag_code_names
[flag_code
]);
3552 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3556 i386_operand (operand_string
)
3557 char *operand_string
;
3561 char *op_string
= operand_string
;
3563 if (is_space_char (*op_string
))
3566 /* We check for an absolute prefix (differentiating,
3567 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3568 if (*op_string
== ABSOLUTE_PREFIX
)
3571 if (is_space_char (*op_string
))
3573 i
.types
[this_operand
] |= JumpAbsolute
;
3576 /* Check if operand is a register. */
3577 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3578 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3580 /* Check for a segment override by searching for ':' after a
3581 segment register. */
3583 if (is_space_char (*op_string
))
3585 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3590 i
.seg
[i
.mem_operands
] = &es
;
3593 i
.seg
[i
.mem_operands
] = &cs
;
3596 i
.seg
[i
.mem_operands
] = &ss
;
3599 i
.seg
[i
.mem_operands
] = &ds
;
3602 i
.seg
[i
.mem_operands
] = &fs
;
3605 i
.seg
[i
.mem_operands
] = &gs
;
3609 /* Skip the ':' and whitespace. */
3611 if (is_space_char (*op_string
))
3614 if (!is_digit_char (*op_string
)
3615 && !is_identifier_char (*op_string
)
3616 && *op_string
!= '('
3617 && *op_string
!= ABSOLUTE_PREFIX
)
3619 as_bad (_("bad memory operand `%s'"), op_string
);
3622 /* Handle case of %es:*foo. */
3623 if (*op_string
== ABSOLUTE_PREFIX
)
3626 if (is_space_char (*op_string
))
3628 i
.types
[this_operand
] |= JumpAbsolute
;
3630 goto do_memory_reference
;
3634 as_bad (_("junk `%s' after register"), op_string
);
3637 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3638 i
.op
[this_operand
].regs
= r
;
3641 else if (*op_string
== REGISTER_PREFIX
)
3643 as_bad (_("bad register name `%s'"), op_string
);
3646 else if (*op_string
== IMMEDIATE_PREFIX
)
3649 if (i
.types
[this_operand
] & JumpAbsolute
)
3651 as_bad (_("immediate operand illegal with absolute jump"));
3654 if (!i386_immediate (op_string
))
3657 else if (is_digit_char (*op_string
)
3658 || is_identifier_char (*op_string
)
3659 || *op_string
== '(' )
3661 /* This is a memory reference of some sort. */
3664 /* Start and end of displacement string expression (if found). */
3665 char *displacement_string_start
;
3666 char *displacement_string_end
;
3668 do_memory_reference
:
3669 if ((i
.mem_operands
== 1
3670 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3671 || i
.mem_operands
== 2)
3673 as_bad (_("too many memory references for `%s'"),
3674 current_templates
->start
->name
);
3678 /* Check for base index form. We detect the base index form by
3679 looking for an ')' at the end of the operand, searching
3680 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3682 base_string
= op_string
+ strlen (op_string
);
3685 if (is_space_char (*base_string
))
3688 /* If we only have a displacement, set-up for it to be parsed later. */
3689 displacement_string_start
= op_string
;
3690 displacement_string_end
= base_string
+ 1;
3692 if (*base_string
== ')')
3695 unsigned int parens_balanced
= 1;
3696 /* We've already checked that the number of left & right ()'s are
3697 equal, so this loop will not be infinite. */
3701 if (*base_string
== ')')
3703 if (*base_string
== '(')
3706 while (parens_balanced
);
3708 temp_string
= base_string
;
3710 /* Skip past '(' and whitespace. */
3712 if (is_space_char (*base_string
))
3715 if (*base_string
== ','
3716 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3717 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3719 displacement_string_end
= temp_string
;
3721 i
.types
[this_operand
] |= BaseIndex
;
3725 base_string
= end_op
;
3726 if (is_space_char (*base_string
))
3730 /* There may be an index reg or scale factor here. */
3731 if (*base_string
== ',')
3734 if (is_space_char (*base_string
))
3737 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3738 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3740 base_string
= end_op
;
3741 if (is_space_char (*base_string
))
3743 if (*base_string
== ',')
3746 if (is_space_char (*base_string
))
3749 else if (*base_string
!= ')' )
3751 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3756 else if (*base_string
== REGISTER_PREFIX
)
3758 as_bad (_("bad register name `%s'"), base_string
);
3762 /* Check for scale factor. */
3763 if (isdigit ((unsigned char) *base_string
))
3765 if (!i386_scale (base_string
))
3769 if (is_space_char (*base_string
))
3771 if (*base_string
!= ')')
3773 as_bad (_("expecting `)' after scale factor in `%s'"),
3778 else if (!i
.index_reg
)
3780 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3785 else if (*base_string
!= ')')
3787 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3792 else if (*base_string
== REGISTER_PREFIX
)
3794 as_bad (_("bad register name `%s'"), base_string
);
3799 /* If there's an expression beginning the operand, parse it,
3800 assuming displacement_string_start and
3801 displacement_string_end are meaningful. */
3802 if (displacement_string_start
!= displacement_string_end
)
3804 if (!i386_displacement (displacement_string_start
,
3805 displacement_string_end
))
3809 /* Special case for (%dx) while doing input/output op. */
3811 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3813 && i
.log2_scale_factor
== 0
3814 && i
.seg
[i
.mem_operands
] == 0
3815 && (i
.types
[this_operand
] & Disp
) == 0)
3817 i
.types
[this_operand
] = InOutPortReg
;
3821 if (i386_index_check (operand_string
) == 0)
3827 /* It's not a memory operand; argh! */
3828 as_bad (_("invalid char %s beginning operand %d `%s'"),
3829 output_invalid (*op_string
),
3834 return 1; /* Normal return. */
3837 /* md_estimate_size_before_relax()
3839 Called just before relax() for rs_machine_dependent frags. The x86
3840 assembler uses these frags to handle variable size jump
3843 Any symbol that is now undefined will not become defined.
3844 Return the correct fr_subtype in the frag.
3845 Return the initial "guess for variable size of frag" to caller.
3846 The guess is actually the growth beyond the fixed part. Whatever
3847 we do to grow the fixed or variable part contributes to our
3851 md_estimate_size_before_relax (fragP
, segment
)
3852 register fragS
*fragP
;
3853 register segT segment
;
3855 /* We've already got fragP->fr_subtype right; all we have to do is
3856 check for un-relaxable symbols. On an ELF system, we can't relax
3857 an externally visible symbol, because it may be overridden by a
3859 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3861 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3862 || S_IS_WEAK (fragP
->fr_symbol
)
3866 /* Symbol is undefined in this segment, or we need to keep a
3867 reloc so that weak symbols can be overridden. */
3868 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3869 #ifdef BFD_ASSEMBLER
3870 enum bfd_reloc_code_real reloc_type
;
3874 unsigned char *opcode
;
3877 if (fragP
->fr_var
!= NO_RELOC
)
3878 reloc_type
= fragP
->fr_var
;
3880 reloc_type
= BFD_RELOC_16_PCREL
;
3882 reloc_type
= BFD_RELOC_32_PCREL
;
3884 old_fr_fix
= fragP
->fr_fix
;
3885 opcode
= (unsigned char *) fragP
->fr_opcode
;
3889 case JUMP_PC_RELATIVE
:
3890 /* Make jmp (0xeb) a dword displacement jump. */
3892 fragP
->fr_fix
+= size
;
3893 fix_new (fragP
, old_fr_fix
, size
,
3895 fragP
->fr_offset
, 1,
3900 /* This changes the byte-displacement jump 0x7N
3901 to the dword-displacement jump 0x0f,0x8N. */
3902 opcode
[1] = opcode
[0] + 0x10;
3903 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3904 /* We've added an opcode byte. */
3905 fragP
->fr_fix
+= 1 + size
;
3906 fix_new (fragP
, old_fr_fix
+ 1, size
,
3908 fragP
->fr_offset
, 1,
3913 return fragP
->fr_fix
- old_fr_fix
;
3915 /* Guess a short jump. */
3919 /* Called after relax() is finished.
3921 In: Address of frag.
3922 fr_type == rs_machine_dependent.
3923 fr_subtype is what the address relaxed to.
3925 Out: Any fixSs and constants are set up.
3926 Caller will turn frag into a ".space 0". */
3928 #ifndef BFD_ASSEMBLER
3930 md_convert_frag (headers
, sec
, fragP
)
3931 object_headers
*headers ATTRIBUTE_UNUSED
;
3932 segT sec ATTRIBUTE_UNUSED
;
3933 register fragS
*fragP
;
3936 md_convert_frag (abfd
, sec
, fragP
)
3937 bfd
*abfd ATTRIBUTE_UNUSED
;
3938 segT sec ATTRIBUTE_UNUSED
;
3939 register fragS
*fragP
;
3942 register unsigned char *opcode
;
3943 unsigned char *where_to_put_displacement
= NULL
;
3944 offsetT target_address
;
3945 offsetT opcode_address
;
3946 unsigned int extension
= 0;
3947 offsetT displacement_from_opcode_start
;
3949 opcode
= (unsigned char *) fragP
->fr_opcode
;
3951 /* Address we want to reach in file space. */
3952 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3953 #ifdef BFD_ASSEMBLER
3954 /* Not needed otherwise? */
3955 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3958 /* Address opcode resides at in file space. */
3959 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3961 /* Displacement from opcode start to fill into instruction. */
3962 displacement_from_opcode_start
= target_address
- opcode_address
;
3964 switch (fragP
->fr_subtype
)
3966 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3967 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3968 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3969 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3970 /* Don't have to change opcode. */
3971 extension
= 1; /* 1 opcode + 1 displacement */
3972 where_to_put_displacement
= &opcode
[1];
3975 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3976 extension
= 5; /* 2 opcode + 4 displacement */
3977 opcode
[1] = opcode
[0] + 0x10;
3978 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3979 where_to_put_displacement
= &opcode
[2];
3982 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3983 extension
= 4; /* 1 opcode + 4 displacement */
3985 where_to_put_displacement
= &opcode
[1];
3988 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3989 extension
= 3; /* 2 opcode + 2 displacement */
3990 opcode
[1] = opcode
[0] + 0x10;
3991 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3992 where_to_put_displacement
= &opcode
[2];
3995 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3996 extension
= 2; /* 1 opcode + 2 displacement */
3998 where_to_put_displacement
= &opcode
[1];
4002 BAD_CASE (fragP
->fr_subtype
);
4005 /* Now put displacement after opcode. */
4006 md_number_to_chars ((char *) where_to_put_displacement
,
4007 (valueT
) (displacement_from_opcode_start
- extension
),
4008 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4009 fragP
->fr_fix
+= extension
;
4012 /* Size of byte displacement jmp. */
4013 int md_short_jump_size
= 2;
4015 /* Size of dword displacement jmp. */
4016 int md_long_jump_size
= 5;
4018 /* Size of relocation record. */
4019 const int md_reloc_size
= 8;
4022 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4024 addressT from_addr
, to_addr
;
4025 fragS
*frag ATTRIBUTE_UNUSED
;
4026 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4030 offset
= to_addr
- (from_addr
+ 2);
4031 /* Opcode for byte-disp jump. */
4032 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4033 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4037 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4039 addressT from_addr
, to_addr
;
4040 fragS
*frag ATTRIBUTE_UNUSED
;
4041 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4045 offset
= to_addr
- (from_addr
+ 5);
4046 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4047 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4050 /* Apply a fixup (fixS) to segment data, once it has been determined
4051 by our caller that we have all the info we need to fix it up.
4053 On the 386, immediates, displacements, and data pointers are all in
4054 the same (little-endian) format, so we don't need to care about which
4058 md_apply_fix3 (fixP
, valp
, seg
)
4059 /* The fix we're to put in. */
4062 /* Pointer to the value of the bits. */
4065 /* Segment fix is from. */
4066 segT seg ATTRIBUTE_UNUSED
;
4068 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4069 valueT value
= *valp
;
4071 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4074 switch (fixP
->fx_r_type
)
4080 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4083 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4086 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4091 /* This is a hack. There should be a better way to handle this.
4092 This covers for the fact that bfd_install_relocation will
4093 subtract the current location (for partial_inplace, PC relative
4094 relocations); see more below. */
4095 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4096 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4097 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4101 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4103 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4106 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4108 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4109 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4111 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4114 || (symbol_section_p (fixP
->fx_addsy
)
4115 && fseg
!= absolute_section
))
4116 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4117 && ! S_IS_WEAK (fixP
->fx_addsy
)
4118 && S_IS_DEFINED (fixP
->fx_addsy
)
4119 && ! S_IS_COMMON (fixP
->fx_addsy
))
4121 /* Yes, we add the values in twice. This is because
4122 bfd_perform_relocation subtracts them out again. I think
4123 bfd_perform_relocation is broken, but I don't dare change
4125 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4129 #if defined (OBJ_COFF) && defined (TE_PE)
4130 /* For some reason, the PE format does not store a section
4131 address offset for a PC relative symbol. */
4132 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4133 value
+= md_pcrel_from (fixP
);
4137 /* Fix a few things - the dynamic linker expects certain values here,
4138 and we must not dissappoint it. */
4139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4140 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4142 switch (fixP
->fx_r_type
)
4144 case BFD_RELOC_386_PLT32
:
4145 case BFD_RELOC_X86_64_PLT32
:
4146 /* Make the jump instruction point to the address of the operand. At
4147 runtime we merely add the offset to the actual PLT entry. */
4150 case BFD_RELOC_386_GOTPC
:
4152 /* This is tough to explain. We end up with this one if we have
4153 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4154 * here is to obtain the absolute address of the GOT, and it is strongly
4155 * preferable from a performance point of view to avoid using a runtime
4156 * relocation for this. The actual sequence of instructions often look
4162 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4164 * The call and pop essentially return the absolute address of
4165 * the label .L66 and store it in %ebx. The linker itself will
4166 * ultimately change the first operand of the addl so that %ebx points to
4167 * the GOT, but to keep things simple, the .o file must have this operand
4168 * set so that it generates not the absolute address of .L66, but the
4169 * absolute address of itself. This allows the linker itself simply
4170 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4171 * added in, and the addend of the relocation is stored in the operand
4172 * field for the instruction itself.
4174 * Our job here is to fix the operand so that it would add the correct
4175 * offset so that %ebx would point to itself. The thing that is tricky is
4176 * that .-.L66 will point to the beginning of the instruction, so we need
4177 * to further modify the operand so that it will point to itself.
4178 * There are other cases where you have something like:
4180 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4182 * and here no correction would be required. Internally in the assembler
4183 * we treat operands of this form as not being pcrel since the '.' is
4184 * explicitly mentioned, and I wonder whether it would simplify matters
4185 * to do it this way. Who knows. In earlier versions of the PIC patches,
4186 * the pcrel_adjust field was used to store the correction, but since the
4187 * expression is not pcrel, I felt it would be confusing to do it this
4192 case BFD_RELOC_386_GOT32
:
4193 case BFD_RELOC_X86_64_GOT32
:
4194 value
= 0; /* Fully resolved at runtime. No addend. */
4196 case BFD_RELOC_386_GOTOFF
:
4197 case BFD_RELOC_X86_64_GOTPCREL
:
4200 case BFD_RELOC_VTABLE_INHERIT
:
4201 case BFD_RELOC_VTABLE_ENTRY
:
4208 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4210 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4212 #ifndef BFD_ASSEMBLER
4213 md_number_to_chars (p
, value
, fixP
->fx_size
);
4215 /* Are we finished with this relocation now? */
4216 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4218 else if (use_rela_relocations
)
4220 fixP
->fx_no_overflow
= 1;
4223 md_number_to_chars (p
, value
, fixP
->fx_size
);
4229 #define MAX_LITTLENUMS 6
4231 /* Turn the string pointed to by litP into a floating point constant
4232 of type TYPE, and emit the appropriate bytes. The number of
4233 LITTLENUMS emitted is stored in *SIZEP. An error message is
4234 returned, or NULL on OK. */
4237 md_atof (type
, litP
, sizeP
)
4243 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4244 LITTLENUM_TYPE
*wordP
;
4266 return _("Bad call to md_atof ()");
4268 t
= atof_ieee (input_line_pointer
, type
, words
);
4270 input_line_pointer
= t
;
4272 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4273 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4274 the bigendian 386. */
4275 for (wordP
= words
+ prec
- 1; prec
--;)
4277 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4278 litP
+= sizeof (LITTLENUM_TYPE
);
4283 char output_invalid_buf
[8];
4290 sprintf (output_invalid_buf
, "'%c'", c
);
4292 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4293 return output_invalid_buf
;
4296 /* REG_STRING starts *before* REGISTER_PREFIX. */
4298 static const reg_entry
*
4299 parse_register (reg_string
, end_op
)
4303 char *s
= reg_string
;
4305 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4308 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4309 if (*s
== REGISTER_PREFIX
)
4312 if (is_space_char (*s
))
4316 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4318 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4319 return (const reg_entry
*) NULL
;
4323 /* For naked regs, make sure that we are not dealing with an identifier.
4324 This prevents confusing an identifier like `eax_var' with register
4326 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4327 return (const reg_entry
*) NULL
;
4331 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4333 /* Handle floating point regs, allowing spaces in the (i) part. */
4334 if (r
== i386_regtab
/* %st is first entry of table */)
4336 if (is_space_char (*s
))
4341 if (is_space_char (*s
))
4343 if (*s
>= '0' && *s
<= '7')
4345 r
= &i386_float_regtab
[*s
- '0'];
4347 if (is_space_char (*s
))
4355 /* We have "%st(" then garbage. */
4356 return (const reg_entry
*) NULL
;
4363 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4364 const char *md_shortopts
= "kVQ:sq";
4366 const char *md_shortopts
= "q";
4368 struct option md_longopts
[] = {
4369 #define OPTION_32 (OPTION_MD_BASE + 0)
4370 {"32", no_argument
, NULL
, OPTION_32
},
4371 #define OPTION_64 (OPTION_MD_BASE + 1)
4372 {"64", no_argument
, NULL
, OPTION_64
},
4373 {NULL
, no_argument
, NULL
, 0}
4375 size_t md_longopts_size
= sizeof (md_longopts
);
4378 md_parse_option (c
, arg
)
4380 char *arg ATTRIBUTE_UNUSED
;
4388 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4389 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4390 should be emitted or not. FIXME: Not implemented. */
4394 /* -V: SVR4 argument to print version ID. */
4396 print_version_id ();
4399 /* -k: Ignore for FreeBSD compatibility. */
4404 /* -s: On i386 Solaris, this tells the native assembler to use
4405 .stab instead of .stab.excl. We always use .stab anyhow. */
4412 const char **list
, **l
;
4414 default_arch
= c
== OPTION_32
? "i386" : "x86_64";
4415 list
= bfd_target_list ();
4416 for (l
= list
; *l
!= NULL
; l
++)
4420 if (strcmp (*l
, "elf32-i386") == 0)
4425 if (strcmp (*l
, "elf64-x86-64") == 0)
4430 as_fatal (_("No compiled in support for %d bit object file format"),
4431 c
== OPTION_32
? 32 : 64);
4444 md_show_usage (stream
)
4447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4448 fprintf (stream
, _("\
4450 -V print assembler version number\n\
4452 -q quieten some warnings\n\
4455 fprintf (stream
, _("\
4456 -q quieten some warnings\n"));
4460 #ifdef BFD_ASSEMBLER
4461 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4462 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4464 /* Pick the target format to use. */
4467 i386_target_format ()
4469 if (!strcmp (default_arch
, "x86_64"))
4470 set_code_flag (CODE_64BIT
);
4471 else if (!strcmp (default_arch
, "i386"))
4472 set_code_flag (CODE_32BIT
);
4474 as_fatal (_("Unknown architecture"));
4475 switch (OUTPUT_FLAVOR
)
4477 #ifdef OBJ_MAYBE_AOUT
4478 case bfd_target_aout_flavour
:
4479 return AOUT_TARGET_FORMAT
;
4481 #ifdef OBJ_MAYBE_COFF
4482 case bfd_target_coff_flavour
:
4485 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4486 case bfd_target_elf_flavour
:
4488 if (flag_code
== CODE_64BIT
)
4489 use_rela_relocations
= 1;
4490 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4499 #endif /* OBJ_MAYBE_ more than one */
4500 #endif /* BFD_ASSEMBLER */
4503 md_undefined_symbol (name
)
4506 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4507 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4508 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4509 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4513 if (symbol_find (name
))
4514 as_bad (_("GOT already in symbol table"));
4515 GOT_symbol
= symbol_new (name
, undefined_section
,
4516 (valueT
) 0, &zero_address_frag
);
4523 /* Round up a section size to the appropriate boundary. */
4526 md_section_align (segment
, size
)
4527 segT segment ATTRIBUTE_UNUSED
;
4530 #ifdef BFD_ASSEMBLER
4531 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4532 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4534 /* For a.out, force the section size to be aligned. If we don't do
4535 this, BFD will align it for us, but it will not write out the
4536 final bytes of the section. This may be a bug in BFD, but it is
4537 easier to fix it here since that is how the other a.out targets
4541 align
= bfd_get_section_alignment (stdoutput
, segment
);
4542 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4550 /* On the i386, PC-relative offsets are relative to the start of the
4551 next instruction. That is, the address of the offset, plus its
4552 size, since the offset is always the last part of the insn. */
4555 md_pcrel_from (fixP
)
4558 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4565 int ignore ATTRIBUTE_UNUSED
;
4569 temp
= get_absolute_expression ();
4570 subseg_set (bss_section
, (subsegT
) temp
);
4571 demand_empty_rest_of_line ();
4576 #ifdef BFD_ASSEMBLER
4579 i386_validate_fix (fixp
)
4582 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4584 /* GOTOFF relocation are nonsense in 64bit mode. */
4585 if (flag_code
== CODE_64BIT
)
4587 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4593 tc_gen_reloc (section
, fixp
)
4594 asection
*section ATTRIBUTE_UNUSED
;
4598 bfd_reloc_code_real_type code
;
4600 switch (fixp
->fx_r_type
)
4602 case BFD_RELOC_X86_64_PLT32
:
4603 case BFD_RELOC_X86_64_GOT32
:
4604 case BFD_RELOC_X86_64_GOTPCREL
:
4605 case BFD_RELOC_386_PLT32
:
4606 case BFD_RELOC_386_GOT32
:
4607 case BFD_RELOC_386_GOTOFF
:
4608 case BFD_RELOC_386_GOTPC
:
4609 case BFD_RELOC_X86_64_32S
:
4611 case BFD_RELOC_VTABLE_ENTRY
:
4612 case BFD_RELOC_VTABLE_INHERIT
:
4613 code
= fixp
->fx_r_type
;
4618 switch (fixp
->fx_size
)
4621 as_bad (_("can not do %d byte pc-relative relocation"),
4623 code
= BFD_RELOC_32_PCREL
;
4625 case 1: code
= BFD_RELOC_8_PCREL
; break;
4626 case 2: code
= BFD_RELOC_16_PCREL
; break;
4627 case 4: code
= BFD_RELOC_32_PCREL
; break;
4632 switch (fixp
->fx_size
)
4635 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4636 code
= BFD_RELOC_32
;
4638 case 1: code
= BFD_RELOC_8
; break;
4639 case 2: code
= BFD_RELOC_16
; break;
4640 case 4: code
= BFD_RELOC_32
; break;
4641 case 8: code
= BFD_RELOC_64
; break;
4647 if (code
== BFD_RELOC_32
4649 && fixp
->fx_addsy
== GOT_symbol
)
4651 /* We don't support GOTPC on 64bit targets. */
4652 if (flag_code
== CODE_64BIT
)
4654 code
= BFD_RELOC_386_GOTPC
;
4657 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4658 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4659 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4661 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4662 if (!use_rela_relocations
)
4664 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4665 vtable entry to be used in the relocation's section offset. */
4666 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4667 rel
->address
= fixp
->fx_offset
;
4670 rel
->addend
= fixp
->fx_addnumber
;
4674 /* Use the rela in 64bit mode. */
4677 rel
->addend
= fixp
->fx_offset
;
4679 /* Ohhh, this is ugly. The problem is that if this is a local global
4680 symbol, the relocation will entirely be performed at link time, not
4681 at assembly time. bfd_perform_reloc doesn't know about this sort
4682 of thing, and as a result we need to fake it out here. */
4683 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4684 && !S_IS_COMMON(fixp
->fx_addsy
))
4685 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4688 rel
->addend
-= fixp
->fx_size
;
4692 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4693 if (rel
->howto
== NULL
)
4695 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4696 _("cannot represent relocation type %s"),
4697 bfd_get_reloc_code_name (code
));
4698 /* Set howto to a garbage value so that we can keep going. */
4699 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4700 assert (rel
->howto
!= NULL
);
4706 #else /* ! BFD_ASSEMBLER */
4708 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4710 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4713 relax_addressT segment_address_in_file
;
4715 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4716 Out: GNU LD relocation length code: 0, 1, or 2. */
4718 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4721 know (fixP
->fx_addsy
!= NULL
);
4723 md_number_to_chars (where
,
4724 (valueT
) (fixP
->fx_frag
->fr_address
4725 + fixP
->fx_where
- segment_address_in_file
),
4728 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4729 ? S_GET_TYPE (fixP
->fx_addsy
)
4730 : fixP
->fx_addsy
->sy_number
);
4732 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4733 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4734 where
[4] = r_symbolnum
& 0x0ff;
4735 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4736 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4737 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4740 #endif /* OBJ_AOUT or OBJ_BOUT. */
4742 #if defined (I386COFF)
4745 tc_coff_fix2rtype (fixP
)
4748 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4751 return (fixP
->fx_pcrel
?
4752 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4753 fixP
->fx_size
== 2 ? R_PCRWORD
:
4755 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4756 fixP
->fx_size
== 2 ? R_RELWORD
:
4761 tc_coff_sizemachdep (frag
)
4765 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4770 #endif /* I386COFF */
4772 #endif /* ! BFD_ASSEMBLER */
4774 /* Parse operands using Intel syntax. This implements a recursive descent
4775 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4778 FIXME: We do not recognize the full operand grammar defined in the MASM
4779 documentation. In particular, all the structure/union and
4780 high-level macro operands are missing.
4782 Uppercase words are terminals, lower case words are non-terminals.
4783 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4784 bars '|' denote choices. Most grammar productions are implemented in
4785 functions called 'intel_<production>'.
4787 Initial production is 'expr'.
4793 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4795 constant digits [[ radixOverride ]]
4797 dataType BYTE | WORD | DWORD | QWORD | XWORD
4830 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4831 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4833 hexdigit a | b | c | d | e | f
4834 | A | B | C | D | E | F
4844 register specialRegister
4848 segmentRegister CS | DS | ES | FS | GS | SS
4850 specialRegister CR0 | CR2 | CR3
4851 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4852 | TR3 | TR4 | TR5 | TR6 | TR7
4854 We simplify the grammar in obvious places (e.g., register parsing is
4855 done by calling parse_register) and eliminate immediate left recursion
4856 to implement a recursive-descent parser.
4896 /* Parsing structure for the intel syntax parser. Used to implement the
4897 semantic actions for the operand grammar. */
4898 struct intel_parser_s
4900 char *op_string
; /* The string being parsed. */
4901 int got_a_float
; /* Whether the operand is a float. */
4902 int op_modifier
; /* Operand modifier. */
4903 int is_mem
; /* 1 if operand is memory reference. */
4904 const reg_entry
*reg
; /* Last register reference found. */
4905 char *disp
; /* Displacement string being built. */
4908 static struct intel_parser_s intel_parser
;
4910 /* Token structure for parsing intel syntax. */
4913 int code
; /* Token code. */
4914 const reg_entry
*reg
; /* Register entry for register tokens. */
4915 char *str
; /* String representation. */
4918 static struct intel_token cur_token
, prev_token
;
4921 /* Token codes for the intel parser. Since T_SHORT is already used
4922 by COFF, undefine it first to prevent a warning. */
4937 /* Prototypes for intel parser functions. */
4938 static int intel_match_token
PARAMS ((int code
));
4939 static void intel_get_token
PARAMS ((void));
4940 static void intel_putback_token
PARAMS ((void));
4941 static int intel_expr
PARAMS ((void));
4942 static int intel_e05
PARAMS ((void));
4943 static int intel_e05_1
PARAMS ((void));
4944 static int intel_e06
PARAMS ((void));
4945 static int intel_e06_1
PARAMS ((void));
4946 static int intel_e09
PARAMS ((void));
4947 static int intel_e09_1
PARAMS ((void));
4948 static int intel_e10
PARAMS ((void));
4949 static int intel_e10_1
PARAMS ((void));
4950 static int intel_e11
PARAMS ((void));
4953 i386_intel_operand (operand_string
, got_a_float
)
4954 char *operand_string
;
4960 /* Initialize token holders. */
4961 cur_token
.code
= prev_token
.code
= T_NIL
;
4962 cur_token
.reg
= prev_token
.reg
= NULL
;
4963 cur_token
.str
= prev_token
.str
= NULL
;
4965 /* Initialize parser structure. */
4966 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4969 strcpy (intel_parser
.op_string
, operand_string
);
4970 intel_parser
.got_a_float
= got_a_float
;
4971 intel_parser
.op_modifier
= -1;
4972 intel_parser
.is_mem
= 0;
4973 intel_parser
.reg
= NULL
;
4974 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4975 if (intel_parser
.disp
== NULL
)
4977 intel_parser
.disp
[0] = '\0';
4979 /* Read the first token and start the parser. */
4981 ret
= intel_expr ();
4985 /* If we found a memory reference, hand it over to i386_displacement
4986 to fill in the rest of the operand fields. */
4987 if (intel_parser
.is_mem
)
4989 if ((i
.mem_operands
== 1
4990 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4991 || i
.mem_operands
== 2)
4993 as_bad (_("too many memory references for '%s'"),
4994 current_templates
->start
->name
);
4999 char *s
= intel_parser
.disp
;
5002 /* Add the displacement expression. */
5004 ret
= i386_displacement (s
, s
+ strlen (s
))
5005 && i386_index_check (s
);
5009 /* Constant and OFFSET expressions are handled by i386_immediate. */
5010 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5011 || intel_parser
.reg
== NULL
)
5012 ret
= i386_immediate (intel_parser
.disp
);
5016 free (intel_parser
.disp
);
5026 /* expr SHORT e05 */
5027 if (cur_token
.code
== T_SHORT
)
5029 intel_parser
.op_modifier
= SHORT
;
5030 intel_match_token (T_SHORT
);
5032 return (intel_e05 ());
5037 return intel_e05 ();
5047 return (intel_e06 () && intel_e05_1 ());
5053 /* e05' addOp e06 e05' */
5054 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5056 strcat (intel_parser
.disp
, cur_token
.str
);
5057 intel_match_token (cur_token
.code
);
5059 return (intel_e06 () && intel_e05_1 ());
5074 return (intel_e09 () && intel_e06_1 ());
5080 /* e06' mulOp e09 e06' */
5081 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5083 strcat (intel_parser
.disp
, cur_token
.str
);
5084 intel_match_token (cur_token
.code
);
5086 return (intel_e09 () && intel_e06_1 ());
5094 /* e09 OFFSET e10 e09'
5103 /* e09 OFFSET e10 e09' */
5104 if (cur_token
.code
== T_OFFSET
)
5106 intel_parser
.is_mem
= 0;
5107 intel_parser
.op_modifier
= OFFSET_FLAT
;
5108 intel_match_token (T_OFFSET
);
5110 return (intel_e10 () && intel_e09_1 ());
5115 return (intel_e10 () && intel_e09_1 ());
5121 /* e09' PTR e10 e09' */
5122 if (cur_token
.code
== T_PTR
)
5124 if (prev_token
.code
== T_BYTE
)
5125 i
.suffix
= BYTE_MNEM_SUFFIX
;
5127 else if (prev_token
.code
== T_WORD
)
5129 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5130 i
.suffix
= SHORT_MNEM_SUFFIX
;
5132 i
.suffix
= WORD_MNEM_SUFFIX
;
5135 else if (prev_token
.code
== T_DWORD
)
5137 if (intel_parser
.got_a_float
== 1) /* "f..." */
5138 i
.suffix
= SHORT_MNEM_SUFFIX
;
5140 i
.suffix
= LONG_MNEM_SUFFIX
;
5143 else if (prev_token
.code
== T_QWORD
)
5145 if (intel_parser
.got_a_float
== 1) /* "f..." */
5146 i
.suffix
= LONG_MNEM_SUFFIX
;
5148 i
.suffix
= QWORD_MNEM_SUFFIX
;
5151 else if (prev_token
.code
== T_XWORD
)
5152 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5156 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5160 intel_match_token (T_PTR
);
5162 return (intel_e10 () && intel_e09_1 ());
5165 /* e09 : e10 e09' */
5166 else if (cur_token
.code
== ':')
5168 /* Mark as a memory operand only if it's not already known to be an
5169 offset expression. */
5170 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5171 intel_parser
.is_mem
= 1;
5173 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5188 return (intel_e11 () && intel_e10_1 ());
5194 /* e10' [ expr ] e10' */
5195 if (cur_token
.code
== '[')
5197 intel_match_token ('[');
5199 /* Mark as a memory operand only if it's not already known to be an
5200 offset expression. If it's an offset expression, we need to keep
5202 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5203 intel_parser
.is_mem
= 1;
5205 strcat (intel_parser
.disp
, "[");
5207 /* Add a '+' to the displacement string if necessary. */
5208 if (*intel_parser
.disp
!= '\0'
5209 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5210 strcat (intel_parser
.disp
, "+");
5212 if (intel_expr () && intel_match_token (']'))
5214 /* Preserve brackets when the operand is an offset expression. */
5215 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5216 strcat (intel_parser
.disp
, "]");
5218 return intel_e10_1 ();
5245 if (cur_token
.code
== '(')
5247 intel_match_token ('(');
5248 strcat (intel_parser
.disp
, "(");
5250 if (intel_expr () && intel_match_token (')'))
5252 strcat (intel_parser
.disp
, ")");
5260 else if (cur_token
.code
== '[')
5262 intel_match_token ('[');
5264 /* Mark as a memory operand only if it's not already known to be an
5265 offset expression. If it's an offset expression, we need to keep
5267 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5268 intel_parser
.is_mem
= 1;
5270 strcat (intel_parser
.disp
, "[");
5272 /* Operands for jump/call inside brackets denote absolute addresses. */
5273 if (current_templates
->start
->opcode_modifier
& Jump
5274 || current_templates
->start
->opcode_modifier
& JumpDword
5275 || current_templates
->start
->opcode_modifier
& JumpByte
5276 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5277 i
.types
[this_operand
] |= JumpAbsolute
;
5279 /* Add a '+' to the displacement string if necessary. */
5280 if (*intel_parser
.disp
!= '\0'
5281 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5282 strcat (intel_parser
.disp
, "+");
5284 if (intel_expr () && intel_match_token (']'))
5286 /* Preserve brackets when the operand is an offset expression. */
5287 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5288 strcat (intel_parser
.disp
, "]");
5301 else if (cur_token
.code
== T_BYTE
5302 || cur_token
.code
== T_WORD
5303 || cur_token
.code
== T_DWORD
5304 || cur_token
.code
== T_QWORD
5305 || cur_token
.code
== T_XWORD
)
5307 intel_match_token (cur_token
.code
);
5314 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5316 strcat (intel_parser
.disp
, cur_token
.str
);
5317 intel_match_token (cur_token
.code
);
5319 /* Mark as a memory operand only if it's not already known to be an
5320 offset expression. */
5321 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5322 intel_parser
.is_mem
= 1;
5328 else if (cur_token
.code
== T_REG
)
5330 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5332 intel_match_token (T_REG
);
5334 /* Check for segment change. */
5335 if (cur_token
.code
== ':')
5337 if (reg
->reg_type
& (SReg2
| SReg3
))
5339 switch (reg
->reg_num
)
5342 i
.seg
[i
.mem_operands
] = &es
;
5345 i
.seg
[i
.mem_operands
] = &cs
;
5348 i
.seg
[i
.mem_operands
] = &ss
;
5351 i
.seg
[i
.mem_operands
] = &ds
;
5354 i
.seg
[i
.mem_operands
] = &fs
;
5357 i
.seg
[i
.mem_operands
] = &gs
;
5363 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5368 /* Not a segment register. Check for register scaling. */
5369 else if (cur_token
.code
== '*')
5371 if (!intel_parser
.is_mem
)
5373 as_bad (_("Register scaling only allowed in memory operands."));
5377 /* What follows must be a valid scale. */
5378 if (intel_match_token ('*')
5379 && strchr ("01248", *cur_token
.str
))
5382 i
.types
[this_operand
] |= BaseIndex
;
5384 /* Set the scale after setting the register (otherwise,
5385 i386_scale will complain) */
5386 i386_scale (cur_token
.str
);
5387 intel_match_token (T_CONST
);
5391 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5397 /* No scaling. If this is a memory operand, the register is either a
5398 base register (first occurrence) or an index register (second
5400 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5402 if (i
.base_reg
&& i
.index_reg
)
5404 as_bad (_("Too many register references in memory operand.\n"));
5408 if (i
.base_reg
== NULL
)
5413 i
.types
[this_operand
] |= BaseIndex
;
5416 /* Offset modifier. Add the register to the displacement string to be
5417 parsed as an immediate expression after we're done. */
5418 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5419 strcat (intel_parser
.disp
, reg
->reg_name
);
5421 /* It's neither base nor index nor offset. */
5424 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5425 i
.op
[this_operand
].regs
= reg
;
5429 /* Since registers are not part of the displacement string (except
5430 when we're parsing offset operands), we may need to remove any
5431 preceding '+' from the displacement string. */
5432 if (*intel_parser
.disp
!= '\0'
5433 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5435 char *s
= intel_parser
.disp
;
5436 s
+= strlen (s
) - 1;
5445 else if (cur_token
.code
== T_ID
)
5447 /* Add the identifier to the displacement string. */
5448 strcat (intel_parser
.disp
, cur_token
.str
);
5449 intel_match_token (T_ID
);
5451 /* The identifier represents a memory reference only if it's not
5452 preceded by an offset modifier. */
5453 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5454 intel_parser
.is_mem
= 1;
5460 else if (cur_token
.code
== T_CONST
5461 || cur_token
.code
== '-'
5462 || cur_token
.code
== '+')
5466 /* Allow constants that start with `+' or `-'. */
5467 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5469 strcat (intel_parser
.disp
, cur_token
.str
);
5470 intel_match_token (cur_token
.code
);
5471 if (cur_token
.code
!= T_CONST
)
5473 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5479 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5480 if (save_str
== NULL
)
5482 strcpy (save_str
, cur_token
.str
);
5484 /* Get the next token to check for register scaling. */
5485 intel_match_token (cur_token
.code
);
5487 /* Check if this constant is a scaling factor for an index register. */
5488 if (cur_token
.code
== '*')
5490 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5492 if (!intel_parser
.is_mem
)
5494 as_bad (_("Register scaling only allowed in memory operands."));
5498 /* The constant is followed by `* reg', so it must be
5500 if (strchr ("01248", *save_str
))
5502 i
.index_reg
= cur_token
.reg
;
5503 i
.types
[this_operand
] |= BaseIndex
;
5505 /* Set the scale after setting the register (otherwise,
5506 i386_scale will complain) */
5507 i386_scale (save_str
);
5508 intel_match_token (T_REG
);
5510 /* Since registers are not part of the displacement
5511 string, we may need to remove any preceding '+' from
5512 the displacement string. */
5513 if (*intel_parser
.disp
!= '\0')
5515 char *s
= intel_parser
.disp
;
5516 s
+= strlen (s
) - 1;
5529 /* The constant was not used for register scaling. Since we have
5530 already consumed the token following `*' we now need to put it
5531 back in the stream. */
5533 intel_putback_token ();
5536 /* Add the constant to the displacement string. */
5537 strcat (intel_parser
.disp
, save_str
);
5543 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5547 /* Match the given token against cur_token. If they match, read the next
5548 token from the operand string. */
5550 intel_match_token (code
)
5553 if (cur_token
.code
== code
)
5560 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5565 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5570 const reg_entry
*reg
;
5571 struct intel_token new_token
;
5573 new_token
.code
= T_NIL
;
5574 new_token
.reg
= NULL
;
5575 new_token
.str
= NULL
;
5577 /* Free the memory allocated to the previous token and move
5578 cur_token to prev_token. */
5580 free (prev_token
.str
);
5582 prev_token
= cur_token
;
5584 /* Skip whitespace. */
5585 while (is_space_char (*intel_parser
.op_string
))
5586 intel_parser
.op_string
++;
5588 /* Return an empty token if we find nothing else on the line. */
5589 if (*intel_parser
.op_string
== '\0')
5591 cur_token
= new_token
;
5595 /* The new token cannot be larger than the remainder of the operand
5597 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5598 if (new_token
.str
== NULL
)
5600 new_token
.str
[0] = '\0';
5602 if (strchr ("0123456789", *intel_parser
.op_string
))
5604 char *p
= new_token
.str
;
5605 char *q
= intel_parser
.op_string
;
5606 new_token
.code
= T_CONST
;
5608 /* Allow any kind of identifier char to encompass floating point and
5609 hexadecimal numbers. */
5610 while (is_identifier_char (*q
))
5614 /* Recognize special symbol names [0-9][bf]. */
5615 if (strlen (intel_parser
.op_string
) == 2
5616 && (intel_parser
.op_string
[1] == 'b'
5617 || intel_parser
.op_string
[1] == 'f'))
5618 new_token
.code
= T_ID
;
5621 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5623 new_token
.code
= *intel_parser
.op_string
;
5624 new_token
.str
[0] = *intel_parser
.op_string
;
5625 new_token
.str
[1] = '\0';
5628 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5629 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5631 new_token
.code
= T_REG
;
5632 new_token
.reg
= reg
;
5634 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5636 new_token
.str
[0] = REGISTER_PREFIX
;
5637 new_token
.str
[1] = '\0';
5640 strcat (new_token
.str
, reg
->reg_name
);
5643 else if (is_identifier_char (*intel_parser
.op_string
))
5645 char *p
= new_token
.str
;
5646 char *q
= intel_parser
.op_string
;
5648 /* A '.' or '$' followed by an identifier char is an identifier.
5649 Otherwise, it's operator '.' followed by an expression. */
5650 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5652 new_token
.code
= *q
;
5653 new_token
.str
[0] = *q
;
5654 new_token
.str
[1] = '\0';
5658 while (is_identifier_char (*q
) || *q
== '@')
5662 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5663 new_token
.code
= T_BYTE
;
5665 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5666 new_token
.code
= T_WORD
;
5668 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5669 new_token
.code
= T_DWORD
;
5671 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5672 new_token
.code
= T_QWORD
;
5674 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5675 new_token
.code
= T_XWORD
;
5677 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5678 new_token
.code
= T_PTR
;
5680 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5681 new_token
.code
= T_SHORT
;
5683 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5685 new_token
.code
= T_OFFSET
;
5687 /* ??? This is not mentioned in the MASM grammar but gcc
5688 makes use of it with -mintel-syntax. OFFSET may be
5689 followed by FLAT: */
5690 if (strncasecmp (q
, " FLAT:", 6) == 0)
5691 strcat (new_token
.str
, " FLAT:");
5694 /* ??? This is not mentioned in the MASM grammar. */
5695 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5696 new_token
.code
= T_OFFSET
;
5699 new_token
.code
= T_ID
;
5704 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5706 intel_parser
.op_string
+= strlen (new_token
.str
);
5707 cur_token
= new_token
;
5710 /* Put cur_token back into the token stream and make cur_token point to
5713 intel_putback_token ()
5715 intel_parser
.op_string
-= strlen (cur_token
.str
);
5716 free (cur_token
.str
);
5717 cur_token
= prev_token
;
5719 /* Forget prev_token. */
5720 prev_token
.code
= T_NIL
;
5721 prev_token
.reg
= NULL
;
5722 prev_token
.str
= NULL
;