1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static void set_code_flag (int);
67 static void set_16bit_gcc_code_flag (int);
68 static void set_intel_syntax (int);
69 static void set_cpu_arch (int);
71 static void pe_directive_secrel (int);
73 static void signed_cons (int);
74 static char *output_invalid (int c
);
75 static int i386_operand (char *);
76 static int i386_intel_operand (char *, int);
77 static const reg_entry
*parse_register (char *, char **);
78 static char *parse_insn (char *, char *);
79 static char *parse_operands (char *, const char *);
80 static void swap_operands (void);
81 static void swap_2_operands (int, int);
82 static void optimize_imm (void);
83 static void optimize_disp (void);
84 static int match_template (void);
85 static int check_string (void);
86 static int process_suffix (void);
87 static int check_byte_reg (void);
88 static int check_long_reg (void);
89 static int check_qword_reg (void);
90 static int check_word_reg (void);
91 static int finalize_imm (void);
92 static int process_operands (void);
93 static const seg_entry
*build_modrm_byte (void);
94 static void output_insn (void);
95 static void output_imm (fragS
*, offsetT
);
96 static void output_disp (fragS
*, offsetT
);
98 static void s_bss (int);
100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
101 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
104 static const char *default_arch
= DEFAULT_ARCH
;
106 /* 'md_assemble ()' gathers together information and puts it into a
113 const reg_entry
*regs
;
118 /* TM holds the template for the insn were currently assembling. */
121 /* SUFFIX holds the instruction mnemonic suffix if given.
122 (e.g. 'l' for 'movl') */
125 /* OPERANDS gives the number of given operands. */
126 unsigned int operands
;
128 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
129 of given register, displacement, memory operands and immediate
131 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
133 /* TYPES [i] is the type (see above #defines) which tells us how to
134 use OP[i] for the corresponding operand. */
135 i386_operand_type types
[MAX_OPERANDS
];
137 /* Displacement expression, immediate expression, or register for each
139 union i386_op op
[MAX_OPERANDS
];
141 /* Flags for operands. */
142 unsigned int flags
[MAX_OPERANDS
];
143 #define Operand_PCrel 1
145 /* Relocation type for operand */
146 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
148 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
149 the base index byte below. */
150 const reg_entry
*base_reg
;
151 const reg_entry
*index_reg
;
152 unsigned int log2_scale_factor
;
154 /* SEG gives the seg_entries of this insn. They are zero unless
155 explicit segment overrides are given. */
156 const seg_entry
*seg
[2];
158 /* PREFIX holds all the given prefix opcodes (usually null).
159 PREFIXES is the number of prefix opcodes. */
160 unsigned int prefixes
;
161 unsigned char prefix
[MAX_PREFIXES
];
163 /* RM and SIB are the modrm byte and the sib byte where the
164 addressing modes of this insn are encoded. */
171 typedef struct _i386_insn i386_insn
;
173 /* List of chars besides those in app.c:symbol_chars that can start an
174 operand. Used to prevent the scrubber eating vital white-space. */
175 const char extra_symbol_chars
[] = "*%-(["
184 #if (defined (TE_I386AIX) \
185 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
186 && !defined (TE_GNU) \
187 && !defined (TE_LINUX) \
188 && !defined (TE_NETWARE) \
189 && !defined (TE_FreeBSD) \
190 && !defined (TE_NetBSD)))
191 /* This array holds the chars that always start a comment. If the
192 pre-processor is disabled, these aren't very useful. The option
193 --divide will remove '/' from this list. */
194 const char *i386_comment_chars
= "#/";
195 #define SVR4_COMMENT_CHARS 1
196 #define PREFIX_SEPARATOR '\\'
199 const char *i386_comment_chars
= "#";
200 #define PREFIX_SEPARATOR '/'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars
[] = "#/";
213 const char line_separator_chars
[] = ";";
215 /* Chars that can be used to separate mant from exp in floating point
217 const char EXP_CHARS
[] = "eE";
219 /* Chars that mean this number is a floating point constant
222 const char FLT_CHARS
[] = "fFdDxX";
224 /* Tables for lexical analysis. */
225 static char mnemonic_chars
[256];
226 static char register_chars
[256];
227 static char operand_chars
[256];
228 static char identifier_chars
[256];
229 static char digit_chars
[256];
231 /* Lexical macros. */
232 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
233 #define is_operand_char(x) (operand_chars[(unsigned char) x])
234 #define is_register_char(x) (register_chars[(unsigned char) x])
235 #define is_space_char(x) ((x) == ' ')
236 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
237 #define is_digit_char(x) (digit_chars[(unsigned char) x])
239 /* All non-digit non-letter characters that may occur in an operand. */
240 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
242 /* md_assemble() always leaves the strings it's passed unaltered. To
243 effect this we maintain a stack of saved characters that we've smashed
244 with '\0's (indicating end of strings for various sub-fields of the
245 assembler instruction). */
246 static char save_stack
[32];
247 static char *save_stack_p
;
248 #define END_STRING_AND_SAVE(s) \
249 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
250 #define RESTORE_END_STRING(s) \
251 do { *(s) = *--save_stack_p; } while (0)
253 /* The instruction we're assembling. */
256 /* Possible templates for current insn. */
257 static const templates
*current_templates
;
259 /* Per instruction expressionS buffers: max displacements & immediates. */
260 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
261 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
263 /* Current operand we are working on. */
264 static int this_operand
;
266 /* We support four different modes. FLAG_CODE variable is used to distinguish
273 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
275 static enum flag_code flag_code
;
276 static unsigned int object_64bit
;
277 static int use_rela_relocations
= 0;
279 /* The names used to print error messages. */
280 static const char *flag_code_names
[] =
287 /* 1 for intel syntax,
289 static int intel_syntax
= 0;
291 /* 1 if register prefix % not required. */
292 static int allow_naked_reg
= 0;
294 /* Register prefix used for error message. */
295 static const char *register_prefix
= "%";
297 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
298 leave, push, and pop instructions so that gcc has the same stack
299 frame as in 32 bit mode. */
300 static char stackop_size
= '\0';
302 /* Non-zero to optimize code alignment. */
303 int optimize_align_code
= 1;
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings
= 0;
309 static const char *cpu_arch_name
= NULL
;
310 static const char *cpu_sub_arch_name
= NULL
;
312 /* CPU feature flags. */
313 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
315 /* Bitwise NOT of cpu_arch_flags. */
316 static i386_cpu_flags cpu_arch_flags_not
;
318 /* If we have selected a cpu we are generating instructions for. */
319 static int cpu_arch_tune_set
= 0;
321 /* Cpu we are generating instructions for. */
322 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
324 /* CPU feature flags of cpu we are generating instructions for. */
325 static i386_cpu_flags cpu_arch_tune_flags
;
327 /* CPU instruction set architecture used. */
328 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
330 /* CPU feature flags of instruction set architecture used. */
331 static i386_cpu_flags cpu_arch_isa_flags
;
333 /* If set, conditional jumps are not automatically promoted to handle
334 larger than a byte offset. */
335 static unsigned int no_cond_jump_promotion
= 0;
337 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
338 static symbolS
*GOT_symbol
;
340 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
341 unsigned int x86_dwarf2_return_column
;
343 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
344 int x86_cie_data_alignment
;
346 /* Interface to relax_segment.
347 There are 3 major relax states for 386 jump insns because the
348 different types of jumps add different sizes to frags when we're
349 figuring out what sort of jump to choose to reach a given label. */
352 #define UNCOND_JUMP 0
354 #define COND_JUMP86 2
359 #define SMALL16 (SMALL | CODE16)
361 #define BIG16 (BIG | CODE16)
365 #define INLINE __inline__
371 #define ENCODE_RELAX_STATE(type, size) \
372 ((relax_substateT) (((type) << 2) | (size)))
373 #define TYPE_FROM_RELAX_STATE(s) \
375 #define DISP_SIZE_FROM_RELAX_STATE(s) \
376 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
378 /* This table is used by relax_frag to promote short jumps to long
379 ones where necessary. SMALL (short) jumps may be promoted to BIG
380 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
381 don't allow a short jump in a 32 bit code segment to be promoted to
382 a 16 bit offset jump because it's slower (requires data size
383 prefix), and doesn't work, unless the destination is in the bottom
384 64k of the code segment (The top 16 bits of eip are zeroed). */
386 const relax_typeS md_relax_table
[] =
389 1) most positive reach of this state,
390 2) most negative reach of this state,
391 3) how many bytes this mode will have in the variable part of the frag
392 4) which index into the table to try if we can't fit into this one. */
394 /* UNCOND_JUMP states. */
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
397 /* dword jmp adds 4 bytes to frag:
398 0 extra opcode bytes, 4 displacement bytes. */
400 /* word jmp adds 2 byte2 to frag:
401 0 extra opcode bytes, 2 displacement bytes. */
404 /* COND_JUMP states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
410 /* word conditionals add 3 bytes to frag:
411 1 extra opcode byte, 2 displacement bytes. */
414 /* COND_JUMP86 states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
420 /* word conditionals add 4 bytes to frag:
421 1 displacement byte and a 3 byte long branch insn. */
425 static const arch_entry cpu_arch
[] =
427 {"generic32", PROCESSOR_GENERIC32
,
428 CPU_GENERIC32_FLAGS
},
429 {"generic64", PROCESSOR_GENERIC64
,
430 CPU_GENERIC64_FLAGS
},
431 {"i8086", PROCESSOR_UNKNOWN
,
433 {"i186", PROCESSOR_UNKNOWN
,
435 {"i286", PROCESSOR_UNKNOWN
,
437 {"i386", PROCESSOR_I386
,
439 {"i486", PROCESSOR_I486
,
441 {"i586", PROCESSOR_PENTIUM
,
443 {"i686", PROCESSOR_PENTIUMPRO
,
445 {"pentium", PROCESSOR_PENTIUM
,
447 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
449 {"pentiumii", PROCESSOR_PENTIUMPRO
,
451 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
453 {"pentium4", PROCESSOR_PENTIUM4
,
455 {"prescott", PROCESSOR_NOCONA
,
457 {"nocona", PROCESSOR_NOCONA
,
459 {"yonah", PROCESSOR_CORE
,
461 {"core", PROCESSOR_CORE
,
463 {"merom", PROCESSOR_CORE2
,
465 {"core2", PROCESSOR_CORE2
,
469 {"k6_2", PROCESSOR_K6
,
471 {"athlon", PROCESSOR_ATHLON
,
473 {"sledgehammer", PROCESSOR_K8
,
475 {"opteron", PROCESSOR_K8
,
479 {"amdfam10", PROCESSOR_AMDFAM10
,
480 CPU_AMDFAM10_FLAGS
},
481 {".mmx", PROCESSOR_UNKNOWN
,
483 {".sse", PROCESSOR_UNKNOWN
,
485 {".sse2", PROCESSOR_UNKNOWN
,
487 {".sse3", PROCESSOR_UNKNOWN
,
489 {".ssse3", PROCESSOR_UNKNOWN
,
491 {".sse4.1", PROCESSOR_UNKNOWN
,
493 {".sse4.2", PROCESSOR_UNKNOWN
,
495 {".sse4", PROCESSOR_UNKNOWN
,
497 {".3dnow", PROCESSOR_UNKNOWN
,
499 {".3dnowa", PROCESSOR_UNKNOWN
,
501 {".padlock", PROCESSOR_UNKNOWN
,
503 {".pacifica", PROCESSOR_UNKNOWN
,
505 {".svme", PROCESSOR_UNKNOWN
,
507 {".sse4a", PROCESSOR_UNKNOWN
,
509 {".abm", PROCESSOR_UNKNOWN
,
513 const pseudo_typeS md_pseudo_table
[] =
515 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes
, 0},
518 {"align", s_align_ptwo
, 0},
520 {"arch", set_cpu_arch
, 0},
524 {"ffloat", float_cons
, 'f'},
525 {"dfloat", float_cons
, 'd'},
526 {"tfloat", float_cons
, 'x'},
528 {"slong", signed_cons
, 4},
529 {"noopt", s_ignore
, 0},
530 {"optim", s_ignore
, 0},
531 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
532 {"code16", set_code_flag
, CODE_16BIT
},
533 {"code32", set_code_flag
, CODE_32BIT
},
534 {"code64", set_code_flag
, CODE_64BIT
},
535 {"intel_syntax", set_intel_syntax
, 1},
536 {"att_syntax", set_intel_syntax
, 0},
537 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
538 {"largecomm", handle_large_common
, 0},
540 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
541 {"loc", dwarf2_directive_loc
, 0},
542 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
545 {"secrel32", pe_directive_secrel
, 0},
550 /* For interface with expression (). */
551 extern char *input_line_pointer
;
553 /* Hash table for instruction mnemonic lookup. */
554 static struct hash_control
*op_hash
;
556 /* Hash table for register lookup. */
557 static struct hash_control
*reg_hash
;
560 i386_align_code (fragS
*fragP
, int count
)
562 /* Various efficient no-op patterns for aligning code labels.
563 Note: Don't try to assemble the instructions in the comments.
564 0L and 0w are not legal. */
565 static const char f32_1
[] =
567 static const char f32_2
[] =
568 {0x66,0x90}; /* xchg %ax,%ax */
569 static const char f32_3
[] =
570 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
571 static const char f32_4
[] =
572 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
573 static const char f32_5
[] =
575 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_6
[] =
577 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
578 static const char f32_7
[] =
579 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
580 static const char f32_8
[] =
582 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_9
[] =
584 {0x89,0xf6, /* movl %esi,%esi */
585 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
586 static const char f32_10
[] =
587 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_11
[] =
590 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_12
[] =
593 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
594 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
595 static const char f32_13
[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_14
[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f16_3
[] =
602 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
603 static const char f16_4
[] =
604 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
605 static const char f16_5
[] =
607 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_6
[] =
609 {0x89,0xf6, /* mov %si,%si */
610 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
611 static const char f16_7
[] =
612 {0x8d,0x74,0x00, /* lea 0(%si),%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_8
[] =
615 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
617 static const char jump_31
[] =
618 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
619 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
620 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
622 static const char *const f32_patt
[] = {
623 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
624 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
626 static const char *const f16_patt
[] = {
627 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
630 static const char alt_3
[] =
632 /* nopl 0(%[re]ax) */
633 static const char alt_4
[] =
634 {0x0f,0x1f,0x40,0x00};
635 /* nopl 0(%[re]ax,%[re]ax,1) */
636 static const char alt_5
[] =
637 {0x0f,0x1f,0x44,0x00,0x00};
638 /* nopw 0(%[re]ax,%[re]ax,1) */
639 static const char alt_6
[] =
640 {0x66,0x0f,0x1f,0x44,0x00,0x00};
641 /* nopl 0L(%[re]ax) */
642 static const char alt_7
[] =
643 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
644 /* nopl 0L(%[re]ax,%[re]ax,1) */
645 static const char alt_8
[] =
646 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
647 /* nopw 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_9
[] =
649 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
651 static const char alt_10
[] =
652 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
654 nopw %cs:0L(%[re]ax,%[re]ax,1) */
655 static const char alt_long_11
[] =
657 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_long_12
[] =
664 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 nopw %cs:0L(%[re]ax,%[re]ax,1) */
669 static const char alt_long_13
[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_14
[] =
684 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
690 nopw %cs:0L(%[re]ax,%[re]ax,1) */
691 static const char alt_long_15
[] =
697 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
698 /* nopl 0(%[re]ax,%[re]ax,1)
699 nopw 0(%[re]ax,%[re]ax,1) */
700 static const char alt_short_11
[] =
701 {0x0f,0x1f,0x44,0x00,0x00,
702 0x66,0x0f,0x1f,0x44,0x00,0x00};
703 /* nopw 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_12
[] =
706 {0x66,0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
710 static const char alt_short_13
[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
715 static const char alt_short_14
[] =
716 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
719 nopl 0L(%[re]ax,%[re]ax,1) */
720 static const char alt_short_15
[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
723 static const char *const alt_short_patt
[] = {
724 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
725 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
726 alt_short_14
, alt_short_15
728 static const char *const alt_long_patt
[] = {
729 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
730 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
731 alt_long_14
, alt_long_15
734 /* Only align for at least a positive non-zero boundary. */
735 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
738 /* We need to decide which NOP sequence to use for 32bit and
739 64bit. When -mtune= is used:
741 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
742 PROCESSOR_GENERIC32, f32_patt will be used.
743 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
744 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
745 alt_long_patt will be used.
746 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
747 PROCESSOR_AMDFAM10, alt_short_patt will be used.
749 When -mtune= isn't used, alt_long_patt will be used if
750 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
753 When -march= or .arch is used, we can't use anything beyond
754 cpu_arch_isa_flags. */
756 if (flag_code
== CODE_16BIT
)
760 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
762 /* Adjust jump offset. */
763 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
766 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
767 f16_patt
[count
- 1], count
);
771 const char *const *patt
= NULL
;
773 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
775 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
776 switch (cpu_arch_tune
)
778 case PROCESSOR_UNKNOWN
:
779 /* We use cpu_arch_isa_flags to check if we SHOULD
780 optimize for Cpu686. */
781 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
782 patt
= alt_long_patt
;
786 case PROCESSOR_PENTIUMPRO
:
787 case PROCESSOR_PENTIUM4
:
788 case PROCESSOR_NOCONA
:
790 case PROCESSOR_CORE2
:
791 case PROCESSOR_GENERIC64
:
792 patt
= alt_long_patt
;
795 case PROCESSOR_ATHLON
:
797 case PROCESSOR_AMDFAM10
:
798 patt
= alt_short_patt
;
802 case PROCESSOR_PENTIUM
:
803 case PROCESSOR_GENERIC32
:
810 switch (cpu_arch_tune
)
812 case PROCESSOR_UNKNOWN
:
813 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
814 PROCESSOR_UNKNOWN. */
820 case PROCESSOR_PENTIUM
:
822 case PROCESSOR_ATHLON
:
824 case PROCESSOR_AMDFAM10
:
825 case PROCESSOR_GENERIC32
:
826 /* We use cpu_arch_isa_flags to check if we CAN optimize
828 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
829 patt
= alt_short_patt
;
833 case PROCESSOR_PENTIUMPRO
:
834 case PROCESSOR_PENTIUM4
:
835 case PROCESSOR_NOCONA
:
837 case PROCESSOR_CORE2
:
838 if (cpu_arch_isa_flags
.bitfield
.cpui686
)
839 patt
= alt_long_patt
;
843 case PROCESSOR_GENERIC64
:
844 patt
= alt_long_patt
;
849 if (patt
== f32_patt
)
851 /* If the padding is less than 15 bytes, we use the normal
852 ones. Otherwise, we use a jump instruction and adjust
855 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
856 patt
[count
- 1], count
);
859 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
861 /* Adjust jump offset. */
862 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
867 /* Maximum length of an instruction is 15 byte. If the
868 padding is greater than 15 bytes and we don't use jump,
869 we have to break it into smaller pieces. */
874 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
879 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
880 patt
[padding
- 1], padding
);
883 fragP
->fr_var
= count
;
887 uints_all_zero (const unsigned int *x
, unsigned int size
)
905 uints_set (unsigned int *x
, unsigned int v
, unsigned int size
)
922 uints_equal (const unsigned int *x
, const unsigned int *y
,
934 return x
[0] == y
[0];
941 #define UINTS_ALL_ZERO(x) \
942 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
943 #define UINTS_SET(x, v) \
944 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
945 #define UINTS_CLEAR(x) \
946 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
947 #define UINTS_EQUAL(x, y) \
948 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
951 cpu_flags_check_cpu64 (i386_cpu_flags f
)
953 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
954 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
957 static INLINE i386_cpu_flags
958 cpu_flags_not (i386_cpu_flags x
)
960 switch (ARRAY_SIZE (x
.array
))
963 x
.array
[2] = ~x
.array
[2];
965 x
.array
[1] = ~x
.array
[1];
967 x
.array
[0] = ~x
.array
[0];
974 x
.bitfield
.unused
= 0;
980 static INLINE i386_cpu_flags
981 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
983 switch (ARRAY_SIZE (x
.array
))
986 x
.array
[2] &= y
.array
[2];
988 x
.array
[1] &= y
.array
[1];
990 x
.array
[0] &= y
.array
[0];
998 static INLINE i386_cpu_flags
999 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1001 switch (ARRAY_SIZE (x
.array
))
1004 x
.array
[2] |= y
.array
[2];
1006 x
.array
[1] |= y
.array
[1];
1008 x
.array
[0] |= y
.array
[0];
1017 cpu_flags_match (i386_cpu_flags x
)
1019 i386_cpu_flags
not = cpu_arch_flags_not
;
1021 not.bitfield
.cpu64
= 1;
1022 not.bitfield
.cpuno64
= 1;
1024 x
.bitfield
.cpu64
= 0;
1025 x
.bitfield
.cpuno64
= 0;
1027 not = cpu_flags_and (x
, not);
1028 return UINTS_ALL_ZERO (not);
1031 static INLINE i386_operand_type
1032 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1034 switch (ARRAY_SIZE (x
.array
))
1037 x
.array
[2] &= y
.array
[2];
1039 x
.array
[1] &= y
.array
[1];
1041 x
.array
[0] &= y
.array
[0];
1049 static INLINE i386_operand_type
1050 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1052 switch (ARRAY_SIZE (x
.array
))
1055 x
.array
[2] |= y
.array
[2];
1057 x
.array
[1] |= y
.array
[1];
1059 x
.array
[0] |= y
.array
[0];
1067 static INLINE i386_operand_type
1068 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1070 switch (ARRAY_SIZE (x
.array
))
1073 x
.array
[2] ^= y
.array
[2];
1075 x
.array
[1] ^= y
.array
[1];
1077 x
.array
[0] ^= y
.array
[0];
1085 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1086 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1087 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1088 static const i386_operand_type reg16_inoutportreg
1089 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1090 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1091 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1092 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1093 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1094 static const i386_operand_type anydisp
1095 = OPERAND_TYPE_ANYDISP
;
1096 static const i386_operand_type baseindex
= OPERAND_TYPE_BASEINDEX
;
1097 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1098 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1099 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1100 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1101 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1102 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1103 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1104 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1105 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1106 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1117 operand_type_check (i386_operand_type t
, enum operand_type c
)
1122 return (t
.bitfield
.reg8
1125 || t
.bitfield
.reg64
);
1128 return (t
.bitfield
.imm8
1132 || t
.bitfield
.imm32s
1133 || t
.bitfield
.imm64
);
1136 return (t
.bitfield
.disp8
1137 || t
.bitfield
.disp16
1138 || t
.bitfield
.disp32
1139 || t
.bitfield
.disp32s
1140 || t
.bitfield
.disp64
);
1143 return (t
.bitfield
.disp8
1144 || t
.bitfield
.disp16
1145 || t
.bitfield
.disp32
1146 || t
.bitfield
.disp32s
1147 || t
.bitfield
.disp64
1148 || t
.bitfield
.baseindex
);
1156 operand_type_match (i386_operand_type overlap
,
1157 i386_operand_type given
)
1159 i386_operand_type temp
= overlap
;
1161 temp
.bitfield
.jumpabsolute
= 0;
1162 if (UINTS_ALL_ZERO (temp
))
1165 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1166 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1169 /* If given types r0 and r1 are registers they must be of the same type
1170 unless the expected operand type register overlap is null.
1171 Note that Acc in a template matches every size of reg. */
1174 operand_type_register_match (i386_operand_type m0
,
1175 i386_operand_type g0
,
1176 i386_operand_type t0
,
1177 i386_operand_type m1
,
1178 i386_operand_type g1
,
1179 i386_operand_type t1
)
1181 if (!operand_type_check (g0
, reg
))
1184 if (!operand_type_check (g1
, reg
))
1187 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1188 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1189 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1190 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1193 if (m0
.bitfield
.acc
)
1195 t0
.bitfield
.reg8
= 1;
1196 t0
.bitfield
.reg16
= 1;
1197 t0
.bitfield
.reg32
= 1;
1198 t0
.bitfield
.reg64
= 1;
1201 if (m1
.bitfield
.acc
)
1203 t1
.bitfield
.reg8
= 1;
1204 t1
.bitfield
.reg16
= 1;
1205 t1
.bitfield
.reg32
= 1;
1206 t1
.bitfield
.reg64
= 1;
1209 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1210 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1211 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1212 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1215 static INLINE
unsigned int
1216 mode_from_disp_size (i386_operand_type t
)
1218 if (t
.bitfield
.disp8
)
1220 else if (t
.bitfield
.disp16
1221 || t
.bitfield
.disp32
1222 || t
.bitfield
.disp32s
)
1229 fits_in_signed_byte (offsetT num
)
1231 return (num
>= -128) && (num
<= 127);
1235 fits_in_unsigned_byte (offsetT num
)
1237 return (num
& 0xff) == num
;
1241 fits_in_unsigned_word (offsetT num
)
1243 return (num
& 0xffff) == num
;
1247 fits_in_signed_word (offsetT num
)
1249 return (-32768 <= num
) && (num
<= 32767);
1253 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1258 return (!(((offsetT
) -1 << 31) & num
)
1259 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1261 } /* fits_in_signed_long() */
1264 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1269 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1271 } /* fits_in_unsigned_long() */
1273 static i386_operand_type
1274 smallest_imm_type (offsetT num
)
1276 i386_operand_type t
;
1279 t
.bitfield
.imm64
= 1;
1281 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1283 /* This code is disabled on the 486 because all the Imm1 forms
1284 in the opcode table are slower on the i486. They're the
1285 versions with the implicitly specified single-position
1286 displacement, which has another syntax if you really want to
1288 t
.bitfield
.imm1
= 1;
1289 t
.bitfield
.imm8
= 1;
1290 t
.bitfield
.imm8s
= 1;
1291 t
.bitfield
.imm16
= 1;
1292 t
.bitfield
.imm32
= 1;
1293 t
.bitfield
.imm32s
= 1;
1295 else if (fits_in_signed_byte (num
))
1297 t
.bitfield
.imm8
= 1;
1298 t
.bitfield
.imm8s
= 1;
1299 t
.bitfield
.imm16
= 1;
1300 t
.bitfield
.imm32
= 1;
1301 t
.bitfield
.imm32s
= 1;
1303 else if (fits_in_unsigned_byte (num
))
1305 t
.bitfield
.imm8
= 1;
1306 t
.bitfield
.imm16
= 1;
1307 t
.bitfield
.imm32
= 1;
1308 t
.bitfield
.imm32s
= 1;
1310 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1312 t
.bitfield
.imm16
= 1;
1313 t
.bitfield
.imm32
= 1;
1314 t
.bitfield
.imm32s
= 1;
1316 else if (fits_in_signed_long (num
))
1318 t
.bitfield
.imm32
= 1;
1319 t
.bitfield
.imm32s
= 1;
1321 else if (fits_in_unsigned_long (num
))
1322 t
.bitfield
.imm32
= 1;
1328 offset_in_range (offsetT val
, int size
)
1334 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1335 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1336 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1338 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1343 /* If BFD64, sign extend val. */
1344 if (!use_rela_relocations
)
1345 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1346 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1348 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1350 char buf1
[40], buf2
[40];
1352 sprint_value (buf1
, val
);
1353 sprint_value (buf2
, val
& mask
);
1354 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1359 /* Returns 0 if attempting to add a prefix where one from the same
1360 class already exists, 1 if non rep/repne added, 2 if rep/repne
1363 add_prefix (unsigned int prefix
)
1368 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1369 && flag_code
== CODE_64BIT
)
1371 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1372 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1373 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1384 case CS_PREFIX_OPCODE
:
1385 case DS_PREFIX_OPCODE
:
1386 case ES_PREFIX_OPCODE
:
1387 case FS_PREFIX_OPCODE
:
1388 case GS_PREFIX_OPCODE
:
1389 case SS_PREFIX_OPCODE
:
1393 case REPNE_PREFIX_OPCODE
:
1394 case REPE_PREFIX_OPCODE
:
1397 case LOCK_PREFIX_OPCODE
:
1405 case ADDR_PREFIX_OPCODE
:
1409 case DATA_PREFIX_OPCODE
:
1413 if (i
.prefix
[q
] != 0)
1421 i
.prefix
[q
] |= prefix
;
1424 as_bad (_("same type of prefix used twice"));
1430 set_code_flag (int value
)
1433 if (flag_code
== CODE_64BIT
)
1435 cpu_arch_flags
.bitfield
.cpu64
= 1;
1436 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1437 cpu_arch_flags_not
.bitfield
.cpu64
= 0;
1438 cpu_arch_flags_not
.bitfield
.cpuno64
= 1;
1442 cpu_arch_flags
.bitfield
.cpu64
= 0;
1443 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1444 cpu_arch_flags_not
.bitfield
.cpu64
= 1;
1445 cpu_arch_flags_not
.bitfield
.cpuno64
= 0;
1447 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1449 as_bad (_("64bit mode not supported on this CPU."));
1451 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1453 as_bad (_("32bit mode not supported on this CPU."));
1455 stackop_size
= '\0';
1459 set_16bit_gcc_code_flag (int new_code_flag
)
1461 flag_code
= new_code_flag
;
1462 if (flag_code
!= CODE_16BIT
)
1464 cpu_arch_flags
.bitfield
.cpu64
= 0;
1465 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1466 cpu_arch_flags_not
.bitfield
.cpu64
= 1;
1467 cpu_arch_flags_not
.bitfield
.cpuno64
= 0;
1468 stackop_size
= LONG_MNEM_SUFFIX
;
1472 set_intel_syntax (int syntax_flag
)
1474 /* Find out if register prefixing is specified. */
1475 int ask_naked_reg
= 0;
1478 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1480 char *string
= input_line_pointer
;
1481 int e
= get_symbol_end ();
1483 if (strcmp (string
, "prefix") == 0)
1485 else if (strcmp (string
, "noprefix") == 0)
1488 as_bad (_("bad argument to syntax directive."));
1489 *input_line_pointer
= e
;
1491 demand_empty_rest_of_line ();
1493 intel_syntax
= syntax_flag
;
1495 if (ask_naked_reg
== 0)
1496 allow_naked_reg
= (intel_syntax
1497 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1499 allow_naked_reg
= (ask_naked_reg
< 0);
1501 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1502 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1503 register_prefix
= allow_naked_reg
? "" : "%";
1507 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1511 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1513 char *string
= input_line_pointer
;
1514 int e
= get_symbol_end ();
1516 i386_cpu_flags flags
;
1518 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1520 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1524 cpu_arch_name
= cpu_arch
[i
].name
;
1525 cpu_sub_arch_name
= NULL
;
1526 cpu_arch_flags
= cpu_arch
[i
].flags
;
1527 if (flag_code
== CODE_64BIT
)
1529 cpu_arch_flags
.bitfield
.cpu64
= 1;
1530 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1534 cpu_arch_flags
.bitfield
.cpu64
= 0;
1535 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1537 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1538 cpu_arch_isa
= cpu_arch
[i
].type
;
1539 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1540 if (!cpu_arch_tune_set
)
1542 cpu_arch_tune
= cpu_arch_isa
;
1543 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1548 flags
= cpu_flags_or (cpu_arch_flags
,
1550 if (!UINTS_EQUAL (flags
, cpu_arch_flags
))
1552 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1553 cpu_arch_flags
= flags
;
1554 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1556 *input_line_pointer
= e
;
1557 demand_empty_rest_of_line ();
1561 if (i
>= ARRAY_SIZE (cpu_arch
))
1562 as_bad (_("no such architecture: `%s'"), string
);
1564 *input_line_pointer
= e
;
1567 as_bad (_("missing cpu architecture"));
1569 no_cond_jump_promotion
= 0;
1570 if (*input_line_pointer
== ','
1571 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1573 char *string
= ++input_line_pointer
;
1574 int e
= get_symbol_end ();
1576 if (strcmp (string
, "nojumps") == 0)
1577 no_cond_jump_promotion
= 1;
1578 else if (strcmp (string
, "jumps") == 0)
1581 as_bad (_("no such architecture modifier: `%s'"), string
);
1583 *input_line_pointer
= e
;
1586 demand_empty_rest_of_line ();
1592 if (!strcmp (default_arch
, "x86_64"))
1593 return bfd_mach_x86_64
;
1594 else if (!strcmp (default_arch
, "i386"))
1595 return bfd_mach_i386_i386
;
1597 as_fatal (_("Unknown architecture"));
1603 const char *hash_err
;
1605 cpu_arch_flags_not
= cpu_flags_not (cpu_arch_flags
);
1607 /* Initialize op_hash hash table. */
1608 op_hash
= hash_new ();
1611 const template *optab
;
1612 templates
*core_optab
;
1614 /* Setup for loop. */
1616 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1617 core_optab
->start
= optab
;
1622 if (optab
->name
== NULL
1623 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1625 /* different name --> ship out current template list;
1626 add to hash table; & begin anew. */
1627 core_optab
->end
= optab
;
1628 hash_err
= hash_insert (op_hash
,
1633 as_fatal (_("Internal Error: Can't hash %s: %s"),
1637 if (optab
->name
== NULL
)
1639 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1640 core_optab
->start
= optab
;
1645 /* Initialize reg_hash hash table. */
1646 reg_hash
= hash_new ();
1648 const reg_entry
*regtab
;
1649 unsigned int regtab_size
= i386_regtab_size
;
1651 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1653 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1655 as_fatal (_("Internal Error: Can't hash %s: %s"),
1661 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1666 for (c
= 0; c
< 256; c
++)
1671 mnemonic_chars
[c
] = c
;
1672 register_chars
[c
] = c
;
1673 operand_chars
[c
] = c
;
1675 else if (ISLOWER (c
))
1677 mnemonic_chars
[c
] = c
;
1678 register_chars
[c
] = c
;
1679 operand_chars
[c
] = c
;
1681 else if (ISUPPER (c
))
1683 mnemonic_chars
[c
] = TOLOWER (c
);
1684 register_chars
[c
] = mnemonic_chars
[c
];
1685 operand_chars
[c
] = c
;
1688 if (ISALPHA (c
) || ISDIGIT (c
))
1689 identifier_chars
[c
] = c
;
1692 identifier_chars
[c
] = c
;
1693 operand_chars
[c
] = c
;
1698 identifier_chars
['@'] = '@';
1701 identifier_chars
['?'] = '?';
1702 operand_chars
['?'] = '?';
1704 digit_chars
['-'] = '-';
1705 mnemonic_chars
['-'] = '-';
1706 mnemonic_chars
['.'] = '.';
1707 identifier_chars
['_'] = '_';
1708 identifier_chars
['.'] = '.';
1710 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1711 operand_chars
[(unsigned char) *p
] = *p
;
1714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1717 record_alignment (text_section
, 2);
1718 record_alignment (data_section
, 2);
1719 record_alignment (bss_section
, 2);
1723 if (flag_code
== CODE_64BIT
)
1725 x86_dwarf2_return_column
= 16;
1726 x86_cie_data_alignment
= -8;
1730 x86_dwarf2_return_column
= 8;
1731 x86_cie_data_alignment
= -4;
1736 i386_print_statistics (FILE *file
)
1738 hash_print_statistics (file
, "i386 opcode", op_hash
);
1739 hash_print_statistics (file
, "i386 register", reg_hash
);
1744 /* Debugging routines for md_assemble. */
1745 static void pte (template *);
1746 static void pt (i386_operand_type
);
1747 static void pe (expressionS
*);
1748 static void ps (symbolS
*);
1751 pi (char *line
, i386_insn
*x
)
1755 fprintf (stdout
, "%s: template ", line
);
1757 fprintf (stdout
, " address: base %s index %s scale %x\n",
1758 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1759 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1760 x
->log2_scale_factor
);
1761 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1762 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1763 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1764 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1765 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1766 (x
->rex
& REX_W
) != 0,
1767 (x
->rex
& REX_R
) != 0,
1768 (x
->rex
& REX_X
) != 0,
1769 (x
->rex
& REX_B
) != 0);
1770 for (i
= 0; i
< x
->operands
; i
++)
1772 fprintf (stdout
, " #%d: ", i
+ 1);
1774 fprintf (stdout
, "\n");
1775 if (x
->types
[i
].bitfield
.reg8
1776 || x
->types
[i
].bitfield
.reg16
1777 || x
->types
[i
].bitfield
.reg32
1778 || x
->types
[i
].bitfield
.reg64
1779 || x
->types
[i
].bitfield
.regmmx
1780 || x
->types
[i
].bitfield
.regxmm
1781 || x
->types
[i
].bitfield
.sreg2
1782 || x
->types
[i
].bitfield
.sreg3
1783 || x
->types
[i
].bitfield
.control
1784 || x
->types
[i
].bitfield
.debug
1785 || x
->types
[i
].bitfield
.test
)
1786 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1787 if (operand_type_check (x
->types
[i
], imm
))
1789 if (operand_type_check (x
->types
[i
], disp
))
1790 pe (x
->op
[i
].disps
);
1798 fprintf (stdout
, " %d operands ", t
->operands
);
1799 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1800 if (t
->extension_opcode
!= None
)
1801 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1802 if (t
->opcode_modifier
.d
)
1803 fprintf (stdout
, "D");
1804 if (t
->opcode_modifier
.w
)
1805 fprintf (stdout
, "W");
1806 fprintf (stdout
, "\n");
1807 for (i
= 0; i
< t
->operands
; i
++)
1809 fprintf (stdout
, " #%d type ", i
+ 1);
1810 pt (t
->operand_types
[i
]);
1811 fprintf (stdout
, "\n");
1818 fprintf (stdout
, " operation %d\n", e
->X_op
);
1819 fprintf (stdout
, " add_number %ld (%lx)\n",
1820 (long) e
->X_add_number
, (long) e
->X_add_number
);
1821 if (e
->X_add_symbol
)
1823 fprintf (stdout
, " add_symbol ");
1824 ps (e
->X_add_symbol
);
1825 fprintf (stdout
, "\n");
1829 fprintf (stdout
, " op_symbol ");
1830 ps (e
->X_op_symbol
);
1831 fprintf (stdout
, "\n");
1838 fprintf (stdout
, "%s type %s%s",
1840 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1841 segment_name (S_GET_SEGMENT (s
)));
1844 static struct type_name
1846 i386_operand_type mask
;
1849 const type_names
[] =
1851 { OPERAND_TYPE_REG8
, "r8" },
1852 { OPERAND_TYPE_REG16
, "r16" },
1853 { OPERAND_TYPE_REG32
, "r32" },
1854 { OPERAND_TYPE_REG64
, "r64" },
1855 { OPERAND_TYPE_IMM8
, "i8" },
1856 { OPERAND_TYPE_IMM8
, "i8s" },
1857 { OPERAND_TYPE_IMM16
, "i16" },
1858 { OPERAND_TYPE_IMM32
, "i32" },
1859 { OPERAND_TYPE_IMM32S
, "i32s" },
1860 { OPERAND_TYPE_IMM64
, "i64" },
1861 { OPERAND_TYPE_IMM1
, "i1" },
1862 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
1863 { OPERAND_TYPE_DISP8
, "d8" },
1864 { OPERAND_TYPE_DISP16
, "d16" },
1865 { OPERAND_TYPE_DISP32
, "d32" },
1866 { OPERAND_TYPE_DISP32S
, "d32s" },
1867 { OPERAND_TYPE_DISP64
, "d64" },
1868 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
1869 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
1870 { OPERAND_TYPE_CONTROL
, "control reg" },
1871 { OPERAND_TYPE_TEST
, "test reg" },
1872 { OPERAND_TYPE_DEBUG
, "debug reg" },
1873 { OPERAND_TYPE_FLOATREG
, "FReg" },
1874 { OPERAND_TYPE_FLOATACC
, "FAcc" },
1875 { OPERAND_TYPE_SREG2
, "SReg2" },
1876 { OPERAND_TYPE_SREG3
, "SReg3" },
1877 { OPERAND_TYPE_ACC
, "Acc" },
1878 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
1879 { OPERAND_TYPE_REGMMX
, "rMMX" },
1880 { OPERAND_TYPE_REGXMM
, "rXMM" },
1881 { OPERAND_TYPE_ESSEG
, "es" },
1885 pt (i386_operand_type t
)
1888 i386_operand_type a
;
1890 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
1892 a
= operand_type_and (t
, type_names
[j
].mask
);
1893 if (!UINTS_ALL_ZERO (a
))
1894 fprintf (stdout
, "%s, ", type_names
[j
].name
);
1899 #endif /* DEBUG386 */
1901 static bfd_reloc_code_real_type
1902 reloc (unsigned int size
,
1905 bfd_reloc_code_real_type other
)
1907 if (other
!= NO_RELOC
)
1909 reloc_howto_type
*reloc
;
1914 case BFD_RELOC_X86_64_GOT32
:
1915 return BFD_RELOC_X86_64_GOT64
;
1917 case BFD_RELOC_X86_64_PLTOFF64
:
1918 return BFD_RELOC_X86_64_PLTOFF64
;
1920 case BFD_RELOC_X86_64_GOTPC32
:
1921 other
= BFD_RELOC_X86_64_GOTPC64
;
1923 case BFD_RELOC_X86_64_GOTPCREL
:
1924 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1926 case BFD_RELOC_X86_64_TPOFF32
:
1927 other
= BFD_RELOC_X86_64_TPOFF64
;
1929 case BFD_RELOC_X86_64_DTPOFF32
:
1930 other
= BFD_RELOC_X86_64_DTPOFF64
;
1936 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1937 if (size
== 4 && flag_code
!= CODE_64BIT
)
1940 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1942 as_bad (_("unknown relocation (%u)"), other
);
1943 else if (size
!= bfd_get_reloc_size (reloc
))
1944 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1945 bfd_get_reloc_size (reloc
),
1947 else if (pcrel
&& !reloc
->pc_relative
)
1948 as_bad (_("non-pc-relative relocation for pc-relative field"));
1949 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1951 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1953 as_bad (_("relocated field and relocation type differ in signedness"));
1962 as_bad (_("there are no unsigned pc-relative relocations"));
1965 case 1: return BFD_RELOC_8_PCREL
;
1966 case 2: return BFD_RELOC_16_PCREL
;
1967 case 4: return BFD_RELOC_32_PCREL
;
1968 case 8: return BFD_RELOC_64_PCREL
;
1970 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1977 case 4: return BFD_RELOC_X86_64_32S
;
1982 case 1: return BFD_RELOC_8
;
1983 case 2: return BFD_RELOC_16
;
1984 case 4: return BFD_RELOC_32
;
1985 case 8: return BFD_RELOC_64
;
1987 as_bad (_("cannot do %s %u byte relocation"),
1988 sign
> 0 ? "signed" : "unsigned", size
);
1992 return BFD_RELOC_NONE
;
1995 /* Here we decide which fixups can be adjusted to make them relative to
1996 the beginning of the section instead of the symbol. Basically we need
1997 to make sure that the dynamic relocations are done correctly, so in
1998 some cases we force the original symbol to be used. */
2001 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2003 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2007 /* Don't adjust pc-relative references to merge sections in 64-bit
2009 if (use_rela_relocations
2010 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2014 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2015 and changed later by validate_fix. */
2016 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2017 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2020 /* adjust_reloc_syms doesn't know about the GOT. */
2021 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2022 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2023 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2024 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2025 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2026 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2027 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2028 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2029 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2030 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2031 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2032 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2033 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2034 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2035 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2036 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2037 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2038 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2039 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2040 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2041 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2042 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2043 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2044 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2045 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2046 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2047 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2048 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2055 intel_float_operand (const char *mnemonic
)
2057 /* Note that the value returned is meaningful only for opcodes with (memory)
2058 operands, hence the code here is free to improperly handle opcodes that
2059 have no operands (for better performance and smaller code). */
2061 if (mnemonic
[0] != 'f')
2062 return 0; /* non-math */
2064 switch (mnemonic
[1])
2066 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2067 the fs segment override prefix not currently handled because no
2068 call path can make opcodes without operands get here */
2070 return 2 /* integer op */;
2072 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2073 return 3; /* fldcw/fldenv */
2076 if (mnemonic
[2] != 'o' /* fnop */)
2077 return 3; /* non-waiting control op */
2080 if (mnemonic
[2] == 's')
2081 return 3; /* frstor/frstpm */
2084 if (mnemonic
[2] == 'a')
2085 return 3; /* fsave */
2086 if (mnemonic
[2] == 't')
2088 switch (mnemonic
[3])
2090 case 'c': /* fstcw */
2091 case 'd': /* fstdw */
2092 case 'e': /* fstenv */
2093 case 's': /* fsts[gw] */
2099 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2100 return 0; /* fxsave/fxrstor are not really math ops */
2107 /* This is the guts of the machine-dependent assembler. LINE points to a
2108 machine dependent instruction. This function is supposed to emit
2109 the frags/bytes it assembles to. */
2116 char mnemonic
[MAX_MNEM_SIZE
];
2118 /* Initialize globals. */
2119 memset (&i
, '\0', sizeof (i
));
2120 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2121 i
.reloc
[j
] = NO_RELOC
;
2122 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2123 memset (im_expressions
, '\0', sizeof (im_expressions
));
2124 save_stack_p
= save_stack
;
2126 /* First parse an instruction mnemonic & call i386_operand for the operands.
2127 We assume that the scrubber has arranged it so that line[0] is the valid
2128 start of a (possibly prefixed) mnemonic. */
2130 line
= parse_insn (line
, mnemonic
);
2134 line
= parse_operands (line
, mnemonic
);
2138 /* Now we've parsed the mnemonic into a set of templates, and have the
2139 operands at hand. */
2141 /* All intel opcodes have reversed operands except for "bound" and
2142 "enter". We also don't reverse intersegment "jmp" and "call"
2143 instructions with 2 immediate operands so that the immediate segment
2144 precedes the offset, as it does when in AT&T mode. */
2147 && (strcmp (mnemonic
, "bound") != 0)
2148 && (strcmp (mnemonic
, "invlpga") != 0)
2149 && !(operand_type_check (i
.types
[0], imm
)
2150 && operand_type_check (i
.types
[1], imm
)))
2153 /* The order of the immediates should be reversed
2154 for 2 immediates extrq and insertq instructions */
2155 if (i
.imm_operands
== 2
2156 && (strcmp (mnemonic
, "extrq") == 0
2157 || strcmp (mnemonic
, "insertq") == 0))
2158 swap_2_operands (0, 1);
2163 /* Don't optimize displacement for movabs since it only takes 64bit
2166 && (flag_code
!= CODE_64BIT
2167 || strcmp (mnemonic
, "movabs") != 0))
2170 /* Next, we find a template that matches the given insn,
2171 making sure the overlap of the given operands types is consistent
2172 with the template operand types. */
2174 if (!match_template ())
2179 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2181 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
2182 i
.tm
.base_opcode
^= Opcode_FloatR
;
2184 /* Zap movzx and movsx suffix. The suffix may have been set from
2185 "word ptr" or "byte ptr" on the source operand, but we'll use
2186 the suffix later to choose the destination register. */
2187 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2189 if (i
.reg_operands
< 2
2191 && (!i
.tm
.opcode_modifier
.no_bsuf
2192 || !i
.tm
.opcode_modifier
.no_wsuf
2193 || !i
.tm
.opcode_modifier
.no_lsuf
2194 || !i
.tm
.opcode_modifier
.no_ssuf
2195 || !i
.tm
.opcode_modifier
.no_xsuf
2196 || !i
.tm
.opcode_modifier
.no_qsuf
))
2197 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2203 if (i
.tm
.opcode_modifier
.fwait
)
2204 if (!add_prefix (FWAIT_OPCODE
))
2207 /* Check string instruction segment overrides. */
2208 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2210 if (!check_string ())
2214 if (!process_suffix ())
2217 /* Make still unresolved immediate matches conform to size of immediate
2218 given in i.suffix. */
2219 if (!finalize_imm ())
2222 if (i
.types
[0].bitfield
.imm1
)
2223 i
.imm_operands
= 0; /* kludge for shift insns. */
2225 for (j
= 0; j
< 3; j
++)
2226 if (i
.types
[j
].bitfield
.inoutportreg
2227 || i
.types
[j
].bitfield
.shiftcount
2228 || i
.types
[j
].bitfield
.acc
2229 || i
.types
[j
].bitfield
.floatacc
)
2232 if (i
.tm
.opcode_modifier
.immext
)
2236 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2238 /* Streaming SIMD extensions 3 Instructions have the fixed
2239 operands with an opcode suffix which is coded in the same
2240 place as an 8-bit immediate field would be. Here we check
2241 those operands and remove them afterwards. */
2244 for (x
= 0; x
< i
.operands
; x
++)
2245 if (i
.op
[x
].regs
->reg_num
!= x
)
2246 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2248 i
.op
[x
].regs
->reg_name
,
2254 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2255 opcode suffix which is coded in the same place as an 8-bit
2256 immediate field would be. Here we fake an 8-bit immediate
2257 operand from the opcode suffix stored in tm.extension_opcode. */
2259 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2261 exp
= &im_expressions
[i
.imm_operands
++];
2262 i
.op
[i
.operands
].imms
= exp
;
2263 UINTS_CLEAR (i
.types
[i
.operands
]);
2264 i
.types
[i
.operands
].bitfield
.imm8
= 1;
2266 exp
->X_op
= O_constant
;
2267 exp
->X_add_number
= i
.tm
.extension_opcode
;
2268 i
.tm
.extension_opcode
= None
;
2271 /* For insns with operands there are more diddles to do to the opcode. */
2274 if (!process_operands ())
2277 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2279 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2280 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2283 /* Handle conversion of 'int $3' --> special int3 insn. */
2284 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2286 i
.tm
.base_opcode
= INT3_OPCODE
;
2290 if ((i
.tm
.opcode_modifier
.jump
2291 || i
.tm
.opcode_modifier
.jumpbyte
2292 || i
.tm
.opcode_modifier
.jumpdword
)
2293 && i
.op
[0].disps
->X_op
== O_constant
)
2295 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2296 the absolute address given by the constant. Since ix86 jumps and
2297 calls are pc relative, we need to generate a reloc. */
2298 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2299 i
.op
[0].disps
->X_op
= O_symbol
;
2302 if (i
.tm
.opcode_modifier
.rex64
)
2305 /* For 8 bit registers we need an empty rex prefix. Also if the
2306 instruction already has a prefix, we need to convert old
2307 registers to new ones. */
2309 if ((i
.types
[0].bitfield
.reg8
2310 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2311 || (i
.types
[1].bitfield
.reg8
2312 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2313 || ((i
.types
[0].bitfield
.reg8
2314 || i
.types
[1].bitfield
.reg8
)
2319 i
.rex
|= REX_OPCODE
;
2320 for (x
= 0; x
< 2; x
++)
2322 /* Look for 8 bit operand that uses old registers. */
2323 if (i
.types
[x
].bitfield
.reg8
2324 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2326 /* In case it is "hi" register, give up. */
2327 if (i
.op
[x
].regs
->reg_num
> 3)
2328 as_bad (_("can't encode register '%s%s' in an "
2329 "instruction requiring REX prefix."),
2330 register_prefix
, i
.op
[x
].regs
->reg_name
);
2332 /* Otherwise it is equivalent to the extended register.
2333 Since the encoding doesn't change this is merely
2334 cosmetic cleanup for debug output. */
2336 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2342 add_prefix (REX_OPCODE
| i
.rex
);
2344 /* We are ready to output the insn. */
2349 parse_insn (char *line
, char *mnemonic
)
2352 char *token_start
= l
;
2357 /* Non-zero if we found a prefix only acceptable with string insns. */
2358 const char *expecting_string_instruction
= NULL
;
2363 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2366 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2368 as_bad (_("no such instruction: `%s'"), token_start
);
2373 if (!is_space_char (*l
)
2374 && *l
!= END_OF_INSN
2376 || (*l
!= PREFIX_SEPARATOR
2379 as_bad (_("invalid character %s in mnemonic"),
2380 output_invalid (*l
));
2383 if (token_start
== l
)
2385 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2386 as_bad (_("expecting prefix; got nothing"));
2388 as_bad (_("expecting mnemonic; got nothing"));
2392 /* Look up instruction (or prefix) via hash table. */
2393 current_templates
= hash_find (op_hash
, mnemonic
);
2395 if (*l
!= END_OF_INSN
2396 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2397 && current_templates
2398 && current_templates
->start
->opcode_modifier
.isprefix
)
2400 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2402 as_bad ((flag_code
!= CODE_64BIT
2403 ? _("`%s' is only supported in 64-bit mode")
2404 : _("`%s' is not supported in 64-bit mode")),
2405 current_templates
->start
->name
);
2408 /* If we are in 16-bit mode, do not allow addr16 or data16.
2409 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2410 if ((current_templates
->start
->opcode_modifier
.size16
2411 || current_templates
->start
->opcode_modifier
.size32
)
2412 && flag_code
!= CODE_64BIT
2413 && (current_templates
->start
->opcode_modifier
.size32
2414 ^ (flag_code
== CODE_16BIT
)))
2416 as_bad (_("redundant %s prefix"),
2417 current_templates
->start
->name
);
2420 /* Add prefix, checking for repeated prefixes. */
2421 switch (add_prefix (current_templates
->start
->base_opcode
))
2426 expecting_string_instruction
= current_templates
->start
->name
;
2429 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2436 if (!current_templates
)
2438 /* See if we can get a match by trimming off a suffix. */
2441 case WORD_MNEM_SUFFIX
:
2442 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2443 i
.suffix
= SHORT_MNEM_SUFFIX
;
2445 case BYTE_MNEM_SUFFIX
:
2446 case QWORD_MNEM_SUFFIX
:
2447 i
.suffix
= mnem_p
[-1];
2449 current_templates
= hash_find (op_hash
, mnemonic
);
2451 case SHORT_MNEM_SUFFIX
:
2452 case LONG_MNEM_SUFFIX
:
2455 i
.suffix
= mnem_p
[-1];
2457 current_templates
= hash_find (op_hash
, mnemonic
);
2465 if (intel_float_operand (mnemonic
) == 1)
2466 i
.suffix
= SHORT_MNEM_SUFFIX
;
2468 i
.suffix
= LONG_MNEM_SUFFIX
;
2470 current_templates
= hash_find (op_hash
, mnemonic
);
2474 if (!current_templates
)
2476 as_bad (_("no such instruction: `%s'"), token_start
);
2481 if (current_templates
->start
->opcode_modifier
.jump
2482 || current_templates
->start
->opcode_modifier
.jumpbyte
)
2484 /* Check for a branch hint. We allow ",pt" and ",pn" for
2485 predict taken and predict not taken respectively.
2486 I'm not sure that branch hints actually do anything on loop
2487 and jcxz insns (JumpByte) for current Pentium4 chips. They
2488 may work in the future and it doesn't hurt to accept them
2490 if (l
[0] == ',' && l
[1] == 'p')
2494 if (!add_prefix (DS_PREFIX_OPCODE
))
2498 else if (l
[2] == 'n')
2500 if (!add_prefix (CS_PREFIX_OPCODE
))
2506 /* Any other comma loses. */
2509 as_bad (_("invalid character %s in mnemonic"),
2510 output_invalid (*l
));
2514 /* Check if instruction is supported on specified architecture. */
2516 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2518 if (cpu_flags_match (t
->cpu_flags
))
2520 if (cpu_flags_check_cpu64 (t
->cpu_flags
))
2523 if (!(supported
& 2))
2525 as_bad (flag_code
== CODE_64BIT
2526 ? _("`%s' is not supported in 64-bit mode")
2527 : _("`%s' is only supported in 64-bit mode"),
2528 current_templates
->start
->name
);
2531 if (!(supported
& 1))
2533 as_warn (_("`%s' is not supported on `%s%s'"),
2534 current_templates
->start
->name
,
2536 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2538 else if (!cpu_arch_flags
.bitfield
.cpui386
2539 && (flag_code
!= CODE_16BIT
))
2541 as_warn (_("use .code16 to ensure correct addressing mode"));
2544 /* Check for rep/repne without a string instruction. */
2545 if (expecting_string_instruction
)
2547 static templates override
;
2549 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2550 if (t
->opcode_modifier
.isstring
)
2552 if (t
>= current_templates
->end
)
2554 as_bad (_("expecting string instruction after `%s'"),
2555 expecting_string_instruction
);
2558 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2559 if (!t
->opcode_modifier
.isstring
)
2562 current_templates
= &override
;
2569 parse_operands (char *l
, const char *mnemonic
)
2573 /* 1 if operand is pending after ','. */
2574 unsigned int expecting_operand
= 0;
2576 /* Non-zero if operand parens not balanced. */
2577 unsigned int paren_not_balanced
;
2579 while (*l
!= END_OF_INSN
)
2581 /* Skip optional white space before operand. */
2582 if (is_space_char (*l
))
2584 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2586 as_bad (_("invalid character %s before operand %d"),
2587 output_invalid (*l
),
2591 token_start
= l
; /* after white space */
2592 paren_not_balanced
= 0;
2593 while (paren_not_balanced
|| *l
!= ',')
2595 if (*l
== END_OF_INSN
)
2597 if (paren_not_balanced
)
2600 as_bad (_("unbalanced parenthesis in operand %d."),
2603 as_bad (_("unbalanced brackets in operand %d."),
2608 break; /* we are done */
2610 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2612 as_bad (_("invalid character %s in operand %d"),
2613 output_invalid (*l
),
2620 ++paren_not_balanced
;
2622 --paren_not_balanced
;
2627 ++paren_not_balanced
;
2629 --paren_not_balanced
;
2633 if (l
!= token_start
)
2634 { /* Yes, we've read in another operand. */
2635 unsigned int operand_ok
;
2636 this_operand
= i
.operands
++;
2637 if (i
.operands
> MAX_OPERANDS
)
2639 as_bad (_("spurious operands; (%d operands/instruction max)"),
2643 /* Now parse operand adding info to 'i' as we go along. */
2644 END_STRING_AND_SAVE (l
);
2648 i386_intel_operand (token_start
,
2649 intel_float_operand (mnemonic
));
2651 operand_ok
= i386_operand (token_start
);
2653 RESTORE_END_STRING (l
);
2659 if (expecting_operand
)
2661 expecting_operand_after_comma
:
2662 as_bad (_("expecting operand after ','; got nothing"));
2667 as_bad (_("expecting operand before ','; got nothing"));
2672 /* Now *l must be either ',' or END_OF_INSN. */
2675 if (*++l
== END_OF_INSN
)
2677 /* Just skip it, if it's \n complain. */
2678 goto expecting_operand_after_comma
;
2680 expecting_operand
= 1;
2687 swap_2_operands (int xchg1
, int xchg2
)
2689 union i386_op temp_op
;
2690 i386_operand_type temp_type
;
2691 enum bfd_reloc_code_real temp_reloc
;
2693 temp_type
= i
.types
[xchg2
];
2694 i
.types
[xchg2
] = i
.types
[xchg1
];
2695 i
.types
[xchg1
] = temp_type
;
2696 temp_op
= i
.op
[xchg2
];
2697 i
.op
[xchg2
] = i
.op
[xchg1
];
2698 i
.op
[xchg1
] = temp_op
;
2699 temp_reloc
= i
.reloc
[xchg2
];
2700 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2701 i
.reloc
[xchg1
] = temp_reloc
;
2705 swap_operands (void)
2710 swap_2_operands (1, i
.operands
- 2);
2713 swap_2_operands (0, i
.operands
- 1);
2719 if (i
.mem_operands
== 2)
2721 const seg_entry
*temp_seg
;
2722 temp_seg
= i
.seg
[0];
2723 i
.seg
[0] = i
.seg
[1];
2724 i
.seg
[1] = temp_seg
;
2728 /* Try to ensure constant immediates are represented in the smallest
2733 char guess_suffix
= 0;
2737 guess_suffix
= i
.suffix
;
2738 else if (i
.reg_operands
)
2740 /* Figure out a suffix from the last register operand specified.
2741 We can't do this properly yet, ie. excluding InOutPortReg,
2742 but the following works for instructions with immediates.
2743 In any case, we can't set i.suffix yet. */
2744 for (op
= i
.operands
; --op
>= 0;)
2745 if (i
.types
[op
].bitfield
.reg8
)
2747 guess_suffix
= BYTE_MNEM_SUFFIX
;
2750 else if (i
.types
[op
].bitfield
.reg16
)
2752 guess_suffix
= WORD_MNEM_SUFFIX
;
2755 else if (i
.types
[op
].bitfield
.reg32
)
2757 guess_suffix
= LONG_MNEM_SUFFIX
;
2760 else if (i
.types
[op
].bitfield
.reg64
)
2762 guess_suffix
= QWORD_MNEM_SUFFIX
;
2766 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2767 guess_suffix
= WORD_MNEM_SUFFIX
;
2769 for (op
= i
.operands
; --op
>= 0;)
2770 if (operand_type_check (i
.types
[op
], imm
))
2772 switch (i
.op
[op
].imms
->X_op
)
2775 /* If a suffix is given, this operand may be shortened. */
2776 switch (guess_suffix
)
2778 case LONG_MNEM_SUFFIX
:
2779 i
.types
[op
].bitfield
.imm32
= 1;
2780 i
.types
[op
].bitfield
.imm64
= 1;
2782 case WORD_MNEM_SUFFIX
:
2783 i
.types
[op
].bitfield
.imm16
= 1;
2784 i
.types
[op
].bitfield
.imm32
= 1;
2785 i
.types
[op
].bitfield
.imm32s
= 1;
2786 i
.types
[op
].bitfield
.imm64
= 1;
2788 case BYTE_MNEM_SUFFIX
:
2789 i
.types
[op
].bitfield
.imm8
= 1;
2790 i
.types
[op
].bitfield
.imm8s
= 1;
2791 i
.types
[op
].bitfield
.imm16
= 1;
2792 i
.types
[op
].bitfield
.imm32
= 1;
2793 i
.types
[op
].bitfield
.imm32s
= 1;
2794 i
.types
[op
].bitfield
.imm64
= 1;
2798 /* If this operand is at most 16 bits, convert it
2799 to a signed 16 bit number before trying to see
2800 whether it will fit in an even smaller size.
2801 This allows a 16-bit operand such as $0xffe0 to
2802 be recognised as within Imm8S range. */
2803 if ((i
.types
[op
].bitfield
.imm16
)
2804 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2806 i
.op
[op
].imms
->X_add_number
=
2807 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2809 if ((i
.types
[op
].bitfield
.imm32
)
2810 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2813 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2814 ^ ((offsetT
) 1 << 31))
2815 - ((offsetT
) 1 << 31));
2818 = operand_type_or (i
.types
[op
],
2819 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
2821 /* We must avoid matching of Imm32 templates when 64bit
2822 only immediate is available. */
2823 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2824 i
.types
[op
].bitfield
.imm32
= 0;
2831 /* Symbols and expressions. */
2833 /* Convert symbolic operand to proper sizes for matching, but don't
2834 prevent matching a set of insns that only supports sizes other
2835 than those matching the insn suffix. */
2837 i386_operand_type mask
, allowed
;
2841 UINTS_CLEAR (allowed
);
2843 for (t
= current_templates
->start
;
2844 t
< current_templates
->end
;
2846 allowed
= operand_type_or (allowed
,
2847 t
->operand_types
[op
]);
2848 switch (guess_suffix
)
2850 case QWORD_MNEM_SUFFIX
:
2851 mask
.bitfield
.imm64
= 1;
2852 mask
.bitfield
.imm32s
= 1;
2854 case LONG_MNEM_SUFFIX
:
2855 mask
.bitfield
.imm32
= 1;
2857 case WORD_MNEM_SUFFIX
:
2858 mask
.bitfield
.imm16
= 1;
2860 case BYTE_MNEM_SUFFIX
:
2861 mask
.bitfield
.imm8
= 1;
2866 allowed
= operand_type_and (mask
, allowed
);
2867 if (!UINTS_ALL_ZERO (allowed
))
2868 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
2875 /* Try to use the smallest displacement type too. */
2877 optimize_disp (void)
2881 for (op
= i
.operands
; --op
>= 0;)
2882 if (operand_type_check (i
.types
[op
], disp
))
2884 if (i
.op
[op
].disps
->X_op
== O_constant
)
2886 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2888 if (i
.types
[op
].bitfield
.disp16
2889 && (disp
& ~(offsetT
) 0xffff) == 0)
2891 /* If this operand is at most 16 bits, convert
2892 to a signed 16 bit number and don't use 64bit
2894 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2895 i
.types
[op
].bitfield
.disp64
= 0;
2897 if (i
.types
[op
].bitfield
.disp32
2898 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2900 /* If this operand is at most 32 bits, convert
2901 to a signed 32 bit number and don't use 64bit
2903 disp
&= (((offsetT
) 2 << 31) - 1);
2904 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2905 i
.types
[op
].bitfield
.disp64
= 0;
2907 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
2909 i
.types
[op
].bitfield
.disp8
= 0;
2910 i
.types
[op
].bitfield
.disp16
= 0;
2911 i
.types
[op
].bitfield
.disp32
= 0;
2912 i
.types
[op
].bitfield
.disp32s
= 0;
2913 i
.types
[op
].bitfield
.disp64
= 0;
2917 else if (flag_code
== CODE_64BIT
)
2919 if (fits_in_signed_long (disp
))
2921 i
.types
[op
].bitfield
.disp64
= 0;
2922 i
.types
[op
].bitfield
.disp32s
= 1;
2924 if (fits_in_unsigned_long (disp
))
2925 i
.types
[op
].bitfield
.disp32
= 1;
2927 if ((i
.types
[op
].bitfield
.disp32
2928 || i
.types
[op
].bitfield
.disp32s
2929 || i
.types
[op
].bitfield
.disp16
)
2930 && fits_in_signed_byte (disp
))
2931 i
.types
[op
].bitfield
.disp8
= 1;
2933 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2934 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2936 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2937 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2938 i
.types
[op
].bitfield
.disp8
= 0;
2939 i
.types
[op
].bitfield
.disp16
= 0;
2940 i
.types
[op
].bitfield
.disp32
= 0;
2941 i
.types
[op
].bitfield
.disp32s
= 0;
2942 i
.types
[op
].bitfield
.disp64
= 0;
2945 /* We only support 64bit displacement on constants. */
2946 i
.types
[op
].bitfield
.disp64
= 0;
2951 match_template (void)
2953 /* Points to template once we've found it. */
2955 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
2956 unsigned int found_reverse_match
;
2957 i386_opcode_modifier suffix_check
;
2958 i386_operand_type operand_types
[MAX_OPERANDS
];
2959 int addr_prefix_disp
;
2961 i386_cpu_flags overlap
;
2963 #if MAX_OPERANDS != 4
2964 # error "MAX_OPERANDS must be 4."
2967 found_reverse_match
= 0;
2968 addr_prefix_disp
= -1;
2970 memset (&suffix_check
, 0, sizeof (suffix_check
));
2971 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2972 suffix_check
.no_bsuf
= 1;
2973 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2974 suffix_check
.no_wsuf
= 1;
2975 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
2976 suffix_check
.no_ssuf
= 1;
2977 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2978 suffix_check
.no_lsuf
= 1;
2979 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2980 suffix_check
.no_qsuf
= 1;
2981 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
2982 suffix_check
.no_xsuf
= 1;
2984 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2986 addr_prefix_disp
= -1;
2988 /* Must have right number of operands. */
2989 if (i
.operands
!= t
->operands
)
2992 /* Check the suffix, except for some instructions in intel mode. */
2993 if (((t
->opcode_modifier
.no_bsuf
& suffix_check
.no_bsuf
)
2994 || (t
->opcode_modifier
.no_wsuf
& suffix_check
.no_wsuf
)
2995 || (t
->opcode_modifier
.no_lsuf
& suffix_check
.no_lsuf
)
2996 || (t
->opcode_modifier
.no_ssuf
& suffix_check
.no_ssuf
)
2997 || (t
->opcode_modifier
.no_qsuf
& suffix_check
.no_qsuf
)
2998 || (t
->opcode_modifier
.no_xsuf
& suffix_check
.no_xsuf
))
2999 && !(intel_syntax
&& t
->opcode_modifier
.ignoresize
))
3002 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3003 operand_types
[j
] = t
->operand_types
[j
];
3005 /* In general, don't allow 64-bit operands in 32-bit mode. */
3006 if (i
.suffix
== QWORD_MNEM_SUFFIX
3007 && flag_code
!= CODE_64BIT
3009 ? (!t
->opcode_modifier
.ignoresize
3010 && !intel_float_operand (t
->name
))
3011 : intel_float_operand (t
->name
) != 2)
3012 && ((!operand_types
[0].bitfield
.regmmx
3013 && !operand_types
[0].bitfield
.regxmm
)
3014 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3015 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
))
3016 && (t
->base_opcode
!= 0x0fc7
3017 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3020 /* Do not verify operands when there are none. */
3023 overlap
= cpu_flags_and (t
->cpu_flags
, cpu_arch_flags_not
);
3026 if (!UINTS_ALL_ZERO (overlap
))
3028 /* We've found a match; break out of loop. */
3033 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3034 into Disp32/Disp16/Disp32 operand. */
3035 if (i
.prefix
[ADDR_PREFIX
] != 0)
3037 /* There should be only one Disp operand. */
3041 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3043 if (operand_types
[j
].bitfield
.disp16
)
3045 addr_prefix_disp
= j
;
3046 operand_types
[j
].bitfield
.disp32
= 1;
3047 operand_types
[j
].bitfield
.disp16
= 0;
3053 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3055 if (operand_types
[j
].bitfield
.disp32
)
3057 addr_prefix_disp
= j
;
3058 operand_types
[j
].bitfield
.disp32
= 0;
3059 operand_types
[j
].bitfield
.disp16
= 1;
3065 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3067 if (operand_types
[j
].bitfield
.disp64
)
3069 addr_prefix_disp
= j
;
3070 operand_types
[j
].bitfield
.disp64
= 0;
3071 operand_types
[j
].bitfield
.disp32
= 1;
3079 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3080 switch (t
->operands
)
3083 if (!operand_type_match (overlap0
, i
.types
[0]))
3087 /* xchg %eax, %eax is a special case. It is an aliase for nop
3088 only in 32bit mode and we can use opcode 0x90. In 64bit
3089 mode, we can't use 0x90 for xchg %eax, %eax since it should
3090 zero-extend %eax to %rax. */
3091 if (flag_code
== CODE_64BIT
3092 && t
->base_opcode
== 0x90
3093 && UINTS_EQUAL (i
.types
[0], acc32
)
3094 && UINTS_EQUAL (i
.types
[1], acc32
))
3098 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3099 if (!operand_type_match (overlap0
, i
.types
[0])
3100 || !operand_type_match (overlap1
, i
.types
[1])
3101 /* monitor in SSE3 is a very special case. The first
3102 register and the second register may have different
3103 sizes. The same applies to crc32 in SSE4.2. It is
3104 also true for invlpga, vmload, vmrun and vmsave in
3106 || !((t
->base_opcode
== 0x0f01
3107 && (t
->extension_opcode
== 0xc8
3108 || t
->extension_opcode
== 0xd8
3109 || t
->extension_opcode
== 0xda
3110 || t
->extension_opcode
== 0xdb
3111 || t
->extension_opcode
== 0xdf))
3112 || t
->base_opcode
== 0xf20f38f1
3113 || operand_type_register_match (overlap0
, i
.types
[0],
3115 overlap1
, i
.types
[1],
3118 /* Check if other direction is valid ... */
3119 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3122 /* Try reversing direction of operands. */
3123 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3124 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3125 if (!operand_type_match (overlap0
, i
.types
[0])
3126 || !operand_type_match (overlap1
, i
.types
[1])
3127 || !operand_type_register_match (overlap0
, i
.types
[0],
3129 overlap1
, i
.types
[1],
3132 /* Does not match either direction. */
3135 /* found_reverse_match holds which of D or FloatDR
3137 if (t
->opcode_modifier
.d
)
3138 found_reverse_match
= Opcode_D
;
3139 else if (t
->opcode_modifier
.floatd
)
3140 found_reverse_match
= Opcode_FloatD
;
3142 found_reverse_match
= 0;
3143 if (t
->opcode_modifier
.floatr
)
3144 found_reverse_match
|= Opcode_FloatR
;
3148 /* Found a forward 2 operand match here. */
3149 switch (t
->operands
)
3152 overlap3
= operand_type_and (i
.types
[3],
3155 overlap2
= operand_type_and (i
.types
[2],
3160 switch (t
->operands
)
3163 if (!operand_type_match (overlap3
, i
.types
[3])
3164 || !operand_type_register_match (overlap2
,
3172 /* Here we make use of the fact that there are no
3173 reverse match 3 operand instructions, and all 3
3174 operand instructions only need to be checked for
3175 register consistency between operands 2 and 3. */
3176 if (!operand_type_match (overlap2
, i
.types
[2])
3177 || !operand_type_register_match (overlap1
,
3187 /* Found either forward/reverse 2, 3 or 4 operand match here:
3188 slip through to break. */
3190 if (!UINTS_ALL_ZERO (overlap
))
3192 found_reverse_match
= 0;
3195 /* We've found a match; break out of loop. */
3199 if (t
== current_templates
->end
)
3201 /* We found no match. */
3202 as_bad (_("suffix or operands invalid for `%s'"),
3203 current_templates
->start
->name
);
3207 if (!quiet_warnings
)
3210 && (i
.types
[0].bitfield
.jumpabsolute
3211 != operand_types
[0].bitfield
.jumpabsolute
))
3213 as_warn (_("indirect %s without `*'"), t
->name
);
3216 if (t
->opcode_modifier
.isprefix
3217 && t
->opcode_modifier
.ignoresize
)
3219 /* Warn them that a data or address size prefix doesn't
3220 affect assembly of the next line of code. */
3221 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3225 /* Copy the template we found. */
3228 if (addr_prefix_disp
!= -1)
3229 i
.tm
.operand_types
[addr_prefix_disp
]
3230 = operand_types
[addr_prefix_disp
];
3232 if (found_reverse_match
)
3234 /* If we found a reverse match we must alter the opcode
3235 direction bit. found_reverse_match holds bits to change
3236 (different for int & float insns). */
3238 i
.tm
.base_opcode
^= found_reverse_match
;
3240 i
.tm
.operand_types
[0] = operand_types
[1];
3241 i
.tm
.operand_types
[1] = operand_types
[0];
3250 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3251 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3253 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3255 as_bad (_("`%s' operand %d must use `%%es' segment"),
3260 /* There's only ever one segment override allowed per instruction.
3261 This instruction possibly has a legal segment override on the
3262 second operand, so copy the segment to where non-string
3263 instructions store it, allowing common code. */
3264 i
.seg
[0] = i
.seg
[1];
3266 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3268 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3270 as_bad (_("`%s' operand %d must use `%%es' segment"),
3280 process_suffix (void)
3282 /* If matched instruction specifies an explicit instruction mnemonic
3284 if (i
.tm
.opcode_modifier
.size16
)
3285 i
.suffix
= WORD_MNEM_SUFFIX
;
3286 else if (i
.tm
.opcode_modifier
.size32
)
3287 i
.suffix
= LONG_MNEM_SUFFIX
;
3288 else if (i
.tm
.opcode_modifier
.size64
)
3289 i
.suffix
= QWORD_MNEM_SUFFIX
;
3290 else if (i
.reg_operands
)
3292 /* If there's no instruction mnemonic suffix we try to invent one
3293 based on register operands. */
3296 /* We take i.suffix from the last register operand specified,
3297 Destination register type is more significant than source
3298 register type. crc32 in SSE4.2 prefers source register
3300 if (i
.tm
.base_opcode
== 0xf20f38f1)
3302 if (i
.types
[0].bitfield
.reg16
)
3303 i
.suffix
= WORD_MNEM_SUFFIX
;
3304 else if (i
.types
[0].bitfield
.reg32
)
3305 i
.suffix
= LONG_MNEM_SUFFIX
;
3306 else if (i
.types
[0].bitfield
.reg64
)
3307 i
.suffix
= QWORD_MNEM_SUFFIX
;
3309 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3311 if (i
.types
[0].bitfield
.reg8
)
3312 i
.suffix
= BYTE_MNEM_SUFFIX
;
3319 if (i
.tm
.base_opcode
== 0xf20f38f1
3320 || i
.tm
.base_opcode
== 0xf20f38f0)
3322 /* We have to know the operand size for crc32. */
3323 as_bad (_("ambiguous memory operand size for `%s`"),
3328 for (op
= i
.operands
; --op
>= 0;)
3329 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3331 if (i
.types
[op
].bitfield
.reg8
)
3333 i
.suffix
= BYTE_MNEM_SUFFIX
;
3336 else if (i
.types
[op
].bitfield
.reg16
)
3338 i
.suffix
= WORD_MNEM_SUFFIX
;
3341 else if (i
.types
[op
].bitfield
.reg32
)
3343 i
.suffix
= LONG_MNEM_SUFFIX
;
3346 else if (i
.types
[op
].bitfield
.reg64
)
3348 i
.suffix
= QWORD_MNEM_SUFFIX
;
3354 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3356 if (!check_byte_reg ())
3359 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3361 if (!check_long_reg ())
3364 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3366 if (!check_qword_reg ())
3369 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3371 if (!check_word_reg ())
3374 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
3375 /* Do nothing if the instruction is going to ignore the prefix. */
3380 else if (i
.tm
.opcode_modifier
.defaultsize
3382 /* exclude fldenv/frstor/fsave/fstenv */
3383 && i
.tm
.opcode_modifier
.no_ssuf
)
3385 i
.suffix
= stackop_size
;
3387 else if (intel_syntax
3389 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
3390 || i
.tm
.opcode_modifier
.jumpbyte
3391 || i
.tm
.opcode_modifier
.jumpintersegment
3392 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
3393 && i
.tm
.extension_opcode
<= 3)))
3398 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3400 i
.suffix
= QWORD_MNEM_SUFFIX
;
3404 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3405 i
.suffix
= LONG_MNEM_SUFFIX
;
3408 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3409 i
.suffix
= WORD_MNEM_SUFFIX
;
3418 if (i
.tm
.opcode_modifier
.w
)
3420 as_bad (_("no instruction mnemonic suffix given and "
3421 "no register operands; can't size instruction"));
3427 unsigned int suffixes
;
3429 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
3430 if (!i
.tm
.opcode_modifier
.no_wsuf
)
3432 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3434 if (!i
.tm
.opcode_modifier
.no_lsuf
)
3436 if (!i
.tm
.opcode_modifier
.no_ssuf
)
3438 if (!i
.tm
.opcode_modifier
.no_qsuf
)
3441 /* There are more than suffix matches. */
3442 if (i
.tm
.opcode_modifier
.w
3443 || ((suffixes
& (suffixes
- 1))
3444 && !i
.tm
.opcode_modifier
.defaultsize
3445 && !i
.tm
.opcode_modifier
.ignoresize
))
3447 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3453 /* Change the opcode based on the operand size given by i.suffix;
3454 We don't need to change things for byte insns. */
3456 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
3458 /* It's not a byte, select word/dword operation. */
3459 if (i
.tm
.opcode_modifier
.w
)
3461 if (i
.tm
.opcode_modifier
.shortform
)
3462 i
.tm
.base_opcode
|= 8;
3464 i
.tm
.base_opcode
|= 1;
3467 /* Now select between word & dword operations via the operand
3468 size prefix, except for instructions that will ignore this
3470 if (i
.tm
.base_opcode
== 0x0f01
3471 && (i
.tm
.extension_opcode
== 0xc8
3472 || i
.tm
.extension_opcode
== 0xd8
3473 || i
.tm
.extension_opcode
== 0xda
3474 || i
.tm
.extension_opcode
== 0xdb
3475 || i
.tm
.extension_opcode
== 0xdf))
3477 /* monitor in SSE3 is a very special case. The default size
3478 of AX is the size of mode. The address size override
3479 prefix will change the size of AX. It is also true for
3480 invlpga, vmload, vmrun and vmsave in SVME. */
3481 if ((flag_code
== CODE_32BIT
3482 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
3483 || (flag_code
!= CODE_32BIT
3484 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
3485 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3488 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3489 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3490 && !i
.tm
.opcode_modifier
.ignoresize
3491 && !i
.tm
.opcode_modifier
.floatmf
3492 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3493 || (flag_code
== CODE_64BIT
3494 && i
.tm
.opcode_modifier
.jumpbyte
)))
3496 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3498 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
3499 prefix
= ADDR_PREFIX_OPCODE
;
3501 if (!add_prefix (prefix
))
3505 /* Set mode64 for an operand. */
3506 if (i
.suffix
== QWORD_MNEM_SUFFIX
3507 && flag_code
== CODE_64BIT
3508 && !i
.tm
.opcode_modifier
.norex64
)
3510 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3511 need rex64. cmpxchg8b is also a special case. */
3512 if (! (i
.operands
== 2
3513 && i
.tm
.base_opcode
== 0x90
3514 && i
.tm
.extension_opcode
== None
3515 && UINTS_EQUAL (i
.types
[0], acc64
)
3516 && UINTS_EQUAL (i
.types
[1], acc64
))
3517 && ! (i
.operands
== 1
3518 && i
.tm
.base_opcode
== 0xfc7
3519 && i
.tm
.extension_opcode
== 1
3520 && !operand_type_check (i
.types
[0], reg
)
3521 && operand_type_check (i
.types
[0], anymem
)))
3525 /* Size floating point instruction. */
3526 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3527 if (i
.tm
.opcode_modifier
.floatmf
)
3528 i
.tm
.base_opcode
^= 4;
3535 check_byte_reg (void)
3539 for (op
= i
.operands
; --op
>= 0;)
3541 /* If this is an eight bit register, it's OK. If it's the 16 or
3542 32 bit version of an eight bit register, we will just use the
3543 low portion, and that's OK too. */
3544 if (i
.types
[op
].bitfield
.reg8
)
3547 /* movzx, movsx, pextrb and pinsrb should not generate this
3550 && (i
.tm
.base_opcode
== 0xfb7
3551 || i
.tm
.base_opcode
== 0xfb6
3552 || i
.tm
.base_opcode
== 0x63
3553 || i
.tm
.base_opcode
== 0xfbe
3554 || i
.tm
.base_opcode
== 0xfbf
3555 || i
.tm
.base_opcode
== 0x660f3a14
3556 || i
.tm
.base_opcode
== 0x660f3a20))
3559 /* crc32 doesn't generate this warning. */
3560 if (i
.tm
.base_opcode
== 0xf20f38f0)
3563 if ((i
.types
[op
].bitfield
.reg16
3564 || i
.types
[op
].bitfield
.reg32
3565 || i
.types
[op
].bitfield
.reg64
)
3566 && i
.op
[op
].regs
->reg_num
< 4)
3568 /* Prohibit these changes in the 64bit mode, since the
3569 lowering is more complicated. */
3570 if (flag_code
== CODE_64BIT
3571 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3573 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3574 register_prefix
, i
.op
[op
].regs
->reg_name
,
3578 #if REGISTER_WARNINGS
3580 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3581 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3583 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
3584 ? REGNAM_AL
- REGNAM_AX
3585 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3587 i
.op
[op
].regs
->reg_name
,
3592 /* Any other register is bad. */
3593 if (i
.types
[op
].bitfield
.reg16
3594 || i
.types
[op
].bitfield
.reg32
3595 || i
.types
[op
].bitfield
.reg64
3596 || i
.types
[op
].bitfield
.regmmx
3597 || i
.types
[op
].bitfield
.regxmm
3598 || i
.types
[op
].bitfield
.sreg2
3599 || i
.types
[op
].bitfield
.sreg3
3600 || i
.types
[op
].bitfield
.control
3601 || i
.types
[op
].bitfield
.debug
3602 || i
.types
[op
].bitfield
.test
3603 || i
.types
[op
].bitfield
.floatreg
3604 || i
.types
[op
].bitfield
.floatacc
)
3606 as_bad (_("`%s%s' not allowed with `%s%c'"),
3608 i
.op
[op
].regs
->reg_name
,
3618 check_long_reg (void)
3622 for (op
= i
.operands
; --op
>= 0;)
3623 /* Reject eight bit registers, except where the template requires
3624 them. (eg. movzb) */
3625 if (i
.types
[op
].bitfield
.reg8
3626 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3627 || i
.tm
.operand_types
[op
].bitfield
.reg32
3628 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3630 as_bad (_("`%s%s' not allowed with `%s%c'"),
3632 i
.op
[op
].regs
->reg_name
,
3637 /* Warn if the e prefix on a general reg is missing. */
3638 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3639 && i
.types
[op
].bitfield
.reg16
3640 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3641 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3643 /* Prohibit these changes in the 64bit mode, since the
3644 lowering is more complicated. */
3645 if (flag_code
== CODE_64BIT
)
3647 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3648 register_prefix
, i
.op
[op
].regs
->reg_name
,
3652 #if REGISTER_WARNINGS
3654 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3656 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3658 i
.op
[op
].regs
->reg_name
,
3662 /* Warn if the r prefix on a general reg is missing. */
3663 else if (i
.types
[op
].bitfield
.reg64
3664 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3665 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3668 && i
.tm
.base_opcode
== 0xf30f2d
3669 && !i
.types
[0].bitfield
.regxmm
)
3671 /* cvtss2si converts DWORD memory to Reg64. We want
3673 i
.suffix
= QWORD_MNEM_SUFFIX
;
3677 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3678 register_prefix
, i
.op
[op
].regs
->reg_name
,
3687 check_qword_reg (void)
3691 for (op
= i
.operands
; --op
>= 0; )
3692 /* Reject eight bit registers, except where the template requires
3693 them. (eg. movzb) */
3694 if (i
.types
[op
].bitfield
.reg8
3695 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3696 || i
.tm
.operand_types
[op
].bitfield
.reg32
3697 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3699 as_bad (_("`%s%s' not allowed with `%s%c'"),
3701 i
.op
[op
].regs
->reg_name
,
3706 /* Warn if the e prefix on a general reg is missing. */
3707 else if ((i
.types
[op
].bitfield
.reg16
3708 || i
.types
[op
].bitfield
.reg32
)
3709 && (i
.tm
.operand_types
[op
].bitfield
.reg32
3710 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3712 /* Prohibit these changes in the 64bit mode, since the
3713 lowering is more complicated. */
3715 && i
.tm
.base_opcode
== 0xf20f2d
3716 && !i
.types
[0].bitfield
.regxmm
)
3718 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3720 i
.suffix
= LONG_MNEM_SUFFIX
;
3724 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3725 register_prefix
, i
.op
[op
].regs
->reg_name
,
3734 check_word_reg (void)
3737 for (op
= i
.operands
; --op
>= 0;)
3738 /* Reject eight bit registers, except where the template requires
3739 them. (eg. movzb) */
3740 if (i
.types
[op
].bitfield
.reg8
3741 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3742 || i
.tm
.operand_types
[op
].bitfield
.reg32
3743 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3745 as_bad (_("`%s%s' not allowed with `%s%c'"),
3747 i
.op
[op
].regs
->reg_name
,
3752 /* Warn if the e prefix on a general reg is present. */
3753 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3754 && i
.types
[op
].bitfield
.reg32
3755 && (i
.tm
.operand_types
[op
].bitfield
.reg16
3756 || i
.tm
.operand_types
[op
].bitfield
.acc
))
3758 /* Prohibit these changes in the 64bit mode, since the
3759 lowering is more complicated. */
3760 if (flag_code
== CODE_64BIT
)
3762 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3763 register_prefix
, i
.op
[op
].regs
->reg_name
,
3768 #if REGISTER_WARNINGS
3769 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3771 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3773 i
.op
[op
].regs
->reg_name
,
3781 update_imm (unsigned int j
)
3783 i386_operand_type overlap
;
3785 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3786 if ((overlap
.bitfield
.imm8
3787 || overlap
.bitfield
.imm8s
3788 || overlap
.bitfield
.imm16
3789 || overlap
.bitfield
.imm32
3790 || overlap
.bitfield
.imm32s
3791 || overlap
.bitfield
.imm64
)
3792 && !UINTS_EQUAL (overlap
, imm8
)
3793 && !UINTS_EQUAL (overlap
, imm8s
)
3794 && !UINTS_EQUAL (overlap
, imm16
)
3795 && !UINTS_EQUAL (overlap
, imm32
)
3796 && !UINTS_EQUAL (overlap
, imm32s
)
3797 && !UINTS_EQUAL (overlap
, imm64
))
3801 i386_operand_type temp
;
3804 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3806 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
3807 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
3809 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3810 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
3811 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3813 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
3814 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
3817 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
3820 else if (UINTS_EQUAL (overlap
, imm16_32_32s
)
3821 || UINTS_EQUAL (overlap
, imm16_32
)
3822 || UINTS_EQUAL (overlap
, imm16_32s
))
3824 UINTS_CLEAR (overlap
);
3825 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3826 overlap
.bitfield
.imm16
= 1;
3828 overlap
.bitfield
.imm32s
= 1;
3830 if (!UINTS_EQUAL (overlap
, imm8
)
3831 && !UINTS_EQUAL (overlap
, imm8s
)
3832 && !UINTS_EQUAL (overlap
, imm16
)
3833 && !UINTS_EQUAL (overlap
, imm32
)
3834 && !UINTS_EQUAL (overlap
, imm32s
)
3835 && !UINTS_EQUAL (overlap
, imm64
))
3837 as_bad (_("no instruction mnemonic suffix given; "
3838 "can't determine immediate size"));
3842 i
.types
[j
] = overlap
;
3852 for (j
= 0; j
< 2; j
++)
3853 if (update_imm (j
) == 0)
3856 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
3857 assert (operand_type_check (i
.types
[2], imm
) == 0);
3863 process_operands (void)
3865 /* Default segment register this instruction will use for memory
3866 accesses. 0 means unknown. This is only for optimizing out
3867 unnecessary segment overrides. */
3868 const seg_entry
*default_seg
= 0;
3870 /* The imul $imm, %reg instruction is converted into
3871 imul $imm, %reg, %reg, and the clr %reg instruction
3872 is converted into xor %reg, %reg. */
3873 if (i
.tm
.opcode_modifier
.regkludge
)
3875 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
3877 /* The first operand in instruction blendvpd, blendvps and
3878 pblendvb in SSE4.1 is implicit and must be xmm0. */
3879 assert (i
.operands
== 3
3880 && i
.reg_operands
>= 2
3881 && UINTS_EQUAL (i
.types
[0], regxmm
));
3882 if (i
.op
[0].regs
->reg_num
!= 0)
3885 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3886 i
.tm
.name
, register_prefix
);
3888 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3889 i
.tm
.name
, register_prefix
);
3894 i
.types
[0] = i
.types
[1];
3895 i
.types
[1] = i
.types
[2];
3899 /* We need to adjust fields in i.tm since they are used by
3900 build_modrm_byte. */
3901 i
.tm
.operand_types
[0] = i
.tm
.operand_types
[1];
3902 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[2];
3907 unsigned int first_reg_op
;
3909 if (operand_type_check (i
.types
[0], reg
))
3913 /* Pretend we saw the extra register operand. */
3914 assert (i
.reg_operands
== 1
3915 && i
.op
[first_reg_op
+ 1].regs
== 0);
3916 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3917 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3923 if (i
.tm
.opcode_modifier
.shortform
)
3925 if (i
.types
[0].bitfield
.sreg2
3926 || i
.types
[0].bitfield
.sreg3
)
3928 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3929 && i
.op
[0].regs
->reg_num
== 1)
3931 as_bad (_("you can't `pop %%cs'"));
3934 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3935 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3940 /* The register or float register operand is in operand 0 or 1. */
3943 if (i
.types
[0].bitfield
.floatreg
3944 || operand_type_check (i
.types
[0], reg
))
3948 /* Register goes in low 3 bits of opcode. */
3949 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3950 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3952 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3954 /* Warn about some common errors, but press on regardless.
3955 The first case can be generated by gcc (<= 2.8.1). */
3956 if (i
.operands
== 2)
3958 /* Reversed arguments on faddp, fsubp, etc. */
3959 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
3960 register_prefix
, i
.op
[1].regs
->reg_name
,
3961 register_prefix
, i
.op
[0].regs
->reg_name
);
3965 /* Extraneous `l' suffix on fp insn. */
3966 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
3967 register_prefix
, i
.op
[0].regs
->reg_name
);
3972 else if (i
.tm
.opcode_modifier
.modrm
)
3974 /* The opcode is completed (modulo i.tm.extension_opcode which
3975 must be put into the modrm byte). Now, we make the modrm and
3976 index base bytes based on all the info we've collected. */
3978 default_seg
= build_modrm_byte ();
3980 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3984 else if (i
.tm
.opcode_modifier
.isstring
)
3986 /* For the string instructions that allow a segment override
3987 on one of their operands, the default segment is ds. */
3991 if (i
.tm
.base_opcode
== 0x8d /* lea */
3994 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3996 /* If a segment was explicitly specified, and the specified segment
3997 is not the default, use an opcode prefix to select it. If we
3998 never figured out what the default segment is, then default_seg
3999 will be zero at this point, and the specified segment prefix will
4001 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4003 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4009 static const seg_entry
*
4010 build_modrm_byte (void)
4012 const seg_entry
*default_seg
= 0;
4014 /* i.reg_operands MUST be the number of real register operands;
4015 implicit registers do not count. */
4016 if (i
.reg_operands
== 2)
4018 unsigned int source
, dest
;
4026 /* When there are 3 operands, one of them may be immediate,
4027 which may be the first or the last operand. Otherwise,
4028 the first operand must be shift count register (cl). */
4029 assert (i
.imm_operands
== 1
4030 || (i
.imm_operands
== 0
4031 && i
.types
[0].bitfield
.shiftcount
));
4032 if (operand_type_check (i
.types
[0], imm
)
4033 || i
.types
[0].bitfield
.shiftcount
)
4039 /* When there are 4 operands, the first two must be immediate
4040 operands. The source operand will be the 3rd one. */
4041 assert (i
.imm_operands
== 2
4042 && operand_type_check (i
.types
[0], imm
)
4043 && operand_type_check (i
.types
[1], imm
));
4053 /* One of the register operands will be encoded in the i.tm.reg
4054 field, the other in the combined i.tm.mode and i.tm.regmem
4055 fields. If no form of this instruction supports a memory
4056 destination operand, then we assume the source operand may
4057 sometimes be a memory operand and so we need to store the
4058 destination in the i.rm.reg field. */
4059 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4060 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4062 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4063 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4064 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4066 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4071 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4072 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4073 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4075 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4078 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4080 if (!i
.types
[0].bitfield
.control
4081 && !i
.types
[1].bitfield
.control
)
4083 i
.rex
&= ~(REX_R
| REX_B
);
4084 add_prefix (LOCK_PREFIX_OPCODE
);
4088 { /* If it's not 2 reg operands... */
4091 unsigned int fake_zero_displacement
= 0;
4094 for (op
= 0; op
< i
.operands
; op
++)
4095 if (operand_type_check (i
.types
[op
], anymem
))
4097 assert (op
< i
.operands
);
4101 if (i
.base_reg
== 0)
4104 if (!i
.disp_operands
)
4105 fake_zero_displacement
= 1;
4106 if (i
.index_reg
== 0)
4108 /* Operand is just <disp> */
4109 if (flag_code
== CODE_64BIT
)
4111 /* 64bit mode overwrites the 32bit absolute
4112 addressing by RIP relative addressing and
4113 absolute addressing is encoded by one of the
4114 redundant SIB forms. */
4115 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4116 i
.sib
.base
= NO_BASE_REGISTER
;
4117 i
.sib
.index
= NO_INDEX_REGISTER
;
4118 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4119 ? disp32s
: disp32
);
4121 else if ((flag_code
== CODE_16BIT
)
4122 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4124 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4125 i
.types
[op
] = disp16
;
4129 i
.rm
.regmem
= NO_BASE_REGISTER
;
4130 i
.types
[op
] = disp32
;
4133 else /* !i.base_reg && i.index_reg */
4135 i
.sib
.index
= i
.index_reg
->reg_num
;
4136 i
.sib
.base
= NO_BASE_REGISTER
;
4137 i
.sib
.scale
= i
.log2_scale_factor
;
4138 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4139 i
.types
[op
].bitfield
.disp8
= 0;
4140 i
.types
[op
].bitfield
.disp16
= 0;
4141 i
.types
[op
].bitfield
.disp64
= 0;
4142 if (flag_code
!= CODE_64BIT
)
4144 /* Must be 32 bit */
4145 i
.types
[op
].bitfield
.disp32
= 1;
4146 i
.types
[op
].bitfield
.disp32s
= 0;
4150 i
.types
[op
].bitfield
.disp32
= 0;
4151 i
.types
[op
].bitfield
.disp32s
= 1;
4153 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4157 /* RIP addressing for 64bit mode. */
4158 else if (UINTS_EQUAL (i
.base_reg
->reg_type
, baseindex
))
4160 i
.rm
.regmem
= NO_BASE_REGISTER
;
4161 i
.types
[op
].bitfield
.disp8
= 0;
4162 i
.types
[op
].bitfield
.disp16
= 0;
4163 i
.types
[op
].bitfield
.disp32
= 0;
4164 i
.types
[op
].bitfield
.disp32s
= 1;
4165 i
.types
[op
].bitfield
.disp64
= 0;
4166 i
.flags
[op
] |= Operand_PCrel
;
4167 if (! i
.disp_operands
)
4168 fake_zero_displacement
= 1;
4170 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
4172 switch (i
.base_reg
->reg_num
)
4175 if (i
.index_reg
== 0)
4177 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4178 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
4182 if (i
.index_reg
== 0)
4185 if (operand_type_check (i
.types
[op
], disp
) == 0)
4187 /* fake (%bp) into 0(%bp) */
4188 i
.types
[op
].bitfield
.disp8
= 1;
4189 fake_zero_displacement
= 1;
4192 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4193 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
4195 default: /* (%si) -> 4 or (%di) -> 5 */
4196 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
4198 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4200 else /* i.base_reg and 32/64 bit mode */
4202 if (flag_code
== CODE_64BIT
4203 && operand_type_check (i
.types
[op
], disp
))
4205 i386_operand_type temp
;
4207 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
4209 if (i
.prefix
[ADDR_PREFIX
] == 0)
4210 i
.types
[op
].bitfield
.disp32s
= 1;
4212 i
.types
[op
].bitfield
.disp32
= 1;
4215 i
.rm
.regmem
= i
.base_reg
->reg_num
;
4216 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
4218 i
.sib
.base
= i
.base_reg
->reg_num
;
4219 /* x86-64 ignores REX prefix bit here to avoid decoder
4221 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
4224 if (i
.disp_operands
== 0)
4226 fake_zero_displacement
= 1;
4227 i
.types
[op
].bitfield
.disp8
= 1;
4230 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
4234 i
.sib
.scale
= i
.log2_scale_factor
;
4235 if (i
.index_reg
== 0)
4237 /* <disp>(%esp) becomes two byte modrm with no index
4238 register. We've already stored the code for esp
4239 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4240 Any base register besides %esp will not use the
4241 extra modrm byte. */
4242 i
.sib
.index
= NO_INDEX_REGISTER
;
4243 #if !SCALE1_WHEN_NO_INDEX
4244 /* Another case where we force the second modrm byte. */
4245 if (i
.log2_scale_factor
)
4246 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4251 i
.sib
.index
= i
.index_reg
->reg_num
;
4252 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4253 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4258 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4259 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
4262 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
4265 if (fake_zero_displacement
)
4267 /* Fakes a zero displacement assuming that i.types[op]
4268 holds the correct displacement size. */
4271 assert (i
.op
[op
].disps
== 0);
4272 exp
= &disp_expressions
[i
.disp_operands
++];
4273 i
.op
[op
].disps
= exp
;
4274 exp
->X_op
= O_constant
;
4275 exp
->X_add_number
= 0;
4276 exp
->X_add_symbol
= (symbolS
*) 0;
4277 exp
->X_op_symbol
= (symbolS
*) 0;
4281 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4282 (if any) based on i.tm.extension_opcode. Again, we must be
4283 careful to make sure that segment/control/debug/test/MMX
4284 registers are coded into the i.rm.reg field. */
4289 for (op
= 0; op
< i
.operands
; op
++)
4290 if (i
.types
[op
].bitfield
.reg8
4291 || i
.types
[op
].bitfield
.reg16
4292 || i
.types
[op
].bitfield
.reg32
4293 || i
.types
[op
].bitfield
.reg64
4294 || i
.types
[op
].bitfield
.regmmx
4295 || i
.types
[op
].bitfield
.regxmm
4296 || i
.types
[op
].bitfield
.sreg2
4297 || i
.types
[op
].bitfield
.sreg3
4298 || i
.types
[op
].bitfield
.control
4299 || i
.types
[op
].bitfield
.debug
4300 || i
.types
[op
].bitfield
.test
)
4302 assert (op
< i
.operands
);
4304 /* If there is an extension opcode to put here, the register
4305 number must be put into the regmem field. */
4306 if (i
.tm
.extension_opcode
!= None
)
4308 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
4309 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4314 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
4315 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4319 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4320 must set it to 3 to indicate this is a register operand
4321 in the regmem field. */
4322 if (!i
.mem_operands
)
4326 /* Fill in i.rm.reg field with extension opcode (if any). */
4327 if (i
.tm
.extension_opcode
!= None
)
4328 i
.rm
.reg
= i
.tm
.extension_opcode
;
4334 output_branch (void)
4339 relax_substateT subtype
;
4344 if (flag_code
== CODE_16BIT
)
4348 if (i
.prefix
[DATA_PREFIX
] != 0)
4354 /* Pentium4 branch hints. */
4355 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4356 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4361 if (i
.prefix
[REX_PREFIX
] != 0)
4367 if (i
.prefixes
!= 0 && !intel_syntax
)
4368 as_warn (_("skipping prefixes on this instruction"));
4370 /* It's always a symbol; End frag & setup for relax.
4371 Make sure there is enough room in this frag for the largest
4372 instruction we may generate in md_convert_frag. This is 2
4373 bytes for the opcode and room for the prefix and largest
4375 frag_grow (prefix
+ 2 + 4);
4376 /* Prefix and 1 opcode byte go in fr_fix. */
4377 p
= frag_more (prefix
+ 1);
4378 if (i
.prefix
[DATA_PREFIX
] != 0)
4379 *p
++ = DATA_PREFIX_OPCODE
;
4380 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
4381 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
4382 *p
++ = i
.prefix
[SEG_PREFIX
];
4383 if (i
.prefix
[REX_PREFIX
] != 0)
4384 *p
++ = i
.prefix
[REX_PREFIX
];
4385 *p
= i
.tm
.base_opcode
;
4387 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
4388 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
4389 else if (cpu_arch_flags
.bitfield
.cpui386
)
4390 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
4392 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
4395 sym
= i
.op
[0].disps
->X_add_symbol
;
4396 off
= i
.op
[0].disps
->X_add_number
;
4398 if (i
.op
[0].disps
->X_op
!= O_constant
4399 && i
.op
[0].disps
->X_op
!= O_symbol
)
4401 /* Handle complex expressions. */
4402 sym
= make_expr_symbol (i
.op
[0].disps
);
4406 /* 1 possible extra opcode + 4 byte displacement go in var part.
4407 Pass reloc in fr_var. */
4408 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
4418 if (i
.tm
.opcode_modifier
.jumpbyte
)
4420 /* This is a loop or jecxz type instruction. */
4422 if (i
.prefix
[ADDR_PREFIX
] != 0)
4424 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
4427 /* Pentium4 branch hints. */
4428 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
4429 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
4431 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
4440 if (flag_code
== CODE_16BIT
)
4443 if (i
.prefix
[DATA_PREFIX
] != 0)
4445 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
4455 if (i
.prefix
[REX_PREFIX
] != 0)
4457 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
4461 if (i
.prefixes
!= 0 && !intel_syntax
)
4462 as_warn (_("skipping prefixes on this instruction"));
4464 p
= frag_more (1 + size
);
4465 *p
++ = i
.tm
.base_opcode
;
4467 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4468 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
4470 /* All jumps handled here are signed, but don't use a signed limit
4471 check for 32 and 16 bit jumps as we want to allow wrap around at
4472 4G and 64k respectively. */
4474 fixP
->fx_signed
= 1;
4478 output_interseg_jump (void)
4486 if (flag_code
== CODE_16BIT
)
4490 if (i
.prefix
[DATA_PREFIX
] != 0)
4496 if (i
.prefix
[REX_PREFIX
] != 0)
4506 if (i
.prefixes
!= 0 && !intel_syntax
)
4507 as_warn (_("skipping prefixes on this instruction"));
4509 /* 1 opcode; 2 segment; offset */
4510 p
= frag_more (prefix
+ 1 + 2 + size
);
4512 if (i
.prefix
[DATA_PREFIX
] != 0)
4513 *p
++ = DATA_PREFIX_OPCODE
;
4515 if (i
.prefix
[REX_PREFIX
] != 0)
4516 *p
++ = i
.prefix
[REX_PREFIX
];
4518 *p
++ = i
.tm
.base_opcode
;
4519 if (i
.op
[1].imms
->X_op
== O_constant
)
4521 offsetT n
= i
.op
[1].imms
->X_add_number
;
4524 && !fits_in_unsigned_word (n
)
4525 && !fits_in_signed_word (n
))
4527 as_bad (_("16-bit jump out of range"));
4530 md_number_to_chars (p
, n
, size
);
4533 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4534 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
4535 if (i
.op
[0].imms
->X_op
!= O_constant
)
4536 as_bad (_("can't handle non absolute segment in `%s'"),
4538 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4544 fragS
*insn_start_frag
;
4545 offsetT insn_start_off
;
4547 /* Tie dwarf2 debug info to the address at the start of the insn.
4548 We can't do this after the insn has been output as the current
4549 frag may have been closed off. eg. by frag_var. */
4550 dwarf2_emit_insn (0);
4552 insn_start_frag
= frag_now
;
4553 insn_start_off
= frag_now_fix ();
4556 if (i
.tm
.opcode_modifier
.jump
)
4558 else if (i
.tm
.opcode_modifier
.jumpbyte
4559 || i
.tm
.opcode_modifier
.jumpdword
)
4561 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
4562 output_interseg_jump ();
4565 /* Output normal instructions here. */
4568 unsigned int prefix
;
4571 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
4572 SSE4 instructions have 3 bytes. We may use one more higher
4573 byte to specify a prefix the instruction requires. Exclude
4574 instructions which are in both SSE4.2 and ABM. */
4575 opc_3b
= (i
.tm
.cpu_flags
.bitfield
.cpussse3
4576 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4577 || (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4578 && !i
.tm
.cpu_flags
.bitfield
.cpuabm
));
4581 if (i
.tm
.base_opcode
& 0xff000000)
4583 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
4587 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
4589 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
4590 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
4593 if (prefix
!= REPE_PREFIX_OPCODE
4594 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
4595 add_prefix (prefix
);
4598 add_prefix (prefix
);
4601 /* The prefix bytes. */
4603 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
4609 md_number_to_chars (p
, (valueT
) *q
, 1);
4613 /* Now the opcode; be careful about word order here! */
4614 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
4616 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
4623 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
4628 /* Put out high byte first: can't use md_number_to_chars! */
4629 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
4630 *p
= i
.tm
.base_opcode
& 0xff;
4633 /* Now the modrm byte and sib byte (if present). */
4634 if (i
.tm
.opcode_modifier
.modrm
)
4637 md_number_to_chars (p
,
4638 (valueT
) (i
.rm
.regmem
<< 0
4642 /* If i.rm.regmem == ESP (4)
4643 && i.rm.mode != (Register mode)
4645 ==> need second modrm byte. */
4646 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
4648 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
4651 md_number_to_chars (p
,
4652 (valueT
) (i
.sib
.base
<< 0
4654 | i
.sib
.scale
<< 6),
4659 if (i
.disp_operands
)
4660 output_disp (insn_start_frag
, insn_start_off
);
4663 output_imm (insn_start_frag
, insn_start_off
);
4669 pi ("" /*line*/, &i
);
4671 #endif /* DEBUG386 */
4674 /* Return the size of the displacement operand N. */
4677 disp_size (unsigned int n
)
4680 if (i
.types
[n
].bitfield
.disp64
)
4682 else if (i
.types
[n
].bitfield
.disp8
)
4684 else if (i
.types
[n
].bitfield
.disp16
)
4689 /* Return the size of the immediate operand N. */
4692 imm_size (unsigned int n
)
4695 if (i
.types
[n
].bitfield
.imm64
)
4697 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
4699 else if (i
.types
[n
].bitfield
.imm16
)
4705 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4710 for (n
= 0; n
< i
.operands
; n
++)
4712 if (operand_type_check (i
.types
[n
], disp
))
4714 if (i
.op
[n
].disps
->X_op
== O_constant
)
4716 int size
= disp_size (n
);
4719 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4721 p
= frag_more (size
);
4722 md_number_to_chars (p
, val
, size
);
4726 enum bfd_reloc_code_real reloc_type
;
4727 int size
= disp_size (n
);
4728 int sign
= i
.types
[n
].bitfield
.disp32s
;
4729 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4731 /* We can't have 8 bit displacement here. */
4732 assert (!i
.types
[n
].bitfield
.disp8
);
4734 /* The PC relative address is computed relative
4735 to the instruction boundary, so in case immediate
4736 fields follows, we need to adjust the value. */
4737 if (pcrel
&& i
.imm_operands
)
4742 for (n1
= 0; n1
< i
.operands
; n1
++)
4743 if (operand_type_check (i
.types
[n1
], imm
))
4745 /* Only one immediate is allowed for PC
4746 relative address. */
4749 i
.op
[n
].disps
->X_add_number
-= sz
;
4751 /* We should find the immediate. */
4755 p
= frag_more (size
);
4756 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4758 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4759 && (((reloc_type
== BFD_RELOC_32
4760 || reloc_type
== BFD_RELOC_X86_64_32S
4761 || (reloc_type
== BFD_RELOC_64
4763 && (i
.op
[n
].disps
->X_op
== O_symbol
4764 || (i
.op
[n
].disps
->X_op
== O_add
4765 && ((symbol_get_value_expression
4766 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4768 || reloc_type
== BFD_RELOC_32_PCREL
))
4772 if (insn_start_frag
== frag_now
)
4773 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4778 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4779 for (fr
= insn_start_frag
->fr_next
;
4780 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4782 add
+= p
- frag_now
->fr_literal
;
4787 reloc_type
= BFD_RELOC_386_GOTPC
;
4788 i
.op
[n
].imms
->X_add_number
+= add
;
4790 else if (reloc_type
== BFD_RELOC_64
)
4791 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4793 /* Don't do the adjustment for x86-64, as there
4794 the pcrel addressing is relative to the _next_
4795 insn, and that is taken care of in other code. */
4796 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4798 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4799 i
.op
[n
].disps
, pcrel
, reloc_type
);
4806 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4811 for (n
= 0; n
< i
.operands
; n
++)
4813 if (operand_type_check (i
.types
[n
], imm
))
4815 if (i
.op
[n
].imms
->X_op
== O_constant
)
4817 int size
= imm_size (n
);
4820 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4822 p
= frag_more (size
);
4823 md_number_to_chars (p
, val
, size
);
4827 /* Not absolute_section.
4828 Need a 32-bit fixup (don't support 8bit
4829 non-absolute imms). Try to support other
4831 enum bfd_reloc_code_real reloc_type
;
4832 int size
= imm_size (n
);
4835 if (i
.types
[n
].bitfield
.imm32s
4836 && (i
.suffix
== QWORD_MNEM_SUFFIX
4837 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
4842 p
= frag_more (size
);
4843 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4845 /* This is tough to explain. We end up with this one if we
4846 * have operands that look like
4847 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4848 * obtain the absolute address of the GOT, and it is strongly
4849 * preferable from a performance point of view to avoid using
4850 * a runtime relocation for this. The actual sequence of
4851 * instructions often look something like:
4856 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4858 * The call and pop essentially return the absolute address
4859 * of the label .L66 and store it in %ebx. The linker itself
4860 * will ultimately change the first operand of the addl so
4861 * that %ebx points to the GOT, but to keep things simple, the
4862 * .o file must have this operand set so that it generates not
4863 * the absolute address of .L66, but the absolute address of
4864 * itself. This allows the linker itself simply treat a GOTPC
4865 * relocation as asking for a pcrel offset to the GOT to be
4866 * added in, and the addend of the relocation is stored in the
4867 * operand field for the instruction itself.
4869 * Our job here is to fix the operand so that it would add
4870 * the correct offset so that %ebx would point to itself. The
4871 * thing that is tricky is that .-.L66 will point to the
4872 * beginning of the instruction, so we need to further modify
4873 * the operand so that it will point to itself. There are
4874 * other cases where you have something like:
4876 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4878 * and here no correction would be required. Internally in
4879 * the assembler we treat operands of this form as not being
4880 * pcrel since the '.' is explicitly mentioned, and I wonder
4881 * whether it would simplify matters to do it this way. Who
4882 * knows. In earlier versions of the PIC patches, the
4883 * pcrel_adjust field was used to store the correction, but
4884 * since the expression is not pcrel, I felt it would be
4885 * confusing to do it this way. */
4887 if ((reloc_type
== BFD_RELOC_32
4888 || reloc_type
== BFD_RELOC_X86_64_32S
4889 || reloc_type
== BFD_RELOC_64
)
4891 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4892 && (i
.op
[n
].imms
->X_op
== O_symbol
4893 || (i
.op
[n
].imms
->X_op
== O_add
4894 && ((symbol_get_value_expression
4895 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4900 if (insn_start_frag
== frag_now
)
4901 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4906 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4907 for (fr
= insn_start_frag
->fr_next
;
4908 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4910 add
+= p
- frag_now
->fr_literal
;
4914 reloc_type
= BFD_RELOC_386_GOTPC
;
4916 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4918 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4919 i
.op
[n
].imms
->X_add_number
+= add
;
4921 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4922 i
.op
[n
].imms
, 0, reloc_type
);
4928 /* x86_cons_fix_new is called via the expression parsing code when a
4929 reloc is needed. We use this hook to get the correct .got reloc. */
4930 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4931 static int cons_sign
= -1;
4934 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4937 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4939 got_reloc
= NO_RELOC
;
4942 if (exp
->X_op
== O_secrel
)
4944 exp
->X_op
= O_symbol
;
4945 r
= BFD_RELOC_32_SECREL
;
4949 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4952 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4953 # define lex_got(reloc, adjust, types) NULL
4955 /* Parse operands of the form
4956 <symbol>@GOTOFF+<nnn>
4957 and similar .plt or .got references.
4959 If we find one, set up the correct relocation in RELOC and copy the
4960 input string, minus the `@GOTOFF' into a malloc'd buffer for
4961 parsing by the calling routine. Return this buffer, and if ADJUST
4962 is non-null set it to the length of the string we removed from the
4963 input line. Otherwise return NULL. */
4965 lex_got (enum bfd_reloc_code_real
*reloc
,
4967 i386_operand_type
*types
)
4969 /* Some of the relocations depend on the size of what field is to
4970 be relocated. But in our callers i386_immediate and i386_displacement
4971 we don't yet know the operand size (this will be set by insn
4972 matching). Hence we record the word32 relocation here,
4973 and adjust the reloc according to the real size in reloc(). */
4974 static const struct {
4976 const enum bfd_reloc_code_real rel
[2];
4977 const i386_operand_type types64
;
4980 BFD_RELOC_X86_64_PLTOFF64
},
4981 OPERAND_TYPE_IMM64
},
4982 { "PLT", { BFD_RELOC_386_PLT32
,
4983 BFD_RELOC_X86_64_PLT32
},
4984 OPERAND_TYPE_IMM32_32S_DISP32
},
4986 BFD_RELOC_X86_64_GOTPLT64
},
4987 OPERAND_TYPE_IMM64_DISP64
},
4988 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4989 BFD_RELOC_X86_64_GOTOFF64
},
4990 OPERAND_TYPE_IMM64_DISP64
},
4992 BFD_RELOC_X86_64_GOTPCREL
},
4993 OPERAND_TYPE_IMM32_32S_DISP32
},
4994 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4995 BFD_RELOC_X86_64_TLSGD
},
4996 OPERAND_TYPE_IMM32_32S_DISP32
},
4997 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4999 OPERAND_TYPE_NONE
},
5001 BFD_RELOC_X86_64_TLSLD
},
5002 OPERAND_TYPE_IMM32_32S_DISP32
},
5003 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5004 BFD_RELOC_X86_64_GOTTPOFF
},
5005 OPERAND_TYPE_IMM32_32S_DISP32
},
5006 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5007 BFD_RELOC_X86_64_TPOFF32
},
5008 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5009 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5011 OPERAND_TYPE_NONE
},
5012 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5013 BFD_RELOC_X86_64_DTPOFF32
},
5015 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5016 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5018 OPERAND_TYPE_NONE
},
5019 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5021 OPERAND_TYPE_NONE
},
5022 { "GOT", { BFD_RELOC_386_GOT32
,
5023 BFD_RELOC_X86_64_GOT32
},
5024 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5025 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5026 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5027 OPERAND_TYPE_IMM32_32S_DISP32
},
5028 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5029 BFD_RELOC_X86_64_TLSDESC_CALL
},
5030 OPERAND_TYPE_IMM32_32S_DISP32
},
5038 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5039 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5042 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
5046 len
= strlen (gotrel
[j
].str
);
5047 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5049 if (gotrel
[j
].rel
[object_64bit
] != 0)
5052 char *tmpbuf
, *past_reloc
;
5054 *reloc
= gotrel
[j
].rel
[object_64bit
];
5060 if (flag_code
!= CODE_64BIT
)
5062 types
->bitfield
.imm32
= 1;
5063 types
->bitfield
.disp32
= 1;
5066 *types
= gotrel
[j
].types64
;
5069 if (GOT_symbol
== NULL
)
5070 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5072 /* The length of the first part of our input line. */
5073 first
= cp
- input_line_pointer
;
5075 /* The second part goes from after the reloc token until
5076 (and including) an end_of_line char or comma. */
5077 past_reloc
= cp
+ 1 + len
;
5079 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5081 second
= cp
+ 1 - past_reloc
;
5083 /* Allocate and copy string. The trailing NUL shouldn't
5084 be necessary, but be safe. */
5085 tmpbuf
= xmalloc (first
+ second
+ 2);
5086 memcpy (tmpbuf
, input_line_pointer
, first
);
5087 if (second
!= 0 && *past_reloc
!= ' ')
5088 /* Replace the relocation token with ' ', so that
5089 errors like foo@GOTOFF1 will be detected. */
5090 tmpbuf
[first
++] = ' ';
5091 memcpy (tmpbuf
+ first
, past_reloc
, second
);
5092 tmpbuf
[first
+ second
] = '\0';
5096 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5097 gotrel
[j
].str
, 1 << (5 + object_64bit
));
5102 /* Might be a symbol version string. Don't as_bad here. */
5107 x86_cons (expressionS
*exp
, int size
)
5109 if (size
== 4 || (object_64bit
&& size
== 8))
5111 /* Handle @GOTOFF and the like in an expression. */
5113 char *gotfree_input_line
;
5116 save
= input_line_pointer
;
5117 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
5118 if (gotfree_input_line
)
5119 input_line_pointer
= gotfree_input_line
;
5123 if (gotfree_input_line
)
5125 /* expression () has merrily parsed up to the end of line,
5126 or a comma - in the wrong buffer. Transfer how far
5127 input_line_pointer has moved to the right buffer. */
5128 input_line_pointer
= (save
5129 + (input_line_pointer
- gotfree_input_line
)
5131 free (gotfree_input_line
);
5132 if (exp
->X_op
== O_constant
5133 || exp
->X_op
== O_absent
5134 || exp
->X_op
== O_illegal
5135 || exp
->X_op
== O_register
5136 || exp
->X_op
== O_big
)
5138 char c
= *input_line_pointer
;
5139 *input_line_pointer
= 0;
5140 as_bad (_("missing or invalid expression `%s'"), save
);
5141 *input_line_pointer
= c
;
5150 static void signed_cons (int size
)
5152 if (flag_code
== CODE_64BIT
)
5160 pe_directive_secrel (dummy
)
5161 int dummy ATTRIBUTE_UNUSED
;
5168 if (exp
.X_op
== O_symbol
)
5169 exp
.X_op
= O_secrel
;
5171 emit_expr (&exp
, 4);
5173 while (*input_line_pointer
++ == ',');
5175 input_line_pointer
--;
5176 demand_empty_rest_of_line ();
5181 i386_immediate (char *imm_start
)
5183 char *save_input_line_pointer
;
5184 char *gotfree_input_line
;
5187 i386_operand_type types
;
5189 UINTS_SET (types
, ~0);
5191 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
5193 as_bad (_("at most %d immediate operands are allowed"),
5194 MAX_IMMEDIATE_OPERANDS
);
5198 exp
= &im_expressions
[i
.imm_operands
++];
5199 i
.op
[this_operand
].imms
= exp
;
5201 if (is_space_char (*imm_start
))
5204 save_input_line_pointer
= input_line_pointer
;
5205 input_line_pointer
= imm_start
;
5207 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5208 if (gotfree_input_line
)
5209 input_line_pointer
= gotfree_input_line
;
5211 exp_seg
= expression (exp
);
5214 if (*input_line_pointer
)
5215 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5217 input_line_pointer
= save_input_line_pointer
;
5218 if (gotfree_input_line
)
5219 free (gotfree_input_line
);
5221 if (exp
->X_op
== O_absent
5222 || exp
->X_op
== O_illegal
5223 || exp
->X_op
== O_big
5224 || (gotfree_input_line
5225 && (exp
->X_op
== O_constant
5226 || exp
->X_op
== O_register
)))
5228 as_bad (_("missing or invalid immediate expression `%s'"),
5232 else if (exp
->X_op
== O_constant
)
5234 /* Size it properly later. */
5235 i
.types
[this_operand
].bitfield
.imm64
= 1;
5236 /* If BFD64, sign extend val. */
5237 if (!use_rela_relocations
5238 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
5240 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
5242 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5243 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
5244 && exp_seg
!= absolute_section
5245 && exp_seg
!= text_section
5246 && exp_seg
!= data_section
5247 && exp_seg
!= bss_section
5248 && exp_seg
!= undefined_section
5249 && !bfd_is_com_section (exp_seg
))
5251 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5255 else if (!intel_syntax
&& exp
->X_op
== O_register
)
5257 as_bad (_("illegal immediate register operand %s"), imm_start
);
5262 /* This is an address. The size of the address will be
5263 determined later, depending on destination register,
5264 suffix, or the default for the section. */
5265 i
.types
[this_operand
].bitfield
.imm8
= 1;
5266 i
.types
[this_operand
].bitfield
.imm16
= 1;
5267 i
.types
[this_operand
].bitfield
.imm32
= 1;
5268 i
.types
[this_operand
].bitfield
.imm32s
= 1;
5269 i
.types
[this_operand
].bitfield
.imm64
= 1;
5270 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5278 i386_scale (char *scale
)
5281 char *save
= input_line_pointer
;
5283 input_line_pointer
= scale
;
5284 val
= get_absolute_expression ();
5289 i
.log2_scale_factor
= 0;
5292 i
.log2_scale_factor
= 1;
5295 i
.log2_scale_factor
= 2;
5298 i
.log2_scale_factor
= 3;
5302 char sep
= *input_line_pointer
;
5304 *input_line_pointer
= '\0';
5305 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5307 *input_line_pointer
= sep
;
5308 input_line_pointer
= save
;
5312 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
5314 as_warn (_("scale factor of %d without an index register"),
5315 1 << i
.log2_scale_factor
);
5316 #if SCALE1_WHEN_NO_INDEX
5317 i
.log2_scale_factor
= 0;
5320 scale
= input_line_pointer
;
5321 input_line_pointer
= save
;
5326 i386_displacement (char *disp_start
, char *disp_end
)
5330 char *save_input_line_pointer
;
5331 char *gotfree_input_line
;
5333 i386_operand_type bigdisp
, types
= anydisp
;
5336 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
5338 as_bad (_("at most %d displacement operands are allowed"),
5339 MAX_MEMORY_OPERANDS
);
5343 UINTS_CLEAR (bigdisp
);
5344 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
5345 || (!current_templates
->start
->opcode_modifier
.jump
5346 && !current_templates
->start
->opcode_modifier
.jumpdword
))
5348 bigdisp
.bitfield
.disp32
= 1;
5349 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5350 if (flag_code
== CODE_64BIT
)
5354 bigdisp
.bitfield
.disp32s
= 1;
5355 bigdisp
.bitfield
.disp64
= 1;
5358 else if ((flag_code
== CODE_16BIT
) ^ override
)
5360 bigdisp
.bitfield
.disp32
= 0;
5361 bigdisp
.bitfield
.disp16
= 1;
5366 /* For PC-relative branches, the width of the displacement
5367 is dependent upon data size, not address size. */
5368 override
= (i
.prefix
[DATA_PREFIX
] != 0);
5369 if (flag_code
== CODE_64BIT
)
5371 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
5372 bigdisp
.bitfield
.disp16
= 1;
5375 bigdisp
.bitfield
.disp32
= 1;
5376 bigdisp
.bitfield
.disp32s
= 1;
5382 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
5384 : LONG_MNEM_SUFFIX
));
5385 bigdisp
.bitfield
.disp32
= 1;
5386 if ((flag_code
== CODE_16BIT
) ^ override
)
5388 bigdisp
.bitfield
.disp32
= 0;
5389 bigdisp
.bitfield
.disp16
= 1;
5393 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5396 exp
= &disp_expressions
[i
.disp_operands
];
5397 i
.op
[this_operand
].disps
= exp
;
5399 save_input_line_pointer
= input_line_pointer
;
5400 input_line_pointer
= disp_start
;
5401 END_STRING_AND_SAVE (disp_end
);
5403 #ifndef GCC_ASM_O_HACK
5404 #define GCC_ASM_O_HACK 0
5407 END_STRING_AND_SAVE (disp_end
+ 1);
5408 if (i
.types
[this_operand
].bitfield
.baseIndex
5409 && displacement_string_end
[-1] == '+')
5411 /* This hack is to avoid a warning when using the "o"
5412 constraint within gcc asm statements.
5415 #define _set_tssldt_desc(n,addr,limit,type) \
5416 __asm__ __volatile__ ( \
5418 "movw %w1,2+%0\n\t" \
5420 "movb %b1,4+%0\n\t" \
5421 "movb %4,5+%0\n\t" \
5422 "movb $0,6+%0\n\t" \
5423 "movb %h1,7+%0\n\t" \
5425 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5427 This works great except that the output assembler ends
5428 up looking a bit weird if it turns out that there is
5429 no offset. You end up producing code that looks like:
5442 So here we provide the missing zero. */
5444 *displacement_string_end
= '0';
5447 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
5448 if (gotfree_input_line
)
5449 input_line_pointer
= gotfree_input_line
;
5451 exp_seg
= expression (exp
);
5454 if (*input_line_pointer
)
5455 as_bad (_("junk `%s' after expression"), input_line_pointer
);
5457 RESTORE_END_STRING (disp_end
+ 1);
5459 input_line_pointer
= save_input_line_pointer
;
5460 if (gotfree_input_line
)
5461 free (gotfree_input_line
);
5464 /* We do this to make sure that the section symbol is in
5465 the symbol table. We will ultimately change the relocation
5466 to be relative to the beginning of the section. */
5467 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
5468 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
5469 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5471 if (exp
->X_op
!= O_symbol
)
5474 if (S_IS_LOCAL (exp
->X_add_symbol
)
5475 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
5476 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
5477 exp
->X_op
= O_subtract
;
5478 exp
->X_op_symbol
= GOT_symbol
;
5479 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
5480 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
5481 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
5482 i
.reloc
[this_operand
] = BFD_RELOC_64
;
5484 i
.reloc
[this_operand
] = BFD_RELOC_32
;
5487 else if (exp
->X_op
== O_absent
5488 || exp
->X_op
== O_illegal
5489 || exp
->X_op
== O_big
5490 || (gotfree_input_line
5491 && (exp
->X_op
== O_constant
5492 || exp
->X_op
== O_register
)))
5495 as_bad (_("missing or invalid displacement expression `%s'"),
5500 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5501 else if (exp
->X_op
!= O_constant
5502 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
5503 && exp_seg
!= absolute_section
5504 && exp_seg
!= text_section
5505 && exp_seg
!= data_section
5506 && exp_seg
!= bss_section
5507 && exp_seg
!= undefined_section
5508 && !bfd_is_com_section (exp_seg
))
5510 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
5515 RESTORE_END_STRING (disp_end
);
5517 /* Check if this is a displacement only operand. */
5518 bigdisp
= i
.types
[this_operand
];
5519 bigdisp
.bitfield
.disp8
= 0;
5520 bigdisp
.bitfield
.disp16
= 0;
5521 bigdisp
.bitfield
.disp32
= 0;
5522 bigdisp
.bitfield
.disp32s
= 0;
5523 bigdisp
.bitfield
.disp64
= 0;
5524 if (UINTS_ALL_ZERO (bigdisp
))
5525 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
5531 /* Make sure the memory operand we've been dealt is valid.
5532 Return 1 on success, 0 on a failure. */
5535 i386_index_check (const char *operand_string
)
5538 #if INFER_ADDR_PREFIX
5544 if (flag_code
== CODE_64BIT
)
5547 && ((i
.prefix
[ADDR_PREFIX
] == 0
5548 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
5549 || (i
.prefix
[ADDR_PREFIX
]
5550 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
5552 || !UINTS_EQUAL (i
.base_reg
->reg_type
, baseindex
)))
5554 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
5555 || (i
.prefix
[ADDR_PREFIX
] == 0
5556 && !i
.index_reg
->reg_type
.bitfield
.reg64
)
5557 || (i
.prefix
[ADDR_PREFIX
]
5558 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
5563 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5567 && (!i
.base_reg
->reg_type
.bitfield
.reg16
5568 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
5570 && (!i
.index_reg
->reg_type
.bitfield
.reg16
5571 || !i
.index_reg
->reg_type
.bitfield
.baseindex
5573 && i
.base_reg
->reg_num
< 6
5574 && i
.index_reg
->reg_num
>= 6
5575 && i
.log2_scale_factor
== 0))))
5582 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
5584 && (!i
.index_reg
->reg_type
.bitfield
.reg32
5585 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
5591 #if INFER_ADDR_PREFIX
5592 if (i
.prefix
[ADDR_PREFIX
] == 0)
5594 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
5596 /* Change the size of any displacement too. At most one of
5597 Disp16 or Disp32 is set.
5598 FIXME. There doesn't seem to be any real need for separate
5599 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
5600 Removing them would probably clean up the code quite a lot. */
5601 if (flag_code
!= CODE_64BIT
5602 && (i
.types
[this_operand
].bitfield
.disp16
5603 || i
.types
[this_operand
].bitfield
.disp32
))
5604 i
.types
[this_operand
]
5605 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
5610 as_bad (_("`%s' is not a valid base/index expression"),
5614 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5616 flag_code_names
[flag_code
]);
5621 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
5625 i386_operand (char *operand_string
)
5629 char *op_string
= operand_string
;
5631 if (is_space_char (*op_string
))
5634 /* We check for an absolute prefix (differentiating,
5635 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
5636 if (*op_string
== ABSOLUTE_PREFIX
)
5639 if (is_space_char (*op_string
))
5641 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
5644 /* Check if operand is a register. */
5645 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
5647 i386_operand_type temp
;
5649 /* Check for a segment override by searching for ':' after a
5650 segment register. */
5652 if (is_space_char (*op_string
))
5654 if (*op_string
== ':'
5655 && (r
->reg_type
.bitfield
.sreg2
5656 || r
->reg_type
.bitfield
.sreg3
))
5661 i
.seg
[i
.mem_operands
] = &es
;
5664 i
.seg
[i
.mem_operands
] = &cs
;
5667 i
.seg
[i
.mem_operands
] = &ss
;
5670 i
.seg
[i
.mem_operands
] = &ds
;
5673 i
.seg
[i
.mem_operands
] = &fs
;
5676 i
.seg
[i
.mem_operands
] = &gs
;
5680 /* Skip the ':' and whitespace. */
5682 if (is_space_char (*op_string
))
5685 if (!is_digit_char (*op_string
)
5686 && !is_identifier_char (*op_string
)
5687 && *op_string
!= '('
5688 && *op_string
!= ABSOLUTE_PREFIX
)
5690 as_bad (_("bad memory operand `%s'"), op_string
);
5693 /* Handle case of %es:*foo. */
5694 if (*op_string
== ABSOLUTE_PREFIX
)
5697 if (is_space_char (*op_string
))
5699 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
5701 goto do_memory_reference
;
5705 as_bad (_("junk `%s' after register"), op_string
);
5709 temp
.bitfield
.baseindex
= 0;
5710 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
5712 i
.op
[this_operand
].regs
= r
;
5715 else if (*op_string
== REGISTER_PREFIX
)
5717 as_bad (_("bad register name `%s'"), op_string
);
5720 else if (*op_string
== IMMEDIATE_PREFIX
)
5723 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
5725 as_bad (_("immediate operand illegal with absolute jump"));
5728 if (!i386_immediate (op_string
))
5731 else if (is_digit_char (*op_string
)
5732 || is_identifier_char (*op_string
)
5733 || *op_string
== '(')
5735 /* This is a memory reference of some sort. */
5738 /* Start and end of displacement string expression (if found). */
5739 char *displacement_string_start
;
5740 char *displacement_string_end
;
5742 do_memory_reference
:
5743 if ((i
.mem_operands
== 1
5744 && !current_templates
->start
->opcode_modifier
.isstring
)
5745 || i
.mem_operands
== 2)
5747 as_bad (_("too many memory references for `%s'"),
5748 current_templates
->start
->name
);
5752 /* Check for base index form. We detect the base index form by
5753 looking for an ')' at the end of the operand, searching
5754 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5756 base_string
= op_string
+ strlen (op_string
);
5759 if (is_space_char (*base_string
))
5762 /* If we only have a displacement, set-up for it to be parsed later. */
5763 displacement_string_start
= op_string
;
5764 displacement_string_end
= base_string
+ 1;
5766 if (*base_string
== ')')
5769 unsigned int parens_balanced
= 1;
5770 /* We've already checked that the number of left & right ()'s are
5771 equal, so this loop will not be infinite. */
5775 if (*base_string
== ')')
5777 if (*base_string
== '(')
5780 while (parens_balanced
);
5782 temp_string
= base_string
;
5784 /* Skip past '(' and whitespace. */
5786 if (is_space_char (*base_string
))
5789 if (*base_string
== ','
5790 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5793 displacement_string_end
= temp_string
;
5795 i
.types
[this_operand
].bitfield
.baseindex
= 1;
5799 base_string
= end_op
;
5800 if (is_space_char (*base_string
))
5804 /* There may be an index reg or scale factor here. */
5805 if (*base_string
== ',')
5808 if (is_space_char (*base_string
))
5811 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5814 base_string
= end_op
;
5815 if (is_space_char (*base_string
))
5817 if (*base_string
== ',')
5820 if (is_space_char (*base_string
))
5823 else if (*base_string
!= ')')
5825 as_bad (_("expecting `,' or `)' "
5826 "after index register in `%s'"),
5831 else if (*base_string
== REGISTER_PREFIX
)
5833 as_bad (_("bad register name `%s'"), base_string
);
5837 /* Check for scale factor. */
5838 if (*base_string
!= ')')
5840 char *end_scale
= i386_scale (base_string
);
5845 base_string
= end_scale
;
5846 if (is_space_char (*base_string
))
5848 if (*base_string
!= ')')
5850 as_bad (_("expecting `)' "
5851 "after scale factor in `%s'"),
5856 else if (!i
.index_reg
)
5858 as_bad (_("expecting index register or scale factor "
5859 "after `,'; got '%c'"),
5864 else if (*base_string
!= ')')
5866 as_bad (_("expecting `,' or `)' "
5867 "after base register in `%s'"),
5872 else if (*base_string
== REGISTER_PREFIX
)
5874 as_bad (_("bad register name `%s'"), base_string
);
5879 /* If there's an expression beginning the operand, parse it,
5880 assuming displacement_string_start and
5881 displacement_string_end are meaningful. */
5882 if (displacement_string_start
!= displacement_string_end
)
5884 if (!i386_displacement (displacement_string_start
,
5885 displacement_string_end
))
5889 /* Special case for (%dx) while doing input/output op. */
5891 && UINTS_EQUAL (i
.base_reg
->reg_type
, reg16_inoutportreg
)
5893 && i
.log2_scale_factor
== 0
5894 && i
.seg
[i
.mem_operands
] == 0
5895 && !operand_type_check (i
.types
[this_operand
], disp
))
5897 UINTS_CLEAR (i
.types
[this_operand
]);
5898 i
.types
[this_operand
].bitfield
.inoutportreg
= 1;
5902 if (i386_index_check (operand_string
) == 0)
5908 /* It's not a memory operand; argh! */
5909 as_bad (_("invalid char %s beginning operand %d `%s'"),
5910 output_invalid (*op_string
),
5915 return 1; /* Normal return. */
5918 /* md_estimate_size_before_relax()
5920 Called just before relax() for rs_machine_dependent frags. The x86
5921 assembler uses these frags to handle variable size jump
5924 Any symbol that is now undefined will not become defined.
5925 Return the correct fr_subtype in the frag.
5926 Return the initial "guess for variable size of frag" to caller.
5927 The guess is actually the growth beyond the fixed part. Whatever
5928 we do to grow the fixed or variable part contributes to our
5932 md_estimate_size_before_relax (fragP
, segment
)
5936 /* We've already got fragP->fr_subtype right; all we have to do is
5937 check for un-relaxable symbols. On an ELF system, we can't relax
5938 an externally visible symbol, because it may be overridden by a
5940 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5941 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5943 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5944 || S_IS_WEAK (fragP
->fr_symbol
)))
5948 /* Symbol is undefined in this segment, or we need to keep a
5949 reloc so that weak symbols can be overridden. */
5950 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5951 enum bfd_reloc_code_real reloc_type
;
5952 unsigned char *opcode
;
5955 if (fragP
->fr_var
!= NO_RELOC
)
5956 reloc_type
= fragP
->fr_var
;
5958 reloc_type
= BFD_RELOC_16_PCREL
;
5960 reloc_type
= BFD_RELOC_32_PCREL
;
5962 old_fr_fix
= fragP
->fr_fix
;
5963 opcode
= (unsigned char *) fragP
->fr_opcode
;
5965 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5968 /* Make jmp (0xeb) a (d)word displacement jump. */
5970 fragP
->fr_fix
+= size
;
5971 fix_new (fragP
, old_fr_fix
, size
,
5973 fragP
->fr_offset
, 1,
5979 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5981 /* Negate the condition, and branch past an
5982 unconditional jump. */
5985 /* Insert an unconditional jump. */
5987 /* We added two extra opcode bytes, and have a two byte
5989 fragP
->fr_fix
+= 2 + 2;
5990 fix_new (fragP
, old_fr_fix
+ 2, 2,
5992 fragP
->fr_offset
, 1,
5999 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
6004 fixP
= fix_new (fragP
, old_fr_fix
, 1,
6006 fragP
->fr_offset
, 1,
6008 fixP
->fx_signed
= 1;
6012 /* This changes the byte-displacement jump 0x7N
6013 to the (d)word-displacement jump 0x0f,0x8N. */
6014 opcode
[1] = opcode
[0] + 0x10;
6015 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6016 /* We've added an opcode byte. */
6017 fragP
->fr_fix
+= 1 + size
;
6018 fix_new (fragP
, old_fr_fix
+ 1, size
,
6020 fragP
->fr_offset
, 1,
6025 BAD_CASE (fragP
->fr_subtype
);
6029 return fragP
->fr_fix
- old_fr_fix
;
6032 /* Guess size depending on current relax state. Initially the relax
6033 state will correspond to a short jump and we return 1, because
6034 the variable part of the frag (the branch offset) is one byte
6035 long. However, we can relax a section more than once and in that
6036 case we must either set fr_subtype back to the unrelaxed state,
6037 or return the value for the appropriate branch. */
6038 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
6041 /* Called after relax() is finished.
6043 In: Address of frag.
6044 fr_type == rs_machine_dependent.
6045 fr_subtype is what the address relaxed to.
6047 Out: Any fixSs and constants are set up.
6048 Caller will turn frag into a ".space 0". */
6051 md_convert_frag (abfd
, sec
, fragP
)
6052 bfd
*abfd ATTRIBUTE_UNUSED
;
6053 segT sec ATTRIBUTE_UNUSED
;
6056 unsigned char *opcode
;
6057 unsigned char *where_to_put_displacement
= NULL
;
6058 offsetT target_address
;
6059 offsetT opcode_address
;
6060 unsigned int extension
= 0;
6061 offsetT displacement_from_opcode_start
;
6063 opcode
= (unsigned char *) fragP
->fr_opcode
;
6065 /* Address we want to reach in file space. */
6066 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
6068 /* Address opcode resides at in file space. */
6069 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
6071 /* Displacement from opcode start to fill into instruction. */
6072 displacement_from_opcode_start
= target_address
- opcode_address
;
6074 if ((fragP
->fr_subtype
& BIG
) == 0)
6076 /* Don't have to change opcode. */
6077 extension
= 1; /* 1 opcode + 1 displacement */
6078 where_to_put_displacement
= &opcode
[1];
6082 if (no_cond_jump_promotion
6083 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
6084 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
6085 _("long jump required"));
6087 switch (fragP
->fr_subtype
)
6089 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
6090 extension
= 4; /* 1 opcode + 4 displacement */
6092 where_to_put_displacement
= &opcode
[1];
6095 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
6096 extension
= 2; /* 1 opcode + 2 displacement */
6098 where_to_put_displacement
= &opcode
[1];
6101 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
6102 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
6103 extension
= 5; /* 2 opcode + 4 displacement */
6104 opcode
[1] = opcode
[0] + 0x10;
6105 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6106 where_to_put_displacement
= &opcode
[2];
6109 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
6110 extension
= 3; /* 2 opcode + 2 displacement */
6111 opcode
[1] = opcode
[0] + 0x10;
6112 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
6113 where_to_put_displacement
= &opcode
[2];
6116 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
6121 where_to_put_displacement
= &opcode
[3];
6125 BAD_CASE (fragP
->fr_subtype
);
6130 /* If size if less then four we are sure that the operand fits,
6131 but if it's 4, then it could be that the displacement is larger
6133 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
6135 && ((addressT
) (displacement_from_opcode_start
- extension
6136 + ((addressT
) 1 << 31))
6137 > (((addressT
) 2 << 31) - 1)))
6139 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6140 _("jump target out of range"));
6141 /* Make us emit 0. */
6142 displacement_from_opcode_start
= extension
;
6144 /* Now put displacement after opcode. */
6145 md_number_to_chars ((char *) where_to_put_displacement
,
6146 (valueT
) (displacement_from_opcode_start
- extension
),
6147 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
6148 fragP
->fr_fix
+= extension
;
6151 /* Size of byte displacement jmp. */
6152 int md_short_jump_size
= 2;
6154 /* Size of dword displacement jmp. */
6155 int md_long_jump_size
= 5;
6158 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
6160 addressT from_addr
, to_addr
;
6161 fragS
*frag ATTRIBUTE_UNUSED
;
6162 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
6166 offset
= to_addr
- (from_addr
+ 2);
6167 /* Opcode for byte-disp jump. */
6168 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
6169 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
6173 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
6175 addressT from_addr
, to_addr
;
6176 fragS
*frag ATTRIBUTE_UNUSED
;
6177 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
6181 offset
= to_addr
- (from_addr
+ 5);
6182 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
6183 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
6186 /* Apply a fixup (fixS) to segment data, once it has been determined
6187 by our caller that we have all the info we need to fix it up.
6189 On the 386, immediates, displacements, and data pointers are all in
6190 the same (little-endian) format, so we don't need to care about which
6194 md_apply_fix (fixP
, valP
, seg
)
6195 /* The fix we're to put in. */
6197 /* Pointer to the value of the bits. */
6199 /* Segment fix is from. */
6200 segT seg ATTRIBUTE_UNUSED
;
6202 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6203 valueT value
= *valP
;
6205 #if !defined (TE_Mach)
6208 switch (fixP
->fx_r_type
)
6214 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6217 case BFD_RELOC_X86_64_32S
:
6218 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6221 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6224 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
6229 if (fixP
->fx_addsy
!= NULL
6230 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
6231 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
6232 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
6233 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
6234 && !use_rela_relocations
)
6236 /* This is a hack. There should be a better way to handle this.
6237 This covers for the fact that bfd_install_relocation will
6238 subtract the current location (for partial_inplace, PC relative
6239 relocations); see more below. */
6243 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
6246 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6251 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
6254 || (symbol_section_p (fixP
->fx_addsy
)
6255 && sym_seg
!= absolute_section
))
6256 && !generic_force_reloc (fixP
))
6258 /* Yes, we add the values in twice. This is because
6259 bfd_install_relocation subtracts them out again. I think
6260 bfd_install_relocation is broken, but I don't dare change
6262 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6266 #if defined (OBJ_COFF) && defined (TE_PE)
6267 /* For some reason, the PE format does not store a
6268 section address offset for a PC relative symbol. */
6269 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
6270 || S_IS_WEAK (fixP
->fx_addsy
))
6271 value
+= md_pcrel_from (fixP
);
6275 /* Fix a few things - the dynamic linker expects certain values here,
6276 and we must not disappoint it. */
6277 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6278 if (IS_ELF
&& fixP
->fx_addsy
)
6279 switch (fixP
->fx_r_type
)
6281 case BFD_RELOC_386_PLT32
:
6282 case BFD_RELOC_X86_64_PLT32
:
6283 /* Make the jump instruction point to the address of the operand. At
6284 runtime we merely add the offset to the actual PLT entry. */
6288 case BFD_RELOC_386_TLS_GD
:
6289 case BFD_RELOC_386_TLS_LDM
:
6290 case BFD_RELOC_386_TLS_IE_32
:
6291 case BFD_RELOC_386_TLS_IE
:
6292 case BFD_RELOC_386_TLS_GOTIE
:
6293 case BFD_RELOC_386_TLS_GOTDESC
:
6294 case BFD_RELOC_X86_64_TLSGD
:
6295 case BFD_RELOC_X86_64_TLSLD
:
6296 case BFD_RELOC_X86_64_GOTTPOFF
:
6297 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6298 value
= 0; /* Fully resolved at runtime. No addend. */
6300 case BFD_RELOC_386_TLS_LE
:
6301 case BFD_RELOC_386_TLS_LDO_32
:
6302 case BFD_RELOC_386_TLS_LE_32
:
6303 case BFD_RELOC_X86_64_DTPOFF32
:
6304 case BFD_RELOC_X86_64_DTPOFF64
:
6305 case BFD_RELOC_X86_64_TPOFF32
:
6306 case BFD_RELOC_X86_64_TPOFF64
:
6307 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6310 case BFD_RELOC_386_TLS_DESC_CALL
:
6311 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6312 value
= 0; /* Fully resolved at runtime. No addend. */
6313 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6317 case BFD_RELOC_386_GOT32
:
6318 case BFD_RELOC_X86_64_GOT32
:
6319 value
= 0; /* Fully resolved at runtime. No addend. */
6322 case BFD_RELOC_VTABLE_INHERIT
:
6323 case BFD_RELOC_VTABLE_ENTRY
:
6330 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6332 #endif /* !defined (TE_Mach) */
6334 /* Are we finished with this relocation now? */
6335 if (fixP
->fx_addsy
== NULL
)
6337 else if (use_rela_relocations
)
6339 fixP
->fx_no_overflow
= 1;
6340 /* Remember value for tc_gen_reloc. */
6341 fixP
->fx_addnumber
= value
;
6345 md_number_to_chars (p
, value
, fixP
->fx_size
);
6348 #define MAX_LITTLENUMS 6
6350 /* Turn the string pointed to by litP into a floating point constant
6351 of type TYPE, and emit the appropriate bytes. The number of
6352 LITTLENUMS emitted is stored in *SIZEP. An error message is
6353 returned, or NULL on OK. */
6356 md_atof (type
, litP
, sizeP
)
6362 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
6363 LITTLENUM_TYPE
*wordP
;
6385 return _("Bad call to md_atof ()");
6387 t
= atof_ieee (input_line_pointer
, type
, words
);
6389 input_line_pointer
= t
;
6391 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
6392 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6393 the bigendian 386. */
6394 for (wordP
= words
+ prec
- 1; prec
--;)
6396 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
6397 litP
+= sizeof (LITTLENUM_TYPE
);
6402 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
6405 output_invalid (int c
)
6408 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6411 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
6412 "(0x%x)", (unsigned char) c
);
6413 return output_invalid_buf
;
6416 /* REG_STRING starts *before* REGISTER_PREFIX. */
6418 static const reg_entry
*
6419 parse_real_register (char *reg_string
, char **end_op
)
6421 char *s
= reg_string
;
6423 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
6426 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6427 if (*s
== REGISTER_PREFIX
)
6430 if (is_space_char (*s
))
6434 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
6436 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
6437 return (const reg_entry
*) NULL
;
6441 /* For naked regs, make sure that we are not dealing with an identifier.
6442 This prevents confusing an identifier like `eax_var' with register
6444 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
6445 return (const reg_entry
*) NULL
;
6449 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
6451 /* Handle floating point regs, allowing spaces in the (i) part. */
6452 if (r
== i386_regtab
/* %st is first entry of table */)
6454 if (is_space_char (*s
))
6459 if (is_space_char (*s
))
6461 if (*s
>= '0' && *s
<= '7')
6465 if (is_space_char (*s
))
6470 r
= hash_find (reg_hash
, "st(0)");
6475 /* We have "%st(" then garbage. */
6476 return (const reg_entry
*) NULL
;
6481 && ((r
->reg_flags
& (RegRex64
| RegRex
))
6482 || r
->reg_type
.bitfield
.reg64
)
6483 && (!cpu_arch_flags
.bitfield
.cpulm
6484 || !UINTS_EQUAL (r
->reg_type
, control
))
6485 && flag_code
!= CODE_64BIT
)
6486 return (const reg_entry
*) NULL
;
6491 /* REG_STRING starts *before* REGISTER_PREFIX. */
6493 static const reg_entry
*
6494 parse_register (char *reg_string
, char **end_op
)
6498 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6499 r
= parse_real_register (reg_string
, end_op
);
6504 char *save
= input_line_pointer
;
6508 input_line_pointer
= reg_string
;
6509 c
= get_symbol_end ();
6510 symbolP
= symbol_find (reg_string
);
6511 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
6513 const expressionS
*e
= symbol_get_value_expression (symbolP
);
6515 know (e
->X_op
== O_register
);
6516 know (e
->X_add_number
>= 0
6517 && (valueT
) e
->X_add_number
< i386_regtab_size
);
6518 r
= i386_regtab
+ e
->X_add_number
;
6519 *end_op
= input_line_pointer
;
6521 *input_line_pointer
= c
;
6522 input_line_pointer
= save
;
6528 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
6531 char *end
= input_line_pointer
;
6534 r
= parse_register (name
, &input_line_pointer
);
6535 if (r
&& end
<= input_line_pointer
)
6537 *nextcharP
= *input_line_pointer
;
6538 *input_line_pointer
= 0;
6539 e
->X_op
= O_register
;
6540 e
->X_add_number
= r
- i386_regtab
;
6543 input_line_pointer
= end
;
6549 md_operand (expressionS
*e
)
6551 if (*input_line_pointer
== REGISTER_PREFIX
)
6554 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
6558 e
->X_op
= O_register
;
6559 e
->X_add_number
= r
- i386_regtab
;
6560 input_line_pointer
= end
;
6566 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6567 const char *md_shortopts
= "kVQ:sqn";
6569 const char *md_shortopts
= "qn";
6572 #define OPTION_32 (OPTION_MD_BASE + 0)
6573 #define OPTION_64 (OPTION_MD_BASE + 1)
6574 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
6575 #define OPTION_MARCH (OPTION_MD_BASE + 3)
6576 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
6578 struct option md_longopts
[] =
6580 {"32", no_argument
, NULL
, OPTION_32
},
6581 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6582 {"64", no_argument
, NULL
, OPTION_64
},
6584 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
6585 {"march", required_argument
, NULL
, OPTION_MARCH
},
6586 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
6587 {NULL
, no_argument
, NULL
, 0}
6589 size_t md_longopts_size
= sizeof (md_longopts
);
6592 md_parse_option (int c
, char *arg
)
6599 optimize_align_code
= 0;
6606 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6607 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6608 should be emitted or not. FIXME: Not implemented. */
6612 /* -V: SVR4 argument to print version ID. */
6614 print_version_id ();
6617 /* -k: Ignore for FreeBSD compatibility. */
6622 /* -s: On i386 Solaris, this tells the native assembler to use
6623 .stab instead of .stab.excl. We always use .stab anyhow. */
6626 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6629 const char **list
, **l
;
6631 list
= bfd_target_list ();
6632 for (l
= list
; *l
!= NULL
; l
++)
6633 if (CONST_STRNEQ (*l
, "elf64-x86-64")
6634 || strcmp (*l
, "coff-x86-64") == 0
6635 || strcmp (*l
, "pe-x86-64") == 0
6636 || strcmp (*l
, "pei-x86-64") == 0)
6638 default_arch
= "x86_64";
6642 as_fatal (_("No compiled in support for x86_64"));
6649 default_arch
= "i386";
6653 #ifdef SVR4_COMMENT_CHARS
6658 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
6660 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
6664 i386_comment_chars
= n
;
6671 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6672 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6674 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6676 cpu_arch_isa
= cpu_arch
[i
].type
;
6677 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
6678 if (!cpu_arch_tune_set
)
6680 cpu_arch_tune
= cpu_arch_isa
;
6681 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
6686 if (i
>= ARRAY_SIZE (cpu_arch
))
6687 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6692 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6693 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6695 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6697 cpu_arch_tune_set
= 1;
6698 cpu_arch_tune
= cpu_arch
[i
].type
;
6699 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
6703 if (i
>= ARRAY_SIZE (cpu_arch
))
6704 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6714 md_show_usage (stream
)
6717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6718 fprintf (stream
, _("\
6720 -V print assembler version number\n\
6723 fprintf (stream
, _("\
6724 -n Do not optimize code alignment\n\
6725 -q quieten some warnings\n"));
6726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6727 fprintf (stream
, _("\
6730 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6731 fprintf (stream
, _("\
6732 --32/--64 generate 32bit/64bit code\n"));
6734 #ifdef SVR4_COMMENT_CHARS
6735 fprintf (stream
, _("\
6736 --divide do not treat `/' as a comment character\n"));
6738 fprintf (stream
, _("\
6739 --divide ignored\n"));
6741 fprintf (stream
, _("\
6742 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6743 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6744 core, core2, k6, athlon, k8, generic32, generic64\n"));
6748 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6749 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
6751 /* Pick the target format to use. */
6754 i386_target_format (void)
6756 if (!strcmp (default_arch
, "x86_64"))
6758 set_code_flag (CODE_64BIT
);
6759 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
6761 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
6762 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
6763 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
6764 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
6765 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
6766 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
6767 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
6768 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
6769 cpu_arch_isa_flags
.bitfield
.cpummx2
= 1;
6770 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
6771 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
6773 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
6775 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
6776 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
6777 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
6778 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
6779 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
6780 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
6781 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
6782 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
6783 cpu_arch_tune_flags
.bitfield
.cpummx2
= 1;
6784 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
6785 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
6788 else if (!strcmp (default_arch
, "i386"))
6790 set_code_flag (CODE_32BIT
);
6791 if (UINTS_ALL_ZERO (cpu_arch_isa_flags
))
6793 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
6794 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
6795 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
6797 if (UINTS_ALL_ZERO (cpu_arch_tune_flags
))
6799 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
6800 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
6801 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
6805 as_fatal (_("Unknown architecture"));
6806 switch (OUTPUT_FLAVOR
)
6809 case bfd_target_coff_flavour
:
6810 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
6813 #ifdef OBJ_MAYBE_AOUT
6814 case bfd_target_aout_flavour
:
6815 return AOUT_TARGET_FORMAT
;
6817 #ifdef OBJ_MAYBE_COFF
6818 case bfd_target_coff_flavour
:
6821 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6822 case bfd_target_elf_flavour
:
6824 if (flag_code
== CODE_64BIT
)
6827 use_rela_relocations
= 1;
6829 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6838 #endif /* OBJ_MAYBE_ more than one */
6840 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6842 i386_elf_emit_arch_note (void)
6844 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6847 asection
*seg
= now_seg
;
6848 subsegT subseg
= now_subseg
;
6849 Elf_Internal_Note i_note
;
6850 Elf_External_Note e_note
;
6851 asection
*note_secp
;
6854 /* Create the .note section. */
6855 note_secp
= subseg_new (".note", 0);
6856 bfd_set_section_flags (stdoutput
,
6858 SEC_HAS_CONTENTS
| SEC_READONLY
);
6860 /* Process the arch string. */
6861 len
= strlen (cpu_arch_name
);
6863 i_note
.namesz
= len
+ 1;
6865 i_note
.type
= NT_ARCH
;
6866 p
= frag_more (sizeof (e_note
.namesz
));
6867 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6868 p
= frag_more (sizeof (e_note
.descsz
));
6869 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6870 p
= frag_more (sizeof (e_note
.type
));
6871 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6872 p
= frag_more (len
+ 1);
6873 strcpy (p
, cpu_arch_name
);
6875 frag_align (2, 0, 0);
6877 subseg_set (seg
, subseg
);
6883 md_undefined_symbol (name
)
6886 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6887 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6888 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6889 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6893 if (symbol_find (name
))
6894 as_bad (_("GOT already in symbol table"));
6895 GOT_symbol
= symbol_new (name
, undefined_section
,
6896 (valueT
) 0, &zero_address_frag
);
6903 /* Round up a section size to the appropriate boundary. */
6906 md_section_align (segment
, size
)
6907 segT segment ATTRIBUTE_UNUSED
;
6910 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6911 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6913 /* For a.out, force the section size to be aligned. If we don't do
6914 this, BFD will align it for us, but it will not write out the
6915 final bytes of the section. This may be a bug in BFD, but it is
6916 easier to fix it here since that is how the other a.out targets
6920 align
= bfd_get_section_alignment (stdoutput
, segment
);
6921 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6928 /* On the i386, PC-relative offsets are relative to the start of the
6929 next instruction. That is, the address of the offset, plus its
6930 size, since the offset is always the last part of the insn. */
6933 md_pcrel_from (fixS
*fixP
)
6935 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6941 s_bss (int ignore ATTRIBUTE_UNUSED
)
6945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6947 obj_elf_section_change_hook ();
6949 temp
= get_absolute_expression ();
6950 subseg_set (bss_section
, (subsegT
) temp
);
6951 demand_empty_rest_of_line ();
6957 i386_validate_fix (fixS
*fixp
)
6959 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6961 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6965 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6970 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6972 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6979 tc_gen_reloc (section
, fixp
)
6980 asection
*section ATTRIBUTE_UNUSED
;
6984 bfd_reloc_code_real_type code
;
6986 switch (fixp
->fx_r_type
)
6988 case BFD_RELOC_X86_64_PLT32
:
6989 case BFD_RELOC_X86_64_GOT32
:
6990 case BFD_RELOC_X86_64_GOTPCREL
:
6991 case BFD_RELOC_386_PLT32
:
6992 case BFD_RELOC_386_GOT32
:
6993 case BFD_RELOC_386_GOTOFF
:
6994 case BFD_RELOC_386_GOTPC
:
6995 case BFD_RELOC_386_TLS_GD
:
6996 case BFD_RELOC_386_TLS_LDM
:
6997 case BFD_RELOC_386_TLS_LDO_32
:
6998 case BFD_RELOC_386_TLS_IE_32
:
6999 case BFD_RELOC_386_TLS_IE
:
7000 case BFD_RELOC_386_TLS_GOTIE
:
7001 case BFD_RELOC_386_TLS_LE_32
:
7002 case BFD_RELOC_386_TLS_LE
:
7003 case BFD_RELOC_386_TLS_GOTDESC
:
7004 case BFD_RELOC_386_TLS_DESC_CALL
:
7005 case BFD_RELOC_X86_64_TLSGD
:
7006 case BFD_RELOC_X86_64_TLSLD
:
7007 case BFD_RELOC_X86_64_DTPOFF32
:
7008 case BFD_RELOC_X86_64_DTPOFF64
:
7009 case BFD_RELOC_X86_64_GOTTPOFF
:
7010 case BFD_RELOC_X86_64_TPOFF32
:
7011 case BFD_RELOC_X86_64_TPOFF64
:
7012 case BFD_RELOC_X86_64_GOTOFF64
:
7013 case BFD_RELOC_X86_64_GOTPC32
:
7014 case BFD_RELOC_X86_64_GOT64
:
7015 case BFD_RELOC_X86_64_GOTPCREL64
:
7016 case BFD_RELOC_X86_64_GOTPC64
:
7017 case BFD_RELOC_X86_64_GOTPLT64
:
7018 case BFD_RELOC_X86_64_PLTOFF64
:
7019 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7020 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7022 case BFD_RELOC_VTABLE_ENTRY
:
7023 case BFD_RELOC_VTABLE_INHERIT
:
7025 case BFD_RELOC_32_SECREL
:
7027 code
= fixp
->fx_r_type
;
7029 case BFD_RELOC_X86_64_32S
:
7030 if (!fixp
->fx_pcrel
)
7032 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7033 code
= fixp
->fx_r_type
;
7039 switch (fixp
->fx_size
)
7042 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7043 _("can not do %d byte pc-relative relocation"),
7045 code
= BFD_RELOC_32_PCREL
;
7047 case 1: code
= BFD_RELOC_8_PCREL
; break;
7048 case 2: code
= BFD_RELOC_16_PCREL
; break;
7049 case 4: code
= BFD_RELOC_32_PCREL
; break;
7051 case 8: code
= BFD_RELOC_64_PCREL
; break;
7057 switch (fixp
->fx_size
)
7060 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7061 _("can not do %d byte relocation"),
7063 code
= BFD_RELOC_32
;
7065 case 1: code
= BFD_RELOC_8
; break;
7066 case 2: code
= BFD_RELOC_16
; break;
7067 case 4: code
= BFD_RELOC_32
; break;
7069 case 8: code
= BFD_RELOC_64
; break;
7076 if ((code
== BFD_RELOC_32
7077 || code
== BFD_RELOC_32_PCREL
7078 || code
== BFD_RELOC_X86_64_32S
)
7080 && fixp
->fx_addsy
== GOT_symbol
)
7083 code
= BFD_RELOC_386_GOTPC
;
7085 code
= BFD_RELOC_X86_64_GOTPC32
;
7087 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
7089 && fixp
->fx_addsy
== GOT_symbol
)
7091 code
= BFD_RELOC_X86_64_GOTPC64
;
7094 rel
= (arelent
*) xmalloc (sizeof (arelent
));
7095 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
7096 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7098 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7100 if (!use_rela_relocations
)
7102 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7103 vtable entry to be used in the relocation's section offset. */
7104 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7105 rel
->address
= fixp
->fx_offset
;
7109 /* Use the rela in 64bit mode. */
7112 if (!fixp
->fx_pcrel
)
7113 rel
->addend
= fixp
->fx_offset
;
7117 case BFD_RELOC_X86_64_PLT32
:
7118 case BFD_RELOC_X86_64_GOT32
:
7119 case BFD_RELOC_X86_64_GOTPCREL
:
7120 case BFD_RELOC_X86_64_TLSGD
:
7121 case BFD_RELOC_X86_64_TLSLD
:
7122 case BFD_RELOC_X86_64_GOTTPOFF
:
7123 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7124 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7125 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
7128 rel
->addend
= (section
->vma
7130 + fixp
->fx_addnumber
7131 + md_pcrel_from (fixp
));
7136 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7137 if (rel
->howto
== NULL
)
7139 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7140 _("cannot represent relocation type %s"),
7141 bfd_get_reloc_code_name (code
));
7142 /* Set howto to a garbage value so that we can keep going. */
7143 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
7144 assert (rel
->howto
!= NULL
);
7151 /* Parse operands using Intel syntax. This implements a recursive descent
7152 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7155 FIXME: We do not recognize the full operand grammar defined in the MASM
7156 documentation. In particular, all the structure/union and
7157 high-level macro operands are missing.
7159 Uppercase words are terminals, lower case words are non-terminals.
7160 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7161 bars '|' denote choices. Most grammar productions are implemented in
7162 functions called 'intel_<production>'.
7164 Initial production is 'expr'.
7170 binOp & | AND | \| | OR | ^ | XOR
7172 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7174 constant digits [[ radixOverride ]]
7176 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7214 => expr expr cmpOp e04
7217 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7218 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7220 hexdigit a | b | c | d | e | f
7221 | A | B | C | D | E | F
7227 mulOp * | / | % | MOD | << | SHL | >> | SHR
7231 register specialRegister
7235 segmentRegister CS | DS | ES | FS | GS | SS
7237 specialRegister CR0 | CR2 | CR3 | CR4
7238 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7239 | TR3 | TR4 | TR5 | TR6 | TR7
7241 We simplify the grammar in obvious places (e.g., register parsing is
7242 done by calling parse_register) and eliminate immediate left recursion
7243 to implement a recursive-descent parser.
7247 expr' cmpOp e04 expr'
7298 /* Parsing structure for the intel syntax parser. Used to implement the
7299 semantic actions for the operand grammar. */
7300 struct intel_parser_s
7302 char *op_string
; /* The string being parsed. */
7303 int got_a_float
; /* Whether the operand is a float. */
7304 int op_modifier
; /* Operand modifier. */
7305 int is_mem
; /* 1 if operand is memory reference. */
7306 int in_offset
; /* >=1 if parsing operand of offset. */
7307 int in_bracket
; /* >=1 if parsing operand in brackets. */
7308 const reg_entry
*reg
; /* Last register reference found. */
7309 char *disp
; /* Displacement string being built. */
7310 char *next_operand
; /* Resume point when splitting operands. */
7313 static struct intel_parser_s intel_parser
;
7315 /* Token structure for parsing intel syntax. */
7318 int code
; /* Token code. */
7319 const reg_entry
*reg
; /* Register entry for register tokens. */
7320 char *str
; /* String representation. */
7323 static struct intel_token cur_token
, prev_token
;
7325 /* Token codes for the intel parser. Since T_SHORT is already used
7326 by COFF, undefine it first to prevent a warning. */
7345 /* Prototypes for intel parser functions. */
7346 static int intel_match_token (int);
7347 static void intel_putback_token (void);
7348 static void intel_get_token (void);
7349 static int intel_expr (void);
7350 static int intel_e04 (void);
7351 static int intel_e05 (void);
7352 static int intel_e06 (void);
7353 static int intel_e09 (void);
7354 static int intel_e10 (void);
7355 static int intel_e11 (void);
7358 i386_intel_operand (char *operand_string
, int got_a_float
)
7363 p
= intel_parser
.op_string
= xstrdup (operand_string
);
7364 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
7368 /* Initialize token holders. */
7369 cur_token
.code
= prev_token
.code
= T_NIL
;
7370 cur_token
.reg
= prev_token
.reg
= NULL
;
7371 cur_token
.str
= prev_token
.str
= NULL
;
7373 /* Initialize parser structure. */
7374 intel_parser
.got_a_float
= got_a_float
;
7375 intel_parser
.op_modifier
= 0;
7376 intel_parser
.is_mem
= 0;
7377 intel_parser
.in_offset
= 0;
7378 intel_parser
.in_bracket
= 0;
7379 intel_parser
.reg
= NULL
;
7380 intel_parser
.disp
[0] = '\0';
7381 intel_parser
.next_operand
= NULL
;
7383 /* Read the first token and start the parser. */
7385 ret
= intel_expr ();
7390 if (cur_token
.code
!= T_NIL
)
7392 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7393 current_templates
->start
->name
, cur_token
.str
);
7396 /* If we found a memory reference, hand it over to i386_displacement
7397 to fill in the rest of the operand fields. */
7398 else if (intel_parser
.is_mem
)
7400 if ((i
.mem_operands
== 1
7401 && !current_templates
->start
->opcode_modifier
.isstring
)
7402 || i
.mem_operands
== 2)
7404 as_bad (_("too many memory references for '%s'"),
7405 current_templates
->start
->name
);
7410 char *s
= intel_parser
.disp
;
7413 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
7414 /* See the comments in intel_bracket_expr. */
7415 as_warn (_("Treating `%s' as memory reference"), operand_string
);
7417 /* Add the displacement expression. */
7419 ret
= i386_displacement (s
, s
+ strlen (s
));
7422 /* Swap base and index in 16-bit memory operands like
7423 [si+bx]. Since i386_index_check is also used in AT&T
7424 mode we have to do that here. */
7427 && i
.base_reg
->reg_type
.bitfield
.reg16
7428 && i
.index_reg
->reg_type
.bitfield
.reg16
7429 && i
.base_reg
->reg_num
>= 6
7430 && i
.index_reg
->reg_num
< 6)
7432 const reg_entry
*base
= i
.index_reg
;
7434 i
.index_reg
= i
.base_reg
;
7437 ret
= i386_index_check (operand_string
);
7442 /* Constant and OFFSET expressions are handled by i386_immediate. */
7443 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
7444 || intel_parser
.reg
== NULL
)
7445 ret
= i386_immediate (intel_parser
.disp
);
7447 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
7449 if (!ret
|| !intel_parser
.next_operand
)
7451 intel_parser
.op_string
= intel_parser
.next_operand
;
7452 this_operand
= i
.operands
++;
7456 free (intel_parser
.disp
);
7461 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7465 expr' cmpOp e04 expr'
7470 /* XXX Implement the comparison operators. */
7471 return intel_e04 ();
7488 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7489 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
7491 if (cur_token
.code
== '+')
7493 else if (cur_token
.code
== '-')
7494 nregs
= NUM_ADDRESS_REGS
;
7498 strcat (intel_parser
.disp
, cur_token
.str
);
7499 intel_match_token (cur_token
.code
);
7510 int nregs
= ~NUM_ADDRESS_REGS
;
7517 if (cur_token
.code
== '&'
7518 || cur_token
.code
== '|'
7519 || cur_token
.code
== '^')
7523 str
[0] = cur_token
.code
;
7525 strcat (intel_parser
.disp
, str
);
7530 intel_match_token (cur_token
.code
);
7535 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7536 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
7547 int nregs
= ~NUM_ADDRESS_REGS
;
7554 if (cur_token
.code
== '*'
7555 || cur_token
.code
== '/'
7556 || cur_token
.code
== '%')
7560 str
[0] = cur_token
.code
;
7562 strcat (intel_parser
.disp
, str
);
7564 else if (cur_token
.code
== T_SHL
)
7565 strcat (intel_parser
.disp
, "<<");
7566 else if (cur_token
.code
== T_SHR
)
7567 strcat (intel_parser
.disp
, ">>");
7571 intel_match_token (cur_token
.code
);
7576 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7577 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
7595 int nregs
= ~NUM_ADDRESS_REGS
;
7600 /* Don't consume constants here. */
7601 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7603 /* Need to look one token ahead - if the next token
7604 is a constant, the current token is its sign. */
7607 intel_match_token (cur_token
.code
);
7608 next_code
= cur_token
.code
;
7609 intel_putback_token ();
7610 if (next_code
== T_CONST
)
7614 /* e09 OFFSET e09 */
7615 if (cur_token
.code
== T_OFFSET
)
7618 ++intel_parser
.in_offset
;
7622 else if (cur_token
.code
== T_SHORT
)
7623 intel_parser
.op_modifier
|= 1 << T_SHORT
;
7626 else if (cur_token
.code
== '+')
7627 strcat (intel_parser
.disp
, "+");
7632 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
7638 str
[0] = cur_token
.code
;
7640 strcat (intel_parser
.disp
, str
);
7647 intel_match_token (cur_token
.code
);
7655 /* e09' PTR e10 e09' */
7656 if (cur_token
.code
== T_PTR
)
7660 if (prev_token
.code
== T_BYTE
)
7661 suffix
= BYTE_MNEM_SUFFIX
;
7663 else if (prev_token
.code
== T_WORD
)
7665 if (current_templates
->start
->name
[0] == 'l'
7666 && current_templates
->start
->name
[2] == 's'
7667 && current_templates
->start
->name
[3] == 0)
7668 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7669 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
7670 suffix
= SHORT_MNEM_SUFFIX
;
7672 suffix
= WORD_MNEM_SUFFIX
;
7675 else if (prev_token
.code
== T_DWORD
)
7677 if (current_templates
->start
->name
[0] == 'l'
7678 && current_templates
->start
->name
[2] == 's'
7679 && current_templates
->start
->name
[3] == 0)
7680 suffix
= WORD_MNEM_SUFFIX
;
7681 else if (flag_code
== CODE_16BIT
7682 && (current_templates
->start
->opcode_modifier
.jump
7683 || current_templates
->start
->opcode_modifier
.jumpdword
))
7684 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7685 else if (intel_parser
.got_a_float
== 1) /* "f..." */
7686 suffix
= SHORT_MNEM_SUFFIX
;
7688 suffix
= LONG_MNEM_SUFFIX
;
7691 else if (prev_token
.code
== T_FWORD
)
7693 if (current_templates
->start
->name
[0] == 'l'
7694 && current_templates
->start
->name
[2] == 's'
7695 && current_templates
->start
->name
[3] == 0)
7696 suffix
= LONG_MNEM_SUFFIX
;
7697 else if (!intel_parser
.got_a_float
)
7699 if (flag_code
== CODE_16BIT
)
7700 add_prefix (DATA_PREFIX_OPCODE
);
7701 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7704 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7707 else if (prev_token
.code
== T_QWORD
)
7709 if (intel_parser
.got_a_float
== 1) /* "f..." */
7710 suffix
= LONG_MNEM_SUFFIX
;
7712 suffix
= QWORD_MNEM_SUFFIX
;
7715 else if (prev_token
.code
== T_TBYTE
)
7717 if (intel_parser
.got_a_float
== 1)
7718 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7720 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7723 else if (prev_token
.code
== T_XMMWORD
)
7725 /* XXX ignored for now, but accepted since gcc uses it */
7731 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7735 /* Operands for jump/call using 'ptr' notation denote absolute
7737 if (current_templates
->start
->opcode_modifier
.jump
7738 || current_templates
->start
->opcode_modifier
.jumpdword
)
7739 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7741 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7745 else if (i
.suffix
!= suffix
)
7747 as_bad (_("Conflicting operand modifiers"));
7753 /* e09' : e10 e09' */
7754 else if (cur_token
.code
== ':')
7756 if (prev_token
.code
!= T_REG
)
7758 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7759 segment/group identifier (which we don't have), using comma
7760 as the operand separator there is even less consistent, since
7761 there all branches only have a single operand. */
7762 if (this_operand
!= 0
7763 || intel_parser
.in_offset
7764 || intel_parser
.in_bracket
7765 || (!current_templates
->start
->opcode_modifier
.jump
7766 && !current_templates
->start
->opcode_modifier
.jumpdword
7767 && !current_templates
->start
->opcode_modifier
.jumpintersegment
7768 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
7769 return intel_match_token (T_NIL
);
7770 /* Remember the start of the 2nd operand and terminate 1st
7772 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7773 another expression), but it gets at least the simplest case
7774 (a plain number or symbol on the left side) right. */
7775 intel_parser
.next_operand
= intel_parser
.op_string
;
7776 *--intel_parser
.op_string
= '\0';
7777 return intel_match_token (':');
7785 intel_match_token (cur_token
.code
);
7791 --intel_parser
.in_offset
;
7794 if (NUM_ADDRESS_REGS
> nregs
)
7796 as_bad (_("Invalid operand to `OFFSET'"));
7799 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7802 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7803 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7808 intel_bracket_expr (void)
7810 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7811 const char *start
= intel_parser
.op_string
;
7814 if (i
.op
[this_operand
].regs
)
7815 return intel_match_token (T_NIL
);
7817 intel_match_token ('[');
7819 /* Mark as a memory operand only if it's not already known to be an
7820 offset expression. If it's an offset expression, we need to keep
7822 if (!intel_parser
.in_offset
)
7824 ++intel_parser
.in_bracket
;
7826 /* Operands for jump/call inside brackets denote absolute addresses. */
7827 if (current_templates
->start
->opcode_modifier
.jump
7828 || current_templates
->start
->opcode_modifier
.jumpdword
)
7829 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7831 /* Unfortunately gas always diverged from MASM in a respect that can't
7832 be easily fixed without risking to break code sequences likely to be
7833 encountered (the testsuite even check for this): MASM doesn't consider
7834 an expression inside brackets unconditionally as a memory reference.
7835 When that is e.g. a constant, an offset expression, or the sum of the
7836 two, this is still taken as a constant load. gas, however, always
7837 treated these as memory references. As a compromise, we'll try to make
7838 offset expressions inside brackets work the MASM way (since that's
7839 less likely to be found in real world code), but make constants alone
7840 continue to work the traditional gas way. In either case, issue a
7842 intel_parser
.op_modifier
&= ~was_offset
;
7845 strcat (intel_parser
.disp
, "[");
7847 /* Add a '+' to the displacement string if necessary. */
7848 if (*intel_parser
.disp
!= '\0'
7849 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7850 strcat (intel_parser
.disp
, "+");
7853 && (len
= intel_parser
.op_string
- start
- 1,
7854 intel_match_token (']')))
7856 /* Preserve brackets when the operand is an offset expression. */
7857 if (intel_parser
.in_offset
)
7858 strcat (intel_parser
.disp
, "]");
7861 --intel_parser
.in_bracket
;
7862 if (i
.base_reg
|| i
.index_reg
)
7863 intel_parser
.is_mem
= 1;
7864 if (!intel_parser
.is_mem
)
7866 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7867 /* Defer the warning until all of the operand was parsed. */
7868 intel_parser
.is_mem
= -1;
7869 else if (!quiet_warnings
)
7870 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7871 len
, start
, len
, start
);
7874 intel_parser
.op_modifier
|= was_offset
;
7891 while (cur_token
.code
== '[')
7893 if (!intel_bracket_expr ())
7918 switch (cur_token
.code
)
7922 intel_match_token ('(');
7923 strcat (intel_parser
.disp
, "(");
7925 if (intel_expr () && intel_match_token (')'))
7927 strcat (intel_parser
.disp
, ")");
7934 return intel_bracket_expr ();
7939 strcat (intel_parser
.disp
, cur_token
.str
);
7940 intel_match_token (cur_token
.code
);
7942 /* Mark as a memory operand only if it's not already known to be an
7943 offset expression. */
7944 if (!intel_parser
.in_offset
)
7945 intel_parser
.is_mem
= 1;
7952 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7954 intel_match_token (T_REG
);
7956 /* Check for segment change. */
7957 if (cur_token
.code
== ':')
7959 if (!reg
->reg_type
.bitfield
.sreg2
7960 && !reg
->reg_type
.bitfield
.sreg3
)
7962 as_bad (_("`%s' is not a valid segment register"),
7966 else if (i
.seg
[i
.mem_operands
])
7967 as_warn (_("Extra segment override ignored"));
7970 if (!intel_parser
.in_offset
)
7971 intel_parser
.is_mem
= 1;
7972 switch (reg
->reg_num
)
7975 i
.seg
[i
.mem_operands
] = &es
;
7978 i
.seg
[i
.mem_operands
] = &cs
;
7981 i
.seg
[i
.mem_operands
] = &ss
;
7984 i
.seg
[i
.mem_operands
] = &ds
;
7987 i
.seg
[i
.mem_operands
] = &fs
;
7990 i
.seg
[i
.mem_operands
] = &gs
;
7996 /* Not a segment register. Check for register scaling. */
7997 else if (cur_token
.code
== '*')
7999 if (!intel_parser
.in_bracket
)
8001 as_bad (_("Register scaling only allowed in memory operands"));
8005 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
8006 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
8007 else if (i
.index_reg
)
8008 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
8010 /* What follows must be a valid scale. */
8011 intel_match_token ('*');
8013 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8015 /* Set the scale after setting the register (otherwise,
8016 i386_scale will complain) */
8017 if (cur_token
.code
== '+' || cur_token
.code
== '-')
8019 char *str
, sign
= cur_token
.code
;
8020 intel_match_token (cur_token
.code
);
8021 if (cur_token
.code
!= T_CONST
)
8023 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8027 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8028 strcpy (str
+ 1, cur_token
.str
);
8030 if (!i386_scale (str
))
8034 else if (!i386_scale (cur_token
.str
))
8036 intel_match_token (cur_token
.code
);
8039 /* No scaling. If this is a memory operand, the register is either a
8040 base register (first occurrence) or an index register (second
8042 else if (intel_parser
.in_bracket
)
8047 else if (!i
.index_reg
)
8051 as_bad (_("Too many register references in memory operand"));
8055 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8058 /* It's neither base nor index. */
8059 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
8061 i386_operand_type temp
= reg
->reg_type
;
8062 temp
.bitfield
.baseindex
= 0;
8063 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8065 i
.op
[this_operand
].regs
= reg
;
8070 as_bad (_("Invalid use of register"));
8074 /* Since registers are not part of the displacement string (except
8075 when we're parsing offset operands), we may need to remove any
8076 preceding '+' from the displacement string. */
8077 if (*intel_parser
.disp
!= '\0'
8078 && !intel_parser
.in_offset
)
8080 char *s
= intel_parser
.disp
;
8081 s
+= strlen (s
) - 1;
8104 intel_match_token (cur_token
.code
);
8106 if (cur_token
.code
== T_PTR
)
8109 /* It must have been an identifier. */
8110 intel_putback_token ();
8111 cur_token
.code
= T_ID
;
8117 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
8121 /* The identifier represents a memory reference only if it's not
8122 preceded by an offset modifier and if it's not an equate. */
8123 symbolP
= symbol_find(cur_token
.str
);
8124 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
8125 intel_parser
.is_mem
= 1;
8133 char *save_str
, sign
= 0;
8135 /* Allow constants that start with `+' or `-'. */
8136 if (cur_token
.code
== '-' || cur_token
.code
== '+')
8138 sign
= cur_token
.code
;
8139 intel_match_token (cur_token
.code
);
8140 if (cur_token
.code
!= T_CONST
)
8142 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8148 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
8149 strcpy (save_str
+ !!sign
, cur_token
.str
);
8153 /* Get the next token to check for register scaling. */
8154 intel_match_token (cur_token
.code
);
8156 /* Check if this constant is a scaling factor for an
8158 if (cur_token
.code
== '*')
8160 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
8162 const reg_entry
*reg
= cur_token
.reg
;
8164 if (!intel_parser
.in_bracket
)
8166 as_bad (_("Register scaling only allowed "
8167 "in memory operands"));
8171 /* Disallow things like [1*si].
8172 sp and esp are invalid as index. */
8173 if (reg
->reg_type
.bitfield
.reg16
)
8174 reg
= i386_regtab
+ REGNAM_AX
+ 4;
8175 else if (i
.index_reg
)
8176 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
8178 /* The constant is followed by `* reg', so it must be
8181 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8183 /* Set the scale after setting the register (otherwise,
8184 i386_scale will complain) */
8185 if (!i386_scale (save_str
))
8187 intel_match_token (T_REG
);
8189 /* Since registers are not part of the displacement
8190 string, we may need to remove any preceding '+' from
8191 the displacement string. */
8192 if (*intel_parser
.disp
!= '\0')
8194 char *s
= intel_parser
.disp
;
8195 s
+= strlen (s
) - 1;
8205 /* The constant was not used for register scaling. Since we have
8206 already consumed the token following `*' we now need to put it
8207 back in the stream. */
8208 intel_putback_token ();
8211 /* Add the constant to the displacement string. */
8212 strcat (intel_parser
.disp
, save_str
);
8219 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
8223 /* Match the given token against cur_token. If they match, read the next
8224 token from the operand string. */
8226 intel_match_token (int code
)
8228 if (cur_token
.code
== code
)
8235 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
8240 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8242 intel_get_token (void)
8245 const reg_entry
*reg
;
8246 struct intel_token new_token
;
8248 new_token
.code
= T_NIL
;
8249 new_token
.reg
= NULL
;
8250 new_token
.str
= NULL
;
8252 /* Free the memory allocated to the previous token and move
8253 cur_token to prev_token. */
8255 free (prev_token
.str
);
8257 prev_token
= cur_token
;
8259 /* Skip whitespace. */
8260 while (is_space_char (*intel_parser
.op_string
))
8261 intel_parser
.op_string
++;
8263 /* Return an empty token if we find nothing else on the line. */
8264 if (*intel_parser
.op_string
== '\0')
8266 cur_token
= new_token
;
8270 /* The new token cannot be larger than the remainder of the operand
8272 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
8273 new_token
.str
[0] = '\0';
8275 if (strchr ("0123456789", *intel_parser
.op_string
))
8277 char *p
= new_token
.str
;
8278 char *q
= intel_parser
.op_string
;
8279 new_token
.code
= T_CONST
;
8281 /* Allow any kind of identifier char to encompass floating point and
8282 hexadecimal numbers. */
8283 while (is_identifier_char (*q
))
8287 /* Recognize special symbol names [0-9][bf]. */
8288 if (strlen (intel_parser
.op_string
) == 2
8289 && (intel_parser
.op_string
[1] == 'b'
8290 || intel_parser
.op_string
[1] == 'f'))
8291 new_token
.code
= T_ID
;
8294 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
8296 size_t len
= end_op
- intel_parser
.op_string
;
8298 new_token
.code
= T_REG
;
8299 new_token
.reg
= reg
;
8301 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
8302 new_token
.str
[len
] = '\0';
8305 else if (is_identifier_char (*intel_parser
.op_string
))
8307 char *p
= new_token
.str
;
8308 char *q
= intel_parser
.op_string
;
8310 /* A '.' or '$' followed by an identifier char is an identifier.
8311 Otherwise, it's operator '.' followed by an expression. */
8312 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
8314 new_token
.code
= '.';
8315 new_token
.str
[0] = '.';
8316 new_token
.str
[1] = '\0';
8320 while (is_identifier_char (*q
) || *q
== '@')
8324 if (strcasecmp (new_token
.str
, "NOT") == 0)
8325 new_token
.code
= '~';
8327 else if (strcasecmp (new_token
.str
, "MOD") == 0)
8328 new_token
.code
= '%';
8330 else if (strcasecmp (new_token
.str
, "AND") == 0)
8331 new_token
.code
= '&';
8333 else if (strcasecmp (new_token
.str
, "OR") == 0)
8334 new_token
.code
= '|';
8336 else if (strcasecmp (new_token
.str
, "XOR") == 0)
8337 new_token
.code
= '^';
8339 else if (strcasecmp (new_token
.str
, "SHL") == 0)
8340 new_token
.code
= T_SHL
;
8342 else if (strcasecmp (new_token
.str
, "SHR") == 0)
8343 new_token
.code
= T_SHR
;
8345 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
8346 new_token
.code
= T_BYTE
;
8348 else if (strcasecmp (new_token
.str
, "WORD") == 0)
8349 new_token
.code
= T_WORD
;
8351 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
8352 new_token
.code
= T_DWORD
;
8354 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
8355 new_token
.code
= T_FWORD
;
8357 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
8358 new_token
.code
= T_QWORD
;
8360 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
8361 /* XXX remove (gcc still uses it) */
8362 || strcasecmp (new_token
.str
, "XWORD") == 0)
8363 new_token
.code
= T_TBYTE
;
8365 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
8366 || strcasecmp (new_token
.str
, "OWORD") == 0)
8367 new_token
.code
= T_XMMWORD
;
8369 else if (strcasecmp (new_token
.str
, "PTR") == 0)
8370 new_token
.code
= T_PTR
;
8372 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
8373 new_token
.code
= T_SHORT
;
8375 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
8377 new_token
.code
= T_OFFSET
;
8379 /* ??? This is not mentioned in the MASM grammar but gcc
8380 makes use of it with -mintel-syntax. OFFSET may be
8381 followed by FLAT: */
8382 if (strncasecmp (q
, " FLAT:", 6) == 0)
8383 strcat (new_token
.str
, " FLAT:");
8386 /* ??? This is not mentioned in the MASM grammar. */
8387 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
8389 new_token
.code
= T_OFFSET
;
8391 strcat (new_token
.str
, ":");
8393 as_bad (_("`:' expected"));
8397 new_token
.code
= T_ID
;
8401 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
8403 new_token
.code
= *intel_parser
.op_string
;
8404 new_token
.str
[0] = *intel_parser
.op_string
;
8405 new_token
.str
[1] = '\0';
8408 else if (strchr ("<>", *intel_parser
.op_string
)
8409 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
8411 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
8412 new_token
.str
[0] = *intel_parser
.op_string
;
8413 new_token
.str
[1] = *intel_parser
.op_string
;
8414 new_token
.str
[2] = '\0';
8418 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
8420 intel_parser
.op_string
+= strlen (new_token
.str
);
8421 cur_token
= new_token
;
8424 /* Put cur_token back into the token stream and make cur_token point to
8427 intel_putback_token (void)
8429 if (cur_token
.code
!= T_NIL
)
8431 intel_parser
.op_string
-= strlen (cur_token
.str
);
8432 free (cur_token
.str
);
8434 cur_token
= prev_token
;
8436 /* Forget prev_token. */
8437 prev_token
.code
= T_NIL
;
8438 prev_token
.reg
= NULL
;
8439 prev_token
.str
= NULL
;
8443 tc_x86_regname_to_dw2regnum (char *regname
)
8445 unsigned int regnum
;
8446 unsigned int regnames_count
;
8447 static const char *const regnames_32
[] =
8449 "eax", "ecx", "edx", "ebx",
8450 "esp", "ebp", "esi", "edi",
8451 "eip", "eflags", NULL
,
8452 "st0", "st1", "st2", "st3",
8453 "st4", "st5", "st6", "st7",
8455 "xmm0", "xmm1", "xmm2", "xmm3",
8456 "xmm4", "xmm5", "xmm6", "xmm7",
8457 "mm0", "mm1", "mm2", "mm3",
8458 "mm4", "mm5", "mm6", "mm7",
8459 "fcw", "fsw", "mxcsr",
8460 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8463 static const char *const regnames_64
[] =
8465 "rax", "rdx", "rcx", "rbx",
8466 "rsi", "rdi", "rbp", "rsp",
8467 "r8", "r9", "r10", "r11",
8468 "r12", "r13", "r14", "r15",
8470 "xmm0", "xmm1", "xmm2", "xmm3",
8471 "xmm4", "xmm5", "xmm6", "xmm7",
8472 "xmm8", "xmm9", "xmm10", "xmm11",
8473 "xmm12", "xmm13", "xmm14", "xmm15",
8474 "st0", "st1", "st2", "st3",
8475 "st4", "st5", "st6", "st7",
8476 "mm0", "mm1", "mm2", "mm3",
8477 "mm4", "mm5", "mm6", "mm7",
8479 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
8480 "fs.base", "gs.base", NULL
, NULL
,
8482 "mxcsr", "fcw", "fsw"
8484 const char *const *regnames
;
8486 if (flag_code
== CODE_64BIT
)
8488 regnames
= regnames_64
;
8489 regnames_count
= ARRAY_SIZE (regnames_64
);
8493 regnames
= regnames_32
;
8494 regnames_count
= ARRAY_SIZE (regnames_32
);
8497 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
8498 if (regnames
[regnum
] != NULL
8499 && strcmp (regname
, regnames
[regnum
]) == 0)
8506 tc_x86_frame_initial_instructions (void)
8508 static unsigned int sp_regno
;
8511 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
8514 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
8515 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8519 i386_elf_section_type (const char *str
, size_t len
)
8521 if (flag_code
== CODE_64BIT
8522 && len
== sizeof ("unwind") - 1
8523 && strncmp (str
, "unwind", 6) == 0)
8524 return SHT_X86_64_UNWIND
;
8531 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8535 expr
.X_op
= O_secrel
;
8536 expr
.X_add_symbol
= symbol
;
8537 expr
.X_add_number
= 0;
8538 emit_expr (&expr
, size
);
8542 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8543 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8546 x86_64_section_letter (int letter
, char **ptr_msg
)
8548 if (flag_code
== CODE_64BIT
)
8551 return SHF_X86_64_LARGE
;
8553 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8556 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8561 x86_64_section_word (char *str
, size_t len
)
8563 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8564 return SHF_X86_64_LARGE
;
8570 handle_large_common (int small ATTRIBUTE_UNUSED
)
8572 if (flag_code
!= CODE_64BIT
)
8574 s_comm_internal (0, elf_common_parse
);
8575 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8579 static segT lbss_section
;
8580 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8581 asection
*saved_bss_section
= bss_section
;
8583 if (lbss_section
== NULL
)
8585 flagword applicable
;
8587 subsegT subseg
= now_subseg
;
8589 /* The .lbss section is for local .largecomm symbols. */
8590 lbss_section
= subseg_new (".lbss", 0);
8591 applicable
= bfd_applicable_section_flags (stdoutput
);
8592 bfd_set_section_flags (stdoutput
, lbss_section
,
8593 applicable
& SEC_ALLOC
);
8594 seg_info (lbss_section
)->bss
= 1;
8596 subseg_set (seg
, subseg
);
8599 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8600 bss_section
= lbss_section
;
8602 s_comm_internal (0, elf_common_parse
);
8604 elf_com_section_ptr
= saved_com_section_ptr
;
8605 bss_section
= saved_bss_section
;
8608 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */