1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
72 #define RELOC_ENUM enum bfd_reloc_code_real
74 #define RELOC_ENUM int
78 #define DEFAULT_ARCH "i386"
80 static char *default_arch
= DEFAULT_ARCH
;
82 /* 'md_assemble ()' gathers together information and puts it into a
89 const reg_entry
*regs
;
94 /* TM holds the template for the insn were currently assembling. */
97 /* SUFFIX holds the instruction mnemonic suffix if given.
98 (e.g. 'l' for 'movl') */
101 /* OPERANDS gives the number of given operands. */
102 unsigned int operands
;
104 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
105 of given register, displacement, memory operands and immediate
107 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
109 /* TYPES [i] is the type (see above #defines) which tells us how to
110 use OP[i] for the corresponding operand. */
111 unsigned int types
[MAX_OPERANDS
];
113 /* Displacement expression, immediate expression, or register for each
115 union i386_op op
[MAX_OPERANDS
];
117 /* Flags for operands. */
118 unsigned int flags
[MAX_OPERANDS
];
119 #define Operand_PCrel 1
121 /* Relocation type for operand */
122 RELOC_ENUM reloc
[MAX_OPERANDS
];
124 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
125 the base index byte below. */
126 const reg_entry
*base_reg
;
127 const reg_entry
*index_reg
;
128 unsigned int log2_scale_factor
;
130 /* SEG gives the seg_entries of this insn. They are zero unless
131 explicit segment overrides are given. */
132 const seg_entry
*seg
[2];
134 /* PREFIX holds all the given prefix opcodes (usually null).
135 PREFIXES is the number of prefix opcodes. */
136 unsigned int prefixes
;
137 unsigned char prefix
[MAX_PREFIXES
];
139 /* RM and SIB are the modrm byte and the sib byte where the
140 addressing modes of this insn are encoded. */
147 typedef struct _i386_insn i386_insn
;
149 /* List of chars besides those in app.c:symbol_chars that can start an
150 operand. Used to prevent the scrubber eating vital white-space. */
152 const char extra_symbol_chars
[] = "*%-(@";
154 const char extra_symbol_chars
[] = "*%-(";
157 /* This array holds the chars that always start a comment. If the
158 pre-processor is disabled, these aren't very useful. */
159 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
160 /* Putting '/' here makes it impossible to use the divide operator.
161 However, we need it for compatibility with SVR4 systems. */
162 const char comment_chars
[] = "#/";
163 #define PREFIX_SEPARATOR '\\'
165 const char comment_chars
[] = "#";
166 #define PREFIX_SEPARATOR '/'
169 /* This array holds the chars that only start a comment at the beginning of
170 a line. If the line seems to have the form '# 123 filename'
171 .line and .file directives will appear in the pre-processed output.
172 Note that input_file.c hand checks for '#' at the beginning of the
173 first line of the input file. This is because the compiler outputs
174 #NO_APP at the beginning of its output.
175 Also note that comments started like this one will always work if
176 '/' isn't otherwise defined. */
177 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD))
178 const char line_comment_chars
[] = "";
180 const char line_comment_chars
[] = "/";
183 const char line_separator_chars
[] = ";";
185 /* Chars that can be used to separate mant from exp in floating point
187 const char EXP_CHARS
[] = "eE";
189 /* Chars that mean this number is a floating point constant
192 const char FLT_CHARS
[] = "fFdDxX";
194 /* Tables for lexical analysis. */
195 static char mnemonic_chars
[256];
196 static char register_chars
[256];
197 static char operand_chars
[256];
198 static char identifier_chars
[256];
199 static char digit_chars
[256];
201 /* Lexical macros. */
202 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
203 #define is_operand_char(x) (operand_chars[(unsigned char) x])
204 #define is_register_char(x) (register_chars[(unsigned char) x])
205 #define is_space_char(x) ((x) == ' ')
206 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
207 #define is_digit_char(x) (digit_chars[(unsigned char) x])
209 /* All non-digit non-letter charcters that may occur in an operand. */
210 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
212 /* md_assemble() always leaves the strings it's passed unaltered. To
213 effect this we maintain a stack of saved characters that we've smashed
214 with '\0's (indicating end of strings for various sub-fields of the
215 assembler instruction). */
216 static char save_stack
[32];
217 static char *save_stack_p
;
218 #define END_STRING_AND_SAVE(s) \
219 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
220 #define RESTORE_END_STRING(s) \
221 do { *(s) = *--save_stack_p; } while (0)
223 /* The instruction we're assembling. */
226 /* Possible templates for current insn. */
227 static const templates
*current_templates
;
229 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
230 static expressionS disp_expressions
[2], im_expressions
[2];
232 /* Current operand we are working on. */
233 static int this_operand
;
235 /* We support four different modes. FLAG_CODE variable is used to distinguish
242 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* If set, conditional jumps are not automatically promoted to handle
277 larger than a byte offset. */
278 static unsigned int no_cond_jump_promotion
= 0;
280 /* Interface to relax_segment.
281 There are 3 major relax states for 386 jump insns because the
282 different types of jumps add different sizes to frags when we're
283 figuring out what sort of jump to choose to reach a given label. */
286 #define UNCOND_JUMP 0
288 #define COND_JUMP86 2
293 #define SMALL16 (SMALL|CODE16)
295 #define BIG16 (BIG|CODE16)
299 #define INLINE __inline__
305 #define ENCODE_RELAX_STATE(type, size) \
306 ((relax_substateT) (((type) << 2) | (size)))
307 #define TYPE_FROM_RELAX_STATE(s) \
309 #define DISP_SIZE_FROM_RELAX_STATE(s) \
310 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
312 /* This table is used by relax_frag to promote short jumps to long
313 ones where necessary. SMALL (short) jumps may be promoted to BIG
314 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
315 don't allow a short jump in a 32 bit code segment to be promoted to
316 a 16 bit offset jump because it's slower (requires data size
317 prefix), and doesn't work, unless the destination is in the bottom
318 64k of the code segment (The top 16 bits of eip are zeroed). */
320 const relax_typeS md_relax_table
[] =
323 1) most positive reach of this state,
324 2) most negative reach of this state,
325 3) how many bytes this mode will have in the variable part of the frag
326 4) which index into the table to try if we can't fit into this one. */
328 /* UNCOND_JUMP states. */
329 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
330 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
331 /* dword jmp adds 4 bytes to frag:
332 0 extra opcode bytes, 4 displacement bytes. */
334 /* word jmp adds 2 byte2 to frag:
335 0 extra opcode bytes, 2 displacement bytes. */
338 /* COND_JUMP states. */
339 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
340 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
341 /* dword conditionals adds 5 bytes to frag:
342 1 extra opcode byte, 4 displacement bytes. */
344 /* word conditionals add 3 bytes to frag:
345 1 extra opcode byte, 2 displacement bytes. */
348 /* COND_JUMP86 states. */
349 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
350 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
351 /* dword conditionals adds 5 bytes to frag:
352 1 extra opcode byte, 4 displacement bytes. */
354 /* word conditionals add 4 bytes to frag:
355 1 displacement byte and a 3 byte long branch insn. */
359 static const arch_entry cpu_arch
[] = {
361 {"i186", Cpu086
|Cpu186
},
362 {"i286", Cpu086
|Cpu186
|Cpu286
},
363 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
364 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
365 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
366 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
367 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
368 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
369 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
370 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
371 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
372 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
377 i386_align_code (fragP
, count
)
381 /* Various efficient no-op patterns for aligning code labels.
382 Note: Don't try to assemble the instructions in the comments.
383 0L and 0w are not legal. */
384 static const char f32_1
[] =
386 static const char f32_2
[] =
387 {0x89,0xf6}; /* movl %esi,%esi */
388 static const char f32_3
[] =
389 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
390 static const char f32_4
[] =
391 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
392 static const char f32_5
[] =
394 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
395 static const char f32_6
[] =
396 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
397 static const char f32_7
[] =
398 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
399 static const char f32_8
[] =
401 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
402 static const char f32_9
[] =
403 {0x89,0xf6, /* movl %esi,%esi */
404 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
405 static const char f32_10
[] =
406 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
407 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
408 static const char f32_11
[] =
409 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
410 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
411 static const char f32_12
[] =
412 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
413 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
414 static const char f32_13
[] =
415 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
416 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
417 static const char f32_14
[] =
418 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
419 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
420 static const char f32_15
[] =
421 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
422 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
423 static const char f16_3
[] =
424 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
425 static const char f16_4
[] =
426 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
427 static const char f16_5
[] =
429 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
430 static const char f16_6
[] =
431 {0x89,0xf6, /* mov %si,%si */
432 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
433 static const char f16_7
[] =
434 {0x8d,0x74,0x00, /* lea 0(%si),%si */
435 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
436 static const char f16_8
[] =
437 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
438 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
439 static const char *const f32_patt
[] = {
440 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
441 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
443 static const char *const f16_patt
[] = {
444 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
445 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
448 /* ??? We can't use these fillers for x86_64, since they often kills the
449 upper halves. Solve later. */
450 if (flag_code
== CODE_64BIT
)
453 if (count
> 0 && count
<= 15)
455 if (flag_code
== CODE_16BIT
)
457 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
458 f16_patt
[count
- 1], count
);
460 /* Adjust jump offset. */
461 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
464 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
465 f32_patt
[count
- 1], count
);
466 fragP
->fr_var
= count
;
470 static char *output_invalid
PARAMS ((int c
));
471 static int i386_operand
PARAMS ((char *operand_string
));
472 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
473 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
477 static void s_bss
PARAMS ((int));
480 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
482 static INLINE
unsigned int
483 mode_from_disp_size (t
)
486 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
490 fits_in_signed_byte (num
)
493 return (num
>= -128) && (num
<= 127);
497 fits_in_unsigned_byte (num
)
500 return (num
& 0xff) == num
;
504 fits_in_unsigned_word (num
)
507 return (num
& 0xffff) == num
;
511 fits_in_signed_word (num
)
514 return (-32768 <= num
) && (num
<= 32767);
517 fits_in_signed_long (num
)
518 offsetT num ATTRIBUTE_UNUSED
;
523 return (!(((offsetT
) -1 << 31) & num
)
524 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
526 } /* fits_in_signed_long() */
528 fits_in_unsigned_long (num
)
529 offsetT num ATTRIBUTE_UNUSED
;
534 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
536 } /* fits_in_unsigned_long() */
539 smallest_imm_type (num
)
542 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
543 && !(cpu_arch_flags
& (CpuUnknown
)))
545 /* This code is disabled on the 486 because all the Imm1 forms
546 in the opcode table are slower on the i486. They're the
547 versions with the implicitly specified single-position
548 displacement, which has another syntax if you really want to
551 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
553 return (fits_in_signed_byte (num
)
554 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
555 : fits_in_unsigned_byte (num
)
556 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
557 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
558 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
559 : fits_in_signed_long (num
)
560 ? (Imm32
| Imm32S
| Imm64
)
561 : fits_in_unsigned_long (num
)
567 offset_in_range (val
, size
)
575 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
576 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
577 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
579 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
584 /* If BFD64, sign extend val. */
585 if (!use_rela_relocations
)
586 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
587 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
589 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
591 char buf1
[40], buf2
[40];
593 sprint_value (buf1
, val
);
594 sprint_value (buf2
, val
& mask
);
595 as_warn (_("%s shortened to %s"), buf1
, buf2
);
600 /* Returns 0 if attempting to add a prefix where one from the same
601 class already exists, 1 if non rep/repne added, 2 if rep/repne
610 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
618 case CS_PREFIX_OPCODE
:
619 case DS_PREFIX_OPCODE
:
620 case ES_PREFIX_OPCODE
:
621 case FS_PREFIX_OPCODE
:
622 case GS_PREFIX_OPCODE
:
623 case SS_PREFIX_OPCODE
:
627 case REPNE_PREFIX_OPCODE
:
628 case REPE_PREFIX_OPCODE
:
631 case LOCK_PREFIX_OPCODE
:
639 case ADDR_PREFIX_OPCODE
:
643 case DATA_PREFIX_OPCODE
:
650 as_bad (_("same type of prefix used twice"));
655 i
.prefix
[q
] = prefix
;
660 set_code_flag (value
)
664 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
665 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
666 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
668 as_bad (_("64bit mode not supported on this CPU."));
670 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
672 as_bad (_("32bit mode not supported on this CPU."));
678 set_16bit_gcc_code_flag (new_code_flag
)
681 flag_code
= new_code_flag
;
682 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
683 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
688 set_intel_syntax (syntax_flag
)
691 /* Find out if register prefixing is specified. */
692 int ask_naked_reg
= 0;
695 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
697 char *string
= input_line_pointer
;
698 int e
= get_symbol_end ();
700 if (strcmp (string
, "prefix") == 0)
702 else if (strcmp (string
, "noprefix") == 0)
705 as_bad (_("bad argument to syntax directive."));
706 *input_line_pointer
= e
;
708 demand_empty_rest_of_line ();
710 intel_syntax
= syntax_flag
;
712 if (ask_naked_reg
== 0)
715 allow_naked_reg
= (intel_syntax
716 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
718 /* Conservative default. */
723 allow_naked_reg
= (ask_naked_reg
< 0);
728 int dummy ATTRIBUTE_UNUSED
;
732 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
734 char *string
= input_line_pointer
;
735 int e
= get_symbol_end ();
738 for (i
= 0; cpu_arch
[i
].name
; i
++)
740 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
742 cpu_arch_name
= cpu_arch
[i
].name
;
743 cpu_arch_flags
= (cpu_arch
[i
].flags
744 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
748 if (!cpu_arch
[i
].name
)
749 as_bad (_("no such architecture: `%s'"), string
);
751 *input_line_pointer
= e
;
754 as_bad (_("missing cpu architecture"));
756 no_cond_jump_promotion
= 0;
757 if (*input_line_pointer
== ','
758 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
760 char *string
= ++input_line_pointer
;
761 int e
= get_symbol_end ();
763 if (strcmp (string
, "nojumps") == 0)
764 no_cond_jump_promotion
= 1;
765 else if (strcmp (string
, "jumps") == 0)
768 as_bad (_("no such architecture modifier: `%s'"), string
);
770 *input_line_pointer
= e
;
773 demand_empty_rest_of_line ();
776 const pseudo_typeS md_pseudo_table
[] =
778 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
779 {"align", s_align_bytes
, 0},
781 {"align", s_align_ptwo
, 0},
783 {"arch", set_cpu_arch
, 0},
787 {"ffloat", float_cons
, 'f'},
788 {"dfloat", float_cons
, 'd'},
789 {"tfloat", float_cons
, 'x'},
791 {"noopt", s_ignore
, 0},
792 {"optim", s_ignore
, 0},
793 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
794 {"code16", set_code_flag
, CODE_16BIT
},
795 {"code32", set_code_flag
, CODE_32BIT
},
796 {"code64", set_code_flag
, CODE_64BIT
},
797 {"intel_syntax", set_intel_syntax
, 1},
798 {"att_syntax", set_intel_syntax
, 0},
799 {"file", dwarf2_directive_file
, 0},
800 {"loc", dwarf2_directive_loc
, 0},
804 /* For interface with expression (). */
805 extern char *input_line_pointer
;
807 /* Hash table for instruction mnemonic lookup. */
808 static struct hash_control
*op_hash
;
810 /* Hash table for register lookup. */
811 static struct hash_control
*reg_hash
;
817 if (!strcmp (default_arch
, "x86_64"))
818 return bfd_mach_x86_64
;
819 else if (!strcmp (default_arch
, "i386"))
820 return bfd_mach_i386_i386
;
822 as_fatal (_("Unknown architecture"));
829 const char *hash_err
;
831 /* Initialize op_hash hash table. */
832 op_hash
= hash_new ();
835 register const template *optab
;
836 register templates
*core_optab
;
838 /* Setup for loop. */
840 core_optab
= (templates
*) xmalloc (sizeof (templates
));
841 core_optab
->start
= optab
;
846 if (optab
->name
== NULL
847 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
849 /* different name --> ship out current template list;
850 add to hash table; & begin anew. */
851 core_optab
->end
= optab
;
852 hash_err
= hash_insert (op_hash
,
857 as_fatal (_("Internal Error: Can't hash %s: %s"),
861 if (optab
->name
== NULL
)
863 core_optab
= (templates
*) xmalloc (sizeof (templates
));
864 core_optab
->start
= optab
;
869 /* Initialize reg_hash hash table. */
870 reg_hash
= hash_new ();
872 register const reg_entry
*regtab
;
874 for (regtab
= i386_regtab
;
875 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
878 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
880 as_fatal (_("Internal Error: Can't hash %s: %s"),
886 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
891 for (c
= 0; c
< 256; c
++)
896 mnemonic_chars
[c
] = c
;
897 register_chars
[c
] = c
;
898 operand_chars
[c
] = c
;
900 else if (ISLOWER (c
))
902 mnemonic_chars
[c
] = c
;
903 register_chars
[c
] = c
;
904 operand_chars
[c
] = c
;
906 else if (ISUPPER (c
))
908 mnemonic_chars
[c
] = TOLOWER (c
);
909 register_chars
[c
] = mnemonic_chars
[c
];
910 operand_chars
[c
] = c
;
913 if (ISALPHA (c
) || ISDIGIT (c
))
914 identifier_chars
[c
] = c
;
917 identifier_chars
[c
] = c
;
918 operand_chars
[c
] = c
;
923 identifier_chars
['@'] = '@';
925 digit_chars
['-'] = '-';
926 identifier_chars
['_'] = '_';
927 identifier_chars
['.'] = '.';
929 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
930 operand_chars
[(unsigned char) *p
] = *p
;
933 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
934 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
936 record_alignment (text_section
, 2);
937 record_alignment (data_section
, 2);
938 record_alignment (bss_section
, 2);
944 i386_print_statistics (file
)
947 hash_print_statistics (file
, "i386 opcode", op_hash
);
948 hash_print_statistics (file
, "i386 register", reg_hash
);
953 /* Debugging routines for md_assemble. */
954 static void pi
PARAMS ((char *, i386_insn
*));
955 static void pte
PARAMS ((template *));
956 static void pt
PARAMS ((unsigned int));
957 static void pe
PARAMS ((expressionS
*));
958 static void ps
PARAMS ((symbolS
*));
967 fprintf (stdout
, "%s: template ", line
);
969 fprintf (stdout
, " address: base %s index %s scale %x\n",
970 x
->base_reg
? x
->base_reg
->reg_name
: "none",
971 x
->index_reg
? x
->index_reg
->reg_name
: "none",
972 x
->log2_scale_factor
);
973 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
974 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
975 fprintf (stdout
, " sib: base %x index %x scale %x\n",
976 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
977 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
978 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
979 for (i
= 0; i
< x
->operands
; i
++)
981 fprintf (stdout
, " #%d: ", i
+ 1);
983 fprintf (stdout
, "\n");
985 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
986 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
987 if (x
->types
[i
] & Imm
)
989 if (x
->types
[i
] & Disp
)
999 fprintf (stdout
, " %d operands ", t
->operands
);
1000 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1001 if (t
->extension_opcode
!= None
)
1002 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1003 if (t
->opcode_modifier
& D
)
1004 fprintf (stdout
, "D");
1005 if (t
->opcode_modifier
& W
)
1006 fprintf (stdout
, "W");
1007 fprintf (stdout
, "\n");
1008 for (i
= 0; i
< t
->operands
; i
++)
1010 fprintf (stdout
, " #%d type ", i
+ 1);
1011 pt (t
->operand_types
[i
]);
1012 fprintf (stdout
, "\n");
1020 fprintf (stdout
, " operation %d\n", e
->X_op
);
1021 fprintf (stdout
, " add_number %ld (%lx)\n",
1022 (long) e
->X_add_number
, (long) e
->X_add_number
);
1023 if (e
->X_add_symbol
)
1025 fprintf (stdout
, " add_symbol ");
1026 ps (e
->X_add_symbol
);
1027 fprintf (stdout
, "\n");
1031 fprintf (stdout
, " op_symbol ");
1032 ps (e
->X_op_symbol
);
1033 fprintf (stdout
, "\n");
1041 fprintf (stdout
, "%s type %s%s",
1043 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1044 segment_name (S_GET_SEGMENT (s
)));
1066 { BaseIndex
, "BaseIndex" },
1070 { Disp32S
, "d32s" },
1072 { InOutPortReg
, "InOutPortReg" },
1073 { ShiftCount
, "ShiftCount" },
1074 { Control
, "control reg" },
1075 { Test
, "test reg" },
1076 { Debug
, "debug reg" },
1077 { FloatReg
, "FReg" },
1078 { FloatAcc
, "FAcc" },
1082 { JumpAbsolute
, "Jump Absolute" },
1093 register struct type_name
*ty
;
1095 for (ty
= type_names
; ty
->mask
; ty
++)
1097 fprintf (stdout
, "%s, ", ty
->tname
);
1101 #endif /* DEBUG386 */
1104 tc_i386_force_relocation (fixp
)
1107 #ifdef BFD_ASSEMBLER
1108 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1109 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1114 return fixp
->fx_r_type
== 7;
1118 #ifdef BFD_ASSEMBLER
1120 static bfd_reloc_code_real_type
1121 reloc (size
, pcrel
, sign
, other
)
1125 bfd_reloc_code_real_type other
;
1127 if (other
!= NO_RELOC
)
1133 as_bad (_("There are no unsigned pc-relative relocations"));
1136 case 1: return BFD_RELOC_8_PCREL
;
1137 case 2: return BFD_RELOC_16_PCREL
;
1138 case 4: return BFD_RELOC_32_PCREL
;
1140 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1147 case 4: return BFD_RELOC_X86_64_32S
;
1152 case 1: return BFD_RELOC_8
;
1153 case 2: return BFD_RELOC_16
;
1154 case 4: return BFD_RELOC_32
;
1155 case 8: return BFD_RELOC_64
;
1157 as_bad (_("can not do %s %d byte relocation"),
1158 sign
? "signed" : "unsigned", size
);
1162 return BFD_RELOC_NONE
;
1165 /* Here we decide which fixups can be adjusted to make them relative to
1166 the beginning of the section instead of the symbol. Basically we need
1167 to make sure that the dynamic relocations are done correctly, so in
1168 some cases we force the original symbol to be used. */
1171 tc_i386_fix_adjustable (fixP
)
1174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1175 /* Prevent all adjustments to global symbols, or else dynamic
1176 linking will not work correctly. */
1177 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1178 || S_IS_WEAK (fixP
->fx_addsy
))
1181 /* adjust_reloc_syms doesn't know about the GOT. */
1182 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1183 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1184 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1185 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1186 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1187 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1188 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1189 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1194 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1195 #define BFD_RELOC_16 0
1196 #define BFD_RELOC_32 0
1197 #define BFD_RELOC_16_PCREL 0
1198 #define BFD_RELOC_32_PCREL 0
1199 #define BFD_RELOC_386_PLT32 0
1200 #define BFD_RELOC_386_GOT32 0
1201 #define BFD_RELOC_386_GOTOFF 0
1202 #define BFD_RELOC_X86_64_PLT32 0
1203 #define BFD_RELOC_X86_64_GOT32 0
1204 #define BFD_RELOC_X86_64_GOTPCREL 0
1207 static int intel_float_operand
PARAMS ((char *mnemonic
));
1210 intel_float_operand (mnemonic
)
1213 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1216 if (mnemonic
[0] == 'f')
1222 /* This is the guts of the machine-dependent assembler. LINE points to a
1223 machine dependent instruction. This function is supposed to emit
1224 the frags/bytes it assembles to. */
1230 /* Points to template once we've found it. */
1235 char mnemonic
[MAX_MNEM_SIZE
];
1237 /* Initialize globals. */
1238 memset (&i
, '\0', sizeof (i
));
1239 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1240 i
.reloc
[j
] = NO_RELOC
;
1241 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1242 memset (im_expressions
, '\0', sizeof (im_expressions
));
1243 save_stack_p
= save_stack
;
1245 /* First parse an instruction mnemonic & call i386_operand for the operands.
1246 We assume that the scrubber has arranged it so that line[0] is the valid
1247 start of a (possibly prefixed) mnemonic. */
1250 char *token_start
= l
;
1253 /* Non-zero if we found a prefix only acceptable with string insns. */
1254 const char *expecting_string_instruction
= NULL
;
1259 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1262 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1264 as_bad (_("no such instruction: `%s'"), token_start
);
1269 if (!is_space_char (*l
)
1270 && *l
!= END_OF_INSN
1271 && *l
!= PREFIX_SEPARATOR
1274 as_bad (_("invalid character %s in mnemonic"),
1275 output_invalid (*l
));
1278 if (token_start
== l
)
1280 if (*l
== PREFIX_SEPARATOR
)
1281 as_bad (_("expecting prefix; got nothing"));
1283 as_bad (_("expecting mnemonic; got nothing"));
1287 /* Look up instruction (or prefix) via hash table. */
1288 current_templates
= hash_find (op_hash
, mnemonic
);
1290 if (*l
!= END_OF_INSN
1291 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1292 && current_templates
1293 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1295 /* If we are in 16-bit mode, do not allow addr16 or data16.
1296 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1297 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1298 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1299 ^ (flag_code
== CODE_16BIT
)))
1301 as_bad (_("redundant %s prefix"),
1302 current_templates
->start
->name
);
1305 /* Add prefix, checking for repeated prefixes. */
1306 switch (add_prefix (current_templates
->start
->base_opcode
))
1311 expecting_string_instruction
= current_templates
->start
->name
;
1314 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1321 if (!current_templates
)
1323 /* See if we can get a match by trimming off a suffix. */
1326 case WORD_MNEM_SUFFIX
:
1327 case BYTE_MNEM_SUFFIX
:
1328 case QWORD_MNEM_SUFFIX
:
1329 i
.suffix
= mnem_p
[-1];
1331 current_templates
= hash_find (op_hash
, mnemonic
);
1333 case SHORT_MNEM_SUFFIX
:
1334 case LONG_MNEM_SUFFIX
:
1337 i
.suffix
= mnem_p
[-1];
1339 current_templates
= hash_find (op_hash
, mnemonic
);
1347 if (intel_float_operand (mnemonic
))
1348 i
.suffix
= SHORT_MNEM_SUFFIX
;
1350 i
.suffix
= LONG_MNEM_SUFFIX
;
1352 current_templates
= hash_find (op_hash
, mnemonic
);
1356 if (!current_templates
)
1358 as_bad (_("no such instruction: `%s'"), token_start
);
1363 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1365 /* Check for a branch hint. We allow ",pt" and ",pn" for
1366 predict taken and predict not taken respectively.
1367 I'm not sure that branch hints actually do anything on loop
1368 and jcxz insns (JumpByte) for current Pentium4 chips. They
1369 may work in the future and it doesn't hurt to accept them
1371 if (l
[0] == ',' && l
[1] == 'p')
1375 if (! add_prefix (DS_PREFIX_OPCODE
))
1379 else if (l
[2] == 'n')
1381 if (! add_prefix (CS_PREFIX_OPCODE
))
1387 /* Any other comma loses. */
1390 as_bad (_("invalid character %s in mnemonic"),
1391 output_invalid (*l
));
1395 /* Check if instruction is supported on specified architecture. */
1396 if (cpu_arch_flags
!= 0)
1398 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1399 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1401 as_warn (_("`%s' is not supported on `%s'"),
1402 current_templates
->start
->name
, cpu_arch_name
);
1404 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1406 as_warn (_("use .code16 to ensure correct addressing mode"));
1410 /* Check for rep/repne without a string instruction. */
1411 if (expecting_string_instruction
1412 && !(current_templates
->start
->opcode_modifier
& IsString
))
1414 as_bad (_("expecting string instruction after `%s'"),
1415 expecting_string_instruction
);
1419 /* There may be operands to parse. */
1420 if (*l
!= END_OF_INSN
)
1422 /* 1 if operand is pending after ','. */
1423 unsigned int expecting_operand
= 0;
1425 /* Non-zero if operand parens not balanced. */
1426 unsigned int paren_not_balanced
;
1430 /* Skip optional white space before operand. */
1431 if (is_space_char (*l
))
1433 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1435 as_bad (_("invalid character %s before operand %d"),
1436 output_invalid (*l
),
1440 token_start
= l
; /* after white space */
1441 paren_not_balanced
= 0;
1442 while (paren_not_balanced
|| *l
!= ',')
1444 if (*l
== END_OF_INSN
)
1446 if (paren_not_balanced
)
1449 as_bad (_("unbalanced parenthesis in operand %d."),
1452 as_bad (_("unbalanced brackets in operand %d."),
1457 break; /* we are done */
1459 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1461 as_bad (_("invalid character %s in operand %d"),
1462 output_invalid (*l
),
1469 ++paren_not_balanced
;
1471 --paren_not_balanced
;
1476 ++paren_not_balanced
;
1478 --paren_not_balanced
;
1482 if (l
!= token_start
)
1483 { /* Yes, we've read in another operand. */
1484 unsigned int operand_ok
;
1485 this_operand
= i
.operands
++;
1486 if (i
.operands
> MAX_OPERANDS
)
1488 as_bad (_("spurious operands; (%d operands/instruction max)"),
1492 /* Now parse operand adding info to 'i' as we go along. */
1493 END_STRING_AND_SAVE (l
);
1497 i386_intel_operand (token_start
,
1498 intel_float_operand (mnemonic
));
1500 operand_ok
= i386_operand (token_start
);
1502 RESTORE_END_STRING (l
);
1508 if (expecting_operand
)
1510 expecting_operand_after_comma
:
1511 as_bad (_("expecting operand after ','; got nothing"));
1516 as_bad (_("expecting operand before ','; got nothing"));
1521 /* Now *l must be either ',' or END_OF_INSN. */
1524 if (*++l
== END_OF_INSN
)
1526 /* Just skip it, if it's \n complain. */
1527 goto expecting_operand_after_comma
;
1529 expecting_operand
= 1;
1532 while (*l
!= END_OF_INSN
);
1536 /* Now we've parsed the mnemonic into a set of templates, and have the
1539 Next, we find a template that matches the given insn,
1540 making sure the overlap of the given operands types is consistent
1541 with the template operand types. */
1543 #define MATCH(overlap, given, template) \
1544 ((overlap & ~JumpAbsolute) \
1545 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1547 /* If given types r0 and r1 are registers they must be of the same type
1548 unless the expected operand type register overlap is null.
1549 Note that Acc in a template matches every size of reg. */
1550 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1551 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1552 ((g0) & Reg) == ((g1) & Reg) || \
1553 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1556 register unsigned int overlap0
, overlap1
;
1557 unsigned int overlap2
;
1558 unsigned int found_reverse_match
;
1561 /* All intel opcodes have reversed operands except for "bound" and
1562 "enter". We also don't reverse intersegment "jmp" and "call"
1563 instructions with 2 immediate operands so that the immediate segment
1564 precedes the offset, as it does when in AT&T mode. "enter" and the
1565 intersegment "jmp" and "call" instructions are the only ones that
1566 have two immediate operands. */
1567 if (intel_syntax
&& i
.operands
> 1
1568 && (strcmp (mnemonic
, "bound") != 0)
1569 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1571 union i386_op temp_op
;
1572 unsigned int temp_type
;
1573 RELOC_ENUM temp_reloc
;
1577 if (i
.operands
== 2)
1582 else if (i
.operands
== 3)
1587 temp_type
= i
.types
[xchg2
];
1588 i
.types
[xchg2
] = i
.types
[xchg1
];
1589 i
.types
[xchg1
] = temp_type
;
1590 temp_op
= i
.op
[xchg2
];
1591 i
.op
[xchg2
] = i
.op
[xchg1
];
1592 i
.op
[xchg1
] = temp_op
;
1593 temp_reloc
= i
.reloc
[xchg2
];
1594 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1595 i
.reloc
[xchg1
] = temp_reloc
;
1597 if (i
.mem_operands
== 2)
1599 const seg_entry
*temp_seg
;
1600 temp_seg
= i
.seg
[0];
1601 i
.seg
[0] = i
.seg
[1];
1602 i
.seg
[1] = temp_seg
;
1608 /* Try to ensure constant immediates are represented in the smallest
1610 char guess_suffix
= 0;
1614 guess_suffix
= i
.suffix
;
1615 else if (i
.reg_operands
)
1617 /* Figure out a suffix from the last register operand specified.
1618 We can't do this properly yet, ie. excluding InOutPortReg,
1619 but the following works for instructions with immediates.
1620 In any case, we can't set i.suffix yet. */
1621 for (op
= i
.operands
; --op
>= 0;)
1622 if (i
.types
[op
] & Reg
)
1624 if (i
.types
[op
] & Reg8
)
1625 guess_suffix
= BYTE_MNEM_SUFFIX
;
1626 else if (i
.types
[op
] & Reg16
)
1627 guess_suffix
= WORD_MNEM_SUFFIX
;
1628 else if (i
.types
[op
] & Reg32
)
1629 guess_suffix
= LONG_MNEM_SUFFIX
;
1630 else if (i
.types
[op
] & Reg64
)
1631 guess_suffix
= QWORD_MNEM_SUFFIX
;
1635 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1636 guess_suffix
= WORD_MNEM_SUFFIX
;
1638 for (op
= i
.operands
; --op
>= 0;)
1639 if (i
.types
[op
] & Imm
)
1641 switch (i
.op
[op
].imms
->X_op
)
1644 /* If a suffix is given, this operand may be shortened. */
1645 switch (guess_suffix
)
1647 case LONG_MNEM_SUFFIX
:
1648 i
.types
[op
] |= Imm32
| Imm64
;
1650 case WORD_MNEM_SUFFIX
:
1651 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1653 case BYTE_MNEM_SUFFIX
:
1654 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1658 /* If this operand is at most 16 bits, convert it
1659 to a signed 16 bit number before trying to see
1660 whether it will fit in an even smaller size.
1661 This allows a 16-bit operand such as $0xffe0 to
1662 be recognised as within Imm8S range. */
1663 if ((i
.types
[op
] & Imm16
)
1664 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1666 i
.op
[op
].imms
->X_add_number
=
1667 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1669 if ((i
.types
[op
] & Imm32
)
1670 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1672 i
.op
[op
].imms
->X_add_number
=
1673 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1675 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1676 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1677 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1678 i
.types
[op
] &= ~Imm32
;
1683 /* Symbols and expressions. */
1685 /* Convert symbolic operand to proper sizes for matching. */
1686 switch (guess_suffix
)
1688 case QWORD_MNEM_SUFFIX
:
1689 i
.types
[op
] = Imm64
| Imm32S
;
1691 case LONG_MNEM_SUFFIX
:
1692 i
.types
[op
] = Imm32
| Imm64
;
1694 case WORD_MNEM_SUFFIX
:
1695 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1698 case BYTE_MNEM_SUFFIX
:
1699 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1708 if (i
.disp_operands
)
1710 /* Try to use the smallest displacement type too. */
1713 for (op
= i
.operands
; --op
>= 0;)
1714 if ((i
.types
[op
] & Disp
)
1715 && i
.op
[op
].disps
->X_op
== O_constant
)
1717 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1719 if (i
.types
[op
] & Disp16
)
1721 /* We know this operand is at most 16 bits, so
1722 convert to a signed 16 bit number before trying
1723 to see whether it will fit in an even smaller
1726 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1728 else if (i
.types
[op
] & Disp32
)
1730 /* We know this operand is at most 32 bits, so convert to a
1731 signed 32 bit number before trying to see whether it will
1732 fit in an even smaller size. */
1733 disp
&= (((offsetT
) 2 << 31) - 1);
1734 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1736 if (flag_code
== CODE_64BIT
)
1738 if (fits_in_signed_long (disp
))
1739 i
.types
[op
] |= Disp32S
;
1740 if (fits_in_unsigned_long (disp
))
1741 i
.types
[op
] |= Disp32
;
1743 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1744 && fits_in_signed_byte (disp
))
1745 i
.types
[op
] |= Disp8
;
1752 found_reverse_match
= 0;
1753 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1755 : (i
.suffix
== WORD_MNEM_SUFFIX
1757 : (i
.suffix
== SHORT_MNEM_SUFFIX
1759 : (i
.suffix
== LONG_MNEM_SUFFIX
1761 : (i
.suffix
== QWORD_MNEM_SUFFIX
1763 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1765 for (t
= current_templates
->start
;
1766 t
< current_templates
->end
;
1769 /* Must have right number of operands. */
1770 if (i
.operands
!= t
->operands
)
1773 /* Check the suffix, except for some instructions in intel mode. */
1774 if ((t
->opcode_modifier
& suffix_check
)
1776 && (t
->opcode_modifier
& IgnoreSize
))
1778 && t
->base_opcode
== 0xd9
1779 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1780 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1783 /* Do not verify operands when there are none. */
1784 else if (!t
->operands
)
1786 if (t
->cpu_flags
& ~cpu_arch_flags
)
1788 /* We've found a match; break out of loop. */
1792 overlap0
= i
.types
[0] & t
->operand_types
[0];
1793 switch (t
->operands
)
1796 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1801 overlap1
= i
.types
[1] & t
->operand_types
[1];
1802 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1803 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1804 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1805 t
->operand_types
[0],
1806 overlap1
, i
.types
[1],
1807 t
->operand_types
[1]))
1809 /* Check if other direction is valid ... */
1810 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1813 /* Try reversing direction of operands. */
1814 overlap0
= i
.types
[0] & t
->operand_types
[1];
1815 overlap1
= i
.types
[1] & t
->operand_types
[0];
1816 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1817 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1818 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1819 t
->operand_types
[1],
1820 overlap1
, i
.types
[1],
1821 t
->operand_types
[0]))
1823 /* Does not match either direction. */
1826 /* found_reverse_match holds which of D or FloatDR
1828 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1830 /* Found a forward 2 operand match here. */
1831 else if (t
->operands
== 3)
1833 /* Here we make use of the fact that there are no
1834 reverse match 3 operand instructions, and all 3
1835 operand instructions only need to be checked for
1836 register consistency between operands 2 and 3. */
1837 overlap2
= i
.types
[2] & t
->operand_types
[2];
1838 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1839 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1840 t
->operand_types
[1],
1841 overlap2
, i
.types
[2],
1842 t
->operand_types
[2]))
1846 /* Found either forward/reverse 2 or 3 operand match here:
1847 slip through to break. */
1849 if (t
->cpu_flags
& ~cpu_arch_flags
)
1851 found_reverse_match
= 0;
1854 /* We've found a match; break out of loop. */
1857 if (t
== current_templates
->end
)
1859 /* We found no match. */
1860 as_bad (_("suffix or operands invalid for `%s'"),
1861 current_templates
->start
->name
);
1865 if (!quiet_warnings
)
1868 && ((i
.types
[0] & JumpAbsolute
)
1869 != (t
->operand_types
[0] & JumpAbsolute
)))
1871 as_warn (_("indirect %s without `*'"), t
->name
);
1874 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1875 == (IsPrefix
|IgnoreSize
))
1877 /* Warn them that a data or address size prefix doesn't
1878 affect assembly of the next line of code. */
1879 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1883 /* Copy the template we found. */
1885 if (found_reverse_match
)
1887 /* If we found a reverse match we must alter the opcode
1888 direction bit. found_reverse_match holds bits to change
1889 (different for int & float insns). */
1891 i
.tm
.base_opcode
^= found_reverse_match
;
1893 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1894 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1897 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1900 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1901 i
.tm
.base_opcode
^= FloatR
;
1903 if (i
.tm
.opcode_modifier
& FWait
)
1904 if (! add_prefix (FWAIT_OPCODE
))
1907 /* Check string instruction segment overrides. */
1908 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1910 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1911 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1913 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1915 as_bad (_("`%s' operand %d must use `%%es' segment"),
1920 /* There's only ever one segment override allowed per instruction.
1921 This instruction possibly has a legal segment override on the
1922 second operand, so copy the segment to where non-string
1923 instructions store it, allowing common code. */
1924 i
.seg
[0] = i
.seg
[1];
1926 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1928 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1930 as_bad (_("`%s' operand %d must use `%%es' segment"),
1938 /* If matched instruction specifies an explicit instruction mnemonic
1940 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1942 if (i
.tm
.opcode_modifier
& Size16
)
1943 i
.suffix
= WORD_MNEM_SUFFIX
;
1944 else if (i
.tm
.opcode_modifier
& Size64
)
1945 i
.suffix
= QWORD_MNEM_SUFFIX
;
1947 i
.suffix
= LONG_MNEM_SUFFIX
;
1949 else if (i
.reg_operands
)
1951 /* If there's no instruction mnemonic suffix we try to invent one
1952 based on register operands. */
1955 /* We take i.suffix from the last register operand specified,
1956 Destination register type is more significant than source
1959 for (op
= i
.operands
; --op
>= 0;)
1960 if ((i
.types
[op
] & Reg
)
1961 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1963 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1964 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1965 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1970 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1973 for (op
= i
.operands
; --op
>= 0;)
1975 /* If this is an eight bit register, it's OK. If it's
1976 the 16 or 32 bit version of an eight bit register,
1977 we will just use the low portion, and that's OK too. */
1978 if (i
.types
[op
] & Reg8
)
1981 /* movzx and movsx should not generate this warning. */
1983 && (i
.tm
.base_opcode
== 0xfb7
1984 || i
.tm
.base_opcode
== 0xfb6
1985 || i
.tm
.base_opcode
== 0x63
1986 || i
.tm
.base_opcode
== 0xfbe
1987 || i
.tm
.base_opcode
== 0xfbf))
1990 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1992 /* Check that the template allows eight bit regs
1993 This kills insns such as `orb $1,%edx', which
1994 maybe should be allowed. */
1995 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1999 /* Prohibit these changes in the 64bit mode, since
2000 the lowering is more complicated. */
2001 if (flag_code
== CODE_64BIT
2002 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2003 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2004 i
.op
[op
].regs
->reg_name
,
2006 #if REGISTER_WARNINGS
2008 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2009 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2011 + (i
.types
[op
] & Reg16
2012 ? REGNAM_AL
- REGNAM_AX
2013 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2014 i
.op
[op
].regs
->reg_name
,
2019 /* Any other register is bad. */
2020 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2022 | Control
| Debug
| Test
2023 | FloatReg
| FloatAcc
))
2025 as_bad (_("`%%%s' not allowed with `%s%c'"),
2026 i
.op
[op
].regs
->reg_name
,
2033 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2037 for (op
= i
.operands
; --op
>= 0;)
2038 /* Reject eight bit registers, except where the template
2039 requires them. (eg. movzb) */
2040 if ((i
.types
[op
] & Reg8
) != 0
2041 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2043 as_bad (_("`%%%s' not allowed with `%s%c'"),
2044 i
.op
[op
].regs
->reg_name
,
2049 /* Warn if the e prefix on a general reg is missing. */
2050 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2051 && (i
.types
[op
] & Reg16
) != 0
2052 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2054 /* Prohibit these changes in the 64bit mode, since
2055 the lowering is more complicated. */
2056 if (flag_code
== CODE_64BIT
)
2057 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2058 i
.op
[op
].regs
->reg_name
,
2060 #if REGISTER_WARNINGS
2062 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2063 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2064 i
.op
[op
].regs
->reg_name
,
2068 /* Warn if the r prefix on a general reg is missing. */
2069 else if ((i
.types
[op
] & Reg64
) != 0
2070 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2072 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2073 i
.op
[op
].regs
->reg_name
,
2077 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2081 for (op
= i
.operands
; --op
>= 0; )
2082 /* Reject eight bit registers, except where the template
2083 requires them. (eg. movzb) */
2084 if ((i
.types
[op
] & Reg8
) != 0
2085 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2087 as_bad (_("`%%%s' not allowed with `%s%c'"),
2088 i
.op
[op
].regs
->reg_name
,
2093 /* Warn if the e prefix on a general reg is missing. */
2094 else if (((i
.types
[op
] & Reg16
) != 0
2095 || (i
.types
[op
] & Reg32
) != 0)
2096 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2098 /* Prohibit these changes in the 64bit mode, since
2099 the lowering is more complicated. */
2100 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2101 i
.op
[op
].regs
->reg_name
,
2105 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2108 for (op
= i
.operands
; --op
>= 0;)
2109 /* Reject eight bit registers, except where the template
2110 requires them. (eg. movzb) */
2111 if ((i
.types
[op
] & Reg8
) != 0
2112 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2114 as_bad (_("`%%%s' not allowed with `%s%c'"),
2115 i
.op
[op
].regs
->reg_name
,
2120 /* Warn if the e prefix on a general reg is present. */
2121 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2122 && (i
.types
[op
] & Reg32
) != 0
2123 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2125 /* Prohibit these changes in the 64bit mode, since
2126 the lowering is more complicated. */
2127 if (flag_code
== CODE_64BIT
)
2128 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2129 i
.op
[op
].regs
->reg_name
,
2132 #if REGISTER_WARNINGS
2133 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2134 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2135 i
.op
[op
].regs
->reg_name
,
2140 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2141 /* Do nothing if the instruction is going to ignore the prefix. */
2146 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2148 i
.suffix
= stackop_size
;
2150 /* Make still unresolved immediate matches conform to size of immediate
2151 given in i.suffix. Note: overlap2 cannot be an immediate! */
2152 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2153 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2154 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2155 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2159 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2160 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2161 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2163 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2164 || overlap0
== (Imm16
| Imm32
)
2165 || overlap0
== (Imm16
| Imm32S
))
2168 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2170 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2171 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2172 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2174 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2178 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2179 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2180 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2181 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2185 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2186 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2187 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2189 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2190 || overlap1
== (Imm16
| Imm32
)
2191 || overlap1
== (Imm16
| Imm32S
))
2194 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2196 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2197 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2198 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2200 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2204 assert ((overlap2
& Imm
) == 0);
2206 i
.types
[0] = overlap0
;
2207 if (overlap0
& ImplicitRegister
)
2209 if (overlap0
& Imm1
)
2210 i
.imm_operands
= 0; /* kludge for shift insns. */
2212 i
.types
[1] = overlap1
;
2213 if (overlap1
& ImplicitRegister
)
2216 i
.types
[2] = overlap2
;
2217 if (overlap2
& ImplicitRegister
)
2220 /* Finalize opcode. First, we change the opcode based on the operand
2221 size given by i.suffix: We need not change things for byte insns. */
2223 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2225 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2229 /* For movzx and movsx, need to check the register type. */
2231 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2232 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2234 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2236 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2237 if (!add_prefix (prefix
))
2241 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2243 /* It's not a byte, select word/dword operation. */
2244 if (i
.tm
.opcode_modifier
& W
)
2246 if (i
.tm
.opcode_modifier
& ShortForm
)
2247 i
.tm
.base_opcode
|= 8;
2249 i
.tm
.base_opcode
|= 1;
2251 /* Now select between word & dword operations via the operand
2252 size prefix, except for instructions that will ignore this
2254 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2255 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2256 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2258 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2259 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2260 prefix
= ADDR_PREFIX_OPCODE
;
2262 if (! add_prefix (prefix
))
2266 /* Set mode64 for an operand. */
2267 if (i
.suffix
== QWORD_MNEM_SUFFIX
2268 && !(i
.tm
.opcode_modifier
& NoRex64
))
2271 if (flag_code
< CODE_64BIT
)
2273 as_bad (_("64bit operations available only in 64bit modes."));
2278 /* Size floating point instruction. */
2279 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2281 if (i
.tm
.opcode_modifier
& FloatMF
)
2282 i
.tm
.base_opcode
^= 4;
2286 if (i
.tm
.opcode_modifier
& ImmExt
)
2288 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2289 opcode suffix which is coded in the same place as an 8-bit
2290 immediate field would be. Here we fake an 8-bit immediate
2291 operand from the opcode suffix stored in tm.extension_opcode. */
2295 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2297 exp
= &im_expressions
[i
.imm_operands
++];
2298 i
.op
[i
.operands
].imms
= exp
;
2299 i
.types
[i
.operands
++] = Imm8
;
2300 exp
->X_op
= O_constant
;
2301 exp
->X_add_number
= i
.tm
.extension_opcode
;
2302 i
.tm
.extension_opcode
= None
;
2305 /* For insns with operands there are more diddles to do to the opcode. */
2308 /* Default segment register this instruction will use
2309 for memory accesses. 0 means unknown.
2310 This is only for optimizing out unnecessary segment overrides. */
2311 const seg_entry
*default_seg
= 0;
2313 /* The imul $imm, %reg instruction is converted into
2314 imul $imm, %reg, %reg, and the clr %reg instruction
2315 is converted into xor %reg, %reg. */
2316 if (i
.tm
.opcode_modifier
& regKludge
)
2318 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2319 /* Pretend we saw the extra register operand. */
2320 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2321 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2322 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2326 if (i
.tm
.opcode_modifier
& ShortForm
)
2328 /* The register or float register operand is in operand 0 or 1. */
2329 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2330 /* Register goes in low 3 bits of opcode. */
2331 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2332 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2334 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2336 /* Warn about some common errors, but press on regardless.
2337 The first case can be generated by gcc (<= 2.8.1). */
2338 if (i
.operands
== 2)
2340 /* Reversed arguments on faddp, fsubp, etc. */
2341 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2342 i
.op
[1].regs
->reg_name
,
2343 i
.op
[0].regs
->reg_name
);
2347 /* Extraneous `l' suffix on fp insn. */
2348 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2349 i
.op
[0].regs
->reg_name
);
2353 else if (i
.tm
.opcode_modifier
& Modrm
)
2355 /* The opcode is completed (modulo i.tm.extension_opcode which
2356 must be put into the modrm byte).
2357 Now, we make the modrm & index base bytes based on all the
2358 info we've collected. */
2360 /* i.reg_operands MUST be the number of real register operands;
2361 implicit registers do not count. */
2362 if (i
.reg_operands
== 2)
2364 unsigned int source
, dest
;
2365 source
= ((i
.types
[0]
2366 & (Reg
| RegMMX
| RegXMM
2368 | Control
| Debug
| Test
))
2373 /* One of the register operands will be encoded in the
2374 i.tm.reg field, the other in the combined i.tm.mode
2375 and i.tm.regmem fields. If no form of this
2376 instruction supports a memory destination operand,
2377 then we assume the source operand may sometimes be
2378 a memory operand and so we need to store the
2379 destination in the i.rm.reg field. */
2380 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2382 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2383 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2384 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2386 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2391 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2392 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2393 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2395 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2400 { /* If it's not 2 reg operands... */
2403 unsigned int fake_zero_displacement
= 0;
2404 unsigned int op
= ((i
.types
[0] & AnyMem
)
2406 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2413 if (! i
.disp_operands
)
2414 fake_zero_displacement
= 1;
2417 /* Operand is just <disp> */
2418 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2420 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2421 i
.types
[op
] &= ~Disp
;
2422 i
.types
[op
] |= Disp16
;
2424 else if (flag_code
!= CODE_64BIT
)
2426 i
.rm
.regmem
= NO_BASE_REGISTER
;
2427 i
.types
[op
] &= ~Disp
;
2428 i
.types
[op
] |= Disp32
;
2432 /* 64bit mode overwrites the 32bit
2433 absolute addressing by RIP relative
2434 addressing and absolute addressing
2435 is encoded by one of the redundant
2438 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2439 i
.sib
.base
= NO_BASE_REGISTER
;
2440 i
.sib
.index
= NO_INDEX_REGISTER
;
2441 i
.types
[op
] &= ~Disp
;
2442 i
.types
[op
] |= Disp32S
;
2445 else /* ! i.base_reg && i.index_reg */
2447 i
.sib
.index
= i
.index_reg
->reg_num
;
2448 i
.sib
.base
= NO_BASE_REGISTER
;
2449 i
.sib
.scale
= i
.log2_scale_factor
;
2450 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2451 i
.types
[op
] &= ~Disp
;
2452 if (flag_code
!= CODE_64BIT
)
2453 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2455 i
.types
[op
] |= Disp32S
;
2456 if (i
.index_reg
->reg_flags
& RegRex
)
2460 /* RIP addressing for 64bit mode. */
2461 else if (i
.base_reg
->reg_type
== BaseIndex
)
2463 i
.rm
.regmem
= NO_BASE_REGISTER
;
2464 i
.types
[op
] &= ~Disp
;
2465 i
.types
[op
] |= Disp32S
;
2466 i
.flags
[op
] = Operand_PCrel
;
2468 else if (i
.base_reg
->reg_type
& Reg16
)
2470 switch (i
.base_reg
->reg_num
)
2475 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2476 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2483 if ((i
.types
[op
] & Disp
) == 0)
2485 /* fake (%bp) into 0(%bp) */
2486 i
.types
[op
] |= Disp8
;
2487 fake_zero_displacement
= 1;
2490 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2491 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2493 default: /* (%si) -> 4 or (%di) -> 5 */
2494 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2496 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2498 else /* i.base_reg and 32/64 bit mode */
2500 if (flag_code
== CODE_64BIT
2501 && (i
.types
[op
] & Disp
))
2503 if (i
.types
[op
] & Disp8
)
2504 i
.types
[op
] = Disp8
| Disp32S
;
2506 i
.types
[op
] = Disp32S
;
2508 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2509 if (i
.base_reg
->reg_flags
& RegRex
)
2511 i
.sib
.base
= i
.base_reg
->reg_num
;
2512 /* x86-64 ignores REX prefix bit here to avoid
2513 decoder complications. */
2514 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2517 if (i
.disp_operands
== 0)
2519 fake_zero_displacement
= 1;
2520 i
.types
[op
] |= Disp8
;
2523 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2527 i
.sib
.scale
= i
.log2_scale_factor
;
2530 /* <disp>(%esp) becomes two byte modrm
2531 with no index register. We've already
2532 stored the code for esp in i.rm.regmem
2533 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2534 base register besides %esp will not use
2535 the extra modrm byte. */
2536 i
.sib
.index
= NO_INDEX_REGISTER
;
2537 #if ! SCALE1_WHEN_NO_INDEX
2538 /* Another case where we force the second
2540 if (i
.log2_scale_factor
)
2541 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2546 i
.sib
.index
= i
.index_reg
->reg_num
;
2547 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2548 if (i
.index_reg
->reg_flags
& RegRex
)
2551 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2554 if (fake_zero_displacement
)
2556 /* Fakes a zero displacement assuming that i.types[op]
2557 holds the correct displacement size. */
2560 assert (i
.op
[op
].disps
== 0);
2561 exp
= &disp_expressions
[i
.disp_operands
++];
2562 i
.op
[op
].disps
= exp
;
2563 exp
->X_op
= O_constant
;
2564 exp
->X_add_number
= 0;
2565 exp
->X_add_symbol
= (symbolS
*) 0;
2566 exp
->X_op_symbol
= (symbolS
*) 0;
2570 /* Fill in i.rm.reg or i.rm.regmem field with register
2571 operand (if any) based on i.tm.extension_opcode.
2572 Again, we must be careful to make sure that
2573 segment/control/debug/test/MMX registers are coded
2574 into the i.rm.reg field. */
2579 & (Reg
| RegMMX
| RegXMM
2581 | Control
| Debug
| Test
))
2584 & (Reg
| RegMMX
| RegXMM
2586 | Control
| Debug
| Test
))
2589 /* If there is an extension opcode to put here, the
2590 register number must be put into the regmem field. */
2591 if (i
.tm
.extension_opcode
!= None
)
2593 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2594 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2599 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2600 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2604 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2605 we must set it to 3 to indicate this is a register
2606 operand in the regmem field. */
2607 if (!i
.mem_operands
)
2611 /* Fill in i.rm.reg field with extension opcode (if any). */
2612 if (i
.tm
.extension_opcode
!= None
)
2613 i
.rm
.reg
= i
.tm
.extension_opcode
;
2616 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2618 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2619 && i
.op
[0].regs
->reg_num
== 1)
2621 as_bad (_("you can't `pop %%cs'"));
2624 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2625 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2628 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2632 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2634 /* For the string instructions that allow a segment override
2635 on one of their operands, the default segment is ds. */
2639 /* If a segment was explicitly specified,
2640 and the specified segment is not the default,
2641 use an opcode prefix to select it.
2642 If we never figured out what the default segment is,
2643 then default_seg will be zero at this point,
2644 and the specified segment prefix will always be used. */
2645 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2647 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2651 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2653 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2654 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2658 /* Handle conversion of 'int $3' --> special int3 insn. */
2659 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2661 i
.tm
.base_opcode
= INT3_OPCODE
;
2665 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2666 && i
.op
[0].disps
->X_op
== O_constant
)
2668 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2669 the absolute address given by the constant. Since ix86 jumps and
2670 calls are pc relative, we need to generate a reloc. */
2671 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2672 i
.op
[0].disps
->X_op
= O_symbol
;
2675 if (i
.tm
.opcode_modifier
& Rex64
)
2678 /* For 8bit registers we would need an empty rex prefix.
2679 Also in the case instruction is already having prefix,
2680 we need to convert old registers to new ones. */
2682 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2683 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2684 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2685 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2689 for (x
= 0; x
< 2; x
++)
2691 /* Look for 8bit operand that does use old registers. */
2692 if (i
.types
[x
] & Reg8
2693 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2695 /* In case it is "hi" register, give up. */
2696 if (i
.op
[x
].regs
->reg_num
> 3)
2697 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2698 i
.op
[x
].regs
->reg_name
);
2700 /* Otherwise it is equivalent to the extended register.
2701 Since the encoding don't change this is merely cosmetical
2702 cleanup for debug output. */
2704 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2709 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2711 | (i
.rex
.mode64
? 8 : 0)
2712 | (i
.rex
.extX
? 4 : 0)
2713 | (i
.rex
.extY
? 2 : 0)
2714 | (i
.rex
.extZ
? 1 : 0));
2716 /* We are ready to output the insn. */
2720 /* Tie dwarf2 debug info to the address at the start of the insn.
2721 We can't do this after the insn has been output as the current
2722 frag may have been closed off. eg. by frag_var. */
2723 dwarf2_emit_insn (0);
2726 if (i
.tm
.opcode_modifier
& Jump
)
2730 relax_substateT subtype
;
2735 if (flag_code
== CODE_16BIT
)
2739 if (i
.prefix
[DATA_PREFIX
])
2745 /* Pentium4 branch hints. */
2746 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2747 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2752 if (i
.prefix
[REX_PREFIX
])
2758 if (i
.prefixes
!= 0 && !intel_syntax
)
2759 as_warn (_("skipping prefixes on this instruction"));
2761 /* It's always a symbol; End frag & setup for relax.
2762 Make sure there is enough room in this frag for the largest
2763 instruction we may generate in md_convert_frag. This is 2
2764 bytes for the opcode and room for the prefix and largest
2766 frag_grow (prefix
+ 2 + 4);
2767 /* Prefix and 1 opcode byte go in fr_fix. */
2768 p
= frag_more (prefix
+ 1);
2769 if (i
.prefix
[DATA_PREFIX
])
2770 *p
++ = DATA_PREFIX_OPCODE
;
2771 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2772 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2773 *p
++ = i
.prefix
[SEG_PREFIX
];
2774 if (i
.prefix
[REX_PREFIX
])
2775 *p
++ = i
.prefix
[REX_PREFIX
];
2776 *p
= i
.tm
.base_opcode
;
2778 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2779 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2780 else if ((cpu_arch_flags
& Cpu386
) != 0)
2781 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2783 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2786 sym
= i
.op
[0].disps
->X_add_symbol
;
2787 off
= i
.op
[0].disps
->X_add_number
;
2789 if (i
.op
[0].disps
->X_op
!= O_constant
2790 && i
.op
[0].disps
->X_op
!= O_symbol
)
2792 /* Handle complex expressions. */
2793 sym
= make_expr_symbol (i
.op
[0].disps
);
2797 /* 1 possible extra opcode + 4 byte displacement go in var part.
2798 Pass reloc in fr_var. */
2799 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2801 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2805 if (i
.tm
.opcode_modifier
& JumpByte
)
2807 /* This is a loop or jecxz type instruction. */
2809 if (i
.prefix
[ADDR_PREFIX
])
2811 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2814 /* Pentium4 branch hints. */
2815 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2816 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2818 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
2827 if (flag_code
== CODE_16BIT
)
2830 if (i
.prefix
[DATA_PREFIX
])
2832 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2842 if (i
.prefix
[REX_PREFIX
])
2844 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2848 if (i
.prefixes
!= 0 && !intel_syntax
)
2849 as_warn (_("skipping prefixes on this instruction"));
2851 p
= frag_more (1 + size
);
2852 *p
++ = i
.tm
.base_opcode
;
2854 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2855 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2857 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2864 if (flag_code
== CODE_16BIT
)
2868 if (i
.prefix
[DATA_PREFIX
])
2874 if (i
.prefix
[REX_PREFIX
])
2884 if (i
.prefixes
!= 0 && !intel_syntax
)
2885 as_warn (_("skipping prefixes on this instruction"));
2887 /* 1 opcode; 2 segment; offset */
2888 p
= frag_more (prefix
+ 1 + 2 + size
);
2890 if (i
.prefix
[DATA_PREFIX
])
2891 *p
++ = DATA_PREFIX_OPCODE
;
2893 if (i
.prefix
[REX_PREFIX
])
2894 *p
++ = i
.prefix
[REX_PREFIX
];
2896 *p
++ = i
.tm
.base_opcode
;
2897 if (i
.op
[1].imms
->X_op
== O_constant
)
2899 offsetT n
= i
.op
[1].imms
->X_add_number
;
2902 && !fits_in_unsigned_word (n
)
2903 && !fits_in_signed_word (n
))
2905 as_bad (_("16-bit jump out of range"));
2908 md_number_to_chars (p
, n
, size
);
2911 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2912 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2913 if (i
.op
[0].imms
->X_op
!= O_constant
)
2914 as_bad (_("can't handle non absolute segment in `%s'"),
2916 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2920 /* Output normal instructions here. */
2923 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2924 byte for the SSE instructions to specify prefix they require. */
2925 if (i
.tm
.base_opcode
& 0xff0000)
2926 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2928 /* The prefix bytes. */
2930 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2936 md_number_to_chars (p
, (valueT
) *q
, 1);
2940 /* Now the opcode; be careful about word order here! */
2941 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2943 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2948 /* Put out high byte first: can't use md_number_to_chars! */
2949 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2950 *p
= i
.tm
.base_opcode
& 0xff;
2953 /* Now the modrm byte and sib byte (if present). */
2954 if (i
.tm
.opcode_modifier
& Modrm
)
2957 md_number_to_chars (p
,
2958 (valueT
) (i
.rm
.regmem
<< 0
2962 /* If i.rm.regmem == ESP (4)
2963 && i.rm.mode != (Register mode)
2965 ==> need second modrm byte. */
2966 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2968 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2971 md_number_to_chars (p
,
2972 (valueT
) (i
.sib
.base
<< 0
2974 | i
.sib
.scale
<< 6),
2979 if (i
.disp_operands
)
2981 register unsigned int n
;
2983 for (n
= 0; n
< i
.operands
; n
++)
2985 if (i
.types
[n
] & Disp
)
2987 if (i
.op
[n
].disps
->X_op
== O_constant
)
2993 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2996 if (i
.types
[n
] & Disp8
)
2998 if (i
.types
[n
] & Disp64
)
3001 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3003 p
= frag_more (size
);
3004 md_number_to_chars (p
, val
, size
);
3010 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3012 /* The PC relative address is computed relative
3013 to the instruction boundary, so in case immediate
3014 fields follows, we need to adjust the value. */
3015 if (pcrel
&& i
.imm_operands
)
3018 register unsigned int n1
;
3020 for (n1
= 0; n1
< i
.operands
; n1
++)
3021 if (i
.types
[n1
] & Imm
)
3023 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3026 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3028 if (i
.types
[n1
] & Imm64
)
3033 /* We should find the immediate. */
3034 if (n1
== i
.operands
)
3036 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3039 if (i
.types
[n
] & Disp32S
)
3042 if (i
.types
[n
] & (Disp16
| Disp64
))
3045 if (i
.types
[n
] & Disp64
)
3049 p
= frag_more (size
);
3050 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3051 i
.op
[n
].disps
, pcrel
,
3052 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3058 /* Output immediate. */
3061 register unsigned int n
;
3063 for (n
= 0; n
< i
.operands
; n
++)
3065 if (i
.types
[n
] & Imm
)
3067 if (i
.op
[n
].imms
->X_op
== O_constant
)
3073 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3076 if (i
.types
[n
] & (Imm8
| Imm8S
))
3078 else if (i
.types
[n
] & Imm64
)
3081 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3083 p
= frag_more (size
);
3084 md_number_to_chars (p
, val
, size
);
3088 /* Not absolute_section.
3089 Need a 32-bit fixup (don't support 8bit
3090 non-absolute imms). Try to support other
3092 RELOC_ENUM reloc_type
;
3096 if ((i
.types
[n
] & (Imm32S
))
3097 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3099 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3102 if (i
.types
[n
] & (Imm8
| Imm8S
))
3104 if (i
.types
[n
] & Imm64
)
3108 p
= frag_more (size
);
3109 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3110 #ifdef BFD_ASSEMBLER
3111 if (reloc_type
== BFD_RELOC_32
3113 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3114 && (i
.op
[n
].imms
->X_op
== O_symbol
3115 || (i
.op
[n
].imms
->X_op
== O_add
3116 && ((symbol_get_value_expression
3117 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3120 /* We don't support dynamic linking on x86-64 yet. */
3121 if (flag_code
== CODE_64BIT
)
3123 reloc_type
= BFD_RELOC_386_GOTPC
;
3124 i
.op
[n
].imms
->X_add_number
+= 3;
3127 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3128 i
.op
[n
].imms
, 0, reloc_type
);
3140 #endif /* DEBUG386 */
3145 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3147 /* Parse operands of the form
3148 <symbol>@GOTOFF+<nnn>
3149 and similar .plt or .got references.
3151 If we find one, set up the correct relocation in RELOC and copy the
3152 input string, minus the `@GOTOFF' into a malloc'd buffer for
3153 parsing by the calling routine. Return this buffer, and if ADJUST
3154 is non-null set it to the length of the string we removed from the
3155 input line. Otherwise return NULL. */
3157 lex_got (reloc
, adjust
)
3161 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3162 static const struct {
3164 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3166 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3167 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3168 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3169 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3174 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3175 if (is_end_of_line
[(unsigned char) *cp
])
3178 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3182 len
= strlen (gotrel
[j
].str
);
3183 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3185 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3188 char *tmpbuf
, *past_reloc
;
3190 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3194 if (GOT_symbol
== NULL
)
3195 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3197 /* Replace the relocation token with ' ', so that
3198 errors like foo@GOTOFF1 will be detected. */
3200 /* The length of the first part of our input line. */
3201 first
= cp
- input_line_pointer
;
3203 /* The second part goes from after the reloc token until
3204 (and including) an end_of_line char. Don't use strlen
3205 here as the end_of_line char may not be a NUL. */
3206 past_reloc
= cp
+ 1 + len
;
3207 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3209 second
= cp
- past_reloc
;
3211 /* Allocate and copy string. The trailing NUL shouldn't
3212 be necessary, but be safe. */
3213 tmpbuf
= xmalloc (first
+ second
+ 2);
3214 memcpy (tmpbuf
, input_line_pointer
, first
);
3215 tmpbuf
[first
] = ' ';
3216 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3217 tmpbuf
[first
+ second
+ 1] = '\0';
3221 as_bad (_("@%s reloc is not supported in %s bit mode"),
3222 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3227 /* Might be a symbol version string. Don't as_bad here. */
3231 /* x86_cons_fix_new is called via the expression parsing code when a
3232 reloc is needed. We use this hook to get the correct .got reloc. */
3233 static RELOC_ENUM got_reloc
= NO_RELOC
;
3236 x86_cons_fix_new (frag
, off
, len
, exp
)
3242 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3243 got_reloc
= NO_RELOC
;
3244 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3248 x86_cons (exp
, size
)
3254 /* Handle @GOTOFF and the like in an expression. */
3256 char *gotfree_input_line
;
3259 save
= input_line_pointer
;
3260 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3261 if (gotfree_input_line
)
3262 input_line_pointer
= gotfree_input_line
;
3266 if (gotfree_input_line
)
3268 /* expression () has merrily parsed up to the end of line,
3269 or a comma - in the wrong buffer. Transfer how far
3270 input_line_pointer has moved to the right buffer. */
3271 input_line_pointer
= (save
3272 + (input_line_pointer
- gotfree_input_line
)
3274 free (gotfree_input_line
);
3282 static int i386_immediate
PARAMS ((char *));
3285 i386_immediate (imm_start
)
3288 char *save_input_line_pointer
;
3290 char *gotfree_input_line
;
3295 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3297 as_bad (_("only 1 or 2 immediate operands are allowed"));
3301 exp
= &im_expressions
[i
.imm_operands
++];
3302 i
.op
[this_operand
].imms
= exp
;
3304 if (is_space_char (*imm_start
))
3307 save_input_line_pointer
= input_line_pointer
;
3308 input_line_pointer
= imm_start
;
3311 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3312 if (gotfree_input_line
)
3313 input_line_pointer
= gotfree_input_line
;
3316 exp_seg
= expression (exp
);
3319 if (*input_line_pointer
)
3320 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3322 input_line_pointer
= save_input_line_pointer
;
3324 if (gotfree_input_line
)
3325 free (gotfree_input_line
);
3328 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3330 /* Missing or bad expr becomes absolute 0. */
3331 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3333 exp
->X_op
= O_constant
;
3334 exp
->X_add_number
= 0;
3335 exp
->X_add_symbol
= (symbolS
*) 0;
3336 exp
->X_op_symbol
= (symbolS
*) 0;
3338 else if (exp
->X_op
== O_constant
)
3340 /* Size it properly later. */
3341 i
.types
[this_operand
] |= Imm64
;
3342 /* If BFD64, sign extend val. */
3343 if (!use_rela_relocations
)
3344 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3345 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3347 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3349 #ifdef BFD_ASSEMBLER
3350 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3352 && exp_seg
!= text_section
3353 && exp_seg
!= data_section
3354 && exp_seg
!= bss_section
3355 && exp_seg
!= undefined_section
3356 #ifdef BFD_ASSEMBLER
3357 && !bfd_is_com_section (exp_seg
)
3361 #ifdef BFD_ASSEMBLER
3362 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3364 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3371 /* This is an address. The size of the address will be
3372 determined later, depending on destination register,
3373 suffix, or the default for the section. */
3374 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3380 static char *i386_scale
PARAMS ((char *));
3387 char *save
= input_line_pointer
;
3389 input_line_pointer
= scale
;
3390 val
= get_absolute_expression ();
3396 i
.log2_scale_factor
= 0;
3399 i
.log2_scale_factor
= 1;
3402 i
.log2_scale_factor
= 2;
3405 i
.log2_scale_factor
= 3;
3408 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3410 input_line_pointer
= save
;
3413 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3415 as_warn (_("scale factor of %d without an index register"),
3416 1 << i
.log2_scale_factor
);
3417 #if SCALE1_WHEN_NO_INDEX
3418 i
.log2_scale_factor
= 0;
3421 scale
= input_line_pointer
;
3422 input_line_pointer
= save
;
3426 static int i386_displacement
PARAMS ((char *, char *));
3429 i386_displacement (disp_start
, disp_end
)
3433 register expressionS
*exp
;
3435 char *save_input_line_pointer
;
3437 char *gotfree_input_line
;
3439 int bigdisp
= Disp32
;
3441 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3443 if (flag_code
== CODE_64BIT
)
3445 i
.types
[this_operand
] |= bigdisp
;
3447 exp
= &disp_expressions
[i
.disp_operands
];
3448 i
.op
[this_operand
].disps
= exp
;
3450 save_input_line_pointer
= input_line_pointer
;
3451 input_line_pointer
= disp_start
;
3452 END_STRING_AND_SAVE (disp_end
);
3454 #ifndef GCC_ASM_O_HACK
3455 #define GCC_ASM_O_HACK 0
3458 END_STRING_AND_SAVE (disp_end
+ 1);
3459 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3460 && displacement_string_end
[-1] == '+')
3462 /* This hack is to avoid a warning when using the "o"
3463 constraint within gcc asm statements.
3466 #define _set_tssldt_desc(n,addr,limit,type) \
3467 __asm__ __volatile__ ( \
3469 "movw %w1,2+%0\n\t" \
3471 "movb %b1,4+%0\n\t" \
3472 "movb %4,5+%0\n\t" \
3473 "movb $0,6+%0\n\t" \
3474 "movb %h1,7+%0\n\t" \
3476 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3478 This works great except that the output assembler ends
3479 up looking a bit weird if it turns out that there is
3480 no offset. You end up producing code that looks like:
3493 So here we provide the missing zero. */
3495 *displacement_string_end
= '0';
3499 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3500 if (gotfree_input_line
)
3501 input_line_pointer
= gotfree_input_line
;
3504 exp_seg
= expression (exp
);
3507 if (*input_line_pointer
)
3508 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3510 RESTORE_END_STRING (disp_end
+ 1);
3512 RESTORE_END_STRING (disp_end
);
3513 input_line_pointer
= save_input_line_pointer
;
3515 if (gotfree_input_line
)
3516 free (gotfree_input_line
);
3519 #ifdef BFD_ASSEMBLER
3520 /* We do this to make sure that the section symbol is in
3521 the symbol table. We will ultimately change the relocation
3522 to be relative to the beginning of the section. */
3523 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3524 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3526 if (exp
->X_op
!= O_symbol
)
3528 as_bad (_("bad expression used with @%s"),
3529 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3535 if (S_IS_LOCAL (exp
->X_add_symbol
)
3536 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3537 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3538 exp
->X_op
= O_subtract
;
3539 exp
->X_op_symbol
= GOT_symbol
;
3540 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3541 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3543 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3547 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3549 /* Missing or bad expr becomes absolute 0. */
3550 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3552 exp
->X_op
= O_constant
;
3553 exp
->X_add_number
= 0;
3554 exp
->X_add_symbol
= (symbolS
*) 0;
3555 exp
->X_op_symbol
= (symbolS
*) 0;
3558 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3559 if (exp
->X_op
!= O_constant
3560 #ifdef BFD_ASSEMBLER
3561 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3563 && exp_seg
!= text_section
3564 && exp_seg
!= data_section
3565 && exp_seg
!= bss_section
3566 && exp_seg
!= undefined_section
)
3568 #ifdef BFD_ASSEMBLER
3569 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3571 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3576 else if (flag_code
== CODE_64BIT
)
3577 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3581 static int i386_index_check
PARAMS ((const char *));
3583 /* Make sure the memory operand we've been dealt is valid.
3584 Return 1 on success, 0 on a failure. */
3587 i386_index_check (operand_string
)
3588 const char *operand_string
;
3591 #if INFER_ADDR_PREFIX
3597 if (flag_code
== CODE_64BIT
)
3601 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3602 && (i
.base_reg
->reg_type
!= BaseIndex
3605 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3606 != (Reg64
|BaseIndex
))))
3611 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3615 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3616 != (Reg16
|BaseIndex
)))
3618 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3619 != (Reg16
|BaseIndex
))
3621 && i
.base_reg
->reg_num
< 6
3622 && i
.index_reg
->reg_num
>= 6
3623 && i
.log2_scale_factor
== 0))))
3630 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3632 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3633 != (Reg32
|BaseIndex
))))
3639 #if INFER_ADDR_PREFIX
3640 if (flag_code
!= CODE_64BIT
3641 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3643 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3645 /* Change the size of any displacement too. At most one of
3646 Disp16 or Disp32 is set.
3647 FIXME. There doesn't seem to be any real need for separate
3648 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3649 Removing them would probably clean up the code quite a lot. */
3650 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3651 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3656 as_bad (_("`%s' is not a valid base/index expression"),
3660 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3662 flag_code_names
[flag_code
]);
3668 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3672 i386_operand (operand_string
)
3673 char *operand_string
;
3677 char *op_string
= operand_string
;
3679 if (is_space_char (*op_string
))
3682 /* We check for an absolute prefix (differentiating,
3683 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3684 if (*op_string
== ABSOLUTE_PREFIX
)
3687 if (is_space_char (*op_string
))
3689 i
.types
[this_operand
] |= JumpAbsolute
;
3692 /* Check if operand is a register. */
3693 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3694 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3696 /* Check for a segment override by searching for ':' after a
3697 segment register. */
3699 if (is_space_char (*op_string
))
3701 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3706 i
.seg
[i
.mem_operands
] = &es
;
3709 i
.seg
[i
.mem_operands
] = &cs
;
3712 i
.seg
[i
.mem_operands
] = &ss
;
3715 i
.seg
[i
.mem_operands
] = &ds
;
3718 i
.seg
[i
.mem_operands
] = &fs
;
3721 i
.seg
[i
.mem_operands
] = &gs
;
3725 /* Skip the ':' and whitespace. */
3727 if (is_space_char (*op_string
))
3730 if (!is_digit_char (*op_string
)
3731 && !is_identifier_char (*op_string
)
3732 && *op_string
!= '('
3733 && *op_string
!= ABSOLUTE_PREFIX
)
3735 as_bad (_("bad memory operand `%s'"), op_string
);
3738 /* Handle case of %es:*foo. */
3739 if (*op_string
== ABSOLUTE_PREFIX
)
3742 if (is_space_char (*op_string
))
3744 i
.types
[this_operand
] |= JumpAbsolute
;
3746 goto do_memory_reference
;
3750 as_bad (_("junk `%s' after register"), op_string
);
3753 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3754 i
.op
[this_operand
].regs
= r
;
3757 else if (*op_string
== REGISTER_PREFIX
)
3759 as_bad (_("bad register name `%s'"), op_string
);
3762 else if (*op_string
== IMMEDIATE_PREFIX
)
3765 if (i
.types
[this_operand
] & JumpAbsolute
)
3767 as_bad (_("immediate operand illegal with absolute jump"));
3770 if (!i386_immediate (op_string
))
3773 else if (is_digit_char (*op_string
)
3774 || is_identifier_char (*op_string
)
3775 || *op_string
== '(')
3777 /* This is a memory reference of some sort. */
3780 /* Start and end of displacement string expression (if found). */
3781 char *displacement_string_start
;
3782 char *displacement_string_end
;
3784 do_memory_reference
:
3785 if ((i
.mem_operands
== 1
3786 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3787 || i
.mem_operands
== 2)
3789 as_bad (_("too many memory references for `%s'"),
3790 current_templates
->start
->name
);
3794 /* Check for base index form. We detect the base index form by
3795 looking for an ')' at the end of the operand, searching
3796 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3798 base_string
= op_string
+ strlen (op_string
);
3801 if (is_space_char (*base_string
))
3804 /* If we only have a displacement, set-up for it to be parsed later. */
3805 displacement_string_start
= op_string
;
3806 displacement_string_end
= base_string
+ 1;
3808 if (*base_string
== ')')
3811 unsigned int parens_balanced
= 1;
3812 /* We've already checked that the number of left & right ()'s are
3813 equal, so this loop will not be infinite. */
3817 if (*base_string
== ')')
3819 if (*base_string
== '(')
3822 while (parens_balanced
);
3824 temp_string
= base_string
;
3826 /* Skip past '(' and whitespace. */
3828 if (is_space_char (*base_string
))
3831 if (*base_string
== ','
3832 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3833 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3835 displacement_string_end
= temp_string
;
3837 i
.types
[this_operand
] |= BaseIndex
;
3841 base_string
= end_op
;
3842 if (is_space_char (*base_string
))
3846 /* There may be an index reg or scale factor here. */
3847 if (*base_string
== ',')
3850 if (is_space_char (*base_string
))
3853 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3854 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3856 base_string
= end_op
;
3857 if (is_space_char (*base_string
))
3859 if (*base_string
== ',')
3862 if (is_space_char (*base_string
))
3865 else if (*base_string
!= ')')
3867 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3872 else if (*base_string
== REGISTER_PREFIX
)
3874 as_bad (_("bad register name `%s'"), base_string
);
3878 /* Check for scale factor. */
3879 if (*base_string
!= ')')
3881 char *end_scale
= i386_scale (base_string
);
3886 base_string
= end_scale
;
3887 if (is_space_char (*base_string
))
3889 if (*base_string
!= ')')
3891 as_bad (_("expecting `)' after scale factor in `%s'"),
3896 else if (!i
.index_reg
)
3898 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3903 else if (*base_string
!= ')')
3905 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3910 else if (*base_string
== REGISTER_PREFIX
)
3912 as_bad (_("bad register name `%s'"), base_string
);
3917 /* If there's an expression beginning the operand, parse it,
3918 assuming displacement_string_start and
3919 displacement_string_end are meaningful. */
3920 if (displacement_string_start
!= displacement_string_end
)
3922 if (!i386_displacement (displacement_string_start
,
3923 displacement_string_end
))
3927 /* Special case for (%dx) while doing input/output op. */
3929 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3931 && i
.log2_scale_factor
== 0
3932 && i
.seg
[i
.mem_operands
] == 0
3933 && (i
.types
[this_operand
] & Disp
) == 0)
3935 i
.types
[this_operand
] = InOutPortReg
;
3939 if (i386_index_check (operand_string
) == 0)
3945 /* It's not a memory operand; argh! */
3946 as_bad (_("invalid char %s beginning operand %d `%s'"),
3947 output_invalid (*op_string
),
3952 return 1; /* Normal return. */
3955 /* md_estimate_size_before_relax()
3957 Called just before relax() for rs_machine_dependent frags. The x86
3958 assembler uses these frags to handle variable size jump
3961 Any symbol that is now undefined will not become defined.
3962 Return the correct fr_subtype in the frag.
3963 Return the initial "guess for variable size of frag" to caller.
3964 The guess is actually the growth beyond the fixed part. Whatever
3965 we do to grow the fixed or variable part contributes to our
3969 md_estimate_size_before_relax (fragP
, segment
)
3970 register fragS
*fragP
;
3971 register segT segment
;
3973 /* We've already got fragP->fr_subtype right; all we have to do is
3974 check for un-relaxable symbols. On an ELF system, we can't relax
3975 an externally visible symbol, because it may be overridden by a
3977 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3979 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3980 || S_IS_WEAK (fragP
->fr_symbol
)
3984 /* Symbol is undefined in this segment, or we need to keep a
3985 reloc so that weak symbols can be overridden. */
3986 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3987 RELOC_ENUM reloc_type
;
3988 unsigned char *opcode
;
3991 if (fragP
->fr_var
!= NO_RELOC
)
3992 reloc_type
= fragP
->fr_var
;
3994 reloc_type
= BFD_RELOC_16_PCREL
;
3996 reloc_type
= BFD_RELOC_32_PCREL
;
3998 old_fr_fix
= fragP
->fr_fix
;
3999 opcode
= (unsigned char *) fragP
->fr_opcode
;
4001 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4004 /* Make jmp (0xeb) a (d)word displacement jump. */
4006 fragP
->fr_fix
+= size
;
4007 fix_new (fragP
, old_fr_fix
, size
,
4009 fragP
->fr_offset
, 1,
4014 if (no_cond_jump_promotion
)
4019 /* Negate the condition, and branch past an
4020 unconditional jump. */
4023 /* Insert an unconditional jump. */
4025 /* We added two extra opcode bytes, and have a two byte
4027 fragP
->fr_fix
+= 2 + 2;
4028 fix_new (fragP
, old_fr_fix
+ 2, 2,
4030 fragP
->fr_offset
, 1,
4037 if (no_cond_jump_promotion
)
4040 /* This changes the byte-displacement jump 0x7N
4041 to the (d)word-displacement jump 0x0f,0x8N. */
4042 opcode
[1] = opcode
[0] + 0x10;
4043 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4044 /* We've added an opcode byte. */
4045 fragP
->fr_fix
+= 1 + size
;
4046 fix_new (fragP
, old_fr_fix
+ 1, size
,
4048 fragP
->fr_offset
, 1,
4053 BAD_CASE (fragP
->fr_subtype
);
4057 return fragP
->fr_fix
- old_fr_fix
;
4061 /* Guess size depending on current relax state. Initially the relax
4062 state will correspond to a short jump and we return 1, because
4063 the variable part of the frag (the branch offset) is one byte
4064 long. However, we can relax a section more than once and in that
4065 case we must either set fr_subtype back to the unrelaxed state,
4066 or return the value for the appropriate branch. */
4067 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4070 /* Called after relax() is finished.
4072 In: Address of frag.
4073 fr_type == rs_machine_dependent.
4074 fr_subtype is what the address relaxed to.
4076 Out: Any fixSs and constants are set up.
4077 Caller will turn frag into a ".space 0". */
4079 #ifndef BFD_ASSEMBLER
4081 md_convert_frag (headers
, sec
, fragP
)
4082 object_headers
*headers ATTRIBUTE_UNUSED
;
4083 segT sec ATTRIBUTE_UNUSED
;
4084 register fragS
*fragP
;
4087 md_convert_frag (abfd
, sec
, fragP
)
4088 bfd
*abfd ATTRIBUTE_UNUSED
;
4089 segT sec ATTRIBUTE_UNUSED
;
4090 register fragS
*fragP
;
4093 register unsigned char *opcode
;
4094 unsigned char *where_to_put_displacement
= NULL
;
4095 offsetT target_address
;
4096 offsetT opcode_address
;
4097 unsigned int extension
= 0;
4098 offsetT displacement_from_opcode_start
;
4100 opcode
= (unsigned char *) fragP
->fr_opcode
;
4102 /* Address we want to reach in file space. */
4103 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4105 /* Address opcode resides at in file space. */
4106 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4108 /* Displacement from opcode start to fill into instruction. */
4109 displacement_from_opcode_start
= target_address
- opcode_address
;
4111 if ((fragP
->fr_subtype
& BIG
) == 0)
4113 /* Don't have to change opcode. */
4114 extension
= 1; /* 1 opcode + 1 displacement */
4115 where_to_put_displacement
= &opcode
[1];
4119 if (no_cond_jump_promotion
4120 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4121 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4123 switch (fragP
->fr_subtype
)
4125 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4126 extension
= 4; /* 1 opcode + 4 displacement */
4128 where_to_put_displacement
= &opcode
[1];
4131 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4132 extension
= 2; /* 1 opcode + 2 displacement */
4134 where_to_put_displacement
= &opcode
[1];
4137 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4138 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4139 extension
= 5; /* 2 opcode + 4 displacement */
4140 opcode
[1] = opcode
[0] + 0x10;
4141 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4142 where_to_put_displacement
= &opcode
[2];
4145 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4146 extension
= 3; /* 2 opcode + 2 displacement */
4147 opcode
[1] = opcode
[0] + 0x10;
4148 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4149 where_to_put_displacement
= &opcode
[2];
4152 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4157 where_to_put_displacement
= &opcode
[3];
4161 BAD_CASE (fragP
->fr_subtype
);
4166 /* Now put displacement after opcode. */
4167 md_number_to_chars ((char *) where_to_put_displacement
,
4168 (valueT
) (displacement_from_opcode_start
- extension
),
4169 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4170 fragP
->fr_fix
+= extension
;
4173 /* Size of byte displacement jmp. */
4174 int md_short_jump_size
= 2;
4176 /* Size of dword displacement jmp. */
4177 int md_long_jump_size
= 5;
4179 /* Size of relocation record. */
4180 const int md_reloc_size
= 8;
4183 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4185 addressT from_addr
, to_addr
;
4186 fragS
*frag ATTRIBUTE_UNUSED
;
4187 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4191 offset
= to_addr
- (from_addr
+ 2);
4192 /* Opcode for byte-disp jump. */
4193 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4194 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4198 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4200 addressT from_addr
, to_addr
;
4201 fragS
*frag ATTRIBUTE_UNUSED
;
4202 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4206 offset
= to_addr
- (from_addr
+ 5);
4207 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4208 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4211 /* Apply a fixup (fixS) to segment data, once it has been determined
4212 by our caller that we have all the info we need to fix it up.
4214 On the 386, immediates, displacements, and data pointers are all in
4215 the same (little-endian) format, so we don't need to care about which
4219 md_apply_fix3 (fixP
, valp
, seg
)
4220 /* The fix we're to put in. */
4223 /* Pointer to the value of the bits. */
4226 /* Segment fix is from. */
4227 segT seg ATTRIBUTE_UNUSED
;
4229 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4230 valueT value
= *valp
;
4232 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4235 switch (fixP
->fx_r_type
)
4241 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4244 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4247 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4252 /* This is a hack. There should be a better way to handle this.
4253 This covers for the fact that bfd_install_relocation will
4254 subtract the current location (for partial_inplace, PC relative
4255 relocations); see more below. */
4256 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4257 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4258 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4259 && fixP
->fx_addsy
&& !use_rela_relocations
)
4262 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4264 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4267 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4269 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4270 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4272 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4275 || (symbol_section_p (fixP
->fx_addsy
)
4276 && fseg
!= absolute_section
))
4277 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4278 && ! S_IS_WEAK (fixP
->fx_addsy
)
4279 && S_IS_DEFINED (fixP
->fx_addsy
)
4280 && ! S_IS_COMMON (fixP
->fx_addsy
))
4282 /* Yes, we add the values in twice. This is because
4283 bfd_perform_relocation subtracts them out again. I think
4284 bfd_perform_relocation is broken, but I don't dare change
4286 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4290 #if defined (OBJ_COFF) && defined (TE_PE)
4291 /* For some reason, the PE format does not store a section
4292 address offset for a PC relative symbol. */
4293 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4294 value
+= md_pcrel_from (fixP
);
4298 /* Fix a few things - the dynamic linker expects certain values here,
4299 and we must not dissappoint it. */
4300 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4301 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4303 switch (fixP
->fx_r_type
)
4305 case BFD_RELOC_386_PLT32
:
4306 case BFD_RELOC_X86_64_PLT32
:
4307 /* Make the jump instruction point to the address of the operand. At
4308 runtime we merely add the offset to the actual PLT entry. */
4311 case BFD_RELOC_386_GOTPC
:
4313 /* This is tough to explain. We end up with this one if we have
4314 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4315 * here is to obtain the absolute address of the GOT, and it is strongly
4316 * preferable from a performance point of view to avoid using a runtime
4317 * relocation for this. The actual sequence of instructions often look
4323 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4325 * The call and pop essentially return the absolute address of
4326 * the label .L66 and store it in %ebx. The linker itself will
4327 * ultimately change the first operand of the addl so that %ebx points to
4328 * the GOT, but to keep things simple, the .o file must have this operand
4329 * set so that it generates not the absolute address of .L66, but the
4330 * absolute address of itself. This allows the linker itself simply
4331 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4332 * added in, and the addend of the relocation is stored in the operand
4333 * field for the instruction itself.
4335 * Our job here is to fix the operand so that it would add the correct
4336 * offset so that %ebx would point to itself. The thing that is tricky is
4337 * that .-.L66 will point to the beginning of the instruction, so we need
4338 * to further modify the operand so that it will point to itself.
4339 * There are other cases where you have something like:
4341 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4343 * and here no correction would be required. Internally in the assembler
4344 * we treat operands of this form as not being pcrel since the '.' is
4345 * explicitly mentioned, and I wonder whether it would simplify matters
4346 * to do it this way. Who knows. In earlier versions of the PIC patches,
4347 * the pcrel_adjust field was used to store the correction, but since the
4348 * expression is not pcrel, I felt it would be confusing to do it this
4353 case BFD_RELOC_386_GOT32
:
4354 case BFD_RELOC_X86_64_GOT32
:
4355 value
= 0; /* Fully resolved at runtime. No addend. */
4357 case BFD_RELOC_386_GOTOFF
:
4358 case BFD_RELOC_X86_64_GOTPCREL
:
4361 case BFD_RELOC_VTABLE_INHERIT
:
4362 case BFD_RELOC_VTABLE_ENTRY
:
4369 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4371 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4373 #ifndef BFD_ASSEMBLER
4374 md_number_to_chars (p
, value
, fixP
->fx_size
);
4376 /* Are we finished with this relocation now? */
4377 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4379 else if (use_rela_relocations
)
4381 fixP
->fx_no_overflow
= 1;
4384 md_number_to_chars (p
, value
, fixP
->fx_size
);
4390 #define MAX_LITTLENUMS 6
4392 /* Turn the string pointed to by litP into a floating point constant
4393 of type TYPE, and emit the appropriate bytes. The number of
4394 LITTLENUMS emitted is stored in *SIZEP. An error message is
4395 returned, or NULL on OK. */
4398 md_atof (type
, litP
, sizeP
)
4404 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4405 LITTLENUM_TYPE
*wordP
;
4427 return _("Bad call to md_atof ()");
4429 t
= atof_ieee (input_line_pointer
, type
, words
);
4431 input_line_pointer
= t
;
4433 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4434 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4435 the bigendian 386. */
4436 for (wordP
= words
+ prec
- 1; prec
--;)
4438 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4439 litP
+= sizeof (LITTLENUM_TYPE
);
4444 char output_invalid_buf
[8];
4451 sprintf (output_invalid_buf
, "'%c'", c
);
4453 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4454 return output_invalid_buf
;
4457 /* REG_STRING starts *before* REGISTER_PREFIX. */
4459 static const reg_entry
*
4460 parse_register (reg_string
, end_op
)
4464 char *s
= reg_string
;
4466 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4469 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4470 if (*s
== REGISTER_PREFIX
)
4473 if (is_space_char (*s
))
4477 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4479 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4480 return (const reg_entry
*) NULL
;
4484 /* For naked regs, make sure that we are not dealing with an identifier.
4485 This prevents confusing an identifier like `eax_var' with register
4487 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4488 return (const reg_entry
*) NULL
;
4492 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4494 /* Handle floating point regs, allowing spaces in the (i) part. */
4495 if (r
== i386_regtab
/* %st is first entry of table */)
4497 if (is_space_char (*s
))
4502 if (is_space_char (*s
))
4504 if (*s
>= '0' && *s
<= '7')
4506 r
= &i386_float_regtab
[*s
- '0'];
4508 if (is_space_char (*s
))
4516 /* We have "%st(" then garbage. */
4517 return (const reg_entry
*) NULL
;
4522 && r
->reg_flags
& (RegRex64
|RegRex
)
4523 && flag_code
!= CODE_64BIT
)
4525 return (const reg_entry
*) NULL
;
4531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4532 const char *md_shortopts
= "kVQ:sq";
4534 const char *md_shortopts
= "q";
4537 struct option md_longopts
[] = {
4538 #define OPTION_32 (OPTION_MD_BASE + 0)
4539 {"32", no_argument
, NULL
, OPTION_32
},
4540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4541 #define OPTION_64 (OPTION_MD_BASE + 1)
4542 {"64", no_argument
, NULL
, OPTION_64
},
4544 {NULL
, no_argument
, NULL
, 0}
4546 size_t md_longopts_size
= sizeof (md_longopts
);
4549 md_parse_option (c
, arg
)
4551 char *arg ATTRIBUTE_UNUSED
;
4559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4560 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4561 should be emitted or not. FIXME: Not implemented. */
4565 /* -V: SVR4 argument to print version ID. */
4567 print_version_id ();
4570 /* -k: Ignore for FreeBSD compatibility. */
4575 /* -s: On i386 Solaris, this tells the native assembler to use
4576 .stab instead of .stab.excl. We always use .stab anyhow. */
4581 const char **list
, **l
;
4583 list
= bfd_target_list ();
4584 for (l
= list
; *l
!= NULL
; l
++)
4585 if (strcmp (*l
, "elf64-x86-64") == 0)
4587 default_arch
= "x86_64";
4591 as_fatal (_("No compiled in support for x86_64"));
4598 default_arch
= "i386";
4608 md_show_usage (stream
)
4611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4612 fprintf (stream
, _("\
4614 -V print assembler version number\n\
4616 -q quieten some warnings\n\
4619 fprintf (stream
, _("\
4620 -q quieten some warnings\n"));
4624 #ifdef BFD_ASSEMBLER
4625 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4626 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4628 /* Pick the target format to use. */
4631 i386_target_format ()
4633 if (!strcmp (default_arch
, "x86_64"))
4634 set_code_flag (CODE_64BIT
);
4635 else if (!strcmp (default_arch
, "i386"))
4636 set_code_flag (CODE_32BIT
);
4638 as_fatal (_("Unknown architecture"));
4639 switch (OUTPUT_FLAVOR
)
4641 #ifdef OBJ_MAYBE_AOUT
4642 case bfd_target_aout_flavour
:
4643 return AOUT_TARGET_FORMAT
;
4645 #ifdef OBJ_MAYBE_COFF
4646 case bfd_target_coff_flavour
:
4649 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4650 case bfd_target_elf_flavour
:
4652 if (flag_code
== CODE_64BIT
)
4653 use_rela_relocations
= 1;
4654 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4663 #endif /* OBJ_MAYBE_ more than one */
4664 #endif /* BFD_ASSEMBLER */
4667 md_undefined_symbol (name
)
4670 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4671 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4672 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4673 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4677 if (symbol_find (name
))
4678 as_bad (_("GOT already in symbol table"));
4679 GOT_symbol
= symbol_new (name
, undefined_section
,
4680 (valueT
) 0, &zero_address_frag
);
4687 /* Round up a section size to the appropriate boundary. */
4690 md_section_align (segment
, size
)
4691 segT segment ATTRIBUTE_UNUSED
;
4694 #ifdef BFD_ASSEMBLER
4695 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4696 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4698 /* For a.out, force the section size to be aligned. If we don't do
4699 this, BFD will align it for us, but it will not write out the
4700 final bytes of the section. This may be a bug in BFD, but it is
4701 easier to fix it here since that is how the other a.out targets
4705 align
= bfd_get_section_alignment (stdoutput
, segment
);
4706 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4714 /* On the i386, PC-relative offsets are relative to the start of the
4715 next instruction. That is, the address of the offset, plus its
4716 size, since the offset is always the last part of the insn. */
4719 md_pcrel_from (fixP
)
4722 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4729 int ignore ATTRIBUTE_UNUSED
;
4733 temp
= get_absolute_expression ();
4734 subseg_set (bss_section
, (subsegT
) temp
);
4735 demand_empty_rest_of_line ();
4740 #ifdef BFD_ASSEMBLER
4743 i386_validate_fix (fixp
)
4746 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4748 /* GOTOFF relocation are nonsense in 64bit mode. */
4749 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4751 if (flag_code
!= CODE_64BIT
)
4753 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4757 if (flag_code
== CODE_64BIT
)
4759 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4766 tc_gen_reloc (section
, fixp
)
4767 asection
*section ATTRIBUTE_UNUSED
;
4771 bfd_reloc_code_real_type code
;
4773 switch (fixp
->fx_r_type
)
4775 case BFD_RELOC_X86_64_PLT32
:
4776 case BFD_RELOC_X86_64_GOT32
:
4777 case BFD_RELOC_X86_64_GOTPCREL
:
4778 case BFD_RELOC_386_PLT32
:
4779 case BFD_RELOC_386_GOT32
:
4780 case BFD_RELOC_386_GOTOFF
:
4781 case BFD_RELOC_386_GOTPC
:
4782 case BFD_RELOC_X86_64_32S
:
4784 case BFD_RELOC_VTABLE_ENTRY
:
4785 case BFD_RELOC_VTABLE_INHERIT
:
4786 code
= fixp
->fx_r_type
;
4791 switch (fixp
->fx_size
)
4794 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4795 _("can not do %d byte pc-relative relocation"),
4797 code
= BFD_RELOC_32_PCREL
;
4799 case 1: code
= BFD_RELOC_8_PCREL
; break;
4800 case 2: code
= BFD_RELOC_16_PCREL
; break;
4801 case 4: code
= BFD_RELOC_32_PCREL
; break;
4806 switch (fixp
->fx_size
)
4809 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4810 _("can not do %d byte relocation"),
4812 code
= BFD_RELOC_32
;
4814 case 1: code
= BFD_RELOC_8
; break;
4815 case 2: code
= BFD_RELOC_16
; break;
4816 case 4: code
= BFD_RELOC_32
; break;
4817 case 8: code
= BFD_RELOC_64
; break;
4823 if (code
== BFD_RELOC_32
4825 && fixp
->fx_addsy
== GOT_symbol
)
4827 /* We don't support GOTPC on 64bit targets. */
4828 if (flag_code
== CODE_64BIT
)
4830 code
= BFD_RELOC_386_GOTPC
;
4833 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4834 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4835 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4837 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4838 if (!use_rela_relocations
)
4840 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4841 vtable entry to be used in the relocation's section offset. */
4842 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4843 rel
->address
= fixp
->fx_offset
;
4846 rel
->addend
= fixp
->fx_addnumber
;
4850 /* Use the rela in 64bit mode. */
4853 rel
->addend
= fixp
->fx_offset
;
4855 rel
->addend
-= fixp
->fx_size
;
4858 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4859 if (rel
->howto
== NULL
)
4861 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4862 _("cannot represent relocation type %s"),
4863 bfd_get_reloc_code_name (code
));
4864 /* Set howto to a garbage value so that we can keep going. */
4865 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4866 assert (rel
->howto
!= NULL
);
4872 #else /* ! BFD_ASSEMBLER */
4874 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4876 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4879 relax_addressT segment_address_in_file
;
4881 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4882 Out: GNU LD relocation length code: 0, 1, or 2. */
4884 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4887 know (fixP
->fx_addsy
!= NULL
);
4889 md_number_to_chars (where
,
4890 (valueT
) (fixP
->fx_frag
->fr_address
4891 + fixP
->fx_where
- segment_address_in_file
),
4894 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4895 ? S_GET_TYPE (fixP
->fx_addsy
)
4896 : fixP
->fx_addsy
->sy_number
);
4898 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4899 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4900 where
[4] = r_symbolnum
& 0x0ff;
4901 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4902 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4903 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4906 #endif /* OBJ_AOUT or OBJ_BOUT. */
4908 #if defined (I386COFF)
4911 tc_coff_fix2rtype (fixP
)
4914 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4917 return (fixP
->fx_pcrel
?
4918 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4919 fixP
->fx_size
== 2 ? R_PCRWORD
:
4921 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4922 fixP
->fx_size
== 2 ? R_RELWORD
:
4927 tc_coff_sizemachdep (frag
)
4931 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4936 #endif /* I386COFF */
4938 #endif /* ! BFD_ASSEMBLER */
4940 /* Parse operands using Intel syntax. This implements a recursive descent
4941 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4944 FIXME: We do not recognize the full operand grammar defined in the MASM
4945 documentation. In particular, all the structure/union and
4946 high-level macro operands are missing.
4948 Uppercase words are terminals, lower case words are non-terminals.
4949 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4950 bars '|' denote choices. Most grammar productions are implemented in
4951 functions called 'intel_<production>'.
4953 Initial production is 'expr'.
4959 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4961 constant digits [[ radixOverride ]]
4963 dataType BYTE | WORD | DWORD | QWORD | XWORD
4996 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4997 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4999 hexdigit a | b | c | d | e | f
5000 | A | B | C | D | E | F
5010 register specialRegister
5014 segmentRegister CS | DS | ES | FS | GS | SS
5016 specialRegister CR0 | CR2 | CR3
5017 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5018 | TR3 | TR4 | TR5 | TR6 | TR7
5020 We simplify the grammar in obvious places (e.g., register parsing is
5021 done by calling parse_register) and eliminate immediate left recursion
5022 to implement a recursive-descent parser.
5062 /* Parsing structure for the intel syntax parser. Used to implement the
5063 semantic actions for the operand grammar. */
5064 struct intel_parser_s
5066 char *op_string
; /* The string being parsed. */
5067 int got_a_float
; /* Whether the operand is a float. */
5068 int op_modifier
; /* Operand modifier. */
5069 int is_mem
; /* 1 if operand is memory reference. */
5070 const reg_entry
*reg
; /* Last register reference found. */
5071 char *disp
; /* Displacement string being built. */
5074 static struct intel_parser_s intel_parser
;
5076 /* Token structure for parsing intel syntax. */
5079 int code
; /* Token code. */
5080 const reg_entry
*reg
; /* Register entry for register tokens. */
5081 char *str
; /* String representation. */
5084 static struct intel_token cur_token
, prev_token
;
5086 /* Token codes for the intel parser. Since T_SHORT is already used
5087 by COFF, undefine it first to prevent a warning. */
5102 /* Prototypes for intel parser functions. */
5103 static int intel_match_token
PARAMS ((int code
));
5104 static void intel_get_token
PARAMS ((void));
5105 static void intel_putback_token
PARAMS ((void));
5106 static int intel_expr
PARAMS ((void));
5107 static int intel_e05
PARAMS ((void));
5108 static int intel_e05_1
PARAMS ((void));
5109 static int intel_e06
PARAMS ((void));
5110 static int intel_e06_1
PARAMS ((void));
5111 static int intel_e09
PARAMS ((void));
5112 static int intel_e09_1
PARAMS ((void));
5113 static int intel_e10
PARAMS ((void));
5114 static int intel_e10_1
PARAMS ((void));
5115 static int intel_e11
PARAMS ((void));
5118 i386_intel_operand (operand_string
, got_a_float
)
5119 char *operand_string
;
5125 /* Initialize token holders. */
5126 cur_token
.code
= prev_token
.code
= T_NIL
;
5127 cur_token
.reg
= prev_token
.reg
= NULL
;
5128 cur_token
.str
= prev_token
.str
= NULL
;
5130 /* Initialize parser structure. */
5131 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5134 strcpy (intel_parser
.op_string
, operand_string
);
5135 intel_parser
.got_a_float
= got_a_float
;
5136 intel_parser
.op_modifier
= -1;
5137 intel_parser
.is_mem
= 0;
5138 intel_parser
.reg
= NULL
;
5139 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5140 if (intel_parser
.disp
== NULL
)
5142 intel_parser
.disp
[0] = '\0';
5144 /* Read the first token and start the parser. */
5146 ret
= intel_expr ();
5150 /* If we found a memory reference, hand it over to i386_displacement
5151 to fill in the rest of the operand fields. */
5152 if (intel_parser
.is_mem
)
5154 if ((i
.mem_operands
== 1
5155 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5156 || i
.mem_operands
== 2)
5158 as_bad (_("too many memory references for '%s'"),
5159 current_templates
->start
->name
);
5164 char *s
= intel_parser
.disp
;
5167 /* Add the displacement expression. */
5169 ret
= i386_displacement (s
, s
+ strlen (s
))
5170 && i386_index_check (s
);
5174 /* Constant and OFFSET expressions are handled by i386_immediate. */
5175 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5176 || intel_parser
.reg
== NULL
)
5177 ret
= i386_immediate (intel_parser
.disp
);
5181 free (intel_parser
.disp
);
5191 /* expr SHORT e05 */
5192 if (cur_token
.code
== T_SHORT
)
5194 intel_parser
.op_modifier
= SHORT
;
5195 intel_match_token (T_SHORT
);
5197 return (intel_e05 ());
5202 return intel_e05 ();
5212 return (intel_e06 () && intel_e05_1 ());
5218 /* e05' addOp e06 e05' */
5219 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5221 strcat (intel_parser
.disp
, cur_token
.str
);
5222 intel_match_token (cur_token
.code
);
5224 return (intel_e06 () && intel_e05_1 ());
5239 return (intel_e09 () && intel_e06_1 ());
5245 /* e06' mulOp e09 e06' */
5246 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5248 strcat (intel_parser
.disp
, cur_token
.str
);
5249 intel_match_token (cur_token
.code
);
5251 return (intel_e09 () && intel_e06_1 ());
5259 /* e09 OFFSET e10 e09'
5268 /* e09 OFFSET e10 e09' */
5269 if (cur_token
.code
== T_OFFSET
)
5271 intel_parser
.is_mem
= 0;
5272 intel_parser
.op_modifier
= OFFSET_FLAT
;
5273 intel_match_token (T_OFFSET
);
5275 return (intel_e10 () && intel_e09_1 ());
5280 return (intel_e10 () && intel_e09_1 ());
5286 /* e09' PTR e10 e09' */
5287 if (cur_token
.code
== T_PTR
)
5289 if (prev_token
.code
== T_BYTE
)
5290 i
.suffix
= BYTE_MNEM_SUFFIX
;
5292 else if (prev_token
.code
== T_WORD
)
5294 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5295 i
.suffix
= SHORT_MNEM_SUFFIX
;
5297 i
.suffix
= WORD_MNEM_SUFFIX
;
5300 else if (prev_token
.code
== T_DWORD
)
5302 if (intel_parser
.got_a_float
== 1) /* "f..." */
5303 i
.suffix
= SHORT_MNEM_SUFFIX
;
5305 i
.suffix
= LONG_MNEM_SUFFIX
;
5308 else if (prev_token
.code
== T_QWORD
)
5310 if (intel_parser
.got_a_float
== 1) /* "f..." */
5311 i
.suffix
= LONG_MNEM_SUFFIX
;
5313 i
.suffix
= QWORD_MNEM_SUFFIX
;
5316 else if (prev_token
.code
== T_XWORD
)
5317 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5321 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5325 intel_match_token (T_PTR
);
5327 return (intel_e10 () && intel_e09_1 ());
5330 /* e09 : e10 e09' */
5331 else if (cur_token
.code
== ':')
5333 /* Mark as a memory operand only if it's not already known to be an
5334 offset expression. */
5335 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5336 intel_parser
.is_mem
= 1;
5338 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5353 return (intel_e11 () && intel_e10_1 ());
5359 /* e10' [ expr ] e10' */
5360 if (cur_token
.code
== '[')
5362 intel_match_token ('[');
5364 /* Mark as a memory operand only if it's not already known to be an
5365 offset expression. If it's an offset expression, we need to keep
5367 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5368 intel_parser
.is_mem
= 1;
5370 strcat (intel_parser
.disp
, "[");
5372 /* Add a '+' to the displacement string if necessary. */
5373 if (*intel_parser
.disp
!= '\0'
5374 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5375 strcat (intel_parser
.disp
, "+");
5377 if (intel_expr () && intel_match_token (']'))
5379 /* Preserve brackets when the operand is an offset expression. */
5380 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5381 strcat (intel_parser
.disp
, "]");
5383 return intel_e10_1 ();
5410 if (cur_token
.code
== '(')
5412 intel_match_token ('(');
5413 strcat (intel_parser
.disp
, "(");
5415 if (intel_expr () && intel_match_token (')'))
5417 strcat (intel_parser
.disp
, ")");
5425 else if (cur_token
.code
== '[')
5427 intel_match_token ('[');
5429 /* Mark as a memory operand only if it's not already known to be an
5430 offset expression. If it's an offset expression, we need to keep
5432 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5433 intel_parser
.is_mem
= 1;
5435 strcat (intel_parser
.disp
, "[");
5437 /* Operands for jump/call inside brackets denote absolute addresses. */
5438 if (current_templates
->start
->opcode_modifier
& Jump
5439 || current_templates
->start
->opcode_modifier
& JumpDword
5440 || current_templates
->start
->opcode_modifier
& JumpByte
5441 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5442 i
.types
[this_operand
] |= JumpAbsolute
;
5444 /* Add a '+' to the displacement string if necessary. */
5445 if (*intel_parser
.disp
!= '\0'
5446 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5447 strcat (intel_parser
.disp
, "+");
5449 if (intel_expr () && intel_match_token (']'))
5451 /* Preserve brackets when the operand is an offset expression. */
5452 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5453 strcat (intel_parser
.disp
, "]");
5466 else if (cur_token
.code
== T_BYTE
5467 || cur_token
.code
== T_WORD
5468 || cur_token
.code
== T_DWORD
5469 || cur_token
.code
== T_QWORD
5470 || cur_token
.code
== T_XWORD
)
5472 intel_match_token (cur_token
.code
);
5479 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5481 strcat (intel_parser
.disp
, cur_token
.str
);
5482 intel_match_token (cur_token
.code
);
5484 /* Mark as a memory operand only if it's not already known to be an
5485 offset expression. */
5486 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5487 intel_parser
.is_mem
= 1;
5493 else if (cur_token
.code
== T_REG
)
5495 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5497 intel_match_token (T_REG
);
5499 /* Check for segment change. */
5500 if (cur_token
.code
== ':')
5502 if (reg
->reg_type
& (SReg2
| SReg3
))
5504 switch (reg
->reg_num
)
5507 i
.seg
[i
.mem_operands
] = &es
;
5510 i
.seg
[i
.mem_operands
] = &cs
;
5513 i
.seg
[i
.mem_operands
] = &ss
;
5516 i
.seg
[i
.mem_operands
] = &ds
;
5519 i
.seg
[i
.mem_operands
] = &fs
;
5522 i
.seg
[i
.mem_operands
] = &gs
;
5528 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5533 /* Not a segment register. Check for register scaling. */
5534 else if (cur_token
.code
== '*')
5536 if (!intel_parser
.is_mem
)
5538 as_bad (_("Register scaling only allowed in memory operands."));
5542 /* What follows must be a valid scale. */
5543 if (intel_match_token ('*')
5544 && strchr ("01248", *cur_token
.str
))
5547 i
.types
[this_operand
] |= BaseIndex
;
5549 /* Set the scale after setting the register (otherwise,
5550 i386_scale will complain) */
5551 i386_scale (cur_token
.str
);
5552 intel_match_token (T_CONST
);
5556 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5562 /* No scaling. If this is a memory operand, the register is either a
5563 base register (first occurrence) or an index register (second
5565 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5567 if (i
.base_reg
&& i
.index_reg
)
5569 as_bad (_("Too many register references in memory operand.\n"));
5573 if (i
.base_reg
== NULL
)
5578 i
.types
[this_operand
] |= BaseIndex
;
5581 /* Offset modifier. Add the register to the displacement string to be
5582 parsed as an immediate expression after we're done. */
5583 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5584 strcat (intel_parser
.disp
, reg
->reg_name
);
5586 /* It's neither base nor index nor offset. */
5589 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5590 i
.op
[this_operand
].regs
= reg
;
5594 /* Since registers are not part of the displacement string (except
5595 when we're parsing offset operands), we may need to remove any
5596 preceding '+' from the displacement string. */
5597 if (*intel_parser
.disp
!= '\0'
5598 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5600 char *s
= intel_parser
.disp
;
5601 s
+= strlen (s
) - 1;
5610 else if (cur_token
.code
== T_ID
)
5612 /* Add the identifier to the displacement string. */
5613 strcat (intel_parser
.disp
, cur_token
.str
);
5614 intel_match_token (T_ID
);
5616 /* The identifier represents a memory reference only if it's not
5617 preceded by an offset modifier. */
5618 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5619 intel_parser
.is_mem
= 1;
5625 else if (cur_token
.code
== T_CONST
5626 || cur_token
.code
== '-'
5627 || cur_token
.code
== '+')
5631 /* Allow constants that start with `+' or `-'. */
5632 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5634 strcat (intel_parser
.disp
, cur_token
.str
);
5635 intel_match_token (cur_token
.code
);
5636 if (cur_token
.code
!= T_CONST
)
5638 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5644 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5645 if (save_str
== NULL
)
5647 strcpy (save_str
, cur_token
.str
);
5649 /* Get the next token to check for register scaling. */
5650 intel_match_token (cur_token
.code
);
5652 /* Check if this constant is a scaling factor for an index register. */
5653 if (cur_token
.code
== '*')
5655 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5657 if (!intel_parser
.is_mem
)
5659 as_bad (_("Register scaling only allowed in memory operands."));
5663 /* The constant is followed by `* reg', so it must be
5665 if (strchr ("01248", *save_str
))
5667 i
.index_reg
= cur_token
.reg
;
5668 i
.types
[this_operand
] |= BaseIndex
;
5670 /* Set the scale after setting the register (otherwise,
5671 i386_scale will complain) */
5672 i386_scale (save_str
);
5673 intel_match_token (T_REG
);
5675 /* Since registers are not part of the displacement
5676 string, we may need to remove any preceding '+' from
5677 the displacement string. */
5678 if (*intel_parser
.disp
!= '\0')
5680 char *s
= intel_parser
.disp
;
5681 s
+= strlen (s
) - 1;
5694 /* The constant was not used for register scaling. Since we have
5695 already consumed the token following `*' we now need to put it
5696 back in the stream. */
5698 intel_putback_token ();
5701 /* Add the constant to the displacement string. */
5702 strcat (intel_parser
.disp
, save_str
);
5708 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5712 /* Match the given token against cur_token. If they match, read the next
5713 token from the operand string. */
5715 intel_match_token (code
)
5718 if (cur_token
.code
== code
)
5725 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5730 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5735 const reg_entry
*reg
;
5736 struct intel_token new_token
;
5738 new_token
.code
= T_NIL
;
5739 new_token
.reg
= NULL
;
5740 new_token
.str
= NULL
;
5742 /* Free the memory allocated to the previous token and move
5743 cur_token to prev_token. */
5745 free (prev_token
.str
);
5747 prev_token
= cur_token
;
5749 /* Skip whitespace. */
5750 while (is_space_char (*intel_parser
.op_string
))
5751 intel_parser
.op_string
++;
5753 /* Return an empty token if we find nothing else on the line. */
5754 if (*intel_parser
.op_string
== '\0')
5756 cur_token
= new_token
;
5760 /* The new token cannot be larger than the remainder of the operand
5762 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5763 if (new_token
.str
== NULL
)
5765 new_token
.str
[0] = '\0';
5767 if (strchr ("0123456789", *intel_parser
.op_string
))
5769 char *p
= new_token
.str
;
5770 char *q
= intel_parser
.op_string
;
5771 new_token
.code
= T_CONST
;
5773 /* Allow any kind of identifier char to encompass floating point and
5774 hexadecimal numbers. */
5775 while (is_identifier_char (*q
))
5779 /* Recognize special symbol names [0-9][bf]. */
5780 if (strlen (intel_parser
.op_string
) == 2
5781 && (intel_parser
.op_string
[1] == 'b'
5782 || intel_parser
.op_string
[1] == 'f'))
5783 new_token
.code
= T_ID
;
5786 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5788 new_token
.code
= *intel_parser
.op_string
;
5789 new_token
.str
[0] = *intel_parser
.op_string
;
5790 new_token
.str
[1] = '\0';
5793 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5794 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5796 new_token
.code
= T_REG
;
5797 new_token
.reg
= reg
;
5799 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5801 new_token
.str
[0] = REGISTER_PREFIX
;
5802 new_token
.str
[1] = '\0';
5805 strcat (new_token
.str
, reg
->reg_name
);
5808 else if (is_identifier_char (*intel_parser
.op_string
))
5810 char *p
= new_token
.str
;
5811 char *q
= intel_parser
.op_string
;
5813 /* A '.' or '$' followed by an identifier char is an identifier.
5814 Otherwise, it's operator '.' followed by an expression. */
5815 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5817 new_token
.code
= *q
;
5818 new_token
.str
[0] = *q
;
5819 new_token
.str
[1] = '\0';
5823 while (is_identifier_char (*q
) || *q
== '@')
5827 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5828 new_token
.code
= T_BYTE
;
5830 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5831 new_token
.code
= T_WORD
;
5833 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5834 new_token
.code
= T_DWORD
;
5836 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5837 new_token
.code
= T_QWORD
;
5839 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5840 new_token
.code
= T_XWORD
;
5842 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5843 new_token
.code
= T_PTR
;
5845 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5846 new_token
.code
= T_SHORT
;
5848 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5850 new_token
.code
= T_OFFSET
;
5852 /* ??? This is not mentioned in the MASM grammar but gcc
5853 makes use of it with -mintel-syntax. OFFSET may be
5854 followed by FLAT: */
5855 if (strncasecmp (q
, " FLAT:", 6) == 0)
5856 strcat (new_token
.str
, " FLAT:");
5859 /* ??? This is not mentioned in the MASM grammar. */
5860 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5861 new_token
.code
= T_OFFSET
;
5864 new_token
.code
= T_ID
;
5869 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5871 intel_parser
.op_string
+= strlen (new_token
.str
);
5872 cur_token
= new_token
;
5875 /* Put cur_token back into the token stream and make cur_token point to
5878 intel_putback_token ()
5880 intel_parser
.op_string
-= strlen (cur_token
.str
);
5881 free (cur_token
.str
);
5882 cur_token
= prev_token
;
5884 /* Forget prev_token. */
5885 prev_token
.code
= T_NIL
;
5886 prev_token
.reg
= NULL
;
5887 prev_token
.str
= NULL
;