1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
308 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
310 /* Non-zero to optimize code alignment. */
311 int optimize_align_code
= 1;
313 /* Non-zero to quieten some warnings. */
314 static int quiet_warnings
= 0;
317 static const char *cpu_arch_name
= NULL
;
318 static const char *cpu_sub_arch_name
= NULL
;
320 /* CPU feature flags. */
321 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
323 /* If set, conditional jumps are not automatically promoted to handle
324 larger than a byte offset. */
325 static unsigned int no_cond_jump_promotion
= 0;
327 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
328 static symbolS
*GOT_symbol
;
330 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
331 unsigned int x86_dwarf2_return_column
;
333 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
334 int x86_cie_data_alignment
;
336 /* Interface to relax_segment.
337 There are 3 major relax states for 386 jump insns because the
338 different types of jumps add different sizes to frags when we're
339 figuring out what sort of jump to choose to reach a given label. */
342 #define UNCOND_JUMP 0
344 #define COND_JUMP86 2
349 #define SMALL16 (SMALL | CODE16)
351 #define BIG16 (BIG | CODE16)
355 #define INLINE __inline__
361 #define ENCODE_RELAX_STATE(type, size) \
362 ((relax_substateT) (((type) << 2) | (size)))
363 #define TYPE_FROM_RELAX_STATE(s) \
365 #define DISP_SIZE_FROM_RELAX_STATE(s) \
366 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
368 /* This table is used by relax_frag to promote short jumps to long
369 ones where necessary. SMALL (short) jumps may be promoted to BIG
370 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
371 don't allow a short jump in a 32 bit code segment to be promoted to
372 a 16 bit offset jump because it's slower (requires data size
373 prefix), and doesn't work, unless the destination is in the bottom
374 64k of the code segment (The top 16 bits of eip are zeroed). */
376 const relax_typeS md_relax_table
[] =
379 1) most positive reach of this state,
380 2) most negative reach of this state,
381 3) how many bytes this mode will have in the variable part of the frag
382 4) which index into the table to try if we can't fit into this one. */
384 /* UNCOND_JUMP states. */
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
386 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
387 /* dword jmp adds 4 bytes to frag:
388 0 extra opcode bytes, 4 displacement bytes. */
390 /* word jmp adds 2 byte2 to frag:
391 0 extra opcode bytes, 2 displacement bytes. */
394 /* COND_JUMP states. */
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
397 /* dword conditionals adds 5 bytes to frag:
398 1 extra opcode byte, 4 displacement bytes. */
400 /* word conditionals add 3 bytes to frag:
401 1 extra opcode byte, 2 displacement bytes. */
404 /* COND_JUMP86 states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
410 /* word conditionals add 4 bytes to frag:
411 1 displacement byte and a 3 byte long branch insn. */
415 static const arch_entry cpu_arch
[] = {
417 {"i186", Cpu086
|Cpu186
},
418 {"i286", Cpu086
|Cpu186
|Cpu286
},
419 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
420 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
421 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
422 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
423 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
424 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
425 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
426 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
427 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
429 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
430 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
431 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
432 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
433 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
435 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
436 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
437 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
438 {".3dnow", CpuMMX
|Cpu3dnow
},
439 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
440 {".padlock", CpuPadLock
},
441 {".pacifica", CpuSVME
},
446 const pseudo_typeS md_pseudo_table
[] =
448 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
449 {"align", s_align_bytes
, 0},
451 {"align", s_align_ptwo
, 0},
453 {"arch", set_cpu_arch
, 0},
457 {"ffloat", float_cons
, 'f'},
458 {"dfloat", float_cons
, 'd'},
459 {"tfloat", float_cons
, 'x'},
461 {"noopt", s_ignore
, 0},
462 {"optim", s_ignore
, 0},
463 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
464 {"code16", set_code_flag
, CODE_16BIT
},
465 {"code32", set_code_flag
, CODE_32BIT
},
466 {"code64", set_code_flag
, CODE_64BIT
},
467 {"intel_syntax", set_intel_syntax
, 1},
468 {"att_syntax", set_intel_syntax
, 0},
469 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
470 {"loc", dwarf2_directive_loc
, 0},
471 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
472 {"largecomm", handle_large_common
, 0},
475 {"secrel32", pe_directive_secrel
, 0},
480 /* For interface with expression (). */
481 extern char *input_line_pointer
;
483 /* Hash table for instruction mnemonic lookup. */
484 static struct hash_control
*op_hash
;
486 /* Hash table for register lookup. */
487 static struct hash_control
*reg_hash
;
490 i386_align_code (fragP
, count
)
494 /* Various efficient no-op patterns for aligning code labels.
495 Note: Don't try to assemble the instructions in the comments.
496 0L and 0w are not legal. */
497 static const char f32_1
[] =
499 static const char f32_2
[] =
500 {0x89,0xf6}; /* movl %esi,%esi */
501 static const char f32_3
[] =
502 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
503 static const char f32_4
[] =
504 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
505 static const char f32_5
[] =
507 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
508 static const char f32_6
[] =
509 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
510 static const char f32_7
[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
512 static const char f32_8
[] =
514 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
515 static const char f32_9
[] =
516 {0x89,0xf6, /* movl %esi,%esi */
517 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
518 static const char f32_10
[] =
519 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
520 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
521 static const char f32_11
[] =
522 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_12
[] =
525 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
526 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
527 static const char f32_13
[] =
528 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_14
[] =
531 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
532 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
533 static const char f32_15
[] =
534 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
535 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
536 static const char f16_3
[] =
537 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
538 static const char f16_4
[] =
539 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
540 static const char f16_5
[] =
542 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
543 static const char f16_6
[] =
544 {0x89,0xf6, /* mov %si,%si */
545 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
546 static const char f16_7
[] =
547 {0x8d,0x74,0x00, /* lea 0(%si),%si */
548 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
549 static const char f16_8
[] =
550 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char *const f32_patt
[] = {
553 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
554 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
556 static const char *const f16_patt
[] = {
557 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
558 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
561 if (count
<= 0 || count
> 15)
564 /* The recommended way to pad 64bit code is to use NOPs preceded by
565 maximally four 0x66 prefixes. Balance the size of nops. */
566 if (flag_code
== CODE_64BIT
)
569 int nnops
= (count
+ 3) / 4;
570 int len
= count
/ nnops
;
571 int remains
= count
- nnops
* len
;
574 for (i
= 0; i
< remains
; i
++)
576 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
577 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
580 for (; i
< nnops
; i
++)
582 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
583 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
588 if (flag_code
== CODE_16BIT
)
590 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
591 f16_patt
[count
- 1], count
);
593 /* Adjust jump offset. */
594 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
597 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
598 f32_patt
[count
- 1], count
);
599 fragP
->fr_var
= count
;
602 static INLINE
unsigned int
603 mode_from_disp_size (t
)
606 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
610 fits_in_signed_byte (num
)
613 return (num
>= -128) && (num
<= 127);
617 fits_in_unsigned_byte (num
)
620 return (num
& 0xff) == num
;
624 fits_in_unsigned_word (num
)
627 return (num
& 0xffff) == num
;
631 fits_in_signed_word (num
)
634 return (-32768 <= num
) && (num
<= 32767);
637 fits_in_signed_long (num
)
638 offsetT num ATTRIBUTE_UNUSED
;
643 return (!(((offsetT
) -1 << 31) & num
)
644 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
646 } /* fits_in_signed_long() */
648 fits_in_unsigned_long (num
)
649 offsetT num ATTRIBUTE_UNUSED
;
654 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
656 } /* fits_in_unsigned_long() */
659 smallest_imm_type (num
)
662 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
664 /* This code is disabled on the 486 because all the Imm1 forms
665 in the opcode table are slower on the i486. They're the
666 versions with the implicitly specified single-position
667 displacement, which has another syntax if you really want to
670 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
672 return (fits_in_signed_byte (num
)
673 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
674 : fits_in_unsigned_byte (num
)
675 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
676 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
677 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
678 : fits_in_signed_long (num
)
679 ? (Imm32
| Imm32S
| Imm64
)
680 : fits_in_unsigned_long (num
)
686 offset_in_range (val
, size
)
694 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
695 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
696 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
698 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
703 /* If BFD64, sign extend val. */
704 if (!use_rela_relocations
)
705 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
706 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
708 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
710 char buf1
[40], buf2
[40];
712 sprint_value (buf1
, val
);
713 sprint_value (buf2
, val
& mask
);
714 as_warn (_("%s shortened to %s"), buf1
, buf2
);
719 /* Returns 0 if attempting to add a prefix where one from the same
720 class already exists, 1 if non rep/repne added, 2 if rep/repne
729 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
730 && flag_code
== CODE_64BIT
)
738 case CS_PREFIX_OPCODE
:
739 case DS_PREFIX_OPCODE
:
740 case ES_PREFIX_OPCODE
:
741 case FS_PREFIX_OPCODE
:
742 case GS_PREFIX_OPCODE
:
743 case SS_PREFIX_OPCODE
:
747 case REPNE_PREFIX_OPCODE
:
748 case REPE_PREFIX_OPCODE
:
751 case LOCK_PREFIX_OPCODE
:
759 case ADDR_PREFIX_OPCODE
:
763 case DATA_PREFIX_OPCODE
:
768 if (i
.prefix
[q
] != 0)
770 as_bad (_("same type of prefix used twice"));
775 i
.prefix
[q
] = prefix
;
780 set_code_flag (value
)
784 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
785 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
786 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
788 as_bad (_("64bit mode not supported on this CPU."));
790 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
792 as_bad (_("32bit mode not supported on this CPU."));
798 set_16bit_gcc_code_flag (new_code_flag
)
801 flag_code
= new_code_flag
;
802 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
803 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
804 stackop_size
= LONG_MNEM_SUFFIX
;
808 set_intel_syntax (syntax_flag
)
811 /* Find out if register prefixing is specified. */
812 int ask_naked_reg
= 0;
815 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
817 char *string
= input_line_pointer
;
818 int e
= get_symbol_end ();
820 if (strcmp (string
, "prefix") == 0)
822 else if (strcmp (string
, "noprefix") == 0)
825 as_bad (_("bad argument to syntax directive."));
826 *input_line_pointer
= e
;
828 demand_empty_rest_of_line ();
830 intel_syntax
= syntax_flag
;
832 if (ask_naked_reg
== 0)
833 allow_naked_reg
= (intel_syntax
834 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
836 allow_naked_reg
= (ask_naked_reg
< 0);
838 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
839 identifier_chars
['$'] = intel_syntax
? '$' : 0;
844 int dummy ATTRIBUTE_UNUSED
;
848 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
850 char *string
= input_line_pointer
;
851 int e
= get_symbol_end ();
854 for (i
= 0; cpu_arch
[i
].name
; i
++)
856 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
860 cpu_arch_name
= cpu_arch
[i
].name
;
861 cpu_sub_arch_name
= NULL
;
862 cpu_arch_flags
= (cpu_arch
[i
].flags
863 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
866 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
868 cpu_sub_arch_name
= cpu_arch
[i
].name
;
869 cpu_arch_flags
|= cpu_arch
[i
].flags
;
871 *input_line_pointer
= e
;
872 demand_empty_rest_of_line ();
876 if (!cpu_arch
[i
].name
)
877 as_bad (_("no such architecture: `%s'"), string
);
879 *input_line_pointer
= e
;
882 as_bad (_("missing cpu architecture"));
884 no_cond_jump_promotion
= 0;
885 if (*input_line_pointer
== ','
886 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
888 char *string
= ++input_line_pointer
;
889 int e
= get_symbol_end ();
891 if (strcmp (string
, "nojumps") == 0)
892 no_cond_jump_promotion
= 1;
893 else if (strcmp (string
, "jumps") == 0)
896 as_bad (_("no such architecture modifier: `%s'"), string
);
898 *input_line_pointer
= e
;
901 demand_empty_rest_of_line ();
907 if (!strcmp (default_arch
, "x86_64"))
908 return bfd_mach_x86_64
;
909 else if (!strcmp (default_arch
, "i386"))
910 return bfd_mach_i386_i386
;
912 as_fatal (_("Unknown architecture"));
918 const char *hash_err
;
920 /* Initialize op_hash hash table. */
921 op_hash
= hash_new ();
924 const template *optab
;
925 templates
*core_optab
;
927 /* Setup for loop. */
929 core_optab
= (templates
*) xmalloc (sizeof (templates
));
930 core_optab
->start
= optab
;
935 if (optab
->name
== NULL
936 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
938 /* different name --> ship out current template list;
939 add to hash table; & begin anew. */
940 core_optab
->end
= optab
;
941 hash_err
= hash_insert (op_hash
,
946 as_fatal (_("Internal Error: Can't hash %s: %s"),
950 if (optab
->name
== NULL
)
952 core_optab
= (templates
*) xmalloc (sizeof (templates
));
953 core_optab
->start
= optab
;
958 /* Initialize reg_hash hash table. */
959 reg_hash
= hash_new ();
961 const reg_entry
*regtab
;
963 for (regtab
= i386_regtab
;
964 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
967 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
969 as_fatal (_("Internal Error: Can't hash %s: %s"),
975 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
980 for (c
= 0; c
< 256; c
++)
985 mnemonic_chars
[c
] = c
;
986 register_chars
[c
] = c
;
987 operand_chars
[c
] = c
;
989 else if (ISLOWER (c
))
991 mnemonic_chars
[c
] = c
;
992 register_chars
[c
] = c
;
993 operand_chars
[c
] = c
;
995 else if (ISUPPER (c
))
997 mnemonic_chars
[c
] = TOLOWER (c
);
998 register_chars
[c
] = mnemonic_chars
[c
];
999 operand_chars
[c
] = c
;
1002 if (ISALPHA (c
) || ISDIGIT (c
))
1003 identifier_chars
[c
] = c
;
1006 identifier_chars
[c
] = c
;
1007 operand_chars
[c
] = c
;
1012 identifier_chars
['@'] = '@';
1015 identifier_chars
['?'] = '?';
1016 operand_chars
['?'] = '?';
1018 digit_chars
['-'] = '-';
1019 mnemonic_chars
['-'] = '-';
1020 identifier_chars
['_'] = '_';
1021 identifier_chars
['.'] = '.';
1023 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1024 operand_chars
[(unsigned char) *p
] = *p
;
1027 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 record_alignment (text_section
, 2);
1031 record_alignment (data_section
, 2);
1032 record_alignment (bss_section
, 2);
1036 if (flag_code
== CODE_64BIT
)
1038 x86_dwarf2_return_column
= 16;
1039 x86_cie_data_alignment
= -8;
1043 x86_dwarf2_return_column
= 8;
1044 x86_cie_data_alignment
= -4;
1049 i386_print_statistics (file
)
1052 hash_print_statistics (file
, "i386 opcode", op_hash
);
1053 hash_print_statistics (file
, "i386 register", reg_hash
);
1058 /* Debugging routines for md_assemble. */
1059 static void pi
PARAMS ((char *, i386_insn
*));
1060 static void pte
PARAMS ((template *));
1061 static void pt
PARAMS ((unsigned int));
1062 static void pe
PARAMS ((expressionS
*));
1063 static void ps
PARAMS ((symbolS
*));
1072 fprintf (stdout
, "%s: template ", line
);
1074 fprintf (stdout
, " address: base %s index %s scale %x\n",
1075 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1076 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1077 x
->log2_scale_factor
);
1078 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1079 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1080 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1081 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1082 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1083 (x
->rex
& REX_MODE64
) != 0,
1084 (x
->rex
& REX_EXTX
) != 0,
1085 (x
->rex
& REX_EXTY
) != 0,
1086 (x
->rex
& REX_EXTZ
) != 0);
1087 for (i
= 0; i
< x
->operands
; i
++)
1089 fprintf (stdout
, " #%d: ", i
+ 1);
1091 fprintf (stdout
, "\n");
1093 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1094 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1095 if (x
->types
[i
] & Imm
)
1097 if (x
->types
[i
] & Disp
)
1098 pe (x
->op
[i
].disps
);
1107 fprintf (stdout
, " %d operands ", t
->operands
);
1108 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1109 if (t
->extension_opcode
!= None
)
1110 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1111 if (t
->opcode_modifier
& D
)
1112 fprintf (stdout
, "D");
1113 if (t
->opcode_modifier
& W
)
1114 fprintf (stdout
, "W");
1115 fprintf (stdout
, "\n");
1116 for (i
= 0; i
< t
->operands
; i
++)
1118 fprintf (stdout
, " #%d type ", i
+ 1);
1119 pt (t
->operand_types
[i
]);
1120 fprintf (stdout
, "\n");
1128 fprintf (stdout
, " operation %d\n", e
->X_op
);
1129 fprintf (stdout
, " add_number %ld (%lx)\n",
1130 (long) e
->X_add_number
, (long) e
->X_add_number
);
1131 if (e
->X_add_symbol
)
1133 fprintf (stdout
, " add_symbol ");
1134 ps (e
->X_add_symbol
);
1135 fprintf (stdout
, "\n");
1139 fprintf (stdout
, " op_symbol ");
1140 ps (e
->X_op_symbol
);
1141 fprintf (stdout
, "\n");
1149 fprintf (stdout
, "%s type %s%s",
1151 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1152 segment_name (S_GET_SEGMENT (s
)));
1161 static const type_names
[] =
1174 { BaseIndex
, "BaseIndex" },
1178 { Disp32S
, "d32s" },
1180 { InOutPortReg
, "InOutPortReg" },
1181 { ShiftCount
, "ShiftCount" },
1182 { Control
, "control reg" },
1183 { Test
, "test reg" },
1184 { Debug
, "debug reg" },
1185 { FloatReg
, "FReg" },
1186 { FloatAcc
, "FAcc" },
1190 { JumpAbsolute
, "Jump Absolute" },
1201 const struct type_name
*ty
;
1203 for (ty
= type_names
; ty
->mask
; ty
++)
1205 fprintf (stdout
, "%s, ", ty
->tname
);
1209 #endif /* DEBUG386 */
1211 static bfd_reloc_code_real_type
1212 reloc (unsigned int size
,
1215 bfd_reloc_code_real_type other
)
1217 if (other
!= NO_RELOC
)
1219 reloc_howto_type
*reloc
;
1224 case BFD_RELOC_X86_64_TPOFF32
:
1225 other
= BFD_RELOC_X86_64_TPOFF64
;
1227 case BFD_RELOC_X86_64_DTPOFF32
:
1228 other
= BFD_RELOC_X86_64_DTPOFF64
;
1233 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1235 as_bad (_("unknown relocation (%u)"), other
);
1236 else if (size
!= bfd_get_reloc_size (reloc
))
1237 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1238 bfd_get_reloc_size (reloc
),
1240 else if (pcrel
&& !reloc
->pc_relative
)
1241 as_bad (_("non-pc-relative relocation for pc-relative field"));
1242 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1244 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1246 as_bad (_("relocated field and relocation type differ in signedness"));
1255 as_bad (_("there are no unsigned pc-relative relocations"));
1258 case 1: return BFD_RELOC_8_PCREL
;
1259 case 2: return BFD_RELOC_16_PCREL
;
1260 case 4: return BFD_RELOC_32_PCREL
;
1261 case 8: return BFD_RELOC_64_PCREL
;
1263 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1270 case 4: return BFD_RELOC_X86_64_32S
;
1275 case 1: return BFD_RELOC_8
;
1276 case 2: return BFD_RELOC_16
;
1277 case 4: return BFD_RELOC_32
;
1278 case 8: return BFD_RELOC_64
;
1280 as_bad (_("cannot do %s %u byte relocation"),
1281 sign
> 0 ? "signed" : "unsigned", size
);
1285 return BFD_RELOC_NONE
;
1288 /* Here we decide which fixups can be adjusted to make them relative to
1289 the beginning of the section instead of the symbol. Basically we need
1290 to make sure that the dynamic relocations are done correctly, so in
1291 some cases we force the original symbol to be used. */
1294 tc_i386_fix_adjustable (fixP
)
1295 fixS
*fixP ATTRIBUTE_UNUSED
;
1297 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1301 /* Don't adjust pc-relative references to merge sections in 64-bit
1303 if (use_rela_relocations
1304 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1308 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1309 and changed later by validate_fix. */
1310 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1311 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1314 /* adjust_reloc_syms doesn't know about the GOT. */
1315 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1316 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1317 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1318 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1319 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1320 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1321 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1322 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1323 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1324 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1326 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1327 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1328 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1329 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1330 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1331 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1332 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1337 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1338 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1344 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1347 intel_float_operand (mnemonic
)
1348 const char *mnemonic
;
1350 /* Note that the value returned is meaningful only for opcodes with (memory)
1351 operands, hence the code here is free to improperly handle opcodes that
1352 have no operands (for better performance and smaller code). */
1354 if (mnemonic
[0] != 'f')
1355 return 0; /* non-math */
1357 switch (mnemonic
[1])
1359 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1360 the fs segment override prefix not currently handled because no
1361 call path can make opcodes without operands get here */
1363 return 2 /* integer op */;
1365 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1366 return 3; /* fldcw/fldenv */
1369 if (mnemonic
[2] != 'o' /* fnop */)
1370 return 3; /* non-waiting control op */
1373 if (mnemonic
[2] == 's')
1374 return 3; /* frstor/frstpm */
1377 if (mnemonic
[2] == 'a')
1378 return 3; /* fsave */
1379 if (mnemonic
[2] == 't')
1381 switch (mnemonic
[3])
1383 case 'c': /* fstcw */
1384 case 'd': /* fstdw */
1385 case 'e': /* fstenv */
1386 case 's': /* fsts[gw] */
1392 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1393 return 0; /* fxsave/fxrstor are not really math ops */
1400 /* This is the guts of the machine-dependent assembler. LINE points to a
1401 machine dependent instruction. This function is supposed to emit
1402 the frags/bytes it assembles to. */
1409 char mnemonic
[MAX_MNEM_SIZE
];
1411 /* Initialize globals. */
1412 memset (&i
, '\0', sizeof (i
));
1413 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1414 i
.reloc
[j
] = NO_RELOC
;
1415 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1416 memset (im_expressions
, '\0', sizeof (im_expressions
));
1417 save_stack_p
= save_stack
;
1419 /* First parse an instruction mnemonic & call i386_operand for the operands.
1420 We assume that the scrubber has arranged it so that line[0] is the valid
1421 start of a (possibly prefixed) mnemonic. */
1423 line
= parse_insn (line
, mnemonic
);
1427 line
= parse_operands (line
, mnemonic
);
1431 /* Now we've parsed the mnemonic into a set of templates, and have the
1432 operands at hand. */
1434 /* All intel opcodes have reversed operands except for "bound" and
1435 "enter". We also don't reverse intersegment "jmp" and "call"
1436 instructions with 2 immediate operands so that the immediate segment
1437 precedes the offset, as it does when in AT&T mode. "enter" and the
1438 intersegment "jmp" and "call" instructions are the only ones that
1439 have two immediate operands. */
1440 if (intel_syntax
&& i
.operands
> 1
1441 && (strcmp (mnemonic
, "bound") != 0)
1442 && (strcmp (mnemonic
, "invlpga") != 0)
1443 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1449 /* Don't optimize displacement for movabs since it only takes 64bit
1452 && (flag_code
!= CODE_64BIT
1453 || strcmp (mnemonic
, "movabs") != 0))
1456 /* Next, we find a template that matches the given insn,
1457 making sure the overlap of the given operands types is consistent
1458 with the template operand types. */
1460 if (!match_template ())
1465 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1467 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1468 i
.tm
.base_opcode
^= FloatR
;
1470 /* Zap movzx and movsx suffix. The suffix may have been set from
1471 "word ptr" or "byte ptr" on the source operand, but we'll use
1472 the suffix later to choose the destination register. */
1473 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1475 if (i
.reg_operands
< 2
1477 && (~i
.tm
.opcode_modifier
1484 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1490 if (i
.tm
.opcode_modifier
& FWait
)
1491 if (!add_prefix (FWAIT_OPCODE
))
1494 /* Check string instruction segment overrides. */
1495 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1497 if (!check_string ())
1501 if (!process_suffix ())
1504 /* Make still unresolved immediate matches conform to size of immediate
1505 given in i.suffix. */
1506 if (!finalize_imm ())
1509 if (i
.types
[0] & Imm1
)
1510 i
.imm_operands
= 0; /* kludge for shift insns. */
1511 if (i
.types
[0] & ImplicitRegister
)
1513 if (i
.types
[1] & ImplicitRegister
)
1515 if (i
.types
[2] & ImplicitRegister
)
1518 if (i
.tm
.opcode_modifier
& ImmExt
)
1522 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1524 /* These Intel Prescott New Instructions have the fixed
1525 operands with an opcode suffix which is coded in the same
1526 place as an 8-bit immediate field would be. Here we check
1527 those operands and remove them afterwards. */
1530 for (x
= 0; x
< i
.operands
; x
++)
1531 if (i
.op
[x
].regs
->reg_num
!= x
)
1532 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1533 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1537 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1538 opcode suffix which is coded in the same place as an 8-bit
1539 immediate field would be. Here we fake an 8-bit immediate
1540 operand from the opcode suffix stored in tm.extension_opcode. */
1542 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1544 exp
= &im_expressions
[i
.imm_operands
++];
1545 i
.op
[i
.operands
].imms
= exp
;
1546 i
.types
[i
.operands
++] = Imm8
;
1547 exp
->X_op
= O_constant
;
1548 exp
->X_add_number
= i
.tm
.extension_opcode
;
1549 i
.tm
.extension_opcode
= None
;
1552 /* For insns with operands there are more diddles to do to the opcode. */
1555 if (!process_operands ())
1558 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1560 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1561 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1564 /* Handle conversion of 'int $3' --> special int3 insn. */
1565 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1567 i
.tm
.base_opcode
= INT3_OPCODE
;
1571 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1572 && i
.op
[0].disps
->X_op
== O_constant
)
1574 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1575 the absolute address given by the constant. Since ix86 jumps and
1576 calls are pc relative, we need to generate a reloc. */
1577 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1578 i
.op
[0].disps
->X_op
= O_symbol
;
1581 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1582 i
.rex
|= REX_MODE64
;
1584 /* For 8 bit registers we need an empty rex prefix. Also if the
1585 instruction already has a prefix, we need to convert old
1586 registers to new ones. */
1588 if (((i
.types
[0] & Reg8
) != 0
1589 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1590 || ((i
.types
[1] & Reg8
) != 0
1591 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1592 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1597 i
.rex
|= REX_OPCODE
;
1598 for (x
= 0; x
< 2; x
++)
1600 /* Look for 8 bit operand that uses old registers. */
1601 if ((i
.types
[x
] & Reg8
) != 0
1602 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1604 /* In case it is "hi" register, give up. */
1605 if (i
.op
[x
].regs
->reg_num
> 3)
1606 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1607 i
.op
[x
].regs
->reg_name
);
1609 /* Otherwise it is equivalent to the extended register.
1610 Since the encoding doesn't change this is merely
1611 cosmetic cleanup for debug output. */
1613 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1619 add_prefix (REX_OPCODE
| i
.rex
);
1621 /* We are ready to output the insn. */
1626 parse_insn (line
, mnemonic
)
1631 char *token_start
= l
;
1636 /* Non-zero if we found a prefix only acceptable with string insns. */
1637 const char *expecting_string_instruction
= NULL
;
1642 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1645 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1647 as_bad (_("no such instruction: `%s'"), token_start
);
1652 if (!is_space_char (*l
)
1653 && *l
!= END_OF_INSN
1655 || (*l
!= PREFIX_SEPARATOR
1658 as_bad (_("invalid character %s in mnemonic"),
1659 output_invalid (*l
));
1662 if (token_start
== l
)
1664 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1665 as_bad (_("expecting prefix; got nothing"));
1667 as_bad (_("expecting mnemonic; got nothing"));
1671 /* Look up instruction (or prefix) via hash table. */
1672 current_templates
= hash_find (op_hash
, mnemonic
);
1674 if (*l
!= END_OF_INSN
1675 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1676 && current_templates
1677 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1679 if (current_templates
->start
->cpu_flags
1680 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1682 as_bad ((flag_code
!= CODE_64BIT
1683 ? _("`%s' is only supported in 64-bit mode")
1684 : _("`%s' is not supported in 64-bit mode")),
1685 current_templates
->start
->name
);
1688 /* If we are in 16-bit mode, do not allow addr16 or data16.
1689 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1690 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1691 && flag_code
!= CODE_64BIT
1692 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1693 ^ (flag_code
== CODE_16BIT
)))
1695 as_bad (_("redundant %s prefix"),
1696 current_templates
->start
->name
);
1699 /* Add prefix, checking for repeated prefixes. */
1700 switch (add_prefix (current_templates
->start
->base_opcode
))
1705 expecting_string_instruction
= current_templates
->start
->name
;
1708 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1715 if (!current_templates
)
1717 /* See if we can get a match by trimming off a suffix. */
1720 case WORD_MNEM_SUFFIX
:
1721 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1722 i
.suffix
= SHORT_MNEM_SUFFIX
;
1724 case BYTE_MNEM_SUFFIX
:
1725 case QWORD_MNEM_SUFFIX
:
1726 i
.suffix
= mnem_p
[-1];
1728 current_templates
= hash_find (op_hash
, mnemonic
);
1730 case SHORT_MNEM_SUFFIX
:
1731 case LONG_MNEM_SUFFIX
:
1734 i
.suffix
= mnem_p
[-1];
1736 current_templates
= hash_find (op_hash
, mnemonic
);
1744 if (intel_float_operand (mnemonic
) == 1)
1745 i
.suffix
= SHORT_MNEM_SUFFIX
;
1747 i
.suffix
= LONG_MNEM_SUFFIX
;
1749 current_templates
= hash_find (op_hash
, mnemonic
);
1753 if (!current_templates
)
1755 as_bad (_("no such instruction: `%s'"), token_start
);
1760 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1762 /* Check for a branch hint. We allow ",pt" and ",pn" for
1763 predict taken and predict not taken respectively.
1764 I'm not sure that branch hints actually do anything on loop
1765 and jcxz insns (JumpByte) for current Pentium4 chips. They
1766 may work in the future and it doesn't hurt to accept them
1768 if (l
[0] == ',' && l
[1] == 'p')
1772 if (!add_prefix (DS_PREFIX_OPCODE
))
1776 else if (l
[2] == 'n')
1778 if (!add_prefix (CS_PREFIX_OPCODE
))
1784 /* Any other comma loses. */
1787 as_bad (_("invalid character %s in mnemonic"),
1788 output_invalid (*l
));
1792 /* Check if instruction is supported on specified architecture. */
1794 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1796 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1797 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1799 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1802 if (!(supported
& 2))
1804 as_bad (flag_code
== CODE_64BIT
1805 ? _("`%s' is not supported in 64-bit mode")
1806 : _("`%s' is only supported in 64-bit mode"),
1807 current_templates
->start
->name
);
1810 if (!(supported
& 1))
1812 as_warn (_("`%s' is not supported on `%s%s'"),
1813 current_templates
->start
->name
,
1815 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1817 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1819 as_warn (_("use .code16 to ensure correct addressing mode"));
1822 /* Check for rep/repne without a string instruction. */
1823 if (expecting_string_instruction
)
1825 static templates override
;
1827 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1828 if (t
->opcode_modifier
& IsString
)
1830 if (t
>= current_templates
->end
)
1832 as_bad (_("expecting string instruction after `%s'"),
1833 expecting_string_instruction
);
1836 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1837 if (!(t
->opcode_modifier
& IsString
))
1840 current_templates
= &override
;
1847 parse_operands (l
, mnemonic
)
1849 const char *mnemonic
;
1853 /* 1 if operand is pending after ','. */
1854 unsigned int expecting_operand
= 0;
1856 /* Non-zero if operand parens not balanced. */
1857 unsigned int paren_not_balanced
;
1859 while (*l
!= END_OF_INSN
)
1861 /* Skip optional white space before operand. */
1862 if (is_space_char (*l
))
1864 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1866 as_bad (_("invalid character %s before operand %d"),
1867 output_invalid (*l
),
1871 token_start
= l
; /* after white space */
1872 paren_not_balanced
= 0;
1873 while (paren_not_balanced
|| *l
!= ',')
1875 if (*l
== END_OF_INSN
)
1877 if (paren_not_balanced
)
1880 as_bad (_("unbalanced parenthesis in operand %d."),
1883 as_bad (_("unbalanced brackets in operand %d."),
1888 break; /* we are done */
1890 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1892 as_bad (_("invalid character %s in operand %d"),
1893 output_invalid (*l
),
1900 ++paren_not_balanced
;
1902 --paren_not_balanced
;
1907 ++paren_not_balanced
;
1909 --paren_not_balanced
;
1913 if (l
!= token_start
)
1914 { /* Yes, we've read in another operand. */
1915 unsigned int operand_ok
;
1916 this_operand
= i
.operands
++;
1917 if (i
.operands
> MAX_OPERANDS
)
1919 as_bad (_("spurious operands; (%d operands/instruction max)"),
1923 /* Now parse operand adding info to 'i' as we go along. */
1924 END_STRING_AND_SAVE (l
);
1928 i386_intel_operand (token_start
,
1929 intel_float_operand (mnemonic
));
1931 operand_ok
= i386_operand (token_start
);
1933 RESTORE_END_STRING (l
);
1939 if (expecting_operand
)
1941 expecting_operand_after_comma
:
1942 as_bad (_("expecting operand after ','; got nothing"));
1947 as_bad (_("expecting operand before ','; got nothing"));
1952 /* Now *l must be either ',' or END_OF_INSN. */
1955 if (*++l
== END_OF_INSN
)
1957 /* Just skip it, if it's \n complain. */
1958 goto expecting_operand_after_comma
;
1960 expecting_operand
= 1;
1969 union i386_op temp_op
;
1970 unsigned int temp_type
;
1971 enum bfd_reloc_code_real temp_reloc
;
1975 if (i
.operands
== 2)
1980 else if (i
.operands
== 3)
1985 temp_type
= i
.types
[xchg2
];
1986 i
.types
[xchg2
] = i
.types
[xchg1
];
1987 i
.types
[xchg1
] = temp_type
;
1988 temp_op
= i
.op
[xchg2
];
1989 i
.op
[xchg2
] = i
.op
[xchg1
];
1990 i
.op
[xchg1
] = temp_op
;
1991 temp_reloc
= i
.reloc
[xchg2
];
1992 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1993 i
.reloc
[xchg1
] = temp_reloc
;
1995 if (i
.mem_operands
== 2)
1997 const seg_entry
*temp_seg
;
1998 temp_seg
= i
.seg
[0];
1999 i
.seg
[0] = i
.seg
[1];
2000 i
.seg
[1] = temp_seg
;
2004 /* Try to ensure constant immediates are represented in the smallest
2009 char guess_suffix
= 0;
2013 guess_suffix
= i
.suffix
;
2014 else if (i
.reg_operands
)
2016 /* Figure out a suffix from the last register operand specified.
2017 We can't do this properly yet, ie. excluding InOutPortReg,
2018 but the following works for instructions with immediates.
2019 In any case, we can't set i.suffix yet. */
2020 for (op
= i
.operands
; --op
>= 0;)
2021 if (i
.types
[op
] & Reg
)
2023 if (i
.types
[op
] & Reg8
)
2024 guess_suffix
= BYTE_MNEM_SUFFIX
;
2025 else if (i
.types
[op
] & Reg16
)
2026 guess_suffix
= WORD_MNEM_SUFFIX
;
2027 else if (i
.types
[op
] & Reg32
)
2028 guess_suffix
= LONG_MNEM_SUFFIX
;
2029 else if (i
.types
[op
] & Reg64
)
2030 guess_suffix
= QWORD_MNEM_SUFFIX
;
2034 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2035 guess_suffix
= WORD_MNEM_SUFFIX
;
2037 for (op
= i
.operands
; --op
>= 0;)
2038 if (i
.types
[op
] & Imm
)
2040 switch (i
.op
[op
].imms
->X_op
)
2043 /* If a suffix is given, this operand may be shortened. */
2044 switch (guess_suffix
)
2046 case LONG_MNEM_SUFFIX
:
2047 i
.types
[op
] |= Imm32
| Imm64
;
2049 case WORD_MNEM_SUFFIX
:
2050 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2052 case BYTE_MNEM_SUFFIX
:
2053 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2057 /* If this operand is at most 16 bits, convert it
2058 to a signed 16 bit number before trying to see
2059 whether it will fit in an even smaller size.
2060 This allows a 16-bit operand such as $0xffe0 to
2061 be recognised as within Imm8S range. */
2062 if ((i
.types
[op
] & Imm16
)
2063 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2065 i
.op
[op
].imms
->X_add_number
=
2066 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2068 if ((i
.types
[op
] & Imm32
)
2069 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2072 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2073 ^ ((offsetT
) 1 << 31))
2074 - ((offsetT
) 1 << 31));
2076 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2078 /* We must avoid matching of Imm32 templates when 64bit
2079 only immediate is available. */
2080 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2081 i
.types
[op
] &= ~Imm32
;
2088 /* Symbols and expressions. */
2090 /* Convert symbolic operand to proper sizes for matching, but don't
2091 prevent matching a set of insns that only supports sizes other
2092 than those matching the insn suffix. */
2094 unsigned int mask
, allowed
= 0;
2097 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2098 allowed
|= t
->operand_types
[op
];
2099 switch (guess_suffix
)
2101 case QWORD_MNEM_SUFFIX
:
2102 mask
= Imm64
| Imm32S
;
2104 case LONG_MNEM_SUFFIX
:
2107 case WORD_MNEM_SUFFIX
:
2110 case BYTE_MNEM_SUFFIX
:
2118 i
.types
[op
] &= mask
;
2125 /* Try to use the smallest displacement type too. */
2131 for (op
= i
.operands
; --op
>= 0;)
2132 if (i
.types
[op
] & Disp
)
2134 if (i
.op
[op
].disps
->X_op
== O_constant
)
2136 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2138 if ((i
.types
[op
] & Disp16
)
2139 && (disp
& ~(offsetT
) 0xffff) == 0)
2141 /* If this operand is at most 16 bits, convert
2142 to a signed 16 bit number and don't use 64bit
2144 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2145 i
.types
[op
] &= ~Disp64
;
2147 if ((i
.types
[op
] & Disp32
)
2148 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2150 /* If this operand is at most 32 bits, convert
2151 to a signed 32 bit number and don't use 64bit
2153 disp
&= (((offsetT
) 2 << 31) - 1);
2154 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2155 i
.types
[op
] &= ~Disp64
;
2157 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2159 i
.types
[op
] &= ~Disp
;
2163 else if (flag_code
== CODE_64BIT
)
2165 if (fits_in_signed_long (disp
))
2167 i
.types
[op
] &= ~Disp64
;
2168 i
.types
[op
] |= Disp32S
;
2170 if (fits_in_unsigned_long (disp
))
2171 i
.types
[op
] |= Disp32
;
2173 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2174 && fits_in_signed_byte (disp
))
2175 i
.types
[op
] |= Disp8
;
2178 /* We only support 64bit displacement on constants. */
2179 i
.types
[op
] &= ~Disp64
;
2186 /* Points to template once we've found it. */
2188 unsigned int overlap0
, overlap1
, overlap2
;
2189 unsigned int found_reverse_match
;
2192 #define MATCH(overlap, given, template) \
2193 ((overlap & ~JumpAbsolute) \
2194 && (((given) & (BaseIndex | JumpAbsolute)) \
2195 == ((overlap) & (BaseIndex | JumpAbsolute))))
2197 /* If given types r0 and r1 are registers they must be of the same type
2198 unless the expected operand type register overlap is null.
2199 Note that Acc in a template matches every size of reg. */
2200 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2201 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2202 || ((g0) & Reg) == ((g1) & Reg) \
2203 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2208 found_reverse_match
= 0;
2209 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2211 : (i
.suffix
== WORD_MNEM_SUFFIX
2213 : (i
.suffix
== SHORT_MNEM_SUFFIX
2215 : (i
.suffix
== LONG_MNEM_SUFFIX
2217 : (i
.suffix
== QWORD_MNEM_SUFFIX
2219 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2220 ? No_xSuf
: 0))))));
2222 t
= current_templates
->start
;
2223 if (i
.suffix
== QWORD_MNEM_SUFFIX
2224 && flag_code
!= CODE_64BIT
2226 ? !(t
->opcode_modifier
& IgnoreSize
)
2227 && !intel_float_operand (t
->name
)
2228 : intel_float_operand (t
->name
) != 2)
2229 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2230 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2231 && (t
->base_opcode
!= 0x0fc7
2232 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2233 t
= current_templates
->end
;
2234 for (; t
< current_templates
->end
; t
++)
2236 /* Must have right number of operands. */
2237 if (i
.operands
!= t
->operands
)
2240 /* Check the suffix, except for some instructions in intel mode. */
2241 if ((t
->opcode_modifier
& suffix_check
)
2243 && (t
->opcode_modifier
& IgnoreSize
)))
2246 /* Do not verify operands when there are none. */
2247 else if (!t
->operands
)
2249 if (t
->cpu_flags
& ~cpu_arch_flags
)
2251 /* We've found a match; break out of loop. */
2255 overlap0
= i
.types
[0] & t
->operand_types
[0];
2256 switch (t
->operands
)
2259 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2264 overlap1
= i
.types
[1] & t
->operand_types
[1];
2265 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2266 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2267 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2268 t
->operand_types
[0],
2269 overlap1
, i
.types
[1],
2270 t
->operand_types
[1]))
2272 /* Check if other direction is valid ... */
2273 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2276 /* Try reversing direction of operands. */
2277 overlap0
= i
.types
[0] & t
->operand_types
[1];
2278 overlap1
= i
.types
[1] & t
->operand_types
[0];
2279 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2280 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2281 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2282 t
->operand_types
[1],
2283 overlap1
, i
.types
[1],
2284 t
->operand_types
[0]))
2286 /* Does not match either direction. */
2289 /* found_reverse_match holds which of D or FloatDR
2291 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2293 /* Found a forward 2 operand match here. */
2294 else if (t
->operands
== 3)
2296 /* Here we make use of the fact that there are no
2297 reverse match 3 operand instructions, and all 3
2298 operand instructions only need to be checked for
2299 register consistency between operands 2 and 3. */
2300 overlap2
= i
.types
[2] & t
->operand_types
[2];
2301 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2302 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2303 t
->operand_types
[1],
2304 overlap2
, i
.types
[2],
2305 t
->operand_types
[2]))
2309 /* Found either forward/reverse 2 or 3 operand match here:
2310 slip through to break. */
2312 if (t
->cpu_flags
& ~cpu_arch_flags
)
2314 found_reverse_match
= 0;
2317 /* We've found a match; break out of loop. */
2321 if (t
== current_templates
->end
)
2323 /* We found no match. */
2324 as_bad (_("suffix or operands invalid for `%s'"),
2325 current_templates
->start
->name
);
2329 if (!quiet_warnings
)
2332 && ((i
.types
[0] & JumpAbsolute
)
2333 != (t
->operand_types
[0] & JumpAbsolute
)))
2335 as_warn (_("indirect %s without `*'"), t
->name
);
2338 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2339 == (IsPrefix
| IgnoreSize
))
2341 /* Warn them that a data or address size prefix doesn't
2342 affect assembly of the next line of code. */
2343 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2347 /* Copy the template we found. */
2349 if (found_reverse_match
)
2351 /* If we found a reverse match we must alter the opcode
2352 direction bit. found_reverse_match holds bits to change
2353 (different for int & float insns). */
2355 i
.tm
.base_opcode
^= found_reverse_match
;
2357 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2358 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2367 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2368 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2370 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2372 as_bad (_("`%s' operand %d must use `%%es' segment"),
2377 /* There's only ever one segment override allowed per instruction.
2378 This instruction possibly has a legal segment override on the
2379 second operand, so copy the segment to where non-string
2380 instructions store it, allowing common code. */
2381 i
.seg
[0] = i
.seg
[1];
2383 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2385 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2387 as_bad (_("`%s' operand %d must use `%%es' segment"),
2397 process_suffix (void)
2399 /* If matched instruction specifies an explicit instruction mnemonic
2401 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2403 if (i
.tm
.opcode_modifier
& Size16
)
2404 i
.suffix
= WORD_MNEM_SUFFIX
;
2405 else if (i
.tm
.opcode_modifier
& Size64
)
2406 i
.suffix
= QWORD_MNEM_SUFFIX
;
2408 i
.suffix
= LONG_MNEM_SUFFIX
;
2410 else if (i
.reg_operands
)
2412 /* If there's no instruction mnemonic suffix we try to invent one
2413 based on register operands. */
2416 /* We take i.suffix from the last register operand specified,
2417 Destination register type is more significant than source
2421 for (op
= i
.operands
; --op
>= 0;)
2422 if ((i
.types
[op
] & Reg
)
2423 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2425 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2426 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2427 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2432 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2434 if (!check_byte_reg ())
2437 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2439 if (!check_long_reg ())
2442 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2444 if (!check_qword_reg ())
2447 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2449 if (!check_word_reg ())
2452 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2453 /* Do nothing if the instruction is going to ignore the prefix. */
2458 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2460 /* exclude fldenv/frstor/fsave/fstenv */
2461 && (i
.tm
.opcode_modifier
& No_sSuf
))
2463 i
.suffix
= stackop_size
;
2465 else if (intel_syntax
2467 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2468 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2469 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2470 && i
.tm
.extension_opcode
<= 3)))
2475 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2477 i
.suffix
= QWORD_MNEM_SUFFIX
;
2481 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2482 i
.suffix
= LONG_MNEM_SUFFIX
;
2485 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2486 i
.suffix
= WORD_MNEM_SUFFIX
;
2495 if (i
.tm
.opcode_modifier
& W
)
2497 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2503 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2511 if ((i
.tm
.opcode_modifier
& W
)
2512 || ((suffixes
& (suffixes
- 1))
2513 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2515 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2521 /* Change the opcode based on the operand size given by i.suffix;
2522 We don't need to change things for byte insns. */
2524 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2526 /* It's not a byte, select word/dword operation. */
2527 if (i
.tm
.opcode_modifier
& W
)
2529 if (i
.tm
.opcode_modifier
& ShortForm
)
2530 i
.tm
.base_opcode
|= 8;
2532 i
.tm
.base_opcode
|= 1;
2535 /* Now select between word & dword operations via the operand
2536 size prefix, except for instructions that will ignore this
2538 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2539 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2540 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2541 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2542 || (flag_code
== CODE_64BIT
2543 && (i
.tm
.opcode_modifier
& JumpByte
))))
2545 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2547 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2548 prefix
= ADDR_PREFIX_OPCODE
;
2550 if (!add_prefix (prefix
))
2554 /* Set mode64 for an operand. */
2555 if (i
.suffix
== QWORD_MNEM_SUFFIX
2556 && flag_code
== CODE_64BIT
2557 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2558 i
.rex
|= REX_MODE64
;
2560 /* Size floating point instruction. */
2561 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2562 if (i
.tm
.opcode_modifier
& FloatMF
)
2563 i
.tm
.base_opcode
^= 4;
2570 check_byte_reg (void)
2574 for (op
= i
.operands
; --op
>= 0;)
2576 /* If this is an eight bit register, it's OK. If it's the 16 or
2577 32 bit version of an eight bit register, we will just use the
2578 low portion, and that's OK too. */
2579 if (i
.types
[op
] & Reg8
)
2582 /* movzx and movsx should not generate this warning. */
2584 && (i
.tm
.base_opcode
== 0xfb7
2585 || i
.tm
.base_opcode
== 0xfb6
2586 || i
.tm
.base_opcode
== 0x63
2587 || i
.tm
.base_opcode
== 0xfbe
2588 || i
.tm
.base_opcode
== 0xfbf))
2591 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2593 /* Prohibit these changes in the 64bit mode, since the
2594 lowering is more complicated. */
2595 if (flag_code
== CODE_64BIT
2596 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2598 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2599 i
.op
[op
].regs
->reg_name
,
2603 #if REGISTER_WARNINGS
2605 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2606 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2607 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2608 ? REGNAM_AL
- REGNAM_AX
2609 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2610 i
.op
[op
].regs
->reg_name
,
2615 /* Any other register is bad. */
2616 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2618 | Control
| Debug
| Test
2619 | FloatReg
| FloatAcc
))
2621 as_bad (_("`%%%s' not allowed with `%s%c'"),
2622 i
.op
[op
].regs
->reg_name
,
2636 for (op
= i
.operands
; --op
>= 0;)
2637 /* Reject eight bit registers, except where the template requires
2638 them. (eg. movzb) */
2639 if ((i
.types
[op
] & Reg8
) != 0
2640 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2642 as_bad (_("`%%%s' not allowed with `%s%c'"),
2643 i
.op
[op
].regs
->reg_name
,
2648 /* Warn if the e prefix on a general reg is missing. */
2649 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2650 && (i
.types
[op
] & Reg16
) != 0
2651 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2653 /* Prohibit these changes in the 64bit mode, since the
2654 lowering is more complicated. */
2655 if (flag_code
== CODE_64BIT
)
2657 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2658 i
.op
[op
].regs
->reg_name
,
2662 #if REGISTER_WARNINGS
2664 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2665 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2666 i
.op
[op
].regs
->reg_name
,
2670 /* Warn if the r prefix on a general reg is missing. */
2671 else if ((i
.types
[op
] & Reg64
) != 0
2672 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2674 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2675 i
.op
[op
].regs
->reg_name
,
2687 for (op
= i
.operands
; --op
>= 0; )
2688 /* Reject eight bit registers, except where the template requires
2689 them. (eg. movzb) */
2690 if ((i
.types
[op
] & Reg8
) != 0
2691 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2693 as_bad (_("`%%%s' not allowed with `%s%c'"),
2694 i
.op
[op
].regs
->reg_name
,
2699 /* Warn if the e prefix on a general reg is missing. */
2700 else if (((i
.types
[op
] & Reg16
) != 0
2701 || (i
.types
[op
] & Reg32
) != 0)
2702 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2704 /* Prohibit these changes in the 64bit mode, since the
2705 lowering is more complicated. */
2706 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2707 i
.op
[op
].regs
->reg_name
,
2718 for (op
= i
.operands
; --op
>= 0;)
2719 /* Reject eight bit registers, except where the template requires
2720 them. (eg. movzb) */
2721 if ((i
.types
[op
] & Reg8
) != 0
2722 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2724 as_bad (_("`%%%s' not allowed with `%s%c'"),
2725 i
.op
[op
].regs
->reg_name
,
2730 /* Warn if the e prefix on a general reg is present. */
2731 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2732 && (i
.types
[op
] & Reg32
) != 0
2733 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2735 /* Prohibit these changes in the 64bit mode, since the
2736 lowering is more complicated. */
2737 if (flag_code
== CODE_64BIT
)
2739 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2740 i
.op
[op
].regs
->reg_name
,
2745 #if REGISTER_WARNINGS
2746 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2747 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2748 i
.op
[op
].regs
->reg_name
,
2758 unsigned int overlap0
, overlap1
, overlap2
;
2760 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2761 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2762 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2763 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2764 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2768 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2770 : (i
.suffix
== WORD_MNEM_SUFFIX
2772 : (i
.suffix
== QWORD_MNEM_SUFFIX
2776 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2777 || overlap0
== (Imm16
| Imm32
)
2778 || overlap0
== (Imm16
| Imm32S
))
2780 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2783 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2784 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2785 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2787 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2791 i
.types
[0] = overlap0
;
2793 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2794 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2795 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2796 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2797 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2801 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2803 : (i
.suffix
== WORD_MNEM_SUFFIX
2805 : (i
.suffix
== QWORD_MNEM_SUFFIX
2809 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2810 || overlap1
== (Imm16
| Imm32
)
2811 || overlap1
== (Imm16
| Imm32S
))
2813 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2816 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2817 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2818 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2820 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2824 i
.types
[1] = overlap1
;
2826 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2827 assert ((overlap2
& Imm
) == 0);
2828 i
.types
[2] = overlap2
;
2836 /* Default segment register this instruction will use for memory
2837 accesses. 0 means unknown. This is only for optimizing out
2838 unnecessary segment overrides. */
2839 const seg_entry
*default_seg
= 0;
2841 /* The imul $imm, %reg instruction is converted into
2842 imul $imm, %reg, %reg, and the clr %reg instruction
2843 is converted into xor %reg, %reg. */
2844 if (i
.tm
.opcode_modifier
& regKludge
)
2846 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2847 /* Pretend we saw the extra register operand. */
2848 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2849 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2850 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2854 if (i
.tm
.opcode_modifier
& ShortForm
)
2856 /* The register or float register operand is in operand 0 or 1. */
2857 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2858 /* Register goes in low 3 bits of opcode. */
2859 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2860 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2862 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2864 /* Warn about some common errors, but press on regardless.
2865 The first case can be generated by gcc (<= 2.8.1). */
2866 if (i
.operands
== 2)
2868 /* Reversed arguments on faddp, fsubp, etc. */
2869 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2870 i
.op
[1].regs
->reg_name
,
2871 i
.op
[0].regs
->reg_name
);
2875 /* Extraneous `l' suffix on fp insn. */
2876 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2877 i
.op
[0].regs
->reg_name
);
2881 else if (i
.tm
.opcode_modifier
& Modrm
)
2883 /* The opcode is completed (modulo i.tm.extension_opcode which
2884 must be put into the modrm byte). Now, we make the modrm and
2885 index base bytes based on all the info we've collected. */
2887 default_seg
= build_modrm_byte ();
2889 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2891 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2892 && i
.op
[0].regs
->reg_num
== 1)
2894 as_bad (_("you can't `pop %%cs'"));
2897 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2898 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2901 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2905 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2907 /* For the string instructions that allow a segment override
2908 on one of their operands, the default segment is ds. */
2912 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2913 || (i
.tm
.cpu_flags
& CpuSVME
))
2914 && i
.seg
[0] && !quiet_warnings
)
2915 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2917 /* If a segment was explicitly specified, and the specified segment
2918 is not the default, use an opcode prefix to select it. If we
2919 never figured out what the default segment is, then default_seg
2920 will be zero at this point, and the specified segment prefix will
2922 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2924 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2930 static const seg_entry
*
2933 const seg_entry
*default_seg
= 0;
2935 /* i.reg_operands MUST be the number of real register operands;
2936 implicit registers do not count. */
2937 if (i
.reg_operands
== 2)
2939 unsigned int source
, dest
;
2940 source
= ((i
.types
[0]
2941 & (Reg
| RegMMX
| RegXMM
2943 | Control
| Debug
| Test
))
2948 /* One of the register operands will be encoded in the i.tm.reg
2949 field, the other in the combined i.tm.mode and i.tm.regmem
2950 fields. If no form of this instruction supports a memory
2951 destination operand, then we assume the source operand may
2952 sometimes be a memory operand and so we need to store the
2953 destination in the i.rm.reg field. */
2954 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2956 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2957 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2958 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2960 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2965 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2966 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2967 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2969 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2972 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2974 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2976 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2977 add_prefix (LOCK_PREFIX_OPCODE
);
2981 { /* If it's not 2 reg operands... */
2984 unsigned int fake_zero_displacement
= 0;
2985 unsigned int op
= ((i
.types
[0] & AnyMem
)
2987 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2991 if (i
.base_reg
== 0)
2994 if (!i
.disp_operands
)
2995 fake_zero_displacement
= 1;
2996 if (i
.index_reg
== 0)
2998 /* Operand is just <disp> */
2999 if (flag_code
== CODE_64BIT
)
3001 /* 64bit mode overwrites the 32bit absolute
3002 addressing by RIP relative addressing and
3003 absolute addressing is encoded by one of the
3004 redundant SIB forms. */
3005 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3006 i
.sib
.base
= NO_BASE_REGISTER
;
3007 i
.sib
.index
= NO_INDEX_REGISTER
;
3008 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3010 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3012 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3013 i
.types
[op
] = Disp16
;
3017 i
.rm
.regmem
= NO_BASE_REGISTER
;
3018 i
.types
[op
] = Disp32
;
3021 else /* !i.base_reg && i.index_reg */
3023 i
.sib
.index
= i
.index_reg
->reg_num
;
3024 i
.sib
.base
= NO_BASE_REGISTER
;
3025 i
.sib
.scale
= i
.log2_scale_factor
;
3026 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3027 i
.types
[op
] &= ~Disp
;
3028 if (flag_code
!= CODE_64BIT
)
3029 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3031 i
.types
[op
] |= Disp32S
;
3032 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3036 /* RIP addressing for 64bit mode. */
3037 else if (i
.base_reg
->reg_type
== BaseIndex
)
3039 i
.rm
.regmem
= NO_BASE_REGISTER
;
3040 i
.types
[op
] &= ~ Disp
;
3041 i
.types
[op
] |= Disp32S
;
3042 i
.flags
[op
] = Operand_PCrel
;
3043 if (! i
.disp_operands
)
3044 fake_zero_displacement
= 1;
3046 else if (i
.base_reg
->reg_type
& Reg16
)
3048 switch (i
.base_reg
->reg_num
)
3051 if (i
.index_reg
== 0)
3053 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3054 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3058 if (i
.index_reg
== 0)
3061 if ((i
.types
[op
] & Disp
) == 0)
3063 /* fake (%bp) into 0(%bp) */
3064 i
.types
[op
] |= Disp8
;
3065 fake_zero_displacement
= 1;
3068 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3069 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3071 default: /* (%si) -> 4 or (%di) -> 5 */
3072 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3074 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3076 else /* i.base_reg and 32/64 bit mode */
3078 if (flag_code
== CODE_64BIT
3079 && (i
.types
[op
] & Disp
))
3080 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3082 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3083 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3085 i
.sib
.base
= i
.base_reg
->reg_num
;
3086 /* x86-64 ignores REX prefix bit here to avoid decoder
3088 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3091 if (i
.disp_operands
== 0)
3093 fake_zero_displacement
= 1;
3094 i
.types
[op
] |= Disp8
;
3097 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3101 i
.sib
.scale
= i
.log2_scale_factor
;
3102 if (i
.index_reg
== 0)
3104 /* <disp>(%esp) becomes two byte modrm with no index
3105 register. We've already stored the code for esp
3106 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3107 Any base register besides %esp will not use the
3108 extra modrm byte. */
3109 i
.sib
.index
= NO_INDEX_REGISTER
;
3110 #if !SCALE1_WHEN_NO_INDEX
3111 /* Another case where we force the second modrm byte. */
3112 if (i
.log2_scale_factor
)
3113 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3118 i
.sib
.index
= i
.index_reg
->reg_num
;
3119 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3120 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3123 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3126 if (fake_zero_displacement
)
3128 /* Fakes a zero displacement assuming that i.types[op]
3129 holds the correct displacement size. */
3132 assert (i
.op
[op
].disps
== 0);
3133 exp
= &disp_expressions
[i
.disp_operands
++];
3134 i
.op
[op
].disps
= exp
;
3135 exp
->X_op
= O_constant
;
3136 exp
->X_add_number
= 0;
3137 exp
->X_add_symbol
= (symbolS
*) 0;
3138 exp
->X_op_symbol
= (symbolS
*) 0;
3142 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3143 (if any) based on i.tm.extension_opcode. Again, we must be
3144 careful to make sure that segment/control/debug/test/MMX
3145 registers are coded into the i.rm.reg field. */
3150 & (Reg
| RegMMX
| RegXMM
3152 | Control
| Debug
| Test
))
3155 & (Reg
| RegMMX
| RegXMM
3157 | Control
| Debug
| Test
))
3160 /* If there is an extension opcode to put here, the register
3161 number must be put into the regmem field. */
3162 if (i
.tm
.extension_opcode
!= None
)
3164 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3165 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3170 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3171 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3175 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3176 must set it to 3 to indicate this is a register operand
3177 in the regmem field. */
3178 if (!i
.mem_operands
)
3182 /* Fill in i.rm.reg field with extension opcode (if any). */
3183 if (i
.tm
.extension_opcode
!= None
)
3184 i
.rm
.reg
= i
.tm
.extension_opcode
;
3195 relax_substateT subtype
;
3200 if (flag_code
== CODE_16BIT
)
3204 if (i
.prefix
[DATA_PREFIX
] != 0)
3210 /* Pentium4 branch hints. */
3211 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3212 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3217 if (i
.prefix
[REX_PREFIX
] != 0)
3223 if (i
.prefixes
!= 0 && !intel_syntax
)
3224 as_warn (_("skipping prefixes on this instruction"));
3226 /* It's always a symbol; End frag & setup for relax.
3227 Make sure there is enough room in this frag for the largest
3228 instruction we may generate in md_convert_frag. This is 2
3229 bytes for the opcode and room for the prefix and largest
3231 frag_grow (prefix
+ 2 + 4);
3232 /* Prefix and 1 opcode byte go in fr_fix. */
3233 p
= frag_more (prefix
+ 1);
3234 if (i
.prefix
[DATA_PREFIX
] != 0)
3235 *p
++ = DATA_PREFIX_OPCODE
;
3236 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3237 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3238 *p
++ = i
.prefix
[SEG_PREFIX
];
3239 if (i
.prefix
[REX_PREFIX
] != 0)
3240 *p
++ = i
.prefix
[REX_PREFIX
];
3241 *p
= i
.tm
.base_opcode
;
3243 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3244 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3245 else if ((cpu_arch_flags
& Cpu386
) != 0)
3246 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3248 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3251 sym
= i
.op
[0].disps
->X_add_symbol
;
3252 off
= i
.op
[0].disps
->X_add_number
;
3254 if (i
.op
[0].disps
->X_op
!= O_constant
3255 && i
.op
[0].disps
->X_op
!= O_symbol
)
3257 /* Handle complex expressions. */
3258 sym
= make_expr_symbol (i
.op
[0].disps
);
3262 /* 1 possible extra opcode + 4 byte displacement go in var part.
3263 Pass reloc in fr_var. */
3264 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3274 if (i
.tm
.opcode_modifier
& JumpByte
)
3276 /* This is a loop or jecxz type instruction. */
3278 if (i
.prefix
[ADDR_PREFIX
] != 0)
3280 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3283 /* Pentium4 branch hints. */
3284 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3285 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3287 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3296 if (flag_code
== CODE_16BIT
)
3299 if (i
.prefix
[DATA_PREFIX
] != 0)
3301 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3311 if (i
.prefix
[REX_PREFIX
] != 0)
3313 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3317 if (i
.prefixes
!= 0 && !intel_syntax
)
3318 as_warn (_("skipping prefixes on this instruction"));
3320 p
= frag_more (1 + size
);
3321 *p
++ = i
.tm
.base_opcode
;
3323 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3324 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3326 /* All jumps handled here are signed, but don't use a signed limit
3327 check for 32 and 16 bit jumps as we want to allow wrap around at
3328 4G and 64k respectively. */
3330 fixP
->fx_signed
= 1;
3334 output_interseg_jump ()
3342 if (flag_code
== CODE_16BIT
)
3346 if (i
.prefix
[DATA_PREFIX
] != 0)
3352 if (i
.prefix
[REX_PREFIX
] != 0)
3362 if (i
.prefixes
!= 0 && !intel_syntax
)
3363 as_warn (_("skipping prefixes on this instruction"));
3365 /* 1 opcode; 2 segment; offset */
3366 p
= frag_more (prefix
+ 1 + 2 + size
);
3368 if (i
.prefix
[DATA_PREFIX
] != 0)
3369 *p
++ = DATA_PREFIX_OPCODE
;
3371 if (i
.prefix
[REX_PREFIX
] != 0)
3372 *p
++ = i
.prefix
[REX_PREFIX
];
3374 *p
++ = i
.tm
.base_opcode
;
3375 if (i
.op
[1].imms
->X_op
== O_constant
)
3377 offsetT n
= i
.op
[1].imms
->X_add_number
;
3380 && !fits_in_unsigned_word (n
)
3381 && !fits_in_signed_word (n
))
3383 as_bad (_("16-bit jump out of range"));
3386 md_number_to_chars (p
, n
, size
);
3389 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3390 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3391 if (i
.op
[0].imms
->X_op
!= O_constant
)
3392 as_bad (_("can't handle non absolute segment in `%s'"),
3394 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3400 fragS
*insn_start_frag
;
3401 offsetT insn_start_off
;
3403 /* Tie dwarf2 debug info to the address at the start of the insn.
3404 We can't do this after the insn has been output as the current
3405 frag may have been closed off. eg. by frag_var. */
3406 dwarf2_emit_insn (0);
3408 insn_start_frag
= frag_now
;
3409 insn_start_off
= frag_now_fix ();
3412 if (i
.tm
.opcode_modifier
& Jump
)
3414 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3416 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3417 output_interseg_jump ();
3420 /* Output normal instructions here. */
3424 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3425 more higher byte to specify a prefix the instruction
3427 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3429 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3431 unsigned int prefix
;
3432 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3434 if (prefix
!= REPE_PREFIX_OPCODE
3435 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3436 add_prefix (prefix
);
3439 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3442 /* The prefix bytes. */
3444 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3450 md_number_to_chars (p
, (valueT
) *q
, 1);
3454 /* Now the opcode; be careful about word order here! */
3455 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3457 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3463 /* Put out high byte first: can't use md_number_to_chars! */
3464 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3465 *p
= i
.tm
.base_opcode
& 0xff;
3468 /* Now the modrm byte and sib byte (if present). */
3469 if (i
.tm
.opcode_modifier
& Modrm
)
3472 md_number_to_chars (p
,
3473 (valueT
) (i
.rm
.regmem
<< 0
3477 /* If i.rm.regmem == ESP (4)
3478 && i.rm.mode != (Register mode)
3480 ==> need second modrm byte. */
3481 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3483 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3486 md_number_to_chars (p
,
3487 (valueT
) (i
.sib
.base
<< 0
3489 | i
.sib
.scale
<< 6),
3494 if (i
.disp_operands
)
3495 output_disp (insn_start_frag
, insn_start_off
);
3498 output_imm (insn_start_frag
, insn_start_off
);
3506 #endif /* DEBUG386 */
3510 output_disp (insn_start_frag
, insn_start_off
)
3511 fragS
*insn_start_frag
;
3512 offsetT insn_start_off
;
3517 for (n
= 0; n
< i
.operands
; n
++)
3519 if (i
.types
[n
] & Disp
)
3521 if (i
.op
[n
].disps
->X_op
== O_constant
)
3527 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3530 if (i
.types
[n
] & Disp8
)
3532 if (i
.types
[n
] & Disp64
)
3535 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3537 p
= frag_more (size
);
3538 md_number_to_chars (p
, val
, size
);
3542 enum bfd_reloc_code_real reloc_type
;
3545 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3547 /* The PC relative address is computed relative
3548 to the instruction boundary, so in case immediate
3549 fields follows, we need to adjust the value. */
3550 if (pcrel
&& i
.imm_operands
)
3555 for (n1
= 0; n1
< i
.operands
; n1
++)
3556 if (i
.types
[n1
] & Imm
)
3558 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3561 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3563 if (i
.types
[n1
] & Imm64
)
3568 /* We should find the immediate. */
3569 if (n1
== i
.operands
)
3571 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3574 if (i
.types
[n
] & Disp32S
)
3577 if (i
.types
[n
] & (Disp16
| Disp64
))
3580 if (i
.types
[n
] & Disp64
)
3584 p
= frag_more (size
);
3585 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3587 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3588 && (((reloc_type
== BFD_RELOC_32
3589 || reloc_type
== BFD_RELOC_X86_64_32S
)
3590 && (i
.op
[n
].disps
->X_op
== O_symbol
3591 || (i
.op
[n
].disps
->X_op
== O_add
3592 && ((symbol_get_value_expression
3593 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3595 || reloc_type
== BFD_RELOC_32_PCREL
))
3599 if (insn_start_frag
== frag_now
)
3600 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3605 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3606 for (fr
= insn_start_frag
->fr_next
;
3607 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3609 add
+= p
- frag_now
->fr_literal
;
3612 if (flag_code
!= CODE_64BIT
)
3613 reloc_type
= BFD_RELOC_386_GOTPC
;
3615 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3616 i
.op
[n
].disps
->X_add_number
+= add
;
3618 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3619 i
.op
[n
].disps
, pcrel
, reloc_type
);
3626 output_imm (insn_start_frag
, insn_start_off
)
3627 fragS
*insn_start_frag
;
3628 offsetT insn_start_off
;
3633 for (n
= 0; n
< i
.operands
; n
++)
3635 if (i
.types
[n
] & Imm
)
3637 if (i
.op
[n
].imms
->X_op
== O_constant
)
3643 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3646 if (i
.types
[n
] & (Imm8
| Imm8S
))
3648 else if (i
.types
[n
] & Imm64
)
3651 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3653 p
= frag_more (size
);
3654 md_number_to_chars (p
, val
, size
);
3658 /* Not absolute_section.
3659 Need a 32-bit fixup (don't support 8bit
3660 non-absolute imms). Try to support other
3662 enum bfd_reloc_code_real reloc_type
;
3666 if ((i
.types
[n
] & (Imm32S
))
3667 && (i
.suffix
== QWORD_MNEM_SUFFIX
3668 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3670 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3673 if (i
.types
[n
] & (Imm8
| Imm8S
))
3675 if (i
.types
[n
] & Imm64
)
3679 p
= frag_more (size
);
3680 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3682 /* This is tough to explain. We end up with this one if we
3683 * have operands that look like
3684 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3685 * obtain the absolute address of the GOT, and it is strongly
3686 * preferable from a performance point of view to avoid using
3687 * a runtime relocation for this. The actual sequence of
3688 * instructions often look something like:
3693 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3695 * The call and pop essentially return the absolute address
3696 * of the label .L66 and store it in %ebx. The linker itself
3697 * will ultimately change the first operand of the addl so
3698 * that %ebx points to the GOT, but to keep things simple, the
3699 * .o file must have this operand set so that it generates not
3700 * the absolute address of .L66, but the absolute address of
3701 * itself. This allows the linker itself simply treat a GOTPC
3702 * relocation as asking for a pcrel offset to the GOT to be
3703 * added in, and the addend of the relocation is stored in the
3704 * operand field for the instruction itself.
3706 * Our job here is to fix the operand so that it would add
3707 * the correct offset so that %ebx would point to itself. The
3708 * thing that is tricky is that .-.L66 will point to the
3709 * beginning of the instruction, so we need to further modify
3710 * the operand so that it will point to itself. There are
3711 * other cases where you have something like:
3713 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3715 * and here no correction would be required. Internally in
3716 * the assembler we treat operands of this form as not being
3717 * pcrel since the '.' is explicitly mentioned, and I wonder
3718 * whether it would simplify matters to do it this way. Who
3719 * knows. In earlier versions of the PIC patches, the
3720 * pcrel_adjust field was used to store the correction, but
3721 * since the expression is not pcrel, I felt it would be
3722 * confusing to do it this way. */
3724 if ((reloc_type
== BFD_RELOC_32
3725 || reloc_type
== BFD_RELOC_X86_64_32S
)
3727 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3728 && (i
.op
[n
].imms
->X_op
== O_symbol
3729 || (i
.op
[n
].imms
->X_op
== O_add
3730 && ((symbol_get_value_expression
3731 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3736 if (insn_start_frag
== frag_now
)
3737 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3742 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3743 for (fr
= insn_start_frag
->fr_next
;
3744 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3746 add
+= p
- frag_now
->fr_literal
;
3749 if (flag_code
!= CODE_64BIT
)
3750 reloc_type
= BFD_RELOC_386_GOTPC
;
3752 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3753 i
.op
[n
].imms
->X_add_number
+= add
;
3755 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3756 i
.op
[n
].imms
, 0, reloc_type
);
3762 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3763 # define lex_got(reloc, adjust, types) NULL
3765 /* Parse operands of the form
3766 <symbol>@GOTOFF+<nnn>
3767 and similar .plt or .got references.
3769 If we find one, set up the correct relocation in RELOC and copy the
3770 input string, minus the `@GOTOFF' into a malloc'd buffer for
3771 parsing by the calling routine. Return this buffer, and if ADJUST
3772 is non-null set it to the length of the string we removed from the
3773 input line. Otherwise return NULL. */
3775 lex_got (enum bfd_reloc_code_real
*reloc
,
3777 unsigned int *types
)
3779 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3780 static const struct {
3782 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3783 const unsigned int types64
;
3785 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3786 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3787 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3788 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3789 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 }, 0 },
3790 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3791 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3792 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3793 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 }, 0 },
3794 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3795 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 }, 0 },
3796 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 }, 0 },
3797 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
}
3805 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3806 if (is_end_of_line
[(unsigned char) *cp
])
3809 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3813 len
= strlen (gotrel
[j
].str
);
3814 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3816 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3819 char *tmpbuf
, *past_reloc
;
3821 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3827 if (flag_code
!= CODE_64BIT
)
3828 *types
= Imm32
|Disp32
;
3830 *types
= gotrel
[j
].types64
;
3833 if (GOT_symbol
== NULL
)
3834 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3836 /* Replace the relocation token with ' ', so that
3837 errors like foo@GOTOFF1 will be detected. */
3839 /* The length of the first part of our input line. */
3840 first
= cp
- input_line_pointer
;
3842 /* The second part goes from after the reloc token until
3843 (and including) an end_of_line char. Don't use strlen
3844 here as the end_of_line char may not be a NUL. */
3845 past_reloc
= cp
+ 1 + len
;
3846 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3848 second
= cp
- past_reloc
;
3850 /* Allocate and copy string. The trailing NUL shouldn't
3851 be necessary, but be safe. */
3852 tmpbuf
= xmalloc (first
+ second
+ 2);
3853 memcpy (tmpbuf
, input_line_pointer
, first
);
3854 tmpbuf
[first
] = ' ';
3855 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3856 tmpbuf
[first
+ second
+ 1] = '\0';
3860 as_bad (_("@%s reloc is not supported in %s bit mode"),
3861 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3866 /* Might be a symbol version string. Don't as_bad here. */
3870 /* x86_cons_fix_new is called via the expression parsing code when a
3871 reloc is needed. We use this hook to get the correct .got reloc. */
3872 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3875 x86_cons_fix_new (frag
, off
, len
, exp
)
3881 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, got_reloc
);
3882 got_reloc
= NO_RELOC
;
3883 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3887 x86_cons (exp
, size
)
3891 if (size
== 4 || (flag_code
== CODE_64BIT
&& size
== 8))
3893 /* Handle @GOTOFF and the like in an expression. */
3895 char *gotfree_input_line
;
3898 save
= input_line_pointer
;
3899 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
3900 if (gotfree_input_line
)
3901 input_line_pointer
= gotfree_input_line
;
3905 if (gotfree_input_line
)
3907 /* expression () has merrily parsed up to the end of line,
3908 or a comma - in the wrong buffer. Transfer how far
3909 input_line_pointer has moved to the right buffer. */
3910 input_line_pointer
= (save
3911 + (input_line_pointer
- gotfree_input_line
)
3913 free (gotfree_input_line
);
3924 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3930 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, NO_RELOC
);
3932 if (exp
->X_op
== O_secrel
)
3934 exp
->X_op
= O_symbol
;
3935 r
= BFD_RELOC_32_SECREL
;
3938 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3942 pe_directive_secrel (dummy
)
3943 int dummy ATTRIBUTE_UNUSED
;
3950 if (exp
.X_op
== O_symbol
)
3951 exp
.X_op
= O_secrel
;
3953 emit_expr (&exp
, 4);
3955 while (*input_line_pointer
++ == ',');
3957 input_line_pointer
--;
3958 demand_empty_rest_of_line ();
3963 static int i386_immediate
PARAMS ((char *));
3966 i386_immediate (imm_start
)
3969 char *save_input_line_pointer
;
3970 char *gotfree_input_line
;
3973 unsigned int types
= ~0U;
3975 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3977 as_bad (_("only 1 or 2 immediate operands are allowed"));
3981 exp
= &im_expressions
[i
.imm_operands
++];
3982 i
.op
[this_operand
].imms
= exp
;
3984 if (is_space_char (*imm_start
))
3987 save_input_line_pointer
= input_line_pointer
;
3988 input_line_pointer
= imm_start
;
3990 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
3991 if (gotfree_input_line
)
3992 input_line_pointer
= gotfree_input_line
;
3994 exp_seg
= expression (exp
);
3997 if (*input_line_pointer
)
3998 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4000 input_line_pointer
= save_input_line_pointer
;
4001 if (gotfree_input_line
)
4002 free (gotfree_input_line
);
4004 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4006 /* Missing or bad expr becomes absolute 0. */
4007 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4009 exp
->X_op
= O_constant
;
4010 exp
->X_add_number
= 0;
4011 exp
->X_add_symbol
= (symbolS
*) 0;
4012 exp
->X_op_symbol
= (symbolS
*) 0;
4014 else if (exp
->X_op
== O_constant
)
4016 /* Size it properly later. */
4017 i
.types
[this_operand
] |= Imm64
;
4018 /* If BFD64, sign extend val. */
4019 if (!use_rela_relocations
)
4020 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4021 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4023 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4024 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4025 && exp_seg
!= absolute_section
4026 && exp_seg
!= text_section
4027 && exp_seg
!= data_section
4028 && exp_seg
!= bss_section
4029 && exp_seg
!= undefined_section
4030 && !bfd_is_com_section (exp_seg
))
4032 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4038 /* This is an address. The size of the address will be
4039 determined later, depending on destination register,
4040 suffix, or the default for the section. */
4041 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4042 i
.types
[this_operand
] &= types
;
4048 static char *i386_scale
PARAMS ((char *));
4055 char *save
= input_line_pointer
;
4057 input_line_pointer
= scale
;
4058 val
= get_absolute_expression ();
4063 i
.log2_scale_factor
= 0;
4066 i
.log2_scale_factor
= 1;
4069 i
.log2_scale_factor
= 2;
4072 i
.log2_scale_factor
= 3;
4076 char sep
= *input_line_pointer
;
4078 *input_line_pointer
= '\0';
4079 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4081 *input_line_pointer
= sep
;
4082 input_line_pointer
= save
;
4086 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4088 as_warn (_("scale factor of %d without an index register"),
4089 1 << i
.log2_scale_factor
);
4090 #if SCALE1_WHEN_NO_INDEX
4091 i
.log2_scale_factor
= 0;
4094 scale
= input_line_pointer
;
4095 input_line_pointer
= save
;
4099 static int i386_displacement
PARAMS ((char *, char *));
4102 i386_displacement (disp_start
, disp_end
)
4108 char *save_input_line_pointer
;
4109 char *gotfree_input_line
;
4110 int bigdisp
= Disp32
;
4111 unsigned int types
= Disp
;
4113 if (flag_code
== CODE_64BIT
)
4115 if (i
.prefix
[ADDR_PREFIX
] == 0)
4116 bigdisp
= Disp64
| Disp32S
| Disp32
;
4118 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4120 i
.types
[this_operand
] |= bigdisp
;
4122 exp
= &disp_expressions
[i
.disp_operands
];
4123 i
.op
[this_operand
].disps
= exp
;
4125 save_input_line_pointer
= input_line_pointer
;
4126 input_line_pointer
= disp_start
;
4127 END_STRING_AND_SAVE (disp_end
);
4129 #ifndef GCC_ASM_O_HACK
4130 #define GCC_ASM_O_HACK 0
4133 END_STRING_AND_SAVE (disp_end
+ 1);
4134 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4135 && displacement_string_end
[-1] == '+')
4137 /* This hack is to avoid a warning when using the "o"
4138 constraint within gcc asm statements.
4141 #define _set_tssldt_desc(n,addr,limit,type) \
4142 __asm__ __volatile__ ( \
4144 "movw %w1,2+%0\n\t" \
4146 "movb %b1,4+%0\n\t" \
4147 "movb %4,5+%0\n\t" \
4148 "movb $0,6+%0\n\t" \
4149 "movb %h1,7+%0\n\t" \
4151 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4153 This works great except that the output assembler ends
4154 up looking a bit weird if it turns out that there is
4155 no offset. You end up producing code that looks like:
4168 So here we provide the missing zero. */
4170 *displacement_string_end
= '0';
4173 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4174 if (gotfree_input_line
)
4175 input_line_pointer
= gotfree_input_line
;
4177 exp_seg
= expression (exp
);
4180 if (*input_line_pointer
)
4181 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4183 RESTORE_END_STRING (disp_end
+ 1);
4185 RESTORE_END_STRING (disp_end
);
4186 input_line_pointer
= save_input_line_pointer
;
4187 if (gotfree_input_line
)
4188 free (gotfree_input_line
);
4190 /* We do this to make sure that the section symbol is in
4191 the symbol table. We will ultimately change the relocation
4192 to be relative to the beginning of the section. */
4193 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4194 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4195 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4197 if (exp
->X_op
!= O_symbol
)
4199 as_bad (_("bad expression used with @%s"),
4200 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4206 if (S_IS_LOCAL (exp
->X_add_symbol
)
4207 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4208 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4209 exp
->X_op
= O_subtract
;
4210 exp
->X_op_symbol
= GOT_symbol
;
4211 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4212 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4213 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4214 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4216 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4219 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4221 /* Missing or bad expr becomes absolute 0. */
4222 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4224 exp
->X_op
= O_constant
;
4225 exp
->X_add_number
= 0;
4226 exp
->X_add_symbol
= (symbolS
*) 0;
4227 exp
->X_op_symbol
= (symbolS
*) 0;
4230 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4231 if (exp
->X_op
!= O_constant
4232 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4233 && exp_seg
!= absolute_section
4234 && exp_seg
!= text_section
4235 && exp_seg
!= data_section
4236 && exp_seg
!= bss_section
4237 && exp_seg
!= undefined_section
4238 && !bfd_is_com_section (exp_seg
))
4240 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4245 if (!(i
.types
[this_operand
] & ~Disp
))
4246 i
.types
[this_operand
] &= types
;
4251 static int i386_index_check
PARAMS ((const char *));
4253 /* Make sure the memory operand we've been dealt is valid.
4254 Return 1 on success, 0 on a failure. */
4257 i386_index_check (operand_string
)
4258 const char *operand_string
;
4261 #if INFER_ADDR_PREFIX
4267 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4268 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4270 /* Memory operands of SVME insns are special in that they only allow
4271 rAX as their memory address and ignore any segment override. */
4274 /* SKINIT is even more restrictive: it always requires EAX. */
4275 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4277 else if (flag_code
== CODE_64BIT
)
4278 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4280 RegXX
= (flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4284 || !(i
.base_reg
->reg_type
& Acc
)
4285 || !(i
.base_reg
->reg_type
& RegXX
)
4287 || (i
.types
[0] & Disp
))
4290 else if (flag_code
== CODE_64BIT
)
4292 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4295 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4296 && (i
.base_reg
->reg_type
!= BaseIndex
4299 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4300 != (RegXX
| BaseIndex
))))
4305 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4309 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4310 != (Reg16
| BaseIndex
)))
4312 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4313 != (Reg16
| BaseIndex
))
4315 && i
.base_reg
->reg_num
< 6
4316 && i
.index_reg
->reg_num
>= 6
4317 && i
.log2_scale_factor
== 0))))
4324 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4326 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4327 != (Reg32
| BaseIndex
))))
4333 #if INFER_ADDR_PREFIX
4334 if (i
.prefix
[ADDR_PREFIX
] == 0)
4336 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4338 /* Change the size of any displacement too. At most one of
4339 Disp16 or Disp32 is set.
4340 FIXME. There doesn't seem to be any real need for separate
4341 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4342 Removing them would probably clean up the code quite a lot. */
4343 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4344 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4349 as_bad (_("`%s' is not a valid base/index expression"),
4353 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4355 flag_code_names
[flag_code
]);
4360 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4364 i386_operand (operand_string
)
4365 char *operand_string
;
4369 char *op_string
= operand_string
;
4371 if (is_space_char (*op_string
))
4374 /* We check for an absolute prefix (differentiating,
4375 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4376 if (*op_string
== ABSOLUTE_PREFIX
)
4379 if (is_space_char (*op_string
))
4381 i
.types
[this_operand
] |= JumpAbsolute
;
4384 /* Check if operand is a register. */
4385 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4386 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4388 /* Check for a segment override by searching for ':' after a
4389 segment register. */
4391 if (is_space_char (*op_string
))
4393 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4398 i
.seg
[i
.mem_operands
] = &es
;
4401 i
.seg
[i
.mem_operands
] = &cs
;
4404 i
.seg
[i
.mem_operands
] = &ss
;
4407 i
.seg
[i
.mem_operands
] = &ds
;
4410 i
.seg
[i
.mem_operands
] = &fs
;
4413 i
.seg
[i
.mem_operands
] = &gs
;
4417 /* Skip the ':' and whitespace. */
4419 if (is_space_char (*op_string
))
4422 if (!is_digit_char (*op_string
)
4423 && !is_identifier_char (*op_string
)
4424 && *op_string
!= '('
4425 && *op_string
!= ABSOLUTE_PREFIX
)
4427 as_bad (_("bad memory operand `%s'"), op_string
);
4430 /* Handle case of %es:*foo. */
4431 if (*op_string
== ABSOLUTE_PREFIX
)
4434 if (is_space_char (*op_string
))
4436 i
.types
[this_operand
] |= JumpAbsolute
;
4438 goto do_memory_reference
;
4442 as_bad (_("junk `%s' after register"), op_string
);
4445 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4446 i
.op
[this_operand
].regs
= r
;
4449 else if (*op_string
== REGISTER_PREFIX
)
4451 as_bad (_("bad register name `%s'"), op_string
);
4454 else if (*op_string
== IMMEDIATE_PREFIX
)
4457 if (i
.types
[this_operand
] & JumpAbsolute
)
4459 as_bad (_("immediate operand illegal with absolute jump"));
4462 if (!i386_immediate (op_string
))
4465 else if (is_digit_char (*op_string
)
4466 || is_identifier_char (*op_string
)
4467 || *op_string
== '(')
4469 /* This is a memory reference of some sort. */
4472 /* Start and end of displacement string expression (if found). */
4473 char *displacement_string_start
;
4474 char *displacement_string_end
;
4476 do_memory_reference
:
4477 if ((i
.mem_operands
== 1
4478 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4479 || i
.mem_operands
== 2)
4481 as_bad (_("too many memory references for `%s'"),
4482 current_templates
->start
->name
);
4486 /* Check for base index form. We detect the base index form by
4487 looking for an ')' at the end of the operand, searching
4488 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4490 base_string
= op_string
+ strlen (op_string
);
4493 if (is_space_char (*base_string
))
4496 /* If we only have a displacement, set-up for it to be parsed later. */
4497 displacement_string_start
= op_string
;
4498 displacement_string_end
= base_string
+ 1;
4500 if (*base_string
== ')')
4503 unsigned int parens_balanced
= 1;
4504 /* We've already checked that the number of left & right ()'s are
4505 equal, so this loop will not be infinite. */
4509 if (*base_string
== ')')
4511 if (*base_string
== '(')
4514 while (parens_balanced
);
4516 temp_string
= base_string
;
4518 /* Skip past '(' and whitespace. */
4520 if (is_space_char (*base_string
))
4523 if (*base_string
== ','
4524 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4525 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4527 displacement_string_end
= temp_string
;
4529 i
.types
[this_operand
] |= BaseIndex
;
4533 base_string
= end_op
;
4534 if (is_space_char (*base_string
))
4538 /* There may be an index reg or scale factor here. */
4539 if (*base_string
== ',')
4542 if (is_space_char (*base_string
))
4545 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4546 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4548 base_string
= end_op
;
4549 if (is_space_char (*base_string
))
4551 if (*base_string
== ',')
4554 if (is_space_char (*base_string
))
4557 else if (*base_string
!= ')')
4559 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4564 else if (*base_string
== REGISTER_PREFIX
)
4566 as_bad (_("bad register name `%s'"), base_string
);
4570 /* Check for scale factor. */
4571 if (*base_string
!= ')')
4573 char *end_scale
= i386_scale (base_string
);
4578 base_string
= end_scale
;
4579 if (is_space_char (*base_string
))
4581 if (*base_string
!= ')')
4583 as_bad (_("expecting `)' after scale factor in `%s'"),
4588 else if (!i
.index_reg
)
4590 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4595 else if (*base_string
!= ')')
4597 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4602 else if (*base_string
== REGISTER_PREFIX
)
4604 as_bad (_("bad register name `%s'"), base_string
);
4609 /* If there's an expression beginning the operand, parse it,
4610 assuming displacement_string_start and
4611 displacement_string_end are meaningful. */
4612 if (displacement_string_start
!= displacement_string_end
)
4614 if (!i386_displacement (displacement_string_start
,
4615 displacement_string_end
))
4619 /* Special case for (%dx) while doing input/output op. */
4621 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4623 && i
.log2_scale_factor
== 0
4624 && i
.seg
[i
.mem_operands
] == 0
4625 && (i
.types
[this_operand
] & Disp
) == 0)
4627 i
.types
[this_operand
] = InOutPortReg
;
4631 if (i386_index_check (operand_string
) == 0)
4637 /* It's not a memory operand; argh! */
4638 as_bad (_("invalid char %s beginning operand %d `%s'"),
4639 output_invalid (*op_string
),
4644 return 1; /* Normal return. */
4647 /* md_estimate_size_before_relax()
4649 Called just before relax() for rs_machine_dependent frags. The x86
4650 assembler uses these frags to handle variable size jump
4653 Any symbol that is now undefined will not become defined.
4654 Return the correct fr_subtype in the frag.
4655 Return the initial "guess for variable size of frag" to caller.
4656 The guess is actually the growth beyond the fixed part. Whatever
4657 we do to grow the fixed or variable part contributes to our
4661 md_estimate_size_before_relax (fragP
, segment
)
4665 /* We've already got fragP->fr_subtype right; all we have to do is
4666 check for un-relaxable symbols. On an ELF system, we can't relax
4667 an externally visible symbol, because it may be overridden by a
4669 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4670 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4672 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4673 || S_IS_WEAK (fragP
->fr_symbol
)))
4677 /* Symbol is undefined in this segment, or we need to keep a
4678 reloc so that weak symbols can be overridden. */
4679 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4680 enum bfd_reloc_code_real reloc_type
;
4681 unsigned char *opcode
;
4684 if (fragP
->fr_var
!= NO_RELOC
)
4685 reloc_type
= fragP
->fr_var
;
4687 reloc_type
= BFD_RELOC_16_PCREL
;
4689 reloc_type
= BFD_RELOC_32_PCREL
;
4691 old_fr_fix
= fragP
->fr_fix
;
4692 opcode
= (unsigned char *) fragP
->fr_opcode
;
4694 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4697 /* Make jmp (0xeb) a (d)word displacement jump. */
4699 fragP
->fr_fix
+= size
;
4700 fix_new (fragP
, old_fr_fix
, size
,
4702 fragP
->fr_offset
, 1,
4708 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4710 /* Negate the condition, and branch past an
4711 unconditional jump. */
4714 /* Insert an unconditional jump. */
4716 /* We added two extra opcode bytes, and have a two byte
4718 fragP
->fr_fix
+= 2 + 2;
4719 fix_new (fragP
, old_fr_fix
+ 2, 2,
4721 fragP
->fr_offset
, 1,
4728 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4733 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4735 fragP
->fr_offset
, 1,
4737 fixP
->fx_signed
= 1;
4741 /* This changes the byte-displacement jump 0x7N
4742 to the (d)word-displacement jump 0x0f,0x8N. */
4743 opcode
[1] = opcode
[0] + 0x10;
4744 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4745 /* We've added an opcode byte. */
4746 fragP
->fr_fix
+= 1 + size
;
4747 fix_new (fragP
, old_fr_fix
+ 1, size
,
4749 fragP
->fr_offset
, 1,
4754 BAD_CASE (fragP
->fr_subtype
);
4758 return fragP
->fr_fix
- old_fr_fix
;
4761 /* Guess size depending on current relax state. Initially the relax
4762 state will correspond to a short jump and we return 1, because
4763 the variable part of the frag (the branch offset) is one byte
4764 long. However, we can relax a section more than once and in that
4765 case we must either set fr_subtype back to the unrelaxed state,
4766 or return the value for the appropriate branch. */
4767 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4770 /* Called after relax() is finished.
4772 In: Address of frag.
4773 fr_type == rs_machine_dependent.
4774 fr_subtype is what the address relaxed to.
4776 Out: Any fixSs and constants are set up.
4777 Caller will turn frag into a ".space 0". */
4780 md_convert_frag (abfd
, sec
, fragP
)
4781 bfd
*abfd ATTRIBUTE_UNUSED
;
4782 segT sec ATTRIBUTE_UNUSED
;
4785 unsigned char *opcode
;
4786 unsigned char *where_to_put_displacement
= NULL
;
4787 offsetT target_address
;
4788 offsetT opcode_address
;
4789 unsigned int extension
= 0;
4790 offsetT displacement_from_opcode_start
;
4792 opcode
= (unsigned char *) fragP
->fr_opcode
;
4794 /* Address we want to reach in file space. */
4795 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4797 /* Address opcode resides at in file space. */
4798 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4800 /* Displacement from opcode start to fill into instruction. */
4801 displacement_from_opcode_start
= target_address
- opcode_address
;
4803 if ((fragP
->fr_subtype
& BIG
) == 0)
4805 /* Don't have to change opcode. */
4806 extension
= 1; /* 1 opcode + 1 displacement */
4807 where_to_put_displacement
= &opcode
[1];
4811 if (no_cond_jump_promotion
4812 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4813 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4815 switch (fragP
->fr_subtype
)
4817 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4818 extension
= 4; /* 1 opcode + 4 displacement */
4820 where_to_put_displacement
= &opcode
[1];
4823 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4824 extension
= 2; /* 1 opcode + 2 displacement */
4826 where_to_put_displacement
= &opcode
[1];
4829 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4830 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4831 extension
= 5; /* 2 opcode + 4 displacement */
4832 opcode
[1] = opcode
[0] + 0x10;
4833 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4834 where_to_put_displacement
= &opcode
[2];
4837 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4838 extension
= 3; /* 2 opcode + 2 displacement */
4839 opcode
[1] = opcode
[0] + 0x10;
4840 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4841 where_to_put_displacement
= &opcode
[2];
4844 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4849 where_to_put_displacement
= &opcode
[3];
4853 BAD_CASE (fragP
->fr_subtype
);
4858 /* Now put displacement after opcode. */
4859 md_number_to_chars ((char *) where_to_put_displacement
,
4860 (valueT
) (displacement_from_opcode_start
- extension
),
4861 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4862 fragP
->fr_fix
+= extension
;
4865 /* Size of byte displacement jmp. */
4866 int md_short_jump_size
= 2;
4868 /* Size of dword displacement jmp. */
4869 int md_long_jump_size
= 5;
4871 /* Size of relocation record. */
4872 const int md_reloc_size
= 8;
4875 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4877 addressT from_addr
, to_addr
;
4878 fragS
*frag ATTRIBUTE_UNUSED
;
4879 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4883 offset
= to_addr
- (from_addr
+ 2);
4884 /* Opcode for byte-disp jump. */
4885 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4886 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4890 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4892 addressT from_addr
, to_addr
;
4893 fragS
*frag ATTRIBUTE_UNUSED
;
4894 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4898 offset
= to_addr
- (from_addr
+ 5);
4899 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4900 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4903 /* Apply a fixup (fixS) to segment data, once it has been determined
4904 by our caller that we have all the info we need to fix it up.
4906 On the 386, immediates, displacements, and data pointers are all in
4907 the same (little-endian) format, so we don't need to care about which
4911 md_apply_fix (fixP
, valP
, seg
)
4912 /* The fix we're to put in. */
4914 /* Pointer to the value of the bits. */
4916 /* Segment fix is from. */
4917 segT seg ATTRIBUTE_UNUSED
;
4919 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4920 valueT value
= *valP
;
4922 #if !defined (TE_Mach)
4925 switch (fixP
->fx_r_type
)
4931 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4934 case BFD_RELOC_X86_64_32S
:
4935 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4938 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4941 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4946 if (fixP
->fx_addsy
!= NULL
4947 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4948 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4949 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4950 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4951 && !use_rela_relocations
)
4953 /* This is a hack. There should be a better way to handle this.
4954 This covers for the fact that bfd_install_relocation will
4955 subtract the current location (for partial_inplace, PC relative
4956 relocations); see more below. */
4960 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4963 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4965 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4968 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4971 || (symbol_section_p (fixP
->fx_addsy
)
4972 && sym_seg
!= absolute_section
))
4973 && !generic_force_reloc (fixP
))
4975 /* Yes, we add the values in twice. This is because
4976 bfd_install_relocation subtracts them out again. I think
4977 bfd_install_relocation is broken, but I don't dare change
4979 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4983 #if defined (OBJ_COFF) && defined (TE_PE)
4984 /* For some reason, the PE format does not store a
4985 section address offset for a PC relative symbol. */
4986 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4987 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4988 || S_IS_WEAK (fixP
->fx_addsy
)
4991 value
+= md_pcrel_from (fixP
);
4995 /* Fix a few things - the dynamic linker expects certain values here,
4996 and we must not disappoint it. */
4997 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4998 if (IS_ELF
&& fixP
->fx_addsy
)
4999 switch (fixP
->fx_r_type
)
5001 case BFD_RELOC_386_PLT32
:
5002 case BFD_RELOC_X86_64_PLT32
:
5003 /* Make the jump instruction point to the address of the operand. At
5004 runtime we merely add the offset to the actual PLT entry. */
5008 case BFD_RELOC_386_TLS_GD
:
5009 case BFD_RELOC_386_TLS_LDM
:
5010 case BFD_RELOC_386_TLS_IE_32
:
5011 case BFD_RELOC_386_TLS_IE
:
5012 case BFD_RELOC_386_TLS_GOTIE
:
5013 case BFD_RELOC_X86_64_TLSGD
:
5014 case BFD_RELOC_X86_64_TLSLD
:
5015 case BFD_RELOC_X86_64_GOTTPOFF
:
5016 value
= 0; /* Fully resolved at runtime. No addend. */
5018 case BFD_RELOC_386_TLS_LE
:
5019 case BFD_RELOC_386_TLS_LDO_32
:
5020 case BFD_RELOC_386_TLS_LE_32
:
5021 case BFD_RELOC_X86_64_DTPOFF32
:
5022 case BFD_RELOC_X86_64_DTPOFF64
:
5023 case BFD_RELOC_X86_64_TPOFF32
:
5024 case BFD_RELOC_X86_64_TPOFF64
:
5025 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5028 case BFD_RELOC_386_GOT32
:
5029 case BFD_RELOC_X86_64_GOT32
:
5030 value
= 0; /* Fully resolved at runtime. No addend. */
5033 case BFD_RELOC_VTABLE_INHERIT
:
5034 case BFD_RELOC_VTABLE_ENTRY
:
5041 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5043 #endif /* !defined (TE_Mach) */
5045 /* Are we finished with this relocation now? */
5046 if (fixP
->fx_addsy
== NULL
)
5048 else if (use_rela_relocations
)
5050 fixP
->fx_no_overflow
= 1;
5051 /* Remember value for tc_gen_reloc. */
5052 fixP
->fx_addnumber
= value
;
5056 md_number_to_chars (p
, value
, fixP
->fx_size
);
5059 #define MAX_LITTLENUMS 6
5061 /* Turn the string pointed to by litP into a floating point constant
5062 of type TYPE, and emit the appropriate bytes. The number of
5063 LITTLENUMS emitted is stored in *SIZEP. An error message is
5064 returned, or NULL on OK. */
5067 md_atof (type
, litP
, sizeP
)
5073 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5074 LITTLENUM_TYPE
*wordP
;
5096 return _("Bad call to md_atof ()");
5098 t
= atof_ieee (input_line_pointer
, type
, words
);
5100 input_line_pointer
= t
;
5102 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5103 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5104 the bigendian 386. */
5105 for (wordP
= words
+ prec
- 1; prec
--;)
5107 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5108 litP
+= sizeof (LITTLENUM_TYPE
);
5113 static char output_invalid_buf
[8];
5120 sprintf (output_invalid_buf
, "'%c'", c
);
5122 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5123 return output_invalid_buf
;
5126 /* REG_STRING starts *before* REGISTER_PREFIX. */
5128 static const reg_entry
*
5129 parse_register (reg_string
, end_op
)
5133 char *s
= reg_string
;
5135 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5138 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5139 if (*s
== REGISTER_PREFIX
)
5142 if (is_space_char (*s
))
5146 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5148 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5149 return (const reg_entry
*) NULL
;
5153 /* For naked regs, make sure that we are not dealing with an identifier.
5154 This prevents confusing an identifier like `eax_var' with register
5156 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5157 return (const reg_entry
*) NULL
;
5161 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5163 /* Handle floating point regs, allowing spaces in the (i) part. */
5164 if (r
== i386_regtab
/* %st is first entry of table */)
5166 if (is_space_char (*s
))
5171 if (is_space_char (*s
))
5173 if (*s
>= '0' && *s
<= '7')
5175 r
= &i386_float_regtab
[*s
- '0'];
5177 if (is_space_char (*s
))
5185 /* We have "%st(" then garbage. */
5186 return (const reg_entry
*) NULL
;
5191 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5192 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5193 && flag_code
!= CODE_64BIT
)
5194 return (const reg_entry
*) NULL
;
5199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5200 const char *md_shortopts
= "kVQ:sqn";
5202 const char *md_shortopts
= "qn";
5205 struct option md_longopts
[] = {
5206 #define OPTION_32 (OPTION_MD_BASE + 0)
5207 {"32", no_argument
, NULL
, OPTION_32
},
5208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5209 #define OPTION_64 (OPTION_MD_BASE + 1)
5210 {"64", no_argument
, NULL
, OPTION_64
},
5212 {NULL
, no_argument
, NULL
, 0}
5214 size_t md_longopts_size
= sizeof (md_longopts
);
5217 md_parse_option (c
, arg
)
5219 char *arg ATTRIBUTE_UNUSED
;
5224 optimize_align_code
= 0;
5231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5232 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5233 should be emitted or not. FIXME: Not implemented. */
5237 /* -V: SVR4 argument to print version ID. */
5239 print_version_id ();
5242 /* -k: Ignore for FreeBSD compatibility. */
5247 /* -s: On i386 Solaris, this tells the native assembler to use
5248 .stab instead of .stab.excl. We always use .stab anyhow. */
5253 const char **list
, **l
;
5255 list
= bfd_target_list ();
5256 for (l
= list
; *l
!= NULL
; l
++)
5257 if (strcmp (*l
, "elf64-x86-64") == 0)
5259 default_arch
= "x86_64";
5263 as_fatal (_("No compiled in support for x86_64"));
5270 default_arch
= "i386";
5280 md_show_usage (stream
)
5283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5284 fprintf (stream
, _("\
5286 -V print assembler version number\n\
5288 -n Do not optimize code alignment\n\
5289 -q quieten some warnings\n\
5292 fprintf (stream
, _("\
5293 -n Do not optimize code alignment\n\
5294 -q quieten some warnings\n"));
5298 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5299 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5301 /* Pick the target format to use. */
5304 i386_target_format ()
5306 if (!strcmp (default_arch
, "x86_64"))
5307 set_code_flag (CODE_64BIT
);
5308 else if (!strcmp (default_arch
, "i386"))
5309 set_code_flag (CODE_32BIT
);
5311 as_fatal (_("Unknown architecture"));
5312 switch (OUTPUT_FLAVOR
)
5314 #ifdef OBJ_MAYBE_AOUT
5315 case bfd_target_aout_flavour
:
5316 return AOUT_TARGET_FORMAT
;
5318 #ifdef OBJ_MAYBE_COFF
5319 case bfd_target_coff_flavour
:
5322 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5323 case bfd_target_elf_flavour
:
5325 if (flag_code
== CODE_64BIT
)
5326 use_rela_relocations
= 1;
5327 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5336 #endif /* OBJ_MAYBE_ more than one */
5338 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5339 void i386_elf_emit_arch_note ()
5341 if (IS_ELF
&& cpu_arch_name
!= NULL
)
5344 asection
*seg
= now_seg
;
5345 subsegT subseg
= now_subseg
;
5346 Elf_Internal_Note i_note
;
5347 Elf_External_Note e_note
;
5348 asection
*note_secp
;
5351 /* Create the .note section. */
5352 note_secp
= subseg_new (".note", 0);
5353 bfd_set_section_flags (stdoutput
,
5355 SEC_HAS_CONTENTS
| SEC_READONLY
);
5357 /* Process the arch string. */
5358 len
= strlen (cpu_arch_name
);
5360 i_note
.namesz
= len
+ 1;
5362 i_note
.type
= NT_ARCH
;
5363 p
= frag_more (sizeof (e_note
.namesz
));
5364 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5365 p
= frag_more (sizeof (e_note
.descsz
));
5366 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5367 p
= frag_more (sizeof (e_note
.type
));
5368 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5369 p
= frag_more (len
+ 1);
5370 strcpy (p
, cpu_arch_name
);
5372 frag_align (2, 0, 0);
5374 subseg_set (seg
, subseg
);
5380 md_undefined_symbol (name
)
5383 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5384 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5385 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5386 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5390 if (symbol_find (name
))
5391 as_bad (_("GOT already in symbol table"));
5392 GOT_symbol
= symbol_new (name
, undefined_section
,
5393 (valueT
) 0, &zero_address_frag
);
5400 /* Round up a section size to the appropriate boundary. */
5403 md_section_align (segment
, size
)
5404 segT segment ATTRIBUTE_UNUSED
;
5407 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5408 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5410 /* For a.out, force the section size to be aligned. If we don't do
5411 this, BFD will align it for us, but it will not write out the
5412 final bytes of the section. This may be a bug in BFD, but it is
5413 easier to fix it here since that is how the other a.out targets
5417 align
= bfd_get_section_alignment (stdoutput
, segment
);
5418 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5425 /* On the i386, PC-relative offsets are relative to the start of the
5426 next instruction. That is, the address of the offset, plus its
5427 size, since the offset is always the last part of the insn. */
5430 md_pcrel_from (fixP
)
5433 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5440 int ignore ATTRIBUTE_UNUSED
;
5444 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5446 obj_elf_section_change_hook ();
5448 temp
= get_absolute_expression ();
5449 subseg_set (bss_section
, (subsegT
) temp
);
5450 demand_empty_rest_of_line ();
5456 i386_validate_fix (fixp
)
5459 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5461 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5463 if (flag_code
!= CODE_64BIT
)
5465 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5469 if (flag_code
!= CODE_64BIT
)
5470 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5472 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5479 tc_gen_reloc (section
, fixp
)
5480 asection
*section ATTRIBUTE_UNUSED
;
5484 bfd_reloc_code_real_type code
;
5486 switch (fixp
->fx_r_type
)
5488 case BFD_RELOC_X86_64_PLT32
:
5489 case BFD_RELOC_X86_64_GOT32
:
5490 case BFD_RELOC_X86_64_GOTPCREL
:
5491 case BFD_RELOC_386_PLT32
:
5492 case BFD_RELOC_386_GOT32
:
5493 case BFD_RELOC_386_GOTOFF
:
5494 case BFD_RELOC_386_GOTPC
:
5495 case BFD_RELOC_386_TLS_GD
:
5496 case BFD_RELOC_386_TLS_LDM
:
5497 case BFD_RELOC_386_TLS_LDO_32
:
5498 case BFD_RELOC_386_TLS_IE_32
:
5499 case BFD_RELOC_386_TLS_IE
:
5500 case BFD_RELOC_386_TLS_GOTIE
:
5501 case BFD_RELOC_386_TLS_LE_32
:
5502 case BFD_RELOC_386_TLS_LE
:
5503 case BFD_RELOC_X86_64_TLSGD
:
5504 case BFD_RELOC_X86_64_TLSLD
:
5505 case BFD_RELOC_X86_64_DTPOFF32
:
5506 case BFD_RELOC_X86_64_DTPOFF64
:
5507 case BFD_RELOC_X86_64_GOTTPOFF
:
5508 case BFD_RELOC_X86_64_TPOFF32
:
5509 case BFD_RELOC_X86_64_TPOFF64
:
5510 case BFD_RELOC_X86_64_GOTOFF64
:
5511 case BFD_RELOC_X86_64_GOTPC32
:
5513 case BFD_RELOC_VTABLE_ENTRY
:
5514 case BFD_RELOC_VTABLE_INHERIT
:
5516 case BFD_RELOC_32_SECREL
:
5518 code
= fixp
->fx_r_type
;
5520 case BFD_RELOC_X86_64_32S
:
5521 if (!fixp
->fx_pcrel
)
5523 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5524 code
= fixp
->fx_r_type
;
5530 switch (fixp
->fx_size
)
5533 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5534 _("can not do %d byte pc-relative relocation"),
5536 code
= BFD_RELOC_32_PCREL
;
5538 case 1: code
= BFD_RELOC_8_PCREL
; break;
5539 case 2: code
= BFD_RELOC_16_PCREL
; break;
5540 case 4: code
= BFD_RELOC_32_PCREL
; break;
5542 case 8: code
= BFD_RELOC_64_PCREL
; break;
5548 switch (fixp
->fx_size
)
5551 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5552 _("can not do %d byte relocation"),
5554 code
= BFD_RELOC_32
;
5556 case 1: code
= BFD_RELOC_8
; break;
5557 case 2: code
= BFD_RELOC_16
; break;
5558 case 4: code
= BFD_RELOC_32
; break;
5560 case 8: code
= BFD_RELOC_64
; break;
5567 if ((code
== BFD_RELOC_32
|| code
== BFD_RELOC_32_PCREL
)
5569 && fixp
->fx_addsy
== GOT_symbol
)
5571 if (flag_code
!= CODE_64BIT
)
5572 code
= BFD_RELOC_386_GOTPC
;
5574 code
= BFD_RELOC_X86_64_GOTPC32
;
5577 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5578 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5579 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5581 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5583 if (!use_rela_relocations
)
5585 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5586 vtable entry to be used in the relocation's section offset. */
5587 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5588 rel
->address
= fixp
->fx_offset
;
5592 /* Use the rela in 64bit mode. */
5595 if (!fixp
->fx_pcrel
)
5596 rel
->addend
= fixp
->fx_offset
;
5600 case BFD_RELOC_X86_64_PLT32
:
5601 case BFD_RELOC_X86_64_GOT32
:
5602 case BFD_RELOC_X86_64_GOTPCREL
:
5603 case BFD_RELOC_X86_64_TLSGD
:
5604 case BFD_RELOC_X86_64_TLSLD
:
5605 case BFD_RELOC_X86_64_GOTTPOFF
:
5606 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5609 rel
->addend
= (section
->vma
5611 + fixp
->fx_addnumber
5612 + md_pcrel_from (fixp
));
5617 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5618 if (rel
->howto
== NULL
)
5620 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5621 _("cannot represent relocation type %s"),
5622 bfd_get_reloc_code_name (code
));
5623 /* Set howto to a garbage value so that we can keep going. */
5624 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5625 assert (rel
->howto
!= NULL
);
5632 /* Parse operands using Intel syntax. This implements a recursive descent
5633 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5636 FIXME: We do not recognize the full operand grammar defined in the MASM
5637 documentation. In particular, all the structure/union and
5638 high-level macro operands are missing.
5640 Uppercase words are terminals, lower case words are non-terminals.
5641 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5642 bars '|' denote choices. Most grammar productions are implemented in
5643 functions called 'intel_<production>'.
5645 Initial production is 'expr'.
5651 binOp & | AND | \| | OR | ^ | XOR
5653 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5655 constant digits [[ radixOverride ]]
5657 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5695 => expr expr cmpOp e04
5698 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5699 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5701 hexdigit a | b | c | d | e | f
5702 | A | B | C | D | E | F
5708 mulOp * | / | % | MOD | << | SHL | >> | SHR
5712 register specialRegister
5716 segmentRegister CS | DS | ES | FS | GS | SS
5718 specialRegister CR0 | CR2 | CR3 | CR4
5719 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5720 | TR3 | TR4 | TR5 | TR6 | TR7
5722 We simplify the grammar in obvious places (e.g., register parsing is
5723 done by calling parse_register) and eliminate immediate left recursion
5724 to implement a recursive-descent parser.
5728 expr' cmpOp e04 expr'
5779 /* Parsing structure for the intel syntax parser. Used to implement the
5780 semantic actions for the operand grammar. */
5781 struct intel_parser_s
5783 char *op_string
; /* The string being parsed. */
5784 int got_a_float
; /* Whether the operand is a float. */
5785 int op_modifier
; /* Operand modifier. */
5786 int is_mem
; /* 1 if operand is memory reference. */
5787 int in_offset
; /* >=1 if parsing operand of offset. */
5788 int in_bracket
; /* >=1 if parsing operand in brackets. */
5789 const reg_entry
*reg
; /* Last register reference found. */
5790 char *disp
; /* Displacement string being built. */
5791 char *next_operand
; /* Resume point when splitting operands. */
5794 static struct intel_parser_s intel_parser
;
5796 /* Token structure for parsing intel syntax. */
5799 int code
; /* Token code. */
5800 const reg_entry
*reg
; /* Register entry for register tokens. */
5801 char *str
; /* String representation. */
5804 static struct intel_token cur_token
, prev_token
;
5806 /* Token codes for the intel parser. Since T_SHORT is already used
5807 by COFF, undefine it first to prevent a warning. */
5826 /* Prototypes for intel parser functions. */
5827 static int intel_match_token
PARAMS ((int code
));
5828 static void intel_get_token
PARAMS ((void));
5829 static void intel_putback_token
PARAMS ((void));
5830 static int intel_expr
PARAMS ((void));
5831 static int intel_e04
PARAMS ((void));
5832 static int intel_e05
PARAMS ((void));
5833 static int intel_e06
PARAMS ((void));
5834 static int intel_e09
PARAMS ((void));
5835 static int intel_bracket_expr
PARAMS ((void));
5836 static int intel_e10
PARAMS ((void));
5837 static int intel_e11
PARAMS ((void));
5840 i386_intel_operand (operand_string
, got_a_float
)
5841 char *operand_string
;
5847 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5848 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5852 /* Initialize token holders. */
5853 cur_token
.code
= prev_token
.code
= T_NIL
;
5854 cur_token
.reg
= prev_token
.reg
= NULL
;
5855 cur_token
.str
= prev_token
.str
= NULL
;
5857 /* Initialize parser structure. */
5858 intel_parser
.got_a_float
= got_a_float
;
5859 intel_parser
.op_modifier
= 0;
5860 intel_parser
.is_mem
= 0;
5861 intel_parser
.in_offset
= 0;
5862 intel_parser
.in_bracket
= 0;
5863 intel_parser
.reg
= NULL
;
5864 intel_parser
.disp
[0] = '\0';
5865 intel_parser
.next_operand
= NULL
;
5867 /* Read the first token and start the parser. */
5869 ret
= intel_expr ();
5874 if (cur_token
.code
!= T_NIL
)
5876 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5877 current_templates
->start
->name
, cur_token
.str
);
5880 /* If we found a memory reference, hand it over to i386_displacement
5881 to fill in the rest of the operand fields. */
5882 else if (intel_parser
.is_mem
)
5884 if ((i
.mem_operands
== 1
5885 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5886 || i
.mem_operands
== 2)
5888 as_bad (_("too many memory references for '%s'"),
5889 current_templates
->start
->name
);
5894 char *s
= intel_parser
.disp
;
5897 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5898 /* See the comments in intel_bracket_expr. */
5899 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5901 /* Add the displacement expression. */
5903 ret
= i386_displacement (s
, s
+ strlen (s
));
5906 /* Swap base and index in 16-bit memory operands like
5907 [si+bx]. Since i386_index_check is also used in AT&T
5908 mode we have to do that here. */
5911 && (i
.base_reg
->reg_type
& Reg16
)
5912 && (i
.index_reg
->reg_type
& Reg16
)
5913 && i
.base_reg
->reg_num
>= 6
5914 && i
.index_reg
->reg_num
< 6)
5916 const reg_entry
*base
= i
.index_reg
;
5918 i
.index_reg
= i
.base_reg
;
5921 ret
= i386_index_check (operand_string
);
5926 /* Constant and OFFSET expressions are handled by i386_immediate. */
5927 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5928 || intel_parser
.reg
== NULL
)
5929 ret
= i386_immediate (intel_parser
.disp
);
5931 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5933 if (!ret
|| !intel_parser
.next_operand
)
5935 intel_parser
.op_string
= intel_parser
.next_operand
;
5936 this_operand
= i
.operands
++;
5940 free (intel_parser
.disp
);
5945 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5949 expr' cmpOp e04 expr'
5954 /* XXX Implement the comparison operators. */
5955 return intel_e04 ();
5972 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5973 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5975 if (cur_token
.code
== '+')
5977 else if (cur_token
.code
== '-')
5978 nregs
= NUM_ADDRESS_REGS
;
5982 strcat (intel_parser
.disp
, cur_token
.str
);
5983 intel_match_token (cur_token
.code
);
5994 int nregs
= ~NUM_ADDRESS_REGS
;
6001 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6005 str
[0] = cur_token
.code
;
6007 strcat (intel_parser
.disp
, str
);
6012 intel_match_token (cur_token
.code
);
6017 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6018 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6029 int nregs
= ~NUM_ADDRESS_REGS
;
6036 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6040 str
[0] = cur_token
.code
;
6042 strcat (intel_parser
.disp
, str
);
6044 else if (cur_token
.code
== T_SHL
)
6045 strcat (intel_parser
.disp
, "<<");
6046 else if (cur_token
.code
== T_SHR
)
6047 strcat (intel_parser
.disp
, ">>");
6051 intel_match_token (cur_token
.code
);
6056 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6057 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6075 int nregs
= ~NUM_ADDRESS_REGS
;
6080 /* Don't consume constants here. */
6081 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6083 /* Need to look one token ahead - if the next token
6084 is a constant, the current token is its sign. */
6087 intel_match_token (cur_token
.code
);
6088 next_code
= cur_token
.code
;
6089 intel_putback_token ();
6090 if (next_code
== T_CONST
)
6094 /* e09 OFFSET e09 */
6095 if (cur_token
.code
== T_OFFSET
)
6098 ++intel_parser
.in_offset
;
6102 else if (cur_token
.code
== T_SHORT
)
6103 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6106 else if (cur_token
.code
== '+')
6107 strcat (intel_parser
.disp
, "+");
6112 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6118 str
[0] = cur_token
.code
;
6120 strcat (intel_parser
.disp
, str
);
6127 intel_match_token (cur_token
.code
);
6135 /* e09' PTR e10 e09' */
6136 if (cur_token
.code
== T_PTR
)
6140 if (prev_token
.code
== T_BYTE
)
6141 suffix
= BYTE_MNEM_SUFFIX
;
6143 else if (prev_token
.code
== T_WORD
)
6145 if (current_templates
->start
->name
[0] == 'l'
6146 && current_templates
->start
->name
[2] == 's'
6147 && current_templates
->start
->name
[3] == 0)
6148 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6149 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6150 suffix
= SHORT_MNEM_SUFFIX
;
6152 suffix
= WORD_MNEM_SUFFIX
;
6155 else if (prev_token
.code
== T_DWORD
)
6157 if (current_templates
->start
->name
[0] == 'l'
6158 && current_templates
->start
->name
[2] == 's'
6159 && current_templates
->start
->name
[3] == 0)
6160 suffix
= WORD_MNEM_SUFFIX
;
6161 else if (flag_code
== CODE_16BIT
6162 && (current_templates
->start
->opcode_modifier
6163 & (Jump
|JumpDword
|JumpInterSegment
)))
6164 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6165 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6166 suffix
= SHORT_MNEM_SUFFIX
;
6168 suffix
= LONG_MNEM_SUFFIX
;
6171 else if (prev_token
.code
== T_FWORD
)
6173 if (current_templates
->start
->name
[0] == 'l'
6174 && current_templates
->start
->name
[2] == 's'
6175 && current_templates
->start
->name
[3] == 0)
6176 suffix
= LONG_MNEM_SUFFIX
;
6177 else if (!intel_parser
.got_a_float
)
6179 if (flag_code
== CODE_16BIT
)
6180 add_prefix (DATA_PREFIX_OPCODE
);
6181 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6184 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6187 else if (prev_token
.code
== T_QWORD
)
6189 if (intel_parser
.got_a_float
== 1) /* "f..." */
6190 suffix
= LONG_MNEM_SUFFIX
;
6192 suffix
= QWORD_MNEM_SUFFIX
;
6195 else if (prev_token
.code
== T_TBYTE
)
6197 if (intel_parser
.got_a_float
== 1)
6198 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6200 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6203 else if (prev_token
.code
== T_XMMWORD
)
6205 /* XXX ignored for now, but accepted since gcc uses it */
6211 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6215 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6219 else if (i
.suffix
!= suffix
)
6221 as_bad (_("Conflicting operand modifiers"));
6227 /* e09' : e10 e09' */
6228 else if (cur_token
.code
== ':')
6230 if (prev_token
.code
!= T_REG
)
6232 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6233 segment/group identifier (which we don't have), using comma
6234 as the operand separator there is even less consistent, since
6235 there all branches only have a single operand. */
6236 if (this_operand
!= 0
6237 || intel_parser
.in_offset
6238 || intel_parser
.in_bracket
6239 || (!(current_templates
->start
->opcode_modifier
6240 & (Jump
|JumpDword
|JumpInterSegment
))
6241 && !(current_templates
->start
->operand_types
[0]
6243 return intel_match_token (T_NIL
);
6244 /* Remember the start of the 2nd operand and terminate 1st
6246 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6247 another expression), but it gets at least the simplest case
6248 (a plain number or symbol on the left side) right. */
6249 intel_parser
.next_operand
= intel_parser
.op_string
;
6250 *--intel_parser
.op_string
= '\0';
6251 return intel_match_token (':');
6259 intel_match_token (cur_token
.code
);
6265 --intel_parser
.in_offset
;
6268 if (NUM_ADDRESS_REGS
> nregs
)
6270 as_bad (_("Invalid operand to `OFFSET'"));
6273 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6276 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6277 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6282 intel_bracket_expr ()
6284 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6285 const char *start
= intel_parser
.op_string
;
6288 if (i
.op
[this_operand
].regs
)
6289 return intel_match_token (T_NIL
);
6291 intel_match_token ('[');
6293 /* Mark as a memory operand only if it's not already known to be an
6294 offset expression. If it's an offset expression, we need to keep
6296 if (!intel_parser
.in_offset
)
6298 ++intel_parser
.in_bracket
;
6299 /* Unfortunately gas always diverged from MASM in a respect that can't
6300 be easily fixed without risking to break code sequences likely to be
6301 encountered (the testsuite even check for this): MASM doesn't consider
6302 an expression inside brackets unconditionally as a memory reference.
6303 When that is e.g. a constant, an offset expression, or the sum of the
6304 two, this is still taken as a constant load. gas, however, always
6305 treated these as memory references. As a compromise, we'll try to make
6306 offset expressions inside brackets work the MASM way (since that's
6307 less likely to be found in real world code), but make constants alone
6308 continue to work the traditional gas way. In either case, issue a
6310 intel_parser
.op_modifier
&= ~was_offset
;
6313 strcat (intel_parser
.disp
, "[");
6315 /* Add a '+' to the displacement string if necessary. */
6316 if (*intel_parser
.disp
!= '\0'
6317 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6318 strcat (intel_parser
.disp
, "+");
6321 && (len
= intel_parser
.op_string
- start
- 1,
6322 intel_match_token (']')))
6324 /* Preserve brackets when the operand is an offset expression. */
6325 if (intel_parser
.in_offset
)
6326 strcat (intel_parser
.disp
, "]");
6329 --intel_parser
.in_bracket
;
6330 if (i
.base_reg
|| i
.index_reg
)
6331 intel_parser
.is_mem
= 1;
6332 if (!intel_parser
.is_mem
)
6334 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6335 /* Defer the warning until all of the operand was parsed. */
6336 intel_parser
.is_mem
= -1;
6337 else if (!quiet_warnings
)
6338 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6341 intel_parser
.op_modifier
|= was_offset
;
6358 while (cur_token
.code
== '[')
6360 if (!intel_bracket_expr ())
6385 switch (cur_token
.code
)
6389 intel_match_token ('(');
6390 strcat (intel_parser
.disp
, "(");
6392 if (intel_expr () && intel_match_token (')'))
6394 strcat (intel_parser
.disp
, ")");
6401 /* Operands for jump/call inside brackets denote absolute addresses.
6402 XXX This shouldn't be needed anymore (or if it should rather live
6403 in intel_bracket_expr). */
6404 if (current_templates
->start
->opcode_modifier
6405 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6406 i
.types
[this_operand
] |= JumpAbsolute
;
6408 return intel_bracket_expr ();
6413 strcat (intel_parser
.disp
, cur_token
.str
);
6414 intel_match_token (cur_token
.code
);
6416 /* Mark as a memory operand only if it's not already known to be an
6417 offset expression. */
6418 if (!intel_parser
.in_offset
)
6419 intel_parser
.is_mem
= 1;
6426 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6428 intel_match_token (T_REG
);
6430 /* Check for segment change. */
6431 if (cur_token
.code
== ':')
6433 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6435 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6438 else if (i
.seg
[i
.mem_operands
])
6439 as_warn (_("Extra segment override ignored"));
6442 if (!intel_parser
.in_offset
)
6443 intel_parser
.is_mem
= 1;
6444 switch (reg
->reg_num
)
6447 i
.seg
[i
.mem_operands
] = &es
;
6450 i
.seg
[i
.mem_operands
] = &cs
;
6453 i
.seg
[i
.mem_operands
] = &ss
;
6456 i
.seg
[i
.mem_operands
] = &ds
;
6459 i
.seg
[i
.mem_operands
] = &fs
;
6462 i
.seg
[i
.mem_operands
] = &gs
;
6468 /* Not a segment register. Check for register scaling. */
6469 else if (cur_token
.code
== '*')
6471 if (!intel_parser
.in_bracket
)
6473 as_bad (_("Register scaling only allowed in memory operands"));
6477 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6478 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6479 else if (i
.index_reg
)
6480 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6482 /* What follows must be a valid scale. */
6483 intel_match_token ('*');
6485 i
.types
[this_operand
] |= BaseIndex
;
6487 /* Set the scale after setting the register (otherwise,
6488 i386_scale will complain) */
6489 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6491 char *str
, sign
= cur_token
.code
;
6492 intel_match_token (cur_token
.code
);
6493 if (cur_token
.code
!= T_CONST
)
6495 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6499 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6500 strcpy (str
+ 1, cur_token
.str
);
6502 if (!i386_scale (str
))
6506 else if (!i386_scale (cur_token
.str
))
6508 intel_match_token (cur_token
.code
);
6511 /* No scaling. If this is a memory operand, the register is either a
6512 base register (first occurrence) or an index register (second
6514 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6519 else if (!i
.index_reg
)
6523 as_bad (_("Too many register references in memory operand"));
6527 i
.types
[this_operand
] |= BaseIndex
;
6530 /* Offset modifier. Add the register to the displacement string to be
6531 parsed as an immediate expression after we're done. */
6532 else if (intel_parser
.in_offset
)
6534 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6535 strcat (intel_parser
.disp
, reg
->reg_name
);
6538 /* It's neither base nor index nor offset. */
6539 else if (!intel_parser
.is_mem
)
6541 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6542 i
.op
[this_operand
].regs
= reg
;
6547 as_bad (_("Invalid use of register"));
6551 /* Since registers are not part of the displacement string (except
6552 when we're parsing offset operands), we may need to remove any
6553 preceding '+' from the displacement string. */
6554 if (*intel_parser
.disp
!= '\0'
6555 && !intel_parser
.in_offset
)
6557 char *s
= intel_parser
.disp
;
6558 s
+= strlen (s
) - 1;
6581 intel_match_token (cur_token
.code
);
6583 if (cur_token
.code
== T_PTR
)
6586 /* It must have been an identifier. */
6587 intel_putback_token ();
6588 cur_token
.code
= T_ID
;
6594 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6598 /* The identifier represents a memory reference only if it's not
6599 preceded by an offset modifier and if it's not an equate. */
6600 symbolP
= symbol_find(cur_token
.str
);
6601 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6602 intel_parser
.is_mem
= 1;
6610 char *save_str
, sign
= 0;
6612 /* Allow constants that start with `+' or `-'. */
6613 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6615 sign
= cur_token
.code
;
6616 intel_match_token (cur_token
.code
);
6617 if (cur_token
.code
!= T_CONST
)
6619 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6625 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6626 strcpy (save_str
+ !!sign
, cur_token
.str
);
6630 /* Get the next token to check for register scaling. */
6631 intel_match_token (cur_token
.code
);
6633 /* Check if this constant is a scaling factor for an index register. */
6634 if (cur_token
.code
== '*')
6636 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6638 const reg_entry
*reg
= cur_token
.reg
;
6640 if (!intel_parser
.in_bracket
)
6642 as_bad (_("Register scaling only allowed in memory operands"));
6646 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6647 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6648 else if (i
.index_reg
)
6649 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6651 /* The constant is followed by `* reg', so it must be
6654 i
.types
[this_operand
] |= BaseIndex
;
6656 /* Set the scale after setting the register (otherwise,
6657 i386_scale will complain) */
6658 if (!i386_scale (save_str
))
6660 intel_match_token (T_REG
);
6662 /* Since registers are not part of the displacement
6663 string, we may need to remove any preceding '+' from
6664 the displacement string. */
6665 if (*intel_parser
.disp
!= '\0')
6667 char *s
= intel_parser
.disp
;
6668 s
+= strlen (s
) - 1;
6678 /* The constant was not used for register scaling. Since we have
6679 already consumed the token following `*' we now need to put it
6680 back in the stream. */
6681 intel_putback_token ();
6684 /* Add the constant to the displacement string. */
6685 strcat (intel_parser
.disp
, save_str
);
6692 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6696 /* Match the given token against cur_token. If they match, read the next
6697 token from the operand string. */
6699 intel_match_token (code
)
6702 if (cur_token
.code
== code
)
6709 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6714 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6719 const reg_entry
*reg
;
6720 struct intel_token new_token
;
6722 new_token
.code
= T_NIL
;
6723 new_token
.reg
= NULL
;
6724 new_token
.str
= NULL
;
6726 /* Free the memory allocated to the previous token and move
6727 cur_token to prev_token. */
6729 free (prev_token
.str
);
6731 prev_token
= cur_token
;
6733 /* Skip whitespace. */
6734 while (is_space_char (*intel_parser
.op_string
))
6735 intel_parser
.op_string
++;
6737 /* Return an empty token if we find nothing else on the line. */
6738 if (*intel_parser
.op_string
== '\0')
6740 cur_token
= new_token
;
6744 /* The new token cannot be larger than the remainder of the operand
6746 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6747 new_token
.str
[0] = '\0';
6749 if (strchr ("0123456789", *intel_parser
.op_string
))
6751 char *p
= new_token
.str
;
6752 char *q
= intel_parser
.op_string
;
6753 new_token
.code
= T_CONST
;
6755 /* Allow any kind of identifier char to encompass floating point and
6756 hexadecimal numbers. */
6757 while (is_identifier_char (*q
))
6761 /* Recognize special symbol names [0-9][bf]. */
6762 if (strlen (intel_parser
.op_string
) == 2
6763 && (intel_parser
.op_string
[1] == 'b'
6764 || intel_parser
.op_string
[1] == 'f'))
6765 new_token
.code
= T_ID
;
6768 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6769 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6771 new_token
.code
= T_REG
;
6772 new_token
.reg
= reg
;
6774 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6776 new_token
.str
[0] = REGISTER_PREFIX
;
6777 new_token
.str
[1] = '\0';
6780 strcat (new_token
.str
, reg
->reg_name
);
6783 else if (is_identifier_char (*intel_parser
.op_string
))
6785 char *p
= new_token
.str
;
6786 char *q
= intel_parser
.op_string
;
6788 /* A '.' or '$' followed by an identifier char is an identifier.
6789 Otherwise, it's operator '.' followed by an expression. */
6790 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6792 new_token
.code
= '.';
6793 new_token
.str
[0] = '.';
6794 new_token
.str
[1] = '\0';
6798 while (is_identifier_char (*q
) || *q
== '@')
6802 if (strcasecmp (new_token
.str
, "NOT") == 0)
6803 new_token
.code
= '~';
6805 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6806 new_token
.code
= '%';
6808 else if (strcasecmp (new_token
.str
, "AND") == 0)
6809 new_token
.code
= '&';
6811 else if (strcasecmp (new_token
.str
, "OR") == 0)
6812 new_token
.code
= '|';
6814 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6815 new_token
.code
= '^';
6817 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6818 new_token
.code
= T_SHL
;
6820 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6821 new_token
.code
= T_SHR
;
6823 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6824 new_token
.code
= T_BYTE
;
6826 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6827 new_token
.code
= T_WORD
;
6829 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6830 new_token
.code
= T_DWORD
;
6832 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6833 new_token
.code
= T_FWORD
;
6835 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6836 new_token
.code
= T_QWORD
;
6838 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6839 /* XXX remove (gcc still uses it) */
6840 || strcasecmp (new_token
.str
, "XWORD") == 0)
6841 new_token
.code
= T_TBYTE
;
6843 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6844 || strcasecmp (new_token
.str
, "OWORD") == 0)
6845 new_token
.code
= T_XMMWORD
;
6847 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6848 new_token
.code
= T_PTR
;
6850 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6851 new_token
.code
= T_SHORT
;
6853 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6855 new_token
.code
= T_OFFSET
;
6857 /* ??? This is not mentioned in the MASM grammar but gcc
6858 makes use of it with -mintel-syntax. OFFSET may be
6859 followed by FLAT: */
6860 if (strncasecmp (q
, " FLAT:", 6) == 0)
6861 strcat (new_token
.str
, " FLAT:");
6864 /* ??? This is not mentioned in the MASM grammar. */
6865 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6867 new_token
.code
= T_OFFSET
;
6869 strcat (new_token
.str
, ":");
6871 as_bad (_("`:' expected"));
6875 new_token
.code
= T_ID
;
6879 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6881 new_token
.code
= *intel_parser
.op_string
;
6882 new_token
.str
[0] = *intel_parser
.op_string
;
6883 new_token
.str
[1] = '\0';
6886 else if (strchr ("<>", *intel_parser
.op_string
)
6887 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6889 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6890 new_token
.str
[0] = *intel_parser
.op_string
;
6891 new_token
.str
[1] = *intel_parser
.op_string
;
6892 new_token
.str
[2] = '\0';
6896 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6898 intel_parser
.op_string
+= strlen (new_token
.str
);
6899 cur_token
= new_token
;
6902 /* Put cur_token back into the token stream and make cur_token point to
6905 intel_putback_token ()
6907 if (cur_token
.code
!= T_NIL
)
6909 intel_parser
.op_string
-= strlen (cur_token
.str
);
6910 free (cur_token
.str
);
6912 cur_token
= prev_token
;
6914 /* Forget prev_token. */
6915 prev_token
.code
= T_NIL
;
6916 prev_token
.reg
= NULL
;
6917 prev_token
.str
= NULL
;
6921 tc_x86_regname_to_dw2regnum (const char *regname
)
6923 unsigned int regnum
;
6924 unsigned int regnames_count
;
6925 static const char *const regnames_32
[] =
6927 "eax", "ecx", "edx", "ebx",
6928 "esp", "ebp", "esi", "edi",
6929 "eip", "eflags", NULL
,
6930 "st0", "st1", "st2", "st3",
6931 "st4", "st5", "st6", "st7",
6933 "xmm0", "xmm1", "xmm2", "xmm3",
6934 "xmm4", "xmm5", "xmm6", "xmm7",
6935 "mm0", "mm1", "mm2", "mm3",
6936 "mm4", "mm5", "mm6", "mm7"
6938 static const char *const regnames_64
[] =
6940 "rax", "rdx", "rcx", "rbx",
6941 "rsi", "rdi", "rbp", "rsp",
6942 "r8", "r9", "r10", "r11",
6943 "r12", "r13", "r14", "r15",
6945 "xmm0", "xmm1", "xmm2", "xmm3",
6946 "xmm4", "xmm5", "xmm6", "xmm7",
6947 "xmm8", "xmm9", "xmm10", "xmm11",
6948 "xmm12", "xmm13", "xmm14", "xmm15",
6949 "st0", "st1", "st2", "st3",
6950 "st4", "st5", "st6", "st7",
6951 "mm0", "mm1", "mm2", "mm3",
6952 "mm4", "mm5", "mm6", "mm7"
6954 const char *const *regnames
;
6956 if (flag_code
== CODE_64BIT
)
6958 regnames
= regnames_64
;
6959 regnames_count
= ARRAY_SIZE (regnames_64
);
6963 regnames
= regnames_32
;
6964 regnames_count
= ARRAY_SIZE (regnames_32
);
6967 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6968 if (regnames
[regnum
] != NULL
6969 && strcmp (regname
, regnames
[regnum
]) == 0)
6976 tc_x86_frame_initial_instructions (void)
6978 static unsigned int sp_regno
;
6981 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6984 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6985 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6989 i386_elf_section_type (const char *str
, size_t len
)
6991 if (flag_code
== CODE_64BIT
6992 && len
== sizeof ("unwind") - 1
6993 && strncmp (str
, "unwind", 6) == 0)
6994 return SHT_X86_64_UNWIND
;
7001 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7005 expr
.X_op
= O_secrel
;
7006 expr
.X_add_symbol
= symbol
;
7007 expr
.X_add_number
= 0;
7008 emit_expr (&expr
, size
);
7012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7013 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7016 x86_64_section_letter (int letter
, char **ptr_msg
)
7018 if (flag_code
== CODE_64BIT
)
7021 return SHF_X86_64_LARGE
;
7023 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7026 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7031 x86_64_section_word (char *str
, size_t len
)
7033 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7034 return SHF_X86_64_LARGE
;
7040 handle_large_common (int small ATTRIBUTE_UNUSED
)
7042 if (flag_code
!= CODE_64BIT
)
7044 s_comm_internal (0, elf_common_parse
);
7045 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7049 static segT lbss_section
;
7050 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7051 asection
*saved_bss_section
= bss_section
;
7053 if (lbss_section
== NULL
)
7055 flagword applicable
;
7057 subsegT subseg
= now_subseg
;
7059 /* The .lbss section is for local .largecomm symbols. */
7060 lbss_section
= subseg_new (".lbss", 0);
7061 applicable
= bfd_applicable_section_flags (stdoutput
);
7062 bfd_set_section_flags (stdoutput
, lbss_section
,
7063 applicable
& SEC_ALLOC
);
7064 seg_info (lbss_section
)->bss
= 1;
7066 subseg_set (seg
, subseg
);
7069 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7070 bss_section
= lbss_section
;
7072 s_comm_internal (0, elf_common_parse
);
7074 elf_com_section_ptr
= saved_com_section_ptr
;
7075 bss_section
= saved_bss_section
;
7078 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */