1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_GABI_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528 /* 1 if generating code for a shared library. */
529 static int shared
= 0;
532 /* 1 for intel syntax,
534 static int intel_syntax
= 0;
536 /* 1 for intel mnemonic,
537 0 if att mnemonic. */
538 static int intel_mnemonic
= !SYSV386_COMPAT
;
540 /* 1 if support old (<= 2.8.1) versions of gcc. */
541 static int old_gcc
= OLDGCC_COMPAT
;
543 /* 1 if pseudo registers are permitted. */
544 static int allow_pseudo_reg
= 0;
546 /* 1 if register prefix % not required. */
547 static int allow_naked_reg
= 0;
549 /* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
552 static int add_bnd_prefix
= 0;
554 /* 1 if pseudo index register, eiz/riz, is allowed . */
555 static int allow_index_reg
= 0;
557 /* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559 static int omit_lock_prefix
= 0;
561 static enum check_kind
567 sse_check
, operand_check
= check_warning
;
569 /* Register prefix used for error message. */
570 static const char *register_prefix
= "%";
572 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575 static char stackop_size
= '\0';
577 /* Non-zero to optimize code alignment. */
578 int optimize_align_code
= 1;
580 /* Non-zero to quieten some warnings. */
581 static int quiet_warnings
= 0;
584 static const char *cpu_arch_name
= NULL
;
585 static char *cpu_sub_arch_name
= NULL
;
587 /* CPU feature flags. */
588 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
590 /* If we have selected a cpu we are generating instructions for. */
591 static int cpu_arch_tune_set
= 0;
593 /* Cpu we are generating instructions for. */
594 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of cpu we are generating instructions for. */
597 static i386_cpu_flags cpu_arch_tune_flags
;
599 /* CPU instruction set architecture used. */
600 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
602 /* CPU feature flags of instruction set architecture used. */
603 i386_cpu_flags cpu_arch_isa_flags
;
605 /* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607 static unsigned int no_cond_jump_promotion
= 0;
609 /* Encode SSE instructions with VEX prefix. */
610 static unsigned int sse2avx
;
612 /* Encode scalar AVX instructions with specific vector length. */
619 /* Encode scalar EVEX LIG instructions with specific vector length. */
627 /* Encode EVEX WIG instructions with specific evex.w. */
634 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
635 static enum rc_type evexrcig
= rne
;
637 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
638 static symbolS
*GOT_symbol
;
640 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
641 unsigned int x86_dwarf2_return_column
;
643 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644 int x86_cie_data_alignment
;
646 /* Interface to relax_segment.
647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
652 #define UNCOND_JUMP 0
654 #define COND_JUMP86 2
659 #define SMALL16 (SMALL | CODE16)
661 #define BIG16 (BIG | CODE16)
665 #define INLINE __inline__
671 #define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673 #define TYPE_FROM_RELAX_STATE(s) \
675 #define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
678 /* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
686 const relax_typeS md_relax_table
[] =
689 1) most positive reach of this state,
690 2) most negative reach of this state,
691 3) how many bytes this mode will have in the variable part of the frag
692 4) which index into the table to try if we can't fit into this one. */
694 /* UNCOND_JUMP states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
710 /* word conditionals add 3 bytes to frag:
711 1 extra opcode byte, 2 displacement bytes. */
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
725 static const arch_entry cpu_arch
[] =
727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
730 CPU_GENERIC32_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
732 CPU_GENERIC64_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
734 CPU_NONE_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
736 CPU_I186_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
738 CPU_I286_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
740 CPU_I386_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
742 CPU_I486_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
744 CPU_I586_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
746 CPU_I686_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
748 CPU_I586_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
750 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
752 CPU_P2_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
754 CPU_P3_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
756 CPU_P4_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
760 CPU_NOCONA_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
762 CPU_CORE_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
764 CPU_CORE_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
766 CPU_CORE2_FLAGS
, 1, 0 },
767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
768 CPU_CORE2_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
770 CPU_COREI7_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
772 CPU_L1OM_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
774 CPU_K1OM_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
776 CPU_IAMCU_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
778 CPU_K6_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
780 CPU_K6_2_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
782 CPU_ATHLON_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
784 CPU_K8_FLAGS
, 1, 0 },
785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
786 CPU_K8_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
788 CPU_K8_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
790 CPU_AMDFAM10_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
792 CPU_BDVER1_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
794 CPU_BDVER2_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
796 CPU_BDVER3_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
798 CPU_BDVER4_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
800 CPU_ZNVER1_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
802 CPU_BTVER1_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
804 CPU_BTVER2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
806 CPU_8087_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
808 CPU_287_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
810 CPU_387_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
812 CPU_ANY87_FLAGS
, 0, 1 },
813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
814 CPU_MMX_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
816 CPU_3DNOWA_FLAGS
, 0, 1 },
817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
818 CPU_SSE_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
820 CPU_SSE2_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
822 CPU_SSE3_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
824 CPU_SSSE3_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
826 CPU_SSE4_1_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
828 CPU_SSE4_2_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
830 CPU_SSE4_2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
832 CPU_ANY_SSE_FLAGS
, 0, 1 },
833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
834 CPU_AVX_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
836 CPU_AVX2_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512F_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512CD_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512ER_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512PF_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
846 CPU_AVX512DQ_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
848 CPU_AVX512BW_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
850 CPU_AVX512VL_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
852 CPU_ANY_AVX_FLAGS
, 0, 1 },
853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
854 CPU_VMX_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
856 CPU_VMFUNC_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
858 CPU_SMX_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVE_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
862 CPU_XSAVEOPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
864 CPU_XSAVEC_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
866 CPU_XSAVES_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
868 CPU_AES_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
870 CPU_PCLMUL_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
872 CPU_PCLMUL_FLAGS
, 1, 0 },
873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
874 CPU_FSGSBASE_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
876 CPU_RDRND_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
878 CPU_F16C_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
880 CPU_BMI2_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
882 CPU_FMA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
884 CPU_FMA4_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
886 CPU_XOP_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
888 CPU_LWP_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
890 CPU_MOVBE_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
892 CPU_CX16_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
894 CPU_EPT_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
896 CPU_LZCNT_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
898 CPU_HLE_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
900 CPU_RTM_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
902 CPU_INVPCID_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
904 CPU_CLFLUSH_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
906 CPU_NOP_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
908 CPU_SYSCALL_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
910 CPU_RDTSCP_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
912 CPU_3DNOW_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
914 CPU_3DNOWA_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
916 CPU_PADLOCK_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
918 CPU_SVME_FLAGS
, 1, 0 },
919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
920 CPU_SVME_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4A_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
924 CPU_ABM_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
926 CPU_BMI_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
928 CPU_TBM_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
930 CPU_ADX_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
932 CPU_RDSEED_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
934 CPU_PRFCHW_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
936 CPU_SMAP_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
938 CPU_MPX_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
940 CPU_SHA_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
942 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
944 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
946 CPU_SE1_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
948 CPU_CLWB_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
950 CPU_PCOMMIT_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
952 CPU_AVX512IFMA_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
954 CPU_AVX512VBMI_FLAGS
, 0, 0 },
955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
956 CPU_CLZERO_FLAGS
, 0, 0 },
957 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
958 CPU_MWAITX_FLAGS
, 0, 0 },
962 /* Like s_lcomm_internal in gas/read.c but the alignment string
963 is allowed to be optional. */
966 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
973 && *input_line_pointer
== ',')
975 align
= parse_align (needs_align
- 1);
977 if (align
== (addressT
) -1)
992 bss_alloc (symbolP
, size
, align
);
997 pe_lcomm (int needs_align
)
999 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1003 const pseudo_typeS md_pseudo_table
[] =
1005 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1006 {"align", s_align_bytes
, 0},
1008 {"align", s_align_ptwo
, 0},
1010 {"arch", set_cpu_arch
, 0},
1014 {"lcomm", pe_lcomm
, 1},
1016 {"ffloat", float_cons
, 'f'},
1017 {"dfloat", float_cons
, 'd'},
1018 {"tfloat", float_cons
, 'x'},
1020 {"slong", signed_cons
, 4},
1021 {"noopt", s_ignore
, 0},
1022 {"optim", s_ignore
, 0},
1023 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1024 {"code16", set_code_flag
, CODE_16BIT
},
1025 {"code32", set_code_flag
, CODE_32BIT
},
1026 {"code64", set_code_flag
, CODE_64BIT
},
1027 {"intel_syntax", set_intel_syntax
, 1},
1028 {"att_syntax", set_intel_syntax
, 0},
1029 {"intel_mnemonic", set_intel_mnemonic
, 1},
1030 {"att_mnemonic", set_intel_mnemonic
, 0},
1031 {"allow_index_reg", set_allow_index_reg
, 1},
1032 {"disallow_index_reg", set_allow_index_reg
, 0},
1033 {"sse_check", set_check
, 0},
1034 {"operand_check", set_check
, 1},
1035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 {"largecomm", handle_large_common
, 0},
1038 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1039 {"loc", dwarf2_directive_loc
, 0},
1040 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1043 {"secrel32", pe_directive_secrel
, 0},
1048 /* For interface with expression (). */
1049 extern char *input_line_pointer
;
1051 /* Hash table for instruction mnemonic lookup. */
1052 static struct hash_control
*op_hash
;
1054 /* Hash table for register lookup. */
1055 static struct hash_control
*reg_hash
;
1058 i386_align_code (fragS
*fragP
, int count
)
1060 /* Various efficient no-op patterns for aligning code labels.
1061 Note: Don't try to assemble the instructions in the comments.
1062 0L and 0w are not legal. */
1063 static const char f32_1
[] =
1065 static const char f32_2
[] =
1066 {0x66,0x90}; /* xchg %ax,%ax */
1067 static const char f32_3
[] =
1068 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1069 static const char f32_4
[] =
1070 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1071 static const char f32_5
[] =
1073 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1074 static const char f32_6
[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1076 static const char f32_7
[] =
1077 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1078 static const char f32_8
[] =
1080 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1081 static const char f32_9
[] =
1082 {0x89,0xf6, /* movl %esi,%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_10
[] =
1085 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_11
[] =
1088 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_12
[] =
1091 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1092 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1093 static const char f32_13
[] =
1094 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1095 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1096 static const char f32_14
[] =
1097 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1099 static const char f16_3
[] =
1100 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1101 static const char f16_4
[] =
1102 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1103 static const char f16_5
[] =
1105 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1106 static const char f16_6
[] =
1107 {0x89,0xf6, /* mov %si,%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char f16_7
[] =
1110 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1111 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1112 static const char f16_8
[] =
1113 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1114 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1115 static const char jump_31
[] =
1116 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1118 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1119 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1120 static const char *const f32_patt
[] = {
1121 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1122 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1124 static const char *const f16_patt
[] = {
1125 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1127 /* nopl (%[re]ax) */
1128 static const char alt_3
[] =
1130 /* nopl 0(%[re]ax) */
1131 static const char alt_4
[] =
1132 {0x0f,0x1f,0x40,0x00};
1133 /* nopl 0(%[re]ax,%[re]ax,1) */
1134 static const char alt_5
[] =
1135 {0x0f,0x1f,0x44,0x00,0x00};
1136 /* nopw 0(%[re]ax,%[re]ax,1) */
1137 static const char alt_6
[] =
1138 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1139 /* nopl 0L(%[re]ax) */
1140 static const char alt_7
[] =
1141 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1142 /* nopl 0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_8
[] =
1144 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 /* nopw 0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_9
[] =
1147 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_10
[] =
1150 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1151 static const char *const alt_patt
[] = {
1152 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1156 /* Only align for at least a positive non-zero boundary. */
1157 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1160 /* We need to decide which NOP sequence to use for 32bit and
1161 64bit. When -mtune= is used:
1163 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1164 PROCESSOR_GENERIC32, f32_patt will be used.
1165 2. For the rest, alt_patt will be used.
1167 When -mtune= isn't used, alt_patt will be used if
1168 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1171 When -march= or .arch is used, we can't use anything beyond
1172 cpu_arch_isa_flags. */
1174 if (flag_code
== CODE_16BIT
)
1178 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1180 /* Adjust jump offset. */
1181 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1184 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1185 f16_patt
[count
- 1], count
);
1189 const char *const *patt
= NULL
;
1191 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1193 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1194 switch (cpu_arch_tune
)
1196 case PROCESSOR_UNKNOWN
:
1197 /* We use cpu_arch_isa_flags to check if we SHOULD
1198 optimize with nops. */
1199 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1204 case PROCESSOR_PENTIUM4
:
1205 case PROCESSOR_NOCONA
:
1206 case PROCESSOR_CORE
:
1207 case PROCESSOR_CORE2
:
1208 case PROCESSOR_COREI7
:
1209 case PROCESSOR_L1OM
:
1210 case PROCESSOR_K1OM
:
1211 case PROCESSOR_GENERIC64
:
1213 case PROCESSOR_ATHLON
:
1215 case PROCESSOR_AMDFAM10
:
1217 case PROCESSOR_ZNVER
:
1221 case PROCESSOR_I386
:
1222 case PROCESSOR_I486
:
1223 case PROCESSOR_PENTIUM
:
1224 case PROCESSOR_PENTIUMPRO
:
1225 case PROCESSOR_IAMCU
:
1226 case PROCESSOR_GENERIC32
:
1233 switch (fragP
->tc_frag_data
.tune
)
1235 case PROCESSOR_UNKNOWN
:
1236 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1237 PROCESSOR_UNKNOWN. */
1241 case PROCESSOR_I386
:
1242 case PROCESSOR_I486
:
1243 case PROCESSOR_PENTIUM
:
1244 case PROCESSOR_IAMCU
:
1246 case PROCESSOR_ATHLON
:
1248 case PROCESSOR_AMDFAM10
:
1250 case PROCESSOR_ZNVER
:
1252 case PROCESSOR_GENERIC32
:
1253 /* We use cpu_arch_isa_flags to check if we CAN optimize
1255 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1260 case PROCESSOR_PENTIUMPRO
:
1261 case PROCESSOR_PENTIUM4
:
1262 case PROCESSOR_NOCONA
:
1263 case PROCESSOR_CORE
:
1264 case PROCESSOR_CORE2
:
1265 case PROCESSOR_COREI7
:
1266 case PROCESSOR_L1OM
:
1267 case PROCESSOR_K1OM
:
1268 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1273 case PROCESSOR_GENERIC64
:
1279 if (patt
== f32_patt
)
1281 /* If the padding is less than 15 bytes, we use the normal
1282 ones. Otherwise, we use a jump instruction and adjust
1286 /* For 64bit, the limit is 3 bytes. */
1287 if (flag_code
== CODE_64BIT
1288 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1293 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1294 patt
[count
- 1], count
);
1297 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1299 /* Adjust jump offset. */
1300 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1305 /* Maximum length of an instruction is 10 byte. If the
1306 padding is greater than 10 bytes and we don't use jump,
1307 we have to break it into smaller pieces. */
1308 int padding
= count
;
1309 while (padding
> 10)
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1317 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1318 patt
[padding
- 1], padding
);
1321 fragP
->fr_var
= count
;
1325 operand_type_all_zero (const union i386_operand_type
*x
)
1327 switch (ARRAY_SIZE(x
->array
))
1336 return !x
->array
[0];
1343 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1345 switch (ARRAY_SIZE(x
->array
))
1360 operand_type_equal (const union i386_operand_type
*x
,
1361 const union i386_operand_type
*y
)
1363 switch (ARRAY_SIZE(x
->array
))
1366 if (x
->array
[2] != y
->array
[2])
1369 if (x
->array
[1] != y
->array
[1])
1372 return x
->array
[0] == y
->array
[0];
1380 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1382 switch (ARRAY_SIZE(x
->array
))
1391 return !x
->array
[0];
1398 cpu_flags_equal (const union i386_cpu_flags
*x
,
1399 const union i386_cpu_flags
*y
)
1401 switch (ARRAY_SIZE(x
->array
))
1404 if (x
->array
[2] != y
->array
[2])
1407 if (x
->array
[1] != y
->array
[1])
1410 return x
->array
[0] == y
->array
[0];
1418 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1420 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1421 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1424 static INLINE i386_cpu_flags
1425 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1427 switch (ARRAY_SIZE (x
.array
))
1430 x
.array
[2] &= y
.array
[2];
1432 x
.array
[1] &= y
.array
[1];
1434 x
.array
[0] &= y
.array
[0];
1442 static INLINE i386_cpu_flags
1443 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1445 switch (ARRAY_SIZE (x
.array
))
1448 x
.array
[2] |= y
.array
[2];
1450 x
.array
[1] |= y
.array
[1];
1452 x
.array
[0] |= y
.array
[0];
1460 static INLINE i386_cpu_flags
1461 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1463 switch (ARRAY_SIZE (x
.array
))
1466 x
.array
[2] &= ~y
.array
[2];
1468 x
.array
[1] &= ~y
.array
[1];
1470 x
.array
[0] &= ~y
.array
[0];
1479 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1481 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1483 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1484 i386_cpu_flags compat_flags
;
1485 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1486 return cpu_flags_all_zero (&compat_flags
);
1492 #define CPU_FLAGS_ARCH_MATCH 0x1
1493 #define CPU_FLAGS_64BIT_MATCH 0x2
1494 #define CPU_FLAGS_AES_MATCH 0x4
1495 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1496 #define CPU_FLAGS_AVX_MATCH 0x10
1498 #define CPU_FLAGS_32BIT_MATCH \
1499 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1500 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1501 #define CPU_FLAGS_PERFECT_MATCH \
1502 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1504 /* Return CPU flags match bits. */
1507 cpu_flags_match (const insn_template
*t
)
1509 i386_cpu_flags x
= t
->cpu_flags
;
1510 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1512 x
.bitfield
.cpu64
= 0;
1513 x
.bitfield
.cpuno64
= 0;
1515 if (cpu_flags_all_zero (&x
))
1517 /* This instruction is available on all archs. */
1518 match
|= CPU_FLAGS_32BIT_MATCH
;
1522 /* This instruction is available only on some archs. */
1523 i386_cpu_flags cpu
= cpu_arch_flags
;
1525 cpu
.bitfield
.cpu64
= 0;
1526 cpu
.bitfield
.cpuno64
= 0;
1527 cpu
= cpu_flags_and (x
, cpu
);
1528 if (!cpu_flags_all_zero (&cpu
))
1530 if (x
.bitfield
.cpuavx
)
1532 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1533 if (cpu
.bitfield
.cpuavx
)
1535 /* Check SSE2AVX. */
1536 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1538 match
|= (CPU_FLAGS_ARCH_MATCH
1539 | CPU_FLAGS_AVX_MATCH
);
1541 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1542 match
|= CPU_FLAGS_AES_MATCH
;
1544 if (!x
.bitfield
.cpupclmul
1545 || cpu
.bitfield
.cpupclmul
)
1546 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1550 match
|= CPU_FLAGS_ARCH_MATCH
;
1553 match
|= CPU_FLAGS_32BIT_MATCH
;
1559 static INLINE i386_operand_type
1560 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1562 switch (ARRAY_SIZE (x
.array
))
1565 x
.array
[2] &= y
.array
[2];
1567 x
.array
[1] &= y
.array
[1];
1569 x
.array
[0] &= y
.array
[0];
1577 static INLINE i386_operand_type
1578 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1580 switch (ARRAY_SIZE (x
.array
))
1583 x
.array
[2] |= y
.array
[2];
1585 x
.array
[1] |= y
.array
[1];
1587 x
.array
[0] |= y
.array
[0];
1595 static INLINE i386_operand_type
1596 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1598 switch (ARRAY_SIZE (x
.array
))
1601 x
.array
[2] ^= y
.array
[2];
1603 x
.array
[1] ^= y
.array
[1];
1605 x
.array
[0] ^= y
.array
[0];
1613 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1614 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1615 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1616 static const i386_operand_type inoutportreg
1617 = OPERAND_TYPE_INOUTPORTREG
;
1618 static const i386_operand_type reg16_inoutportreg
1619 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1620 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1621 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1622 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1623 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1624 static const i386_operand_type anydisp
1625 = OPERAND_TYPE_ANYDISP
;
1626 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1627 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1628 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1629 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1630 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1631 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1632 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1633 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1634 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1635 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1636 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1637 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1638 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1639 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1650 operand_type_check (i386_operand_type t
, enum operand_type c
)
1655 return (t
.bitfield
.reg8
1658 || t
.bitfield
.reg64
);
1661 return (t
.bitfield
.imm8
1665 || t
.bitfield
.imm32s
1666 || t
.bitfield
.imm64
);
1669 return (t
.bitfield
.disp8
1670 || t
.bitfield
.disp16
1671 || t
.bitfield
.disp32
1672 || t
.bitfield
.disp32s
1673 || t
.bitfield
.disp64
);
1676 return (t
.bitfield
.disp8
1677 || t
.bitfield
.disp16
1678 || t
.bitfield
.disp32
1679 || t
.bitfield
.disp32s
1680 || t
.bitfield
.disp64
1681 || t
.bitfield
.baseindex
);
1690 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1691 operand J for instruction template T. */
1694 match_reg_size (const insn_template
*t
, unsigned int j
)
1696 return !((i
.types
[j
].bitfield
.byte
1697 && !t
->operand_types
[j
].bitfield
.byte
)
1698 || (i
.types
[j
].bitfield
.word
1699 && !t
->operand_types
[j
].bitfield
.word
)
1700 || (i
.types
[j
].bitfield
.dword
1701 && !t
->operand_types
[j
].bitfield
.dword
)
1702 || (i
.types
[j
].bitfield
.qword
1703 && !t
->operand_types
[j
].bitfield
.qword
));
1706 /* Return 1 if there is no conflict in any size on operand J for
1707 instruction template T. */
1710 match_mem_size (const insn_template
*t
, unsigned int j
)
1712 return (match_reg_size (t
, j
)
1713 && !((i
.types
[j
].bitfield
.unspecified
1715 && !t
->operand_types
[j
].bitfield
.unspecified
)
1716 || (i
.types
[j
].bitfield
.fword
1717 && !t
->operand_types
[j
].bitfield
.fword
)
1718 || (i
.types
[j
].bitfield
.tbyte
1719 && !t
->operand_types
[j
].bitfield
.tbyte
)
1720 || (i
.types
[j
].bitfield
.xmmword
1721 && !t
->operand_types
[j
].bitfield
.xmmword
)
1722 || (i
.types
[j
].bitfield
.ymmword
1723 && !t
->operand_types
[j
].bitfield
.ymmword
)
1724 || (i
.types
[j
].bitfield
.zmmword
1725 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1728 /* Return 1 if there is no size conflict on any operands for
1729 instruction template T. */
1732 operand_size_match (const insn_template
*t
)
1737 /* Don't check jump instructions. */
1738 if (t
->opcode_modifier
.jump
1739 || t
->opcode_modifier
.jumpbyte
1740 || t
->opcode_modifier
.jumpdword
1741 || t
->opcode_modifier
.jumpintersegment
)
1744 /* Check memory and accumulator operand size. */
1745 for (j
= 0; j
< i
.operands
; j
++)
1747 if (t
->operand_types
[j
].bitfield
.anysize
)
1750 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1756 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1765 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1768 i
.error
= operand_size_mismatch
;
1772 /* Check reverse. */
1773 gas_assert (i
.operands
== 2);
1776 for (j
= 0; j
< 2; j
++)
1778 if (t
->operand_types
[j
].bitfield
.acc
1779 && !match_reg_size (t
, j
? 0 : 1))
1782 if (i
.types
[j
].bitfield
.mem
1783 && !match_mem_size (t
, j
? 0 : 1))
1791 operand_type_match (i386_operand_type overlap
,
1792 i386_operand_type given
)
1794 i386_operand_type temp
= overlap
;
1796 temp
.bitfield
.jumpabsolute
= 0;
1797 temp
.bitfield
.unspecified
= 0;
1798 temp
.bitfield
.byte
= 0;
1799 temp
.bitfield
.word
= 0;
1800 temp
.bitfield
.dword
= 0;
1801 temp
.bitfield
.fword
= 0;
1802 temp
.bitfield
.qword
= 0;
1803 temp
.bitfield
.tbyte
= 0;
1804 temp
.bitfield
.xmmword
= 0;
1805 temp
.bitfield
.ymmword
= 0;
1806 temp
.bitfield
.zmmword
= 0;
1807 if (operand_type_all_zero (&temp
))
1810 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1811 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1815 i
.error
= operand_type_mismatch
;
1819 /* If given types g0 and g1 are registers they must be of the same type
1820 unless the expected operand type register overlap is null.
1821 Note that Acc in a template matches every size of reg. */
1824 operand_type_register_match (i386_operand_type m0
,
1825 i386_operand_type g0
,
1826 i386_operand_type t0
,
1827 i386_operand_type m1
,
1828 i386_operand_type g1
,
1829 i386_operand_type t1
)
1831 if (!operand_type_check (g0
, reg
))
1834 if (!operand_type_check (g1
, reg
))
1837 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1838 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1839 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1840 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1843 if (m0
.bitfield
.acc
)
1845 t0
.bitfield
.reg8
= 1;
1846 t0
.bitfield
.reg16
= 1;
1847 t0
.bitfield
.reg32
= 1;
1848 t0
.bitfield
.reg64
= 1;
1851 if (m1
.bitfield
.acc
)
1853 t1
.bitfield
.reg8
= 1;
1854 t1
.bitfield
.reg16
= 1;
1855 t1
.bitfield
.reg32
= 1;
1856 t1
.bitfield
.reg64
= 1;
1859 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1860 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1861 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1862 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1865 i
.error
= register_type_mismatch
;
1870 static INLINE
unsigned int
1871 register_number (const reg_entry
*r
)
1873 unsigned int nr
= r
->reg_num
;
1875 if (r
->reg_flags
& RegRex
)
1881 static INLINE
unsigned int
1882 mode_from_disp_size (i386_operand_type t
)
1884 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1886 else if (t
.bitfield
.disp16
1887 || t
.bitfield
.disp32
1888 || t
.bitfield
.disp32s
)
1895 fits_in_signed_byte (addressT num
)
1897 return num
+ 0x80 <= 0xff;
1901 fits_in_unsigned_byte (addressT num
)
1907 fits_in_unsigned_word (addressT num
)
1909 return num
<= 0xffff;
1913 fits_in_signed_word (addressT num
)
1915 return num
+ 0x8000 <= 0xffff;
1919 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1924 return num
+ 0x80000000 <= 0xffffffff;
1926 } /* fits_in_signed_long() */
1929 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1934 return num
<= 0xffffffff;
1936 } /* fits_in_unsigned_long() */
1939 fits_in_vec_disp8 (offsetT num
)
1941 int shift
= i
.memshift
;
1947 mask
= (1 << shift
) - 1;
1949 /* Return 0 if NUM isn't properly aligned. */
1953 /* Check if NUM will fit in 8bit after shift. */
1954 return fits_in_signed_byte (num
>> shift
);
1958 fits_in_imm4 (offsetT num
)
1960 return (num
& 0xf) == num
;
1963 static i386_operand_type
1964 smallest_imm_type (offsetT num
)
1966 i386_operand_type t
;
1968 operand_type_set (&t
, 0);
1969 t
.bitfield
.imm64
= 1;
1971 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1973 /* This code is disabled on the 486 because all the Imm1 forms
1974 in the opcode table are slower on the i486. They're the
1975 versions with the implicitly specified single-position
1976 displacement, which has another syntax if you really want to
1978 t
.bitfield
.imm1
= 1;
1979 t
.bitfield
.imm8
= 1;
1980 t
.bitfield
.imm8s
= 1;
1981 t
.bitfield
.imm16
= 1;
1982 t
.bitfield
.imm32
= 1;
1983 t
.bitfield
.imm32s
= 1;
1985 else if (fits_in_signed_byte (num
))
1987 t
.bitfield
.imm8
= 1;
1988 t
.bitfield
.imm8s
= 1;
1989 t
.bitfield
.imm16
= 1;
1990 t
.bitfield
.imm32
= 1;
1991 t
.bitfield
.imm32s
= 1;
1993 else if (fits_in_unsigned_byte (num
))
1995 t
.bitfield
.imm8
= 1;
1996 t
.bitfield
.imm16
= 1;
1997 t
.bitfield
.imm32
= 1;
1998 t
.bitfield
.imm32s
= 1;
2000 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2002 t
.bitfield
.imm16
= 1;
2003 t
.bitfield
.imm32
= 1;
2004 t
.bitfield
.imm32s
= 1;
2006 else if (fits_in_signed_long (num
))
2008 t
.bitfield
.imm32
= 1;
2009 t
.bitfield
.imm32s
= 1;
2011 else if (fits_in_unsigned_long (num
))
2012 t
.bitfield
.imm32
= 1;
2018 offset_in_range (offsetT val
, int size
)
2024 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2025 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2026 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2028 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2034 /* If BFD64, sign extend val for 32bit address mode. */
2035 if (flag_code
!= CODE_64BIT
2036 || i
.prefix
[ADDR_PREFIX
])
2037 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2038 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2041 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2043 char buf1
[40], buf2
[40];
2045 sprint_value (buf1
, val
);
2046 sprint_value (buf2
, val
& mask
);
2047 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2061 a. PREFIX_EXIST if attempting to add a prefix where one from the
2062 same class already exists.
2063 b. PREFIX_LOCK if lock prefix is added.
2064 c. PREFIX_REP if rep/repne prefix is added.
2065 d. PREFIX_OTHER if other prefix is added.
2068 static enum PREFIX_GROUP
2069 add_prefix (unsigned int prefix
)
2071 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2074 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2075 && flag_code
== CODE_64BIT
)
2077 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2078 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2079 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2090 case CS_PREFIX_OPCODE
:
2091 case DS_PREFIX_OPCODE
:
2092 case ES_PREFIX_OPCODE
:
2093 case FS_PREFIX_OPCODE
:
2094 case GS_PREFIX_OPCODE
:
2095 case SS_PREFIX_OPCODE
:
2099 case REPNE_PREFIX_OPCODE
:
2100 case REPE_PREFIX_OPCODE
:
2105 case LOCK_PREFIX_OPCODE
:
2114 case ADDR_PREFIX_OPCODE
:
2118 case DATA_PREFIX_OPCODE
:
2122 if (i
.prefix
[q
] != 0)
2130 i
.prefix
[q
] |= prefix
;
2133 as_bad (_("same type of prefix used twice"));
2139 update_code_flag (int value
, int check
)
2141 PRINTF_LIKE ((*as_error
));
2143 flag_code
= (enum flag_code
) value
;
2144 if (flag_code
== CODE_64BIT
)
2146 cpu_arch_flags
.bitfield
.cpu64
= 1;
2147 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2151 cpu_arch_flags
.bitfield
.cpu64
= 0;
2152 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2154 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2157 as_error
= as_fatal
;
2160 (*as_error
) (_("64bit mode not supported on `%s'."),
2161 cpu_arch_name
? cpu_arch_name
: default_arch
);
2163 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2166 as_error
= as_fatal
;
2169 (*as_error
) (_("32bit mode not supported on `%s'."),
2170 cpu_arch_name
? cpu_arch_name
: default_arch
);
2172 stackop_size
= '\0';
2176 set_code_flag (int value
)
2178 update_code_flag (value
, 0);
2182 set_16bit_gcc_code_flag (int new_code_flag
)
2184 flag_code
= (enum flag_code
) new_code_flag
;
2185 if (flag_code
!= CODE_16BIT
)
2187 cpu_arch_flags
.bitfield
.cpu64
= 0;
2188 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2189 stackop_size
= LONG_MNEM_SUFFIX
;
2193 set_intel_syntax (int syntax_flag
)
2195 /* Find out if register prefixing is specified. */
2196 int ask_naked_reg
= 0;
2199 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2202 int e
= get_symbol_name (&string
);
2204 if (strcmp (string
, "prefix") == 0)
2206 else if (strcmp (string
, "noprefix") == 0)
2209 as_bad (_("bad argument to syntax directive."));
2210 (void) restore_line_pointer (e
);
2212 demand_empty_rest_of_line ();
2214 intel_syntax
= syntax_flag
;
2216 if (ask_naked_reg
== 0)
2217 allow_naked_reg
= (intel_syntax
2218 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2220 allow_naked_reg
= (ask_naked_reg
< 0);
2222 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2224 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2225 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2226 register_prefix
= allow_naked_reg
? "" : "%";
2230 set_intel_mnemonic (int mnemonic_flag
)
2232 intel_mnemonic
= mnemonic_flag
;
2236 set_allow_index_reg (int flag
)
2238 allow_index_reg
= flag
;
2242 set_check (int what
)
2244 enum check_kind
*kind
;
2249 kind
= &operand_check
;
2260 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2263 int e
= get_symbol_name (&string
);
2265 if (strcmp (string
, "none") == 0)
2267 else if (strcmp (string
, "warning") == 0)
2268 *kind
= check_warning
;
2269 else if (strcmp (string
, "error") == 0)
2270 *kind
= check_error
;
2272 as_bad (_("bad argument to %s_check directive."), str
);
2273 (void) restore_line_pointer (e
);
2276 as_bad (_("missing argument for %s_check directive"), str
);
2278 demand_empty_rest_of_line ();
2282 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2283 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2286 static const char *arch
;
2288 /* Intel LIOM is only supported on ELF. */
2294 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2295 use default_arch. */
2296 arch
= cpu_arch_name
;
2298 arch
= default_arch
;
2301 /* If we are targeting Intel MCU, we must enable it. */
2302 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2303 || new_flag
.bitfield
.cpuiamcu
)
2306 /* If we are targeting Intel L1OM, we must enable it. */
2307 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2308 || new_flag
.bitfield
.cpul1om
)
2311 /* If we are targeting Intel K1OM, we must enable it. */
2312 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2313 || new_flag
.bitfield
.cpuk1om
)
2316 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2321 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2325 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2328 int e
= get_symbol_name (&string
);
2330 i386_cpu_flags flags
;
2332 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2334 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2336 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2340 cpu_arch_name
= cpu_arch
[j
].name
;
2341 cpu_sub_arch_name
= NULL
;
2342 cpu_arch_flags
= cpu_arch
[j
].flags
;
2343 if (flag_code
== CODE_64BIT
)
2345 cpu_arch_flags
.bitfield
.cpu64
= 1;
2346 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2350 cpu_arch_flags
.bitfield
.cpu64
= 0;
2351 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2353 cpu_arch_isa
= cpu_arch
[j
].type
;
2354 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2355 if (!cpu_arch_tune_set
)
2357 cpu_arch_tune
= cpu_arch_isa
;
2358 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2363 if (!cpu_arch
[j
].negated
)
2364 flags
= cpu_flags_or (cpu_arch_flags
,
2367 flags
= cpu_flags_and_not (cpu_arch_flags
,
2370 if (!valid_iamcu_cpu_flags (&flags
))
2371 as_fatal (_("`%s' isn't valid for Intel MCU"),
2373 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2375 if (cpu_sub_arch_name
)
2377 char *name
= cpu_sub_arch_name
;
2378 cpu_sub_arch_name
= concat (name
,
2380 (const char *) NULL
);
2384 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2385 cpu_arch_flags
= flags
;
2386 cpu_arch_isa_flags
= flags
;
2388 (void) restore_line_pointer (e
);
2389 demand_empty_rest_of_line ();
2393 if (j
>= ARRAY_SIZE (cpu_arch
))
2394 as_bad (_("no such architecture: `%s'"), string
);
2396 *input_line_pointer
= e
;
2399 as_bad (_("missing cpu architecture"));
2401 no_cond_jump_promotion
= 0;
2402 if (*input_line_pointer
== ','
2403 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2408 ++input_line_pointer
;
2409 e
= get_symbol_name (&string
);
2411 if (strcmp (string
, "nojumps") == 0)
2412 no_cond_jump_promotion
= 1;
2413 else if (strcmp (string
, "jumps") == 0)
2416 as_bad (_("no such architecture modifier: `%s'"), string
);
2418 (void) restore_line_pointer (e
);
2421 demand_empty_rest_of_line ();
2424 enum bfd_architecture
2427 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2429 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2430 || flag_code
!= CODE_64BIT
)
2431 as_fatal (_("Intel L1OM is 64bit ELF only"));
2432 return bfd_arch_l1om
;
2434 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2436 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2437 || flag_code
!= CODE_64BIT
)
2438 as_fatal (_("Intel K1OM is 64bit ELF only"));
2439 return bfd_arch_k1om
;
2441 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2443 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2444 || flag_code
== CODE_64BIT
)
2445 as_fatal (_("Intel MCU is 32bit ELF only"));
2446 return bfd_arch_iamcu
;
2449 return bfd_arch_i386
;
2455 if (!strncmp (default_arch
, "x86_64", 6))
2457 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2459 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2460 || default_arch
[6] != '\0')
2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_mach_l1om
;
2464 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2466 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2467 || default_arch
[6] != '\0')
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_mach_k1om
;
2471 else if (default_arch
[6] == '\0')
2472 return bfd_mach_x86_64
;
2474 return bfd_mach_x64_32
;
2476 else if (!strcmp (default_arch
, "i386")
2477 || !strcmp (default_arch
, "iamcu"))
2479 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2481 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2482 as_fatal (_("Intel MCU is 32bit ELF only"));
2483 return bfd_mach_i386_iamcu
;
2486 return bfd_mach_i386_i386
;
2489 as_fatal (_("unknown architecture"));
2495 const char *hash_err
;
2497 /* Initialize op_hash hash table. */
2498 op_hash
= hash_new ();
2501 const insn_template
*optab
;
2502 templates
*core_optab
;
2504 /* Setup for loop. */
2506 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2507 core_optab
->start
= optab
;
2512 if (optab
->name
== NULL
2513 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2515 /* different name --> ship out current template list;
2516 add to hash table; & begin anew. */
2517 core_optab
->end
= optab
;
2518 hash_err
= hash_insert (op_hash
,
2520 (void *) core_optab
);
2523 as_fatal (_("can't hash %s: %s"),
2527 if (optab
->name
== NULL
)
2529 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2530 core_optab
->start
= optab
;
2535 /* Initialize reg_hash hash table. */
2536 reg_hash
= hash_new ();
2538 const reg_entry
*regtab
;
2539 unsigned int regtab_size
= i386_regtab_size
;
2541 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2543 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2545 as_fatal (_("can't hash %s: %s"),
2551 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2556 for (c
= 0; c
< 256; c
++)
2561 mnemonic_chars
[c
] = c
;
2562 register_chars
[c
] = c
;
2563 operand_chars
[c
] = c
;
2565 else if (ISLOWER (c
))
2567 mnemonic_chars
[c
] = c
;
2568 register_chars
[c
] = c
;
2569 operand_chars
[c
] = c
;
2571 else if (ISUPPER (c
))
2573 mnemonic_chars
[c
] = TOLOWER (c
);
2574 register_chars
[c
] = mnemonic_chars
[c
];
2575 operand_chars
[c
] = c
;
2577 else if (c
== '{' || c
== '}')
2578 operand_chars
[c
] = c
;
2580 if (ISALPHA (c
) || ISDIGIT (c
))
2581 identifier_chars
[c
] = c
;
2584 identifier_chars
[c
] = c
;
2585 operand_chars
[c
] = c
;
2590 identifier_chars
['@'] = '@';
2593 identifier_chars
['?'] = '?';
2594 operand_chars
['?'] = '?';
2596 digit_chars
['-'] = '-';
2597 mnemonic_chars
['_'] = '_';
2598 mnemonic_chars
['-'] = '-';
2599 mnemonic_chars
['.'] = '.';
2600 identifier_chars
['_'] = '_';
2601 identifier_chars
['.'] = '.';
2603 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2604 operand_chars
[(unsigned char) *p
] = *p
;
2607 if (flag_code
== CODE_64BIT
)
2609 #if defined (OBJ_COFF) && defined (TE_PE)
2610 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2613 x86_dwarf2_return_column
= 16;
2615 x86_cie_data_alignment
= -8;
2619 x86_dwarf2_return_column
= 8;
2620 x86_cie_data_alignment
= -4;
2625 i386_print_statistics (FILE *file
)
2627 hash_print_statistics (file
, "i386 opcode", op_hash
);
2628 hash_print_statistics (file
, "i386 register", reg_hash
);
2633 /* Debugging routines for md_assemble. */
2634 static void pte (insn_template
*);
2635 static void pt (i386_operand_type
);
2636 static void pe (expressionS
*);
2637 static void ps (symbolS
*);
2640 pi (char *line
, i386_insn
*x
)
2644 fprintf (stdout
, "%s: template ", line
);
2646 fprintf (stdout
, " address: base %s index %s scale %x\n",
2647 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2648 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2649 x
->log2_scale_factor
);
2650 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2651 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2652 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2653 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2654 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2655 (x
->rex
& REX_W
) != 0,
2656 (x
->rex
& REX_R
) != 0,
2657 (x
->rex
& REX_X
) != 0,
2658 (x
->rex
& REX_B
) != 0);
2659 for (j
= 0; j
< x
->operands
; j
++)
2661 fprintf (stdout
, " #%d: ", j
+ 1);
2663 fprintf (stdout
, "\n");
2664 if (x
->types
[j
].bitfield
.reg8
2665 || x
->types
[j
].bitfield
.reg16
2666 || x
->types
[j
].bitfield
.reg32
2667 || x
->types
[j
].bitfield
.reg64
2668 || x
->types
[j
].bitfield
.regmmx
2669 || x
->types
[j
].bitfield
.regxmm
2670 || x
->types
[j
].bitfield
.regymm
2671 || x
->types
[j
].bitfield
.regzmm
2672 || x
->types
[j
].bitfield
.sreg2
2673 || x
->types
[j
].bitfield
.sreg3
2674 || x
->types
[j
].bitfield
.control
2675 || x
->types
[j
].bitfield
.debug
2676 || x
->types
[j
].bitfield
.test
)
2677 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2678 if (operand_type_check (x
->types
[j
], imm
))
2680 if (operand_type_check (x
->types
[j
], disp
))
2681 pe (x
->op
[j
].disps
);
2686 pte (insn_template
*t
)
2689 fprintf (stdout
, " %d operands ", t
->operands
);
2690 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2691 if (t
->extension_opcode
!= None
)
2692 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2693 if (t
->opcode_modifier
.d
)
2694 fprintf (stdout
, "D");
2695 if (t
->opcode_modifier
.w
)
2696 fprintf (stdout
, "W");
2697 fprintf (stdout
, "\n");
2698 for (j
= 0; j
< t
->operands
; j
++)
2700 fprintf (stdout
, " #%d type ", j
+ 1);
2701 pt (t
->operand_types
[j
]);
2702 fprintf (stdout
, "\n");
2709 fprintf (stdout
, " operation %d\n", e
->X_op
);
2710 fprintf (stdout
, " add_number %ld (%lx)\n",
2711 (long) e
->X_add_number
, (long) e
->X_add_number
);
2712 if (e
->X_add_symbol
)
2714 fprintf (stdout
, " add_symbol ");
2715 ps (e
->X_add_symbol
);
2716 fprintf (stdout
, "\n");
2720 fprintf (stdout
, " op_symbol ");
2721 ps (e
->X_op_symbol
);
2722 fprintf (stdout
, "\n");
2729 fprintf (stdout
, "%s type %s%s",
2731 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2732 segment_name (S_GET_SEGMENT (s
)));
2735 static struct type_name
2737 i386_operand_type mask
;
2740 const type_names
[] =
2742 { OPERAND_TYPE_REG8
, "r8" },
2743 { OPERAND_TYPE_REG16
, "r16" },
2744 { OPERAND_TYPE_REG32
, "r32" },
2745 { OPERAND_TYPE_REG64
, "r64" },
2746 { OPERAND_TYPE_IMM8
, "i8" },
2747 { OPERAND_TYPE_IMM8
, "i8s" },
2748 { OPERAND_TYPE_IMM16
, "i16" },
2749 { OPERAND_TYPE_IMM32
, "i32" },
2750 { OPERAND_TYPE_IMM32S
, "i32s" },
2751 { OPERAND_TYPE_IMM64
, "i64" },
2752 { OPERAND_TYPE_IMM1
, "i1" },
2753 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2754 { OPERAND_TYPE_DISP8
, "d8" },
2755 { OPERAND_TYPE_DISP16
, "d16" },
2756 { OPERAND_TYPE_DISP32
, "d32" },
2757 { OPERAND_TYPE_DISP32S
, "d32s" },
2758 { OPERAND_TYPE_DISP64
, "d64" },
2759 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2760 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2761 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2762 { OPERAND_TYPE_CONTROL
, "control reg" },
2763 { OPERAND_TYPE_TEST
, "test reg" },
2764 { OPERAND_TYPE_DEBUG
, "debug reg" },
2765 { OPERAND_TYPE_FLOATREG
, "FReg" },
2766 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2767 { OPERAND_TYPE_SREG2
, "SReg2" },
2768 { OPERAND_TYPE_SREG3
, "SReg3" },
2769 { OPERAND_TYPE_ACC
, "Acc" },
2770 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2771 { OPERAND_TYPE_REGMMX
, "rMMX" },
2772 { OPERAND_TYPE_REGXMM
, "rXMM" },
2773 { OPERAND_TYPE_REGYMM
, "rYMM" },
2774 { OPERAND_TYPE_REGZMM
, "rZMM" },
2775 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2776 { OPERAND_TYPE_ESSEG
, "es" },
2780 pt (i386_operand_type t
)
2783 i386_operand_type a
;
2785 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2787 a
= operand_type_and (t
, type_names
[j
].mask
);
2788 if (!operand_type_all_zero (&a
))
2789 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2794 #endif /* DEBUG386 */
2796 static bfd_reloc_code_real_type
2797 reloc (unsigned int size
,
2800 bfd_reloc_code_real_type other
)
2802 if (other
!= NO_RELOC
)
2804 reloc_howto_type
*rel
;
2809 case BFD_RELOC_X86_64_GOT32
:
2810 return BFD_RELOC_X86_64_GOT64
;
2812 case BFD_RELOC_X86_64_GOTPLT64
:
2813 return BFD_RELOC_X86_64_GOTPLT64
;
2815 case BFD_RELOC_X86_64_PLTOFF64
:
2816 return BFD_RELOC_X86_64_PLTOFF64
;
2818 case BFD_RELOC_X86_64_GOTPC32
:
2819 other
= BFD_RELOC_X86_64_GOTPC64
;
2821 case BFD_RELOC_X86_64_GOTPCREL
:
2822 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2824 case BFD_RELOC_X86_64_TPOFF32
:
2825 other
= BFD_RELOC_X86_64_TPOFF64
;
2827 case BFD_RELOC_X86_64_DTPOFF32
:
2828 other
= BFD_RELOC_X86_64_DTPOFF64
;
2834 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2835 if (other
== BFD_RELOC_SIZE32
)
2838 other
= BFD_RELOC_SIZE64
;
2841 as_bad (_("there are no pc-relative size relocations"));
2847 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2848 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2851 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2853 as_bad (_("unknown relocation (%u)"), other
);
2854 else if (size
!= bfd_get_reloc_size (rel
))
2855 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2856 bfd_get_reloc_size (rel
),
2858 else if (pcrel
&& !rel
->pc_relative
)
2859 as_bad (_("non-pc-relative relocation for pc-relative field"));
2860 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2862 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2864 as_bad (_("relocated field and relocation type differ in signedness"));
2873 as_bad (_("there are no unsigned pc-relative relocations"));
2876 case 1: return BFD_RELOC_8_PCREL
;
2877 case 2: return BFD_RELOC_16_PCREL
;
2878 case 4: return BFD_RELOC_32_PCREL
;
2879 case 8: return BFD_RELOC_64_PCREL
;
2881 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2888 case 4: return BFD_RELOC_X86_64_32S
;
2893 case 1: return BFD_RELOC_8
;
2894 case 2: return BFD_RELOC_16
;
2895 case 4: return BFD_RELOC_32
;
2896 case 8: return BFD_RELOC_64
;
2898 as_bad (_("cannot do %s %u byte relocation"),
2899 sign
> 0 ? "signed" : "unsigned", size
);
2905 /* Here we decide which fixups can be adjusted to make them relative to
2906 the beginning of the section instead of the symbol. Basically we need
2907 to make sure that the dynamic relocations are done correctly, so in
2908 some cases we force the original symbol to be used. */
2911 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2917 /* Don't adjust pc-relative references to merge sections in 64-bit
2919 if (use_rela_relocations
2920 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2924 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2925 and changed later by validate_fix. */
2926 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2927 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2930 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2931 for size relocations. */
2932 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2933 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2934 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2935 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2936 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2944 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2945 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2946 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2960 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2961 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2968 intel_float_operand (const char *mnemonic
)
2970 /* Note that the value returned is meaningful only for opcodes with (memory)
2971 operands, hence the code here is free to improperly handle opcodes that
2972 have no operands (for better performance and smaller code). */
2974 if (mnemonic
[0] != 'f')
2975 return 0; /* non-math */
2977 switch (mnemonic
[1])
2979 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2980 the fs segment override prefix not currently handled because no
2981 call path can make opcodes without operands get here */
2983 return 2 /* integer op */;
2985 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2986 return 3; /* fldcw/fldenv */
2989 if (mnemonic
[2] != 'o' /* fnop */)
2990 return 3; /* non-waiting control op */
2993 if (mnemonic
[2] == 's')
2994 return 3; /* frstor/frstpm */
2997 if (mnemonic
[2] == 'a')
2998 return 3; /* fsave */
2999 if (mnemonic
[2] == 't')
3001 switch (mnemonic
[3])
3003 case 'c': /* fstcw */
3004 case 'd': /* fstdw */
3005 case 'e': /* fstenv */
3006 case 's': /* fsts[gw] */
3012 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3013 return 0; /* fxsave/fxrstor are not really math ops */
3020 /* Build the VEX prefix. */
3023 build_vex_prefix (const insn_template
*t
)
3025 unsigned int register_specifier
;
3026 unsigned int implied_prefix
;
3027 unsigned int vector_length
;
3029 /* Check register specifier. */
3030 if (i
.vex
.register_specifier
)
3032 register_specifier
=
3033 ~register_number (i
.vex
.register_specifier
) & 0xf;
3034 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3037 register_specifier
= 0xf;
3039 /* Use 2-byte VEX prefix by swappping destination and source
3042 && i
.operands
== i
.reg_operands
3043 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3044 && i
.tm
.opcode_modifier
.s
3047 unsigned int xchg
= i
.operands
- 1;
3048 union i386_op temp_op
;
3049 i386_operand_type temp_type
;
3051 temp_type
= i
.types
[xchg
];
3052 i
.types
[xchg
] = i
.types
[0];
3053 i
.types
[0] = temp_type
;
3054 temp_op
= i
.op
[xchg
];
3055 i
.op
[xchg
] = i
.op
[0];
3058 gas_assert (i
.rm
.mode
== 3);
3062 i
.rm
.regmem
= i
.rm
.reg
;
3065 /* Use the next insn. */
3069 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3070 vector_length
= avxscalar
;
3072 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3074 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3079 case DATA_PREFIX_OPCODE
:
3082 case REPE_PREFIX_OPCODE
:
3085 case REPNE_PREFIX_OPCODE
:
3092 /* Use 2-byte VEX prefix if possible. */
3093 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3094 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3095 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3097 /* 2-byte VEX prefix. */
3101 i
.vex
.bytes
[0] = 0xc5;
3103 /* Check the REX.R bit. */
3104 r
= (i
.rex
& REX_R
) ? 0 : 1;
3105 i
.vex
.bytes
[1] = (r
<< 7
3106 | register_specifier
<< 3
3107 | vector_length
<< 2
3112 /* 3-byte VEX prefix. */
3117 switch (i
.tm
.opcode_modifier
.vexopcode
)
3121 i
.vex
.bytes
[0] = 0xc4;
3125 i
.vex
.bytes
[0] = 0xc4;
3129 i
.vex
.bytes
[0] = 0xc4;
3133 i
.vex
.bytes
[0] = 0x8f;
3137 i
.vex
.bytes
[0] = 0x8f;
3141 i
.vex
.bytes
[0] = 0x8f;
3147 /* The high 3 bits of the second VEX byte are 1's compliment
3148 of RXB bits from REX. */
3149 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3151 /* Check the REX.W bit. */
3152 w
= (i
.rex
& REX_W
) ? 1 : 0;
3153 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3156 i
.vex
.bytes
[2] = (w
<< 7
3157 | register_specifier
<< 3
3158 | vector_length
<< 2
3163 /* Build the EVEX prefix. */
3166 build_evex_prefix (void)
3168 unsigned int register_specifier
;
3169 unsigned int implied_prefix
;
3171 rex_byte vrex_used
= 0;
3173 /* Check register specifier. */
3174 if (i
.vex
.register_specifier
)
3176 gas_assert ((i
.vrex
& REX_X
) == 0);
3178 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3179 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3180 register_specifier
+= 8;
3181 /* The upper 16 registers are encoded in the fourth byte of the
3183 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3184 i
.vex
.bytes
[3] = 0x8;
3185 register_specifier
= ~register_specifier
& 0xf;
3189 register_specifier
= 0xf;
3191 /* Encode upper 16 vector index register in the fourth byte of
3193 if (!(i
.vrex
& REX_X
))
3194 i
.vex
.bytes
[3] = 0x8;
3199 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3204 case DATA_PREFIX_OPCODE
:
3207 case REPE_PREFIX_OPCODE
:
3210 case REPNE_PREFIX_OPCODE
:
3217 /* 4 byte EVEX prefix. */
3219 i
.vex
.bytes
[0] = 0x62;
3222 switch (i
.tm
.opcode_modifier
.vexopcode
)
3238 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3240 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3242 /* The fifth bit of the second EVEX byte is 1's compliment of the
3243 REX_R bit in VREX. */
3244 if (!(i
.vrex
& REX_R
))
3245 i
.vex
.bytes
[1] |= 0x10;
3249 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3251 /* When all operands are registers, the REX_X bit in REX is not
3252 used. We reuse it to encode the upper 16 registers, which is
3253 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3254 as 1's compliment. */
3255 if ((i
.vrex
& REX_B
))
3258 i
.vex
.bytes
[1] &= ~0x40;
3262 /* EVEX instructions shouldn't need the REX prefix. */
3263 i
.vrex
&= ~vrex_used
;
3264 gas_assert (i
.vrex
== 0);
3266 /* Check the REX.W bit. */
3267 w
= (i
.rex
& REX_W
) ? 1 : 0;
3268 if (i
.tm
.opcode_modifier
.vexw
)
3270 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3273 /* If w is not set it means we are dealing with WIG instruction. */
3276 if (evexwig
== evexw1
)
3280 /* Encode the U bit. */
3281 implied_prefix
|= 0x4;
3283 /* The third byte of the EVEX prefix. */
3284 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3286 /* The fourth byte of the EVEX prefix. */
3287 /* The zeroing-masking bit. */
3288 if (i
.mask
&& i
.mask
->zeroing
)
3289 i
.vex
.bytes
[3] |= 0x80;
3291 /* Don't always set the broadcast bit if there is no RC. */
3294 /* Encode the vector length. */
3295 unsigned int vec_length
;
3297 switch (i
.tm
.opcode_modifier
.evex
)
3299 case EVEXLIG
: /* LL' is ignored */
3300 vec_length
= evexlig
<< 5;
3303 vec_length
= 0 << 5;
3306 vec_length
= 1 << 5;
3309 vec_length
= 2 << 5;
3315 i
.vex
.bytes
[3] |= vec_length
;
3316 /* Encode the broadcast bit. */
3318 i
.vex
.bytes
[3] |= 0x10;
3322 if (i
.rounding
->type
!= saeonly
)
3323 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3325 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3328 if (i
.mask
&& i
.mask
->mask
)
3329 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3333 process_immext (void)
3337 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3340 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3341 with an opcode suffix which is coded in the same place as an
3342 8-bit immediate field would be.
3343 Here we check those operands and remove them afterwards. */
3346 for (x
= 0; x
< i
.operands
; x
++)
3347 if (register_number (i
.op
[x
].regs
) != x
)
3348 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3349 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3355 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3357 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3358 suffix which is coded in the same place as an 8-bit immediate
3360 Here we check those operands and remove them afterwards. */
3363 if (i
.operands
!= 3)
3366 for (x
= 0; x
< 2; x
++)
3367 if (register_number (i
.op
[x
].regs
) != x
)
3368 goto bad_register_operand
;
3370 /* Check for third operand for mwaitx/monitorx insn. */
3371 if (register_number (i
.op
[x
].regs
)
3372 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3374 bad_register_operand
:
3375 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3376 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3383 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3384 which is coded in the same place as an 8-bit immediate field
3385 would be. Here we fake an 8-bit immediate operand from the
3386 opcode suffix stored in tm.extension_opcode.
3388 AVX instructions also use this encoding, for some of
3389 3 argument instructions. */
3391 gas_assert (i
.imm_operands
<= 1
3393 || ((i
.tm
.opcode_modifier
.vex
3394 || i
.tm
.opcode_modifier
.evex
)
3395 && i
.operands
<= 4)));
3397 exp
= &im_expressions
[i
.imm_operands
++];
3398 i
.op
[i
.operands
].imms
= exp
;
3399 i
.types
[i
.operands
] = imm8
;
3401 exp
->X_op
= O_constant
;
3402 exp
->X_add_number
= i
.tm
.extension_opcode
;
3403 i
.tm
.extension_opcode
= None
;
3410 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3415 as_bad (_("invalid instruction `%s' after `%s'"),
3416 i
.tm
.name
, i
.hle_prefix
);
3419 if (i
.prefix
[LOCK_PREFIX
])
3421 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3425 case HLEPrefixRelease
:
3426 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3428 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3432 if (i
.mem_operands
== 0
3433 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3435 as_bad (_("memory destination needed for instruction `%s'"
3436 " after `xrelease'"), i
.tm
.name
);
3443 /* This is the guts of the machine-dependent assembler. LINE points to a
3444 machine dependent instruction. This function is supposed to emit
3445 the frags/bytes it assembles to. */
3448 md_assemble (char *line
)
3451 char mnemonic
[MAX_MNEM_SIZE
];
3452 const insn_template
*t
;
3454 /* Initialize globals. */
3455 memset (&i
, '\0', sizeof (i
));
3456 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3457 i
.reloc
[j
] = NO_RELOC
;
3458 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3459 memset (im_expressions
, '\0', sizeof (im_expressions
));
3460 save_stack_p
= save_stack
;
3462 /* First parse an instruction mnemonic & call i386_operand for the operands.
3463 We assume that the scrubber has arranged it so that line[0] is the valid
3464 start of a (possibly prefixed) mnemonic. */
3466 line
= parse_insn (line
, mnemonic
);
3470 line
= parse_operands (line
, mnemonic
);
3475 /* Now we've parsed the mnemonic into a set of templates, and have the
3476 operands at hand. */
3478 /* All intel opcodes have reversed operands except for "bound" and
3479 "enter". We also don't reverse intersegment "jmp" and "call"
3480 instructions with 2 immediate operands so that the immediate segment
3481 precedes the offset, as it does when in AT&T mode. */
3484 && (strcmp (mnemonic
, "bound") != 0)
3485 && (strcmp (mnemonic
, "invlpga") != 0)
3486 && !(operand_type_check (i
.types
[0], imm
)
3487 && operand_type_check (i
.types
[1], imm
)))
3490 /* The order of the immediates should be reversed
3491 for 2 immediates extrq and insertq instructions */
3492 if (i
.imm_operands
== 2
3493 && (strcmp (mnemonic
, "extrq") == 0
3494 || strcmp (mnemonic
, "insertq") == 0))
3495 swap_2_operands (0, 1);
3500 /* Don't optimize displacement for movabs since it only takes 64bit
3503 && i
.disp_encoding
!= disp_encoding_32bit
3504 && (flag_code
!= CODE_64BIT
3505 || strcmp (mnemonic
, "movabs") != 0))
3508 /* Next, we find a template that matches the given insn,
3509 making sure the overlap of the given operands types is consistent
3510 with the template operand types. */
3512 if (!(t
= match_template ()))
3515 if (sse_check
!= check_none
3516 && !i
.tm
.opcode_modifier
.noavx
3517 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3518 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3519 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3520 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3521 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3522 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3524 (sse_check
== check_warning
3526 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3529 /* Zap movzx and movsx suffix. The suffix has been set from
3530 "word ptr" or "byte ptr" on the source operand in Intel syntax
3531 or extracted from mnemonic in AT&T syntax. But we'll use
3532 the destination register to choose the suffix for encoding. */
3533 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3535 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3536 there is no suffix, the default will be byte extension. */
3537 if (i
.reg_operands
!= 2
3540 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3545 if (i
.tm
.opcode_modifier
.fwait
)
3546 if (!add_prefix (FWAIT_OPCODE
))
3549 /* Check if REP prefix is OK. */
3550 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3552 as_bad (_("invalid instruction `%s' after `%s'"),
3553 i
.tm
.name
, i
.rep_prefix
);
3557 /* Check for lock without a lockable instruction. Destination operand
3558 must be memory unless it is xchg (0x86). */
3559 if (i
.prefix
[LOCK_PREFIX
]
3560 && (!i
.tm
.opcode_modifier
.islockable
3561 || i
.mem_operands
== 0
3562 || (i
.tm
.base_opcode
!= 0x86
3563 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3565 as_bad (_("expecting lockable instruction after `lock'"));
3569 /* Check if HLE prefix is OK. */
3570 if (i
.hle_prefix
&& !check_hle ())
3573 /* Check BND prefix. */
3574 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3575 as_bad (_("expecting valid branch instruction after `bnd'"));
3577 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3578 && flag_code
== CODE_64BIT
3579 && i
.prefix
[ADDR_PREFIX
])
3580 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3582 /* Insert BND prefix. */
3584 && i
.tm
.opcode_modifier
.bndprefixok
3585 && !i
.prefix
[BND_PREFIX
])
3586 add_prefix (BND_PREFIX_OPCODE
);
3588 /* Check string instruction segment overrides. */
3589 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3591 if (!check_string ())
3593 i
.disp_operands
= 0;
3596 if (!process_suffix ())
3599 /* Update operand types. */
3600 for (j
= 0; j
< i
.operands
; j
++)
3601 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3603 /* Make still unresolved immediate matches conform to size of immediate
3604 given in i.suffix. */
3605 if (!finalize_imm ())
3608 if (i
.types
[0].bitfield
.imm1
)
3609 i
.imm_operands
= 0; /* kludge for shift insns. */
3611 /* We only need to check those implicit registers for instructions
3612 with 3 operands or less. */
3613 if (i
.operands
<= 3)
3614 for (j
= 0; j
< i
.operands
; j
++)
3615 if (i
.types
[j
].bitfield
.inoutportreg
3616 || i
.types
[j
].bitfield
.shiftcount
3617 || i
.types
[j
].bitfield
.acc
3618 || i
.types
[j
].bitfield
.floatacc
)
3621 /* ImmExt should be processed after SSE2AVX. */
3622 if (!i
.tm
.opcode_modifier
.sse2avx
3623 && i
.tm
.opcode_modifier
.immext
)
3626 /* For insns with operands there are more diddles to do to the opcode. */
3629 if (!process_operands ())
3632 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3634 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3635 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3638 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3640 if (flag_code
== CODE_16BIT
)
3642 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3647 if (i
.tm
.opcode_modifier
.vex
)
3648 build_vex_prefix (t
);
3650 build_evex_prefix ();
3653 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3654 instructions may define INT_OPCODE as well, so avoid this corner
3655 case for those instructions that use MODRM. */
3656 if (i
.tm
.base_opcode
== INT_OPCODE
3657 && !i
.tm
.opcode_modifier
.modrm
3658 && i
.op
[0].imms
->X_add_number
== 3)
3660 i
.tm
.base_opcode
= INT3_OPCODE
;
3664 if ((i
.tm
.opcode_modifier
.jump
3665 || i
.tm
.opcode_modifier
.jumpbyte
3666 || i
.tm
.opcode_modifier
.jumpdword
)
3667 && i
.op
[0].disps
->X_op
== O_constant
)
3669 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3670 the absolute address given by the constant. Since ix86 jumps and
3671 calls are pc relative, we need to generate a reloc. */
3672 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3673 i
.op
[0].disps
->X_op
= O_symbol
;
3676 if (i
.tm
.opcode_modifier
.rex64
)
3679 /* For 8 bit registers we need an empty rex prefix. Also if the
3680 instruction already has a prefix, we need to convert old
3681 registers to new ones. */
3683 if ((i
.types
[0].bitfield
.reg8
3684 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3685 || (i
.types
[1].bitfield
.reg8
3686 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3687 || ((i
.types
[0].bitfield
.reg8
3688 || i
.types
[1].bitfield
.reg8
)
3693 i
.rex
|= REX_OPCODE
;
3694 for (x
= 0; x
< 2; x
++)
3696 /* Look for 8 bit operand that uses old registers. */
3697 if (i
.types
[x
].bitfield
.reg8
3698 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3700 /* In case it is "hi" register, give up. */
3701 if (i
.op
[x
].regs
->reg_num
> 3)
3702 as_bad (_("can't encode register '%s%s' in an "
3703 "instruction requiring REX prefix."),
3704 register_prefix
, i
.op
[x
].regs
->reg_name
);
3706 /* Otherwise it is equivalent to the extended register.
3707 Since the encoding doesn't change this is merely
3708 cosmetic cleanup for debug output. */
3710 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3716 add_prefix (REX_OPCODE
| i
.rex
);
3718 /* We are ready to output the insn. */
3723 parse_insn (char *line
, char *mnemonic
)
3726 char *token_start
= l
;
3729 const insn_template
*t
;
3735 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3740 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3742 as_bad (_("no such instruction: `%s'"), token_start
);
3747 if (!is_space_char (*l
)
3748 && *l
!= END_OF_INSN
3750 || (*l
!= PREFIX_SEPARATOR
3753 as_bad (_("invalid character %s in mnemonic"),
3754 output_invalid (*l
));
3757 if (token_start
== l
)
3759 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3760 as_bad (_("expecting prefix; got nothing"));
3762 as_bad (_("expecting mnemonic; got nothing"));
3766 /* Look up instruction (or prefix) via hash table. */
3767 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3769 if (*l
!= END_OF_INSN
3770 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3771 && current_templates
3772 && current_templates
->start
->opcode_modifier
.isprefix
)
3774 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3776 as_bad ((flag_code
!= CODE_64BIT
3777 ? _("`%s' is only supported in 64-bit mode")
3778 : _("`%s' is not supported in 64-bit mode")),
3779 current_templates
->start
->name
);
3782 /* If we are in 16-bit mode, do not allow addr16 or data16.
3783 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3784 if ((current_templates
->start
->opcode_modifier
.size16
3785 || current_templates
->start
->opcode_modifier
.size32
)
3786 && flag_code
!= CODE_64BIT
3787 && (current_templates
->start
->opcode_modifier
.size32
3788 ^ (flag_code
== CODE_16BIT
)))
3790 as_bad (_("redundant %s prefix"),
3791 current_templates
->start
->name
);
3794 /* Add prefix, checking for repeated prefixes. */
3795 switch (add_prefix (current_templates
->start
->base_opcode
))
3800 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3801 i
.hle_prefix
= current_templates
->start
->name
;
3802 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3803 i
.bnd_prefix
= current_templates
->start
->name
;
3805 i
.rep_prefix
= current_templates
->start
->name
;
3810 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3817 if (!current_templates
)
3819 /* Check if we should swap operand or force 32bit displacement in
3821 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3823 else if (mnem_p
- 3 == dot_p
3826 i
.disp_encoding
= disp_encoding_8bit
;
3827 else if (mnem_p
- 4 == dot_p
3831 i
.disp_encoding
= disp_encoding_32bit
;
3836 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3839 if (!current_templates
)
3842 /* See if we can get a match by trimming off a suffix. */
3845 case WORD_MNEM_SUFFIX
:
3846 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3847 i
.suffix
= SHORT_MNEM_SUFFIX
;
3849 case BYTE_MNEM_SUFFIX
:
3850 case QWORD_MNEM_SUFFIX
:
3851 i
.suffix
= mnem_p
[-1];
3853 current_templates
= (const templates
*) hash_find (op_hash
,
3856 case SHORT_MNEM_SUFFIX
:
3857 case LONG_MNEM_SUFFIX
:
3860 i
.suffix
= mnem_p
[-1];
3862 current_templates
= (const templates
*) hash_find (op_hash
,
3871 if (intel_float_operand (mnemonic
) == 1)
3872 i
.suffix
= SHORT_MNEM_SUFFIX
;
3874 i
.suffix
= LONG_MNEM_SUFFIX
;
3876 current_templates
= (const templates
*) hash_find (op_hash
,
3881 if (!current_templates
)
3883 as_bad (_("no such instruction: `%s'"), token_start
);
3888 if (current_templates
->start
->opcode_modifier
.jump
3889 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3891 /* Check for a branch hint. We allow ",pt" and ",pn" for
3892 predict taken and predict not taken respectively.
3893 I'm not sure that branch hints actually do anything on loop
3894 and jcxz insns (JumpByte) for current Pentium4 chips. They
3895 may work in the future and it doesn't hurt to accept them
3897 if (l
[0] == ',' && l
[1] == 'p')
3901 if (!add_prefix (DS_PREFIX_OPCODE
))
3905 else if (l
[2] == 'n')
3907 if (!add_prefix (CS_PREFIX_OPCODE
))
3913 /* Any other comma loses. */
3916 as_bad (_("invalid character %s in mnemonic"),
3917 output_invalid (*l
));
3921 /* Check if instruction is supported on specified architecture. */
3923 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3925 supported
|= cpu_flags_match (t
);
3926 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3930 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3932 as_bad (flag_code
== CODE_64BIT
3933 ? _("`%s' is not supported in 64-bit mode")
3934 : _("`%s' is only supported in 64-bit mode"),
3935 current_templates
->start
->name
);
3938 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3940 as_bad (_("`%s' is not supported on `%s%s'"),
3941 current_templates
->start
->name
,
3942 cpu_arch_name
? cpu_arch_name
: default_arch
,
3943 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3948 if (!cpu_arch_flags
.bitfield
.cpui386
3949 && (flag_code
!= CODE_16BIT
))
3951 as_warn (_("use .code16 to ensure correct addressing mode"));
3958 parse_operands (char *l
, const char *mnemonic
)
3962 /* 1 if operand is pending after ','. */
3963 unsigned int expecting_operand
= 0;
3965 /* Non-zero if operand parens not balanced. */
3966 unsigned int paren_not_balanced
;
3968 while (*l
!= END_OF_INSN
)
3970 /* Skip optional white space before operand. */
3971 if (is_space_char (*l
))
3973 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3975 as_bad (_("invalid character %s before operand %d"),
3976 output_invalid (*l
),
3980 token_start
= l
; /* After white space. */
3981 paren_not_balanced
= 0;
3982 while (paren_not_balanced
|| *l
!= ',')
3984 if (*l
== END_OF_INSN
)
3986 if (paren_not_balanced
)
3989 as_bad (_("unbalanced parenthesis in operand %d."),
3992 as_bad (_("unbalanced brackets in operand %d."),
3997 break; /* we are done */
3999 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4001 as_bad (_("invalid character %s in operand %d"),
4002 output_invalid (*l
),
4009 ++paren_not_balanced
;
4011 --paren_not_balanced
;
4016 ++paren_not_balanced
;
4018 --paren_not_balanced
;
4022 if (l
!= token_start
)
4023 { /* Yes, we've read in another operand. */
4024 unsigned int operand_ok
;
4025 this_operand
= i
.operands
++;
4026 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4027 if (i
.operands
> MAX_OPERANDS
)
4029 as_bad (_("spurious operands; (%d operands/instruction max)"),
4033 /* Now parse operand adding info to 'i' as we go along. */
4034 END_STRING_AND_SAVE (l
);
4038 i386_intel_operand (token_start
,
4039 intel_float_operand (mnemonic
));
4041 operand_ok
= i386_att_operand (token_start
);
4043 RESTORE_END_STRING (l
);
4049 if (expecting_operand
)
4051 expecting_operand_after_comma
:
4052 as_bad (_("expecting operand after ','; got nothing"));
4057 as_bad (_("expecting operand before ','; got nothing"));
4062 /* Now *l must be either ',' or END_OF_INSN. */
4065 if (*++l
== END_OF_INSN
)
4067 /* Just skip it, if it's \n complain. */
4068 goto expecting_operand_after_comma
;
4070 expecting_operand
= 1;
4077 swap_2_operands (int xchg1
, int xchg2
)
4079 union i386_op temp_op
;
4080 i386_operand_type temp_type
;
4081 enum bfd_reloc_code_real temp_reloc
;
4083 temp_type
= i
.types
[xchg2
];
4084 i
.types
[xchg2
] = i
.types
[xchg1
];
4085 i
.types
[xchg1
] = temp_type
;
4086 temp_op
= i
.op
[xchg2
];
4087 i
.op
[xchg2
] = i
.op
[xchg1
];
4088 i
.op
[xchg1
] = temp_op
;
4089 temp_reloc
= i
.reloc
[xchg2
];
4090 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4091 i
.reloc
[xchg1
] = temp_reloc
;
4095 if (i
.mask
->operand
== xchg1
)
4096 i
.mask
->operand
= xchg2
;
4097 else if (i
.mask
->operand
== xchg2
)
4098 i
.mask
->operand
= xchg1
;
4102 if (i
.broadcast
->operand
== xchg1
)
4103 i
.broadcast
->operand
= xchg2
;
4104 else if (i
.broadcast
->operand
== xchg2
)
4105 i
.broadcast
->operand
= xchg1
;
4109 if (i
.rounding
->operand
== xchg1
)
4110 i
.rounding
->operand
= xchg2
;
4111 else if (i
.rounding
->operand
== xchg2
)
4112 i
.rounding
->operand
= xchg1
;
4117 swap_operands (void)
4123 swap_2_operands (1, i
.operands
- 2);
4126 swap_2_operands (0, i
.operands
- 1);
4132 if (i
.mem_operands
== 2)
4134 const seg_entry
*temp_seg
;
4135 temp_seg
= i
.seg
[0];
4136 i
.seg
[0] = i
.seg
[1];
4137 i
.seg
[1] = temp_seg
;
4141 /* Try to ensure constant immediates are represented in the smallest
4146 char guess_suffix
= 0;
4150 guess_suffix
= i
.suffix
;
4151 else if (i
.reg_operands
)
4153 /* Figure out a suffix from the last register operand specified.
4154 We can't do this properly yet, ie. excluding InOutPortReg,
4155 but the following works for instructions with immediates.
4156 In any case, we can't set i.suffix yet. */
4157 for (op
= i
.operands
; --op
>= 0;)
4158 if (i
.types
[op
].bitfield
.reg8
)
4160 guess_suffix
= BYTE_MNEM_SUFFIX
;
4163 else if (i
.types
[op
].bitfield
.reg16
)
4165 guess_suffix
= WORD_MNEM_SUFFIX
;
4168 else if (i
.types
[op
].bitfield
.reg32
)
4170 guess_suffix
= LONG_MNEM_SUFFIX
;
4173 else if (i
.types
[op
].bitfield
.reg64
)
4175 guess_suffix
= QWORD_MNEM_SUFFIX
;
4179 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4180 guess_suffix
= WORD_MNEM_SUFFIX
;
4182 for (op
= i
.operands
; --op
>= 0;)
4183 if (operand_type_check (i
.types
[op
], imm
))
4185 switch (i
.op
[op
].imms
->X_op
)
4188 /* If a suffix is given, this operand may be shortened. */
4189 switch (guess_suffix
)
4191 case LONG_MNEM_SUFFIX
:
4192 i
.types
[op
].bitfield
.imm32
= 1;
4193 i
.types
[op
].bitfield
.imm64
= 1;
4195 case WORD_MNEM_SUFFIX
:
4196 i
.types
[op
].bitfield
.imm16
= 1;
4197 i
.types
[op
].bitfield
.imm32
= 1;
4198 i
.types
[op
].bitfield
.imm32s
= 1;
4199 i
.types
[op
].bitfield
.imm64
= 1;
4201 case BYTE_MNEM_SUFFIX
:
4202 i
.types
[op
].bitfield
.imm8
= 1;
4203 i
.types
[op
].bitfield
.imm8s
= 1;
4204 i
.types
[op
].bitfield
.imm16
= 1;
4205 i
.types
[op
].bitfield
.imm32
= 1;
4206 i
.types
[op
].bitfield
.imm32s
= 1;
4207 i
.types
[op
].bitfield
.imm64
= 1;
4211 /* If this operand is at most 16 bits, convert it
4212 to a signed 16 bit number before trying to see
4213 whether it will fit in an even smaller size.
4214 This allows a 16-bit operand such as $0xffe0 to
4215 be recognised as within Imm8S range. */
4216 if ((i
.types
[op
].bitfield
.imm16
)
4217 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4219 i
.op
[op
].imms
->X_add_number
=
4220 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4222 if ((i
.types
[op
].bitfield
.imm32
)
4223 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4226 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4227 ^ ((offsetT
) 1 << 31))
4228 - ((offsetT
) 1 << 31));
4231 = operand_type_or (i
.types
[op
],
4232 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4234 /* We must avoid matching of Imm32 templates when 64bit
4235 only immediate is available. */
4236 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4237 i
.types
[op
].bitfield
.imm32
= 0;
4244 /* Symbols and expressions. */
4246 /* Convert symbolic operand to proper sizes for matching, but don't
4247 prevent matching a set of insns that only supports sizes other
4248 than those matching the insn suffix. */
4250 i386_operand_type mask
, allowed
;
4251 const insn_template
*t
;
4253 operand_type_set (&mask
, 0);
4254 operand_type_set (&allowed
, 0);
4256 for (t
= current_templates
->start
;
4257 t
< current_templates
->end
;
4259 allowed
= operand_type_or (allowed
,
4260 t
->operand_types
[op
]);
4261 switch (guess_suffix
)
4263 case QWORD_MNEM_SUFFIX
:
4264 mask
.bitfield
.imm64
= 1;
4265 mask
.bitfield
.imm32s
= 1;
4267 case LONG_MNEM_SUFFIX
:
4268 mask
.bitfield
.imm32
= 1;
4270 case WORD_MNEM_SUFFIX
:
4271 mask
.bitfield
.imm16
= 1;
4273 case BYTE_MNEM_SUFFIX
:
4274 mask
.bitfield
.imm8
= 1;
4279 allowed
= operand_type_and (mask
, allowed
);
4280 if (!operand_type_all_zero (&allowed
))
4281 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4288 /* Try to use the smallest displacement type too. */
4290 optimize_disp (void)
4294 for (op
= i
.operands
; --op
>= 0;)
4295 if (operand_type_check (i
.types
[op
], disp
))
4297 if (i
.op
[op
].disps
->X_op
== O_constant
)
4299 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4301 if (i
.types
[op
].bitfield
.disp16
4302 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4304 /* If this operand is at most 16 bits, convert
4305 to a signed 16 bit number and don't use 64bit
4307 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4308 i
.types
[op
].bitfield
.disp64
= 0;
4310 if (i
.types
[op
].bitfield
.disp32
4311 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4313 /* If this operand is at most 32 bits, convert
4314 to a signed 32 bit number and don't use 64bit
4316 op_disp
&= (((offsetT
) 2 << 31) - 1);
4317 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4318 i
.types
[op
].bitfield
.disp64
= 0;
4320 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4322 i
.types
[op
].bitfield
.disp8
= 0;
4323 i
.types
[op
].bitfield
.disp16
= 0;
4324 i
.types
[op
].bitfield
.disp32
= 0;
4325 i
.types
[op
].bitfield
.disp32s
= 0;
4326 i
.types
[op
].bitfield
.disp64
= 0;
4330 else if (flag_code
== CODE_64BIT
)
4332 if (fits_in_signed_long (op_disp
))
4334 i
.types
[op
].bitfield
.disp64
= 0;
4335 i
.types
[op
].bitfield
.disp32s
= 1;
4337 if (i
.prefix
[ADDR_PREFIX
]
4338 && fits_in_unsigned_long (op_disp
))
4339 i
.types
[op
].bitfield
.disp32
= 1;
4341 if ((i
.types
[op
].bitfield
.disp32
4342 || i
.types
[op
].bitfield
.disp32s
4343 || i
.types
[op
].bitfield
.disp16
)
4344 && fits_in_signed_byte (op_disp
))
4345 i
.types
[op
].bitfield
.disp8
= 1;
4347 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4348 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4350 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4351 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4352 i
.types
[op
].bitfield
.disp8
= 0;
4353 i
.types
[op
].bitfield
.disp16
= 0;
4354 i
.types
[op
].bitfield
.disp32
= 0;
4355 i
.types
[op
].bitfield
.disp32s
= 0;
4356 i
.types
[op
].bitfield
.disp64
= 0;
4359 /* We only support 64bit displacement on constants. */
4360 i
.types
[op
].bitfield
.disp64
= 0;
4364 /* Check if operands are valid for the instruction. */
4367 check_VecOperands (const insn_template
*t
)
4371 /* Without VSIB byte, we can't have a vector register for index. */
4372 if (!t
->opcode_modifier
.vecsib
4374 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4375 || i
.index_reg
->reg_type
.bitfield
.regymm
4376 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4378 i
.error
= unsupported_vector_index_register
;
4382 /* Check if default mask is allowed. */
4383 if (t
->opcode_modifier
.nodefmask
4384 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4386 i
.error
= no_default_mask
;
4390 /* For VSIB byte, we need a vector register for index, and all vector
4391 registers must be distinct. */
4392 if (t
->opcode_modifier
.vecsib
)
4395 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4396 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4397 || (t
->opcode_modifier
.vecsib
== VecSIB256
4398 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4399 || (t
->opcode_modifier
.vecsib
== VecSIB512
4400 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4402 i
.error
= invalid_vsib_address
;
4406 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4407 if (i
.reg_operands
== 2 && !i
.mask
)
4409 gas_assert (i
.types
[0].bitfield
.regxmm
4410 || i
.types
[0].bitfield
.regymm
);
4411 gas_assert (i
.types
[2].bitfield
.regxmm
4412 || i
.types
[2].bitfield
.regymm
);
4413 if (operand_check
== check_none
)
4415 if (register_number (i
.op
[0].regs
)
4416 != register_number (i
.index_reg
)
4417 && register_number (i
.op
[2].regs
)
4418 != register_number (i
.index_reg
)
4419 && register_number (i
.op
[0].regs
)
4420 != register_number (i
.op
[2].regs
))
4422 if (operand_check
== check_error
)
4424 i
.error
= invalid_vector_register_set
;
4427 as_warn (_("mask, index, and destination registers should be distinct"));
4429 else if (i
.reg_operands
== 1 && i
.mask
)
4431 if ((i
.types
[1].bitfield
.regymm
4432 || i
.types
[1].bitfield
.regzmm
)
4433 && (register_number (i
.op
[1].regs
)
4434 == register_number (i
.index_reg
)))
4436 if (operand_check
== check_error
)
4438 i
.error
= invalid_vector_register_set
;
4441 if (operand_check
!= check_none
)
4442 as_warn (_("index and destination registers should be distinct"));
4447 /* Check if broadcast is supported by the instruction and is applied
4448 to the memory operand. */
4451 int broadcasted_opnd_size
;
4453 /* Check if specified broadcast is supported in this instruction,
4454 and it's applied to memory operand of DWORD or QWORD type,
4455 depending on VecESize. */
4456 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4457 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4458 || (t
->opcode_modifier
.vecesize
== 0
4459 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4460 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4461 || (t
->opcode_modifier
.vecesize
== 1
4462 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4463 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4466 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4467 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4468 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4469 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4470 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4471 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4472 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4473 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4474 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4478 if ((broadcasted_opnd_size
== 256
4479 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4480 || (broadcasted_opnd_size
== 512
4481 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4484 i
.error
= unsupported_broadcast
;
4488 /* If broadcast is supported in this instruction, we need to check if
4489 operand of one-element size isn't specified without broadcast. */
4490 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4492 /* Find memory operand. */
4493 for (op
= 0; op
< i
.operands
; op
++)
4494 if (operand_type_check (i
.types
[op
], anymem
))
4496 gas_assert (op
< i
.operands
);
4497 /* Check size of the memory operand. */
4498 if ((t
->opcode_modifier
.vecesize
== 0
4499 && i
.types
[op
].bitfield
.dword
)
4500 || (t
->opcode_modifier
.vecesize
== 1
4501 && i
.types
[op
].bitfield
.qword
))
4503 i
.error
= broadcast_needed
;
4508 /* Check if requested masking is supported. */
4510 && (!t
->opcode_modifier
.masking
4512 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4514 i
.error
= unsupported_masking
;
4518 /* Check if masking is applied to dest operand. */
4519 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4521 i
.error
= mask_not_on_destination
;
4528 if ((i
.rounding
->type
!= saeonly
4529 && !t
->opcode_modifier
.staticrounding
)
4530 || (i
.rounding
->type
== saeonly
4531 && (t
->opcode_modifier
.staticrounding
4532 || !t
->opcode_modifier
.sae
)))
4534 i
.error
= unsupported_rc_sae
;
4537 /* If the instruction has several immediate operands and one of
4538 them is rounding, the rounding operand should be the last
4539 immediate operand. */
4540 if (i
.imm_operands
> 1
4541 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4543 i
.error
= rc_sae_operand_not_last_imm
;
4548 /* Check vector Disp8 operand. */
4549 if (t
->opcode_modifier
.disp8memshift
)
4552 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4554 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4556 for (op
= 0; op
< i
.operands
; op
++)
4557 if (operand_type_check (i
.types
[op
], disp
)
4558 && i
.op
[op
].disps
->X_op
== O_constant
)
4560 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4561 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4562 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4565 i
.types
[op
].bitfield
.vec_disp8
= 1;
4568 /* Vector insn can only have Vec_Disp8/Disp32 in
4569 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4571 i
.types
[op
].bitfield
.disp8
= 0;
4572 if (flag_code
!= CODE_16BIT
)
4573 i
.types
[op
].bitfield
.disp16
= 0;
4576 else if (flag_code
!= CODE_16BIT
)
4578 /* One form of this instruction supports vector Disp8.
4579 Try vector Disp8 if we need to use Disp32. */
4580 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4582 i
.error
= try_vector_disp8
;
4594 /* Check if operands are valid for the instruction. Update VEX
4598 VEX_check_operands (const insn_template
*t
)
4600 /* VREX is only valid with EVEX prefix. */
4601 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4603 i
.error
= invalid_register_operand
;
4607 if (!t
->opcode_modifier
.vex
)
4610 /* Only check VEX_Imm4, which must be the first operand. */
4611 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4613 if (i
.op
[0].imms
->X_op
!= O_constant
4614 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4620 /* Turn off Imm8 so that update_imm won't complain. */
4621 i
.types
[0] = vec_imm4
;
4627 static const insn_template
*
4628 match_template (void)
4630 /* Points to template once we've found it. */
4631 const insn_template
*t
;
4632 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4633 i386_operand_type overlap4
;
4634 unsigned int found_reverse_match
;
4635 i386_opcode_modifier suffix_check
;
4636 i386_operand_type operand_types
[MAX_OPERANDS
];
4637 int addr_prefix_disp
;
4639 unsigned int found_cpu_match
;
4640 unsigned int check_register
;
4641 enum i386_error specific_error
= 0;
4643 #if MAX_OPERANDS != 5
4644 # error "MAX_OPERANDS must be 5."
4647 found_reverse_match
= 0;
4648 addr_prefix_disp
= -1;
4650 memset (&suffix_check
, 0, sizeof (suffix_check
));
4651 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4652 suffix_check
.no_bsuf
= 1;
4653 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4654 suffix_check
.no_wsuf
= 1;
4655 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4656 suffix_check
.no_ssuf
= 1;
4657 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4658 suffix_check
.no_lsuf
= 1;
4659 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4660 suffix_check
.no_qsuf
= 1;
4661 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4662 suffix_check
.no_ldsuf
= 1;
4664 /* Must have right number of operands. */
4665 i
.error
= number_of_operands_mismatch
;
4667 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4669 addr_prefix_disp
= -1;
4671 if (i
.operands
!= t
->operands
)
4674 /* Check processor support. */
4675 i
.error
= unsupported
;
4676 found_cpu_match
= (cpu_flags_match (t
)
4677 == CPU_FLAGS_PERFECT_MATCH
);
4678 if (!found_cpu_match
)
4681 /* Check old gcc support. */
4682 i
.error
= old_gcc_only
;
4683 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4686 /* Check AT&T mnemonic. */
4687 i
.error
= unsupported_with_intel_mnemonic
;
4688 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4691 /* Check AT&T/Intel syntax. */
4692 i
.error
= unsupported_syntax
;
4693 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4694 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4697 /* Check the suffix, except for some instructions in intel mode. */
4698 i
.error
= invalid_instruction_suffix
;
4699 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4700 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4701 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4702 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4703 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4704 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4705 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4708 if (!operand_size_match (t
))
4711 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4712 operand_types
[j
] = t
->operand_types
[j
];
4714 /* In general, don't allow 64-bit operands in 32-bit mode. */
4715 if (i
.suffix
== QWORD_MNEM_SUFFIX
4716 && flag_code
!= CODE_64BIT
4718 ? (!t
->opcode_modifier
.ignoresize
4719 && !intel_float_operand (t
->name
))
4720 : intel_float_operand (t
->name
) != 2)
4721 && ((!operand_types
[0].bitfield
.regmmx
4722 && !operand_types
[0].bitfield
.regxmm
4723 && !operand_types
[0].bitfield
.regymm
4724 && !operand_types
[0].bitfield
.regzmm
)
4725 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4726 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4727 && operand_types
[t
->operands
> 1].bitfield
.regymm
4728 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4729 && (t
->base_opcode
!= 0x0fc7
4730 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4733 /* In general, don't allow 32-bit operands on pre-386. */
4734 else if (i
.suffix
== LONG_MNEM_SUFFIX
4735 && !cpu_arch_flags
.bitfield
.cpui386
4737 ? (!t
->opcode_modifier
.ignoresize
4738 && !intel_float_operand (t
->name
))
4739 : intel_float_operand (t
->name
) != 2)
4740 && ((!operand_types
[0].bitfield
.regmmx
4741 && !operand_types
[0].bitfield
.regxmm
)
4742 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4743 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4746 /* Do not verify operands when there are none. */
4750 /* We've found a match; break out of loop. */
4754 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4755 into Disp32/Disp16/Disp32 operand. */
4756 if (i
.prefix
[ADDR_PREFIX
] != 0)
4758 /* There should be only one Disp operand. */
4762 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4764 if (operand_types
[j
].bitfield
.disp16
)
4766 addr_prefix_disp
= j
;
4767 operand_types
[j
].bitfield
.disp32
= 1;
4768 operand_types
[j
].bitfield
.disp16
= 0;
4774 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4776 if (operand_types
[j
].bitfield
.disp32
)
4778 addr_prefix_disp
= j
;
4779 operand_types
[j
].bitfield
.disp32
= 0;
4780 operand_types
[j
].bitfield
.disp16
= 1;
4786 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4788 if (operand_types
[j
].bitfield
.disp64
)
4790 addr_prefix_disp
= j
;
4791 operand_types
[j
].bitfield
.disp64
= 0;
4792 operand_types
[j
].bitfield
.disp32
= 1;
4800 /* We check register size if needed. */
4801 check_register
= t
->opcode_modifier
.checkregsize
;
4802 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4803 switch (t
->operands
)
4806 if (!operand_type_match (overlap0
, i
.types
[0]))
4810 /* xchg %eax, %eax is a special case. It is an aliase for nop
4811 only in 32bit mode and we can use opcode 0x90. In 64bit
4812 mode, we can't use 0x90 for xchg %eax, %eax since it should
4813 zero-extend %eax to %rax. */
4814 if (flag_code
== CODE_64BIT
4815 && t
->base_opcode
== 0x90
4816 && operand_type_equal (&i
.types
[0], &acc32
)
4817 && operand_type_equal (&i
.types
[1], &acc32
))
4821 /* If we swap operand in encoding, we either match
4822 the next one or reverse direction of operands. */
4823 if (t
->opcode_modifier
.s
)
4825 else if (t
->opcode_modifier
.d
)
4830 /* If we swap operand in encoding, we match the next one. */
4831 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4835 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4836 if (!operand_type_match (overlap0
, i
.types
[0])
4837 || !operand_type_match (overlap1
, i
.types
[1])
4839 && !operand_type_register_match (overlap0
, i
.types
[0],
4841 overlap1
, i
.types
[1],
4844 /* Check if other direction is valid ... */
4845 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4849 /* Try reversing direction of operands. */
4850 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4851 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4852 if (!operand_type_match (overlap0
, i
.types
[0])
4853 || !operand_type_match (overlap1
, i
.types
[1])
4855 && !operand_type_register_match (overlap0
,
4862 /* Does not match either direction. */
4865 /* found_reverse_match holds which of D or FloatDR
4867 if (t
->opcode_modifier
.d
)
4868 found_reverse_match
= Opcode_D
;
4869 else if (t
->opcode_modifier
.floatd
)
4870 found_reverse_match
= Opcode_FloatD
;
4872 found_reverse_match
= 0;
4873 if (t
->opcode_modifier
.floatr
)
4874 found_reverse_match
|= Opcode_FloatR
;
4878 /* Found a forward 2 operand match here. */
4879 switch (t
->operands
)
4882 overlap4
= operand_type_and (i
.types
[4],
4885 overlap3
= operand_type_and (i
.types
[3],
4888 overlap2
= operand_type_and (i
.types
[2],
4893 switch (t
->operands
)
4896 if (!operand_type_match (overlap4
, i
.types
[4])
4897 || !operand_type_register_match (overlap3
,
4905 if (!operand_type_match (overlap3
, i
.types
[3])
4907 && !operand_type_register_match (overlap2
,
4915 /* Here we make use of the fact that there are no
4916 reverse match 3 operand instructions, and all 3
4917 operand instructions only need to be checked for
4918 register consistency between operands 2 and 3. */
4919 if (!operand_type_match (overlap2
, i
.types
[2])
4921 && !operand_type_register_match (overlap1
,
4931 /* Found either forward/reverse 2, 3 or 4 operand match here:
4932 slip through to break. */
4934 if (!found_cpu_match
)
4936 found_reverse_match
= 0;
4940 /* Check if vector and VEX operands are valid. */
4941 if (check_VecOperands (t
) || VEX_check_operands (t
))
4943 specific_error
= i
.error
;
4947 /* We've found a match; break out of loop. */
4951 if (t
== current_templates
->end
)
4953 /* We found no match. */
4954 const char *err_msg
;
4955 switch (specific_error
? specific_error
: i
.error
)
4959 case operand_size_mismatch
:
4960 err_msg
= _("operand size mismatch");
4962 case operand_type_mismatch
:
4963 err_msg
= _("operand type mismatch");
4965 case register_type_mismatch
:
4966 err_msg
= _("register type mismatch");
4968 case number_of_operands_mismatch
:
4969 err_msg
= _("number of operands mismatch");
4971 case invalid_instruction_suffix
:
4972 err_msg
= _("invalid instruction suffix");
4975 err_msg
= _("constant doesn't fit in 4 bits");
4978 err_msg
= _("only supported with old gcc");
4980 case unsupported_with_intel_mnemonic
:
4981 err_msg
= _("unsupported with Intel mnemonic");
4983 case unsupported_syntax
:
4984 err_msg
= _("unsupported syntax");
4987 as_bad (_("unsupported instruction `%s'"),
4988 current_templates
->start
->name
);
4990 case invalid_vsib_address
:
4991 err_msg
= _("invalid VSIB address");
4993 case invalid_vector_register_set
:
4994 err_msg
= _("mask, index, and destination registers must be distinct");
4996 case unsupported_vector_index_register
:
4997 err_msg
= _("unsupported vector index register");
4999 case unsupported_broadcast
:
5000 err_msg
= _("unsupported broadcast");
5002 case broadcast_not_on_src_operand
:
5003 err_msg
= _("broadcast not on source memory operand");
5005 case broadcast_needed
:
5006 err_msg
= _("broadcast is needed for operand of such type");
5008 case unsupported_masking
:
5009 err_msg
= _("unsupported masking");
5011 case mask_not_on_destination
:
5012 err_msg
= _("mask not on destination operand");
5014 case no_default_mask
:
5015 err_msg
= _("default mask isn't allowed");
5017 case unsupported_rc_sae
:
5018 err_msg
= _("unsupported static rounding/sae");
5020 case rc_sae_operand_not_last_imm
:
5022 err_msg
= _("RC/SAE operand must precede immediate operands");
5024 err_msg
= _("RC/SAE operand must follow immediate operands");
5026 case invalid_register_operand
:
5027 err_msg
= _("invalid register operand");
5030 as_bad (_("%s for `%s'"), err_msg
,
5031 current_templates
->start
->name
);
5035 if (!quiet_warnings
)
5038 && (i
.types
[0].bitfield
.jumpabsolute
5039 != operand_types
[0].bitfield
.jumpabsolute
))
5041 as_warn (_("indirect %s without `*'"), t
->name
);
5044 if (t
->opcode_modifier
.isprefix
5045 && t
->opcode_modifier
.ignoresize
)
5047 /* Warn them that a data or address size prefix doesn't
5048 affect assembly of the next line of code. */
5049 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5053 /* Copy the template we found. */
5056 if (addr_prefix_disp
!= -1)
5057 i
.tm
.operand_types
[addr_prefix_disp
]
5058 = operand_types
[addr_prefix_disp
];
5060 if (found_reverse_match
)
5062 /* If we found a reverse match we must alter the opcode
5063 direction bit. found_reverse_match holds bits to change
5064 (different for int & float insns). */
5066 i
.tm
.base_opcode
^= found_reverse_match
;
5068 i
.tm
.operand_types
[0] = operand_types
[1];
5069 i
.tm
.operand_types
[1] = operand_types
[0];
5078 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5079 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5081 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5083 as_bad (_("`%s' operand %d must use `%ses' segment"),
5089 /* There's only ever one segment override allowed per instruction.
5090 This instruction possibly has a legal segment override on the
5091 second operand, so copy the segment to where non-string
5092 instructions store it, allowing common code. */
5093 i
.seg
[0] = i
.seg
[1];
5095 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5097 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5099 as_bad (_("`%s' operand %d must use `%ses' segment"),
5110 process_suffix (void)
5112 /* If matched instruction specifies an explicit instruction mnemonic
5114 if (i
.tm
.opcode_modifier
.size16
)
5115 i
.suffix
= WORD_MNEM_SUFFIX
;
5116 else if (i
.tm
.opcode_modifier
.size32
)
5117 i
.suffix
= LONG_MNEM_SUFFIX
;
5118 else if (i
.tm
.opcode_modifier
.size64
)
5119 i
.suffix
= QWORD_MNEM_SUFFIX
;
5120 else if (i
.reg_operands
)
5122 /* If there's no instruction mnemonic suffix we try to invent one
5123 based on register operands. */
5126 /* We take i.suffix from the last register operand specified,
5127 Destination register type is more significant than source
5128 register type. crc32 in SSE4.2 prefers source register
5130 if (i
.tm
.base_opcode
== 0xf20f38f1)
5132 if (i
.types
[0].bitfield
.reg16
)
5133 i
.suffix
= WORD_MNEM_SUFFIX
;
5134 else if (i
.types
[0].bitfield
.reg32
)
5135 i
.suffix
= LONG_MNEM_SUFFIX
;
5136 else if (i
.types
[0].bitfield
.reg64
)
5137 i
.suffix
= QWORD_MNEM_SUFFIX
;
5139 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5141 if (i
.types
[0].bitfield
.reg8
)
5142 i
.suffix
= BYTE_MNEM_SUFFIX
;
5149 if (i
.tm
.base_opcode
== 0xf20f38f1
5150 || i
.tm
.base_opcode
== 0xf20f38f0)
5152 /* We have to know the operand size for crc32. */
5153 as_bad (_("ambiguous memory operand size for `%s`"),
5158 for (op
= i
.operands
; --op
>= 0;)
5159 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5161 if (i
.types
[op
].bitfield
.reg8
)
5163 i
.suffix
= BYTE_MNEM_SUFFIX
;
5166 else if (i
.types
[op
].bitfield
.reg16
)
5168 i
.suffix
= WORD_MNEM_SUFFIX
;
5171 else if (i
.types
[op
].bitfield
.reg32
)
5173 i
.suffix
= LONG_MNEM_SUFFIX
;
5176 else if (i
.types
[op
].bitfield
.reg64
)
5178 i
.suffix
= QWORD_MNEM_SUFFIX
;
5184 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5187 && i
.tm
.opcode_modifier
.ignoresize
5188 && i
.tm
.opcode_modifier
.no_bsuf
)
5190 else if (!check_byte_reg ())
5193 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5196 && i
.tm
.opcode_modifier
.ignoresize
5197 && i
.tm
.opcode_modifier
.no_lsuf
)
5199 else if (!check_long_reg ())
5202 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5205 && i
.tm
.opcode_modifier
.ignoresize
5206 && i
.tm
.opcode_modifier
.no_qsuf
)
5208 else if (!check_qword_reg ())
5211 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5214 && i
.tm
.opcode_modifier
.ignoresize
5215 && i
.tm
.opcode_modifier
.no_wsuf
)
5217 else if (!check_word_reg ())
5220 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5221 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5222 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5224 /* Skip if the instruction has x/y/z suffix. match_template
5225 should check if it is a valid suffix. */
5227 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5228 /* Do nothing if the instruction is going to ignore the prefix. */
5233 else if (i
.tm
.opcode_modifier
.defaultsize
5235 /* exclude fldenv/frstor/fsave/fstenv */
5236 && i
.tm
.opcode_modifier
.no_ssuf
)
5238 i
.suffix
= stackop_size
;
5240 else if (intel_syntax
5242 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5243 || i
.tm
.opcode_modifier
.jumpbyte
5244 || i
.tm
.opcode_modifier
.jumpintersegment
5245 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5246 && i
.tm
.extension_opcode
<= 3)))
5251 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5253 i
.suffix
= QWORD_MNEM_SUFFIX
;
5257 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5258 i
.suffix
= LONG_MNEM_SUFFIX
;
5261 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5262 i
.suffix
= WORD_MNEM_SUFFIX
;
5271 if (i
.tm
.opcode_modifier
.w
)
5273 as_bad (_("no instruction mnemonic suffix given and "
5274 "no register operands; can't size instruction"));
5280 unsigned int suffixes
;
5282 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5283 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5285 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5287 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5289 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5291 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5294 /* There are more than suffix matches. */
5295 if (i
.tm
.opcode_modifier
.w
5296 || ((suffixes
& (suffixes
- 1))
5297 && !i
.tm
.opcode_modifier
.defaultsize
5298 && !i
.tm
.opcode_modifier
.ignoresize
))
5300 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5306 /* Change the opcode based on the operand size given by i.suffix;
5307 We don't need to change things for byte insns. */
5310 && i
.suffix
!= BYTE_MNEM_SUFFIX
5311 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5312 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5313 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5315 /* It's not a byte, select word/dword operation. */
5316 if (i
.tm
.opcode_modifier
.w
)
5318 if (i
.tm
.opcode_modifier
.shortform
)
5319 i
.tm
.base_opcode
|= 8;
5321 i
.tm
.base_opcode
|= 1;
5324 /* Now select between word & dword operations via the operand
5325 size prefix, except for instructions that will ignore this
5327 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5329 /* The address size override prefix changes the size of the
5331 if ((flag_code
== CODE_32BIT
5332 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5333 || (flag_code
!= CODE_32BIT
5334 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5335 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5338 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5339 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5340 && !i
.tm
.opcode_modifier
.ignoresize
5341 && !i
.tm
.opcode_modifier
.floatmf
5342 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5343 || (flag_code
== CODE_64BIT
5344 && i
.tm
.opcode_modifier
.jumpbyte
)))
5346 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5348 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5349 prefix
= ADDR_PREFIX_OPCODE
;
5351 if (!add_prefix (prefix
))
5355 /* Set mode64 for an operand. */
5356 if (i
.suffix
== QWORD_MNEM_SUFFIX
5357 && flag_code
== CODE_64BIT
5358 && !i
.tm
.opcode_modifier
.norex64
)
5360 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5361 need rex64. cmpxchg8b is also a special case. */
5362 if (! (i
.operands
== 2
5363 && i
.tm
.base_opcode
== 0x90
5364 && i
.tm
.extension_opcode
== None
5365 && operand_type_equal (&i
.types
[0], &acc64
)
5366 && operand_type_equal (&i
.types
[1], &acc64
))
5367 && ! (i
.operands
== 1
5368 && i
.tm
.base_opcode
== 0xfc7
5369 && i
.tm
.extension_opcode
== 1
5370 && !operand_type_check (i
.types
[0], reg
)
5371 && operand_type_check (i
.types
[0], anymem
)))
5375 /* Size floating point instruction. */
5376 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5377 if (i
.tm
.opcode_modifier
.floatmf
)
5378 i
.tm
.base_opcode
^= 4;
5385 check_byte_reg (void)
5389 for (op
= i
.operands
; --op
>= 0;)
5391 /* If this is an eight bit register, it's OK. If it's the 16 or
5392 32 bit version of an eight bit register, we will just use the
5393 low portion, and that's OK too. */
5394 if (i
.types
[op
].bitfield
.reg8
)
5397 /* I/O port address operands are OK too. */
5398 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5401 /* crc32 doesn't generate this warning. */
5402 if (i
.tm
.base_opcode
== 0xf20f38f0)
5405 if ((i
.types
[op
].bitfield
.reg16
5406 || i
.types
[op
].bitfield
.reg32
5407 || i
.types
[op
].bitfield
.reg64
)
5408 && i
.op
[op
].regs
->reg_num
< 4
5409 /* Prohibit these changes in 64bit mode, since the lowering
5410 would be more complicated. */
5411 && flag_code
!= CODE_64BIT
)
5413 #if REGISTER_WARNINGS
5414 if (!quiet_warnings
)
5415 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5417 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5418 ? REGNAM_AL
- REGNAM_AX
5419 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5421 i
.op
[op
].regs
->reg_name
,
5426 /* Any other register is bad. */
5427 if (i
.types
[op
].bitfield
.reg16
5428 || i
.types
[op
].bitfield
.reg32
5429 || i
.types
[op
].bitfield
.reg64
5430 || i
.types
[op
].bitfield
.regmmx
5431 || i
.types
[op
].bitfield
.regxmm
5432 || i
.types
[op
].bitfield
.regymm
5433 || i
.types
[op
].bitfield
.regzmm
5434 || i
.types
[op
].bitfield
.sreg2
5435 || i
.types
[op
].bitfield
.sreg3
5436 || i
.types
[op
].bitfield
.control
5437 || i
.types
[op
].bitfield
.debug
5438 || i
.types
[op
].bitfield
.test
5439 || i
.types
[op
].bitfield
.floatreg
5440 || i
.types
[op
].bitfield
.floatacc
)
5442 as_bad (_("`%s%s' not allowed with `%s%c'"),
5444 i
.op
[op
].regs
->reg_name
,
5454 check_long_reg (void)
5458 for (op
= i
.operands
; --op
>= 0;)
5459 /* Reject eight bit registers, except where the template requires
5460 them. (eg. movzb) */
5461 if (i
.types
[op
].bitfield
.reg8
5462 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5463 || i
.tm
.operand_types
[op
].bitfield
.reg32
5464 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5466 as_bad (_("`%s%s' not allowed with `%s%c'"),
5468 i
.op
[op
].regs
->reg_name
,
5473 /* Warn if the e prefix on a general reg is missing. */
5474 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5475 && i
.types
[op
].bitfield
.reg16
5476 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5477 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5479 /* Prohibit these changes in the 64bit mode, since the
5480 lowering is more complicated. */
5481 if (flag_code
== CODE_64BIT
)
5483 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5484 register_prefix
, i
.op
[op
].regs
->reg_name
,
5488 #if REGISTER_WARNINGS
5489 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5491 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5492 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5495 /* Warn if the r prefix on a general reg is present. */
5496 else if (i
.types
[op
].bitfield
.reg64
5497 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5498 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5501 && i
.tm
.opcode_modifier
.toqword
5502 && !i
.types
[0].bitfield
.regxmm
)
5504 /* Convert to QWORD. We want REX byte. */
5505 i
.suffix
= QWORD_MNEM_SUFFIX
;
5509 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5510 register_prefix
, i
.op
[op
].regs
->reg_name
,
5519 check_qword_reg (void)
5523 for (op
= i
.operands
; --op
>= 0; )
5524 /* Reject eight bit registers, except where the template requires
5525 them. (eg. movzb) */
5526 if (i
.types
[op
].bitfield
.reg8
5527 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5528 || i
.tm
.operand_types
[op
].bitfield
.reg32
5529 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5531 as_bad (_("`%s%s' not allowed with `%s%c'"),
5533 i
.op
[op
].regs
->reg_name
,
5538 /* Warn if the r prefix on a general reg is missing. */
5539 else if ((i
.types
[op
].bitfield
.reg16
5540 || i
.types
[op
].bitfield
.reg32
)
5541 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5542 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5544 /* Prohibit these changes in the 64bit mode, since the
5545 lowering is more complicated. */
5547 && i
.tm
.opcode_modifier
.todword
5548 && !i
.types
[0].bitfield
.regxmm
)
5550 /* Convert to DWORD. We don't want REX byte. */
5551 i
.suffix
= LONG_MNEM_SUFFIX
;
5555 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5556 register_prefix
, i
.op
[op
].regs
->reg_name
,
5565 check_word_reg (void)
5568 for (op
= i
.operands
; --op
>= 0;)
5569 /* Reject eight bit registers, except where the template requires
5570 them. (eg. movzb) */
5571 if (i
.types
[op
].bitfield
.reg8
5572 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5573 || i
.tm
.operand_types
[op
].bitfield
.reg32
5574 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5576 as_bad (_("`%s%s' not allowed with `%s%c'"),
5578 i
.op
[op
].regs
->reg_name
,
5583 /* Warn if the e or r prefix on a general reg is present. */
5584 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5585 && (i
.types
[op
].bitfield
.reg32
5586 || i
.types
[op
].bitfield
.reg64
)
5587 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5588 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5590 /* Prohibit these changes in the 64bit mode, since the
5591 lowering is more complicated. */
5592 if (flag_code
== CODE_64BIT
)
5594 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5595 register_prefix
, i
.op
[op
].regs
->reg_name
,
5599 #if REGISTER_WARNINGS
5600 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5602 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5603 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5610 update_imm (unsigned int j
)
5612 i386_operand_type overlap
= i
.types
[j
];
5613 if ((overlap
.bitfield
.imm8
5614 || overlap
.bitfield
.imm8s
5615 || overlap
.bitfield
.imm16
5616 || overlap
.bitfield
.imm32
5617 || overlap
.bitfield
.imm32s
5618 || overlap
.bitfield
.imm64
)
5619 && !operand_type_equal (&overlap
, &imm8
)
5620 && !operand_type_equal (&overlap
, &imm8s
)
5621 && !operand_type_equal (&overlap
, &imm16
)
5622 && !operand_type_equal (&overlap
, &imm32
)
5623 && !operand_type_equal (&overlap
, &imm32s
)
5624 && !operand_type_equal (&overlap
, &imm64
))
5628 i386_operand_type temp
;
5630 operand_type_set (&temp
, 0);
5631 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5633 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5634 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5636 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5637 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5638 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5640 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5641 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5644 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5647 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5648 || operand_type_equal (&overlap
, &imm16_32
)
5649 || operand_type_equal (&overlap
, &imm16_32s
))
5651 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5656 if (!operand_type_equal (&overlap
, &imm8
)
5657 && !operand_type_equal (&overlap
, &imm8s
)
5658 && !operand_type_equal (&overlap
, &imm16
)
5659 && !operand_type_equal (&overlap
, &imm32
)
5660 && !operand_type_equal (&overlap
, &imm32s
)
5661 && !operand_type_equal (&overlap
, &imm64
))
5663 as_bad (_("no instruction mnemonic suffix given; "
5664 "can't determine immediate size"));
5668 i
.types
[j
] = overlap
;
5678 /* Update the first 2 immediate operands. */
5679 n
= i
.operands
> 2 ? 2 : i
.operands
;
5682 for (j
= 0; j
< n
; j
++)
5683 if (update_imm (j
) == 0)
5686 /* The 3rd operand can't be immediate operand. */
5687 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5694 bad_implicit_operand (int xmm
)
5696 const char *ireg
= xmm
? "xmm0" : "ymm0";
5699 as_bad (_("the last operand of `%s' must be `%s%s'"),
5700 i
.tm
.name
, register_prefix
, ireg
);
5702 as_bad (_("the first operand of `%s' must be `%s%s'"),
5703 i
.tm
.name
, register_prefix
, ireg
);
5708 process_operands (void)
5710 /* Default segment register this instruction will use for memory
5711 accesses. 0 means unknown. This is only for optimizing out
5712 unnecessary segment overrides. */
5713 const seg_entry
*default_seg
= 0;
5715 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5717 unsigned int dupl
= i
.operands
;
5718 unsigned int dest
= dupl
- 1;
5721 /* The destination must be an xmm register. */
5722 gas_assert (i
.reg_operands
5723 && MAX_OPERANDS
> dupl
5724 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5726 if (i
.tm
.opcode_modifier
.firstxmm0
)
5728 /* The first operand is implicit and must be xmm0. */
5729 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5730 if (register_number (i
.op
[0].regs
) != 0)
5731 return bad_implicit_operand (1);
5733 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5735 /* Keep xmm0 for instructions with VEX prefix and 3
5741 /* We remove the first xmm0 and keep the number of
5742 operands unchanged, which in fact duplicates the
5744 for (j
= 1; j
< i
.operands
; j
++)
5746 i
.op
[j
- 1] = i
.op
[j
];
5747 i
.types
[j
- 1] = i
.types
[j
];
5748 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5752 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5754 gas_assert ((MAX_OPERANDS
- 1) > dupl
5755 && (i
.tm
.opcode_modifier
.vexsources
5758 /* Add the implicit xmm0 for instructions with VEX prefix
5760 for (j
= i
.operands
; j
> 0; j
--)
5762 i
.op
[j
] = i
.op
[j
- 1];
5763 i
.types
[j
] = i
.types
[j
- 1];
5764 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5767 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5768 i
.types
[0] = regxmm
;
5769 i
.tm
.operand_types
[0] = regxmm
;
5772 i
.reg_operands
+= 2;
5777 i
.op
[dupl
] = i
.op
[dest
];
5778 i
.types
[dupl
] = i
.types
[dest
];
5779 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5788 i
.op
[dupl
] = i
.op
[dest
];
5789 i
.types
[dupl
] = i
.types
[dest
];
5790 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5793 if (i
.tm
.opcode_modifier
.immext
)
5796 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5800 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5801 gas_assert (i
.reg_operands
5802 && (operand_type_equal (&i
.types
[0], ®xmm
)
5803 || operand_type_equal (&i
.types
[0], ®ymm
)
5804 || operand_type_equal (&i
.types
[0], ®zmm
)));
5805 if (register_number (i
.op
[0].regs
) != 0)
5806 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5808 for (j
= 1; j
< i
.operands
; j
++)
5810 i
.op
[j
- 1] = i
.op
[j
];
5811 i
.types
[j
- 1] = i
.types
[j
];
5813 /* We need to adjust fields in i.tm since they are used by
5814 build_modrm_byte. */
5815 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5822 else if (i
.tm
.opcode_modifier
.regkludge
)
5824 /* The imul $imm, %reg instruction is converted into
5825 imul $imm, %reg, %reg, and the clr %reg instruction
5826 is converted into xor %reg, %reg. */
5828 unsigned int first_reg_op
;
5830 if (operand_type_check (i
.types
[0], reg
))
5834 /* Pretend we saw the extra register operand. */
5835 gas_assert (i
.reg_operands
== 1
5836 && i
.op
[first_reg_op
+ 1].regs
== 0);
5837 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5838 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5843 if (i
.tm
.opcode_modifier
.shortform
)
5845 if (i
.types
[0].bitfield
.sreg2
5846 || i
.types
[0].bitfield
.sreg3
)
5848 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5849 && i
.op
[0].regs
->reg_num
== 1)
5851 as_bad (_("you can't `pop %scs'"), register_prefix
);
5854 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5855 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5860 /* The register or float register operand is in operand
5864 if (i
.types
[0].bitfield
.floatreg
5865 || operand_type_check (i
.types
[0], reg
))
5869 /* Register goes in low 3 bits of opcode. */
5870 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5871 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5873 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5875 /* Warn about some common errors, but press on regardless.
5876 The first case can be generated by gcc (<= 2.8.1). */
5877 if (i
.operands
== 2)
5879 /* Reversed arguments on faddp, fsubp, etc. */
5880 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5881 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5882 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5886 /* Extraneous `l' suffix on fp insn. */
5887 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5888 register_prefix
, i
.op
[0].regs
->reg_name
);
5893 else if (i
.tm
.opcode_modifier
.modrm
)
5895 /* The opcode is completed (modulo i.tm.extension_opcode which
5896 must be put into the modrm byte). Now, we make the modrm and
5897 index base bytes based on all the info we've collected. */
5899 default_seg
= build_modrm_byte ();
5901 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5905 else if (i
.tm
.opcode_modifier
.isstring
)
5907 /* For the string instructions that allow a segment override
5908 on one of their operands, the default segment is ds. */
5912 if (i
.tm
.base_opcode
== 0x8d /* lea */
5915 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5917 /* If a segment was explicitly specified, and the specified segment
5918 is not the default, use an opcode prefix to select it. If we
5919 never figured out what the default segment is, then default_seg
5920 will be zero at this point, and the specified segment prefix will
5922 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5924 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5930 static const seg_entry
*
5931 build_modrm_byte (void)
5933 const seg_entry
*default_seg
= 0;
5934 unsigned int source
, dest
;
5937 /* The first operand of instructions with VEX prefix and 3 sources
5938 must be VEX_Imm4. */
5939 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5942 unsigned int nds
, reg_slot
;
5945 if (i
.tm
.opcode_modifier
.veximmext
5946 && i
.tm
.opcode_modifier
.immext
)
5948 dest
= i
.operands
- 2;
5949 gas_assert (dest
== 3);
5952 dest
= i
.operands
- 1;
5955 /* There are 2 kinds of instructions:
5956 1. 5 operands: 4 register operands or 3 register operands
5957 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5958 VexW0 or VexW1. The destination must be either XMM, YMM or
5960 2. 4 operands: 4 register operands or 3 register operands
5961 plus 1 memory operand, VexXDS, and VexImmExt */
5962 gas_assert ((i
.reg_operands
== 4
5963 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5964 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5965 && (i
.tm
.opcode_modifier
.veximmext
5966 || (i
.imm_operands
== 1
5967 && i
.types
[0].bitfield
.vec_imm4
5968 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5969 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5970 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5971 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5972 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5974 if (i
.imm_operands
== 0)
5976 /* When there is no immediate operand, generate an 8bit
5977 immediate operand to encode the first operand. */
5978 exp
= &im_expressions
[i
.imm_operands
++];
5979 i
.op
[i
.operands
].imms
= exp
;
5980 i
.types
[i
.operands
] = imm8
;
5982 /* If VexW1 is set, the first operand is the source and
5983 the second operand is encoded in the immediate operand. */
5984 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5995 /* FMA swaps REG and NDS. */
5996 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6004 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6006 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6008 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6010 exp
->X_op
= O_constant
;
6011 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6012 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6016 unsigned int imm_slot
;
6018 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6020 /* If VexW0 is set, the third operand is the source and
6021 the second operand is encoded in the immediate
6028 /* VexW1 is set, the second operand is the source and
6029 the third operand is encoded in the immediate
6035 if (i
.tm
.opcode_modifier
.immext
)
6037 /* When ImmExt is set, the immdiate byte is the last
6039 imm_slot
= i
.operands
- 1;
6047 /* Turn on Imm8 so that output_imm will generate it. */
6048 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6051 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6053 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6055 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6057 i
.op
[imm_slot
].imms
->X_add_number
6058 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6059 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6062 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6063 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6065 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6067 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6072 /* i.reg_operands MUST be the number of real register operands;
6073 implicit registers do not count. If there are 3 register
6074 operands, it must be a instruction with VexNDS. For a
6075 instruction with VexNDD, the destination register is encoded
6076 in VEX prefix. If there are 4 register operands, it must be
6077 a instruction with VEX prefix and 3 sources. */
6078 if (i
.mem_operands
== 0
6079 && ((i
.reg_operands
== 2
6080 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6081 || (i
.reg_operands
== 3
6082 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6083 || (i
.reg_operands
== 4 && vex_3_sources
)))
6091 /* When there are 3 operands, one of them may be immediate,
6092 which may be the first or the last operand. Otherwise,
6093 the first operand must be shift count register (cl) or it
6094 is an instruction with VexNDS. */
6095 gas_assert (i
.imm_operands
== 1
6096 || (i
.imm_operands
== 0
6097 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6098 || i
.types
[0].bitfield
.shiftcount
)));
6099 if (operand_type_check (i
.types
[0], imm
)
6100 || i
.types
[0].bitfield
.shiftcount
)
6106 /* When there are 4 operands, the first two must be 8bit
6107 immediate operands. The source operand will be the 3rd
6110 For instructions with VexNDS, if the first operand
6111 an imm8, the source operand is the 2nd one. If the last
6112 operand is imm8, the source operand is the first one. */
6113 gas_assert ((i
.imm_operands
== 2
6114 && i
.types
[0].bitfield
.imm8
6115 && i
.types
[1].bitfield
.imm8
)
6116 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6117 && i
.imm_operands
== 1
6118 && (i
.types
[0].bitfield
.imm8
6119 || i
.types
[i
.operands
- 1].bitfield
.imm8
6121 if (i
.imm_operands
== 2)
6125 if (i
.types
[0].bitfield
.imm8
)
6132 if (i
.tm
.opcode_modifier
.evex
)
6134 /* For EVEX instructions, when there are 5 operands, the
6135 first one must be immediate operand. If the second one
6136 is immediate operand, the source operand is the 3th
6137 one. If the last one is immediate operand, the source
6138 operand is the 2nd one. */
6139 gas_assert (i
.imm_operands
== 2
6140 && i
.tm
.opcode_modifier
.sae
6141 && operand_type_check (i
.types
[0], imm
));
6142 if (operand_type_check (i
.types
[1], imm
))
6144 else if (operand_type_check (i
.types
[4], imm
))
6158 /* RC/SAE operand could be between DEST and SRC. That happens
6159 when one operand is GPR and the other one is XMM/YMM/ZMM
6161 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6164 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6166 /* For instructions with VexNDS, the register-only source
6167 operand must be 32/64bit integer, XMM, YMM or ZMM
6168 register. It is encoded in VEX prefix. We need to
6169 clear RegMem bit before calling operand_type_equal. */
6171 i386_operand_type op
;
6174 /* Check register-only source operand when two source
6175 operands are swapped. */
6176 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6177 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6185 op
= i
.tm
.operand_types
[vvvv
];
6186 op
.bitfield
.regmem
= 0;
6187 if ((dest
+ 1) >= i
.operands
6188 || (!op
.bitfield
.reg32
6189 && op
.bitfield
.reg64
6190 && !operand_type_equal (&op
, ®xmm
)
6191 && !operand_type_equal (&op
, ®ymm
)
6192 && !operand_type_equal (&op
, ®zmm
)
6193 && !operand_type_equal (&op
, ®mask
)))
6195 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6201 /* One of the register operands will be encoded in the i.tm.reg
6202 field, the other in the combined i.tm.mode and i.tm.regmem
6203 fields. If no form of this instruction supports a memory
6204 destination operand, then we assume the source operand may
6205 sometimes be a memory operand and so we need to store the
6206 destination in the i.rm.reg field. */
6207 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6208 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6210 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6211 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6212 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6214 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6216 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6218 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6223 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6224 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6225 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6227 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6229 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6231 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6234 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6236 if (!i
.types
[0].bitfield
.control
6237 && !i
.types
[1].bitfield
.control
)
6239 i
.rex
&= ~(REX_R
| REX_B
);
6240 add_prefix (LOCK_PREFIX_OPCODE
);
6244 { /* If it's not 2 reg operands... */
6249 unsigned int fake_zero_displacement
= 0;
6252 for (op
= 0; op
< i
.operands
; op
++)
6253 if (operand_type_check (i
.types
[op
], anymem
))
6255 gas_assert (op
< i
.operands
);
6257 if (i
.tm
.opcode_modifier
.vecsib
)
6259 if (i
.index_reg
->reg_num
== RegEiz
6260 || i
.index_reg
->reg_num
== RegRiz
)
6263 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6266 i
.sib
.base
= NO_BASE_REGISTER
;
6267 i
.sib
.scale
= i
.log2_scale_factor
;
6268 /* No Vec_Disp8 if there is no base. */
6269 i
.types
[op
].bitfield
.vec_disp8
= 0;
6270 i
.types
[op
].bitfield
.disp8
= 0;
6271 i
.types
[op
].bitfield
.disp16
= 0;
6272 i
.types
[op
].bitfield
.disp64
= 0;
6273 if (flag_code
!= CODE_64BIT
)
6275 /* Must be 32 bit */
6276 i
.types
[op
].bitfield
.disp32
= 1;
6277 i
.types
[op
].bitfield
.disp32s
= 0;
6281 i
.types
[op
].bitfield
.disp32
= 0;
6282 i
.types
[op
].bitfield
.disp32s
= 1;
6285 i
.sib
.index
= i
.index_reg
->reg_num
;
6286 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6288 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6294 if (i
.base_reg
== 0)
6297 if (!i
.disp_operands
)
6299 fake_zero_displacement
= 1;
6300 /* Instructions with VSIB byte need 32bit displacement
6301 if there is no base register. */
6302 if (i
.tm
.opcode_modifier
.vecsib
)
6303 i
.types
[op
].bitfield
.disp32
= 1;
6305 if (i
.index_reg
== 0)
6307 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6308 /* Operand is just <disp> */
6309 if (flag_code
== CODE_64BIT
)
6311 /* 64bit mode overwrites the 32bit absolute
6312 addressing by RIP relative addressing and
6313 absolute addressing is encoded by one of the
6314 redundant SIB forms. */
6315 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6316 i
.sib
.base
= NO_BASE_REGISTER
;
6317 i
.sib
.index
= NO_INDEX_REGISTER
;
6318 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6319 ? disp32s
: disp32
);
6321 else if ((flag_code
== CODE_16BIT
)
6322 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6324 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6325 i
.types
[op
] = disp16
;
6329 i
.rm
.regmem
= NO_BASE_REGISTER
;
6330 i
.types
[op
] = disp32
;
6333 else if (!i
.tm
.opcode_modifier
.vecsib
)
6335 /* !i.base_reg && i.index_reg */
6336 if (i
.index_reg
->reg_num
== RegEiz
6337 || i
.index_reg
->reg_num
== RegRiz
)
6338 i
.sib
.index
= NO_INDEX_REGISTER
;
6340 i
.sib
.index
= i
.index_reg
->reg_num
;
6341 i
.sib
.base
= NO_BASE_REGISTER
;
6342 i
.sib
.scale
= i
.log2_scale_factor
;
6343 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6344 /* No Vec_Disp8 if there is no base. */
6345 i
.types
[op
].bitfield
.vec_disp8
= 0;
6346 i
.types
[op
].bitfield
.disp8
= 0;
6347 i
.types
[op
].bitfield
.disp16
= 0;
6348 i
.types
[op
].bitfield
.disp64
= 0;
6349 if (flag_code
!= CODE_64BIT
)
6351 /* Must be 32 bit */
6352 i
.types
[op
].bitfield
.disp32
= 1;
6353 i
.types
[op
].bitfield
.disp32s
= 0;
6357 i
.types
[op
].bitfield
.disp32
= 0;
6358 i
.types
[op
].bitfield
.disp32s
= 1;
6360 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6364 /* RIP addressing for 64bit mode. */
6365 else if (i
.base_reg
->reg_num
== RegRip
||
6366 i
.base_reg
->reg_num
== RegEip
)
6368 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6369 i
.rm
.regmem
= NO_BASE_REGISTER
;
6370 i
.types
[op
].bitfield
.disp8
= 0;
6371 i
.types
[op
].bitfield
.disp16
= 0;
6372 i
.types
[op
].bitfield
.disp32
= 0;
6373 i
.types
[op
].bitfield
.disp32s
= 1;
6374 i
.types
[op
].bitfield
.disp64
= 0;
6375 i
.types
[op
].bitfield
.vec_disp8
= 0;
6376 i
.flags
[op
] |= Operand_PCrel
;
6377 if (! i
.disp_operands
)
6378 fake_zero_displacement
= 1;
6380 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6382 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6383 switch (i
.base_reg
->reg_num
)
6386 if (i
.index_reg
== 0)
6388 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6389 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6393 if (i
.index_reg
== 0)
6396 if (operand_type_check (i
.types
[op
], disp
) == 0)
6398 /* fake (%bp) into 0(%bp) */
6399 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6400 i
.types
[op
].bitfield
.vec_disp8
= 1;
6402 i
.types
[op
].bitfield
.disp8
= 1;
6403 fake_zero_displacement
= 1;
6406 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6407 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6409 default: /* (%si) -> 4 or (%di) -> 5 */
6410 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6412 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6414 else /* i.base_reg and 32/64 bit mode */
6416 if (flag_code
== CODE_64BIT
6417 && operand_type_check (i
.types
[op
], disp
))
6419 i386_operand_type temp
;
6420 operand_type_set (&temp
, 0);
6421 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6422 temp
.bitfield
.vec_disp8
6423 = i
.types
[op
].bitfield
.vec_disp8
;
6425 if (i
.prefix
[ADDR_PREFIX
] == 0)
6426 i
.types
[op
].bitfield
.disp32s
= 1;
6428 i
.types
[op
].bitfield
.disp32
= 1;
6431 if (!i
.tm
.opcode_modifier
.vecsib
)
6432 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6433 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6435 i
.sib
.base
= i
.base_reg
->reg_num
;
6436 /* x86-64 ignores REX prefix bit here to avoid decoder
6438 if (!(i
.base_reg
->reg_flags
& RegRex
)
6439 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6440 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6442 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6444 fake_zero_displacement
= 1;
6445 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6446 i
.types
[op
].bitfield
.vec_disp8
= 1;
6448 i
.types
[op
].bitfield
.disp8
= 1;
6450 i
.sib
.scale
= i
.log2_scale_factor
;
6451 if (i
.index_reg
== 0)
6453 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6454 /* <disp>(%esp) becomes two byte modrm with no index
6455 register. We've already stored the code for esp
6456 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6457 Any base register besides %esp will not use the
6458 extra modrm byte. */
6459 i
.sib
.index
= NO_INDEX_REGISTER
;
6461 else if (!i
.tm
.opcode_modifier
.vecsib
)
6463 if (i
.index_reg
->reg_num
== RegEiz
6464 || i
.index_reg
->reg_num
== RegRiz
)
6465 i
.sib
.index
= NO_INDEX_REGISTER
;
6467 i
.sib
.index
= i
.index_reg
->reg_num
;
6468 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6469 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6474 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6475 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6479 if (!fake_zero_displacement
6483 fake_zero_displacement
= 1;
6484 if (i
.disp_encoding
== disp_encoding_8bit
)
6485 i
.types
[op
].bitfield
.disp8
= 1;
6487 i
.types
[op
].bitfield
.disp32
= 1;
6489 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6493 if (fake_zero_displacement
)
6495 /* Fakes a zero displacement assuming that i.types[op]
6496 holds the correct displacement size. */
6499 gas_assert (i
.op
[op
].disps
== 0);
6500 exp
= &disp_expressions
[i
.disp_operands
++];
6501 i
.op
[op
].disps
= exp
;
6502 exp
->X_op
= O_constant
;
6503 exp
->X_add_number
= 0;
6504 exp
->X_add_symbol
= (symbolS
*) 0;
6505 exp
->X_op_symbol
= (symbolS
*) 0;
6513 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6515 if (operand_type_check (i
.types
[0], imm
))
6516 i
.vex
.register_specifier
= NULL
;
6519 /* VEX.vvvv encodes one of the sources when the first
6520 operand is not an immediate. */
6521 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6522 i
.vex
.register_specifier
= i
.op
[0].regs
;
6524 i
.vex
.register_specifier
= i
.op
[1].regs
;
6527 /* Destination is a XMM register encoded in the ModRM.reg
6529 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6530 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6533 /* ModRM.rm and VEX.B encodes the other source. */
6534 if (!i
.mem_operands
)
6538 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6539 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6541 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6543 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6547 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6549 i
.vex
.register_specifier
= i
.op
[2].regs
;
6550 if (!i
.mem_operands
)
6553 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6554 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6558 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6559 (if any) based on i.tm.extension_opcode. Again, we must be
6560 careful to make sure that segment/control/debug/test/MMX
6561 registers are coded into the i.rm.reg field. */
6562 else if (i
.reg_operands
)
6565 unsigned int vex_reg
= ~0;
6567 for (op
= 0; op
< i
.operands
; op
++)
6568 if (i
.types
[op
].bitfield
.reg8
6569 || i
.types
[op
].bitfield
.reg16
6570 || i
.types
[op
].bitfield
.reg32
6571 || i
.types
[op
].bitfield
.reg64
6572 || i
.types
[op
].bitfield
.regmmx
6573 || i
.types
[op
].bitfield
.regxmm
6574 || i
.types
[op
].bitfield
.regymm
6575 || i
.types
[op
].bitfield
.regbnd
6576 || i
.types
[op
].bitfield
.regzmm
6577 || i
.types
[op
].bitfield
.regmask
6578 || i
.types
[op
].bitfield
.sreg2
6579 || i
.types
[op
].bitfield
.sreg3
6580 || i
.types
[op
].bitfield
.control
6581 || i
.types
[op
].bitfield
.debug
6582 || i
.types
[op
].bitfield
.test
)
6587 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6589 /* For instructions with VexNDS, the register-only
6590 source operand is encoded in VEX prefix. */
6591 gas_assert (mem
!= (unsigned int) ~0);
6596 gas_assert (op
< i
.operands
);
6600 /* Check register-only source operand when two source
6601 operands are swapped. */
6602 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6603 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6607 gas_assert (mem
== (vex_reg
+ 1)
6608 && op
< i
.operands
);
6613 gas_assert (vex_reg
< i
.operands
);
6617 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6619 /* For instructions with VexNDD, the register destination
6620 is encoded in VEX prefix. */
6621 if (i
.mem_operands
== 0)
6623 /* There is no memory operand. */
6624 gas_assert ((op
+ 2) == i
.operands
);
6629 /* There are only 2 operands. */
6630 gas_assert (op
< 2 && i
.operands
== 2);
6635 gas_assert (op
< i
.operands
);
6637 if (vex_reg
!= (unsigned int) ~0)
6639 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6641 if (type
->bitfield
.reg32
!= 1
6642 && type
->bitfield
.reg64
!= 1
6643 && !operand_type_equal (type
, ®xmm
)
6644 && !operand_type_equal (type
, ®ymm
)
6645 && !operand_type_equal (type
, ®zmm
)
6646 && !operand_type_equal (type
, ®mask
))
6649 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6652 /* Don't set OP operand twice. */
6655 /* If there is an extension opcode to put here, the
6656 register number must be put into the regmem field. */
6657 if (i
.tm
.extension_opcode
!= None
)
6659 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6660 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6662 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6667 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6668 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6670 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6675 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6676 must set it to 3 to indicate this is a register operand
6677 in the regmem field. */
6678 if (!i
.mem_operands
)
6682 /* Fill in i.rm.reg field with extension opcode (if any). */
6683 if (i
.tm
.extension_opcode
!= None
)
6684 i
.rm
.reg
= i
.tm
.extension_opcode
;
6690 output_branch (void)
6696 relax_substateT subtype
;
6700 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6701 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6704 if (i
.prefix
[DATA_PREFIX
] != 0)
6710 /* Pentium4 branch hints. */
6711 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6712 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6717 if (i
.prefix
[REX_PREFIX
] != 0)
6723 /* BND prefixed jump. */
6724 if (i
.prefix
[BND_PREFIX
] != 0)
6726 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6730 if (i
.prefixes
!= 0 && !intel_syntax
)
6731 as_warn (_("skipping prefixes on this instruction"));
6733 /* It's always a symbol; End frag & setup for relax.
6734 Make sure there is enough room in this frag for the largest
6735 instruction we may generate in md_convert_frag. This is 2
6736 bytes for the opcode and room for the prefix and largest
6738 frag_grow (prefix
+ 2 + 4);
6739 /* Prefix and 1 opcode byte go in fr_fix. */
6740 p
= frag_more (prefix
+ 1);
6741 if (i
.prefix
[DATA_PREFIX
] != 0)
6742 *p
++ = DATA_PREFIX_OPCODE
;
6743 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6744 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6745 *p
++ = i
.prefix
[SEG_PREFIX
];
6746 if (i
.prefix
[REX_PREFIX
] != 0)
6747 *p
++ = i
.prefix
[REX_PREFIX
];
6748 *p
= i
.tm
.base_opcode
;
6750 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6751 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6752 else if (cpu_arch_flags
.bitfield
.cpui386
)
6753 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6755 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6758 sym
= i
.op
[0].disps
->X_add_symbol
;
6759 off
= i
.op
[0].disps
->X_add_number
;
6761 if (i
.op
[0].disps
->X_op
!= O_constant
6762 && i
.op
[0].disps
->X_op
!= O_symbol
)
6764 /* Handle complex expressions. */
6765 sym
= make_expr_symbol (i
.op
[0].disps
);
6769 /* 1 possible extra opcode + 4 byte displacement go in var part.
6770 Pass reloc in fr_var. */
6771 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6781 if (i
.tm
.opcode_modifier
.jumpbyte
)
6783 /* This is a loop or jecxz type instruction. */
6785 if (i
.prefix
[ADDR_PREFIX
] != 0)
6787 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6790 /* Pentium4 branch hints. */
6791 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6792 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6794 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6803 if (flag_code
== CODE_16BIT
)
6806 if (i
.prefix
[DATA_PREFIX
] != 0)
6808 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6818 if (i
.prefix
[REX_PREFIX
] != 0)
6820 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6824 /* BND prefixed jump. */
6825 if (i
.prefix
[BND_PREFIX
] != 0)
6827 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6831 if (i
.prefixes
!= 0 && !intel_syntax
)
6832 as_warn (_("skipping prefixes on this instruction"));
6834 p
= frag_more (i
.tm
.opcode_length
+ size
);
6835 switch (i
.tm
.opcode_length
)
6838 *p
++ = i
.tm
.base_opcode
>> 8;
6840 *p
++ = i
.tm
.base_opcode
;
6846 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6847 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6849 /* All jumps handled here are signed, but don't use a signed limit
6850 check for 32 and 16 bit jumps as we want to allow wrap around at
6851 4G and 64k respectively. */
6853 fixP
->fx_signed
= 1;
6857 output_interseg_jump (void)
6865 if (flag_code
== CODE_16BIT
)
6869 if (i
.prefix
[DATA_PREFIX
] != 0)
6875 if (i
.prefix
[REX_PREFIX
] != 0)
6885 if (i
.prefixes
!= 0 && !intel_syntax
)
6886 as_warn (_("skipping prefixes on this instruction"));
6888 /* 1 opcode; 2 segment; offset */
6889 p
= frag_more (prefix
+ 1 + 2 + size
);
6891 if (i
.prefix
[DATA_PREFIX
] != 0)
6892 *p
++ = DATA_PREFIX_OPCODE
;
6894 if (i
.prefix
[REX_PREFIX
] != 0)
6895 *p
++ = i
.prefix
[REX_PREFIX
];
6897 *p
++ = i
.tm
.base_opcode
;
6898 if (i
.op
[1].imms
->X_op
== O_constant
)
6900 offsetT n
= i
.op
[1].imms
->X_add_number
;
6903 && !fits_in_unsigned_word (n
)
6904 && !fits_in_signed_word (n
))
6906 as_bad (_("16-bit jump out of range"));
6909 md_number_to_chars (p
, n
, size
);
6912 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6913 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6914 if (i
.op
[0].imms
->X_op
!= O_constant
)
6915 as_bad (_("can't handle non absolute segment in `%s'"),
6917 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6923 fragS
*insn_start_frag
;
6924 offsetT insn_start_off
;
6926 /* Tie dwarf2 debug info to the address at the start of the insn.
6927 We can't do this after the insn has been output as the current
6928 frag may have been closed off. eg. by frag_var. */
6929 dwarf2_emit_insn (0);
6931 insn_start_frag
= frag_now
;
6932 insn_start_off
= frag_now_fix ();
6935 if (i
.tm
.opcode_modifier
.jump
)
6937 else if (i
.tm
.opcode_modifier
.jumpbyte
6938 || i
.tm
.opcode_modifier
.jumpdword
)
6940 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6941 output_interseg_jump ();
6944 /* Output normal instructions here. */
6948 unsigned int prefix
;
6950 /* Some processors fail on LOCK prefix. This options makes
6951 assembler ignore LOCK prefix and serves as a workaround. */
6952 if (omit_lock_prefix
)
6954 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6956 i
.prefix
[LOCK_PREFIX
] = 0;
6959 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6960 don't need the explicit prefix. */
6961 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6963 switch (i
.tm
.opcode_length
)
6966 if (i
.tm
.base_opcode
& 0xff000000)
6968 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6973 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6975 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6976 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6979 if (prefix
!= REPE_PREFIX_OPCODE
6980 || (i
.prefix
[REP_PREFIX
]
6981 != REPE_PREFIX_OPCODE
))
6982 add_prefix (prefix
);
6985 add_prefix (prefix
);
6994 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6995 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6996 R_X86_64_GOTTPOFF relocation so that linker can safely
6997 perform IE->LE optimization. */
6998 if (x86_elf_abi
== X86_64_X32_ABI
7000 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7001 && i
.prefix
[REX_PREFIX
] == 0)
7002 add_prefix (REX_OPCODE
);
7005 /* The prefix bytes. */
7006 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7008 FRAG_APPEND_1_CHAR (*q
);
7012 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7017 /* REX byte is encoded in VEX prefix. */
7021 FRAG_APPEND_1_CHAR (*q
);
7024 /* There should be no other prefixes for instructions
7029 /* For EVEX instructions i.vrex should become 0 after
7030 build_evex_prefix. For VEX instructions upper 16 registers
7031 aren't available, so VREX should be 0. */
7034 /* Now the VEX prefix. */
7035 p
= frag_more (i
.vex
.length
);
7036 for (j
= 0; j
< i
.vex
.length
; j
++)
7037 p
[j
] = i
.vex
.bytes
[j
];
7040 /* Now the opcode; be careful about word order here! */
7041 if (i
.tm
.opcode_length
== 1)
7043 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7047 switch (i
.tm
.opcode_length
)
7051 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7052 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7056 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7066 /* Put out high byte first: can't use md_number_to_chars! */
7067 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7068 *p
= i
.tm
.base_opcode
& 0xff;
7071 /* Now the modrm byte and sib byte (if present). */
7072 if (i
.tm
.opcode_modifier
.modrm
)
7074 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7077 /* If i.rm.regmem == ESP (4)
7078 && i.rm.mode != (Register mode)
7080 ==> need second modrm byte. */
7081 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7083 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7084 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7086 | i
.sib
.scale
<< 6));
7089 if (i
.disp_operands
)
7090 output_disp (insn_start_frag
, insn_start_off
);
7093 output_imm (insn_start_frag
, insn_start_off
);
7099 pi ("" /*line*/, &i
);
7101 #endif /* DEBUG386 */
7104 /* Return the size of the displacement operand N. */
7107 disp_size (unsigned int n
)
7111 /* Vec_Disp8 has to be 8bit. */
7112 if (i
.types
[n
].bitfield
.vec_disp8
)
7114 else if (i
.types
[n
].bitfield
.disp64
)
7116 else if (i
.types
[n
].bitfield
.disp8
)
7118 else if (i
.types
[n
].bitfield
.disp16
)
7123 /* Return the size of the immediate operand N. */
7126 imm_size (unsigned int n
)
7129 if (i
.types
[n
].bitfield
.imm64
)
7131 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7133 else if (i
.types
[n
].bitfield
.imm16
)
7139 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7144 for (n
= 0; n
< i
.operands
; n
++)
7146 if (i
.types
[n
].bitfield
.vec_disp8
7147 || operand_type_check (i
.types
[n
], disp
))
7149 if (i
.op
[n
].disps
->X_op
== O_constant
)
7151 int size
= disp_size (n
);
7152 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7154 if (i
.types
[n
].bitfield
.vec_disp8
)
7156 val
= offset_in_range (val
, size
);
7157 p
= frag_more (size
);
7158 md_number_to_chars (p
, val
, size
);
7162 enum bfd_reloc_code_real reloc_type
;
7163 int size
= disp_size (n
);
7164 int sign
= i
.types
[n
].bitfield
.disp32s
;
7165 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7167 /* We can't have 8 bit displacement here. */
7168 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7170 /* The PC relative address is computed relative
7171 to the instruction boundary, so in case immediate
7172 fields follows, we need to adjust the value. */
7173 if (pcrel
&& i
.imm_operands
)
7178 for (n1
= 0; n1
< i
.operands
; n1
++)
7179 if (operand_type_check (i
.types
[n1
], imm
))
7181 /* Only one immediate is allowed for PC
7182 relative address. */
7183 gas_assert (sz
== 0);
7185 i
.op
[n
].disps
->X_add_number
-= sz
;
7187 /* We should find the immediate. */
7188 gas_assert (sz
!= 0);
7191 p
= frag_more (size
);
7192 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7194 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7195 && (((reloc_type
== BFD_RELOC_32
7196 || reloc_type
== BFD_RELOC_X86_64_32S
7197 || (reloc_type
== BFD_RELOC_64
7199 && (i
.op
[n
].disps
->X_op
== O_symbol
7200 || (i
.op
[n
].disps
->X_op
== O_add
7201 && ((symbol_get_value_expression
7202 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7204 || reloc_type
== BFD_RELOC_32_PCREL
))
7208 if (insn_start_frag
== frag_now
)
7209 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7214 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7215 for (fr
= insn_start_frag
->fr_next
;
7216 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7218 add
+= p
- frag_now
->fr_literal
;
7223 reloc_type
= BFD_RELOC_386_GOTPC
;
7224 i
.op
[n
].imms
->X_add_number
+= add
;
7226 else if (reloc_type
== BFD_RELOC_64
)
7227 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7229 /* Don't do the adjustment for x86-64, as there
7230 the pcrel addressing is relative to the _next_
7231 insn, and that is taken care of in other code. */
7232 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7234 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7235 i
.op
[n
].disps
, pcrel
, reloc_type
);
7242 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7247 for (n
= 0; n
< i
.operands
; n
++)
7249 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7250 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7253 if (operand_type_check (i
.types
[n
], imm
))
7255 if (i
.op
[n
].imms
->X_op
== O_constant
)
7257 int size
= imm_size (n
);
7260 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7262 p
= frag_more (size
);
7263 md_number_to_chars (p
, val
, size
);
7267 /* Not absolute_section.
7268 Need a 32-bit fixup (don't support 8bit
7269 non-absolute imms). Try to support other
7271 enum bfd_reloc_code_real reloc_type
;
7272 int size
= imm_size (n
);
7275 if (i
.types
[n
].bitfield
.imm32s
7276 && (i
.suffix
== QWORD_MNEM_SUFFIX
7277 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7282 p
= frag_more (size
);
7283 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7285 /* This is tough to explain. We end up with this one if we
7286 * have operands that look like
7287 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7288 * obtain the absolute address of the GOT, and it is strongly
7289 * preferable from a performance point of view to avoid using
7290 * a runtime relocation for this. The actual sequence of
7291 * instructions often look something like:
7296 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7298 * The call and pop essentially return the absolute address
7299 * of the label .L66 and store it in %ebx. The linker itself
7300 * will ultimately change the first operand of the addl so
7301 * that %ebx points to the GOT, but to keep things simple, the
7302 * .o file must have this operand set so that it generates not
7303 * the absolute address of .L66, but the absolute address of
7304 * itself. This allows the linker itself simply treat a GOTPC
7305 * relocation as asking for a pcrel offset to the GOT to be
7306 * added in, and the addend of the relocation is stored in the
7307 * operand field for the instruction itself.
7309 * Our job here is to fix the operand so that it would add
7310 * the correct offset so that %ebx would point to itself. The
7311 * thing that is tricky is that .-.L66 will point to the
7312 * beginning of the instruction, so we need to further modify
7313 * the operand so that it will point to itself. There are
7314 * other cases where you have something like:
7316 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7318 * and here no correction would be required. Internally in
7319 * the assembler we treat operands of this form as not being
7320 * pcrel since the '.' is explicitly mentioned, and I wonder
7321 * whether it would simplify matters to do it this way. Who
7322 * knows. In earlier versions of the PIC patches, the
7323 * pcrel_adjust field was used to store the correction, but
7324 * since the expression is not pcrel, I felt it would be
7325 * confusing to do it this way. */
7327 if ((reloc_type
== BFD_RELOC_32
7328 || reloc_type
== BFD_RELOC_X86_64_32S
7329 || reloc_type
== BFD_RELOC_64
)
7331 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7332 && (i
.op
[n
].imms
->X_op
== O_symbol
7333 || (i
.op
[n
].imms
->X_op
== O_add
7334 && ((symbol_get_value_expression
7335 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7340 if (insn_start_frag
== frag_now
)
7341 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7346 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7347 for (fr
= insn_start_frag
->fr_next
;
7348 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7350 add
+= p
- frag_now
->fr_literal
;
7354 reloc_type
= BFD_RELOC_386_GOTPC
;
7356 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7358 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7359 i
.op
[n
].imms
->X_add_number
+= add
;
7361 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7362 i
.op
[n
].imms
, 0, reloc_type
);
7368 /* x86_cons_fix_new is called via the expression parsing code when a
7369 reloc is needed. We use this hook to get the correct .got reloc. */
7370 static int cons_sign
= -1;
7373 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7374 expressionS
*exp
, bfd_reloc_code_real_type r
)
7376 r
= reloc (len
, 0, cons_sign
, r
);
7379 if (exp
->X_op
== O_secrel
)
7381 exp
->X_op
= O_symbol
;
7382 r
= BFD_RELOC_32_SECREL
;
7386 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7389 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7390 purpose of the `.dc.a' internal pseudo-op. */
7393 x86_address_bytes (void)
7395 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7397 return stdoutput
->arch_info
->bits_per_address
/ 8;
7400 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7402 # define lex_got(reloc, adjust, types) NULL
7404 /* Parse operands of the form
7405 <symbol>@GOTOFF+<nnn>
7406 and similar .plt or .got references.
7408 If we find one, set up the correct relocation in RELOC and copy the
7409 input string, minus the `@GOTOFF' into a malloc'd buffer for
7410 parsing by the calling routine. Return this buffer, and if ADJUST
7411 is non-null set it to the length of the string we removed from the
7412 input line. Otherwise return NULL. */
7414 lex_got (enum bfd_reloc_code_real
*rel
,
7416 i386_operand_type
*types
)
7418 /* Some of the relocations depend on the size of what field is to
7419 be relocated. But in our callers i386_immediate and i386_displacement
7420 we don't yet know the operand size (this will be set by insn
7421 matching). Hence we record the word32 relocation here,
7422 and adjust the reloc according to the real size in reloc(). */
7423 static const struct {
7426 const enum bfd_reloc_code_real rel
[2];
7427 const i386_operand_type types64
;
7429 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7430 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7432 OPERAND_TYPE_IMM32_64
},
7434 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7435 BFD_RELOC_X86_64_PLTOFF64
},
7436 OPERAND_TYPE_IMM64
},
7437 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7438 BFD_RELOC_X86_64_PLT32
},
7439 OPERAND_TYPE_IMM32_32S_DISP32
},
7440 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7441 BFD_RELOC_X86_64_GOTPLT64
},
7442 OPERAND_TYPE_IMM64_DISP64
},
7443 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7444 BFD_RELOC_X86_64_GOTOFF64
},
7445 OPERAND_TYPE_IMM64_DISP64
},
7446 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7447 BFD_RELOC_X86_64_GOTPCREL
},
7448 OPERAND_TYPE_IMM32_32S_DISP32
},
7449 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7450 BFD_RELOC_X86_64_TLSGD
},
7451 OPERAND_TYPE_IMM32_32S_DISP32
},
7452 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7453 _dummy_first_bfd_reloc_code_real
},
7454 OPERAND_TYPE_NONE
},
7455 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7456 BFD_RELOC_X86_64_TLSLD
},
7457 OPERAND_TYPE_IMM32_32S_DISP32
},
7458 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7459 BFD_RELOC_X86_64_GOTTPOFF
},
7460 OPERAND_TYPE_IMM32_32S_DISP32
},
7461 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7462 BFD_RELOC_X86_64_TPOFF32
},
7463 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7464 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7465 _dummy_first_bfd_reloc_code_real
},
7466 OPERAND_TYPE_NONE
},
7467 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7468 BFD_RELOC_X86_64_DTPOFF32
},
7469 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7470 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7471 _dummy_first_bfd_reloc_code_real
},
7472 OPERAND_TYPE_NONE
},
7473 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7474 _dummy_first_bfd_reloc_code_real
},
7475 OPERAND_TYPE_NONE
},
7476 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7477 BFD_RELOC_X86_64_GOT32
},
7478 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7479 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7480 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7481 OPERAND_TYPE_IMM32_32S_DISP32
},
7482 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7483 BFD_RELOC_X86_64_TLSDESC_CALL
},
7484 OPERAND_TYPE_IMM32_32S_DISP32
},
7489 #if defined (OBJ_MAYBE_ELF)
7494 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7495 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7498 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7500 int len
= gotrel
[j
].len
;
7501 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7503 if (gotrel
[j
].rel
[object_64bit
] != 0)
7506 char *tmpbuf
, *past_reloc
;
7508 *rel
= gotrel
[j
].rel
[object_64bit
];
7512 if (flag_code
!= CODE_64BIT
)
7514 types
->bitfield
.imm32
= 1;
7515 types
->bitfield
.disp32
= 1;
7518 *types
= gotrel
[j
].types64
;
7521 if (j
!= 0 && GOT_symbol
== NULL
)
7522 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7524 /* The length of the first part of our input line. */
7525 first
= cp
- input_line_pointer
;
7527 /* The second part goes from after the reloc token until
7528 (and including) an end_of_line char or comma. */
7529 past_reloc
= cp
+ 1 + len
;
7531 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7533 second
= cp
+ 1 - past_reloc
;
7535 /* Allocate and copy string. The trailing NUL shouldn't
7536 be necessary, but be safe. */
7537 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7538 memcpy (tmpbuf
, input_line_pointer
, first
);
7539 if (second
!= 0 && *past_reloc
!= ' ')
7540 /* Replace the relocation token with ' ', so that
7541 errors like foo@GOTOFF1 will be detected. */
7542 tmpbuf
[first
++] = ' ';
7544 /* Increment length by 1 if the relocation token is
7549 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7550 tmpbuf
[first
+ second
] = '\0';
7554 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7555 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7560 /* Might be a symbol version string. Don't as_bad here. */
7569 /* Parse operands of the form
7570 <symbol>@SECREL32+<nnn>
7572 If we find one, set up the correct relocation in RELOC and copy the
7573 input string, minus the `@SECREL32' into a malloc'd buffer for
7574 parsing by the calling routine. Return this buffer, and if ADJUST
7575 is non-null set it to the length of the string we removed from the
7576 input line. Otherwise return NULL.
7578 This function is copied from the ELF version above adjusted for PE targets. */
7581 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7582 int *adjust ATTRIBUTE_UNUSED
,
7583 i386_operand_type
*types
)
7589 const enum bfd_reloc_code_real rel
[2];
7590 const i386_operand_type types64
;
7594 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7595 BFD_RELOC_32_SECREL
},
7596 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7602 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7603 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7606 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7608 int len
= gotrel
[j
].len
;
7610 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7612 if (gotrel
[j
].rel
[object_64bit
] != 0)
7615 char *tmpbuf
, *past_reloc
;
7617 *rel
= gotrel
[j
].rel
[object_64bit
];
7623 if (flag_code
!= CODE_64BIT
)
7625 types
->bitfield
.imm32
= 1;
7626 types
->bitfield
.disp32
= 1;
7629 *types
= gotrel
[j
].types64
;
7632 /* The length of the first part of our input line. */
7633 first
= cp
- input_line_pointer
;
7635 /* The second part goes from after the reloc token until
7636 (and including) an end_of_line char or comma. */
7637 past_reloc
= cp
+ 1 + len
;
7639 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7641 second
= cp
+ 1 - past_reloc
;
7643 /* Allocate and copy string. The trailing NUL shouldn't
7644 be necessary, but be safe. */
7645 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7646 memcpy (tmpbuf
, input_line_pointer
, first
);
7647 if (second
!= 0 && *past_reloc
!= ' ')
7648 /* Replace the relocation token with ' ', so that
7649 errors like foo@SECLREL321 will be detected. */
7650 tmpbuf
[first
++] = ' ';
7651 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7652 tmpbuf
[first
+ second
] = '\0';
7656 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7657 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7662 /* Might be a symbol version string. Don't as_bad here. */
7668 bfd_reloc_code_real_type
7669 x86_cons (expressionS
*exp
, int size
)
7671 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7673 intel_syntax
= -intel_syntax
;
7676 if (size
== 4 || (object_64bit
&& size
== 8))
7678 /* Handle @GOTOFF and the like in an expression. */
7680 char *gotfree_input_line
;
7683 save
= input_line_pointer
;
7684 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7685 if (gotfree_input_line
)
7686 input_line_pointer
= gotfree_input_line
;
7690 if (gotfree_input_line
)
7692 /* expression () has merrily parsed up to the end of line,
7693 or a comma - in the wrong buffer. Transfer how far
7694 input_line_pointer has moved to the right buffer. */
7695 input_line_pointer
= (save
7696 + (input_line_pointer
- gotfree_input_line
)
7698 free (gotfree_input_line
);
7699 if (exp
->X_op
== O_constant
7700 || exp
->X_op
== O_absent
7701 || exp
->X_op
== O_illegal
7702 || exp
->X_op
== O_register
7703 || exp
->X_op
== O_big
)
7705 char c
= *input_line_pointer
;
7706 *input_line_pointer
= 0;
7707 as_bad (_("missing or invalid expression `%s'"), save
);
7708 *input_line_pointer
= c
;
7715 intel_syntax
= -intel_syntax
;
7718 i386_intel_simplify (exp
);
7724 signed_cons (int size
)
7726 if (flag_code
== CODE_64BIT
)
7734 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7741 if (exp
.X_op
== O_symbol
)
7742 exp
.X_op
= O_secrel
;
7744 emit_expr (&exp
, 4);
7746 while (*input_line_pointer
++ == ',');
7748 input_line_pointer
--;
7749 demand_empty_rest_of_line ();
7753 /* Handle Vector operations. */
7756 check_VecOperations (char *op_string
, char *op_end
)
7758 const reg_entry
*mask
;
7763 && (op_end
== NULL
|| op_string
< op_end
))
7766 if (*op_string
== '{')
7770 /* Check broadcasts. */
7771 if (strncmp (op_string
, "1to", 3) == 0)
7776 goto duplicated_vec_op
;
7779 if (*op_string
== '8')
7780 bcst_type
= BROADCAST_1TO8
;
7781 else if (*op_string
== '4')
7782 bcst_type
= BROADCAST_1TO4
;
7783 else if (*op_string
== '2')
7784 bcst_type
= BROADCAST_1TO2
;
7785 else if (*op_string
== '1'
7786 && *(op_string
+1) == '6')
7788 bcst_type
= BROADCAST_1TO16
;
7793 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7798 broadcast_op
.type
= bcst_type
;
7799 broadcast_op
.operand
= this_operand
;
7800 i
.broadcast
= &broadcast_op
;
7802 /* Check masking operation. */
7803 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7805 /* k0 can't be used for write mask. */
7806 if (mask
->reg_num
== 0)
7808 as_bad (_("`%s' can't be used for write mask"),
7815 mask_op
.mask
= mask
;
7816 mask_op
.zeroing
= 0;
7817 mask_op
.operand
= this_operand
;
7823 goto duplicated_vec_op
;
7825 i
.mask
->mask
= mask
;
7827 /* Only "{z}" is allowed here. No need to check
7828 zeroing mask explicitly. */
7829 if (i
.mask
->operand
!= this_operand
)
7831 as_bad (_("invalid write mask `%s'"), saved
);
7838 /* Check zeroing-flag for masking operation. */
7839 else if (*op_string
== 'z')
7843 mask_op
.mask
= NULL
;
7844 mask_op
.zeroing
= 1;
7845 mask_op
.operand
= this_operand
;
7850 if (i
.mask
->zeroing
)
7853 as_bad (_("duplicated `%s'"), saved
);
7857 i
.mask
->zeroing
= 1;
7859 /* Only "{%k}" is allowed here. No need to check mask
7860 register explicitly. */
7861 if (i
.mask
->operand
!= this_operand
)
7863 as_bad (_("invalid zeroing-masking `%s'"),
7872 goto unknown_vec_op
;
7874 if (*op_string
!= '}')
7876 as_bad (_("missing `}' in `%s'"), saved
);
7883 /* We don't know this one. */
7884 as_bad (_("unknown vector operation: `%s'"), saved
);
7892 i386_immediate (char *imm_start
)
7894 char *save_input_line_pointer
;
7895 char *gotfree_input_line
;
7898 i386_operand_type types
;
7900 operand_type_set (&types
, ~0);
7902 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7904 as_bad (_("at most %d immediate operands are allowed"),
7905 MAX_IMMEDIATE_OPERANDS
);
7909 exp
= &im_expressions
[i
.imm_operands
++];
7910 i
.op
[this_operand
].imms
= exp
;
7912 if (is_space_char (*imm_start
))
7915 save_input_line_pointer
= input_line_pointer
;
7916 input_line_pointer
= imm_start
;
7918 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7919 if (gotfree_input_line
)
7920 input_line_pointer
= gotfree_input_line
;
7922 exp_seg
= expression (exp
);
7926 /* Handle vector operations. */
7927 if (*input_line_pointer
== '{')
7929 input_line_pointer
= check_VecOperations (input_line_pointer
,
7931 if (input_line_pointer
== NULL
)
7935 if (*input_line_pointer
)
7936 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7938 input_line_pointer
= save_input_line_pointer
;
7939 if (gotfree_input_line
)
7941 free (gotfree_input_line
);
7943 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7944 exp
->X_op
= O_illegal
;
7947 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7951 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7952 i386_operand_type types
, const char *imm_start
)
7954 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7957 as_bad (_("missing or invalid immediate expression `%s'"),
7961 else if (exp
->X_op
== O_constant
)
7963 /* Size it properly later. */
7964 i
.types
[this_operand
].bitfield
.imm64
= 1;
7965 /* If not 64bit, sign extend val. */
7966 if (flag_code
!= CODE_64BIT
7967 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7969 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7971 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7972 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7973 && exp_seg
!= absolute_section
7974 && exp_seg
!= text_section
7975 && exp_seg
!= data_section
7976 && exp_seg
!= bss_section
7977 && exp_seg
!= undefined_section
7978 && !bfd_is_com_section (exp_seg
))
7980 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7984 else if (!intel_syntax
&& exp_seg
== reg_section
)
7987 as_bad (_("illegal immediate register operand %s"), imm_start
);
7992 /* This is an address. The size of the address will be
7993 determined later, depending on destination register,
7994 suffix, or the default for the section. */
7995 i
.types
[this_operand
].bitfield
.imm8
= 1;
7996 i
.types
[this_operand
].bitfield
.imm16
= 1;
7997 i
.types
[this_operand
].bitfield
.imm32
= 1;
7998 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7999 i
.types
[this_operand
].bitfield
.imm64
= 1;
8000 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8008 i386_scale (char *scale
)
8011 char *save
= input_line_pointer
;
8013 input_line_pointer
= scale
;
8014 val
= get_absolute_expression ();
8019 i
.log2_scale_factor
= 0;
8022 i
.log2_scale_factor
= 1;
8025 i
.log2_scale_factor
= 2;
8028 i
.log2_scale_factor
= 3;
8032 char sep
= *input_line_pointer
;
8034 *input_line_pointer
= '\0';
8035 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8037 *input_line_pointer
= sep
;
8038 input_line_pointer
= save
;
8042 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8044 as_warn (_("scale factor of %d without an index register"),
8045 1 << i
.log2_scale_factor
);
8046 i
.log2_scale_factor
= 0;
8048 scale
= input_line_pointer
;
8049 input_line_pointer
= save
;
8054 i386_displacement (char *disp_start
, char *disp_end
)
8058 char *save_input_line_pointer
;
8059 char *gotfree_input_line
;
8061 i386_operand_type bigdisp
, types
= anydisp
;
8064 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8066 as_bad (_("at most %d displacement operands are allowed"),
8067 MAX_MEMORY_OPERANDS
);
8071 operand_type_set (&bigdisp
, 0);
8072 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8073 || (!current_templates
->start
->opcode_modifier
.jump
8074 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8076 bigdisp
.bitfield
.disp32
= 1;
8077 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8078 if (flag_code
== CODE_64BIT
)
8082 bigdisp
.bitfield
.disp32s
= 1;
8083 bigdisp
.bitfield
.disp64
= 1;
8086 else if ((flag_code
== CODE_16BIT
) ^ override
)
8088 bigdisp
.bitfield
.disp32
= 0;
8089 bigdisp
.bitfield
.disp16
= 1;
8094 /* For PC-relative branches, the width of the displacement
8095 is dependent upon data size, not address size. */
8096 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8097 if (flag_code
== CODE_64BIT
)
8099 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8100 bigdisp
.bitfield
.disp16
= 1;
8103 bigdisp
.bitfield
.disp32
= 1;
8104 bigdisp
.bitfield
.disp32s
= 1;
8110 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8112 : LONG_MNEM_SUFFIX
));
8113 bigdisp
.bitfield
.disp32
= 1;
8114 if ((flag_code
== CODE_16BIT
) ^ override
)
8116 bigdisp
.bitfield
.disp32
= 0;
8117 bigdisp
.bitfield
.disp16
= 1;
8121 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8124 exp
= &disp_expressions
[i
.disp_operands
];
8125 i
.op
[this_operand
].disps
= exp
;
8127 save_input_line_pointer
= input_line_pointer
;
8128 input_line_pointer
= disp_start
;
8129 END_STRING_AND_SAVE (disp_end
);
8131 #ifndef GCC_ASM_O_HACK
8132 #define GCC_ASM_O_HACK 0
8135 END_STRING_AND_SAVE (disp_end
+ 1);
8136 if (i
.types
[this_operand
].bitfield
.baseIndex
8137 && displacement_string_end
[-1] == '+')
8139 /* This hack is to avoid a warning when using the "o"
8140 constraint within gcc asm statements.
8143 #define _set_tssldt_desc(n,addr,limit,type) \
8144 __asm__ __volatile__ ( \
8146 "movw %w1,2+%0\n\t" \
8148 "movb %b1,4+%0\n\t" \
8149 "movb %4,5+%0\n\t" \
8150 "movb $0,6+%0\n\t" \
8151 "movb %h1,7+%0\n\t" \
8153 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8155 This works great except that the output assembler ends
8156 up looking a bit weird if it turns out that there is
8157 no offset. You end up producing code that looks like:
8170 So here we provide the missing zero. */
8172 *displacement_string_end
= '0';
8175 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8176 if (gotfree_input_line
)
8177 input_line_pointer
= gotfree_input_line
;
8179 exp_seg
= expression (exp
);
8182 if (*input_line_pointer
)
8183 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8185 RESTORE_END_STRING (disp_end
+ 1);
8187 input_line_pointer
= save_input_line_pointer
;
8188 if (gotfree_input_line
)
8190 free (gotfree_input_line
);
8192 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8193 exp
->X_op
= O_illegal
;
8196 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8198 RESTORE_END_STRING (disp_end
);
8204 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8205 i386_operand_type types
, const char *disp_start
)
8207 i386_operand_type bigdisp
;
8210 /* We do this to make sure that the section symbol is in
8211 the symbol table. We will ultimately change the relocation
8212 to be relative to the beginning of the section. */
8213 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8214 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8215 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8217 if (exp
->X_op
!= O_symbol
)
8220 if (S_IS_LOCAL (exp
->X_add_symbol
)
8221 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8222 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8223 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8224 exp
->X_op
= O_subtract
;
8225 exp
->X_op_symbol
= GOT_symbol
;
8226 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8227 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8228 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8229 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8231 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8234 else if (exp
->X_op
== O_absent
8235 || exp
->X_op
== O_illegal
8236 || exp
->X_op
== O_big
)
8239 as_bad (_("missing or invalid displacement expression `%s'"),
8244 else if (flag_code
== CODE_64BIT
8245 && !i
.prefix
[ADDR_PREFIX
]
8246 && exp
->X_op
== O_constant
)
8248 /* Since displacement is signed extended to 64bit, don't allow
8249 disp32 and turn off disp32s if they are out of range. */
8250 i
.types
[this_operand
].bitfield
.disp32
= 0;
8251 if (!fits_in_signed_long (exp
->X_add_number
))
8253 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8254 if (i
.types
[this_operand
].bitfield
.baseindex
)
8256 as_bad (_("0x%lx out range of signed 32bit displacement"),
8257 (long) exp
->X_add_number
);
8263 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8264 else if (exp
->X_op
!= O_constant
8265 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8266 && exp_seg
!= absolute_section
8267 && exp_seg
!= text_section
8268 && exp_seg
!= data_section
8269 && exp_seg
!= bss_section
8270 && exp_seg
!= undefined_section
8271 && !bfd_is_com_section (exp_seg
))
8273 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8278 /* Check if this is a displacement only operand. */
8279 bigdisp
= i
.types
[this_operand
];
8280 bigdisp
.bitfield
.disp8
= 0;
8281 bigdisp
.bitfield
.disp16
= 0;
8282 bigdisp
.bitfield
.disp32
= 0;
8283 bigdisp
.bitfield
.disp32s
= 0;
8284 bigdisp
.bitfield
.disp64
= 0;
8285 if (operand_type_all_zero (&bigdisp
))
8286 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8292 /* Make sure the memory operand we've been dealt is valid.
8293 Return 1 on success, 0 on a failure. */
8296 i386_index_check (const char *operand_string
)
8298 const char *kind
= "base/index";
8299 enum flag_code addr_mode
;
8301 if (i
.prefix
[ADDR_PREFIX
])
8302 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8305 addr_mode
= flag_code
;
8307 #if INFER_ADDR_PREFIX
8308 if (i
.mem_operands
== 0)
8310 /* Infer address prefix from the first memory operand. */
8311 const reg_entry
*addr_reg
= i
.base_reg
;
8313 if (addr_reg
== NULL
)
8314 addr_reg
= i
.index_reg
;
8318 if (addr_reg
->reg_num
== RegEip
8319 || addr_reg
->reg_num
== RegEiz
8320 || addr_reg
->reg_type
.bitfield
.reg32
)
8321 addr_mode
= CODE_32BIT
;
8322 else if (flag_code
!= CODE_64BIT
8323 && addr_reg
->reg_type
.bitfield
.reg16
)
8324 addr_mode
= CODE_16BIT
;
8326 if (addr_mode
!= flag_code
)
8328 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8330 /* Change the size of any displacement too. At most one
8331 of Disp16 or Disp32 is set.
8332 FIXME. There doesn't seem to be any real need for
8333 separate Disp16 and Disp32 flags. The same goes for
8334 Imm16 and Imm32. Removing them would probably clean
8335 up the code quite a lot. */
8336 if (flag_code
!= CODE_64BIT
8337 && (i
.types
[this_operand
].bitfield
.disp16
8338 || i
.types
[this_operand
].bitfield
.disp32
))
8339 i
.types
[this_operand
]
8340 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8347 if (current_templates
->start
->opcode_modifier
.isstring
8348 && !current_templates
->start
->opcode_modifier
.immext
8349 && (current_templates
->end
[-1].opcode_modifier
.isstring
8352 /* Memory operands of string insns are special in that they only allow
8353 a single register (rDI, rSI, or rBX) as their memory address. */
8354 const reg_entry
*expected_reg
;
8355 static const char *di_si
[][2] =
8361 static const char *bx
[] = { "ebx", "bx", "rbx" };
8363 kind
= "string address";
8365 if (current_templates
->start
->opcode_modifier
.w
)
8367 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8369 if (!type
.bitfield
.baseindex
8370 || ((!i
.mem_operands
!= !intel_syntax
)
8371 && current_templates
->end
[-1].operand_types
[1]
8372 .bitfield
.baseindex
))
8373 type
= current_templates
->end
[-1].operand_types
[1];
8374 expected_reg
= hash_find (reg_hash
,
8375 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8379 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8381 if (i
.base_reg
!= expected_reg
8383 || operand_type_check (i
.types
[this_operand
], disp
))
8385 /* The second memory operand must have the same size as
8389 && !((addr_mode
== CODE_64BIT
8390 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8391 || (addr_mode
== CODE_32BIT
8392 ? i
.base_reg
->reg_type
.bitfield
.reg32
8393 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8396 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8398 intel_syntax
? '[' : '(',
8400 expected_reg
->reg_name
,
8401 intel_syntax
? ']' : ')');
8408 as_bad (_("`%s' is not a valid %s expression"),
8409 operand_string
, kind
);
8414 if (addr_mode
!= CODE_16BIT
)
8416 /* 32-bit/64-bit checks. */
8418 && (addr_mode
== CODE_64BIT
8419 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8420 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8422 || (i
.base_reg
->reg_num
8423 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8425 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8426 && !i
.index_reg
->reg_type
.bitfield
.regymm
8427 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8428 && ((addr_mode
== CODE_64BIT
8429 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8430 || i
.index_reg
->reg_num
== RegRiz
)
8431 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8432 || i
.index_reg
->reg_num
== RegEiz
))
8433 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8438 /* 16-bit checks. */
8440 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8441 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8443 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8444 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8446 && i
.base_reg
->reg_num
< 6
8447 && i
.index_reg
->reg_num
>= 6
8448 && i
.log2_scale_factor
== 0))))
8455 /* Handle vector immediates. */
8458 RC_SAE_immediate (const char *imm_start
)
8460 unsigned int match_found
, j
;
8461 const char *pstr
= imm_start
;
8469 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8471 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8475 rc_op
.type
= RC_NamesTable
[j
].type
;
8476 rc_op
.operand
= this_operand
;
8477 i
.rounding
= &rc_op
;
8481 as_bad (_("duplicated `%s'"), imm_start
);
8484 pstr
+= RC_NamesTable
[j
].len
;
8494 as_bad (_("Missing '}': '%s'"), imm_start
);
8497 /* RC/SAE immediate string should contain nothing more. */;
8500 as_bad (_("Junk after '}': '%s'"), imm_start
);
8504 exp
= &im_expressions
[i
.imm_operands
++];
8505 i
.op
[this_operand
].imms
= exp
;
8507 exp
->X_op
= O_constant
;
8508 exp
->X_add_number
= 0;
8509 exp
->X_add_symbol
= (symbolS
*) 0;
8510 exp
->X_op_symbol
= (symbolS
*) 0;
8512 i
.types
[this_operand
].bitfield
.imm8
= 1;
8516 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8520 i386_att_operand (char *operand_string
)
8524 char *op_string
= operand_string
;
8526 if (is_space_char (*op_string
))
8529 /* We check for an absolute prefix (differentiating,
8530 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8531 if (*op_string
== ABSOLUTE_PREFIX
)
8534 if (is_space_char (*op_string
))
8536 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8539 /* Check if operand is a register. */
8540 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8542 i386_operand_type temp
;
8544 /* Check for a segment override by searching for ':' after a
8545 segment register. */
8547 if (is_space_char (*op_string
))
8549 if (*op_string
== ':'
8550 && (r
->reg_type
.bitfield
.sreg2
8551 || r
->reg_type
.bitfield
.sreg3
))
8556 i
.seg
[i
.mem_operands
] = &es
;
8559 i
.seg
[i
.mem_operands
] = &cs
;
8562 i
.seg
[i
.mem_operands
] = &ss
;
8565 i
.seg
[i
.mem_operands
] = &ds
;
8568 i
.seg
[i
.mem_operands
] = &fs
;
8571 i
.seg
[i
.mem_operands
] = &gs
;
8575 /* Skip the ':' and whitespace. */
8577 if (is_space_char (*op_string
))
8580 if (!is_digit_char (*op_string
)
8581 && !is_identifier_char (*op_string
)
8582 && *op_string
!= '('
8583 && *op_string
!= ABSOLUTE_PREFIX
)
8585 as_bad (_("bad memory operand `%s'"), op_string
);
8588 /* Handle case of %es:*foo. */
8589 if (*op_string
== ABSOLUTE_PREFIX
)
8592 if (is_space_char (*op_string
))
8594 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8596 goto do_memory_reference
;
8599 /* Handle vector operations. */
8600 if (*op_string
== '{')
8602 op_string
= check_VecOperations (op_string
, NULL
);
8603 if (op_string
== NULL
)
8609 as_bad (_("junk `%s' after register"), op_string
);
8613 temp
.bitfield
.baseindex
= 0;
8614 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8616 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8617 i
.op
[this_operand
].regs
= r
;
8620 else if (*op_string
== REGISTER_PREFIX
)
8622 as_bad (_("bad register name `%s'"), op_string
);
8625 else if (*op_string
== IMMEDIATE_PREFIX
)
8628 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8630 as_bad (_("immediate operand illegal with absolute jump"));
8633 if (!i386_immediate (op_string
))
8636 else if (RC_SAE_immediate (operand_string
))
8638 /* If it is a RC or SAE immediate, do nothing. */
8641 else if (is_digit_char (*op_string
)
8642 || is_identifier_char (*op_string
)
8643 || *op_string
== '"'
8644 || *op_string
== '(')
8646 /* This is a memory reference of some sort. */
8649 /* Start and end of displacement string expression (if found). */
8650 char *displacement_string_start
;
8651 char *displacement_string_end
;
8654 do_memory_reference
:
8655 if ((i
.mem_operands
== 1
8656 && !current_templates
->start
->opcode_modifier
.isstring
)
8657 || i
.mem_operands
== 2)
8659 as_bad (_("too many memory references for `%s'"),
8660 current_templates
->start
->name
);
8664 /* Check for base index form. We detect the base index form by
8665 looking for an ')' at the end of the operand, searching
8666 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8668 base_string
= op_string
+ strlen (op_string
);
8670 /* Handle vector operations. */
8671 vop_start
= strchr (op_string
, '{');
8672 if (vop_start
&& vop_start
< base_string
)
8674 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8676 base_string
= vop_start
;
8680 if (is_space_char (*base_string
))
8683 /* If we only have a displacement, set-up for it to be parsed later. */
8684 displacement_string_start
= op_string
;
8685 displacement_string_end
= base_string
+ 1;
8687 if (*base_string
== ')')
8690 unsigned int parens_balanced
= 1;
8691 /* We've already checked that the number of left & right ()'s are
8692 equal, so this loop will not be infinite. */
8696 if (*base_string
== ')')
8698 if (*base_string
== '(')
8701 while (parens_balanced
);
8703 temp_string
= base_string
;
8705 /* Skip past '(' and whitespace. */
8707 if (is_space_char (*base_string
))
8710 if (*base_string
== ','
8711 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8714 displacement_string_end
= temp_string
;
8716 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8720 base_string
= end_op
;
8721 if (is_space_char (*base_string
))
8725 /* There may be an index reg or scale factor here. */
8726 if (*base_string
== ',')
8729 if (is_space_char (*base_string
))
8732 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8735 base_string
= end_op
;
8736 if (is_space_char (*base_string
))
8738 if (*base_string
== ',')
8741 if (is_space_char (*base_string
))
8744 else if (*base_string
!= ')')
8746 as_bad (_("expecting `,' or `)' "
8747 "after index register in `%s'"),
8752 else if (*base_string
== REGISTER_PREFIX
)
8754 end_op
= strchr (base_string
, ',');
8757 as_bad (_("bad register name `%s'"), base_string
);
8761 /* Check for scale factor. */
8762 if (*base_string
!= ')')
8764 char *end_scale
= i386_scale (base_string
);
8769 base_string
= end_scale
;
8770 if (is_space_char (*base_string
))
8772 if (*base_string
!= ')')
8774 as_bad (_("expecting `)' "
8775 "after scale factor in `%s'"),
8780 else if (!i
.index_reg
)
8782 as_bad (_("expecting index register or scale factor "
8783 "after `,'; got '%c'"),
8788 else if (*base_string
!= ')')
8790 as_bad (_("expecting `,' or `)' "
8791 "after base register in `%s'"),
8796 else if (*base_string
== REGISTER_PREFIX
)
8798 end_op
= strchr (base_string
, ',');
8801 as_bad (_("bad register name `%s'"), base_string
);
8806 /* If there's an expression beginning the operand, parse it,
8807 assuming displacement_string_start and
8808 displacement_string_end are meaningful. */
8809 if (displacement_string_start
!= displacement_string_end
)
8811 if (!i386_displacement (displacement_string_start
,
8812 displacement_string_end
))
8816 /* Special case for (%dx) while doing input/output op. */
8818 && operand_type_equal (&i
.base_reg
->reg_type
,
8819 ®16_inoutportreg
)
8821 && i
.log2_scale_factor
== 0
8822 && i
.seg
[i
.mem_operands
] == 0
8823 && !operand_type_check (i
.types
[this_operand
], disp
))
8825 i
.types
[this_operand
] = inoutportreg
;
8829 if (i386_index_check (operand_string
) == 0)
8831 i
.types
[this_operand
].bitfield
.mem
= 1;
8836 /* It's not a memory operand; argh! */
8837 as_bad (_("invalid char %s beginning operand %d `%s'"),
8838 output_invalid (*op_string
),
8843 return 1; /* Normal return. */
8846 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8847 that an rs_machine_dependent frag may reach. */
8850 i386_frag_max_var (fragS
*frag
)
8852 /* The only relaxable frags are for jumps.
8853 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8854 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8855 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8860 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8862 /* STT_GNU_IFUNC symbol must go through PLT. */
8863 if ((symbol_get_bfdsym (fr_symbol
)->flags
8864 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8867 if (!S_IS_EXTERNAL (fr_symbol
))
8868 /* Symbol may be weak or local. */
8869 return !S_IS_WEAK (fr_symbol
);
8871 /* Global symbols with non-default visibility can't be preempted. */
8872 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8875 if (fr_var
!= NO_RELOC
)
8876 switch ((enum bfd_reloc_code_real
) fr_var
)
8878 case BFD_RELOC_386_PLT32
:
8879 case BFD_RELOC_X86_64_PLT32
:
8880 /* Symbol with PLT relocatin may be preempted. */
8886 /* Global symbols with default visibility in a shared library may be
8887 preempted by another definition. */
8892 /* md_estimate_size_before_relax()
8894 Called just before relax() for rs_machine_dependent frags. The x86
8895 assembler uses these frags to handle variable size jump
8898 Any symbol that is now undefined will not become defined.
8899 Return the correct fr_subtype in the frag.
8900 Return the initial "guess for variable size of frag" to caller.
8901 The guess is actually the growth beyond the fixed part. Whatever
8902 we do to grow the fixed or variable part contributes to our
8906 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8908 /* We've already got fragP->fr_subtype right; all we have to do is
8909 check for un-relaxable symbols. On an ELF system, we can't relax
8910 an externally visible symbol, because it may be overridden by a
8912 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8915 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8918 #if defined (OBJ_COFF) && defined (TE_PE)
8919 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8920 && S_IS_WEAK (fragP
->fr_symbol
))
8924 /* Symbol is undefined in this segment, or we need to keep a
8925 reloc so that weak symbols can be overridden. */
8926 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8927 enum bfd_reloc_code_real reloc_type
;
8928 unsigned char *opcode
;
8931 if (fragP
->fr_var
!= NO_RELOC
)
8932 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8934 reloc_type
= BFD_RELOC_16_PCREL
;
8936 reloc_type
= BFD_RELOC_32_PCREL
;
8938 old_fr_fix
= fragP
->fr_fix
;
8939 opcode
= (unsigned char *) fragP
->fr_opcode
;
8941 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8944 /* Make jmp (0xeb) a (d)word displacement jump. */
8946 fragP
->fr_fix
+= size
;
8947 fix_new (fragP
, old_fr_fix
, size
,
8949 fragP
->fr_offset
, 1,
8955 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8957 /* Negate the condition, and branch past an
8958 unconditional jump. */
8961 /* Insert an unconditional jump. */
8963 /* We added two extra opcode bytes, and have a two byte
8965 fragP
->fr_fix
+= 2 + 2;
8966 fix_new (fragP
, old_fr_fix
+ 2, 2,
8968 fragP
->fr_offset
, 1,
8975 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8980 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8982 fragP
->fr_offset
, 1,
8984 fixP
->fx_signed
= 1;
8988 /* This changes the byte-displacement jump 0x7N
8989 to the (d)word-displacement jump 0x0f,0x8N. */
8990 opcode
[1] = opcode
[0] + 0x10;
8991 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8992 /* We've added an opcode byte. */
8993 fragP
->fr_fix
+= 1 + size
;
8994 fix_new (fragP
, old_fr_fix
+ 1, size
,
8996 fragP
->fr_offset
, 1,
9001 BAD_CASE (fragP
->fr_subtype
);
9005 return fragP
->fr_fix
- old_fr_fix
;
9008 /* Guess size depending on current relax state. Initially the relax
9009 state will correspond to a short jump and we return 1, because
9010 the variable part of the frag (the branch offset) is one byte
9011 long. However, we can relax a section more than once and in that
9012 case we must either set fr_subtype back to the unrelaxed state,
9013 or return the value for the appropriate branch. */
9014 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9017 /* Called after relax() is finished.
9019 In: Address of frag.
9020 fr_type == rs_machine_dependent.
9021 fr_subtype is what the address relaxed to.
9023 Out: Any fixSs and constants are set up.
9024 Caller will turn frag into a ".space 0". */
9027 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9030 unsigned char *opcode
;
9031 unsigned char *where_to_put_displacement
= NULL
;
9032 offsetT target_address
;
9033 offsetT opcode_address
;
9034 unsigned int extension
= 0;
9035 offsetT displacement_from_opcode_start
;
9037 opcode
= (unsigned char *) fragP
->fr_opcode
;
9039 /* Address we want to reach in file space. */
9040 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9042 /* Address opcode resides at in file space. */
9043 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9045 /* Displacement from opcode start to fill into instruction. */
9046 displacement_from_opcode_start
= target_address
- opcode_address
;
9048 if ((fragP
->fr_subtype
& BIG
) == 0)
9050 /* Don't have to change opcode. */
9051 extension
= 1; /* 1 opcode + 1 displacement */
9052 where_to_put_displacement
= &opcode
[1];
9056 if (no_cond_jump_promotion
9057 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9058 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9059 _("long jump required"));
9061 switch (fragP
->fr_subtype
)
9063 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9064 extension
= 4; /* 1 opcode + 4 displacement */
9066 where_to_put_displacement
= &opcode
[1];
9069 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9070 extension
= 2; /* 1 opcode + 2 displacement */
9072 where_to_put_displacement
= &opcode
[1];
9075 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9076 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9077 extension
= 5; /* 2 opcode + 4 displacement */
9078 opcode
[1] = opcode
[0] + 0x10;
9079 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9080 where_to_put_displacement
= &opcode
[2];
9083 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9084 extension
= 3; /* 2 opcode + 2 displacement */
9085 opcode
[1] = opcode
[0] + 0x10;
9086 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9087 where_to_put_displacement
= &opcode
[2];
9090 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9095 where_to_put_displacement
= &opcode
[3];
9099 BAD_CASE (fragP
->fr_subtype
);
9104 /* If size if less then four we are sure that the operand fits,
9105 but if it's 4, then it could be that the displacement is larger
9107 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9109 && ((addressT
) (displacement_from_opcode_start
- extension
9110 + ((addressT
) 1 << 31))
9111 > (((addressT
) 2 << 31) - 1)))
9113 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9114 _("jump target out of range"));
9115 /* Make us emit 0. */
9116 displacement_from_opcode_start
= extension
;
9118 /* Now put displacement after opcode. */
9119 md_number_to_chars ((char *) where_to_put_displacement
,
9120 (valueT
) (displacement_from_opcode_start
- extension
),
9121 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9122 fragP
->fr_fix
+= extension
;
9125 /* Apply a fixup (fixP) to segment data, once it has been determined
9126 by our caller that we have all the info we need to fix it up.
9128 Parameter valP is the pointer to the value of the bits.
9130 On the 386, immediates, displacements, and data pointers are all in
9131 the same (little-endian) format, so we don't need to care about which
9135 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9137 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9138 valueT value
= *valP
;
9140 #if !defined (TE_Mach)
9143 switch (fixP
->fx_r_type
)
9149 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9152 case BFD_RELOC_X86_64_32S
:
9153 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9156 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9159 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9164 if (fixP
->fx_addsy
!= NULL
9165 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9166 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9167 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9168 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9169 && !use_rela_relocations
)
9171 /* This is a hack. There should be a better way to handle this.
9172 This covers for the fact that bfd_install_relocation will
9173 subtract the current location (for partial_inplace, PC relative
9174 relocations); see more below. */
9178 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9181 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9186 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9189 || (symbol_section_p (fixP
->fx_addsy
)
9190 && sym_seg
!= absolute_section
))
9191 && !generic_force_reloc (fixP
))
9193 /* Yes, we add the values in twice. This is because
9194 bfd_install_relocation subtracts them out again. I think
9195 bfd_install_relocation is broken, but I don't dare change
9197 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9201 #if defined (OBJ_COFF) && defined (TE_PE)
9202 /* For some reason, the PE format does not store a
9203 section address offset for a PC relative symbol. */
9204 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9205 || S_IS_WEAK (fixP
->fx_addsy
))
9206 value
+= md_pcrel_from (fixP
);
9209 #if defined (OBJ_COFF) && defined (TE_PE)
9210 if (fixP
->fx_addsy
!= NULL
9211 && S_IS_WEAK (fixP
->fx_addsy
)
9212 /* PR 16858: Do not modify weak function references. */
9213 && ! fixP
->fx_pcrel
)
9215 #if !defined (TE_PEP)
9216 /* For x86 PE weak function symbols are neither PC-relative
9217 nor do they set S_IS_FUNCTION. So the only reliable way
9218 to detect them is to check the flags of their containing
9220 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9221 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9225 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9229 /* Fix a few things - the dynamic linker expects certain values here,
9230 and we must not disappoint it. */
9231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9232 if (IS_ELF
&& fixP
->fx_addsy
)
9233 switch (fixP
->fx_r_type
)
9235 case BFD_RELOC_386_PLT32
:
9236 case BFD_RELOC_X86_64_PLT32
:
9237 /* Make the jump instruction point to the address of the operand. At
9238 runtime we merely add the offset to the actual PLT entry. */
9242 case BFD_RELOC_386_TLS_GD
:
9243 case BFD_RELOC_386_TLS_LDM
:
9244 case BFD_RELOC_386_TLS_IE_32
:
9245 case BFD_RELOC_386_TLS_IE
:
9246 case BFD_RELOC_386_TLS_GOTIE
:
9247 case BFD_RELOC_386_TLS_GOTDESC
:
9248 case BFD_RELOC_X86_64_TLSGD
:
9249 case BFD_RELOC_X86_64_TLSLD
:
9250 case BFD_RELOC_X86_64_GOTTPOFF
:
9251 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9252 value
= 0; /* Fully resolved at runtime. No addend. */
9254 case BFD_RELOC_386_TLS_LE
:
9255 case BFD_RELOC_386_TLS_LDO_32
:
9256 case BFD_RELOC_386_TLS_LE_32
:
9257 case BFD_RELOC_X86_64_DTPOFF32
:
9258 case BFD_RELOC_X86_64_DTPOFF64
:
9259 case BFD_RELOC_X86_64_TPOFF32
:
9260 case BFD_RELOC_X86_64_TPOFF64
:
9261 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9264 case BFD_RELOC_386_TLS_DESC_CALL
:
9265 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9266 value
= 0; /* Fully resolved at runtime. No addend. */
9267 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9271 case BFD_RELOC_386_GOT32
:
9272 case BFD_RELOC_X86_64_GOT32
:
9273 value
= 0; /* Fully resolved at runtime. No addend. */
9276 case BFD_RELOC_VTABLE_INHERIT
:
9277 case BFD_RELOC_VTABLE_ENTRY
:
9284 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9286 #endif /* !defined (TE_Mach) */
9288 /* Are we finished with this relocation now? */
9289 if (fixP
->fx_addsy
== NULL
)
9291 #if defined (OBJ_COFF) && defined (TE_PE)
9292 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9295 /* Remember value for tc_gen_reloc. */
9296 fixP
->fx_addnumber
= value
;
9297 /* Clear out the frag for now. */
9301 else if (use_rela_relocations
)
9303 fixP
->fx_no_overflow
= 1;
9304 /* Remember value for tc_gen_reloc. */
9305 fixP
->fx_addnumber
= value
;
9309 md_number_to_chars (p
, value
, fixP
->fx_size
);
9313 md_atof (int type
, char *litP
, int *sizeP
)
9315 /* This outputs the LITTLENUMs in REVERSE order;
9316 in accord with the bigendian 386. */
9317 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9320 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9323 output_invalid (int c
)
9326 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9329 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9330 "(0x%x)", (unsigned char) c
);
9331 return output_invalid_buf
;
9334 /* REG_STRING starts *before* REGISTER_PREFIX. */
9336 static const reg_entry
*
9337 parse_real_register (char *reg_string
, char **end_op
)
9339 char *s
= reg_string
;
9341 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9344 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9345 if (*s
== REGISTER_PREFIX
)
9348 if (is_space_char (*s
))
9352 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9354 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9355 return (const reg_entry
*) NULL
;
9359 /* For naked regs, make sure that we are not dealing with an identifier.
9360 This prevents confusing an identifier like `eax_var' with register
9362 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9363 return (const reg_entry
*) NULL
;
9367 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9369 /* Handle floating point regs, allowing spaces in the (i) part. */
9370 if (r
== i386_regtab
/* %st is first entry of table */)
9372 if (is_space_char (*s
))
9377 if (is_space_char (*s
))
9379 if (*s
>= '0' && *s
<= '7')
9383 if (is_space_char (*s
))
9388 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9393 /* We have "%st(" then garbage. */
9394 return (const reg_entry
*) NULL
;
9398 if (r
== NULL
|| allow_pseudo_reg
)
9401 if (operand_type_all_zero (&r
->reg_type
))
9402 return (const reg_entry
*) NULL
;
9404 if ((r
->reg_type
.bitfield
.reg32
9405 || r
->reg_type
.bitfield
.sreg3
9406 || r
->reg_type
.bitfield
.control
9407 || r
->reg_type
.bitfield
.debug
9408 || r
->reg_type
.bitfield
.test
)
9409 && !cpu_arch_flags
.bitfield
.cpui386
)
9410 return (const reg_entry
*) NULL
;
9412 if (r
->reg_type
.bitfield
.floatreg
9413 && !cpu_arch_flags
.bitfield
.cpu8087
9414 && !cpu_arch_flags
.bitfield
.cpu287
9415 && !cpu_arch_flags
.bitfield
.cpu387
)
9416 return (const reg_entry
*) NULL
;
9418 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9419 return (const reg_entry
*) NULL
;
9421 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9422 return (const reg_entry
*) NULL
;
9424 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9425 return (const reg_entry
*) NULL
;
9427 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9428 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9429 return (const reg_entry
*) NULL
;
9431 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9432 if (!allow_index_reg
9433 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9434 return (const reg_entry
*) NULL
;
9436 /* Upper 16 vector register is only available with VREX in 64bit
9438 if ((r
->reg_flags
& RegVRex
))
9440 if (!cpu_arch_flags
.bitfield
.cpuvrex
9441 || flag_code
!= CODE_64BIT
)
9442 return (const reg_entry
*) NULL
;
9447 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9448 || r
->reg_type
.bitfield
.reg64
)
9449 && (!cpu_arch_flags
.bitfield
.cpulm
9450 || !operand_type_equal (&r
->reg_type
, &control
))
9451 && flag_code
!= CODE_64BIT
)
9452 return (const reg_entry
*) NULL
;
9454 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9455 return (const reg_entry
*) NULL
;
9460 /* REG_STRING starts *before* REGISTER_PREFIX. */
9462 static const reg_entry
*
9463 parse_register (char *reg_string
, char **end_op
)
9467 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9468 r
= parse_real_register (reg_string
, end_op
);
9473 char *save
= input_line_pointer
;
9477 input_line_pointer
= reg_string
;
9478 c
= get_symbol_name (®_string
);
9479 symbolP
= symbol_find (reg_string
);
9480 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9482 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9484 know (e
->X_op
== O_register
);
9485 know (e
->X_add_number
>= 0
9486 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9487 r
= i386_regtab
+ e
->X_add_number
;
9488 if ((r
->reg_flags
& RegVRex
))
9490 *end_op
= input_line_pointer
;
9492 *input_line_pointer
= c
;
9493 input_line_pointer
= save
;
9499 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9502 char *end
= input_line_pointer
;
9505 r
= parse_register (name
, &input_line_pointer
);
9506 if (r
&& end
<= input_line_pointer
)
9508 *nextcharP
= *input_line_pointer
;
9509 *input_line_pointer
= 0;
9510 e
->X_op
= O_register
;
9511 e
->X_add_number
= r
- i386_regtab
;
9514 input_line_pointer
= end
;
9516 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9520 md_operand (expressionS
*e
)
9525 switch (*input_line_pointer
)
9527 case REGISTER_PREFIX
:
9528 r
= parse_real_register (input_line_pointer
, &end
);
9531 e
->X_op
= O_register
;
9532 e
->X_add_number
= r
- i386_regtab
;
9533 input_line_pointer
= end
;
9538 gas_assert (intel_syntax
);
9539 end
= input_line_pointer
++;
9541 if (*input_line_pointer
== ']')
9543 ++input_line_pointer
;
9544 e
->X_op_symbol
= make_expr_symbol (e
);
9545 e
->X_add_symbol
= NULL
;
9546 e
->X_add_number
= 0;
9552 input_line_pointer
= end
;
9559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9560 const char *md_shortopts
= "kVQ:sqn";
9562 const char *md_shortopts
= "qn";
9565 #define OPTION_32 (OPTION_MD_BASE + 0)
9566 #define OPTION_64 (OPTION_MD_BASE + 1)
9567 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9568 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9569 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9570 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9571 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9572 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9573 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9574 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9575 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9576 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9577 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9578 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9579 #define OPTION_X32 (OPTION_MD_BASE + 14)
9580 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9581 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9582 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9583 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9584 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9585 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9586 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9587 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9588 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9590 struct option md_longopts
[] =
9592 {"32", no_argument
, NULL
, OPTION_32
},
9593 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9594 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9595 {"64", no_argument
, NULL
, OPTION_64
},
9597 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9598 {"x32", no_argument
, NULL
, OPTION_X32
},
9599 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9601 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9602 {"march", required_argument
, NULL
, OPTION_MARCH
},
9603 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9604 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9605 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9606 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9607 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9608 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9609 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9610 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9611 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9612 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9613 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9614 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9615 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9616 # if defined (TE_PE) || defined (TE_PEP)
9617 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9619 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9620 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9621 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9622 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9623 {NULL
, no_argument
, NULL
, 0}
9625 size_t md_longopts_size
= sizeof (md_longopts
);
9628 md_parse_option (int c
, char *arg
)
9636 optimize_align_code
= 0;
9643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9644 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9645 should be emitted or not. FIXME: Not implemented. */
9649 /* -V: SVR4 argument to print version ID. */
9651 print_version_id ();
9654 /* -k: Ignore for FreeBSD compatibility. */
9659 /* -s: On i386 Solaris, this tells the native assembler to use
9660 .stab instead of .stab.excl. We always use .stab anyhow. */
9663 case OPTION_MSHARED
:
9667 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9668 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9671 const char **list
, **l
;
9673 list
= bfd_target_list ();
9674 for (l
= list
; *l
!= NULL
; l
++)
9675 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9676 || strcmp (*l
, "coff-x86-64") == 0
9677 || strcmp (*l
, "pe-x86-64") == 0
9678 || strcmp (*l
, "pei-x86-64") == 0
9679 || strcmp (*l
, "mach-o-x86-64") == 0)
9681 default_arch
= "x86_64";
9685 as_fatal (_("no compiled in support for x86_64"));
9691 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9695 const char **list
, **l
;
9697 list
= bfd_target_list ();
9698 for (l
= list
; *l
!= NULL
; l
++)
9699 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9701 default_arch
= "x86_64:32";
9705 as_fatal (_("no compiled in support for 32bit x86_64"));
9709 as_fatal (_("32bit x86_64 is only supported for ELF"));
9714 default_arch
= "i386";
9718 #ifdef SVR4_COMMENT_CHARS
9723 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9725 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9729 i386_comment_chars
= n
;
9735 arch
= xstrdup (arg
);
9739 as_fatal (_("invalid -march= option: `%s'"), arg
);
9740 next
= strchr (arch
, '+');
9743 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9745 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9748 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9751 cpu_arch_name
= cpu_arch
[j
].name
;
9752 cpu_sub_arch_name
= NULL
;
9753 cpu_arch_flags
= cpu_arch
[j
].flags
;
9754 cpu_arch_isa
= cpu_arch
[j
].type
;
9755 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9756 if (!cpu_arch_tune_set
)
9758 cpu_arch_tune
= cpu_arch_isa
;
9759 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9763 else if (*cpu_arch
[j
].name
== '.'
9764 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9766 /* ISA entension. */
9767 i386_cpu_flags flags
;
9769 if (!cpu_arch
[j
].negated
)
9770 flags
= cpu_flags_or (cpu_arch_flags
,
9773 flags
= cpu_flags_and_not (cpu_arch_flags
,
9776 if (!valid_iamcu_cpu_flags (&flags
))
9777 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9778 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9780 if (cpu_sub_arch_name
)
9782 char *name
= cpu_sub_arch_name
;
9783 cpu_sub_arch_name
= concat (name
,
9785 (const char *) NULL
);
9789 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9790 cpu_arch_flags
= flags
;
9791 cpu_arch_isa_flags
= flags
;
9797 if (j
>= ARRAY_SIZE (cpu_arch
))
9798 as_fatal (_("invalid -march= option: `%s'"), arg
);
9802 while (next
!= NULL
);
9807 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9808 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9810 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9812 cpu_arch_tune_set
= 1;
9813 cpu_arch_tune
= cpu_arch
[j
].type
;
9814 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9818 if (j
>= ARRAY_SIZE (cpu_arch
))
9819 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9822 case OPTION_MMNEMONIC
:
9823 if (strcasecmp (arg
, "att") == 0)
9825 else if (strcasecmp (arg
, "intel") == 0)
9828 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9831 case OPTION_MSYNTAX
:
9832 if (strcasecmp (arg
, "att") == 0)
9834 else if (strcasecmp (arg
, "intel") == 0)
9837 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9840 case OPTION_MINDEX_REG
:
9841 allow_index_reg
= 1;
9844 case OPTION_MNAKED_REG
:
9845 allow_naked_reg
= 1;
9848 case OPTION_MOLD_GCC
:
9852 case OPTION_MSSE2AVX
:
9856 case OPTION_MSSE_CHECK
:
9857 if (strcasecmp (arg
, "error") == 0)
9858 sse_check
= check_error
;
9859 else if (strcasecmp (arg
, "warning") == 0)
9860 sse_check
= check_warning
;
9861 else if (strcasecmp (arg
, "none") == 0)
9862 sse_check
= check_none
;
9864 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9867 case OPTION_MOPERAND_CHECK
:
9868 if (strcasecmp (arg
, "error") == 0)
9869 operand_check
= check_error
;
9870 else if (strcasecmp (arg
, "warning") == 0)
9871 operand_check
= check_warning
;
9872 else if (strcasecmp (arg
, "none") == 0)
9873 operand_check
= check_none
;
9875 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9878 case OPTION_MAVXSCALAR
:
9879 if (strcasecmp (arg
, "128") == 0)
9881 else if (strcasecmp (arg
, "256") == 0)
9884 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9887 case OPTION_MADD_BND_PREFIX
:
9891 case OPTION_MEVEXLIG
:
9892 if (strcmp (arg
, "128") == 0)
9894 else if (strcmp (arg
, "256") == 0)
9896 else if (strcmp (arg
, "512") == 0)
9899 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9902 case OPTION_MEVEXRCIG
:
9903 if (strcmp (arg
, "rne") == 0)
9905 else if (strcmp (arg
, "rd") == 0)
9907 else if (strcmp (arg
, "ru") == 0)
9909 else if (strcmp (arg
, "rz") == 0)
9912 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9915 case OPTION_MEVEXWIG
:
9916 if (strcmp (arg
, "0") == 0)
9918 else if (strcmp (arg
, "1") == 0)
9921 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9924 # if defined (TE_PE) || defined (TE_PEP)
9925 case OPTION_MBIG_OBJ
:
9930 case OPTION_OMIT_LOCK_PREFIX
:
9931 if (strcasecmp (arg
, "yes") == 0)
9932 omit_lock_prefix
= 1;
9933 else if (strcasecmp (arg
, "no") == 0)
9934 omit_lock_prefix
= 0;
9936 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9940 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
9941 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
9942 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
9943 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
9946 case OPTION_MINTEL64
:
9947 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
9948 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
9949 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
9950 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
9959 #define MESSAGE_TEMPLATE \
9963 show_arch (FILE *stream
, int ext
, int check
)
9965 static char message
[] = MESSAGE_TEMPLATE
;
9966 char *start
= message
+ 27;
9968 int size
= sizeof (MESSAGE_TEMPLATE
);
9975 left
= size
- (start
- message
);
9976 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9978 /* Should it be skipped? */
9979 if (cpu_arch
[j
].skip
)
9982 name
= cpu_arch
[j
].name
;
9983 len
= cpu_arch
[j
].len
;
9986 /* It is an extension. Skip if we aren't asked to show it. */
9997 /* It is an processor. Skip if we show only extension. */
10000 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10002 /* It is an impossible processor - skip. */
10006 /* Reserve 2 spaces for ", " or ",\0" */
10009 /* Check if there is any room. */
10017 p
= mempcpy (p
, name
, len
);
10021 /* Output the current message now and start a new one. */
10024 fprintf (stream
, "%s\n", message
);
10026 left
= size
- (start
- message
) - len
- 2;
10028 gas_assert (left
>= 0);
10030 p
= mempcpy (p
, name
, len
);
10035 fprintf (stream
, "%s\n", message
);
10039 md_show_usage (FILE *stream
)
10041 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10042 fprintf (stream
, _("\
10044 -V print assembler version number\n\
10047 fprintf (stream
, _("\
10048 -n Do not optimize code alignment\n\
10049 -q quieten some warnings\n"));
10050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10051 fprintf (stream
, _("\
10054 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10055 || defined (TE_PE) || defined (TE_PEP))
10056 fprintf (stream
, _("\
10057 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10059 #ifdef SVR4_COMMENT_CHARS
10060 fprintf (stream
, _("\
10061 --divide do not treat `/' as a comment character\n"));
10063 fprintf (stream
, _("\
10064 --divide ignored\n"));
10066 fprintf (stream
, _("\
10067 -march=CPU[,+EXTENSION...]\n\
10068 generate code for CPU and EXTENSION, CPU is one of:\n"));
10069 show_arch (stream
, 0, 1);
10070 fprintf (stream
, _("\
10071 EXTENSION is combination of:\n"));
10072 show_arch (stream
, 1, 0);
10073 fprintf (stream
, _("\
10074 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10075 show_arch (stream
, 0, 0);
10076 fprintf (stream
, _("\
10077 -msse2avx encode SSE instructions with VEX prefix\n"));
10078 fprintf (stream
, _("\
10079 -msse-check=[none|error|warning]\n\
10080 check SSE instructions\n"));
10081 fprintf (stream
, _("\
10082 -moperand-check=[none|error|warning]\n\
10083 check operand combinations for validity\n"));
10084 fprintf (stream
, _("\
10085 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10087 fprintf (stream
, _("\
10088 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10090 fprintf (stream
, _("\
10091 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10092 for EVEX.W bit ignored instructions\n"));
10093 fprintf (stream
, _("\
10094 -mevexrcig=[rne|rd|ru|rz]\n\
10095 encode EVEX instructions with specific EVEX.RC value\n\
10096 for SAE-only ignored instructions\n"));
10097 fprintf (stream
, _("\
10098 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10099 fprintf (stream
, _("\
10100 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10101 fprintf (stream
, _("\
10102 -mindex-reg support pseudo index registers\n"));
10103 fprintf (stream
, _("\
10104 -mnaked-reg don't require `%%' prefix for registers\n"));
10105 fprintf (stream
, _("\
10106 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10107 fprintf (stream
, _("\
10108 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10109 fprintf (stream
, _("\
10110 -mshared disable branch optimization for shared code\n"));
10111 # if defined (TE_PE) || defined (TE_PEP)
10112 fprintf (stream
, _("\
10113 -mbig-obj generate big object files\n"));
10115 fprintf (stream
, _("\
10116 -momit-lock-prefix=[no|yes]\n\
10117 strip all lock prefixes\n"));
10118 fprintf (stream
, _("\
10119 -mamd64 accept only AMD64 ISA\n"));
10120 fprintf (stream
, _("\
10121 -mintel64 accept only Intel64 ISA\n"));
10124 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10125 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10126 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10128 /* Pick the target format to use. */
10131 i386_target_format (void)
10133 if (!strncmp (default_arch
, "x86_64", 6))
10135 update_code_flag (CODE_64BIT
, 1);
10136 if (default_arch
[6] == '\0')
10137 x86_elf_abi
= X86_64_ABI
;
10139 x86_elf_abi
= X86_64_X32_ABI
;
10141 else if (!strcmp (default_arch
, "i386"))
10142 update_code_flag (CODE_32BIT
, 1);
10143 else if (!strcmp (default_arch
, "iamcu"))
10145 update_code_flag (CODE_32BIT
, 1);
10146 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10148 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10149 cpu_arch_name
= "iamcu";
10150 cpu_sub_arch_name
= NULL
;
10151 cpu_arch_flags
= iamcu_flags
;
10152 cpu_arch_isa
= PROCESSOR_IAMCU
;
10153 cpu_arch_isa_flags
= iamcu_flags
;
10154 if (!cpu_arch_tune_set
)
10156 cpu_arch_tune
= cpu_arch_isa
;
10157 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10161 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10165 as_fatal (_("unknown architecture"));
10167 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10168 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10169 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10170 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10172 switch (OUTPUT_FLAVOR
)
10174 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10175 case bfd_target_aout_flavour
:
10176 return AOUT_TARGET_FORMAT
;
10178 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10179 # if defined (TE_PE) || defined (TE_PEP)
10180 case bfd_target_coff_flavour
:
10181 if (flag_code
== CODE_64BIT
)
10182 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10185 # elif defined (TE_GO32)
10186 case bfd_target_coff_flavour
:
10187 return "coff-go32";
10189 case bfd_target_coff_flavour
:
10190 return "coff-i386";
10193 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10194 case bfd_target_elf_flavour
:
10196 const char *format
;
10198 switch (x86_elf_abi
)
10201 format
= ELF_TARGET_FORMAT
;
10204 use_rela_relocations
= 1;
10206 format
= ELF_TARGET_FORMAT64
;
10208 case X86_64_X32_ABI
:
10209 use_rela_relocations
= 1;
10211 disallow_64bit_reloc
= 1;
10212 format
= ELF_TARGET_FORMAT32
;
10215 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10217 if (x86_elf_abi
!= X86_64_ABI
)
10218 as_fatal (_("Intel L1OM is 64bit only"));
10219 return ELF_TARGET_L1OM_FORMAT
;
10221 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10223 if (x86_elf_abi
!= X86_64_ABI
)
10224 as_fatal (_("Intel K1OM is 64bit only"));
10225 return ELF_TARGET_K1OM_FORMAT
;
10227 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10229 if (x86_elf_abi
!= I386_ABI
)
10230 as_fatal (_("Intel MCU is 32bit only"));
10231 return ELF_TARGET_IAMCU_FORMAT
;
10237 #if defined (OBJ_MACH_O)
10238 case bfd_target_mach_o_flavour
:
10239 if (flag_code
== CODE_64BIT
)
10241 use_rela_relocations
= 1;
10243 return "mach-o-x86-64";
10246 return "mach-o-i386";
10254 #endif /* OBJ_MAYBE_ more than one */
10257 md_undefined_symbol (char *name
)
10259 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10260 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10261 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10262 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10266 if (symbol_find (name
))
10267 as_bad (_("GOT already in symbol table"));
10268 GOT_symbol
= symbol_new (name
, undefined_section
,
10269 (valueT
) 0, &zero_address_frag
);
10276 /* Round up a section size to the appropriate boundary. */
10279 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10281 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10282 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10284 /* For a.out, force the section size to be aligned. If we don't do
10285 this, BFD will align it for us, but it will not write out the
10286 final bytes of the section. This may be a bug in BFD, but it is
10287 easier to fix it here since that is how the other a.out targets
10291 align
= bfd_get_section_alignment (stdoutput
, segment
);
10292 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10299 /* On the i386, PC-relative offsets are relative to the start of the
10300 next instruction. That is, the address of the offset, plus its
10301 size, since the offset is always the last part of the insn. */
10304 md_pcrel_from (fixS
*fixP
)
10306 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10312 s_bss (int ignore ATTRIBUTE_UNUSED
)
10316 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10318 obj_elf_section_change_hook ();
10320 temp
= get_absolute_expression ();
10321 subseg_set (bss_section
, (subsegT
) temp
);
10322 demand_empty_rest_of_line ();
10328 i386_validate_fix (fixS
*fixp
)
10330 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10332 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10336 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10341 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10343 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10345 fixp
->fx_subsy
= 0;
10350 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10353 bfd_reloc_code_real_type code
;
10355 switch (fixp
->fx_r_type
)
10357 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10358 case BFD_RELOC_SIZE32
:
10359 case BFD_RELOC_SIZE64
:
10360 if (S_IS_DEFINED (fixp
->fx_addsy
)
10361 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10363 /* Resolve size relocation against local symbol to size of
10364 the symbol plus addend. */
10365 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10366 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10367 && !fits_in_unsigned_long (value
))
10368 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10369 _("symbol size computation overflow"));
10370 fixp
->fx_addsy
= NULL
;
10371 fixp
->fx_subsy
= NULL
;
10372 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10377 case BFD_RELOC_X86_64_PLT32
:
10378 case BFD_RELOC_X86_64_GOT32
:
10379 case BFD_RELOC_X86_64_GOTPCREL
:
10380 case BFD_RELOC_386_PLT32
:
10381 case BFD_RELOC_386_GOT32
:
10382 case BFD_RELOC_386_GOTOFF
:
10383 case BFD_RELOC_386_GOTPC
:
10384 case BFD_RELOC_386_TLS_GD
:
10385 case BFD_RELOC_386_TLS_LDM
:
10386 case BFD_RELOC_386_TLS_LDO_32
:
10387 case BFD_RELOC_386_TLS_IE_32
:
10388 case BFD_RELOC_386_TLS_IE
:
10389 case BFD_RELOC_386_TLS_GOTIE
:
10390 case BFD_RELOC_386_TLS_LE_32
:
10391 case BFD_RELOC_386_TLS_LE
:
10392 case BFD_RELOC_386_TLS_GOTDESC
:
10393 case BFD_RELOC_386_TLS_DESC_CALL
:
10394 case BFD_RELOC_X86_64_TLSGD
:
10395 case BFD_RELOC_X86_64_TLSLD
:
10396 case BFD_RELOC_X86_64_DTPOFF32
:
10397 case BFD_RELOC_X86_64_DTPOFF64
:
10398 case BFD_RELOC_X86_64_GOTTPOFF
:
10399 case BFD_RELOC_X86_64_TPOFF32
:
10400 case BFD_RELOC_X86_64_TPOFF64
:
10401 case BFD_RELOC_X86_64_GOTOFF64
:
10402 case BFD_RELOC_X86_64_GOTPC32
:
10403 case BFD_RELOC_X86_64_GOT64
:
10404 case BFD_RELOC_X86_64_GOTPCREL64
:
10405 case BFD_RELOC_X86_64_GOTPC64
:
10406 case BFD_RELOC_X86_64_GOTPLT64
:
10407 case BFD_RELOC_X86_64_PLTOFF64
:
10408 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10409 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10410 case BFD_RELOC_RVA
:
10411 case BFD_RELOC_VTABLE_ENTRY
:
10412 case BFD_RELOC_VTABLE_INHERIT
:
10414 case BFD_RELOC_32_SECREL
:
10416 code
= fixp
->fx_r_type
;
10418 case BFD_RELOC_X86_64_32S
:
10419 if (!fixp
->fx_pcrel
)
10421 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10422 code
= fixp
->fx_r_type
;
10426 if (fixp
->fx_pcrel
)
10428 switch (fixp
->fx_size
)
10431 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10432 _("can not do %d byte pc-relative relocation"),
10434 code
= BFD_RELOC_32_PCREL
;
10436 case 1: code
= BFD_RELOC_8_PCREL
; break;
10437 case 2: code
= BFD_RELOC_16_PCREL
; break;
10438 case 4: code
= BFD_RELOC_32_PCREL
; break;
10440 case 8: code
= BFD_RELOC_64_PCREL
; break;
10446 switch (fixp
->fx_size
)
10449 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10450 _("can not do %d byte relocation"),
10452 code
= BFD_RELOC_32
;
10454 case 1: code
= BFD_RELOC_8
; break;
10455 case 2: code
= BFD_RELOC_16
; break;
10456 case 4: code
= BFD_RELOC_32
; break;
10458 case 8: code
= BFD_RELOC_64
; break;
10465 if ((code
== BFD_RELOC_32
10466 || code
== BFD_RELOC_32_PCREL
10467 || code
== BFD_RELOC_X86_64_32S
)
10469 && fixp
->fx_addsy
== GOT_symbol
)
10472 code
= BFD_RELOC_386_GOTPC
;
10474 code
= BFD_RELOC_X86_64_GOTPC32
;
10476 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10478 && fixp
->fx_addsy
== GOT_symbol
)
10480 code
= BFD_RELOC_X86_64_GOTPC64
;
10483 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10484 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10485 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10487 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10489 if (!use_rela_relocations
)
10491 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10492 vtable entry to be used in the relocation's section offset. */
10493 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10494 rel
->address
= fixp
->fx_offset
;
10495 #if defined (OBJ_COFF) && defined (TE_PE)
10496 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10497 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10502 /* Use the rela in 64bit mode. */
10505 if (disallow_64bit_reloc
)
10508 case BFD_RELOC_X86_64_DTPOFF64
:
10509 case BFD_RELOC_X86_64_TPOFF64
:
10510 case BFD_RELOC_64_PCREL
:
10511 case BFD_RELOC_X86_64_GOTOFF64
:
10512 case BFD_RELOC_X86_64_GOT64
:
10513 case BFD_RELOC_X86_64_GOTPCREL64
:
10514 case BFD_RELOC_X86_64_GOTPC64
:
10515 case BFD_RELOC_X86_64_GOTPLT64
:
10516 case BFD_RELOC_X86_64_PLTOFF64
:
10517 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10518 _("cannot represent relocation type %s in x32 mode"),
10519 bfd_get_reloc_code_name (code
));
10525 if (!fixp
->fx_pcrel
)
10526 rel
->addend
= fixp
->fx_offset
;
10530 case BFD_RELOC_X86_64_PLT32
:
10531 case BFD_RELOC_X86_64_GOT32
:
10532 case BFD_RELOC_X86_64_GOTPCREL
:
10533 case BFD_RELOC_X86_64_TLSGD
:
10534 case BFD_RELOC_X86_64_TLSLD
:
10535 case BFD_RELOC_X86_64_GOTTPOFF
:
10536 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10537 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10538 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10541 rel
->addend
= (section
->vma
10543 + fixp
->fx_addnumber
10544 + md_pcrel_from (fixp
));
10549 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10550 if (rel
->howto
== NULL
)
10552 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10553 _("cannot represent relocation type %s"),
10554 bfd_get_reloc_code_name (code
));
10555 /* Set howto to a garbage value so that we can keep going. */
10556 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10557 gas_assert (rel
->howto
!= NULL
);
10563 #include "tc-i386-intel.c"
10566 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10568 int saved_naked_reg
;
10569 char saved_register_dot
;
10571 saved_naked_reg
= allow_naked_reg
;
10572 allow_naked_reg
= 1;
10573 saved_register_dot
= register_chars
['.'];
10574 register_chars
['.'] = '.';
10575 allow_pseudo_reg
= 1;
10576 expression_and_evaluate (exp
);
10577 allow_pseudo_reg
= 0;
10578 register_chars
['.'] = saved_register_dot
;
10579 allow_naked_reg
= saved_naked_reg
;
10581 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10583 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10585 exp
->X_op
= O_constant
;
10586 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10587 .dw2_regnum
[flag_code
>> 1];
10590 exp
->X_op
= O_illegal
;
10595 tc_x86_frame_initial_instructions (void)
10597 static unsigned int sp_regno
[2];
10599 if (!sp_regno
[flag_code
>> 1])
10601 char *saved_input
= input_line_pointer
;
10602 char sp
[][4] = {"esp", "rsp"};
10605 input_line_pointer
= sp
[flag_code
>> 1];
10606 tc_x86_parse_to_dw2regnum (&exp
);
10607 gas_assert (exp
.X_op
== O_constant
);
10608 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10609 input_line_pointer
= saved_input
;
10612 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10613 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10617 x86_dwarf2_addr_size (void)
10619 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10620 if (x86_elf_abi
== X86_64_X32_ABI
)
10623 return bfd_arch_bits_per_address (stdoutput
) / 8;
10627 i386_elf_section_type (const char *str
, size_t len
)
10629 if (flag_code
== CODE_64BIT
10630 && len
== sizeof ("unwind") - 1
10631 && strncmp (str
, "unwind", 6) == 0)
10632 return SHT_X86_64_UNWIND
;
10639 i386_solaris_fix_up_eh_frame (segT sec
)
10641 if (flag_code
== CODE_64BIT
)
10642 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10648 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10652 exp
.X_op
= O_secrel
;
10653 exp
.X_add_symbol
= symbol
;
10654 exp
.X_add_number
= 0;
10655 emit_expr (&exp
, size
);
10659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10660 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10663 x86_64_section_letter (int letter
, char **ptr_msg
)
10665 if (flag_code
== CODE_64BIT
)
10668 return SHF_X86_64_LARGE
;
10670 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10673 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10678 x86_64_section_word (char *str
, size_t len
)
10680 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10681 return SHF_X86_64_LARGE
;
10687 handle_large_common (int small ATTRIBUTE_UNUSED
)
10689 if (flag_code
!= CODE_64BIT
)
10691 s_comm_internal (0, elf_common_parse
);
10692 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10696 static segT lbss_section
;
10697 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10698 asection
*saved_bss_section
= bss_section
;
10700 if (lbss_section
== NULL
)
10702 flagword applicable
;
10703 segT seg
= now_seg
;
10704 subsegT subseg
= now_subseg
;
10706 /* The .lbss section is for local .largecomm symbols. */
10707 lbss_section
= subseg_new (".lbss", 0);
10708 applicable
= bfd_applicable_section_flags (stdoutput
);
10709 bfd_set_section_flags (stdoutput
, lbss_section
,
10710 applicable
& SEC_ALLOC
);
10711 seg_info (lbss_section
)->bss
= 1;
10713 subseg_set (seg
, subseg
);
10716 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10717 bss_section
= lbss_section
;
10719 s_comm_internal (0, elf_common_parse
);
10721 elf_com_section_ptr
= saved_com_section_ptr
;
10722 bss_section
= saved_bss_section
;
10725 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */