1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static enum flag_code
i386_addressing_mode (void);
186 static void optimize_imm (void);
187 static void optimize_disp (void);
188 static const insn_template
*match_template (char);
189 static int check_string (void);
190 static int process_suffix (void);
191 static int check_byte_reg (void);
192 static int check_long_reg (void);
193 static int check_qword_reg (void);
194 static int check_word_reg (void);
195 static int finalize_imm (void);
196 static int process_operands (void);
197 static const seg_entry
*build_modrm_byte (void);
198 static void output_insn (void);
199 static void output_imm (fragS
*, offsetT
);
200 static void output_disp (fragS
*, offsetT
);
202 static void s_bss (int);
204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
205 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
207 /* GNU_PROPERTY_X86_ISA_1_USED. */
208 static unsigned int x86_isa_1_used
;
209 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
210 static unsigned int x86_feature_2_used
;
211 /* Generate x86 used ISA and feature properties. */
212 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
215 static const char *default_arch
= DEFAULT_ARCH
;
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* The operand to a branch insn indicates an absolute branch. */
358 bfd_boolean jumpabsolute
;
360 /* Has MMX register operands. */
361 bfd_boolean has_regmmx
;
363 /* Has XMM register operands. */
364 bfd_boolean has_regxmm
;
366 /* Has YMM register operands. */
367 bfd_boolean has_regymm
;
369 /* Has ZMM register operands. */
370 bfd_boolean has_regzmm
;
372 /* Has GOTPC or TLS relocation. */
373 bfd_boolean has_gotpc_tls_reloc
;
375 /* RM and SIB are the modrm byte and the sib byte where the
376 addressing modes of this insn are encoded. */
383 /* Masking attributes. */
384 struct Mask_Operation
*mask
;
386 /* Rounding control and SAE attributes. */
387 struct RC_Operation
*rounding
;
389 /* Broadcasting attributes. */
390 struct Broadcast_Operation
*broadcast
;
392 /* Compressed disp8*N attribute. */
393 unsigned int memshift
;
395 /* Prefer load or store in encoding. */
398 dir_encoding_default
= 0,
404 /* Prefer 8bit or 32bit displacement in encoding. */
407 disp_encoding_default
= 0,
412 /* Prefer the REX byte in encoding. */
413 bfd_boolean rex_encoding
;
415 /* Disable instruction size optimization. */
416 bfd_boolean no_optimize
;
418 /* How to encode vector instructions. */
421 vex_encoding_default
= 0,
428 const char *rep_prefix
;
431 const char *hle_prefix
;
433 /* Have BND prefix. */
434 const char *bnd_prefix
;
436 /* Have NOTRACK prefix. */
437 const char *notrack_prefix
;
440 enum i386_error error
;
443 typedef struct _i386_insn i386_insn
;
445 /* Link RC type with corresponding string, that'll be looked for in
454 static const struct RC_name RC_NamesTable
[] =
456 { rne
, STRING_COMMA_LEN ("rn-sae") },
457 { rd
, STRING_COMMA_LEN ("rd-sae") },
458 { ru
, STRING_COMMA_LEN ("ru-sae") },
459 { rz
, STRING_COMMA_LEN ("rz-sae") },
460 { saeonly
, STRING_COMMA_LEN ("sae") },
463 /* List of chars besides those in app.c:symbol_chars that can start an
464 operand. Used to prevent the scrubber eating vital white-space. */
465 const char extra_symbol_chars
[] = "*%-([{}"
474 #if (defined (TE_I386AIX) \
475 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
476 && !defined (TE_GNU) \
477 && !defined (TE_LINUX) \
478 && !defined (TE_NACL) \
479 && !defined (TE_FreeBSD) \
480 && !defined (TE_DragonFly) \
481 && !defined (TE_NetBSD)))
482 /* This array holds the chars that always start a comment. If the
483 pre-processor is disabled, these aren't very useful. The option
484 --divide will remove '/' from this list. */
485 const char *i386_comment_chars
= "#/";
486 #define SVR4_COMMENT_CHARS 1
487 #define PREFIX_SEPARATOR '\\'
490 const char *i386_comment_chars
= "#";
491 #define PREFIX_SEPARATOR '/'
494 /* This array holds the chars that only start a comment at the beginning of
495 a line. If the line seems to have the form '# 123 filename'
496 .line and .file directives will appear in the pre-processed output.
497 Note that input_file.c hand checks for '#' at the beginning of the
498 first line of the input file. This is because the compiler outputs
499 #NO_APP at the beginning of its output.
500 Also note that comments started like this one will always work if
501 '/' isn't otherwise defined. */
502 const char line_comment_chars
[] = "#/";
504 const char line_separator_chars
[] = ";";
506 /* Chars that can be used to separate mant from exp in floating point
508 const char EXP_CHARS
[] = "eE";
510 /* Chars that mean this number is a floating point constant
513 const char FLT_CHARS
[] = "fFdDxX";
515 /* Tables for lexical analysis. */
516 static char mnemonic_chars
[256];
517 static char register_chars
[256];
518 static char operand_chars
[256];
519 static char identifier_chars
[256];
520 static char digit_chars
[256];
522 /* Lexical macros. */
523 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
524 #define is_operand_char(x) (operand_chars[(unsigned char) x])
525 #define is_register_char(x) (register_chars[(unsigned char) x])
526 #define is_space_char(x) ((x) == ' ')
527 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
528 #define is_digit_char(x) (digit_chars[(unsigned char) x])
530 /* All non-digit non-letter characters that may occur in an operand. */
531 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
533 /* md_assemble() always leaves the strings it's passed unaltered. To
534 effect this we maintain a stack of saved characters that we've smashed
535 with '\0's (indicating end of strings for various sub-fields of the
536 assembler instruction). */
537 static char save_stack
[32];
538 static char *save_stack_p
;
539 #define END_STRING_AND_SAVE(s) \
540 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
541 #define RESTORE_END_STRING(s) \
542 do { *(s) = *--save_stack_p; } while (0)
544 /* The instruction we're assembling. */
547 /* Possible templates for current insn. */
548 static const templates
*current_templates
;
550 /* Per instruction expressionS buffers: max displacements & immediates. */
551 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
552 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
554 /* Current operand we are working on. */
555 static int this_operand
= -1;
557 /* We support four different modes. FLAG_CODE variable is used to distinguish
565 static enum flag_code flag_code
;
566 static unsigned int object_64bit
;
567 static unsigned int disallow_64bit_reloc
;
568 static int use_rela_relocations
= 0;
569 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
570 static const char *tls_get_addr
;
572 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
573 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
574 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
576 /* The ELF ABI to use. */
584 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
587 #if defined (TE_PE) || defined (TE_PEP)
588 /* Use big object file format. */
589 static int use_big_obj
= 0;
592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
593 /* 1 if generating code for a shared library. */
594 static int shared
= 0;
597 /* 1 for intel syntax,
599 static int intel_syntax
= 0;
601 /* 1 for Intel64 ISA,
605 /* 1 for intel mnemonic,
606 0 if att mnemonic. */
607 static int intel_mnemonic
= !SYSV386_COMPAT
;
609 /* 1 if pseudo registers are permitted. */
610 static int allow_pseudo_reg
= 0;
612 /* 1 if register prefix % not required. */
613 static int allow_naked_reg
= 0;
615 /* 1 if the assembler should add BND prefix for all control-transferring
616 instructions supporting it, even if this prefix wasn't specified
618 static int add_bnd_prefix
= 0;
620 /* 1 if pseudo index register, eiz/riz, is allowed . */
621 static int allow_index_reg
= 0;
623 /* 1 if the assembler should ignore LOCK prefix, even if it was
624 specified explicitly. */
625 static int omit_lock_prefix
= 0;
627 /* 1 if the assembler should encode lfence, mfence, and sfence as
628 "lock addl $0, (%{re}sp)". */
629 static int avoid_fence
= 0;
631 /* Type of the previous instruction. */
646 /* 1 if the assembler should generate relax relocations. */
648 static int generate_relax_relocations
649 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
651 static enum check_kind
657 sse_check
, operand_check
= check_warning
;
659 /* Non-zero if branches should be aligned within power of 2 boundary. */
660 static int align_branch_power
= 0;
662 /* Types of branches to align. */
663 enum align_branch_kind
665 align_branch_none
= 0,
666 align_branch_jcc
= 1,
667 align_branch_fused
= 2,
668 align_branch_jmp
= 3,
669 align_branch_call
= 4,
670 align_branch_indirect
= 5,
674 /* Type bits of branches to align. */
675 enum align_branch_bit
677 align_branch_jcc_bit
= 1 << align_branch_jcc
,
678 align_branch_fused_bit
= 1 << align_branch_fused
,
679 align_branch_jmp_bit
= 1 << align_branch_jmp
,
680 align_branch_call_bit
= 1 << align_branch_call
,
681 align_branch_indirect_bit
= 1 << align_branch_indirect
,
682 align_branch_ret_bit
= 1 << align_branch_ret
685 static unsigned int align_branch
= (align_branch_jcc_bit
686 | align_branch_fused_bit
687 | align_branch_jmp_bit
);
689 /* The maximum padding size for fused jcc. CMP like instruction can
690 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
692 #define MAX_FUSED_JCC_PADDING_SIZE 20
694 /* The maximum number of prefixes added for an instruction. */
695 static unsigned int align_branch_prefix_size
= 5;
698 1. Clear the REX_W bit with register operand if possible.
699 2. Above plus use 128bit vector instruction to clear the full vector
702 static int optimize
= 0;
705 1. Clear the REX_W bit with register operand if possible.
706 2. Above plus use 128bit vector instruction to clear the full vector
708 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
711 static int optimize_for_space
= 0;
713 /* Register prefix used for error message. */
714 static const char *register_prefix
= "%";
716 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
717 leave, push, and pop instructions so that gcc has the same stack
718 frame as in 32 bit mode. */
719 static char stackop_size
= '\0';
721 /* Non-zero to optimize code alignment. */
722 int optimize_align_code
= 1;
724 /* Non-zero to quieten some warnings. */
725 static int quiet_warnings
= 0;
728 static const char *cpu_arch_name
= NULL
;
729 static char *cpu_sub_arch_name
= NULL
;
731 /* CPU feature flags. */
732 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
734 /* If we have selected a cpu we are generating instructions for. */
735 static int cpu_arch_tune_set
= 0;
737 /* Cpu we are generating instructions for. */
738 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
740 /* CPU feature flags of cpu we are generating instructions for. */
741 static i386_cpu_flags cpu_arch_tune_flags
;
743 /* CPU instruction set architecture used. */
744 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
746 /* CPU feature flags of instruction set architecture used. */
747 i386_cpu_flags cpu_arch_isa_flags
;
749 /* If set, conditional jumps are not automatically promoted to handle
750 larger than a byte offset. */
751 static unsigned int no_cond_jump_promotion
= 0;
753 /* Encode SSE instructions with VEX prefix. */
754 static unsigned int sse2avx
;
756 /* Encode scalar AVX instructions with specific vector length. */
763 /* Encode VEX WIG instructions with specific vex.w. */
770 /* Encode scalar EVEX LIG instructions with specific vector length. */
778 /* Encode EVEX WIG instructions with specific evex.w. */
785 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
786 static enum rc_type evexrcig
= rne
;
788 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
789 static symbolS
*GOT_symbol
;
791 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
792 unsigned int x86_dwarf2_return_column
;
794 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
795 int x86_cie_data_alignment
;
797 /* Interface to relax_segment.
798 There are 3 major relax states for 386 jump insns because the
799 different types of jumps add different sizes to frags when we're
800 figuring out what sort of jump to choose to reach a given label.
802 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
803 branches which are handled by md_estimate_size_before_relax() and
804 i386_generic_table_relax_frag(). */
807 #define UNCOND_JUMP 0
809 #define COND_JUMP86 2
810 #define BRANCH_PADDING 3
811 #define BRANCH_PREFIX 4
812 #define FUSED_JCC_PADDING 5
817 #define SMALL16 (SMALL | CODE16)
819 #define BIG16 (BIG | CODE16)
823 #define INLINE __inline__
829 #define ENCODE_RELAX_STATE(type, size) \
830 ((relax_substateT) (((type) << 2) | (size)))
831 #define TYPE_FROM_RELAX_STATE(s) \
833 #define DISP_SIZE_FROM_RELAX_STATE(s) \
834 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
836 /* This table is used by relax_frag to promote short jumps to long
837 ones where necessary. SMALL (short) jumps may be promoted to BIG
838 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
839 don't allow a short jump in a 32 bit code segment to be promoted to
840 a 16 bit offset jump because it's slower (requires data size
841 prefix), and doesn't work, unless the destination is in the bottom
842 64k of the code segment (The top 16 bits of eip are zeroed). */
844 const relax_typeS md_relax_table
[] =
847 1) most positive reach of this state,
848 2) most negative reach of this state,
849 3) how many bytes this mode will have in the variable part of the frag
850 4) which index into the table to try if we can't fit into this one. */
852 /* UNCOND_JUMP states. */
853 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
855 /* dword jmp adds 4 bytes to frag:
856 0 extra opcode bytes, 4 displacement bytes. */
858 /* word jmp adds 2 byte2 to frag:
859 0 extra opcode bytes, 2 displacement bytes. */
862 /* COND_JUMP states. */
863 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
865 /* dword conditionals adds 5 bytes to frag:
866 1 extra opcode byte, 4 displacement bytes. */
868 /* word conditionals add 3 bytes to frag:
869 1 extra opcode byte, 2 displacement bytes. */
872 /* COND_JUMP86 states. */
873 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
875 /* dword conditionals adds 5 bytes to frag:
876 1 extra opcode byte, 4 displacement bytes. */
878 /* word conditionals add 4 bytes to frag:
879 1 displacement byte and a 3 byte long branch insn. */
883 static const arch_entry cpu_arch
[] =
885 /* Do not replace the first two entries - i386_target_format()
886 relies on them being there in this order. */
887 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
888 CPU_GENERIC32_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
890 CPU_GENERIC64_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
899 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
901 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
903 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
905 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
907 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
908 CPU_PENTIUMPRO_FLAGS
, 0 },
909 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
911 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
913 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
915 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
917 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
918 CPU_NOCONA_FLAGS
, 0 },
919 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
921 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
923 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
924 CPU_CORE2_FLAGS
, 1 },
925 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
926 CPU_CORE2_FLAGS
, 0 },
927 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
928 CPU_COREI7_FLAGS
, 0 },
929 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
931 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
933 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
934 CPU_IAMCU_FLAGS
, 0 },
935 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
937 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
939 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
940 CPU_ATHLON_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
943 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
945 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
947 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
948 CPU_AMDFAM10_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
950 CPU_BDVER1_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
952 CPU_BDVER2_FLAGS
, 0 },
953 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
954 CPU_BDVER3_FLAGS
, 0 },
955 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
956 CPU_BDVER4_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
958 CPU_ZNVER1_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
960 CPU_ZNVER2_FLAGS
, 0 },
961 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
962 CPU_BTVER1_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
964 CPU_BTVER2_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
983 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
986 CPU_SSSE3_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
988 CPU_SSE4_1_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
990 CPU_SSE4_2_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
992 CPU_SSE4_2_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
998 CPU_AVX512F_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1000 CPU_AVX512CD_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1002 CPU_AVX512ER_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1004 CPU_AVX512PF_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1006 CPU_AVX512DQ_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1008 CPU_AVX512BW_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1010 CPU_AVX512VL_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1014 CPU_VMFUNC_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1018 CPU_XSAVE_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1020 CPU_XSAVEOPT_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1022 CPU_XSAVEC_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1024 CPU_XSAVES_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1028 CPU_PCLMUL_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1030 CPU_PCLMUL_FLAGS
, 1 },
1031 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1032 CPU_FSGSBASE_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1034 CPU_RDRND_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1036 CPU_F16C_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1038 CPU_BMI2_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1042 CPU_FMA4_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1045 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1048 CPU_MOVBE_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1050 CPU_CX16_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1053 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1054 CPU_LZCNT_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1057 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1059 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1060 CPU_INVPCID_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1062 CPU_CLFLUSH_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1066 CPU_SYSCALL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1068 CPU_RDTSCP_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1070 CPU_3DNOW_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1072 CPU_3DNOWA_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1074 CPU_PADLOCK_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1076 CPU_SVME_FLAGS
, 1 },
1077 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1078 CPU_SVME_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1080 CPU_SSE4A_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1089 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1090 CPU_RDSEED_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1092 CPU_PRFCHW_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1094 CPU_SMAP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1100 CPU_CLFLUSHOPT_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1102 CPU_PREFETCHWT1_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1106 CPU_CLWB_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1108 CPU_AVX512IFMA_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1110 CPU_AVX512VBMI_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1112 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1114 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1116 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1118 CPU_AVX512_VBMI2_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1120 CPU_AVX512_VNNI_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1122 CPU_AVX512_BITALG_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1124 CPU_CLZERO_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1126 CPU_MWAITX_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1128 CPU_OSPKE_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1130 CPU_RDPID_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1132 CPU_PTWRITE_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1135 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1136 CPU_SHSTK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1138 CPU_GFNI_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1140 CPU_VAES_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1142 CPU_VPCLMULQDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1144 CPU_WBNOINVD_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1146 CPU_PCONFIG_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1148 CPU_WAITPKG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1150 CPU_CLDEMOTE_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1152 CPU_MOVDIRI_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1154 CPU_MOVDIR64B_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1156 CPU_AVX512_BF16_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1158 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1160 CPU_ENQCMD_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1162 CPU_RDPRU_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1164 CPU_MCOMMIT_FLAGS
, 0 },
1167 static const noarch_entry cpu_noarch
[] =
1169 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1170 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1171 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1172 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1173 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1174 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1175 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1176 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1177 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1178 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1179 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1180 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1183 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1184 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1185 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1186 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1200 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1201 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1202 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1203 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1204 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1205 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1206 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1210 /* Like s_lcomm_internal in gas/read.c but the alignment string
1211 is allowed to be optional. */
1214 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1221 && *input_line_pointer
== ',')
1223 align
= parse_align (needs_align
- 1);
1225 if (align
== (addressT
) -1)
1240 bss_alloc (symbolP
, size
, align
);
1245 pe_lcomm (int needs_align
)
1247 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1251 const pseudo_typeS md_pseudo_table
[] =
1253 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1254 {"align", s_align_bytes
, 0},
1256 {"align", s_align_ptwo
, 0},
1258 {"arch", set_cpu_arch
, 0},
1262 {"lcomm", pe_lcomm
, 1},
1264 {"ffloat", float_cons
, 'f'},
1265 {"dfloat", float_cons
, 'd'},
1266 {"tfloat", float_cons
, 'x'},
1268 {"slong", signed_cons
, 4},
1269 {"noopt", s_ignore
, 0},
1270 {"optim", s_ignore
, 0},
1271 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1272 {"code16", set_code_flag
, CODE_16BIT
},
1273 {"code32", set_code_flag
, CODE_32BIT
},
1275 {"code64", set_code_flag
, CODE_64BIT
},
1277 {"intel_syntax", set_intel_syntax
, 1},
1278 {"att_syntax", set_intel_syntax
, 0},
1279 {"intel_mnemonic", set_intel_mnemonic
, 1},
1280 {"att_mnemonic", set_intel_mnemonic
, 0},
1281 {"allow_index_reg", set_allow_index_reg
, 1},
1282 {"disallow_index_reg", set_allow_index_reg
, 0},
1283 {"sse_check", set_check
, 0},
1284 {"operand_check", set_check
, 1},
1285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1286 {"largecomm", handle_large_common
, 0},
1288 {"file", dwarf2_directive_file
, 0},
1289 {"loc", dwarf2_directive_loc
, 0},
1290 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1293 {"secrel32", pe_directive_secrel
, 0},
1298 /* For interface with expression (). */
1299 extern char *input_line_pointer
;
1301 /* Hash table for instruction mnemonic lookup. */
1302 static struct hash_control
*op_hash
;
1304 /* Hash table for register lookup. */
1305 static struct hash_control
*reg_hash
;
1307 /* Various efficient no-op patterns for aligning code labels.
1308 Note: Don't try to assemble the instructions in the comments.
1309 0L and 0w are not legal. */
1310 static const unsigned char f32_1
[] =
1312 static const unsigned char f32_2
[] =
1313 {0x66,0x90}; /* xchg %ax,%ax */
1314 static const unsigned char f32_3
[] =
1315 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1316 static const unsigned char f32_4
[] =
1317 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1318 static const unsigned char f32_6
[] =
1319 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1320 static const unsigned char f32_7
[] =
1321 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1322 static const unsigned char f16_3
[] =
1323 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1324 static const unsigned char f16_4
[] =
1325 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1326 static const unsigned char jump_disp8
[] =
1327 {0xeb}; /* jmp disp8 */
1328 static const unsigned char jump32_disp32
[] =
1329 {0xe9}; /* jmp disp32 */
1330 static const unsigned char jump16_disp32
[] =
1331 {0x66,0xe9}; /* jmp disp32 */
1332 /* 32-bit NOPs patterns. */
1333 static const unsigned char *const f32_patt
[] = {
1334 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1336 /* 16-bit NOPs patterns. */
1337 static const unsigned char *const f16_patt
[] = {
1338 f32_1
, f32_2
, f16_3
, f16_4
1340 /* nopl (%[re]ax) */
1341 static const unsigned char alt_3
[] =
1343 /* nopl 0(%[re]ax) */
1344 static const unsigned char alt_4
[] =
1345 {0x0f,0x1f,0x40,0x00};
1346 /* nopl 0(%[re]ax,%[re]ax,1) */
1347 static const unsigned char alt_5
[] =
1348 {0x0f,0x1f,0x44,0x00,0x00};
1349 /* nopw 0(%[re]ax,%[re]ax,1) */
1350 static const unsigned char alt_6
[] =
1351 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1352 /* nopl 0L(%[re]ax) */
1353 static const unsigned char alt_7
[] =
1354 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1355 /* nopl 0L(%[re]ax,%[re]ax,1) */
1356 static const unsigned char alt_8
[] =
1357 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1358 /* nopw 0L(%[re]ax,%[re]ax,1) */
1359 static const unsigned char alt_9
[] =
1360 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1361 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1362 static const unsigned char alt_10
[] =
1363 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1364 /* data16 nopw %cs:0L(%eax,%eax,1) */
1365 static const unsigned char alt_11
[] =
1366 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1367 /* 32-bit and 64-bit NOPs patterns. */
1368 static const unsigned char *const alt_patt
[] = {
1369 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1370 alt_9
, alt_10
, alt_11
1373 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1374 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1377 i386_output_nops (char *where
, const unsigned char *const *patt
,
1378 int count
, int max_single_nop_size
)
1381 /* Place the longer NOP first. */
1384 const unsigned char *nops
;
1386 if (max_single_nop_size
< 1)
1388 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1389 max_single_nop_size
);
1393 nops
= patt
[max_single_nop_size
- 1];
1395 /* Use the smaller one if the requsted one isn't available. */
1398 max_single_nop_size
--;
1399 nops
= patt
[max_single_nop_size
- 1];
1402 last
= count
% max_single_nop_size
;
1405 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1406 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1410 nops
= patt
[last
- 1];
1413 /* Use the smaller one plus one-byte NOP if the needed one
1416 nops
= patt
[last
- 1];
1417 memcpy (where
+ offset
, nops
, last
);
1418 where
[offset
+ last
] = *patt
[0];
1421 memcpy (where
+ offset
, nops
, last
);
1426 fits_in_imm7 (offsetT num
)
1428 return (num
& 0x7f) == num
;
1432 fits_in_imm31 (offsetT num
)
1434 return (num
& 0x7fffffff) == num
;
1437 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1438 single NOP instruction LIMIT. */
1441 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1443 const unsigned char *const *patt
= NULL
;
1444 int max_single_nop_size
;
1445 /* Maximum number of NOPs before switching to jump over NOPs. */
1446 int max_number_of_nops
;
1448 switch (fragP
->fr_type
)
1453 case rs_machine_dependent
:
1454 /* Allow NOP padding for jumps and calls. */
1455 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1456 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1463 /* We need to decide which NOP sequence to use for 32bit and
1464 64bit. When -mtune= is used:
1466 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1467 PROCESSOR_GENERIC32, f32_patt will be used.
1468 2. For the rest, alt_patt will be used.
1470 When -mtune= isn't used, alt_patt will be used if
1471 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1474 When -march= or .arch is used, we can't use anything beyond
1475 cpu_arch_isa_flags. */
1477 if (flag_code
== CODE_16BIT
)
1480 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1481 /* Limit number of NOPs to 2 in 16-bit mode. */
1482 max_number_of_nops
= 2;
1486 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1488 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1489 switch (cpu_arch_tune
)
1491 case PROCESSOR_UNKNOWN
:
1492 /* We use cpu_arch_isa_flags to check if we SHOULD
1493 optimize with nops. */
1494 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1499 case PROCESSOR_PENTIUM4
:
1500 case PROCESSOR_NOCONA
:
1501 case PROCESSOR_CORE
:
1502 case PROCESSOR_CORE2
:
1503 case PROCESSOR_COREI7
:
1504 case PROCESSOR_L1OM
:
1505 case PROCESSOR_K1OM
:
1506 case PROCESSOR_GENERIC64
:
1508 case PROCESSOR_ATHLON
:
1510 case PROCESSOR_AMDFAM10
:
1512 case PROCESSOR_ZNVER
:
1516 case PROCESSOR_I386
:
1517 case PROCESSOR_I486
:
1518 case PROCESSOR_PENTIUM
:
1519 case PROCESSOR_PENTIUMPRO
:
1520 case PROCESSOR_IAMCU
:
1521 case PROCESSOR_GENERIC32
:
1528 switch (fragP
->tc_frag_data
.tune
)
1530 case PROCESSOR_UNKNOWN
:
1531 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1532 PROCESSOR_UNKNOWN. */
1536 case PROCESSOR_I386
:
1537 case PROCESSOR_I486
:
1538 case PROCESSOR_PENTIUM
:
1539 case PROCESSOR_IAMCU
:
1541 case PROCESSOR_ATHLON
:
1543 case PROCESSOR_AMDFAM10
:
1545 case PROCESSOR_ZNVER
:
1547 case PROCESSOR_GENERIC32
:
1548 /* We use cpu_arch_isa_flags to check if we CAN optimize
1550 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1555 case PROCESSOR_PENTIUMPRO
:
1556 case PROCESSOR_PENTIUM4
:
1557 case PROCESSOR_NOCONA
:
1558 case PROCESSOR_CORE
:
1559 case PROCESSOR_CORE2
:
1560 case PROCESSOR_COREI7
:
1561 case PROCESSOR_L1OM
:
1562 case PROCESSOR_K1OM
:
1563 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1568 case PROCESSOR_GENERIC64
:
1574 if (patt
== f32_patt
)
1576 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1577 /* Limit number of NOPs to 2 for older processors. */
1578 max_number_of_nops
= 2;
1582 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1583 /* Limit number of NOPs to 7 for newer processors. */
1584 max_number_of_nops
= 7;
1589 limit
= max_single_nop_size
;
1591 if (fragP
->fr_type
== rs_fill_nop
)
1593 /* Output NOPs for .nop directive. */
1594 if (limit
> max_single_nop_size
)
1596 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1597 _("invalid single nop size: %d "
1598 "(expect within [0, %d])"),
1599 limit
, max_single_nop_size
);
1603 else if (fragP
->fr_type
!= rs_machine_dependent
)
1604 fragP
->fr_var
= count
;
1606 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1608 /* Generate jump over NOPs. */
1609 offsetT disp
= count
- 2;
1610 if (fits_in_imm7 (disp
))
1612 /* Use "jmp disp8" if possible. */
1614 where
[0] = jump_disp8
[0];
1620 unsigned int size_of_jump
;
1622 if (flag_code
== CODE_16BIT
)
1624 where
[0] = jump16_disp32
[0];
1625 where
[1] = jump16_disp32
[1];
1630 where
[0] = jump32_disp32
[0];
1634 count
-= size_of_jump
+ 4;
1635 if (!fits_in_imm31 (count
))
1637 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1638 _("jump over nop padding out of range"));
1642 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1643 where
+= size_of_jump
+ 4;
1647 /* Generate multiple NOPs. */
1648 i386_output_nops (where
, patt
, count
, limit
);
1652 operand_type_all_zero (const union i386_operand_type
*x
)
1654 switch (ARRAY_SIZE(x
->array
))
1665 return !x
->array
[0];
1672 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1674 switch (ARRAY_SIZE(x
->array
))
1690 x
->bitfield
.class = ClassNone
;
1691 x
->bitfield
.instance
= InstanceNone
;
1695 operand_type_equal (const union i386_operand_type
*x
,
1696 const union i386_operand_type
*y
)
1698 switch (ARRAY_SIZE(x
->array
))
1701 if (x
->array
[2] != y
->array
[2])
1705 if (x
->array
[1] != y
->array
[1])
1709 return x
->array
[0] == y
->array
[0];
1717 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1719 switch (ARRAY_SIZE(x
->array
))
1734 return !x
->array
[0];
1741 cpu_flags_equal (const union i386_cpu_flags
*x
,
1742 const union i386_cpu_flags
*y
)
1744 switch (ARRAY_SIZE(x
->array
))
1747 if (x
->array
[3] != y
->array
[3])
1751 if (x
->array
[2] != y
->array
[2])
1755 if (x
->array
[1] != y
->array
[1])
1759 return x
->array
[0] == y
->array
[0];
1767 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1769 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1770 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1773 static INLINE i386_cpu_flags
1774 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[3] &= y
.array
[3];
1782 x
.array
[2] &= y
.array
[2];
1785 x
.array
[1] &= y
.array
[1];
1788 x
.array
[0] &= y
.array
[0];
1796 static INLINE i386_cpu_flags
1797 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1799 switch (ARRAY_SIZE (x
.array
))
1802 x
.array
[3] |= y
.array
[3];
1805 x
.array
[2] |= y
.array
[2];
1808 x
.array
[1] |= y
.array
[1];
1811 x
.array
[0] |= y
.array
[0];
1819 static INLINE i386_cpu_flags
1820 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1822 switch (ARRAY_SIZE (x
.array
))
1825 x
.array
[3] &= ~y
.array
[3];
1828 x
.array
[2] &= ~y
.array
[2];
1831 x
.array
[1] &= ~y
.array
[1];
1834 x
.array
[0] &= ~y
.array
[0];
1842 #define CPU_FLAGS_ARCH_MATCH 0x1
1843 #define CPU_FLAGS_64BIT_MATCH 0x2
1845 #define CPU_FLAGS_PERFECT_MATCH \
1846 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1848 /* Return CPU flags match bits. */
1851 cpu_flags_match (const insn_template
*t
)
1853 i386_cpu_flags x
= t
->cpu_flags
;
1854 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1856 x
.bitfield
.cpu64
= 0;
1857 x
.bitfield
.cpuno64
= 0;
1859 if (cpu_flags_all_zero (&x
))
1861 /* This instruction is available on all archs. */
1862 match
|= CPU_FLAGS_ARCH_MATCH
;
1866 /* This instruction is available only on some archs. */
1867 i386_cpu_flags cpu
= cpu_arch_flags
;
1869 /* AVX512VL is no standalone feature - match it and then strip it. */
1870 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1872 x
.bitfield
.cpuavx512vl
= 0;
1874 cpu
= cpu_flags_and (x
, cpu
);
1875 if (!cpu_flags_all_zero (&cpu
))
1877 if (x
.bitfield
.cpuavx
)
1879 /* We need to check a few extra flags with AVX. */
1880 if (cpu
.bitfield
.cpuavx
1881 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1882 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1883 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1884 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1885 match
|= CPU_FLAGS_ARCH_MATCH
;
1887 else if (x
.bitfield
.cpuavx512f
)
1889 /* We need to check a few extra flags with AVX512F. */
1890 if (cpu
.bitfield
.cpuavx512f
1891 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1892 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1893 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1894 match
|= CPU_FLAGS_ARCH_MATCH
;
1897 match
|= CPU_FLAGS_ARCH_MATCH
;
1903 static INLINE i386_operand_type
1904 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1906 if (x
.bitfield
.class != y
.bitfield
.class)
1907 x
.bitfield
.class = ClassNone
;
1908 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1909 x
.bitfield
.instance
= InstanceNone
;
1911 switch (ARRAY_SIZE (x
.array
))
1914 x
.array
[2] &= y
.array
[2];
1917 x
.array
[1] &= y
.array
[1];
1920 x
.array
[0] &= y
.array
[0];
1928 static INLINE i386_operand_type
1929 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1931 gas_assert (y
.bitfield
.class == ClassNone
);
1932 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1934 switch (ARRAY_SIZE (x
.array
))
1937 x
.array
[2] &= ~y
.array
[2];
1940 x
.array
[1] &= ~y
.array
[1];
1943 x
.array
[0] &= ~y
.array
[0];
1951 static INLINE i386_operand_type
1952 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1954 gas_assert (x
.bitfield
.class == ClassNone
||
1955 y
.bitfield
.class == ClassNone
||
1956 x
.bitfield
.class == y
.bitfield
.class);
1957 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1958 y
.bitfield
.instance
== InstanceNone
||
1959 x
.bitfield
.instance
== y
.bitfield
.instance
);
1961 switch (ARRAY_SIZE (x
.array
))
1964 x
.array
[2] |= y
.array
[2];
1967 x
.array
[1] |= y
.array
[1];
1970 x
.array
[0] |= y
.array
[0];
1978 static INLINE i386_operand_type
1979 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1981 gas_assert (y
.bitfield
.class == ClassNone
);
1982 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1984 switch (ARRAY_SIZE (x
.array
))
1987 x
.array
[2] ^= y
.array
[2];
1990 x
.array
[1] ^= y
.array
[1];
1993 x
.array
[0] ^= y
.array
[0];
2001 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2002 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2003 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2004 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2005 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2006 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2007 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2008 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2009 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2010 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2011 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2012 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2013 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2014 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2015 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2016 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2017 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2028 operand_type_check (i386_operand_type t
, enum operand_type c
)
2033 return t
.bitfield
.class == Reg
;
2036 return (t
.bitfield
.imm8
2040 || t
.bitfield
.imm32s
2041 || t
.bitfield
.imm64
);
2044 return (t
.bitfield
.disp8
2045 || t
.bitfield
.disp16
2046 || t
.bitfield
.disp32
2047 || t
.bitfield
.disp32s
2048 || t
.bitfield
.disp64
);
2051 return (t
.bitfield
.disp8
2052 || t
.bitfield
.disp16
2053 || t
.bitfield
.disp32
2054 || t
.bitfield
.disp32s
2055 || t
.bitfield
.disp64
2056 || t
.bitfield
.baseindex
);
2065 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2066 between operand GIVEN and opeand WANTED for instruction template T. */
2069 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2072 return !((i
.types
[given
].bitfield
.byte
2073 && !t
->operand_types
[wanted
].bitfield
.byte
)
2074 || (i
.types
[given
].bitfield
.word
2075 && !t
->operand_types
[wanted
].bitfield
.word
)
2076 || (i
.types
[given
].bitfield
.dword
2077 && !t
->operand_types
[wanted
].bitfield
.dword
)
2078 || (i
.types
[given
].bitfield
.qword
2079 && !t
->operand_types
[wanted
].bitfield
.qword
)
2080 || (i
.types
[given
].bitfield
.tbyte
2081 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2084 /* Return 1 if there is no conflict in SIMD register between operand
2085 GIVEN and opeand WANTED for instruction template T. */
2088 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2091 return !((i
.types
[given
].bitfield
.xmmword
2092 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2093 || (i
.types
[given
].bitfield
.ymmword
2094 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2095 || (i
.types
[given
].bitfield
.zmmword
2096 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2099 /* Return 1 if there is no conflict in any size between operand GIVEN
2100 and opeand WANTED for instruction template T. */
2103 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2106 return (match_operand_size (t
, wanted
, given
)
2107 && !((i
.types
[given
].bitfield
.unspecified
2109 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2110 || (i
.types
[given
].bitfield
.fword
2111 && !t
->operand_types
[wanted
].bitfield
.fword
)
2112 /* For scalar opcode templates to allow register and memory
2113 operands at the same time, some special casing is needed
2114 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2115 down-conversion vpmov*. */
2116 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2117 && !t
->opcode_modifier
.broadcast
2118 && (t
->operand_types
[wanted
].bitfield
.byte
2119 || t
->operand_types
[wanted
].bitfield
.word
2120 || t
->operand_types
[wanted
].bitfield
.dword
2121 || t
->operand_types
[wanted
].bitfield
.qword
))
2122 ? (i
.types
[given
].bitfield
.xmmword
2123 || i
.types
[given
].bitfield
.ymmword
2124 || i
.types
[given
].bitfield
.zmmword
)
2125 : !match_simd_size(t
, wanted
, given
))));
2128 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2129 operands for instruction template T, and it has MATCH_REVERSE set if there
2130 is no size conflict on any operands for the template with operands reversed
2131 (and the template allows for reversing in the first place). */
2133 #define MATCH_STRAIGHT 1
2134 #define MATCH_REVERSE 2
2136 static INLINE
unsigned int
2137 operand_size_match (const insn_template
*t
)
2139 unsigned int j
, match
= MATCH_STRAIGHT
;
2141 /* Don't check non-absolute jump instructions. */
2142 if (t
->opcode_modifier
.jump
2143 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2146 /* Check memory and accumulator operand size. */
2147 for (j
= 0; j
< i
.operands
; j
++)
2149 if (i
.types
[j
].bitfield
.class != Reg
2150 && i
.types
[j
].bitfield
.class != RegSIMD
2151 && t
->opcode_modifier
.anysize
)
2154 if (t
->operand_types
[j
].bitfield
.class == Reg
2155 && !match_operand_size (t
, j
, j
))
2161 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2162 && !match_simd_size (t
, j
, j
))
2168 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2169 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2175 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2182 if (!t
->opcode_modifier
.d
)
2186 i
.error
= operand_size_mismatch
;
2190 /* Check reverse. */
2191 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2193 for (j
= 0; j
< i
.operands
; j
++)
2195 unsigned int given
= i
.operands
- j
- 1;
2197 if (t
->operand_types
[j
].bitfield
.class == Reg
2198 && !match_operand_size (t
, j
, given
))
2201 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2202 && !match_simd_size (t
, j
, given
))
2205 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2206 && (!match_operand_size (t
, j
, given
)
2207 || !match_simd_size (t
, j
, given
)))
2210 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2214 return match
| MATCH_REVERSE
;
2218 operand_type_match (i386_operand_type overlap
,
2219 i386_operand_type given
)
2221 i386_operand_type temp
= overlap
;
2223 temp
.bitfield
.unspecified
= 0;
2224 temp
.bitfield
.byte
= 0;
2225 temp
.bitfield
.word
= 0;
2226 temp
.bitfield
.dword
= 0;
2227 temp
.bitfield
.fword
= 0;
2228 temp
.bitfield
.qword
= 0;
2229 temp
.bitfield
.tbyte
= 0;
2230 temp
.bitfield
.xmmword
= 0;
2231 temp
.bitfield
.ymmword
= 0;
2232 temp
.bitfield
.zmmword
= 0;
2233 if (operand_type_all_zero (&temp
))
2236 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2240 i
.error
= operand_type_mismatch
;
2244 /* If given types g0 and g1 are registers they must be of the same type
2245 unless the expected operand type register overlap is null.
2246 Memory operand size of certain SIMD instructions is also being checked
2250 operand_type_register_match (i386_operand_type g0
,
2251 i386_operand_type t0
,
2252 i386_operand_type g1
,
2253 i386_operand_type t1
)
2255 if (g0
.bitfield
.class != Reg
2256 && g0
.bitfield
.class != RegSIMD
2257 && (!operand_type_check (g0
, anymem
)
2258 || g0
.bitfield
.unspecified
2259 || t0
.bitfield
.class != RegSIMD
))
2262 if (g1
.bitfield
.class != Reg
2263 && g1
.bitfield
.class != RegSIMD
2264 && (!operand_type_check (g1
, anymem
)
2265 || g1
.bitfield
.unspecified
2266 || t1
.bitfield
.class != RegSIMD
))
2269 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2270 && g0
.bitfield
.word
== g1
.bitfield
.word
2271 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2272 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2273 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2274 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2275 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2278 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2279 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2280 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2281 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2282 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2283 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2284 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2287 i
.error
= register_type_mismatch
;
2292 static INLINE
unsigned int
2293 register_number (const reg_entry
*r
)
2295 unsigned int nr
= r
->reg_num
;
2297 if (r
->reg_flags
& RegRex
)
2300 if (r
->reg_flags
& RegVRex
)
2306 static INLINE
unsigned int
2307 mode_from_disp_size (i386_operand_type t
)
2309 if (t
.bitfield
.disp8
)
2311 else if (t
.bitfield
.disp16
2312 || t
.bitfield
.disp32
2313 || t
.bitfield
.disp32s
)
2320 fits_in_signed_byte (addressT num
)
2322 return num
+ 0x80 <= 0xff;
2326 fits_in_unsigned_byte (addressT num
)
2332 fits_in_unsigned_word (addressT num
)
2334 return num
<= 0xffff;
2338 fits_in_signed_word (addressT num
)
2340 return num
+ 0x8000 <= 0xffff;
2344 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2349 return num
+ 0x80000000 <= 0xffffffff;
2351 } /* fits_in_signed_long() */
2354 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2359 return num
<= 0xffffffff;
2361 } /* fits_in_unsigned_long() */
2364 fits_in_disp8 (offsetT num
)
2366 int shift
= i
.memshift
;
2372 mask
= (1 << shift
) - 1;
2374 /* Return 0 if NUM isn't properly aligned. */
2378 /* Check if NUM will fit in 8bit after shift. */
2379 return fits_in_signed_byte (num
>> shift
);
2383 fits_in_imm4 (offsetT num
)
2385 return (num
& 0xf) == num
;
2388 static i386_operand_type
2389 smallest_imm_type (offsetT num
)
2391 i386_operand_type t
;
2393 operand_type_set (&t
, 0);
2394 t
.bitfield
.imm64
= 1;
2396 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2398 /* This code is disabled on the 486 because all the Imm1 forms
2399 in the opcode table are slower on the i486. They're the
2400 versions with the implicitly specified single-position
2401 displacement, which has another syntax if you really want to
2403 t
.bitfield
.imm1
= 1;
2404 t
.bitfield
.imm8
= 1;
2405 t
.bitfield
.imm8s
= 1;
2406 t
.bitfield
.imm16
= 1;
2407 t
.bitfield
.imm32
= 1;
2408 t
.bitfield
.imm32s
= 1;
2410 else if (fits_in_signed_byte (num
))
2412 t
.bitfield
.imm8
= 1;
2413 t
.bitfield
.imm8s
= 1;
2414 t
.bitfield
.imm16
= 1;
2415 t
.bitfield
.imm32
= 1;
2416 t
.bitfield
.imm32s
= 1;
2418 else if (fits_in_unsigned_byte (num
))
2420 t
.bitfield
.imm8
= 1;
2421 t
.bitfield
.imm16
= 1;
2422 t
.bitfield
.imm32
= 1;
2423 t
.bitfield
.imm32s
= 1;
2425 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2427 t
.bitfield
.imm16
= 1;
2428 t
.bitfield
.imm32
= 1;
2429 t
.bitfield
.imm32s
= 1;
2431 else if (fits_in_signed_long (num
))
2433 t
.bitfield
.imm32
= 1;
2434 t
.bitfield
.imm32s
= 1;
2436 else if (fits_in_unsigned_long (num
))
2437 t
.bitfield
.imm32
= 1;
2443 offset_in_range (offsetT val
, int size
)
2449 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2450 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2451 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2453 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2459 /* If BFD64, sign extend val for 32bit address mode. */
2460 if (flag_code
!= CODE_64BIT
2461 || i
.prefix
[ADDR_PREFIX
])
2462 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2463 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2466 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2468 char buf1
[40], buf2
[40];
2470 sprint_value (buf1
, val
);
2471 sprint_value (buf2
, val
& mask
);
2472 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2487 a. PREFIX_EXIST if attempting to add a prefix where one from the
2488 same class already exists.
2489 b. PREFIX_LOCK if lock prefix is added.
2490 c. PREFIX_REP if rep/repne prefix is added.
2491 d. PREFIX_DS if ds prefix is added.
2492 e. PREFIX_OTHER if other prefix is added.
2495 static enum PREFIX_GROUP
2496 add_prefix (unsigned int prefix
)
2498 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2501 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2502 && flag_code
== CODE_64BIT
)
2504 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2505 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2506 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2507 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2518 case DS_PREFIX_OPCODE
:
2521 case CS_PREFIX_OPCODE
:
2522 case ES_PREFIX_OPCODE
:
2523 case FS_PREFIX_OPCODE
:
2524 case GS_PREFIX_OPCODE
:
2525 case SS_PREFIX_OPCODE
:
2529 case REPNE_PREFIX_OPCODE
:
2530 case REPE_PREFIX_OPCODE
:
2535 case LOCK_PREFIX_OPCODE
:
2544 case ADDR_PREFIX_OPCODE
:
2548 case DATA_PREFIX_OPCODE
:
2552 if (i
.prefix
[q
] != 0)
2560 i
.prefix
[q
] |= prefix
;
2563 as_bad (_("same type of prefix used twice"));
2569 update_code_flag (int value
, int check
)
2571 PRINTF_LIKE ((*as_error
));
2573 flag_code
= (enum flag_code
) value
;
2574 if (flag_code
== CODE_64BIT
)
2576 cpu_arch_flags
.bitfield
.cpu64
= 1;
2577 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2581 cpu_arch_flags
.bitfield
.cpu64
= 0;
2582 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2584 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2587 as_error
= as_fatal
;
2590 (*as_error
) (_("64bit mode not supported on `%s'."),
2591 cpu_arch_name
? cpu_arch_name
: default_arch
);
2593 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2596 as_error
= as_fatal
;
2599 (*as_error
) (_("32bit mode not supported on `%s'."),
2600 cpu_arch_name
? cpu_arch_name
: default_arch
);
2602 stackop_size
= '\0';
2606 set_code_flag (int value
)
2608 update_code_flag (value
, 0);
2612 set_16bit_gcc_code_flag (int new_code_flag
)
2614 flag_code
= (enum flag_code
) new_code_flag
;
2615 if (flag_code
!= CODE_16BIT
)
2617 cpu_arch_flags
.bitfield
.cpu64
= 0;
2618 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2619 stackop_size
= LONG_MNEM_SUFFIX
;
2623 set_intel_syntax (int syntax_flag
)
2625 /* Find out if register prefixing is specified. */
2626 int ask_naked_reg
= 0;
2629 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2632 int e
= get_symbol_name (&string
);
2634 if (strcmp (string
, "prefix") == 0)
2636 else if (strcmp (string
, "noprefix") == 0)
2639 as_bad (_("bad argument to syntax directive."));
2640 (void) restore_line_pointer (e
);
2642 demand_empty_rest_of_line ();
2644 intel_syntax
= syntax_flag
;
2646 if (ask_naked_reg
== 0)
2647 allow_naked_reg
= (intel_syntax
2648 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2650 allow_naked_reg
= (ask_naked_reg
< 0);
2652 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2654 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2655 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2656 register_prefix
= allow_naked_reg
? "" : "%";
2660 set_intel_mnemonic (int mnemonic_flag
)
2662 intel_mnemonic
= mnemonic_flag
;
2666 set_allow_index_reg (int flag
)
2668 allow_index_reg
= flag
;
2672 set_check (int what
)
2674 enum check_kind
*kind
;
2679 kind
= &operand_check
;
2690 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2693 int e
= get_symbol_name (&string
);
2695 if (strcmp (string
, "none") == 0)
2697 else if (strcmp (string
, "warning") == 0)
2698 *kind
= check_warning
;
2699 else if (strcmp (string
, "error") == 0)
2700 *kind
= check_error
;
2702 as_bad (_("bad argument to %s_check directive."), str
);
2703 (void) restore_line_pointer (e
);
2706 as_bad (_("missing argument for %s_check directive"), str
);
2708 demand_empty_rest_of_line ();
2712 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2713 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2715 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2716 static const char *arch
;
2718 /* Intel LIOM is only supported on ELF. */
2724 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2725 use default_arch. */
2726 arch
= cpu_arch_name
;
2728 arch
= default_arch
;
2731 /* If we are targeting Intel MCU, we must enable it. */
2732 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2733 || new_flag
.bitfield
.cpuiamcu
)
2736 /* If we are targeting Intel L1OM, we must enable it. */
2737 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2738 || new_flag
.bitfield
.cpul1om
)
2741 /* If we are targeting Intel K1OM, we must enable it. */
2742 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2743 || new_flag
.bitfield
.cpuk1om
)
2746 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2751 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2755 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2758 int e
= get_symbol_name (&string
);
2760 i386_cpu_flags flags
;
2762 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2764 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2766 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2770 cpu_arch_name
= cpu_arch
[j
].name
;
2771 cpu_sub_arch_name
= NULL
;
2772 cpu_arch_flags
= cpu_arch
[j
].flags
;
2773 if (flag_code
== CODE_64BIT
)
2775 cpu_arch_flags
.bitfield
.cpu64
= 1;
2776 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2780 cpu_arch_flags
.bitfield
.cpu64
= 0;
2781 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2783 cpu_arch_isa
= cpu_arch
[j
].type
;
2784 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2785 if (!cpu_arch_tune_set
)
2787 cpu_arch_tune
= cpu_arch_isa
;
2788 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2793 flags
= cpu_flags_or (cpu_arch_flags
,
2796 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2798 if (cpu_sub_arch_name
)
2800 char *name
= cpu_sub_arch_name
;
2801 cpu_sub_arch_name
= concat (name
,
2803 (const char *) NULL
);
2807 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2808 cpu_arch_flags
= flags
;
2809 cpu_arch_isa_flags
= flags
;
2813 = cpu_flags_or (cpu_arch_isa_flags
,
2815 (void) restore_line_pointer (e
);
2816 demand_empty_rest_of_line ();
2821 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2823 /* Disable an ISA extension. */
2824 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2825 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2827 flags
= cpu_flags_and_not (cpu_arch_flags
,
2828 cpu_noarch
[j
].flags
);
2829 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2831 if (cpu_sub_arch_name
)
2833 char *name
= cpu_sub_arch_name
;
2834 cpu_sub_arch_name
= concat (name
, string
,
2835 (const char *) NULL
);
2839 cpu_sub_arch_name
= xstrdup (string
);
2840 cpu_arch_flags
= flags
;
2841 cpu_arch_isa_flags
= flags
;
2843 (void) restore_line_pointer (e
);
2844 demand_empty_rest_of_line ();
2848 j
= ARRAY_SIZE (cpu_arch
);
2851 if (j
>= ARRAY_SIZE (cpu_arch
))
2852 as_bad (_("no such architecture: `%s'"), string
);
2854 *input_line_pointer
= e
;
2857 as_bad (_("missing cpu architecture"));
2859 no_cond_jump_promotion
= 0;
2860 if (*input_line_pointer
== ','
2861 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2866 ++input_line_pointer
;
2867 e
= get_symbol_name (&string
);
2869 if (strcmp (string
, "nojumps") == 0)
2870 no_cond_jump_promotion
= 1;
2871 else if (strcmp (string
, "jumps") == 0)
2874 as_bad (_("no such architecture modifier: `%s'"), string
);
2876 (void) restore_line_pointer (e
);
2879 demand_empty_rest_of_line ();
2882 enum bfd_architecture
2885 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2887 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2888 || flag_code
!= CODE_64BIT
)
2889 as_fatal (_("Intel L1OM is 64bit ELF only"));
2890 return bfd_arch_l1om
;
2892 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2894 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2895 || flag_code
!= CODE_64BIT
)
2896 as_fatal (_("Intel K1OM is 64bit ELF only"));
2897 return bfd_arch_k1om
;
2899 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2901 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2902 || flag_code
== CODE_64BIT
)
2903 as_fatal (_("Intel MCU is 32bit ELF only"));
2904 return bfd_arch_iamcu
;
2907 return bfd_arch_i386
;
2913 if (!strncmp (default_arch
, "x86_64", 6))
2915 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2917 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2918 || default_arch
[6] != '\0')
2919 as_fatal (_("Intel L1OM is 64bit ELF only"));
2920 return bfd_mach_l1om
;
2922 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2924 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2925 || default_arch
[6] != '\0')
2926 as_fatal (_("Intel K1OM is 64bit ELF only"));
2927 return bfd_mach_k1om
;
2929 else if (default_arch
[6] == '\0')
2930 return bfd_mach_x86_64
;
2932 return bfd_mach_x64_32
;
2934 else if (!strcmp (default_arch
, "i386")
2935 || !strcmp (default_arch
, "iamcu"))
2937 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2939 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2940 as_fatal (_("Intel MCU is 32bit ELF only"));
2941 return bfd_mach_i386_iamcu
;
2944 return bfd_mach_i386_i386
;
2947 as_fatal (_("unknown architecture"));
2953 const char *hash_err
;
2955 /* Support pseudo prefixes like {disp32}. */
2956 lex_type
['{'] = LEX_BEGIN_NAME
;
2958 /* Initialize op_hash hash table. */
2959 op_hash
= hash_new ();
2962 const insn_template
*optab
;
2963 templates
*core_optab
;
2965 /* Setup for loop. */
2967 core_optab
= XNEW (templates
);
2968 core_optab
->start
= optab
;
2973 if (optab
->name
== NULL
2974 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2976 /* different name --> ship out current template list;
2977 add to hash table; & begin anew. */
2978 core_optab
->end
= optab
;
2979 hash_err
= hash_insert (op_hash
,
2981 (void *) core_optab
);
2984 as_fatal (_("can't hash %s: %s"),
2988 if (optab
->name
== NULL
)
2990 core_optab
= XNEW (templates
);
2991 core_optab
->start
= optab
;
2996 /* Initialize reg_hash hash table. */
2997 reg_hash
= hash_new ();
2999 const reg_entry
*regtab
;
3000 unsigned int regtab_size
= i386_regtab_size
;
3002 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3004 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3006 as_fatal (_("can't hash %s: %s"),
3012 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3017 for (c
= 0; c
< 256; c
++)
3022 mnemonic_chars
[c
] = c
;
3023 register_chars
[c
] = c
;
3024 operand_chars
[c
] = c
;
3026 else if (ISLOWER (c
))
3028 mnemonic_chars
[c
] = c
;
3029 register_chars
[c
] = c
;
3030 operand_chars
[c
] = c
;
3032 else if (ISUPPER (c
))
3034 mnemonic_chars
[c
] = TOLOWER (c
);
3035 register_chars
[c
] = mnemonic_chars
[c
];
3036 operand_chars
[c
] = c
;
3038 else if (c
== '{' || c
== '}')
3040 mnemonic_chars
[c
] = c
;
3041 operand_chars
[c
] = c
;
3044 if (ISALPHA (c
) || ISDIGIT (c
))
3045 identifier_chars
[c
] = c
;
3048 identifier_chars
[c
] = c
;
3049 operand_chars
[c
] = c
;
3054 identifier_chars
['@'] = '@';
3057 identifier_chars
['?'] = '?';
3058 operand_chars
['?'] = '?';
3060 digit_chars
['-'] = '-';
3061 mnemonic_chars
['_'] = '_';
3062 mnemonic_chars
['-'] = '-';
3063 mnemonic_chars
['.'] = '.';
3064 identifier_chars
['_'] = '_';
3065 identifier_chars
['.'] = '.';
3067 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3068 operand_chars
[(unsigned char) *p
] = *p
;
3071 if (flag_code
== CODE_64BIT
)
3073 #if defined (OBJ_COFF) && defined (TE_PE)
3074 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3077 x86_dwarf2_return_column
= 16;
3079 x86_cie_data_alignment
= -8;
3083 x86_dwarf2_return_column
= 8;
3084 x86_cie_data_alignment
= -4;
3087 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3088 can be turned into BRANCH_PREFIX frag. */
3089 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3094 i386_print_statistics (FILE *file
)
3096 hash_print_statistics (file
, "i386 opcode", op_hash
);
3097 hash_print_statistics (file
, "i386 register", reg_hash
);
3102 /* Debugging routines for md_assemble. */
3103 static void pte (insn_template
*);
3104 static void pt (i386_operand_type
);
3105 static void pe (expressionS
*);
3106 static void ps (symbolS
*);
3109 pi (const char *line
, i386_insn
*x
)
3113 fprintf (stdout
, "%s: template ", line
);
3115 fprintf (stdout
, " address: base %s index %s scale %x\n",
3116 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3117 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3118 x
->log2_scale_factor
);
3119 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3120 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3121 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3122 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3123 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3124 (x
->rex
& REX_W
) != 0,
3125 (x
->rex
& REX_R
) != 0,
3126 (x
->rex
& REX_X
) != 0,
3127 (x
->rex
& REX_B
) != 0);
3128 for (j
= 0; j
< x
->operands
; j
++)
3130 fprintf (stdout
, " #%d: ", j
+ 1);
3132 fprintf (stdout
, "\n");
3133 if (x
->types
[j
].bitfield
.class == Reg
3134 || x
->types
[j
].bitfield
.class == RegMMX
3135 || x
->types
[j
].bitfield
.class == RegSIMD
3136 || x
->types
[j
].bitfield
.class == SReg
3137 || x
->types
[j
].bitfield
.class == RegCR
3138 || x
->types
[j
].bitfield
.class == RegDR
3139 || x
->types
[j
].bitfield
.class == RegTR
)
3140 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3141 if (operand_type_check (x
->types
[j
], imm
))
3143 if (operand_type_check (x
->types
[j
], disp
))
3144 pe (x
->op
[j
].disps
);
3149 pte (insn_template
*t
)
3152 fprintf (stdout
, " %d operands ", t
->operands
);
3153 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3154 if (t
->extension_opcode
!= None
)
3155 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3156 if (t
->opcode_modifier
.d
)
3157 fprintf (stdout
, "D");
3158 if (t
->opcode_modifier
.w
)
3159 fprintf (stdout
, "W");
3160 fprintf (stdout
, "\n");
3161 for (j
= 0; j
< t
->operands
; j
++)
3163 fprintf (stdout
, " #%d type ", j
+ 1);
3164 pt (t
->operand_types
[j
]);
3165 fprintf (stdout
, "\n");
3172 fprintf (stdout
, " operation %d\n", e
->X_op
);
3173 fprintf (stdout
, " add_number %ld (%lx)\n",
3174 (long) e
->X_add_number
, (long) e
->X_add_number
);
3175 if (e
->X_add_symbol
)
3177 fprintf (stdout
, " add_symbol ");
3178 ps (e
->X_add_symbol
);
3179 fprintf (stdout
, "\n");
3183 fprintf (stdout
, " op_symbol ");
3184 ps (e
->X_op_symbol
);
3185 fprintf (stdout
, "\n");
3192 fprintf (stdout
, "%s type %s%s",
3194 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3195 segment_name (S_GET_SEGMENT (s
)));
3198 static struct type_name
3200 i386_operand_type mask
;
3203 const type_names
[] =
3205 { OPERAND_TYPE_REG8
, "r8" },
3206 { OPERAND_TYPE_REG16
, "r16" },
3207 { OPERAND_TYPE_REG32
, "r32" },
3208 { OPERAND_TYPE_REG64
, "r64" },
3209 { OPERAND_TYPE_ACC8
, "acc8" },
3210 { OPERAND_TYPE_ACC16
, "acc16" },
3211 { OPERAND_TYPE_ACC32
, "acc32" },
3212 { OPERAND_TYPE_ACC64
, "acc64" },
3213 { OPERAND_TYPE_IMM8
, "i8" },
3214 { OPERAND_TYPE_IMM8
, "i8s" },
3215 { OPERAND_TYPE_IMM16
, "i16" },
3216 { OPERAND_TYPE_IMM32
, "i32" },
3217 { OPERAND_TYPE_IMM32S
, "i32s" },
3218 { OPERAND_TYPE_IMM64
, "i64" },
3219 { OPERAND_TYPE_IMM1
, "i1" },
3220 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3221 { OPERAND_TYPE_DISP8
, "d8" },
3222 { OPERAND_TYPE_DISP16
, "d16" },
3223 { OPERAND_TYPE_DISP32
, "d32" },
3224 { OPERAND_TYPE_DISP32S
, "d32s" },
3225 { OPERAND_TYPE_DISP64
, "d64" },
3226 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3227 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3228 { OPERAND_TYPE_CONTROL
, "control reg" },
3229 { OPERAND_TYPE_TEST
, "test reg" },
3230 { OPERAND_TYPE_DEBUG
, "debug reg" },
3231 { OPERAND_TYPE_FLOATREG
, "FReg" },
3232 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3233 { OPERAND_TYPE_SREG
, "SReg" },
3234 { OPERAND_TYPE_REGMMX
, "rMMX" },
3235 { OPERAND_TYPE_REGXMM
, "rXMM" },
3236 { OPERAND_TYPE_REGYMM
, "rYMM" },
3237 { OPERAND_TYPE_REGZMM
, "rZMM" },
3238 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3242 pt (i386_operand_type t
)
3245 i386_operand_type a
;
3247 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3249 a
= operand_type_and (t
, type_names
[j
].mask
);
3250 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3251 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3256 #endif /* DEBUG386 */
3258 static bfd_reloc_code_real_type
3259 reloc (unsigned int size
,
3262 bfd_reloc_code_real_type other
)
3264 if (other
!= NO_RELOC
)
3266 reloc_howto_type
*rel
;
3271 case BFD_RELOC_X86_64_GOT32
:
3272 return BFD_RELOC_X86_64_GOT64
;
3274 case BFD_RELOC_X86_64_GOTPLT64
:
3275 return BFD_RELOC_X86_64_GOTPLT64
;
3277 case BFD_RELOC_X86_64_PLTOFF64
:
3278 return BFD_RELOC_X86_64_PLTOFF64
;
3280 case BFD_RELOC_X86_64_GOTPC32
:
3281 other
= BFD_RELOC_X86_64_GOTPC64
;
3283 case BFD_RELOC_X86_64_GOTPCREL
:
3284 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3286 case BFD_RELOC_X86_64_TPOFF32
:
3287 other
= BFD_RELOC_X86_64_TPOFF64
;
3289 case BFD_RELOC_X86_64_DTPOFF32
:
3290 other
= BFD_RELOC_X86_64_DTPOFF64
;
3296 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3297 if (other
== BFD_RELOC_SIZE32
)
3300 other
= BFD_RELOC_SIZE64
;
3303 as_bad (_("there are no pc-relative size relocations"));
3309 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3310 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3313 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3315 as_bad (_("unknown relocation (%u)"), other
);
3316 else if (size
!= bfd_get_reloc_size (rel
))
3317 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3318 bfd_get_reloc_size (rel
),
3320 else if (pcrel
&& !rel
->pc_relative
)
3321 as_bad (_("non-pc-relative relocation for pc-relative field"));
3322 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3324 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3326 as_bad (_("relocated field and relocation type differ in signedness"));
3335 as_bad (_("there are no unsigned pc-relative relocations"));
3338 case 1: return BFD_RELOC_8_PCREL
;
3339 case 2: return BFD_RELOC_16_PCREL
;
3340 case 4: return BFD_RELOC_32_PCREL
;
3341 case 8: return BFD_RELOC_64_PCREL
;
3343 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3350 case 4: return BFD_RELOC_X86_64_32S
;
3355 case 1: return BFD_RELOC_8
;
3356 case 2: return BFD_RELOC_16
;
3357 case 4: return BFD_RELOC_32
;
3358 case 8: return BFD_RELOC_64
;
3360 as_bad (_("cannot do %s %u byte relocation"),
3361 sign
> 0 ? "signed" : "unsigned", size
);
3367 /* Here we decide which fixups can be adjusted to make them relative to
3368 the beginning of the section instead of the symbol. Basically we need
3369 to make sure that the dynamic relocations are done correctly, so in
3370 some cases we force the original symbol to be used. */
3373 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3379 /* Don't adjust pc-relative references to merge sections in 64-bit
3381 if (use_rela_relocations
3382 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3386 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3387 and changed later by validate_fix. */
3388 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3389 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3392 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3393 for size relocations. */
3394 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3395 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3396 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3397 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3398 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3399 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3400 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3401 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3402 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3403 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3404 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3405 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3410 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3411 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3412 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3413 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3414 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3415 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3425 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3426 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3433 intel_float_operand (const char *mnemonic
)
3435 /* Note that the value returned is meaningful only for opcodes with (memory)
3436 operands, hence the code here is free to improperly handle opcodes that
3437 have no operands (for better performance and smaller code). */
3439 if (mnemonic
[0] != 'f')
3440 return 0; /* non-math */
3442 switch (mnemonic
[1])
3444 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3445 the fs segment override prefix not currently handled because no
3446 call path can make opcodes without operands get here */
3448 return 2 /* integer op */;
3450 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3451 return 3; /* fldcw/fldenv */
3454 if (mnemonic
[2] != 'o' /* fnop */)
3455 return 3; /* non-waiting control op */
3458 if (mnemonic
[2] == 's')
3459 return 3; /* frstor/frstpm */
3462 if (mnemonic
[2] == 'a')
3463 return 3; /* fsave */
3464 if (mnemonic
[2] == 't')
3466 switch (mnemonic
[3])
3468 case 'c': /* fstcw */
3469 case 'd': /* fstdw */
3470 case 'e': /* fstenv */
3471 case 's': /* fsts[gw] */
3477 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3478 return 0; /* fxsave/fxrstor are not really math ops */
3485 /* Build the VEX prefix. */
3488 build_vex_prefix (const insn_template
*t
)
3490 unsigned int register_specifier
;
3491 unsigned int implied_prefix
;
3492 unsigned int vector_length
;
3495 /* Check register specifier. */
3496 if (i
.vex
.register_specifier
)
3498 register_specifier
=
3499 ~register_number (i
.vex
.register_specifier
) & 0xf;
3500 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3503 register_specifier
= 0xf;
3505 /* Use 2-byte VEX prefix by swapping destination and source operand
3506 if there are more than 1 register operand. */
3507 if (i
.reg_operands
> 1
3508 && i
.vec_encoding
!= vex_encoding_vex3
3509 && i
.dir_encoding
== dir_encoding_default
3510 && i
.operands
== i
.reg_operands
3511 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3512 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3513 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3516 unsigned int xchg
= i
.operands
- 1;
3517 union i386_op temp_op
;
3518 i386_operand_type temp_type
;
3520 temp_type
= i
.types
[xchg
];
3521 i
.types
[xchg
] = i
.types
[0];
3522 i
.types
[0] = temp_type
;
3523 temp_op
= i
.op
[xchg
];
3524 i
.op
[xchg
] = i
.op
[0];
3527 gas_assert (i
.rm
.mode
== 3);
3531 i
.rm
.regmem
= i
.rm
.reg
;
3534 if (i
.tm
.opcode_modifier
.d
)
3535 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3536 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3537 else /* Use the next insn. */
3541 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3542 are no memory operands and at least 3 register ones. */
3543 if (i
.reg_operands
>= 3
3544 && i
.vec_encoding
!= vex_encoding_vex3
3545 && i
.reg_operands
== i
.operands
- i
.imm_operands
3546 && i
.tm
.opcode_modifier
.vex
3547 && i
.tm
.opcode_modifier
.commutative
3548 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3550 && i
.vex
.register_specifier
3551 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3553 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3554 union i386_op temp_op
;
3555 i386_operand_type temp_type
;
3557 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3558 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3559 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3560 &i
.types
[i
.operands
- 3]));
3561 gas_assert (i
.rm
.mode
== 3);
3563 temp_type
= i
.types
[xchg
];
3564 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3565 i
.types
[xchg
+ 1] = temp_type
;
3566 temp_op
= i
.op
[xchg
];
3567 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3568 i
.op
[xchg
+ 1] = temp_op
;
3571 xchg
= i
.rm
.regmem
| 8;
3572 i
.rm
.regmem
= ~register_specifier
& 0xf;
3573 gas_assert (!(i
.rm
.regmem
& 8));
3574 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3575 register_specifier
= ~xchg
& 0xf;
3578 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3579 vector_length
= avxscalar
;
3580 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3586 /* Determine vector length from the last multi-length vector
3589 for (op
= t
->operands
; op
--;)
3590 if (t
->operand_types
[op
].bitfield
.xmmword
3591 && t
->operand_types
[op
].bitfield
.ymmword
3592 && i
.types
[op
].bitfield
.ymmword
)
3599 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3604 case DATA_PREFIX_OPCODE
:
3607 case REPE_PREFIX_OPCODE
:
3610 case REPNE_PREFIX_OPCODE
:
3617 /* Check the REX.W bit and VEXW. */
3618 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3619 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3620 else if (i
.tm
.opcode_modifier
.vexw
)
3621 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3623 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3625 /* Use 2-byte VEX prefix if possible. */
3627 && i
.vec_encoding
!= vex_encoding_vex3
3628 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3629 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3631 /* 2-byte VEX prefix. */
3635 i
.vex
.bytes
[0] = 0xc5;
3637 /* Check the REX.R bit. */
3638 r
= (i
.rex
& REX_R
) ? 0 : 1;
3639 i
.vex
.bytes
[1] = (r
<< 7
3640 | register_specifier
<< 3
3641 | vector_length
<< 2
3646 /* 3-byte VEX prefix. */
3651 switch (i
.tm
.opcode_modifier
.vexopcode
)
3655 i
.vex
.bytes
[0] = 0xc4;
3659 i
.vex
.bytes
[0] = 0xc4;
3663 i
.vex
.bytes
[0] = 0xc4;
3667 i
.vex
.bytes
[0] = 0x8f;
3671 i
.vex
.bytes
[0] = 0x8f;
3675 i
.vex
.bytes
[0] = 0x8f;
3681 /* The high 3 bits of the second VEX byte are 1's compliment
3682 of RXB bits from REX. */
3683 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3685 i
.vex
.bytes
[2] = (w
<< 7
3686 | register_specifier
<< 3
3687 | vector_length
<< 2
3692 static INLINE bfd_boolean
3693 is_evex_encoding (const insn_template
*t
)
3695 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3696 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3697 || t
->opcode_modifier
.sae
;
3700 static INLINE bfd_boolean
3701 is_any_vex_encoding (const insn_template
*t
)
3703 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3704 || is_evex_encoding (t
);
3707 /* Build the EVEX prefix. */
3710 build_evex_prefix (void)
3712 unsigned int register_specifier
;
3713 unsigned int implied_prefix
;
3715 rex_byte vrex_used
= 0;
3717 /* Check register specifier. */
3718 if (i
.vex
.register_specifier
)
3720 gas_assert ((i
.vrex
& REX_X
) == 0);
3722 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3723 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3724 register_specifier
+= 8;
3725 /* The upper 16 registers are encoded in the fourth byte of the
3727 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3728 i
.vex
.bytes
[3] = 0x8;
3729 register_specifier
= ~register_specifier
& 0xf;
3733 register_specifier
= 0xf;
3735 /* Encode upper 16 vector index register in the fourth byte of
3737 if (!(i
.vrex
& REX_X
))
3738 i
.vex
.bytes
[3] = 0x8;
3743 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3748 case DATA_PREFIX_OPCODE
:
3751 case REPE_PREFIX_OPCODE
:
3754 case REPNE_PREFIX_OPCODE
:
3761 /* 4 byte EVEX prefix. */
3763 i
.vex
.bytes
[0] = 0x62;
3766 switch (i
.tm
.opcode_modifier
.vexopcode
)
3782 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3784 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3786 /* The fifth bit of the second EVEX byte is 1's compliment of the
3787 REX_R bit in VREX. */
3788 if (!(i
.vrex
& REX_R
))
3789 i
.vex
.bytes
[1] |= 0x10;
3793 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3795 /* When all operands are registers, the REX_X bit in REX is not
3796 used. We reuse it to encode the upper 16 registers, which is
3797 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3798 as 1's compliment. */
3799 if ((i
.vrex
& REX_B
))
3802 i
.vex
.bytes
[1] &= ~0x40;
3806 /* EVEX instructions shouldn't need the REX prefix. */
3807 i
.vrex
&= ~vrex_used
;
3808 gas_assert (i
.vrex
== 0);
3810 /* Check the REX.W bit and VEXW. */
3811 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3812 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3813 else if (i
.tm
.opcode_modifier
.vexw
)
3814 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3816 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3818 /* Encode the U bit. */
3819 implied_prefix
|= 0x4;
3821 /* The third byte of the EVEX prefix. */
3822 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3824 /* The fourth byte of the EVEX prefix. */
3825 /* The zeroing-masking bit. */
3826 if (i
.mask
&& i
.mask
->zeroing
)
3827 i
.vex
.bytes
[3] |= 0x80;
3829 /* Don't always set the broadcast bit if there is no RC. */
3832 /* Encode the vector length. */
3833 unsigned int vec_length
;
3835 if (!i
.tm
.opcode_modifier
.evex
3836 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3840 /* Determine vector length from the last multi-length vector
3843 for (op
= i
.operands
; op
--;)
3844 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3845 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3846 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3848 if (i
.types
[op
].bitfield
.zmmword
)
3850 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3853 else if (i
.types
[op
].bitfield
.ymmword
)
3855 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3858 else if (i
.types
[op
].bitfield
.xmmword
)
3860 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3863 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3865 switch (i
.broadcast
->bytes
)
3868 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3871 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3874 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3883 if (op
>= MAX_OPERANDS
)
3887 switch (i
.tm
.opcode_modifier
.evex
)
3889 case EVEXLIG
: /* LL' is ignored */
3890 vec_length
= evexlig
<< 5;
3893 vec_length
= 0 << 5;
3896 vec_length
= 1 << 5;
3899 vec_length
= 2 << 5;
3905 i
.vex
.bytes
[3] |= vec_length
;
3906 /* Encode the broadcast bit. */
3908 i
.vex
.bytes
[3] |= 0x10;
3912 if (i
.rounding
->type
!= saeonly
)
3913 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3915 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3918 if (i
.mask
&& i
.mask
->mask
)
3919 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3923 process_immext (void)
3927 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3928 which is coded in the same place as an 8-bit immediate field
3929 would be. Here we fake an 8-bit immediate operand from the
3930 opcode suffix stored in tm.extension_opcode.
3932 AVX instructions also use this encoding, for some of
3933 3 argument instructions. */
3935 gas_assert (i
.imm_operands
<= 1
3937 || (is_any_vex_encoding (&i
.tm
)
3938 && i
.operands
<= 4)));
3940 exp
= &im_expressions
[i
.imm_operands
++];
3941 i
.op
[i
.operands
].imms
= exp
;
3942 i
.types
[i
.operands
] = imm8
;
3944 exp
->X_op
= O_constant
;
3945 exp
->X_add_number
= i
.tm
.extension_opcode
;
3946 i
.tm
.extension_opcode
= None
;
3953 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3958 as_bad (_("invalid instruction `%s' after `%s'"),
3959 i
.tm
.name
, i
.hle_prefix
);
3962 if (i
.prefix
[LOCK_PREFIX
])
3964 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3968 case HLEPrefixRelease
:
3969 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3971 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3975 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3977 as_bad (_("memory destination needed for instruction `%s'"
3978 " after `xrelease'"), i
.tm
.name
);
3985 /* Try the shortest encoding by shortening operand size. */
3988 optimize_encoding (void)
3992 if (optimize_for_space
3993 && i
.reg_operands
== 1
3994 && i
.imm_operands
== 1
3995 && !i
.types
[1].bitfield
.byte
3996 && i
.op
[0].imms
->X_op
== O_constant
3997 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3998 && ((i
.tm
.base_opcode
== 0xa8
3999 && i
.tm
.extension_opcode
== None
)
4000 || (i
.tm
.base_opcode
== 0xf6
4001 && i
.tm
.extension_opcode
== 0x0)))
4004 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4006 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4007 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4009 i
.types
[1].bitfield
.byte
= 1;
4010 /* Ignore the suffix. */
4012 if (base_regnum
>= 4)
4014 /* Handle SP, BP, SI, DI and R12-R15 registers. */
4015 if (i
.types
[1].bitfield
.word
)
4017 else if (i
.types
[1].bitfield
.dword
)
4025 else if (flag_code
== CODE_64BIT
4026 && ((i
.types
[1].bitfield
.qword
4027 && i
.reg_operands
== 1
4028 && i
.imm_operands
== 1
4029 && i
.op
[0].imms
->X_op
== O_constant
4030 && ((i
.tm
.base_opcode
== 0xb8
4031 && i
.tm
.extension_opcode
== None
4032 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4033 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4034 && (((i
.tm
.base_opcode
== 0x24
4035 || i
.tm
.base_opcode
== 0xa8)
4036 && i
.tm
.extension_opcode
== None
)
4037 || (i
.tm
.base_opcode
== 0x80
4038 && i
.tm
.extension_opcode
== 0x4)
4039 || ((i
.tm
.base_opcode
== 0xf6
4040 || (i
.tm
.base_opcode
| 1) == 0xc7)
4041 && i
.tm
.extension_opcode
== 0x0)))
4042 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4043 && i
.tm
.base_opcode
== 0x83
4044 && i
.tm
.extension_opcode
== 0x4)))
4045 || (i
.types
[0].bitfield
.qword
4046 && ((i
.reg_operands
== 2
4047 && i
.op
[0].regs
== i
.op
[1].regs
4048 && ((i
.tm
.base_opcode
== 0x30
4049 || i
.tm
.base_opcode
== 0x28)
4050 && i
.tm
.extension_opcode
== None
))
4051 || (i
.reg_operands
== 1
4053 && i
.tm
.base_opcode
== 0x30
4054 && i
.tm
.extension_opcode
== None
)))))
4057 andq $imm31, %r64 -> andl $imm31, %r32
4058 andq $imm7, %r64 -> andl $imm7, %r32
4059 testq $imm31, %r64 -> testl $imm31, %r32
4060 xorq %r64, %r64 -> xorl %r32, %r32
4061 subq %r64, %r64 -> subl %r32, %r32
4062 movq $imm31, %r64 -> movl $imm31, %r32
4063 movq $imm32, %r64 -> movl $imm32, %r32
4065 i
.tm
.opcode_modifier
.norex64
= 1;
4066 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4069 movq $imm31, %r64 -> movl $imm31, %r32
4070 movq $imm32, %r64 -> movl $imm32, %r32
4072 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4073 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4074 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4075 i
.types
[0].bitfield
.imm32
= 1;
4076 i
.types
[0].bitfield
.imm32s
= 0;
4077 i
.types
[0].bitfield
.imm64
= 0;
4078 i
.types
[1].bitfield
.dword
= 1;
4079 i
.types
[1].bitfield
.qword
= 0;
4080 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4083 movq $imm31, %r64 -> movl $imm31, %r32
4085 i
.tm
.base_opcode
= 0xb8;
4086 i
.tm
.extension_opcode
= None
;
4087 i
.tm
.opcode_modifier
.w
= 0;
4088 i
.tm
.opcode_modifier
.shortform
= 1;
4089 i
.tm
.opcode_modifier
.modrm
= 0;
4093 else if (optimize
> 1
4094 && !optimize_for_space
4095 && i
.reg_operands
== 2
4096 && i
.op
[0].regs
== i
.op
[1].regs
4097 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4098 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4099 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4102 andb %rN, %rN -> testb %rN, %rN
4103 andw %rN, %rN -> testw %rN, %rN
4104 andq %rN, %rN -> testq %rN, %rN
4105 orb %rN, %rN -> testb %rN, %rN
4106 orw %rN, %rN -> testw %rN, %rN
4107 orq %rN, %rN -> testq %rN, %rN
4109 and outside of 64-bit mode
4111 andl %rN, %rN -> testl %rN, %rN
4112 orl %rN, %rN -> testl %rN, %rN
4114 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4116 else if (i
.reg_operands
== 3
4117 && i
.op
[0].regs
== i
.op
[1].regs
4118 && !i
.types
[2].bitfield
.xmmword
4119 && (i
.tm
.opcode_modifier
.vex
4120 || ((!i
.mask
|| i
.mask
->zeroing
)
4122 && is_evex_encoding (&i
.tm
)
4123 && (i
.vec_encoding
!= vex_encoding_evex
4124 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4125 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4126 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4127 && i
.types
[2].bitfield
.ymmword
))))
4128 && ((i
.tm
.base_opcode
== 0x55
4129 || i
.tm
.base_opcode
== 0x6655
4130 || i
.tm
.base_opcode
== 0x66df
4131 || i
.tm
.base_opcode
== 0x57
4132 || i
.tm
.base_opcode
== 0x6657
4133 || i
.tm
.base_opcode
== 0x66ef
4134 || i
.tm
.base_opcode
== 0x66f8
4135 || i
.tm
.base_opcode
== 0x66f9
4136 || i
.tm
.base_opcode
== 0x66fa
4137 || i
.tm
.base_opcode
== 0x66fb
4138 || i
.tm
.base_opcode
== 0x42
4139 || i
.tm
.base_opcode
== 0x6642
4140 || i
.tm
.base_opcode
== 0x47
4141 || i
.tm
.base_opcode
== 0x6647)
4142 && i
.tm
.extension_opcode
== None
))
4145 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4147 EVEX VOP %zmmM, %zmmM, %zmmN
4148 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4149 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4150 EVEX VOP %ymmM, %ymmM, %ymmN
4151 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4152 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4153 VEX VOP %ymmM, %ymmM, %ymmN
4154 -> VEX VOP %xmmM, %xmmM, %xmmN
4155 VOP, one of vpandn and vpxor:
4156 VEX VOP %ymmM, %ymmM, %ymmN
4157 -> VEX VOP %xmmM, %xmmM, %xmmN
4158 VOP, one of vpandnd and vpandnq:
4159 EVEX VOP %zmmM, %zmmM, %zmmN
4160 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4161 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4162 EVEX VOP %ymmM, %ymmM, %ymmN
4163 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4164 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4165 VOP, one of vpxord and vpxorq:
4166 EVEX VOP %zmmM, %zmmM, %zmmN
4167 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4168 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4169 EVEX VOP %ymmM, %ymmM, %ymmN
4170 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4171 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4172 VOP, one of kxord and kxorq:
4173 VEX VOP %kM, %kM, %kN
4174 -> VEX kxorw %kM, %kM, %kN
4175 VOP, one of kandnd and kandnq:
4176 VEX VOP %kM, %kM, %kN
4177 -> VEX kandnw %kM, %kM, %kN
4179 if (is_evex_encoding (&i
.tm
))
4181 if (i
.vec_encoding
!= vex_encoding_evex
)
4183 i
.tm
.opcode_modifier
.vex
= VEX128
;
4184 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4185 i
.tm
.opcode_modifier
.evex
= 0;
4187 else if (optimize
> 1)
4188 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4192 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4194 i
.tm
.base_opcode
&= 0xff;
4195 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4198 i
.tm
.opcode_modifier
.vex
= VEX128
;
4200 if (i
.tm
.opcode_modifier
.vex
)
4201 for (j
= 0; j
< 3; j
++)
4203 i
.types
[j
].bitfield
.xmmword
= 1;
4204 i
.types
[j
].bitfield
.ymmword
= 0;
4207 else if (i
.vec_encoding
!= vex_encoding_evex
4208 && !i
.types
[0].bitfield
.zmmword
4209 && !i
.types
[1].bitfield
.zmmword
4212 && is_evex_encoding (&i
.tm
)
4213 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4214 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4215 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4216 || (i
.tm
.base_opcode
& ~4) == 0x66db
4217 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4218 && i
.tm
.extension_opcode
== None
)
4221 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4222 vmovdqu32 and vmovdqu64:
4223 EVEX VOP %xmmM, %xmmN
4224 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4225 EVEX VOP %ymmM, %ymmN
4226 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4228 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4230 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4232 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4234 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4235 VOP, one of vpand, vpandn, vpor, vpxor:
4236 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4237 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4238 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4239 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4240 EVEX VOP{d,q} mem, %xmmM, %xmmN
4241 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4242 EVEX VOP{d,q} mem, %ymmM, %ymmN
4243 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4245 for (j
= 0; j
< i
.operands
; j
++)
4246 if (operand_type_check (i
.types
[j
], disp
)
4247 && i
.op
[j
].disps
->X_op
== O_constant
)
4249 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4250 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4251 bytes, we choose EVEX Disp8 over VEX Disp32. */
4252 int evex_disp8
, vex_disp8
;
4253 unsigned int memshift
= i
.memshift
;
4254 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4256 evex_disp8
= fits_in_disp8 (n
);
4258 vex_disp8
= fits_in_disp8 (n
);
4259 if (evex_disp8
!= vex_disp8
)
4261 i
.memshift
= memshift
;
4265 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4268 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4269 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4270 i
.tm
.opcode_modifier
.vex
4271 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4272 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4273 /* VPAND, VPOR, and VPXOR are commutative. */
4274 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4275 i
.tm
.opcode_modifier
.commutative
= 1;
4276 i
.tm
.opcode_modifier
.evex
= 0;
4277 i
.tm
.opcode_modifier
.masking
= 0;
4278 i
.tm
.opcode_modifier
.broadcast
= 0;
4279 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4282 i
.types
[j
].bitfield
.disp8
4283 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4287 /* This is the guts of the machine-dependent assembler. LINE points to a
4288 machine dependent instruction. This function is supposed to emit
4289 the frags/bytes it assembles to. */
4292 md_assemble (char *line
)
4295 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4296 const insn_template
*t
;
4298 /* Initialize globals. */
4299 memset (&i
, '\0', sizeof (i
));
4300 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4301 i
.reloc
[j
] = NO_RELOC
;
4302 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4303 memset (im_expressions
, '\0', sizeof (im_expressions
));
4304 save_stack_p
= save_stack
;
4306 /* First parse an instruction mnemonic & call i386_operand for the operands.
4307 We assume that the scrubber has arranged it so that line[0] is the valid
4308 start of a (possibly prefixed) mnemonic. */
4310 line
= parse_insn (line
, mnemonic
);
4313 mnem_suffix
= i
.suffix
;
4315 line
= parse_operands (line
, mnemonic
);
4317 xfree (i
.memop1_string
);
4318 i
.memop1_string
= NULL
;
4322 /* Now we've parsed the mnemonic into a set of templates, and have the
4323 operands at hand. */
4325 /* All intel opcodes have reversed operands except for "bound" and
4326 "enter". We also don't reverse intersegment "jmp" and "call"
4327 instructions with 2 immediate operands so that the immediate segment
4328 precedes the offset, as it does when in AT&T mode. */
4331 && (strcmp (mnemonic
, "bound") != 0)
4332 && (strcmp (mnemonic
, "invlpga") != 0)
4333 && !(operand_type_check (i
.types
[0], imm
)
4334 && operand_type_check (i
.types
[1], imm
)))
4337 /* The order of the immediates should be reversed
4338 for 2 immediates extrq and insertq instructions */
4339 if (i
.imm_operands
== 2
4340 && (strcmp (mnemonic
, "extrq") == 0
4341 || strcmp (mnemonic
, "insertq") == 0))
4342 swap_2_operands (0, 1);
4347 /* Don't optimize displacement for movabs since it only takes 64bit
4350 && i
.disp_encoding
!= disp_encoding_32bit
4351 && (flag_code
!= CODE_64BIT
4352 || strcmp (mnemonic
, "movabs") != 0))
4355 /* Next, we find a template that matches the given insn,
4356 making sure the overlap of the given operands types is consistent
4357 with the template operand types. */
4359 if (!(t
= match_template (mnem_suffix
)))
4362 if (sse_check
!= check_none
4363 && !i
.tm
.opcode_modifier
.noavx
4364 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4365 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4366 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4367 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4368 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4369 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4371 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4372 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4373 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4374 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4375 || i
.tm
.cpu_flags
.bitfield
.cpusha
4376 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4378 (sse_check
== check_warning
4380 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4383 /* Zap movzx and movsx suffix. The suffix has been set from
4384 "word ptr" or "byte ptr" on the source operand in Intel syntax
4385 or extracted from mnemonic in AT&T syntax. But we'll use
4386 the destination register to choose the suffix for encoding. */
4387 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4389 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4390 there is no suffix, the default will be byte extension. */
4391 if (i
.reg_operands
!= 2
4394 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4399 if (i
.tm
.opcode_modifier
.fwait
)
4400 if (!add_prefix (FWAIT_OPCODE
))
4403 /* Check if REP prefix is OK. */
4404 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4406 as_bad (_("invalid instruction `%s' after `%s'"),
4407 i
.tm
.name
, i
.rep_prefix
);
4411 /* Check for lock without a lockable instruction. Destination operand
4412 must be memory unless it is xchg (0x86). */
4413 if (i
.prefix
[LOCK_PREFIX
]
4414 && (!i
.tm
.opcode_modifier
.islockable
4415 || i
.mem_operands
== 0
4416 || (i
.tm
.base_opcode
!= 0x86
4417 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4419 as_bad (_("expecting lockable instruction after `lock'"));
4423 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4424 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4426 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4430 /* Check if HLE prefix is OK. */
4431 if (i
.hle_prefix
&& !check_hle ())
4434 /* Check BND prefix. */
4435 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4436 as_bad (_("expecting valid branch instruction after `bnd'"));
4438 /* Check NOTRACK prefix. */
4439 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4440 as_bad (_("expecting indirect branch instruction after `notrack'"));
4442 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4444 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4445 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4446 else if (flag_code
!= CODE_16BIT
4447 ? i
.prefix
[ADDR_PREFIX
]
4448 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4449 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4452 /* Insert BND prefix. */
4453 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4455 if (!i
.prefix
[BND_PREFIX
])
4456 add_prefix (BND_PREFIX_OPCODE
);
4457 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4459 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4460 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4464 /* Check string instruction segment overrides. */
4465 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4467 gas_assert (i
.mem_operands
);
4468 if (!check_string ())
4470 i
.disp_operands
= 0;
4473 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4474 optimize_encoding ();
4476 if (!process_suffix ())
4479 /* Update operand types. */
4480 for (j
= 0; j
< i
.operands
; j
++)
4481 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4483 /* Make still unresolved immediate matches conform to size of immediate
4484 given in i.suffix. */
4485 if (!finalize_imm ())
4488 if (i
.types
[0].bitfield
.imm1
)
4489 i
.imm_operands
= 0; /* kludge for shift insns. */
4491 /* We only need to check those implicit registers for instructions
4492 with 3 operands or less. */
4493 if (i
.operands
<= 3)
4494 for (j
= 0; j
< i
.operands
; j
++)
4495 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4496 && !i
.types
[j
].bitfield
.xmmword
)
4499 /* ImmExt should be processed after SSE2AVX. */
4500 if (!i
.tm
.opcode_modifier
.sse2avx
4501 && i
.tm
.opcode_modifier
.immext
)
4504 /* For insns with operands there are more diddles to do to the opcode. */
4507 if (!process_operands ())
4510 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4512 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4513 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4516 if (is_any_vex_encoding (&i
.tm
))
4518 if (!cpu_arch_flags
.bitfield
.cpui286
)
4520 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4525 if (i
.tm
.opcode_modifier
.vex
)
4526 build_vex_prefix (t
);
4528 build_evex_prefix ();
4531 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4532 instructions may define INT_OPCODE as well, so avoid this corner
4533 case for those instructions that use MODRM. */
4534 if (i
.tm
.base_opcode
== INT_OPCODE
4535 && !i
.tm
.opcode_modifier
.modrm
4536 && i
.op
[0].imms
->X_add_number
== 3)
4538 i
.tm
.base_opcode
= INT3_OPCODE
;
4542 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4543 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4544 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4545 && i
.op
[0].disps
->X_op
== O_constant
)
4547 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4548 the absolute address given by the constant. Since ix86 jumps and
4549 calls are pc relative, we need to generate a reloc. */
4550 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4551 i
.op
[0].disps
->X_op
= O_symbol
;
4554 if (i
.tm
.opcode_modifier
.rex64
)
4557 /* For 8 bit registers we need an empty rex prefix. Also if the
4558 instruction already has a prefix, we need to convert old
4559 registers to new ones. */
4561 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4562 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4563 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4564 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4565 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4566 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4571 i
.rex
|= REX_OPCODE
;
4572 for (x
= 0; x
< 2; x
++)
4574 /* Look for 8 bit operand that uses old registers. */
4575 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4576 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4578 /* In case it is "hi" register, give up. */
4579 if (i
.op
[x
].regs
->reg_num
> 3)
4580 as_bad (_("can't encode register '%s%s' in an "
4581 "instruction requiring REX prefix."),
4582 register_prefix
, i
.op
[x
].regs
->reg_name
);
4584 /* Otherwise it is equivalent to the extended register.
4585 Since the encoding doesn't change this is merely
4586 cosmetic cleanup for debug output. */
4588 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4593 if (i
.rex
== 0 && i
.rex_encoding
)
4595 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4596 that uses legacy register. If it is "hi" register, don't add
4597 the REX_OPCODE byte. */
4599 for (x
= 0; x
< 2; x
++)
4600 if (i
.types
[x
].bitfield
.class == Reg
4601 && i
.types
[x
].bitfield
.byte
4602 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4603 && i
.op
[x
].regs
->reg_num
> 3)
4605 i
.rex_encoding
= FALSE
;
4614 add_prefix (REX_OPCODE
| i
.rex
);
4616 /* We are ready to output the insn. */
4619 last_insn
.seg
= now_seg
;
4621 if (i
.tm
.opcode_modifier
.isprefix
)
4623 last_insn
.kind
= last_insn_prefix
;
4624 last_insn
.name
= i
.tm
.name
;
4625 last_insn
.file
= as_where (&last_insn
.line
);
4628 last_insn
.kind
= last_insn_other
;
4632 parse_insn (char *line
, char *mnemonic
)
4635 char *token_start
= l
;
4638 const insn_template
*t
;
4644 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4649 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4651 as_bad (_("no such instruction: `%s'"), token_start
);
4656 if (!is_space_char (*l
)
4657 && *l
!= END_OF_INSN
4659 || (*l
!= PREFIX_SEPARATOR
4662 as_bad (_("invalid character %s in mnemonic"),
4663 output_invalid (*l
));
4666 if (token_start
== l
)
4668 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4669 as_bad (_("expecting prefix; got nothing"));
4671 as_bad (_("expecting mnemonic; got nothing"));
4675 /* Look up instruction (or prefix) via hash table. */
4676 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4678 if (*l
!= END_OF_INSN
4679 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4680 && current_templates
4681 && current_templates
->start
->opcode_modifier
.isprefix
)
4683 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4685 as_bad ((flag_code
!= CODE_64BIT
4686 ? _("`%s' is only supported in 64-bit mode")
4687 : _("`%s' is not supported in 64-bit mode")),
4688 current_templates
->start
->name
);
4691 /* If we are in 16-bit mode, do not allow addr16 or data16.
4692 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4693 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4694 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4695 && flag_code
!= CODE_64BIT
4696 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4697 ^ (flag_code
== CODE_16BIT
)))
4699 as_bad (_("redundant %s prefix"),
4700 current_templates
->start
->name
);
4703 if (current_templates
->start
->opcode_length
== 0)
4705 /* Handle pseudo prefixes. */
4706 switch (current_templates
->start
->base_opcode
)
4710 i
.disp_encoding
= disp_encoding_8bit
;
4714 i
.disp_encoding
= disp_encoding_32bit
;
4718 i
.dir_encoding
= dir_encoding_load
;
4722 i
.dir_encoding
= dir_encoding_store
;
4726 i
.vec_encoding
= vex_encoding_vex2
;
4730 i
.vec_encoding
= vex_encoding_vex3
;
4734 i
.vec_encoding
= vex_encoding_evex
;
4738 i
.rex_encoding
= TRUE
;
4742 i
.no_optimize
= TRUE
;
4750 /* Add prefix, checking for repeated prefixes. */
4751 switch (add_prefix (current_templates
->start
->base_opcode
))
4756 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4757 i
.notrack_prefix
= current_templates
->start
->name
;
4760 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4761 i
.hle_prefix
= current_templates
->start
->name
;
4762 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4763 i
.bnd_prefix
= current_templates
->start
->name
;
4765 i
.rep_prefix
= current_templates
->start
->name
;
4771 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4778 if (!current_templates
)
4780 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4781 Check if we should swap operand or force 32bit displacement in
4783 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4784 i
.dir_encoding
= dir_encoding_swap
;
4785 else if (mnem_p
- 3 == dot_p
4788 i
.disp_encoding
= disp_encoding_8bit
;
4789 else if (mnem_p
- 4 == dot_p
4793 i
.disp_encoding
= disp_encoding_32bit
;
4798 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4801 if (!current_templates
)
4804 if (mnem_p
> mnemonic
)
4806 /* See if we can get a match by trimming off a suffix. */
4809 case WORD_MNEM_SUFFIX
:
4810 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4811 i
.suffix
= SHORT_MNEM_SUFFIX
;
4814 case BYTE_MNEM_SUFFIX
:
4815 case QWORD_MNEM_SUFFIX
:
4816 i
.suffix
= mnem_p
[-1];
4818 current_templates
= (const templates
*) hash_find (op_hash
,
4821 case SHORT_MNEM_SUFFIX
:
4822 case LONG_MNEM_SUFFIX
:
4825 i
.suffix
= mnem_p
[-1];
4827 current_templates
= (const templates
*) hash_find (op_hash
,
4836 if (intel_float_operand (mnemonic
) == 1)
4837 i
.suffix
= SHORT_MNEM_SUFFIX
;
4839 i
.suffix
= LONG_MNEM_SUFFIX
;
4841 current_templates
= (const templates
*) hash_find (op_hash
,
4848 if (!current_templates
)
4850 as_bad (_("no such instruction: `%s'"), token_start
);
4855 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4856 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4858 /* Check for a branch hint. We allow ",pt" and ",pn" for
4859 predict taken and predict not taken respectively.
4860 I'm not sure that branch hints actually do anything on loop
4861 and jcxz insns (JumpByte) for current Pentium4 chips. They
4862 may work in the future and it doesn't hurt to accept them
4864 if (l
[0] == ',' && l
[1] == 'p')
4868 if (!add_prefix (DS_PREFIX_OPCODE
))
4872 else if (l
[2] == 'n')
4874 if (!add_prefix (CS_PREFIX_OPCODE
))
4880 /* Any other comma loses. */
4883 as_bad (_("invalid character %s in mnemonic"),
4884 output_invalid (*l
));
4888 /* Check if instruction is supported on specified architecture. */
4890 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4892 supported
|= cpu_flags_match (t
);
4893 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4895 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4896 as_warn (_("use .code16 to ensure correct addressing mode"));
4902 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4903 as_bad (flag_code
== CODE_64BIT
4904 ? _("`%s' is not supported in 64-bit mode")
4905 : _("`%s' is only supported in 64-bit mode"),
4906 current_templates
->start
->name
);
4908 as_bad (_("`%s' is not supported on `%s%s'"),
4909 current_templates
->start
->name
,
4910 cpu_arch_name
? cpu_arch_name
: default_arch
,
4911 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4917 parse_operands (char *l
, const char *mnemonic
)
4921 /* 1 if operand is pending after ','. */
4922 unsigned int expecting_operand
= 0;
4924 /* Non-zero if operand parens not balanced. */
4925 unsigned int paren_not_balanced
;
4927 while (*l
!= END_OF_INSN
)
4929 /* Skip optional white space before operand. */
4930 if (is_space_char (*l
))
4932 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4934 as_bad (_("invalid character %s before operand %d"),
4935 output_invalid (*l
),
4939 token_start
= l
; /* After white space. */
4940 paren_not_balanced
= 0;
4941 while (paren_not_balanced
|| *l
!= ',')
4943 if (*l
== END_OF_INSN
)
4945 if (paren_not_balanced
)
4948 as_bad (_("unbalanced parenthesis in operand %d."),
4951 as_bad (_("unbalanced brackets in operand %d."),
4956 break; /* we are done */
4958 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4960 as_bad (_("invalid character %s in operand %d"),
4961 output_invalid (*l
),
4968 ++paren_not_balanced
;
4970 --paren_not_balanced
;
4975 ++paren_not_balanced
;
4977 --paren_not_balanced
;
4981 if (l
!= token_start
)
4982 { /* Yes, we've read in another operand. */
4983 unsigned int operand_ok
;
4984 this_operand
= i
.operands
++;
4985 if (i
.operands
> MAX_OPERANDS
)
4987 as_bad (_("spurious operands; (%d operands/instruction max)"),
4991 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4992 /* Now parse operand adding info to 'i' as we go along. */
4993 END_STRING_AND_SAVE (l
);
4995 if (i
.mem_operands
> 1)
4997 as_bad (_("too many memory references for `%s'"),
5004 i386_intel_operand (token_start
,
5005 intel_float_operand (mnemonic
));
5007 operand_ok
= i386_att_operand (token_start
);
5009 RESTORE_END_STRING (l
);
5015 if (expecting_operand
)
5017 expecting_operand_after_comma
:
5018 as_bad (_("expecting operand after ','; got nothing"));
5023 as_bad (_("expecting operand before ','; got nothing"));
5028 /* Now *l must be either ',' or END_OF_INSN. */
5031 if (*++l
== END_OF_INSN
)
5033 /* Just skip it, if it's \n complain. */
5034 goto expecting_operand_after_comma
;
5036 expecting_operand
= 1;
5043 swap_2_operands (int xchg1
, int xchg2
)
5045 union i386_op temp_op
;
5046 i386_operand_type temp_type
;
5047 unsigned int temp_flags
;
5048 enum bfd_reloc_code_real temp_reloc
;
5050 temp_type
= i
.types
[xchg2
];
5051 i
.types
[xchg2
] = i
.types
[xchg1
];
5052 i
.types
[xchg1
] = temp_type
;
5054 temp_flags
= i
.flags
[xchg2
];
5055 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5056 i
.flags
[xchg1
] = temp_flags
;
5058 temp_op
= i
.op
[xchg2
];
5059 i
.op
[xchg2
] = i
.op
[xchg1
];
5060 i
.op
[xchg1
] = temp_op
;
5062 temp_reloc
= i
.reloc
[xchg2
];
5063 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5064 i
.reloc
[xchg1
] = temp_reloc
;
5068 if (i
.mask
->operand
== xchg1
)
5069 i
.mask
->operand
= xchg2
;
5070 else if (i
.mask
->operand
== xchg2
)
5071 i
.mask
->operand
= xchg1
;
5075 if (i
.broadcast
->operand
== xchg1
)
5076 i
.broadcast
->operand
= xchg2
;
5077 else if (i
.broadcast
->operand
== xchg2
)
5078 i
.broadcast
->operand
= xchg1
;
5082 if (i
.rounding
->operand
== xchg1
)
5083 i
.rounding
->operand
= xchg2
;
5084 else if (i
.rounding
->operand
== xchg2
)
5085 i
.rounding
->operand
= xchg1
;
5090 swap_operands (void)
5096 swap_2_operands (1, i
.operands
- 2);
5100 swap_2_operands (0, i
.operands
- 1);
5106 if (i
.mem_operands
== 2)
5108 const seg_entry
*temp_seg
;
5109 temp_seg
= i
.seg
[0];
5110 i
.seg
[0] = i
.seg
[1];
5111 i
.seg
[1] = temp_seg
;
5115 /* Try to ensure constant immediates are represented in the smallest
5120 char guess_suffix
= 0;
5124 guess_suffix
= i
.suffix
;
5125 else if (i
.reg_operands
)
5127 /* Figure out a suffix from the last register operand specified.
5128 We can't do this properly yet, i.e. excluding special register
5129 instances, but the following works for instructions with
5130 immediates. In any case, we can't set i.suffix yet. */
5131 for (op
= i
.operands
; --op
>= 0;)
5132 if (i
.types
[op
].bitfield
.class != Reg
)
5134 else if (i
.types
[op
].bitfield
.byte
)
5136 guess_suffix
= BYTE_MNEM_SUFFIX
;
5139 else if (i
.types
[op
].bitfield
.word
)
5141 guess_suffix
= WORD_MNEM_SUFFIX
;
5144 else if (i
.types
[op
].bitfield
.dword
)
5146 guess_suffix
= LONG_MNEM_SUFFIX
;
5149 else if (i
.types
[op
].bitfield
.qword
)
5151 guess_suffix
= QWORD_MNEM_SUFFIX
;
5155 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5156 guess_suffix
= WORD_MNEM_SUFFIX
;
5158 for (op
= i
.operands
; --op
>= 0;)
5159 if (operand_type_check (i
.types
[op
], imm
))
5161 switch (i
.op
[op
].imms
->X_op
)
5164 /* If a suffix is given, this operand may be shortened. */
5165 switch (guess_suffix
)
5167 case LONG_MNEM_SUFFIX
:
5168 i
.types
[op
].bitfield
.imm32
= 1;
5169 i
.types
[op
].bitfield
.imm64
= 1;
5171 case WORD_MNEM_SUFFIX
:
5172 i
.types
[op
].bitfield
.imm16
= 1;
5173 i
.types
[op
].bitfield
.imm32
= 1;
5174 i
.types
[op
].bitfield
.imm32s
= 1;
5175 i
.types
[op
].bitfield
.imm64
= 1;
5177 case BYTE_MNEM_SUFFIX
:
5178 i
.types
[op
].bitfield
.imm8
= 1;
5179 i
.types
[op
].bitfield
.imm8s
= 1;
5180 i
.types
[op
].bitfield
.imm16
= 1;
5181 i
.types
[op
].bitfield
.imm32
= 1;
5182 i
.types
[op
].bitfield
.imm32s
= 1;
5183 i
.types
[op
].bitfield
.imm64
= 1;
5187 /* If this operand is at most 16 bits, convert it
5188 to a signed 16 bit number before trying to see
5189 whether it will fit in an even smaller size.
5190 This allows a 16-bit operand such as $0xffe0 to
5191 be recognised as within Imm8S range. */
5192 if ((i
.types
[op
].bitfield
.imm16
)
5193 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5195 i
.op
[op
].imms
->X_add_number
=
5196 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5199 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5200 if ((i
.types
[op
].bitfield
.imm32
)
5201 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5204 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5205 ^ ((offsetT
) 1 << 31))
5206 - ((offsetT
) 1 << 31));
5210 = operand_type_or (i
.types
[op
],
5211 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5213 /* We must avoid matching of Imm32 templates when 64bit
5214 only immediate is available. */
5215 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5216 i
.types
[op
].bitfield
.imm32
= 0;
5223 /* Symbols and expressions. */
5225 /* Convert symbolic operand to proper sizes for matching, but don't
5226 prevent matching a set of insns that only supports sizes other
5227 than those matching the insn suffix. */
5229 i386_operand_type mask
, allowed
;
5230 const insn_template
*t
;
5232 operand_type_set (&mask
, 0);
5233 operand_type_set (&allowed
, 0);
5235 for (t
= current_templates
->start
;
5236 t
< current_templates
->end
;
5239 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5240 allowed
= operand_type_and (allowed
, anyimm
);
5242 switch (guess_suffix
)
5244 case QWORD_MNEM_SUFFIX
:
5245 mask
.bitfield
.imm64
= 1;
5246 mask
.bitfield
.imm32s
= 1;
5248 case LONG_MNEM_SUFFIX
:
5249 mask
.bitfield
.imm32
= 1;
5251 case WORD_MNEM_SUFFIX
:
5252 mask
.bitfield
.imm16
= 1;
5254 case BYTE_MNEM_SUFFIX
:
5255 mask
.bitfield
.imm8
= 1;
5260 allowed
= operand_type_and (mask
, allowed
);
5261 if (!operand_type_all_zero (&allowed
))
5262 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5269 /* Try to use the smallest displacement type too. */
5271 optimize_disp (void)
5275 for (op
= i
.operands
; --op
>= 0;)
5276 if (operand_type_check (i
.types
[op
], disp
))
5278 if (i
.op
[op
].disps
->X_op
== O_constant
)
5280 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5282 if (i
.types
[op
].bitfield
.disp16
5283 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5285 /* If this operand is at most 16 bits, convert
5286 to a signed 16 bit number and don't use 64bit
5288 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5289 i
.types
[op
].bitfield
.disp64
= 0;
5292 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5293 if (i
.types
[op
].bitfield
.disp32
5294 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5296 /* If this operand is at most 32 bits, convert
5297 to a signed 32 bit number and don't use 64bit
5299 op_disp
&= (((offsetT
) 2 << 31) - 1);
5300 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5301 i
.types
[op
].bitfield
.disp64
= 0;
5304 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5306 i
.types
[op
].bitfield
.disp8
= 0;
5307 i
.types
[op
].bitfield
.disp16
= 0;
5308 i
.types
[op
].bitfield
.disp32
= 0;
5309 i
.types
[op
].bitfield
.disp32s
= 0;
5310 i
.types
[op
].bitfield
.disp64
= 0;
5314 else if (flag_code
== CODE_64BIT
)
5316 if (fits_in_signed_long (op_disp
))
5318 i
.types
[op
].bitfield
.disp64
= 0;
5319 i
.types
[op
].bitfield
.disp32s
= 1;
5321 if (i
.prefix
[ADDR_PREFIX
]
5322 && fits_in_unsigned_long (op_disp
))
5323 i
.types
[op
].bitfield
.disp32
= 1;
5325 if ((i
.types
[op
].bitfield
.disp32
5326 || i
.types
[op
].bitfield
.disp32s
5327 || i
.types
[op
].bitfield
.disp16
)
5328 && fits_in_disp8 (op_disp
))
5329 i
.types
[op
].bitfield
.disp8
= 1;
5331 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5332 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5334 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5335 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5336 i
.types
[op
].bitfield
.disp8
= 0;
5337 i
.types
[op
].bitfield
.disp16
= 0;
5338 i
.types
[op
].bitfield
.disp32
= 0;
5339 i
.types
[op
].bitfield
.disp32s
= 0;
5340 i
.types
[op
].bitfield
.disp64
= 0;
5343 /* We only support 64bit displacement on constants. */
5344 i
.types
[op
].bitfield
.disp64
= 0;
5348 /* Return 1 if there is a match in broadcast bytes between operand
5349 GIVEN and instruction template T. */
5352 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5354 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5355 && i
.types
[given
].bitfield
.byte
)
5356 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5357 && i
.types
[given
].bitfield
.word
)
5358 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5359 && i
.types
[given
].bitfield
.dword
)
5360 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5361 && i
.types
[given
].bitfield
.qword
));
5364 /* Check if operands are valid for the instruction. */
5367 check_VecOperands (const insn_template
*t
)
5371 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5373 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5374 any one operand are implicity requiring AVX512VL support if the actual
5375 operand size is YMMword or XMMword. Since this function runs after
5376 template matching, there's no need to check for YMMword/XMMword in
5378 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5379 if (!cpu_flags_all_zero (&cpu
)
5380 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5381 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5383 for (op
= 0; op
< t
->operands
; ++op
)
5385 if (t
->operand_types
[op
].bitfield
.zmmword
5386 && (i
.types
[op
].bitfield
.ymmword
5387 || i
.types
[op
].bitfield
.xmmword
))
5389 i
.error
= unsupported
;
5395 /* Without VSIB byte, we can't have a vector register for index. */
5396 if (!t
->opcode_modifier
.vecsib
5398 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5399 || i
.index_reg
->reg_type
.bitfield
.ymmword
5400 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5402 i
.error
= unsupported_vector_index_register
;
5406 /* Check if default mask is allowed. */
5407 if (t
->opcode_modifier
.nodefmask
5408 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5410 i
.error
= no_default_mask
;
5414 /* For VSIB byte, we need a vector register for index, and all vector
5415 registers must be distinct. */
5416 if (t
->opcode_modifier
.vecsib
)
5419 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5420 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5421 || (t
->opcode_modifier
.vecsib
== VecSIB256
5422 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5423 || (t
->opcode_modifier
.vecsib
== VecSIB512
5424 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5426 i
.error
= invalid_vsib_address
;
5430 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5431 if (i
.reg_operands
== 2 && !i
.mask
)
5433 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5434 gas_assert (i
.types
[0].bitfield
.xmmword
5435 || i
.types
[0].bitfield
.ymmword
);
5436 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5437 gas_assert (i
.types
[2].bitfield
.xmmword
5438 || i
.types
[2].bitfield
.ymmword
);
5439 if (operand_check
== check_none
)
5441 if (register_number (i
.op
[0].regs
)
5442 != register_number (i
.index_reg
)
5443 && register_number (i
.op
[2].regs
)
5444 != register_number (i
.index_reg
)
5445 && register_number (i
.op
[0].regs
)
5446 != register_number (i
.op
[2].regs
))
5448 if (operand_check
== check_error
)
5450 i
.error
= invalid_vector_register_set
;
5453 as_warn (_("mask, index, and destination registers should be distinct"));
5455 else if (i
.reg_operands
== 1 && i
.mask
)
5457 if (i
.types
[1].bitfield
.class == RegSIMD
5458 && (i
.types
[1].bitfield
.xmmword
5459 || i
.types
[1].bitfield
.ymmword
5460 || i
.types
[1].bitfield
.zmmword
)
5461 && (register_number (i
.op
[1].regs
)
5462 == register_number (i
.index_reg
)))
5464 if (operand_check
== check_error
)
5466 i
.error
= invalid_vector_register_set
;
5469 if (operand_check
!= check_none
)
5470 as_warn (_("index and destination registers should be distinct"));
5475 /* Check if broadcast is supported by the instruction and is applied
5476 to the memory operand. */
5479 i386_operand_type type
, overlap
;
5481 /* Check if specified broadcast is supported in this instruction,
5482 and its broadcast bytes match the memory operand. */
5483 op
= i
.broadcast
->operand
;
5484 if (!t
->opcode_modifier
.broadcast
5485 || !(i
.flags
[op
] & Operand_Mem
)
5486 || (!i
.types
[op
].bitfield
.unspecified
5487 && !match_broadcast_size (t
, op
)))
5490 i
.error
= unsupported_broadcast
;
5494 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5495 * i
.broadcast
->type
);
5496 operand_type_set (&type
, 0);
5497 switch (i
.broadcast
->bytes
)
5500 type
.bitfield
.word
= 1;
5503 type
.bitfield
.dword
= 1;
5506 type
.bitfield
.qword
= 1;
5509 type
.bitfield
.xmmword
= 1;
5512 type
.bitfield
.ymmword
= 1;
5515 type
.bitfield
.zmmword
= 1;
5521 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5522 if (operand_type_all_zero (&overlap
))
5525 if (t
->opcode_modifier
.checkregsize
)
5529 type
.bitfield
.baseindex
= 1;
5530 for (j
= 0; j
< i
.operands
; ++j
)
5533 && !operand_type_register_match(i
.types
[j
],
5534 t
->operand_types
[j
],
5536 t
->operand_types
[op
]))
5541 /* If broadcast is supported in this instruction, we need to check if
5542 operand of one-element size isn't specified without broadcast. */
5543 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5545 /* Find memory operand. */
5546 for (op
= 0; op
< i
.operands
; op
++)
5547 if (i
.flags
[op
] & Operand_Mem
)
5549 gas_assert (op
< i
.operands
);
5550 /* Check size of the memory operand. */
5551 if (match_broadcast_size (t
, op
))
5553 i
.error
= broadcast_needed
;
5558 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5560 /* Check if requested masking is supported. */
5563 switch (t
->opcode_modifier
.masking
)
5567 case MERGING_MASKING
:
5568 if (i
.mask
->zeroing
)
5571 i
.error
= unsupported_masking
;
5575 case DYNAMIC_MASKING
:
5576 /* Memory destinations allow only merging masking. */
5577 if (i
.mask
->zeroing
&& i
.mem_operands
)
5579 /* Find memory operand. */
5580 for (op
= 0; op
< i
.operands
; op
++)
5581 if (i
.flags
[op
] & Operand_Mem
)
5583 gas_assert (op
< i
.operands
);
5584 if (op
== i
.operands
- 1)
5586 i
.error
= unsupported_masking
;
5596 /* Check if masking is applied to dest operand. */
5597 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5599 i
.error
= mask_not_on_destination
;
5606 if (!t
->opcode_modifier
.sae
5607 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5609 i
.error
= unsupported_rc_sae
;
5612 /* If the instruction has several immediate operands and one of
5613 them is rounding, the rounding operand should be the last
5614 immediate operand. */
5615 if (i
.imm_operands
> 1
5616 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5618 i
.error
= rc_sae_operand_not_last_imm
;
5623 /* Check vector Disp8 operand. */
5624 if (t
->opcode_modifier
.disp8memshift
5625 && i
.disp_encoding
!= disp_encoding_32bit
)
5628 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5629 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5630 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5633 const i386_operand_type
*type
= NULL
;
5636 for (op
= 0; op
< i
.operands
; op
++)
5637 if (i
.flags
[op
] & Operand_Mem
)
5639 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5640 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5641 else if (t
->operand_types
[op
].bitfield
.xmmword
5642 + t
->operand_types
[op
].bitfield
.ymmword
5643 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5644 type
= &t
->operand_types
[op
];
5645 else if (!i
.types
[op
].bitfield
.unspecified
)
5646 type
= &i
.types
[op
];
5648 else if (i
.types
[op
].bitfield
.class == RegSIMD
5649 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5651 if (i
.types
[op
].bitfield
.zmmword
)
5653 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5655 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5661 if (type
->bitfield
.zmmword
)
5663 else if (type
->bitfield
.ymmword
)
5665 else if (type
->bitfield
.xmmword
)
5669 /* For the check in fits_in_disp8(). */
5670 if (i
.memshift
== 0)
5674 for (op
= 0; op
< i
.operands
; op
++)
5675 if (operand_type_check (i
.types
[op
], disp
)
5676 && i
.op
[op
].disps
->X_op
== O_constant
)
5678 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5680 i
.types
[op
].bitfield
.disp8
= 1;
5683 i
.types
[op
].bitfield
.disp8
= 0;
5692 /* Check if operands are valid for the instruction. Update VEX
5696 VEX_check_operands (const insn_template
*t
)
5698 if (i
.vec_encoding
== vex_encoding_evex
)
5700 /* This instruction must be encoded with EVEX prefix. */
5701 if (!is_evex_encoding (t
))
5703 i
.error
= unsupported
;
5709 if (!t
->opcode_modifier
.vex
)
5711 /* This instruction template doesn't have VEX prefix. */
5712 if (i
.vec_encoding
!= vex_encoding_default
)
5714 i
.error
= unsupported
;
5720 /* Check the special Imm4 cases; must be the first operand. */
5721 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5723 if (i
.op
[0].imms
->X_op
!= O_constant
5724 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5730 /* Turn off Imm<N> so that update_imm won't complain. */
5731 operand_type_set (&i
.types
[0], 0);
5737 static const insn_template
*
5738 match_template (char mnem_suffix
)
5740 /* Points to template once we've found it. */
5741 const insn_template
*t
;
5742 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5743 i386_operand_type overlap4
;
5744 unsigned int found_reverse_match
;
5745 i386_opcode_modifier suffix_check
;
5746 i386_operand_type operand_types
[MAX_OPERANDS
];
5747 int addr_prefix_disp
;
5749 unsigned int found_cpu_match
, size_match
;
5750 unsigned int check_register
;
5751 enum i386_error specific_error
= 0;
5753 #if MAX_OPERANDS != 5
5754 # error "MAX_OPERANDS must be 5."
5757 found_reverse_match
= 0;
5758 addr_prefix_disp
= -1;
5760 /* Prepare for mnemonic suffix check. */
5761 memset (&suffix_check
, 0, sizeof (suffix_check
));
5762 switch (mnem_suffix
)
5764 case BYTE_MNEM_SUFFIX
:
5765 suffix_check
.no_bsuf
= 1;
5767 case WORD_MNEM_SUFFIX
:
5768 suffix_check
.no_wsuf
= 1;
5770 case SHORT_MNEM_SUFFIX
:
5771 suffix_check
.no_ssuf
= 1;
5773 case LONG_MNEM_SUFFIX
:
5774 suffix_check
.no_lsuf
= 1;
5776 case QWORD_MNEM_SUFFIX
:
5777 suffix_check
.no_qsuf
= 1;
5780 /* NB: In Intel syntax, normally we can check for memory operand
5781 size when there is no mnemonic suffix. But jmp and call have
5782 2 different encodings with Dword memory operand size, one with
5783 No_ldSuf and the other without. i.suffix is set to
5784 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5785 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5786 suffix_check
.no_ldsuf
= 1;
5789 /* Must have right number of operands. */
5790 i
.error
= number_of_operands_mismatch
;
5792 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5794 addr_prefix_disp
= -1;
5795 found_reverse_match
= 0;
5797 if (i
.operands
!= t
->operands
)
5800 /* Check processor support. */
5801 i
.error
= unsupported
;
5802 found_cpu_match
= (cpu_flags_match (t
)
5803 == CPU_FLAGS_PERFECT_MATCH
);
5804 if (!found_cpu_match
)
5807 /* Check AT&T mnemonic. */
5808 i
.error
= unsupported_with_intel_mnemonic
;
5809 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5812 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5813 i
.error
= unsupported_syntax
;
5814 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5815 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5816 || (intel64
&& t
->opcode_modifier
.amd64
)
5817 || (!intel64
&& t
->opcode_modifier
.intel64
))
5820 /* Check the suffix. */
5821 i
.error
= invalid_instruction_suffix
;
5822 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5823 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5824 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5825 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5826 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5827 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5830 size_match
= operand_size_match (t
);
5834 /* This is intentionally not
5836 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5838 as the case of a missing * on the operand is accepted (perhaps with
5839 a warning, issued further down). */
5840 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5842 i
.error
= operand_type_mismatch
;
5846 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5847 operand_types
[j
] = t
->operand_types
[j
];
5849 /* In general, don't allow 64-bit operands in 32-bit mode. */
5850 if (i
.suffix
== QWORD_MNEM_SUFFIX
5851 && flag_code
!= CODE_64BIT
5853 ? (!t
->opcode_modifier
.ignoresize
5854 && !t
->opcode_modifier
.broadcast
5855 && !intel_float_operand (t
->name
))
5856 : intel_float_operand (t
->name
) != 2)
5857 && ((operand_types
[0].bitfield
.class != RegMMX
5858 && operand_types
[0].bitfield
.class != RegSIMD
)
5859 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5860 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5861 && (t
->base_opcode
!= 0x0fc7
5862 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5865 /* In general, don't allow 32-bit operands on pre-386. */
5866 else if (i
.suffix
== LONG_MNEM_SUFFIX
5867 && !cpu_arch_flags
.bitfield
.cpui386
5869 ? (!t
->opcode_modifier
.ignoresize
5870 && !intel_float_operand (t
->name
))
5871 : intel_float_operand (t
->name
) != 2)
5872 && ((operand_types
[0].bitfield
.class != RegMMX
5873 && operand_types
[0].bitfield
.class != RegSIMD
)
5874 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5875 && operand_types
[t
->operands
> 1].bitfield
.class
5879 /* Do not verify operands when there are none. */
5883 /* We've found a match; break out of loop. */
5887 if (!t
->opcode_modifier
.jump
5888 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5890 /* There should be only one Disp operand. */
5891 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5892 if (operand_type_check (operand_types
[j
], disp
))
5894 if (j
< MAX_OPERANDS
)
5896 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5898 addr_prefix_disp
= j
;
5900 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5901 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5905 override
= !override
;
5908 if (operand_types
[j
].bitfield
.disp32
5909 && operand_types
[j
].bitfield
.disp16
)
5911 operand_types
[j
].bitfield
.disp16
= override
;
5912 operand_types
[j
].bitfield
.disp32
= !override
;
5914 operand_types
[j
].bitfield
.disp32s
= 0;
5915 operand_types
[j
].bitfield
.disp64
= 0;
5919 if (operand_types
[j
].bitfield
.disp32s
5920 || operand_types
[j
].bitfield
.disp64
)
5922 operand_types
[j
].bitfield
.disp64
&= !override
;
5923 operand_types
[j
].bitfield
.disp32s
&= !override
;
5924 operand_types
[j
].bitfield
.disp32
= override
;
5926 operand_types
[j
].bitfield
.disp16
= 0;
5932 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5933 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5936 /* We check register size if needed. */
5937 if (t
->opcode_modifier
.checkregsize
)
5939 check_register
= (1 << t
->operands
) - 1;
5941 check_register
&= ~(1 << i
.broadcast
->operand
);
5946 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5947 switch (t
->operands
)
5950 if (!operand_type_match (overlap0
, i
.types
[0]))
5954 /* xchg %eax, %eax is a special case. It is an alias for nop
5955 only in 32bit mode and we can use opcode 0x90. In 64bit
5956 mode, we can't use 0x90 for xchg %eax, %eax since it should
5957 zero-extend %eax to %rax. */
5958 if (flag_code
== CODE_64BIT
5959 && t
->base_opcode
== 0x90
5960 && i
.types
[0].bitfield
.instance
== Accum
5961 && i
.types
[0].bitfield
.dword
5962 && i
.types
[1].bitfield
.instance
== Accum
5963 && i
.types
[1].bitfield
.dword
)
5965 /* xrelease mov %eax, <disp> is another special case. It must not
5966 match the accumulator-only encoding of mov. */
5967 if (flag_code
!= CODE_64BIT
5969 && t
->base_opcode
== 0xa0
5970 && i
.types
[0].bitfield
.instance
== Accum
5971 && (i
.flags
[1] & Operand_Mem
))
5976 if (!(size_match
& MATCH_STRAIGHT
))
5978 /* Reverse direction of operands if swapping is possible in the first
5979 place (operands need to be symmetric) and
5980 - the load form is requested, and the template is a store form,
5981 - the store form is requested, and the template is a load form,
5982 - the non-default (swapped) form is requested. */
5983 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5984 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5985 && !operand_type_all_zero (&overlap1
))
5986 switch (i
.dir_encoding
)
5988 case dir_encoding_load
:
5989 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5990 || t
->opcode_modifier
.regmem
)
5994 case dir_encoding_store
:
5995 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5996 && !t
->opcode_modifier
.regmem
)
6000 case dir_encoding_swap
:
6003 case dir_encoding_default
:
6006 /* If we want store form, we skip the current load. */
6007 if ((i
.dir_encoding
== dir_encoding_store
6008 || i
.dir_encoding
== dir_encoding_swap
)
6009 && i
.mem_operands
== 0
6010 && t
->opcode_modifier
.load
)
6015 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6016 if (!operand_type_match (overlap0
, i
.types
[0])
6017 || !operand_type_match (overlap1
, i
.types
[1])
6018 || ((check_register
& 3) == 3
6019 && !operand_type_register_match (i
.types
[0],
6024 /* Check if other direction is valid ... */
6025 if (!t
->opcode_modifier
.d
)
6029 if (!(size_match
& MATCH_REVERSE
))
6031 /* Try reversing direction of operands. */
6032 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6033 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6034 if (!operand_type_match (overlap0
, i
.types
[0])
6035 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6037 && !operand_type_register_match (i
.types
[0],
6038 operand_types
[i
.operands
- 1],
6039 i
.types
[i
.operands
- 1],
6042 /* Does not match either direction. */
6045 /* found_reverse_match holds which of D or FloatR
6047 if (!t
->opcode_modifier
.d
)
6048 found_reverse_match
= 0;
6049 else if (operand_types
[0].bitfield
.tbyte
)
6050 found_reverse_match
= Opcode_FloatD
;
6051 else if (operand_types
[0].bitfield
.xmmword
6052 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6053 || operand_types
[0].bitfield
.class == RegMMX
6054 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6055 || is_any_vex_encoding(t
))
6056 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6057 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6059 found_reverse_match
= Opcode_D
;
6060 if (t
->opcode_modifier
.floatr
)
6061 found_reverse_match
|= Opcode_FloatR
;
6065 /* Found a forward 2 operand match here. */
6066 switch (t
->operands
)
6069 overlap4
= operand_type_and (i
.types
[4],
6073 overlap3
= operand_type_and (i
.types
[3],
6077 overlap2
= operand_type_and (i
.types
[2],
6082 switch (t
->operands
)
6085 if (!operand_type_match (overlap4
, i
.types
[4])
6086 || !operand_type_register_match (i
.types
[3],
6093 if (!operand_type_match (overlap3
, i
.types
[3])
6094 || ((check_register
& 0xa) == 0xa
6095 && !operand_type_register_match (i
.types
[1],
6099 || ((check_register
& 0xc) == 0xc
6100 && !operand_type_register_match (i
.types
[2],
6107 /* Here we make use of the fact that there are no
6108 reverse match 3 operand instructions. */
6109 if (!operand_type_match (overlap2
, i
.types
[2])
6110 || ((check_register
& 5) == 5
6111 && !operand_type_register_match (i
.types
[0],
6115 || ((check_register
& 6) == 6
6116 && !operand_type_register_match (i
.types
[1],
6124 /* Found either forward/reverse 2, 3 or 4 operand match here:
6125 slip through to break. */
6127 if (!found_cpu_match
)
6130 /* Check if vector and VEX operands are valid. */
6131 if (check_VecOperands (t
) || VEX_check_operands (t
))
6133 specific_error
= i
.error
;
6137 /* We've found a match; break out of loop. */
6141 if (t
== current_templates
->end
)
6143 /* We found no match. */
6144 const char *err_msg
;
6145 switch (specific_error
? specific_error
: i
.error
)
6149 case operand_size_mismatch
:
6150 err_msg
= _("operand size mismatch");
6152 case operand_type_mismatch
:
6153 err_msg
= _("operand type mismatch");
6155 case register_type_mismatch
:
6156 err_msg
= _("register type mismatch");
6158 case number_of_operands_mismatch
:
6159 err_msg
= _("number of operands mismatch");
6161 case invalid_instruction_suffix
:
6162 err_msg
= _("invalid instruction suffix");
6165 err_msg
= _("constant doesn't fit in 4 bits");
6167 case unsupported_with_intel_mnemonic
:
6168 err_msg
= _("unsupported with Intel mnemonic");
6170 case unsupported_syntax
:
6171 err_msg
= _("unsupported syntax");
6174 as_bad (_("unsupported instruction `%s'"),
6175 current_templates
->start
->name
);
6177 case invalid_vsib_address
:
6178 err_msg
= _("invalid VSIB address");
6180 case invalid_vector_register_set
:
6181 err_msg
= _("mask, index, and destination registers must be distinct");
6183 case unsupported_vector_index_register
:
6184 err_msg
= _("unsupported vector index register");
6186 case unsupported_broadcast
:
6187 err_msg
= _("unsupported broadcast");
6189 case broadcast_needed
:
6190 err_msg
= _("broadcast is needed for operand of such type");
6192 case unsupported_masking
:
6193 err_msg
= _("unsupported masking");
6195 case mask_not_on_destination
:
6196 err_msg
= _("mask not on destination operand");
6198 case no_default_mask
:
6199 err_msg
= _("default mask isn't allowed");
6201 case unsupported_rc_sae
:
6202 err_msg
= _("unsupported static rounding/sae");
6204 case rc_sae_operand_not_last_imm
:
6206 err_msg
= _("RC/SAE operand must precede immediate operands");
6208 err_msg
= _("RC/SAE operand must follow immediate operands");
6210 case invalid_register_operand
:
6211 err_msg
= _("invalid register operand");
6214 as_bad (_("%s for `%s'"), err_msg
,
6215 current_templates
->start
->name
);
6219 if (!quiet_warnings
)
6222 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6223 as_warn (_("indirect %s without `*'"), t
->name
);
6225 if (t
->opcode_modifier
.isprefix
6226 && t
->opcode_modifier
.ignoresize
)
6228 /* Warn them that a data or address size prefix doesn't
6229 affect assembly of the next line of code. */
6230 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6234 /* Copy the template we found. */
6237 if (addr_prefix_disp
!= -1)
6238 i
.tm
.operand_types
[addr_prefix_disp
]
6239 = operand_types
[addr_prefix_disp
];
6241 if (found_reverse_match
)
6243 /* If we found a reverse match we must alter the opcode direction
6244 bit and clear/flip the regmem modifier one. found_reverse_match
6245 holds bits to change (different for int & float insns). */
6247 i
.tm
.base_opcode
^= found_reverse_match
;
6249 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6250 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6252 /* Certain SIMD insns have their load forms specified in the opcode
6253 table, and hence we need to _set_ RegMem instead of clearing it.
6254 We need to avoid setting the bit though on insns like KMOVW. */
6255 i
.tm
.opcode_modifier
.regmem
6256 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6257 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6258 && !i
.tm
.opcode_modifier
.regmem
;
6267 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6268 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6270 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6272 as_bad (_("`%s' operand %u must use `%ses' segment"),
6274 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6279 /* There's only ever one segment override allowed per instruction.
6280 This instruction possibly has a legal segment override on the
6281 second operand, so copy the segment to where non-string
6282 instructions store it, allowing common code. */
6283 i
.seg
[op
] = i
.seg
[1];
6289 process_suffix (void)
6291 /* If matched instruction specifies an explicit instruction mnemonic
6293 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6294 i
.suffix
= WORD_MNEM_SUFFIX
;
6295 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6296 i
.suffix
= LONG_MNEM_SUFFIX
;
6297 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6298 i
.suffix
= QWORD_MNEM_SUFFIX
;
6299 else if (i
.reg_operands
6300 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6302 /* If there's no instruction mnemonic suffix we try to invent one
6303 based on GPR operands. */
6306 /* We take i.suffix from the last register operand specified,
6307 Destination register type is more significant than source
6308 register type. crc32 in SSE4.2 prefers source register
6310 if (i
.tm
.base_opcode
== 0xf20f38f0
6311 && i
.types
[0].bitfield
.class == Reg
)
6313 if (i
.types
[0].bitfield
.byte
)
6314 i
.suffix
= BYTE_MNEM_SUFFIX
;
6315 else if (i
.types
[0].bitfield
.word
)
6316 i
.suffix
= WORD_MNEM_SUFFIX
;
6317 else if (i
.types
[0].bitfield
.dword
)
6318 i
.suffix
= LONG_MNEM_SUFFIX
;
6319 else if (i
.types
[0].bitfield
.qword
)
6320 i
.suffix
= QWORD_MNEM_SUFFIX
;
6327 if (i
.tm
.base_opcode
== 0xf20f38f0)
6329 /* We have to know the operand size for crc32. */
6330 as_bad (_("ambiguous memory operand size for `%s`"),
6335 for (op
= i
.operands
; --op
>= 0;)
6336 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6337 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6339 if (i
.types
[op
].bitfield
.class != Reg
)
6341 if (i
.types
[op
].bitfield
.byte
)
6342 i
.suffix
= BYTE_MNEM_SUFFIX
;
6343 else if (i
.types
[op
].bitfield
.word
)
6344 i
.suffix
= WORD_MNEM_SUFFIX
;
6345 else if (i
.types
[op
].bitfield
.dword
)
6346 i
.suffix
= LONG_MNEM_SUFFIX
;
6347 else if (i
.types
[op
].bitfield
.qword
)
6348 i
.suffix
= QWORD_MNEM_SUFFIX
;
6355 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6358 && i
.tm
.opcode_modifier
.ignoresize
6359 && i
.tm
.opcode_modifier
.no_bsuf
)
6361 else if (!check_byte_reg ())
6364 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6367 && i
.tm
.opcode_modifier
.ignoresize
6368 && i
.tm
.opcode_modifier
.no_lsuf
6369 && !i
.tm
.opcode_modifier
.todword
6370 && !i
.tm
.opcode_modifier
.toqword
)
6372 else if (!check_long_reg ())
6375 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6378 && i
.tm
.opcode_modifier
.ignoresize
6379 && i
.tm
.opcode_modifier
.no_qsuf
6380 && !i
.tm
.opcode_modifier
.todword
6381 && !i
.tm
.opcode_modifier
.toqword
)
6383 else if (!check_qword_reg ())
6386 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6389 && i
.tm
.opcode_modifier
.ignoresize
6390 && i
.tm
.opcode_modifier
.no_wsuf
)
6392 else if (!check_word_reg ())
6395 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6396 /* Do nothing if the instruction is going to ignore the prefix. */
6401 else if (i
.tm
.opcode_modifier
.defaultsize
6403 /* exclude fldenv/frstor/fsave/fstenv */
6404 && i
.tm
.opcode_modifier
.no_ssuf
6405 /* exclude sysret */
6406 && i
.tm
.base_opcode
!= 0x0f07)
6408 i
.suffix
= stackop_size
;
6409 if (stackop_size
== LONG_MNEM_SUFFIX
)
6411 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6412 .code16gcc directive to support 16-bit mode with
6413 32-bit address. For IRET without a suffix, generate
6414 16-bit IRET (opcode 0xcf) to return from an interrupt
6416 if (i
.tm
.base_opcode
== 0xcf)
6418 i
.suffix
= WORD_MNEM_SUFFIX
;
6419 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6421 /* Warn about changed behavior for segment register push/pop. */
6422 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6423 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6427 else if (intel_syntax
6429 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6430 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6431 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6432 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6433 && i
.tm
.extension_opcode
<= 3)))
6438 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6440 i
.suffix
= QWORD_MNEM_SUFFIX
;
6445 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6446 i
.suffix
= LONG_MNEM_SUFFIX
;
6449 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6450 i
.suffix
= WORD_MNEM_SUFFIX
;
6459 if (i
.tm
.opcode_modifier
.w
)
6461 as_bad (_("no instruction mnemonic suffix given and "
6462 "no register operands; can't size instruction"));
6468 unsigned int suffixes
;
6470 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6471 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6473 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6475 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6477 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6479 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6482 /* There are more than suffix matches. */
6483 if (i
.tm
.opcode_modifier
.w
6484 || ((suffixes
& (suffixes
- 1))
6485 && !i
.tm
.opcode_modifier
.defaultsize
6486 && !i
.tm
.opcode_modifier
.ignoresize
))
6488 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6494 /* Change the opcode based on the operand size given by i.suffix. */
6497 /* Size floating point instruction. */
6498 case LONG_MNEM_SUFFIX
:
6499 if (i
.tm
.opcode_modifier
.floatmf
)
6501 i
.tm
.base_opcode
^= 4;
6505 case WORD_MNEM_SUFFIX
:
6506 case QWORD_MNEM_SUFFIX
:
6507 /* It's not a byte, select word/dword operation. */
6508 if (i
.tm
.opcode_modifier
.w
)
6510 if (i
.tm
.opcode_modifier
.shortform
)
6511 i
.tm
.base_opcode
|= 8;
6513 i
.tm
.base_opcode
|= 1;
6516 case SHORT_MNEM_SUFFIX
:
6517 /* Now select between word & dword operations via the operand
6518 size prefix, except for instructions that will ignore this
6520 if (i
.reg_operands
> 0
6521 && i
.types
[0].bitfield
.class == Reg
6522 && i
.tm
.opcode_modifier
.addrprefixopreg
6523 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6524 || i
.operands
== 1))
6526 /* The address size override prefix changes the size of the
6528 if ((flag_code
== CODE_32BIT
6529 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6530 || (flag_code
!= CODE_32BIT
6531 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6532 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6535 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6536 && !i
.tm
.opcode_modifier
.ignoresize
6537 && !i
.tm
.opcode_modifier
.floatmf
6538 && !is_any_vex_encoding (&i
.tm
)
6539 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6540 || (flag_code
== CODE_64BIT
6541 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6543 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6545 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6546 prefix
= ADDR_PREFIX_OPCODE
;
6548 if (!add_prefix (prefix
))
6552 /* Set mode64 for an operand. */
6553 if (i
.suffix
== QWORD_MNEM_SUFFIX
6554 && flag_code
== CODE_64BIT
6555 && !i
.tm
.opcode_modifier
.norex64
6556 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6558 && ! (i
.operands
== 2
6559 && i
.tm
.base_opcode
== 0x90
6560 && i
.tm
.extension_opcode
== None
6561 && i
.types
[0].bitfield
.instance
== Accum
6562 && i
.types
[0].bitfield
.qword
6563 && i
.types
[1].bitfield
.instance
== Accum
6564 && i
.types
[1].bitfield
.qword
))
6570 if (i
.reg_operands
!= 0
6572 && i
.tm
.opcode_modifier
.addrprefixopreg
6573 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6575 /* Check invalid register operand when the address size override
6576 prefix changes the size of register operands. */
6578 enum { need_word
, need_dword
, need_qword
} need
;
6580 if (flag_code
== CODE_32BIT
)
6581 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6584 if (i
.prefix
[ADDR_PREFIX
])
6587 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6590 for (op
= 0; op
< i
.operands
; op
++)
6591 if (i
.types
[op
].bitfield
.class == Reg
6592 && ((need
== need_word
6593 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6594 || (need
== need_dword
6595 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6596 || (need
== need_qword
6597 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6599 as_bad (_("invalid register operand size for `%s'"),
6609 check_byte_reg (void)
6613 for (op
= i
.operands
; --op
>= 0;)
6615 /* Skip non-register operands. */
6616 if (i
.types
[op
].bitfield
.class != Reg
)
6619 /* If this is an eight bit register, it's OK. If it's the 16 or
6620 32 bit version of an eight bit register, we will just use the
6621 low portion, and that's OK too. */
6622 if (i
.types
[op
].bitfield
.byte
)
6625 /* I/O port address operands are OK too. */
6626 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6627 && i
.tm
.operand_types
[op
].bitfield
.word
)
6630 /* crc32 doesn't generate this warning. */
6631 if (i
.tm
.base_opcode
== 0xf20f38f0)
6634 if ((i
.types
[op
].bitfield
.word
6635 || i
.types
[op
].bitfield
.dword
6636 || i
.types
[op
].bitfield
.qword
)
6637 && i
.op
[op
].regs
->reg_num
< 4
6638 /* Prohibit these changes in 64bit mode, since the lowering
6639 would be more complicated. */
6640 && flag_code
!= CODE_64BIT
)
6642 #if REGISTER_WARNINGS
6643 if (!quiet_warnings
)
6644 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6646 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6647 ? REGNAM_AL
- REGNAM_AX
6648 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6650 i
.op
[op
].regs
->reg_name
,
6655 /* Any other register is bad. */
6656 if (i
.types
[op
].bitfield
.class == Reg
6657 || i
.types
[op
].bitfield
.class == RegMMX
6658 || i
.types
[op
].bitfield
.class == RegSIMD
6659 || i
.types
[op
].bitfield
.class == SReg
6660 || i
.types
[op
].bitfield
.class == RegCR
6661 || i
.types
[op
].bitfield
.class == RegDR
6662 || i
.types
[op
].bitfield
.class == RegTR
)
6664 as_bad (_("`%s%s' not allowed with `%s%c'"),
6666 i
.op
[op
].regs
->reg_name
,
6676 check_long_reg (void)
6680 for (op
= i
.operands
; --op
>= 0;)
6681 /* Skip non-register operands. */
6682 if (i
.types
[op
].bitfield
.class != Reg
)
6684 /* Reject eight bit registers, except where the template requires
6685 them. (eg. movzb) */
6686 else if (i
.types
[op
].bitfield
.byte
6687 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6688 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6689 && (i
.tm
.operand_types
[op
].bitfield
.word
6690 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6692 as_bad (_("`%s%s' not allowed with `%s%c'"),
6694 i
.op
[op
].regs
->reg_name
,
6699 /* Warn if the e prefix on a general reg is missing. */
6700 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6701 && i
.types
[op
].bitfield
.word
6702 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6703 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6704 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6706 /* Prohibit these changes in the 64bit mode, since the
6707 lowering is more complicated. */
6708 if (flag_code
== CODE_64BIT
)
6710 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6711 register_prefix
, i
.op
[op
].regs
->reg_name
,
6715 #if REGISTER_WARNINGS
6716 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6718 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6719 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6722 /* Warn if the r prefix on a general reg is present. */
6723 else if (i
.types
[op
].bitfield
.qword
6724 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6725 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6726 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6729 && i
.tm
.opcode_modifier
.toqword
6730 && i
.types
[0].bitfield
.class != RegSIMD
)
6732 /* Convert to QWORD. We want REX byte. */
6733 i
.suffix
= QWORD_MNEM_SUFFIX
;
6737 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6738 register_prefix
, i
.op
[op
].regs
->reg_name
,
6747 check_qword_reg (void)
6751 for (op
= i
.operands
; --op
>= 0; )
6752 /* Skip non-register operands. */
6753 if (i
.types
[op
].bitfield
.class != Reg
)
6755 /* Reject eight bit registers, except where the template requires
6756 them. (eg. movzb) */
6757 else if (i
.types
[op
].bitfield
.byte
6758 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6759 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6760 && (i
.tm
.operand_types
[op
].bitfield
.word
6761 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6763 as_bad (_("`%s%s' not allowed with `%s%c'"),
6765 i
.op
[op
].regs
->reg_name
,
6770 /* Warn if the r prefix on a general reg is missing. */
6771 else if ((i
.types
[op
].bitfield
.word
6772 || i
.types
[op
].bitfield
.dword
)
6773 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6774 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6775 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6777 /* Prohibit these changes in the 64bit mode, since the
6778 lowering is more complicated. */
6780 && i
.tm
.opcode_modifier
.todword
6781 && i
.types
[0].bitfield
.class != RegSIMD
)
6783 /* Convert to DWORD. We don't want REX byte. */
6784 i
.suffix
= LONG_MNEM_SUFFIX
;
6788 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6789 register_prefix
, i
.op
[op
].regs
->reg_name
,
6798 check_word_reg (void)
6801 for (op
= i
.operands
; --op
>= 0;)
6802 /* Skip non-register operands. */
6803 if (i
.types
[op
].bitfield
.class != Reg
)
6805 /* Reject eight bit registers, except where the template requires
6806 them. (eg. movzb) */
6807 else if (i
.types
[op
].bitfield
.byte
6808 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6809 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6810 && (i
.tm
.operand_types
[op
].bitfield
.word
6811 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6813 as_bad (_("`%s%s' not allowed with `%s%c'"),
6815 i
.op
[op
].regs
->reg_name
,
6820 /* Warn if the e or r prefix on a general reg is present. */
6821 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6822 && (i
.types
[op
].bitfield
.dword
6823 || i
.types
[op
].bitfield
.qword
)
6824 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6825 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6826 && i
.tm
.operand_types
[op
].bitfield
.word
)
6828 /* Prohibit these changes in the 64bit mode, since the
6829 lowering is more complicated. */
6830 if (flag_code
== CODE_64BIT
)
6832 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6833 register_prefix
, i
.op
[op
].regs
->reg_name
,
6837 #if REGISTER_WARNINGS
6838 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6840 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6841 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6848 update_imm (unsigned int j
)
6850 i386_operand_type overlap
= i
.types
[j
];
6851 if ((overlap
.bitfield
.imm8
6852 || overlap
.bitfield
.imm8s
6853 || overlap
.bitfield
.imm16
6854 || overlap
.bitfield
.imm32
6855 || overlap
.bitfield
.imm32s
6856 || overlap
.bitfield
.imm64
)
6857 && !operand_type_equal (&overlap
, &imm8
)
6858 && !operand_type_equal (&overlap
, &imm8s
)
6859 && !operand_type_equal (&overlap
, &imm16
)
6860 && !operand_type_equal (&overlap
, &imm32
)
6861 && !operand_type_equal (&overlap
, &imm32s
)
6862 && !operand_type_equal (&overlap
, &imm64
))
6866 i386_operand_type temp
;
6868 operand_type_set (&temp
, 0);
6869 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6871 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6872 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6874 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6875 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6876 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6878 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6879 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6882 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6885 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6886 || operand_type_equal (&overlap
, &imm16_32
)
6887 || operand_type_equal (&overlap
, &imm16_32s
))
6889 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6894 if (!operand_type_equal (&overlap
, &imm8
)
6895 && !operand_type_equal (&overlap
, &imm8s
)
6896 && !operand_type_equal (&overlap
, &imm16
)
6897 && !operand_type_equal (&overlap
, &imm32
)
6898 && !operand_type_equal (&overlap
, &imm32s
)
6899 && !operand_type_equal (&overlap
, &imm64
))
6901 as_bad (_("no instruction mnemonic suffix given; "
6902 "can't determine immediate size"));
6906 i
.types
[j
] = overlap
;
6916 /* Update the first 2 immediate operands. */
6917 n
= i
.operands
> 2 ? 2 : i
.operands
;
6920 for (j
= 0; j
< n
; j
++)
6921 if (update_imm (j
) == 0)
6924 /* The 3rd operand can't be immediate operand. */
6925 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6932 process_operands (void)
6934 /* Default segment register this instruction will use for memory
6935 accesses. 0 means unknown. This is only for optimizing out
6936 unnecessary segment overrides. */
6937 const seg_entry
*default_seg
= 0;
6939 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6941 unsigned int dupl
= i
.operands
;
6942 unsigned int dest
= dupl
- 1;
6945 /* The destination must be an xmm register. */
6946 gas_assert (i
.reg_operands
6947 && MAX_OPERANDS
> dupl
6948 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6950 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6951 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6953 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6955 /* Keep xmm0 for instructions with VEX prefix and 3
6957 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6958 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6963 /* We remove the first xmm0 and keep the number of
6964 operands unchanged, which in fact duplicates the
6966 for (j
= 1; j
< i
.operands
; j
++)
6968 i
.op
[j
- 1] = i
.op
[j
];
6969 i
.types
[j
- 1] = i
.types
[j
];
6970 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6971 i
.flags
[j
- 1] = i
.flags
[j
];
6975 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6977 gas_assert ((MAX_OPERANDS
- 1) > dupl
6978 && (i
.tm
.opcode_modifier
.vexsources
6981 /* Add the implicit xmm0 for instructions with VEX prefix
6983 for (j
= i
.operands
; j
> 0; j
--)
6985 i
.op
[j
] = i
.op
[j
- 1];
6986 i
.types
[j
] = i
.types
[j
- 1];
6987 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6988 i
.flags
[j
] = i
.flags
[j
- 1];
6991 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6992 i
.types
[0] = regxmm
;
6993 i
.tm
.operand_types
[0] = regxmm
;
6996 i
.reg_operands
+= 2;
7001 i
.op
[dupl
] = i
.op
[dest
];
7002 i
.types
[dupl
] = i
.types
[dest
];
7003 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7004 i
.flags
[dupl
] = i
.flags
[dest
];
7013 i
.op
[dupl
] = i
.op
[dest
];
7014 i
.types
[dupl
] = i
.types
[dest
];
7015 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7016 i
.flags
[dupl
] = i
.flags
[dest
];
7019 if (i
.tm
.opcode_modifier
.immext
)
7022 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7023 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7027 for (j
= 1; j
< i
.operands
; j
++)
7029 i
.op
[j
- 1] = i
.op
[j
];
7030 i
.types
[j
- 1] = i
.types
[j
];
7032 /* We need to adjust fields in i.tm since they are used by
7033 build_modrm_byte. */
7034 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7036 i
.flags
[j
- 1] = i
.flags
[j
];
7043 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7045 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7047 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7048 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7049 regnum
= register_number (i
.op
[1].regs
);
7050 first_reg_in_group
= regnum
& ~3;
7051 last_reg_in_group
= first_reg_in_group
+ 3;
7052 if (regnum
!= first_reg_in_group
)
7053 as_warn (_("source register `%s%s' implicitly denotes"
7054 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7055 register_prefix
, i
.op
[1].regs
->reg_name
,
7056 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7057 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7060 else if (i
.tm
.opcode_modifier
.regkludge
)
7062 /* The imul $imm, %reg instruction is converted into
7063 imul $imm, %reg, %reg, and the clr %reg instruction
7064 is converted into xor %reg, %reg. */
7066 unsigned int first_reg_op
;
7068 if (operand_type_check (i
.types
[0], reg
))
7072 /* Pretend we saw the extra register operand. */
7073 gas_assert (i
.reg_operands
== 1
7074 && i
.op
[first_reg_op
+ 1].regs
== 0);
7075 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7076 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7081 if (i
.tm
.opcode_modifier
.modrm
)
7083 /* The opcode is completed (modulo i.tm.extension_opcode which
7084 must be put into the modrm byte). Now, we make the modrm and
7085 index base bytes based on all the info we've collected. */
7087 default_seg
= build_modrm_byte ();
7089 else if (i
.types
[0].bitfield
.class == SReg
)
7091 if (flag_code
!= CODE_64BIT
7092 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7093 && i
.op
[0].regs
->reg_num
== 1
7094 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7095 && i
.op
[0].regs
->reg_num
< 4)
7097 as_bad (_("you can't `%s %s%s'"),
7098 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7101 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7103 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7104 i
.tm
.opcode_length
= 2;
7106 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7108 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7112 else if (i
.tm
.opcode_modifier
.isstring
)
7114 /* For the string instructions that allow a segment override
7115 on one of their operands, the default segment is ds. */
7118 else if (i
.tm
.opcode_modifier
.shortform
)
7120 /* The register or float register operand is in operand
7122 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7124 /* Register goes in low 3 bits of opcode. */
7125 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7126 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7128 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7130 /* Warn about some common errors, but press on regardless.
7131 The first case can be generated by gcc (<= 2.8.1). */
7132 if (i
.operands
== 2)
7134 /* Reversed arguments on faddp, fsubp, etc. */
7135 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7136 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7137 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7141 /* Extraneous `l' suffix on fp insn. */
7142 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7143 register_prefix
, i
.op
[0].regs
->reg_name
);
7148 if (i
.tm
.base_opcode
== 0x8d /* lea */
7151 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7153 /* If a segment was explicitly specified, and the specified segment
7154 is not the default, use an opcode prefix to select it. If we
7155 never figured out what the default segment is, then default_seg
7156 will be zero at this point, and the specified segment prefix will
7158 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7160 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7166 static const seg_entry
*
7167 build_modrm_byte (void)
7169 const seg_entry
*default_seg
= 0;
7170 unsigned int source
, dest
;
7173 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7176 unsigned int nds
, reg_slot
;
7179 dest
= i
.operands
- 1;
7182 /* There are 2 kinds of instructions:
7183 1. 5 operands: 4 register operands or 3 register operands
7184 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7185 VexW0 or VexW1. The destination must be either XMM, YMM or
7187 2. 4 operands: 4 register operands or 3 register operands
7188 plus 1 memory operand, with VexXDS. */
7189 gas_assert ((i
.reg_operands
== 4
7190 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7191 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7192 && i
.tm
.opcode_modifier
.vexw
7193 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7195 /* If VexW1 is set, the first non-immediate operand is the source and
7196 the second non-immediate one is encoded in the immediate operand. */
7197 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7199 source
= i
.imm_operands
;
7200 reg_slot
= i
.imm_operands
+ 1;
7204 source
= i
.imm_operands
+ 1;
7205 reg_slot
= i
.imm_operands
;
7208 if (i
.imm_operands
== 0)
7210 /* When there is no immediate operand, generate an 8bit
7211 immediate operand to encode the first operand. */
7212 exp
= &im_expressions
[i
.imm_operands
++];
7213 i
.op
[i
.operands
].imms
= exp
;
7214 i
.types
[i
.operands
] = imm8
;
7217 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7218 exp
->X_op
= O_constant
;
7219 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7220 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7224 gas_assert (i
.imm_operands
== 1);
7225 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7226 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7228 /* Turn on Imm8 again so that output_imm will generate it. */
7229 i
.types
[0].bitfield
.imm8
= 1;
7231 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7232 i
.op
[0].imms
->X_add_number
7233 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7234 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7237 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7238 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7243 /* i.reg_operands MUST be the number of real register operands;
7244 implicit registers do not count. If there are 3 register
7245 operands, it must be a instruction with VexNDS. For a
7246 instruction with VexNDD, the destination register is encoded
7247 in VEX prefix. If there are 4 register operands, it must be
7248 a instruction with VEX prefix and 3 sources. */
7249 if (i
.mem_operands
== 0
7250 && ((i
.reg_operands
== 2
7251 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7252 || (i
.reg_operands
== 3
7253 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7254 || (i
.reg_operands
== 4 && vex_3_sources
)))
7262 /* When there are 3 operands, one of them may be immediate,
7263 which may be the first or the last operand. Otherwise,
7264 the first operand must be shift count register (cl) or it
7265 is an instruction with VexNDS. */
7266 gas_assert (i
.imm_operands
== 1
7267 || (i
.imm_operands
== 0
7268 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7269 || (i
.types
[0].bitfield
.instance
== RegC
7270 && i
.types
[0].bitfield
.byte
))));
7271 if (operand_type_check (i
.types
[0], imm
)
7272 || (i
.types
[0].bitfield
.instance
== RegC
7273 && i
.types
[0].bitfield
.byte
))
7279 /* When there are 4 operands, the first two must be 8bit
7280 immediate operands. The source operand will be the 3rd
7283 For instructions with VexNDS, if the first operand
7284 an imm8, the source operand is the 2nd one. If the last
7285 operand is imm8, the source operand is the first one. */
7286 gas_assert ((i
.imm_operands
== 2
7287 && i
.types
[0].bitfield
.imm8
7288 && i
.types
[1].bitfield
.imm8
)
7289 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7290 && i
.imm_operands
== 1
7291 && (i
.types
[0].bitfield
.imm8
7292 || i
.types
[i
.operands
- 1].bitfield
.imm8
7294 if (i
.imm_operands
== 2)
7298 if (i
.types
[0].bitfield
.imm8
)
7305 if (is_evex_encoding (&i
.tm
))
7307 /* For EVEX instructions, when there are 5 operands, the
7308 first one must be immediate operand. If the second one
7309 is immediate operand, the source operand is the 3th
7310 one. If the last one is immediate operand, the source
7311 operand is the 2nd one. */
7312 gas_assert (i
.imm_operands
== 2
7313 && i
.tm
.opcode_modifier
.sae
7314 && operand_type_check (i
.types
[0], imm
));
7315 if (operand_type_check (i
.types
[1], imm
))
7317 else if (operand_type_check (i
.types
[4], imm
))
7331 /* RC/SAE operand could be between DEST and SRC. That happens
7332 when one operand is GPR and the other one is XMM/YMM/ZMM
7334 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7337 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7339 /* For instructions with VexNDS, the register-only source
7340 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7341 register. It is encoded in VEX prefix. */
7343 i386_operand_type op
;
7346 /* Check register-only source operand when two source
7347 operands are swapped. */
7348 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7349 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7357 op
= i
.tm
.operand_types
[vvvv
];
7358 if ((dest
+ 1) >= i
.operands
7359 || ((op
.bitfield
.class != Reg
7360 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7361 && op
.bitfield
.class != RegSIMD
7362 && !operand_type_equal (&op
, ®mask
)))
7364 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7370 /* One of the register operands will be encoded in the i.rm.reg
7371 field, the other in the combined i.rm.mode and i.rm.regmem
7372 fields. If no form of this instruction supports a memory
7373 destination operand, then we assume the source operand may
7374 sometimes be a memory operand and so we need to store the
7375 destination in the i.rm.reg field. */
7376 if (!i
.tm
.opcode_modifier
.regmem
7377 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7379 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7380 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7381 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7382 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7383 i
.has_regmmx
= TRUE
;
7384 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7385 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7387 if (i
.types
[dest
].bitfield
.zmmword
7388 || i
.types
[source
].bitfield
.zmmword
)
7389 i
.has_regzmm
= TRUE
;
7390 else if (i
.types
[dest
].bitfield
.ymmword
7391 || i
.types
[source
].bitfield
.ymmword
)
7392 i
.has_regymm
= TRUE
;
7394 i
.has_regxmm
= TRUE
;
7396 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7398 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7400 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7402 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7407 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7408 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7409 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7411 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7413 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7415 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7418 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7420 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7423 add_prefix (LOCK_PREFIX_OPCODE
);
7427 { /* If it's not 2 reg operands... */
7432 unsigned int fake_zero_displacement
= 0;
7435 for (op
= 0; op
< i
.operands
; op
++)
7436 if (i
.flags
[op
] & Operand_Mem
)
7438 gas_assert (op
< i
.operands
);
7440 if (i
.tm
.opcode_modifier
.vecsib
)
7442 if (i
.index_reg
->reg_num
== RegIZ
)
7445 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7448 i
.sib
.base
= NO_BASE_REGISTER
;
7449 i
.sib
.scale
= i
.log2_scale_factor
;
7450 i
.types
[op
].bitfield
.disp8
= 0;
7451 i
.types
[op
].bitfield
.disp16
= 0;
7452 i
.types
[op
].bitfield
.disp64
= 0;
7453 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7455 /* Must be 32 bit */
7456 i
.types
[op
].bitfield
.disp32
= 1;
7457 i
.types
[op
].bitfield
.disp32s
= 0;
7461 i
.types
[op
].bitfield
.disp32
= 0;
7462 i
.types
[op
].bitfield
.disp32s
= 1;
7465 i
.sib
.index
= i
.index_reg
->reg_num
;
7466 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7468 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7474 if (i
.base_reg
== 0)
7477 if (!i
.disp_operands
)
7478 fake_zero_displacement
= 1;
7479 if (i
.index_reg
== 0)
7481 i386_operand_type newdisp
;
7483 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7484 /* Operand is just <disp> */
7485 if (flag_code
== CODE_64BIT
)
7487 /* 64bit mode overwrites the 32bit absolute
7488 addressing by RIP relative addressing and
7489 absolute addressing is encoded by one of the
7490 redundant SIB forms. */
7491 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7492 i
.sib
.base
= NO_BASE_REGISTER
;
7493 i
.sib
.index
= NO_INDEX_REGISTER
;
7494 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7496 else if ((flag_code
== CODE_16BIT
)
7497 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7499 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7504 i
.rm
.regmem
= NO_BASE_REGISTER
;
7507 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7508 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7510 else if (!i
.tm
.opcode_modifier
.vecsib
)
7512 /* !i.base_reg && i.index_reg */
7513 if (i
.index_reg
->reg_num
== RegIZ
)
7514 i
.sib
.index
= NO_INDEX_REGISTER
;
7516 i
.sib
.index
= i
.index_reg
->reg_num
;
7517 i
.sib
.base
= NO_BASE_REGISTER
;
7518 i
.sib
.scale
= i
.log2_scale_factor
;
7519 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7520 i
.types
[op
].bitfield
.disp8
= 0;
7521 i
.types
[op
].bitfield
.disp16
= 0;
7522 i
.types
[op
].bitfield
.disp64
= 0;
7523 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7525 /* Must be 32 bit */
7526 i
.types
[op
].bitfield
.disp32
= 1;
7527 i
.types
[op
].bitfield
.disp32s
= 0;
7531 i
.types
[op
].bitfield
.disp32
= 0;
7532 i
.types
[op
].bitfield
.disp32s
= 1;
7534 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7538 /* RIP addressing for 64bit mode. */
7539 else if (i
.base_reg
->reg_num
== RegIP
)
7541 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7542 i
.rm
.regmem
= NO_BASE_REGISTER
;
7543 i
.types
[op
].bitfield
.disp8
= 0;
7544 i
.types
[op
].bitfield
.disp16
= 0;
7545 i
.types
[op
].bitfield
.disp32
= 0;
7546 i
.types
[op
].bitfield
.disp32s
= 1;
7547 i
.types
[op
].bitfield
.disp64
= 0;
7548 i
.flags
[op
] |= Operand_PCrel
;
7549 if (! i
.disp_operands
)
7550 fake_zero_displacement
= 1;
7552 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7554 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7555 switch (i
.base_reg
->reg_num
)
7558 if (i
.index_reg
== 0)
7560 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7561 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7565 if (i
.index_reg
== 0)
7568 if (operand_type_check (i
.types
[op
], disp
) == 0)
7570 /* fake (%bp) into 0(%bp) */
7571 i
.types
[op
].bitfield
.disp8
= 1;
7572 fake_zero_displacement
= 1;
7575 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7576 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7578 default: /* (%si) -> 4 or (%di) -> 5 */
7579 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7581 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7583 else /* i.base_reg and 32/64 bit mode */
7585 if (flag_code
== CODE_64BIT
7586 && operand_type_check (i
.types
[op
], disp
))
7588 i
.types
[op
].bitfield
.disp16
= 0;
7589 i
.types
[op
].bitfield
.disp64
= 0;
7590 if (i
.prefix
[ADDR_PREFIX
] == 0)
7592 i
.types
[op
].bitfield
.disp32
= 0;
7593 i
.types
[op
].bitfield
.disp32s
= 1;
7597 i
.types
[op
].bitfield
.disp32
= 1;
7598 i
.types
[op
].bitfield
.disp32s
= 0;
7602 if (!i
.tm
.opcode_modifier
.vecsib
)
7603 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7604 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7606 i
.sib
.base
= i
.base_reg
->reg_num
;
7607 /* x86-64 ignores REX prefix bit here to avoid decoder
7609 if (!(i
.base_reg
->reg_flags
& RegRex
)
7610 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7611 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7613 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7615 fake_zero_displacement
= 1;
7616 i
.types
[op
].bitfield
.disp8
= 1;
7618 i
.sib
.scale
= i
.log2_scale_factor
;
7619 if (i
.index_reg
== 0)
7621 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7622 /* <disp>(%esp) becomes two byte modrm with no index
7623 register. We've already stored the code for esp
7624 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7625 Any base register besides %esp will not use the
7626 extra modrm byte. */
7627 i
.sib
.index
= NO_INDEX_REGISTER
;
7629 else if (!i
.tm
.opcode_modifier
.vecsib
)
7631 if (i
.index_reg
->reg_num
== RegIZ
)
7632 i
.sib
.index
= NO_INDEX_REGISTER
;
7634 i
.sib
.index
= i
.index_reg
->reg_num
;
7635 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7636 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7641 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7642 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7646 if (!fake_zero_displacement
7650 fake_zero_displacement
= 1;
7651 if (i
.disp_encoding
== disp_encoding_8bit
)
7652 i
.types
[op
].bitfield
.disp8
= 1;
7654 i
.types
[op
].bitfield
.disp32
= 1;
7656 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7660 if (fake_zero_displacement
)
7662 /* Fakes a zero displacement assuming that i.types[op]
7663 holds the correct displacement size. */
7666 gas_assert (i
.op
[op
].disps
== 0);
7667 exp
= &disp_expressions
[i
.disp_operands
++];
7668 i
.op
[op
].disps
= exp
;
7669 exp
->X_op
= O_constant
;
7670 exp
->X_add_number
= 0;
7671 exp
->X_add_symbol
= (symbolS
*) 0;
7672 exp
->X_op_symbol
= (symbolS
*) 0;
7680 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7682 if (operand_type_check (i
.types
[0], imm
))
7683 i
.vex
.register_specifier
= NULL
;
7686 /* VEX.vvvv encodes one of the sources when the first
7687 operand is not an immediate. */
7688 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7689 i
.vex
.register_specifier
= i
.op
[0].regs
;
7691 i
.vex
.register_specifier
= i
.op
[1].regs
;
7694 /* Destination is a XMM register encoded in the ModRM.reg
7696 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7697 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7700 /* ModRM.rm and VEX.B encodes the other source. */
7701 if (!i
.mem_operands
)
7705 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7706 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7708 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7710 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7714 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7716 i
.vex
.register_specifier
= i
.op
[2].regs
;
7717 if (!i
.mem_operands
)
7720 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7721 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7725 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7726 (if any) based on i.tm.extension_opcode. Again, we must be
7727 careful to make sure that segment/control/debug/test/MMX
7728 registers are coded into the i.rm.reg field. */
7729 else if (i
.reg_operands
)
7732 unsigned int vex_reg
= ~0;
7734 for (op
= 0; op
< i
.operands
; op
++)
7736 if (i
.types
[op
].bitfield
.class == Reg
7737 || i
.types
[op
].bitfield
.class == RegBND
7738 || i
.types
[op
].bitfield
.class == RegMask
7739 || i
.types
[op
].bitfield
.class == SReg
7740 || i
.types
[op
].bitfield
.class == RegCR
7741 || i
.types
[op
].bitfield
.class == RegDR
7742 || i
.types
[op
].bitfield
.class == RegTR
)
7744 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7746 if (i
.types
[op
].bitfield
.zmmword
)
7747 i
.has_regzmm
= TRUE
;
7748 else if (i
.types
[op
].bitfield
.ymmword
)
7749 i
.has_regymm
= TRUE
;
7751 i
.has_regxmm
= TRUE
;
7754 if (i
.types
[op
].bitfield
.class == RegMMX
)
7756 i
.has_regmmx
= TRUE
;
7763 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7765 /* For instructions with VexNDS, the register-only
7766 source operand is encoded in VEX prefix. */
7767 gas_assert (mem
!= (unsigned int) ~0);
7772 gas_assert (op
< i
.operands
);
7776 /* Check register-only source operand when two source
7777 operands are swapped. */
7778 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7779 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7783 gas_assert (mem
== (vex_reg
+ 1)
7784 && op
< i
.operands
);
7789 gas_assert (vex_reg
< i
.operands
);
7793 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7795 /* For instructions with VexNDD, the register destination
7796 is encoded in VEX prefix. */
7797 if (i
.mem_operands
== 0)
7799 /* There is no memory operand. */
7800 gas_assert ((op
+ 2) == i
.operands
);
7805 /* There are only 2 non-immediate operands. */
7806 gas_assert (op
< i
.imm_operands
+ 2
7807 && i
.operands
== i
.imm_operands
+ 2);
7808 vex_reg
= i
.imm_operands
+ 1;
7812 gas_assert (op
< i
.operands
);
7814 if (vex_reg
!= (unsigned int) ~0)
7816 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7818 if ((type
->bitfield
.class != Reg
7819 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7820 && type
->bitfield
.class != RegSIMD
7821 && !operand_type_equal (type
, ®mask
))
7824 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7827 /* Don't set OP operand twice. */
7830 /* If there is an extension opcode to put here, the
7831 register number must be put into the regmem field. */
7832 if (i
.tm
.extension_opcode
!= None
)
7834 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7835 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7837 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7842 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7843 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7845 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7850 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7851 must set it to 3 to indicate this is a register operand
7852 in the regmem field. */
7853 if (!i
.mem_operands
)
7857 /* Fill in i.rm.reg field with extension opcode (if any). */
7858 if (i
.tm
.extension_opcode
!= None
)
7859 i
.rm
.reg
= i
.tm
.extension_opcode
;
7865 output_branch (void)
7871 relax_substateT subtype
;
7875 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7876 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7879 if (i
.prefix
[DATA_PREFIX
] != 0)
7885 /* Pentium4 branch hints. */
7886 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7887 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7892 if (i
.prefix
[REX_PREFIX
] != 0)
7898 /* BND prefixed jump. */
7899 if (i
.prefix
[BND_PREFIX
] != 0)
7901 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7905 if (i
.prefixes
!= 0 && !intel_syntax
)
7906 as_warn (_("skipping prefixes on this instruction"));
7908 /* It's always a symbol; End frag & setup for relax.
7909 Make sure there is enough room in this frag for the largest
7910 instruction we may generate in md_convert_frag. This is 2
7911 bytes for the opcode and room for the prefix and largest
7913 frag_grow (prefix
+ 2 + 4);
7914 /* Prefix and 1 opcode byte go in fr_fix. */
7915 p
= frag_more (prefix
+ 1);
7916 if (i
.prefix
[DATA_PREFIX
] != 0)
7917 *p
++ = DATA_PREFIX_OPCODE
;
7918 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7919 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7920 *p
++ = i
.prefix
[SEG_PREFIX
];
7921 if (i
.prefix
[REX_PREFIX
] != 0)
7922 *p
++ = i
.prefix
[REX_PREFIX
];
7923 *p
= i
.tm
.base_opcode
;
7925 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7926 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7927 else if (cpu_arch_flags
.bitfield
.cpui386
)
7928 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7930 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7933 sym
= i
.op
[0].disps
->X_add_symbol
;
7934 off
= i
.op
[0].disps
->X_add_number
;
7936 if (i
.op
[0].disps
->X_op
!= O_constant
7937 && i
.op
[0].disps
->X_op
!= O_symbol
)
7939 /* Handle complex expressions. */
7940 sym
= make_expr_symbol (i
.op
[0].disps
);
7944 /* 1 possible extra opcode + 4 byte displacement go in var part.
7945 Pass reloc in fr_var. */
7946 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7950 /* Return TRUE iff PLT32 relocation should be used for branching to
7954 need_plt32_p (symbolS
*s
)
7956 /* PLT32 relocation is ELF only. */
7961 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7962 krtld support it. */
7966 /* Since there is no need to prepare for PLT branch on x86-64, we
7967 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7968 be used as a marker for 32-bit PC-relative branches. */
7972 /* Weak or undefined symbol need PLT32 relocation. */
7973 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7976 /* Non-global symbol doesn't need PLT32 relocation. */
7977 if (! S_IS_EXTERNAL (s
))
7980 /* Other global symbols need PLT32 relocation. NB: Symbol with
7981 non-default visibilities are treated as normal global symbol
7982 so that PLT32 relocation can be used as a marker for 32-bit
7983 PC-relative branches. It is useful for linker relaxation. */
7994 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7996 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
7998 /* This is a loop or jecxz type instruction. */
8000 if (i
.prefix
[ADDR_PREFIX
] != 0)
8002 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8005 /* Pentium4 branch hints. */
8006 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8007 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8009 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8018 if (flag_code
== CODE_16BIT
)
8021 if (i
.prefix
[DATA_PREFIX
] != 0)
8023 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8033 if (i
.prefix
[REX_PREFIX
] != 0)
8035 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8039 /* BND prefixed jump. */
8040 if (i
.prefix
[BND_PREFIX
] != 0)
8042 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8046 if (i
.prefixes
!= 0 && !intel_syntax
)
8047 as_warn (_("skipping prefixes on this instruction"));
8049 p
= frag_more (i
.tm
.opcode_length
+ size
);
8050 switch (i
.tm
.opcode_length
)
8053 *p
++ = i
.tm
.base_opcode
>> 8;
8056 *p
++ = i
.tm
.base_opcode
;
8062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8064 && jump_reloc
== NO_RELOC
8065 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8066 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8069 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8071 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8072 i
.op
[0].disps
, 1, jump_reloc
);
8074 /* All jumps handled here are signed, but don't use a signed limit
8075 check for 32 and 16 bit jumps as we want to allow wrap around at
8076 4G and 64k respectively. */
8078 fixP
->fx_signed
= 1;
8082 output_interseg_jump (void)
8090 if (flag_code
== CODE_16BIT
)
8094 if (i
.prefix
[DATA_PREFIX
] != 0)
8100 if (i
.prefix
[REX_PREFIX
] != 0)
8110 if (i
.prefixes
!= 0 && !intel_syntax
)
8111 as_warn (_("skipping prefixes on this instruction"));
8113 /* 1 opcode; 2 segment; offset */
8114 p
= frag_more (prefix
+ 1 + 2 + size
);
8116 if (i
.prefix
[DATA_PREFIX
] != 0)
8117 *p
++ = DATA_PREFIX_OPCODE
;
8119 if (i
.prefix
[REX_PREFIX
] != 0)
8120 *p
++ = i
.prefix
[REX_PREFIX
];
8122 *p
++ = i
.tm
.base_opcode
;
8123 if (i
.op
[1].imms
->X_op
== O_constant
)
8125 offsetT n
= i
.op
[1].imms
->X_add_number
;
8128 && !fits_in_unsigned_word (n
)
8129 && !fits_in_signed_word (n
))
8131 as_bad (_("16-bit jump out of range"));
8134 md_number_to_chars (p
, n
, size
);
8137 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8138 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8139 if (i
.op
[0].imms
->X_op
!= O_constant
)
8140 as_bad (_("can't handle non absolute segment in `%s'"),
8142 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8145 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8150 asection
*seg
= now_seg
;
8151 subsegT subseg
= now_subseg
;
8153 unsigned int alignment
, align_size_1
;
8154 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8155 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8156 unsigned int padding
;
8158 if (!IS_ELF
|| !x86_used_note
)
8161 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8163 /* The .note.gnu.property section layout:
8165 Field Length Contents
8168 n_descsz 4 The note descriptor size
8169 n_type 4 NT_GNU_PROPERTY_TYPE_0
8171 n_desc n_descsz The program property array
8175 /* Create the .note.gnu.property section. */
8176 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8177 bfd_set_section_flags (sec
,
8184 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8195 bfd_set_section_alignment (sec
, alignment
);
8196 elf_section_type (sec
) = SHT_NOTE
;
8198 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8200 isa_1_descsz_raw
= 4 + 4 + 4;
8201 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8202 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8204 feature_2_descsz_raw
= isa_1_descsz
;
8205 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8207 feature_2_descsz_raw
+= 4 + 4 + 4;
8208 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8209 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8212 descsz
= feature_2_descsz
;
8213 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8214 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8216 /* Write n_namsz. */
8217 md_number_to_chars (p
, (valueT
) 4, 4);
8219 /* Write n_descsz. */
8220 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8223 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8226 memcpy (p
+ 4 * 3, "GNU", 4);
8228 /* Write 4-byte type. */
8229 md_number_to_chars (p
+ 4 * 4,
8230 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8232 /* Write 4-byte data size. */
8233 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8235 /* Write 4-byte data. */
8236 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8238 /* Zero out paddings. */
8239 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8241 memset (p
+ 4 * 7, 0, padding
);
8243 /* Write 4-byte type. */
8244 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8245 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8247 /* Write 4-byte data size. */
8248 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8250 /* Write 4-byte data. */
8251 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8252 (valueT
) x86_feature_2_used
, 4);
8254 /* Zero out paddings. */
8255 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8257 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8259 /* We probably can't restore the current segment, for there likely
8262 subseg_set (seg
, subseg
);
8267 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8268 const char *frag_now_ptr
)
8270 unsigned int len
= 0;
8272 if (start_frag
!= frag_now
)
8274 const fragS
*fr
= start_frag
;
8279 } while (fr
&& fr
!= frag_now
);
8282 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8285 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8286 be macro-fused with conditional jumps. */
8289 maybe_fused_with_jcc_p (void)
8291 /* No RIP address. */
8292 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8295 /* No VEX/EVEX encoding. */
8296 if (is_any_vex_encoding (&i
.tm
))
8299 /* and, add, sub with destination register. */
8300 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8301 || i
.tm
.base_opcode
<= 5
8302 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8303 || ((i
.tm
.base_opcode
| 3) == 0x83
8304 && ((i
.tm
.extension_opcode
| 1) == 0x5
8305 || i
.tm
.extension_opcode
== 0x0)))
8306 return (i
.types
[1].bitfield
.class == Reg
8307 || i
.types
[1].bitfield
.instance
== Accum
);
8309 /* test, cmp with any register. */
8310 if ((i
.tm
.base_opcode
| 1) == 0x85
8311 || (i
.tm
.base_opcode
| 1) == 0xa9
8312 || ((i
.tm
.base_opcode
| 1) == 0xf7
8313 && i
.tm
.extension_opcode
== 0)
8314 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8315 || ((i
.tm
.base_opcode
| 3) == 0x83
8316 && (i
.tm
.extension_opcode
== 0x7)))
8317 return (i
.types
[0].bitfield
.class == Reg
8318 || i
.types
[0].bitfield
.instance
== Accum
8319 || i
.types
[1].bitfield
.class == Reg
8320 || i
.types
[1].bitfield
.instance
== Accum
);
8322 /* inc, dec with any register. */
8323 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8324 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8325 || ((i
.tm
.base_opcode
| 1) == 0xff
8326 && i
.tm
.extension_opcode
<= 0x1))
8327 return (i
.types
[0].bitfield
.class == Reg
8328 || i
.types
[0].bitfield
.instance
== Accum
);
8333 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8336 add_fused_jcc_padding_frag_p (void)
8338 /* NB: Don't work with COND_JUMP86 without i386. */
8339 if (!align_branch_power
8340 || now_seg
== absolute_section
8341 || !cpu_arch_flags
.bitfield
.cpui386
8342 || !(align_branch
& align_branch_fused_bit
))
8345 if (maybe_fused_with_jcc_p ())
8347 if (last_insn
.kind
== last_insn_other
8348 || last_insn
.seg
!= now_seg
)
8351 as_warn_where (last_insn
.file
, last_insn
.line
,
8352 _("`%s` skips -malign-branch-boundary on `%s`"),
8353 last_insn
.name
, i
.tm
.name
);
8359 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8362 add_branch_prefix_frag_p (void)
8364 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8365 to PadLock instructions since they include prefixes in opcode. */
8366 if (!align_branch_power
8367 || !align_branch_prefix_size
8368 || now_seg
== absolute_section
8369 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8370 || !cpu_arch_flags
.bitfield
.cpui386
)
8373 /* Don't add prefix if it is a prefix or there is no operand in case
8374 that segment prefix is special. */
8375 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8378 if (last_insn
.kind
== last_insn_other
8379 || last_insn
.seg
!= now_seg
)
8383 as_warn_where (last_insn
.file
, last_insn
.line
,
8384 _("`%s` skips -malign-branch-boundary on `%s`"),
8385 last_insn
.name
, i
.tm
.name
);
8390 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8393 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8397 /* NB: Don't work with COND_JUMP86 without i386. */
8398 if (!align_branch_power
8399 || now_seg
== absolute_section
8400 || !cpu_arch_flags
.bitfield
.cpui386
)
8405 /* Check for jcc and direct jmp. */
8406 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8408 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8410 *branch_p
= align_branch_jmp
;
8411 add_padding
= align_branch
& align_branch_jmp_bit
;
8415 *branch_p
= align_branch_jcc
;
8416 if ((align_branch
& align_branch_jcc_bit
))
8420 else if (is_any_vex_encoding (&i
.tm
))
8422 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8425 *branch_p
= align_branch_ret
;
8426 if ((align_branch
& align_branch_ret_bit
))
8431 /* Check for indirect jmp, direct and indirect calls. */
8432 if (i
.tm
.base_opcode
== 0xe8)
8435 *branch_p
= align_branch_call
;
8436 if ((align_branch
& align_branch_call_bit
))
8439 else if (i
.tm
.base_opcode
== 0xff
8440 && (i
.tm
.extension_opcode
== 2
8441 || i
.tm
.extension_opcode
== 4))
8443 /* Indirect call and jmp. */
8444 *branch_p
= align_branch_indirect
;
8445 if ((align_branch
& align_branch_indirect_bit
))
8452 && (i
.op
[0].disps
->X_op
== O_symbol
8453 || (i
.op
[0].disps
->X_op
== O_subtract
8454 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8456 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8457 /* No padding to call to global or undefined tls_get_addr. */
8458 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8459 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8465 && last_insn
.kind
!= last_insn_other
8466 && last_insn
.seg
== now_seg
)
8469 as_warn_where (last_insn
.file
, last_insn
.line
,
8470 _("`%s` skips -malign-branch-boundary on `%s`"),
8471 last_insn
.name
, i
.tm
.name
);
8481 fragS
*insn_start_frag
;
8482 offsetT insn_start_off
;
8483 fragS
*fragP
= NULL
;
8484 enum align_branch_kind branch
= align_branch_none
;
8486 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8487 if (IS_ELF
&& x86_used_note
)
8489 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8490 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8491 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8492 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8493 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8494 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8495 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8496 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8497 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8498 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8499 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8500 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8501 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8502 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8503 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8504 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8505 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8506 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8507 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8508 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8509 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8510 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8511 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8512 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8513 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8514 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8515 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8516 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8517 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8518 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8519 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8520 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8521 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8522 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8523 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8524 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8525 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8526 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8527 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8528 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8529 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8530 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8531 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8532 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8533 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8534 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8535 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8536 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8537 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8538 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8540 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8541 || i
.tm
.cpu_flags
.bitfield
.cpu287
8542 || i
.tm
.cpu_flags
.bitfield
.cpu387
8543 || i
.tm
.cpu_flags
.bitfield
.cpu687
8544 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8545 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8547 || i
.tm
.base_opcode
== 0xf77 /* emms */
8548 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8549 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8551 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8553 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8555 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8556 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8557 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8558 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8559 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8560 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8561 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8562 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8563 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8567 /* Tie dwarf2 debug info to the address at the start of the insn.
8568 We can't do this after the insn has been output as the current
8569 frag may have been closed off. eg. by frag_var. */
8570 dwarf2_emit_insn (0);
8572 insn_start_frag
= frag_now
;
8573 insn_start_off
= frag_now_fix ();
8575 if (add_branch_padding_frag_p (&branch
))
8578 /* Branch can be 8 bytes. Leave some room for prefixes. */
8579 unsigned int max_branch_padding_size
= 14;
8581 /* Align section to boundary. */
8582 record_alignment (now_seg
, align_branch_power
);
8584 /* Make room for padding. */
8585 frag_grow (max_branch_padding_size
);
8587 /* Start of the padding. */
8592 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8593 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8596 fragP
->tc_frag_data
.branch_type
= branch
;
8597 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8601 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8603 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8604 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8606 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8607 output_interseg_jump ();
8610 /* Output normal instructions here. */
8614 unsigned int prefix
;
8617 && (i
.tm
.base_opcode
== 0xfaee8
8618 || i
.tm
.base_opcode
== 0xfaef0
8619 || i
.tm
.base_opcode
== 0xfaef8))
8621 /* Encode lfence, mfence, and sfence as
8622 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8623 offsetT val
= 0x240483f0ULL
;
8625 md_number_to_chars (p
, val
, 5);
8629 /* Some processors fail on LOCK prefix. This options makes
8630 assembler ignore LOCK prefix and serves as a workaround. */
8631 if (omit_lock_prefix
)
8633 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8635 i
.prefix
[LOCK_PREFIX
] = 0;
8639 /* Skip if this is a branch. */
8641 else if (add_fused_jcc_padding_frag_p ())
8643 /* Make room for padding. */
8644 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8649 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8650 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8653 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8654 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8656 else if (add_branch_prefix_frag_p ())
8658 unsigned int max_prefix_size
= align_branch_prefix_size
;
8660 /* Make room for padding. */
8661 frag_grow (max_prefix_size
);
8666 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8667 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8670 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8673 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8674 don't need the explicit prefix. */
8675 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8677 switch (i
.tm
.opcode_length
)
8680 if (i
.tm
.base_opcode
& 0xff000000)
8682 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8683 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8684 || prefix
!= REPE_PREFIX_OPCODE
8685 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8686 add_prefix (prefix
);
8690 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8692 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8693 add_prefix (prefix
);
8699 /* Check for pseudo prefixes. */
8700 as_bad_where (insn_start_frag
->fr_file
,
8701 insn_start_frag
->fr_line
,
8702 _("pseudo prefix without instruction"));
8708 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8709 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8710 R_X86_64_GOTTPOFF relocation so that linker can safely
8711 perform IE->LE optimization. */
8712 if (x86_elf_abi
== X86_64_X32_ABI
8714 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8715 && i
.prefix
[REX_PREFIX
] == 0)
8716 add_prefix (REX_OPCODE
);
8719 /* The prefix bytes. */
8720 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8722 FRAG_APPEND_1_CHAR (*q
);
8726 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8731 /* REX byte is encoded in VEX prefix. */
8735 FRAG_APPEND_1_CHAR (*q
);
8738 /* There should be no other prefixes for instructions
8743 /* For EVEX instructions i.vrex should become 0 after
8744 build_evex_prefix. For VEX instructions upper 16 registers
8745 aren't available, so VREX should be 0. */
8748 /* Now the VEX prefix. */
8749 p
= frag_more (i
.vex
.length
);
8750 for (j
= 0; j
< i
.vex
.length
; j
++)
8751 p
[j
] = i
.vex
.bytes
[j
];
8754 /* Now the opcode; be careful about word order here! */
8755 if (i
.tm
.opcode_length
== 1)
8757 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8761 switch (i
.tm
.opcode_length
)
8765 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8766 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8770 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8780 /* Put out high byte first: can't use md_number_to_chars! */
8781 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8782 *p
= i
.tm
.base_opcode
& 0xff;
8785 /* Now the modrm byte and sib byte (if present). */
8786 if (i
.tm
.opcode_modifier
.modrm
)
8788 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8791 /* If i.rm.regmem == ESP (4)
8792 && i.rm.mode != (Register mode)
8794 ==> need second modrm byte. */
8795 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8797 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8798 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8800 | i
.sib
.scale
<< 6));
8803 if (i
.disp_operands
)
8804 output_disp (insn_start_frag
, insn_start_off
);
8807 output_imm (insn_start_frag
, insn_start_off
);
8810 * frag_now_fix () returning plain abs_section_offset when we're in the
8811 * absolute section, and abs_section_offset not getting updated as data
8812 * gets added to the frag breaks the logic below.
8814 if (now_seg
!= absolute_section
)
8816 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8818 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8822 /* NB: Don't add prefix with GOTPC relocation since
8823 output_disp() above depends on the fixed encoding
8824 length. Can't add prefix with TLS relocation since
8825 it breaks TLS linker optimization. */
8826 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8827 /* Prefix count on the current instruction. */
8828 unsigned int count
= i
.vex
.length
;
8830 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8831 /* REX byte is encoded in VEX/EVEX prefix. */
8832 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8835 /* Count prefixes for extended opcode maps. */
8837 switch (i
.tm
.opcode_length
)
8840 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8843 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8855 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8864 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8867 /* Set the maximum prefix size in BRANCH_PREFIX
8869 if (fragP
->tc_frag_data
.max_bytes
> max
)
8870 fragP
->tc_frag_data
.max_bytes
= max
;
8871 if (fragP
->tc_frag_data
.max_bytes
> count
)
8872 fragP
->tc_frag_data
.max_bytes
-= count
;
8874 fragP
->tc_frag_data
.max_bytes
= 0;
8878 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8880 unsigned int max_prefix_size
;
8881 if (align_branch_prefix_size
> max
)
8882 max_prefix_size
= max
;
8884 max_prefix_size
= align_branch_prefix_size
;
8885 if (max_prefix_size
> count
)
8886 fragP
->tc_frag_data
.max_prefix_length
8887 = max_prefix_size
- count
;
8890 /* Use existing segment prefix if possible. Use CS
8891 segment prefix in 64-bit mode. In 32-bit mode, use SS
8892 segment prefix with ESP/EBP base register and use DS
8893 segment prefix without ESP/EBP base register. */
8894 if (i
.prefix
[SEG_PREFIX
])
8895 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8896 else if (flag_code
== CODE_64BIT
)
8897 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8899 && (i
.base_reg
->reg_num
== 4
8900 || i
.base_reg
->reg_num
== 5))
8901 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8903 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8908 /* NB: Don't work with COND_JUMP86 without i386. */
8909 if (align_branch_power
8910 && now_seg
!= absolute_section
8911 && cpu_arch_flags
.bitfield
.cpui386
)
8913 /* Terminate each frag so that we can add prefix and check for
8915 frag_wane (frag_now
);
8922 pi ("" /*line*/, &i
);
8924 #endif /* DEBUG386 */
8927 /* Return the size of the displacement operand N. */
8930 disp_size (unsigned int n
)
8934 if (i
.types
[n
].bitfield
.disp64
)
8936 else if (i
.types
[n
].bitfield
.disp8
)
8938 else if (i
.types
[n
].bitfield
.disp16
)
8943 /* Return the size of the immediate operand N. */
8946 imm_size (unsigned int n
)
8949 if (i
.types
[n
].bitfield
.imm64
)
8951 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8953 else if (i
.types
[n
].bitfield
.imm16
)
8959 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8964 for (n
= 0; n
< i
.operands
; n
++)
8966 if (operand_type_check (i
.types
[n
], disp
))
8968 if (i
.op
[n
].disps
->X_op
== O_constant
)
8970 int size
= disp_size (n
);
8971 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8973 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8975 p
= frag_more (size
);
8976 md_number_to_chars (p
, val
, size
);
8980 enum bfd_reloc_code_real reloc_type
;
8981 int size
= disp_size (n
);
8982 int sign
= i
.types
[n
].bitfield
.disp32s
;
8983 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8986 /* We can't have 8 bit displacement here. */
8987 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8989 /* The PC relative address is computed relative
8990 to the instruction boundary, so in case immediate
8991 fields follows, we need to adjust the value. */
8992 if (pcrel
&& i
.imm_operands
)
8997 for (n1
= 0; n1
< i
.operands
; n1
++)
8998 if (operand_type_check (i
.types
[n1
], imm
))
9000 /* Only one immediate is allowed for PC
9001 relative address. */
9002 gas_assert (sz
== 0);
9004 i
.op
[n
].disps
->X_add_number
-= sz
;
9006 /* We should find the immediate. */
9007 gas_assert (sz
!= 0);
9010 p
= frag_more (size
);
9011 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9013 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9014 && (((reloc_type
== BFD_RELOC_32
9015 || reloc_type
== BFD_RELOC_X86_64_32S
9016 || (reloc_type
== BFD_RELOC_64
9018 && (i
.op
[n
].disps
->X_op
== O_symbol
9019 || (i
.op
[n
].disps
->X_op
== O_add
9020 && ((symbol_get_value_expression
9021 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9023 || reloc_type
== BFD_RELOC_32_PCREL
))
9027 reloc_type
= BFD_RELOC_386_GOTPC
;
9028 i
.has_gotpc_tls_reloc
= TRUE
;
9029 i
.op
[n
].imms
->X_add_number
+=
9030 encoding_length (insn_start_frag
, insn_start_off
, p
);
9032 else if (reloc_type
== BFD_RELOC_64
)
9033 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9035 /* Don't do the adjustment for x86-64, as there
9036 the pcrel addressing is relative to the _next_
9037 insn, and that is taken care of in other code. */
9038 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9040 else if (align_branch_power
)
9044 case BFD_RELOC_386_TLS_GD
:
9045 case BFD_RELOC_386_TLS_LDM
:
9046 case BFD_RELOC_386_TLS_IE
:
9047 case BFD_RELOC_386_TLS_IE_32
:
9048 case BFD_RELOC_386_TLS_GOTIE
:
9049 case BFD_RELOC_386_TLS_GOTDESC
:
9050 case BFD_RELOC_386_TLS_DESC_CALL
:
9051 case BFD_RELOC_X86_64_TLSGD
:
9052 case BFD_RELOC_X86_64_TLSLD
:
9053 case BFD_RELOC_X86_64_GOTTPOFF
:
9054 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9055 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9056 i
.has_gotpc_tls_reloc
= TRUE
;
9061 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9062 size
, i
.op
[n
].disps
, pcrel
,
9064 /* Check for "call/jmp *mem", "mov mem, %reg",
9065 "test %reg, mem" and "binop mem, %reg" where binop
9066 is one of adc, add, and, cmp, or, sbb, sub, xor
9067 instructions without data prefix. Always generate
9068 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9069 if (i
.prefix
[DATA_PREFIX
] == 0
9070 && (generate_relax_relocations
9073 && i
.rm
.regmem
== 5))
9075 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9076 && ((i
.operands
== 1
9077 && i
.tm
.base_opcode
== 0xff
9078 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9080 && (i
.tm
.base_opcode
== 0x8b
9081 || i
.tm
.base_opcode
== 0x85
9082 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
9086 fixP
->fx_tcbit
= i
.rex
!= 0;
9088 && (i
.base_reg
->reg_num
== RegIP
))
9089 fixP
->fx_tcbit2
= 1;
9092 fixP
->fx_tcbit2
= 1;
9100 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9105 for (n
= 0; n
< i
.operands
; n
++)
9107 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9108 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9111 if (operand_type_check (i
.types
[n
], imm
))
9113 if (i
.op
[n
].imms
->X_op
== O_constant
)
9115 int size
= imm_size (n
);
9118 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9120 p
= frag_more (size
);
9121 md_number_to_chars (p
, val
, size
);
9125 /* Not absolute_section.
9126 Need a 32-bit fixup (don't support 8bit
9127 non-absolute imms). Try to support other
9129 enum bfd_reloc_code_real reloc_type
;
9130 int size
= imm_size (n
);
9133 if (i
.types
[n
].bitfield
.imm32s
9134 && (i
.suffix
== QWORD_MNEM_SUFFIX
9135 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9140 p
= frag_more (size
);
9141 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9143 /* This is tough to explain. We end up with this one if we
9144 * have operands that look like
9145 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9146 * obtain the absolute address of the GOT, and it is strongly
9147 * preferable from a performance point of view to avoid using
9148 * a runtime relocation for this. The actual sequence of
9149 * instructions often look something like:
9154 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9156 * The call and pop essentially return the absolute address
9157 * of the label .L66 and store it in %ebx. The linker itself
9158 * will ultimately change the first operand of the addl so
9159 * that %ebx points to the GOT, but to keep things simple, the
9160 * .o file must have this operand set so that it generates not
9161 * the absolute address of .L66, but the absolute address of
9162 * itself. This allows the linker itself simply treat a GOTPC
9163 * relocation as asking for a pcrel offset to the GOT to be
9164 * added in, and the addend of the relocation is stored in the
9165 * operand field for the instruction itself.
9167 * Our job here is to fix the operand so that it would add
9168 * the correct offset so that %ebx would point to itself. The
9169 * thing that is tricky is that .-.L66 will point to the
9170 * beginning of the instruction, so we need to further modify
9171 * the operand so that it will point to itself. There are
9172 * other cases where you have something like:
9174 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9176 * and here no correction would be required. Internally in
9177 * the assembler we treat operands of this form as not being
9178 * pcrel since the '.' is explicitly mentioned, and I wonder
9179 * whether it would simplify matters to do it this way. Who
9180 * knows. In earlier versions of the PIC patches, the
9181 * pcrel_adjust field was used to store the correction, but
9182 * since the expression is not pcrel, I felt it would be
9183 * confusing to do it this way. */
9185 if ((reloc_type
== BFD_RELOC_32
9186 || reloc_type
== BFD_RELOC_X86_64_32S
9187 || reloc_type
== BFD_RELOC_64
)
9189 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9190 && (i
.op
[n
].imms
->X_op
== O_symbol
9191 || (i
.op
[n
].imms
->X_op
== O_add
9192 && ((symbol_get_value_expression
9193 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9197 reloc_type
= BFD_RELOC_386_GOTPC
;
9199 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9201 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9202 i
.has_gotpc_tls_reloc
= TRUE
;
9203 i
.op
[n
].imms
->X_add_number
+=
9204 encoding_length (insn_start_frag
, insn_start_off
, p
);
9206 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9207 i
.op
[n
].imms
, 0, reloc_type
);
9213 /* x86_cons_fix_new is called via the expression parsing code when a
9214 reloc is needed. We use this hook to get the correct .got reloc. */
9215 static int cons_sign
= -1;
9218 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9219 expressionS
*exp
, bfd_reloc_code_real_type r
)
9221 r
= reloc (len
, 0, cons_sign
, r
);
9224 if (exp
->X_op
== O_secrel
)
9226 exp
->X_op
= O_symbol
;
9227 r
= BFD_RELOC_32_SECREL
;
9231 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9234 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9235 purpose of the `.dc.a' internal pseudo-op. */
9238 x86_address_bytes (void)
9240 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9242 return stdoutput
->arch_info
->bits_per_address
/ 8;
9245 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9247 # define lex_got(reloc, adjust, types) NULL
9249 /* Parse operands of the form
9250 <symbol>@GOTOFF+<nnn>
9251 and similar .plt or .got references.
9253 If we find one, set up the correct relocation in RELOC and copy the
9254 input string, minus the `@GOTOFF' into a malloc'd buffer for
9255 parsing by the calling routine. Return this buffer, and if ADJUST
9256 is non-null set it to the length of the string we removed from the
9257 input line. Otherwise return NULL. */
9259 lex_got (enum bfd_reloc_code_real
*rel
,
9261 i386_operand_type
*types
)
9263 /* Some of the relocations depend on the size of what field is to
9264 be relocated. But in our callers i386_immediate and i386_displacement
9265 we don't yet know the operand size (this will be set by insn
9266 matching). Hence we record the word32 relocation here,
9267 and adjust the reloc according to the real size in reloc(). */
9268 static const struct {
9271 const enum bfd_reloc_code_real rel
[2];
9272 const i386_operand_type types64
;
9274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9275 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9277 OPERAND_TYPE_IMM32_64
},
9279 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9280 BFD_RELOC_X86_64_PLTOFF64
},
9281 OPERAND_TYPE_IMM64
},
9282 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9283 BFD_RELOC_X86_64_PLT32
},
9284 OPERAND_TYPE_IMM32_32S_DISP32
},
9285 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9286 BFD_RELOC_X86_64_GOTPLT64
},
9287 OPERAND_TYPE_IMM64_DISP64
},
9288 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9289 BFD_RELOC_X86_64_GOTOFF64
},
9290 OPERAND_TYPE_IMM64_DISP64
},
9291 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9292 BFD_RELOC_X86_64_GOTPCREL
},
9293 OPERAND_TYPE_IMM32_32S_DISP32
},
9294 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9295 BFD_RELOC_X86_64_TLSGD
},
9296 OPERAND_TYPE_IMM32_32S_DISP32
},
9297 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9298 _dummy_first_bfd_reloc_code_real
},
9299 OPERAND_TYPE_NONE
},
9300 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9301 BFD_RELOC_X86_64_TLSLD
},
9302 OPERAND_TYPE_IMM32_32S_DISP32
},
9303 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9304 BFD_RELOC_X86_64_GOTTPOFF
},
9305 OPERAND_TYPE_IMM32_32S_DISP32
},
9306 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9307 BFD_RELOC_X86_64_TPOFF32
},
9308 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9309 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9310 _dummy_first_bfd_reloc_code_real
},
9311 OPERAND_TYPE_NONE
},
9312 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9313 BFD_RELOC_X86_64_DTPOFF32
},
9314 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9315 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9316 _dummy_first_bfd_reloc_code_real
},
9317 OPERAND_TYPE_NONE
},
9318 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9319 _dummy_first_bfd_reloc_code_real
},
9320 OPERAND_TYPE_NONE
},
9321 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9322 BFD_RELOC_X86_64_GOT32
},
9323 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9324 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9325 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9326 OPERAND_TYPE_IMM32_32S_DISP32
},
9327 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9328 BFD_RELOC_X86_64_TLSDESC_CALL
},
9329 OPERAND_TYPE_IMM32_32S_DISP32
},
9334 #if defined (OBJ_MAYBE_ELF)
9339 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9340 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9343 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9345 int len
= gotrel
[j
].len
;
9346 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9348 if (gotrel
[j
].rel
[object_64bit
] != 0)
9351 char *tmpbuf
, *past_reloc
;
9353 *rel
= gotrel
[j
].rel
[object_64bit
];
9357 if (flag_code
!= CODE_64BIT
)
9359 types
->bitfield
.imm32
= 1;
9360 types
->bitfield
.disp32
= 1;
9363 *types
= gotrel
[j
].types64
;
9366 if (j
!= 0 && GOT_symbol
== NULL
)
9367 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9369 /* The length of the first part of our input line. */
9370 first
= cp
- input_line_pointer
;
9372 /* The second part goes from after the reloc token until
9373 (and including) an end_of_line char or comma. */
9374 past_reloc
= cp
+ 1 + len
;
9376 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9378 second
= cp
+ 1 - past_reloc
;
9380 /* Allocate and copy string. The trailing NUL shouldn't
9381 be necessary, but be safe. */
9382 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9383 memcpy (tmpbuf
, input_line_pointer
, first
);
9384 if (second
!= 0 && *past_reloc
!= ' ')
9385 /* Replace the relocation token with ' ', so that
9386 errors like foo@GOTOFF1 will be detected. */
9387 tmpbuf
[first
++] = ' ';
9389 /* Increment length by 1 if the relocation token is
9394 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9395 tmpbuf
[first
+ second
] = '\0';
9399 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9400 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9405 /* Might be a symbol version string. Don't as_bad here. */
9414 /* Parse operands of the form
9415 <symbol>@SECREL32+<nnn>
9417 If we find one, set up the correct relocation in RELOC and copy the
9418 input string, minus the `@SECREL32' into a malloc'd buffer for
9419 parsing by the calling routine. Return this buffer, and if ADJUST
9420 is non-null set it to the length of the string we removed from the
9421 input line. Otherwise return NULL.
9423 This function is copied from the ELF version above adjusted for PE targets. */
9426 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9427 int *adjust ATTRIBUTE_UNUSED
,
9428 i386_operand_type
*types
)
9434 const enum bfd_reloc_code_real rel
[2];
9435 const i386_operand_type types64
;
9439 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9440 BFD_RELOC_32_SECREL
},
9441 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9447 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9448 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9451 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9453 int len
= gotrel
[j
].len
;
9455 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9457 if (gotrel
[j
].rel
[object_64bit
] != 0)
9460 char *tmpbuf
, *past_reloc
;
9462 *rel
= gotrel
[j
].rel
[object_64bit
];
9468 if (flag_code
!= CODE_64BIT
)
9470 types
->bitfield
.imm32
= 1;
9471 types
->bitfield
.disp32
= 1;
9474 *types
= gotrel
[j
].types64
;
9477 /* The length of the first part of our input line. */
9478 first
= cp
- input_line_pointer
;
9480 /* The second part goes from after the reloc token until
9481 (and including) an end_of_line char or comma. */
9482 past_reloc
= cp
+ 1 + len
;
9484 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9486 second
= cp
+ 1 - past_reloc
;
9488 /* Allocate and copy string. The trailing NUL shouldn't
9489 be necessary, but be safe. */
9490 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9491 memcpy (tmpbuf
, input_line_pointer
, first
);
9492 if (second
!= 0 && *past_reloc
!= ' ')
9493 /* Replace the relocation token with ' ', so that
9494 errors like foo@SECLREL321 will be detected. */
9495 tmpbuf
[first
++] = ' ';
9496 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9497 tmpbuf
[first
+ second
] = '\0';
9501 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9502 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9507 /* Might be a symbol version string. Don't as_bad here. */
9513 bfd_reloc_code_real_type
9514 x86_cons (expressionS
*exp
, int size
)
9516 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9518 intel_syntax
= -intel_syntax
;
9521 if (size
== 4 || (object_64bit
&& size
== 8))
9523 /* Handle @GOTOFF and the like in an expression. */
9525 char *gotfree_input_line
;
9528 save
= input_line_pointer
;
9529 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9530 if (gotfree_input_line
)
9531 input_line_pointer
= gotfree_input_line
;
9535 if (gotfree_input_line
)
9537 /* expression () has merrily parsed up to the end of line,
9538 or a comma - in the wrong buffer. Transfer how far
9539 input_line_pointer has moved to the right buffer. */
9540 input_line_pointer
= (save
9541 + (input_line_pointer
- gotfree_input_line
)
9543 free (gotfree_input_line
);
9544 if (exp
->X_op
== O_constant
9545 || exp
->X_op
== O_absent
9546 || exp
->X_op
== O_illegal
9547 || exp
->X_op
== O_register
9548 || exp
->X_op
== O_big
)
9550 char c
= *input_line_pointer
;
9551 *input_line_pointer
= 0;
9552 as_bad (_("missing or invalid expression `%s'"), save
);
9553 *input_line_pointer
= c
;
9555 else if ((got_reloc
== BFD_RELOC_386_PLT32
9556 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9557 && exp
->X_op
!= O_symbol
)
9559 char c
= *input_line_pointer
;
9560 *input_line_pointer
= 0;
9561 as_bad (_("invalid PLT expression `%s'"), save
);
9562 *input_line_pointer
= c
;
9569 intel_syntax
= -intel_syntax
;
9572 i386_intel_simplify (exp
);
9578 signed_cons (int size
)
9580 if (flag_code
== CODE_64BIT
)
9588 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9595 if (exp
.X_op
== O_symbol
)
9596 exp
.X_op
= O_secrel
;
9598 emit_expr (&exp
, 4);
9600 while (*input_line_pointer
++ == ',');
9602 input_line_pointer
--;
9603 demand_empty_rest_of_line ();
9607 /* Handle Vector operations. */
9610 check_VecOperations (char *op_string
, char *op_end
)
9612 const reg_entry
*mask
;
9617 && (op_end
== NULL
|| op_string
< op_end
))
9620 if (*op_string
== '{')
9624 /* Check broadcasts. */
9625 if (strncmp (op_string
, "1to", 3) == 0)
9630 goto duplicated_vec_op
;
9633 if (*op_string
== '8')
9635 else if (*op_string
== '4')
9637 else if (*op_string
== '2')
9639 else if (*op_string
== '1'
9640 && *(op_string
+1) == '6')
9647 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9652 broadcast_op
.type
= bcst_type
;
9653 broadcast_op
.operand
= this_operand
;
9654 broadcast_op
.bytes
= 0;
9655 i
.broadcast
= &broadcast_op
;
9657 /* Check masking operation. */
9658 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9660 /* k0 can't be used for write mask. */
9661 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9663 as_bad (_("`%s%s' can't be used for write mask"),
9664 register_prefix
, mask
->reg_name
);
9670 mask_op
.mask
= mask
;
9671 mask_op
.zeroing
= 0;
9672 mask_op
.operand
= this_operand
;
9678 goto duplicated_vec_op
;
9680 i
.mask
->mask
= mask
;
9682 /* Only "{z}" is allowed here. No need to check
9683 zeroing mask explicitly. */
9684 if (i
.mask
->operand
!= this_operand
)
9686 as_bad (_("invalid write mask `%s'"), saved
);
9693 /* Check zeroing-flag for masking operation. */
9694 else if (*op_string
== 'z')
9698 mask_op
.mask
= NULL
;
9699 mask_op
.zeroing
= 1;
9700 mask_op
.operand
= this_operand
;
9705 if (i
.mask
->zeroing
)
9708 as_bad (_("duplicated `%s'"), saved
);
9712 i
.mask
->zeroing
= 1;
9714 /* Only "{%k}" is allowed here. No need to check mask
9715 register explicitly. */
9716 if (i
.mask
->operand
!= this_operand
)
9718 as_bad (_("invalid zeroing-masking `%s'"),
9727 goto unknown_vec_op
;
9729 if (*op_string
!= '}')
9731 as_bad (_("missing `}' in `%s'"), saved
);
9736 /* Strip whitespace since the addition of pseudo prefixes
9737 changed how the scrubber treats '{'. */
9738 if (is_space_char (*op_string
))
9744 /* We don't know this one. */
9745 as_bad (_("unknown vector operation: `%s'"), saved
);
9749 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9751 as_bad (_("zeroing-masking only allowed with write mask"));
9759 i386_immediate (char *imm_start
)
9761 char *save_input_line_pointer
;
9762 char *gotfree_input_line
;
9765 i386_operand_type types
;
9767 operand_type_set (&types
, ~0);
9769 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9771 as_bad (_("at most %d immediate operands are allowed"),
9772 MAX_IMMEDIATE_OPERANDS
);
9776 exp
= &im_expressions
[i
.imm_operands
++];
9777 i
.op
[this_operand
].imms
= exp
;
9779 if (is_space_char (*imm_start
))
9782 save_input_line_pointer
= input_line_pointer
;
9783 input_line_pointer
= imm_start
;
9785 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9786 if (gotfree_input_line
)
9787 input_line_pointer
= gotfree_input_line
;
9789 exp_seg
= expression (exp
);
9793 /* Handle vector operations. */
9794 if (*input_line_pointer
== '{')
9796 input_line_pointer
= check_VecOperations (input_line_pointer
,
9798 if (input_line_pointer
== NULL
)
9802 if (*input_line_pointer
)
9803 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9805 input_line_pointer
= save_input_line_pointer
;
9806 if (gotfree_input_line
)
9808 free (gotfree_input_line
);
9810 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9811 exp
->X_op
= O_illegal
;
9814 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9818 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9819 i386_operand_type types
, const char *imm_start
)
9821 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9824 as_bad (_("missing or invalid immediate expression `%s'"),
9828 else if (exp
->X_op
== O_constant
)
9830 /* Size it properly later. */
9831 i
.types
[this_operand
].bitfield
.imm64
= 1;
9832 /* If not 64bit, sign extend val. */
9833 if (flag_code
!= CODE_64BIT
9834 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9836 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9838 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9839 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9840 && exp_seg
!= absolute_section
9841 && exp_seg
!= text_section
9842 && exp_seg
!= data_section
9843 && exp_seg
!= bss_section
9844 && exp_seg
!= undefined_section
9845 && !bfd_is_com_section (exp_seg
))
9847 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9851 else if (!intel_syntax
&& exp_seg
== reg_section
)
9854 as_bad (_("illegal immediate register operand %s"), imm_start
);
9859 /* This is an address. The size of the address will be
9860 determined later, depending on destination register,
9861 suffix, or the default for the section. */
9862 i
.types
[this_operand
].bitfield
.imm8
= 1;
9863 i
.types
[this_operand
].bitfield
.imm16
= 1;
9864 i
.types
[this_operand
].bitfield
.imm32
= 1;
9865 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9866 i
.types
[this_operand
].bitfield
.imm64
= 1;
9867 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9875 i386_scale (char *scale
)
9878 char *save
= input_line_pointer
;
9880 input_line_pointer
= scale
;
9881 val
= get_absolute_expression ();
9886 i
.log2_scale_factor
= 0;
9889 i
.log2_scale_factor
= 1;
9892 i
.log2_scale_factor
= 2;
9895 i
.log2_scale_factor
= 3;
9899 char sep
= *input_line_pointer
;
9901 *input_line_pointer
= '\0';
9902 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9904 *input_line_pointer
= sep
;
9905 input_line_pointer
= save
;
9909 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9911 as_warn (_("scale factor of %d without an index register"),
9912 1 << i
.log2_scale_factor
);
9913 i
.log2_scale_factor
= 0;
9915 scale
= input_line_pointer
;
9916 input_line_pointer
= save
;
9921 i386_displacement (char *disp_start
, char *disp_end
)
9925 char *save_input_line_pointer
;
9926 char *gotfree_input_line
;
9928 i386_operand_type bigdisp
, types
= anydisp
;
9931 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9933 as_bad (_("at most %d displacement operands are allowed"),
9934 MAX_MEMORY_OPERANDS
);
9938 operand_type_set (&bigdisp
, 0);
9940 || i
.types
[this_operand
].bitfield
.baseindex
9941 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9942 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9944 i386_addressing_mode ();
9945 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9946 if (flag_code
== CODE_64BIT
)
9950 bigdisp
.bitfield
.disp32s
= 1;
9951 bigdisp
.bitfield
.disp64
= 1;
9954 bigdisp
.bitfield
.disp32
= 1;
9956 else if ((flag_code
== CODE_16BIT
) ^ override
)
9957 bigdisp
.bitfield
.disp16
= 1;
9959 bigdisp
.bitfield
.disp32
= 1;
9963 /* For PC-relative branches, the width of the displacement
9964 is dependent upon data size, not address size. */
9965 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9966 if (flag_code
== CODE_64BIT
)
9968 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9969 bigdisp
.bitfield
.disp16
= 1;
9971 bigdisp
.bitfield
.disp32s
= 1;
9976 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9978 : LONG_MNEM_SUFFIX
));
9979 bigdisp
.bitfield
.disp32
= 1;
9980 if ((flag_code
== CODE_16BIT
) ^ override
)
9982 bigdisp
.bitfield
.disp32
= 0;
9983 bigdisp
.bitfield
.disp16
= 1;
9987 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9990 exp
= &disp_expressions
[i
.disp_operands
];
9991 i
.op
[this_operand
].disps
= exp
;
9993 save_input_line_pointer
= input_line_pointer
;
9994 input_line_pointer
= disp_start
;
9995 END_STRING_AND_SAVE (disp_end
);
9997 #ifndef GCC_ASM_O_HACK
9998 #define GCC_ASM_O_HACK 0
10001 END_STRING_AND_SAVE (disp_end
+ 1);
10002 if (i
.types
[this_operand
].bitfield
.baseIndex
10003 && displacement_string_end
[-1] == '+')
10005 /* This hack is to avoid a warning when using the "o"
10006 constraint within gcc asm statements.
10009 #define _set_tssldt_desc(n,addr,limit,type) \
10010 __asm__ __volatile__ ( \
10011 "movw %w2,%0\n\t" \
10012 "movw %w1,2+%0\n\t" \
10013 "rorl $16,%1\n\t" \
10014 "movb %b1,4+%0\n\t" \
10015 "movb %4,5+%0\n\t" \
10016 "movb $0,6+%0\n\t" \
10017 "movb %h1,7+%0\n\t" \
10019 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10021 This works great except that the output assembler ends
10022 up looking a bit weird if it turns out that there is
10023 no offset. You end up producing code that looks like:
10036 So here we provide the missing zero. */
10038 *displacement_string_end
= '0';
10041 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10042 if (gotfree_input_line
)
10043 input_line_pointer
= gotfree_input_line
;
10045 exp_seg
= expression (exp
);
10047 SKIP_WHITESPACE ();
10048 if (*input_line_pointer
)
10049 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10051 RESTORE_END_STRING (disp_end
+ 1);
10053 input_line_pointer
= save_input_line_pointer
;
10054 if (gotfree_input_line
)
10056 free (gotfree_input_line
);
10058 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10059 exp
->X_op
= O_illegal
;
10062 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10064 RESTORE_END_STRING (disp_end
);
10070 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10071 i386_operand_type types
, const char *disp_start
)
10073 i386_operand_type bigdisp
;
10076 /* We do this to make sure that the section symbol is in
10077 the symbol table. We will ultimately change the relocation
10078 to be relative to the beginning of the section. */
10079 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10080 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10081 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10083 if (exp
->X_op
!= O_symbol
)
10086 if (S_IS_LOCAL (exp
->X_add_symbol
)
10087 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10088 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10089 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10090 exp
->X_op
= O_subtract
;
10091 exp
->X_op_symbol
= GOT_symbol
;
10092 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10093 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10094 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10095 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10097 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10100 else if (exp
->X_op
== O_absent
10101 || exp
->X_op
== O_illegal
10102 || exp
->X_op
== O_big
)
10105 as_bad (_("missing or invalid displacement expression `%s'"),
10110 else if (flag_code
== CODE_64BIT
10111 && !i
.prefix
[ADDR_PREFIX
]
10112 && exp
->X_op
== O_constant
)
10114 /* Since displacement is signed extended to 64bit, don't allow
10115 disp32 and turn off disp32s if they are out of range. */
10116 i
.types
[this_operand
].bitfield
.disp32
= 0;
10117 if (!fits_in_signed_long (exp
->X_add_number
))
10119 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10120 if (i
.types
[this_operand
].bitfield
.baseindex
)
10122 as_bad (_("0x%lx out range of signed 32bit displacement"),
10123 (long) exp
->X_add_number
);
10129 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10130 else if (exp
->X_op
!= O_constant
10131 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10132 && exp_seg
!= absolute_section
10133 && exp_seg
!= text_section
10134 && exp_seg
!= data_section
10135 && exp_seg
!= bss_section
10136 && exp_seg
!= undefined_section
10137 && !bfd_is_com_section (exp_seg
))
10139 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10144 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10145 /* Constants get taken care of by optimize_disp(). */
10146 && exp
->X_op
!= O_constant
)
10147 i
.types
[this_operand
].bitfield
.disp8
= 1;
10149 /* Check if this is a displacement only operand. */
10150 bigdisp
= i
.types
[this_operand
];
10151 bigdisp
.bitfield
.disp8
= 0;
10152 bigdisp
.bitfield
.disp16
= 0;
10153 bigdisp
.bitfield
.disp32
= 0;
10154 bigdisp
.bitfield
.disp32s
= 0;
10155 bigdisp
.bitfield
.disp64
= 0;
10156 if (operand_type_all_zero (&bigdisp
))
10157 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10163 /* Return the active addressing mode, taking address override and
10164 registers forming the address into consideration. Update the
10165 address override prefix if necessary. */
10167 static enum flag_code
10168 i386_addressing_mode (void)
10170 enum flag_code addr_mode
;
10172 if (i
.prefix
[ADDR_PREFIX
])
10173 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10176 addr_mode
= flag_code
;
10178 #if INFER_ADDR_PREFIX
10179 if (i
.mem_operands
== 0)
10181 /* Infer address prefix from the first memory operand. */
10182 const reg_entry
*addr_reg
= i
.base_reg
;
10184 if (addr_reg
== NULL
)
10185 addr_reg
= i
.index_reg
;
10189 if (addr_reg
->reg_type
.bitfield
.dword
)
10190 addr_mode
= CODE_32BIT
;
10191 else if (flag_code
!= CODE_64BIT
10192 && addr_reg
->reg_type
.bitfield
.word
)
10193 addr_mode
= CODE_16BIT
;
10195 if (addr_mode
!= flag_code
)
10197 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10199 /* Change the size of any displacement too. At most one
10200 of Disp16 or Disp32 is set.
10201 FIXME. There doesn't seem to be any real need for
10202 separate Disp16 and Disp32 flags. The same goes for
10203 Imm16 and Imm32. Removing them would probably clean
10204 up the code quite a lot. */
10205 if (flag_code
!= CODE_64BIT
10206 && (i
.types
[this_operand
].bitfield
.disp16
10207 || i
.types
[this_operand
].bitfield
.disp32
))
10208 i
.types
[this_operand
]
10209 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10219 /* Make sure the memory operand we've been dealt is valid.
10220 Return 1 on success, 0 on a failure. */
10223 i386_index_check (const char *operand_string
)
10225 const char *kind
= "base/index";
10226 enum flag_code addr_mode
= i386_addressing_mode ();
10228 if (current_templates
->start
->opcode_modifier
.isstring
10229 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10230 && (current_templates
->end
[-1].opcode_modifier
.isstring
10231 || i
.mem_operands
))
10233 /* Memory operands of string insns are special in that they only allow
10234 a single register (rDI, rSI, or rBX) as their memory address. */
10235 const reg_entry
*expected_reg
;
10236 static const char *di_si
[][2] =
10242 static const char *bx
[] = { "ebx", "bx", "rbx" };
10244 kind
= "string address";
10246 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10248 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10249 - IS_STRING_ES_OP0
;
10252 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10253 || ((!i
.mem_operands
!= !intel_syntax
)
10254 && current_templates
->end
[-1].operand_types
[1]
10255 .bitfield
.baseindex
))
10257 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10260 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10262 if (i
.base_reg
!= expected_reg
10264 || operand_type_check (i
.types
[this_operand
], disp
))
10266 /* The second memory operand must have the same size as
10270 && !((addr_mode
== CODE_64BIT
10271 && i
.base_reg
->reg_type
.bitfield
.qword
)
10272 || (addr_mode
== CODE_32BIT
10273 ? i
.base_reg
->reg_type
.bitfield
.dword
10274 : i
.base_reg
->reg_type
.bitfield
.word
)))
10277 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10279 intel_syntax
? '[' : '(',
10281 expected_reg
->reg_name
,
10282 intel_syntax
? ']' : ')');
10289 as_bad (_("`%s' is not a valid %s expression"),
10290 operand_string
, kind
);
10295 if (addr_mode
!= CODE_16BIT
)
10297 /* 32-bit/64-bit checks. */
10299 && ((addr_mode
== CODE_64BIT
10300 ? !i
.base_reg
->reg_type
.bitfield
.qword
10301 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10302 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10303 || i
.base_reg
->reg_num
== RegIZ
))
10305 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10306 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10307 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10308 && ((addr_mode
== CODE_64BIT
10309 ? !i
.index_reg
->reg_type
.bitfield
.qword
10310 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10311 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10314 /* bndmk, bndldx, and bndstx have special restrictions. */
10315 if (current_templates
->start
->base_opcode
== 0xf30f1b
10316 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10318 /* They cannot use RIP-relative addressing. */
10319 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10321 as_bad (_("`%s' cannot be used here"), operand_string
);
10325 /* bndldx and bndstx ignore their scale factor. */
10326 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10327 && i
.log2_scale_factor
)
10328 as_warn (_("register scaling is being ignored here"));
10333 /* 16-bit checks. */
10335 && (!i
.base_reg
->reg_type
.bitfield
.word
10336 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10338 && (!i
.index_reg
->reg_type
.bitfield
.word
10339 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10341 && i
.base_reg
->reg_num
< 6
10342 && i
.index_reg
->reg_num
>= 6
10343 && i
.log2_scale_factor
== 0))))
10350 /* Handle vector immediates. */
10353 RC_SAE_immediate (const char *imm_start
)
10355 unsigned int match_found
, j
;
10356 const char *pstr
= imm_start
;
10364 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10366 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10370 rc_op
.type
= RC_NamesTable
[j
].type
;
10371 rc_op
.operand
= this_operand
;
10372 i
.rounding
= &rc_op
;
10376 as_bad (_("duplicated `%s'"), imm_start
);
10379 pstr
+= RC_NamesTable
[j
].len
;
10387 if (*pstr
++ != '}')
10389 as_bad (_("Missing '}': '%s'"), imm_start
);
10392 /* RC/SAE immediate string should contain nothing more. */;
10395 as_bad (_("Junk after '}': '%s'"), imm_start
);
10399 exp
= &im_expressions
[i
.imm_operands
++];
10400 i
.op
[this_operand
].imms
= exp
;
10402 exp
->X_op
= O_constant
;
10403 exp
->X_add_number
= 0;
10404 exp
->X_add_symbol
= (symbolS
*) 0;
10405 exp
->X_op_symbol
= (symbolS
*) 0;
10407 i
.types
[this_operand
].bitfield
.imm8
= 1;
10411 /* Only string instructions can have a second memory operand, so
10412 reduce current_templates to just those if it contains any. */
10414 maybe_adjust_templates (void)
10416 const insn_template
*t
;
10418 gas_assert (i
.mem_operands
== 1);
10420 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10421 if (t
->opcode_modifier
.isstring
)
10424 if (t
< current_templates
->end
)
10426 static templates aux_templates
;
10427 bfd_boolean recheck
;
10429 aux_templates
.start
= t
;
10430 for (; t
< current_templates
->end
; ++t
)
10431 if (!t
->opcode_modifier
.isstring
)
10433 aux_templates
.end
= t
;
10435 /* Determine whether to re-check the first memory operand. */
10436 recheck
= (aux_templates
.start
!= current_templates
->start
10437 || t
!= current_templates
->end
);
10439 current_templates
= &aux_templates
;
10443 i
.mem_operands
= 0;
10444 if (i
.memop1_string
!= NULL
10445 && i386_index_check (i
.memop1_string
) == 0)
10447 i
.mem_operands
= 1;
10454 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10458 i386_att_operand (char *operand_string
)
10460 const reg_entry
*r
;
10462 char *op_string
= operand_string
;
10464 if (is_space_char (*op_string
))
10467 /* We check for an absolute prefix (differentiating,
10468 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10469 if (*op_string
== ABSOLUTE_PREFIX
)
10472 if (is_space_char (*op_string
))
10474 i
.jumpabsolute
= TRUE
;
10477 /* Check if operand is a register. */
10478 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10480 i386_operand_type temp
;
10482 /* Check for a segment override by searching for ':' after a
10483 segment register. */
10484 op_string
= end_op
;
10485 if (is_space_char (*op_string
))
10487 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10489 switch (r
->reg_num
)
10492 i
.seg
[i
.mem_operands
] = &es
;
10495 i
.seg
[i
.mem_operands
] = &cs
;
10498 i
.seg
[i
.mem_operands
] = &ss
;
10501 i
.seg
[i
.mem_operands
] = &ds
;
10504 i
.seg
[i
.mem_operands
] = &fs
;
10507 i
.seg
[i
.mem_operands
] = &gs
;
10511 /* Skip the ':' and whitespace. */
10513 if (is_space_char (*op_string
))
10516 if (!is_digit_char (*op_string
)
10517 && !is_identifier_char (*op_string
)
10518 && *op_string
!= '('
10519 && *op_string
!= ABSOLUTE_PREFIX
)
10521 as_bad (_("bad memory operand `%s'"), op_string
);
10524 /* Handle case of %es:*foo. */
10525 if (*op_string
== ABSOLUTE_PREFIX
)
10528 if (is_space_char (*op_string
))
10530 i
.jumpabsolute
= TRUE
;
10532 goto do_memory_reference
;
10535 /* Handle vector operations. */
10536 if (*op_string
== '{')
10538 op_string
= check_VecOperations (op_string
, NULL
);
10539 if (op_string
== NULL
)
10545 as_bad (_("junk `%s' after register"), op_string
);
10548 temp
= r
->reg_type
;
10549 temp
.bitfield
.baseindex
= 0;
10550 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10552 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10553 i
.op
[this_operand
].regs
= r
;
10556 else if (*op_string
== REGISTER_PREFIX
)
10558 as_bad (_("bad register name `%s'"), op_string
);
10561 else if (*op_string
== IMMEDIATE_PREFIX
)
10564 if (i
.jumpabsolute
)
10566 as_bad (_("immediate operand illegal with absolute jump"));
10569 if (!i386_immediate (op_string
))
10572 else if (RC_SAE_immediate (operand_string
))
10574 /* If it is a RC or SAE immediate, do nothing. */
10577 else if (is_digit_char (*op_string
)
10578 || is_identifier_char (*op_string
)
10579 || *op_string
== '"'
10580 || *op_string
== '(')
10582 /* This is a memory reference of some sort. */
10585 /* Start and end of displacement string expression (if found). */
10586 char *displacement_string_start
;
10587 char *displacement_string_end
;
10590 do_memory_reference
:
10591 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10593 if ((i
.mem_operands
== 1
10594 && !current_templates
->start
->opcode_modifier
.isstring
)
10595 || i
.mem_operands
== 2)
10597 as_bad (_("too many memory references for `%s'"),
10598 current_templates
->start
->name
);
10602 /* Check for base index form. We detect the base index form by
10603 looking for an ')' at the end of the operand, searching
10604 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10606 base_string
= op_string
+ strlen (op_string
);
10608 /* Handle vector operations. */
10609 vop_start
= strchr (op_string
, '{');
10610 if (vop_start
&& vop_start
< base_string
)
10612 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10614 base_string
= vop_start
;
10618 if (is_space_char (*base_string
))
10621 /* If we only have a displacement, set-up for it to be parsed later. */
10622 displacement_string_start
= op_string
;
10623 displacement_string_end
= base_string
+ 1;
10625 if (*base_string
== ')')
10628 unsigned int parens_balanced
= 1;
10629 /* We've already checked that the number of left & right ()'s are
10630 equal, so this loop will not be infinite. */
10634 if (*base_string
== ')')
10636 if (*base_string
== '(')
10639 while (parens_balanced
);
10641 temp_string
= base_string
;
10643 /* Skip past '(' and whitespace. */
10645 if (is_space_char (*base_string
))
10648 if (*base_string
== ','
10649 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10652 displacement_string_end
= temp_string
;
10654 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10658 base_string
= end_op
;
10659 if (is_space_char (*base_string
))
10663 /* There may be an index reg or scale factor here. */
10664 if (*base_string
== ',')
10667 if (is_space_char (*base_string
))
10670 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10673 base_string
= end_op
;
10674 if (is_space_char (*base_string
))
10676 if (*base_string
== ',')
10679 if (is_space_char (*base_string
))
10682 else if (*base_string
!= ')')
10684 as_bad (_("expecting `,' or `)' "
10685 "after index register in `%s'"),
10690 else if (*base_string
== REGISTER_PREFIX
)
10692 end_op
= strchr (base_string
, ',');
10695 as_bad (_("bad register name `%s'"), base_string
);
10699 /* Check for scale factor. */
10700 if (*base_string
!= ')')
10702 char *end_scale
= i386_scale (base_string
);
10707 base_string
= end_scale
;
10708 if (is_space_char (*base_string
))
10710 if (*base_string
!= ')')
10712 as_bad (_("expecting `)' "
10713 "after scale factor in `%s'"),
10718 else if (!i
.index_reg
)
10720 as_bad (_("expecting index register or scale factor "
10721 "after `,'; got '%c'"),
10726 else if (*base_string
!= ')')
10728 as_bad (_("expecting `,' or `)' "
10729 "after base register in `%s'"),
10734 else if (*base_string
== REGISTER_PREFIX
)
10736 end_op
= strchr (base_string
, ',');
10739 as_bad (_("bad register name `%s'"), base_string
);
10744 /* If there's an expression beginning the operand, parse it,
10745 assuming displacement_string_start and
10746 displacement_string_end are meaningful. */
10747 if (displacement_string_start
!= displacement_string_end
)
10749 if (!i386_displacement (displacement_string_start
,
10750 displacement_string_end
))
10754 /* Special case for (%dx) while doing input/output op. */
10756 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10757 && i
.base_reg
->reg_type
.bitfield
.word
10758 && i
.index_reg
== 0
10759 && i
.log2_scale_factor
== 0
10760 && i
.seg
[i
.mem_operands
] == 0
10761 && !operand_type_check (i
.types
[this_operand
], disp
))
10763 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10767 if (i386_index_check (operand_string
) == 0)
10769 i
.flags
[this_operand
] |= Operand_Mem
;
10770 if (i
.mem_operands
== 0)
10771 i
.memop1_string
= xstrdup (operand_string
);
10776 /* It's not a memory operand; argh! */
10777 as_bad (_("invalid char %s beginning operand %d `%s'"),
10778 output_invalid (*op_string
),
10783 return 1; /* Normal return. */
10786 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10787 that an rs_machine_dependent frag may reach. */
10790 i386_frag_max_var (fragS
*frag
)
10792 /* The only relaxable frags are for jumps.
10793 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10794 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10795 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10798 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10800 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10802 /* STT_GNU_IFUNC symbol must go through PLT. */
10803 if ((symbol_get_bfdsym (fr_symbol
)->flags
10804 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10807 if (!S_IS_EXTERNAL (fr_symbol
))
10808 /* Symbol may be weak or local. */
10809 return !S_IS_WEAK (fr_symbol
);
10811 /* Global symbols with non-default visibility can't be preempted. */
10812 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10815 if (fr_var
!= NO_RELOC
)
10816 switch ((enum bfd_reloc_code_real
) fr_var
)
10818 case BFD_RELOC_386_PLT32
:
10819 case BFD_RELOC_X86_64_PLT32
:
10820 /* Symbol with PLT relocation may be preempted. */
10826 /* Global symbols with default visibility in a shared library may be
10827 preempted by another definition. */
10832 /* Return the next non-empty frag. */
10835 i386_next_non_empty_frag (fragS
*fragP
)
10837 /* There may be a frag with a ".fill 0" when there is no room in
10838 the current frag for frag_grow in output_insn. */
10839 for (fragP
= fragP
->fr_next
;
10841 && fragP
->fr_type
== rs_fill
10842 && fragP
->fr_fix
== 0);
10843 fragP
= fragP
->fr_next
)
10848 /* Return the next jcc frag after BRANCH_PADDING. */
10851 i386_next_jcc_frag (fragS
*fragP
)
10856 if (fragP
->fr_type
== rs_machine_dependent
10857 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10858 == BRANCH_PADDING
))
10860 fragP
= i386_next_non_empty_frag (fragP
);
10861 if (fragP
->fr_type
!= rs_machine_dependent
)
10863 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10870 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10873 i386_classify_machine_dependent_frag (fragS
*fragP
)
10877 fragS
*branch_fragP
;
10879 unsigned int max_prefix_length
;
10881 if (fragP
->tc_frag_data
.classified
)
10884 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10885 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10886 for (next_fragP
= fragP
;
10887 next_fragP
!= NULL
;
10888 next_fragP
= next_fragP
->fr_next
)
10890 next_fragP
->tc_frag_data
.classified
= 1;
10891 if (next_fragP
->fr_type
== rs_machine_dependent
)
10892 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10894 case BRANCH_PADDING
:
10895 /* The BRANCH_PADDING frag must be followed by a branch
10897 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10898 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10900 case FUSED_JCC_PADDING
:
10901 /* Check if this is a fused jcc:
10903 CMP like instruction
10907 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10908 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10909 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10912 /* The BRANCH_PADDING frag is merged with the
10913 FUSED_JCC_PADDING frag. */
10914 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10915 /* CMP like instruction size. */
10916 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10917 frag_wane (pad_fragP
);
10918 /* Skip to branch_fragP. */
10919 next_fragP
= branch_fragP
;
10921 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10923 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10925 next_fragP
->fr_subtype
10926 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10927 next_fragP
->tc_frag_data
.max_bytes
10928 = next_fragP
->tc_frag_data
.max_prefix_length
;
10929 /* This will be updated in the BRANCH_PREFIX scan. */
10930 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10933 frag_wane (next_fragP
);
10938 /* Stop if there is no BRANCH_PREFIX. */
10939 if (!align_branch_prefix_size
)
10942 /* Scan for BRANCH_PREFIX. */
10943 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
10945 if (fragP
->fr_type
!= rs_machine_dependent
10946 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10950 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
10951 COND_JUMP_PREFIX. */
10952 max_prefix_length
= 0;
10953 for (next_fragP
= fragP
;
10954 next_fragP
!= NULL
;
10955 next_fragP
= next_fragP
->fr_next
)
10957 if (next_fragP
->fr_type
== rs_fill
)
10958 /* Skip rs_fill frags. */
10960 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
10961 /* Stop for all other frags. */
10964 /* rs_machine_dependent frags. */
10965 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10968 /* Count BRANCH_PREFIX frags. */
10969 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
10971 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
10972 frag_wane (next_fragP
);
10976 += next_fragP
->tc_frag_data
.max_bytes
;
10978 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10980 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10981 == FUSED_JCC_PADDING
))
10983 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
10984 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
10988 /* Stop for other rs_machine_dependent frags. */
10992 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
10994 /* Skip to the next frag. */
10995 fragP
= next_fragP
;
10999 /* Compute padding size for
11002 CMP like instruction
11004 COND_JUMP/UNCOND_JUMP
11009 COND_JUMP/UNCOND_JUMP
11013 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11015 unsigned int offset
, size
, padding_size
;
11016 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11018 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11020 address
= fragP
->fr_address
;
11021 address
+= fragP
->fr_fix
;
11023 /* CMP like instrunction size. */
11024 size
= fragP
->tc_frag_data
.cmp_size
;
11026 /* The base size of the branch frag. */
11027 size
+= branch_fragP
->fr_fix
;
11029 /* Add opcode and displacement bytes for the rs_machine_dependent
11031 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11032 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11034 /* Check if branch is within boundary and doesn't end at the last
11036 offset
= address
& ((1U << align_branch_power
) - 1);
11037 if ((offset
+ size
) >= (1U << align_branch_power
))
11038 /* Padding needed to avoid crossing boundary. */
11039 padding_size
= (1U << align_branch_power
) - offset
;
11041 /* No padding needed. */
11044 /* The return value may be saved in tc_frag_data.length which is
11046 if (!fits_in_unsigned_byte (padding_size
))
11049 return padding_size
;
11052 /* i386_generic_table_relax_frag()
11054 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11055 grow/shrink padding to align branch frags. Hand others to
11059 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11061 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11062 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11064 long padding_size
= i386_branch_padding_size (fragP
, 0);
11065 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11067 /* When the BRANCH_PREFIX frag is used, the computed address
11068 must match the actual address and there should be no padding. */
11069 if (fragP
->tc_frag_data
.padding_address
11070 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11074 /* Update the padding size. */
11076 fragP
->tc_frag_data
.length
= padding_size
;
11080 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11082 fragS
*padding_fragP
, *next_fragP
;
11083 long padding_size
, left_size
, last_size
;
11085 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11086 if (!padding_fragP
)
11087 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11088 return (fragP
->tc_frag_data
.length
11089 - fragP
->tc_frag_data
.last_length
);
11091 /* Compute the relative address of the padding frag in the very
11092 first time where the BRANCH_PREFIX frag sizes are zero. */
11093 if (!fragP
->tc_frag_data
.padding_address
)
11094 fragP
->tc_frag_data
.padding_address
11095 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11097 /* First update the last length from the previous interation. */
11098 left_size
= fragP
->tc_frag_data
.prefix_length
;
11099 for (next_fragP
= fragP
;
11100 next_fragP
!= padding_fragP
;
11101 next_fragP
= next_fragP
->fr_next
)
11102 if (next_fragP
->fr_type
== rs_machine_dependent
11103 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11108 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11112 if (max
> left_size
)
11117 next_fragP
->tc_frag_data
.last_length
= size
;
11121 next_fragP
->tc_frag_data
.last_length
= 0;
11124 /* Check the padding size for the padding frag. */
11125 padding_size
= i386_branch_padding_size
11126 (padding_fragP
, (fragP
->fr_address
11127 + fragP
->tc_frag_data
.padding_address
));
11129 last_size
= fragP
->tc_frag_data
.prefix_length
;
11130 /* Check if there is change from the last interation. */
11131 if (padding_size
== last_size
)
11133 /* Update the expected address of the padding frag. */
11134 padding_fragP
->tc_frag_data
.padding_address
11135 = (fragP
->fr_address
+ padding_size
11136 + fragP
->tc_frag_data
.padding_address
);
11140 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11142 /* No padding if there is no sufficient room. Clear the
11143 expected address of the padding frag. */
11144 padding_fragP
->tc_frag_data
.padding_address
= 0;
11148 /* Store the expected address of the padding frag. */
11149 padding_fragP
->tc_frag_data
.padding_address
11150 = (fragP
->fr_address
+ padding_size
11151 + fragP
->tc_frag_data
.padding_address
);
11153 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11155 /* Update the length for the current interation. */
11156 left_size
= padding_size
;
11157 for (next_fragP
= fragP
;
11158 next_fragP
!= padding_fragP
;
11159 next_fragP
= next_fragP
->fr_next
)
11160 if (next_fragP
->fr_type
== rs_machine_dependent
11161 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11166 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11170 if (max
> left_size
)
11175 next_fragP
->tc_frag_data
.length
= size
;
11179 next_fragP
->tc_frag_data
.length
= 0;
11182 return (fragP
->tc_frag_data
.length
11183 - fragP
->tc_frag_data
.last_length
);
11185 return relax_frag (segment
, fragP
, stretch
);
11188 /* md_estimate_size_before_relax()
11190 Called just before relax() for rs_machine_dependent frags. The x86
11191 assembler uses these frags to handle variable size jump
11194 Any symbol that is now undefined will not become defined.
11195 Return the correct fr_subtype in the frag.
11196 Return the initial "guess for variable size of frag" to caller.
11197 The guess is actually the growth beyond the fixed part. Whatever
11198 we do to grow the fixed or variable part contributes to our
11202 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11204 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11205 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11206 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11208 i386_classify_machine_dependent_frag (fragP
);
11209 return fragP
->tc_frag_data
.length
;
11212 /* We've already got fragP->fr_subtype right; all we have to do is
11213 check for un-relaxable symbols. On an ELF system, we can't relax
11214 an externally visible symbol, because it may be overridden by a
11216 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11219 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11222 #if defined (OBJ_COFF) && defined (TE_PE)
11223 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11224 && S_IS_WEAK (fragP
->fr_symbol
))
11228 /* Symbol is undefined in this segment, or we need to keep a
11229 reloc so that weak symbols can be overridden. */
11230 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11231 enum bfd_reloc_code_real reloc_type
;
11232 unsigned char *opcode
;
11235 if (fragP
->fr_var
!= NO_RELOC
)
11236 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11237 else if (size
== 2)
11238 reloc_type
= BFD_RELOC_16_PCREL
;
11239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11240 else if (need_plt32_p (fragP
->fr_symbol
))
11241 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11244 reloc_type
= BFD_RELOC_32_PCREL
;
11246 old_fr_fix
= fragP
->fr_fix
;
11247 opcode
= (unsigned char *) fragP
->fr_opcode
;
11249 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11252 /* Make jmp (0xeb) a (d)word displacement jump. */
11254 fragP
->fr_fix
+= size
;
11255 fix_new (fragP
, old_fr_fix
, size
,
11257 fragP
->fr_offset
, 1,
11263 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11265 /* Negate the condition, and branch past an
11266 unconditional jump. */
11269 /* Insert an unconditional jump. */
11271 /* We added two extra opcode bytes, and have a two byte
11273 fragP
->fr_fix
+= 2 + 2;
11274 fix_new (fragP
, old_fr_fix
+ 2, 2,
11276 fragP
->fr_offset
, 1,
11280 /* Fall through. */
11283 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11287 fragP
->fr_fix
+= 1;
11288 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11290 fragP
->fr_offset
, 1,
11291 BFD_RELOC_8_PCREL
);
11292 fixP
->fx_signed
= 1;
11296 /* This changes the byte-displacement jump 0x7N
11297 to the (d)word-displacement jump 0x0f,0x8N. */
11298 opcode
[1] = opcode
[0] + 0x10;
11299 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11300 /* We've added an opcode byte. */
11301 fragP
->fr_fix
+= 1 + size
;
11302 fix_new (fragP
, old_fr_fix
+ 1, size
,
11304 fragP
->fr_offset
, 1,
11309 BAD_CASE (fragP
->fr_subtype
);
11313 return fragP
->fr_fix
- old_fr_fix
;
11316 /* Guess size depending on current relax state. Initially the relax
11317 state will correspond to a short jump and we return 1, because
11318 the variable part of the frag (the branch offset) is one byte
11319 long. However, we can relax a section more than once and in that
11320 case we must either set fr_subtype back to the unrelaxed state,
11321 or return the value for the appropriate branch. */
11322 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11325 /* Called after relax() is finished.
11327 In: Address of frag.
11328 fr_type == rs_machine_dependent.
11329 fr_subtype is what the address relaxed to.
11331 Out: Any fixSs and constants are set up.
11332 Caller will turn frag into a ".space 0". */
11335 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11338 unsigned char *opcode
;
11339 unsigned char *where_to_put_displacement
= NULL
;
11340 offsetT target_address
;
11341 offsetT opcode_address
;
11342 unsigned int extension
= 0;
11343 offsetT displacement_from_opcode_start
;
11345 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11346 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11347 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11349 /* Generate nop padding. */
11350 unsigned int size
= fragP
->tc_frag_data
.length
;
11353 if (size
> fragP
->tc_frag_data
.max_bytes
)
11359 const char *branch
= "branch";
11360 const char *prefix
= "";
11361 fragS
*padding_fragP
;
11362 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11365 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11366 switch (fragP
->tc_frag_data
.default_prefix
)
11371 case CS_PREFIX_OPCODE
:
11374 case DS_PREFIX_OPCODE
:
11377 case ES_PREFIX_OPCODE
:
11380 case FS_PREFIX_OPCODE
:
11383 case GS_PREFIX_OPCODE
:
11386 case SS_PREFIX_OPCODE
:
11391 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11392 "%s within %d-byte boundary\n");
11394 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11395 "align %s within %d-byte boundary\n");
11399 padding_fragP
= fragP
;
11400 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11401 "%s within %d-byte boundary\n");
11405 switch (padding_fragP
->tc_frag_data
.branch_type
)
11407 case align_branch_jcc
:
11410 case align_branch_fused
:
11411 branch
= "fused jcc";
11413 case align_branch_jmp
:
11416 case align_branch_call
:
11419 case align_branch_indirect
:
11420 branch
= "indiret branch";
11422 case align_branch_ret
:
11429 fprintf (stdout
, msg
,
11430 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11431 (long long) fragP
->fr_address
, branch
,
11432 1 << align_branch_power
);
11434 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11435 memset (fragP
->fr_opcode
,
11436 fragP
->tc_frag_data
.default_prefix
, size
);
11438 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11440 fragP
->fr_fix
+= size
;
11445 opcode
= (unsigned char *) fragP
->fr_opcode
;
11447 /* Address we want to reach in file space. */
11448 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11450 /* Address opcode resides at in file space. */
11451 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11453 /* Displacement from opcode start to fill into instruction. */
11454 displacement_from_opcode_start
= target_address
- opcode_address
;
11456 if ((fragP
->fr_subtype
& BIG
) == 0)
11458 /* Don't have to change opcode. */
11459 extension
= 1; /* 1 opcode + 1 displacement */
11460 where_to_put_displacement
= &opcode
[1];
11464 if (no_cond_jump_promotion
11465 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11466 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11467 _("long jump required"));
11469 switch (fragP
->fr_subtype
)
11471 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11472 extension
= 4; /* 1 opcode + 4 displacement */
11474 where_to_put_displacement
= &opcode
[1];
11477 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11478 extension
= 2; /* 1 opcode + 2 displacement */
11480 where_to_put_displacement
= &opcode
[1];
11483 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11484 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11485 extension
= 5; /* 2 opcode + 4 displacement */
11486 opcode
[1] = opcode
[0] + 0x10;
11487 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11488 where_to_put_displacement
= &opcode
[2];
11491 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11492 extension
= 3; /* 2 opcode + 2 displacement */
11493 opcode
[1] = opcode
[0] + 0x10;
11494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11495 where_to_put_displacement
= &opcode
[2];
11498 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11503 where_to_put_displacement
= &opcode
[3];
11507 BAD_CASE (fragP
->fr_subtype
);
11512 /* If size if less then four we are sure that the operand fits,
11513 but if it's 4, then it could be that the displacement is larger
11515 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11517 && ((addressT
) (displacement_from_opcode_start
- extension
11518 + ((addressT
) 1 << 31))
11519 > (((addressT
) 2 << 31) - 1)))
11521 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11522 _("jump target out of range"));
11523 /* Make us emit 0. */
11524 displacement_from_opcode_start
= extension
;
11526 /* Now put displacement after opcode. */
11527 md_number_to_chars ((char *) where_to_put_displacement
,
11528 (valueT
) (displacement_from_opcode_start
- extension
),
11529 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11530 fragP
->fr_fix
+= extension
;
11533 /* Apply a fixup (fixP) to segment data, once it has been determined
11534 by our caller that we have all the info we need to fix it up.
11536 Parameter valP is the pointer to the value of the bits.
11538 On the 386, immediates, displacements, and data pointers are all in
11539 the same (little-endian) format, so we don't need to care about which
11540 we are handling. */
11543 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11545 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11546 valueT value
= *valP
;
11548 #if !defined (TE_Mach)
11549 if (fixP
->fx_pcrel
)
11551 switch (fixP
->fx_r_type
)
11557 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11560 case BFD_RELOC_X86_64_32S
:
11561 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11564 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11567 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11572 if (fixP
->fx_addsy
!= NULL
11573 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11574 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11575 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11576 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11577 && !use_rela_relocations
)
11579 /* This is a hack. There should be a better way to handle this.
11580 This covers for the fact that bfd_install_relocation will
11581 subtract the current location (for partial_inplace, PC relative
11582 relocations); see more below. */
11586 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11589 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11594 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11596 if ((sym_seg
== seg
11597 || (symbol_section_p (fixP
->fx_addsy
)
11598 && sym_seg
!= absolute_section
))
11599 && !generic_force_reloc (fixP
))
11601 /* Yes, we add the values in twice. This is because
11602 bfd_install_relocation subtracts them out again. I think
11603 bfd_install_relocation is broken, but I don't dare change
11605 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11609 #if defined (OBJ_COFF) && defined (TE_PE)
11610 /* For some reason, the PE format does not store a
11611 section address offset for a PC relative symbol. */
11612 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11613 || S_IS_WEAK (fixP
->fx_addsy
))
11614 value
+= md_pcrel_from (fixP
);
11617 #if defined (OBJ_COFF) && defined (TE_PE)
11618 if (fixP
->fx_addsy
!= NULL
11619 && S_IS_WEAK (fixP
->fx_addsy
)
11620 /* PR 16858: Do not modify weak function references. */
11621 && ! fixP
->fx_pcrel
)
11623 #if !defined (TE_PEP)
11624 /* For x86 PE weak function symbols are neither PC-relative
11625 nor do they set S_IS_FUNCTION. So the only reliable way
11626 to detect them is to check the flags of their containing
11628 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11629 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11633 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11637 /* Fix a few things - the dynamic linker expects certain values here,
11638 and we must not disappoint it. */
11639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11640 if (IS_ELF
&& fixP
->fx_addsy
)
11641 switch (fixP
->fx_r_type
)
11643 case BFD_RELOC_386_PLT32
:
11644 case BFD_RELOC_X86_64_PLT32
:
11645 /* Make the jump instruction point to the address of the operand.
11646 At runtime we merely add the offset to the actual PLT entry.
11647 NB: Subtract the offset size only for jump instructions. */
11648 if (fixP
->fx_pcrel
)
11652 case BFD_RELOC_386_TLS_GD
:
11653 case BFD_RELOC_386_TLS_LDM
:
11654 case BFD_RELOC_386_TLS_IE_32
:
11655 case BFD_RELOC_386_TLS_IE
:
11656 case BFD_RELOC_386_TLS_GOTIE
:
11657 case BFD_RELOC_386_TLS_GOTDESC
:
11658 case BFD_RELOC_X86_64_TLSGD
:
11659 case BFD_RELOC_X86_64_TLSLD
:
11660 case BFD_RELOC_X86_64_GOTTPOFF
:
11661 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11662 value
= 0; /* Fully resolved at runtime. No addend. */
11664 case BFD_RELOC_386_TLS_LE
:
11665 case BFD_RELOC_386_TLS_LDO_32
:
11666 case BFD_RELOC_386_TLS_LE_32
:
11667 case BFD_RELOC_X86_64_DTPOFF32
:
11668 case BFD_RELOC_X86_64_DTPOFF64
:
11669 case BFD_RELOC_X86_64_TPOFF32
:
11670 case BFD_RELOC_X86_64_TPOFF64
:
11671 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11674 case BFD_RELOC_386_TLS_DESC_CALL
:
11675 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11676 value
= 0; /* Fully resolved at runtime. No addend. */
11677 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11681 case BFD_RELOC_VTABLE_INHERIT
:
11682 case BFD_RELOC_VTABLE_ENTRY
:
11689 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11691 #endif /* !defined (TE_Mach) */
11693 /* Are we finished with this relocation now? */
11694 if (fixP
->fx_addsy
== NULL
)
11696 #if defined (OBJ_COFF) && defined (TE_PE)
11697 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11700 /* Remember value for tc_gen_reloc. */
11701 fixP
->fx_addnumber
= value
;
11702 /* Clear out the frag for now. */
11706 else if (use_rela_relocations
)
11708 fixP
->fx_no_overflow
= 1;
11709 /* Remember value for tc_gen_reloc. */
11710 fixP
->fx_addnumber
= value
;
11714 md_number_to_chars (p
, value
, fixP
->fx_size
);
11718 md_atof (int type
, char *litP
, int *sizeP
)
11720 /* This outputs the LITTLENUMs in REVERSE order;
11721 in accord with the bigendian 386. */
11722 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11725 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11728 output_invalid (int c
)
11731 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11734 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11735 "(0x%x)", (unsigned char) c
);
11736 return output_invalid_buf
;
11739 /* REG_STRING starts *before* REGISTER_PREFIX. */
11741 static const reg_entry
*
11742 parse_real_register (char *reg_string
, char **end_op
)
11744 char *s
= reg_string
;
11746 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11747 const reg_entry
*r
;
11749 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11750 if (*s
== REGISTER_PREFIX
)
11753 if (is_space_char (*s
))
11756 p
= reg_name_given
;
11757 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11759 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11760 return (const reg_entry
*) NULL
;
11764 /* For naked regs, make sure that we are not dealing with an identifier.
11765 This prevents confusing an identifier like `eax_var' with register
11767 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11768 return (const reg_entry
*) NULL
;
11772 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11774 /* Handle floating point regs, allowing spaces in the (i) part. */
11775 if (r
== i386_regtab
/* %st is first entry of table */)
11777 if (!cpu_arch_flags
.bitfield
.cpu8087
11778 && !cpu_arch_flags
.bitfield
.cpu287
11779 && !cpu_arch_flags
.bitfield
.cpu387
)
11780 return (const reg_entry
*) NULL
;
11782 if (is_space_char (*s
))
11787 if (is_space_char (*s
))
11789 if (*s
>= '0' && *s
<= '7')
11791 int fpr
= *s
- '0';
11793 if (is_space_char (*s
))
11798 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11803 /* We have "%st(" then garbage. */
11804 return (const reg_entry
*) NULL
;
11808 if (r
== NULL
|| allow_pseudo_reg
)
11811 if (operand_type_all_zero (&r
->reg_type
))
11812 return (const reg_entry
*) NULL
;
11814 if ((r
->reg_type
.bitfield
.dword
11815 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11816 || r
->reg_type
.bitfield
.class == RegCR
11817 || r
->reg_type
.bitfield
.class == RegDR
11818 || r
->reg_type
.bitfield
.class == RegTR
)
11819 && !cpu_arch_flags
.bitfield
.cpui386
)
11820 return (const reg_entry
*) NULL
;
11822 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11823 return (const reg_entry
*) NULL
;
11825 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11827 if (r
->reg_type
.bitfield
.zmmword
11828 || r
->reg_type
.bitfield
.class == RegMask
)
11829 return (const reg_entry
*) NULL
;
11831 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11833 if (r
->reg_type
.bitfield
.ymmword
)
11834 return (const reg_entry
*) NULL
;
11836 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11837 return (const reg_entry
*) NULL
;
11841 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11842 return (const reg_entry
*) NULL
;
11844 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11845 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11846 return (const reg_entry
*) NULL
;
11848 /* Upper 16 vector registers are only available with VREX in 64bit
11849 mode, and require EVEX encoding. */
11850 if (r
->reg_flags
& RegVRex
)
11852 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11853 || flag_code
!= CODE_64BIT
)
11854 return (const reg_entry
*) NULL
;
11856 i
.vec_encoding
= vex_encoding_evex
;
11859 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11860 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11861 && flag_code
!= CODE_64BIT
)
11862 return (const reg_entry
*) NULL
;
11864 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11866 return (const reg_entry
*) NULL
;
11871 /* REG_STRING starts *before* REGISTER_PREFIX. */
11873 static const reg_entry
*
11874 parse_register (char *reg_string
, char **end_op
)
11876 const reg_entry
*r
;
11878 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11879 r
= parse_real_register (reg_string
, end_op
);
11884 char *save
= input_line_pointer
;
11888 input_line_pointer
= reg_string
;
11889 c
= get_symbol_name (®_string
);
11890 symbolP
= symbol_find (reg_string
);
11891 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11893 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11895 know (e
->X_op
== O_register
);
11896 know (e
->X_add_number
>= 0
11897 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11898 r
= i386_regtab
+ e
->X_add_number
;
11899 if ((r
->reg_flags
& RegVRex
))
11900 i
.vec_encoding
= vex_encoding_evex
;
11901 *end_op
= input_line_pointer
;
11903 *input_line_pointer
= c
;
11904 input_line_pointer
= save
;
11910 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11912 const reg_entry
*r
;
11913 char *end
= input_line_pointer
;
11916 r
= parse_register (name
, &input_line_pointer
);
11917 if (r
&& end
<= input_line_pointer
)
11919 *nextcharP
= *input_line_pointer
;
11920 *input_line_pointer
= 0;
11921 e
->X_op
= O_register
;
11922 e
->X_add_number
= r
- i386_regtab
;
11925 input_line_pointer
= end
;
11927 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11931 md_operand (expressionS
*e
)
11934 const reg_entry
*r
;
11936 switch (*input_line_pointer
)
11938 case REGISTER_PREFIX
:
11939 r
= parse_real_register (input_line_pointer
, &end
);
11942 e
->X_op
= O_register
;
11943 e
->X_add_number
= r
- i386_regtab
;
11944 input_line_pointer
= end
;
11949 gas_assert (intel_syntax
);
11950 end
= input_line_pointer
++;
11952 if (*input_line_pointer
== ']')
11954 ++input_line_pointer
;
11955 e
->X_op_symbol
= make_expr_symbol (e
);
11956 e
->X_add_symbol
= NULL
;
11957 e
->X_add_number
= 0;
11962 e
->X_op
= O_absent
;
11963 input_line_pointer
= end
;
11970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11971 const char *md_shortopts
= "kVQ:sqnO::";
11973 const char *md_shortopts
= "qnO::";
11976 #define OPTION_32 (OPTION_MD_BASE + 0)
11977 #define OPTION_64 (OPTION_MD_BASE + 1)
11978 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11979 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11980 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11981 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11982 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11983 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11984 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11985 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11986 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11987 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11988 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11989 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11990 #define OPTION_X32 (OPTION_MD_BASE + 14)
11991 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11992 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11993 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11994 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11995 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11996 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11997 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11998 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11999 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12000 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12001 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12002 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12003 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12004 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12005 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12006 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12008 struct option md_longopts
[] =
12010 {"32", no_argument
, NULL
, OPTION_32
},
12011 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12012 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12013 {"64", no_argument
, NULL
, OPTION_64
},
12015 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12016 {"x32", no_argument
, NULL
, OPTION_X32
},
12017 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12018 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12020 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12021 {"march", required_argument
, NULL
, OPTION_MARCH
},
12022 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12023 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12024 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12025 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12026 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12027 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12028 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12029 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12030 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12031 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12032 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12033 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12034 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12035 # if defined (TE_PE) || defined (TE_PEP)
12036 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12038 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12039 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12040 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12041 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12042 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12043 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12044 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12045 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12046 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12047 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12048 {NULL
, no_argument
, NULL
, 0}
12050 size_t md_longopts_size
= sizeof (md_longopts
);
12053 md_parse_option (int c
, const char *arg
)
12056 char *arch
, *next
, *saved
, *type
;
12061 optimize_align_code
= 0;
12065 quiet_warnings
= 1;
12068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12069 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12070 should be emitted or not. FIXME: Not implemented. */
12072 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12076 /* -V: SVR4 argument to print version ID. */
12078 print_version_id ();
12081 /* -k: Ignore for FreeBSD compatibility. */
12086 /* -s: On i386 Solaris, this tells the native assembler to use
12087 .stab instead of .stab.excl. We always use .stab anyhow. */
12090 case OPTION_MSHARED
:
12094 case OPTION_X86_USED_NOTE
:
12095 if (strcasecmp (arg
, "yes") == 0)
12097 else if (strcasecmp (arg
, "no") == 0)
12100 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12105 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12106 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12109 const char **list
, **l
;
12111 list
= bfd_target_list ();
12112 for (l
= list
; *l
!= NULL
; l
++)
12113 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12114 || strcmp (*l
, "coff-x86-64") == 0
12115 || strcmp (*l
, "pe-x86-64") == 0
12116 || strcmp (*l
, "pei-x86-64") == 0
12117 || strcmp (*l
, "mach-o-x86-64") == 0)
12119 default_arch
= "x86_64";
12123 as_fatal (_("no compiled in support for x86_64"));
12129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12133 const char **list
, **l
;
12135 list
= bfd_target_list ();
12136 for (l
= list
; *l
!= NULL
; l
++)
12137 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12139 default_arch
= "x86_64:32";
12143 as_fatal (_("no compiled in support for 32bit x86_64"));
12147 as_fatal (_("32bit x86_64 is only supported for ELF"));
12152 default_arch
= "i386";
12155 case OPTION_DIVIDE
:
12156 #ifdef SVR4_COMMENT_CHARS
12161 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12163 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12167 i386_comment_chars
= n
;
12173 saved
= xstrdup (arg
);
12175 /* Allow -march=+nosse. */
12181 as_fatal (_("invalid -march= option: `%s'"), arg
);
12182 next
= strchr (arch
, '+');
12185 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12187 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12190 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12193 cpu_arch_name
= cpu_arch
[j
].name
;
12194 cpu_sub_arch_name
= NULL
;
12195 cpu_arch_flags
= cpu_arch
[j
].flags
;
12196 cpu_arch_isa
= cpu_arch
[j
].type
;
12197 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12198 if (!cpu_arch_tune_set
)
12200 cpu_arch_tune
= cpu_arch_isa
;
12201 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12205 else if (*cpu_arch
[j
].name
== '.'
12206 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12208 /* ISA extension. */
12209 i386_cpu_flags flags
;
12211 flags
= cpu_flags_or (cpu_arch_flags
,
12212 cpu_arch
[j
].flags
);
12214 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12216 if (cpu_sub_arch_name
)
12218 char *name
= cpu_sub_arch_name
;
12219 cpu_sub_arch_name
= concat (name
,
12221 (const char *) NULL
);
12225 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12226 cpu_arch_flags
= flags
;
12227 cpu_arch_isa_flags
= flags
;
12231 = cpu_flags_or (cpu_arch_isa_flags
,
12232 cpu_arch
[j
].flags
);
12237 if (j
>= ARRAY_SIZE (cpu_arch
))
12239 /* Disable an ISA extension. */
12240 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12241 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12243 i386_cpu_flags flags
;
12245 flags
= cpu_flags_and_not (cpu_arch_flags
,
12246 cpu_noarch
[j
].flags
);
12247 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12249 if (cpu_sub_arch_name
)
12251 char *name
= cpu_sub_arch_name
;
12252 cpu_sub_arch_name
= concat (arch
,
12253 (const char *) NULL
);
12257 cpu_sub_arch_name
= xstrdup (arch
);
12258 cpu_arch_flags
= flags
;
12259 cpu_arch_isa_flags
= flags
;
12264 if (j
>= ARRAY_SIZE (cpu_noarch
))
12265 j
= ARRAY_SIZE (cpu_arch
);
12268 if (j
>= ARRAY_SIZE (cpu_arch
))
12269 as_fatal (_("invalid -march= option: `%s'"), arg
);
12273 while (next
!= NULL
);
12279 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12280 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12282 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12284 cpu_arch_tune_set
= 1;
12285 cpu_arch_tune
= cpu_arch
[j
].type
;
12286 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12290 if (j
>= ARRAY_SIZE (cpu_arch
))
12291 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12294 case OPTION_MMNEMONIC
:
12295 if (strcasecmp (arg
, "att") == 0)
12296 intel_mnemonic
= 0;
12297 else if (strcasecmp (arg
, "intel") == 0)
12298 intel_mnemonic
= 1;
12300 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12303 case OPTION_MSYNTAX
:
12304 if (strcasecmp (arg
, "att") == 0)
12306 else if (strcasecmp (arg
, "intel") == 0)
12309 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12312 case OPTION_MINDEX_REG
:
12313 allow_index_reg
= 1;
12316 case OPTION_MNAKED_REG
:
12317 allow_naked_reg
= 1;
12320 case OPTION_MSSE2AVX
:
12324 case OPTION_MSSE_CHECK
:
12325 if (strcasecmp (arg
, "error") == 0)
12326 sse_check
= check_error
;
12327 else if (strcasecmp (arg
, "warning") == 0)
12328 sse_check
= check_warning
;
12329 else if (strcasecmp (arg
, "none") == 0)
12330 sse_check
= check_none
;
12332 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12335 case OPTION_MOPERAND_CHECK
:
12336 if (strcasecmp (arg
, "error") == 0)
12337 operand_check
= check_error
;
12338 else if (strcasecmp (arg
, "warning") == 0)
12339 operand_check
= check_warning
;
12340 else if (strcasecmp (arg
, "none") == 0)
12341 operand_check
= check_none
;
12343 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12346 case OPTION_MAVXSCALAR
:
12347 if (strcasecmp (arg
, "128") == 0)
12348 avxscalar
= vex128
;
12349 else if (strcasecmp (arg
, "256") == 0)
12350 avxscalar
= vex256
;
12352 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12355 case OPTION_MVEXWIG
:
12356 if (strcmp (arg
, "0") == 0)
12358 else if (strcmp (arg
, "1") == 0)
12361 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12364 case OPTION_MADD_BND_PREFIX
:
12365 add_bnd_prefix
= 1;
12368 case OPTION_MEVEXLIG
:
12369 if (strcmp (arg
, "128") == 0)
12370 evexlig
= evexl128
;
12371 else if (strcmp (arg
, "256") == 0)
12372 evexlig
= evexl256
;
12373 else if (strcmp (arg
, "512") == 0)
12374 evexlig
= evexl512
;
12376 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12379 case OPTION_MEVEXRCIG
:
12380 if (strcmp (arg
, "rne") == 0)
12382 else if (strcmp (arg
, "rd") == 0)
12384 else if (strcmp (arg
, "ru") == 0)
12386 else if (strcmp (arg
, "rz") == 0)
12389 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12392 case OPTION_MEVEXWIG
:
12393 if (strcmp (arg
, "0") == 0)
12395 else if (strcmp (arg
, "1") == 0)
12398 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12401 # if defined (TE_PE) || defined (TE_PEP)
12402 case OPTION_MBIG_OBJ
:
12407 case OPTION_MOMIT_LOCK_PREFIX
:
12408 if (strcasecmp (arg
, "yes") == 0)
12409 omit_lock_prefix
= 1;
12410 else if (strcasecmp (arg
, "no") == 0)
12411 omit_lock_prefix
= 0;
12413 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12416 case OPTION_MFENCE_AS_LOCK_ADD
:
12417 if (strcasecmp (arg
, "yes") == 0)
12419 else if (strcasecmp (arg
, "no") == 0)
12422 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12425 case OPTION_MRELAX_RELOCATIONS
:
12426 if (strcasecmp (arg
, "yes") == 0)
12427 generate_relax_relocations
= 1;
12428 else if (strcasecmp (arg
, "no") == 0)
12429 generate_relax_relocations
= 0;
12431 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12434 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12437 long int align
= strtoul (arg
, &end
, 0);
12442 align_branch_power
= 0;
12445 else if (align
>= 16)
12448 for (align_power
= 0;
12450 align
>>= 1, align_power
++)
12452 /* Limit alignment power to 31. */
12453 if (align
== 1 && align_power
< 32)
12455 align_branch_power
= align_power
;
12460 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12464 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12467 int align
= strtoul (arg
, &end
, 0);
12468 /* Some processors only support 5 prefixes. */
12469 if (*end
== '\0' && align
>= 0 && align
< 6)
12471 align_branch_prefix_size
= align
;
12474 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12479 case OPTION_MALIGN_BRANCH
:
12481 saved
= xstrdup (arg
);
12485 next
= strchr (type
, '+');
12488 if (strcasecmp (type
, "jcc") == 0)
12489 align_branch
|= align_branch_jcc_bit
;
12490 else if (strcasecmp (type
, "fused") == 0)
12491 align_branch
|= align_branch_fused_bit
;
12492 else if (strcasecmp (type
, "jmp") == 0)
12493 align_branch
|= align_branch_jmp_bit
;
12494 else if (strcasecmp (type
, "call") == 0)
12495 align_branch
|= align_branch_call_bit
;
12496 else if (strcasecmp (type
, "ret") == 0)
12497 align_branch
|= align_branch_ret_bit
;
12498 else if (strcasecmp (type
, "indirect") == 0)
12499 align_branch
|= align_branch_indirect_bit
;
12501 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12504 while (next
!= NULL
);
12508 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12509 align_branch_power
= 5;
12510 align_branch_prefix_size
= 5;
12511 align_branch
= (align_branch_jcc_bit
12512 | align_branch_fused_bit
12513 | align_branch_jmp_bit
);
12516 case OPTION_MAMD64
:
12520 case OPTION_MINTEL64
:
12528 /* Turn off -Os. */
12529 optimize_for_space
= 0;
12531 else if (*arg
== 's')
12533 optimize_for_space
= 1;
12534 /* Turn on all encoding optimizations. */
12535 optimize
= INT_MAX
;
12539 optimize
= atoi (arg
);
12540 /* Turn off -Os. */
12541 optimize_for_space
= 0;
12551 #define MESSAGE_TEMPLATE \
12555 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12556 int *left_p
, const char *name
, int len
)
12558 int size
= sizeof (MESSAGE_TEMPLATE
);
12559 int left
= *left_p
;
12561 /* Reserve 2 spaces for ", " or ",\0" */
12564 /* Check if there is any room. */
12572 p
= mempcpy (p
, name
, len
);
12576 /* Output the current message now and start a new one. */
12579 fprintf (stream
, "%s\n", message
);
12581 left
= size
- (start
- message
) - len
- 2;
12583 gas_assert (left
>= 0);
12585 p
= mempcpy (p
, name
, len
);
12593 show_arch (FILE *stream
, int ext
, int check
)
12595 static char message
[] = MESSAGE_TEMPLATE
;
12596 char *start
= message
+ 27;
12598 int size
= sizeof (MESSAGE_TEMPLATE
);
12605 left
= size
- (start
- message
);
12606 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12608 /* Should it be skipped? */
12609 if (cpu_arch
[j
].skip
)
12612 name
= cpu_arch
[j
].name
;
12613 len
= cpu_arch
[j
].len
;
12616 /* It is an extension. Skip if we aren't asked to show it. */
12627 /* It is an processor. Skip if we show only extension. */
12630 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12632 /* It is an impossible processor - skip. */
12636 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12639 /* Display disabled extensions. */
12641 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12643 name
= cpu_noarch
[j
].name
;
12644 len
= cpu_noarch
[j
].len
;
12645 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12650 fprintf (stream
, "%s\n", message
);
12654 md_show_usage (FILE *stream
)
12656 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12657 fprintf (stream
, _("\
12658 -Qy, -Qn ignored\n\
12659 -V print assembler version number\n\
12662 fprintf (stream
, _("\
12663 -n Do not optimize code alignment\n\
12664 -q quieten some warnings\n"));
12665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12666 fprintf (stream
, _("\
12669 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12670 || defined (TE_PE) || defined (TE_PEP))
12671 fprintf (stream
, _("\
12672 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12674 #ifdef SVR4_COMMENT_CHARS
12675 fprintf (stream
, _("\
12676 --divide do not treat `/' as a comment character\n"));
12678 fprintf (stream
, _("\
12679 --divide ignored\n"));
12681 fprintf (stream
, _("\
12682 -march=CPU[,+EXTENSION...]\n\
12683 generate code for CPU and EXTENSION, CPU is one of:\n"));
12684 show_arch (stream
, 0, 1);
12685 fprintf (stream
, _("\
12686 EXTENSION is combination of:\n"));
12687 show_arch (stream
, 1, 0);
12688 fprintf (stream
, _("\
12689 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12690 show_arch (stream
, 0, 0);
12691 fprintf (stream
, _("\
12692 -msse2avx encode SSE instructions with VEX prefix\n"));
12693 fprintf (stream
, _("\
12694 -msse-check=[none|error|warning] (default: warning)\n\
12695 check SSE instructions\n"));
12696 fprintf (stream
, _("\
12697 -moperand-check=[none|error|warning] (default: warning)\n\
12698 check operand combinations for validity\n"));
12699 fprintf (stream
, _("\
12700 -mavxscalar=[128|256] (default: 128)\n\
12701 encode scalar AVX instructions with specific vector\n\
12703 fprintf (stream
, _("\
12704 -mvexwig=[0|1] (default: 0)\n\
12705 encode VEX instructions with specific VEX.W value\n\
12706 for VEX.W bit ignored instructions\n"));
12707 fprintf (stream
, _("\
12708 -mevexlig=[128|256|512] (default: 128)\n\
12709 encode scalar EVEX instructions with specific vector\n\
12711 fprintf (stream
, _("\
12712 -mevexwig=[0|1] (default: 0)\n\
12713 encode EVEX instructions with specific EVEX.W value\n\
12714 for EVEX.W bit ignored instructions\n"));
12715 fprintf (stream
, _("\
12716 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12717 encode EVEX instructions with specific EVEX.RC value\n\
12718 for SAE-only ignored instructions\n"));
12719 fprintf (stream
, _("\
12720 -mmnemonic=[att|intel] "));
12721 if (SYSV386_COMPAT
)
12722 fprintf (stream
, _("(default: att)\n"));
12724 fprintf (stream
, _("(default: intel)\n"));
12725 fprintf (stream
, _("\
12726 use AT&T/Intel mnemonic\n"));
12727 fprintf (stream
, _("\
12728 -msyntax=[att|intel] (default: att)\n\
12729 use AT&T/Intel syntax\n"));
12730 fprintf (stream
, _("\
12731 -mindex-reg support pseudo index registers\n"));
12732 fprintf (stream
, _("\
12733 -mnaked-reg don't require `%%' prefix for registers\n"));
12734 fprintf (stream
, _("\
12735 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12737 fprintf (stream
, _("\
12738 -mshared disable branch optimization for shared code\n"));
12739 fprintf (stream
, _("\
12740 -mx86-used-note=[no|yes] "));
12741 if (DEFAULT_X86_USED_NOTE
)
12742 fprintf (stream
, _("(default: yes)\n"));
12744 fprintf (stream
, _("(default: no)\n"));
12745 fprintf (stream
, _("\
12746 generate x86 used ISA and feature properties\n"));
12748 #if defined (TE_PE) || defined (TE_PEP)
12749 fprintf (stream
, _("\
12750 -mbig-obj generate big object files\n"));
12752 fprintf (stream
, _("\
12753 -momit-lock-prefix=[no|yes] (default: no)\n\
12754 strip all lock prefixes\n"));
12755 fprintf (stream
, _("\
12756 -mfence-as-lock-add=[no|yes] (default: no)\n\
12757 encode lfence, mfence and sfence as\n\
12758 lock addl $0x0, (%%{re}sp)\n"));
12759 fprintf (stream
, _("\
12760 -mrelax-relocations=[no|yes] "));
12761 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12762 fprintf (stream
, _("(default: yes)\n"));
12764 fprintf (stream
, _("(default: no)\n"));
12765 fprintf (stream
, _("\
12766 generate relax relocations\n"));
12767 fprintf (stream
, _("\
12768 -malign-branch-boundary=NUM (default: 0)\n\
12769 align branches within NUM byte boundary\n"));
12770 fprintf (stream
, _("\
12771 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12772 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12774 specify types of branches to align\n"));
12775 fprintf (stream
, _("\
12776 -malign-branch-prefix-size=NUM (default: 5)\n\
12777 align branches with NUM prefixes per instruction\n"));
12778 fprintf (stream
, _("\
12779 -mbranches-within-32B-boundaries\n\
12780 align branches within 32 byte boundary\n"));
12781 fprintf (stream
, _("\
12782 -mamd64 accept only AMD64 ISA [default]\n"));
12783 fprintf (stream
, _("\
12784 -mintel64 accept only Intel64 ISA\n"));
12787 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12788 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12789 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12791 /* Pick the target format to use. */
12794 i386_target_format (void)
12796 if (!strncmp (default_arch
, "x86_64", 6))
12798 update_code_flag (CODE_64BIT
, 1);
12799 if (default_arch
[6] == '\0')
12800 x86_elf_abi
= X86_64_ABI
;
12802 x86_elf_abi
= X86_64_X32_ABI
;
12804 else if (!strcmp (default_arch
, "i386"))
12805 update_code_flag (CODE_32BIT
, 1);
12806 else if (!strcmp (default_arch
, "iamcu"))
12808 update_code_flag (CODE_32BIT
, 1);
12809 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12811 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12812 cpu_arch_name
= "iamcu";
12813 cpu_sub_arch_name
= NULL
;
12814 cpu_arch_flags
= iamcu_flags
;
12815 cpu_arch_isa
= PROCESSOR_IAMCU
;
12816 cpu_arch_isa_flags
= iamcu_flags
;
12817 if (!cpu_arch_tune_set
)
12819 cpu_arch_tune
= cpu_arch_isa
;
12820 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12823 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12824 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12828 as_fatal (_("unknown architecture"));
12830 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12831 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12832 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12833 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12835 switch (OUTPUT_FLAVOR
)
12837 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12838 case bfd_target_aout_flavour
:
12839 return AOUT_TARGET_FORMAT
;
12841 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12842 # if defined (TE_PE) || defined (TE_PEP)
12843 case bfd_target_coff_flavour
:
12844 if (flag_code
== CODE_64BIT
)
12845 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12848 # elif defined (TE_GO32)
12849 case bfd_target_coff_flavour
:
12850 return "coff-go32";
12852 case bfd_target_coff_flavour
:
12853 return "coff-i386";
12856 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12857 case bfd_target_elf_flavour
:
12859 const char *format
;
12861 switch (x86_elf_abi
)
12864 format
= ELF_TARGET_FORMAT
;
12866 tls_get_addr
= "___tls_get_addr";
12870 use_rela_relocations
= 1;
12873 tls_get_addr
= "__tls_get_addr";
12875 format
= ELF_TARGET_FORMAT64
;
12877 case X86_64_X32_ABI
:
12878 use_rela_relocations
= 1;
12881 tls_get_addr
= "__tls_get_addr";
12883 disallow_64bit_reloc
= 1;
12884 format
= ELF_TARGET_FORMAT32
;
12887 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12889 if (x86_elf_abi
!= X86_64_ABI
)
12890 as_fatal (_("Intel L1OM is 64bit only"));
12891 return ELF_TARGET_L1OM_FORMAT
;
12893 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12895 if (x86_elf_abi
!= X86_64_ABI
)
12896 as_fatal (_("Intel K1OM is 64bit only"));
12897 return ELF_TARGET_K1OM_FORMAT
;
12899 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12901 if (x86_elf_abi
!= I386_ABI
)
12902 as_fatal (_("Intel MCU is 32bit only"));
12903 return ELF_TARGET_IAMCU_FORMAT
;
12909 #if defined (OBJ_MACH_O)
12910 case bfd_target_mach_o_flavour
:
12911 if (flag_code
== CODE_64BIT
)
12913 use_rela_relocations
= 1;
12915 return "mach-o-x86-64";
12918 return "mach-o-i386";
12926 #endif /* OBJ_MAYBE_ more than one */
12929 md_undefined_symbol (char *name
)
12931 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12932 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12933 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12934 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12938 if (symbol_find (name
))
12939 as_bad (_("GOT already in symbol table"));
12940 GOT_symbol
= symbol_new (name
, undefined_section
,
12941 (valueT
) 0, &zero_address_frag
);
12948 /* Round up a section size to the appropriate boundary. */
12951 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
12953 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12954 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
12956 /* For a.out, force the section size to be aligned. If we don't do
12957 this, BFD will align it for us, but it will not write out the
12958 final bytes of the section. This may be a bug in BFD, but it is
12959 easier to fix it here since that is how the other a.out targets
12963 align
= bfd_section_alignment (segment
);
12964 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
12971 /* On the i386, PC-relative offsets are relative to the start of the
12972 next instruction. That is, the address of the offset, plus its
12973 size, since the offset is always the last part of the insn. */
12976 md_pcrel_from (fixS
*fixP
)
12978 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12984 s_bss (int ignore ATTRIBUTE_UNUSED
)
12988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12990 obj_elf_section_change_hook ();
12992 temp
= get_absolute_expression ();
12993 subseg_set (bss_section
, (subsegT
) temp
);
12994 demand_empty_rest_of_line ();
12999 /* Remember constant directive. */
13002 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13004 if (last_insn
.kind
!= last_insn_directive
13005 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13007 last_insn
.seg
= now_seg
;
13008 last_insn
.kind
= last_insn_directive
;
13009 last_insn
.name
= "constant directive";
13010 last_insn
.file
= as_where (&last_insn
.line
);
13015 i386_validate_fix (fixS
*fixp
)
13017 if (fixp
->fx_subsy
)
13019 if (fixp
->fx_subsy
== GOT_symbol
)
13021 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13025 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13026 if (fixp
->fx_tcbit2
)
13027 fixp
->fx_r_type
= (fixp
->fx_tcbit
13028 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13029 : BFD_RELOC_X86_64_GOTPCRELX
);
13032 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13037 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13039 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13041 fixp
->fx_subsy
= 0;
13044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13045 else if (!object_64bit
)
13047 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13048 && fixp
->fx_tcbit2
)
13049 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13055 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13058 bfd_reloc_code_real_type code
;
13060 switch (fixp
->fx_r_type
)
13062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13063 case BFD_RELOC_SIZE32
:
13064 case BFD_RELOC_SIZE64
:
13065 if (S_IS_DEFINED (fixp
->fx_addsy
)
13066 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13068 /* Resolve size relocation against local symbol to size of
13069 the symbol plus addend. */
13070 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13071 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13072 && !fits_in_unsigned_long (value
))
13073 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13074 _("symbol size computation overflow"));
13075 fixp
->fx_addsy
= NULL
;
13076 fixp
->fx_subsy
= NULL
;
13077 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13081 /* Fall through. */
13083 case BFD_RELOC_X86_64_PLT32
:
13084 case BFD_RELOC_X86_64_GOT32
:
13085 case BFD_RELOC_X86_64_GOTPCREL
:
13086 case BFD_RELOC_X86_64_GOTPCRELX
:
13087 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13088 case BFD_RELOC_386_PLT32
:
13089 case BFD_RELOC_386_GOT32
:
13090 case BFD_RELOC_386_GOT32X
:
13091 case BFD_RELOC_386_GOTOFF
:
13092 case BFD_RELOC_386_GOTPC
:
13093 case BFD_RELOC_386_TLS_GD
:
13094 case BFD_RELOC_386_TLS_LDM
:
13095 case BFD_RELOC_386_TLS_LDO_32
:
13096 case BFD_RELOC_386_TLS_IE_32
:
13097 case BFD_RELOC_386_TLS_IE
:
13098 case BFD_RELOC_386_TLS_GOTIE
:
13099 case BFD_RELOC_386_TLS_LE_32
:
13100 case BFD_RELOC_386_TLS_LE
:
13101 case BFD_RELOC_386_TLS_GOTDESC
:
13102 case BFD_RELOC_386_TLS_DESC_CALL
:
13103 case BFD_RELOC_X86_64_TLSGD
:
13104 case BFD_RELOC_X86_64_TLSLD
:
13105 case BFD_RELOC_X86_64_DTPOFF32
:
13106 case BFD_RELOC_X86_64_DTPOFF64
:
13107 case BFD_RELOC_X86_64_GOTTPOFF
:
13108 case BFD_RELOC_X86_64_TPOFF32
:
13109 case BFD_RELOC_X86_64_TPOFF64
:
13110 case BFD_RELOC_X86_64_GOTOFF64
:
13111 case BFD_RELOC_X86_64_GOTPC32
:
13112 case BFD_RELOC_X86_64_GOT64
:
13113 case BFD_RELOC_X86_64_GOTPCREL64
:
13114 case BFD_RELOC_X86_64_GOTPC64
:
13115 case BFD_RELOC_X86_64_GOTPLT64
:
13116 case BFD_RELOC_X86_64_PLTOFF64
:
13117 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13118 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13119 case BFD_RELOC_RVA
:
13120 case BFD_RELOC_VTABLE_ENTRY
:
13121 case BFD_RELOC_VTABLE_INHERIT
:
13123 case BFD_RELOC_32_SECREL
:
13125 code
= fixp
->fx_r_type
;
13127 case BFD_RELOC_X86_64_32S
:
13128 if (!fixp
->fx_pcrel
)
13130 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13131 code
= fixp
->fx_r_type
;
13134 /* Fall through. */
13136 if (fixp
->fx_pcrel
)
13138 switch (fixp
->fx_size
)
13141 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13142 _("can not do %d byte pc-relative relocation"),
13144 code
= BFD_RELOC_32_PCREL
;
13146 case 1: code
= BFD_RELOC_8_PCREL
; break;
13147 case 2: code
= BFD_RELOC_16_PCREL
; break;
13148 case 4: code
= BFD_RELOC_32_PCREL
; break;
13150 case 8: code
= BFD_RELOC_64_PCREL
; break;
13156 switch (fixp
->fx_size
)
13159 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13160 _("can not do %d byte relocation"),
13162 code
= BFD_RELOC_32
;
13164 case 1: code
= BFD_RELOC_8
; break;
13165 case 2: code
= BFD_RELOC_16
; break;
13166 case 4: code
= BFD_RELOC_32
; break;
13168 case 8: code
= BFD_RELOC_64
; break;
13175 if ((code
== BFD_RELOC_32
13176 || code
== BFD_RELOC_32_PCREL
13177 || code
== BFD_RELOC_X86_64_32S
)
13179 && fixp
->fx_addsy
== GOT_symbol
)
13182 code
= BFD_RELOC_386_GOTPC
;
13184 code
= BFD_RELOC_X86_64_GOTPC32
;
13186 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13188 && fixp
->fx_addsy
== GOT_symbol
)
13190 code
= BFD_RELOC_X86_64_GOTPC64
;
13193 rel
= XNEW (arelent
);
13194 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13195 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13197 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13199 if (!use_rela_relocations
)
13201 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13202 vtable entry to be used in the relocation's section offset. */
13203 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13204 rel
->address
= fixp
->fx_offset
;
13205 #if defined (OBJ_COFF) && defined (TE_PE)
13206 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13207 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13212 /* Use the rela in 64bit mode. */
13215 if (disallow_64bit_reloc
)
13218 case BFD_RELOC_X86_64_DTPOFF64
:
13219 case BFD_RELOC_X86_64_TPOFF64
:
13220 case BFD_RELOC_64_PCREL
:
13221 case BFD_RELOC_X86_64_GOTOFF64
:
13222 case BFD_RELOC_X86_64_GOT64
:
13223 case BFD_RELOC_X86_64_GOTPCREL64
:
13224 case BFD_RELOC_X86_64_GOTPC64
:
13225 case BFD_RELOC_X86_64_GOTPLT64
:
13226 case BFD_RELOC_X86_64_PLTOFF64
:
13227 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13228 _("cannot represent relocation type %s in x32 mode"),
13229 bfd_get_reloc_code_name (code
));
13235 if (!fixp
->fx_pcrel
)
13236 rel
->addend
= fixp
->fx_offset
;
13240 case BFD_RELOC_X86_64_PLT32
:
13241 case BFD_RELOC_X86_64_GOT32
:
13242 case BFD_RELOC_X86_64_GOTPCREL
:
13243 case BFD_RELOC_X86_64_GOTPCRELX
:
13244 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13245 case BFD_RELOC_X86_64_TLSGD
:
13246 case BFD_RELOC_X86_64_TLSLD
:
13247 case BFD_RELOC_X86_64_GOTTPOFF
:
13248 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13249 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13250 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13253 rel
->addend
= (section
->vma
13255 + fixp
->fx_addnumber
13256 + md_pcrel_from (fixp
));
13261 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13262 if (rel
->howto
== NULL
)
13264 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13265 _("cannot represent relocation type %s"),
13266 bfd_get_reloc_code_name (code
));
13267 /* Set howto to a garbage value so that we can keep going. */
13268 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13269 gas_assert (rel
->howto
!= NULL
);
13275 #include "tc-i386-intel.c"
13278 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13280 int saved_naked_reg
;
13281 char saved_register_dot
;
13283 saved_naked_reg
= allow_naked_reg
;
13284 allow_naked_reg
= 1;
13285 saved_register_dot
= register_chars
['.'];
13286 register_chars
['.'] = '.';
13287 allow_pseudo_reg
= 1;
13288 expression_and_evaluate (exp
);
13289 allow_pseudo_reg
= 0;
13290 register_chars
['.'] = saved_register_dot
;
13291 allow_naked_reg
= saved_naked_reg
;
13293 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13295 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13297 exp
->X_op
= O_constant
;
13298 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13299 .dw2_regnum
[flag_code
>> 1];
13302 exp
->X_op
= O_illegal
;
13307 tc_x86_frame_initial_instructions (void)
13309 static unsigned int sp_regno
[2];
13311 if (!sp_regno
[flag_code
>> 1])
13313 char *saved_input
= input_line_pointer
;
13314 char sp
[][4] = {"esp", "rsp"};
13317 input_line_pointer
= sp
[flag_code
>> 1];
13318 tc_x86_parse_to_dw2regnum (&exp
);
13319 gas_assert (exp
.X_op
== O_constant
);
13320 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13321 input_line_pointer
= saved_input
;
13324 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13325 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13329 x86_dwarf2_addr_size (void)
13331 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13332 if (x86_elf_abi
== X86_64_X32_ABI
)
13335 return bfd_arch_bits_per_address (stdoutput
) / 8;
13339 i386_elf_section_type (const char *str
, size_t len
)
13341 if (flag_code
== CODE_64BIT
13342 && len
== sizeof ("unwind") - 1
13343 && strncmp (str
, "unwind", 6) == 0)
13344 return SHT_X86_64_UNWIND
;
13351 i386_solaris_fix_up_eh_frame (segT sec
)
13353 if (flag_code
== CODE_64BIT
)
13354 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13360 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13364 exp
.X_op
= O_secrel
;
13365 exp
.X_add_symbol
= symbol
;
13366 exp
.X_add_number
= 0;
13367 emit_expr (&exp
, size
);
13371 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13372 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13375 x86_64_section_letter (int letter
, const char **ptr_msg
)
13377 if (flag_code
== CODE_64BIT
)
13380 return SHF_X86_64_LARGE
;
13382 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13385 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13390 x86_64_section_word (char *str
, size_t len
)
13392 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13393 return SHF_X86_64_LARGE
;
13399 handle_large_common (int small ATTRIBUTE_UNUSED
)
13401 if (flag_code
!= CODE_64BIT
)
13403 s_comm_internal (0, elf_common_parse
);
13404 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13408 static segT lbss_section
;
13409 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13410 asection
*saved_bss_section
= bss_section
;
13412 if (lbss_section
== NULL
)
13414 flagword applicable
;
13415 segT seg
= now_seg
;
13416 subsegT subseg
= now_subseg
;
13418 /* The .lbss section is for local .largecomm symbols. */
13419 lbss_section
= subseg_new (".lbss", 0);
13420 applicable
= bfd_applicable_section_flags (stdoutput
);
13421 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13422 seg_info (lbss_section
)->bss
= 1;
13424 subseg_set (seg
, subseg
);
13427 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13428 bss_section
= lbss_section
;
13430 s_comm_internal (0, elf_common_parse
);
13432 elf_com_section_ptr
= saved_com_section_ptr
;
13433 bss_section
= saved_bss_section
;
13436 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */