1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
63 #define INLINE __inline__
69 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
70 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
73 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
75 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
76 static int smallest_imm_type
PARAMS ((offsetT
));
77 static offsetT offset_in_range
PARAMS ((offsetT
, int));
78 static int add_prefix
PARAMS ((unsigned int));
79 static void set_code_flag
PARAMS ((int));
80 static void set_16bit_gcc_code_flag
PARAMS ((int));
81 static void set_intel_syntax
PARAMS ((int));
82 static void set_cpu_arch
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 RELOC_ENUM reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
187 const char extra_symbol_chars
[] = "*%-(@[";
189 const char extra_symbol_chars
[] = "*%-([";
192 #if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
197 /* This array holds the chars that always start a comment. If the
198 pre-processor is disabled, these aren't very useful. */
199 const char comment_chars
[] = "#/";
200 #define PREFIX_SEPARATOR '\\'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "";
213 /* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215 const char comment_chars
[] = "#";
216 #define PREFIX_SEPARATOR '/'
218 const char line_comment_chars
[] = "/";
221 const char line_separator_chars
[] = ";";
223 /* Chars that can be used to separate mant from exp in floating point
225 const char EXP_CHARS
[] = "eE";
227 /* Chars that mean this number is a floating point constant
230 const char FLT_CHARS
[] = "fFdDxX";
232 /* Tables for lexical analysis. */
233 static char mnemonic_chars
[256];
234 static char register_chars
[256];
235 static char operand_chars
[256];
236 static char identifier_chars
[256];
237 static char digit_chars
[256];
239 /* Lexical macros. */
240 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241 #define is_operand_char(x) (operand_chars[(unsigned char) x])
242 #define is_register_char(x) (register_chars[(unsigned char) x])
243 #define is_space_char(x) ((x) == ' ')
244 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245 #define is_digit_char(x) (digit_chars[(unsigned char) x])
247 /* All non-digit non-letter charcters that may occur in an operand. */
248 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
250 /* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
253 assembler instruction). */
254 static char save_stack
[32];
255 static char *save_stack_p
;
256 #define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258 #define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
261 /* The instruction we're assembling. */
264 /* Possible templates for current insn. */
265 static const templates
*current_templates
;
267 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
268 static expressionS disp_expressions
[2], im_expressions
[2];
270 /* Current operand we are working on. */
271 static int this_operand
;
273 /* We support four different modes. FLAG_CODE variable is used to distinguish
280 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
282 static enum flag_code flag_code
;
283 static int use_rela_relocations
= 0;
285 /* The names used to print error messages. */
286 static const char *flag_code_names
[] =
293 /* 1 for intel syntax,
295 static int intel_syntax
= 0;
297 /* 1 if register prefix % not required. */
298 static int allow_naked_reg
= 0;
300 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303 static char stackop_size
= '\0';
305 /* Non-zero to quieten some warnings. */
306 static int quiet_warnings
= 0;
309 static const char *cpu_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316 static unsigned int no_cond_jump_promotion
= 0;
318 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
321 /* Interface to relax_segment.
322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
327 #define UNCOND_JUMP 0
329 #define COND_JUMP86 2
334 #define SMALL16 (SMALL | CODE16)
336 #define BIG16 (BIG | CODE16)
340 #define INLINE __inline__
346 #define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348 #define TYPE_FROM_RELAX_STATE(s) \
350 #define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
353 /* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
361 const relax_typeS md_relax_table
[] =
364 1) most positive reach of this state,
365 2) most negative reach of this state,
366 3) how many bytes this mode will have in the variable part of the frag
367 4) which index into the table to try if we can't fit into this one. */
369 /* UNCOND_JUMP states. */
370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
385 /* word conditionals add 3 bytes to frag:
386 1 extra opcode byte, 2 displacement bytes. */
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
400 static const arch_entry cpu_arch
[] = {
402 {"i186", Cpu086
|Cpu186
},
403 {"i286", Cpu086
|Cpu186
|Cpu286
},
404 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
405 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
406 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
407 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
408 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
409 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
410 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
411 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
412 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
413 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
417 const pseudo_typeS md_pseudo_table
[] =
419 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes
, 0},
422 {"align", s_align_ptwo
, 0},
424 {"arch", set_cpu_arch
, 0},
428 {"ffloat", float_cons
, 'f'},
429 {"dfloat", float_cons
, 'd'},
430 {"tfloat", float_cons
, 'x'},
432 {"noopt", s_ignore
, 0},
433 {"optim", s_ignore
, 0},
434 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
435 {"code16", set_code_flag
, CODE_16BIT
},
436 {"code32", set_code_flag
, CODE_32BIT
},
437 {"code64", set_code_flag
, CODE_64BIT
},
438 {"intel_syntax", set_intel_syntax
, 1},
439 {"att_syntax", set_intel_syntax
, 0},
440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
441 {"loc", dwarf2_directive_loc
, 0},
445 /* For interface with expression (). */
446 extern char *input_line_pointer
;
448 /* Hash table for instruction mnemonic lookup. */
449 static struct hash_control
*op_hash
;
451 /* Hash table for register lookup. */
452 static struct hash_control
*reg_hash
;
455 i386_align_code (fragP
, count
)
459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
462 static const char f32_1
[] =
464 static const char f32_2
[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3
[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4
[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5
[] =
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6
[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7
[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8
[] =
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9
[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10
[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11
[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12
[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13
[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14
[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15
[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
501 static const char f16_3
[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
503 static const char f16_4
[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5
[] =
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6
[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7
[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8
[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt
[] = {
518 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
519 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
521 static const char *const f16_patt
[] = {
522 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
523 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
526 if (count
<= 0 || count
> 15)
529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code
== CODE_64BIT
)
534 int nnops
= (count
+ 3) / 4;
535 int len
= count
/ nnops
;
536 int remains
= count
- nnops
* len
;
539 for (i
= 0; i
< remains
; i
++)
541 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
542 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
545 for (; i
< nnops
; i
++)
547 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
548 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
553 if (flag_code
== CODE_16BIT
)
555 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
556 f16_patt
[count
- 1], count
);
558 /* Adjust jump offset. */
559 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
562 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
563 f32_patt
[count
- 1], count
);
564 fragP
->fr_var
= count
;
567 static INLINE
unsigned int
568 mode_from_disp_size (t
)
571 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
575 fits_in_signed_byte (num
)
578 return (num
>= -128) && (num
<= 127);
582 fits_in_unsigned_byte (num
)
585 return (num
& 0xff) == num
;
589 fits_in_unsigned_word (num
)
592 return (num
& 0xffff) == num
;
596 fits_in_signed_word (num
)
599 return (-32768 <= num
) && (num
<= 32767);
602 fits_in_signed_long (num
)
603 offsetT num ATTRIBUTE_UNUSED
;
608 return (!(((offsetT
) -1 << 31) & num
)
609 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
611 } /* fits_in_signed_long() */
613 fits_in_unsigned_long (num
)
614 offsetT num ATTRIBUTE_UNUSED
;
619 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
621 } /* fits_in_unsigned_long() */
624 smallest_imm_type (num
)
627 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
635 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
637 return (fits_in_signed_byte (num
)
638 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
639 : fits_in_unsigned_byte (num
)
640 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
641 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
642 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
643 : fits_in_signed_long (num
)
644 ? (Imm32
| Imm32S
| Imm64
)
645 : fits_in_unsigned_long (num
)
651 offset_in_range (val
, size
)
659 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
660 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
661 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
663 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
668 /* If BFD64, sign extend val. */
669 if (!use_rela_relocations
)
670 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
671 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
673 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
675 char buf1
[40], buf2
[40];
677 sprint_value (buf1
, val
);
678 sprint_value (buf2
, val
& mask
);
679 as_warn (_("%s shortened to %s"), buf1
, buf2
);
684 /* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
694 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
695 && flag_code
== CODE_64BIT
)
703 case CS_PREFIX_OPCODE
:
704 case DS_PREFIX_OPCODE
:
705 case ES_PREFIX_OPCODE
:
706 case FS_PREFIX_OPCODE
:
707 case GS_PREFIX_OPCODE
:
708 case SS_PREFIX_OPCODE
:
712 case REPNE_PREFIX_OPCODE
:
713 case REPE_PREFIX_OPCODE
:
716 case LOCK_PREFIX_OPCODE
:
724 case ADDR_PREFIX_OPCODE
:
728 case DATA_PREFIX_OPCODE
:
733 if (i
.prefix
[q
] != 0)
735 as_bad (_("same type of prefix used twice"));
740 i
.prefix
[q
] = prefix
;
745 set_code_flag (value
)
749 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
750 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
751 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
753 as_bad (_("64bit mode not supported on this CPU."));
755 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
757 as_bad (_("32bit mode not supported on this CPU."));
763 set_16bit_gcc_code_flag (new_code_flag
)
766 flag_code
= new_code_flag
;
767 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
768 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
773 set_intel_syntax (syntax_flag
)
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg
= 0;
780 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
782 char *string
= input_line_pointer
;
783 int e
= get_symbol_end ();
785 if (strcmp (string
, "prefix") == 0)
787 else if (strcmp (string
, "noprefix") == 0)
790 as_bad (_("bad argument to syntax directive."));
791 *input_line_pointer
= e
;
793 demand_empty_rest_of_line ();
795 intel_syntax
= syntax_flag
;
797 if (ask_naked_reg
== 0)
800 allow_naked_reg
= (intel_syntax
801 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
803 /* Conservative default. */
808 allow_naked_reg
= (ask_naked_reg
< 0);
813 int dummy ATTRIBUTE_UNUSED
;
817 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
819 char *string
= input_line_pointer
;
820 int e
= get_symbol_end ();
823 for (i
= 0; cpu_arch
[i
].name
; i
++)
825 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
827 cpu_arch_name
= cpu_arch
[i
].name
;
828 cpu_arch_flags
= (cpu_arch
[i
].flags
829 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
833 if (!cpu_arch
[i
].name
)
834 as_bad (_("no such architecture: `%s'"), string
);
836 *input_line_pointer
= e
;
839 as_bad (_("missing cpu architecture"));
841 no_cond_jump_promotion
= 0;
842 if (*input_line_pointer
== ','
843 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
845 char *string
= ++input_line_pointer
;
846 int e
= get_symbol_end ();
848 if (strcmp (string
, "nojumps") == 0)
849 no_cond_jump_promotion
= 1;
850 else if (strcmp (string
, "jumps") == 0)
853 as_bad (_("no such architecture modifier: `%s'"), string
);
855 *input_line_pointer
= e
;
858 demand_empty_rest_of_line ();
865 if (!strcmp (default_arch
, "x86_64"))
866 return bfd_mach_x86_64
;
867 else if (!strcmp (default_arch
, "i386"))
868 return bfd_mach_i386_i386
;
870 as_fatal (_("Unknown architecture"));
877 const char *hash_err
;
879 /* Initialize op_hash hash table. */
880 op_hash
= hash_new ();
883 const template *optab
;
884 templates
*core_optab
;
886 /* Setup for loop. */
888 core_optab
= (templates
*) xmalloc (sizeof (templates
));
889 core_optab
->start
= optab
;
894 if (optab
->name
== NULL
895 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
897 /* different name --> ship out current template list;
898 add to hash table; & begin anew. */
899 core_optab
->end
= optab
;
900 hash_err
= hash_insert (op_hash
,
905 as_fatal (_("Internal Error: Can't hash %s: %s"),
909 if (optab
->name
== NULL
)
911 core_optab
= (templates
*) xmalloc (sizeof (templates
));
912 core_optab
->start
= optab
;
917 /* Initialize reg_hash hash table. */
918 reg_hash
= hash_new ();
920 const reg_entry
*regtab
;
922 for (regtab
= i386_regtab
;
923 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
926 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
928 as_fatal (_("Internal Error: Can't hash %s: %s"),
934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
939 for (c
= 0; c
< 256; c
++)
944 mnemonic_chars
[c
] = c
;
945 register_chars
[c
] = c
;
946 operand_chars
[c
] = c
;
948 else if (ISLOWER (c
))
950 mnemonic_chars
[c
] = c
;
951 register_chars
[c
] = c
;
952 operand_chars
[c
] = c
;
954 else if (ISUPPER (c
))
956 mnemonic_chars
[c
] = TOLOWER (c
);
957 register_chars
[c
] = mnemonic_chars
[c
];
958 operand_chars
[c
] = c
;
961 if (ISALPHA (c
) || ISDIGIT (c
))
962 identifier_chars
[c
] = c
;
965 identifier_chars
[c
] = c
;
966 operand_chars
[c
] = c
;
971 identifier_chars
['@'] = '@';
973 digit_chars
['-'] = '-';
974 identifier_chars
['_'] = '_';
975 identifier_chars
['.'] = '.';
977 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
978 operand_chars
[(unsigned char) *p
] = *p
;
981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
984 record_alignment (text_section
, 2);
985 record_alignment (data_section
, 2);
986 record_alignment (bss_section
, 2);
992 i386_print_statistics (file
)
995 hash_print_statistics (file
, "i386 opcode", op_hash
);
996 hash_print_statistics (file
, "i386 register", reg_hash
);
1001 /* Debugging routines for md_assemble. */
1002 static void pi
PARAMS ((char *, i386_insn
*));
1003 static void pte
PARAMS ((template *));
1004 static void pt
PARAMS ((unsigned int));
1005 static void pe
PARAMS ((expressionS
*));
1006 static void ps
PARAMS ((symbolS
*));
1015 fprintf (stdout
, "%s: template ", line
);
1017 fprintf (stdout
, " address: base %s index %s scale %x\n",
1018 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1019 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1020 x
->log2_scale_factor
);
1021 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1022 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1023 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1024 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1025 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1026 (x
->rex
& REX_MODE64
) != 0,
1027 (x
->rex
& REX_EXTX
) != 0,
1028 (x
->rex
& REX_EXTY
) != 0,
1029 (x
->rex
& REX_EXTZ
) != 0);
1030 for (i
= 0; i
< x
->operands
; i
++)
1032 fprintf (stdout
, " #%d: ", i
+ 1);
1034 fprintf (stdout
, "\n");
1036 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1037 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1038 if (x
->types
[i
] & Imm
)
1040 if (x
->types
[i
] & Disp
)
1041 pe (x
->op
[i
].disps
);
1050 fprintf (stdout
, " %d operands ", t
->operands
);
1051 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1052 if (t
->extension_opcode
!= None
)
1053 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1054 if (t
->opcode_modifier
& D
)
1055 fprintf (stdout
, "D");
1056 if (t
->opcode_modifier
& W
)
1057 fprintf (stdout
, "W");
1058 fprintf (stdout
, "\n");
1059 for (i
= 0; i
< t
->operands
; i
++)
1061 fprintf (stdout
, " #%d type ", i
+ 1);
1062 pt (t
->operand_types
[i
]);
1063 fprintf (stdout
, "\n");
1071 fprintf (stdout
, " operation %d\n", e
->X_op
);
1072 fprintf (stdout
, " add_number %ld (%lx)\n",
1073 (long) e
->X_add_number
, (long) e
->X_add_number
);
1074 if (e
->X_add_symbol
)
1076 fprintf (stdout
, " add_symbol ");
1077 ps (e
->X_add_symbol
);
1078 fprintf (stdout
, "\n");
1082 fprintf (stdout
, " op_symbol ");
1083 ps (e
->X_op_symbol
);
1084 fprintf (stdout
, "\n");
1092 fprintf (stdout
, "%s type %s%s",
1094 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s
)));
1104 static const type_names
[] =
1117 { BaseIndex
, "BaseIndex" },
1121 { Disp32S
, "d32s" },
1123 { InOutPortReg
, "InOutPortReg" },
1124 { ShiftCount
, "ShiftCount" },
1125 { Control
, "control reg" },
1126 { Test
, "test reg" },
1127 { Debug
, "debug reg" },
1128 { FloatReg
, "FReg" },
1129 { FloatAcc
, "FAcc" },
1133 { JumpAbsolute
, "Jump Absolute" },
1144 const struct type_name
*ty
;
1146 for (ty
= type_names
; ty
->mask
; ty
++)
1148 fprintf (stdout
, "%s, ", ty
->tname
);
1152 #endif /* DEBUG386 */
1154 #ifdef BFD_ASSEMBLER
1155 static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1158 static bfd_reloc_code_real_type
1159 reloc (size
, pcrel
, sign
, other
)
1163 bfd_reloc_code_real_type other
;
1165 if (other
!= NO_RELOC
)
1171 as_bad (_("There are no unsigned pc-relative relocations"));
1174 case 1: return BFD_RELOC_8_PCREL
;
1175 case 2: return BFD_RELOC_16_PCREL
;
1176 case 4: return BFD_RELOC_32_PCREL
;
1178 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1185 case 4: return BFD_RELOC_X86_64_32S
;
1190 case 1: return BFD_RELOC_8
;
1191 case 2: return BFD_RELOC_16
;
1192 case 4: return BFD_RELOC_32
;
1193 case 8: return BFD_RELOC_64
;
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign
? "signed" : "unsigned", size
);
1200 return BFD_RELOC_NONE
;
1203 /* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1209 tc_i386_fix_adjustable (fixP
)
1210 fixS
*fixP ATTRIBUTE_UNUSED
;
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1223 /* adjust_reloc_syms doesn't know about the GOT. */
1224 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1225 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1226 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1233 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1236 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1237 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1243 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1244 #define BFD_RELOC_8 0
1245 #define BFD_RELOC_16 0
1246 #define BFD_RELOC_32 0
1247 #define BFD_RELOC_8_PCREL 0
1248 #define BFD_RELOC_16_PCREL 0
1249 #define BFD_RELOC_32_PCREL 0
1250 #define BFD_RELOC_386_PLT32 0
1251 #define BFD_RELOC_386_GOT32 0
1252 #define BFD_RELOC_386_GOTOFF 0
1253 #define BFD_RELOC_386_TLS_GD 0
1254 #define BFD_RELOC_386_TLS_LDM 0
1255 #define BFD_RELOC_386_TLS_LDO_32 0
1256 #define BFD_RELOC_386_TLS_IE_32 0
1257 #define BFD_RELOC_386_TLS_LE_32 0
1258 #define BFD_RELOC_386_TLS_LE 0
1259 #define BFD_RELOC_X86_64_PLT32 0
1260 #define BFD_RELOC_X86_64_GOT32 0
1261 #define BFD_RELOC_X86_64_GOTPCREL 0
1264 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1267 intel_float_operand (mnemonic
)
1268 const char *mnemonic
;
1270 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1273 if (mnemonic
[0] == 'f')
1279 /* This is the guts of the machine-dependent assembler. LINE points to a
1280 machine dependent instruction. This function is supposed to emit
1281 the frags/bytes it assembles to. */
1288 char mnemonic
[MAX_MNEM_SIZE
];
1290 /* Initialize globals. */
1291 memset (&i
, '\0', sizeof (i
));
1292 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1293 i
.reloc
[j
] = NO_RELOC
;
1294 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1295 memset (im_expressions
, '\0', sizeof (im_expressions
));
1296 save_stack_p
= save_stack
;
1298 /* First parse an instruction mnemonic & call i386_operand for the operands.
1299 We assume that the scrubber has arranged it so that line[0] is the valid
1300 start of a (possibly prefixed) mnemonic. */
1302 line
= parse_insn (line
, mnemonic
);
1306 line
= parse_operands (line
, mnemonic
);
1310 /* Now we've parsed the mnemonic into a set of templates, and have the
1311 operands at hand. */
1313 /* All intel opcodes have reversed operands except for "bound" and
1314 "enter". We also don't reverse intersegment "jmp" and "call"
1315 instructions with 2 immediate operands so that the immediate segment
1316 precedes the offset, as it does when in AT&T mode. "enter" and the
1317 intersegment "jmp" and "call" instructions are the only ones that
1318 have two immediate operands. */
1319 if (intel_syntax
&& i
.operands
> 1
1320 && (strcmp (mnemonic
, "bound") != 0)
1321 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1327 if (i
.disp_operands
)
1330 /* Next, we find a template that matches the given insn,
1331 making sure the overlap of the given operands types is consistent
1332 with the template operand types. */
1334 if (!match_template ())
1339 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1341 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1342 i
.tm
.base_opcode
^= FloatR
;
1344 /* Zap movzx and movsx suffix. The suffix may have been set from
1345 "word ptr" or "byte ptr" on the source operand, but we'll use
1346 the suffix later to choose the destination register. */
1347 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1351 if (i
.tm
.opcode_modifier
& FWait
)
1352 if (!add_prefix (FWAIT_OPCODE
))
1355 /* Check string instruction segment overrides. */
1356 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1358 if (!check_string ())
1362 if (!process_suffix ())
1365 /* Make still unresolved immediate matches conform to size of immediate
1366 given in i.suffix. */
1367 if (!finalize_imm ())
1370 if (i
.types
[0] & Imm1
)
1371 i
.imm_operands
= 0; /* kludge for shift insns. */
1372 if (i
.types
[0] & ImplicitRegister
)
1374 if (i
.types
[1] & ImplicitRegister
)
1376 if (i
.types
[2] & ImplicitRegister
)
1379 if (i
.tm
.opcode_modifier
& ImmExt
)
1381 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1382 opcode suffix which is coded in the same place as an 8-bit
1383 immediate field would be. Here we fake an 8-bit immediate
1384 operand from the opcode suffix stored in tm.extension_opcode. */
1388 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1390 exp
= &im_expressions
[i
.imm_operands
++];
1391 i
.op
[i
.operands
].imms
= exp
;
1392 i
.types
[i
.operands
++] = Imm8
;
1393 exp
->X_op
= O_constant
;
1394 exp
->X_add_number
= i
.tm
.extension_opcode
;
1395 i
.tm
.extension_opcode
= None
;
1398 /* For insns with operands there are more diddles to do to the opcode. */
1401 if (!process_operands ())
1404 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1406 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1407 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1410 /* Handle conversion of 'int $3' --> special int3 insn. */
1411 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1413 i
.tm
.base_opcode
= INT3_OPCODE
;
1417 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1418 && i
.op
[0].disps
->X_op
== O_constant
)
1420 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1421 the absolute address given by the constant. Since ix86 jumps and
1422 calls are pc relative, we need to generate a reloc. */
1423 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1424 i
.op
[0].disps
->X_op
= O_symbol
;
1427 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1428 i
.rex
|= REX_MODE64
;
1430 /* For 8 bit registers we need an empty rex prefix. Also if the
1431 instruction already has a prefix, we need to convert old
1432 registers to new ones. */
1434 if (((i
.types
[0] & Reg8
) != 0
1435 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1436 || ((i
.types
[1] & Reg8
) != 0
1437 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1438 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1443 i
.rex
|= REX_OPCODE
;
1444 for (x
= 0; x
< 2; x
++)
1446 /* Look for 8 bit operand that uses old registers. */
1447 if ((i
.types
[x
] & Reg8
) != 0
1448 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1450 /* In case it is "hi" register, give up. */
1451 if (i
.op
[x
].regs
->reg_num
> 3)
1452 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1453 i
.op
[x
].regs
->reg_name
);
1455 /* Otherwise it is equivalent to the extended register.
1456 Since the encoding doesn't change this is merely
1457 cosmetic cleanup for debug output. */
1459 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1465 add_prefix (REX_OPCODE
| i
.rex
);
1467 /* We are ready to output the insn. */
1472 parse_insn (line
, mnemonic
)
1477 char *token_start
= l
;
1480 /* Non-zero if we found a prefix only acceptable with string insns. */
1481 const char *expecting_string_instruction
= NULL
;
1486 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1489 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1491 as_bad (_("no such instruction: `%s'"), token_start
);
1496 if (!is_space_char (*l
)
1497 && *l
!= END_OF_INSN
1498 && *l
!= PREFIX_SEPARATOR
1501 as_bad (_("invalid character %s in mnemonic"),
1502 output_invalid (*l
));
1505 if (token_start
== l
)
1507 if (*l
== PREFIX_SEPARATOR
)
1508 as_bad (_("expecting prefix; got nothing"));
1510 as_bad (_("expecting mnemonic; got nothing"));
1514 /* Look up instruction (or prefix) via hash table. */
1515 current_templates
= hash_find (op_hash
, mnemonic
);
1517 if (*l
!= END_OF_INSN
1518 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1519 && current_templates
1520 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1522 /* If we are in 16-bit mode, do not allow addr16 or data16.
1523 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1524 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1525 && flag_code
!= CODE_64BIT
1526 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1527 ^ (flag_code
== CODE_16BIT
)))
1529 as_bad (_("redundant %s prefix"),
1530 current_templates
->start
->name
);
1533 /* Add prefix, checking for repeated prefixes. */
1534 switch (add_prefix (current_templates
->start
->base_opcode
))
1539 expecting_string_instruction
= current_templates
->start
->name
;
1542 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1549 if (!current_templates
)
1551 /* See if we can get a match by trimming off a suffix. */
1554 case WORD_MNEM_SUFFIX
:
1555 case BYTE_MNEM_SUFFIX
:
1556 case QWORD_MNEM_SUFFIX
:
1557 i
.suffix
= mnem_p
[-1];
1559 current_templates
= hash_find (op_hash
, mnemonic
);
1561 case SHORT_MNEM_SUFFIX
:
1562 case LONG_MNEM_SUFFIX
:
1565 i
.suffix
= mnem_p
[-1];
1567 current_templates
= hash_find (op_hash
, mnemonic
);
1575 if (intel_float_operand (mnemonic
))
1576 i
.suffix
= SHORT_MNEM_SUFFIX
;
1578 i
.suffix
= LONG_MNEM_SUFFIX
;
1580 current_templates
= hash_find (op_hash
, mnemonic
);
1584 if (!current_templates
)
1586 as_bad (_("no such instruction: `%s'"), token_start
);
1591 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1593 /* Check for a branch hint. We allow ",pt" and ",pn" for
1594 predict taken and predict not taken respectively.
1595 I'm not sure that branch hints actually do anything on loop
1596 and jcxz insns (JumpByte) for current Pentium4 chips. They
1597 may work in the future and it doesn't hurt to accept them
1599 if (l
[0] == ',' && l
[1] == 'p')
1603 if (!add_prefix (DS_PREFIX_OPCODE
))
1607 else if (l
[2] == 'n')
1609 if (!add_prefix (CS_PREFIX_OPCODE
))
1615 /* Any other comma loses. */
1618 as_bad (_("invalid character %s in mnemonic"),
1619 output_invalid (*l
));
1623 /* Check if instruction is supported on specified architecture. */
1624 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1625 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1627 as_warn (_("`%s' is not supported on `%s'"),
1628 current_templates
->start
->name
, cpu_arch_name
);
1630 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1632 as_warn (_("use .code16 to ensure correct addressing mode"));
1635 /* Check for rep/repne without a string instruction. */
1636 if (expecting_string_instruction
1637 && !(current_templates
->start
->opcode_modifier
& IsString
))
1639 as_bad (_("expecting string instruction after `%s'"),
1640 expecting_string_instruction
);
1648 parse_operands (l
, mnemonic
)
1650 const char *mnemonic
;
1654 /* 1 if operand is pending after ','. */
1655 unsigned int expecting_operand
= 0;
1657 /* Non-zero if operand parens not balanced. */
1658 unsigned int paren_not_balanced
;
1660 while (*l
!= END_OF_INSN
)
1662 /* Skip optional white space before operand. */
1663 if (is_space_char (*l
))
1665 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1667 as_bad (_("invalid character %s before operand %d"),
1668 output_invalid (*l
),
1672 token_start
= l
; /* after white space */
1673 paren_not_balanced
= 0;
1674 while (paren_not_balanced
|| *l
!= ',')
1676 if (*l
== END_OF_INSN
)
1678 if (paren_not_balanced
)
1681 as_bad (_("unbalanced parenthesis in operand %d."),
1684 as_bad (_("unbalanced brackets in operand %d."),
1689 break; /* we are done */
1691 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1693 as_bad (_("invalid character %s in operand %d"),
1694 output_invalid (*l
),
1701 ++paren_not_balanced
;
1703 --paren_not_balanced
;
1708 ++paren_not_balanced
;
1710 --paren_not_balanced
;
1714 if (l
!= token_start
)
1715 { /* Yes, we've read in another operand. */
1716 unsigned int operand_ok
;
1717 this_operand
= i
.operands
++;
1718 if (i
.operands
> MAX_OPERANDS
)
1720 as_bad (_("spurious operands; (%d operands/instruction max)"),
1724 /* Now parse operand adding info to 'i' as we go along. */
1725 END_STRING_AND_SAVE (l
);
1729 i386_intel_operand (token_start
,
1730 intel_float_operand (mnemonic
));
1732 operand_ok
= i386_operand (token_start
);
1734 RESTORE_END_STRING (l
);
1740 if (expecting_operand
)
1742 expecting_operand_after_comma
:
1743 as_bad (_("expecting operand after ','; got nothing"));
1748 as_bad (_("expecting operand before ','; got nothing"));
1753 /* Now *l must be either ',' or END_OF_INSN. */
1756 if (*++l
== END_OF_INSN
)
1758 /* Just skip it, if it's \n complain. */
1759 goto expecting_operand_after_comma
;
1761 expecting_operand
= 1;
1770 union i386_op temp_op
;
1771 unsigned int temp_type
;
1772 RELOC_ENUM temp_reloc
;
1776 if (i
.operands
== 2)
1781 else if (i
.operands
== 3)
1786 temp_type
= i
.types
[xchg2
];
1787 i
.types
[xchg2
] = i
.types
[xchg1
];
1788 i
.types
[xchg1
] = temp_type
;
1789 temp_op
= i
.op
[xchg2
];
1790 i
.op
[xchg2
] = i
.op
[xchg1
];
1791 i
.op
[xchg1
] = temp_op
;
1792 temp_reloc
= i
.reloc
[xchg2
];
1793 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1794 i
.reloc
[xchg1
] = temp_reloc
;
1796 if (i
.mem_operands
== 2)
1798 const seg_entry
*temp_seg
;
1799 temp_seg
= i
.seg
[0];
1800 i
.seg
[0] = i
.seg
[1];
1801 i
.seg
[1] = temp_seg
;
1805 /* Try to ensure constant immediates are represented in the smallest
1810 char guess_suffix
= 0;
1814 guess_suffix
= i
.suffix
;
1815 else if (i
.reg_operands
)
1817 /* Figure out a suffix from the last register operand specified.
1818 We can't do this properly yet, ie. excluding InOutPortReg,
1819 but the following works for instructions with immediates.
1820 In any case, we can't set i.suffix yet. */
1821 for (op
= i
.operands
; --op
>= 0;)
1822 if (i
.types
[op
] & Reg
)
1824 if (i
.types
[op
] & Reg8
)
1825 guess_suffix
= BYTE_MNEM_SUFFIX
;
1826 else if (i
.types
[op
] & Reg16
)
1827 guess_suffix
= WORD_MNEM_SUFFIX
;
1828 else if (i
.types
[op
] & Reg32
)
1829 guess_suffix
= LONG_MNEM_SUFFIX
;
1830 else if (i
.types
[op
] & Reg64
)
1831 guess_suffix
= QWORD_MNEM_SUFFIX
;
1835 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1836 guess_suffix
= WORD_MNEM_SUFFIX
;
1838 for (op
= i
.operands
; --op
>= 0;)
1839 if (i
.types
[op
] & Imm
)
1841 switch (i
.op
[op
].imms
->X_op
)
1844 /* If a suffix is given, this operand may be shortened. */
1845 switch (guess_suffix
)
1847 case LONG_MNEM_SUFFIX
:
1848 i
.types
[op
] |= Imm32
| Imm64
;
1850 case WORD_MNEM_SUFFIX
:
1851 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1853 case BYTE_MNEM_SUFFIX
:
1854 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1858 /* If this operand is at most 16 bits, convert it
1859 to a signed 16 bit number before trying to see
1860 whether it will fit in an even smaller size.
1861 This allows a 16-bit operand such as $0xffe0 to
1862 be recognised as within Imm8S range. */
1863 if ((i
.types
[op
] & Imm16
)
1864 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1866 i
.op
[op
].imms
->X_add_number
=
1867 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1869 if ((i
.types
[op
] & Imm32
)
1870 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1873 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1874 ^ ((offsetT
) 1 << 31))
1875 - ((offsetT
) 1 << 31));
1877 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1879 /* We must avoid matching of Imm32 templates when 64bit
1880 only immediate is available. */
1881 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1882 i
.types
[op
] &= ~Imm32
;
1889 /* Symbols and expressions. */
1891 /* Convert symbolic operand to proper sizes for matching. */
1892 switch (guess_suffix
)
1894 case QWORD_MNEM_SUFFIX
:
1895 i
.types
[op
] = Imm64
| Imm32S
;
1897 case LONG_MNEM_SUFFIX
:
1898 i
.types
[op
] = Imm32
| Imm64
;
1900 case WORD_MNEM_SUFFIX
:
1901 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1904 case BYTE_MNEM_SUFFIX
:
1905 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1914 /* Try to use the smallest displacement type too. */
1920 for (op
= i
.operands
; --op
>= 0;)
1921 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1923 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1925 if (i
.types
[op
] & Disp16
)
1927 /* We know this operand is at most 16 bits, so
1928 convert to a signed 16 bit number before trying
1929 to see whether it will fit in an even smaller
1932 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1934 else if (i
.types
[op
] & Disp32
)
1936 /* We know this operand is at most 32 bits, so convert to a
1937 signed 32 bit number before trying to see whether it will
1938 fit in an even smaller size. */
1939 disp
&= (((offsetT
) 2 << 31) - 1);
1940 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1942 if (flag_code
== CODE_64BIT
)
1944 if (fits_in_signed_long (disp
))
1945 i
.types
[op
] |= Disp32S
;
1946 if (fits_in_unsigned_long (disp
))
1947 i
.types
[op
] |= Disp32
;
1949 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1950 && fits_in_signed_byte (disp
))
1951 i
.types
[op
] |= Disp8
;
1958 /* Points to template once we've found it. */
1960 unsigned int overlap0
, overlap1
, overlap2
;
1961 unsigned int found_reverse_match
;
1964 #define MATCH(overlap, given, template) \
1965 ((overlap & ~JumpAbsolute) \
1966 && (((given) & (BaseIndex | JumpAbsolute)) \
1967 == ((overlap) & (BaseIndex | JumpAbsolute))))
1969 /* If given types r0 and r1 are registers they must be of the same type
1970 unless the expected operand type register overlap is null.
1971 Note that Acc in a template matches every size of reg. */
1972 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1973 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1974 || ((g0) & Reg) == ((g1) & Reg) \
1975 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1980 found_reverse_match
= 0;
1981 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1983 : (i
.suffix
== WORD_MNEM_SUFFIX
1985 : (i
.suffix
== SHORT_MNEM_SUFFIX
1987 : (i
.suffix
== LONG_MNEM_SUFFIX
1989 : (i
.suffix
== QWORD_MNEM_SUFFIX
1991 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
1992 ? No_xSuf
: 0))))));
1994 for (t
= current_templates
->start
;
1995 t
< current_templates
->end
;
1998 /* Must have right number of operands. */
1999 if (i
.operands
!= t
->operands
)
2002 /* Check the suffix, except for some instructions in intel mode. */
2003 if ((t
->opcode_modifier
& suffix_check
)
2005 && (t
->opcode_modifier
& IgnoreSize
))
2007 && t
->base_opcode
== 0xd9
2008 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2009 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2012 /* Do not verify operands when there are none. */
2013 else if (!t
->operands
)
2015 if (t
->cpu_flags
& ~cpu_arch_flags
)
2017 /* We've found a match; break out of loop. */
2021 overlap0
= i
.types
[0] & t
->operand_types
[0];
2022 switch (t
->operands
)
2025 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2030 overlap1
= i
.types
[1] & t
->operand_types
[1];
2031 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2032 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2033 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2034 t
->operand_types
[0],
2035 overlap1
, i
.types
[1],
2036 t
->operand_types
[1]))
2038 /* Check if other direction is valid ... */
2039 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2042 /* Try reversing direction of operands. */
2043 overlap0
= i
.types
[0] & t
->operand_types
[1];
2044 overlap1
= i
.types
[1] & t
->operand_types
[0];
2045 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2046 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2047 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2048 t
->operand_types
[1],
2049 overlap1
, i
.types
[1],
2050 t
->operand_types
[0]))
2052 /* Does not match either direction. */
2055 /* found_reverse_match holds which of D or FloatDR
2057 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2059 /* Found a forward 2 operand match here. */
2060 else if (t
->operands
== 3)
2062 /* Here we make use of the fact that there are no
2063 reverse match 3 operand instructions, and all 3
2064 operand instructions only need to be checked for
2065 register consistency between operands 2 and 3. */
2066 overlap2
= i
.types
[2] & t
->operand_types
[2];
2067 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2068 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2069 t
->operand_types
[1],
2070 overlap2
, i
.types
[2],
2071 t
->operand_types
[2]))
2075 /* Found either forward/reverse 2 or 3 operand match here:
2076 slip through to break. */
2078 if (t
->cpu_flags
& ~cpu_arch_flags
)
2080 found_reverse_match
= 0;
2083 /* We've found a match; break out of loop. */
2087 if (t
== current_templates
->end
)
2089 /* We found no match. */
2090 as_bad (_("suffix or operands invalid for `%s'"),
2091 current_templates
->start
->name
);
2095 if (!quiet_warnings
)
2098 && ((i
.types
[0] & JumpAbsolute
)
2099 != (t
->operand_types
[0] & JumpAbsolute
)))
2101 as_warn (_("indirect %s without `*'"), t
->name
);
2104 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2105 == (IsPrefix
| IgnoreSize
))
2107 /* Warn them that a data or address size prefix doesn't
2108 affect assembly of the next line of code. */
2109 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2113 /* Copy the template we found. */
2115 if (found_reverse_match
)
2117 /* If we found a reverse match we must alter the opcode
2118 direction bit. found_reverse_match holds bits to change
2119 (different for int & float insns). */
2121 i
.tm
.base_opcode
^= found_reverse_match
;
2123 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2124 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2133 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2134 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2136 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2138 as_bad (_("`%s' operand %d must use `%%es' segment"),
2143 /* There's only ever one segment override allowed per instruction.
2144 This instruction possibly has a legal segment override on the
2145 second operand, so copy the segment to where non-string
2146 instructions store it, allowing common code. */
2147 i
.seg
[0] = i
.seg
[1];
2149 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2151 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2153 as_bad (_("`%s' operand %d must use `%%es' segment"),
2165 /* If matched instruction specifies an explicit instruction mnemonic
2167 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2169 if (i
.tm
.opcode_modifier
& Size16
)
2170 i
.suffix
= WORD_MNEM_SUFFIX
;
2171 else if (i
.tm
.opcode_modifier
& Size64
)
2172 i
.suffix
= QWORD_MNEM_SUFFIX
;
2174 i
.suffix
= LONG_MNEM_SUFFIX
;
2176 else if (i
.reg_operands
)
2178 /* If there's no instruction mnemonic suffix we try to invent one
2179 based on register operands. */
2182 /* We take i.suffix from the last register operand specified,
2183 Destination register type is more significant than source
2186 for (op
= i
.operands
; --op
>= 0;)
2187 if ((i
.types
[op
] & Reg
)
2188 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2190 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2191 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2192 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2197 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2199 if (!check_byte_reg ())
2202 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2204 if (!check_long_reg ())
2207 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2209 if (!check_qword_reg ())
2212 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2214 if (!check_word_reg ())
2217 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2218 /* Do nothing if the instruction is going to ignore the prefix. */
2223 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2225 i
.suffix
= stackop_size
;
2228 /* Change the opcode based on the operand size given by i.suffix;
2229 We need not change things for byte insns. */
2231 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2233 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2237 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2239 /* It's not a byte, select word/dword operation. */
2240 if (i
.tm
.opcode_modifier
& W
)
2242 if (i
.tm
.opcode_modifier
& ShortForm
)
2243 i
.tm
.base_opcode
|= 8;
2245 i
.tm
.base_opcode
|= 1;
2248 /* Now select between word & dword operations via the operand
2249 size prefix, except for instructions that will ignore this
2251 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2252 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2253 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2254 || (flag_code
== CODE_64BIT
2255 && (i
.tm
.opcode_modifier
& JumpByte
))))
2257 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2258 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2259 prefix
= ADDR_PREFIX_OPCODE
;
2261 if (!add_prefix (prefix
))
2265 /* Set mode64 for an operand. */
2266 if (i
.suffix
== QWORD_MNEM_SUFFIX
2267 && flag_code
== CODE_64BIT
2268 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2269 i
.rex
|= REX_MODE64
;
2271 /* Size floating point instruction. */
2272 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2274 if (i
.tm
.opcode_modifier
& FloatMF
)
2275 i
.tm
.base_opcode
^= 4;
2286 for (op
= i
.operands
; --op
>= 0;)
2288 /* If this is an eight bit register, it's OK. If it's the 16 or
2289 32 bit version of an eight bit register, we will just use the
2290 low portion, and that's OK too. */
2291 if (i
.types
[op
] & Reg8
)
2294 /* movzx and movsx should not generate this warning. */
2296 && (i
.tm
.base_opcode
== 0xfb7
2297 || i
.tm
.base_opcode
== 0xfb6
2298 || i
.tm
.base_opcode
== 0x63
2299 || i
.tm
.base_opcode
== 0xfbe
2300 || i
.tm
.base_opcode
== 0xfbf))
2303 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2305 /* Check that the template allows eight bit regs. This
2306 kills insns such as `orb $1,%edx', which maybe should be
2308 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2312 /* Prohibit these changes in the 64bit mode, since the
2313 lowering is more complicated. */
2314 if (flag_code
== CODE_64BIT
2315 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2317 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2318 i
.op
[op
].regs
->reg_name
,
2322 #if REGISTER_WARNINGS
2324 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2325 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2326 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2327 ? REGNAM_AL
- REGNAM_AX
2328 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2329 i
.op
[op
].regs
->reg_name
,
2334 /* Any other register is bad. */
2335 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2337 | Control
| Debug
| Test
2338 | FloatReg
| FloatAcc
))
2340 as_bad (_("`%%%s' not allowed with `%s%c'"),
2341 i
.op
[op
].regs
->reg_name
,
2355 for (op
= i
.operands
; --op
>= 0;)
2356 /* Reject eight bit registers, except where the template requires
2357 them. (eg. movzb) */
2358 if ((i
.types
[op
] & Reg8
) != 0
2359 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2361 as_bad (_("`%%%s' not allowed with `%s%c'"),
2362 i
.op
[op
].regs
->reg_name
,
2367 /* Warn if the e prefix on a general reg is missing. */
2368 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2369 && (i
.types
[op
] & Reg16
) != 0
2370 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2372 /* Prohibit these changes in the 64bit mode, since the
2373 lowering is more complicated. */
2374 if (flag_code
== CODE_64BIT
)
2376 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2377 i
.op
[op
].regs
->reg_name
,
2381 #if REGISTER_WARNINGS
2383 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2384 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2385 i
.op
[op
].regs
->reg_name
,
2389 /* Warn if the r prefix on a general reg is missing. */
2390 else if ((i
.types
[op
] & Reg64
) != 0
2391 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2393 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2394 i
.op
[op
].regs
->reg_name
,
2406 for (op
= i
.operands
; --op
>= 0; )
2407 /* Reject eight bit registers, except where the template requires
2408 them. (eg. movzb) */
2409 if ((i
.types
[op
] & Reg8
) != 0
2410 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2412 as_bad (_("`%%%s' not allowed with `%s%c'"),
2413 i
.op
[op
].regs
->reg_name
,
2418 /* Warn if the e prefix on a general reg is missing. */
2419 else if (((i
.types
[op
] & Reg16
) != 0
2420 || (i
.types
[op
] & Reg32
) != 0)
2421 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2423 /* Prohibit these changes in the 64bit mode, since the
2424 lowering is more complicated. */
2425 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2426 i
.op
[op
].regs
->reg_name
,
2437 for (op
= i
.operands
; --op
>= 0;)
2438 /* Reject eight bit registers, except where the template requires
2439 them. (eg. movzb) */
2440 if ((i
.types
[op
] & Reg8
) != 0
2441 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2443 as_bad (_("`%%%s' not allowed with `%s%c'"),
2444 i
.op
[op
].regs
->reg_name
,
2449 /* Warn if the e prefix on a general reg is present. */
2450 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2451 && (i
.types
[op
] & Reg32
) != 0
2452 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2454 /* Prohibit these changes in the 64bit mode, since the
2455 lowering is more complicated. */
2456 if (flag_code
== CODE_64BIT
)
2458 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2459 i
.op
[op
].regs
->reg_name
,
2464 #if REGISTER_WARNINGS
2465 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2466 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2467 i
.op
[op
].regs
->reg_name
,
2477 unsigned int overlap0
, overlap1
, overlap2
;
2479 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2480 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2481 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2482 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2483 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2487 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2489 : (i
.suffix
== WORD_MNEM_SUFFIX
2491 : (i
.suffix
== QWORD_MNEM_SUFFIX
2495 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2496 || overlap0
== (Imm16
| Imm32
)
2497 || overlap0
== (Imm16
| Imm32S
))
2499 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2502 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2503 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2504 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2506 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2510 i
.types
[0] = overlap0
;
2512 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2513 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2514 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2515 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2516 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2520 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2522 : (i
.suffix
== WORD_MNEM_SUFFIX
2524 : (i
.suffix
== QWORD_MNEM_SUFFIX
2528 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2529 || overlap1
== (Imm16
| Imm32
)
2530 || overlap1
== (Imm16
| Imm32S
))
2532 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2535 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2536 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2537 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2539 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2543 i
.types
[1] = overlap1
;
2545 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2546 assert ((overlap2
& Imm
) == 0);
2547 i
.types
[2] = overlap2
;
2555 /* Default segment register this instruction will use for memory
2556 accesses. 0 means unknown. This is only for optimizing out
2557 unnecessary segment overrides. */
2558 const seg_entry
*default_seg
= 0;
2560 /* The imul $imm, %reg instruction is converted into
2561 imul $imm, %reg, %reg, and the clr %reg instruction
2562 is converted into xor %reg, %reg. */
2563 if (i
.tm
.opcode_modifier
& regKludge
)
2565 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2566 /* Pretend we saw the extra register operand. */
2567 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2568 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2569 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2573 if (i
.tm
.opcode_modifier
& ShortForm
)
2575 /* The register or float register operand is in operand 0 or 1. */
2576 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2577 /* Register goes in low 3 bits of opcode. */
2578 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2579 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2581 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2583 /* Warn about some common errors, but press on regardless.
2584 The first case can be generated by gcc (<= 2.8.1). */
2585 if (i
.operands
== 2)
2587 /* Reversed arguments on faddp, fsubp, etc. */
2588 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2589 i
.op
[1].regs
->reg_name
,
2590 i
.op
[0].regs
->reg_name
);
2594 /* Extraneous `l' suffix on fp insn. */
2595 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2596 i
.op
[0].regs
->reg_name
);
2600 else if (i
.tm
.opcode_modifier
& Modrm
)
2602 /* The opcode is completed (modulo i.tm.extension_opcode which
2603 must be put into the modrm byte).
2604 Now, we make the modrm & index base bytes based on all the
2605 info we've collected. */
2607 default_seg
= build_modrm_byte ();
2609 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2611 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2612 && i
.op
[0].regs
->reg_num
== 1)
2614 as_bad (_("you can't `pop %%cs'"));
2617 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2618 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2621 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2625 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2627 /* For the string instructions that allow a segment override
2628 on one of their operands, the default segment is ds. */
2632 /* If a segment was explicitly specified,
2633 and the specified segment is not the default,
2634 use an opcode prefix to select it.
2635 If we never figured out what the default segment is,
2636 then default_seg will be zero at this point,
2637 and the specified segment prefix will always be used. */
2638 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2640 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2646 static const seg_entry
*
2649 const seg_entry
*default_seg
= 0;
2651 /* i.reg_operands MUST be the number of real register operands;
2652 implicit registers do not count. */
2653 if (i
.reg_operands
== 2)
2655 unsigned int source
, dest
;
2656 source
= ((i
.types
[0]
2657 & (Reg
| RegMMX
| RegXMM
2659 | Control
| Debug
| Test
))
2664 /* One of the register operands will be encoded in the i.tm.reg
2665 field, the other in the combined i.tm.mode and i.tm.regmem
2666 fields. If no form of this instruction supports a memory
2667 destination operand, then we assume the source operand may
2668 sometimes be a memory operand and so we need to store the
2669 destination in the i.rm.reg field. */
2670 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2672 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2673 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2674 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2676 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2681 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2682 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2683 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2685 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2690 { /* If it's not 2 reg operands... */
2693 unsigned int fake_zero_displacement
= 0;
2694 unsigned int op
= ((i
.types
[0] & AnyMem
)
2696 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2700 if (i
.base_reg
== 0)
2703 if (!i
.disp_operands
)
2704 fake_zero_displacement
= 1;
2705 if (i
.index_reg
== 0)
2707 /* Operand is just <disp> */
2708 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2709 && (flag_code
!= CODE_64BIT
))
2711 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2712 i
.types
[op
] &= ~Disp
;
2713 i
.types
[op
] |= Disp16
;
2715 else if (flag_code
!= CODE_64BIT
2716 || (i
.prefix
[ADDR_PREFIX
] != 0))
2718 i
.rm
.regmem
= NO_BASE_REGISTER
;
2719 i
.types
[op
] &= ~Disp
;
2720 i
.types
[op
] |= Disp32
;
2724 /* 64bit mode overwrites the 32bit absolute
2725 addressing by RIP relative addressing and
2726 absolute addressing is encoded by one of the
2727 redundant SIB forms. */
2728 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2729 i
.sib
.base
= NO_BASE_REGISTER
;
2730 i
.sib
.index
= NO_INDEX_REGISTER
;
2731 i
.types
[op
] &= ~Disp
;
2732 i
.types
[op
] |= Disp32S
;
2735 else /* !i.base_reg && i.index_reg */
2737 i
.sib
.index
= i
.index_reg
->reg_num
;
2738 i
.sib
.base
= NO_BASE_REGISTER
;
2739 i
.sib
.scale
= i
.log2_scale_factor
;
2740 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2741 i
.types
[op
] &= ~Disp
;
2742 if (flag_code
!= CODE_64BIT
)
2743 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2745 i
.types
[op
] |= Disp32S
;
2746 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2750 /* RIP addressing for 64bit mode. */
2751 else if (i
.base_reg
->reg_type
== BaseIndex
)
2753 i
.rm
.regmem
= NO_BASE_REGISTER
;
2754 i
.types
[op
] &= ~Disp
;
2755 i
.types
[op
] |= Disp32S
;
2756 i
.flags
[op
] = Operand_PCrel
;
2758 else if (i
.base_reg
->reg_type
& Reg16
)
2760 switch (i
.base_reg
->reg_num
)
2763 if (i
.index_reg
== 0)
2765 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2766 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2770 if (i
.index_reg
== 0)
2773 if ((i
.types
[op
] & Disp
) == 0)
2775 /* fake (%bp) into 0(%bp) */
2776 i
.types
[op
] |= Disp8
;
2777 fake_zero_displacement
= 1;
2780 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2781 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2783 default: /* (%si) -> 4 or (%di) -> 5 */
2784 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2786 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2788 else /* i.base_reg and 32/64 bit mode */
2790 if (flag_code
== CODE_64BIT
2791 && (i
.types
[op
] & Disp
))
2793 if (i
.types
[op
] & Disp8
)
2794 i
.types
[op
] = Disp8
| Disp32S
;
2796 i
.types
[op
] = Disp32S
;
2798 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2799 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2801 i
.sib
.base
= i
.base_reg
->reg_num
;
2802 /* x86-64 ignores REX prefix bit here to avoid decoder
2804 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2807 if (i
.disp_operands
== 0)
2809 fake_zero_displacement
= 1;
2810 i
.types
[op
] |= Disp8
;
2813 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2817 i
.sib
.scale
= i
.log2_scale_factor
;
2818 if (i
.index_reg
== 0)
2820 /* <disp>(%esp) becomes two byte modrm with no index
2821 register. We've already stored the code for esp
2822 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2823 Any base register besides %esp will not use the
2824 extra modrm byte. */
2825 i
.sib
.index
= NO_INDEX_REGISTER
;
2826 #if !SCALE1_WHEN_NO_INDEX
2827 /* Another case where we force the second modrm byte. */
2828 if (i
.log2_scale_factor
)
2829 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2834 i
.sib
.index
= i
.index_reg
->reg_num
;
2835 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2836 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2839 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2842 if (fake_zero_displacement
)
2844 /* Fakes a zero displacement assuming that i.types[op]
2845 holds the correct displacement size. */
2848 assert (i
.op
[op
].disps
== 0);
2849 exp
= &disp_expressions
[i
.disp_operands
++];
2850 i
.op
[op
].disps
= exp
;
2851 exp
->X_op
= O_constant
;
2852 exp
->X_add_number
= 0;
2853 exp
->X_add_symbol
= (symbolS
*) 0;
2854 exp
->X_op_symbol
= (symbolS
*) 0;
2858 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2859 (if any) based on i.tm.extension_opcode. Again, we must be
2860 careful to make sure that segment/control/debug/test/MMX
2861 registers are coded into the i.rm.reg field. */
2866 & (Reg
| RegMMX
| RegXMM
2868 | Control
| Debug
| Test
))
2871 & (Reg
| RegMMX
| RegXMM
2873 | Control
| Debug
| Test
))
2876 /* If there is an extension opcode to put here, the register
2877 number must be put into the regmem field. */
2878 if (i
.tm
.extension_opcode
!= None
)
2880 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2881 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2886 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2887 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2891 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2892 must set it to 3 to indicate this is a register operand
2893 in the regmem field. */
2894 if (!i
.mem_operands
)
2898 /* Fill in i.rm.reg field with extension opcode (if any). */
2899 if (i
.tm
.extension_opcode
!= None
)
2900 i
.rm
.reg
= i
.tm
.extension_opcode
;
2911 relax_substateT subtype
;
2916 if (flag_code
== CODE_16BIT
)
2920 if (i
.prefix
[DATA_PREFIX
] != 0)
2926 /* Pentium4 branch hints. */
2927 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2928 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2933 if (i
.prefix
[REX_PREFIX
] != 0)
2939 if (i
.prefixes
!= 0 && !intel_syntax
)
2940 as_warn (_("skipping prefixes on this instruction"));
2942 /* It's always a symbol; End frag & setup for relax.
2943 Make sure there is enough room in this frag for the largest
2944 instruction we may generate in md_convert_frag. This is 2
2945 bytes for the opcode and room for the prefix and largest
2947 frag_grow (prefix
+ 2 + 4);
2948 /* Prefix and 1 opcode byte go in fr_fix. */
2949 p
= frag_more (prefix
+ 1);
2950 if (i
.prefix
[DATA_PREFIX
] != 0)
2951 *p
++ = DATA_PREFIX_OPCODE
;
2952 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2953 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2954 *p
++ = i
.prefix
[SEG_PREFIX
];
2955 if (i
.prefix
[REX_PREFIX
] != 0)
2956 *p
++ = i
.prefix
[REX_PREFIX
];
2957 *p
= i
.tm
.base_opcode
;
2959 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2960 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2961 else if ((cpu_arch_flags
& Cpu386
) != 0)
2962 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2964 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2967 sym
= i
.op
[0].disps
->X_add_symbol
;
2968 off
= i
.op
[0].disps
->X_add_number
;
2970 if (i
.op
[0].disps
->X_op
!= O_constant
2971 && i
.op
[0].disps
->X_op
!= O_symbol
)
2973 /* Handle complex expressions. */
2974 sym
= make_expr_symbol (i
.op
[0].disps
);
2978 /* 1 possible extra opcode + 4 byte displacement go in var part.
2979 Pass reloc in fr_var. */
2980 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
2989 if (i
.tm
.opcode_modifier
& JumpByte
)
2991 /* This is a loop or jecxz type instruction. */
2993 if (i
.prefix
[ADDR_PREFIX
] != 0)
2995 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2998 /* Pentium4 branch hints. */
2999 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3000 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3002 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3011 if (flag_code
== CODE_16BIT
)
3014 if (i
.prefix
[DATA_PREFIX
] != 0)
3016 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3026 if (i
.prefix
[REX_PREFIX
] != 0)
3028 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3032 if (i
.prefixes
!= 0 && !intel_syntax
)
3033 as_warn (_("skipping prefixes on this instruction"));
3035 p
= frag_more (1 + size
);
3036 *p
++ = i
.tm
.base_opcode
;
3038 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3039 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3043 output_interseg_jump ()
3051 if (flag_code
== CODE_16BIT
)
3055 if (i
.prefix
[DATA_PREFIX
] != 0)
3061 if (i
.prefix
[REX_PREFIX
] != 0)
3071 if (i
.prefixes
!= 0 && !intel_syntax
)
3072 as_warn (_("skipping prefixes on this instruction"));
3074 /* 1 opcode; 2 segment; offset */
3075 p
= frag_more (prefix
+ 1 + 2 + size
);
3077 if (i
.prefix
[DATA_PREFIX
] != 0)
3078 *p
++ = DATA_PREFIX_OPCODE
;
3080 if (i
.prefix
[REX_PREFIX
] != 0)
3081 *p
++ = i
.prefix
[REX_PREFIX
];
3083 *p
++ = i
.tm
.base_opcode
;
3084 if (i
.op
[1].imms
->X_op
== O_constant
)
3086 offsetT n
= i
.op
[1].imms
->X_add_number
;
3089 && !fits_in_unsigned_word (n
)
3090 && !fits_in_signed_word (n
))
3092 as_bad (_("16-bit jump out of range"));
3095 md_number_to_chars (p
, n
, size
);
3098 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3099 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3100 if (i
.op
[0].imms
->X_op
!= O_constant
)
3101 as_bad (_("can't handle non absolute segment in `%s'"),
3103 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3110 fragS
*insn_start_frag
;
3111 offsetT insn_start_off
;
3113 /* Tie dwarf2 debug info to the address at the start of the insn.
3114 We can't do this after the insn has been output as the current
3115 frag may have been closed off. eg. by frag_var. */
3116 dwarf2_emit_insn (0);
3118 insn_start_frag
= frag_now
;
3119 insn_start_off
= frag_now_fix ();
3122 if (i
.tm
.opcode_modifier
& Jump
)
3124 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3126 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3127 output_interseg_jump ();
3130 /* Output normal instructions here. */
3134 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3135 byte for the SSE instructions to specify a prefix they require. */
3136 if (i
.tm
.base_opcode
& 0xff0000)
3137 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3139 /* The prefix bytes. */
3141 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3147 md_number_to_chars (p
, (valueT
) *q
, 1);
3151 /* Now the opcode; be careful about word order here! */
3152 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3154 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3159 /* Put out high byte first: can't use md_number_to_chars! */
3160 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3161 *p
= i
.tm
.base_opcode
& 0xff;
3164 /* Now the modrm byte and sib byte (if present). */
3165 if (i
.tm
.opcode_modifier
& Modrm
)
3168 md_number_to_chars (p
,
3169 (valueT
) (i
.rm
.regmem
<< 0
3173 /* If i.rm.regmem == ESP (4)
3174 && i.rm.mode != (Register mode)
3176 ==> need second modrm byte. */
3177 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3179 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3182 md_number_to_chars (p
,
3183 (valueT
) (i
.sib
.base
<< 0
3185 | i
.sib
.scale
<< 6),
3190 if (i
.disp_operands
)
3191 output_disp (insn_start_frag
, insn_start_off
);
3194 output_imm (insn_start_frag
, insn_start_off
);
3202 #endif /* DEBUG386 */
3206 output_disp (insn_start_frag
, insn_start_off
)
3207 fragS
*insn_start_frag
;
3208 offsetT insn_start_off
;
3213 for (n
= 0; n
< i
.operands
; n
++)
3215 if (i
.types
[n
] & Disp
)
3217 if (i
.op
[n
].disps
->X_op
== O_constant
)
3223 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3226 if (i
.types
[n
] & Disp8
)
3228 if (i
.types
[n
] & Disp64
)
3231 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3233 p
= frag_more (size
);
3234 md_number_to_chars (p
, val
, size
);
3238 RELOC_ENUM reloc_type
;
3241 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3243 /* The PC relative address is computed relative
3244 to the instruction boundary, so in case immediate
3245 fields follows, we need to adjust the value. */
3246 if (pcrel
&& i
.imm_operands
)
3251 for (n1
= 0; n1
< i
.operands
; n1
++)
3252 if (i
.types
[n1
] & Imm
)
3254 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3257 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3259 if (i
.types
[n1
] & Imm64
)
3264 /* We should find the immediate. */
3265 if (n1
== i
.operands
)
3267 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3270 if (i
.types
[n
] & Disp32S
)
3273 if (i
.types
[n
] & (Disp16
| Disp64
))
3276 if (i
.types
[n
] & Disp64
)
3280 p
= frag_more (size
);
3281 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3282 #ifdef BFD_ASSEMBLER
3283 if (reloc_type
== BFD_RELOC_32
3285 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3286 && (i
.op
[n
].disps
->X_op
== O_symbol
3287 || (i
.op
[n
].disps
->X_op
== O_add
3288 && ((symbol_get_value_expression
3289 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3294 if (insn_start_frag
== frag_now
)
3295 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3300 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3301 for (fr
= insn_start_frag
->fr_next
;
3302 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3304 add
+= p
- frag_now
->fr_literal
;
3307 /* We don't support dynamic linking on x86-64 yet. */
3308 if (flag_code
== CODE_64BIT
)
3310 reloc_type
= BFD_RELOC_386_GOTPC
;
3311 i
.op
[n
].disps
->X_add_number
+= add
;
3314 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3315 i
.op
[n
].disps
, pcrel
, reloc_type
);
3322 output_imm (insn_start_frag
, insn_start_off
)
3323 fragS
*insn_start_frag
;
3324 offsetT insn_start_off
;
3329 for (n
= 0; n
< i
.operands
; n
++)
3331 if (i
.types
[n
] & Imm
)
3333 if (i
.op
[n
].imms
->X_op
== O_constant
)
3339 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3342 if (i
.types
[n
] & (Imm8
| Imm8S
))
3344 else if (i
.types
[n
] & Imm64
)
3347 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3349 p
= frag_more (size
);
3350 md_number_to_chars (p
, val
, size
);
3354 /* Not absolute_section.
3355 Need a 32-bit fixup (don't support 8bit
3356 non-absolute imms). Try to support other
3358 RELOC_ENUM reloc_type
;
3362 if ((i
.types
[n
] & (Imm32S
))
3363 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3365 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3368 if (i
.types
[n
] & (Imm8
| Imm8S
))
3370 if (i
.types
[n
] & Imm64
)
3374 p
= frag_more (size
);
3375 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3376 #ifdef BFD_ASSEMBLER
3377 /* This is tough to explain. We end up with this one if we
3378 * have operands that look like
3379 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3380 * obtain the absolute address of the GOT, and it is strongly
3381 * preferable from a performance point of view to avoid using
3382 * a runtime relocation for this. The actual sequence of
3383 * instructions often look something like:
3388 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3390 * The call and pop essentially return the absolute address
3391 * of the label .L66 and store it in %ebx. The linker itself
3392 * will ultimately change the first operand of the addl so
3393 * that %ebx points to the GOT, but to keep things simple, the
3394 * .o file must have this operand set so that it generates not
3395 * the absolute address of .L66, but the absolute address of
3396 * itself. This allows the linker itself simply treat a GOTPC
3397 * relocation as asking for a pcrel offset to the GOT to be
3398 * added in, and the addend of the relocation is stored in the
3399 * operand field for the instruction itself.
3401 * Our job here is to fix the operand so that it would add
3402 * the correct offset so that %ebx would point to itself. The
3403 * thing that is tricky is that .-.L66 will point to the
3404 * beginning of the instruction, so we need to further modify
3405 * the operand so that it will point to itself. There are
3406 * other cases where you have something like:
3408 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3410 * and here no correction would be required. Internally in
3411 * the assembler we treat operands of this form as not being
3412 * pcrel since the '.' is explicitly mentioned, and I wonder
3413 * whether it would simplify matters to do it this way. Who
3414 * knows. In earlier versions of the PIC patches, the
3415 * pcrel_adjust field was used to store the correction, but
3416 * since the expression is not pcrel, I felt it would be
3417 * confusing to do it this way. */
3419 if (reloc_type
== BFD_RELOC_32
3421 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3422 && (i
.op
[n
].imms
->X_op
== O_symbol
3423 || (i
.op
[n
].imms
->X_op
== O_add
3424 && ((symbol_get_value_expression
3425 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3430 if (insn_start_frag
== frag_now
)
3431 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3436 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3437 for (fr
= insn_start_frag
->fr_next
;
3438 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3440 add
+= p
- frag_now
->fr_literal
;
3443 /* We don't support dynamic linking on x86-64 yet. */
3444 if (flag_code
== CODE_64BIT
)
3446 reloc_type
= BFD_RELOC_386_GOTPC
;
3447 i
.op
[n
].imms
->X_add_number
+= add
;
3450 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3451 i
.op
[n
].imms
, 0, reloc_type
);
3458 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3460 /* Parse operands of the form
3461 <symbol>@GOTOFF+<nnn>
3462 and similar .plt or .got references.
3464 If we find one, set up the correct relocation in RELOC and copy the
3465 input string, minus the `@GOTOFF' into a malloc'd buffer for
3466 parsing by the calling routine. Return this buffer, and if ADJUST
3467 is non-null set it to the length of the string we removed from the
3468 input line. Otherwise return NULL. */
3470 lex_got (reloc
, adjust
)
3474 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3475 static const struct {
3477 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3479 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3480 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3481 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3482 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, 0 } },
3483 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3484 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, 0 } },
3485 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, 0 } },
3486 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3487 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, 0 } },
3488 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3493 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3494 if (is_end_of_line
[(unsigned char) *cp
])
3497 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3501 len
= strlen (gotrel
[j
].str
);
3502 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3504 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3507 char *tmpbuf
, *past_reloc
;
3509 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3513 if (GOT_symbol
== NULL
)
3514 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3516 /* Replace the relocation token with ' ', so that
3517 errors like foo@GOTOFF1 will be detected. */
3519 /* The length of the first part of our input line. */
3520 first
= cp
- input_line_pointer
;
3522 /* The second part goes from after the reloc token until
3523 (and including) an end_of_line char. Don't use strlen
3524 here as the end_of_line char may not be a NUL. */
3525 past_reloc
= cp
+ 1 + len
;
3526 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3528 second
= cp
- past_reloc
;
3530 /* Allocate and copy string. The trailing NUL shouldn't
3531 be necessary, but be safe. */
3532 tmpbuf
= xmalloc (first
+ second
+ 2);
3533 memcpy (tmpbuf
, input_line_pointer
, first
);
3534 tmpbuf
[first
] = ' ';
3535 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3536 tmpbuf
[first
+ second
+ 1] = '\0';
3540 as_bad (_("@%s reloc is not supported in %s bit mode"),
3541 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3546 /* Might be a symbol version string. Don't as_bad here. */
3550 /* x86_cons_fix_new is called via the expression parsing code when a
3551 reloc is needed. We use this hook to get the correct .got reloc. */
3552 static RELOC_ENUM got_reloc
= NO_RELOC
;
3555 x86_cons_fix_new (frag
, off
, len
, exp
)
3561 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3562 got_reloc
= NO_RELOC
;
3563 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3567 x86_cons (exp
, size
)
3573 /* Handle @GOTOFF and the like in an expression. */
3575 char *gotfree_input_line
;
3578 save
= input_line_pointer
;
3579 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3580 if (gotfree_input_line
)
3581 input_line_pointer
= gotfree_input_line
;
3585 if (gotfree_input_line
)
3587 /* expression () has merrily parsed up to the end of line,
3588 or a comma - in the wrong buffer. Transfer how far
3589 input_line_pointer has moved to the right buffer. */
3590 input_line_pointer
= (save
3591 + (input_line_pointer
- gotfree_input_line
)
3593 free (gotfree_input_line
);
3601 static int i386_immediate
PARAMS ((char *));
3604 i386_immediate (imm_start
)
3607 char *save_input_line_pointer
;
3609 char *gotfree_input_line
;
3614 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3616 as_bad (_("only 1 or 2 immediate operands are allowed"));
3620 exp
= &im_expressions
[i
.imm_operands
++];
3621 i
.op
[this_operand
].imms
= exp
;
3623 if (is_space_char (*imm_start
))
3626 save_input_line_pointer
= input_line_pointer
;
3627 input_line_pointer
= imm_start
;
3630 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3631 if (gotfree_input_line
)
3632 input_line_pointer
= gotfree_input_line
;
3635 exp_seg
= expression (exp
);
3638 if (*input_line_pointer
)
3639 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3641 input_line_pointer
= save_input_line_pointer
;
3643 if (gotfree_input_line
)
3644 free (gotfree_input_line
);
3647 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3649 /* Missing or bad expr becomes absolute 0. */
3650 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3652 exp
->X_op
= O_constant
;
3653 exp
->X_add_number
= 0;
3654 exp
->X_add_symbol
= (symbolS
*) 0;
3655 exp
->X_op_symbol
= (symbolS
*) 0;
3657 else if (exp
->X_op
== O_constant
)
3659 /* Size it properly later. */
3660 i
.types
[this_operand
] |= Imm64
;
3661 /* If BFD64, sign extend val. */
3662 if (!use_rela_relocations
)
3663 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3664 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3666 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3668 #ifdef BFD_ASSEMBLER
3669 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3671 && exp_seg
!= absolute_section
3672 && exp_seg
!= text_section
3673 && exp_seg
!= data_section
3674 && exp_seg
!= bss_section
3675 && exp_seg
!= undefined_section
3676 #ifdef BFD_ASSEMBLER
3677 && !bfd_is_com_section (exp_seg
)
3681 #ifdef BFD_ASSEMBLER
3682 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3684 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3691 /* This is an address. The size of the address will be
3692 determined later, depending on destination register,
3693 suffix, or the default for the section. */
3694 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3700 static char *i386_scale
PARAMS ((char *));
3707 char *save
= input_line_pointer
;
3709 input_line_pointer
= scale
;
3710 val
= get_absolute_expression ();
3716 i
.log2_scale_factor
= 0;
3719 i
.log2_scale_factor
= 1;
3722 i
.log2_scale_factor
= 2;
3725 i
.log2_scale_factor
= 3;
3728 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3730 input_line_pointer
= save
;
3733 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3735 as_warn (_("scale factor of %d without an index register"),
3736 1 << i
.log2_scale_factor
);
3737 #if SCALE1_WHEN_NO_INDEX
3738 i
.log2_scale_factor
= 0;
3741 scale
= input_line_pointer
;
3742 input_line_pointer
= save
;
3746 static int i386_displacement
PARAMS ((char *, char *));
3749 i386_displacement (disp_start
, disp_end
)
3755 char *save_input_line_pointer
;
3757 char *gotfree_input_line
;
3759 int bigdisp
= Disp32
;
3761 if (flag_code
== CODE_64BIT
)
3763 if (i
.prefix
[ADDR_PREFIX
] == 0)
3766 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3768 i
.types
[this_operand
] |= bigdisp
;
3770 exp
= &disp_expressions
[i
.disp_operands
];
3771 i
.op
[this_operand
].disps
= exp
;
3773 save_input_line_pointer
= input_line_pointer
;
3774 input_line_pointer
= disp_start
;
3775 END_STRING_AND_SAVE (disp_end
);
3777 #ifndef GCC_ASM_O_HACK
3778 #define GCC_ASM_O_HACK 0
3781 END_STRING_AND_SAVE (disp_end
+ 1);
3782 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3783 && displacement_string_end
[-1] == '+')
3785 /* This hack is to avoid a warning when using the "o"
3786 constraint within gcc asm statements.
3789 #define _set_tssldt_desc(n,addr,limit,type) \
3790 __asm__ __volatile__ ( \
3792 "movw %w1,2+%0\n\t" \
3794 "movb %b1,4+%0\n\t" \
3795 "movb %4,5+%0\n\t" \
3796 "movb $0,6+%0\n\t" \
3797 "movb %h1,7+%0\n\t" \
3799 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3801 This works great except that the output assembler ends
3802 up looking a bit weird if it turns out that there is
3803 no offset. You end up producing code that looks like:
3816 So here we provide the missing zero. */
3818 *displacement_string_end
= '0';
3822 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3823 if (gotfree_input_line
)
3824 input_line_pointer
= gotfree_input_line
;
3827 exp_seg
= expression (exp
);
3830 if (*input_line_pointer
)
3831 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3833 RESTORE_END_STRING (disp_end
+ 1);
3835 RESTORE_END_STRING (disp_end
);
3836 input_line_pointer
= save_input_line_pointer
;
3838 if (gotfree_input_line
)
3839 free (gotfree_input_line
);
3842 #ifdef BFD_ASSEMBLER
3843 /* We do this to make sure that the section symbol is in
3844 the symbol table. We will ultimately change the relocation
3845 to be relative to the beginning of the section. */
3846 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3847 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3849 if (exp
->X_op
!= O_symbol
)
3851 as_bad (_("bad expression used with @%s"),
3852 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3858 if (S_IS_LOCAL (exp
->X_add_symbol
)
3859 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3860 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3861 exp
->X_op
= O_subtract
;
3862 exp
->X_op_symbol
= GOT_symbol
;
3863 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3864 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3866 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3870 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3872 /* Missing or bad expr becomes absolute 0. */
3873 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3875 exp
->X_op
= O_constant
;
3876 exp
->X_add_number
= 0;
3877 exp
->X_add_symbol
= (symbolS
*) 0;
3878 exp
->X_op_symbol
= (symbolS
*) 0;
3881 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3882 if (exp
->X_op
!= O_constant
3883 #ifdef BFD_ASSEMBLER
3884 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3886 && exp_seg
!= absolute_section
3887 && exp_seg
!= text_section
3888 && exp_seg
!= data_section
3889 && exp_seg
!= bss_section
3890 && exp_seg
!= undefined_section
3891 #ifdef BFD_ASSEMBLER
3892 && !bfd_is_com_section (exp_seg
)
3896 #ifdef BFD_ASSEMBLER
3897 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3899 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3904 else if (flag_code
== CODE_64BIT
)
3905 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3909 static int i386_index_check
PARAMS ((const char *));
3911 /* Make sure the memory operand we've been dealt is valid.
3912 Return 1 on success, 0 on a failure. */
3915 i386_index_check (operand_string
)
3916 const char *operand_string
;
3919 #if INFER_ADDR_PREFIX
3925 if (flag_code
== CODE_64BIT
)
3927 if (i
.prefix
[ADDR_PREFIX
] == 0)
3931 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3932 && (i
.base_reg
->reg_type
!= BaseIndex
3935 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3936 != (Reg64
| BaseIndex
))))
3943 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3945 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3946 != (Reg32
| BaseIndex
))))
3952 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3956 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3957 != (Reg16
| BaseIndex
)))
3959 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3960 != (Reg16
| BaseIndex
))
3962 && i
.base_reg
->reg_num
< 6
3963 && i
.index_reg
->reg_num
>= 6
3964 && i
.log2_scale_factor
== 0))))
3971 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3973 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3974 != (Reg32
| BaseIndex
))))
3980 #if INFER_ADDR_PREFIX
3981 if (flag_code
!= CODE_64BIT
3982 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3984 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3986 /* Change the size of any displacement too. At most one of
3987 Disp16 or Disp32 is set.
3988 FIXME. There doesn't seem to be any real need for separate
3989 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3990 Removing them would probably clean up the code quite a lot. */
3991 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
3992 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
3997 as_bad (_("`%s' is not a valid base/index expression"),
4001 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4003 flag_code_names
[flag_code
]);
4009 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4013 i386_operand (operand_string
)
4014 char *operand_string
;
4018 char *op_string
= operand_string
;
4020 if (is_space_char (*op_string
))
4023 /* We check for an absolute prefix (differentiating,
4024 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4025 if (*op_string
== ABSOLUTE_PREFIX
)
4028 if (is_space_char (*op_string
))
4030 i
.types
[this_operand
] |= JumpAbsolute
;
4033 /* Check if operand is a register. */
4034 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4035 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4037 /* Check for a segment override by searching for ':' after a
4038 segment register. */
4040 if (is_space_char (*op_string
))
4042 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4047 i
.seg
[i
.mem_operands
] = &es
;
4050 i
.seg
[i
.mem_operands
] = &cs
;
4053 i
.seg
[i
.mem_operands
] = &ss
;
4056 i
.seg
[i
.mem_operands
] = &ds
;
4059 i
.seg
[i
.mem_operands
] = &fs
;
4062 i
.seg
[i
.mem_operands
] = &gs
;
4066 /* Skip the ':' and whitespace. */
4068 if (is_space_char (*op_string
))
4071 if (!is_digit_char (*op_string
)
4072 && !is_identifier_char (*op_string
)
4073 && *op_string
!= '('
4074 && *op_string
!= ABSOLUTE_PREFIX
)
4076 as_bad (_("bad memory operand `%s'"), op_string
);
4079 /* Handle case of %es:*foo. */
4080 if (*op_string
== ABSOLUTE_PREFIX
)
4083 if (is_space_char (*op_string
))
4085 i
.types
[this_operand
] |= JumpAbsolute
;
4087 goto do_memory_reference
;
4091 as_bad (_("junk `%s' after register"), op_string
);
4094 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4095 i
.op
[this_operand
].regs
= r
;
4098 else if (*op_string
== REGISTER_PREFIX
)
4100 as_bad (_("bad register name `%s'"), op_string
);
4103 else if (*op_string
== IMMEDIATE_PREFIX
)
4106 if (i
.types
[this_operand
] & JumpAbsolute
)
4108 as_bad (_("immediate operand illegal with absolute jump"));
4111 if (!i386_immediate (op_string
))
4114 else if (is_digit_char (*op_string
)
4115 || is_identifier_char (*op_string
)
4116 || *op_string
== '(')
4118 /* This is a memory reference of some sort. */
4121 /* Start and end of displacement string expression (if found). */
4122 char *displacement_string_start
;
4123 char *displacement_string_end
;
4125 do_memory_reference
:
4126 if ((i
.mem_operands
== 1
4127 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4128 || i
.mem_operands
== 2)
4130 as_bad (_("too many memory references for `%s'"),
4131 current_templates
->start
->name
);
4135 /* Check for base index form. We detect the base index form by
4136 looking for an ')' at the end of the operand, searching
4137 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4139 base_string
= op_string
+ strlen (op_string
);
4142 if (is_space_char (*base_string
))
4145 /* If we only have a displacement, set-up for it to be parsed later. */
4146 displacement_string_start
= op_string
;
4147 displacement_string_end
= base_string
+ 1;
4149 if (*base_string
== ')')
4152 unsigned int parens_balanced
= 1;
4153 /* We've already checked that the number of left & right ()'s are
4154 equal, so this loop will not be infinite. */
4158 if (*base_string
== ')')
4160 if (*base_string
== '(')
4163 while (parens_balanced
);
4165 temp_string
= base_string
;
4167 /* Skip past '(' and whitespace. */
4169 if (is_space_char (*base_string
))
4172 if (*base_string
== ','
4173 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4174 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4176 displacement_string_end
= temp_string
;
4178 i
.types
[this_operand
] |= BaseIndex
;
4182 base_string
= end_op
;
4183 if (is_space_char (*base_string
))
4187 /* There may be an index reg or scale factor here. */
4188 if (*base_string
== ',')
4191 if (is_space_char (*base_string
))
4194 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4195 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4197 base_string
= end_op
;
4198 if (is_space_char (*base_string
))
4200 if (*base_string
== ',')
4203 if (is_space_char (*base_string
))
4206 else if (*base_string
!= ')')
4208 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4213 else if (*base_string
== REGISTER_PREFIX
)
4215 as_bad (_("bad register name `%s'"), base_string
);
4219 /* Check for scale factor. */
4220 if (*base_string
!= ')')
4222 char *end_scale
= i386_scale (base_string
);
4227 base_string
= end_scale
;
4228 if (is_space_char (*base_string
))
4230 if (*base_string
!= ')')
4232 as_bad (_("expecting `)' after scale factor in `%s'"),
4237 else if (!i
.index_reg
)
4239 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4244 else if (*base_string
!= ')')
4246 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4251 else if (*base_string
== REGISTER_PREFIX
)
4253 as_bad (_("bad register name `%s'"), base_string
);
4258 /* If there's an expression beginning the operand, parse it,
4259 assuming displacement_string_start and
4260 displacement_string_end are meaningful. */
4261 if (displacement_string_start
!= displacement_string_end
)
4263 if (!i386_displacement (displacement_string_start
,
4264 displacement_string_end
))
4268 /* Special case for (%dx) while doing input/output op. */
4270 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4272 && i
.log2_scale_factor
== 0
4273 && i
.seg
[i
.mem_operands
] == 0
4274 && (i
.types
[this_operand
] & Disp
) == 0)
4276 i
.types
[this_operand
] = InOutPortReg
;
4280 if (i386_index_check (operand_string
) == 0)
4286 /* It's not a memory operand; argh! */
4287 as_bad (_("invalid char %s beginning operand %d `%s'"),
4288 output_invalid (*op_string
),
4293 return 1; /* Normal return. */
4296 /* md_estimate_size_before_relax()
4298 Called just before relax() for rs_machine_dependent frags. The x86
4299 assembler uses these frags to handle variable size jump
4302 Any symbol that is now undefined will not become defined.
4303 Return the correct fr_subtype in the frag.
4304 Return the initial "guess for variable size of frag" to caller.
4305 The guess is actually the growth beyond the fixed part. Whatever
4306 we do to grow the fixed or variable part contributes to our
4310 md_estimate_size_before_relax (fragP
, segment
)
4314 /* We've already got fragP->fr_subtype right; all we have to do is
4315 check for un-relaxable symbols. On an ELF system, we can't relax
4316 an externally visible symbol, because it may be overridden by a
4318 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4319 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4320 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4321 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4322 || S_IS_WEAK (fragP
->fr_symbol
)))
4326 /* Symbol is undefined in this segment, or we need to keep a
4327 reloc so that weak symbols can be overridden. */
4328 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4329 RELOC_ENUM reloc_type
;
4330 unsigned char *opcode
;
4333 if (fragP
->fr_var
!= NO_RELOC
)
4334 reloc_type
= fragP
->fr_var
;
4336 reloc_type
= BFD_RELOC_16_PCREL
;
4338 reloc_type
= BFD_RELOC_32_PCREL
;
4340 old_fr_fix
= fragP
->fr_fix
;
4341 opcode
= (unsigned char *) fragP
->fr_opcode
;
4343 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4346 /* Make jmp (0xeb) a (d)word displacement jump. */
4348 fragP
->fr_fix
+= size
;
4349 fix_new (fragP
, old_fr_fix
, size
,
4351 fragP
->fr_offset
, 1,
4357 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4359 /* Negate the condition, and branch past an
4360 unconditional jump. */
4363 /* Insert an unconditional jump. */
4365 /* We added two extra opcode bytes, and have a two byte
4367 fragP
->fr_fix
+= 2 + 2;
4368 fix_new (fragP
, old_fr_fix
+ 2, 2,
4370 fragP
->fr_offset
, 1,
4377 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4380 fix_new (fragP
, old_fr_fix
, 1,
4382 fragP
->fr_offset
, 1,
4387 /* This changes the byte-displacement jump 0x7N
4388 to the (d)word-displacement jump 0x0f,0x8N. */
4389 opcode
[1] = opcode
[0] + 0x10;
4390 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4391 /* We've added an opcode byte. */
4392 fragP
->fr_fix
+= 1 + size
;
4393 fix_new (fragP
, old_fr_fix
+ 1, size
,
4395 fragP
->fr_offset
, 1,
4400 BAD_CASE (fragP
->fr_subtype
);
4404 return fragP
->fr_fix
- old_fr_fix
;
4407 /* Guess size depending on current relax state. Initially the relax
4408 state will correspond to a short jump and we return 1, because
4409 the variable part of the frag (the branch offset) is one byte
4410 long. However, we can relax a section more than once and in that
4411 case we must either set fr_subtype back to the unrelaxed state,
4412 or return the value for the appropriate branch. */
4413 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4416 /* Called after relax() is finished.
4418 In: Address of frag.
4419 fr_type == rs_machine_dependent.
4420 fr_subtype is what the address relaxed to.
4422 Out: Any fixSs and constants are set up.
4423 Caller will turn frag into a ".space 0". */
4425 #ifndef BFD_ASSEMBLER
4427 md_convert_frag (headers
, sec
, fragP
)
4428 object_headers
*headers ATTRIBUTE_UNUSED
;
4429 segT sec ATTRIBUTE_UNUSED
;
4433 md_convert_frag (abfd
, sec
, fragP
)
4434 bfd
*abfd ATTRIBUTE_UNUSED
;
4435 segT sec ATTRIBUTE_UNUSED
;
4439 unsigned char *opcode
;
4440 unsigned char *where_to_put_displacement
= NULL
;
4441 offsetT target_address
;
4442 offsetT opcode_address
;
4443 unsigned int extension
= 0;
4444 offsetT displacement_from_opcode_start
;
4446 opcode
= (unsigned char *) fragP
->fr_opcode
;
4448 /* Address we want to reach in file space. */
4449 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4451 /* Address opcode resides at in file space. */
4452 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4454 /* Displacement from opcode start to fill into instruction. */
4455 displacement_from_opcode_start
= target_address
- opcode_address
;
4457 if ((fragP
->fr_subtype
& BIG
) == 0)
4459 /* Don't have to change opcode. */
4460 extension
= 1; /* 1 opcode + 1 displacement */
4461 where_to_put_displacement
= &opcode
[1];
4465 if (no_cond_jump_promotion
4466 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4467 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4469 switch (fragP
->fr_subtype
)
4471 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4472 extension
= 4; /* 1 opcode + 4 displacement */
4474 where_to_put_displacement
= &opcode
[1];
4477 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4478 extension
= 2; /* 1 opcode + 2 displacement */
4480 where_to_put_displacement
= &opcode
[1];
4483 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4484 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4485 extension
= 5; /* 2 opcode + 4 displacement */
4486 opcode
[1] = opcode
[0] + 0x10;
4487 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4488 where_to_put_displacement
= &opcode
[2];
4491 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4492 extension
= 3; /* 2 opcode + 2 displacement */
4493 opcode
[1] = opcode
[0] + 0x10;
4494 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4495 where_to_put_displacement
= &opcode
[2];
4498 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4503 where_to_put_displacement
= &opcode
[3];
4507 BAD_CASE (fragP
->fr_subtype
);
4512 /* Now put displacement after opcode. */
4513 md_number_to_chars ((char *) where_to_put_displacement
,
4514 (valueT
) (displacement_from_opcode_start
- extension
),
4515 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4516 fragP
->fr_fix
+= extension
;
4519 /* Size of byte displacement jmp. */
4520 int md_short_jump_size
= 2;
4522 /* Size of dword displacement jmp. */
4523 int md_long_jump_size
= 5;
4525 /* Size of relocation record. */
4526 const int md_reloc_size
= 8;
4529 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4531 addressT from_addr
, to_addr
;
4532 fragS
*frag ATTRIBUTE_UNUSED
;
4533 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4537 offset
= to_addr
- (from_addr
+ 2);
4538 /* Opcode for byte-disp jump. */
4539 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4540 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4544 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4546 addressT from_addr
, to_addr
;
4547 fragS
*frag ATTRIBUTE_UNUSED
;
4548 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4552 offset
= to_addr
- (from_addr
+ 5);
4553 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4554 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4557 /* Apply a fixup (fixS) to segment data, once it has been determined
4558 by our caller that we have all the info we need to fix it up.
4560 On the 386, immediates, displacements, and data pointers are all in
4561 the same (little-endian) format, so we don't need to care about which
4565 md_apply_fix3 (fixP
, valP
, seg
)
4566 /* The fix we're to put in. */
4568 /* Pointer to the value of the bits. */
4570 /* Segment fix is from. */
4571 segT seg ATTRIBUTE_UNUSED
;
4573 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4574 valueT value
= *valP
;
4576 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4579 switch (fixP
->fx_r_type
)
4585 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4588 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4591 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4596 if (fixP
->fx_addsy
!= NULL
4597 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4598 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4599 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4600 && !use_rela_relocations
)
4602 /* This is a hack. There should be a better way to handle this.
4603 This covers for the fact that bfd_install_relocation will
4604 subtract the current location (for partial_inplace, PC relative
4605 relocations); see more below. */
4607 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4609 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4612 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4614 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4615 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4617 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4620 || (symbol_section_p (fixP
->fx_addsy
)
4621 && fseg
!= absolute_section
))
4622 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
4623 && !S_IS_WEAK (fixP
->fx_addsy
)
4624 && S_IS_DEFINED (fixP
->fx_addsy
)
4625 && !S_IS_COMMON (fixP
->fx_addsy
))
4627 /* Yes, we add the values in twice. This is because
4628 bfd_perform_relocation subtracts them out again. I think
4629 bfd_perform_relocation is broken, but I don't dare change
4631 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4635 #if defined (OBJ_COFF) && defined (TE_PE)
4636 /* For some reason, the PE format does not store a section
4637 address offset for a PC relative symbol. */
4638 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4639 value
+= md_pcrel_from (fixP
);
4643 /* Fix a few things - the dynamic linker expects certain values here,
4644 and we must not dissappoint it. */
4645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4646 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4648 switch (fixP
->fx_r_type
)
4650 case BFD_RELOC_386_PLT32
:
4651 case BFD_RELOC_X86_64_PLT32
:
4652 /* Make the jump instruction point to the address of the operand. At
4653 runtime we merely add the offset to the actual PLT entry. */
4657 case BFD_RELOC_386_GOT32
:
4658 case BFD_RELOC_386_TLS_GD
:
4659 case BFD_RELOC_386_TLS_LDM
:
4660 case BFD_RELOC_386_TLS_IE_32
:
4661 case BFD_RELOC_X86_64_GOT32
:
4662 value
= 0; /* Fully resolved at runtime. No addend. */
4665 case BFD_RELOC_VTABLE_INHERIT
:
4666 case BFD_RELOC_VTABLE_ENTRY
:
4673 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4675 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4677 /* Are we finished with this relocation now? */
4678 if (fixP
->fx_addsy
== NULL
)
4680 #ifdef BFD_ASSEMBLER
4681 else if (use_rela_relocations
)
4683 fixP
->fx_no_overflow
= 1;
4684 /* Remember value for tc_gen_reloc. */
4685 fixP
->fx_addnumber
= value
;
4689 md_number_to_chars (p
, value
, fixP
->fx_size
);
4692 #define MAX_LITTLENUMS 6
4694 /* Turn the string pointed to by litP into a floating point constant
4695 of type TYPE, and emit the appropriate bytes. The number of
4696 LITTLENUMS emitted is stored in *SIZEP. An error message is
4697 returned, or NULL on OK. */
4700 md_atof (type
, litP
, sizeP
)
4706 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4707 LITTLENUM_TYPE
*wordP
;
4729 return _("Bad call to md_atof ()");
4731 t
= atof_ieee (input_line_pointer
, type
, words
);
4733 input_line_pointer
= t
;
4735 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4736 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4737 the bigendian 386. */
4738 for (wordP
= words
+ prec
- 1; prec
--;)
4740 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4741 litP
+= sizeof (LITTLENUM_TYPE
);
4746 char output_invalid_buf
[8];
4753 sprintf (output_invalid_buf
, "'%c'", c
);
4755 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4756 return output_invalid_buf
;
4759 /* REG_STRING starts *before* REGISTER_PREFIX. */
4761 static const reg_entry
*
4762 parse_register (reg_string
, end_op
)
4766 char *s
= reg_string
;
4768 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4771 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4772 if (*s
== REGISTER_PREFIX
)
4775 if (is_space_char (*s
))
4779 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4781 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4782 return (const reg_entry
*) NULL
;
4786 /* For naked regs, make sure that we are not dealing with an identifier.
4787 This prevents confusing an identifier like `eax_var' with register
4789 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4790 return (const reg_entry
*) NULL
;
4794 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4796 /* Handle floating point regs, allowing spaces in the (i) part. */
4797 if (r
== i386_regtab
/* %st is first entry of table */)
4799 if (is_space_char (*s
))
4804 if (is_space_char (*s
))
4806 if (*s
>= '0' && *s
<= '7')
4808 r
= &i386_float_regtab
[*s
- '0'];
4810 if (is_space_char (*s
))
4818 /* We have "%st(" then garbage. */
4819 return (const reg_entry
*) NULL
;
4824 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4825 && flag_code
!= CODE_64BIT
)
4827 return (const reg_entry
*) NULL
;
4833 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4834 const char *md_shortopts
= "kVQ:sq";
4836 const char *md_shortopts
= "q";
4839 struct option md_longopts
[] = {
4840 #define OPTION_32 (OPTION_MD_BASE + 0)
4841 {"32", no_argument
, NULL
, OPTION_32
},
4842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4843 #define OPTION_64 (OPTION_MD_BASE + 1)
4844 {"64", no_argument
, NULL
, OPTION_64
},
4846 {NULL
, no_argument
, NULL
, 0}
4848 size_t md_longopts_size
= sizeof (md_longopts
);
4851 md_parse_option (c
, arg
)
4853 char *arg ATTRIBUTE_UNUSED
;
4861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4862 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4863 should be emitted or not. FIXME: Not implemented. */
4867 /* -V: SVR4 argument to print version ID. */
4869 print_version_id ();
4872 /* -k: Ignore for FreeBSD compatibility. */
4877 /* -s: On i386 Solaris, this tells the native assembler to use
4878 .stab instead of .stab.excl. We always use .stab anyhow. */
4883 const char **list
, **l
;
4885 list
= bfd_target_list ();
4886 for (l
= list
; *l
!= NULL
; l
++)
4887 if (strcmp (*l
, "elf64-x86-64") == 0)
4889 default_arch
= "x86_64";
4893 as_fatal (_("No compiled in support for x86_64"));
4900 default_arch
= "i386";
4910 md_show_usage (stream
)
4913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4914 fprintf (stream
, _("\
4916 -V print assembler version number\n\
4918 -q quieten some warnings\n\
4921 fprintf (stream
, _("\
4922 -q quieten some warnings\n"));
4926 #ifdef BFD_ASSEMBLER
4927 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4928 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4930 /* Pick the target format to use. */
4933 i386_target_format ()
4935 if (!strcmp (default_arch
, "x86_64"))
4936 set_code_flag (CODE_64BIT
);
4937 else if (!strcmp (default_arch
, "i386"))
4938 set_code_flag (CODE_32BIT
);
4940 as_fatal (_("Unknown architecture"));
4941 switch (OUTPUT_FLAVOR
)
4943 #ifdef OBJ_MAYBE_AOUT
4944 case bfd_target_aout_flavour
:
4945 return AOUT_TARGET_FORMAT
;
4947 #ifdef OBJ_MAYBE_COFF
4948 case bfd_target_coff_flavour
:
4951 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4952 case bfd_target_elf_flavour
:
4954 if (flag_code
== CODE_64BIT
)
4955 use_rela_relocations
= 1;
4956 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
4965 #endif /* OBJ_MAYBE_ more than one */
4967 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4968 void i386_elf_emit_arch_note ()
4970 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4971 && cpu_arch_name
!= NULL
)
4974 asection
*seg
= now_seg
;
4975 subsegT subseg
= now_subseg
;
4976 Elf_Internal_Note i_note
;
4977 Elf_External_Note e_note
;
4978 asection
*note_secp
;
4981 /* Create the .note section. */
4982 note_secp
= subseg_new (".note", 0);
4983 bfd_set_section_flags (stdoutput
,
4985 SEC_HAS_CONTENTS
| SEC_READONLY
);
4987 /* Process the arch string. */
4988 len
= strlen (cpu_arch_name
);
4990 i_note
.namesz
= len
+ 1;
4992 i_note
.type
= NT_ARCH
;
4993 p
= frag_more (sizeof (e_note
.namesz
));
4994 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
4995 p
= frag_more (sizeof (e_note
.descsz
));
4996 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
4997 p
= frag_more (sizeof (e_note
.type
));
4998 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
4999 p
= frag_more (len
+ 1);
5000 strcpy (p
, cpu_arch_name
);
5002 frag_align (2, 0, 0);
5004 subseg_set (seg
, subseg
);
5008 #endif /* BFD_ASSEMBLER */
5011 md_undefined_symbol (name
)
5014 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5015 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5016 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5017 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5021 if (symbol_find (name
))
5022 as_bad (_("GOT already in symbol table"));
5023 GOT_symbol
= symbol_new (name
, undefined_section
,
5024 (valueT
) 0, &zero_address_frag
);
5031 /* Round up a section size to the appropriate boundary. */
5034 md_section_align (segment
, size
)
5035 segT segment ATTRIBUTE_UNUSED
;
5038 #ifdef BFD_ASSEMBLER
5039 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5040 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5042 /* For a.out, force the section size to be aligned. If we don't do
5043 this, BFD will align it for us, but it will not write out the
5044 final bytes of the section. This may be a bug in BFD, but it is
5045 easier to fix it here since that is how the other a.out targets
5049 align
= bfd_get_section_alignment (stdoutput
, segment
);
5050 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5058 /* On the i386, PC-relative offsets are relative to the start of the
5059 next instruction. That is, the address of the offset, plus its
5060 size, since the offset is always the last part of the insn. */
5063 md_pcrel_from (fixP
)
5066 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5073 int ignore ATTRIBUTE_UNUSED
;
5077 temp
= get_absolute_expression ();
5078 subseg_set (bss_section
, (subsegT
) temp
);
5079 demand_empty_rest_of_line ();
5084 #ifdef BFD_ASSEMBLER
5087 i386_validate_fix (fixp
)
5090 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5092 /* GOTOFF relocation are nonsense in 64bit mode. */
5093 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5095 if (flag_code
!= CODE_64BIT
)
5097 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5101 if (flag_code
== CODE_64BIT
)
5103 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5110 i386_force_relocation (fixp
)
5113 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5114 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5117 return S_FORCE_RELOC (fixp
->fx_addsy
);
5121 tc_gen_reloc (section
, fixp
)
5122 asection
*section ATTRIBUTE_UNUSED
;
5126 bfd_reloc_code_real_type code
;
5128 switch (fixp
->fx_r_type
)
5130 case BFD_RELOC_X86_64_PLT32
:
5131 case BFD_RELOC_X86_64_GOT32
:
5132 case BFD_RELOC_X86_64_GOTPCREL
:
5133 case BFD_RELOC_386_PLT32
:
5134 case BFD_RELOC_386_GOT32
:
5135 case BFD_RELOC_386_GOTOFF
:
5136 case BFD_RELOC_386_GOTPC
:
5137 case BFD_RELOC_386_TLS_GD
:
5138 case BFD_RELOC_386_TLS_LDM
:
5139 case BFD_RELOC_386_TLS_LDO_32
:
5140 case BFD_RELOC_386_TLS_IE_32
:
5141 case BFD_RELOC_386_TLS_LE_32
:
5142 case BFD_RELOC_386_TLS_LE
:
5143 case BFD_RELOC_X86_64_32S
:
5145 case BFD_RELOC_VTABLE_ENTRY
:
5146 case BFD_RELOC_VTABLE_INHERIT
:
5147 code
= fixp
->fx_r_type
;
5152 switch (fixp
->fx_size
)
5155 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5156 _("can not do %d byte pc-relative relocation"),
5158 code
= BFD_RELOC_32_PCREL
;
5160 case 1: code
= BFD_RELOC_8_PCREL
; break;
5161 case 2: code
= BFD_RELOC_16_PCREL
; break;
5162 case 4: code
= BFD_RELOC_32_PCREL
; break;
5167 switch (fixp
->fx_size
)
5170 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5171 _("can not do %d byte relocation"),
5173 code
= BFD_RELOC_32
;
5175 case 1: code
= BFD_RELOC_8
; break;
5176 case 2: code
= BFD_RELOC_16
; break;
5177 case 4: code
= BFD_RELOC_32
; break;
5179 case 8: code
= BFD_RELOC_64
; break;
5186 if (code
== BFD_RELOC_32
5188 && fixp
->fx_addsy
== GOT_symbol
)
5190 /* We don't support GOTPC on 64bit targets. */
5191 if (flag_code
== CODE_64BIT
)
5193 code
= BFD_RELOC_386_GOTPC
;
5196 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5197 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5198 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5200 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5201 if (!use_rela_relocations
)
5203 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5204 vtable entry to be used in the relocation's section offset. */
5205 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5206 rel
->address
= fixp
->fx_offset
;
5210 /* Use the rela in 64bit mode. */
5213 if (!fixp
->fx_pcrel
)
5214 rel
->addend
= fixp
->fx_offset
;
5218 case BFD_RELOC_X86_64_PLT32
:
5219 case BFD_RELOC_X86_64_GOT32
:
5220 case BFD_RELOC_X86_64_GOTPCREL
:
5221 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5224 rel
->addend
= (section
->vma
5226 + fixp
->fx_addnumber
5227 + md_pcrel_from (fixp
));
5232 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5233 if (rel
->howto
== NULL
)
5235 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5236 _("cannot represent relocation type %s"),
5237 bfd_get_reloc_code_name (code
));
5238 /* Set howto to a garbage value so that we can keep going. */
5239 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5240 assert (rel
->howto
!= NULL
);
5246 #else /* !BFD_ASSEMBLER */
5248 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5250 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5253 relax_addressT segment_address_in_file
;
5255 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5256 Out: GNU LD relocation length code: 0, 1, or 2. */
5258 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5261 know (fixP
->fx_addsy
!= NULL
);
5263 md_number_to_chars (where
,
5264 (valueT
) (fixP
->fx_frag
->fr_address
5265 + fixP
->fx_where
- segment_address_in_file
),
5268 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5269 ? S_GET_TYPE (fixP
->fx_addsy
)
5270 : fixP
->fx_addsy
->sy_number
);
5272 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5273 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5274 where
[4] = r_symbolnum
& 0x0ff;
5275 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5276 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5277 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5280 #endif /* OBJ_AOUT or OBJ_BOUT. */
5282 #if defined (I386COFF)
5285 tc_coff_fix2rtype (fixP
)
5288 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5291 return (fixP
->fx_pcrel
?
5292 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5293 fixP
->fx_size
== 2 ? R_PCRWORD
:
5295 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5296 fixP
->fx_size
== 2 ? R_RELWORD
:
5301 tc_coff_sizemachdep (frag
)
5305 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5310 #endif /* I386COFF */
5312 #endif /* !BFD_ASSEMBLER */
5314 /* Parse operands using Intel syntax. This implements a recursive descent
5315 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5318 FIXME: We do not recognize the full operand grammar defined in the MASM
5319 documentation. In particular, all the structure/union and
5320 high-level macro operands are missing.
5322 Uppercase words are terminals, lower case words are non-terminals.
5323 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5324 bars '|' denote choices. Most grammar productions are implemented in
5325 functions called 'intel_<production>'.
5327 Initial production is 'expr'.
5333 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5335 constant digits [[ radixOverride ]]
5337 dataType BYTE | WORD | DWORD | QWORD | XWORD
5370 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5371 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5373 hexdigit a | b | c | d | e | f
5374 | A | B | C | D | E | F
5384 register specialRegister
5388 segmentRegister CS | DS | ES | FS | GS | SS
5390 specialRegister CR0 | CR2 | CR3
5391 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5392 | TR3 | TR4 | TR5 | TR6 | TR7
5394 We simplify the grammar in obvious places (e.g., register parsing is
5395 done by calling parse_register) and eliminate immediate left recursion
5396 to implement a recursive-descent parser.
5436 /* Parsing structure for the intel syntax parser. Used to implement the
5437 semantic actions for the operand grammar. */
5438 struct intel_parser_s
5440 char *op_string
; /* The string being parsed. */
5441 int got_a_float
; /* Whether the operand is a float. */
5442 int op_modifier
; /* Operand modifier. */
5443 int is_mem
; /* 1 if operand is memory reference. */
5444 const reg_entry
*reg
; /* Last register reference found. */
5445 char *disp
; /* Displacement string being built. */
5448 static struct intel_parser_s intel_parser
;
5450 /* Token structure for parsing intel syntax. */
5453 int code
; /* Token code. */
5454 const reg_entry
*reg
; /* Register entry for register tokens. */
5455 char *str
; /* String representation. */
5458 static struct intel_token cur_token
, prev_token
;
5460 /* Token codes for the intel parser. Since T_SHORT is already used
5461 by COFF, undefine it first to prevent a warning. */
5476 /* Prototypes for intel parser functions. */
5477 static int intel_match_token
PARAMS ((int code
));
5478 static void intel_get_token
PARAMS ((void));
5479 static void intel_putback_token
PARAMS ((void));
5480 static int intel_expr
PARAMS ((void));
5481 static int intel_e05
PARAMS ((void));
5482 static int intel_e05_1
PARAMS ((void));
5483 static int intel_e06
PARAMS ((void));
5484 static int intel_e06_1
PARAMS ((void));
5485 static int intel_e09
PARAMS ((void));
5486 static int intel_e09_1
PARAMS ((void));
5487 static int intel_e10
PARAMS ((void));
5488 static int intel_e10_1
PARAMS ((void));
5489 static int intel_e11
PARAMS ((void));
5492 i386_intel_operand (operand_string
, got_a_float
)
5493 char *operand_string
;
5499 /* Initialize token holders. */
5500 cur_token
.code
= prev_token
.code
= T_NIL
;
5501 cur_token
.reg
= prev_token
.reg
= NULL
;
5502 cur_token
.str
= prev_token
.str
= NULL
;
5504 /* Initialize parser structure. */
5505 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5508 strcpy (intel_parser
.op_string
, operand_string
);
5509 intel_parser
.got_a_float
= got_a_float
;
5510 intel_parser
.op_modifier
= -1;
5511 intel_parser
.is_mem
= 0;
5512 intel_parser
.reg
= NULL
;
5513 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5514 if (intel_parser
.disp
== NULL
)
5516 intel_parser
.disp
[0] = '\0';
5518 /* Read the first token and start the parser. */
5520 ret
= intel_expr ();
5524 /* If we found a memory reference, hand it over to i386_displacement
5525 to fill in the rest of the operand fields. */
5526 if (intel_parser
.is_mem
)
5528 if ((i
.mem_operands
== 1
5529 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5530 || i
.mem_operands
== 2)
5532 as_bad (_("too many memory references for '%s'"),
5533 current_templates
->start
->name
);
5538 char *s
= intel_parser
.disp
;
5541 /* Add the displacement expression. */
5543 ret
= i386_displacement (s
, s
+ strlen (s
))
5544 && i386_index_check (s
);
5548 /* Constant and OFFSET expressions are handled by i386_immediate. */
5549 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5550 || intel_parser
.reg
== NULL
)
5551 ret
= i386_immediate (intel_parser
.disp
);
5555 free (intel_parser
.disp
);
5565 /* expr SHORT e05 */
5566 if (cur_token
.code
== T_SHORT
)
5568 intel_parser
.op_modifier
= SHORT
;
5569 intel_match_token (T_SHORT
);
5571 return (intel_e05 ());
5576 return intel_e05 ();
5586 return (intel_e06 () && intel_e05_1 ());
5592 /* e05' addOp e06 e05' */
5593 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5595 strcat (intel_parser
.disp
, cur_token
.str
);
5596 intel_match_token (cur_token
.code
);
5598 return (intel_e06 () && intel_e05_1 ());
5613 return (intel_e09 () && intel_e06_1 ());
5619 /* e06' mulOp e09 e06' */
5620 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5622 strcat (intel_parser
.disp
, cur_token
.str
);
5623 intel_match_token (cur_token
.code
);
5625 return (intel_e09 () && intel_e06_1 ());
5633 /* e09 OFFSET e10 e09'
5642 /* e09 OFFSET e10 e09' */
5643 if (cur_token
.code
== T_OFFSET
)
5645 intel_parser
.is_mem
= 0;
5646 intel_parser
.op_modifier
= OFFSET_FLAT
;
5647 intel_match_token (T_OFFSET
);
5649 return (intel_e10 () && intel_e09_1 ());
5654 return (intel_e10 () && intel_e09_1 ());
5660 /* e09' PTR e10 e09' */
5661 if (cur_token
.code
== T_PTR
)
5663 if (prev_token
.code
== T_BYTE
)
5664 i
.suffix
= BYTE_MNEM_SUFFIX
;
5666 else if (prev_token
.code
== T_WORD
)
5668 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5669 i
.suffix
= SHORT_MNEM_SUFFIX
;
5671 i
.suffix
= WORD_MNEM_SUFFIX
;
5674 else if (prev_token
.code
== T_DWORD
)
5676 if (intel_parser
.got_a_float
== 1) /* "f..." */
5677 i
.suffix
= SHORT_MNEM_SUFFIX
;
5679 i
.suffix
= LONG_MNEM_SUFFIX
;
5682 else if (prev_token
.code
== T_QWORD
)
5684 if (intel_parser
.got_a_float
== 1) /* "f..." */
5685 i
.suffix
= LONG_MNEM_SUFFIX
;
5687 i
.suffix
= QWORD_MNEM_SUFFIX
;
5690 else if (prev_token
.code
== T_XWORD
)
5691 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5695 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5699 intel_match_token (T_PTR
);
5701 return (intel_e10 () && intel_e09_1 ());
5704 /* e09 : e10 e09' */
5705 else if (cur_token
.code
== ':')
5707 /* Mark as a memory operand only if it's not already known to be an
5708 offset expression. */
5709 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5710 intel_parser
.is_mem
= 1;
5712 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5727 return (intel_e11 () && intel_e10_1 ());
5733 /* e10' [ expr ] e10' */
5734 if (cur_token
.code
== '[')
5736 intel_match_token ('[');
5738 /* Mark as a memory operand only if it's not already known to be an
5739 offset expression. If it's an offset expression, we need to keep
5741 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5742 intel_parser
.is_mem
= 1;
5744 strcat (intel_parser
.disp
, "[");
5746 /* Add a '+' to the displacement string if necessary. */
5747 if (*intel_parser
.disp
!= '\0'
5748 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5749 strcat (intel_parser
.disp
, "+");
5751 if (intel_expr () && intel_match_token (']'))
5753 /* Preserve brackets when the operand is an offset expression. */
5754 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5755 strcat (intel_parser
.disp
, "]");
5757 return intel_e10_1 ();
5784 if (cur_token
.code
== '(')
5786 intel_match_token ('(');
5787 strcat (intel_parser
.disp
, "(");
5789 if (intel_expr () && intel_match_token (')'))
5791 strcat (intel_parser
.disp
, ")");
5799 else if (cur_token
.code
== '[')
5801 intel_match_token ('[');
5803 /* Mark as a memory operand only if it's not already known to be an
5804 offset expression. If it's an offset expression, we need to keep
5806 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5807 intel_parser
.is_mem
= 1;
5809 strcat (intel_parser
.disp
, "[");
5811 /* Operands for jump/call inside brackets denote absolute addresses. */
5812 if (current_templates
->start
->opcode_modifier
& Jump
5813 || current_templates
->start
->opcode_modifier
& JumpDword
5814 || current_templates
->start
->opcode_modifier
& JumpByte
5815 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5816 i
.types
[this_operand
] |= JumpAbsolute
;
5818 /* Add a '+' to the displacement string if necessary. */
5819 if (*intel_parser
.disp
!= '\0'
5820 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5821 strcat (intel_parser
.disp
, "+");
5823 if (intel_expr () && intel_match_token (']'))
5825 /* Preserve brackets when the operand is an offset expression. */
5826 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5827 strcat (intel_parser
.disp
, "]");
5840 else if (cur_token
.code
== T_BYTE
5841 || cur_token
.code
== T_WORD
5842 || cur_token
.code
== T_DWORD
5843 || cur_token
.code
== T_QWORD
5844 || cur_token
.code
== T_XWORD
)
5846 intel_match_token (cur_token
.code
);
5853 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5855 strcat (intel_parser
.disp
, cur_token
.str
);
5856 intel_match_token (cur_token
.code
);
5858 /* Mark as a memory operand only if it's not already known to be an
5859 offset expression. */
5860 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5861 intel_parser
.is_mem
= 1;
5867 else if (cur_token
.code
== T_REG
)
5869 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5871 intel_match_token (T_REG
);
5873 /* Check for segment change. */
5874 if (cur_token
.code
== ':')
5876 if (reg
->reg_type
& (SReg2
| SReg3
))
5878 switch (reg
->reg_num
)
5881 i
.seg
[i
.mem_operands
] = &es
;
5884 i
.seg
[i
.mem_operands
] = &cs
;
5887 i
.seg
[i
.mem_operands
] = &ss
;
5890 i
.seg
[i
.mem_operands
] = &ds
;
5893 i
.seg
[i
.mem_operands
] = &fs
;
5896 i
.seg
[i
.mem_operands
] = &gs
;
5902 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5907 /* Not a segment register. Check for register scaling. */
5908 else if (cur_token
.code
== '*')
5910 if (!intel_parser
.is_mem
)
5912 as_bad (_("Register scaling only allowed in memory operands."));
5916 /* What follows must be a valid scale. */
5917 if (intel_match_token ('*')
5918 && strchr ("01248", *cur_token
.str
))
5921 i
.types
[this_operand
] |= BaseIndex
;
5923 /* Set the scale after setting the register (otherwise,
5924 i386_scale will complain) */
5925 i386_scale (cur_token
.str
);
5926 intel_match_token (T_CONST
);
5930 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5936 /* No scaling. If this is a memory operand, the register is either a
5937 base register (first occurrence) or an index register (second
5939 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5941 if (i
.base_reg
&& i
.index_reg
)
5943 as_bad (_("Too many register references in memory operand.\n"));
5947 if (i
.base_reg
== NULL
)
5952 i
.types
[this_operand
] |= BaseIndex
;
5955 /* Offset modifier. Add the register to the displacement string to be
5956 parsed as an immediate expression after we're done. */
5957 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5958 strcat (intel_parser
.disp
, reg
->reg_name
);
5960 /* It's neither base nor index nor offset. */
5963 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5964 i
.op
[this_operand
].regs
= reg
;
5968 /* Since registers are not part of the displacement string (except
5969 when we're parsing offset operands), we may need to remove any
5970 preceding '+' from the displacement string. */
5971 if (*intel_parser
.disp
!= '\0'
5972 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5974 char *s
= intel_parser
.disp
;
5975 s
+= strlen (s
) - 1;
5984 else if (cur_token
.code
== T_ID
)
5986 /* Add the identifier to the displacement string. */
5987 strcat (intel_parser
.disp
, cur_token
.str
);
5988 intel_match_token (T_ID
);
5990 /* The identifier represents a memory reference only if it's not
5991 preceded by an offset modifier. */
5992 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5993 intel_parser
.is_mem
= 1;
5999 else if (cur_token
.code
== T_CONST
6000 || cur_token
.code
== '-'
6001 || cur_token
.code
== '+')
6005 /* Allow constants that start with `+' or `-'. */
6006 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6008 strcat (intel_parser
.disp
, cur_token
.str
);
6009 intel_match_token (cur_token
.code
);
6010 if (cur_token
.code
!= T_CONST
)
6012 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6018 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6019 if (save_str
== NULL
)
6021 strcpy (save_str
, cur_token
.str
);
6023 /* Get the next token to check for register scaling. */
6024 intel_match_token (cur_token
.code
);
6026 /* Check if this constant is a scaling factor for an index register. */
6027 if (cur_token
.code
== '*')
6029 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6031 if (!intel_parser
.is_mem
)
6033 as_bad (_("Register scaling only allowed in memory operands."));
6037 /* The constant is followed by `* reg', so it must be
6039 if (strchr ("01248", *save_str
))
6041 i
.index_reg
= cur_token
.reg
;
6042 i
.types
[this_operand
] |= BaseIndex
;
6044 /* Set the scale after setting the register (otherwise,
6045 i386_scale will complain) */
6046 i386_scale (save_str
);
6047 intel_match_token (T_REG
);
6049 /* Since registers are not part of the displacement
6050 string, we may need to remove any preceding '+' from
6051 the displacement string. */
6052 if (*intel_parser
.disp
!= '\0')
6054 char *s
= intel_parser
.disp
;
6055 s
+= strlen (s
) - 1;
6068 /* The constant was not used for register scaling. Since we have
6069 already consumed the token following `*' we now need to put it
6070 back in the stream. */
6072 intel_putback_token ();
6075 /* Add the constant to the displacement string. */
6076 strcat (intel_parser
.disp
, save_str
);
6082 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6086 /* Match the given token against cur_token. If they match, read the next
6087 token from the operand string. */
6089 intel_match_token (code
)
6092 if (cur_token
.code
== code
)
6099 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6104 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6109 const reg_entry
*reg
;
6110 struct intel_token new_token
;
6112 new_token
.code
= T_NIL
;
6113 new_token
.reg
= NULL
;
6114 new_token
.str
= NULL
;
6116 /* Free the memory allocated to the previous token and move
6117 cur_token to prev_token. */
6119 free (prev_token
.str
);
6121 prev_token
= cur_token
;
6123 /* Skip whitespace. */
6124 while (is_space_char (*intel_parser
.op_string
))
6125 intel_parser
.op_string
++;
6127 /* Return an empty token if we find nothing else on the line. */
6128 if (*intel_parser
.op_string
== '\0')
6130 cur_token
= new_token
;
6134 /* The new token cannot be larger than the remainder of the operand
6136 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6137 if (new_token
.str
== NULL
)
6139 new_token
.str
[0] = '\0';
6141 if (strchr ("0123456789", *intel_parser
.op_string
))
6143 char *p
= new_token
.str
;
6144 char *q
= intel_parser
.op_string
;
6145 new_token
.code
= T_CONST
;
6147 /* Allow any kind of identifier char to encompass floating point and
6148 hexadecimal numbers. */
6149 while (is_identifier_char (*q
))
6153 /* Recognize special symbol names [0-9][bf]. */
6154 if (strlen (intel_parser
.op_string
) == 2
6155 && (intel_parser
.op_string
[1] == 'b'
6156 || intel_parser
.op_string
[1] == 'f'))
6157 new_token
.code
= T_ID
;
6160 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6162 new_token
.code
= *intel_parser
.op_string
;
6163 new_token
.str
[0] = *intel_parser
.op_string
;
6164 new_token
.str
[1] = '\0';
6167 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6168 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6170 new_token
.code
= T_REG
;
6171 new_token
.reg
= reg
;
6173 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6175 new_token
.str
[0] = REGISTER_PREFIX
;
6176 new_token
.str
[1] = '\0';
6179 strcat (new_token
.str
, reg
->reg_name
);
6182 else if (is_identifier_char (*intel_parser
.op_string
))
6184 char *p
= new_token
.str
;
6185 char *q
= intel_parser
.op_string
;
6187 /* A '.' or '$' followed by an identifier char is an identifier.
6188 Otherwise, it's operator '.' followed by an expression. */
6189 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6191 new_token
.code
= *q
;
6192 new_token
.str
[0] = *q
;
6193 new_token
.str
[1] = '\0';
6197 while (is_identifier_char (*q
) || *q
== '@')
6201 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6202 new_token
.code
= T_BYTE
;
6204 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6205 new_token
.code
= T_WORD
;
6207 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6208 new_token
.code
= T_DWORD
;
6210 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6211 new_token
.code
= T_QWORD
;
6213 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6214 new_token
.code
= T_XWORD
;
6216 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6217 new_token
.code
= T_PTR
;
6219 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6220 new_token
.code
= T_SHORT
;
6222 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6224 new_token
.code
= T_OFFSET
;
6226 /* ??? This is not mentioned in the MASM grammar but gcc
6227 makes use of it with -mintel-syntax. OFFSET may be
6228 followed by FLAT: */
6229 if (strncasecmp (q
, " FLAT:", 6) == 0)
6230 strcat (new_token
.str
, " FLAT:");
6233 /* ??? This is not mentioned in the MASM grammar. */
6234 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6235 new_token
.code
= T_OFFSET
;
6238 new_token
.code
= T_ID
;
6243 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6245 intel_parser
.op_string
+= strlen (new_token
.str
);
6246 cur_token
= new_token
;
6249 /* Put cur_token back into the token stream and make cur_token point to
6252 intel_putback_token ()
6254 intel_parser
.op_string
-= strlen (cur_token
.str
);
6255 free (cur_token
.str
);
6256 cur_token
= prev_token
;
6258 /* Forget prev_token. */
6259 prev_token
.code
= T_NIL
;
6260 prev_token
.reg
= NULL
;
6261 prev_token
.str
= NULL
;