1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 /* 1 for intel syntax,
529 static int intel_syntax
= 0;
531 /* 1 for intel mnemonic,
532 0 if att mnemonic. */
533 static int intel_mnemonic
= !SYSV386_COMPAT
;
535 /* 1 if support old (<= 2.8.1) versions of gcc. */
536 static int old_gcc
= OLDGCC_COMPAT
;
538 /* 1 if pseudo registers are permitted. */
539 static int allow_pseudo_reg
= 0;
541 /* 1 if register prefix % not required. */
542 static int allow_naked_reg
= 0;
544 /* 1 if the assembler should add BND prefix for all control-tranferring
545 instructions supporting it, even if this prefix wasn't specified
547 static int add_bnd_prefix
= 0;
549 /* 1 if pseudo index register, eiz/riz, is allowed . */
550 static int allow_index_reg
= 0;
552 /* 1 if the assembler should ignore LOCK prefix, even if it was
553 specified explicitly. */
554 static int omit_lock_prefix
= 0;
556 static enum check_kind
562 sse_check
, operand_check
= check_warning
;
564 /* Register prefix used for error message. */
565 static const char *register_prefix
= "%";
567 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
568 leave, push, and pop instructions so that gcc has the same stack
569 frame as in 32 bit mode. */
570 static char stackop_size
= '\0';
572 /* Non-zero to optimize code alignment. */
573 int optimize_align_code
= 1;
575 /* Non-zero to quieten some warnings. */
576 static int quiet_warnings
= 0;
579 static const char *cpu_arch_name
= NULL
;
580 static char *cpu_sub_arch_name
= NULL
;
582 /* CPU feature flags. */
583 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
585 /* If we have selected a cpu we are generating instructions for. */
586 static int cpu_arch_tune_set
= 0;
588 /* Cpu we are generating instructions for. */
589 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of cpu we are generating instructions for. */
592 static i386_cpu_flags cpu_arch_tune_flags
;
594 /* CPU instruction set architecture used. */
595 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
597 /* CPU feature flags of instruction set architecture used. */
598 i386_cpu_flags cpu_arch_isa_flags
;
600 /* If set, conditional jumps are not automatically promoted to handle
601 larger than a byte offset. */
602 static unsigned int no_cond_jump_promotion
= 0;
604 /* Encode SSE instructions with VEX prefix. */
605 static unsigned int sse2avx
;
607 /* Encode scalar AVX instructions with specific vector length. */
614 /* Encode scalar EVEX LIG instructions with specific vector length. */
622 /* Encode EVEX WIG instructions with specific evex.w. */
629 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
630 static enum rc_type evexrcig
= rne
;
632 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
633 static symbolS
*GOT_symbol
;
635 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
636 unsigned int x86_dwarf2_return_column
;
638 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
639 int x86_cie_data_alignment
;
641 /* Interface to relax_segment.
642 There are 3 major relax states for 386 jump insns because the
643 different types of jumps add different sizes to frags when we're
644 figuring out what sort of jump to choose to reach a given label. */
647 #define UNCOND_JUMP 0
649 #define COND_JUMP86 2
654 #define SMALL16 (SMALL | CODE16)
656 #define BIG16 (BIG | CODE16)
660 #define INLINE __inline__
666 #define ENCODE_RELAX_STATE(type, size) \
667 ((relax_substateT) (((type) << 2) | (size)))
668 #define TYPE_FROM_RELAX_STATE(s) \
670 #define DISP_SIZE_FROM_RELAX_STATE(s) \
671 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
673 /* This table is used by relax_frag to promote short jumps to long
674 ones where necessary. SMALL (short) jumps may be promoted to BIG
675 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
676 don't allow a short jump in a 32 bit code segment to be promoted to
677 a 16 bit offset jump because it's slower (requires data size
678 prefix), and doesn't work, unless the destination is in the bottom
679 64k of the code segment (The top 16 bits of eip are zeroed). */
681 const relax_typeS md_relax_table
[] =
684 1) most positive reach of this state,
685 2) most negative reach of this state,
686 3) how many bytes this mode will have in the variable part of the frag
687 4) which index into the table to try if we can't fit into this one. */
689 /* UNCOND_JUMP states. */
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
691 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
692 /* dword jmp adds 4 bytes to frag:
693 0 extra opcode bytes, 4 displacement bytes. */
695 /* word jmp adds 2 byte2 to frag:
696 0 extra opcode bytes, 2 displacement bytes. */
699 /* COND_JUMP states. */
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
701 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
702 /* dword conditionals adds 5 bytes to frag:
703 1 extra opcode byte, 4 displacement bytes. */
705 /* word conditionals add 3 bytes to frag:
706 1 extra opcode byte, 2 displacement bytes. */
709 /* COND_JUMP86 states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
712 /* dword conditionals adds 5 bytes to frag:
713 1 extra opcode byte, 4 displacement bytes. */
715 /* word conditionals add 4 bytes to frag:
716 1 displacement byte and a 3 byte long branch insn. */
720 static const arch_entry cpu_arch
[] =
722 /* Do not replace the first two entries - i386_target_format()
723 relies on them being there in this order. */
724 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
725 CPU_GENERIC32_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
727 CPU_GENERIC64_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
729 CPU_NONE_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
731 CPU_I186_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
733 CPU_I286_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
735 CPU_I386_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
737 CPU_I486_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
739 CPU_I586_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
741 CPU_I686_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
743 CPU_I586_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
745 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
747 CPU_P2_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
749 CPU_P3_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
751 CPU_P4_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
755 CPU_NOCONA_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
757 CPU_CORE_FLAGS
, 1, 0 },
758 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
759 CPU_CORE_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
761 CPU_CORE2_FLAGS
, 1, 0 },
762 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
763 CPU_CORE2_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
765 CPU_COREI7_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
767 CPU_L1OM_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
769 CPU_K1OM_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
771 CPU_K6_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
773 CPU_K6_2_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
775 CPU_ATHLON_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
777 CPU_K8_FLAGS
, 1, 0 },
778 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
779 CPU_K8_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
781 CPU_K8_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
783 CPU_AMDFAM10_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
785 CPU_BDVER1_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
787 CPU_BDVER2_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
789 CPU_BDVER3_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
791 CPU_BDVER4_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
793 CPU_ZNVER1_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
795 CPU_BTVER1_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
797 CPU_BTVER2_FLAGS
, 0, 0 },
798 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
799 CPU_8087_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
801 CPU_287_FLAGS
, 0, 0 },
802 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
803 CPU_387_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
805 CPU_ANY87_FLAGS
, 0, 1 },
806 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
807 CPU_MMX_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
809 CPU_3DNOWA_FLAGS
, 0, 1 },
810 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
811 CPU_SSE_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
815 CPU_SSE3_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
817 CPU_SSSE3_FLAGS
, 0, 0 },
818 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
819 CPU_SSE4_1_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
821 CPU_SSE4_2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
823 CPU_SSE4_2_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
825 CPU_ANY_SSE_FLAGS
, 0, 1 },
826 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
827 CPU_AVX_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
829 CPU_AVX2_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
831 CPU_AVX512F_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512CD_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512ER_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
837 CPU_AVX512PF_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
839 CPU_AVX512DQ_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
841 CPU_AVX512BW_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512VL_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
845 CPU_ANY_AVX_FLAGS
, 0, 1 },
846 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
847 CPU_VMX_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
849 CPU_VMFUNC_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
851 CPU_SMX_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
853 CPU_XSAVE_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
855 CPU_XSAVEOPT_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
857 CPU_XSAVEC_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
859 CPU_XSAVES_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
861 CPU_AES_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
863 CPU_PCLMUL_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
865 CPU_PCLMUL_FLAGS
, 1, 0 },
866 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
867 CPU_FSGSBASE_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
869 CPU_RDRND_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
871 CPU_F16C_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
873 CPU_BMI2_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
875 CPU_FMA_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
877 CPU_FMA4_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
879 CPU_XOP_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
881 CPU_LWP_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
883 CPU_MOVBE_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
885 CPU_CX16_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
887 CPU_EPT_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
889 CPU_LZCNT_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
891 CPU_HLE_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
893 CPU_RTM_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
895 CPU_INVPCID_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
897 CPU_CLFLUSH_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
899 CPU_NOP_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
901 CPU_SYSCALL_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
903 CPU_RDTSCP_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
905 CPU_3DNOW_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
907 CPU_3DNOWA_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
909 CPU_PADLOCK_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
911 CPU_SVME_FLAGS
, 1, 0 },
912 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
913 CPU_SVME_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
915 CPU_SSE4A_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
917 CPU_ABM_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
919 CPU_BMI_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
921 CPU_TBM_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
923 CPU_ADX_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
925 CPU_RDSEED_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
927 CPU_PRFCHW_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
929 CPU_SMAP_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
931 CPU_MPX_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
933 CPU_SHA_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
935 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
937 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
939 CPU_SE1_FLAGS
, 0, 0 },
940 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
941 CPU_CLWB_FLAGS
, 0, 0 },
942 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
943 CPU_PCOMMIT_FLAGS
, 0, 0 },
944 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
945 CPU_AVX512IFMA_FLAGS
, 0, 0 },
946 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
947 CPU_AVX512VBMI_FLAGS
, 0, 0 },
948 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
949 CPU_CLZERO_FLAGS
, 0, 0 },
953 /* Like s_lcomm_internal in gas/read.c but the alignment string
954 is allowed to be optional. */
957 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
964 && *input_line_pointer
== ',')
966 align
= parse_align (needs_align
- 1);
968 if (align
== (addressT
) -1)
983 bss_alloc (symbolP
, size
, align
);
988 pe_lcomm (int needs_align
)
990 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
994 const pseudo_typeS md_pseudo_table
[] =
996 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
997 {"align", s_align_bytes
, 0},
999 {"align", s_align_ptwo
, 0},
1001 {"arch", set_cpu_arch
, 0},
1005 {"lcomm", pe_lcomm
, 1},
1007 {"ffloat", float_cons
, 'f'},
1008 {"dfloat", float_cons
, 'd'},
1009 {"tfloat", float_cons
, 'x'},
1011 {"slong", signed_cons
, 4},
1012 {"noopt", s_ignore
, 0},
1013 {"optim", s_ignore
, 0},
1014 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1015 {"code16", set_code_flag
, CODE_16BIT
},
1016 {"code32", set_code_flag
, CODE_32BIT
},
1017 {"code64", set_code_flag
, CODE_64BIT
},
1018 {"intel_syntax", set_intel_syntax
, 1},
1019 {"att_syntax", set_intel_syntax
, 0},
1020 {"intel_mnemonic", set_intel_mnemonic
, 1},
1021 {"att_mnemonic", set_intel_mnemonic
, 0},
1022 {"allow_index_reg", set_allow_index_reg
, 1},
1023 {"disallow_index_reg", set_allow_index_reg
, 0},
1024 {"sse_check", set_check
, 0},
1025 {"operand_check", set_check
, 1},
1026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1027 {"largecomm", handle_large_common
, 0},
1029 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1030 {"loc", dwarf2_directive_loc
, 0},
1031 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1034 {"secrel32", pe_directive_secrel
, 0},
1039 /* For interface with expression (). */
1040 extern char *input_line_pointer
;
1042 /* Hash table for instruction mnemonic lookup. */
1043 static struct hash_control
*op_hash
;
1045 /* Hash table for register lookup. */
1046 static struct hash_control
*reg_hash
;
1049 i386_align_code (fragS
*fragP
, int count
)
1051 /* Various efficient no-op patterns for aligning code labels.
1052 Note: Don't try to assemble the instructions in the comments.
1053 0L and 0w are not legal. */
1054 static const char f32_1
[] =
1056 static const char f32_2
[] =
1057 {0x66,0x90}; /* xchg %ax,%ax */
1058 static const char f32_3
[] =
1059 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1060 static const char f32_4
[] =
1061 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1062 static const char f32_5
[] =
1064 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_6
[] =
1066 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1067 static const char f32_7
[] =
1068 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1069 static const char f32_8
[] =
1071 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_9
[] =
1073 {0x89,0xf6, /* movl %esi,%esi */
1074 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1075 static const char f32_10
[] =
1076 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_11
[] =
1079 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_12
[] =
1082 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1083 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1084 static const char f32_13
[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_14
[] =
1088 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f16_3
[] =
1091 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1092 static const char f16_4
[] =
1093 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1094 static const char f16_5
[] =
1096 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_6
[] =
1098 {0x89,0xf6, /* mov %si,%si */
1099 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1100 static const char f16_7
[] =
1101 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_8
[] =
1104 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char jump_31
[] =
1107 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1108 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1109 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1110 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1111 static const char *const f32_patt
[] = {
1112 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1113 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1115 static const char *const f16_patt
[] = {
1116 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1118 /* nopl (%[re]ax) */
1119 static const char alt_3
[] =
1121 /* nopl 0(%[re]ax) */
1122 static const char alt_4
[] =
1123 {0x0f,0x1f,0x40,0x00};
1124 /* nopl 0(%[re]ax,%[re]ax,1) */
1125 static const char alt_5
[] =
1126 {0x0f,0x1f,0x44,0x00,0x00};
1127 /* nopw 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_6
[] =
1129 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopl 0L(%[re]ax) */
1131 static const char alt_7
[] =
1132 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1133 /* nopl 0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_8
[] =
1135 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 /* nopw 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_9
[] =
1138 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_10
[] =
1141 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 static const char *const alt_patt
[] = {
1143 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1147 /* Only align for at least a positive non-zero boundary. */
1148 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1151 /* We need to decide which NOP sequence to use for 32bit and
1152 64bit. When -mtune= is used:
1154 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1155 PROCESSOR_GENERIC32, f32_patt will be used.
1156 2. For the rest, alt_patt will be used.
1158 When -mtune= isn't used, alt_patt will be used if
1159 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1162 When -march= or .arch is used, we can't use anything beyond
1163 cpu_arch_isa_flags. */
1165 if (flag_code
== CODE_16BIT
)
1169 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1171 /* Adjust jump offset. */
1172 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1175 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1176 f16_patt
[count
- 1], count
);
1180 const char *const *patt
= NULL
;
1182 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1184 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1185 switch (cpu_arch_tune
)
1187 case PROCESSOR_UNKNOWN
:
1188 /* We use cpu_arch_isa_flags to check if we SHOULD
1189 optimize with nops. */
1190 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1195 case PROCESSOR_PENTIUM4
:
1196 case PROCESSOR_NOCONA
:
1197 case PROCESSOR_CORE
:
1198 case PROCESSOR_CORE2
:
1199 case PROCESSOR_COREI7
:
1200 case PROCESSOR_L1OM
:
1201 case PROCESSOR_K1OM
:
1202 case PROCESSOR_GENERIC64
:
1204 case PROCESSOR_ATHLON
:
1206 case PROCESSOR_AMDFAM10
:
1208 case PROCESSOR_ZNVER
:
1212 case PROCESSOR_I386
:
1213 case PROCESSOR_I486
:
1214 case PROCESSOR_PENTIUM
:
1215 case PROCESSOR_PENTIUMPRO
:
1216 case PROCESSOR_GENERIC32
:
1223 switch (fragP
->tc_frag_data
.tune
)
1225 case PROCESSOR_UNKNOWN
:
1226 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1227 PROCESSOR_UNKNOWN. */
1231 case PROCESSOR_I386
:
1232 case PROCESSOR_I486
:
1233 case PROCESSOR_PENTIUM
:
1235 case PROCESSOR_ATHLON
:
1237 case PROCESSOR_AMDFAM10
:
1239 case PROCESSOR_ZNVER
:
1241 case PROCESSOR_GENERIC32
:
1242 /* We use cpu_arch_isa_flags to check if we CAN optimize
1244 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1249 case PROCESSOR_PENTIUMPRO
:
1250 case PROCESSOR_PENTIUM4
:
1251 case PROCESSOR_NOCONA
:
1252 case PROCESSOR_CORE
:
1253 case PROCESSOR_CORE2
:
1254 case PROCESSOR_COREI7
:
1255 case PROCESSOR_L1OM
:
1256 case PROCESSOR_K1OM
:
1257 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1262 case PROCESSOR_GENERIC64
:
1268 if (patt
== f32_patt
)
1270 /* If the padding is less than 15 bytes, we use the normal
1271 ones. Otherwise, we use a jump instruction and adjust
1275 /* For 64bit, the limit is 3 bytes. */
1276 if (flag_code
== CODE_64BIT
1277 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1282 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1283 patt
[count
- 1], count
);
1286 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1288 /* Adjust jump offset. */
1289 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1294 /* Maximum length of an instruction is 10 byte. If the
1295 padding is greater than 10 bytes and we don't use jump,
1296 we have to break it into smaller pieces. */
1297 int padding
= count
;
1298 while (padding
> 10)
1301 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1306 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1307 patt
[padding
- 1], padding
);
1310 fragP
->fr_var
= count
;
1314 operand_type_all_zero (const union i386_operand_type
*x
)
1316 switch (ARRAY_SIZE(x
->array
))
1325 return !x
->array
[0];
1332 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1334 switch (ARRAY_SIZE(x
->array
))
1349 operand_type_equal (const union i386_operand_type
*x
,
1350 const union i386_operand_type
*y
)
1352 switch (ARRAY_SIZE(x
->array
))
1355 if (x
->array
[2] != y
->array
[2])
1358 if (x
->array
[1] != y
->array
[1])
1361 return x
->array
[0] == y
->array
[0];
1369 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1371 switch (ARRAY_SIZE(x
->array
))
1380 return !x
->array
[0];
1387 cpu_flags_equal (const union i386_cpu_flags
*x
,
1388 const union i386_cpu_flags
*y
)
1390 switch (ARRAY_SIZE(x
->array
))
1393 if (x
->array
[2] != y
->array
[2])
1396 if (x
->array
[1] != y
->array
[1])
1399 return x
->array
[0] == y
->array
[0];
1407 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1409 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1410 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1413 static INLINE i386_cpu_flags
1414 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1416 switch (ARRAY_SIZE (x
.array
))
1419 x
.array
[2] &= y
.array
[2];
1421 x
.array
[1] &= y
.array
[1];
1423 x
.array
[0] &= y
.array
[0];
1431 static INLINE i386_cpu_flags
1432 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1434 switch (ARRAY_SIZE (x
.array
))
1437 x
.array
[2] |= y
.array
[2];
1439 x
.array
[1] |= y
.array
[1];
1441 x
.array
[0] |= y
.array
[0];
1449 static INLINE i386_cpu_flags
1450 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1452 switch (ARRAY_SIZE (x
.array
))
1455 x
.array
[2] &= ~y
.array
[2];
1457 x
.array
[1] &= ~y
.array
[1];
1459 x
.array
[0] &= ~y
.array
[0];
1467 #define CPU_FLAGS_ARCH_MATCH 0x1
1468 #define CPU_FLAGS_64BIT_MATCH 0x2
1469 #define CPU_FLAGS_AES_MATCH 0x4
1470 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1471 #define CPU_FLAGS_AVX_MATCH 0x10
1473 #define CPU_FLAGS_32BIT_MATCH \
1474 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1475 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1476 #define CPU_FLAGS_PERFECT_MATCH \
1477 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1479 /* Return CPU flags match bits. */
1482 cpu_flags_match (const insn_template
*t
)
1484 i386_cpu_flags x
= t
->cpu_flags
;
1485 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1487 x
.bitfield
.cpu64
= 0;
1488 x
.bitfield
.cpuno64
= 0;
1490 if (cpu_flags_all_zero (&x
))
1492 /* This instruction is available on all archs. */
1493 match
|= CPU_FLAGS_32BIT_MATCH
;
1497 /* This instruction is available only on some archs. */
1498 i386_cpu_flags cpu
= cpu_arch_flags
;
1500 cpu
.bitfield
.cpu64
= 0;
1501 cpu
.bitfield
.cpuno64
= 0;
1502 cpu
= cpu_flags_and (x
, cpu
);
1503 if (!cpu_flags_all_zero (&cpu
))
1505 if (x
.bitfield
.cpuavx
)
1507 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1508 if (cpu
.bitfield
.cpuavx
)
1510 /* Check SSE2AVX. */
1511 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1513 match
|= (CPU_FLAGS_ARCH_MATCH
1514 | CPU_FLAGS_AVX_MATCH
);
1516 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1517 match
|= CPU_FLAGS_AES_MATCH
;
1519 if (!x
.bitfield
.cpupclmul
1520 || cpu
.bitfield
.cpupclmul
)
1521 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1525 match
|= CPU_FLAGS_ARCH_MATCH
;
1528 match
|= CPU_FLAGS_32BIT_MATCH
;
1534 static INLINE i386_operand_type
1535 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1537 switch (ARRAY_SIZE (x
.array
))
1540 x
.array
[2] &= y
.array
[2];
1542 x
.array
[1] &= y
.array
[1];
1544 x
.array
[0] &= y
.array
[0];
1552 static INLINE i386_operand_type
1553 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1555 switch (ARRAY_SIZE (x
.array
))
1558 x
.array
[2] |= y
.array
[2];
1560 x
.array
[1] |= y
.array
[1];
1562 x
.array
[0] |= y
.array
[0];
1570 static INLINE i386_operand_type
1571 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1573 switch (ARRAY_SIZE (x
.array
))
1576 x
.array
[2] ^= y
.array
[2];
1578 x
.array
[1] ^= y
.array
[1];
1580 x
.array
[0] ^= y
.array
[0];
1588 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1589 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1590 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1591 static const i386_operand_type inoutportreg
1592 = OPERAND_TYPE_INOUTPORTREG
;
1593 static const i386_operand_type reg16_inoutportreg
1594 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1595 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1596 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1597 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1598 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1599 static const i386_operand_type anydisp
1600 = OPERAND_TYPE_ANYDISP
;
1601 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1602 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1603 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1604 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1605 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1606 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1607 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1608 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1609 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1610 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1611 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1612 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1613 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1614 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1625 operand_type_check (i386_operand_type t
, enum operand_type c
)
1630 return (t
.bitfield
.reg8
1633 || t
.bitfield
.reg64
);
1636 return (t
.bitfield
.imm8
1640 || t
.bitfield
.imm32s
1641 || t
.bitfield
.imm64
);
1644 return (t
.bitfield
.disp8
1645 || t
.bitfield
.disp16
1646 || t
.bitfield
.disp32
1647 || t
.bitfield
.disp32s
1648 || t
.bitfield
.disp64
);
1651 return (t
.bitfield
.disp8
1652 || t
.bitfield
.disp16
1653 || t
.bitfield
.disp32
1654 || t
.bitfield
.disp32s
1655 || t
.bitfield
.disp64
1656 || t
.bitfield
.baseindex
);
1665 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1666 operand J for instruction template T. */
1669 match_reg_size (const insn_template
*t
, unsigned int j
)
1671 return !((i
.types
[j
].bitfield
.byte
1672 && !t
->operand_types
[j
].bitfield
.byte
)
1673 || (i
.types
[j
].bitfield
.word
1674 && !t
->operand_types
[j
].bitfield
.word
)
1675 || (i
.types
[j
].bitfield
.dword
1676 && !t
->operand_types
[j
].bitfield
.dword
)
1677 || (i
.types
[j
].bitfield
.qword
1678 && !t
->operand_types
[j
].bitfield
.qword
));
1681 /* Return 1 if there is no conflict in any size on operand J for
1682 instruction template T. */
1685 match_mem_size (const insn_template
*t
, unsigned int j
)
1687 return (match_reg_size (t
, j
)
1688 && !((i
.types
[j
].bitfield
.unspecified
1689 && !t
->operand_types
[j
].bitfield
.unspecified
)
1690 || (i
.types
[j
].bitfield
.fword
1691 && !t
->operand_types
[j
].bitfield
.fword
)
1692 || (i
.types
[j
].bitfield
.tbyte
1693 && !t
->operand_types
[j
].bitfield
.tbyte
)
1694 || (i
.types
[j
].bitfield
.xmmword
1695 && !t
->operand_types
[j
].bitfield
.xmmword
)
1696 || (i
.types
[j
].bitfield
.ymmword
1697 && !t
->operand_types
[j
].bitfield
.ymmword
)
1698 || (i
.types
[j
].bitfield
.zmmword
1699 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1702 /* Return 1 if there is no size conflict on any operands for
1703 instruction template T. */
1706 operand_size_match (const insn_template
*t
)
1711 /* Don't check jump instructions. */
1712 if (t
->opcode_modifier
.jump
1713 || t
->opcode_modifier
.jumpbyte
1714 || t
->opcode_modifier
.jumpdword
1715 || t
->opcode_modifier
.jumpintersegment
)
1718 /* Check memory and accumulator operand size. */
1719 for (j
= 0; j
< i
.operands
; j
++)
1721 if (t
->operand_types
[j
].bitfield
.anysize
)
1724 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1730 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1739 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1742 i
.error
= operand_size_mismatch
;
1746 /* Check reverse. */
1747 gas_assert (i
.operands
== 2);
1750 for (j
= 0; j
< 2; j
++)
1752 if (t
->operand_types
[j
].bitfield
.acc
1753 && !match_reg_size (t
, j
? 0 : 1))
1756 if (i
.types
[j
].bitfield
.mem
1757 && !match_mem_size (t
, j
? 0 : 1))
1765 operand_type_match (i386_operand_type overlap
,
1766 i386_operand_type given
)
1768 i386_operand_type temp
= overlap
;
1770 temp
.bitfield
.jumpabsolute
= 0;
1771 temp
.bitfield
.unspecified
= 0;
1772 temp
.bitfield
.byte
= 0;
1773 temp
.bitfield
.word
= 0;
1774 temp
.bitfield
.dword
= 0;
1775 temp
.bitfield
.fword
= 0;
1776 temp
.bitfield
.qword
= 0;
1777 temp
.bitfield
.tbyte
= 0;
1778 temp
.bitfield
.xmmword
= 0;
1779 temp
.bitfield
.ymmword
= 0;
1780 temp
.bitfield
.zmmword
= 0;
1781 if (operand_type_all_zero (&temp
))
1784 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1785 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1789 i
.error
= operand_type_mismatch
;
1793 /* If given types g0 and g1 are registers they must be of the same type
1794 unless the expected operand type register overlap is null.
1795 Note that Acc in a template matches every size of reg. */
1798 operand_type_register_match (i386_operand_type m0
,
1799 i386_operand_type g0
,
1800 i386_operand_type t0
,
1801 i386_operand_type m1
,
1802 i386_operand_type g1
,
1803 i386_operand_type t1
)
1805 if (!operand_type_check (g0
, reg
))
1808 if (!operand_type_check (g1
, reg
))
1811 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1812 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1813 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1814 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1817 if (m0
.bitfield
.acc
)
1819 t0
.bitfield
.reg8
= 1;
1820 t0
.bitfield
.reg16
= 1;
1821 t0
.bitfield
.reg32
= 1;
1822 t0
.bitfield
.reg64
= 1;
1825 if (m1
.bitfield
.acc
)
1827 t1
.bitfield
.reg8
= 1;
1828 t1
.bitfield
.reg16
= 1;
1829 t1
.bitfield
.reg32
= 1;
1830 t1
.bitfield
.reg64
= 1;
1833 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1834 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1835 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1836 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1839 i
.error
= register_type_mismatch
;
1844 static INLINE
unsigned int
1845 register_number (const reg_entry
*r
)
1847 unsigned int nr
= r
->reg_num
;
1849 if (r
->reg_flags
& RegRex
)
1855 static INLINE
unsigned int
1856 mode_from_disp_size (i386_operand_type t
)
1858 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1860 else if (t
.bitfield
.disp16
1861 || t
.bitfield
.disp32
1862 || t
.bitfield
.disp32s
)
1869 fits_in_signed_byte (addressT num
)
1871 return num
+ 0x80 <= 0xff;
1875 fits_in_unsigned_byte (addressT num
)
1881 fits_in_unsigned_word (addressT num
)
1883 return num
<= 0xffff;
1887 fits_in_signed_word (addressT num
)
1889 return num
+ 0x8000 <= 0xffff;
1893 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1898 return num
+ 0x80000000 <= 0xffffffff;
1900 } /* fits_in_signed_long() */
1903 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1908 return num
<= 0xffffffff;
1910 } /* fits_in_unsigned_long() */
1913 fits_in_vec_disp8 (offsetT num
)
1915 int shift
= i
.memshift
;
1921 mask
= (1 << shift
) - 1;
1923 /* Return 0 if NUM isn't properly aligned. */
1927 /* Check if NUM will fit in 8bit after shift. */
1928 return fits_in_signed_byte (num
>> shift
);
1932 fits_in_imm4 (offsetT num
)
1934 return (num
& 0xf) == num
;
1937 static i386_operand_type
1938 smallest_imm_type (offsetT num
)
1940 i386_operand_type t
;
1942 operand_type_set (&t
, 0);
1943 t
.bitfield
.imm64
= 1;
1945 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1947 /* This code is disabled on the 486 because all the Imm1 forms
1948 in the opcode table are slower on the i486. They're the
1949 versions with the implicitly specified single-position
1950 displacement, which has another syntax if you really want to
1952 t
.bitfield
.imm1
= 1;
1953 t
.bitfield
.imm8
= 1;
1954 t
.bitfield
.imm8s
= 1;
1955 t
.bitfield
.imm16
= 1;
1956 t
.bitfield
.imm32
= 1;
1957 t
.bitfield
.imm32s
= 1;
1959 else if (fits_in_signed_byte (num
))
1961 t
.bitfield
.imm8
= 1;
1962 t
.bitfield
.imm8s
= 1;
1963 t
.bitfield
.imm16
= 1;
1964 t
.bitfield
.imm32
= 1;
1965 t
.bitfield
.imm32s
= 1;
1967 else if (fits_in_unsigned_byte (num
))
1969 t
.bitfield
.imm8
= 1;
1970 t
.bitfield
.imm16
= 1;
1971 t
.bitfield
.imm32
= 1;
1972 t
.bitfield
.imm32s
= 1;
1974 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1976 t
.bitfield
.imm16
= 1;
1977 t
.bitfield
.imm32
= 1;
1978 t
.bitfield
.imm32s
= 1;
1980 else if (fits_in_signed_long (num
))
1982 t
.bitfield
.imm32
= 1;
1983 t
.bitfield
.imm32s
= 1;
1985 else if (fits_in_unsigned_long (num
))
1986 t
.bitfield
.imm32
= 1;
1992 offset_in_range (offsetT val
, int size
)
1998 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1999 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2000 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2002 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2008 /* If BFD64, sign extend val for 32bit address mode. */
2009 if (flag_code
!= CODE_64BIT
2010 || i
.prefix
[ADDR_PREFIX
])
2011 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2012 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2015 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2017 char buf1
[40], buf2
[40];
2019 sprint_value (buf1
, val
);
2020 sprint_value (buf2
, val
& mask
);
2021 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2035 a. PREFIX_EXIST if attempting to add a prefix where one from the
2036 same class already exists.
2037 b. PREFIX_LOCK if lock prefix is added.
2038 c. PREFIX_REP if rep/repne prefix is added.
2039 d. PREFIX_OTHER if other prefix is added.
2042 static enum PREFIX_GROUP
2043 add_prefix (unsigned int prefix
)
2045 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2048 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2049 && flag_code
== CODE_64BIT
)
2051 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2052 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2053 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2064 case CS_PREFIX_OPCODE
:
2065 case DS_PREFIX_OPCODE
:
2066 case ES_PREFIX_OPCODE
:
2067 case FS_PREFIX_OPCODE
:
2068 case GS_PREFIX_OPCODE
:
2069 case SS_PREFIX_OPCODE
:
2073 case REPNE_PREFIX_OPCODE
:
2074 case REPE_PREFIX_OPCODE
:
2079 case LOCK_PREFIX_OPCODE
:
2088 case ADDR_PREFIX_OPCODE
:
2092 case DATA_PREFIX_OPCODE
:
2096 if (i
.prefix
[q
] != 0)
2104 i
.prefix
[q
] |= prefix
;
2107 as_bad (_("same type of prefix used twice"));
2113 update_code_flag (int value
, int check
)
2115 PRINTF_LIKE ((*as_error
));
2117 flag_code
= (enum flag_code
) value
;
2118 if (flag_code
== CODE_64BIT
)
2120 cpu_arch_flags
.bitfield
.cpu64
= 1;
2121 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2125 cpu_arch_flags
.bitfield
.cpu64
= 0;
2126 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2128 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2131 as_error
= as_fatal
;
2134 (*as_error
) (_("64bit mode not supported on `%s'."),
2135 cpu_arch_name
? cpu_arch_name
: default_arch
);
2137 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2140 as_error
= as_fatal
;
2143 (*as_error
) (_("32bit mode not supported on `%s'."),
2144 cpu_arch_name
? cpu_arch_name
: default_arch
);
2146 stackop_size
= '\0';
2150 set_code_flag (int value
)
2152 update_code_flag (value
, 0);
2156 set_16bit_gcc_code_flag (int new_code_flag
)
2158 flag_code
= (enum flag_code
) new_code_flag
;
2159 if (flag_code
!= CODE_16BIT
)
2161 cpu_arch_flags
.bitfield
.cpu64
= 0;
2162 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2163 stackop_size
= LONG_MNEM_SUFFIX
;
2167 set_intel_syntax (int syntax_flag
)
2169 /* Find out if register prefixing is specified. */
2170 int ask_naked_reg
= 0;
2173 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2175 char *string
= input_line_pointer
;
2176 int e
= get_symbol_end ();
2178 if (strcmp (string
, "prefix") == 0)
2180 else if (strcmp (string
, "noprefix") == 0)
2183 as_bad (_("bad argument to syntax directive."));
2184 *input_line_pointer
= e
;
2186 demand_empty_rest_of_line ();
2188 intel_syntax
= syntax_flag
;
2190 if (ask_naked_reg
== 0)
2191 allow_naked_reg
= (intel_syntax
2192 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2194 allow_naked_reg
= (ask_naked_reg
< 0);
2196 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2198 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2199 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2200 register_prefix
= allow_naked_reg
? "" : "%";
2204 set_intel_mnemonic (int mnemonic_flag
)
2206 intel_mnemonic
= mnemonic_flag
;
2210 set_allow_index_reg (int flag
)
2212 allow_index_reg
= flag
;
2216 set_check (int what
)
2218 enum check_kind
*kind
;
2223 kind
= &operand_check
;
2234 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2236 char *string
= input_line_pointer
;
2237 int e
= get_symbol_end ();
2239 if (strcmp (string
, "none") == 0)
2241 else if (strcmp (string
, "warning") == 0)
2242 *kind
= check_warning
;
2243 else if (strcmp (string
, "error") == 0)
2244 *kind
= check_error
;
2246 as_bad (_("bad argument to %s_check directive."), str
);
2247 *input_line_pointer
= e
;
2250 as_bad (_("missing argument for %s_check directive"), str
);
2252 demand_empty_rest_of_line ();
2256 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2257 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2260 static const char *arch
;
2262 /* Intel LIOM is only supported on ELF. */
2268 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2269 use default_arch. */
2270 arch
= cpu_arch_name
;
2272 arch
= default_arch
;
2275 /* If we are targeting Intel L1OM, we must enable it. */
2276 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2277 || new_flag
.bitfield
.cpul1om
)
2280 /* If we are targeting Intel K1OM, we must enable it. */
2281 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2282 || new_flag
.bitfield
.cpuk1om
)
2285 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2290 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2294 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2296 char *string
= input_line_pointer
;
2297 int e
= get_symbol_end ();
2299 i386_cpu_flags flags
;
2301 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2303 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2305 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2309 cpu_arch_name
= cpu_arch
[j
].name
;
2310 cpu_sub_arch_name
= NULL
;
2311 cpu_arch_flags
= cpu_arch
[j
].flags
;
2312 if (flag_code
== CODE_64BIT
)
2314 cpu_arch_flags
.bitfield
.cpu64
= 1;
2315 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2319 cpu_arch_flags
.bitfield
.cpu64
= 0;
2320 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2322 cpu_arch_isa
= cpu_arch
[j
].type
;
2323 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2324 if (!cpu_arch_tune_set
)
2326 cpu_arch_tune
= cpu_arch_isa
;
2327 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2332 if (!cpu_arch
[j
].negated
)
2333 flags
= cpu_flags_or (cpu_arch_flags
,
2336 flags
= cpu_flags_and_not (cpu_arch_flags
,
2338 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2340 if (cpu_sub_arch_name
)
2342 char *name
= cpu_sub_arch_name
;
2343 cpu_sub_arch_name
= concat (name
,
2345 (const char *) NULL
);
2349 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2350 cpu_arch_flags
= flags
;
2351 cpu_arch_isa_flags
= flags
;
2353 *input_line_pointer
= e
;
2354 demand_empty_rest_of_line ();
2358 if (j
>= ARRAY_SIZE (cpu_arch
))
2359 as_bad (_("no such architecture: `%s'"), string
);
2361 *input_line_pointer
= e
;
2364 as_bad (_("missing cpu architecture"));
2366 no_cond_jump_promotion
= 0;
2367 if (*input_line_pointer
== ','
2368 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2370 char *string
= ++input_line_pointer
;
2371 int e
= get_symbol_end ();
2373 if (strcmp (string
, "nojumps") == 0)
2374 no_cond_jump_promotion
= 1;
2375 else if (strcmp (string
, "jumps") == 0)
2378 as_bad (_("no such architecture modifier: `%s'"), string
);
2380 *input_line_pointer
= e
;
2383 demand_empty_rest_of_line ();
2386 enum bfd_architecture
2389 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2391 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2392 || flag_code
!= CODE_64BIT
)
2393 as_fatal (_("Intel L1OM is 64bit ELF only"));
2394 return bfd_arch_l1om
;
2396 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2398 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2399 || flag_code
!= CODE_64BIT
)
2400 as_fatal (_("Intel K1OM is 64bit ELF only"));
2401 return bfd_arch_k1om
;
2404 return bfd_arch_i386
;
2410 if (!strncmp (default_arch
, "x86_64", 6))
2412 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2414 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2415 || default_arch
[6] != '\0')
2416 as_fatal (_("Intel L1OM is 64bit ELF only"));
2417 return bfd_mach_l1om
;
2419 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2421 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2422 || default_arch
[6] != '\0')
2423 as_fatal (_("Intel K1OM is 64bit ELF only"));
2424 return bfd_mach_k1om
;
2426 else if (default_arch
[6] == '\0')
2427 return bfd_mach_x86_64
;
2429 return bfd_mach_x64_32
;
2431 else if (!strcmp (default_arch
, "i386"))
2432 return bfd_mach_i386_i386
;
2434 as_fatal (_("unknown architecture"));
2440 const char *hash_err
;
2442 /* Initialize op_hash hash table. */
2443 op_hash
= hash_new ();
2446 const insn_template
*optab
;
2447 templates
*core_optab
;
2449 /* Setup for loop. */
2451 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2452 core_optab
->start
= optab
;
2457 if (optab
->name
== NULL
2458 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2460 /* different name --> ship out current template list;
2461 add to hash table; & begin anew. */
2462 core_optab
->end
= optab
;
2463 hash_err
= hash_insert (op_hash
,
2465 (void *) core_optab
);
2468 as_fatal (_("can't hash %s: %s"),
2472 if (optab
->name
== NULL
)
2474 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2475 core_optab
->start
= optab
;
2480 /* Initialize reg_hash hash table. */
2481 reg_hash
= hash_new ();
2483 const reg_entry
*regtab
;
2484 unsigned int regtab_size
= i386_regtab_size
;
2486 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2488 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2490 as_fatal (_("can't hash %s: %s"),
2496 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2501 for (c
= 0; c
< 256; c
++)
2506 mnemonic_chars
[c
] = c
;
2507 register_chars
[c
] = c
;
2508 operand_chars
[c
] = c
;
2510 else if (ISLOWER (c
))
2512 mnemonic_chars
[c
] = c
;
2513 register_chars
[c
] = c
;
2514 operand_chars
[c
] = c
;
2516 else if (ISUPPER (c
))
2518 mnemonic_chars
[c
] = TOLOWER (c
);
2519 register_chars
[c
] = mnemonic_chars
[c
];
2520 operand_chars
[c
] = c
;
2522 else if (c
== '{' || c
== '}')
2523 operand_chars
[c
] = c
;
2525 if (ISALPHA (c
) || ISDIGIT (c
))
2526 identifier_chars
[c
] = c
;
2529 identifier_chars
[c
] = c
;
2530 operand_chars
[c
] = c
;
2535 identifier_chars
['@'] = '@';
2538 identifier_chars
['?'] = '?';
2539 operand_chars
['?'] = '?';
2541 digit_chars
['-'] = '-';
2542 mnemonic_chars
['_'] = '_';
2543 mnemonic_chars
['-'] = '-';
2544 mnemonic_chars
['.'] = '.';
2545 identifier_chars
['_'] = '_';
2546 identifier_chars
['.'] = '.';
2548 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2549 operand_chars
[(unsigned char) *p
] = *p
;
2552 if (flag_code
== CODE_64BIT
)
2554 #if defined (OBJ_COFF) && defined (TE_PE)
2555 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2558 x86_dwarf2_return_column
= 16;
2560 x86_cie_data_alignment
= -8;
2564 x86_dwarf2_return_column
= 8;
2565 x86_cie_data_alignment
= -4;
2570 i386_print_statistics (FILE *file
)
2572 hash_print_statistics (file
, "i386 opcode", op_hash
);
2573 hash_print_statistics (file
, "i386 register", reg_hash
);
2578 /* Debugging routines for md_assemble. */
2579 static void pte (insn_template
*);
2580 static void pt (i386_operand_type
);
2581 static void pe (expressionS
*);
2582 static void ps (symbolS
*);
2585 pi (char *line
, i386_insn
*x
)
2589 fprintf (stdout
, "%s: template ", line
);
2591 fprintf (stdout
, " address: base %s index %s scale %x\n",
2592 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2593 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2594 x
->log2_scale_factor
);
2595 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2596 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2597 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2598 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2599 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2600 (x
->rex
& REX_W
) != 0,
2601 (x
->rex
& REX_R
) != 0,
2602 (x
->rex
& REX_X
) != 0,
2603 (x
->rex
& REX_B
) != 0);
2604 for (j
= 0; j
< x
->operands
; j
++)
2606 fprintf (stdout
, " #%d: ", j
+ 1);
2608 fprintf (stdout
, "\n");
2609 if (x
->types
[j
].bitfield
.reg8
2610 || x
->types
[j
].bitfield
.reg16
2611 || x
->types
[j
].bitfield
.reg32
2612 || x
->types
[j
].bitfield
.reg64
2613 || x
->types
[j
].bitfield
.regmmx
2614 || x
->types
[j
].bitfield
.regxmm
2615 || x
->types
[j
].bitfield
.regymm
2616 || x
->types
[j
].bitfield
.regzmm
2617 || x
->types
[j
].bitfield
.sreg2
2618 || x
->types
[j
].bitfield
.sreg3
2619 || x
->types
[j
].bitfield
.control
2620 || x
->types
[j
].bitfield
.debug
2621 || x
->types
[j
].bitfield
.test
)
2622 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2623 if (operand_type_check (x
->types
[j
], imm
))
2625 if (operand_type_check (x
->types
[j
], disp
))
2626 pe (x
->op
[j
].disps
);
2631 pte (insn_template
*t
)
2634 fprintf (stdout
, " %d operands ", t
->operands
);
2635 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2636 if (t
->extension_opcode
!= None
)
2637 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2638 if (t
->opcode_modifier
.d
)
2639 fprintf (stdout
, "D");
2640 if (t
->opcode_modifier
.w
)
2641 fprintf (stdout
, "W");
2642 fprintf (stdout
, "\n");
2643 for (j
= 0; j
< t
->operands
; j
++)
2645 fprintf (stdout
, " #%d type ", j
+ 1);
2646 pt (t
->operand_types
[j
]);
2647 fprintf (stdout
, "\n");
2654 fprintf (stdout
, " operation %d\n", e
->X_op
);
2655 fprintf (stdout
, " add_number %ld (%lx)\n",
2656 (long) e
->X_add_number
, (long) e
->X_add_number
);
2657 if (e
->X_add_symbol
)
2659 fprintf (stdout
, " add_symbol ");
2660 ps (e
->X_add_symbol
);
2661 fprintf (stdout
, "\n");
2665 fprintf (stdout
, " op_symbol ");
2666 ps (e
->X_op_symbol
);
2667 fprintf (stdout
, "\n");
2674 fprintf (stdout
, "%s type %s%s",
2676 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2677 segment_name (S_GET_SEGMENT (s
)));
2680 static struct type_name
2682 i386_operand_type mask
;
2685 const type_names
[] =
2687 { OPERAND_TYPE_REG8
, "r8" },
2688 { OPERAND_TYPE_REG16
, "r16" },
2689 { OPERAND_TYPE_REG32
, "r32" },
2690 { OPERAND_TYPE_REG64
, "r64" },
2691 { OPERAND_TYPE_IMM8
, "i8" },
2692 { OPERAND_TYPE_IMM8
, "i8s" },
2693 { OPERAND_TYPE_IMM16
, "i16" },
2694 { OPERAND_TYPE_IMM32
, "i32" },
2695 { OPERAND_TYPE_IMM32S
, "i32s" },
2696 { OPERAND_TYPE_IMM64
, "i64" },
2697 { OPERAND_TYPE_IMM1
, "i1" },
2698 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2699 { OPERAND_TYPE_DISP8
, "d8" },
2700 { OPERAND_TYPE_DISP16
, "d16" },
2701 { OPERAND_TYPE_DISP32
, "d32" },
2702 { OPERAND_TYPE_DISP32S
, "d32s" },
2703 { OPERAND_TYPE_DISP64
, "d64" },
2704 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2705 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2706 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2707 { OPERAND_TYPE_CONTROL
, "control reg" },
2708 { OPERAND_TYPE_TEST
, "test reg" },
2709 { OPERAND_TYPE_DEBUG
, "debug reg" },
2710 { OPERAND_TYPE_FLOATREG
, "FReg" },
2711 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2712 { OPERAND_TYPE_SREG2
, "SReg2" },
2713 { OPERAND_TYPE_SREG3
, "SReg3" },
2714 { OPERAND_TYPE_ACC
, "Acc" },
2715 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2716 { OPERAND_TYPE_REGMMX
, "rMMX" },
2717 { OPERAND_TYPE_REGXMM
, "rXMM" },
2718 { OPERAND_TYPE_REGYMM
, "rYMM" },
2719 { OPERAND_TYPE_REGZMM
, "rZMM" },
2720 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2721 { OPERAND_TYPE_ESSEG
, "es" },
2725 pt (i386_operand_type t
)
2728 i386_operand_type a
;
2730 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2732 a
= operand_type_and (t
, type_names
[j
].mask
);
2733 if (!operand_type_all_zero (&a
))
2734 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2739 #endif /* DEBUG386 */
2741 static bfd_reloc_code_real_type
2742 reloc (unsigned int size
,
2745 bfd_reloc_code_real_type other
)
2747 if (other
!= NO_RELOC
)
2749 reloc_howto_type
*rel
;
2754 case BFD_RELOC_X86_64_GOT32
:
2755 return BFD_RELOC_X86_64_GOT64
;
2757 case BFD_RELOC_X86_64_GOTPLT64
:
2758 return BFD_RELOC_X86_64_GOTPLT64
;
2760 case BFD_RELOC_X86_64_PLTOFF64
:
2761 return BFD_RELOC_X86_64_PLTOFF64
;
2763 case BFD_RELOC_X86_64_GOTPC32
:
2764 other
= BFD_RELOC_X86_64_GOTPC64
;
2766 case BFD_RELOC_X86_64_GOTPCREL
:
2767 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2769 case BFD_RELOC_X86_64_TPOFF32
:
2770 other
= BFD_RELOC_X86_64_TPOFF64
;
2772 case BFD_RELOC_X86_64_DTPOFF32
:
2773 other
= BFD_RELOC_X86_64_DTPOFF64
;
2779 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2780 if (other
== BFD_RELOC_SIZE32
)
2783 other
= BFD_RELOC_SIZE64
;
2786 as_bad (_("there are no pc-relative size relocations"));
2792 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2793 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2796 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2798 as_bad (_("unknown relocation (%u)"), other
);
2799 else if (size
!= bfd_get_reloc_size (rel
))
2800 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2801 bfd_get_reloc_size (rel
),
2803 else if (pcrel
&& !rel
->pc_relative
)
2804 as_bad (_("non-pc-relative relocation for pc-relative field"));
2805 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2807 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2809 as_bad (_("relocated field and relocation type differ in signedness"));
2818 as_bad (_("there are no unsigned pc-relative relocations"));
2821 case 1: return BFD_RELOC_8_PCREL
;
2822 case 2: return BFD_RELOC_16_PCREL
;
2823 case 4: return BFD_RELOC_32_PCREL
;
2824 case 8: return BFD_RELOC_64_PCREL
;
2826 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2833 case 4: return BFD_RELOC_X86_64_32S
;
2838 case 1: return BFD_RELOC_8
;
2839 case 2: return BFD_RELOC_16
;
2840 case 4: return BFD_RELOC_32
;
2841 case 8: return BFD_RELOC_64
;
2843 as_bad (_("cannot do %s %u byte relocation"),
2844 sign
> 0 ? "signed" : "unsigned", size
);
2850 /* Here we decide which fixups can be adjusted to make them relative to
2851 the beginning of the section instead of the symbol. Basically we need
2852 to make sure that the dynamic relocations are done correctly, so in
2853 some cases we force the original symbol to be used. */
2856 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2862 /* Don't adjust pc-relative references to merge sections in 64-bit
2864 if (use_rela_relocations
2865 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2869 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2870 and changed later by validate_fix. */
2871 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2872 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2875 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2876 for size relocations. */
2877 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2878 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2879 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2880 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2881 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2882 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2883 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2884 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2885 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2886 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2887 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2888 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2889 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2890 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2891 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2892 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2893 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2894 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2895 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2896 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2897 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2898 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2899 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2900 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2901 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2902 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2903 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2904 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2905 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2906 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2913 intel_float_operand (const char *mnemonic
)
2915 /* Note that the value returned is meaningful only for opcodes with (memory)
2916 operands, hence the code here is free to improperly handle opcodes that
2917 have no operands (for better performance and smaller code). */
2919 if (mnemonic
[0] != 'f')
2920 return 0; /* non-math */
2922 switch (mnemonic
[1])
2924 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2925 the fs segment override prefix not currently handled because no
2926 call path can make opcodes without operands get here */
2928 return 2 /* integer op */;
2930 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2931 return 3; /* fldcw/fldenv */
2934 if (mnemonic
[2] != 'o' /* fnop */)
2935 return 3; /* non-waiting control op */
2938 if (mnemonic
[2] == 's')
2939 return 3; /* frstor/frstpm */
2942 if (mnemonic
[2] == 'a')
2943 return 3; /* fsave */
2944 if (mnemonic
[2] == 't')
2946 switch (mnemonic
[3])
2948 case 'c': /* fstcw */
2949 case 'd': /* fstdw */
2950 case 'e': /* fstenv */
2951 case 's': /* fsts[gw] */
2957 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2958 return 0; /* fxsave/fxrstor are not really math ops */
2965 /* Build the VEX prefix. */
2968 build_vex_prefix (const insn_template
*t
)
2970 unsigned int register_specifier
;
2971 unsigned int implied_prefix
;
2972 unsigned int vector_length
;
2974 /* Check register specifier. */
2975 if (i
.vex
.register_specifier
)
2977 register_specifier
=
2978 ~register_number (i
.vex
.register_specifier
) & 0xf;
2979 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
2982 register_specifier
= 0xf;
2984 /* Use 2-byte VEX prefix by swappping destination and source
2987 && i
.operands
== i
.reg_operands
2988 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2989 && i
.tm
.opcode_modifier
.s
2992 unsigned int xchg
= i
.operands
- 1;
2993 union i386_op temp_op
;
2994 i386_operand_type temp_type
;
2996 temp_type
= i
.types
[xchg
];
2997 i
.types
[xchg
] = i
.types
[0];
2998 i
.types
[0] = temp_type
;
2999 temp_op
= i
.op
[xchg
];
3000 i
.op
[xchg
] = i
.op
[0];
3003 gas_assert (i
.rm
.mode
== 3);
3007 i
.rm
.regmem
= i
.rm
.reg
;
3010 /* Use the next insn. */
3014 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3015 vector_length
= avxscalar
;
3017 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3019 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3024 case DATA_PREFIX_OPCODE
:
3027 case REPE_PREFIX_OPCODE
:
3030 case REPNE_PREFIX_OPCODE
:
3037 /* Use 2-byte VEX prefix if possible. */
3038 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3039 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3040 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3042 /* 2-byte VEX prefix. */
3046 i
.vex
.bytes
[0] = 0xc5;
3048 /* Check the REX.R bit. */
3049 r
= (i
.rex
& REX_R
) ? 0 : 1;
3050 i
.vex
.bytes
[1] = (r
<< 7
3051 | register_specifier
<< 3
3052 | vector_length
<< 2
3057 /* 3-byte VEX prefix. */
3062 switch (i
.tm
.opcode_modifier
.vexopcode
)
3066 i
.vex
.bytes
[0] = 0xc4;
3070 i
.vex
.bytes
[0] = 0xc4;
3074 i
.vex
.bytes
[0] = 0xc4;
3078 i
.vex
.bytes
[0] = 0x8f;
3082 i
.vex
.bytes
[0] = 0x8f;
3086 i
.vex
.bytes
[0] = 0x8f;
3092 /* The high 3 bits of the second VEX byte are 1's compliment
3093 of RXB bits from REX. */
3094 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3096 /* Check the REX.W bit. */
3097 w
= (i
.rex
& REX_W
) ? 1 : 0;
3098 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3101 i
.vex
.bytes
[2] = (w
<< 7
3102 | register_specifier
<< 3
3103 | vector_length
<< 2
3108 /* Build the EVEX prefix. */
3111 build_evex_prefix (void)
3113 unsigned int register_specifier
;
3114 unsigned int implied_prefix
;
3116 rex_byte vrex_used
= 0;
3118 /* Check register specifier. */
3119 if (i
.vex
.register_specifier
)
3121 gas_assert ((i
.vrex
& REX_X
) == 0);
3123 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3124 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3125 register_specifier
+= 8;
3126 /* The upper 16 registers are encoded in the fourth byte of the
3128 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3129 i
.vex
.bytes
[3] = 0x8;
3130 register_specifier
= ~register_specifier
& 0xf;
3134 register_specifier
= 0xf;
3136 /* Encode upper 16 vector index register in the fourth byte of
3138 if (!(i
.vrex
& REX_X
))
3139 i
.vex
.bytes
[3] = 0x8;
3144 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3149 case DATA_PREFIX_OPCODE
:
3152 case REPE_PREFIX_OPCODE
:
3155 case REPNE_PREFIX_OPCODE
:
3162 /* 4 byte EVEX prefix. */
3164 i
.vex
.bytes
[0] = 0x62;
3167 switch (i
.tm
.opcode_modifier
.vexopcode
)
3183 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3185 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3187 /* The fifth bit of the second EVEX byte is 1's compliment of the
3188 REX_R bit in VREX. */
3189 if (!(i
.vrex
& REX_R
))
3190 i
.vex
.bytes
[1] |= 0x10;
3194 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3196 /* When all operands are registers, the REX_X bit in REX is not
3197 used. We reuse it to encode the upper 16 registers, which is
3198 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3199 as 1's compliment. */
3200 if ((i
.vrex
& REX_B
))
3203 i
.vex
.bytes
[1] &= ~0x40;
3207 /* EVEX instructions shouldn't need the REX prefix. */
3208 i
.vrex
&= ~vrex_used
;
3209 gas_assert (i
.vrex
== 0);
3211 /* Check the REX.W bit. */
3212 w
= (i
.rex
& REX_W
) ? 1 : 0;
3213 if (i
.tm
.opcode_modifier
.vexw
)
3215 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3218 /* If w is not set it means we are dealing with WIG instruction. */
3221 if (evexwig
== evexw1
)
3225 /* Encode the U bit. */
3226 implied_prefix
|= 0x4;
3228 /* The third byte of the EVEX prefix. */
3229 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3231 /* The fourth byte of the EVEX prefix. */
3232 /* The zeroing-masking bit. */
3233 if (i
.mask
&& i
.mask
->zeroing
)
3234 i
.vex
.bytes
[3] |= 0x80;
3236 /* Don't always set the broadcast bit if there is no RC. */
3239 /* Encode the vector length. */
3240 unsigned int vec_length
;
3242 switch (i
.tm
.opcode_modifier
.evex
)
3244 case EVEXLIG
: /* LL' is ignored */
3245 vec_length
= evexlig
<< 5;
3248 vec_length
= 0 << 5;
3251 vec_length
= 1 << 5;
3254 vec_length
= 2 << 5;
3260 i
.vex
.bytes
[3] |= vec_length
;
3261 /* Encode the broadcast bit. */
3263 i
.vex
.bytes
[3] |= 0x10;
3267 if (i
.rounding
->type
!= saeonly
)
3268 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3270 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3273 if (i
.mask
&& i
.mask
->mask
)
3274 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3278 process_immext (void)
3282 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3285 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3286 with an opcode suffix which is coded in the same place as an
3287 8-bit immediate field would be.
3288 Here we check those operands and remove them afterwards. */
3291 for (x
= 0; x
< i
.operands
; x
++)
3292 if (register_number (i
.op
[x
].regs
) != x
)
3293 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3294 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3300 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3301 which is coded in the same place as an 8-bit immediate field
3302 would be. Here we fake an 8-bit immediate operand from the
3303 opcode suffix stored in tm.extension_opcode.
3305 AVX instructions also use this encoding, for some of
3306 3 argument instructions. */
3308 gas_assert (i
.imm_operands
<= 1
3310 || ((i
.tm
.opcode_modifier
.vex
3311 || i
.tm
.opcode_modifier
.evex
)
3312 && i
.operands
<= 4)));
3314 exp
= &im_expressions
[i
.imm_operands
++];
3315 i
.op
[i
.operands
].imms
= exp
;
3316 i
.types
[i
.operands
] = imm8
;
3318 exp
->X_op
= O_constant
;
3319 exp
->X_add_number
= i
.tm
.extension_opcode
;
3320 i
.tm
.extension_opcode
= None
;
3327 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3332 as_bad (_("invalid instruction `%s' after `%s'"),
3333 i
.tm
.name
, i
.hle_prefix
);
3336 if (i
.prefix
[LOCK_PREFIX
])
3338 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3342 case HLEPrefixRelease
:
3343 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3345 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3349 if (i
.mem_operands
== 0
3350 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3352 as_bad (_("memory destination needed for instruction `%s'"
3353 " after `xrelease'"), i
.tm
.name
);
3360 /* This is the guts of the machine-dependent assembler. LINE points to a
3361 machine dependent instruction. This function is supposed to emit
3362 the frags/bytes it assembles to. */
3365 md_assemble (char *line
)
3368 char mnemonic
[MAX_MNEM_SIZE
];
3369 const insn_template
*t
;
3371 /* Initialize globals. */
3372 memset (&i
, '\0', sizeof (i
));
3373 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3374 i
.reloc
[j
] = NO_RELOC
;
3375 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3376 memset (im_expressions
, '\0', sizeof (im_expressions
));
3377 save_stack_p
= save_stack
;
3379 /* First parse an instruction mnemonic & call i386_operand for the operands.
3380 We assume that the scrubber has arranged it so that line[0] is the valid
3381 start of a (possibly prefixed) mnemonic. */
3383 line
= parse_insn (line
, mnemonic
);
3387 line
= parse_operands (line
, mnemonic
);
3392 /* Now we've parsed the mnemonic into a set of templates, and have the
3393 operands at hand. */
3395 /* All intel opcodes have reversed operands except for "bound" and
3396 "enter". We also don't reverse intersegment "jmp" and "call"
3397 instructions with 2 immediate operands so that the immediate segment
3398 precedes the offset, as it does when in AT&T mode. */
3401 && (strcmp (mnemonic
, "bound") != 0)
3402 && (strcmp (mnemonic
, "invlpga") != 0)
3403 && !(operand_type_check (i
.types
[0], imm
)
3404 && operand_type_check (i
.types
[1], imm
)))
3407 /* The order of the immediates should be reversed
3408 for 2 immediates extrq and insertq instructions */
3409 if (i
.imm_operands
== 2
3410 && (strcmp (mnemonic
, "extrq") == 0
3411 || strcmp (mnemonic
, "insertq") == 0))
3412 swap_2_operands (0, 1);
3417 /* Don't optimize displacement for movabs since it only takes 64bit
3420 && i
.disp_encoding
!= disp_encoding_32bit
3421 && (flag_code
!= CODE_64BIT
3422 || strcmp (mnemonic
, "movabs") != 0))
3425 /* Next, we find a template that matches the given insn,
3426 making sure the overlap of the given operands types is consistent
3427 with the template operand types. */
3429 if (!(t
= match_template ()))
3432 if (sse_check
!= check_none
3433 && !i
.tm
.opcode_modifier
.noavx
3434 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3435 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3436 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3437 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3438 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3439 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3441 (sse_check
== check_warning
3443 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3446 /* Zap movzx and movsx suffix. The suffix has been set from
3447 "word ptr" or "byte ptr" on the source operand in Intel syntax
3448 or extracted from mnemonic in AT&T syntax. But we'll use
3449 the destination register to choose the suffix for encoding. */
3450 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3452 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3453 there is no suffix, the default will be byte extension. */
3454 if (i
.reg_operands
!= 2
3457 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3462 if (i
.tm
.opcode_modifier
.fwait
)
3463 if (!add_prefix (FWAIT_OPCODE
))
3466 /* Check if REP prefix is OK. */
3467 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3469 as_bad (_("invalid instruction `%s' after `%s'"),
3470 i
.tm
.name
, i
.rep_prefix
);
3474 /* Check for lock without a lockable instruction. Destination operand
3475 must be memory unless it is xchg (0x86). */
3476 if (i
.prefix
[LOCK_PREFIX
]
3477 && (!i
.tm
.opcode_modifier
.islockable
3478 || i
.mem_operands
== 0
3479 || (i
.tm
.base_opcode
!= 0x86
3480 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3482 as_bad (_("expecting lockable instruction after `lock'"));
3486 /* Check if HLE prefix is OK. */
3487 if (i
.hle_prefix
&& !check_hle ())
3490 /* Check BND prefix. */
3491 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3492 as_bad (_("expecting valid branch instruction after `bnd'"));
3494 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3495 && flag_code
== CODE_64BIT
3496 && i
.prefix
[ADDR_PREFIX
])
3497 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3499 /* Insert BND prefix. */
3501 && i
.tm
.opcode_modifier
.bndprefixok
3502 && !i
.prefix
[BND_PREFIX
])
3503 add_prefix (BND_PREFIX_OPCODE
);
3505 /* Check string instruction segment overrides. */
3506 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3508 if (!check_string ())
3510 i
.disp_operands
= 0;
3513 if (!process_suffix ())
3516 /* Update operand types. */
3517 for (j
= 0; j
< i
.operands
; j
++)
3518 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3520 /* Make still unresolved immediate matches conform to size of immediate
3521 given in i.suffix. */
3522 if (!finalize_imm ())
3525 if (i
.types
[0].bitfield
.imm1
)
3526 i
.imm_operands
= 0; /* kludge for shift insns. */
3528 /* We only need to check those implicit registers for instructions
3529 with 3 operands or less. */
3530 if (i
.operands
<= 3)
3531 for (j
= 0; j
< i
.operands
; j
++)
3532 if (i
.types
[j
].bitfield
.inoutportreg
3533 || i
.types
[j
].bitfield
.shiftcount
3534 || i
.types
[j
].bitfield
.acc
3535 || i
.types
[j
].bitfield
.floatacc
)
3538 /* ImmExt should be processed after SSE2AVX. */
3539 if (!i
.tm
.opcode_modifier
.sse2avx
3540 && i
.tm
.opcode_modifier
.immext
)
3543 /* For insns with operands there are more diddles to do to the opcode. */
3546 if (!process_operands ())
3549 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3551 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3552 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3555 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3557 if (flag_code
== CODE_16BIT
)
3559 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3564 if (i
.tm
.opcode_modifier
.vex
)
3565 build_vex_prefix (t
);
3567 build_evex_prefix ();
3570 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3571 instructions may define INT_OPCODE as well, so avoid this corner
3572 case for those instructions that use MODRM. */
3573 if (i
.tm
.base_opcode
== INT_OPCODE
3574 && !i
.tm
.opcode_modifier
.modrm
3575 && i
.op
[0].imms
->X_add_number
== 3)
3577 i
.tm
.base_opcode
= INT3_OPCODE
;
3581 if ((i
.tm
.opcode_modifier
.jump
3582 || i
.tm
.opcode_modifier
.jumpbyte
3583 || i
.tm
.opcode_modifier
.jumpdword
)
3584 && i
.op
[0].disps
->X_op
== O_constant
)
3586 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3587 the absolute address given by the constant. Since ix86 jumps and
3588 calls are pc relative, we need to generate a reloc. */
3589 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3590 i
.op
[0].disps
->X_op
= O_symbol
;
3593 if (i
.tm
.opcode_modifier
.rex64
)
3596 /* For 8 bit registers we need an empty rex prefix. Also if the
3597 instruction already has a prefix, we need to convert old
3598 registers to new ones. */
3600 if ((i
.types
[0].bitfield
.reg8
3601 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3602 || (i
.types
[1].bitfield
.reg8
3603 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3604 || ((i
.types
[0].bitfield
.reg8
3605 || i
.types
[1].bitfield
.reg8
)
3610 i
.rex
|= REX_OPCODE
;
3611 for (x
= 0; x
< 2; x
++)
3613 /* Look for 8 bit operand that uses old registers. */
3614 if (i
.types
[x
].bitfield
.reg8
3615 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3617 /* In case it is "hi" register, give up. */
3618 if (i
.op
[x
].regs
->reg_num
> 3)
3619 as_bad (_("can't encode register '%s%s' in an "
3620 "instruction requiring REX prefix."),
3621 register_prefix
, i
.op
[x
].regs
->reg_name
);
3623 /* Otherwise it is equivalent to the extended register.
3624 Since the encoding doesn't change this is merely
3625 cosmetic cleanup for debug output. */
3627 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3633 add_prefix (REX_OPCODE
| i
.rex
);
3635 /* We are ready to output the insn. */
3640 parse_insn (char *line
, char *mnemonic
)
3643 char *token_start
= l
;
3646 const insn_template
*t
;
3652 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3657 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3659 as_bad (_("no such instruction: `%s'"), token_start
);
3664 if (!is_space_char (*l
)
3665 && *l
!= END_OF_INSN
3667 || (*l
!= PREFIX_SEPARATOR
3670 as_bad (_("invalid character %s in mnemonic"),
3671 output_invalid (*l
));
3674 if (token_start
== l
)
3676 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3677 as_bad (_("expecting prefix; got nothing"));
3679 as_bad (_("expecting mnemonic; got nothing"));
3683 /* Look up instruction (or prefix) via hash table. */
3684 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3686 if (*l
!= END_OF_INSN
3687 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3688 && current_templates
3689 && current_templates
->start
->opcode_modifier
.isprefix
)
3691 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3693 as_bad ((flag_code
!= CODE_64BIT
3694 ? _("`%s' is only supported in 64-bit mode")
3695 : _("`%s' is not supported in 64-bit mode")),
3696 current_templates
->start
->name
);
3699 /* If we are in 16-bit mode, do not allow addr16 or data16.
3700 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3701 if ((current_templates
->start
->opcode_modifier
.size16
3702 || current_templates
->start
->opcode_modifier
.size32
)
3703 && flag_code
!= CODE_64BIT
3704 && (current_templates
->start
->opcode_modifier
.size32
3705 ^ (flag_code
== CODE_16BIT
)))
3707 as_bad (_("redundant %s prefix"),
3708 current_templates
->start
->name
);
3711 /* Add prefix, checking for repeated prefixes. */
3712 switch (add_prefix (current_templates
->start
->base_opcode
))
3717 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3718 i
.hle_prefix
= current_templates
->start
->name
;
3719 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3720 i
.bnd_prefix
= current_templates
->start
->name
;
3722 i
.rep_prefix
= current_templates
->start
->name
;
3727 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3734 if (!current_templates
)
3736 /* Check if we should swap operand or force 32bit displacement in
3738 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3740 else if (mnem_p
- 3 == dot_p
3743 i
.disp_encoding
= disp_encoding_8bit
;
3744 else if (mnem_p
- 4 == dot_p
3748 i
.disp_encoding
= disp_encoding_32bit
;
3753 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3756 if (!current_templates
)
3759 /* See if we can get a match by trimming off a suffix. */
3762 case WORD_MNEM_SUFFIX
:
3763 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3764 i
.suffix
= SHORT_MNEM_SUFFIX
;
3766 case BYTE_MNEM_SUFFIX
:
3767 case QWORD_MNEM_SUFFIX
:
3768 i
.suffix
= mnem_p
[-1];
3770 current_templates
= (const templates
*) hash_find (op_hash
,
3773 case SHORT_MNEM_SUFFIX
:
3774 case LONG_MNEM_SUFFIX
:
3777 i
.suffix
= mnem_p
[-1];
3779 current_templates
= (const templates
*) hash_find (op_hash
,
3788 if (intel_float_operand (mnemonic
) == 1)
3789 i
.suffix
= SHORT_MNEM_SUFFIX
;
3791 i
.suffix
= LONG_MNEM_SUFFIX
;
3793 current_templates
= (const templates
*) hash_find (op_hash
,
3798 if (!current_templates
)
3800 as_bad (_("no such instruction: `%s'"), token_start
);
3805 if (current_templates
->start
->opcode_modifier
.jump
3806 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3808 /* Check for a branch hint. We allow ",pt" and ",pn" for
3809 predict taken and predict not taken respectively.
3810 I'm not sure that branch hints actually do anything on loop
3811 and jcxz insns (JumpByte) for current Pentium4 chips. They
3812 may work in the future and it doesn't hurt to accept them
3814 if (l
[0] == ',' && l
[1] == 'p')
3818 if (!add_prefix (DS_PREFIX_OPCODE
))
3822 else if (l
[2] == 'n')
3824 if (!add_prefix (CS_PREFIX_OPCODE
))
3830 /* Any other comma loses. */
3833 as_bad (_("invalid character %s in mnemonic"),
3834 output_invalid (*l
));
3838 /* Check if instruction is supported on specified architecture. */
3840 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3842 supported
|= cpu_flags_match (t
);
3843 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3847 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3849 as_bad (flag_code
== CODE_64BIT
3850 ? _("`%s' is not supported in 64-bit mode")
3851 : _("`%s' is only supported in 64-bit mode"),
3852 current_templates
->start
->name
);
3855 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3857 as_bad (_("`%s' is not supported on `%s%s'"),
3858 current_templates
->start
->name
,
3859 cpu_arch_name
? cpu_arch_name
: default_arch
,
3860 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3865 if (!cpu_arch_flags
.bitfield
.cpui386
3866 && (flag_code
!= CODE_16BIT
))
3868 as_warn (_("use .code16 to ensure correct addressing mode"));
3875 parse_operands (char *l
, const char *mnemonic
)
3879 /* 1 if operand is pending after ','. */
3880 unsigned int expecting_operand
= 0;
3882 /* Non-zero if operand parens not balanced. */
3883 unsigned int paren_not_balanced
;
3885 while (*l
!= END_OF_INSN
)
3887 /* Skip optional white space before operand. */
3888 if (is_space_char (*l
))
3890 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3892 as_bad (_("invalid character %s before operand %d"),
3893 output_invalid (*l
),
3897 token_start
= l
; /* after white space */
3898 paren_not_balanced
= 0;
3899 while (paren_not_balanced
|| *l
!= ',')
3901 if (*l
== END_OF_INSN
)
3903 if (paren_not_balanced
)
3906 as_bad (_("unbalanced parenthesis in operand %d."),
3909 as_bad (_("unbalanced brackets in operand %d."),
3914 break; /* we are done */
3916 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3918 as_bad (_("invalid character %s in operand %d"),
3919 output_invalid (*l
),
3926 ++paren_not_balanced
;
3928 --paren_not_balanced
;
3933 ++paren_not_balanced
;
3935 --paren_not_balanced
;
3939 if (l
!= token_start
)
3940 { /* Yes, we've read in another operand. */
3941 unsigned int operand_ok
;
3942 this_operand
= i
.operands
++;
3943 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3944 if (i
.operands
> MAX_OPERANDS
)
3946 as_bad (_("spurious operands; (%d operands/instruction max)"),
3950 /* Now parse operand adding info to 'i' as we go along. */
3951 END_STRING_AND_SAVE (l
);
3955 i386_intel_operand (token_start
,
3956 intel_float_operand (mnemonic
));
3958 operand_ok
= i386_att_operand (token_start
);
3960 RESTORE_END_STRING (l
);
3966 if (expecting_operand
)
3968 expecting_operand_after_comma
:
3969 as_bad (_("expecting operand after ','; got nothing"));
3974 as_bad (_("expecting operand before ','; got nothing"));
3979 /* Now *l must be either ',' or END_OF_INSN. */
3982 if (*++l
== END_OF_INSN
)
3984 /* Just skip it, if it's \n complain. */
3985 goto expecting_operand_after_comma
;
3987 expecting_operand
= 1;
3994 swap_2_operands (int xchg1
, int xchg2
)
3996 union i386_op temp_op
;
3997 i386_operand_type temp_type
;
3998 enum bfd_reloc_code_real temp_reloc
;
4000 temp_type
= i
.types
[xchg2
];
4001 i
.types
[xchg2
] = i
.types
[xchg1
];
4002 i
.types
[xchg1
] = temp_type
;
4003 temp_op
= i
.op
[xchg2
];
4004 i
.op
[xchg2
] = i
.op
[xchg1
];
4005 i
.op
[xchg1
] = temp_op
;
4006 temp_reloc
= i
.reloc
[xchg2
];
4007 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4008 i
.reloc
[xchg1
] = temp_reloc
;
4012 if (i
.mask
->operand
== xchg1
)
4013 i
.mask
->operand
= xchg2
;
4014 else if (i
.mask
->operand
== xchg2
)
4015 i
.mask
->operand
= xchg1
;
4019 if (i
.broadcast
->operand
== xchg1
)
4020 i
.broadcast
->operand
= xchg2
;
4021 else if (i
.broadcast
->operand
== xchg2
)
4022 i
.broadcast
->operand
= xchg1
;
4026 if (i
.rounding
->operand
== xchg1
)
4027 i
.rounding
->operand
= xchg2
;
4028 else if (i
.rounding
->operand
== xchg2
)
4029 i
.rounding
->operand
= xchg1
;
4034 swap_operands (void)
4040 swap_2_operands (1, i
.operands
- 2);
4043 swap_2_operands (0, i
.operands
- 1);
4049 if (i
.mem_operands
== 2)
4051 const seg_entry
*temp_seg
;
4052 temp_seg
= i
.seg
[0];
4053 i
.seg
[0] = i
.seg
[1];
4054 i
.seg
[1] = temp_seg
;
4058 /* Try to ensure constant immediates are represented in the smallest
4063 char guess_suffix
= 0;
4067 guess_suffix
= i
.suffix
;
4068 else if (i
.reg_operands
)
4070 /* Figure out a suffix from the last register operand specified.
4071 We can't do this properly yet, ie. excluding InOutPortReg,
4072 but the following works for instructions with immediates.
4073 In any case, we can't set i.suffix yet. */
4074 for (op
= i
.operands
; --op
>= 0;)
4075 if (i
.types
[op
].bitfield
.reg8
)
4077 guess_suffix
= BYTE_MNEM_SUFFIX
;
4080 else if (i
.types
[op
].bitfield
.reg16
)
4082 guess_suffix
= WORD_MNEM_SUFFIX
;
4085 else if (i
.types
[op
].bitfield
.reg32
)
4087 guess_suffix
= LONG_MNEM_SUFFIX
;
4090 else if (i
.types
[op
].bitfield
.reg64
)
4092 guess_suffix
= QWORD_MNEM_SUFFIX
;
4096 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4097 guess_suffix
= WORD_MNEM_SUFFIX
;
4099 for (op
= i
.operands
; --op
>= 0;)
4100 if (operand_type_check (i
.types
[op
], imm
))
4102 switch (i
.op
[op
].imms
->X_op
)
4105 /* If a suffix is given, this operand may be shortened. */
4106 switch (guess_suffix
)
4108 case LONG_MNEM_SUFFIX
:
4109 i
.types
[op
].bitfield
.imm32
= 1;
4110 i
.types
[op
].bitfield
.imm64
= 1;
4112 case WORD_MNEM_SUFFIX
:
4113 i
.types
[op
].bitfield
.imm16
= 1;
4114 i
.types
[op
].bitfield
.imm32
= 1;
4115 i
.types
[op
].bitfield
.imm32s
= 1;
4116 i
.types
[op
].bitfield
.imm64
= 1;
4118 case BYTE_MNEM_SUFFIX
:
4119 i
.types
[op
].bitfield
.imm8
= 1;
4120 i
.types
[op
].bitfield
.imm8s
= 1;
4121 i
.types
[op
].bitfield
.imm16
= 1;
4122 i
.types
[op
].bitfield
.imm32
= 1;
4123 i
.types
[op
].bitfield
.imm32s
= 1;
4124 i
.types
[op
].bitfield
.imm64
= 1;
4128 /* If this operand is at most 16 bits, convert it
4129 to a signed 16 bit number before trying to see
4130 whether it will fit in an even smaller size.
4131 This allows a 16-bit operand such as $0xffe0 to
4132 be recognised as within Imm8S range. */
4133 if ((i
.types
[op
].bitfield
.imm16
)
4134 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4136 i
.op
[op
].imms
->X_add_number
=
4137 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4139 if ((i
.types
[op
].bitfield
.imm32
)
4140 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4143 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4144 ^ ((offsetT
) 1 << 31))
4145 - ((offsetT
) 1 << 31));
4148 = operand_type_or (i
.types
[op
],
4149 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4151 /* We must avoid matching of Imm32 templates when 64bit
4152 only immediate is available. */
4153 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4154 i
.types
[op
].bitfield
.imm32
= 0;
4161 /* Symbols and expressions. */
4163 /* Convert symbolic operand to proper sizes for matching, but don't
4164 prevent matching a set of insns that only supports sizes other
4165 than those matching the insn suffix. */
4167 i386_operand_type mask
, allowed
;
4168 const insn_template
*t
;
4170 operand_type_set (&mask
, 0);
4171 operand_type_set (&allowed
, 0);
4173 for (t
= current_templates
->start
;
4174 t
< current_templates
->end
;
4176 allowed
= operand_type_or (allowed
,
4177 t
->operand_types
[op
]);
4178 switch (guess_suffix
)
4180 case QWORD_MNEM_SUFFIX
:
4181 mask
.bitfield
.imm64
= 1;
4182 mask
.bitfield
.imm32s
= 1;
4184 case LONG_MNEM_SUFFIX
:
4185 mask
.bitfield
.imm32
= 1;
4187 case WORD_MNEM_SUFFIX
:
4188 mask
.bitfield
.imm16
= 1;
4190 case BYTE_MNEM_SUFFIX
:
4191 mask
.bitfield
.imm8
= 1;
4196 allowed
= operand_type_and (mask
, allowed
);
4197 if (!operand_type_all_zero (&allowed
))
4198 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4205 /* Try to use the smallest displacement type too. */
4207 optimize_disp (void)
4211 for (op
= i
.operands
; --op
>= 0;)
4212 if (operand_type_check (i
.types
[op
], disp
))
4214 if (i
.op
[op
].disps
->X_op
== O_constant
)
4216 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4218 if (i
.types
[op
].bitfield
.disp16
4219 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4221 /* If this operand is at most 16 bits, convert
4222 to a signed 16 bit number and don't use 64bit
4224 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4225 i
.types
[op
].bitfield
.disp64
= 0;
4227 if (i
.types
[op
].bitfield
.disp32
4228 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4230 /* If this operand is at most 32 bits, convert
4231 to a signed 32 bit number and don't use 64bit
4233 op_disp
&= (((offsetT
) 2 << 31) - 1);
4234 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4235 i
.types
[op
].bitfield
.disp64
= 0;
4237 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4239 i
.types
[op
].bitfield
.disp8
= 0;
4240 i
.types
[op
].bitfield
.disp16
= 0;
4241 i
.types
[op
].bitfield
.disp32
= 0;
4242 i
.types
[op
].bitfield
.disp32s
= 0;
4243 i
.types
[op
].bitfield
.disp64
= 0;
4247 else if (flag_code
== CODE_64BIT
)
4249 if (fits_in_signed_long (op_disp
))
4251 i
.types
[op
].bitfield
.disp64
= 0;
4252 i
.types
[op
].bitfield
.disp32s
= 1;
4254 if (i
.prefix
[ADDR_PREFIX
]
4255 && fits_in_unsigned_long (op_disp
))
4256 i
.types
[op
].bitfield
.disp32
= 1;
4258 if ((i
.types
[op
].bitfield
.disp32
4259 || i
.types
[op
].bitfield
.disp32s
4260 || i
.types
[op
].bitfield
.disp16
)
4261 && fits_in_signed_byte (op_disp
))
4262 i
.types
[op
].bitfield
.disp8
= 1;
4264 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4265 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4267 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4268 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4269 i
.types
[op
].bitfield
.disp8
= 0;
4270 i
.types
[op
].bitfield
.disp16
= 0;
4271 i
.types
[op
].bitfield
.disp32
= 0;
4272 i
.types
[op
].bitfield
.disp32s
= 0;
4273 i
.types
[op
].bitfield
.disp64
= 0;
4276 /* We only support 64bit displacement on constants. */
4277 i
.types
[op
].bitfield
.disp64
= 0;
4281 /* Check if operands are valid for the instruction. */
4284 check_VecOperands (const insn_template
*t
)
4288 /* Without VSIB byte, we can't have a vector register for index. */
4289 if (!t
->opcode_modifier
.vecsib
4291 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4292 || i
.index_reg
->reg_type
.bitfield
.regymm
4293 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4295 i
.error
= unsupported_vector_index_register
;
4299 /* Check if default mask is allowed. */
4300 if (t
->opcode_modifier
.nodefmask
4301 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4303 i
.error
= no_default_mask
;
4307 /* For VSIB byte, we need a vector register for index, and all vector
4308 registers must be distinct. */
4309 if (t
->opcode_modifier
.vecsib
)
4312 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4313 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4314 || (t
->opcode_modifier
.vecsib
== VecSIB256
4315 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4316 || (t
->opcode_modifier
.vecsib
== VecSIB512
4317 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4319 i
.error
= invalid_vsib_address
;
4323 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4324 if (i
.reg_operands
== 2 && !i
.mask
)
4326 gas_assert (i
.types
[0].bitfield
.regxmm
4327 || i
.types
[0].bitfield
.regymm
);
4328 gas_assert (i
.types
[2].bitfield
.regxmm
4329 || i
.types
[2].bitfield
.regymm
);
4330 if (operand_check
== check_none
)
4332 if (register_number (i
.op
[0].regs
)
4333 != register_number (i
.index_reg
)
4334 && register_number (i
.op
[2].regs
)
4335 != register_number (i
.index_reg
)
4336 && register_number (i
.op
[0].regs
)
4337 != register_number (i
.op
[2].regs
))
4339 if (operand_check
== check_error
)
4341 i
.error
= invalid_vector_register_set
;
4344 as_warn (_("mask, index, and destination registers should be distinct"));
4346 else if (i
.reg_operands
== 1 && i
.mask
)
4348 if ((i
.types
[1].bitfield
.regymm
4349 || i
.types
[1].bitfield
.regzmm
)
4350 && (register_number (i
.op
[1].regs
)
4351 == register_number (i
.index_reg
)))
4353 if (operand_check
== check_error
)
4355 i
.error
= invalid_vector_register_set
;
4358 if (operand_check
!= check_none
)
4359 as_warn (_("index and destination registers should be distinct"));
4364 /* Check if broadcast is supported by the instruction and is applied
4365 to the memory operand. */
4368 int broadcasted_opnd_size
;
4370 /* Check if specified broadcast is supported in this instruction,
4371 and it's applied to memory operand of DWORD or QWORD type,
4372 depending on VecESize. */
4373 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4374 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4375 || (t
->opcode_modifier
.vecesize
== 0
4376 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4377 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4378 || (t
->opcode_modifier
.vecesize
== 1
4379 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4380 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4383 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4384 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4385 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4386 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4387 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4388 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4389 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4390 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4391 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4395 if ((broadcasted_opnd_size
== 256
4396 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4397 || (broadcasted_opnd_size
== 512
4398 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4401 i
.error
= unsupported_broadcast
;
4405 /* If broadcast is supported in this instruction, we need to check if
4406 operand of one-element size isn't specified without broadcast. */
4407 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4409 /* Find memory operand. */
4410 for (op
= 0; op
< i
.operands
; op
++)
4411 if (operand_type_check (i
.types
[op
], anymem
))
4413 gas_assert (op
< i
.operands
);
4414 /* Check size of the memory operand. */
4415 if ((t
->opcode_modifier
.vecesize
== 0
4416 && i
.types
[op
].bitfield
.dword
)
4417 || (t
->opcode_modifier
.vecesize
== 1
4418 && i
.types
[op
].bitfield
.qword
))
4420 i
.error
= broadcast_needed
;
4425 /* Check if requested masking is supported. */
4427 && (!t
->opcode_modifier
.masking
4429 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4431 i
.error
= unsupported_masking
;
4435 /* Check if masking is applied to dest operand. */
4436 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4438 i
.error
= mask_not_on_destination
;
4445 if ((i
.rounding
->type
!= saeonly
4446 && !t
->opcode_modifier
.staticrounding
)
4447 || (i
.rounding
->type
== saeonly
4448 && (t
->opcode_modifier
.staticrounding
4449 || !t
->opcode_modifier
.sae
)))
4451 i
.error
= unsupported_rc_sae
;
4454 /* If the instruction has several immediate operands and one of
4455 them is rounding, the rounding operand should be the last
4456 immediate operand. */
4457 if (i
.imm_operands
> 1
4458 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4460 i
.error
= rc_sae_operand_not_last_imm
;
4465 /* Check vector Disp8 operand. */
4466 if (t
->opcode_modifier
.disp8memshift
)
4469 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4471 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4473 for (op
= 0; op
< i
.operands
; op
++)
4474 if (operand_type_check (i
.types
[op
], disp
)
4475 && i
.op
[op
].disps
->X_op
== O_constant
)
4477 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4478 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4479 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4482 i
.types
[op
].bitfield
.vec_disp8
= 1;
4485 /* Vector insn can only have Vec_Disp8/Disp32 in
4486 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4488 i
.types
[op
].bitfield
.disp8
= 0;
4489 if (flag_code
!= CODE_16BIT
)
4490 i
.types
[op
].bitfield
.disp16
= 0;
4493 else if (flag_code
!= CODE_16BIT
)
4495 /* One form of this instruction supports vector Disp8.
4496 Try vector Disp8 if we need to use Disp32. */
4497 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4499 i
.error
= try_vector_disp8
;
4511 /* Check if operands are valid for the instruction. Update VEX
4515 VEX_check_operands (const insn_template
*t
)
4517 /* VREX is only valid with EVEX prefix. */
4518 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4520 i
.error
= invalid_register_operand
;
4524 if (!t
->opcode_modifier
.vex
)
4527 /* Only check VEX_Imm4, which must be the first operand. */
4528 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4530 if (i
.op
[0].imms
->X_op
!= O_constant
4531 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4537 /* Turn off Imm8 so that update_imm won't complain. */
4538 i
.types
[0] = vec_imm4
;
4544 static const insn_template
*
4545 match_template (void)
4547 /* Points to template once we've found it. */
4548 const insn_template
*t
;
4549 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4550 i386_operand_type overlap4
;
4551 unsigned int found_reverse_match
;
4552 i386_opcode_modifier suffix_check
;
4553 i386_operand_type operand_types
[MAX_OPERANDS
];
4554 int addr_prefix_disp
;
4556 unsigned int found_cpu_match
;
4557 unsigned int check_register
;
4558 enum i386_error specific_error
= 0;
4560 #if MAX_OPERANDS != 5
4561 # error "MAX_OPERANDS must be 5."
4564 found_reverse_match
= 0;
4565 addr_prefix_disp
= -1;
4567 memset (&suffix_check
, 0, sizeof (suffix_check
));
4568 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4569 suffix_check
.no_bsuf
= 1;
4570 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4571 suffix_check
.no_wsuf
= 1;
4572 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4573 suffix_check
.no_ssuf
= 1;
4574 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4575 suffix_check
.no_lsuf
= 1;
4576 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4577 suffix_check
.no_qsuf
= 1;
4578 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4579 suffix_check
.no_ldsuf
= 1;
4581 /* Must have right number of operands. */
4582 i
.error
= number_of_operands_mismatch
;
4584 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4586 addr_prefix_disp
= -1;
4588 if (i
.operands
!= t
->operands
)
4591 /* Check processor support. */
4592 i
.error
= unsupported
;
4593 found_cpu_match
= (cpu_flags_match (t
)
4594 == CPU_FLAGS_PERFECT_MATCH
);
4595 if (!found_cpu_match
)
4598 /* Check old gcc support. */
4599 i
.error
= old_gcc_only
;
4600 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4603 /* Check AT&T mnemonic. */
4604 i
.error
= unsupported_with_intel_mnemonic
;
4605 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4608 /* Check AT&T/Intel syntax. */
4609 i
.error
= unsupported_syntax
;
4610 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4611 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4614 /* Check the suffix, except for some instructions in intel mode. */
4615 i
.error
= invalid_instruction_suffix
;
4616 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4617 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4618 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4619 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4620 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4621 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4622 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4625 if (!operand_size_match (t
))
4628 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4629 operand_types
[j
] = t
->operand_types
[j
];
4631 /* In general, don't allow 64-bit operands in 32-bit mode. */
4632 if (i
.suffix
== QWORD_MNEM_SUFFIX
4633 && flag_code
!= CODE_64BIT
4635 ? (!t
->opcode_modifier
.ignoresize
4636 && !intel_float_operand (t
->name
))
4637 : intel_float_operand (t
->name
) != 2)
4638 && ((!operand_types
[0].bitfield
.regmmx
4639 && !operand_types
[0].bitfield
.regxmm
4640 && !operand_types
[0].bitfield
.regymm
4641 && !operand_types
[0].bitfield
.regzmm
)
4642 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4643 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4644 && operand_types
[t
->operands
> 1].bitfield
.regymm
4645 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4646 && (t
->base_opcode
!= 0x0fc7
4647 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4650 /* In general, don't allow 32-bit operands on pre-386. */
4651 else if (i
.suffix
== LONG_MNEM_SUFFIX
4652 && !cpu_arch_flags
.bitfield
.cpui386
4654 ? (!t
->opcode_modifier
.ignoresize
4655 && !intel_float_operand (t
->name
))
4656 : intel_float_operand (t
->name
) != 2)
4657 && ((!operand_types
[0].bitfield
.regmmx
4658 && !operand_types
[0].bitfield
.regxmm
)
4659 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4660 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4663 /* Do not verify operands when there are none. */
4667 /* We've found a match; break out of loop. */
4671 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4672 into Disp32/Disp16/Disp32 operand. */
4673 if (i
.prefix
[ADDR_PREFIX
] != 0)
4675 /* There should be only one Disp operand. */
4679 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4681 if (operand_types
[j
].bitfield
.disp16
)
4683 addr_prefix_disp
= j
;
4684 operand_types
[j
].bitfield
.disp32
= 1;
4685 operand_types
[j
].bitfield
.disp16
= 0;
4691 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4693 if (operand_types
[j
].bitfield
.disp32
)
4695 addr_prefix_disp
= j
;
4696 operand_types
[j
].bitfield
.disp32
= 0;
4697 operand_types
[j
].bitfield
.disp16
= 1;
4703 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4705 if (operand_types
[j
].bitfield
.disp64
)
4707 addr_prefix_disp
= j
;
4708 operand_types
[j
].bitfield
.disp64
= 0;
4709 operand_types
[j
].bitfield
.disp32
= 1;
4717 /* We check register size if needed. */
4718 check_register
= t
->opcode_modifier
.checkregsize
;
4719 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4720 switch (t
->operands
)
4723 if (!operand_type_match (overlap0
, i
.types
[0]))
4727 /* xchg %eax, %eax is a special case. It is an aliase for nop
4728 only in 32bit mode and we can use opcode 0x90. In 64bit
4729 mode, we can't use 0x90 for xchg %eax, %eax since it should
4730 zero-extend %eax to %rax. */
4731 if (flag_code
== CODE_64BIT
4732 && t
->base_opcode
== 0x90
4733 && operand_type_equal (&i
.types
[0], &acc32
)
4734 && operand_type_equal (&i
.types
[1], &acc32
))
4738 /* If we swap operand in encoding, we either match
4739 the next one or reverse direction of operands. */
4740 if (t
->opcode_modifier
.s
)
4742 else if (t
->opcode_modifier
.d
)
4747 /* If we swap operand in encoding, we match the next one. */
4748 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4752 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4753 if (!operand_type_match (overlap0
, i
.types
[0])
4754 || !operand_type_match (overlap1
, i
.types
[1])
4756 && !operand_type_register_match (overlap0
, i
.types
[0],
4758 overlap1
, i
.types
[1],
4761 /* Check if other direction is valid ... */
4762 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4766 /* Try reversing direction of operands. */
4767 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4768 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4769 if (!operand_type_match (overlap0
, i
.types
[0])
4770 || !operand_type_match (overlap1
, i
.types
[1])
4772 && !operand_type_register_match (overlap0
,
4779 /* Does not match either direction. */
4782 /* found_reverse_match holds which of D or FloatDR
4784 if (t
->opcode_modifier
.d
)
4785 found_reverse_match
= Opcode_D
;
4786 else if (t
->opcode_modifier
.floatd
)
4787 found_reverse_match
= Opcode_FloatD
;
4789 found_reverse_match
= 0;
4790 if (t
->opcode_modifier
.floatr
)
4791 found_reverse_match
|= Opcode_FloatR
;
4795 /* Found a forward 2 operand match here. */
4796 switch (t
->operands
)
4799 overlap4
= operand_type_and (i
.types
[4],
4802 overlap3
= operand_type_and (i
.types
[3],
4805 overlap2
= operand_type_and (i
.types
[2],
4810 switch (t
->operands
)
4813 if (!operand_type_match (overlap4
, i
.types
[4])
4814 || !operand_type_register_match (overlap3
,
4822 if (!operand_type_match (overlap3
, i
.types
[3])
4824 && !operand_type_register_match (overlap2
,
4832 /* Here we make use of the fact that there are no
4833 reverse match 3 operand instructions, and all 3
4834 operand instructions only need to be checked for
4835 register consistency between operands 2 and 3. */
4836 if (!operand_type_match (overlap2
, i
.types
[2])
4838 && !operand_type_register_match (overlap1
,
4848 /* Found either forward/reverse 2, 3 or 4 operand match here:
4849 slip through to break. */
4851 if (!found_cpu_match
)
4853 found_reverse_match
= 0;
4857 /* Check if vector and VEX operands are valid. */
4858 if (check_VecOperands (t
) || VEX_check_operands (t
))
4860 specific_error
= i
.error
;
4864 /* We've found a match; break out of loop. */
4868 if (t
== current_templates
->end
)
4870 /* We found no match. */
4871 const char *err_msg
;
4872 switch (specific_error
? specific_error
: i
.error
)
4876 case operand_size_mismatch
:
4877 err_msg
= _("operand size mismatch");
4879 case operand_type_mismatch
:
4880 err_msg
= _("operand type mismatch");
4882 case register_type_mismatch
:
4883 err_msg
= _("register type mismatch");
4885 case number_of_operands_mismatch
:
4886 err_msg
= _("number of operands mismatch");
4888 case invalid_instruction_suffix
:
4889 err_msg
= _("invalid instruction suffix");
4892 err_msg
= _("constant doesn't fit in 4 bits");
4895 err_msg
= _("only supported with old gcc");
4897 case unsupported_with_intel_mnemonic
:
4898 err_msg
= _("unsupported with Intel mnemonic");
4900 case unsupported_syntax
:
4901 err_msg
= _("unsupported syntax");
4904 as_bad (_("unsupported instruction `%s'"),
4905 current_templates
->start
->name
);
4907 case invalid_vsib_address
:
4908 err_msg
= _("invalid VSIB address");
4910 case invalid_vector_register_set
:
4911 err_msg
= _("mask, index, and destination registers must be distinct");
4913 case unsupported_vector_index_register
:
4914 err_msg
= _("unsupported vector index register");
4916 case unsupported_broadcast
:
4917 err_msg
= _("unsupported broadcast");
4919 case broadcast_not_on_src_operand
:
4920 err_msg
= _("broadcast not on source memory operand");
4922 case broadcast_needed
:
4923 err_msg
= _("broadcast is needed for operand of such type");
4925 case unsupported_masking
:
4926 err_msg
= _("unsupported masking");
4928 case mask_not_on_destination
:
4929 err_msg
= _("mask not on destination operand");
4931 case no_default_mask
:
4932 err_msg
= _("default mask isn't allowed");
4934 case unsupported_rc_sae
:
4935 err_msg
= _("unsupported static rounding/sae");
4937 case rc_sae_operand_not_last_imm
:
4939 err_msg
= _("RC/SAE operand must precede immediate operands");
4941 err_msg
= _("RC/SAE operand must follow immediate operands");
4943 case invalid_register_operand
:
4944 err_msg
= _("invalid register operand");
4947 as_bad (_("%s for `%s'"), err_msg
,
4948 current_templates
->start
->name
);
4952 if (!quiet_warnings
)
4955 && (i
.types
[0].bitfield
.jumpabsolute
4956 != operand_types
[0].bitfield
.jumpabsolute
))
4958 as_warn (_("indirect %s without `*'"), t
->name
);
4961 if (t
->opcode_modifier
.isprefix
4962 && t
->opcode_modifier
.ignoresize
)
4964 /* Warn them that a data or address size prefix doesn't
4965 affect assembly of the next line of code. */
4966 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4970 /* Copy the template we found. */
4973 if (addr_prefix_disp
!= -1)
4974 i
.tm
.operand_types
[addr_prefix_disp
]
4975 = operand_types
[addr_prefix_disp
];
4977 if (found_reverse_match
)
4979 /* If we found a reverse match we must alter the opcode
4980 direction bit. found_reverse_match holds bits to change
4981 (different for int & float insns). */
4983 i
.tm
.base_opcode
^= found_reverse_match
;
4985 i
.tm
.operand_types
[0] = operand_types
[1];
4986 i
.tm
.operand_types
[1] = operand_types
[0];
4995 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4996 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4998 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5000 as_bad (_("`%s' operand %d must use `%ses' segment"),
5006 /* There's only ever one segment override allowed per instruction.
5007 This instruction possibly has a legal segment override on the
5008 second operand, so copy the segment to where non-string
5009 instructions store it, allowing common code. */
5010 i
.seg
[0] = i
.seg
[1];
5012 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5014 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5016 as_bad (_("`%s' operand %d must use `%ses' segment"),
5027 process_suffix (void)
5029 /* If matched instruction specifies an explicit instruction mnemonic
5031 if (i
.tm
.opcode_modifier
.size16
)
5032 i
.suffix
= WORD_MNEM_SUFFIX
;
5033 else if (i
.tm
.opcode_modifier
.size32
)
5034 i
.suffix
= LONG_MNEM_SUFFIX
;
5035 else if (i
.tm
.opcode_modifier
.size64
)
5036 i
.suffix
= QWORD_MNEM_SUFFIX
;
5037 else if (i
.reg_operands
)
5039 /* If there's no instruction mnemonic suffix we try to invent one
5040 based on register operands. */
5043 /* We take i.suffix from the last register operand specified,
5044 Destination register type is more significant than source
5045 register type. crc32 in SSE4.2 prefers source register
5047 if (i
.tm
.base_opcode
== 0xf20f38f1)
5049 if (i
.types
[0].bitfield
.reg16
)
5050 i
.suffix
= WORD_MNEM_SUFFIX
;
5051 else if (i
.types
[0].bitfield
.reg32
)
5052 i
.suffix
= LONG_MNEM_SUFFIX
;
5053 else if (i
.types
[0].bitfield
.reg64
)
5054 i
.suffix
= QWORD_MNEM_SUFFIX
;
5056 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5058 if (i
.types
[0].bitfield
.reg8
)
5059 i
.suffix
= BYTE_MNEM_SUFFIX
;
5066 if (i
.tm
.base_opcode
== 0xf20f38f1
5067 || i
.tm
.base_opcode
== 0xf20f38f0)
5069 /* We have to know the operand size for crc32. */
5070 as_bad (_("ambiguous memory operand size for `%s`"),
5075 for (op
= i
.operands
; --op
>= 0;)
5076 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5078 if (i
.types
[op
].bitfield
.reg8
)
5080 i
.suffix
= BYTE_MNEM_SUFFIX
;
5083 else if (i
.types
[op
].bitfield
.reg16
)
5085 i
.suffix
= WORD_MNEM_SUFFIX
;
5088 else if (i
.types
[op
].bitfield
.reg32
)
5090 i
.suffix
= LONG_MNEM_SUFFIX
;
5093 else if (i
.types
[op
].bitfield
.reg64
)
5095 i
.suffix
= QWORD_MNEM_SUFFIX
;
5101 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5104 && i
.tm
.opcode_modifier
.ignoresize
5105 && i
.tm
.opcode_modifier
.no_bsuf
)
5107 else if (!check_byte_reg ())
5110 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5113 && i
.tm
.opcode_modifier
.ignoresize
5114 && i
.tm
.opcode_modifier
.no_lsuf
)
5116 else if (!check_long_reg ())
5119 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5122 && i
.tm
.opcode_modifier
.ignoresize
5123 && i
.tm
.opcode_modifier
.no_qsuf
)
5125 else if (!check_qword_reg ())
5128 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5131 && i
.tm
.opcode_modifier
.ignoresize
5132 && i
.tm
.opcode_modifier
.no_wsuf
)
5134 else if (!check_word_reg ())
5137 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5138 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5139 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5141 /* Skip if the instruction has x/y/z suffix. match_template
5142 should check if it is a valid suffix. */
5144 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5145 /* Do nothing if the instruction is going to ignore the prefix. */
5150 else if (i
.tm
.opcode_modifier
.defaultsize
5152 /* exclude fldenv/frstor/fsave/fstenv */
5153 && i
.tm
.opcode_modifier
.no_ssuf
)
5155 i
.suffix
= stackop_size
;
5157 else if (intel_syntax
5159 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5160 || i
.tm
.opcode_modifier
.jumpbyte
5161 || i
.tm
.opcode_modifier
.jumpintersegment
5162 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5163 && i
.tm
.extension_opcode
<= 3)))
5168 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5170 i
.suffix
= QWORD_MNEM_SUFFIX
;
5174 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5175 i
.suffix
= LONG_MNEM_SUFFIX
;
5178 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5179 i
.suffix
= WORD_MNEM_SUFFIX
;
5188 if (i
.tm
.opcode_modifier
.w
)
5190 as_bad (_("no instruction mnemonic suffix given and "
5191 "no register operands; can't size instruction"));
5197 unsigned int suffixes
;
5199 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5200 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5202 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5204 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5206 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5208 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5211 /* There are more than suffix matches. */
5212 if (i
.tm
.opcode_modifier
.w
5213 || ((suffixes
& (suffixes
- 1))
5214 && !i
.tm
.opcode_modifier
.defaultsize
5215 && !i
.tm
.opcode_modifier
.ignoresize
))
5217 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5223 /* Change the opcode based on the operand size given by i.suffix;
5224 We don't need to change things for byte insns. */
5227 && i
.suffix
!= BYTE_MNEM_SUFFIX
5228 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5229 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5230 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5232 /* It's not a byte, select word/dword operation. */
5233 if (i
.tm
.opcode_modifier
.w
)
5235 if (i
.tm
.opcode_modifier
.shortform
)
5236 i
.tm
.base_opcode
|= 8;
5238 i
.tm
.base_opcode
|= 1;
5241 /* Now select between word & dword operations via the operand
5242 size prefix, except for instructions that will ignore this
5244 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5246 /* The address size override prefix changes the size of the
5248 if ((flag_code
== CODE_32BIT
5249 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5250 || (flag_code
!= CODE_32BIT
5251 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5252 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5255 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5256 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5257 && !i
.tm
.opcode_modifier
.ignoresize
5258 && !i
.tm
.opcode_modifier
.floatmf
5259 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5260 || (flag_code
== CODE_64BIT
5261 && i
.tm
.opcode_modifier
.jumpbyte
)))
5263 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5265 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5266 prefix
= ADDR_PREFIX_OPCODE
;
5268 if (!add_prefix (prefix
))
5272 /* Set mode64 for an operand. */
5273 if (i
.suffix
== QWORD_MNEM_SUFFIX
5274 && flag_code
== CODE_64BIT
5275 && !i
.tm
.opcode_modifier
.norex64
)
5277 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5278 need rex64. cmpxchg8b is also a special case. */
5279 if (! (i
.operands
== 2
5280 && i
.tm
.base_opcode
== 0x90
5281 && i
.tm
.extension_opcode
== None
5282 && operand_type_equal (&i
.types
[0], &acc64
)
5283 && operand_type_equal (&i
.types
[1], &acc64
))
5284 && ! (i
.operands
== 1
5285 && i
.tm
.base_opcode
== 0xfc7
5286 && i
.tm
.extension_opcode
== 1
5287 && !operand_type_check (i
.types
[0], reg
)
5288 && operand_type_check (i
.types
[0], anymem
)))
5292 /* Size floating point instruction. */
5293 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5294 if (i
.tm
.opcode_modifier
.floatmf
)
5295 i
.tm
.base_opcode
^= 4;
5302 check_byte_reg (void)
5306 for (op
= i
.operands
; --op
>= 0;)
5308 /* If this is an eight bit register, it's OK. If it's the 16 or
5309 32 bit version of an eight bit register, we will just use the
5310 low portion, and that's OK too. */
5311 if (i
.types
[op
].bitfield
.reg8
)
5314 /* I/O port address operands are OK too. */
5315 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5318 /* crc32 doesn't generate this warning. */
5319 if (i
.tm
.base_opcode
== 0xf20f38f0)
5322 if ((i
.types
[op
].bitfield
.reg16
5323 || i
.types
[op
].bitfield
.reg32
5324 || i
.types
[op
].bitfield
.reg64
)
5325 && i
.op
[op
].regs
->reg_num
< 4
5326 /* Prohibit these changes in 64bit mode, since the lowering
5327 would be more complicated. */
5328 && flag_code
!= CODE_64BIT
)
5330 #if REGISTER_WARNINGS
5331 if (!quiet_warnings
)
5332 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5334 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5335 ? REGNAM_AL
- REGNAM_AX
5336 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5338 i
.op
[op
].regs
->reg_name
,
5343 /* Any other register is bad. */
5344 if (i
.types
[op
].bitfield
.reg16
5345 || i
.types
[op
].bitfield
.reg32
5346 || i
.types
[op
].bitfield
.reg64
5347 || i
.types
[op
].bitfield
.regmmx
5348 || i
.types
[op
].bitfield
.regxmm
5349 || i
.types
[op
].bitfield
.regymm
5350 || i
.types
[op
].bitfield
.regzmm
5351 || i
.types
[op
].bitfield
.sreg2
5352 || i
.types
[op
].bitfield
.sreg3
5353 || i
.types
[op
].bitfield
.control
5354 || i
.types
[op
].bitfield
.debug
5355 || i
.types
[op
].bitfield
.test
5356 || i
.types
[op
].bitfield
.floatreg
5357 || i
.types
[op
].bitfield
.floatacc
)
5359 as_bad (_("`%s%s' not allowed with `%s%c'"),
5361 i
.op
[op
].regs
->reg_name
,
5371 check_long_reg (void)
5375 for (op
= i
.operands
; --op
>= 0;)
5376 /* Reject eight bit registers, except where the template requires
5377 them. (eg. movzb) */
5378 if (i
.types
[op
].bitfield
.reg8
5379 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5380 || i
.tm
.operand_types
[op
].bitfield
.reg32
5381 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5383 as_bad (_("`%s%s' not allowed with `%s%c'"),
5385 i
.op
[op
].regs
->reg_name
,
5390 /* Warn if the e prefix on a general reg is missing. */
5391 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5392 && i
.types
[op
].bitfield
.reg16
5393 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5394 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5396 /* Prohibit these changes in the 64bit mode, since the
5397 lowering is more complicated. */
5398 if (flag_code
== CODE_64BIT
)
5400 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5401 register_prefix
, i
.op
[op
].regs
->reg_name
,
5405 #if REGISTER_WARNINGS
5406 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5408 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5409 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5412 /* Warn if the r prefix on a general reg is present. */
5413 else if (i
.types
[op
].bitfield
.reg64
5414 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5415 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5418 && i
.tm
.opcode_modifier
.toqword
5419 && !i
.types
[0].bitfield
.regxmm
)
5421 /* Convert to QWORD. We want REX byte. */
5422 i
.suffix
= QWORD_MNEM_SUFFIX
;
5426 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5427 register_prefix
, i
.op
[op
].regs
->reg_name
,
5436 check_qword_reg (void)
5440 for (op
= i
.operands
; --op
>= 0; )
5441 /* Reject eight bit registers, except where the template requires
5442 them. (eg. movzb) */
5443 if (i
.types
[op
].bitfield
.reg8
5444 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5445 || i
.tm
.operand_types
[op
].bitfield
.reg32
5446 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5448 as_bad (_("`%s%s' not allowed with `%s%c'"),
5450 i
.op
[op
].regs
->reg_name
,
5455 /* Warn if the r prefix on a general reg is missing. */
5456 else if ((i
.types
[op
].bitfield
.reg16
5457 || i
.types
[op
].bitfield
.reg32
)
5458 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5459 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5461 /* Prohibit these changes in the 64bit mode, since the
5462 lowering is more complicated. */
5464 && i
.tm
.opcode_modifier
.todword
5465 && !i
.types
[0].bitfield
.regxmm
)
5467 /* Convert to DWORD. We don't want REX byte. */
5468 i
.suffix
= LONG_MNEM_SUFFIX
;
5472 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5473 register_prefix
, i
.op
[op
].regs
->reg_name
,
5482 check_word_reg (void)
5485 for (op
= i
.operands
; --op
>= 0;)
5486 /* Reject eight bit registers, except where the template requires
5487 them. (eg. movzb) */
5488 if (i
.types
[op
].bitfield
.reg8
5489 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5490 || i
.tm
.operand_types
[op
].bitfield
.reg32
5491 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5493 as_bad (_("`%s%s' not allowed with `%s%c'"),
5495 i
.op
[op
].regs
->reg_name
,
5500 /* Warn if the e or r prefix on a general reg is present. */
5501 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5502 && (i
.types
[op
].bitfield
.reg32
5503 || i
.types
[op
].bitfield
.reg64
)
5504 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5505 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5507 /* Prohibit these changes in the 64bit mode, since the
5508 lowering is more complicated. */
5509 if (flag_code
== CODE_64BIT
)
5511 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5512 register_prefix
, i
.op
[op
].regs
->reg_name
,
5516 #if REGISTER_WARNINGS
5517 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5519 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5520 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5527 update_imm (unsigned int j
)
5529 i386_operand_type overlap
= i
.types
[j
];
5530 if ((overlap
.bitfield
.imm8
5531 || overlap
.bitfield
.imm8s
5532 || overlap
.bitfield
.imm16
5533 || overlap
.bitfield
.imm32
5534 || overlap
.bitfield
.imm32s
5535 || overlap
.bitfield
.imm64
)
5536 && !operand_type_equal (&overlap
, &imm8
)
5537 && !operand_type_equal (&overlap
, &imm8s
)
5538 && !operand_type_equal (&overlap
, &imm16
)
5539 && !operand_type_equal (&overlap
, &imm32
)
5540 && !operand_type_equal (&overlap
, &imm32s
)
5541 && !operand_type_equal (&overlap
, &imm64
))
5545 i386_operand_type temp
;
5547 operand_type_set (&temp
, 0);
5548 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5550 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5551 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5553 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5554 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5555 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5557 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5558 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5561 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5564 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5565 || operand_type_equal (&overlap
, &imm16_32
)
5566 || operand_type_equal (&overlap
, &imm16_32s
))
5568 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5573 if (!operand_type_equal (&overlap
, &imm8
)
5574 && !operand_type_equal (&overlap
, &imm8s
)
5575 && !operand_type_equal (&overlap
, &imm16
)
5576 && !operand_type_equal (&overlap
, &imm32
)
5577 && !operand_type_equal (&overlap
, &imm32s
)
5578 && !operand_type_equal (&overlap
, &imm64
))
5580 as_bad (_("no instruction mnemonic suffix given; "
5581 "can't determine immediate size"));
5585 i
.types
[j
] = overlap
;
5595 /* Update the first 2 immediate operands. */
5596 n
= i
.operands
> 2 ? 2 : i
.operands
;
5599 for (j
= 0; j
< n
; j
++)
5600 if (update_imm (j
) == 0)
5603 /* The 3rd operand can't be immediate operand. */
5604 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5611 bad_implicit_operand (int xmm
)
5613 const char *ireg
= xmm
? "xmm0" : "ymm0";
5616 as_bad (_("the last operand of `%s' must be `%s%s'"),
5617 i
.tm
.name
, register_prefix
, ireg
);
5619 as_bad (_("the first operand of `%s' must be `%s%s'"),
5620 i
.tm
.name
, register_prefix
, ireg
);
5625 process_operands (void)
5627 /* Default segment register this instruction will use for memory
5628 accesses. 0 means unknown. This is only for optimizing out
5629 unnecessary segment overrides. */
5630 const seg_entry
*default_seg
= 0;
5632 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5634 unsigned int dupl
= i
.operands
;
5635 unsigned int dest
= dupl
- 1;
5638 /* The destination must be an xmm register. */
5639 gas_assert (i
.reg_operands
5640 && MAX_OPERANDS
> dupl
5641 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5643 if (i
.tm
.opcode_modifier
.firstxmm0
)
5645 /* The first operand is implicit and must be xmm0. */
5646 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5647 if (register_number (i
.op
[0].regs
) != 0)
5648 return bad_implicit_operand (1);
5650 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5652 /* Keep xmm0 for instructions with VEX prefix and 3
5658 /* We remove the first xmm0 and keep the number of
5659 operands unchanged, which in fact duplicates the
5661 for (j
= 1; j
< i
.operands
; j
++)
5663 i
.op
[j
- 1] = i
.op
[j
];
5664 i
.types
[j
- 1] = i
.types
[j
];
5665 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5669 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5671 gas_assert ((MAX_OPERANDS
- 1) > dupl
5672 && (i
.tm
.opcode_modifier
.vexsources
5675 /* Add the implicit xmm0 for instructions with VEX prefix
5677 for (j
= i
.operands
; j
> 0; j
--)
5679 i
.op
[j
] = i
.op
[j
- 1];
5680 i
.types
[j
] = i
.types
[j
- 1];
5681 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5684 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5685 i
.types
[0] = regxmm
;
5686 i
.tm
.operand_types
[0] = regxmm
;
5689 i
.reg_operands
+= 2;
5694 i
.op
[dupl
] = i
.op
[dest
];
5695 i
.types
[dupl
] = i
.types
[dest
];
5696 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5705 i
.op
[dupl
] = i
.op
[dest
];
5706 i
.types
[dupl
] = i
.types
[dest
];
5707 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5710 if (i
.tm
.opcode_modifier
.immext
)
5713 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5717 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5718 gas_assert (i
.reg_operands
5719 && (operand_type_equal (&i
.types
[0], ®xmm
)
5720 || operand_type_equal (&i
.types
[0], ®ymm
)
5721 || operand_type_equal (&i
.types
[0], ®zmm
)));
5722 if (register_number (i
.op
[0].regs
) != 0)
5723 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5725 for (j
= 1; j
< i
.operands
; j
++)
5727 i
.op
[j
- 1] = i
.op
[j
];
5728 i
.types
[j
- 1] = i
.types
[j
];
5730 /* We need to adjust fields in i.tm since they are used by
5731 build_modrm_byte. */
5732 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5739 else if (i
.tm
.opcode_modifier
.regkludge
)
5741 /* The imul $imm, %reg instruction is converted into
5742 imul $imm, %reg, %reg, and the clr %reg instruction
5743 is converted into xor %reg, %reg. */
5745 unsigned int first_reg_op
;
5747 if (operand_type_check (i
.types
[0], reg
))
5751 /* Pretend we saw the extra register operand. */
5752 gas_assert (i
.reg_operands
== 1
5753 && i
.op
[first_reg_op
+ 1].regs
== 0);
5754 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5755 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5760 if (i
.tm
.opcode_modifier
.shortform
)
5762 if (i
.types
[0].bitfield
.sreg2
5763 || i
.types
[0].bitfield
.sreg3
)
5765 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5766 && i
.op
[0].regs
->reg_num
== 1)
5768 as_bad (_("you can't `pop %scs'"), register_prefix
);
5771 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5772 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5777 /* The register or float register operand is in operand
5781 if (i
.types
[0].bitfield
.floatreg
5782 || operand_type_check (i
.types
[0], reg
))
5786 /* Register goes in low 3 bits of opcode. */
5787 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5788 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5790 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5792 /* Warn about some common errors, but press on regardless.
5793 The first case can be generated by gcc (<= 2.8.1). */
5794 if (i
.operands
== 2)
5796 /* Reversed arguments on faddp, fsubp, etc. */
5797 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5798 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5799 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5803 /* Extraneous `l' suffix on fp insn. */
5804 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5805 register_prefix
, i
.op
[0].regs
->reg_name
);
5810 else if (i
.tm
.opcode_modifier
.modrm
)
5812 /* The opcode is completed (modulo i.tm.extension_opcode which
5813 must be put into the modrm byte). Now, we make the modrm and
5814 index base bytes based on all the info we've collected. */
5816 default_seg
= build_modrm_byte ();
5818 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5822 else if (i
.tm
.opcode_modifier
.isstring
)
5824 /* For the string instructions that allow a segment override
5825 on one of their operands, the default segment is ds. */
5829 if (i
.tm
.base_opcode
== 0x8d /* lea */
5832 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5834 /* If a segment was explicitly specified, and the specified segment
5835 is not the default, use an opcode prefix to select it. If we
5836 never figured out what the default segment is, then default_seg
5837 will be zero at this point, and the specified segment prefix will
5839 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5841 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5847 static const seg_entry
*
5848 build_modrm_byte (void)
5850 const seg_entry
*default_seg
= 0;
5851 unsigned int source
, dest
;
5854 /* The first operand of instructions with VEX prefix and 3 sources
5855 must be VEX_Imm4. */
5856 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5859 unsigned int nds
, reg_slot
;
5862 if (i
.tm
.opcode_modifier
.veximmext
5863 && i
.tm
.opcode_modifier
.immext
)
5865 dest
= i
.operands
- 2;
5866 gas_assert (dest
== 3);
5869 dest
= i
.operands
- 1;
5872 /* There are 2 kinds of instructions:
5873 1. 5 operands: 4 register operands or 3 register operands
5874 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5875 VexW0 or VexW1. The destination must be either XMM, YMM or
5877 2. 4 operands: 4 register operands or 3 register operands
5878 plus 1 memory operand, VexXDS, and VexImmExt */
5879 gas_assert ((i
.reg_operands
== 4
5880 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5881 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5882 && (i
.tm
.opcode_modifier
.veximmext
5883 || (i
.imm_operands
== 1
5884 && i
.types
[0].bitfield
.vec_imm4
5885 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5886 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5887 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5888 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5889 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5891 if (i
.imm_operands
== 0)
5893 /* When there is no immediate operand, generate an 8bit
5894 immediate operand to encode the first operand. */
5895 exp
= &im_expressions
[i
.imm_operands
++];
5896 i
.op
[i
.operands
].imms
= exp
;
5897 i
.types
[i
.operands
] = imm8
;
5899 /* If VexW1 is set, the first operand is the source and
5900 the second operand is encoded in the immediate operand. */
5901 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5912 /* FMA swaps REG and NDS. */
5913 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5921 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5923 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5925 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5927 exp
->X_op
= O_constant
;
5928 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5929 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5933 unsigned int imm_slot
;
5935 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5937 /* If VexW0 is set, the third operand is the source and
5938 the second operand is encoded in the immediate
5945 /* VexW1 is set, the second operand is the source and
5946 the third operand is encoded in the immediate
5952 if (i
.tm
.opcode_modifier
.immext
)
5954 /* When ImmExt is set, the immdiate byte is the last
5956 imm_slot
= i
.operands
- 1;
5964 /* Turn on Imm8 so that output_imm will generate it. */
5965 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5968 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5970 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5972 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5974 i
.op
[imm_slot
].imms
->X_add_number
5975 |= register_number (i
.op
[reg_slot
].regs
) << 4;
5976 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5979 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5980 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5982 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5984 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5989 /* i.reg_operands MUST be the number of real register operands;
5990 implicit registers do not count. If there are 3 register
5991 operands, it must be a instruction with VexNDS. For a
5992 instruction with VexNDD, the destination register is encoded
5993 in VEX prefix. If there are 4 register operands, it must be
5994 a instruction with VEX prefix and 3 sources. */
5995 if (i
.mem_operands
== 0
5996 && ((i
.reg_operands
== 2
5997 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5998 || (i
.reg_operands
== 3
5999 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6000 || (i
.reg_operands
== 4 && vex_3_sources
)))
6008 /* When there are 3 operands, one of them may be immediate,
6009 which may be the first or the last operand. Otherwise,
6010 the first operand must be shift count register (cl) or it
6011 is an instruction with VexNDS. */
6012 gas_assert (i
.imm_operands
== 1
6013 || (i
.imm_operands
== 0
6014 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6015 || i
.types
[0].bitfield
.shiftcount
)));
6016 if (operand_type_check (i
.types
[0], imm
)
6017 || i
.types
[0].bitfield
.shiftcount
)
6023 /* When there are 4 operands, the first two must be 8bit
6024 immediate operands. The source operand will be the 3rd
6027 For instructions with VexNDS, if the first operand
6028 an imm8, the source operand is the 2nd one. If the last
6029 operand is imm8, the source operand is the first one. */
6030 gas_assert ((i
.imm_operands
== 2
6031 && i
.types
[0].bitfield
.imm8
6032 && i
.types
[1].bitfield
.imm8
)
6033 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6034 && i
.imm_operands
== 1
6035 && (i
.types
[0].bitfield
.imm8
6036 || i
.types
[i
.operands
- 1].bitfield
.imm8
6038 if (i
.imm_operands
== 2)
6042 if (i
.types
[0].bitfield
.imm8
)
6049 if (i
.tm
.opcode_modifier
.evex
)
6051 /* For EVEX instructions, when there are 5 operands, the
6052 first one must be immediate operand. If the second one
6053 is immediate operand, the source operand is the 3th
6054 one. If the last one is immediate operand, the source
6055 operand is the 2nd one. */
6056 gas_assert (i
.imm_operands
== 2
6057 && i
.tm
.opcode_modifier
.sae
6058 && operand_type_check (i
.types
[0], imm
));
6059 if (operand_type_check (i
.types
[1], imm
))
6061 else if (operand_type_check (i
.types
[4], imm
))
6075 /* RC/SAE operand could be between DEST and SRC. That happens
6076 when one operand is GPR and the other one is XMM/YMM/ZMM
6078 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6081 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6083 /* For instructions with VexNDS, the register-only source
6084 operand must be 32/64bit integer, XMM, YMM or ZMM
6085 register. It is encoded in VEX prefix. We need to
6086 clear RegMem bit before calling operand_type_equal. */
6088 i386_operand_type op
;
6091 /* Check register-only source operand when two source
6092 operands are swapped. */
6093 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6094 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6102 op
= i
.tm
.operand_types
[vvvv
];
6103 op
.bitfield
.regmem
= 0;
6104 if ((dest
+ 1) >= i
.operands
6105 || (!op
.bitfield
.reg32
6106 && op
.bitfield
.reg64
6107 && !operand_type_equal (&op
, ®xmm
)
6108 && !operand_type_equal (&op
, ®ymm
)
6109 && !operand_type_equal (&op
, ®zmm
)
6110 && !operand_type_equal (&op
, ®mask
)))
6112 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6118 /* One of the register operands will be encoded in the i.tm.reg
6119 field, the other in the combined i.tm.mode and i.tm.regmem
6120 fields. If no form of this instruction supports a memory
6121 destination operand, then we assume the source operand may
6122 sometimes be a memory operand and so we need to store the
6123 destination in the i.rm.reg field. */
6124 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6125 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6127 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6128 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6129 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6131 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6133 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6135 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6140 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6141 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6142 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6144 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6146 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6148 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6151 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6153 if (!i
.types
[0].bitfield
.control
6154 && !i
.types
[1].bitfield
.control
)
6156 i
.rex
&= ~(REX_R
| REX_B
);
6157 add_prefix (LOCK_PREFIX_OPCODE
);
6161 { /* If it's not 2 reg operands... */
6166 unsigned int fake_zero_displacement
= 0;
6169 for (op
= 0; op
< i
.operands
; op
++)
6170 if (operand_type_check (i
.types
[op
], anymem
))
6172 gas_assert (op
< i
.operands
);
6174 if (i
.tm
.opcode_modifier
.vecsib
)
6176 if (i
.index_reg
->reg_num
== RegEiz
6177 || i
.index_reg
->reg_num
== RegRiz
)
6180 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6183 i
.sib
.base
= NO_BASE_REGISTER
;
6184 i
.sib
.scale
= i
.log2_scale_factor
;
6185 /* No Vec_Disp8 if there is no base. */
6186 i
.types
[op
].bitfield
.vec_disp8
= 0;
6187 i
.types
[op
].bitfield
.disp8
= 0;
6188 i
.types
[op
].bitfield
.disp16
= 0;
6189 i
.types
[op
].bitfield
.disp64
= 0;
6190 if (flag_code
!= CODE_64BIT
)
6192 /* Must be 32 bit */
6193 i
.types
[op
].bitfield
.disp32
= 1;
6194 i
.types
[op
].bitfield
.disp32s
= 0;
6198 i
.types
[op
].bitfield
.disp32
= 0;
6199 i
.types
[op
].bitfield
.disp32s
= 1;
6202 i
.sib
.index
= i
.index_reg
->reg_num
;
6203 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6205 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6211 if (i
.base_reg
== 0)
6214 if (!i
.disp_operands
)
6216 fake_zero_displacement
= 1;
6217 /* Instructions with VSIB byte need 32bit displacement
6218 if there is no base register. */
6219 if (i
.tm
.opcode_modifier
.vecsib
)
6220 i
.types
[op
].bitfield
.disp32
= 1;
6222 if (i
.index_reg
== 0)
6224 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6225 /* Operand is just <disp> */
6226 if (flag_code
== CODE_64BIT
)
6228 /* 64bit mode overwrites the 32bit absolute
6229 addressing by RIP relative addressing and
6230 absolute addressing is encoded by one of the
6231 redundant SIB forms. */
6232 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6233 i
.sib
.base
= NO_BASE_REGISTER
;
6234 i
.sib
.index
= NO_INDEX_REGISTER
;
6235 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6236 ? disp32s
: disp32
);
6238 else if ((flag_code
== CODE_16BIT
)
6239 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6241 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6242 i
.types
[op
] = disp16
;
6246 i
.rm
.regmem
= NO_BASE_REGISTER
;
6247 i
.types
[op
] = disp32
;
6250 else if (!i
.tm
.opcode_modifier
.vecsib
)
6252 /* !i.base_reg && i.index_reg */
6253 if (i
.index_reg
->reg_num
== RegEiz
6254 || i
.index_reg
->reg_num
== RegRiz
)
6255 i
.sib
.index
= NO_INDEX_REGISTER
;
6257 i
.sib
.index
= i
.index_reg
->reg_num
;
6258 i
.sib
.base
= NO_BASE_REGISTER
;
6259 i
.sib
.scale
= i
.log2_scale_factor
;
6260 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6261 /* No Vec_Disp8 if there is no base. */
6262 i
.types
[op
].bitfield
.vec_disp8
= 0;
6263 i
.types
[op
].bitfield
.disp8
= 0;
6264 i
.types
[op
].bitfield
.disp16
= 0;
6265 i
.types
[op
].bitfield
.disp64
= 0;
6266 if (flag_code
!= CODE_64BIT
)
6268 /* Must be 32 bit */
6269 i
.types
[op
].bitfield
.disp32
= 1;
6270 i
.types
[op
].bitfield
.disp32s
= 0;
6274 i
.types
[op
].bitfield
.disp32
= 0;
6275 i
.types
[op
].bitfield
.disp32s
= 1;
6277 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6281 /* RIP addressing for 64bit mode. */
6282 else if (i
.base_reg
->reg_num
== RegRip
||
6283 i
.base_reg
->reg_num
== RegEip
)
6285 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6286 i
.rm
.regmem
= NO_BASE_REGISTER
;
6287 i
.types
[op
].bitfield
.disp8
= 0;
6288 i
.types
[op
].bitfield
.disp16
= 0;
6289 i
.types
[op
].bitfield
.disp32
= 0;
6290 i
.types
[op
].bitfield
.disp32s
= 1;
6291 i
.types
[op
].bitfield
.disp64
= 0;
6292 i
.types
[op
].bitfield
.vec_disp8
= 0;
6293 i
.flags
[op
] |= Operand_PCrel
;
6294 if (! i
.disp_operands
)
6295 fake_zero_displacement
= 1;
6297 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6299 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6300 switch (i
.base_reg
->reg_num
)
6303 if (i
.index_reg
== 0)
6305 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6306 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6310 if (i
.index_reg
== 0)
6313 if (operand_type_check (i
.types
[op
], disp
) == 0)
6315 /* fake (%bp) into 0(%bp) */
6316 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6317 i
.types
[op
].bitfield
.vec_disp8
= 1;
6319 i
.types
[op
].bitfield
.disp8
= 1;
6320 fake_zero_displacement
= 1;
6323 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6324 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6326 default: /* (%si) -> 4 or (%di) -> 5 */
6327 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6329 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6331 else /* i.base_reg and 32/64 bit mode */
6333 if (flag_code
== CODE_64BIT
6334 && operand_type_check (i
.types
[op
], disp
))
6336 i386_operand_type temp
;
6337 operand_type_set (&temp
, 0);
6338 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6339 temp
.bitfield
.vec_disp8
6340 = i
.types
[op
].bitfield
.vec_disp8
;
6342 if (i
.prefix
[ADDR_PREFIX
] == 0)
6343 i
.types
[op
].bitfield
.disp32s
= 1;
6345 i
.types
[op
].bitfield
.disp32
= 1;
6348 if (!i
.tm
.opcode_modifier
.vecsib
)
6349 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6350 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6352 i
.sib
.base
= i
.base_reg
->reg_num
;
6353 /* x86-64 ignores REX prefix bit here to avoid decoder
6355 if (!(i
.base_reg
->reg_flags
& RegRex
)
6356 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6357 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6359 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6361 fake_zero_displacement
= 1;
6362 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6363 i
.types
[op
].bitfield
.vec_disp8
= 1;
6365 i
.types
[op
].bitfield
.disp8
= 1;
6367 i
.sib
.scale
= i
.log2_scale_factor
;
6368 if (i
.index_reg
== 0)
6370 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6371 /* <disp>(%esp) becomes two byte modrm with no index
6372 register. We've already stored the code for esp
6373 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6374 Any base register besides %esp will not use the
6375 extra modrm byte. */
6376 i
.sib
.index
= NO_INDEX_REGISTER
;
6378 else if (!i
.tm
.opcode_modifier
.vecsib
)
6380 if (i
.index_reg
->reg_num
== RegEiz
6381 || i
.index_reg
->reg_num
== RegRiz
)
6382 i
.sib
.index
= NO_INDEX_REGISTER
;
6384 i
.sib
.index
= i
.index_reg
->reg_num
;
6385 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6386 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6391 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6392 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6396 if (!fake_zero_displacement
6400 fake_zero_displacement
= 1;
6401 if (i
.disp_encoding
== disp_encoding_8bit
)
6402 i
.types
[op
].bitfield
.disp8
= 1;
6404 i
.types
[op
].bitfield
.disp32
= 1;
6406 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6410 if (fake_zero_displacement
)
6412 /* Fakes a zero displacement assuming that i.types[op]
6413 holds the correct displacement size. */
6416 gas_assert (i
.op
[op
].disps
== 0);
6417 exp
= &disp_expressions
[i
.disp_operands
++];
6418 i
.op
[op
].disps
= exp
;
6419 exp
->X_op
= O_constant
;
6420 exp
->X_add_number
= 0;
6421 exp
->X_add_symbol
= (symbolS
*) 0;
6422 exp
->X_op_symbol
= (symbolS
*) 0;
6430 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6432 if (operand_type_check (i
.types
[0], imm
))
6433 i
.vex
.register_specifier
= NULL
;
6436 /* VEX.vvvv encodes one of the sources when the first
6437 operand is not an immediate. */
6438 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6439 i
.vex
.register_specifier
= i
.op
[0].regs
;
6441 i
.vex
.register_specifier
= i
.op
[1].regs
;
6444 /* Destination is a XMM register encoded in the ModRM.reg
6446 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6447 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6450 /* ModRM.rm and VEX.B encodes the other source. */
6451 if (!i
.mem_operands
)
6455 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6456 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6458 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6460 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6464 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6466 i
.vex
.register_specifier
= i
.op
[2].regs
;
6467 if (!i
.mem_operands
)
6470 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6471 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6475 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6476 (if any) based on i.tm.extension_opcode. Again, we must be
6477 careful to make sure that segment/control/debug/test/MMX
6478 registers are coded into the i.rm.reg field. */
6479 else if (i
.reg_operands
)
6482 unsigned int vex_reg
= ~0;
6484 for (op
= 0; op
< i
.operands
; op
++)
6485 if (i
.types
[op
].bitfield
.reg8
6486 || i
.types
[op
].bitfield
.reg16
6487 || i
.types
[op
].bitfield
.reg32
6488 || i
.types
[op
].bitfield
.reg64
6489 || i
.types
[op
].bitfield
.regmmx
6490 || i
.types
[op
].bitfield
.regxmm
6491 || i
.types
[op
].bitfield
.regymm
6492 || i
.types
[op
].bitfield
.regbnd
6493 || i
.types
[op
].bitfield
.regzmm
6494 || i
.types
[op
].bitfield
.regmask
6495 || i
.types
[op
].bitfield
.sreg2
6496 || i
.types
[op
].bitfield
.sreg3
6497 || i
.types
[op
].bitfield
.control
6498 || i
.types
[op
].bitfield
.debug
6499 || i
.types
[op
].bitfield
.test
)
6504 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6506 /* For instructions with VexNDS, the register-only
6507 source operand is encoded in VEX prefix. */
6508 gas_assert (mem
!= (unsigned int) ~0);
6513 gas_assert (op
< i
.operands
);
6517 /* Check register-only source operand when two source
6518 operands are swapped. */
6519 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6520 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6524 gas_assert (mem
== (vex_reg
+ 1)
6525 && op
< i
.operands
);
6530 gas_assert (vex_reg
< i
.operands
);
6534 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6536 /* For instructions with VexNDD, the register destination
6537 is encoded in VEX prefix. */
6538 if (i
.mem_operands
== 0)
6540 /* There is no memory operand. */
6541 gas_assert ((op
+ 2) == i
.operands
);
6546 /* There are only 2 operands. */
6547 gas_assert (op
< 2 && i
.operands
== 2);
6552 gas_assert (op
< i
.operands
);
6554 if (vex_reg
!= (unsigned int) ~0)
6556 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6558 if (type
->bitfield
.reg32
!= 1
6559 && type
->bitfield
.reg64
!= 1
6560 && !operand_type_equal (type
, ®xmm
)
6561 && !operand_type_equal (type
, ®ymm
)
6562 && !operand_type_equal (type
, ®zmm
)
6563 && !operand_type_equal (type
, ®mask
))
6566 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6569 /* Don't set OP operand twice. */
6572 /* If there is an extension opcode to put here, the
6573 register number must be put into the regmem field. */
6574 if (i
.tm
.extension_opcode
!= None
)
6576 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6577 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6579 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6584 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6585 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6587 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6592 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6593 must set it to 3 to indicate this is a register operand
6594 in the regmem field. */
6595 if (!i
.mem_operands
)
6599 /* Fill in i.rm.reg field with extension opcode (if any). */
6600 if (i
.tm
.extension_opcode
!= None
)
6601 i
.rm
.reg
= i
.tm
.extension_opcode
;
6607 output_branch (void)
6613 relax_substateT subtype
;
6617 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6618 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6621 if (i
.prefix
[DATA_PREFIX
] != 0)
6627 /* Pentium4 branch hints. */
6628 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6629 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6634 if (i
.prefix
[REX_PREFIX
] != 0)
6640 /* BND prefixed jump. */
6641 if (i
.prefix
[BND_PREFIX
] != 0)
6643 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6647 if (i
.prefixes
!= 0 && !intel_syntax
)
6648 as_warn (_("skipping prefixes on this instruction"));
6650 /* It's always a symbol; End frag & setup for relax.
6651 Make sure there is enough room in this frag for the largest
6652 instruction we may generate in md_convert_frag. This is 2
6653 bytes for the opcode and room for the prefix and largest
6655 frag_grow (prefix
+ 2 + 4);
6656 /* Prefix and 1 opcode byte go in fr_fix. */
6657 p
= frag_more (prefix
+ 1);
6658 if (i
.prefix
[DATA_PREFIX
] != 0)
6659 *p
++ = DATA_PREFIX_OPCODE
;
6660 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6661 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6662 *p
++ = i
.prefix
[SEG_PREFIX
];
6663 if (i
.prefix
[REX_PREFIX
] != 0)
6664 *p
++ = i
.prefix
[REX_PREFIX
];
6665 *p
= i
.tm
.base_opcode
;
6667 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6668 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6669 else if (cpu_arch_flags
.bitfield
.cpui386
)
6670 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6672 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6675 sym
= i
.op
[0].disps
->X_add_symbol
;
6676 off
= i
.op
[0].disps
->X_add_number
;
6678 if (i
.op
[0].disps
->X_op
!= O_constant
6679 && i
.op
[0].disps
->X_op
!= O_symbol
)
6681 /* Handle complex expressions. */
6682 sym
= make_expr_symbol (i
.op
[0].disps
);
6686 /* 1 possible extra opcode + 4 byte displacement go in var part.
6687 Pass reloc in fr_var. */
6688 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6698 if (i
.tm
.opcode_modifier
.jumpbyte
)
6700 /* This is a loop or jecxz type instruction. */
6702 if (i
.prefix
[ADDR_PREFIX
] != 0)
6704 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6707 /* Pentium4 branch hints. */
6708 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6709 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6711 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6720 if (flag_code
== CODE_16BIT
)
6723 if (i
.prefix
[DATA_PREFIX
] != 0)
6725 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6735 if (i
.prefix
[REX_PREFIX
] != 0)
6737 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6741 /* BND prefixed jump. */
6742 if (i
.prefix
[BND_PREFIX
] != 0)
6744 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6748 if (i
.prefixes
!= 0 && !intel_syntax
)
6749 as_warn (_("skipping prefixes on this instruction"));
6751 p
= frag_more (i
.tm
.opcode_length
+ size
);
6752 switch (i
.tm
.opcode_length
)
6755 *p
++ = i
.tm
.base_opcode
>> 8;
6757 *p
++ = i
.tm
.base_opcode
;
6763 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6764 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6766 /* All jumps handled here are signed, but don't use a signed limit
6767 check for 32 and 16 bit jumps as we want to allow wrap around at
6768 4G and 64k respectively. */
6770 fixP
->fx_signed
= 1;
6774 output_interseg_jump (void)
6782 if (flag_code
== CODE_16BIT
)
6786 if (i
.prefix
[DATA_PREFIX
] != 0)
6792 if (i
.prefix
[REX_PREFIX
] != 0)
6802 if (i
.prefixes
!= 0 && !intel_syntax
)
6803 as_warn (_("skipping prefixes on this instruction"));
6805 /* 1 opcode; 2 segment; offset */
6806 p
= frag_more (prefix
+ 1 + 2 + size
);
6808 if (i
.prefix
[DATA_PREFIX
] != 0)
6809 *p
++ = DATA_PREFIX_OPCODE
;
6811 if (i
.prefix
[REX_PREFIX
] != 0)
6812 *p
++ = i
.prefix
[REX_PREFIX
];
6814 *p
++ = i
.tm
.base_opcode
;
6815 if (i
.op
[1].imms
->X_op
== O_constant
)
6817 offsetT n
= i
.op
[1].imms
->X_add_number
;
6820 && !fits_in_unsigned_word (n
)
6821 && !fits_in_signed_word (n
))
6823 as_bad (_("16-bit jump out of range"));
6826 md_number_to_chars (p
, n
, size
);
6829 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6830 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6831 if (i
.op
[0].imms
->X_op
!= O_constant
)
6832 as_bad (_("can't handle non absolute segment in `%s'"),
6834 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6840 fragS
*insn_start_frag
;
6841 offsetT insn_start_off
;
6843 /* Tie dwarf2 debug info to the address at the start of the insn.
6844 We can't do this after the insn has been output as the current
6845 frag may have been closed off. eg. by frag_var. */
6846 dwarf2_emit_insn (0);
6848 insn_start_frag
= frag_now
;
6849 insn_start_off
= frag_now_fix ();
6852 if (i
.tm
.opcode_modifier
.jump
)
6854 else if (i
.tm
.opcode_modifier
.jumpbyte
6855 || i
.tm
.opcode_modifier
.jumpdword
)
6857 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6858 output_interseg_jump ();
6861 /* Output normal instructions here. */
6865 unsigned int prefix
;
6867 /* Some processors fail on LOCK prefix. This options makes
6868 assembler ignore LOCK prefix and serves as a workaround. */
6869 if (omit_lock_prefix
)
6871 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6873 i
.prefix
[LOCK_PREFIX
] = 0;
6876 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6877 don't need the explicit prefix. */
6878 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6880 switch (i
.tm
.opcode_length
)
6883 if (i
.tm
.base_opcode
& 0xff000000)
6885 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6890 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6892 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6893 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6896 if (prefix
!= REPE_PREFIX_OPCODE
6897 || (i
.prefix
[REP_PREFIX
]
6898 != REPE_PREFIX_OPCODE
))
6899 add_prefix (prefix
);
6902 add_prefix (prefix
);
6911 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6912 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6913 R_X86_64_GOTTPOFF relocation so that linker can safely
6914 perform IE->LE optimization. */
6915 if (x86_elf_abi
== X86_64_X32_ABI
6917 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
6918 && i
.prefix
[REX_PREFIX
] == 0)
6919 add_prefix (REX_OPCODE
);
6922 /* The prefix bytes. */
6923 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6925 FRAG_APPEND_1_CHAR (*q
);
6929 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6934 /* REX byte is encoded in VEX prefix. */
6938 FRAG_APPEND_1_CHAR (*q
);
6941 /* There should be no other prefixes for instructions
6946 /* For EVEX instructions i.vrex should become 0 after
6947 build_evex_prefix. For VEX instructions upper 16 registers
6948 aren't available, so VREX should be 0. */
6951 /* Now the VEX prefix. */
6952 p
= frag_more (i
.vex
.length
);
6953 for (j
= 0; j
< i
.vex
.length
; j
++)
6954 p
[j
] = i
.vex
.bytes
[j
];
6957 /* Now the opcode; be careful about word order here! */
6958 if (i
.tm
.opcode_length
== 1)
6960 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6964 switch (i
.tm
.opcode_length
)
6968 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
6969 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6973 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6983 /* Put out high byte first: can't use md_number_to_chars! */
6984 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6985 *p
= i
.tm
.base_opcode
& 0xff;
6988 /* Now the modrm byte and sib byte (if present). */
6989 if (i
.tm
.opcode_modifier
.modrm
)
6991 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6994 /* If i.rm.regmem == ESP (4)
6995 && i.rm.mode != (Register mode)
6997 ==> need second modrm byte. */
6998 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7000 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7001 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7003 | i
.sib
.scale
<< 6));
7006 if (i
.disp_operands
)
7007 output_disp (insn_start_frag
, insn_start_off
);
7010 output_imm (insn_start_frag
, insn_start_off
);
7016 pi ("" /*line*/, &i
);
7018 #endif /* DEBUG386 */
7021 /* Return the size of the displacement operand N. */
7024 disp_size (unsigned int n
)
7028 /* Vec_Disp8 has to be 8bit. */
7029 if (i
.types
[n
].bitfield
.vec_disp8
)
7031 else if (i
.types
[n
].bitfield
.disp64
)
7033 else if (i
.types
[n
].bitfield
.disp8
)
7035 else if (i
.types
[n
].bitfield
.disp16
)
7040 /* Return the size of the immediate operand N. */
7043 imm_size (unsigned int n
)
7046 if (i
.types
[n
].bitfield
.imm64
)
7048 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7050 else if (i
.types
[n
].bitfield
.imm16
)
7056 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7061 for (n
= 0; n
< i
.operands
; n
++)
7063 if (i
.types
[n
].bitfield
.vec_disp8
7064 || operand_type_check (i
.types
[n
], disp
))
7066 if (i
.op
[n
].disps
->X_op
== O_constant
)
7068 int size
= disp_size (n
);
7069 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7071 if (i
.types
[n
].bitfield
.vec_disp8
)
7073 val
= offset_in_range (val
, size
);
7074 p
= frag_more (size
);
7075 md_number_to_chars (p
, val
, size
);
7079 enum bfd_reloc_code_real reloc_type
;
7080 int size
= disp_size (n
);
7081 int sign
= i
.types
[n
].bitfield
.disp32s
;
7082 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7084 /* We can't have 8 bit displacement here. */
7085 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7087 /* The PC relative address is computed relative
7088 to the instruction boundary, so in case immediate
7089 fields follows, we need to adjust the value. */
7090 if (pcrel
&& i
.imm_operands
)
7095 for (n1
= 0; n1
< i
.operands
; n1
++)
7096 if (operand_type_check (i
.types
[n1
], imm
))
7098 /* Only one immediate is allowed for PC
7099 relative address. */
7100 gas_assert (sz
== 0);
7102 i
.op
[n
].disps
->X_add_number
-= sz
;
7104 /* We should find the immediate. */
7105 gas_assert (sz
!= 0);
7108 p
= frag_more (size
);
7109 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7111 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7112 && (((reloc_type
== BFD_RELOC_32
7113 || reloc_type
== BFD_RELOC_X86_64_32S
7114 || (reloc_type
== BFD_RELOC_64
7116 && (i
.op
[n
].disps
->X_op
== O_symbol
7117 || (i
.op
[n
].disps
->X_op
== O_add
7118 && ((symbol_get_value_expression
7119 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7121 || reloc_type
== BFD_RELOC_32_PCREL
))
7125 if (insn_start_frag
== frag_now
)
7126 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7131 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7132 for (fr
= insn_start_frag
->fr_next
;
7133 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7135 add
+= p
- frag_now
->fr_literal
;
7140 reloc_type
= BFD_RELOC_386_GOTPC
;
7141 i
.op
[n
].imms
->X_add_number
+= add
;
7143 else if (reloc_type
== BFD_RELOC_64
)
7144 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7146 /* Don't do the adjustment for x86-64, as there
7147 the pcrel addressing is relative to the _next_
7148 insn, and that is taken care of in other code. */
7149 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7151 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7152 i
.op
[n
].disps
, pcrel
, reloc_type
);
7159 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7164 for (n
= 0; n
< i
.operands
; n
++)
7166 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7167 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7170 if (operand_type_check (i
.types
[n
], imm
))
7172 if (i
.op
[n
].imms
->X_op
== O_constant
)
7174 int size
= imm_size (n
);
7177 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7179 p
= frag_more (size
);
7180 md_number_to_chars (p
, val
, size
);
7184 /* Not absolute_section.
7185 Need a 32-bit fixup (don't support 8bit
7186 non-absolute imms). Try to support other
7188 enum bfd_reloc_code_real reloc_type
;
7189 int size
= imm_size (n
);
7192 if (i
.types
[n
].bitfield
.imm32s
7193 && (i
.suffix
== QWORD_MNEM_SUFFIX
7194 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7199 p
= frag_more (size
);
7200 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7202 /* This is tough to explain. We end up with this one if we
7203 * have operands that look like
7204 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7205 * obtain the absolute address of the GOT, and it is strongly
7206 * preferable from a performance point of view to avoid using
7207 * a runtime relocation for this. The actual sequence of
7208 * instructions often look something like:
7213 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7215 * The call and pop essentially return the absolute address
7216 * of the label .L66 and store it in %ebx. The linker itself
7217 * will ultimately change the first operand of the addl so
7218 * that %ebx points to the GOT, but to keep things simple, the
7219 * .o file must have this operand set so that it generates not
7220 * the absolute address of .L66, but the absolute address of
7221 * itself. This allows the linker itself simply treat a GOTPC
7222 * relocation as asking for a pcrel offset to the GOT to be
7223 * added in, and the addend of the relocation is stored in the
7224 * operand field for the instruction itself.
7226 * Our job here is to fix the operand so that it would add
7227 * the correct offset so that %ebx would point to itself. The
7228 * thing that is tricky is that .-.L66 will point to the
7229 * beginning of the instruction, so we need to further modify
7230 * the operand so that it will point to itself. There are
7231 * other cases where you have something like:
7233 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7235 * and here no correction would be required. Internally in
7236 * the assembler we treat operands of this form as not being
7237 * pcrel since the '.' is explicitly mentioned, and I wonder
7238 * whether it would simplify matters to do it this way. Who
7239 * knows. In earlier versions of the PIC patches, the
7240 * pcrel_adjust field was used to store the correction, but
7241 * since the expression is not pcrel, I felt it would be
7242 * confusing to do it this way. */
7244 if ((reloc_type
== BFD_RELOC_32
7245 || reloc_type
== BFD_RELOC_X86_64_32S
7246 || reloc_type
== BFD_RELOC_64
)
7248 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7249 && (i
.op
[n
].imms
->X_op
== O_symbol
7250 || (i
.op
[n
].imms
->X_op
== O_add
7251 && ((symbol_get_value_expression
7252 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7257 if (insn_start_frag
== frag_now
)
7258 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7263 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7264 for (fr
= insn_start_frag
->fr_next
;
7265 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7267 add
+= p
- frag_now
->fr_literal
;
7271 reloc_type
= BFD_RELOC_386_GOTPC
;
7273 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7275 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7276 i
.op
[n
].imms
->X_add_number
+= add
;
7278 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7279 i
.op
[n
].imms
, 0, reloc_type
);
7285 /* x86_cons_fix_new is called via the expression parsing code when a
7286 reloc is needed. We use this hook to get the correct .got reloc. */
7287 static int cons_sign
= -1;
7290 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7291 expressionS
*exp
, bfd_reloc_code_real_type r
)
7293 r
= reloc (len
, 0, cons_sign
, r
);
7296 if (exp
->X_op
== O_secrel
)
7298 exp
->X_op
= O_symbol
;
7299 r
= BFD_RELOC_32_SECREL
;
7303 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7306 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7307 purpose of the `.dc.a' internal pseudo-op. */
7310 x86_address_bytes (void)
7312 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7314 return stdoutput
->arch_info
->bits_per_address
/ 8;
7317 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7319 # define lex_got(reloc, adjust, types) NULL
7321 /* Parse operands of the form
7322 <symbol>@GOTOFF+<nnn>
7323 and similar .plt or .got references.
7325 If we find one, set up the correct relocation in RELOC and copy the
7326 input string, minus the `@GOTOFF' into a malloc'd buffer for
7327 parsing by the calling routine. Return this buffer, and if ADJUST
7328 is non-null set it to the length of the string we removed from the
7329 input line. Otherwise return NULL. */
7331 lex_got (enum bfd_reloc_code_real
*rel
,
7333 i386_operand_type
*types
)
7335 /* Some of the relocations depend on the size of what field is to
7336 be relocated. But in our callers i386_immediate and i386_displacement
7337 we don't yet know the operand size (this will be set by insn
7338 matching). Hence we record the word32 relocation here,
7339 and adjust the reloc according to the real size in reloc(). */
7340 static const struct {
7343 const enum bfd_reloc_code_real rel
[2];
7344 const i386_operand_type types64
;
7346 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7347 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7349 OPERAND_TYPE_IMM32_64
},
7351 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7352 BFD_RELOC_X86_64_PLTOFF64
},
7353 OPERAND_TYPE_IMM64
},
7354 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7355 BFD_RELOC_X86_64_PLT32
},
7356 OPERAND_TYPE_IMM32_32S_DISP32
},
7357 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7358 BFD_RELOC_X86_64_GOTPLT64
},
7359 OPERAND_TYPE_IMM64_DISP64
},
7360 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7361 BFD_RELOC_X86_64_GOTOFF64
},
7362 OPERAND_TYPE_IMM64_DISP64
},
7363 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7364 BFD_RELOC_X86_64_GOTPCREL
},
7365 OPERAND_TYPE_IMM32_32S_DISP32
},
7366 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7367 BFD_RELOC_X86_64_TLSGD
},
7368 OPERAND_TYPE_IMM32_32S_DISP32
},
7369 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7370 _dummy_first_bfd_reloc_code_real
},
7371 OPERAND_TYPE_NONE
},
7372 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7373 BFD_RELOC_X86_64_TLSLD
},
7374 OPERAND_TYPE_IMM32_32S_DISP32
},
7375 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7376 BFD_RELOC_X86_64_GOTTPOFF
},
7377 OPERAND_TYPE_IMM32_32S_DISP32
},
7378 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7379 BFD_RELOC_X86_64_TPOFF32
},
7380 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7381 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7382 _dummy_first_bfd_reloc_code_real
},
7383 OPERAND_TYPE_NONE
},
7384 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7385 BFD_RELOC_X86_64_DTPOFF32
},
7386 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7387 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7388 _dummy_first_bfd_reloc_code_real
},
7389 OPERAND_TYPE_NONE
},
7390 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7391 _dummy_first_bfd_reloc_code_real
},
7392 OPERAND_TYPE_NONE
},
7393 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7394 BFD_RELOC_X86_64_GOT32
},
7395 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7396 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7397 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7398 OPERAND_TYPE_IMM32_32S_DISP32
},
7399 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7400 BFD_RELOC_X86_64_TLSDESC_CALL
},
7401 OPERAND_TYPE_IMM32_32S_DISP32
},
7406 #if defined (OBJ_MAYBE_ELF)
7411 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7412 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7415 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7417 int len
= gotrel
[j
].len
;
7418 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7420 if (gotrel
[j
].rel
[object_64bit
] != 0)
7423 char *tmpbuf
, *past_reloc
;
7425 *rel
= gotrel
[j
].rel
[object_64bit
];
7429 if (flag_code
!= CODE_64BIT
)
7431 types
->bitfield
.imm32
= 1;
7432 types
->bitfield
.disp32
= 1;
7435 *types
= gotrel
[j
].types64
;
7438 if (j
!= 0 && GOT_symbol
== NULL
)
7439 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7441 /* The length of the first part of our input line. */
7442 first
= cp
- input_line_pointer
;
7444 /* The second part goes from after the reloc token until
7445 (and including) an end_of_line char or comma. */
7446 past_reloc
= cp
+ 1 + len
;
7448 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7450 second
= cp
+ 1 - past_reloc
;
7452 /* Allocate and copy string. The trailing NUL shouldn't
7453 be necessary, but be safe. */
7454 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7455 memcpy (tmpbuf
, input_line_pointer
, first
);
7456 if (second
!= 0 && *past_reloc
!= ' ')
7457 /* Replace the relocation token with ' ', so that
7458 errors like foo@GOTOFF1 will be detected. */
7459 tmpbuf
[first
++] = ' ';
7461 /* Increment length by 1 if the relocation token is
7466 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7467 tmpbuf
[first
+ second
] = '\0';
7471 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7472 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7477 /* Might be a symbol version string. Don't as_bad here. */
7486 /* Parse operands of the form
7487 <symbol>@SECREL32+<nnn>
7489 If we find one, set up the correct relocation in RELOC and copy the
7490 input string, minus the `@SECREL32' into a malloc'd buffer for
7491 parsing by the calling routine. Return this buffer, and if ADJUST
7492 is non-null set it to the length of the string we removed from the
7493 input line. Otherwise return NULL.
7495 This function is copied from the ELF version above adjusted for PE targets. */
7498 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7499 int *adjust ATTRIBUTE_UNUSED
,
7500 i386_operand_type
*types
)
7506 const enum bfd_reloc_code_real rel
[2];
7507 const i386_operand_type types64
;
7511 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7512 BFD_RELOC_32_SECREL
},
7513 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7519 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7520 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7523 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7525 int len
= gotrel
[j
].len
;
7527 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7529 if (gotrel
[j
].rel
[object_64bit
] != 0)
7532 char *tmpbuf
, *past_reloc
;
7534 *rel
= gotrel
[j
].rel
[object_64bit
];
7540 if (flag_code
!= CODE_64BIT
)
7542 types
->bitfield
.imm32
= 1;
7543 types
->bitfield
.disp32
= 1;
7546 *types
= gotrel
[j
].types64
;
7549 /* The length of the first part of our input line. */
7550 first
= cp
- input_line_pointer
;
7552 /* The second part goes from after the reloc token until
7553 (and including) an end_of_line char or comma. */
7554 past_reloc
= cp
+ 1 + len
;
7556 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7558 second
= cp
+ 1 - past_reloc
;
7560 /* Allocate and copy string. The trailing NUL shouldn't
7561 be necessary, but be safe. */
7562 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7563 memcpy (tmpbuf
, input_line_pointer
, first
);
7564 if (second
!= 0 && *past_reloc
!= ' ')
7565 /* Replace the relocation token with ' ', so that
7566 errors like foo@SECLREL321 will be detected. */
7567 tmpbuf
[first
++] = ' ';
7568 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7569 tmpbuf
[first
+ second
] = '\0';
7573 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7574 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7579 /* Might be a symbol version string. Don't as_bad here. */
7585 bfd_reloc_code_real_type
7586 x86_cons (expressionS
*exp
, int size
)
7588 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7590 intel_syntax
= -intel_syntax
;
7593 if (size
== 4 || (object_64bit
&& size
== 8))
7595 /* Handle @GOTOFF and the like in an expression. */
7597 char *gotfree_input_line
;
7600 save
= input_line_pointer
;
7601 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7602 if (gotfree_input_line
)
7603 input_line_pointer
= gotfree_input_line
;
7607 if (gotfree_input_line
)
7609 /* expression () has merrily parsed up to the end of line,
7610 or a comma - in the wrong buffer. Transfer how far
7611 input_line_pointer has moved to the right buffer. */
7612 input_line_pointer
= (save
7613 + (input_line_pointer
- gotfree_input_line
)
7615 free (gotfree_input_line
);
7616 if (exp
->X_op
== O_constant
7617 || exp
->X_op
== O_absent
7618 || exp
->X_op
== O_illegal
7619 || exp
->X_op
== O_register
7620 || exp
->X_op
== O_big
)
7622 char c
= *input_line_pointer
;
7623 *input_line_pointer
= 0;
7624 as_bad (_("missing or invalid expression `%s'"), save
);
7625 *input_line_pointer
= c
;
7632 intel_syntax
= -intel_syntax
;
7635 i386_intel_simplify (exp
);
7641 signed_cons (int size
)
7643 if (flag_code
== CODE_64BIT
)
7651 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7658 if (exp
.X_op
== O_symbol
)
7659 exp
.X_op
= O_secrel
;
7661 emit_expr (&exp
, 4);
7663 while (*input_line_pointer
++ == ',');
7665 input_line_pointer
--;
7666 demand_empty_rest_of_line ();
7670 /* Handle Vector operations. */
7673 check_VecOperations (char *op_string
, char *op_end
)
7675 const reg_entry
*mask
;
7680 && (op_end
== NULL
|| op_string
< op_end
))
7683 if (*op_string
== '{')
7687 /* Check broadcasts. */
7688 if (strncmp (op_string
, "1to", 3) == 0)
7693 goto duplicated_vec_op
;
7696 if (*op_string
== '8')
7697 bcst_type
= BROADCAST_1TO8
;
7698 else if (*op_string
== '4')
7699 bcst_type
= BROADCAST_1TO4
;
7700 else if (*op_string
== '2')
7701 bcst_type
= BROADCAST_1TO2
;
7702 else if (*op_string
== '1'
7703 && *(op_string
+1) == '6')
7705 bcst_type
= BROADCAST_1TO16
;
7710 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7715 broadcast_op
.type
= bcst_type
;
7716 broadcast_op
.operand
= this_operand
;
7717 i
.broadcast
= &broadcast_op
;
7719 /* Check masking operation. */
7720 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7722 /* k0 can't be used for write mask. */
7723 if (mask
->reg_num
== 0)
7725 as_bad (_("`%s' can't be used for write mask"),
7732 mask_op
.mask
= mask
;
7733 mask_op
.zeroing
= 0;
7734 mask_op
.operand
= this_operand
;
7740 goto duplicated_vec_op
;
7742 i
.mask
->mask
= mask
;
7744 /* Only "{z}" is allowed here. No need to check
7745 zeroing mask explicitly. */
7746 if (i
.mask
->operand
!= this_operand
)
7748 as_bad (_("invalid write mask `%s'"), saved
);
7755 /* Check zeroing-flag for masking operation. */
7756 else if (*op_string
== 'z')
7760 mask_op
.mask
= NULL
;
7761 mask_op
.zeroing
= 1;
7762 mask_op
.operand
= this_operand
;
7767 if (i
.mask
->zeroing
)
7770 as_bad (_("duplicated `%s'"), saved
);
7774 i
.mask
->zeroing
= 1;
7776 /* Only "{%k}" is allowed here. No need to check mask
7777 register explicitly. */
7778 if (i
.mask
->operand
!= this_operand
)
7780 as_bad (_("invalid zeroing-masking `%s'"),
7789 goto unknown_vec_op
;
7791 if (*op_string
!= '}')
7793 as_bad (_("missing `}' in `%s'"), saved
);
7800 /* We don't know this one. */
7801 as_bad (_("unknown vector operation: `%s'"), saved
);
7809 i386_immediate (char *imm_start
)
7811 char *save_input_line_pointer
;
7812 char *gotfree_input_line
;
7815 i386_operand_type types
;
7817 operand_type_set (&types
, ~0);
7819 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7821 as_bad (_("at most %d immediate operands are allowed"),
7822 MAX_IMMEDIATE_OPERANDS
);
7826 exp
= &im_expressions
[i
.imm_operands
++];
7827 i
.op
[this_operand
].imms
= exp
;
7829 if (is_space_char (*imm_start
))
7832 save_input_line_pointer
= input_line_pointer
;
7833 input_line_pointer
= imm_start
;
7835 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7836 if (gotfree_input_line
)
7837 input_line_pointer
= gotfree_input_line
;
7839 exp_seg
= expression (exp
);
7843 /* Handle vector operations. */
7844 if (*input_line_pointer
== '{')
7846 input_line_pointer
= check_VecOperations (input_line_pointer
,
7848 if (input_line_pointer
== NULL
)
7852 if (*input_line_pointer
)
7853 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7855 input_line_pointer
= save_input_line_pointer
;
7856 if (gotfree_input_line
)
7858 free (gotfree_input_line
);
7860 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7861 exp
->X_op
= O_illegal
;
7864 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7868 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7869 i386_operand_type types
, const char *imm_start
)
7871 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7874 as_bad (_("missing or invalid immediate expression `%s'"),
7878 else if (exp
->X_op
== O_constant
)
7880 /* Size it properly later. */
7881 i
.types
[this_operand
].bitfield
.imm64
= 1;
7882 /* If not 64bit, sign extend val. */
7883 if (flag_code
!= CODE_64BIT
7884 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7886 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7888 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7889 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7890 && exp_seg
!= absolute_section
7891 && exp_seg
!= text_section
7892 && exp_seg
!= data_section
7893 && exp_seg
!= bss_section
7894 && exp_seg
!= undefined_section
7895 && !bfd_is_com_section (exp_seg
))
7897 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7901 else if (!intel_syntax
&& exp_seg
== reg_section
)
7904 as_bad (_("illegal immediate register operand %s"), imm_start
);
7909 /* This is an address. The size of the address will be
7910 determined later, depending on destination register,
7911 suffix, or the default for the section. */
7912 i
.types
[this_operand
].bitfield
.imm8
= 1;
7913 i
.types
[this_operand
].bitfield
.imm16
= 1;
7914 i
.types
[this_operand
].bitfield
.imm32
= 1;
7915 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7916 i
.types
[this_operand
].bitfield
.imm64
= 1;
7917 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7925 i386_scale (char *scale
)
7928 char *save
= input_line_pointer
;
7930 input_line_pointer
= scale
;
7931 val
= get_absolute_expression ();
7936 i
.log2_scale_factor
= 0;
7939 i
.log2_scale_factor
= 1;
7942 i
.log2_scale_factor
= 2;
7945 i
.log2_scale_factor
= 3;
7949 char sep
= *input_line_pointer
;
7951 *input_line_pointer
= '\0';
7952 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7954 *input_line_pointer
= sep
;
7955 input_line_pointer
= save
;
7959 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
7961 as_warn (_("scale factor of %d without an index register"),
7962 1 << i
.log2_scale_factor
);
7963 i
.log2_scale_factor
= 0;
7965 scale
= input_line_pointer
;
7966 input_line_pointer
= save
;
7971 i386_displacement (char *disp_start
, char *disp_end
)
7975 char *save_input_line_pointer
;
7976 char *gotfree_input_line
;
7978 i386_operand_type bigdisp
, types
= anydisp
;
7981 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
7983 as_bad (_("at most %d displacement operands are allowed"),
7984 MAX_MEMORY_OPERANDS
);
7988 operand_type_set (&bigdisp
, 0);
7989 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
7990 || (!current_templates
->start
->opcode_modifier
.jump
7991 && !current_templates
->start
->opcode_modifier
.jumpdword
))
7993 bigdisp
.bitfield
.disp32
= 1;
7994 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7995 if (flag_code
== CODE_64BIT
)
7999 bigdisp
.bitfield
.disp32s
= 1;
8000 bigdisp
.bitfield
.disp64
= 1;
8003 else if ((flag_code
== CODE_16BIT
) ^ override
)
8005 bigdisp
.bitfield
.disp32
= 0;
8006 bigdisp
.bitfield
.disp16
= 1;
8011 /* For PC-relative branches, the width of the displacement
8012 is dependent upon data size, not address size. */
8013 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8014 if (flag_code
== CODE_64BIT
)
8016 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8017 bigdisp
.bitfield
.disp16
= 1;
8020 bigdisp
.bitfield
.disp32
= 1;
8021 bigdisp
.bitfield
.disp32s
= 1;
8027 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8029 : LONG_MNEM_SUFFIX
));
8030 bigdisp
.bitfield
.disp32
= 1;
8031 if ((flag_code
== CODE_16BIT
) ^ override
)
8033 bigdisp
.bitfield
.disp32
= 0;
8034 bigdisp
.bitfield
.disp16
= 1;
8038 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8041 exp
= &disp_expressions
[i
.disp_operands
];
8042 i
.op
[this_operand
].disps
= exp
;
8044 save_input_line_pointer
= input_line_pointer
;
8045 input_line_pointer
= disp_start
;
8046 END_STRING_AND_SAVE (disp_end
);
8048 #ifndef GCC_ASM_O_HACK
8049 #define GCC_ASM_O_HACK 0
8052 END_STRING_AND_SAVE (disp_end
+ 1);
8053 if (i
.types
[this_operand
].bitfield
.baseIndex
8054 && displacement_string_end
[-1] == '+')
8056 /* This hack is to avoid a warning when using the "o"
8057 constraint within gcc asm statements.
8060 #define _set_tssldt_desc(n,addr,limit,type) \
8061 __asm__ __volatile__ ( \
8063 "movw %w1,2+%0\n\t" \
8065 "movb %b1,4+%0\n\t" \
8066 "movb %4,5+%0\n\t" \
8067 "movb $0,6+%0\n\t" \
8068 "movb %h1,7+%0\n\t" \
8070 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8072 This works great except that the output assembler ends
8073 up looking a bit weird if it turns out that there is
8074 no offset. You end up producing code that looks like:
8087 So here we provide the missing zero. */
8089 *displacement_string_end
= '0';
8092 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8093 if (gotfree_input_line
)
8094 input_line_pointer
= gotfree_input_line
;
8096 exp_seg
= expression (exp
);
8099 if (*input_line_pointer
)
8100 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8102 RESTORE_END_STRING (disp_end
+ 1);
8104 input_line_pointer
= save_input_line_pointer
;
8105 if (gotfree_input_line
)
8107 free (gotfree_input_line
);
8109 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8110 exp
->X_op
= O_illegal
;
8113 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8115 RESTORE_END_STRING (disp_end
);
8121 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8122 i386_operand_type types
, const char *disp_start
)
8124 i386_operand_type bigdisp
;
8127 /* We do this to make sure that the section symbol is in
8128 the symbol table. We will ultimately change the relocation
8129 to be relative to the beginning of the section. */
8130 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8131 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8132 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8134 if (exp
->X_op
!= O_symbol
)
8137 if (S_IS_LOCAL (exp
->X_add_symbol
)
8138 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8139 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8140 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8141 exp
->X_op
= O_subtract
;
8142 exp
->X_op_symbol
= GOT_symbol
;
8143 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8144 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8145 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8146 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8148 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8151 else if (exp
->X_op
== O_absent
8152 || exp
->X_op
== O_illegal
8153 || exp
->X_op
== O_big
)
8156 as_bad (_("missing or invalid displacement expression `%s'"),
8161 else if (flag_code
== CODE_64BIT
8162 && !i
.prefix
[ADDR_PREFIX
]
8163 && exp
->X_op
== O_constant
)
8165 /* Since displacement is signed extended to 64bit, don't allow
8166 disp32 and turn off disp32s if they are out of range. */
8167 i
.types
[this_operand
].bitfield
.disp32
= 0;
8168 if (!fits_in_signed_long (exp
->X_add_number
))
8170 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8171 if (i
.types
[this_operand
].bitfield
.baseindex
)
8173 as_bad (_("0x%lx out range of signed 32bit displacement"),
8174 (long) exp
->X_add_number
);
8180 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8181 else if (exp
->X_op
!= O_constant
8182 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8183 && exp_seg
!= absolute_section
8184 && exp_seg
!= text_section
8185 && exp_seg
!= data_section
8186 && exp_seg
!= bss_section
8187 && exp_seg
!= undefined_section
8188 && !bfd_is_com_section (exp_seg
))
8190 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8195 /* Check if this is a displacement only operand. */
8196 bigdisp
= i
.types
[this_operand
];
8197 bigdisp
.bitfield
.disp8
= 0;
8198 bigdisp
.bitfield
.disp16
= 0;
8199 bigdisp
.bitfield
.disp32
= 0;
8200 bigdisp
.bitfield
.disp32s
= 0;
8201 bigdisp
.bitfield
.disp64
= 0;
8202 if (operand_type_all_zero (&bigdisp
))
8203 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8209 /* Make sure the memory operand we've been dealt is valid.
8210 Return 1 on success, 0 on a failure. */
8213 i386_index_check (const char *operand_string
)
8215 const char *kind
= "base/index";
8216 enum flag_code addr_mode
;
8218 if (i
.prefix
[ADDR_PREFIX
])
8219 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8222 addr_mode
= flag_code
;
8224 #if INFER_ADDR_PREFIX
8225 if (i
.mem_operands
== 0)
8227 /* Infer address prefix from the first memory operand. */
8228 const reg_entry
*addr_reg
= i
.base_reg
;
8230 if (addr_reg
== NULL
)
8231 addr_reg
= i
.index_reg
;
8235 if (addr_reg
->reg_num
== RegEip
8236 || addr_reg
->reg_num
== RegEiz
8237 || addr_reg
->reg_type
.bitfield
.reg32
)
8238 addr_mode
= CODE_32BIT
;
8239 else if (flag_code
!= CODE_64BIT
8240 && addr_reg
->reg_type
.bitfield
.reg16
)
8241 addr_mode
= CODE_16BIT
;
8243 if (addr_mode
!= flag_code
)
8245 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8247 /* Change the size of any displacement too. At most one
8248 of Disp16 or Disp32 is set.
8249 FIXME. There doesn't seem to be any real need for
8250 separate Disp16 and Disp32 flags. The same goes for
8251 Imm16 and Imm32. Removing them would probably clean
8252 up the code quite a lot. */
8253 if (flag_code
!= CODE_64BIT
8254 && (i
.types
[this_operand
].bitfield
.disp16
8255 || i
.types
[this_operand
].bitfield
.disp32
))
8256 i
.types
[this_operand
]
8257 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8264 if (current_templates
->start
->opcode_modifier
.isstring
8265 && !current_templates
->start
->opcode_modifier
.immext
8266 && (current_templates
->end
[-1].opcode_modifier
.isstring
8269 /* Memory operands of string insns are special in that they only allow
8270 a single register (rDI, rSI, or rBX) as their memory address. */
8271 const reg_entry
*expected_reg
;
8272 static const char *di_si
[][2] =
8278 static const char *bx
[] = { "ebx", "bx", "rbx" };
8280 kind
= "string address";
8282 if (current_templates
->start
->opcode_modifier
.w
)
8284 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8286 if (!type
.bitfield
.baseindex
8287 || ((!i
.mem_operands
!= !intel_syntax
)
8288 && current_templates
->end
[-1].operand_types
[1]
8289 .bitfield
.baseindex
))
8290 type
= current_templates
->end
[-1].operand_types
[1];
8291 expected_reg
= hash_find (reg_hash
,
8292 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8296 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8298 if (i
.base_reg
!= expected_reg
8300 || operand_type_check (i
.types
[this_operand
], disp
))
8302 /* The second memory operand must have the same size as
8306 && !((addr_mode
== CODE_64BIT
8307 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8308 || (addr_mode
== CODE_32BIT
8309 ? i
.base_reg
->reg_type
.bitfield
.reg32
8310 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8313 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8315 intel_syntax
? '[' : '(',
8317 expected_reg
->reg_name
,
8318 intel_syntax
? ']' : ')');
8325 as_bad (_("`%s' is not a valid %s expression"),
8326 operand_string
, kind
);
8331 if (addr_mode
!= CODE_16BIT
)
8333 /* 32-bit/64-bit checks. */
8335 && (addr_mode
== CODE_64BIT
8336 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8337 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8339 || (i
.base_reg
->reg_num
8340 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8342 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8343 && !i
.index_reg
->reg_type
.bitfield
.regymm
8344 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8345 && ((addr_mode
== CODE_64BIT
8346 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8347 || i
.index_reg
->reg_num
== RegRiz
)
8348 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8349 || i
.index_reg
->reg_num
== RegEiz
))
8350 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8355 /* 16-bit checks. */
8357 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8358 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8360 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8361 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8363 && i
.base_reg
->reg_num
< 6
8364 && i
.index_reg
->reg_num
>= 6
8365 && i
.log2_scale_factor
== 0))))
8372 /* Handle vector immediates. */
8375 RC_SAE_immediate (const char *imm_start
)
8377 unsigned int match_found
, j
;
8378 const char *pstr
= imm_start
;
8386 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8388 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8392 rc_op
.type
= RC_NamesTable
[j
].type
;
8393 rc_op
.operand
= this_operand
;
8394 i
.rounding
= &rc_op
;
8398 as_bad (_("duplicated `%s'"), imm_start
);
8401 pstr
+= RC_NamesTable
[j
].len
;
8411 as_bad (_("Missing '}': '%s'"), imm_start
);
8414 /* RC/SAE immediate string should contain nothing more. */;
8417 as_bad (_("Junk after '}': '%s'"), imm_start
);
8421 exp
= &im_expressions
[i
.imm_operands
++];
8422 i
.op
[this_operand
].imms
= exp
;
8424 exp
->X_op
= O_constant
;
8425 exp
->X_add_number
= 0;
8426 exp
->X_add_symbol
= (symbolS
*) 0;
8427 exp
->X_op_symbol
= (symbolS
*) 0;
8429 i
.types
[this_operand
].bitfield
.imm8
= 1;
8433 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8437 i386_att_operand (char *operand_string
)
8441 char *op_string
= operand_string
;
8443 if (is_space_char (*op_string
))
8446 /* We check for an absolute prefix (differentiating,
8447 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8448 if (*op_string
== ABSOLUTE_PREFIX
)
8451 if (is_space_char (*op_string
))
8453 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8456 /* Check if operand is a register. */
8457 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8459 i386_operand_type temp
;
8461 /* Check for a segment override by searching for ':' after a
8462 segment register. */
8464 if (is_space_char (*op_string
))
8466 if (*op_string
== ':'
8467 && (r
->reg_type
.bitfield
.sreg2
8468 || r
->reg_type
.bitfield
.sreg3
))
8473 i
.seg
[i
.mem_operands
] = &es
;
8476 i
.seg
[i
.mem_operands
] = &cs
;
8479 i
.seg
[i
.mem_operands
] = &ss
;
8482 i
.seg
[i
.mem_operands
] = &ds
;
8485 i
.seg
[i
.mem_operands
] = &fs
;
8488 i
.seg
[i
.mem_operands
] = &gs
;
8492 /* Skip the ':' and whitespace. */
8494 if (is_space_char (*op_string
))
8497 if (!is_digit_char (*op_string
)
8498 && !is_identifier_char (*op_string
)
8499 && *op_string
!= '('
8500 && *op_string
!= ABSOLUTE_PREFIX
)
8502 as_bad (_("bad memory operand `%s'"), op_string
);
8505 /* Handle case of %es:*foo. */
8506 if (*op_string
== ABSOLUTE_PREFIX
)
8509 if (is_space_char (*op_string
))
8511 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8513 goto do_memory_reference
;
8516 /* Handle vector operations. */
8517 if (*op_string
== '{')
8519 op_string
= check_VecOperations (op_string
, NULL
);
8520 if (op_string
== NULL
)
8526 as_bad (_("junk `%s' after register"), op_string
);
8530 temp
.bitfield
.baseindex
= 0;
8531 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8533 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8534 i
.op
[this_operand
].regs
= r
;
8537 else if (*op_string
== REGISTER_PREFIX
)
8539 as_bad (_("bad register name `%s'"), op_string
);
8542 else if (*op_string
== IMMEDIATE_PREFIX
)
8545 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8547 as_bad (_("immediate operand illegal with absolute jump"));
8550 if (!i386_immediate (op_string
))
8553 else if (RC_SAE_immediate (operand_string
))
8555 /* If it is a RC or SAE immediate, do nothing. */
8558 else if (is_digit_char (*op_string
)
8559 || is_identifier_char (*op_string
)
8560 || *op_string
== '(')
8562 /* This is a memory reference of some sort. */
8565 /* Start and end of displacement string expression (if found). */
8566 char *displacement_string_start
;
8567 char *displacement_string_end
;
8570 do_memory_reference
:
8571 if ((i
.mem_operands
== 1
8572 && !current_templates
->start
->opcode_modifier
.isstring
)
8573 || i
.mem_operands
== 2)
8575 as_bad (_("too many memory references for `%s'"),
8576 current_templates
->start
->name
);
8580 /* Check for base index form. We detect the base index form by
8581 looking for an ')' at the end of the operand, searching
8582 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8584 base_string
= op_string
+ strlen (op_string
);
8586 /* Handle vector operations. */
8587 vop_start
= strchr (op_string
, '{');
8588 if (vop_start
&& vop_start
< base_string
)
8590 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8592 base_string
= vop_start
;
8596 if (is_space_char (*base_string
))
8599 /* If we only have a displacement, set-up for it to be parsed later. */
8600 displacement_string_start
= op_string
;
8601 displacement_string_end
= base_string
+ 1;
8603 if (*base_string
== ')')
8606 unsigned int parens_balanced
= 1;
8607 /* We've already checked that the number of left & right ()'s are
8608 equal, so this loop will not be infinite. */
8612 if (*base_string
== ')')
8614 if (*base_string
== '(')
8617 while (parens_balanced
);
8619 temp_string
= base_string
;
8621 /* Skip past '(' and whitespace. */
8623 if (is_space_char (*base_string
))
8626 if (*base_string
== ','
8627 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8630 displacement_string_end
= temp_string
;
8632 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8636 base_string
= end_op
;
8637 if (is_space_char (*base_string
))
8641 /* There may be an index reg or scale factor here. */
8642 if (*base_string
== ',')
8645 if (is_space_char (*base_string
))
8648 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8651 base_string
= end_op
;
8652 if (is_space_char (*base_string
))
8654 if (*base_string
== ',')
8657 if (is_space_char (*base_string
))
8660 else if (*base_string
!= ')')
8662 as_bad (_("expecting `,' or `)' "
8663 "after index register in `%s'"),
8668 else if (*base_string
== REGISTER_PREFIX
)
8670 end_op
= strchr (base_string
, ',');
8673 as_bad (_("bad register name `%s'"), base_string
);
8677 /* Check for scale factor. */
8678 if (*base_string
!= ')')
8680 char *end_scale
= i386_scale (base_string
);
8685 base_string
= end_scale
;
8686 if (is_space_char (*base_string
))
8688 if (*base_string
!= ')')
8690 as_bad (_("expecting `)' "
8691 "after scale factor in `%s'"),
8696 else if (!i
.index_reg
)
8698 as_bad (_("expecting index register or scale factor "
8699 "after `,'; got '%c'"),
8704 else if (*base_string
!= ')')
8706 as_bad (_("expecting `,' or `)' "
8707 "after base register in `%s'"),
8712 else if (*base_string
== REGISTER_PREFIX
)
8714 end_op
= strchr (base_string
, ',');
8717 as_bad (_("bad register name `%s'"), base_string
);
8722 /* If there's an expression beginning the operand, parse it,
8723 assuming displacement_string_start and
8724 displacement_string_end are meaningful. */
8725 if (displacement_string_start
!= displacement_string_end
)
8727 if (!i386_displacement (displacement_string_start
,
8728 displacement_string_end
))
8732 /* Special case for (%dx) while doing input/output op. */
8734 && operand_type_equal (&i
.base_reg
->reg_type
,
8735 ®16_inoutportreg
)
8737 && i
.log2_scale_factor
== 0
8738 && i
.seg
[i
.mem_operands
] == 0
8739 && !operand_type_check (i
.types
[this_operand
], disp
))
8741 i
.types
[this_operand
] = inoutportreg
;
8745 if (i386_index_check (operand_string
) == 0)
8747 i
.types
[this_operand
].bitfield
.mem
= 1;
8752 /* It's not a memory operand; argh! */
8753 as_bad (_("invalid char %s beginning operand %d `%s'"),
8754 output_invalid (*op_string
),
8759 return 1; /* Normal return. */
8762 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8763 that an rs_machine_dependent frag may reach. */
8766 i386_frag_max_var (fragS
*frag
)
8768 /* The only relaxable frags are for jumps.
8769 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8770 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8771 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8774 /* md_estimate_size_before_relax()
8776 Called just before relax() for rs_machine_dependent frags. The x86
8777 assembler uses these frags to handle variable size jump
8780 Any symbol that is now undefined will not become defined.
8781 Return the correct fr_subtype in the frag.
8782 Return the initial "guess for variable size of frag" to caller.
8783 The guess is actually the growth beyond the fixed part. Whatever
8784 we do to grow the fixed or variable part contributes to our
8788 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8790 /* We've already got fragP->fr_subtype right; all we have to do is
8791 check for un-relaxable symbols. On an ELF system, we can't relax
8792 an externally visible symbol, because it may be overridden by a
8794 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8795 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8797 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8798 || S_IS_WEAK (fragP
->fr_symbol
)
8799 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8800 & BSF_GNU_INDIRECT_FUNCTION
))))
8802 #if defined (OBJ_COFF) && defined (TE_PE)
8803 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8804 && S_IS_WEAK (fragP
->fr_symbol
))
8808 /* Symbol is undefined in this segment, or we need to keep a
8809 reloc so that weak symbols can be overridden. */
8810 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8811 enum bfd_reloc_code_real reloc_type
;
8812 unsigned char *opcode
;
8815 if (fragP
->fr_var
!= NO_RELOC
)
8816 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8818 reloc_type
= BFD_RELOC_16_PCREL
;
8820 reloc_type
= BFD_RELOC_32_PCREL
;
8822 old_fr_fix
= fragP
->fr_fix
;
8823 opcode
= (unsigned char *) fragP
->fr_opcode
;
8825 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8828 /* Make jmp (0xeb) a (d)word displacement jump. */
8830 fragP
->fr_fix
+= size
;
8831 fix_new (fragP
, old_fr_fix
, size
,
8833 fragP
->fr_offset
, 1,
8839 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8841 /* Negate the condition, and branch past an
8842 unconditional jump. */
8845 /* Insert an unconditional jump. */
8847 /* We added two extra opcode bytes, and have a two byte
8849 fragP
->fr_fix
+= 2 + 2;
8850 fix_new (fragP
, old_fr_fix
+ 2, 2,
8852 fragP
->fr_offset
, 1,
8859 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8864 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8866 fragP
->fr_offset
, 1,
8868 fixP
->fx_signed
= 1;
8872 /* This changes the byte-displacement jump 0x7N
8873 to the (d)word-displacement jump 0x0f,0x8N. */
8874 opcode
[1] = opcode
[0] + 0x10;
8875 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8876 /* We've added an opcode byte. */
8877 fragP
->fr_fix
+= 1 + size
;
8878 fix_new (fragP
, old_fr_fix
+ 1, size
,
8880 fragP
->fr_offset
, 1,
8885 BAD_CASE (fragP
->fr_subtype
);
8889 return fragP
->fr_fix
- old_fr_fix
;
8892 /* Guess size depending on current relax state. Initially the relax
8893 state will correspond to a short jump and we return 1, because
8894 the variable part of the frag (the branch offset) is one byte
8895 long. However, we can relax a section more than once and in that
8896 case we must either set fr_subtype back to the unrelaxed state,
8897 or return the value for the appropriate branch. */
8898 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8901 /* Called after relax() is finished.
8903 In: Address of frag.
8904 fr_type == rs_machine_dependent.
8905 fr_subtype is what the address relaxed to.
8907 Out: Any fixSs and constants are set up.
8908 Caller will turn frag into a ".space 0". */
8911 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8914 unsigned char *opcode
;
8915 unsigned char *where_to_put_displacement
= NULL
;
8916 offsetT target_address
;
8917 offsetT opcode_address
;
8918 unsigned int extension
= 0;
8919 offsetT displacement_from_opcode_start
;
8921 opcode
= (unsigned char *) fragP
->fr_opcode
;
8923 /* Address we want to reach in file space. */
8924 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
8926 /* Address opcode resides at in file space. */
8927 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
8929 /* Displacement from opcode start to fill into instruction. */
8930 displacement_from_opcode_start
= target_address
- opcode_address
;
8932 if ((fragP
->fr_subtype
& BIG
) == 0)
8934 /* Don't have to change opcode. */
8935 extension
= 1; /* 1 opcode + 1 displacement */
8936 where_to_put_displacement
= &opcode
[1];
8940 if (no_cond_jump_promotion
8941 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
8942 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
8943 _("long jump required"));
8945 switch (fragP
->fr_subtype
)
8947 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
8948 extension
= 4; /* 1 opcode + 4 displacement */
8950 where_to_put_displacement
= &opcode
[1];
8953 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
8954 extension
= 2; /* 1 opcode + 2 displacement */
8956 where_to_put_displacement
= &opcode
[1];
8959 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
8960 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
8961 extension
= 5; /* 2 opcode + 4 displacement */
8962 opcode
[1] = opcode
[0] + 0x10;
8963 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8964 where_to_put_displacement
= &opcode
[2];
8967 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
8968 extension
= 3; /* 2 opcode + 2 displacement */
8969 opcode
[1] = opcode
[0] + 0x10;
8970 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8971 where_to_put_displacement
= &opcode
[2];
8974 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
8979 where_to_put_displacement
= &opcode
[3];
8983 BAD_CASE (fragP
->fr_subtype
);
8988 /* If size if less then four we are sure that the operand fits,
8989 but if it's 4, then it could be that the displacement is larger
8991 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
8993 && ((addressT
) (displacement_from_opcode_start
- extension
8994 + ((addressT
) 1 << 31))
8995 > (((addressT
) 2 << 31) - 1)))
8997 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
8998 _("jump target out of range"));
8999 /* Make us emit 0. */
9000 displacement_from_opcode_start
= extension
;
9002 /* Now put displacement after opcode. */
9003 md_number_to_chars ((char *) where_to_put_displacement
,
9004 (valueT
) (displacement_from_opcode_start
- extension
),
9005 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9006 fragP
->fr_fix
+= extension
;
9009 /* Apply a fixup (fixP) to segment data, once it has been determined
9010 by our caller that we have all the info we need to fix it up.
9012 Parameter valP is the pointer to the value of the bits.
9014 On the 386, immediates, displacements, and data pointers are all in
9015 the same (little-endian) format, so we don't need to care about which
9019 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9021 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9022 valueT value
= *valP
;
9024 #if !defined (TE_Mach)
9027 switch (fixP
->fx_r_type
)
9033 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9036 case BFD_RELOC_X86_64_32S
:
9037 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9040 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9043 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9048 if (fixP
->fx_addsy
!= NULL
9049 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9050 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9051 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9052 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9053 && !use_rela_relocations
)
9055 /* This is a hack. There should be a better way to handle this.
9056 This covers for the fact that bfd_install_relocation will
9057 subtract the current location (for partial_inplace, PC relative
9058 relocations); see more below. */
9062 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9065 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9070 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9073 || (symbol_section_p (fixP
->fx_addsy
)
9074 && sym_seg
!= absolute_section
))
9075 && !generic_force_reloc (fixP
))
9077 /* Yes, we add the values in twice. This is because
9078 bfd_install_relocation subtracts them out again. I think
9079 bfd_install_relocation is broken, but I don't dare change
9081 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9085 #if defined (OBJ_COFF) && defined (TE_PE)
9086 /* For some reason, the PE format does not store a
9087 section address offset for a PC relative symbol. */
9088 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9089 || S_IS_WEAK (fixP
->fx_addsy
))
9090 value
+= md_pcrel_from (fixP
);
9093 #if defined (OBJ_COFF) && defined (TE_PE)
9094 if (fixP
->fx_addsy
!= NULL
9095 && S_IS_WEAK (fixP
->fx_addsy
)
9096 /* PR 16858: Do not modify weak function references. */
9097 && ! fixP
->fx_pcrel
)
9099 #if !defined (TE_PEP)
9100 /* For x86 PE weak function symbols are neither PC-relative
9101 nor do they set S_IS_FUNCTION. So the only reliable way
9102 to detect them is to check the flags of their containing
9104 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9105 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9109 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9113 /* Fix a few things - the dynamic linker expects certain values here,
9114 and we must not disappoint it. */
9115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9116 if (IS_ELF
&& fixP
->fx_addsy
)
9117 switch (fixP
->fx_r_type
)
9119 case BFD_RELOC_386_PLT32
:
9120 case BFD_RELOC_X86_64_PLT32
:
9121 /* Make the jump instruction point to the address of the operand. At
9122 runtime we merely add the offset to the actual PLT entry. */
9126 case BFD_RELOC_386_TLS_GD
:
9127 case BFD_RELOC_386_TLS_LDM
:
9128 case BFD_RELOC_386_TLS_IE_32
:
9129 case BFD_RELOC_386_TLS_IE
:
9130 case BFD_RELOC_386_TLS_GOTIE
:
9131 case BFD_RELOC_386_TLS_GOTDESC
:
9132 case BFD_RELOC_X86_64_TLSGD
:
9133 case BFD_RELOC_X86_64_TLSLD
:
9134 case BFD_RELOC_X86_64_GOTTPOFF
:
9135 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9136 value
= 0; /* Fully resolved at runtime. No addend. */
9138 case BFD_RELOC_386_TLS_LE
:
9139 case BFD_RELOC_386_TLS_LDO_32
:
9140 case BFD_RELOC_386_TLS_LE_32
:
9141 case BFD_RELOC_X86_64_DTPOFF32
:
9142 case BFD_RELOC_X86_64_DTPOFF64
:
9143 case BFD_RELOC_X86_64_TPOFF32
:
9144 case BFD_RELOC_X86_64_TPOFF64
:
9145 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9148 case BFD_RELOC_386_TLS_DESC_CALL
:
9149 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9150 value
= 0; /* Fully resolved at runtime. No addend. */
9151 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9155 case BFD_RELOC_386_GOT32
:
9156 case BFD_RELOC_X86_64_GOT32
:
9157 value
= 0; /* Fully resolved at runtime. No addend. */
9160 case BFD_RELOC_VTABLE_INHERIT
:
9161 case BFD_RELOC_VTABLE_ENTRY
:
9168 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9170 #endif /* !defined (TE_Mach) */
9172 /* Are we finished with this relocation now? */
9173 if (fixP
->fx_addsy
== NULL
)
9175 #if defined (OBJ_COFF) && defined (TE_PE)
9176 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9179 /* Remember value for tc_gen_reloc. */
9180 fixP
->fx_addnumber
= value
;
9181 /* Clear out the frag for now. */
9185 else if (use_rela_relocations
)
9187 fixP
->fx_no_overflow
= 1;
9188 /* Remember value for tc_gen_reloc. */
9189 fixP
->fx_addnumber
= value
;
9193 md_number_to_chars (p
, value
, fixP
->fx_size
);
9197 md_atof (int type
, char *litP
, int *sizeP
)
9199 /* This outputs the LITTLENUMs in REVERSE order;
9200 in accord with the bigendian 386. */
9201 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9204 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9207 output_invalid (int c
)
9210 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9213 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9214 "(0x%x)", (unsigned char) c
);
9215 return output_invalid_buf
;
9218 /* REG_STRING starts *before* REGISTER_PREFIX. */
9220 static const reg_entry
*
9221 parse_real_register (char *reg_string
, char **end_op
)
9223 char *s
= reg_string
;
9225 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9228 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9229 if (*s
== REGISTER_PREFIX
)
9232 if (is_space_char (*s
))
9236 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9238 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9239 return (const reg_entry
*) NULL
;
9243 /* For naked regs, make sure that we are not dealing with an identifier.
9244 This prevents confusing an identifier like `eax_var' with register
9246 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9247 return (const reg_entry
*) NULL
;
9251 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9253 /* Handle floating point regs, allowing spaces in the (i) part. */
9254 if (r
== i386_regtab
/* %st is first entry of table */)
9256 if (is_space_char (*s
))
9261 if (is_space_char (*s
))
9263 if (*s
>= '0' && *s
<= '7')
9267 if (is_space_char (*s
))
9272 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9277 /* We have "%st(" then garbage. */
9278 return (const reg_entry
*) NULL
;
9282 if (r
== NULL
|| allow_pseudo_reg
)
9285 if (operand_type_all_zero (&r
->reg_type
))
9286 return (const reg_entry
*) NULL
;
9288 if ((r
->reg_type
.bitfield
.reg32
9289 || r
->reg_type
.bitfield
.sreg3
9290 || r
->reg_type
.bitfield
.control
9291 || r
->reg_type
.bitfield
.debug
9292 || r
->reg_type
.bitfield
.test
)
9293 && !cpu_arch_flags
.bitfield
.cpui386
)
9294 return (const reg_entry
*) NULL
;
9296 if (r
->reg_type
.bitfield
.floatreg
9297 && !cpu_arch_flags
.bitfield
.cpu8087
9298 && !cpu_arch_flags
.bitfield
.cpu287
9299 && !cpu_arch_flags
.bitfield
.cpu387
)
9300 return (const reg_entry
*) NULL
;
9302 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9303 return (const reg_entry
*) NULL
;
9305 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9306 return (const reg_entry
*) NULL
;
9308 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9309 return (const reg_entry
*) NULL
;
9311 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9312 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9313 return (const reg_entry
*) NULL
;
9315 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9316 if (!allow_index_reg
9317 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9318 return (const reg_entry
*) NULL
;
9320 /* Upper 16 vector register is only available with VREX in 64bit
9322 if ((r
->reg_flags
& RegVRex
))
9324 if (!cpu_arch_flags
.bitfield
.cpuvrex
9325 || flag_code
!= CODE_64BIT
)
9326 return (const reg_entry
*) NULL
;
9331 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9332 || r
->reg_type
.bitfield
.reg64
)
9333 && (!cpu_arch_flags
.bitfield
.cpulm
9334 || !operand_type_equal (&r
->reg_type
, &control
))
9335 && flag_code
!= CODE_64BIT
)
9336 return (const reg_entry
*) NULL
;
9338 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9339 return (const reg_entry
*) NULL
;
9344 /* REG_STRING starts *before* REGISTER_PREFIX. */
9346 static const reg_entry
*
9347 parse_register (char *reg_string
, char **end_op
)
9351 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9352 r
= parse_real_register (reg_string
, end_op
);
9357 char *save
= input_line_pointer
;
9361 input_line_pointer
= reg_string
;
9362 c
= get_symbol_end ();
9363 symbolP
= symbol_find (reg_string
);
9364 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9366 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9368 know (e
->X_op
== O_register
);
9369 know (e
->X_add_number
>= 0
9370 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9371 r
= i386_regtab
+ e
->X_add_number
;
9372 if ((r
->reg_flags
& RegVRex
))
9374 *end_op
= input_line_pointer
;
9376 *input_line_pointer
= c
;
9377 input_line_pointer
= save
;
9383 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9386 char *end
= input_line_pointer
;
9389 r
= parse_register (name
, &input_line_pointer
);
9390 if (r
&& end
<= input_line_pointer
)
9392 *nextcharP
= *input_line_pointer
;
9393 *input_line_pointer
= 0;
9394 e
->X_op
= O_register
;
9395 e
->X_add_number
= r
- i386_regtab
;
9398 input_line_pointer
= end
;
9400 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9404 md_operand (expressionS
*e
)
9409 switch (*input_line_pointer
)
9411 case REGISTER_PREFIX
:
9412 r
= parse_real_register (input_line_pointer
, &end
);
9415 e
->X_op
= O_register
;
9416 e
->X_add_number
= r
- i386_regtab
;
9417 input_line_pointer
= end
;
9422 gas_assert (intel_syntax
);
9423 end
= input_line_pointer
++;
9425 if (*input_line_pointer
== ']')
9427 ++input_line_pointer
;
9428 e
->X_op_symbol
= make_expr_symbol (e
);
9429 e
->X_add_symbol
= NULL
;
9430 e
->X_add_number
= 0;
9436 input_line_pointer
= end
;
9443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9444 const char *md_shortopts
= "kVQ:sqn";
9446 const char *md_shortopts
= "qn";
9449 #define OPTION_32 (OPTION_MD_BASE + 0)
9450 #define OPTION_64 (OPTION_MD_BASE + 1)
9451 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9452 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9453 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9454 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9455 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9456 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9457 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9458 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9459 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9460 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9461 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9462 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9463 #define OPTION_X32 (OPTION_MD_BASE + 14)
9464 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9465 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9466 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9467 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9468 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9469 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9471 struct option md_longopts
[] =
9473 {"32", no_argument
, NULL
, OPTION_32
},
9474 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9475 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9476 {"64", no_argument
, NULL
, OPTION_64
},
9478 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9479 {"x32", no_argument
, NULL
, OPTION_X32
},
9481 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9482 {"march", required_argument
, NULL
, OPTION_MARCH
},
9483 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9484 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9485 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9486 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9487 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9488 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9489 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9490 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9491 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9492 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9493 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9494 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9495 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9496 # if defined (TE_PE) || defined (TE_PEP)
9497 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9499 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9500 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9501 {NULL
, no_argument
, NULL
, 0}
9503 size_t md_longopts_size
= sizeof (md_longopts
);
9506 md_parse_option (int c
, char *arg
)
9514 optimize_align_code
= 0;
9521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9522 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9523 should be emitted or not. FIXME: Not implemented. */
9527 /* -V: SVR4 argument to print version ID. */
9529 print_version_id ();
9532 /* -k: Ignore for FreeBSD compatibility. */
9537 /* -s: On i386 Solaris, this tells the native assembler to use
9538 .stab instead of .stab.excl. We always use .stab anyhow. */
9541 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9542 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9545 const char **list
, **l
;
9547 list
= bfd_target_list ();
9548 for (l
= list
; *l
!= NULL
; l
++)
9549 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9550 || strcmp (*l
, "coff-x86-64") == 0
9551 || strcmp (*l
, "pe-x86-64") == 0
9552 || strcmp (*l
, "pei-x86-64") == 0
9553 || strcmp (*l
, "mach-o-x86-64") == 0)
9555 default_arch
= "x86_64";
9559 as_fatal (_("no compiled in support for x86_64"));
9565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9569 const char **list
, **l
;
9571 list
= bfd_target_list ();
9572 for (l
= list
; *l
!= NULL
; l
++)
9573 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9575 default_arch
= "x86_64:32";
9579 as_fatal (_("no compiled in support for 32bit x86_64"));
9583 as_fatal (_("32bit x86_64 is only supported for ELF"));
9588 default_arch
= "i386";
9592 #ifdef SVR4_COMMENT_CHARS
9597 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9599 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9603 i386_comment_chars
= n
;
9609 arch
= xstrdup (arg
);
9613 as_fatal (_("invalid -march= option: `%s'"), arg
);
9614 next
= strchr (arch
, '+');
9617 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9619 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9622 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9625 cpu_arch_name
= cpu_arch
[j
].name
;
9626 cpu_sub_arch_name
= NULL
;
9627 cpu_arch_flags
= cpu_arch
[j
].flags
;
9628 cpu_arch_isa
= cpu_arch
[j
].type
;
9629 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9630 if (!cpu_arch_tune_set
)
9632 cpu_arch_tune
= cpu_arch_isa
;
9633 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9637 else if (*cpu_arch
[j
].name
== '.'
9638 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9640 /* ISA entension. */
9641 i386_cpu_flags flags
;
9643 if (!cpu_arch
[j
].negated
)
9644 flags
= cpu_flags_or (cpu_arch_flags
,
9647 flags
= cpu_flags_and_not (cpu_arch_flags
,
9649 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9651 if (cpu_sub_arch_name
)
9653 char *name
= cpu_sub_arch_name
;
9654 cpu_sub_arch_name
= concat (name
,
9656 (const char *) NULL
);
9660 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9661 cpu_arch_flags
= flags
;
9662 cpu_arch_isa_flags
= flags
;
9668 if (j
>= ARRAY_SIZE (cpu_arch
))
9669 as_fatal (_("invalid -march= option: `%s'"), arg
);
9673 while (next
!= NULL
);
9678 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9679 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9681 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9683 cpu_arch_tune_set
= 1;
9684 cpu_arch_tune
= cpu_arch
[j
].type
;
9685 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9689 if (j
>= ARRAY_SIZE (cpu_arch
))
9690 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9693 case OPTION_MMNEMONIC
:
9694 if (strcasecmp (arg
, "att") == 0)
9696 else if (strcasecmp (arg
, "intel") == 0)
9699 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9702 case OPTION_MSYNTAX
:
9703 if (strcasecmp (arg
, "att") == 0)
9705 else if (strcasecmp (arg
, "intel") == 0)
9708 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9711 case OPTION_MINDEX_REG
:
9712 allow_index_reg
= 1;
9715 case OPTION_MNAKED_REG
:
9716 allow_naked_reg
= 1;
9719 case OPTION_MOLD_GCC
:
9723 case OPTION_MSSE2AVX
:
9727 case OPTION_MSSE_CHECK
:
9728 if (strcasecmp (arg
, "error") == 0)
9729 sse_check
= check_error
;
9730 else if (strcasecmp (arg
, "warning") == 0)
9731 sse_check
= check_warning
;
9732 else if (strcasecmp (arg
, "none") == 0)
9733 sse_check
= check_none
;
9735 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9738 case OPTION_MOPERAND_CHECK
:
9739 if (strcasecmp (arg
, "error") == 0)
9740 operand_check
= check_error
;
9741 else if (strcasecmp (arg
, "warning") == 0)
9742 operand_check
= check_warning
;
9743 else if (strcasecmp (arg
, "none") == 0)
9744 operand_check
= check_none
;
9746 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9749 case OPTION_MAVXSCALAR
:
9750 if (strcasecmp (arg
, "128") == 0)
9752 else if (strcasecmp (arg
, "256") == 0)
9755 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9758 case OPTION_MADD_BND_PREFIX
:
9762 case OPTION_MEVEXLIG
:
9763 if (strcmp (arg
, "128") == 0)
9765 else if (strcmp (arg
, "256") == 0)
9767 else if (strcmp (arg
, "512") == 0)
9770 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9773 case OPTION_MEVEXRCIG
:
9774 if (strcmp (arg
, "rne") == 0)
9776 else if (strcmp (arg
, "rd") == 0)
9778 else if (strcmp (arg
, "ru") == 0)
9780 else if (strcmp (arg
, "rz") == 0)
9783 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9786 case OPTION_MEVEXWIG
:
9787 if (strcmp (arg
, "0") == 0)
9789 else if (strcmp (arg
, "1") == 0)
9792 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9795 # if defined (TE_PE) || defined (TE_PEP)
9796 case OPTION_MBIG_OBJ
:
9801 case OPTION_OMIT_LOCK_PREFIX
:
9802 if (strcasecmp (arg
, "yes") == 0)
9803 omit_lock_prefix
= 1;
9804 else if (strcasecmp (arg
, "no") == 0)
9805 omit_lock_prefix
= 0;
9807 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9816 #define MESSAGE_TEMPLATE \
9820 show_arch (FILE *stream
, int ext
, int check
)
9822 static char message
[] = MESSAGE_TEMPLATE
;
9823 char *start
= message
+ 27;
9825 int size
= sizeof (MESSAGE_TEMPLATE
);
9832 left
= size
- (start
- message
);
9833 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9835 /* Should it be skipped? */
9836 if (cpu_arch
[j
].skip
)
9839 name
= cpu_arch
[j
].name
;
9840 len
= cpu_arch
[j
].len
;
9843 /* It is an extension. Skip if we aren't asked to show it. */
9854 /* It is an processor. Skip if we show only extension. */
9857 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9859 /* It is an impossible processor - skip. */
9863 /* Reserve 2 spaces for ", " or ",\0" */
9866 /* Check if there is any room. */
9874 p
= mempcpy (p
, name
, len
);
9878 /* Output the current message now and start a new one. */
9881 fprintf (stream
, "%s\n", message
);
9883 left
= size
- (start
- message
) - len
- 2;
9885 gas_assert (left
>= 0);
9887 p
= mempcpy (p
, name
, len
);
9892 fprintf (stream
, "%s\n", message
);
9896 md_show_usage (FILE *stream
)
9898 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9899 fprintf (stream
, _("\
9901 -V print assembler version number\n\
9904 fprintf (stream
, _("\
9905 -n Do not optimize code alignment\n\
9906 -q quieten some warnings\n"));
9907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9908 fprintf (stream
, _("\
9911 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9912 || defined (TE_PE) || defined (TE_PEP))
9913 fprintf (stream
, _("\
9914 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9916 #ifdef SVR4_COMMENT_CHARS
9917 fprintf (stream
, _("\
9918 --divide do not treat `/' as a comment character\n"));
9920 fprintf (stream
, _("\
9921 --divide ignored\n"));
9923 fprintf (stream
, _("\
9924 -march=CPU[,+EXTENSION...]\n\
9925 generate code for CPU and EXTENSION, CPU is one of:\n"));
9926 show_arch (stream
, 0, 1);
9927 fprintf (stream
, _("\
9928 EXTENSION is combination of:\n"));
9929 show_arch (stream
, 1, 0);
9930 fprintf (stream
, _("\
9931 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9932 show_arch (stream
, 0, 0);
9933 fprintf (stream
, _("\
9934 -msse2avx encode SSE instructions with VEX prefix\n"));
9935 fprintf (stream
, _("\
9936 -msse-check=[none|error|warning]\n\
9937 check SSE instructions\n"));
9938 fprintf (stream
, _("\
9939 -moperand-check=[none|error|warning]\n\
9940 check operand combinations for validity\n"));
9941 fprintf (stream
, _("\
9942 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9944 fprintf (stream
, _("\
9945 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9947 fprintf (stream
, _("\
9948 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9949 for EVEX.W bit ignored instructions\n"));
9950 fprintf (stream
, _("\
9951 -mevexrcig=[rne|rd|ru|rz]\n\
9952 encode EVEX instructions with specific EVEX.RC value\n\
9953 for SAE-only ignored instructions\n"));
9954 fprintf (stream
, _("\
9955 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9956 fprintf (stream
, _("\
9957 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9958 fprintf (stream
, _("\
9959 -mindex-reg support pseudo index registers\n"));
9960 fprintf (stream
, _("\
9961 -mnaked-reg don't require `%%' prefix for registers\n"));
9962 fprintf (stream
, _("\
9963 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9964 fprintf (stream
, _("\
9965 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9966 # if defined (TE_PE) || defined (TE_PEP)
9967 fprintf (stream
, _("\
9968 -mbig-obj generate big object files\n"));
9970 fprintf (stream
, _("\
9971 -momit-lock-prefix=[no|yes]\n\
9972 strip all lock prefixes\n"));
9975 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9976 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9977 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9979 /* Pick the target format to use. */
9982 i386_target_format (void)
9984 if (!strncmp (default_arch
, "x86_64", 6))
9986 update_code_flag (CODE_64BIT
, 1);
9987 if (default_arch
[6] == '\0')
9988 x86_elf_abi
= X86_64_ABI
;
9990 x86_elf_abi
= X86_64_X32_ABI
;
9992 else if (!strcmp (default_arch
, "i386"))
9993 update_code_flag (CODE_32BIT
, 1);
9995 as_fatal (_("unknown architecture"));
9997 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
9998 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
9999 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10000 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10002 switch (OUTPUT_FLAVOR
)
10004 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10005 case bfd_target_aout_flavour
:
10006 return AOUT_TARGET_FORMAT
;
10008 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10009 # if defined (TE_PE) || defined (TE_PEP)
10010 case bfd_target_coff_flavour
:
10011 if (flag_code
== CODE_64BIT
)
10012 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10015 # elif defined (TE_GO32)
10016 case bfd_target_coff_flavour
:
10017 return "coff-go32";
10019 case bfd_target_coff_flavour
:
10020 return "coff-i386";
10023 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10024 case bfd_target_elf_flavour
:
10026 const char *format
;
10028 switch (x86_elf_abi
)
10031 format
= ELF_TARGET_FORMAT
;
10034 use_rela_relocations
= 1;
10036 format
= ELF_TARGET_FORMAT64
;
10038 case X86_64_X32_ABI
:
10039 use_rela_relocations
= 1;
10041 disallow_64bit_reloc
= 1;
10042 format
= ELF_TARGET_FORMAT32
;
10045 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10047 if (x86_elf_abi
!= X86_64_ABI
)
10048 as_fatal (_("Intel L1OM is 64bit only"));
10049 return ELF_TARGET_L1OM_FORMAT
;
10051 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10053 if (x86_elf_abi
!= X86_64_ABI
)
10054 as_fatal (_("Intel K1OM is 64bit only"));
10055 return ELF_TARGET_K1OM_FORMAT
;
10061 #if defined (OBJ_MACH_O)
10062 case bfd_target_mach_o_flavour
:
10063 if (flag_code
== CODE_64BIT
)
10065 use_rela_relocations
= 1;
10067 return "mach-o-x86-64";
10070 return "mach-o-i386";
10078 #endif /* OBJ_MAYBE_ more than one */
10080 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10082 i386_elf_emit_arch_note (void)
10084 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10087 asection
*seg
= now_seg
;
10088 subsegT subseg
= now_subseg
;
10089 Elf_Internal_Note i_note
;
10090 Elf_External_Note e_note
;
10091 asection
*note_secp
;
10094 /* Create the .note section. */
10095 note_secp
= subseg_new (".note", 0);
10096 bfd_set_section_flags (stdoutput
,
10098 SEC_HAS_CONTENTS
| SEC_READONLY
);
10100 /* Process the arch string. */
10101 len
= strlen (cpu_arch_name
);
10103 i_note
.namesz
= len
+ 1;
10105 i_note
.type
= NT_ARCH
;
10106 p
= frag_more (sizeof (e_note
.namesz
));
10107 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10108 p
= frag_more (sizeof (e_note
.descsz
));
10109 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10110 p
= frag_more (sizeof (e_note
.type
));
10111 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10112 p
= frag_more (len
+ 1);
10113 strcpy (p
, cpu_arch_name
);
10115 frag_align (2, 0, 0);
10117 subseg_set (seg
, subseg
);
10123 md_undefined_symbol (char *name
)
10125 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10126 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10127 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10128 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10132 if (symbol_find (name
))
10133 as_bad (_("GOT already in symbol table"));
10134 GOT_symbol
= symbol_new (name
, undefined_section
,
10135 (valueT
) 0, &zero_address_frag
);
10142 /* Round up a section size to the appropriate boundary. */
10145 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10147 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10148 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10150 /* For a.out, force the section size to be aligned. If we don't do
10151 this, BFD will align it for us, but it will not write out the
10152 final bytes of the section. This may be a bug in BFD, but it is
10153 easier to fix it here since that is how the other a.out targets
10157 align
= bfd_get_section_alignment (stdoutput
, segment
);
10158 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10165 /* On the i386, PC-relative offsets are relative to the start of the
10166 next instruction. That is, the address of the offset, plus its
10167 size, since the offset is always the last part of the insn. */
10170 md_pcrel_from (fixS
*fixP
)
10172 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10178 s_bss (int ignore ATTRIBUTE_UNUSED
)
10182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10184 obj_elf_section_change_hook ();
10186 temp
= get_absolute_expression ();
10187 subseg_set (bss_section
, (subsegT
) temp
);
10188 demand_empty_rest_of_line ();
10194 i386_validate_fix (fixS
*fixp
)
10196 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10198 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10202 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10207 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10209 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10211 fixp
->fx_subsy
= 0;
10216 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10219 bfd_reloc_code_real_type code
;
10221 switch (fixp
->fx_r_type
)
10223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10224 case BFD_RELOC_SIZE32
:
10225 case BFD_RELOC_SIZE64
:
10226 if (S_IS_DEFINED (fixp
->fx_addsy
)
10227 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10229 /* Resolve size relocation against local symbol to size of
10230 the symbol plus addend. */
10231 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10232 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10233 && !fits_in_unsigned_long (value
))
10234 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10235 _("symbol size computation overflow"));
10236 fixp
->fx_addsy
= NULL
;
10237 fixp
->fx_subsy
= NULL
;
10238 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10243 case BFD_RELOC_X86_64_PLT32
:
10244 case BFD_RELOC_X86_64_GOT32
:
10245 case BFD_RELOC_X86_64_GOTPCREL
:
10246 case BFD_RELOC_386_PLT32
:
10247 case BFD_RELOC_386_GOT32
:
10248 case BFD_RELOC_386_GOTOFF
:
10249 case BFD_RELOC_386_GOTPC
:
10250 case BFD_RELOC_386_TLS_GD
:
10251 case BFD_RELOC_386_TLS_LDM
:
10252 case BFD_RELOC_386_TLS_LDO_32
:
10253 case BFD_RELOC_386_TLS_IE_32
:
10254 case BFD_RELOC_386_TLS_IE
:
10255 case BFD_RELOC_386_TLS_GOTIE
:
10256 case BFD_RELOC_386_TLS_LE_32
:
10257 case BFD_RELOC_386_TLS_LE
:
10258 case BFD_RELOC_386_TLS_GOTDESC
:
10259 case BFD_RELOC_386_TLS_DESC_CALL
:
10260 case BFD_RELOC_X86_64_TLSGD
:
10261 case BFD_RELOC_X86_64_TLSLD
:
10262 case BFD_RELOC_X86_64_DTPOFF32
:
10263 case BFD_RELOC_X86_64_DTPOFF64
:
10264 case BFD_RELOC_X86_64_GOTTPOFF
:
10265 case BFD_RELOC_X86_64_TPOFF32
:
10266 case BFD_RELOC_X86_64_TPOFF64
:
10267 case BFD_RELOC_X86_64_GOTOFF64
:
10268 case BFD_RELOC_X86_64_GOTPC32
:
10269 case BFD_RELOC_X86_64_GOT64
:
10270 case BFD_RELOC_X86_64_GOTPCREL64
:
10271 case BFD_RELOC_X86_64_GOTPC64
:
10272 case BFD_RELOC_X86_64_GOTPLT64
:
10273 case BFD_RELOC_X86_64_PLTOFF64
:
10274 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10275 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10276 case BFD_RELOC_RVA
:
10277 case BFD_RELOC_VTABLE_ENTRY
:
10278 case BFD_RELOC_VTABLE_INHERIT
:
10280 case BFD_RELOC_32_SECREL
:
10282 code
= fixp
->fx_r_type
;
10284 case BFD_RELOC_X86_64_32S
:
10285 if (!fixp
->fx_pcrel
)
10287 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10288 code
= fixp
->fx_r_type
;
10292 if (fixp
->fx_pcrel
)
10294 switch (fixp
->fx_size
)
10297 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10298 _("can not do %d byte pc-relative relocation"),
10300 code
= BFD_RELOC_32_PCREL
;
10302 case 1: code
= BFD_RELOC_8_PCREL
; break;
10303 case 2: code
= BFD_RELOC_16_PCREL
; break;
10304 case 4: code
= BFD_RELOC_32_PCREL
; break;
10306 case 8: code
= BFD_RELOC_64_PCREL
; break;
10312 switch (fixp
->fx_size
)
10315 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10316 _("can not do %d byte relocation"),
10318 code
= BFD_RELOC_32
;
10320 case 1: code
= BFD_RELOC_8
; break;
10321 case 2: code
= BFD_RELOC_16
; break;
10322 case 4: code
= BFD_RELOC_32
; break;
10324 case 8: code
= BFD_RELOC_64
; break;
10331 if ((code
== BFD_RELOC_32
10332 || code
== BFD_RELOC_32_PCREL
10333 || code
== BFD_RELOC_X86_64_32S
)
10335 && fixp
->fx_addsy
== GOT_symbol
)
10338 code
= BFD_RELOC_386_GOTPC
;
10340 code
= BFD_RELOC_X86_64_GOTPC32
;
10342 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10344 && fixp
->fx_addsy
== GOT_symbol
)
10346 code
= BFD_RELOC_X86_64_GOTPC64
;
10349 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10350 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10351 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10353 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10355 if (!use_rela_relocations
)
10357 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10358 vtable entry to be used in the relocation's section offset. */
10359 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10360 rel
->address
= fixp
->fx_offset
;
10361 #if defined (OBJ_COFF) && defined (TE_PE)
10362 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10363 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10368 /* Use the rela in 64bit mode. */
10371 if (disallow_64bit_reloc
)
10374 case BFD_RELOC_X86_64_DTPOFF64
:
10375 case BFD_RELOC_X86_64_TPOFF64
:
10376 case BFD_RELOC_64_PCREL
:
10377 case BFD_RELOC_X86_64_GOTOFF64
:
10378 case BFD_RELOC_X86_64_GOT64
:
10379 case BFD_RELOC_X86_64_GOTPCREL64
:
10380 case BFD_RELOC_X86_64_GOTPC64
:
10381 case BFD_RELOC_X86_64_GOTPLT64
:
10382 case BFD_RELOC_X86_64_PLTOFF64
:
10383 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10384 _("cannot represent relocation type %s in x32 mode"),
10385 bfd_get_reloc_code_name (code
));
10391 if (!fixp
->fx_pcrel
)
10392 rel
->addend
= fixp
->fx_offset
;
10396 case BFD_RELOC_X86_64_PLT32
:
10397 case BFD_RELOC_X86_64_GOT32
:
10398 case BFD_RELOC_X86_64_GOTPCREL
:
10399 case BFD_RELOC_X86_64_TLSGD
:
10400 case BFD_RELOC_X86_64_TLSLD
:
10401 case BFD_RELOC_X86_64_GOTTPOFF
:
10402 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10403 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10404 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10407 rel
->addend
= (section
->vma
10409 + fixp
->fx_addnumber
10410 + md_pcrel_from (fixp
));
10415 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10416 if (rel
->howto
== NULL
)
10418 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10419 _("cannot represent relocation type %s"),
10420 bfd_get_reloc_code_name (code
));
10421 /* Set howto to a garbage value so that we can keep going. */
10422 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10423 gas_assert (rel
->howto
!= NULL
);
10429 #include "tc-i386-intel.c"
10432 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10434 int saved_naked_reg
;
10435 char saved_register_dot
;
10437 saved_naked_reg
= allow_naked_reg
;
10438 allow_naked_reg
= 1;
10439 saved_register_dot
= register_chars
['.'];
10440 register_chars
['.'] = '.';
10441 allow_pseudo_reg
= 1;
10442 expression_and_evaluate (exp
);
10443 allow_pseudo_reg
= 0;
10444 register_chars
['.'] = saved_register_dot
;
10445 allow_naked_reg
= saved_naked_reg
;
10447 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10449 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10451 exp
->X_op
= O_constant
;
10452 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10453 .dw2_regnum
[flag_code
>> 1];
10456 exp
->X_op
= O_illegal
;
10461 tc_x86_frame_initial_instructions (void)
10463 static unsigned int sp_regno
[2];
10465 if (!sp_regno
[flag_code
>> 1])
10467 char *saved_input
= input_line_pointer
;
10468 char sp
[][4] = {"esp", "rsp"};
10471 input_line_pointer
= sp
[flag_code
>> 1];
10472 tc_x86_parse_to_dw2regnum (&exp
);
10473 gas_assert (exp
.X_op
== O_constant
);
10474 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10475 input_line_pointer
= saved_input
;
10478 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10479 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10483 x86_dwarf2_addr_size (void)
10485 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10486 if (x86_elf_abi
== X86_64_X32_ABI
)
10489 return bfd_arch_bits_per_address (stdoutput
) / 8;
10493 i386_elf_section_type (const char *str
, size_t len
)
10495 if (flag_code
== CODE_64BIT
10496 && len
== sizeof ("unwind") - 1
10497 && strncmp (str
, "unwind", 6) == 0)
10498 return SHT_X86_64_UNWIND
;
10505 i386_solaris_fix_up_eh_frame (segT sec
)
10507 if (flag_code
== CODE_64BIT
)
10508 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10514 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10518 exp
.X_op
= O_secrel
;
10519 exp
.X_add_symbol
= symbol
;
10520 exp
.X_add_number
= 0;
10521 emit_expr (&exp
, size
);
10525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10526 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10529 x86_64_section_letter (int letter
, char **ptr_msg
)
10531 if (flag_code
== CODE_64BIT
)
10534 return SHF_X86_64_LARGE
;
10536 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10539 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10544 x86_64_section_word (char *str
, size_t len
)
10546 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10547 return SHF_X86_64_LARGE
;
10553 handle_large_common (int small ATTRIBUTE_UNUSED
)
10555 if (flag_code
!= CODE_64BIT
)
10557 s_comm_internal (0, elf_common_parse
);
10558 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10562 static segT lbss_section
;
10563 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10564 asection
*saved_bss_section
= bss_section
;
10566 if (lbss_section
== NULL
)
10568 flagword applicable
;
10569 segT seg
= now_seg
;
10570 subsegT subseg
= now_subseg
;
10572 /* The .lbss section is for local .largecomm symbols. */
10573 lbss_section
= subseg_new (".lbss", 0);
10574 applicable
= bfd_applicable_section_flags (stdoutput
);
10575 bfd_set_section_flags (stdoutput
, lbss_section
,
10576 applicable
& SEC_ALLOC
);
10577 seg_info (lbss_section
)->bss
= 1;
10579 subseg_set (seg
, subseg
);
10582 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10583 bss_section
= lbss_section
;
10585 s_comm_internal (0, elf_common_parse
);
10587 elf_com_section_ptr
= saved_com_section_ptr
;
10588 bss_section
= saved_bss_section
;
10591 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */