1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used
;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used
;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
200 static const char *default_arch
= DEFAULT_ARCH
;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op
;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry
*mask
;
224 unsigned int zeroing
;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op
;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op
;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes
[4];
253 /* Destination or source register specifier. */
254 const reg_entry
*register_specifier
;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry
*regs
;
269 operand_size_mismatch
,
270 operand_type_mismatch
,
271 register_type_mismatch
,
272 number_of_operands_mismatch
,
273 invalid_instruction_suffix
,
275 unsupported_with_intel_mnemonic
,
278 invalid_vsib_address
,
279 invalid_vector_register_set
,
280 unsupported_vector_index_register
,
281 unsupported_broadcast
,
284 mask_not_on_destination
,
287 rc_sae_operand_not_last_imm
,
288 invalid_register_operand
,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands
;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types
[MAX_OPERANDS
];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op
[MAX_OPERANDS
];
316 /* Flags for operands. */
317 unsigned int flags
[MAX_OPERANDS
];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry
*base_reg
;
327 const reg_entry
*index_reg
;
328 unsigned int log2_scale_factor
;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry
*seg
[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes
;
340 unsigned char prefix
[MAX_PREFIXES
];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx
;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm
;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm
;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm
;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation
*mask
;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation
*rounding
;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation
*broadcast
;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift
;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default
= 0,
383 /* Prefer 8bit or 32bit displacement in encoding. */
386 disp_encoding_default
= 0,
391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding
;
394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize
;
397 /* How to encode vector instructions. */
400 vex_encoding_default
= 0,
407 const char *rep_prefix
;
410 const char *hle_prefix
;
412 /* Have BND prefix. */
413 const char *bnd_prefix
;
415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix
;
419 enum i386_error error
;
422 typedef struct _i386_insn i386_insn
;
424 /* Link RC type with corresponding string, that'll be looked for in
433 static const struct RC_name RC_NamesTable
[] =
435 { rne
, STRING_COMMA_LEN ("rn-sae") },
436 { rd
, STRING_COMMA_LEN ("rd-sae") },
437 { ru
, STRING_COMMA_LEN ("ru-sae") },
438 { rz
, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly
, STRING_COMMA_LEN ("sae") },
442 /* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
444 const char extra_symbol_chars
[] = "*%-([{}"
453 #if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
455 && !defined (TE_GNU) \
456 && !defined (TE_LINUX) \
457 && !defined (TE_NACL) \
458 && !defined (TE_FreeBSD) \
459 && !defined (TE_DragonFly) \
460 && !defined (TE_NetBSD)))
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464 const char *i386_comment_chars
= "#/";
465 #define SVR4_COMMENT_CHARS 1
466 #define PREFIX_SEPARATOR '\\'
469 const char *i386_comment_chars
= "#";
470 #define PREFIX_SEPARATOR '/'
473 /* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
477 first line of the input file. This is because the compiler outputs
478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
480 '/' isn't otherwise defined. */
481 const char line_comment_chars
[] = "#/";
483 const char line_separator_chars
[] = ";";
485 /* Chars that can be used to separate mant from exp in floating point
487 const char EXP_CHARS
[] = "eE";
489 /* Chars that mean this number is a floating point constant
492 const char FLT_CHARS
[] = "fFdDxX";
494 /* Tables for lexical analysis. */
495 static char mnemonic_chars
[256];
496 static char register_chars
[256];
497 static char operand_chars
[256];
498 static char identifier_chars
[256];
499 static char digit_chars
[256];
501 /* Lexical macros. */
502 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503 #define is_operand_char(x) (operand_chars[(unsigned char) x])
504 #define is_register_char(x) (register_chars[(unsigned char) x])
505 #define is_space_char(x) ((x) == ' ')
506 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507 #define is_digit_char(x) (digit_chars[(unsigned char) x])
509 /* All non-digit non-letter characters that may occur in an operand. */
510 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
512 /* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
515 assembler instruction). */
516 static char save_stack
[32];
517 static char *save_stack_p
;
518 #define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520 #define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
523 /* The instruction we're assembling. */
526 /* Possible templates for current insn. */
527 static const templates
*current_templates
;
529 /* Per instruction expressionS buffers: max displacements & immediates. */
530 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
531 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
533 /* Current operand we are working on. */
534 static int this_operand
= -1;
536 /* We support four different modes. FLAG_CODE variable is used to distinguish
544 static enum flag_code flag_code
;
545 static unsigned int object_64bit
;
546 static unsigned int disallow_64bit_reloc
;
547 static int use_rela_relocations
= 0;
549 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
553 /* The ELF ABI to use. */
561 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
564 #if defined (TE_PE) || defined (TE_PEP)
565 /* Use big object file format. */
566 static int use_big_obj
= 0;
569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570 /* 1 if generating code for a shared library. */
571 static int shared
= 0;
574 /* 1 for intel syntax,
576 static int intel_syntax
= 0;
578 /* 1 for Intel64 ISA,
582 /* 1 for intel mnemonic,
583 0 if att mnemonic. */
584 static int intel_mnemonic
= !SYSV386_COMPAT
;
586 /* 1 if pseudo registers are permitted. */
587 static int allow_pseudo_reg
= 0;
589 /* 1 if register prefix % not required. */
590 static int allow_naked_reg
= 0;
592 /* 1 if the assembler should add BND prefix for all control-transferring
593 instructions supporting it, even if this prefix wasn't specified
595 static int add_bnd_prefix
= 0;
597 /* 1 if pseudo index register, eiz/riz, is allowed . */
598 static int allow_index_reg
= 0;
600 /* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602 static int omit_lock_prefix
= 0;
604 /* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606 static int avoid_fence
= 0;
608 /* 1 if the assembler should generate relax relocations. */
610 static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
613 static enum check_kind
619 sse_check
, operand_check
= check_warning
;
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
626 static int optimize
= 0;
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
635 static int optimize_for_space
= 0;
637 /* Register prefix used for error message. */
638 static const char *register_prefix
= "%";
640 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643 static char stackop_size
= '\0';
645 /* Non-zero to optimize code alignment. */
646 int optimize_align_code
= 1;
648 /* Non-zero to quieten some warnings. */
649 static int quiet_warnings
= 0;
652 static const char *cpu_arch_name
= NULL
;
653 static char *cpu_sub_arch_name
= NULL
;
655 /* CPU feature flags. */
656 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
658 /* If we have selected a cpu we are generating instructions for. */
659 static int cpu_arch_tune_set
= 0;
661 /* Cpu we are generating instructions for. */
662 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
664 /* CPU feature flags of cpu we are generating instructions for. */
665 static i386_cpu_flags cpu_arch_tune_flags
;
667 /* CPU instruction set architecture used. */
668 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
670 /* CPU feature flags of instruction set architecture used. */
671 i386_cpu_flags cpu_arch_isa_flags
;
673 /* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675 static unsigned int no_cond_jump_promotion
= 0;
677 /* Encode SSE instructions with VEX prefix. */
678 static unsigned int sse2avx
;
680 /* Encode scalar AVX instructions with specific vector length. */
687 /* Encode VEX WIG instructions with specific vex.w. */
694 /* Encode scalar EVEX LIG instructions with specific vector length. */
702 /* Encode EVEX WIG instructions with specific evex.w. */
709 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
710 static enum rc_type evexrcig
= rne
;
712 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
713 static symbolS
*GOT_symbol
;
715 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
716 unsigned int x86_dwarf2_return_column
;
718 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
719 int x86_cie_data_alignment
;
721 /* Interface to relax_segment.
722 There are 3 major relax states for 386 jump insns because the
723 different types of jumps add different sizes to frags when we're
724 figuring out what sort of jump to choose to reach a given label. */
727 #define UNCOND_JUMP 0
729 #define COND_JUMP86 2
734 #define SMALL16 (SMALL | CODE16)
736 #define BIG16 (BIG | CODE16)
740 #define INLINE __inline__
746 #define ENCODE_RELAX_STATE(type, size) \
747 ((relax_substateT) (((type) << 2) | (size)))
748 #define TYPE_FROM_RELAX_STATE(s) \
750 #define DISP_SIZE_FROM_RELAX_STATE(s) \
751 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
753 /* This table is used by relax_frag to promote short jumps to long
754 ones where necessary. SMALL (short) jumps may be promoted to BIG
755 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
756 don't allow a short jump in a 32 bit code segment to be promoted to
757 a 16 bit offset jump because it's slower (requires data size
758 prefix), and doesn't work, unless the destination is in the bottom
759 64k of the code segment (The top 16 bits of eip are zeroed). */
761 const relax_typeS md_relax_table
[] =
764 1) most positive reach of this state,
765 2) most negative reach of this state,
766 3) how many bytes this mode will have in the variable part of the frag
767 4) which index into the table to try if we can't fit into this one. */
769 /* UNCOND_JUMP states. */
770 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
771 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
772 /* dword jmp adds 4 bytes to frag:
773 0 extra opcode bytes, 4 displacement bytes. */
775 /* word jmp adds 2 byte2 to frag:
776 0 extra opcode bytes, 2 displacement bytes. */
779 /* COND_JUMP states. */
780 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
782 /* dword conditionals adds 5 bytes to frag:
783 1 extra opcode byte, 4 displacement bytes. */
785 /* word conditionals add 3 bytes to frag:
786 1 extra opcode byte, 2 displacement bytes. */
789 /* COND_JUMP86 states. */
790 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
792 /* dword conditionals adds 5 bytes to frag:
793 1 extra opcode byte, 4 displacement bytes. */
795 /* word conditionals add 4 bytes to frag:
796 1 displacement byte and a 3 byte long branch insn. */
800 static const arch_entry cpu_arch
[] =
802 /* Do not replace the first two entries - i386_target_format()
803 relies on them being there in this order. */
804 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
805 CPU_GENERIC32_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
807 CPU_GENERIC64_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
810 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
812 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
814 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
816 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
818 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
820 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
822 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
824 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
825 CPU_PENTIUMPRO_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
828 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
830 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
832 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
834 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
835 CPU_NOCONA_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
838 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
840 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
841 CPU_CORE2_FLAGS
, 1 },
842 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
843 CPU_CORE2_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
845 CPU_COREI7_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
848 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
850 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
851 CPU_IAMCU_FLAGS
, 0 },
852 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
854 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
856 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
857 CPU_ATHLON_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
860 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
862 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
864 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
865 CPU_AMDFAM10_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
867 CPU_BDVER1_FLAGS
, 0 },
868 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
869 CPU_BDVER2_FLAGS
, 0 },
870 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
871 CPU_BDVER3_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
873 CPU_BDVER4_FLAGS
, 0 },
874 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
875 CPU_ZNVER1_FLAGS
, 0 },
876 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
877 CPU_ZNVER2_FLAGS
, 0 },
878 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
879 CPU_BTVER1_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
881 CPU_BTVER2_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
903 CPU_SSSE3_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
905 CPU_SSE4_1_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
907 CPU_SSE4_2_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
909 CPU_SSE4_2_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
915 CPU_AVX512F_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
917 CPU_AVX512CD_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
919 CPU_AVX512ER_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
921 CPU_AVX512PF_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
923 CPU_AVX512DQ_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
925 CPU_AVX512BW_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
927 CPU_AVX512VL_FLAGS
, 0 },
928 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
931 CPU_VMFUNC_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
935 CPU_XSAVE_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
937 CPU_XSAVEOPT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
939 CPU_XSAVEC_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
941 CPU_XSAVES_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
945 CPU_PCLMUL_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
947 CPU_PCLMUL_FLAGS
, 1 },
948 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
949 CPU_FSGSBASE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
951 CPU_RDRND_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
965 CPU_MOVBE_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
971 CPU_LZCNT_FLAGS
, 0 },
972 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
977 CPU_INVPCID_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
979 CPU_CLFLUSH_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
983 CPU_SYSCALL_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
985 CPU_RDTSCP_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
987 CPU_3DNOW_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
989 CPU_3DNOWA_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
991 CPU_PADLOCK_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
994 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
997 CPU_SSE4A_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1000 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1002 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1004 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1006 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1007 CPU_RDSEED_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1009 CPU_PRFCHW_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1011 CPU_SMAP_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1017 CPU_CLFLUSHOPT_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1019 CPU_PREFETCHWT1_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1023 CPU_CLWB_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1025 CPU_AVX512IFMA_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1027 CPU_AVX512VBMI_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1029 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1031 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1033 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1035 CPU_AVX512_VBMI2_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1037 CPU_AVX512_VNNI_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512_BITALG_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1041 CPU_CLZERO_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1043 CPU_MWAITX_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1045 CPU_OSPKE_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1047 CPU_RDPID_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1049 CPU_PTWRITE_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1052 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1053 CPU_SHSTK_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1055 CPU_GFNI_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1057 CPU_VAES_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1059 CPU_VPCLMULQDQ_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1061 CPU_WBNOINVD_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1063 CPU_PCONFIG_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1065 CPU_WAITPKG_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1067 CPU_CLDEMOTE_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1069 CPU_MOVDIRI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1071 CPU_MOVDIR64B_FLAGS
, 0 },
1074 static const noarch_entry cpu_noarch
[] =
1076 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1077 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1078 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1079 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1080 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1081 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1082 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1083 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1084 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1085 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1086 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1087 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1088 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1089 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1090 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1091 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1092 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1093 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1094 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1095 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1096 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1097 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1098 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1099 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1100 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1101 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1102 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1103 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1104 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1105 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1106 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1107 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1108 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1109 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1110 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1114 /* Like s_lcomm_internal in gas/read.c but the alignment string
1115 is allowed to be optional. */
1118 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1125 && *input_line_pointer
== ',')
1127 align
= parse_align (needs_align
- 1);
1129 if (align
== (addressT
) -1)
1144 bss_alloc (symbolP
, size
, align
);
1149 pe_lcomm (int needs_align
)
1151 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1155 const pseudo_typeS md_pseudo_table
[] =
1157 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1158 {"align", s_align_bytes
, 0},
1160 {"align", s_align_ptwo
, 0},
1162 {"arch", set_cpu_arch
, 0},
1166 {"lcomm", pe_lcomm
, 1},
1168 {"ffloat", float_cons
, 'f'},
1169 {"dfloat", float_cons
, 'd'},
1170 {"tfloat", float_cons
, 'x'},
1172 {"slong", signed_cons
, 4},
1173 {"noopt", s_ignore
, 0},
1174 {"optim", s_ignore
, 0},
1175 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1176 {"code16", set_code_flag
, CODE_16BIT
},
1177 {"code32", set_code_flag
, CODE_32BIT
},
1179 {"code64", set_code_flag
, CODE_64BIT
},
1181 {"intel_syntax", set_intel_syntax
, 1},
1182 {"att_syntax", set_intel_syntax
, 0},
1183 {"intel_mnemonic", set_intel_mnemonic
, 1},
1184 {"att_mnemonic", set_intel_mnemonic
, 0},
1185 {"allow_index_reg", set_allow_index_reg
, 1},
1186 {"disallow_index_reg", set_allow_index_reg
, 0},
1187 {"sse_check", set_check
, 0},
1188 {"operand_check", set_check
, 1},
1189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1190 {"largecomm", handle_large_common
, 0},
1192 {"file", dwarf2_directive_file
, 0},
1193 {"loc", dwarf2_directive_loc
, 0},
1194 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1197 {"secrel32", pe_directive_secrel
, 0},
1202 /* For interface with expression (). */
1203 extern char *input_line_pointer
;
1205 /* Hash table for instruction mnemonic lookup. */
1206 static struct hash_control
*op_hash
;
1208 /* Hash table for register lookup. */
1209 static struct hash_control
*reg_hash
;
1211 /* Various efficient no-op patterns for aligning code labels.
1212 Note: Don't try to assemble the instructions in the comments.
1213 0L and 0w are not legal. */
1214 static const unsigned char f32_1
[] =
1216 static const unsigned char f32_2
[] =
1217 {0x66,0x90}; /* xchg %ax,%ax */
1218 static const unsigned char f32_3
[] =
1219 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1220 static const unsigned char f32_4
[] =
1221 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1222 static const unsigned char f32_6
[] =
1223 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1224 static const unsigned char f32_7
[] =
1225 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1226 static const unsigned char f16_3
[] =
1227 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1228 static const unsigned char f16_4
[] =
1229 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1230 static const unsigned char jump_disp8
[] =
1231 {0xeb}; /* jmp disp8 */
1232 static const unsigned char jump32_disp32
[] =
1233 {0xe9}; /* jmp disp32 */
1234 static const unsigned char jump16_disp32
[] =
1235 {0x66,0xe9}; /* jmp disp32 */
1236 /* 32-bit NOPs patterns. */
1237 static const unsigned char *const f32_patt
[] = {
1238 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1240 /* 16-bit NOPs patterns. */
1241 static const unsigned char *const f16_patt
[] = {
1242 f32_1
, f32_2
, f16_3
, f16_4
1244 /* nopl (%[re]ax) */
1245 static const unsigned char alt_3
[] =
1247 /* nopl 0(%[re]ax) */
1248 static const unsigned char alt_4
[] =
1249 {0x0f,0x1f,0x40,0x00};
1250 /* nopl 0(%[re]ax,%[re]ax,1) */
1251 static const unsigned char alt_5
[] =
1252 {0x0f,0x1f,0x44,0x00,0x00};
1253 /* nopw 0(%[re]ax,%[re]ax,1) */
1254 static const unsigned char alt_6
[] =
1255 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1256 /* nopl 0L(%[re]ax) */
1257 static const unsigned char alt_7
[] =
1258 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1259 /* nopl 0L(%[re]ax,%[re]ax,1) */
1260 static const unsigned char alt_8
[] =
1261 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1262 /* nopw 0L(%[re]ax,%[re]ax,1) */
1263 static const unsigned char alt_9
[] =
1264 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1265 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1266 static const unsigned char alt_10
[] =
1267 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1268 /* data16 nopw %cs:0L(%eax,%eax,1) */
1269 static const unsigned char alt_11
[] =
1270 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1271 /* 32-bit and 64-bit NOPs patterns. */
1272 static const unsigned char *const alt_patt
[] = {
1273 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1274 alt_9
, alt_10
, alt_11
1277 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1278 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1281 i386_output_nops (char *where
, const unsigned char *const *patt
,
1282 int count
, int max_single_nop_size
)
1285 /* Place the longer NOP first. */
1288 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1290 /* Use the smaller one if the requsted one isn't available. */
1293 max_single_nop_size
--;
1294 nops
= patt
[max_single_nop_size
- 1];
1297 last
= count
% max_single_nop_size
;
1300 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1301 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1305 nops
= patt
[last
- 1];
1308 /* Use the smaller one plus one-byte NOP if the needed one
1311 nops
= patt
[last
- 1];
1312 memcpy (where
+ offset
, nops
, last
);
1313 where
[offset
+ last
] = *patt
[0];
1316 memcpy (where
+ offset
, nops
, last
);
1321 fits_in_imm7 (offsetT num
)
1323 return (num
& 0x7f) == num
;
1327 fits_in_imm31 (offsetT num
)
1329 return (num
& 0x7fffffff) == num
;
1332 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1333 single NOP instruction LIMIT. */
1336 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1338 const unsigned char *const *patt
= NULL
;
1339 int max_single_nop_size
;
1340 /* Maximum number of NOPs before switching to jump over NOPs. */
1341 int max_number_of_nops
;
1343 switch (fragP
->fr_type
)
1352 /* We need to decide which NOP sequence to use for 32bit and
1353 64bit. When -mtune= is used:
1355 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1356 PROCESSOR_GENERIC32, f32_patt will be used.
1357 2. For the rest, alt_patt will be used.
1359 When -mtune= isn't used, alt_patt will be used if
1360 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1363 When -march= or .arch is used, we can't use anything beyond
1364 cpu_arch_isa_flags. */
1366 if (flag_code
== CODE_16BIT
)
1369 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1370 /* Limit number of NOPs to 2 in 16-bit mode. */
1371 max_number_of_nops
= 2;
1375 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1377 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1378 switch (cpu_arch_tune
)
1380 case PROCESSOR_UNKNOWN
:
1381 /* We use cpu_arch_isa_flags to check if we SHOULD
1382 optimize with nops. */
1383 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1388 case PROCESSOR_PENTIUM4
:
1389 case PROCESSOR_NOCONA
:
1390 case PROCESSOR_CORE
:
1391 case PROCESSOR_CORE2
:
1392 case PROCESSOR_COREI7
:
1393 case PROCESSOR_L1OM
:
1394 case PROCESSOR_K1OM
:
1395 case PROCESSOR_GENERIC64
:
1397 case PROCESSOR_ATHLON
:
1399 case PROCESSOR_AMDFAM10
:
1401 case PROCESSOR_ZNVER
:
1405 case PROCESSOR_I386
:
1406 case PROCESSOR_I486
:
1407 case PROCESSOR_PENTIUM
:
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_IAMCU
:
1410 case PROCESSOR_GENERIC32
:
1417 switch (fragP
->tc_frag_data
.tune
)
1419 case PROCESSOR_UNKNOWN
:
1420 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1421 PROCESSOR_UNKNOWN. */
1425 case PROCESSOR_I386
:
1426 case PROCESSOR_I486
:
1427 case PROCESSOR_PENTIUM
:
1428 case PROCESSOR_IAMCU
:
1430 case PROCESSOR_ATHLON
:
1432 case PROCESSOR_AMDFAM10
:
1434 case PROCESSOR_ZNVER
:
1436 case PROCESSOR_GENERIC32
:
1437 /* We use cpu_arch_isa_flags to check if we CAN optimize
1439 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1444 case PROCESSOR_PENTIUMPRO
:
1445 case PROCESSOR_PENTIUM4
:
1446 case PROCESSOR_NOCONA
:
1447 case PROCESSOR_CORE
:
1448 case PROCESSOR_CORE2
:
1449 case PROCESSOR_COREI7
:
1450 case PROCESSOR_L1OM
:
1451 case PROCESSOR_K1OM
:
1452 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1457 case PROCESSOR_GENERIC64
:
1463 if (patt
== f32_patt
)
1465 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1466 /* Limit number of NOPs to 2 for older processors. */
1467 max_number_of_nops
= 2;
1471 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1472 /* Limit number of NOPs to 7 for newer processors. */
1473 max_number_of_nops
= 7;
1478 limit
= max_single_nop_size
;
1480 if (fragP
->fr_type
== rs_fill_nop
)
1482 /* Output NOPs for .nop directive. */
1483 if (limit
> max_single_nop_size
)
1485 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1486 _("invalid single nop size: %d "
1487 "(expect within [0, %d])"),
1488 limit
, max_single_nop_size
);
1493 fragP
->fr_var
= count
;
1495 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1497 /* Generate jump over NOPs. */
1498 offsetT disp
= count
- 2;
1499 if (fits_in_imm7 (disp
))
1501 /* Use "jmp disp8" if possible. */
1503 where
[0] = jump_disp8
[0];
1509 unsigned int size_of_jump
;
1511 if (flag_code
== CODE_16BIT
)
1513 where
[0] = jump16_disp32
[0];
1514 where
[1] = jump16_disp32
[1];
1519 where
[0] = jump32_disp32
[0];
1523 count
-= size_of_jump
+ 4;
1524 if (!fits_in_imm31 (count
))
1526 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1527 _("jump over nop padding out of range"));
1531 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1532 where
+= size_of_jump
+ 4;
1536 /* Generate multiple NOPs. */
1537 i386_output_nops (where
, patt
, count
, limit
);
1541 operand_type_all_zero (const union i386_operand_type
*x
)
1543 switch (ARRAY_SIZE(x
->array
))
1554 return !x
->array
[0];
1561 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1563 switch (ARRAY_SIZE(x
->array
))
1581 operand_type_equal (const union i386_operand_type
*x
,
1582 const union i386_operand_type
*y
)
1584 switch (ARRAY_SIZE(x
->array
))
1587 if (x
->array
[2] != y
->array
[2])
1591 if (x
->array
[1] != y
->array
[1])
1595 return x
->array
[0] == y
->array
[0];
1603 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1605 switch (ARRAY_SIZE(x
->array
))
1620 return !x
->array
[0];
1627 cpu_flags_equal (const union i386_cpu_flags
*x
,
1628 const union i386_cpu_flags
*y
)
1630 switch (ARRAY_SIZE(x
->array
))
1633 if (x
->array
[3] != y
->array
[3])
1637 if (x
->array
[2] != y
->array
[2])
1641 if (x
->array
[1] != y
->array
[1])
1645 return x
->array
[0] == y
->array
[0];
1653 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1655 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1656 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1659 static INLINE i386_cpu_flags
1660 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1662 switch (ARRAY_SIZE (x
.array
))
1665 x
.array
[3] &= y
.array
[3];
1668 x
.array
[2] &= y
.array
[2];
1671 x
.array
[1] &= y
.array
[1];
1674 x
.array
[0] &= y
.array
[0];
1682 static INLINE i386_cpu_flags
1683 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1685 switch (ARRAY_SIZE (x
.array
))
1688 x
.array
[3] |= y
.array
[3];
1691 x
.array
[2] |= y
.array
[2];
1694 x
.array
[1] |= y
.array
[1];
1697 x
.array
[0] |= y
.array
[0];
1705 static INLINE i386_cpu_flags
1706 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1708 switch (ARRAY_SIZE (x
.array
))
1711 x
.array
[3] &= ~y
.array
[3];
1714 x
.array
[2] &= ~y
.array
[2];
1717 x
.array
[1] &= ~y
.array
[1];
1720 x
.array
[0] &= ~y
.array
[0];
1728 #define CPU_FLAGS_ARCH_MATCH 0x1
1729 #define CPU_FLAGS_64BIT_MATCH 0x2
1731 #define CPU_FLAGS_PERFECT_MATCH \
1732 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1734 /* Return CPU flags match bits. */
1737 cpu_flags_match (const insn_template
*t
)
1739 i386_cpu_flags x
= t
->cpu_flags
;
1740 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1742 x
.bitfield
.cpu64
= 0;
1743 x
.bitfield
.cpuno64
= 0;
1745 if (cpu_flags_all_zero (&x
))
1747 /* This instruction is available on all archs. */
1748 match
|= CPU_FLAGS_ARCH_MATCH
;
1752 /* This instruction is available only on some archs. */
1753 i386_cpu_flags cpu
= cpu_arch_flags
;
1755 /* AVX512VL is no standalone feature - match it and then strip it. */
1756 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1758 x
.bitfield
.cpuavx512vl
= 0;
1760 cpu
= cpu_flags_and (x
, cpu
);
1761 if (!cpu_flags_all_zero (&cpu
))
1763 if (x
.bitfield
.cpuavx
)
1765 /* We need to check a few extra flags with AVX. */
1766 if (cpu
.bitfield
.cpuavx
1767 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1768 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1769 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1770 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1771 match
|= CPU_FLAGS_ARCH_MATCH
;
1773 else if (x
.bitfield
.cpuavx512f
)
1775 /* We need to check a few extra flags with AVX512F. */
1776 if (cpu
.bitfield
.cpuavx512f
1777 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1778 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1779 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1780 match
|= CPU_FLAGS_ARCH_MATCH
;
1783 match
|= CPU_FLAGS_ARCH_MATCH
;
1789 static INLINE i386_operand_type
1790 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1792 switch (ARRAY_SIZE (x
.array
))
1795 x
.array
[2] &= y
.array
[2];
1798 x
.array
[1] &= y
.array
[1];
1801 x
.array
[0] &= y
.array
[0];
1809 static INLINE i386_operand_type
1810 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1812 switch (ARRAY_SIZE (x
.array
))
1815 x
.array
[2] &= ~y
.array
[2];
1818 x
.array
[1] &= ~y
.array
[1];
1821 x
.array
[0] &= ~y
.array
[0];
1829 static INLINE i386_operand_type
1830 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1832 switch (ARRAY_SIZE (x
.array
))
1835 x
.array
[2] |= y
.array
[2];
1838 x
.array
[1] |= y
.array
[1];
1841 x
.array
[0] |= y
.array
[0];
1849 static INLINE i386_operand_type
1850 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1852 switch (ARRAY_SIZE (x
.array
))
1855 x
.array
[2] ^= y
.array
[2];
1858 x
.array
[1] ^= y
.array
[1];
1861 x
.array
[0] ^= y
.array
[0];
1869 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1870 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1871 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1872 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1873 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1874 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1875 static const i386_operand_type anydisp
1876 = OPERAND_TYPE_ANYDISP
;
1877 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1878 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1879 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1880 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1881 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1882 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1883 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1884 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1885 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1886 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1887 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1888 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1899 operand_type_check (i386_operand_type t
, enum operand_type c
)
1904 return t
.bitfield
.reg
;
1907 return (t
.bitfield
.imm8
1911 || t
.bitfield
.imm32s
1912 || t
.bitfield
.imm64
);
1915 return (t
.bitfield
.disp8
1916 || t
.bitfield
.disp16
1917 || t
.bitfield
.disp32
1918 || t
.bitfield
.disp32s
1919 || t
.bitfield
.disp64
);
1922 return (t
.bitfield
.disp8
1923 || t
.bitfield
.disp16
1924 || t
.bitfield
.disp32
1925 || t
.bitfield
.disp32s
1926 || t
.bitfield
.disp64
1927 || t
.bitfield
.baseindex
);
1936 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1937 between operand GIVEN and opeand WANTED for instruction template T. */
1940 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1943 return !((i
.types
[given
].bitfield
.byte
1944 && !t
->operand_types
[wanted
].bitfield
.byte
)
1945 || (i
.types
[given
].bitfield
.word
1946 && !t
->operand_types
[wanted
].bitfield
.word
)
1947 || (i
.types
[given
].bitfield
.dword
1948 && !t
->operand_types
[wanted
].bitfield
.dword
)
1949 || (i
.types
[given
].bitfield
.qword
1950 && !t
->operand_types
[wanted
].bitfield
.qword
)
1951 || (i
.types
[given
].bitfield
.tbyte
1952 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1955 /* Return 1 if there is no conflict in SIMD register between operand
1956 GIVEN and opeand WANTED for instruction template T. */
1959 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1962 return !((i
.types
[given
].bitfield
.xmmword
1963 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1964 || (i
.types
[given
].bitfield
.ymmword
1965 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1966 || (i
.types
[given
].bitfield
.zmmword
1967 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1970 /* Return 1 if there is no conflict in any size between operand GIVEN
1971 and opeand WANTED for instruction template T. */
1974 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1977 return (match_operand_size (t
, wanted
, given
)
1978 && !((i
.types
[given
].bitfield
.unspecified
1980 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1981 || (i
.types
[given
].bitfield
.fword
1982 && !t
->operand_types
[wanted
].bitfield
.fword
)
1983 /* For scalar opcode templates to allow register and memory
1984 operands at the same time, some special casing is needed
1985 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1986 down-conversion vpmov*. */
1987 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1988 && !t
->opcode_modifier
.broadcast
1989 && (t
->operand_types
[wanted
].bitfield
.byte
1990 || t
->operand_types
[wanted
].bitfield
.word
1991 || t
->operand_types
[wanted
].bitfield
.dword
1992 || t
->operand_types
[wanted
].bitfield
.qword
))
1993 ? (i
.types
[given
].bitfield
.xmmword
1994 || i
.types
[given
].bitfield
.ymmword
1995 || i
.types
[given
].bitfield
.zmmword
)
1996 : !match_simd_size(t
, wanted
, given
))));
1999 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2000 operands for instruction template T, and it has MATCH_REVERSE set if there
2001 is no size conflict on any operands for the template with operands reversed
2002 (and the template allows for reversing in the first place). */
2004 #define MATCH_STRAIGHT 1
2005 #define MATCH_REVERSE 2
2007 static INLINE
unsigned int
2008 operand_size_match (const insn_template
*t
)
2010 unsigned int j
, match
= MATCH_STRAIGHT
;
2012 /* Don't check jump instructions. */
2013 if (t
->opcode_modifier
.jump
2014 || t
->opcode_modifier
.jumpbyte
2015 || t
->opcode_modifier
.jumpdword
2016 || t
->opcode_modifier
.jumpintersegment
)
2019 /* Check memory and accumulator operand size. */
2020 for (j
= 0; j
< i
.operands
; j
++)
2022 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2023 && t
->operand_types
[j
].bitfield
.anysize
)
2026 if (t
->operand_types
[j
].bitfield
.reg
2027 && !match_operand_size (t
, j
, j
))
2033 if (t
->operand_types
[j
].bitfield
.regsimd
2034 && !match_simd_size (t
, j
, j
))
2040 if (t
->operand_types
[j
].bitfield
.acc
2041 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2047 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2054 if (!t
->opcode_modifier
.d
)
2058 i
.error
= operand_size_mismatch
;
2062 /* Check reverse. */
2063 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2065 for (j
= 0; j
< i
.operands
; j
++)
2067 unsigned int given
= i
.operands
- j
- 1;
2069 if (t
->operand_types
[j
].bitfield
.reg
2070 && !match_operand_size (t
, j
, given
))
2073 if (t
->operand_types
[j
].bitfield
.regsimd
2074 && !match_simd_size (t
, j
, given
))
2077 if (t
->operand_types
[j
].bitfield
.acc
2078 && (!match_operand_size (t
, j
, given
)
2079 || !match_simd_size (t
, j
, given
)))
2082 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2086 return match
| MATCH_REVERSE
;
2090 operand_type_match (i386_operand_type overlap
,
2091 i386_operand_type given
)
2093 i386_operand_type temp
= overlap
;
2095 temp
.bitfield
.jumpabsolute
= 0;
2096 temp
.bitfield
.unspecified
= 0;
2097 temp
.bitfield
.byte
= 0;
2098 temp
.bitfield
.word
= 0;
2099 temp
.bitfield
.dword
= 0;
2100 temp
.bitfield
.fword
= 0;
2101 temp
.bitfield
.qword
= 0;
2102 temp
.bitfield
.tbyte
= 0;
2103 temp
.bitfield
.xmmword
= 0;
2104 temp
.bitfield
.ymmword
= 0;
2105 temp
.bitfield
.zmmword
= 0;
2106 if (operand_type_all_zero (&temp
))
2109 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2110 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2114 i
.error
= operand_type_mismatch
;
2118 /* If given types g0 and g1 are registers they must be of the same type
2119 unless the expected operand type register overlap is null.
2120 Memory operand size of certain SIMD instructions is also being checked
2124 operand_type_register_match (i386_operand_type g0
,
2125 i386_operand_type t0
,
2126 i386_operand_type g1
,
2127 i386_operand_type t1
)
2129 if (!g0
.bitfield
.reg
2130 && !g0
.bitfield
.regsimd
2131 && (!operand_type_check (g0
, anymem
)
2132 || g0
.bitfield
.unspecified
2133 || !t0
.bitfield
.regsimd
))
2136 if (!g1
.bitfield
.reg
2137 && !g1
.bitfield
.regsimd
2138 && (!operand_type_check (g1
, anymem
)
2139 || g1
.bitfield
.unspecified
2140 || !t1
.bitfield
.regsimd
))
2143 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2144 && g0
.bitfield
.word
== g1
.bitfield
.word
2145 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2146 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2147 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2148 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2149 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2152 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2153 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2154 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2155 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2156 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2157 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2158 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2161 i
.error
= register_type_mismatch
;
2166 static INLINE
unsigned int
2167 register_number (const reg_entry
*r
)
2169 unsigned int nr
= r
->reg_num
;
2171 if (r
->reg_flags
& RegRex
)
2174 if (r
->reg_flags
& RegVRex
)
2180 static INLINE
unsigned int
2181 mode_from_disp_size (i386_operand_type t
)
2183 if (t
.bitfield
.disp8
)
2185 else if (t
.bitfield
.disp16
2186 || t
.bitfield
.disp32
2187 || t
.bitfield
.disp32s
)
2194 fits_in_signed_byte (addressT num
)
2196 return num
+ 0x80 <= 0xff;
2200 fits_in_unsigned_byte (addressT num
)
2206 fits_in_unsigned_word (addressT num
)
2208 return num
<= 0xffff;
2212 fits_in_signed_word (addressT num
)
2214 return num
+ 0x8000 <= 0xffff;
2218 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2223 return num
+ 0x80000000 <= 0xffffffff;
2225 } /* fits_in_signed_long() */
2228 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2233 return num
<= 0xffffffff;
2235 } /* fits_in_unsigned_long() */
2238 fits_in_disp8 (offsetT num
)
2240 int shift
= i
.memshift
;
2246 mask
= (1 << shift
) - 1;
2248 /* Return 0 if NUM isn't properly aligned. */
2252 /* Check if NUM will fit in 8bit after shift. */
2253 return fits_in_signed_byte (num
>> shift
);
2257 fits_in_imm4 (offsetT num
)
2259 return (num
& 0xf) == num
;
2262 static i386_operand_type
2263 smallest_imm_type (offsetT num
)
2265 i386_operand_type t
;
2267 operand_type_set (&t
, 0);
2268 t
.bitfield
.imm64
= 1;
2270 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2272 /* This code is disabled on the 486 because all the Imm1 forms
2273 in the opcode table are slower on the i486. They're the
2274 versions with the implicitly specified single-position
2275 displacement, which has another syntax if you really want to
2277 t
.bitfield
.imm1
= 1;
2278 t
.bitfield
.imm8
= 1;
2279 t
.bitfield
.imm8s
= 1;
2280 t
.bitfield
.imm16
= 1;
2281 t
.bitfield
.imm32
= 1;
2282 t
.bitfield
.imm32s
= 1;
2284 else if (fits_in_signed_byte (num
))
2286 t
.bitfield
.imm8
= 1;
2287 t
.bitfield
.imm8s
= 1;
2288 t
.bitfield
.imm16
= 1;
2289 t
.bitfield
.imm32
= 1;
2290 t
.bitfield
.imm32s
= 1;
2292 else if (fits_in_unsigned_byte (num
))
2294 t
.bitfield
.imm8
= 1;
2295 t
.bitfield
.imm16
= 1;
2296 t
.bitfield
.imm32
= 1;
2297 t
.bitfield
.imm32s
= 1;
2299 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2301 t
.bitfield
.imm16
= 1;
2302 t
.bitfield
.imm32
= 1;
2303 t
.bitfield
.imm32s
= 1;
2305 else if (fits_in_signed_long (num
))
2307 t
.bitfield
.imm32
= 1;
2308 t
.bitfield
.imm32s
= 1;
2310 else if (fits_in_unsigned_long (num
))
2311 t
.bitfield
.imm32
= 1;
2317 offset_in_range (offsetT val
, int size
)
2323 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2324 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2325 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2327 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2333 /* If BFD64, sign extend val for 32bit address mode. */
2334 if (flag_code
!= CODE_64BIT
2335 || i
.prefix
[ADDR_PREFIX
])
2336 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2337 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2340 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2342 char buf1
[40], buf2
[40];
2344 sprint_value (buf1
, val
);
2345 sprint_value (buf2
, val
& mask
);
2346 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2361 a. PREFIX_EXIST if attempting to add a prefix where one from the
2362 same class already exists.
2363 b. PREFIX_LOCK if lock prefix is added.
2364 c. PREFIX_REP if rep/repne prefix is added.
2365 d. PREFIX_DS if ds prefix is added.
2366 e. PREFIX_OTHER if other prefix is added.
2369 static enum PREFIX_GROUP
2370 add_prefix (unsigned int prefix
)
2372 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2375 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2376 && flag_code
== CODE_64BIT
)
2378 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2379 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2380 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2381 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2392 case DS_PREFIX_OPCODE
:
2395 case CS_PREFIX_OPCODE
:
2396 case ES_PREFIX_OPCODE
:
2397 case FS_PREFIX_OPCODE
:
2398 case GS_PREFIX_OPCODE
:
2399 case SS_PREFIX_OPCODE
:
2403 case REPNE_PREFIX_OPCODE
:
2404 case REPE_PREFIX_OPCODE
:
2409 case LOCK_PREFIX_OPCODE
:
2418 case ADDR_PREFIX_OPCODE
:
2422 case DATA_PREFIX_OPCODE
:
2426 if (i
.prefix
[q
] != 0)
2434 i
.prefix
[q
] |= prefix
;
2437 as_bad (_("same type of prefix used twice"));
2443 update_code_flag (int value
, int check
)
2445 PRINTF_LIKE ((*as_error
));
2447 flag_code
= (enum flag_code
) value
;
2448 if (flag_code
== CODE_64BIT
)
2450 cpu_arch_flags
.bitfield
.cpu64
= 1;
2451 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2455 cpu_arch_flags
.bitfield
.cpu64
= 0;
2456 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2458 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2461 as_error
= as_fatal
;
2464 (*as_error
) (_("64bit mode not supported on `%s'."),
2465 cpu_arch_name
? cpu_arch_name
: default_arch
);
2467 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2470 as_error
= as_fatal
;
2473 (*as_error
) (_("32bit mode not supported on `%s'."),
2474 cpu_arch_name
? cpu_arch_name
: default_arch
);
2476 stackop_size
= '\0';
2480 set_code_flag (int value
)
2482 update_code_flag (value
, 0);
2486 set_16bit_gcc_code_flag (int new_code_flag
)
2488 flag_code
= (enum flag_code
) new_code_flag
;
2489 if (flag_code
!= CODE_16BIT
)
2491 cpu_arch_flags
.bitfield
.cpu64
= 0;
2492 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2493 stackop_size
= LONG_MNEM_SUFFIX
;
2497 set_intel_syntax (int syntax_flag
)
2499 /* Find out if register prefixing is specified. */
2500 int ask_naked_reg
= 0;
2503 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2506 int e
= get_symbol_name (&string
);
2508 if (strcmp (string
, "prefix") == 0)
2510 else if (strcmp (string
, "noprefix") == 0)
2513 as_bad (_("bad argument to syntax directive."));
2514 (void) restore_line_pointer (e
);
2516 demand_empty_rest_of_line ();
2518 intel_syntax
= syntax_flag
;
2520 if (ask_naked_reg
== 0)
2521 allow_naked_reg
= (intel_syntax
2522 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2524 allow_naked_reg
= (ask_naked_reg
< 0);
2526 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2528 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2529 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2530 register_prefix
= allow_naked_reg
? "" : "%";
2534 set_intel_mnemonic (int mnemonic_flag
)
2536 intel_mnemonic
= mnemonic_flag
;
2540 set_allow_index_reg (int flag
)
2542 allow_index_reg
= flag
;
2546 set_check (int what
)
2548 enum check_kind
*kind
;
2553 kind
= &operand_check
;
2564 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2567 int e
= get_symbol_name (&string
);
2569 if (strcmp (string
, "none") == 0)
2571 else if (strcmp (string
, "warning") == 0)
2572 *kind
= check_warning
;
2573 else if (strcmp (string
, "error") == 0)
2574 *kind
= check_error
;
2576 as_bad (_("bad argument to %s_check directive."), str
);
2577 (void) restore_line_pointer (e
);
2580 as_bad (_("missing argument for %s_check directive"), str
);
2582 demand_empty_rest_of_line ();
2586 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2587 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2590 static const char *arch
;
2592 /* Intel LIOM is only supported on ELF. */
2598 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2599 use default_arch. */
2600 arch
= cpu_arch_name
;
2602 arch
= default_arch
;
2605 /* If we are targeting Intel MCU, we must enable it. */
2606 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2607 || new_flag
.bitfield
.cpuiamcu
)
2610 /* If we are targeting Intel L1OM, we must enable it. */
2611 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2612 || new_flag
.bitfield
.cpul1om
)
2615 /* If we are targeting Intel K1OM, we must enable it. */
2616 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2617 || new_flag
.bitfield
.cpuk1om
)
2620 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2625 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2629 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2632 int e
= get_symbol_name (&string
);
2634 i386_cpu_flags flags
;
2636 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2638 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2640 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2644 cpu_arch_name
= cpu_arch
[j
].name
;
2645 cpu_sub_arch_name
= NULL
;
2646 cpu_arch_flags
= cpu_arch
[j
].flags
;
2647 if (flag_code
== CODE_64BIT
)
2649 cpu_arch_flags
.bitfield
.cpu64
= 1;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2654 cpu_arch_flags
.bitfield
.cpu64
= 0;
2655 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2657 cpu_arch_isa
= cpu_arch
[j
].type
;
2658 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2659 if (!cpu_arch_tune_set
)
2661 cpu_arch_tune
= cpu_arch_isa
;
2662 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2667 flags
= cpu_flags_or (cpu_arch_flags
,
2670 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2672 if (cpu_sub_arch_name
)
2674 char *name
= cpu_sub_arch_name
;
2675 cpu_sub_arch_name
= concat (name
,
2677 (const char *) NULL
);
2681 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2682 cpu_arch_flags
= flags
;
2683 cpu_arch_isa_flags
= flags
;
2687 = cpu_flags_or (cpu_arch_isa_flags
,
2689 (void) restore_line_pointer (e
);
2690 demand_empty_rest_of_line ();
2695 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2697 /* Disable an ISA extension. */
2698 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2699 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2701 flags
= cpu_flags_and_not (cpu_arch_flags
,
2702 cpu_noarch
[j
].flags
);
2703 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2705 if (cpu_sub_arch_name
)
2707 char *name
= cpu_sub_arch_name
;
2708 cpu_sub_arch_name
= concat (name
, string
,
2709 (const char *) NULL
);
2713 cpu_sub_arch_name
= xstrdup (string
);
2714 cpu_arch_flags
= flags
;
2715 cpu_arch_isa_flags
= flags
;
2717 (void) restore_line_pointer (e
);
2718 demand_empty_rest_of_line ();
2722 j
= ARRAY_SIZE (cpu_arch
);
2725 if (j
>= ARRAY_SIZE (cpu_arch
))
2726 as_bad (_("no such architecture: `%s'"), string
);
2728 *input_line_pointer
= e
;
2731 as_bad (_("missing cpu architecture"));
2733 no_cond_jump_promotion
= 0;
2734 if (*input_line_pointer
== ','
2735 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2740 ++input_line_pointer
;
2741 e
= get_symbol_name (&string
);
2743 if (strcmp (string
, "nojumps") == 0)
2744 no_cond_jump_promotion
= 1;
2745 else if (strcmp (string
, "jumps") == 0)
2748 as_bad (_("no such architecture modifier: `%s'"), string
);
2750 (void) restore_line_pointer (e
);
2753 demand_empty_rest_of_line ();
2756 enum bfd_architecture
2759 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2761 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2762 || flag_code
!= CODE_64BIT
)
2763 as_fatal (_("Intel L1OM is 64bit ELF only"));
2764 return bfd_arch_l1om
;
2766 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2768 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2769 || flag_code
!= CODE_64BIT
)
2770 as_fatal (_("Intel K1OM is 64bit ELF only"));
2771 return bfd_arch_k1om
;
2773 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2775 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2776 || flag_code
== CODE_64BIT
)
2777 as_fatal (_("Intel MCU is 32bit ELF only"));
2778 return bfd_arch_iamcu
;
2781 return bfd_arch_i386
;
2787 if (!strncmp (default_arch
, "x86_64", 6))
2789 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2791 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2792 || default_arch
[6] != '\0')
2793 as_fatal (_("Intel L1OM is 64bit ELF only"));
2794 return bfd_mach_l1om
;
2796 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2798 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2799 || default_arch
[6] != '\0')
2800 as_fatal (_("Intel K1OM is 64bit ELF only"));
2801 return bfd_mach_k1om
;
2803 else if (default_arch
[6] == '\0')
2804 return bfd_mach_x86_64
;
2806 return bfd_mach_x64_32
;
2808 else if (!strcmp (default_arch
, "i386")
2809 || !strcmp (default_arch
, "iamcu"))
2811 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2813 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2814 as_fatal (_("Intel MCU is 32bit ELF only"));
2815 return bfd_mach_i386_iamcu
;
2818 return bfd_mach_i386_i386
;
2821 as_fatal (_("unknown architecture"));
2827 const char *hash_err
;
2829 /* Support pseudo prefixes like {disp32}. */
2830 lex_type
['{'] = LEX_BEGIN_NAME
;
2832 /* Initialize op_hash hash table. */
2833 op_hash
= hash_new ();
2836 const insn_template
*optab
;
2837 templates
*core_optab
;
2839 /* Setup for loop. */
2841 core_optab
= XNEW (templates
);
2842 core_optab
->start
= optab
;
2847 if (optab
->name
== NULL
2848 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2850 /* different name --> ship out current template list;
2851 add to hash table; & begin anew. */
2852 core_optab
->end
= optab
;
2853 hash_err
= hash_insert (op_hash
,
2855 (void *) core_optab
);
2858 as_fatal (_("can't hash %s: %s"),
2862 if (optab
->name
== NULL
)
2864 core_optab
= XNEW (templates
);
2865 core_optab
->start
= optab
;
2870 /* Initialize reg_hash hash table. */
2871 reg_hash
= hash_new ();
2873 const reg_entry
*regtab
;
2874 unsigned int regtab_size
= i386_regtab_size
;
2876 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2878 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2880 as_fatal (_("can't hash %s: %s"),
2886 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2891 for (c
= 0; c
< 256; c
++)
2896 mnemonic_chars
[c
] = c
;
2897 register_chars
[c
] = c
;
2898 operand_chars
[c
] = c
;
2900 else if (ISLOWER (c
))
2902 mnemonic_chars
[c
] = c
;
2903 register_chars
[c
] = c
;
2904 operand_chars
[c
] = c
;
2906 else if (ISUPPER (c
))
2908 mnemonic_chars
[c
] = TOLOWER (c
);
2909 register_chars
[c
] = mnemonic_chars
[c
];
2910 operand_chars
[c
] = c
;
2912 else if (c
== '{' || c
== '}')
2914 mnemonic_chars
[c
] = c
;
2915 operand_chars
[c
] = c
;
2918 if (ISALPHA (c
) || ISDIGIT (c
))
2919 identifier_chars
[c
] = c
;
2922 identifier_chars
[c
] = c
;
2923 operand_chars
[c
] = c
;
2928 identifier_chars
['@'] = '@';
2931 identifier_chars
['?'] = '?';
2932 operand_chars
['?'] = '?';
2934 digit_chars
['-'] = '-';
2935 mnemonic_chars
['_'] = '_';
2936 mnemonic_chars
['-'] = '-';
2937 mnemonic_chars
['.'] = '.';
2938 identifier_chars
['_'] = '_';
2939 identifier_chars
['.'] = '.';
2941 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2942 operand_chars
[(unsigned char) *p
] = *p
;
2945 if (flag_code
== CODE_64BIT
)
2947 #if defined (OBJ_COFF) && defined (TE_PE)
2948 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2951 x86_dwarf2_return_column
= 16;
2953 x86_cie_data_alignment
= -8;
2957 x86_dwarf2_return_column
= 8;
2958 x86_cie_data_alignment
= -4;
2963 i386_print_statistics (FILE *file
)
2965 hash_print_statistics (file
, "i386 opcode", op_hash
);
2966 hash_print_statistics (file
, "i386 register", reg_hash
);
2971 /* Debugging routines for md_assemble. */
2972 static void pte (insn_template
*);
2973 static void pt (i386_operand_type
);
2974 static void pe (expressionS
*);
2975 static void ps (symbolS
*);
2978 pi (char *line
, i386_insn
*x
)
2982 fprintf (stdout
, "%s: template ", line
);
2984 fprintf (stdout
, " address: base %s index %s scale %x\n",
2985 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2986 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2987 x
->log2_scale_factor
);
2988 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2989 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2990 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2991 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2992 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2993 (x
->rex
& REX_W
) != 0,
2994 (x
->rex
& REX_R
) != 0,
2995 (x
->rex
& REX_X
) != 0,
2996 (x
->rex
& REX_B
) != 0);
2997 for (j
= 0; j
< x
->operands
; j
++)
2999 fprintf (stdout
, " #%d: ", j
+ 1);
3001 fprintf (stdout
, "\n");
3002 if (x
->types
[j
].bitfield
.reg
3003 || x
->types
[j
].bitfield
.regmmx
3004 || x
->types
[j
].bitfield
.regsimd
3005 || x
->types
[j
].bitfield
.sreg2
3006 || x
->types
[j
].bitfield
.sreg3
3007 || x
->types
[j
].bitfield
.control
3008 || x
->types
[j
].bitfield
.debug
3009 || x
->types
[j
].bitfield
.test
)
3010 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3011 if (operand_type_check (x
->types
[j
], imm
))
3013 if (operand_type_check (x
->types
[j
], disp
))
3014 pe (x
->op
[j
].disps
);
3019 pte (insn_template
*t
)
3022 fprintf (stdout
, " %d operands ", t
->operands
);
3023 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3024 if (t
->extension_opcode
!= None
)
3025 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3026 if (t
->opcode_modifier
.d
)
3027 fprintf (stdout
, "D");
3028 if (t
->opcode_modifier
.w
)
3029 fprintf (stdout
, "W");
3030 fprintf (stdout
, "\n");
3031 for (j
= 0; j
< t
->operands
; j
++)
3033 fprintf (stdout
, " #%d type ", j
+ 1);
3034 pt (t
->operand_types
[j
]);
3035 fprintf (stdout
, "\n");
3042 fprintf (stdout
, " operation %d\n", e
->X_op
);
3043 fprintf (stdout
, " add_number %ld (%lx)\n",
3044 (long) e
->X_add_number
, (long) e
->X_add_number
);
3045 if (e
->X_add_symbol
)
3047 fprintf (stdout
, " add_symbol ");
3048 ps (e
->X_add_symbol
);
3049 fprintf (stdout
, "\n");
3053 fprintf (stdout
, " op_symbol ");
3054 ps (e
->X_op_symbol
);
3055 fprintf (stdout
, "\n");
3062 fprintf (stdout
, "%s type %s%s",
3064 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3065 segment_name (S_GET_SEGMENT (s
)));
3068 static struct type_name
3070 i386_operand_type mask
;
3073 const type_names
[] =
3075 { OPERAND_TYPE_REG8
, "r8" },
3076 { OPERAND_TYPE_REG16
, "r16" },
3077 { OPERAND_TYPE_REG32
, "r32" },
3078 { OPERAND_TYPE_REG64
, "r64" },
3079 { OPERAND_TYPE_IMM8
, "i8" },
3080 { OPERAND_TYPE_IMM8
, "i8s" },
3081 { OPERAND_TYPE_IMM16
, "i16" },
3082 { OPERAND_TYPE_IMM32
, "i32" },
3083 { OPERAND_TYPE_IMM32S
, "i32s" },
3084 { OPERAND_TYPE_IMM64
, "i64" },
3085 { OPERAND_TYPE_IMM1
, "i1" },
3086 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3087 { OPERAND_TYPE_DISP8
, "d8" },
3088 { OPERAND_TYPE_DISP16
, "d16" },
3089 { OPERAND_TYPE_DISP32
, "d32" },
3090 { OPERAND_TYPE_DISP32S
, "d32s" },
3091 { OPERAND_TYPE_DISP64
, "d64" },
3092 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3093 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3094 { OPERAND_TYPE_CONTROL
, "control reg" },
3095 { OPERAND_TYPE_TEST
, "test reg" },
3096 { OPERAND_TYPE_DEBUG
, "debug reg" },
3097 { OPERAND_TYPE_FLOATREG
, "FReg" },
3098 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3099 { OPERAND_TYPE_SREG2
, "SReg2" },
3100 { OPERAND_TYPE_SREG3
, "SReg3" },
3101 { OPERAND_TYPE_ACC
, "Acc" },
3102 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3103 { OPERAND_TYPE_REGMMX
, "rMMX" },
3104 { OPERAND_TYPE_REGXMM
, "rXMM" },
3105 { OPERAND_TYPE_REGYMM
, "rYMM" },
3106 { OPERAND_TYPE_REGZMM
, "rZMM" },
3107 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3108 { OPERAND_TYPE_ESSEG
, "es" },
3112 pt (i386_operand_type t
)
3115 i386_operand_type a
;
3117 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3119 a
= operand_type_and (t
, type_names
[j
].mask
);
3120 if (!operand_type_all_zero (&a
))
3121 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3126 #endif /* DEBUG386 */
3128 static bfd_reloc_code_real_type
3129 reloc (unsigned int size
,
3132 bfd_reloc_code_real_type other
)
3134 if (other
!= NO_RELOC
)
3136 reloc_howto_type
*rel
;
3141 case BFD_RELOC_X86_64_GOT32
:
3142 return BFD_RELOC_X86_64_GOT64
;
3144 case BFD_RELOC_X86_64_GOTPLT64
:
3145 return BFD_RELOC_X86_64_GOTPLT64
;
3147 case BFD_RELOC_X86_64_PLTOFF64
:
3148 return BFD_RELOC_X86_64_PLTOFF64
;
3150 case BFD_RELOC_X86_64_GOTPC32
:
3151 other
= BFD_RELOC_X86_64_GOTPC64
;
3153 case BFD_RELOC_X86_64_GOTPCREL
:
3154 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3156 case BFD_RELOC_X86_64_TPOFF32
:
3157 other
= BFD_RELOC_X86_64_TPOFF64
;
3159 case BFD_RELOC_X86_64_DTPOFF32
:
3160 other
= BFD_RELOC_X86_64_DTPOFF64
;
3166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3167 if (other
== BFD_RELOC_SIZE32
)
3170 other
= BFD_RELOC_SIZE64
;
3173 as_bad (_("there are no pc-relative size relocations"));
3179 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3180 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3183 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3185 as_bad (_("unknown relocation (%u)"), other
);
3186 else if (size
!= bfd_get_reloc_size (rel
))
3187 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3188 bfd_get_reloc_size (rel
),
3190 else if (pcrel
&& !rel
->pc_relative
)
3191 as_bad (_("non-pc-relative relocation for pc-relative field"));
3192 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3194 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3196 as_bad (_("relocated field and relocation type differ in signedness"));
3205 as_bad (_("there are no unsigned pc-relative relocations"));
3208 case 1: return BFD_RELOC_8_PCREL
;
3209 case 2: return BFD_RELOC_16_PCREL
;
3210 case 4: return BFD_RELOC_32_PCREL
;
3211 case 8: return BFD_RELOC_64_PCREL
;
3213 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3220 case 4: return BFD_RELOC_X86_64_32S
;
3225 case 1: return BFD_RELOC_8
;
3226 case 2: return BFD_RELOC_16
;
3227 case 4: return BFD_RELOC_32
;
3228 case 8: return BFD_RELOC_64
;
3230 as_bad (_("cannot do %s %u byte relocation"),
3231 sign
> 0 ? "signed" : "unsigned", size
);
3237 /* Here we decide which fixups can be adjusted to make them relative to
3238 the beginning of the section instead of the symbol. Basically we need
3239 to make sure that the dynamic relocations are done correctly, so in
3240 some cases we force the original symbol to be used. */
3243 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3249 /* Don't adjust pc-relative references to merge sections in 64-bit
3251 if (use_rela_relocations
3252 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3256 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3257 and changed later by validate_fix. */
3258 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3259 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3262 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3263 for size relocations. */
3264 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3265 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3266 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3267 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3268 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3269 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3270 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3271 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3272 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3273 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3274 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3275 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3276 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3277 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3278 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3279 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3280 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3281 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3282 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3283 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3284 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3285 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3286 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3287 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3288 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3289 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3290 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3295 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3296 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3303 intel_float_operand (const char *mnemonic
)
3305 /* Note that the value returned is meaningful only for opcodes with (memory)
3306 operands, hence the code here is free to improperly handle opcodes that
3307 have no operands (for better performance and smaller code). */
3309 if (mnemonic
[0] != 'f')
3310 return 0; /* non-math */
3312 switch (mnemonic
[1])
3314 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3315 the fs segment override prefix not currently handled because no
3316 call path can make opcodes without operands get here */
3318 return 2 /* integer op */;
3320 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3321 return 3; /* fldcw/fldenv */
3324 if (mnemonic
[2] != 'o' /* fnop */)
3325 return 3; /* non-waiting control op */
3328 if (mnemonic
[2] == 's')
3329 return 3; /* frstor/frstpm */
3332 if (mnemonic
[2] == 'a')
3333 return 3; /* fsave */
3334 if (mnemonic
[2] == 't')
3336 switch (mnemonic
[3])
3338 case 'c': /* fstcw */
3339 case 'd': /* fstdw */
3340 case 'e': /* fstenv */
3341 case 's': /* fsts[gw] */
3347 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3348 return 0; /* fxsave/fxrstor are not really math ops */
3355 /* Build the VEX prefix. */
3358 build_vex_prefix (const insn_template
*t
)
3360 unsigned int register_specifier
;
3361 unsigned int implied_prefix
;
3362 unsigned int vector_length
;
3365 /* Check register specifier. */
3366 if (i
.vex
.register_specifier
)
3368 register_specifier
=
3369 ~register_number (i
.vex
.register_specifier
) & 0xf;
3370 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3373 register_specifier
= 0xf;
3375 /* Use 2-byte VEX prefix by swapping destination and source operand
3376 if there are more than 1 register operand. */
3377 if (i
.reg_operands
> 1
3378 && i
.vec_encoding
!= vex_encoding_vex3
3379 && i
.dir_encoding
== dir_encoding_default
3380 && i
.operands
== i
.reg_operands
3381 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3382 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3383 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3386 unsigned int xchg
= i
.operands
- 1;
3387 union i386_op temp_op
;
3388 i386_operand_type temp_type
;
3390 temp_type
= i
.types
[xchg
];
3391 i
.types
[xchg
] = i
.types
[0];
3392 i
.types
[0] = temp_type
;
3393 temp_op
= i
.op
[xchg
];
3394 i
.op
[xchg
] = i
.op
[0];
3397 gas_assert (i
.rm
.mode
== 3);
3401 i
.rm
.regmem
= i
.rm
.reg
;
3404 if (i
.tm
.opcode_modifier
.d
)
3405 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3406 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3407 else /* Use the next insn. */
3411 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3412 vector_length
= avxscalar
;
3413 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3419 /* Determine vector length from the last multi-length vector
3422 for (op
= t
->operands
; op
--;)
3423 if (t
->operand_types
[op
].bitfield
.xmmword
3424 && t
->operand_types
[op
].bitfield
.ymmword
3425 && i
.types
[op
].bitfield
.ymmword
)
3432 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3437 case DATA_PREFIX_OPCODE
:
3440 case REPE_PREFIX_OPCODE
:
3443 case REPNE_PREFIX_OPCODE
:
3450 /* Check the REX.W bit and VEXW. */
3451 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3452 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3453 else if (i
.tm
.opcode_modifier
.vexw
)
3454 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3456 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3458 /* Use 2-byte VEX prefix if possible. */
3460 && i
.vec_encoding
!= vex_encoding_vex3
3461 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3462 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3464 /* 2-byte VEX prefix. */
3468 i
.vex
.bytes
[0] = 0xc5;
3470 /* Check the REX.R bit. */
3471 r
= (i
.rex
& REX_R
) ? 0 : 1;
3472 i
.vex
.bytes
[1] = (r
<< 7
3473 | register_specifier
<< 3
3474 | vector_length
<< 2
3479 /* 3-byte VEX prefix. */
3484 switch (i
.tm
.opcode_modifier
.vexopcode
)
3488 i
.vex
.bytes
[0] = 0xc4;
3492 i
.vex
.bytes
[0] = 0xc4;
3496 i
.vex
.bytes
[0] = 0xc4;
3500 i
.vex
.bytes
[0] = 0x8f;
3504 i
.vex
.bytes
[0] = 0x8f;
3508 i
.vex
.bytes
[0] = 0x8f;
3514 /* The high 3 bits of the second VEX byte are 1's compliment
3515 of RXB bits from REX. */
3516 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3518 i
.vex
.bytes
[2] = (w
<< 7
3519 | register_specifier
<< 3
3520 | vector_length
<< 2
3525 static INLINE bfd_boolean
3526 is_evex_encoding (const insn_template
*t
)
3528 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3529 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3530 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3533 static INLINE bfd_boolean
3534 is_any_vex_encoding (const insn_template
*t
)
3536 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3537 || is_evex_encoding (t
);
3540 /* Build the EVEX prefix. */
3543 build_evex_prefix (void)
3545 unsigned int register_specifier
;
3546 unsigned int implied_prefix
;
3548 rex_byte vrex_used
= 0;
3550 /* Check register specifier. */
3551 if (i
.vex
.register_specifier
)
3553 gas_assert ((i
.vrex
& REX_X
) == 0);
3555 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3556 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3557 register_specifier
+= 8;
3558 /* The upper 16 registers are encoded in the fourth byte of the
3560 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3561 i
.vex
.bytes
[3] = 0x8;
3562 register_specifier
= ~register_specifier
& 0xf;
3566 register_specifier
= 0xf;
3568 /* Encode upper 16 vector index register in the fourth byte of
3570 if (!(i
.vrex
& REX_X
))
3571 i
.vex
.bytes
[3] = 0x8;
3576 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3581 case DATA_PREFIX_OPCODE
:
3584 case REPE_PREFIX_OPCODE
:
3587 case REPNE_PREFIX_OPCODE
:
3594 /* 4 byte EVEX prefix. */
3596 i
.vex
.bytes
[0] = 0x62;
3599 switch (i
.tm
.opcode_modifier
.vexopcode
)
3615 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3617 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3619 /* The fifth bit of the second EVEX byte is 1's compliment of the
3620 REX_R bit in VREX. */
3621 if (!(i
.vrex
& REX_R
))
3622 i
.vex
.bytes
[1] |= 0x10;
3626 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3628 /* When all operands are registers, the REX_X bit in REX is not
3629 used. We reuse it to encode the upper 16 registers, which is
3630 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3631 as 1's compliment. */
3632 if ((i
.vrex
& REX_B
))
3635 i
.vex
.bytes
[1] &= ~0x40;
3639 /* EVEX instructions shouldn't need the REX prefix. */
3640 i
.vrex
&= ~vrex_used
;
3641 gas_assert (i
.vrex
== 0);
3643 /* Check the REX.W bit and VEXW. */
3644 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3645 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3646 else if (i
.tm
.opcode_modifier
.vexw
)
3647 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3649 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3651 /* Encode the U bit. */
3652 implied_prefix
|= 0x4;
3654 /* The third byte of the EVEX prefix. */
3655 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3657 /* The fourth byte of the EVEX prefix. */
3658 /* The zeroing-masking bit. */
3659 if (i
.mask
&& i
.mask
->zeroing
)
3660 i
.vex
.bytes
[3] |= 0x80;
3662 /* Don't always set the broadcast bit if there is no RC. */
3665 /* Encode the vector length. */
3666 unsigned int vec_length
;
3668 if (!i
.tm
.opcode_modifier
.evex
3669 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3673 /* Determine vector length from the last multi-length vector
3676 for (op
= i
.operands
; op
--;)
3677 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3678 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3679 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3681 if (i
.types
[op
].bitfield
.zmmword
)
3683 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3686 else if (i
.types
[op
].bitfield
.ymmword
)
3688 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3691 else if (i
.types
[op
].bitfield
.xmmword
)
3693 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3696 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3698 switch (i
.broadcast
->bytes
)
3701 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3704 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3707 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3716 if (op
>= MAX_OPERANDS
)
3720 switch (i
.tm
.opcode_modifier
.evex
)
3722 case EVEXLIG
: /* LL' is ignored */
3723 vec_length
= evexlig
<< 5;
3726 vec_length
= 0 << 5;
3729 vec_length
= 1 << 5;
3732 vec_length
= 2 << 5;
3738 i
.vex
.bytes
[3] |= vec_length
;
3739 /* Encode the broadcast bit. */
3741 i
.vex
.bytes
[3] |= 0x10;
3745 if (i
.rounding
->type
!= saeonly
)
3746 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3748 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3751 if (i
.mask
&& i
.mask
->mask
)
3752 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3756 process_immext (void)
3760 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3763 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3764 with an opcode suffix which is coded in the same place as an
3765 8-bit immediate field would be.
3766 Here we check those operands and remove them afterwards. */
3769 for (x
= 0; x
< i
.operands
; x
++)
3770 if (register_number (i
.op
[x
].regs
) != x
)
3771 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3772 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3778 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3780 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3781 suffix which is coded in the same place as an 8-bit immediate
3783 Here we check those operands and remove them afterwards. */
3786 if (i
.operands
!= 3)
3789 for (x
= 0; x
< 2; x
++)
3790 if (register_number (i
.op
[x
].regs
) != x
)
3791 goto bad_register_operand
;
3793 /* Check for third operand for mwaitx/monitorx insn. */
3794 if (register_number (i
.op
[x
].regs
)
3795 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3797 bad_register_operand
:
3798 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3799 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3806 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3807 which is coded in the same place as an 8-bit immediate field
3808 would be. Here we fake an 8-bit immediate operand from the
3809 opcode suffix stored in tm.extension_opcode.
3811 AVX instructions also use this encoding, for some of
3812 3 argument instructions. */
3814 gas_assert (i
.imm_operands
<= 1
3816 || (is_any_vex_encoding (&i
.tm
)
3817 && i
.operands
<= 4)));
3819 exp
= &im_expressions
[i
.imm_operands
++];
3820 i
.op
[i
.operands
].imms
= exp
;
3821 i
.types
[i
.operands
] = imm8
;
3823 exp
->X_op
= O_constant
;
3824 exp
->X_add_number
= i
.tm
.extension_opcode
;
3825 i
.tm
.extension_opcode
= None
;
3832 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3837 as_bad (_("invalid instruction `%s' after `%s'"),
3838 i
.tm
.name
, i
.hle_prefix
);
3841 if (i
.prefix
[LOCK_PREFIX
])
3843 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3847 case HLEPrefixRelease
:
3848 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3850 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3854 if (i
.mem_operands
== 0
3855 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3857 as_bad (_("memory destination needed for instruction `%s'"
3858 " after `xrelease'"), i
.tm
.name
);
3865 /* Try the shortest encoding by shortening operand size. */
3868 optimize_encoding (void)
3872 if (optimize_for_space
3873 && i
.reg_operands
== 1
3874 && i
.imm_operands
== 1
3875 && !i
.types
[1].bitfield
.byte
3876 && i
.op
[0].imms
->X_op
== O_constant
3877 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3878 && ((i
.tm
.base_opcode
== 0xa8
3879 && i
.tm
.extension_opcode
== None
)
3880 || (i
.tm
.base_opcode
== 0xf6
3881 && i
.tm
.extension_opcode
== 0x0)))
3884 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3886 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3887 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3889 i
.types
[1].bitfield
.byte
= 1;
3890 /* Ignore the suffix. */
3892 if (base_regnum
>= 4
3893 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3895 /* Handle SP, BP, SI and DI registers. */
3896 if (i
.types
[1].bitfield
.word
)
3898 else if (i
.types
[1].bitfield
.dword
)
3906 else if (flag_code
== CODE_64BIT
3907 && ((i
.types
[1].bitfield
.qword
3908 && i
.reg_operands
== 1
3909 && i
.imm_operands
== 1
3910 && i
.op
[0].imms
->X_op
== O_constant
3911 && ((i
.tm
.base_opcode
== 0xb0
3912 && i
.tm
.extension_opcode
== None
3913 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3914 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3915 && (((i
.tm
.base_opcode
== 0x24
3916 || i
.tm
.base_opcode
== 0xa8)
3917 && i
.tm
.extension_opcode
== None
)
3918 || (i
.tm
.base_opcode
== 0x80
3919 && i
.tm
.extension_opcode
== 0x4)
3920 || ((i
.tm
.base_opcode
== 0xf6
3921 || i
.tm
.base_opcode
== 0xc6)
3922 && i
.tm
.extension_opcode
== 0x0)))))
3923 || (i
.types
[0].bitfield
.qword
3924 && ((i
.reg_operands
== 2
3925 && i
.op
[0].regs
== i
.op
[1].regs
3926 && ((i
.tm
.base_opcode
== 0x30
3927 || i
.tm
.base_opcode
== 0x28)
3928 && i
.tm
.extension_opcode
== None
))
3929 || (i
.reg_operands
== 1
3931 && i
.tm
.base_opcode
== 0x30
3932 && i
.tm
.extension_opcode
== None
)))))
3935 andq $imm31, %r64 -> andl $imm31, %r32
3936 testq $imm31, %r64 -> testl $imm31, %r32
3937 xorq %r64, %r64 -> xorl %r32, %r32
3938 subq %r64, %r64 -> subl %r32, %r32
3939 movq $imm31, %r64 -> movl $imm31, %r32
3940 movq $imm32, %r64 -> movl $imm32, %r32
3942 i
.tm
.opcode_modifier
.norex64
= 1;
3943 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3946 movq $imm31, %r64 -> movl $imm31, %r32
3947 movq $imm32, %r64 -> movl $imm32, %r32
3949 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3950 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3951 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3952 i
.types
[0].bitfield
.imm32
= 1;
3953 i
.types
[0].bitfield
.imm32s
= 0;
3954 i
.types
[0].bitfield
.imm64
= 0;
3955 i
.types
[1].bitfield
.dword
= 1;
3956 i
.types
[1].bitfield
.qword
= 0;
3957 if (i
.tm
.base_opcode
== 0xc6)
3960 movq $imm31, %r64 -> movl $imm31, %r32
3962 i
.tm
.base_opcode
= 0xb0;
3963 i
.tm
.extension_opcode
= None
;
3964 i
.tm
.opcode_modifier
.shortform
= 1;
3965 i
.tm
.opcode_modifier
.modrm
= 0;
3969 else if (optimize
> 1
3970 && i
.reg_operands
== 3
3971 && i
.op
[0].regs
== i
.op
[1].regs
3972 && !i
.types
[2].bitfield
.xmmword
3973 && (i
.tm
.opcode_modifier
.vex
3974 || ((!i
.mask
|| i
.mask
->zeroing
)
3976 && is_evex_encoding (&i
.tm
)
3977 && (i
.vec_encoding
!= vex_encoding_evex
3978 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3979 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3980 && i
.types
[2].bitfield
.ymmword
)
3981 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3982 && ((i
.tm
.base_opcode
== 0x55
3983 || i
.tm
.base_opcode
== 0x6655
3984 || i
.tm
.base_opcode
== 0x66df
3985 || i
.tm
.base_opcode
== 0x57
3986 || i
.tm
.base_opcode
== 0x6657
3987 || i
.tm
.base_opcode
== 0x66ef
3988 || i
.tm
.base_opcode
== 0x66f8
3989 || i
.tm
.base_opcode
== 0x66f9
3990 || i
.tm
.base_opcode
== 0x66fa
3991 || i
.tm
.base_opcode
== 0x66fb
3992 || i
.tm
.base_opcode
== 0x42
3993 || i
.tm
.base_opcode
== 0x6642
3994 || i
.tm
.base_opcode
== 0x47
3995 || i
.tm
.base_opcode
== 0x6647)
3996 && i
.tm
.extension_opcode
== None
))
3999 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4001 EVEX VOP %zmmM, %zmmM, %zmmN
4002 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4003 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4004 EVEX VOP %ymmM, %ymmM, %ymmN
4005 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4006 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4007 VEX VOP %ymmM, %ymmM, %ymmN
4008 -> VEX VOP %xmmM, %xmmM, %xmmN
4009 VOP, one of vpandn and vpxor:
4010 VEX VOP %ymmM, %ymmM, %ymmN
4011 -> VEX VOP %xmmM, %xmmM, %xmmN
4012 VOP, one of vpandnd and vpandnq:
4013 EVEX VOP %zmmM, %zmmM, %zmmN
4014 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4015 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4016 EVEX VOP %ymmM, %ymmM, %ymmN
4017 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4018 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4019 VOP, one of vpxord and vpxorq:
4020 EVEX VOP %zmmM, %zmmM, %zmmN
4021 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4022 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4023 EVEX VOP %ymmM, %ymmM, %ymmN
4024 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4025 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4026 VOP, one of kxord and kxorq:
4027 VEX VOP %kM, %kM, %kN
4028 -> VEX kxorw %kM, %kM, %kN
4029 VOP, one of kandnd and kandnq:
4030 VEX VOP %kM, %kM, %kN
4031 -> VEX kandnw %kM, %kM, %kN
4033 if (is_evex_encoding (&i
.tm
))
4035 if (i
.vec_encoding
== vex_encoding_evex
)
4036 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4039 i
.tm
.opcode_modifier
.vex
= VEX128
;
4040 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4041 i
.tm
.opcode_modifier
.evex
= 0;
4044 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4046 i
.tm
.base_opcode
&= 0xff;
4047 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4050 i
.tm
.opcode_modifier
.vex
= VEX128
;
4052 if (i
.tm
.opcode_modifier
.vex
)
4053 for (j
= 0; j
< 3; j
++)
4055 i
.types
[j
].bitfield
.xmmword
= 1;
4056 i
.types
[j
].bitfield
.ymmword
= 0;
4061 /* This is the guts of the machine-dependent assembler. LINE points to a
4062 machine dependent instruction. This function is supposed to emit
4063 the frags/bytes it assembles to. */
4066 md_assemble (char *line
)
4069 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4070 const insn_template
*t
;
4072 /* Initialize globals. */
4073 memset (&i
, '\0', sizeof (i
));
4074 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4075 i
.reloc
[j
] = NO_RELOC
;
4076 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4077 memset (im_expressions
, '\0', sizeof (im_expressions
));
4078 save_stack_p
= save_stack
;
4080 /* First parse an instruction mnemonic & call i386_operand for the operands.
4081 We assume that the scrubber has arranged it so that line[0] is the valid
4082 start of a (possibly prefixed) mnemonic. */
4084 line
= parse_insn (line
, mnemonic
);
4087 mnem_suffix
= i
.suffix
;
4089 line
= parse_operands (line
, mnemonic
);
4091 xfree (i
.memop1_string
);
4092 i
.memop1_string
= NULL
;
4096 /* Now we've parsed the mnemonic into a set of templates, and have the
4097 operands at hand. */
4099 /* All intel opcodes have reversed operands except for "bound" and
4100 "enter". We also don't reverse intersegment "jmp" and "call"
4101 instructions with 2 immediate operands so that the immediate segment
4102 precedes the offset, as it does when in AT&T mode. */
4105 && (strcmp (mnemonic
, "bound") != 0)
4106 && (strcmp (mnemonic
, "invlpga") != 0)
4107 && !(operand_type_check (i
.types
[0], imm
)
4108 && operand_type_check (i
.types
[1], imm
)))
4111 /* The order of the immediates should be reversed
4112 for 2 immediates extrq and insertq instructions */
4113 if (i
.imm_operands
== 2
4114 && (strcmp (mnemonic
, "extrq") == 0
4115 || strcmp (mnemonic
, "insertq") == 0))
4116 swap_2_operands (0, 1);
4121 /* Don't optimize displacement for movabs since it only takes 64bit
4124 && i
.disp_encoding
!= disp_encoding_32bit
4125 && (flag_code
!= CODE_64BIT
4126 || strcmp (mnemonic
, "movabs") != 0))
4129 /* Next, we find a template that matches the given insn,
4130 making sure the overlap of the given operands types is consistent
4131 with the template operand types. */
4133 if (!(t
= match_template (mnem_suffix
)))
4136 if (sse_check
!= check_none
4137 && !i
.tm
.opcode_modifier
.noavx
4138 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4139 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4140 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4141 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4142 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4143 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4144 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4145 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4146 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4147 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4149 (sse_check
== check_warning
4151 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4154 /* Zap movzx and movsx suffix. The suffix has been set from
4155 "word ptr" or "byte ptr" on the source operand in Intel syntax
4156 or extracted from mnemonic in AT&T syntax. But we'll use
4157 the destination register to choose the suffix for encoding. */
4158 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4160 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4161 there is no suffix, the default will be byte extension. */
4162 if (i
.reg_operands
!= 2
4165 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4170 if (i
.tm
.opcode_modifier
.fwait
)
4171 if (!add_prefix (FWAIT_OPCODE
))
4174 /* Check if REP prefix is OK. */
4175 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4177 as_bad (_("invalid instruction `%s' after `%s'"),
4178 i
.tm
.name
, i
.rep_prefix
);
4182 /* Check for lock without a lockable instruction. Destination operand
4183 must be memory unless it is xchg (0x86). */
4184 if (i
.prefix
[LOCK_PREFIX
]
4185 && (!i
.tm
.opcode_modifier
.islockable
4186 || i
.mem_operands
== 0
4187 || (i
.tm
.base_opcode
!= 0x86
4188 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4190 as_bad (_("expecting lockable instruction after `lock'"));
4194 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4195 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4197 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4201 /* Check if HLE prefix is OK. */
4202 if (i
.hle_prefix
&& !check_hle ())
4205 /* Check BND prefix. */
4206 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4207 as_bad (_("expecting valid branch instruction after `bnd'"));
4209 /* Check NOTRACK prefix. */
4210 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4211 as_bad (_("expecting indirect branch instruction after `notrack'"));
4213 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4215 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4216 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4217 else if (flag_code
!= CODE_16BIT
4218 ? i
.prefix
[ADDR_PREFIX
]
4219 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4220 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4223 /* Insert BND prefix. */
4224 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4226 if (!i
.prefix
[BND_PREFIX
])
4227 add_prefix (BND_PREFIX_OPCODE
);
4228 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4230 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4231 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4235 /* Check string instruction segment overrides. */
4236 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4238 if (!check_string ())
4240 i
.disp_operands
= 0;
4243 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4244 optimize_encoding ();
4246 if (!process_suffix ())
4249 /* Update operand types. */
4250 for (j
= 0; j
< i
.operands
; j
++)
4251 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4253 /* Make still unresolved immediate matches conform to size of immediate
4254 given in i.suffix. */
4255 if (!finalize_imm ())
4258 if (i
.types
[0].bitfield
.imm1
)
4259 i
.imm_operands
= 0; /* kludge for shift insns. */
4261 /* We only need to check those implicit registers for instructions
4262 with 3 operands or less. */
4263 if (i
.operands
<= 3)
4264 for (j
= 0; j
< i
.operands
; j
++)
4265 if (i
.types
[j
].bitfield
.inoutportreg
4266 || i
.types
[j
].bitfield
.shiftcount
4267 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4270 /* ImmExt should be processed after SSE2AVX. */
4271 if (!i
.tm
.opcode_modifier
.sse2avx
4272 && i
.tm
.opcode_modifier
.immext
)
4275 /* For insns with operands there are more diddles to do to the opcode. */
4278 if (!process_operands ())
4281 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4283 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4284 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4287 if (is_any_vex_encoding (&i
.tm
))
4289 if (flag_code
== CODE_16BIT
)
4291 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4296 if (i
.tm
.opcode_modifier
.vex
)
4297 build_vex_prefix (t
);
4299 build_evex_prefix ();
4302 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4303 instructions may define INT_OPCODE as well, so avoid this corner
4304 case for those instructions that use MODRM. */
4305 if (i
.tm
.base_opcode
== INT_OPCODE
4306 && !i
.tm
.opcode_modifier
.modrm
4307 && i
.op
[0].imms
->X_add_number
== 3)
4309 i
.tm
.base_opcode
= INT3_OPCODE
;
4313 if ((i
.tm
.opcode_modifier
.jump
4314 || i
.tm
.opcode_modifier
.jumpbyte
4315 || i
.tm
.opcode_modifier
.jumpdword
)
4316 && i
.op
[0].disps
->X_op
== O_constant
)
4318 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4319 the absolute address given by the constant. Since ix86 jumps and
4320 calls are pc relative, we need to generate a reloc. */
4321 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4322 i
.op
[0].disps
->X_op
= O_symbol
;
4325 if (i
.tm
.opcode_modifier
.rex64
)
4328 /* For 8 bit registers we need an empty rex prefix. Also if the
4329 instruction already has a prefix, we need to convert old
4330 registers to new ones. */
4332 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4333 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4334 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4335 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4336 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4337 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4342 i
.rex
|= REX_OPCODE
;
4343 for (x
= 0; x
< 2; x
++)
4345 /* Look for 8 bit operand that uses old registers. */
4346 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4347 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4349 /* In case it is "hi" register, give up. */
4350 if (i
.op
[x
].regs
->reg_num
> 3)
4351 as_bad (_("can't encode register '%s%s' in an "
4352 "instruction requiring REX prefix."),
4353 register_prefix
, i
.op
[x
].regs
->reg_name
);
4355 /* Otherwise it is equivalent to the extended register.
4356 Since the encoding doesn't change this is merely
4357 cosmetic cleanup for debug output. */
4359 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4364 if (i
.rex
== 0 && i
.rex_encoding
)
4366 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4367 that uses legacy register. If it is "hi" register, don't add
4368 the REX_OPCODE byte. */
4370 for (x
= 0; x
< 2; x
++)
4371 if (i
.types
[x
].bitfield
.reg
4372 && i
.types
[x
].bitfield
.byte
4373 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4374 && i
.op
[x
].regs
->reg_num
> 3)
4376 i
.rex_encoding
= FALSE
;
4385 add_prefix (REX_OPCODE
| i
.rex
);
4387 /* We are ready to output the insn. */
4392 parse_insn (char *line
, char *mnemonic
)
4395 char *token_start
= l
;
4398 const insn_template
*t
;
4404 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4409 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4411 as_bad (_("no such instruction: `%s'"), token_start
);
4416 if (!is_space_char (*l
)
4417 && *l
!= END_OF_INSN
4419 || (*l
!= PREFIX_SEPARATOR
4422 as_bad (_("invalid character %s in mnemonic"),
4423 output_invalid (*l
));
4426 if (token_start
== l
)
4428 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4429 as_bad (_("expecting prefix; got nothing"));
4431 as_bad (_("expecting mnemonic; got nothing"));
4435 /* Look up instruction (or prefix) via hash table. */
4436 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4438 if (*l
!= END_OF_INSN
4439 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4440 && current_templates
4441 && current_templates
->start
->opcode_modifier
.isprefix
)
4443 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4445 as_bad ((flag_code
!= CODE_64BIT
4446 ? _("`%s' is only supported in 64-bit mode")
4447 : _("`%s' is not supported in 64-bit mode")),
4448 current_templates
->start
->name
);
4451 /* If we are in 16-bit mode, do not allow addr16 or data16.
4452 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4453 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4454 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4455 && flag_code
!= CODE_64BIT
4456 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4457 ^ (flag_code
== CODE_16BIT
)))
4459 as_bad (_("redundant %s prefix"),
4460 current_templates
->start
->name
);
4463 if (current_templates
->start
->opcode_length
== 0)
4465 /* Handle pseudo prefixes. */
4466 switch (current_templates
->start
->base_opcode
)
4470 i
.disp_encoding
= disp_encoding_8bit
;
4474 i
.disp_encoding
= disp_encoding_32bit
;
4478 i
.dir_encoding
= dir_encoding_load
;
4482 i
.dir_encoding
= dir_encoding_store
;
4486 i
.vec_encoding
= vex_encoding_vex2
;
4490 i
.vec_encoding
= vex_encoding_vex3
;
4494 i
.vec_encoding
= vex_encoding_evex
;
4498 i
.rex_encoding
= TRUE
;
4502 i
.no_optimize
= TRUE
;
4510 /* Add prefix, checking for repeated prefixes. */
4511 switch (add_prefix (current_templates
->start
->base_opcode
))
4516 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4517 i
.notrack_prefix
= current_templates
->start
->name
;
4520 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4521 i
.hle_prefix
= current_templates
->start
->name
;
4522 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4523 i
.bnd_prefix
= current_templates
->start
->name
;
4525 i
.rep_prefix
= current_templates
->start
->name
;
4531 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4538 if (!current_templates
)
4540 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4541 Check if we should swap operand or force 32bit displacement in
4543 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4544 i
.dir_encoding
= dir_encoding_swap
;
4545 else if (mnem_p
- 3 == dot_p
4548 i
.disp_encoding
= disp_encoding_8bit
;
4549 else if (mnem_p
- 4 == dot_p
4553 i
.disp_encoding
= disp_encoding_32bit
;
4558 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4561 if (!current_templates
)
4564 if (mnem_p
> mnemonic
)
4566 /* See if we can get a match by trimming off a suffix. */
4569 case WORD_MNEM_SUFFIX
:
4570 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4571 i
.suffix
= SHORT_MNEM_SUFFIX
;
4574 case BYTE_MNEM_SUFFIX
:
4575 case QWORD_MNEM_SUFFIX
:
4576 i
.suffix
= mnem_p
[-1];
4578 current_templates
= (const templates
*) hash_find (op_hash
,
4581 case SHORT_MNEM_SUFFIX
:
4582 case LONG_MNEM_SUFFIX
:
4585 i
.suffix
= mnem_p
[-1];
4587 current_templates
= (const templates
*) hash_find (op_hash
,
4596 if (intel_float_operand (mnemonic
) == 1)
4597 i
.suffix
= SHORT_MNEM_SUFFIX
;
4599 i
.suffix
= LONG_MNEM_SUFFIX
;
4601 current_templates
= (const templates
*) hash_find (op_hash
,
4608 if (!current_templates
)
4610 as_bad (_("no such instruction: `%s'"), token_start
);
4615 if (current_templates
->start
->opcode_modifier
.jump
4616 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4618 /* Check for a branch hint. We allow ",pt" and ",pn" for
4619 predict taken and predict not taken respectively.
4620 I'm not sure that branch hints actually do anything on loop
4621 and jcxz insns (JumpByte) for current Pentium4 chips. They
4622 may work in the future and it doesn't hurt to accept them
4624 if (l
[0] == ',' && l
[1] == 'p')
4628 if (!add_prefix (DS_PREFIX_OPCODE
))
4632 else if (l
[2] == 'n')
4634 if (!add_prefix (CS_PREFIX_OPCODE
))
4640 /* Any other comma loses. */
4643 as_bad (_("invalid character %s in mnemonic"),
4644 output_invalid (*l
));
4648 /* Check if instruction is supported on specified architecture. */
4650 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4652 supported
|= cpu_flags_match (t
);
4653 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4655 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4656 as_warn (_("use .code16 to ensure correct addressing mode"));
4662 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4663 as_bad (flag_code
== CODE_64BIT
4664 ? _("`%s' is not supported in 64-bit mode")
4665 : _("`%s' is only supported in 64-bit mode"),
4666 current_templates
->start
->name
);
4668 as_bad (_("`%s' is not supported on `%s%s'"),
4669 current_templates
->start
->name
,
4670 cpu_arch_name
? cpu_arch_name
: default_arch
,
4671 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4677 parse_operands (char *l
, const char *mnemonic
)
4681 /* 1 if operand is pending after ','. */
4682 unsigned int expecting_operand
= 0;
4684 /* Non-zero if operand parens not balanced. */
4685 unsigned int paren_not_balanced
;
4687 while (*l
!= END_OF_INSN
)
4689 /* Skip optional white space before operand. */
4690 if (is_space_char (*l
))
4692 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4694 as_bad (_("invalid character %s before operand %d"),
4695 output_invalid (*l
),
4699 token_start
= l
; /* After white space. */
4700 paren_not_balanced
= 0;
4701 while (paren_not_balanced
|| *l
!= ',')
4703 if (*l
== END_OF_INSN
)
4705 if (paren_not_balanced
)
4708 as_bad (_("unbalanced parenthesis in operand %d."),
4711 as_bad (_("unbalanced brackets in operand %d."),
4716 break; /* we are done */
4718 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4720 as_bad (_("invalid character %s in operand %d"),
4721 output_invalid (*l
),
4728 ++paren_not_balanced
;
4730 --paren_not_balanced
;
4735 ++paren_not_balanced
;
4737 --paren_not_balanced
;
4741 if (l
!= token_start
)
4742 { /* Yes, we've read in another operand. */
4743 unsigned int operand_ok
;
4744 this_operand
= i
.operands
++;
4745 if (i
.operands
> MAX_OPERANDS
)
4747 as_bad (_("spurious operands; (%d operands/instruction max)"),
4751 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4752 /* Now parse operand adding info to 'i' as we go along. */
4753 END_STRING_AND_SAVE (l
);
4755 if (i
.mem_operands
> 1)
4757 as_bad (_("too many memory references for `%s'"),
4764 i386_intel_operand (token_start
,
4765 intel_float_operand (mnemonic
));
4767 operand_ok
= i386_att_operand (token_start
);
4769 RESTORE_END_STRING (l
);
4775 if (expecting_operand
)
4777 expecting_operand_after_comma
:
4778 as_bad (_("expecting operand after ','; got nothing"));
4783 as_bad (_("expecting operand before ','; got nothing"));
4788 /* Now *l must be either ',' or END_OF_INSN. */
4791 if (*++l
== END_OF_INSN
)
4793 /* Just skip it, if it's \n complain. */
4794 goto expecting_operand_after_comma
;
4796 expecting_operand
= 1;
4803 swap_2_operands (int xchg1
, int xchg2
)
4805 union i386_op temp_op
;
4806 i386_operand_type temp_type
;
4807 unsigned int temp_flags
;
4808 enum bfd_reloc_code_real temp_reloc
;
4810 temp_type
= i
.types
[xchg2
];
4811 i
.types
[xchg2
] = i
.types
[xchg1
];
4812 i
.types
[xchg1
] = temp_type
;
4814 temp_flags
= i
.flags
[xchg2
];
4815 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4816 i
.flags
[xchg1
] = temp_flags
;
4818 temp_op
= i
.op
[xchg2
];
4819 i
.op
[xchg2
] = i
.op
[xchg1
];
4820 i
.op
[xchg1
] = temp_op
;
4822 temp_reloc
= i
.reloc
[xchg2
];
4823 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4824 i
.reloc
[xchg1
] = temp_reloc
;
4828 if (i
.mask
->operand
== xchg1
)
4829 i
.mask
->operand
= xchg2
;
4830 else if (i
.mask
->operand
== xchg2
)
4831 i
.mask
->operand
= xchg1
;
4835 if (i
.broadcast
->operand
== xchg1
)
4836 i
.broadcast
->operand
= xchg2
;
4837 else if (i
.broadcast
->operand
== xchg2
)
4838 i
.broadcast
->operand
= xchg1
;
4842 if (i
.rounding
->operand
== xchg1
)
4843 i
.rounding
->operand
= xchg2
;
4844 else if (i
.rounding
->operand
== xchg2
)
4845 i
.rounding
->operand
= xchg1
;
4850 swap_operands (void)
4856 swap_2_operands (1, i
.operands
- 2);
4860 swap_2_operands (0, i
.operands
- 1);
4866 if (i
.mem_operands
== 2)
4868 const seg_entry
*temp_seg
;
4869 temp_seg
= i
.seg
[0];
4870 i
.seg
[0] = i
.seg
[1];
4871 i
.seg
[1] = temp_seg
;
4875 /* Try to ensure constant immediates are represented in the smallest
4880 char guess_suffix
= 0;
4884 guess_suffix
= i
.suffix
;
4885 else if (i
.reg_operands
)
4887 /* Figure out a suffix from the last register operand specified.
4888 We can't do this properly yet, ie. excluding InOutPortReg,
4889 but the following works for instructions with immediates.
4890 In any case, we can't set i.suffix yet. */
4891 for (op
= i
.operands
; --op
>= 0;)
4892 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4894 guess_suffix
= BYTE_MNEM_SUFFIX
;
4897 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4899 guess_suffix
= WORD_MNEM_SUFFIX
;
4902 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4904 guess_suffix
= LONG_MNEM_SUFFIX
;
4907 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4909 guess_suffix
= QWORD_MNEM_SUFFIX
;
4913 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4914 guess_suffix
= WORD_MNEM_SUFFIX
;
4916 for (op
= i
.operands
; --op
>= 0;)
4917 if (operand_type_check (i
.types
[op
], imm
))
4919 switch (i
.op
[op
].imms
->X_op
)
4922 /* If a suffix is given, this operand may be shortened. */
4923 switch (guess_suffix
)
4925 case LONG_MNEM_SUFFIX
:
4926 i
.types
[op
].bitfield
.imm32
= 1;
4927 i
.types
[op
].bitfield
.imm64
= 1;
4929 case WORD_MNEM_SUFFIX
:
4930 i
.types
[op
].bitfield
.imm16
= 1;
4931 i
.types
[op
].bitfield
.imm32
= 1;
4932 i
.types
[op
].bitfield
.imm32s
= 1;
4933 i
.types
[op
].bitfield
.imm64
= 1;
4935 case BYTE_MNEM_SUFFIX
:
4936 i
.types
[op
].bitfield
.imm8
= 1;
4937 i
.types
[op
].bitfield
.imm8s
= 1;
4938 i
.types
[op
].bitfield
.imm16
= 1;
4939 i
.types
[op
].bitfield
.imm32
= 1;
4940 i
.types
[op
].bitfield
.imm32s
= 1;
4941 i
.types
[op
].bitfield
.imm64
= 1;
4945 /* If this operand is at most 16 bits, convert it
4946 to a signed 16 bit number before trying to see
4947 whether it will fit in an even smaller size.
4948 This allows a 16-bit operand such as $0xffe0 to
4949 be recognised as within Imm8S range. */
4950 if ((i
.types
[op
].bitfield
.imm16
)
4951 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4953 i
.op
[op
].imms
->X_add_number
=
4954 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4957 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4958 if ((i
.types
[op
].bitfield
.imm32
)
4959 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4962 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4963 ^ ((offsetT
) 1 << 31))
4964 - ((offsetT
) 1 << 31));
4968 = operand_type_or (i
.types
[op
],
4969 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4971 /* We must avoid matching of Imm32 templates when 64bit
4972 only immediate is available. */
4973 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4974 i
.types
[op
].bitfield
.imm32
= 0;
4981 /* Symbols and expressions. */
4983 /* Convert symbolic operand to proper sizes for matching, but don't
4984 prevent matching a set of insns that only supports sizes other
4985 than those matching the insn suffix. */
4987 i386_operand_type mask
, allowed
;
4988 const insn_template
*t
;
4990 operand_type_set (&mask
, 0);
4991 operand_type_set (&allowed
, 0);
4993 for (t
= current_templates
->start
;
4994 t
< current_templates
->end
;
4996 allowed
= operand_type_or (allowed
,
4997 t
->operand_types
[op
]);
4998 switch (guess_suffix
)
5000 case QWORD_MNEM_SUFFIX
:
5001 mask
.bitfield
.imm64
= 1;
5002 mask
.bitfield
.imm32s
= 1;
5004 case LONG_MNEM_SUFFIX
:
5005 mask
.bitfield
.imm32
= 1;
5007 case WORD_MNEM_SUFFIX
:
5008 mask
.bitfield
.imm16
= 1;
5010 case BYTE_MNEM_SUFFIX
:
5011 mask
.bitfield
.imm8
= 1;
5016 allowed
= operand_type_and (mask
, allowed
);
5017 if (!operand_type_all_zero (&allowed
))
5018 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5025 /* Try to use the smallest displacement type too. */
5027 optimize_disp (void)
5031 for (op
= i
.operands
; --op
>= 0;)
5032 if (operand_type_check (i
.types
[op
], disp
))
5034 if (i
.op
[op
].disps
->X_op
== O_constant
)
5036 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5038 if (i
.types
[op
].bitfield
.disp16
5039 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5041 /* If this operand is at most 16 bits, convert
5042 to a signed 16 bit number and don't use 64bit
5044 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5045 i
.types
[op
].bitfield
.disp64
= 0;
5048 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5049 if (i
.types
[op
].bitfield
.disp32
5050 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5052 /* If this operand is at most 32 bits, convert
5053 to a signed 32 bit number and don't use 64bit
5055 op_disp
&= (((offsetT
) 2 << 31) - 1);
5056 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5057 i
.types
[op
].bitfield
.disp64
= 0;
5060 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5062 i
.types
[op
].bitfield
.disp8
= 0;
5063 i
.types
[op
].bitfield
.disp16
= 0;
5064 i
.types
[op
].bitfield
.disp32
= 0;
5065 i
.types
[op
].bitfield
.disp32s
= 0;
5066 i
.types
[op
].bitfield
.disp64
= 0;
5070 else if (flag_code
== CODE_64BIT
)
5072 if (fits_in_signed_long (op_disp
))
5074 i
.types
[op
].bitfield
.disp64
= 0;
5075 i
.types
[op
].bitfield
.disp32s
= 1;
5077 if (i
.prefix
[ADDR_PREFIX
]
5078 && fits_in_unsigned_long (op_disp
))
5079 i
.types
[op
].bitfield
.disp32
= 1;
5081 if ((i
.types
[op
].bitfield
.disp32
5082 || i
.types
[op
].bitfield
.disp32s
5083 || i
.types
[op
].bitfield
.disp16
)
5084 && fits_in_disp8 (op_disp
))
5085 i
.types
[op
].bitfield
.disp8
= 1;
5087 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5088 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5090 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5091 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5092 i
.types
[op
].bitfield
.disp8
= 0;
5093 i
.types
[op
].bitfield
.disp16
= 0;
5094 i
.types
[op
].bitfield
.disp32
= 0;
5095 i
.types
[op
].bitfield
.disp32s
= 0;
5096 i
.types
[op
].bitfield
.disp64
= 0;
5099 /* We only support 64bit displacement on constants. */
5100 i
.types
[op
].bitfield
.disp64
= 0;
5104 /* Return 1 if there is a match in broadcast bytes between operand
5105 GIVEN and instruction template T. */
5108 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5110 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5111 && i
.types
[given
].bitfield
.byte
)
5112 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5113 && i
.types
[given
].bitfield
.word
)
5114 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5115 && i
.types
[given
].bitfield
.dword
)
5116 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5117 && i
.types
[given
].bitfield
.qword
));
5120 /* Check if operands are valid for the instruction. */
5123 check_VecOperands (const insn_template
*t
)
5127 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5129 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5130 any one operand are implicity requiring AVX512VL support if the actual
5131 operand size is YMMword or XMMword. Since this function runs after
5132 template matching, there's no need to check for YMMword/XMMword in
5134 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5135 if (!cpu_flags_all_zero (&cpu
)
5136 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5137 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5139 for (op
= 0; op
< t
->operands
; ++op
)
5141 if (t
->operand_types
[op
].bitfield
.zmmword
5142 && (i
.types
[op
].bitfield
.ymmword
5143 || i
.types
[op
].bitfield
.xmmword
))
5145 i
.error
= unsupported
;
5151 /* Without VSIB byte, we can't have a vector register for index. */
5152 if (!t
->opcode_modifier
.vecsib
5154 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5155 || i
.index_reg
->reg_type
.bitfield
.ymmword
5156 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5158 i
.error
= unsupported_vector_index_register
;
5162 /* Check if default mask is allowed. */
5163 if (t
->opcode_modifier
.nodefmask
5164 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5166 i
.error
= no_default_mask
;
5170 /* For VSIB byte, we need a vector register for index, and all vector
5171 registers must be distinct. */
5172 if (t
->opcode_modifier
.vecsib
)
5175 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5176 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5177 || (t
->opcode_modifier
.vecsib
== VecSIB256
5178 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5179 || (t
->opcode_modifier
.vecsib
== VecSIB512
5180 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5182 i
.error
= invalid_vsib_address
;
5186 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5187 if (i
.reg_operands
== 2 && !i
.mask
)
5189 gas_assert (i
.types
[0].bitfield
.regsimd
);
5190 gas_assert (i
.types
[0].bitfield
.xmmword
5191 || i
.types
[0].bitfield
.ymmword
);
5192 gas_assert (i
.types
[2].bitfield
.regsimd
);
5193 gas_assert (i
.types
[2].bitfield
.xmmword
5194 || i
.types
[2].bitfield
.ymmword
);
5195 if (operand_check
== check_none
)
5197 if (register_number (i
.op
[0].regs
)
5198 != register_number (i
.index_reg
)
5199 && register_number (i
.op
[2].regs
)
5200 != register_number (i
.index_reg
)
5201 && register_number (i
.op
[0].regs
)
5202 != register_number (i
.op
[2].regs
))
5204 if (operand_check
== check_error
)
5206 i
.error
= invalid_vector_register_set
;
5209 as_warn (_("mask, index, and destination registers should be distinct"));
5211 else if (i
.reg_operands
== 1 && i
.mask
)
5213 if (i
.types
[1].bitfield
.regsimd
5214 && (i
.types
[1].bitfield
.xmmword
5215 || i
.types
[1].bitfield
.ymmword
5216 || i
.types
[1].bitfield
.zmmword
)
5217 && (register_number (i
.op
[1].regs
)
5218 == register_number (i
.index_reg
)))
5220 if (operand_check
== check_error
)
5222 i
.error
= invalid_vector_register_set
;
5225 if (operand_check
!= check_none
)
5226 as_warn (_("index and destination registers should be distinct"));
5231 /* Check if broadcast is supported by the instruction and is applied
5232 to the memory operand. */
5235 i386_operand_type type
, overlap
;
5237 /* Check if specified broadcast is supported in this instruction,
5238 and its broadcast bytes match the memory operand. */
5239 op
= i
.broadcast
->operand
;
5240 if (!t
->opcode_modifier
.broadcast
5241 || !(i
.flags
[op
] & Operand_Mem
)
5242 || (!i
.types
[op
].bitfield
.unspecified
5243 && !match_broadcast_size (t
, op
)))
5246 i
.error
= unsupported_broadcast
;
5250 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5251 * i
.broadcast
->type
);
5252 operand_type_set (&type
, 0);
5253 switch (i
.broadcast
->bytes
)
5256 type
.bitfield
.word
= 1;
5259 type
.bitfield
.dword
= 1;
5262 type
.bitfield
.qword
= 1;
5265 type
.bitfield
.xmmword
= 1;
5268 type
.bitfield
.ymmword
= 1;
5271 type
.bitfield
.zmmword
= 1;
5277 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5278 if (operand_type_all_zero (&overlap
))
5281 if (t
->opcode_modifier
.checkregsize
)
5285 type
.bitfield
.baseindex
= 1;
5286 for (j
= 0; j
< i
.operands
; ++j
)
5289 && !operand_type_register_match(i
.types
[j
],
5290 t
->operand_types
[j
],
5292 t
->operand_types
[op
]))
5297 /* If broadcast is supported in this instruction, we need to check if
5298 operand of one-element size isn't specified without broadcast. */
5299 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5301 /* Find memory operand. */
5302 for (op
= 0; op
< i
.operands
; op
++)
5303 if (operand_type_check (i
.types
[op
], anymem
))
5305 gas_assert (op
< i
.operands
);
5306 /* Check size of the memory operand. */
5307 if (match_broadcast_size (t
, op
))
5309 i
.error
= broadcast_needed
;
5314 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5316 /* Check if requested masking is supported. */
5319 switch (t
->opcode_modifier
.masking
)
5323 case MERGING_MASKING
:
5324 if (i
.mask
->zeroing
)
5327 i
.error
= unsupported_masking
;
5331 case DYNAMIC_MASKING
:
5332 /* Memory destinations allow only merging masking. */
5333 if (i
.mask
->zeroing
&& i
.mem_operands
)
5335 /* Find memory operand. */
5336 for (op
= 0; op
< i
.operands
; op
++)
5337 if (i
.flags
[op
] & Operand_Mem
)
5339 gas_assert (op
< i
.operands
);
5340 if (op
== i
.operands
- 1)
5342 i
.error
= unsupported_masking
;
5352 /* Check if masking is applied to dest operand. */
5353 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5355 i
.error
= mask_not_on_destination
;
5362 if ((i
.rounding
->type
!= saeonly
5363 && !t
->opcode_modifier
.staticrounding
)
5364 || (i
.rounding
->type
== saeonly
5365 && (t
->opcode_modifier
.staticrounding
5366 || !t
->opcode_modifier
.sae
)))
5368 i
.error
= unsupported_rc_sae
;
5371 /* If the instruction has several immediate operands and one of
5372 them is rounding, the rounding operand should be the last
5373 immediate operand. */
5374 if (i
.imm_operands
> 1
5375 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5377 i
.error
= rc_sae_operand_not_last_imm
;
5382 /* Check vector Disp8 operand. */
5383 if (t
->opcode_modifier
.disp8memshift
5384 && i
.disp_encoding
!= disp_encoding_32bit
)
5387 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5388 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5389 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5392 const i386_operand_type
*type
= NULL
;
5395 for (op
= 0; op
< i
.operands
; op
++)
5396 if (operand_type_check (i
.types
[op
], anymem
))
5398 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5399 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5400 else if (t
->operand_types
[op
].bitfield
.xmmword
5401 + t
->operand_types
[op
].bitfield
.ymmword
5402 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5403 type
= &t
->operand_types
[op
];
5404 else if (!i
.types
[op
].bitfield
.unspecified
)
5405 type
= &i
.types
[op
];
5407 else if (i
.types
[op
].bitfield
.regsimd
5408 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5410 if (i
.types
[op
].bitfield
.zmmword
)
5412 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5414 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5420 if (type
->bitfield
.zmmword
)
5422 else if (type
->bitfield
.ymmword
)
5424 else if (type
->bitfield
.xmmword
)
5428 /* For the check in fits_in_disp8(). */
5429 if (i
.memshift
== 0)
5433 for (op
= 0; op
< i
.operands
; op
++)
5434 if (operand_type_check (i
.types
[op
], disp
)
5435 && i
.op
[op
].disps
->X_op
== O_constant
)
5437 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5439 i
.types
[op
].bitfield
.disp8
= 1;
5442 i
.types
[op
].bitfield
.disp8
= 0;
5451 /* Check if operands are valid for the instruction. Update VEX
5455 VEX_check_operands (const insn_template
*t
)
5457 if (i
.vec_encoding
== vex_encoding_evex
)
5459 /* This instruction must be encoded with EVEX prefix. */
5460 if (!is_evex_encoding (t
))
5462 i
.error
= unsupported
;
5468 if (!t
->opcode_modifier
.vex
)
5470 /* This instruction template doesn't have VEX prefix. */
5471 if (i
.vec_encoding
!= vex_encoding_default
)
5473 i
.error
= unsupported
;
5479 /* Only check VEX_Imm4, which must be the first operand. */
5480 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5482 if (i
.op
[0].imms
->X_op
!= O_constant
5483 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5489 /* Turn off Imm8 so that update_imm won't complain. */
5490 i
.types
[0] = vec_imm4
;
5496 static const insn_template
*
5497 match_template (char mnem_suffix
)
5499 /* Points to template once we've found it. */
5500 const insn_template
*t
;
5501 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5502 i386_operand_type overlap4
;
5503 unsigned int found_reverse_match
;
5504 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5505 i386_operand_type operand_types
[MAX_OPERANDS
];
5506 int addr_prefix_disp
;
5508 unsigned int found_cpu_match
, size_match
;
5509 unsigned int check_register
;
5510 enum i386_error specific_error
= 0;
5512 #if MAX_OPERANDS != 5
5513 # error "MAX_OPERANDS must be 5."
5516 found_reverse_match
= 0;
5517 addr_prefix_disp
= -1;
5519 memset (&suffix_check
, 0, sizeof (suffix_check
));
5520 if (intel_syntax
&& i
.broadcast
)
5522 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5523 suffix_check
.no_bsuf
= 1;
5524 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5525 suffix_check
.no_wsuf
= 1;
5526 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5527 suffix_check
.no_ssuf
= 1;
5528 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5529 suffix_check
.no_lsuf
= 1;
5530 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5531 suffix_check
.no_qsuf
= 1;
5532 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5533 suffix_check
.no_ldsuf
= 1;
5535 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5538 switch (mnem_suffix
)
5540 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5541 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5542 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5543 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5544 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5548 /* Must have right number of operands. */
5549 i
.error
= number_of_operands_mismatch
;
5551 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5553 addr_prefix_disp
= -1;
5554 found_reverse_match
= 0;
5556 if (i
.operands
!= t
->operands
)
5559 /* Check processor support. */
5560 i
.error
= unsupported
;
5561 found_cpu_match
= (cpu_flags_match (t
)
5562 == CPU_FLAGS_PERFECT_MATCH
);
5563 if (!found_cpu_match
)
5566 /* Check AT&T mnemonic. */
5567 i
.error
= unsupported_with_intel_mnemonic
;
5568 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5571 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5572 i
.error
= unsupported_syntax
;
5573 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5574 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5575 || (intel64
&& t
->opcode_modifier
.amd64
)
5576 || (!intel64
&& t
->opcode_modifier
.intel64
))
5579 /* Check the suffix, except for some instructions in intel mode. */
5580 i
.error
= invalid_instruction_suffix
;
5581 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5582 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5583 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5584 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5585 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5586 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5587 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5589 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5590 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5591 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5592 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5593 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5594 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5595 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5598 size_match
= operand_size_match (t
);
5602 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5603 operand_types
[j
] = t
->operand_types
[j
];
5605 /* In general, don't allow 64-bit operands in 32-bit mode. */
5606 if (i
.suffix
== QWORD_MNEM_SUFFIX
5607 && flag_code
!= CODE_64BIT
5609 ? (!t
->opcode_modifier
.ignoresize
5610 && !t
->opcode_modifier
.broadcast
5611 && !intel_float_operand (t
->name
))
5612 : intel_float_operand (t
->name
) != 2)
5613 && ((!operand_types
[0].bitfield
.regmmx
5614 && !operand_types
[0].bitfield
.regsimd
)
5615 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5616 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5617 && (t
->base_opcode
!= 0x0fc7
5618 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5621 /* In general, don't allow 32-bit operands on pre-386. */
5622 else if (i
.suffix
== LONG_MNEM_SUFFIX
5623 && !cpu_arch_flags
.bitfield
.cpui386
5625 ? (!t
->opcode_modifier
.ignoresize
5626 && !intel_float_operand (t
->name
))
5627 : intel_float_operand (t
->name
) != 2)
5628 && ((!operand_types
[0].bitfield
.regmmx
5629 && !operand_types
[0].bitfield
.regsimd
)
5630 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5631 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5634 /* Do not verify operands when there are none. */
5638 /* We've found a match; break out of loop. */
5642 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5643 into Disp32/Disp16/Disp32 operand. */
5644 if (i
.prefix
[ADDR_PREFIX
] != 0)
5646 /* There should be only one Disp operand. */
5650 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5652 if (operand_types
[j
].bitfield
.disp16
)
5654 addr_prefix_disp
= j
;
5655 operand_types
[j
].bitfield
.disp32
= 1;
5656 operand_types
[j
].bitfield
.disp16
= 0;
5662 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5664 if (operand_types
[j
].bitfield
.disp32
)
5666 addr_prefix_disp
= j
;
5667 operand_types
[j
].bitfield
.disp32
= 0;
5668 operand_types
[j
].bitfield
.disp16
= 1;
5674 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5676 if (operand_types
[j
].bitfield
.disp64
)
5678 addr_prefix_disp
= j
;
5679 operand_types
[j
].bitfield
.disp64
= 0;
5680 operand_types
[j
].bitfield
.disp32
= 1;
5688 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5689 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5692 /* We check register size if needed. */
5693 if (t
->opcode_modifier
.checkregsize
)
5695 check_register
= (1 << t
->operands
) - 1;
5697 check_register
&= ~(1 << i
.broadcast
->operand
);
5702 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5703 switch (t
->operands
)
5706 if (!operand_type_match (overlap0
, i
.types
[0]))
5710 /* xchg %eax, %eax is a special case. It is an alias for nop
5711 only in 32bit mode and we can use opcode 0x90. In 64bit
5712 mode, we can't use 0x90 for xchg %eax, %eax since it should
5713 zero-extend %eax to %rax. */
5714 if (flag_code
== CODE_64BIT
5715 && t
->base_opcode
== 0x90
5716 && operand_type_equal (&i
.types
[0], &acc32
)
5717 && operand_type_equal (&i
.types
[1], &acc32
))
5719 /* xrelease mov %eax, <disp> is another special case. It must not
5720 match the accumulator-only encoding of mov. */
5721 if (flag_code
!= CODE_64BIT
5723 && t
->base_opcode
== 0xa0
5724 && i
.types
[0].bitfield
.acc
5725 && operand_type_check (i
.types
[1], anymem
))
5730 if (!(size_match
& MATCH_STRAIGHT
))
5732 /* Reverse direction of operands if swapping is possible in the first
5733 place (operands need to be symmetric) and
5734 - the load form is requested, and the template is a store form,
5735 - the store form is requested, and the template is a load form,
5736 - the non-default (swapped) form is requested. */
5737 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5738 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5739 && !operand_type_all_zero (&overlap1
))
5740 switch (i
.dir_encoding
)
5742 case dir_encoding_load
:
5743 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5744 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5748 case dir_encoding_store
:
5749 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5750 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5754 case dir_encoding_swap
:
5757 case dir_encoding_default
:
5760 /* If we want store form, we skip the current load. */
5761 if ((i
.dir_encoding
== dir_encoding_store
5762 || i
.dir_encoding
== dir_encoding_swap
)
5763 && i
.mem_operands
== 0
5764 && t
->opcode_modifier
.load
)
5769 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5770 if (!operand_type_match (overlap0
, i
.types
[0])
5771 || !operand_type_match (overlap1
, i
.types
[1])
5772 || ((check_register
& 3) == 3
5773 && !operand_type_register_match (i
.types
[0],
5778 /* Check if other direction is valid ... */
5779 if (!t
->opcode_modifier
.d
)
5783 if (!(size_match
& MATCH_REVERSE
))
5785 /* Try reversing direction of operands. */
5786 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5787 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5788 if (!operand_type_match (overlap0
, i
.types
[0])
5789 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5791 && !operand_type_register_match (i
.types
[0],
5792 operand_types
[i
.operands
- 1],
5793 i
.types
[i
.operands
- 1],
5796 /* Does not match either direction. */
5799 /* found_reverse_match holds which of D or FloatR
5801 if (!t
->opcode_modifier
.d
)
5802 found_reverse_match
= 0;
5803 else if (operand_types
[0].bitfield
.tbyte
)
5804 found_reverse_match
= Opcode_FloatD
;
5805 else if (operand_types
[0].bitfield
.xmmword
5806 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5807 || operand_types
[0].bitfield
.regmmx
5808 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5809 || is_any_vex_encoding(t
))
5810 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5811 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5813 found_reverse_match
= Opcode_D
;
5814 if (t
->opcode_modifier
.floatr
)
5815 found_reverse_match
|= Opcode_FloatR
;
5819 /* Found a forward 2 operand match here. */
5820 switch (t
->operands
)
5823 overlap4
= operand_type_and (i
.types
[4],
5827 overlap3
= operand_type_and (i
.types
[3],
5831 overlap2
= operand_type_and (i
.types
[2],
5836 switch (t
->operands
)
5839 if (!operand_type_match (overlap4
, i
.types
[4])
5840 || !operand_type_register_match (i
.types
[3],
5847 if (!operand_type_match (overlap3
, i
.types
[3])
5848 || ((check_register
& 0xa) == 0xa
5849 && !operand_type_register_match (i
.types
[1],
5853 || ((check_register
& 0xc) == 0xc
5854 && !operand_type_register_match (i
.types
[2],
5861 /* Here we make use of the fact that there are no
5862 reverse match 3 operand instructions. */
5863 if (!operand_type_match (overlap2
, i
.types
[2])
5864 || ((check_register
& 5) == 5
5865 && !operand_type_register_match (i
.types
[0],
5869 || ((check_register
& 6) == 6
5870 && !operand_type_register_match (i
.types
[1],
5878 /* Found either forward/reverse 2, 3 or 4 operand match here:
5879 slip through to break. */
5881 if (!found_cpu_match
)
5884 /* Check if vector and VEX operands are valid. */
5885 if (check_VecOperands (t
) || VEX_check_operands (t
))
5887 specific_error
= i
.error
;
5891 /* We've found a match; break out of loop. */
5895 if (t
== current_templates
->end
)
5897 /* We found no match. */
5898 const char *err_msg
;
5899 switch (specific_error
? specific_error
: i
.error
)
5903 case operand_size_mismatch
:
5904 err_msg
= _("operand size mismatch");
5906 case operand_type_mismatch
:
5907 err_msg
= _("operand type mismatch");
5909 case register_type_mismatch
:
5910 err_msg
= _("register type mismatch");
5912 case number_of_operands_mismatch
:
5913 err_msg
= _("number of operands mismatch");
5915 case invalid_instruction_suffix
:
5916 err_msg
= _("invalid instruction suffix");
5919 err_msg
= _("constant doesn't fit in 4 bits");
5921 case unsupported_with_intel_mnemonic
:
5922 err_msg
= _("unsupported with Intel mnemonic");
5924 case unsupported_syntax
:
5925 err_msg
= _("unsupported syntax");
5928 as_bad (_("unsupported instruction `%s'"),
5929 current_templates
->start
->name
);
5931 case invalid_vsib_address
:
5932 err_msg
= _("invalid VSIB address");
5934 case invalid_vector_register_set
:
5935 err_msg
= _("mask, index, and destination registers must be distinct");
5937 case unsupported_vector_index_register
:
5938 err_msg
= _("unsupported vector index register");
5940 case unsupported_broadcast
:
5941 err_msg
= _("unsupported broadcast");
5943 case broadcast_needed
:
5944 err_msg
= _("broadcast is needed for operand of such type");
5946 case unsupported_masking
:
5947 err_msg
= _("unsupported masking");
5949 case mask_not_on_destination
:
5950 err_msg
= _("mask not on destination operand");
5952 case no_default_mask
:
5953 err_msg
= _("default mask isn't allowed");
5955 case unsupported_rc_sae
:
5956 err_msg
= _("unsupported static rounding/sae");
5958 case rc_sae_operand_not_last_imm
:
5960 err_msg
= _("RC/SAE operand must precede immediate operands");
5962 err_msg
= _("RC/SAE operand must follow immediate operands");
5964 case invalid_register_operand
:
5965 err_msg
= _("invalid register operand");
5968 as_bad (_("%s for `%s'"), err_msg
,
5969 current_templates
->start
->name
);
5973 if (!quiet_warnings
)
5976 && (i
.types
[0].bitfield
.jumpabsolute
5977 != operand_types
[0].bitfield
.jumpabsolute
))
5979 as_warn (_("indirect %s without `*'"), t
->name
);
5982 if (t
->opcode_modifier
.isprefix
5983 && t
->opcode_modifier
.ignoresize
)
5985 /* Warn them that a data or address size prefix doesn't
5986 affect assembly of the next line of code. */
5987 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5991 /* Copy the template we found. */
5994 if (addr_prefix_disp
!= -1)
5995 i
.tm
.operand_types
[addr_prefix_disp
]
5996 = operand_types
[addr_prefix_disp
];
5998 if (found_reverse_match
)
6000 /* If we found a reverse match we must alter the opcode
6001 direction bit. found_reverse_match holds bits to change
6002 (different for int & float insns). */
6004 i
.tm
.base_opcode
^= found_reverse_match
;
6006 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6007 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6016 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6017 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6019 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6021 as_bad (_("`%s' operand %d must use `%ses' segment"),
6027 /* There's only ever one segment override allowed per instruction.
6028 This instruction possibly has a legal segment override on the
6029 second operand, so copy the segment to where non-string
6030 instructions store it, allowing common code. */
6031 i
.seg
[0] = i
.seg
[1];
6033 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6035 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6037 as_bad (_("`%s' operand %d must use `%ses' segment"),
6048 process_suffix (void)
6050 /* If matched instruction specifies an explicit instruction mnemonic
6052 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6053 i
.suffix
= WORD_MNEM_SUFFIX
;
6054 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6055 i
.suffix
= LONG_MNEM_SUFFIX
;
6056 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6057 i
.suffix
= QWORD_MNEM_SUFFIX
;
6058 else if (i
.reg_operands
)
6060 /* If there's no instruction mnemonic suffix we try to invent one
6061 based on register operands. */
6064 /* We take i.suffix from the last register operand specified,
6065 Destination register type is more significant than source
6066 register type. crc32 in SSE4.2 prefers source register
6068 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6070 if (i
.types
[0].bitfield
.byte
)
6071 i
.suffix
= BYTE_MNEM_SUFFIX
;
6072 else if (i
.types
[0].bitfield
.word
)
6073 i
.suffix
= WORD_MNEM_SUFFIX
;
6074 else if (i
.types
[0].bitfield
.dword
)
6075 i
.suffix
= LONG_MNEM_SUFFIX
;
6076 else if (i
.types
[0].bitfield
.qword
)
6077 i
.suffix
= QWORD_MNEM_SUFFIX
;
6084 if (i
.tm
.base_opcode
== 0xf20f38f0)
6086 /* We have to know the operand size for crc32. */
6087 as_bad (_("ambiguous memory operand size for `%s`"),
6092 for (op
= i
.operands
; --op
>= 0;)
6093 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6094 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6096 if (!i
.types
[op
].bitfield
.reg
)
6098 if (i
.types
[op
].bitfield
.byte
)
6099 i
.suffix
= BYTE_MNEM_SUFFIX
;
6100 else if (i
.types
[op
].bitfield
.word
)
6101 i
.suffix
= WORD_MNEM_SUFFIX
;
6102 else if (i
.types
[op
].bitfield
.dword
)
6103 i
.suffix
= LONG_MNEM_SUFFIX
;
6104 else if (i
.types
[op
].bitfield
.qword
)
6105 i
.suffix
= QWORD_MNEM_SUFFIX
;
6112 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6115 && i
.tm
.opcode_modifier
.ignoresize
6116 && i
.tm
.opcode_modifier
.no_bsuf
)
6118 else if (!check_byte_reg ())
6121 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6124 && i
.tm
.opcode_modifier
.ignoresize
6125 && i
.tm
.opcode_modifier
.no_lsuf
6126 && !i
.tm
.opcode_modifier
.todword
6127 && !i
.tm
.opcode_modifier
.toqword
)
6129 else if (!check_long_reg ())
6132 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6135 && i
.tm
.opcode_modifier
.ignoresize
6136 && i
.tm
.opcode_modifier
.no_qsuf
6137 && !i
.tm
.opcode_modifier
.todword
6138 && !i
.tm
.opcode_modifier
.toqword
)
6140 else if (!check_qword_reg ())
6143 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6146 && i
.tm
.opcode_modifier
.ignoresize
6147 && i
.tm
.opcode_modifier
.no_wsuf
)
6149 else if (!check_word_reg ())
6152 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6153 /* Do nothing if the instruction is going to ignore the prefix. */
6158 else if (i
.tm
.opcode_modifier
.defaultsize
6160 /* exclude fldenv/frstor/fsave/fstenv */
6161 && i
.tm
.opcode_modifier
.no_ssuf
)
6163 i
.suffix
= stackop_size
;
6165 else if (intel_syntax
6167 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6168 || i
.tm
.opcode_modifier
.jumpbyte
6169 || i
.tm
.opcode_modifier
.jumpintersegment
6170 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6171 && i
.tm
.extension_opcode
<= 3)))
6176 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6178 i
.suffix
= QWORD_MNEM_SUFFIX
;
6183 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6184 i
.suffix
= LONG_MNEM_SUFFIX
;
6187 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6188 i
.suffix
= WORD_MNEM_SUFFIX
;
6197 if (i
.tm
.opcode_modifier
.w
)
6199 as_bad (_("no instruction mnemonic suffix given and "
6200 "no register operands; can't size instruction"));
6206 unsigned int suffixes
;
6208 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6209 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6211 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6213 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6215 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6217 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6220 /* There are more than suffix matches. */
6221 if (i
.tm
.opcode_modifier
.w
6222 || ((suffixes
& (suffixes
- 1))
6223 && !i
.tm
.opcode_modifier
.defaultsize
6224 && !i
.tm
.opcode_modifier
.ignoresize
))
6226 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6232 /* Change the opcode based on the operand size given by i.suffix. */
6235 /* Size floating point instruction. */
6236 case LONG_MNEM_SUFFIX
:
6237 if (i
.tm
.opcode_modifier
.floatmf
)
6239 i
.tm
.base_opcode
^= 4;
6243 case WORD_MNEM_SUFFIX
:
6244 case QWORD_MNEM_SUFFIX
:
6245 /* It's not a byte, select word/dword operation. */
6246 if (i
.tm
.opcode_modifier
.w
)
6248 if (i
.tm
.opcode_modifier
.shortform
)
6249 i
.tm
.base_opcode
|= 8;
6251 i
.tm
.base_opcode
|= 1;
6254 case SHORT_MNEM_SUFFIX
:
6255 /* Now select between word & dword operations via the operand
6256 size prefix, except for instructions that will ignore this
6258 if (i
.reg_operands
> 0
6259 && i
.types
[0].bitfield
.reg
6260 && i
.tm
.opcode_modifier
.addrprefixopreg
6261 && (i
.tm
.opcode_modifier
.immext
6262 || i
.operands
== 1))
6264 /* The address size override prefix changes the size of the
6266 if ((flag_code
== CODE_32BIT
6267 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6268 || (flag_code
!= CODE_32BIT
6269 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6270 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6273 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6274 && !i
.tm
.opcode_modifier
.ignoresize
6275 && !i
.tm
.opcode_modifier
.floatmf
6276 && !i
.tm
.opcode_modifier
.vex
6277 && !i
.tm
.opcode_modifier
.vexopcode
6278 && !is_evex_encoding (&i
.tm
)
6279 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6280 || (flag_code
== CODE_64BIT
6281 && i
.tm
.opcode_modifier
.jumpbyte
)))
6283 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6285 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6286 prefix
= ADDR_PREFIX_OPCODE
;
6288 if (!add_prefix (prefix
))
6292 /* Set mode64 for an operand. */
6293 if (i
.suffix
== QWORD_MNEM_SUFFIX
6294 && flag_code
== CODE_64BIT
6295 && !i
.tm
.opcode_modifier
.norex64
6296 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6298 && ! (i
.operands
== 2
6299 && i
.tm
.base_opcode
== 0x90
6300 && i
.tm
.extension_opcode
== None
6301 && operand_type_equal (&i
.types
[0], &acc64
)
6302 && operand_type_equal (&i
.types
[1], &acc64
)))
6308 if (i
.reg_operands
!= 0
6310 && i
.tm
.opcode_modifier
.addrprefixopreg
6311 && !i
.tm
.opcode_modifier
.immext
)
6313 /* Check invalid register operand when the address size override
6314 prefix changes the size of register operands. */
6316 enum { need_word
, need_dword
, need_qword
} need
;
6318 if (flag_code
== CODE_32BIT
)
6319 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6322 if (i
.prefix
[ADDR_PREFIX
])
6325 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6328 for (op
= 0; op
< i
.operands
; op
++)
6329 if (i
.types
[op
].bitfield
.reg
6330 && ((need
== need_word
6331 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6332 || (need
== need_dword
6333 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6334 || (need
== need_qword
6335 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6337 as_bad (_("invalid register operand size for `%s'"),
6347 check_byte_reg (void)
6351 for (op
= i
.operands
; --op
>= 0;)
6353 /* Skip non-register operands. */
6354 if (!i
.types
[op
].bitfield
.reg
)
6357 /* If this is an eight bit register, it's OK. If it's the 16 or
6358 32 bit version of an eight bit register, we will just use the
6359 low portion, and that's OK too. */
6360 if (i
.types
[op
].bitfield
.byte
)
6363 /* I/O port address operands are OK too. */
6364 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6367 /* crc32 doesn't generate this warning. */
6368 if (i
.tm
.base_opcode
== 0xf20f38f0)
6371 if ((i
.types
[op
].bitfield
.word
6372 || i
.types
[op
].bitfield
.dword
6373 || i
.types
[op
].bitfield
.qword
)
6374 && i
.op
[op
].regs
->reg_num
< 4
6375 /* Prohibit these changes in 64bit mode, since the lowering
6376 would be more complicated. */
6377 && flag_code
!= CODE_64BIT
)
6379 #if REGISTER_WARNINGS
6380 if (!quiet_warnings
)
6381 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6383 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6384 ? REGNAM_AL
- REGNAM_AX
6385 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6387 i
.op
[op
].regs
->reg_name
,
6392 /* Any other register is bad. */
6393 if (i
.types
[op
].bitfield
.reg
6394 || i
.types
[op
].bitfield
.regmmx
6395 || i
.types
[op
].bitfield
.regsimd
6396 || i
.types
[op
].bitfield
.sreg2
6397 || i
.types
[op
].bitfield
.sreg3
6398 || i
.types
[op
].bitfield
.control
6399 || i
.types
[op
].bitfield
.debug
6400 || i
.types
[op
].bitfield
.test
)
6402 as_bad (_("`%s%s' not allowed with `%s%c'"),
6404 i
.op
[op
].regs
->reg_name
,
6414 check_long_reg (void)
6418 for (op
= i
.operands
; --op
>= 0;)
6419 /* Skip non-register operands. */
6420 if (!i
.types
[op
].bitfield
.reg
)
6422 /* Reject eight bit registers, except where the template requires
6423 them. (eg. movzb) */
6424 else if (i
.types
[op
].bitfield
.byte
6425 && (i
.tm
.operand_types
[op
].bitfield
.reg
6426 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6427 && (i
.tm
.operand_types
[op
].bitfield
.word
6428 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6430 as_bad (_("`%s%s' not allowed with `%s%c'"),
6432 i
.op
[op
].regs
->reg_name
,
6437 /* Warn if the e prefix on a general reg is missing. */
6438 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6439 && i
.types
[op
].bitfield
.word
6440 && (i
.tm
.operand_types
[op
].bitfield
.reg
6441 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6442 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6444 /* Prohibit these changes in the 64bit mode, since the
6445 lowering is more complicated. */
6446 if (flag_code
== CODE_64BIT
)
6448 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6449 register_prefix
, i
.op
[op
].regs
->reg_name
,
6453 #if REGISTER_WARNINGS
6454 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6456 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6457 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6460 /* Warn if the r prefix on a general reg is present. */
6461 else if (i
.types
[op
].bitfield
.qword
6462 && (i
.tm
.operand_types
[op
].bitfield
.reg
6463 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6464 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6467 && i
.tm
.opcode_modifier
.toqword
6468 && !i
.types
[0].bitfield
.regsimd
)
6470 /* Convert to QWORD. We want REX byte. */
6471 i
.suffix
= QWORD_MNEM_SUFFIX
;
6475 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6476 register_prefix
, i
.op
[op
].regs
->reg_name
,
6485 check_qword_reg (void)
6489 for (op
= i
.operands
; --op
>= 0; )
6490 /* Skip non-register operands. */
6491 if (!i
.types
[op
].bitfield
.reg
)
6493 /* Reject eight bit registers, except where the template requires
6494 them. (eg. movzb) */
6495 else if (i
.types
[op
].bitfield
.byte
6496 && (i
.tm
.operand_types
[op
].bitfield
.reg
6497 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6498 && (i
.tm
.operand_types
[op
].bitfield
.word
6499 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6501 as_bad (_("`%s%s' not allowed with `%s%c'"),
6503 i
.op
[op
].regs
->reg_name
,
6508 /* Warn if the r prefix on a general reg is missing. */
6509 else if ((i
.types
[op
].bitfield
.word
6510 || i
.types
[op
].bitfield
.dword
)
6511 && (i
.tm
.operand_types
[op
].bitfield
.reg
6512 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6513 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6515 /* Prohibit these changes in the 64bit mode, since the
6516 lowering is more complicated. */
6518 && i
.tm
.opcode_modifier
.todword
6519 && !i
.types
[0].bitfield
.regsimd
)
6521 /* Convert to DWORD. We don't want REX byte. */
6522 i
.suffix
= LONG_MNEM_SUFFIX
;
6526 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6527 register_prefix
, i
.op
[op
].regs
->reg_name
,
6536 check_word_reg (void)
6539 for (op
= i
.operands
; --op
>= 0;)
6540 /* Skip non-register operands. */
6541 if (!i
.types
[op
].bitfield
.reg
)
6543 /* Reject eight bit registers, except where the template requires
6544 them. (eg. movzb) */
6545 else if (i
.types
[op
].bitfield
.byte
6546 && (i
.tm
.operand_types
[op
].bitfield
.reg
6547 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6548 && (i
.tm
.operand_types
[op
].bitfield
.word
6549 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6551 as_bad (_("`%s%s' not allowed with `%s%c'"),
6553 i
.op
[op
].regs
->reg_name
,
6558 /* Warn if the e or r prefix on a general reg is present. */
6559 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6560 && (i
.types
[op
].bitfield
.dword
6561 || i
.types
[op
].bitfield
.qword
)
6562 && (i
.tm
.operand_types
[op
].bitfield
.reg
6563 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6564 && i
.tm
.operand_types
[op
].bitfield
.word
)
6566 /* Prohibit these changes in the 64bit mode, since the
6567 lowering is more complicated. */
6568 if (flag_code
== CODE_64BIT
)
6570 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6571 register_prefix
, i
.op
[op
].regs
->reg_name
,
6575 #if REGISTER_WARNINGS
6576 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6578 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6579 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6586 update_imm (unsigned int j
)
6588 i386_operand_type overlap
= i
.types
[j
];
6589 if ((overlap
.bitfield
.imm8
6590 || overlap
.bitfield
.imm8s
6591 || overlap
.bitfield
.imm16
6592 || overlap
.bitfield
.imm32
6593 || overlap
.bitfield
.imm32s
6594 || overlap
.bitfield
.imm64
)
6595 && !operand_type_equal (&overlap
, &imm8
)
6596 && !operand_type_equal (&overlap
, &imm8s
)
6597 && !operand_type_equal (&overlap
, &imm16
)
6598 && !operand_type_equal (&overlap
, &imm32
)
6599 && !operand_type_equal (&overlap
, &imm32s
)
6600 && !operand_type_equal (&overlap
, &imm64
))
6604 i386_operand_type temp
;
6606 operand_type_set (&temp
, 0);
6607 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6609 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6610 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6612 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6613 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6614 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6616 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6617 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6620 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6623 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6624 || operand_type_equal (&overlap
, &imm16_32
)
6625 || operand_type_equal (&overlap
, &imm16_32s
))
6627 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6632 if (!operand_type_equal (&overlap
, &imm8
)
6633 && !operand_type_equal (&overlap
, &imm8s
)
6634 && !operand_type_equal (&overlap
, &imm16
)
6635 && !operand_type_equal (&overlap
, &imm32
)
6636 && !operand_type_equal (&overlap
, &imm32s
)
6637 && !operand_type_equal (&overlap
, &imm64
))
6639 as_bad (_("no instruction mnemonic suffix given; "
6640 "can't determine immediate size"));
6644 i
.types
[j
] = overlap
;
6654 /* Update the first 2 immediate operands. */
6655 n
= i
.operands
> 2 ? 2 : i
.operands
;
6658 for (j
= 0; j
< n
; j
++)
6659 if (update_imm (j
) == 0)
6662 /* The 3rd operand can't be immediate operand. */
6663 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6670 process_operands (void)
6672 /* Default segment register this instruction will use for memory
6673 accesses. 0 means unknown. This is only for optimizing out
6674 unnecessary segment overrides. */
6675 const seg_entry
*default_seg
= 0;
6677 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6679 unsigned int dupl
= i
.operands
;
6680 unsigned int dest
= dupl
- 1;
6683 /* The destination must be an xmm register. */
6684 gas_assert (i
.reg_operands
6685 && MAX_OPERANDS
> dupl
6686 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6688 if (i
.tm
.operand_types
[0].bitfield
.acc
6689 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6691 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6693 /* Keep xmm0 for instructions with VEX prefix and 3
6695 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6696 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6701 /* We remove the first xmm0 and keep the number of
6702 operands unchanged, which in fact duplicates the
6704 for (j
= 1; j
< i
.operands
; j
++)
6706 i
.op
[j
- 1] = i
.op
[j
];
6707 i
.types
[j
- 1] = i
.types
[j
];
6708 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6712 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6714 gas_assert ((MAX_OPERANDS
- 1) > dupl
6715 && (i
.tm
.opcode_modifier
.vexsources
6718 /* Add the implicit xmm0 for instructions with VEX prefix
6720 for (j
= i
.operands
; j
> 0; j
--)
6722 i
.op
[j
] = i
.op
[j
- 1];
6723 i
.types
[j
] = i
.types
[j
- 1];
6724 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6727 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6728 i
.types
[0] = regxmm
;
6729 i
.tm
.operand_types
[0] = regxmm
;
6732 i
.reg_operands
+= 2;
6737 i
.op
[dupl
] = i
.op
[dest
];
6738 i
.types
[dupl
] = i
.types
[dest
];
6739 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6748 i
.op
[dupl
] = i
.op
[dest
];
6749 i
.types
[dupl
] = i
.types
[dest
];
6750 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6753 if (i
.tm
.opcode_modifier
.immext
)
6756 else if (i
.tm
.operand_types
[0].bitfield
.acc
6757 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6761 for (j
= 1; j
< i
.operands
; j
++)
6763 i
.op
[j
- 1] = i
.op
[j
];
6764 i
.types
[j
- 1] = i
.types
[j
];
6766 /* We need to adjust fields in i.tm since they are used by
6767 build_modrm_byte. */
6768 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6775 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6777 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6779 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6780 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6781 regnum
= register_number (i
.op
[1].regs
);
6782 first_reg_in_group
= regnum
& ~3;
6783 last_reg_in_group
= first_reg_in_group
+ 3;
6784 if (regnum
!= first_reg_in_group
)
6785 as_warn (_("source register `%s%s' implicitly denotes"
6786 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6787 register_prefix
, i
.op
[1].regs
->reg_name
,
6788 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6789 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6792 else if (i
.tm
.opcode_modifier
.regkludge
)
6794 /* The imul $imm, %reg instruction is converted into
6795 imul $imm, %reg, %reg, and the clr %reg instruction
6796 is converted into xor %reg, %reg. */
6798 unsigned int first_reg_op
;
6800 if (operand_type_check (i
.types
[0], reg
))
6804 /* Pretend we saw the extra register operand. */
6805 gas_assert (i
.reg_operands
== 1
6806 && i
.op
[first_reg_op
+ 1].regs
== 0);
6807 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6808 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6813 if (i
.tm
.opcode_modifier
.shortform
)
6815 if (i
.types
[0].bitfield
.sreg2
6816 || i
.types
[0].bitfield
.sreg3
)
6818 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6819 && i
.op
[0].regs
->reg_num
== 1)
6821 as_bad (_("you can't `pop %scs'"), register_prefix
);
6824 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6825 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6830 /* The register or float register operand is in operand
6834 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6835 || operand_type_check (i
.types
[0], reg
))
6839 /* Register goes in low 3 bits of opcode. */
6840 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6841 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6843 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6845 /* Warn about some common errors, but press on regardless.
6846 The first case can be generated by gcc (<= 2.8.1). */
6847 if (i
.operands
== 2)
6849 /* Reversed arguments on faddp, fsubp, etc. */
6850 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6851 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6852 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6856 /* Extraneous `l' suffix on fp insn. */
6857 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6858 register_prefix
, i
.op
[0].regs
->reg_name
);
6863 else if (i
.tm
.opcode_modifier
.modrm
)
6865 /* The opcode is completed (modulo i.tm.extension_opcode which
6866 must be put into the modrm byte). Now, we make the modrm and
6867 index base bytes based on all the info we've collected. */
6869 default_seg
= build_modrm_byte ();
6871 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6875 else if (i
.tm
.opcode_modifier
.isstring
)
6877 /* For the string instructions that allow a segment override
6878 on one of their operands, the default segment is ds. */
6882 if (i
.tm
.base_opcode
== 0x8d /* lea */
6885 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6887 /* If a segment was explicitly specified, and the specified segment
6888 is not the default, use an opcode prefix to select it. If we
6889 never figured out what the default segment is, then default_seg
6890 will be zero at this point, and the specified segment prefix will
6892 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6894 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6900 static const seg_entry
*
6901 build_modrm_byte (void)
6903 const seg_entry
*default_seg
= 0;
6904 unsigned int source
, dest
;
6907 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6910 unsigned int nds
, reg_slot
;
6913 dest
= i
.operands
- 1;
6916 /* There are 2 kinds of instructions:
6917 1. 5 operands: 4 register operands or 3 register operands
6918 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6919 VexW0 or VexW1. The destination must be either XMM, YMM or
6921 2. 4 operands: 4 register operands or 3 register operands
6922 plus 1 memory operand, with VexXDS. */
6923 gas_assert ((i
.reg_operands
== 4
6924 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6925 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6926 && i
.tm
.opcode_modifier
.vexw
6927 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6929 /* If VexW1 is set, the first non-immediate operand is the source and
6930 the second non-immediate one is encoded in the immediate operand. */
6931 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6933 source
= i
.imm_operands
;
6934 reg_slot
= i
.imm_operands
+ 1;
6938 source
= i
.imm_operands
+ 1;
6939 reg_slot
= i
.imm_operands
;
6942 if (i
.imm_operands
== 0)
6944 /* When there is no immediate operand, generate an 8bit
6945 immediate operand to encode the first operand. */
6946 exp
= &im_expressions
[i
.imm_operands
++];
6947 i
.op
[i
.operands
].imms
= exp
;
6948 i
.types
[i
.operands
] = imm8
;
6951 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6952 exp
->X_op
= O_constant
;
6953 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6954 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6958 unsigned int imm_slot
;
6960 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6962 if (i
.tm
.opcode_modifier
.immext
)
6964 /* When ImmExt is set, the immediate byte is the last
6966 imm_slot
= i
.operands
- 1;
6974 /* Turn on Imm8 so that output_imm will generate it. */
6975 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6978 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6979 i
.op
[imm_slot
].imms
->X_add_number
6980 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6981 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6984 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6985 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6990 /* i.reg_operands MUST be the number of real register operands;
6991 implicit registers do not count. If there are 3 register
6992 operands, it must be a instruction with VexNDS. For a
6993 instruction with VexNDD, the destination register is encoded
6994 in VEX prefix. If there are 4 register operands, it must be
6995 a instruction with VEX prefix and 3 sources. */
6996 if (i
.mem_operands
== 0
6997 && ((i
.reg_operands
== 2
6998 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6999 || (i
.reg_operands
== 3
7000 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7001 || (i
.reg_operands
== 4 && vex_3_sources
)))
7009 /* When there are 3 operands, one of them may be immediate,
7010 which may be the first or the last operand. Otherwise,
7011 the first operand must be shift count register (cl) or it
7012 is an instruction with VexNDS. */
7013 gas_assert (i
.imm_operands
== 1
7014 || (i
.imm_operands
== 0
7015 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7016 || i
.types
[0].bitfield
.shiftcount
)));
7017 if (operand_type_check (i
.types
[0], imm
)
7018 || i
.types
[0].bitfield
.shiftcount
)
7024 /* When there are 4 operands, the first two must be 8bit
7025 immediate operands. The source operand will be the 3rd
7028 For instructions with VexNDS, if the first operand
7029 an imm8, the source operand is the 2nd one. If the last
7030 operand is imm8, the source operand is the first one. */
7031 gas_assert ((i
.imm_operands
== 2
7032 && i
.types
[0].bitfield
.imm8
7033 && i
.types
[1].bitfield
.imm8
)
7034 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7035 && i
.imm_operands
== 1
7036 && (i
.types
[0].bitfield
.imm8
7037 || i
.types
[i
.operands
- 1].bitfield
.imm8
7039 if (i
.imm_operands
== 2)
7043 if (i
.types
[0].bitfield
.imm8
)
7050 if (is_evex_encoding (&i
.tm
))
7052 /* For EVEX instructions, when there are 5 operands, the
7053 first one must be immediate operand. If the second one
7054 is immediate operand, the source operand is the 3th
7055 one. If the last one is immediate operand, the source
7056 operand is the 2nd one. */
7057 gas_assert (i
.imm_operands
== 2
7058 && i
.tm
.opcode_modifier
.sae
7059 && operand_type_check (i
.types
[0], imm
));
7060 if (operand_type_check (i
.types
[1], imm
))
7062 else if (operand_type_check (i
.types
[4], imm
))
7076 /* RC/SAE operand could be between DEST and SRC. That happens
7077 when one operand is GPR and the other one is XMM/YMM/ZMM
7079 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7082 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7084 /* For instructions with VexNDS, the register-only source
7085 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7086 register. It is encoded in VEX prefix. We need to
7087 clear RegMem bit before calling operand_type_equal. */
7089 i386_operand_type op
;
7092 /* Check register-only source operand when two source
7093 operands are swapped. */
7094 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7095 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7103 op
= i
.tm
.operand_types
[vvvv
];
7104 op
.bitfield
.regmem
= 0;
7105 if ((dest
+ 1) >= i
.operands
7106 || ((!op
.bitfield
.reg
7107 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7108 && !op
.bitfield
.regsimd
7109 && !operand_type_equal (&op
, ®mask
)))
7111 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7117 /* One of the register operands will be encoded in the i.tm.reg
7118 field, the other in the combined i.tm.mode and i.tm.regmem
7119 fields. If no form of this instruction supports a memory
7120 destination operand, then we assume the source operand may
7121 sometimes be a memory operand and so we need to store the
7122 destination in the i.rm.reg field. */
7123 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7124 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7126 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7127 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7128 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7129 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7130 i
.has_regmmx
= TRUE
;
7131 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7132 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7134 if (i
.types
[dest
].bitfield
.zmmword
7135 || i
.types
[source
].bitfield
.zmmword
)
7136 i
.has_regzmm
= TRUE
;
7137 else if (i
.types
[dest
].bitfield
.ymmword
7138 || i
.types
[source
].bitfield
.ymmword
)
7139 i
.has_regymm
= TRUE
;
7141 i
.has_regxmm
= TRUE
;
7143 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7145 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7147 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7149 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7154 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7155 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7156 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7158 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7160 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7162 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7165 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7167 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7170 add_prefix (LOCK_PREFIX_OPCODE
);
7174 { /* If it's not 2 reg operands... */
7179 unsigned int fake_zero_displacement
= 0;
7182 for (op
= 0; op
< i
.operands
; op
++)
7183 if (operand_type_check (i
.types
[op
], anymem
))
7185 gas_assert (op
< i
.operands
);
7187 if (i
.tm
.opcode_modifier
.vecsib
)
7189 if (i
.index_reg
->reg_num
== RegIZ
)
7192 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7195 i
.sib
.base
= NO_BASE_REGISTER
;
7196 i
.sib
.scale
= i
.log2_scale_factor
;
7197 i
.types
[op
].bitfield
.disp8
= 0;
7198 i
.types
[op
].bitfield
.disp16
= 0;
7199 i
.types
[op
].bitfield
.disp64
= 0;
7200 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7202 /* Must be 32 bit */
7203 i
.types
[op
].bitfield
.disp32
= 1;
7204 i
.types
[op
].bitfield
.disp32s
= 0;
7208 i
.types
[op
].bitfield
.disp32
= 0;
7209 i
.types
[op
].bitfield
.disp32s
= 1;
7212 i
.sib
.index
= i
.index_reg
->reg_num
;
7213 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7215 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7221 if (i
.base_reg
== 0)
7224 if (!i
.disp_operands
)
7225 fake_zero_displacement
= 1;
7226 if (i
.index_reg
== 0)
7228 i386_operand_type newdisp
;
7230 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7231 /* Operand is just <disp> */
7232 if (flag_code
== CODE_64BIT
)
7234 /* 64bit mode overwrites the 32bit absolute
7235 addressing by RIP relative addressing and
7236 absolute addressing is encoded by one of the
7237 redundant SIB forms. */
7238 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7239 i
.sib
.base
= NO_BASE_REGISTER
;
7240 i
.sib
.index
= NO_INDEX_REGISTER
;
7241 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7243 else if ((flag_code
== CODE_16BIT
)
7244 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7246 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7251 i
.rm
.regmem
= NO_BASE_REGISTER
;
7254 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7255 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7257 else if (!i
.tm
.opcode_modifier
.vecsib
)
7259 /* !i.base_reg && i.index_reg */
7260 if (i
.index_reg
->reg_num
== RegIZ
)
7261 i
.sib
.index
= NO_INDEX_REGISTER
;
7263 i
.sib
.index
= i
.index_reg
->reg_num
;
7264 i
.sib
.base
= NO_BASE_REGISTER
;
7265 i
.sib
.scale
= i
.log2_scale_factor
;
7266 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7267 i
.types
[op
].bitfield
.disp8
= 0;
7268 i
.types
[op
].bitfield
.disp16
= 0;
7269 i
.types
[op
].bitfield
.disp64
= 0;
7270 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7272 /* Must be 32 bit */
7273 i
.types
[op
].bitfield
.disp32
= 1;
7274 i
.types
[op
].bitfield
.disp32s
= 0;
7278 i
.types
[op
].bitfield
.disp32
= 0;
7279 i
.types
[op
].bitfield
.disp32s
= 1;
7281 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7285 /* RIP addressing for 64bit mode. */
7286 else if (i
.base_reg
->reg_num
== RegIP
)
7288 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7289 i
.rm
.regmem
= NO_BASE_REGISTER
;
7290 i
.types
[op
].bitfield
.disp8
= 0;
7291 i
.types
[op
].bitfield
.disp16
= 0;
7292 i
.types
[op
].bitfield
.disp32
= 0;
7293 i
.types
[op
].bitfield
.disp32s
= 1;
7294 i
.types
[op
].bitfield
.disp64
= 0;
7295 i
.flags
[op
] |= Operand_PCrel
;
7296 if (! i
.disp_operands
)
7297 fake_zero_displacement
= 1;
7299 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7301 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7302 switch (i
.base_reg
->reg_num
)
7305 if (i
.index_reg
== 0)
7307 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7308 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7312 if (i
.index_reg
== 0)
7315 if (operand_type_check (i
.types
[op
], disp
) == 0)
7317 /* fake (%bp) into 0(%bp) */
7318 i
.types
[op
].bitfield
.disp8
= 1;
7319 fake_zero_displacement
= 1;
7322 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7323 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7325 default: /* (%si) -> 4 or (%di) -> 5 */
7326 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7328 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7330 else /* i.base_reg and 32/64 bit mode */
7332 if (flag_code
== CODE_64BIT
7333 && operand_type_check (i
.types
[op
], disp
))
7335 i
.types
[op
].bitfield
.disp16
= 0;
7336 i
.types
[op
].bitfield
.disp64
= 0;
7337 if (i
.prefix
[ADDR_PREFIX
] == 0)
7339 i
.types
[op
].bitfield
.disp32
= 0;
7340 i
.types
[op
].bitfield
.disp32s
= 1;
7344 i
.types
[op
].bitfield
.disp32
= 1;
7345 i
.types
[op
].bitfield
.disp32s
= 0;
7349 if (!i
.tm
.opcode_modifier
.vecsib
)
7350 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7351 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7353 i
.sib
.base
= i
.base_reg
->reg_num
;
7354 /* x86-64 ignores REX prefix bit here to avoid decoder
7356 if (!(i
.base_reg
->reg_flags
& RegRex
)
7357 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7358 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7360 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7362 fake_zero_displacement
= 1;
7363 i
.types
[op
].bitfield
.disp8
= 1;
7365 i
.sib
.scale
= i
.log2_scale_factor
;
7366 if (i
.index_reg
== 0)
7368 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7369 /* <disp>(%esp) becomes two byte modrm with no index
7370 register. We've already stored the code for esp
7371 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7372 Any base register besides %esp will not use the
7373 extra modrm byte. */
7374 i
.sib
.index
= NO_INDEX_REGISTER
;
7376 else if (!i
.tm
.opcode_modifier
.vecsib
)
7378 if (i
.index_reg
->reg_num
== RegIZ
)
7379 i
.sib
.index
= NO_INDEX_REGISTER
;
7381 i
.sib
.index
= i
.index_reg
->reg_num
;
7382 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7383 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7388 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7389 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7393 if (!fake_zero_displacement
7397 fake_zero_displacement
= 1;
7398 if (i
.disp_encoding
== disp_encoding_8bit
)
7399 i
.types
[op
].bitfield
.disp8
= 1;
7401 i
.types
[op
].bitfield
.disp32
= 1;
7403 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7407 if (fake_zero_displacement
)
7409 /* Fakes a zero displacement assuming that i.types[op]
7410 holds the correct displacement size. */
7413 gas_assert (i
.op
[op
].disps
== 0);
7414 exp
= &disp_expressions
[i
.disp_operands
++];
7415 i
.op
[op
].disps
= exp
;
7416 exp
->X_op
= O_constant
;
7417 exp
->X_add_number
= 0;
7418 exp
->X_add_symbol
= (symbolS
*) 0;
7419 exp
->X_op_symbol
= (symbolS
*) 0;
7427 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7429 if (operand_type_check (i
.types
[0], imm
))
7430 i
.vex
.register_specifier
= NULL
;
7433 /* VEX.vvvv encodes one of the sources when the first
7434 operand is not an immediate. */
7435 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7436 i
.vex
.register_specifier
= i
.op
[0].regs
;
7438 i
.vex
.register_specifier
= i
.op
[1].regs
;
7441 /* Destination is a XMM register encoded in the ModRM.reg
7443 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7444 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7447 /* ModRM.rm and VEX.B encodes the other source. */
7448 if (!i
.mem_operands
)
7452 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7453 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7455 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7457 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7461 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7463 i
.vex
.register_specifier
= i
.op
[2].regs
;
7464 if (!i
.mem_operands
)
7467 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7468 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7472 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7473 (if any) based on i.tm.extension_opcode. Again, we must be
7474 careful to make sure that segment/control/debug/test/MMX
7475 registers are coded into the i.rm.reg field. */
7476 else if (i
.reg_operands
)
7479 unsigned int vex_reg
= ~0;
7481 for (op
= 0; op
< i
.operands
; op
++)
7483 if (i
.types
[op
].bitfield
.reg
7484 || i
.types
[op
].bitfield
.regbnd
7485 || i
.types
[op
].bitfield
.regmask
7486 || i
.types
[op
].bitfield
.sreg2
7487 || i
.types
[op
].bitfield
.sreg3
7488 || i
.types
[op
].bitfield
.control
7489 || i
.types
[op
].bitfield
.debug
7490 || i
.types
[op
].bitfield
.test
)
7492 if (i
.types
[op
].bitfield
.regsimd
)
7494 if (i
.types
[op
].bitfield
.zmmword
)
7495 i
.has_regzmm
= TRUE
;
7496 else if (i
.types
[op
].bitfield
.ymmword
)
7497 i
.has_regymm
= TRUE
;
7499 i
.has_regxmm
= TRUE
;
7502 if (i
.types
[op
].bitfield
.regmmx
)
7504 i
.has_regmmx
= TRUE
;
7511 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7513 /* For instructions with VexNDS, the register-only
7514 source operand is encoded in VEX prefix. */
7515 gas_assert (mem
!= (unsigned int) ~0);
7520 gas_assert (op
< i
.operands
);
7524 /* Check register-only source operand when two source
7525 operands are swapped. */
7526 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7527 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7531 gas_assert (mem
== (vex_reg
+ 1)
7532 && op
< i
.operands
);
7537 gas_assert (vex_reg
< i
.operands
);
7541 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7543 /* For instructions with VexNDD, the register destination
7544 is encoded in VEX prefix. */
7545 if (i
.mem_operands
== 0)
7547 /* There is no memory operand. */
7548 gas_assert ((op
+ 2) == i
.operands
);
7553 /* There are only 2 non-immediate operands. */
7554 gas_assert (op
< i
.imm_operands
+ 2
7555 && i
.operands
== i
.imm_operands
+ 2);
7556 vex_reg
= i
.imm_operands
+ 1;
7560 gas_assert (op
< i
.operands
);
7562 if (vex_reg
!= (unsigned int) ~0)
7564 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7566 if ((!type
->bitfield
.reg
7567 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7568 && !type
->bitfield
.regsimd
7569 && !operand_type_equal (type
, ®mask
))
7572 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7575 /* Don't set OP operand twice. */
7578 /* If there is an extension opcode to put here, the
7579 register number must be put into the regmem field. */
7580 if (i
.tm
.extension_opcode
!= None
)
7582 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7583 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7585 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7590 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7591 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7593 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7598 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7599 must set it to 3 to indicate this is a register operand
7600 in the regmem field. */
7601 if (!i
.mem_operands
)
7605 /* Fill in i.rm.reg field with extension opcode (if any). */
7606 if (i
.tm
.extension_opcode
!= None
)
7607 i
.rm
.reg
= i
.tm
.extension_opcode
;
7613 output_branch (void)
7619 relax_substateT subtype
;
7623 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7624 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7627 if (i
.prefix
[DATA_PREFIX
] != 0)
7633 /* Pentium4 branch hints. */
7634 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7635 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7640 if (i
.prefix
[REX_PREFIX
] != 0)
7646 /* BND prefixed jump. */
7647 if (i
.prefix
[BND_PREFIX
] != 0)
7649 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7653 if (i
.prefixes
!= 0 && !intel_syntax
)
7654 as_warn (_("skipping prefixes on this instruction"));
7656 /* It's always a symbol; End frag & setup for relax.
7657 Make sure there is enough room in this frag for the largest
7658 instruction we may generate in md_convert_frag. This is 2
7659 bytes for the opcode and room for the prefix and largest
7661 frag_grow (prefix
+ 2 + 4);
7662 /* Prefix and 1 opcode byte go in fr_fix. */
7663 p
= frag_more (prefix
+ 1);
7664 if (i
.prefix
[DATA_PREFIX
] != 0)
7665 *p
++ = DATA_PREFIX_OPCODE
;
7666 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7667 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7668 *p
++ = i
.prefix
[SEG_PREFIX
];
7669 if (i
.prefix
[REX_PREFIX
] != 0)
7670 *p
++ = i
.prefix
[REX_PREFIX
];
7671 *p
= i
.tm
.base_opcode
;
7673 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7674 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7675 else if (cpu_arch_flags
.bitfield
.cpui386
)
7676 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7678 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7681 sym
= i
.op
[0].disps
->X_add_symbol
;
7682 off
= i
.op
[0].disps
->X_add_number
;
7684 if (i
.op
[0].disps
->X_op
!= O_constant
7685 && i
.op
[0].disps
->X_op
!= O_symbol
)
7687 /* Handle complex expressions. */
7688 sym
= make_expr_symbol (i
.op
[0].disps
);
7692 /* 1 possible extra opcode + 4 byte displacement go in var part.
7693 Pass reloc in fr_var. */
7694 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7697 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7698 /* Return TRUE iff PLT32 relocation should be used for branching to
7702 need_plt32_p (symbolS
*s
)
7704 /* PLT32 relocation is ELF only. */
7708 /* Since there is no need to prepare for PLT branch on x86-64, we
7709 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7710 be used as a marker for 32-bit PC-relative branches. */
7714 /* Weak or undefined symbol need PLT32 relocation. */
7715 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7718 /* Non-global symbol doesn't need PLT32 relocation. */
7719 if (! S_IS_EXTERNAL (s
))
7722 /* Other global symbols need PLT32 relocation. NB: Symbol with
7723 non-default visibilities are treated as normal global symbol
7724 so that PLT32 relocation can be used as a marker for 32-bit
7725 PC-relative branches. It is useful for linker relaxation. */
7736 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7738 if (i
.tm
.opcode_modifier
.jumpbyte
)
7740 /* This is a loop or jecxz type instruction. */
7742 if (i
.prefix
[ADDR_PREFIX
] != 0)
7744 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7747 /* Pentium4 branch hints. */
7748 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7749 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7751 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7760 if (flag_code
== CODE_16BIT
)
7763 if (i
.prefix
[DATA_PREFIX
] != 0)
7765 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7775 if (i
.prefix
[REX_PREFIX
] != 0)
7777 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7781 /* BND prefixed jump. */
7782 if (i
.prefix
[BND_PREFIX
] != 0)
7784 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7788 if (i
.prefixes
!= 0 && !intel_syntax
)
7789 as_warn (_("skipping prefixes on this instruction"));
7791 p
= frag_more (i
.tm
.opcode_length
+ size
);
7792 switch (i
.tm
.opcode_length
)
7795 *p
++ = i
.tm
.base_opcode
>> 8;
7798 *p
++ = i
.tm
.base_opcode
;
7804 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7806 && jump_reloc
== NO_RELOC
7807 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7808 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7811 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7813 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7814 i
.op
[0].disps
, 1, jump_reloc
);
7816 /* All jumps handled here are signed, but don't use a signed limit
7817 check for 32 and 16 bit jumps as we want to allow wrap around at
7818 4G and 64k respectively. */
7820 fixP
->fx_signed
= 1;
7824 output_interseg_jump (void)
7832 if (flag_code
== CODE_16BIT
)
7836 if (i
.prefix
[DATA_PREFIX
] != 0)
7842 if (i
.prefix
[REX_PREFIX
] != 0)
7852 if (i
.prefixes
!= 0 && !intel_syntax
)
7853 as_warn (_("skipping prefixes on this instruction"));
7855 /* 1 opcode; 2 segment; offset */
7856 p
= frag_more (prefix
+ 1 + 2 + size
);
7858 if (i
.prefix
[DATA_PREFIX
] != 0)
7859 *p
++ = DATA_PREFIX_OPCODE
;
7861 if (i
.prefix
[REX_PREFIX
] != 0)
7862 *p
++ = i
.prefix
[REX_PREFIX
];
7864 *p
++ = i
.tm
.base_opcode
;
7865 if (i
.op
[1].imms
->X_op
== O_constant
)
7867 offsetT n
= i
.op
[1].imms
->X_add_number
;
7870 && !fits_in_unsigned_word (n
)
7871 && !fits_in_signed_word (n
))
7873 as_bad (_("16-bit jump out of range"));
7876 md_number_to_chars (p
, n
, size
);
7879 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7880 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7881 if (i
.op
[0].imms
->X_op
!= O_constant
)
7882 as_bad (_("can't handle non absolute segment in `%s'"),
7884 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7892 asection
*seg
= now_seg
;
7893 subsegT subseg
= now_subseg
;
7895 unsigned int alignment
, align_size_1
;
7896 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7897 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7898 unsigned int padding
;
7900 if (!IS_ELF
|| !x86_used_note
)
7903 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7905 /* The .note.gnu.property section layout:
7907 Field Length Contents
7910 n_descsz 4 The note descriptor size
7911 n_type 4 NT_GNU_PROPERTY_TYPE_0
7913 n_desc n_descsz The program property array
7917 /* Create the .note.gnu.property section. */
7918 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7919 bfd_set_section_flags (stdoutput
, sec
,
7926 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7937 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
7938 elf_section_type (sec
) = SHT_NOTE
;
7940 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7942 isa_1_descsz_raw
= 4 + 4 + 4;
7943 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7944 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
7946 feature_2_descsz_raw
= isa_1_descsz
;
7947 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7949 feature_2_descsz_raw
+= 4 + 4 + 4;
7950 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7951 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
7954 descsz
= feature_2_descsz
;
7955 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7956 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
7958 /* Write n_namsz. */
7959 md_number_to_chars (p
, (valueT
) 4, 4);
7961 /* Write n_descsz. */
7962 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
7965 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
7968 memcpy (p
+ 4 * 3, "GNU", 4);
7970 /* Write 4-byte type. */
7971 md_number_to_chars (p
+ 4 * 4,
7972 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
7974 /* Write 4-byte data size. */
7975 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
7977 /* Write 4-byte data. */
7978 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
7980 /* Zero out paddings. */
7981 padding
= isa_1_descsz
- isa_1_descsz_raw
;
7983 memset (p
+ 4 * 7, 0, padding
);
7985 /* Write 4-byte type. */
7986 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
7987 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
7989 /* Write 4-byte data size. */
7990 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
7992 /* Write 4-byte data. */
7993 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
7994 (valueT
) x86_feature_2_used
, 4);
7996 /* Zero out paddings. */
7997 padding
= feature_2_descsz
- feature_2_descsz_raw
;
7999 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8001 /* We probably can't restore the current segment, for there likely
8004 subseg_set (seg
, subseg
);
8011 fragS
*insn_start_frag
;
8012 offsetT insn_start_off
;
8014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8015 if (IS_ELF
&& x86_used_note
)
8017 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8018 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8019 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8020 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8021 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8022 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8023 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8024 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8025 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8026 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8027 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8028 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8029 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8030 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8031 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8032 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8033 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8034 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8035 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8036 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8037 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8038 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8039 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8040 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8041 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8042 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8043 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8044 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8045 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8046 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8047 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8048 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8049 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8050 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8051 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8052 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8053 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8054 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8055 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8056 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8057 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8058 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8059 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8060 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8061 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8062 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8063 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8064 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8066 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8067 || i
.tm
.cpu_flags
.bitfield
.cpu287
8068 || i
.tm
.cpu_flags
.bitfield
.cpu387
8069 || i
.tm
.cpu_flags
.bitfield
.cpu687
8070 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8071 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8072 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8073 Xfence instructions. */
8074 if (i
.tm
.base_opcode
!= 0xf18
8075 && i
.tm
.base_opcode
!= 0xf0d
8076 && i
.tm
.base_opcode
!= 0xfae
8078 || i
.tm
.cpu_flags
.bitfield
.cpummx
8079 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8080 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8081 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8083 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8085 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8087 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8088 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8089 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8090 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8091 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8092 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8093 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8094 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8095 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8099 /* Tie dwarf2 debug info to the address at the start of the insn.
8100 We can't do this after the insn has been output as the current
8101 frag may have been closed off. eg. by frag_var. */
8102 dwarf2_emit_insn (0);
8104 insn_start_frag
= frag_now
;
8105 insn_start_off
= frag_now_fix ();
8108 if (i
.tm
.opcode_modifier
.jump
)
8110 else if (i
.tm
.opcode_modifier
.jumpbyte
8111 || i
.tm
.opcode_modifier
.jumpdword
)
8113 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8114 output_interseg_jump ();
8117 /* Output normal instructions here. */
8121 unsigned int prefix
;
8124 && i
.tm
.base_opcode
== 0xfae
8126 && i
.imm_operands
== 1
8127 && (i
.op
[0].imms
->X_add_number
== 0xe8
8128 || i
.op
[0].imms
->X_add_number
== 0xf0
8129 || i
.op
[0].imms
->X_add_number
== 0xf8))
8131 /* Encode lfence, mfence, and sfence as
8132 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8133 offsetT val
= 0x240483f0ULL
;
8135 md_number_to_chars (p
, val
, 5);
8139 /* Some processors fail on LOCK prefix. This options makes
8140 assembler ignore LOCK prefix and serves as a workaround. */
8141 if (omit_lock_prefix
)
8143 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8145 i
.prefix
[LOCK_PREFIX
] = 0;
8148 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8149 don't need the explicit prefix. */
8150 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8152 switch (i
.tm
.opcode_length
)
8155 if (i
.tm
.base_opcode
& 0xff000000)
8157 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8158 add_prefix (prefix
);
8162 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8164 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8165 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8166 || prefix
!= REPE_PREFIX_OPCODE
8167 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8168 add_prefix (prefix
);
8174 /* Check for pseudo prefixes. */
8175 as_bad_where (insn_start_frag
->fr_file
,
8176 insn_start_frag
->fr_line
,
8177 _("pseudo prefix without instruction"));
8183 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8184 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8185 R_X86_64_GOTTPOFF relocation so that linker can safely
8186 perform IE->LE optimization. */
8187 if (x86_elf_abi
== X86_64_X32_ABI
8189 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8190 && i
.prefix
[REX_PREFIX
] == 0)
8191 add_prefix (REX_OPCODE
);
8194 /* The prefix bytes. */
8195 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8197 FRAG_APPEND_1_CHAR (*q
);
8201 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8206 /* REX byte is encoded in VEX prefix. */
8210 FRAG_APPEND_1_CHAR (*q
);
8213 /* There should be no other prefixes for instructions
8218 /* For EVEX instructions i.vrex should become 0 after
8219 build_evex_prefix. For VEX instructions upper 16 registers
8220 aren't available, so VREX should be 0. */
8223 /* Now the VEX prefix. */
8224 p
= frag_more (i
.vex
.length
);
8225 for (j
= 0; j
< i
.vex
.length
; j
++)
8226 p
[j
] = i
.vex
.bytes
[j
];
8229 /* Now the opcode; be careful about word order here! */
8230 if (i
.tm
.opcode_length
== 1)
8232 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8236 switch (i
.tm
.opcode_length
)
8240 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8241 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8245 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8255 /* Put out high byte first: can't use md_number_to_chars! */
8256 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8257 *p
= i
.tm
.base_opcode
& 0xff;
8260 /* Now the modrm byte and sib byte (if present). */
8261 if (i
.tm
.opcode_modifier
.modrm
)
8263 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8266 /* If i.rm.regmem == ESP (4)
8267 && i.rm.mode != (Register mode)
8269 ==> need second modrm byte. */
8270 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8272 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8273 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8275 | i
.sib
.scale
<< 6));
8278 if (i
.disp_operands
)
8279 output_disp (insn_start_frag
, insn_start_off
);
8282 output_imm (insn_start_frag
, insn_start_off
);
8288 pi ("" /*line*/, &i
);
8290 #endif /* DEBUG386 */
8293 /* Return the size of the displacement operand N. */
8296 disp_size (unsigned int n
)
8300 if (i
.types
[n
].bitfield
.disp64
)
8302 else if (i
.types
[n
].bitfield
.disp8
)
8304 else if (i
.types
[n
].bitfield
.disp16
)
8309 /* Return the size of the immediate operand N. */
8312 imm_size (unsigned int n
)
8315 if (i
.types
[n
].bitfield
.imm64
)
8317 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8319 else if (i
.types
[n
].bitfield
.imm16
)
8325 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8330 for (n
= 0; n
< i
.operands
; n
++)
8332 if (operand_type_check (i
.types
[n
], disp
))
8334 if (i
.op
[n
].disps
->X_op
== O_constant
)
8336 int size
= disp_size (n
);
8337 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8339 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8341 p
= frag_more (size
);
8342 md_number_to_chars (p
, val
, size
);
8346 enum bfd_reloc_code_real reloc_type
;
8347 int size
= disp_size (n
);
8348 int sign
= i
.types
[n
].bitfield
.disp32s
;
8349 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8352 /* We can't have 8 bit displacement here. */
8353 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8355 /* The PC relative address is computed relative
8356 to the instruction boundary, so in case immediate
8357 fields follows, we need to adjust the value. */
8358 if (pcrel
&& i
.imm_operands
)
8363 for (n1
= 0; n1
< i
.operands
; n1
++)
8364 if (operand_type_check (i
.types
[n1
], imm
))
8366 /* Only one immediate is allowed for PC
8367 relative address. */
8368 gas_assert (sz
== 0);
8370 i
.op
[n
].disps
->X_add_number
-= sz
;
8372 /* We should find the immediate. */
8373 gas_assert (sz
!= 0);
8376 p
= frag_more (size
);
8377 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8379 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8380 && (((reloc_type
== BFD_RELOC_32
8381 || reloc_type
== BFD_RELOC_X86_64_32S
8382 || (reloc_type
== BFD_RELOC_64
8384 && (i
.op
[n
].disps
->X_op
== O_symbol
8385 || (i
.op
[n
].disps
->X_op
== O_add
8386 && ((symbol_get_value_expression
8387 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8389 || reloc_type
== BFD_RELOC_32_PCREL
))
8393 if (insn_start_frag
== frag_now
)
8394 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8399 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8400 for (fr
= insn_start_frag
->fr_next
;
8401 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8403 add
+= p
- frag_now
->fr_literal
;
8408 reloc_type
= BFD_RELOC_386_GOTPC
;
8409 i
.op
[n
].imms
->X_add_number
+= add
;
8411 else if (reloc_type
== BFD_RELOC_64
)
8412 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8414 /* Don't do the adjustment for x86-64, as there
8415 the pcrel addressing is relative to the _next_
8416 insn, and that is taken care of in other code. */
8417 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8419 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8420 size
, i
.op
[n
].disps
, pcrel
,
8422 /* Check for "call/jmp *mem", "mov mem, %reg",
8423 "test %reg, mem" and "binop mem, %reg" where binop
8424 is one of adc, add, and, cmp, or, sbb, sub, xor
8425 instructions without data prefix. Always generate
8426 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8427 if (i
.prefix
[DATA_PREFIX
] == 0
8428 && (generate_relax_relocations
8431 && i
.rm
.regmem
== 5))
8433 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8434 && ((i
.operands
== 1
8435 && i
.tm
.base_opcode
== 0xff
8436 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8438 && (i
.tm
.base_opcode
== 0x8b
8439 || i
.tm
.base_opcode
== 0x85
8440 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8444 fixP
->fx_tcbit
= i
.rex
!= 0;
8446 && (i
.base_reg
->reg_num
== RegIP
))
8447 fixP
->fx_tcbit2
= 1;
8450 fixP
->fx_tcbit2
= 1;
8458 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8463 for (n
= 0; n
< i
.operands
; n
++)
8465 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8466 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8469 if (operand_type_check (i
.types
[n
], imm
))
8471 if (i
.op
[n
].imms
->X_op
== O_constant
)
8473 int size
= imm_size (n
);
8476 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8478 p
= frag_more (size
);
8479 md_number_to_chars (p
, val
, size
);
8483 /* Not absolute_section.
8484 Need a 32-bit fixup (don't support 8bit
8485 non-absolute imms). Try to support other
8487 enum bfd_reloc_code_real reloc_type
;
8488 int size
= imm_size (n
);
8491 if (i
.types
[n
].bitfield
.imm32s
8492 && (i
.suffix
== QWORD_MNEM_SUFFIX
8493 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8498 p
= frag_more (size
);
8499 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8501 /* This is tough to explain. We end up with this one if we
8502 * have operands that look like
8503 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8504 * obtain the absolute address of the GOT, and it is strongly
8505 * preferable from a performance point of view to avoid using
8506 * a runtime relocation for this. The actual sequence of
8507 * instructions often look something like:
8512 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8514 * The call and pop essentially return the absolute address
8515 * of the label .L66 and store it in %ebx. The linker itself
8516 * will ultimately change the first operand of the addl so
8517 * that %ebx points to the GOT, but to keep things simple, the
8518 * .o file must have this operand set so that it generates not
8519 * the absolute address of .L66, but the absolute address of
8520 * itself. This allows the linker itself simply treat a GOTPC
8521 * relocation as asking for a pcrel offset to the GOT to be
8522 * added in, and the addend of the relocation is stored in the
8523 * operand field for the instruction itself.
8525 * Our job here is to fix the operand so that it would add
8526 * the correct offset so that %ebx would point to itself. The
8527 * thing that is tricky is that .-.L66 will point to the
8528 * beginning of the instruction, so we need to further modify
8529 * the operand so that it will point to itself. There are
8530 * other cases where you have something like:
8532 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8534 * and here no correction would be required. Internally in
8535 * the assembler we treat operands of this form as not being
8536 * pcrel since the '.' is explicitly mentioned, and I wonder
8537 * whether it would simplify matters to do it this way. Who
8538 * knows. In earlier versions of the PIC patches, the
8539 * pcrel_adjust field was used to store the correction, but
8540 * since the expression is not pcrel, I felt it would be
8541 * confusing to do it this way. */
8543 if ((reloc_type
== BFD_RELOC_32
8544 || reloc_type
== BFD_RELOC_X86_64_32S
8545 || reloc_type
== BFD_RELOC_64
)
8547 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8548 && (i
.op
[n
].imms
->X_op
== O_symbol
8549 || (i
.op
[n
].imms
->X_op
== O_add
8550 && ((symbol_get_value_expression
8551 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8556 if (insn_start_frag
== frag_now
)
8557 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8562 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8563 for (fr
= insn_start_frag
->fr_next
;
8564 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8566 add
+= p
- frag_now
->fr_literal
;
8570 reloc_type
= BFD_RELOC_386_GOTPC
;
8572 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8574 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8575 i
.op
[n
].imms
->X_add_number
+= add
;
8577 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8578 i
.op
[n
].imms
, 0, reloc_type
);
8584 /* x86_cons_fix_new is called via the expression parsing code when a
8585 reloc is needed. We use this hook to get the correct .got reloc. */
8586 static int cons_sign
= -1;
8589 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8590 expressionS
*exp
, bfd_reloc_code_real_type r
)
8592 r
= reloc (len
, 0, cons_sign
, r
);
8595 if (exp
->X_op
== O_secrel
)
8597 exp
->X_op
= O_symbol
;
8598 r
= BFD_RELOC_32_SECREL
;
8602 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8605 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8606 purpose of the `.dc.a' internal pseudo-op. */
8609 x86_address_bytes (void)
8611 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8613 return stdoutput
->arch_info
->bits_per_address
/ 8;
8616 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8618 # define lex_got(reloc, adjust, types) NULL
8620 /* Parse operands of the form
8621 <symbol>@GOTOFF+<nnn>
8622 and similar .plt or .got references.
8624 If we find one, set up the correct relocation in RELOC and copy the
8625 input string, minus the `@GOTOFF' into a malloc'd buffer for
8626 parsing by the calling routine. Return this buffer, and if ADJUST
8627 is non-null set it to the length of the string we removed from the
8628 input line. Otherwise return NULL. */
8630 lex_got (enum bfd_reloc_code_real
*rel
,
8632 i386_operand_type
*types
)
8634 /* Some of the relocations depend on the size of what field is to
8635 be relocated. But in our callers i386_immediate and i386_displacement
8636 we don't yet know the operand size (this will be set by insn
8637 matching). Hence we record the word32 relocation here,
8638 and adjust the reloc according to the real size in reloc(). */
8639 static const struct {
8642 const enum bfd_reloc_code_real rel
[2];
8643 const i386_operand_type types64
;
8645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8646 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8648 OPERAND_TYPE_IMM32_64
},
8650 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8651 BFD_RELOC_X86_64_PLTOFF64
},
8652 OPERAND_TYPE_IMM64
},
8653 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8654 BFD_RELOC_X86_64_PLT32
},
8655 OPERAND_TYPE_IMM32_32S_DISP32
},
8656 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8657 BFD_RELOC_X86_64_GOTPLT64
},
8658 OPERAND_TYPE_IMM64_DISP64
},
8659 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8660 BFD_RELOC_X86_64_GOTOFF64
},
8661 OPERAND_TYPE_IMM64_DISP64
},
8662 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8663 BFD_RELOC_X86_64_GOTPCREL
},
8664 OPERAND_TYPE_IMM32_32S_DISP32
},
8665 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8666 BFD_RELOC_X86_64_TLSGD
},
8667 OPERAND_TYPE_IMM32_32S_DISP32
},
8668 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8669 _dummy_first_bfd_reloc_code_real
},
8670 OPERAND_TYPE_NONE
},
8671 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8672 BFD_RELOC_X86_64_TLSLD
},
8673 OPERAND_TYPE_IMM32_32S_DISP32
},
8674 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8675 BFD_RELOC_X86_64_GOTTPOFF
},
8676 OPERAND_TYPE_IMM32_32S_DISP32
},
8677 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8678 BFD_RELOC_X86_64_TPOFF32
},
8679 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8680 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8681 _dummy_first_bfd_reloc_code_real
},
8682 OPERAND_TYPE_NONE
},
8683 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8684 BFD_RELOC_X86_64_DTPOFF32
},
8685 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8686 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8687 _dummy_first_bfd_reloc_code_real
},
8688 OPERAND_TYPE_NONE
},
8689 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8690 _dummy_first_bfd_reloc_code_real
},
8691 OPERAND_TYPE_NONE
},
8692 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8693 BFD_RELOC_X86_64_GOT32
},
8694 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8695 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8696 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8697 OPERAND_TYPE_IMM32_32S_DISP32
},
8698 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8699 BFD_RELOC_X86_64_TLSDESC_CALL
},
8700 OPERAND_TYPE_IMM32_32S_DISP32
},
8705 #if defined (OBJ_MAYBE_ELF)
8710 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8711 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8714 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8716 int len
= gotrel
[j
].len
;
8717 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8719 if (gotrel
[j
].rel
[object_64bit
] != 0)
8722 char *tmpbuf
, *past_reloc
;
8724 *rel
= gotrel
[j
].rel
[object_64bit
];
8728 if (flag_code
!= CODE_64BIT
)
8730 types
->bitfield
.imm32
= 1;
8731 types
->bitfield
.disp32
= 1;
8734 *types
= gotrel
[j
].types64
;
8737 if (j
!= 0 && GOT_symbol
== NULL
)
8738 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8740 /* The length of the first part of our input line. */
8741 first
= cp
- input_line_pointer
;
8743 /* The second part goes from after the reloc token until
8744 (and including) an end_of_line char or comma. */
8745 past_reloc
= cp
+ 1 + len
;
8747 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8749 second
= cp
+ 1 - past_reloc
;
8751 /* Allocate and copy string. The trailing NUL shouldn't
8752 be necessary, but be safe. */
8753 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8754 memcpy (tmpbuf
, input_line_pointer
, first
);
8755 if (second
!= 0 && *past_reloc
!= ' ')
8756 /* Replace the relocation token with ' ', so that
8757 errors like foo@GOTOFF1 will be detected. */
8758 tmpbuf
[first
++] = ' ';
8760 /* Increment length by 1 if the relocation token is
8765 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8766 tmpbuf
[first
+ second
] = '\0';
8770 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8771 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8776 /* Might be a symbol version string. Don't as_bad here. */
8785 /* Parse operands of the form
8786 <symbol>@SECREL32+<nnn>
8788 If we find one, set up the correct relocation in RELOC and copy the
8789 input string, minus the `@SECREL32' into a malloc'd buffer for
8790 parsing by the calling routine. Return this buffer, and if ADJUST
8791 is non-null set it to the length of the string we removed from the
8792 input line. Otherwise return NULL.
8794 This function is copied from the ELF version above adjusted for PE targets. */
8797 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8798 int *adjust ATTRIBUTE_UNUSED
,
8799 i386_operand_type
*types
)
8805 const enum bfd_reloc_code_real rel
[2];
8806 const i386_operand_type types64
;
8810 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8811 BFD_RELOC_32_SECREL
},
8812 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8818 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8819 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8822 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8824 int len
= gotrel
[j
].len
;
8826 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8828 if (gotrel
[j
].rel
[object_64bit
] != 0)
8831 char *tmpbuf
, *past_reloc
;
8833 *rel
= gotrel
[j
].rel
[object_64bit
];
8839 if (flag_code
!= CODE_64BIT
)
8841 types
->bitfield
.imm32
= 1;
8842 types
->bitfield
.disp32
= 1;
8845 *types
= gotrel
[j
].types64
;
8848 /* The length of the first part of our input line. */
8849 first
= cp
- input_line_pointer
;
8851 /* The second part goes from after the reloc token until
8852 (and including) an end_of_line char or comma. */
8853 past_reloc
= cp
+ 1 + len
;
8855 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8857 second
= cp
+ 1 - past_reloc
;
8859 /* Allocate and copy string. The trailing NUL shouldn't
8860 be necessary, but be safe. */
8861 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8862 memcpy (tmpbuf
, input_line_pointer
, first
);
8863 if (second
!= 0 && *past_reloc
!= ' ')
8864 /* Replace the relocation token with ' ', so that
8865 errors like foo@SECLREL321 will be detected. */
8866 tmpbuf
[first
++] = ' ';
8867 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8868 tmpbuf
[first
+ second
] = '\0';
8872 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8873 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8878 /* Might be a symbol version string. Don't as_bad here. */
8884 bfd_reloc_code_real_type
8885 x86_cons (expressionS
*exp
, int size
)
8887 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8889 intel_syntax
= -intel_syntax
;
8892 if (size
== 4 || (object_64bit
&& size
== 8))
8894 /* Handle @GOTOFF and the like in an expression. */
8896 char *gotfree_input_line
;
8899 save
= input_line_pointer
;
8900 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8901 if (gotfree_input_line
)
8902 input_line_pointer
= gotfree_input_line
;
8906 if (gotfree_input_line
)
8908 /* expression () has merrily parsed up to the end of line,
8909 or a comma - in the wrong buffer. Transfer how far
8910 input_line_pointer has moved to the right buffer. */
8911 input_line_pointer
= (save
8912 + (input_line_pointer
- gotfree_input_line
)
8914 free (gotfree_input_line
);
8915 if (exp
->X_op
== O_constant
8916 || exp
->X_op
== O_absent
8917 || exp
->X_op
== O_illegal
8918 || exp
->X_op
== O_register
8919 || exp
->X_op
== O_big
)
8921 char c
= *input_line_pointer
;
8922 *input_line_pointer
= 0;
8923 as_bad (_("missing or invalid expression `%s'"), save
);
8924 *input_line_pointer
= c
;
8926 else if ((got_reloc
== BFD_RELOC_386_PLT32
8927 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
8928 && exp
->X_op
!= O_symbol
)
8930 char c
= *input_line_pointer
;
8931 *input_line_pointer
= 0;
8932 as_bad (_("invalid PLT expression `%s'"), save
);
8933 *input_line_pointer
= c
;
8940 intel_syntax
= -intel_syntax
;
8943 i386_intel_simplify (exp
);
8949 signed_cons (int size
)
8951 if (flag_code
== CODE_64BIT
)
8959 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8966 if (exp
.X_op
== O_symbol
)
8967 exp
.X_op
= O_secrel
;
8969 emit_expr (&exp
, 4);
8971 while (*input_line_pointer
++ == ',');
8973 input_line_pointer
--;
8974 demand_empty_rest_of_line ();
8978 /* Handle Vector operations. */
8981 check_VecOperations (char *op_string
, char *op_end
)
8983 const reg_entry
*mask
;
8988 && (op_end
== NULL
|| op_string
< op_end
))
8991 if (*op_string
== '{')
8995 /* Check broadcasts. */
8996 if (strncmp (op_string
, "1to", 3) == 0)
9001 goto duplicated_vec_op
;
9004 if (*op_string
== '8')
9006 else if (*op_string
== '4')
9008 else if (*op_string
== '2')
9010 else if (*op_string
== '1'
9011 && *(op_string
+1) == '6')
9018 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9023 broadcast_op
.type
= bcst_type
;
9024 broadcast_op
.operand
= this_operand
;
9025 broadcast_op
.bytes
= 0;
9026 i
.broadcast
= &broadcast_op
;
9028 /* Check masking operation. */
9029 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9031 /* k0 can't be used for write mask. */
9032 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9034 as_bad (_("`%s%s' can't be used for write mask"),
9035 register_prefix
, mask
->reg_name
);
9041 mask_op
.mask
= mask
;
9042 mask_op
.zeroing
= 0;
9043 mask_op
.operand
= this_operand
;
9049 goto duplicated_vec_op
;
9051 i
.mask
->mask
= mask
;
9053 /* Only "{z}" is allowed here. No need to check
9054 zeroing mask explicitly. */
9055 if (i
.mask
->operand
!= this_operand
)
9057 as_bad (_("invalid write mask `%s'"), saved
);
9064 /* Check zeroing-flag for masking operation. */
9065 else if (*op_string
== 'z')
9069 mask_op
.mask
= NULL
;
9070 mask_op
.zeroing
= 1;
9071 mask_op
.operand
= this_operand
;
9076 if (i
.mask
->zeroing
)
9079 as_bad (_("duplicated `%s'"), saved
);
9083 i
.mask
->zeroing
= 1;
9085 /* Only "{%k}" is allowed here. No need to check mask
9086 register explicitly. */
9087 if (i
.mask
->operand
!= this_operand
)
9089 as_bad (_("invalid zeroing-masking `%s'"),
9098 goto unknown_vec_op
;
9100 if (*op_string
!= '}')
9102 as_bad (_("missing `}' in `%s'"), saved
);
9107 /* Strip whitespace since the addition of pseudo prefixes
9108 changed how the scrubber treats '{'. */
9109 if (is_space_char (*op_string
))
9115 /* We don't know this one. */
9116 as_bad (_("unknown vector operation: `%s'"), saved
);
9120 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9122 as_bad (_("zeroing-masking only allowed with write mask"));
9130 i386_immediate (char *imm_start
)
9132 char *save_input_line_pointer
;
9133 char *gotfree_input_line
;
9136 i386_operand_type types
;
9138 operand_type_set (&types
, ~0);
9140 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9142 as_bad (_("at most %d immediate operands are allowed"),
9143 MAX_IMMEDIATE_OPERANDS
);
9147 exp
= &im_expressions
[i
.imm_operands
++];
9148 i
.op
[this_operand
].imms
= exp
;
9150 if (is_space_char (*imm_start
))
9153 save_input_line_pointer
= input_line_pointer
;
9154 input_line_pointer
= imm_start
;
9156 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9157 if (gotfree_input_line
)
9158 input_line_pointer
= gotfree_input_line
;
9160 exp_seg
= expression (exp
);
9164 /* Handle vector operations. */
9165 if (*input_line_pointer
== '{')
9167 input_line_pointer
= check_VecOperations (input_line_pointer
,
9169 if (input_line_pointer
== NULL
)
9173 if (*input_line_pointer
)
9174 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9176 input_line_pointer
= save_input_line_pointer
;
9177 if (gotfree_input_line
)
9179 free (gotfree_input_line
);
9181 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9182 exp
->X_op
= O_illegal
;
9185 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9189 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9190 i386_operand_type types
, const char *imm_start
)
9192 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9195 as_bad (_("missing or invalid immediate expression `%s'"),
9199 else if (exp
->X_op
== O_constant
)
9201 /* Size it properly later. */
9202 i
.types
[this_operand
].bitfield
.imm64
= 1;
9203 /* If not 64bit, sign extend val. */
9204 if (flag_code
!= CODE_64BIT
9205 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9207 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9209 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9210 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9211 && exp_seg
!= absolute_section
9212 && exp_seg
!= text_section
9213 && exp_seg
!= data_section
9214 && exp_seg
!= bss_section
9215 && exp_seg
!= undefined_section
9216 && !bfd_is_com_section (exp_seg
))
9218 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9222 else if (!intel_syntax
&& exp_seg
== reg_section
)
9225 as_bad (_("illegal immediate register operand %s"), imm_start
);
9230 /* This is an address. The size of the address will be
9231 determined later, depending on destination register,
9232 suffix, or the default for the section. */
9233 i
.types
[this_operand
].bitfield
.imm8
= 1;
9234 i
.types
[this_operand
].bitfield
.imm16
= 1;
9235 i
.types
[this_operand
].bitfield
.imm32
= 1;
9236 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9237 i
.types
[this_operand
].bitfield
.imm64
= 1;
9238 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9246 i386_scale (char *scale
)
9249 char *save
= input_line_pointer
;
9251 input_line_pointer
= scale
;
9252 val
= get_absolute_expression ();
9257 i
.log2_scale_factor
= 0;
9260 i
.log2_scale_factor
= 1;
9263 i
.log2_scale_factor
= 2;
9266 i
.log2_scale_factor
= 3;
9270 char sep
= *input_line_pointer
;
9272 *input_line_pointer
= '\0';
9273 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9275 *input_line_pointer
= sep
;
9276 input_line_pointer
= save
;
9280 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9282 as_warn (_("scale factor of %d without an index register"),
9283 1 << i
.log2_scale_factor
);
9284 i
.log2_scale_factor
= 0;
9286 scale
= input_line_pointer
;
9287 input_line_pointer
= save
;
9292 i386_displacement (char *disp_start
, char *disp_end
)
9296 char *save_input_line_pointer
;
9297 char *gotfree_input_line
;
9299 i386_operand_type bigdisp
, types
= anydisp
;
9302 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9304 as_bad (_("at most %d displacement operands are allowed"),
9305 MAX_MEMORY_OPERANDS
);
9309 operand_type_set (&bigdisp
, 0);
9310 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9311 || (!current_templates
->start
->opcode_modifier
.jump
9312 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9314 bigdisp
.bitfield
.disp32
= 1;
9315 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9316 if (flag_code
== CODE_64BIT
)
9320 bigdisp
.bitfield
.disp32s
= 1;
9321 bigdisp
.bitfield
.disp64
= 1;
9324 else if ((flag_code
== CODE_16BIT
) ^ override
)
9326 bigdisp
.bitfield
.disp32
= 0;
9327 bigdisp
.bitfield
.disp16
= 1;
9332 /* For PC-relative branches, the width of the displacement
9333 is dependent upon data size, not address size. */
9334 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9335 if (flag_code
== CODE_64BIT
)
9337 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9338 bigdisp
.bitfield
.disp16
= 1;
9341 bigdisp
.bitfield
.disp32
= 1;
9342 bigdisp
.bitfield
.disp32s
= 1;
9348 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9350 : LONG_MNEM_SUFFIX
));
9351 bigdisp
.bitfield
.disp32
= 1;
9352 if ((flag_code
== CODE_16BIT
) ^ override
)
9354 bigdisp
.bitfield
.disp32
= 0;
9355 bigdisp
.bitfield
.disp16
= 1;
9359 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9362 exp
= &disp_expressions
[i
.disp_operands
];
9363 i
.op
[this_operand
].disps
= exp
;
9365 save_input_line_pointer
= input_line_pointer
;
9366 input_line_pointer
= disp_start
;
9367 END_STRING_AND_SAVE (disp_end
);
9369 #ifndef GCC_ASM_O_HACK
9370 #define GCC_ASM_O_HACK 0
9373 END_STRING_AND_SAVE (disp_end
+ 1);
9374 if (i
.types
[this_operand
].bitfield
.baseIndex
9375 && displacement_string_end
[-1] == '+')
9377 /* This hack is to avoid a warning when using the "o"
9378 constraint within gcc asm statements.
9381 #define _set_tssldt_desc(n,addr,limit,type) \
9382 __asm__ __volatile__ ( \
9384 "movw %w1,2+%0\n\t" \
9386 "movb %b1,4+%0\n\t" \
9387 "movb %4,5+%0\n\t" \
9388 "movb $0,6+%0\n\t" \
9389 "movb %h1,7+%0\n\t" \
9391 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9393 This works great except that the output assembler ends
9394 up looking a bit weird if it turns out that there is
9395 no offset. You end up producing code that looks like:
9408 So here we provide the missing zero. */
9410 *displacement_string_end
= '0';
9413 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9414 if (gotfree_input_line
)
9415 input_line_pointer
= gotfree_input_line
;
9417 exp_seg
= expression (exp
);
9420 if (*input_line_pointer
)
9421 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9423 RESTORE_END_STRING (disp_end
+ 1);
9425 input_line_pointer
= save_input_line_pointer
;
9426 if (gotfree_input_line
)
9428 free (gotfree_input_line
);
9430 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9431 exp
->X_op
= O_illegal
;
9434 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9436 RESTORE_END_STRING (disp_end
);
9442 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9443 i386_operand_type types
, const char *disp_start
)
9445 i386_operand_type bigdisp
;
9448 /* We do this to make sure that the section symbol is in
9449 the symbol table. We will ultimately change the relocation
9450 to be relative to the beginning of the section. */
9451 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9452 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9453 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9455 if (exp
->X_op
!= O_symbol
)
9458 if (S_IS_LOCAL (exp
->X_add_symbol
)
9459 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9460 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9461 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9462 exp
->X_op
= O_subtract
;
9463 exp
->X_op_symbol
= GOT_symbol
;
9464 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9465 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9466 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9467 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9469 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9472 else if (exp
->X_op
== O_absent
9473 || exp
->X_op
== O_illegal
9474 || exp
->X_op
== O_big
)
9477 as_bad (_("missing or invalid displacement expression `%s'"),
9482 else if (flag_code
== CODE_64BIT
9483 && !i
.prefix
[ADDR_PREFIX
]
9484 && exp
->X_op
== O_constant
)
9486 /* Since displacement is signed extended to 64bit, don't allow
9487 disp32 and turn off disp32s if they are out of range. */
9488 i
.types
[this_operand
].bitfield
.disp32
= 0;
9489 if (!fits_in_signed_long (exp
->X_add_number
))
9491 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9492 if (i
.types
[this_operand
].bitfield
.baseindex
)
9494 as_bad (_("0x%lx out range of signed 32bit displacement"),
9495 (long) exp
->X_add_number
);
9501 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9502 else if (exp
->X_op
!= O_constant
9503 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9504 && exp_seg
!= absolute_section
9505 && exp_seg
!= text_section
9506 && exp_seg
!= data_section
9507 && exp_seg
!= bss_section
9508 && exp_seg
!= undefined_section
9509 && !bfd_is_com_section (exp_seg
))
9511 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9516 /* Check if this is a displacement only operand. */
9517 bigdisp
= i
.types
[this_operand
];
9518 bigdisp
.bitfield
.disp8
= 0;
9519 bigdisp
.bitfield
.disp16
= 0;
9520 bigdisp
.bitfield
.disp32
= 0;
9521 bigdisp
.bitfield
.disp32s
= 0;
9522 bigdisp
.bitfield
.disp64
= 0;
9523 if (operand_type_all_zero (&bigdisp
))
9524 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9530 /* Return the active addressing mode, taking address override and
9531 registers forming the address into consideration. Update the
9532 address override prefix if necessary. */
9534 static enum flag_code
9535 i386_addressing_mode (void)
9537 enum flag_code addr_mode
;
9539 if (i
.prefix
[ADDR_PREFIX
])
9540 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9543 addr_mode
= flag_code
;
9545 #if INFER_ADDR_PREFIX
9546 if (i
.mem_operands
== 0)
9548 /* Infer address prefix from the first memory operand. */
9549 const reg_entry
*addr_reg
= i
.base_reg
;
9551 if (addr_reg
== NULL
)
9552 addr_reg
= i
.index_reg
;
9556 if (addr_reg
->reg_type
.bitfield
.dword
)
9557 addr_mode
= CODE_32BIT
;
9558 else if (flag_code
!= CODE_64BIT
9559 && addr_reg
->reg_type
.bitfield
.word
)
9560 addr_mode
= CODE_16BIT
;
9562 if (addr_mode
!= flag_code
)
9564 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9566 /* Change the size of any displacement too. At most one
9567 of Disp16 or Disp32 is set.
9568 FIXME. There doesn't seem to be any real need for
9569 separate Disp16 and Disp32 flags. The same goes for
9570 Imm16 and Imm32. Removing them would probably clean
9571 up the code quite a lot. */
9572 if (flag_code
!= CODE_64BIT
9573 && (i
.types
[this_operand
].bitfield
.disp16
9574 || i
.types
[this_operand
].bitfield
.disp32
))
9575 i
.types
[this_operand
]
9576 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9586 /* Make sure the memory operand we've been dealt is valid.
9587 Return 1 on success, 0 on a failure. */
9590 i386_index_check (const char *operand_string
)
9592 const char *kind
= "base/index";
9593 enum flag_code addr_mode
= i386_addressing_mode ();
9595 if (current_templates
->start
->opcode_modifier
.isstring
9596 && !current_templates
->start
->opcode_modifier
.immext
9597 && (current_templates
->end
[-1].opcode_modifier
.isstring
9600 /* Memory operands of string insns are special in that they only allow
9601 a single register (rDI, rSI, or rBX) as their memory address. */
9602 const reg_entry
*expected_reg
;
9603 static const char *di_si
[][2] =
9609 static const char *bx
[] = { "ebx", "bx", "rbx" };
9611 kind
= "string address";
9613 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9615 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9617 if (!type
.bitfield
.baseindex
9618 || ((!i
.mem_operands
!= !intel_syntax
)
9619 && current_templates
->end
[-1].operand_types
[1]
9620 .bitfield
.baseindex
))
9621 type
= current_templates
->end
[-1].operand_types
[1];
9622 expected_reg
= hash_find (reg_hash
,
9623 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9627 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9629 if (i
.base_reg
!= expected_reg
9631 || operand_type_check (i
.types
[this_operand
], disp
))
9633 /* The second memory operand must have the same size as
9637 && !((addr_mode
== CODE_64BIT
9638 && i
.base_reg
->reg_type
.bitfield
.qword
)
9639 || (addr_mode
== CODE_32BIT
9640 ? i
.base_reg
->reg_type
.bitfield
.dword
9641 : i
.base_reg
->reg_type
.bitfield
.word
)))
9644 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9646 intel_syntax
? '[' : '(',
9648 expected_reg
->reg_name
,
9649 intel_syntax
? ']' : ')');
9656 as_bad (_("`%s' is not a valid %s expression"),
9657 operand_string
, kind
);
9662 if (addr_mode
!= CODE_16BIT
)
9664 /* 32-bit/64-bit checks. */
9666 && ((addr_mode
== CODE_64BIT
9667 ? !i
.base_reg
->reg_type
.bitfield
.qword
9668 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9669 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9670 || i
.base_reg
->reg_num
== RegIZ
))
9672 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9673 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9674 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9675 && ((addr_mode
== CODE_64BIT
9676 ? !i
.index_reg
->reg_type
.bitfield
.qword
9677 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9678 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9681 /* bndmk, bndldx, and bndstx have special restrictions. */
9682 if (current_templates
->start
->base_opcode
== 0xf30f1b
9683 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9685 /* They cannot use RIP-relative addressing. */
9686 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9688 as_bad (_("`%s' cannot be used here"), operand_string
);
9692 /* bndldx and bndstx ignore their scale factor. */
9693 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9694 && i
.log2_scale_factor
)
9695 as_warn (_("register scaling is being ignored here"));
9700 /* 16-bit checks. */
9702 && (!i
.base_reg
->reg_type
.bitfield
.word
9703 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9705 && (!i
.index_reg
->reg_type
.bitfield
.word
9706 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9708 && i
.base_reg
->reg_num
< 6
9709 && i
.index_reg
->reg_num
>= 6
9710 && i
.log2_scale_factor
== 0))))
9717 /* Handle vector immediates. */
9720 RC_SAE_immediate (const char *imm_start
)
9722 unsigned int match_found
, j
;
9723 const char *pstr
= imm_start
;
9731 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9733 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9737 rc_op
.type
= RC_NamesTable
[j
].type
;
9738 rc_op
.operand
= this_operand
;
9739 i
.rounding
= &rc_op
;
9743 as_bad (_("duplicated `%s'"), imm_start
);
9746 pstr
+= RC_NamesTable
[j
].len
;
9756 as_bad (_("Missing '}': '%s'"), imm_start
);
9759 /* RC/SAE immediate string should contain nothing more. */;
9762 as_bad (_("Junk after '}': '%s'"), imm_start
);
9766 exp
= &im_expressions
[i
.imm_operands
++];
9767 i
.op
[this_operand
].imms
= exp
;
9769 exp
->X_op
= O_constant
;
9770 exp
->X_add_number
= 0;
9771 exp
->X_add_symbol
= (symbolS
*) 0;
9772 exp
->X_op_symbol
= (symbolS
*) 0;
9774 i
.types
[this_operand
].bitfield
.imm8
= 1;
9778 /* Only string instructions can have a second memory operand, so
9779 reduce current_templates to just those if it contains any. */
9781 maybe_adjust_templates (void)
9783 const insn_template
*t
;
9785 gas_assert (i
.mem_operands
== 1);
9787 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9788 if (t
->opcode_modifier
.isstring
)
9791 if (t
< current_templates
->end
)
9793 static templates aux_templates
;
9794 bfd_boolean recheck
;
9796 aux_templates
.start
= t
;
9797 for (; t
< current_templates
->end
; ++t
)
9798 if (!t
->opcode_modifier
.isstring
)
9800 aux_templates
.end
= t
;
9802 /* Determine whether to re-check the first memory operand. */
9803 recheck
= (aux_templates
.start
!= current_templates
->start
9804 || t
!= current_templates
->end
);
9806 current_templates
= &aux_templates
;
9811 if (i
.memop1_string
!= NULL
9812 && i386_index_check (i
.memop1_string
) == 0)
9821 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9825 i386_att_operand (char *operand_string
)
9829 char *op_string
= operand_string
;
9831 if (is_space_char (*op_string
))
9834 /* We check for an absolute prefix (differentiating,
9835 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9836 if (*op_string
== ABSOLUTE_PREFIX
)
9839 if (is_space_char (*op_string
))
9841 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9844 /* Check if operand is a register. */
9845 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9847 i386_operand_type temp
;
9849 /* Check for a segment override by searching for ':' after a
9850 segment register. */
9852 if (is_space_char (*op_string
))
9854 if (*op_string
== ':'
9855 && (r
->reg_type
.bitfield
.sreg2
9856 || r
->reg_type
.bitfield
.sreg3
))
9861 i
.seg
[i
.mem_operands
] = &es
;
9864 i
.seg
[i
.mem_operands
] = &cs
;
9867 i
.seg
[i
.mem_operands
] = &ss
;
9870 i
.seg
[i
.mem_operands
] = &ds
;
9873 i
.seg
[i
.mem_operands
] = &fs
;
9876 i
.seg
[i
.mem_operands
] = &gs
;
9880 /* Skip the ':' and whitespace. */
9882 if (is_space_char (*op_string
))
9885 if (!is_digit_char (*op_string
)
9886 && !is_identifier_char (*op_string
)
9887 && *op_string
!= '('
9888 && *op_string
!= ABSOLUTE_PREFIX
)
9890 as_bad (_("bad memory operand `%s'"), op_string
);
9893 /* Handle case of %es:*foo. */
9894 if (*op_string
== ABSOLUTE_PREFIX
)
9897 if (is_space_char (*op_string
))
9899 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9901 goto do_memory_reference
;
9904 /* Handle vector operations. */
9905 if (*op_string
== '{')
9907 op_string
= check_VecOperations (op_string
, NULL
);
9908 if (op_string
== NULL
)
9914 as_bad (_("junk `%s' after register"), op_string
);
9918 temp
.bitfield
.baseindex
= 0;
9919 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9921 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9922 i
.op
[this_operand
].regs
= r
;
9925 else if (*op_string
== REGISTER_PREFIX
)
9927 as_bad (_("bad register name `%s'"), op_string
);
9930 else if (*op_string
== IMMEDIATE_PREFIX
)
9933 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9935 as_bad (_("immediate operand illegal with absolute jump"));
9938 if (!i386_immediate (op_string
))
9941 else if (RC_SAE_immediate (operand_string
))
9943 /* If it is a RC or SAE immediate, do nothing. */
9946 else if (is_digit_char (*op_string
)
9947 || is_identifier_char (*op_string
)
9948 || *op_string
== '"'
9949 || *op_string
== '(')
9951 /* This is a memory reference of some sort. */
9954 /* Start and end of displacement string expression (if found). */
9955 char *displacement_string_start
;
9956 char *displacement_string_end
;
9959 do_memory_reference
:
9960 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9962 if ((i
.mem_operands
== 1
9963 && !current_templates
->start
->opcode_modifier
.isstring
)
9964 || i
.mem_operands
== 2)
9966 as_bad (_("too many memory references for `%s'"),
9967 current_templates
->start
->name
);
9971 /* Check for base index form. We detect the base index form by
9972 looking for an ')' at the end of the operand, searching
9973 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9975 base_string
= op_string
+ strlen (op_string
);
9977 /* Handle vector operations. */
9978 vop_start
= strchr (op_string
, '{');
9979 if (vop_start
&& vop_start
< base_string
)
9981 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9983 base_string
= vop_start
;
9987 if (is_space_char (*base_string
))
9990 /* If we only have a displacement, set-up for it to be parsed later. */
9991 displacement_string_start
= op_string
;
9992 displacement_string_end
= base_string
+ 1;
9994 if (*base_string
== ')')
9997 unsigned int parens_balanced
= 1;
9998 /* We've already checked that the number of left & right ()'s are
9999 equal, so this loop will not be infinite. */
10003 if (*base_string
== ')')
10005 if (*base_string
== '(')
10008 while (parens_balanced
);
10010 temp_string
= base_string
;
10012 /* Skip past '(' and whitespace. */
10014 if (is_space_char (*base_string
))
10017 if (*base_string
== ','
10018 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10021 displacement_string_end
= temp_string
;
10023 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10027 base_string
= end_op
;
10028 if (is_space_char (*base_string
))
10032 /* There may be an index reg or scale factor here. */
10033 if (*base_string
== ',')
10036 if (is_space_char (*base_string
))
10039 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10042 base_string
= end_op
;
10043 if (is_space_char (*base_string
))
10045 if (*base_string
== ',')
10048 if (is_space_char (*base_string
))
10051 else if (*base_string
!= ')')
10053 as_bad (_("expecting `,' or `)' "
10054 "after index register in `%s'"),
10059 else if (*base_string
== REGISTER_PREFIX
)
10061 end_op
= strchr (base_string
, ',');
10064 as_bad (_("bad register name `%s'"), base_string
);
10068 /* Check for scale factor. */
10069 if (*base_string
!= ')')
10071 char *end_scale
= i386_scale (base_string
);
10076 base_string
= end_scale
;
10077 if (is_space_char (*base_string
))
10079 if (*base_string
!= ')')
10081 as_bad (_("expecting `)' "
10082 "after scale factor in `%s'"),
10087 else if (!i
.index_reg
)
10089 as_bad (_("expecting index register or scale factor "
10090 "after `,'; got '%c'"),
10095 else if (*base_string
!= ')')
10097 as_bad (_("expecting `,' or `)' "
10098 "after base register in `%s'"),
10103 else if (*base_string
== REGISTER_PREFIX
)
10105 end_op
= strchr (base_string
, ',');
10108 as_bad (_("bad register name `%s'"), base_string
);
10113 /* If there's an expression beginning the operand, parse it,
10114 assuming displacement_string_start and
10115 displacement_string_end are meaningful. */
10116 if (displacement_string_start
!= displacement_string_end
)
10118 if (!i386_displacement (displacement_string_start
,
10119 displacement_string_end
))
10123 /* Special case for (%dx) while doing input/output op. */
10125 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10126 && i
.index_reg
== 0
10127 && i
.log2_scale_factor
== 0
10128 && i
.seg
[i
.mem_operands
] == 0
10129 && !operand_type_check (i
.types
[this_operand
], disp
))
10131 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10135 if (i386_index_check (operand_string
) == 0)
10137 i
.flags
[this_operand
] |= Operand_Mem
;
10138 if (i
.mem_operands
== 0)
10139 i
.memop1_string
= xstrdup (operand_string
);
10144 /* It's not a memory operand; argh! */
10145 as_bad (_("invalid char %s beginning operand %d `%s'"),
10146 output_invalid (*op_string
),
10151 return 1; /* Normal return. */
10154 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10155 that an rs_machine_dependent frag may reach. */
10158 i386_frag_max_var (fragS
*frag
)
10160 /* The only relaxable frags are for jumps.
10161 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10162 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10163 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10168 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10170 /* STT_GNU_IFUNC symbol must go through PLT. */
10171 if ((symbol_get_bfdsym (fr_symbol
)->flags
10172 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10175 if (!S_IS_EXTERNAL (fr_symbol
))
10176 /* Symbol may be weak or local. */
10177 return !S_IS_WEAK (fr_symbol
);
10179 /* Global symbols with non-default visibility can't be preempted. */
10180 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10183 if (fr_var
!= NO_RELOC
)
10184 switch ((enum bfd_reloc_code_real
) fr_var
)
10186 case BFD_RELOC_386_PLT32
:
10187 case BFD_RELOC_X86_64_PLT32
:
10188 /* Symbol with PLT relocation may be preempted. */
10194 /* Global symbols with default visibility in a shared library may be
10195 preempted by another definition. */
10200 /* md_estimate_size_before_relax()
10202 Called just before relax() for rs_machine_dependent frags. The x86
10203 assembler uses these frags to handle variable size jump
10206 Any symbol that is now undefined will not become defined.
10207 Return the correct fr_subtype in the frag.
10208 Return the initial "guess for variable size of frag" to caller.
10209 The guess is actually the growth beyond the fixed part. Whatever
10210 we do to grow the fixed or variable part contributes to our
10214 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10216 /* We've already got fragP->fr_subtype right; all we have to do is
10217 check for un-relaxable symbols. On an ELF system, we can't relax
10218 an externally visible symbol, because it may be overridden by a
10220 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10221 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10223 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10226 #if defined (OBJ_COFF) && defined (TE_PE)
10227 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10228 && S_IS_WEAK (fragP
->fr_symbol
))
10232 /* Symbol is undefined in this segment, or we need to keep a
10233 reloc so that weak symbols can be overridden. */
10234 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10235 enum bfd_reloc_code_real reloc_type
;
10236 unsigned char *opcode
;
10239 if (fragP
->fr_var
!= NO_RELOC
)
10240 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10241 else if (size
== 2)
10242 reloc_type
= BFD_RELOC_16_PCREL
;
10243 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10244 else if (need_plt32_p (fragP
->fr_symbol
))
10245 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10248 reloc_type
= BFD_RELOC_32_PCREL
;
10250 old_fr_fix
= fragP
->fr_fix
;
10251 opcode
= (unsigned char *) fragP
->fr_opcode
;
10253 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10256 /* Make jmp (0xeb) a (d)word displacement jump. */
10258 fragP
->fr_fix
+= size
;
10259 fix_new (fragP
, old_fr_fix
, size
,
10261 fragP
->fr_offset
, 1,
10267 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10269 /* Negate the condition, and branch past an
10270 unconditional jump. */
10273 /* Insert an unconditional jump. */
10275 /* We added two extra opcode bytes, and have a two byte
10277 fragP
->fr_fix
+= 2 + 2;
10278 fix_new (fragP
, old_fr_fix
+ 2, 2,
10280 fragP
->fr_offset
, 1,
10284 /* Fall through. */
10287 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10291 fragP
->fr_fix
+= 1;
10292 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10294 fragP
->fr_offset
, 1,
10295 BFD_RELOC_8_PCREL
);
10296 fixP
->fx_signed
= 1;
10300 /* This changes the byte-displacement jump 0x7N
10301 to the (d)word-displacement jump 0x0f,0x8N. */
10302 opcode
[1] = opcode
[0] + 0x10;
10303 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10304 /* We've added an opcode byte. */
10305 fragP
->fr_fix
+= 1 + size
;
10306 fix_new (fragP
, old_fr_fix
+ 1, size
,
10308 fragP
->fr_offset
, 1,
10313 BAD_CASE (fragP
->fr_subtype
);
10317 return fragP
->fr_fix
- old_fr_fix
;
10320 /* Guess size depending on current relax state. Initially the relax
10321 state will correspond to a short jump and we return 1, because
10322 the variable part of the frag (the branch offset) is one byte
10323 long. However, we can relax a section more than once and in that
10324 case we must either set fr_subtype back to the unrelaxed state,
10325 or return the value for the appropriate branch. */
10326 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10329 /* Called after relax() is finished.
10331 In: Address of frag.
10332 fr_type == rs_machine_dependent.
10333 fr_subtype is what the address relaxed to.
10335 Out: Any fixSs and constants are set up.
10336 Caller will turn frag into a ".space 0". */
10339 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10342 unsigned char *opcode
;
10343 unsigned char *where_to_put_displacement
= NULL
;
10344 offsetT target_address
;
10345 offsetT opcode_address
;
10346 unsigned int extension
= 0;
10347 offsetT displacement_from_opcode_start
;
10349 opcode
= (unsigned char *) fragP
->fr_opcode
;
10351 /* Address we want to reach in file space. */
10352 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10354 /* Address opcode resides at in file space. */
10355 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10357 /* Displacement from opcode start to fill into instruction. */
10358 displacement_from_opcode_start
= target_address
- opcode_address
;
10360 if ((fragP
->fr_subtype
& BIG
) == 0)
10362 /* Don't have to change opcode. */
10363 extension
= 1; /* 1 opcode + 1 displacement */
10364 where_to_put_displacement
= &opcode
[1];
10368 if (no_cond_jump_promotion
10369 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10370 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10371 _("long jump required"));
10373 switch (fragP
->fr_subtype
)
10375 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10376 extension
= 4; /* 1 opcode + 4 displacement */
10378 where_to_put_displacement
= &opcode
[1];
10381 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10382 extension
= 2; /* 1 opcode + 2 displacement */
10384 where_to_put_displacement
= &opcode
[1];
10387 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10388 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10389 extension
= 5; /* 2 opcode + 4 displacement */
10390 opcode
[1] = opcode
[0] + 0x10;
10391 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10392 where_to_put_displacement
= &opcode
[2];
10395 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10396 extension
= 3; /* 2 opcode + 2 displacement */
10397 opcode
[1] = opcode
[0] + 0x10;
10398 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10399 where_to_put_displacement
= &opcode
[2];
10402 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10407 where_to_put_displacement
= &opcode
[3];
10411 BAD_CASE (fragP
->fr_subtype
);
10416 /* If size if less then four we are sure that the operand fits,
10417 but if it's 4, then it could be that the displacement is larger
10419 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10421 && ((addressT
) (displacement_from_opcode_start
- extension
10422 + ((addressT
) 1 << 31))
10423 > (((addressT
) 2 << 31) - 1)))
10425 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10426 _("jump target out of range"));
10427 /* Make us emit 0. */
10428 displacement_from_opcode_start
= extension
;
10430 /* Now put displacement after opcode. */
10431 md_number_to_chars ((char *) where_to_put_displacement
,
10432 (valueT
) (displacement_from_opcode_start
- extension
),
10433 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10434 fragP
->fr_fix
+= extension
;
10437 /* Apply a fixup (fixP) to segment data, once it has been determined
10438 by our caller that we have all the info we need to fix it up.
10440 Parameter valP is the pointer to the value of the bits.
10442 On the 386, immediates, displacements, and data pointers are all in
10443 the same (little-endian) format, so we don't need to care about which
10444 we are handling. */
10447 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10449 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10450 valueT value
= *valP
;
10452 #if !defined (TE_Mach)
10453 if (fixP
->fx_pcrel
)
10455 switch (fixP
->fx_r_type
)
10461 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10464 case BFD_RELOC_X86_64_32S
:
10465 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10468 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10471 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10476 if (fixP
->fx_addsy
!= NULL
10477 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10478 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10479 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10480 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10481 && !use_rela_relocations
)
10483 /* This is a hack. There should be a better way to handle this.
10484 This covers for the fact that bfd_install_relocation will
10485 subtract the current location (for partial_inplace, PC relative
10486 relocations); see more below. */
10490 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10493 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10495 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10498 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10500 if ((sym_seg
== seg
10501 || (symbol_section_p (fixP
->fx_addsy
)
10502 && sym_seg
!= absolute_section
))
10503 && !generic_force_reloc (fixP
))
10505 /* Yes, we add the values in twice. This is because
10506 bfd_install_relocation subtracts them out again. I think
10507 bfd_install_relocation is broken, but I don't dare change
10509 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10513 #if defined (OBJ_COFF) && defined (TE_PE)
10514 /* For some reason, the PE format does not store a
10515 section address offset for a PC relative symbol. */
10516 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10517 || S_IS_WEAK (fixP
->fx_addsy
))
10518 value
+= md_pcrel_from (fixP
);
10521 #if defined (OBJ_COFF) && defined (TE_PE)
10522 if (fixP
->fx_addsy
!= NULL
10523 && S_IS_WEAK (fixP
->fx_addsy
)
10524 /* PR 16858: Do not modify weak function references. */
10525 && ! fixP
->fx_pcrel
)
10527 #if !defined (TE_PEP)
10528 /* For x86 PE weak function symbols are neither PC-relative
10529 nor do they set S_IS_FUNCTION. So the only reliable way
10530 to detect them is to check the flags of their containing
10532 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10533 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10537 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10541 /* Fix a few things - the dynamic linker expects certain values here,
10542 and we must not disappoint it. */
10543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10544 if (IS_ELF
&& fixP
->fx_addsy
)
10545 switch (fixP
->fx_r_type
)
10547 case BFD_RELOC_386_PLT32
:
10548 case BFD_RELOC_X86_64_PLT32
:
10549 /* Make the jump instruction point to the address of the operand.
10550 At runtime we merely add the offset to the actual PLT entry.
10551 NB: Subtract the offset size only for jump instructions. */
10552 if (fixP
->fx_pcrel
)
10556 case BFD_RELOC_386_TLS_GD
:
10557 case BFD_RELOC_386_TLS_LDM
:
10558 case BFD_RELOC_386_TLS_IE_32
:
10559 case BFD_RELOC_386_TLS_IE
:
10560 case BFD_RELOC_386_TLS_GOTIE
:
10561 case BFD_RELOC_386_TLS_GOTDESC
:
10562 case BFD_RELOC_X86_64_TLSGD
:
10563 case BFD_RELOC_X86_64_TLSLD
:
10564 case BFD_RELOC_X86_64_GOTTPOFF
:
10565 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10566 value
= 0; /* Fully resolved at runtime. No addend. */
10568 case BFD_RELOC_386_TLS_LE
:
10569 case BFD_RELOC_386_TLS_LDO_32
:
10570 case BFD_RELOC_386_TLS_LE_32
:
10571 case BFD_RELOC_X86_64_DTPOFF32
:
10572 case BFD_RELOC_X86_64_DTPOFF64
:
10573 case BFD_RELOC_X86_64_TPOFF32
:
10574 case BFD_RELOC_X86_64_TPOFF64
:
10575 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10578 case BFD_RELOC_386_TLS_DESC_CALL
:
10579 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10580 value
= 0; /* Fully resolved at runtime. No addend. */
10581 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10585 case BFD_RELOC_VTABLE_INHERIT
:
10586 case BFD_RELOC_VTABLE_ENTRY
:
10593 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10595 #endif /* !defined (TE_Mach) */
10597 /* Are we finished with this relocation now? */
10598 if (fixP
->fx_addsy
== NULL
)
10600 #if defined (OBJ_COFF) && defined (TE_PE)
10601 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10604 /* Remember value for tc_gen_reloc. */
10605 fixP
->fx_addnumber
= value
;
10606 /* Clear out the frag for now. */
10610 else if (use_rela_relocations
)
10612 fixP
->fx_no_overflow
= 1;
10613 /* Remember value for tc_gen_reloc. */
10614 fixP
->fx_addnumber
= value
;
10618 md_number_to_chars (p
, value
, fixP
->fx_size
);
10622 md_atof (int type
, char *litP
, int *sizeP
)
10624 /* This outputs the LITTLENUMs in REVERSE order;
10625 in accord with the bigendian 386. */
10626 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10629 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10632 output_invalid (int c
)
10635 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10638 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10639 "(0x%x)", (unsigned char) c
);
10640 return output_invalid_buf
;
10643 /* REG_STRING starts *before* REGISTER_PREFIX. */
10645 static const reg_entry
*
10646 parse_real_register (char *reg_string
, char **end_op
)
10648 char *s
= reg_string
;
10650 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10651 const reg_entry
*r
;
10653 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10654 if (*s
== REGISTER_PREFIX
)
10657 if (is_space_char (*s
))
10660 p
= reg_name_given
;
10661 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10663 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10664 return (const reg_entry
*) NULL
;
10668 /* For naked regs, make sure that we are not dealing with an identifier.
10669 This prevents confusing an identifier like `eax_var' with register
10671 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10672 return (const reg_entry
*) NULL
;
10676 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10678 /* Handle floating point regs, allowing spaces in the (i) part. */
10679 if (r
== i386_regtab
/* %st is first entry of table */)
10681 if (!cpu_arch_flags
.bitfield
.cpu8087
10682 && !cpu_arch_flags
.bitfield
.cpu287
10683 && !cpu_arch_flags
.bitfield
.cpu387
)
10684 return (const reg_entry
*) NULL
;
10686 if (is_space_char (*s
))
10691 if (is_space_char (*s
))
10693 if (*s
>= '0' && *s
<= '7')
10695 int fpr
= *s
- '0';
10697 if (is_space_char (*s
))
10702 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10707 /* We have "%st(" then garbage. */
10708 return (const reg_entry
*) NULL
;
10712 if (r
== NULL
|| allow_pseudo_reg
)
10715 if (operand_type_all_zero (&r
->reg_type
))
10716 return (const reg_entry
*) NULL
;
10718 if ((r
->reg_type
.bitfield
.dword
10719 || r
->reg_type
.bitfield
.sreg3
10720 || r
->reg_type
.bitfield
.control
10721 || r
->reg_type
.bitfield
.debug
10722 || r
->reg_type
.bitfield
.test
)
10723 && !cpu_arch_flags
.bitfield
.cpui386
)
10724 return (const reg_entry
*) NULL
;
10726 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10727 return (const reg_entry
*) NULL
;
10729 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10731 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10732 return (const reg_entry
*) NULL
;
10734 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10736 if (r
->reg_type
.bitfield
.ymmword
)
10737 return (const reg_entry
*) NULL
;
10739 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10740 return (const reg_entry
*) NULL
;
10744 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10745 return (const reg_entry
*) NULL
;
10747 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10748 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10749 return (const reg_entry
*) NULL
;
10751 /* Upper 16 vector registers are only available with VREX in 64bit
10752 mode, and require EVEX encoding. */
10753 if (r
->reg_flags
& RegVRex
)
10755 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10756 || flag_code
!= CODE_64BIT
)
10757 return (const reg_entry
*) NULL
;
10759 i
.vec_encoding
= vex_encoding_evex
;
10762 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10763 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10764 && flag_code
!= CODE_64BIT
)
10765 return (const reg_entry
*) NULL
;
10767 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10768 return (const reg_entry
*) NULL
;
10773 /* REG_STRING starts *before* REGISTER_PREFIX. */
10775 static const reg_entry
*
10776 parse_register (char *reg_string
, char **end_op
)
10778 const reg_entry
*r
;
10780 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10781 r
= parse_real_register (reg_string
, end_op
);
10786 char *save
= input_line_pointer
;
10790 input_line_pointer
= reg_string
;
10791 c
= get_symbol_name (®_string
);
10792 symbolP
= symbol_find (reg_string
);
10793 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10795 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10797 know (e
->X_op
== O_register
);
10798 know (e
->X_add_number
>= 0
10799 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10800 r
= i386_regtab
+ e
->X_add_number
;
10801 if ((r
->reg_flags
& RegVRex
))
10802 i
.vec_encoding
= vex_encoding_evex
;
10803 *end_op
= input_line_pointer
;
10805 *input_line_pointer
= c
;
10806 input_line_pointer
= save
;
10812 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10814 const reg_entry
*r
;
10815 char *end
= input_line_pointer
;
10818 r
= parse_register (name
, &input_line_pointer
);
10819 if (r
&& end
<= input_line_pointer
)
10821 *nextcharP
= *input_line_pointer
;
10822 *input_line_pointer
= 0;
10823 e
->X_op
= O_register
;
10824 e
->X_add_number
= r
- i386_regtab
;
10827 input_line_pointer
= end
;
10829 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10833 md_operand (expressionS
*e
)
10836 const reg_entry
*r
;
10838 switch (*input_line_pointer
)
10840 case REGISTER_PREFIX
:
10841 r
= parse_real_register (input_line_pointer
, &end
);
10844 e
->X_op
= O_register
;
10845 e
->X_add_number
= r
- i386_regtab
;
10846 input_line_pointer
= end
;
10851 gas_assert (intel_syntax
);
10852 end
= input_line_pointer
++;
10854 if (*input_line_pointer
== ']')
10856 ++input_line_pointer
;
10857 e
->X_op_symbol
= make_expr_symbol (e
);
10858 e
->X_add_symbol
= NULL
;
10859 e
->X_add_number
= 0;
10864 e
->X_op
= O_absent
;
10865 input_line_pointer
= end
;
10872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10873 const char *md_shortopts
= "kVQ:sqnO::";
10875 const char *md_shortopts
= "qnO::";
10878 #define OPTION_32 (OPTION_MD_BASE + 0)
10879 #define OPTION_64 (OPTION_MD_BASE + 1)
10880 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10881 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10882 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10883 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10884 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10885 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10886 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10887 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10888 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10889 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10890 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10891 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10892 #define OPTION_X32 (OPTION_MD_BASE + 14)
10893 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10894 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10895 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10896 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10897 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10898 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10899 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10900 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10901 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10902 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10903 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10904 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10906 struct option md_longopts
[] =
10908 {"32", no_argument
, NULL
, OPTION_32
},
10909 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10910 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10911 {"64", no_argument
, NULL
, OPTION_64
},
10913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10914 {"x32", no_argument
, NULL
, OPTION_X32
},
10915 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10916 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10918 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10919 {"march", required_argument
, NULL
, OPTION_MARCH
},
10920 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10921 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10922 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10923 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10924 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10925 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10926 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10927 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10928 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10929 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
10930 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10931 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10932 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10933 # if defined (TE_PE) || defined (TE_PEP)
10934 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10936 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10937 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10938 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10939 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10940 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10941 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10942 {NULL
, no_argument
, NULL
, 0}
10944 size_t md_longopts_size
= sizeof (md_longopts
);
10947 md_parse_option (int c
, const char *arg
)
10950 char *arch
, *next
, *saved
;
10955 optimize_align_code
= 0;
10959 quiet_warnings
= 1;
10962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10963 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10964 should be emitted or not. FIXME: Not implemented. */
10968 /* -V: SVR4 argument to print version ID. */
10970 print_version_id ();
10973 /* -k: Ignore for FreeBSD compatibility. */
10978 /* -s: On i386 Solaris, this tells the native assembler to use
10979 .stab instead of .stab.excl. We always use .stab anyhow. */
10982 case OPTION_MSHARED
:
10986 case OPTION_X86_USED_NOTE
:
10987 if (strcasecmp (arg
, "yes") == 0)
10989 else if (strcasecmp (arg
, "no") == 0)
10992 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
10997 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10998 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11001 const char **list
, **l
;
11003 list
= bfd_target_list ();
11004 for (l
= list
; *l
!= NULL
; l
++)
11005 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11006 || strcmp (*l
, "coff-x86-64") == 0
11007 || strcmp (*l
, "pe-x86-64") == 0
11008 || strcmp (*l
, "pei-x86-64") == 0
11009 || strcmp (*l
, "mach-o-x86-64") == 0)
11011 default_arch
= "x86_64";
11015 as_fatal (_("no compiled in support for x86_64"));
11021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11025 const char **list
, **l
;
11027 list
= bfd_target_list ();
11028 for (l
= list
; *l
!= NULL
; l
++)
11029 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11031 default_arch
= "x86_64:32";
11035 as_fatal (_("no compiled in support for 32bit x86_64"));
11039 as_fatal (_("32bit x86_64 is only supported for ELF"));
11044 default_arch
= "i386";
11047 case OPTION_DIVIDE
:
11048 #ifdef SVR4_COMMENT_CHARS
11053 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11055 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11059 i386_comment_chars
= n
;
11065 saved
= xstrdup (arg
);
11067 /* Allow -march=+nosse. */
11073 as_fatal (_("invalid -march= option: `%s'"), arg
);
11074 next
= strchr (arch
, '+');
11077 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11079 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11082 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11085 cpu_arch_name
= cpu_arch
[j
].name
;
11086 cpu_sub_arch_name
= NULL
;
11087 cpu_arch_flags
= cpu_arch
[j
].flags
;
11088 cpu_arch_isa
= cpu_arch
[j
].type
;
11089 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11090 if (!cpu_arch_tune_set
)
11092 cpu_arch_tune
= cpu_arch_isa
;
11093 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11097 else if (*cpu_arch
[j
].name
== '.'
11098 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11100 /* ISA extension. */
11101 i386_cpu_flags flags
;
11103 flags
= cpu_flags_or (cpu_arch_flags
,
11104 cpu_arch
[j
].flags
);
11106 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11108 if (cpu_sub_arch_name
)
11110 char *name
= cpu_sub_arch_name
;
11111 cpu_sub_arch_name
= concat (name
,
11113 (const char *) NULL
);
11117 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11118 cpu_arch_flags
= flags
;
11119 cpu_arch_isa_flags
= flags
;
11123 = cpu_flags_or (cpu_arch_isa_flags
,
11124 cpu_arch
[j
].flags
);
11129 if (j
>= ARRAY_SIZE (cpu_arch
))
11131 /* Disable an ISA extension. */
11132 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11133 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11135 i386_cpu_flags flags
;
11137 flags
= cpu_flags_and_not (cpu_arch_flags
,
11138 cpu_noarch
[j
].flags
);
11139 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11141 if (cpu_sub_arch_name
)
11143 char *name
= cpu_sub_arch_name
;
11144 cpu_sub_arch_name
= concat (arch
,
11145 (const char *) NULL
);
11149 cpu_sub_arch_name
= xstrdup (arch
);
11150 cpu_arch_flags
= flags
;
11151 cpu_arch_isa_flags
= flags
;
11156 if (j
>= ARRAY_SIZE (cpu_noarch
))
11157 j
= ARRAY_SIZE (cpu_arch
);
11160 if (j
>= ARRAY_SIZE (cpu_arch
))
11161 as_fatal (_("invalid -march= option: `%s'"), arg
);
11165 while (next
!= NULL
);
11171 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11172 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11174 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11176 cpu_arch_tune_set
= 1;
11177 cpu_arch_tune
= cpu_arch
[j
].type
;
11178 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11182 if (j
>= ARRAY_SIZE (cpu_arch
))
11183 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11186 case OPTION_MMNEMONIC
:
11187 if (strcasecmp (arg
, "att") == 0)
11188 intel_mnemonic
= 0;
11189 else if (strcasecmp (arg
, "intel") == 0)
11190 intel_mnemonic
= 1;
11192 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11195 case OPTION_MSYNTAX
:
11196 if (strcasecmp (arg
, "att") == 0)
11198 else if (strcasecmp (arg
, "intel") == 0)
11201 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11204 case OPTION_MINDEX_REG
:
11205 allow_index_reg
= 1;
11208 case OPTION_MNAKED_REG
:
11209 allow_naked_reg
= 1;
11212 case OPTION_MSSE2AVX
:
11216 case OPTION_MSSE_CHECK
:
11217 if (strcasecmp (arg
, "error") == 0)
11218 sse_check
= check_error
;
11219 else if (strcasecmp (arg
, "warning") == 0)
11220 sse_check
= check_warning
;
11221 else if (strcasecmp (arg
, "none") == 0)
11222 sse_check
= check_none
;
11224 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11227 case OPTION_MOPERAND_CHECK
:
11228 if (strcasecmp (arg
, "error") == 0)
11229 operand_check
= check_error
;
11230 else if (strcasecmp (arg
, "warning") == 0)
11231 operand_check
= check_warning
;
11232 else if (strcasecmp (arg
, "none") == 0)
11233 operand_check
= check_none
;
11235 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11238 case OPTION_MAVXSCALAR
:
11239 if (strcasecmp (arg
, "128") == 0)
11240 avxscalar
= vex128
;
11241 else if (strcasecmp (arg
, "256") == 0)
11242 avxscalar
= vex256
;
11244 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11247 case OPTION_MVEXWIG
:
11248 if (strcmp (arg
, "0") == 0)
11250 else if (strcmp (arg
, "1") == 0)
11253 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11256 case OPTION_MADD_BND_PREFIX
:
11257 add_bnd_prefix
= 1;
11260 case OPTION_MEVEXLIG
:
11261 if (strcmp (arg
, "128") == 0)
11262 evexlig
= evexl128
;
11263 else if (strcmp (arg
, "256") == 0)
11264 evexlig
= evexl256
;
11265 else if (strcmp (arg
, "512") == 0)
11266 evexlig
= evexl512
;
11268 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11271 case OPTION_MEVEXRCIG
:
11272 if (strcmp (arg
, "rne") == 0)
11274 else if (strcmp (arg
, "rd") == 0)
11276 else if (strcmp (arg
, "ru") == 0)
11278 else if (strcmp (arg
, "rz") == 0)
11281 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11284 case OPTION_MEVEXWIG
:
11285 if (strcmp (arg
, "0") == 0)
11287 else if (strcmp (arg
, "1") == 0)
11290 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11293 # if defined (TE_PE) || defined (TE_PEP)
11294 case OPTION_MBIG_OBJ
:
11299 case OPTION_MOMIT_LOCK_PREFIX
:
11300 if (strcasecmp (arg
, "yes") == 0)
11301 omit_lock_prefix
= 1;
11302 else if (strcasecmp (arg
, "no") == 0)
11303 omit_lock_prefix
= 0;
11305 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11308 case OPTION_MFENCE_AS_LOCK_ADD
:
11309 if (strcasecmp (arg
, "yes") == 0)
11311 else if (strcasecmp (arg
, "no") == 0)
11314 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11317 case OPTION_MRELAX_RELOCATIONS
:
11318 if (strcasecmp (arg
, "yes") == 0)
11319 generate_relax_relocations
= 1;
11320 else if (strcasecmp (arg
, "no") == 0)
11321 generate_relax_relocations
= 0;
11323 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11326 case OPTION_MAMD64
:
11330 case OPTION_MINTEL64
:
11338 /* Turn off -Os. */
11339 optimize_for_space
= 0;
11341 else if (*arg
== 's')
11343 optimize_for_space
= 1;
11344 /* Turn on all encoding optimizations. */
11349 optimize
= atoi (arg
);
11350 /* Turn off -Os. */
11351 optimize_for_space
= 0;
11361 #define MESSAGE_TEMPLATE \
11365 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11366 int *left_p
, const char *name
, int len
)
11368 int size
= sizeof (MESSAGE_TEMPLATE
);
11369 int left
= *left_p
;
11371 /* Reserve 2 spaces for ", " or ",\0" */
11374 /* Check if there is any room. */
11382 p
= mempcpy (p
, name
, len
);
11386 /* Output the current message now and start a new one. */
11389 fprintf (stream
, "%s\n", message
);
11391 left
= size
- (start
- message
) - len
- 2;
11393 gas_assert (left
>= 0);
11395 p
= mempcpy (p
, name
, len
);
11403 show_arch (FILE *stream
, int ext
, int check
)
11405 static char message
[] = MESSAGE_TEMPLATE
;
11406 char *start
= message
+ 27;
11408 int size
= sizeof (MESSAGE_TEMPLATE
);
11415 left
= size
- (start
- message
);
11416 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11418 /* Should it be skipped? */
11419 if (cpu_arch
[j
].skip
)
11422 name
= cpu_arch
[j
].name
;
11423 len
= cpu_arch
[j
].len
;
11426 /* It is an extension. Skip if we aren't asked to show it. */
11437 /* It is an processor. Skip if we show only extension. */
11440 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11442 /* It is an impossible processor - skip. */
11446 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11449 /* Display disabled extensions. */
11451 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11453 name
= cpu_noarch
[j
].name
;
11454 len
= cpu_noarch
[j
].len
;
11455 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11460 fprintf (stream
, "%s\n", message
);
11464 md_show_usage (FILE *stream
)
11466 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11467 fprintf (stream
, _("\
11469 -V print assembler version number\n\
11472 fprintf (stream
, _("\
11473 -n Do not optimize code alignment\n\
11474 -q quieten some warnings\n"));
11475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11476 fprintf (stream
, _("\
11479 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11480 || defined (TE_PE) || defined (TE_PEP))
11481 fprintf (stream
, _("\
11482 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11484 #ifdef SVR4_COMMENT_CHARS
11485 fprintf (stream
, _("\
11486 --divide do not treat `/' as a comment character\n"));
11488 fprintf (stream
, _("\
11489 --divide ignored\n"));
11491 fprintf (stream
, _("\
11492 -march=CPU[,+EXTENSION...]\n\
11493 generate code for CPU and EXTENSION, CPU is one of:\n"));
11494 show_arch (stream
, 0, 1);
11495 fprintf (stream
, _("\
11496 EXTENSION is combination of:\n"));
11497 show_arch (stream
, 1, 0);
11498 fprintf (stream
, _("\
11499 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11500 show_arch (stream
, 0, 0);
11501 fprintf (stream
, _("\
11502 -msse2avx encode SSE instructions with VEX prefix\n"));
11503 fprintf (stream
, _("\
11504 -msse-check=[none|error|warning] (default: warning)\n\
11505 check SSE instructions\n"));
11506 fprintf (stream
, _("\
11507 -moperand-check=[none|error|warning] (default: warning)\n\
11508 check operand combinations for validity\n"));
11509 fprintf (stream
, _("\
11510 -mavxscalar=[128|256] (default: 128)\n\
11511 encode scalar AVX instructions with specific vector\n\
11513 fprintf (stream
, _("\
11514 -mvexwig=[0|1] (default: 0)\n\
11515 encode VEX instructions with specific VEX.W value\n\
11516 for VEX.W bit ignored instructions\n"));
11517 fprintf (stream
, _("\
11518 -mevexlig=[128|256|512] (default: 128)\n\
11519 encode scalar EVEX instructions with specific vector\n\
11521 fprintf (stream
, _("\
11522 -mevexwig=[0|1] (default: 0)\n\
11523 encode EVEX instructions with specific EVEX.W value\n\
11524 for EVEX.W bit ignored instructions\n"));
11525 fprintf (stream
, _("\
11526 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11527 encode EVEX instructions with specific EVEX.RC value\n\
11528 for SAE-only ignored instructions\n"));
11529 fprintf (stream
, _("\
11530 -mmnemonic=[att|intel] "));
11531 if (SYSV386_COMPAT
)
11532 fprintf (stream
, _("(default: att)\n"));
11534 fprintf (stream
, _("(default: intel)\n"));
11535 fprintf (stream
, _("\
11536 use AT&T/Intel mnemonic\n"));
11537 fprintf (stream
, _("\
11538 -msyntax=[att|intel] (default: att)\n\
11539 use AT&T/Intel syntax\n"));
11540 fprintf (stream
, _("\
11541 -mindex-reg support pseudo index registers\n"));
11542 fprintf (stream
, _("\
11543 -mnaked-reg don't require `%%' prefix for registers\n"));
11544 fprintf (stream
, _("\
11545 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11547 fprintf (stream
, _("\
11548 -mshared disable branch optimization for shared code\n"));
11549 fprintf (stream
, _("\
11550 -mx86-used-note=[no|yes] "));
11551 if (DEFAULT_X86_USED_NOTE
)
11552 fprintf (stream
, _("(default: yes)\n"));
11554 fprintf (stream
, _("(default: no)\n"));
11555 fprintf (stream
, _("\
11556 generate x86 used ISA and feature properties\n"));
11558 #if defined (TE_PE) || defined (TE_PEP)
11559 fprintf (stream
, _("\
11560 -mbig-obj generate big object files\n"));
11562 fprintf (stream
, _("\
11563 -momit-lock-prefix=[no|yes] (default: no)\n\
11564 strip all lock prefixes\n"));
11565 fprintf (stream
, _("\
11566 -mfence-as-lock-add=[no|yes] (default: no)\n\
11567 encode lfence, mfence and sfence as\n\
11568 lock addl $0x0, (%%{re}sp)\n"));
11569 fprintf (stream
, _("\
11570 -mrelax-relocations=[no|yes] "));
11571 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11572 fprintf (stream
, _("(default: yes)\n"));
11574 fprintf (stream
, _("(default: no)\n"));
11575 fprintf (stream
, _("\
11576 generate relax relocations\n"));
11577 fprintf (stream
, _("\
11578 -mamd64 accept only AMD64 ISA [default]\n"));
11579 fprintf (stream
, _("\
11580 -mintel64 accept only Intel64 ISA\n"));
11583 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11584 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11585 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11587 /* Pick the target format to use. */
11590 i386_target_format (void)
11592 if (!strncmp (default_arch
, "x86_64", 6))
11594 update_code_flag (CODE_64BIT
, 1);
11595 if (default_arch
[6] == '\0')
11596 x86_elf_abi
= X86_64_ABI
;
11598 x86_elf_abi
= X86_64_X32_ABI
;
11600 else if (!strcmp (default_arch
, "i386"))
11601 update_code_flag (CODE_32BIT
, 1);
11602 else if (!strcmp (default_arch
, "iamcu"))
11604 update_code_flag (CODE_32BIT
, 1);
11605 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11607 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11608 cpu_arch_name
= "iamcu";
11609 cpu_sub_arch_name
= NULL
;
11610 cpu_arch_flags
= iamcu_flags
;
11611 cpu_arch_isa
= PROCESSOR_IAMCU
;
11612 cpu_arch_isa_flags
= iamcu_flags
;
11613 if (!cpu_arch_tune_set
)
11615 cpu_arch_tune
= cpu_arch_isa
;
11616 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11619 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11620 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11624 as_fatal (_("unknown architecture"));
11626 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11627 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11628 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11629 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11631 switch (OUTPUT_FLAVOR
)
11633 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11634 case bfd_target_aout_flavour
:
11635 return AOUT_TARGET_FORMAT
;
11637 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11638 # if defined (TE_PE) || defined (TE_PEP)
11639 case bfd_target_coff_flavour
:
11640 if (flag_code
== CODE_64BIT
)
11641 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11644 # elif defined (TE_GO32)
11645 case bfd_target_coff_flavour
:
11646 return "coff-go32";
11648 case bfd_target_coff_flavour
:
11649 return "coff-i386";
11652 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11653 case bfd_target_elf_flavour
:
11655 const char *format
;
11657 switch (x86_elf_abi
)
11660 format
= ELF_TARGET_FORMAT
;
11663 use_rela_relocations
= 1;
11665 format
= ELF_TARGET_FORMAT64
;
11667 case X86_64_X32_ABI
:
11668 use_rela_relocations
= 1;
11670 disallow_64bit_reloc
= 1;
11671 format
= ELF_TARGET_FORMAT32
;
11674 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11676 if (x86_elf_abi
!= X86_64_ABI
)
11677 as_fatal (_("Intel L1OM is 64bit only"));
11678 return ELF_TARGET_L1OM_FORMAT
;
11680 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11682 if (x86_elf_abi
!= X86_64_ABI
)
11683 as_fatal (_("Intel K1OM is 64bit only"));
11684 return ELF_TARGET_K1OM_FORMAT
;
11686 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11688 if (x86_elf_abi
!= I386_ABI
)
11689 as_fatal (_("Intel MCU is 32bit only"));
11690 return ELF_TARGET_IAMCU_FORMAT
;
11696 #if defined (OBJ_MACH_O)
11697 case bfd_target_mach_o_flavour
:
11698 if (flag_code
== CODE_64BIT
)
11700 use_rela_relocations
= 1;
11702 return "mach-o-x86-64";
11705 return "mach-o-i386";
11713 #endif /* OBJ_MAYBE_ more than one */
11716 md_undefined_symbol (char *name
)
11718 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11719 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11720 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11721 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11725 if (symbol_find (name
))
11726 as_bad (_("GOT already in symbol table"));
11727 GOT_symbol
= symbol_new (name
, undefined_section
,
11728 (valueT
) 0, &zero_address_frag
);
11735 /* Round up a section size to the appropriate boundary. */
11738 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11740 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11741 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11743 /* For a.out, force the section size to be aligned. If we don't do
11744 this, BFD will align it for us, but it will not write out the
11745 final bytes of the section. This may be a bug in BFD, but it is
11746 easier to fix it here since that is how the other a.out targets
11750 align
= bfd_get_section_alignment (stdoutput
, segment
);
11751 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11758 /* On the i386, PC-relative offsets are relative to the start of the
11759 next instruction. That is, the address of the offset, plus its
11760 size, since the offset is always the last part of the insn. */
11763 md_pcrel_from (fixS
*fixP
)
11765 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11771 s_bss (int ignore ATTRIBUTE_UNUSED
)
11775 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11777 obj_elf_section_change_hook ();
11779 temp
= get_absolute_expression ();
11780 subseg_set (bss_section
, (subsegT
) temp
);
11781 demand_empty_rest_of_line ();
11787 i386_validate_fix (fixS
*fixp
)
11789 if (fixp
->fx_subsy
)
11791 if (fixp
->fx_subsy
== GOT_symbol
)
11793 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11798 if (fixp
->fx_tcbit2
)
11799 fixp
->fx_r_type
= (fixp
->fx_tcbit
11800 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11801 : BFD_RELOC_X86_64_GOTPCRELX
);
11804 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11809 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11811 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11813 fixp
->fx_subsy
= 0;
11816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11817 else if (!object_64bit
)
11819 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11820 && fixp
->fx_tcbit2
)
11821 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11827 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11830 bfd_reloc_code_real_type code
;
11832 switch (fixp
->fx_r_type
)
11834 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11835 case BFD_RELOC_SIZE32
:
11836 case BFD_RELOC_SIZE64
:
11837 if (S_IS_DEFINED (fixp
->fx_addsy
)
11838 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11840 /* Resolve size relocation against local symbol to size of
11841 the symbol plus addend. */
11842 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11843 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11844 && !fits_in_unsigned_long (value
))
11845 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11846 _("symbol size computation overflow"));
11847 fixp
->fx_addsy
= NULL
;
11848 fixp
->fx_subsy
= NULL
;
11849 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11853 /* Fall through. */
11855 case BFD_RELOC_X86_64_PLT32
:
11856 case BFD_RELOC_X86_64_GOT32
:
11857 case BFD_RELOC_X86_64_GOTPCREL
:
11858 case BFD_RELOC_X86_64_GOTPCRELX
:
11859 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11860 case BFD_RELOC_386_PLT32
:
11861 case BFD_RELOC_386_GOT32
:
11862 case BFD_RELOC_386_GOT32X
:
11863 case BFD_RELOC_386_GOTOFF
:
11864 case BFD_RELOC_386_GOTPC
:
11865 case BFD_RELOC_386_TLS_GD
:
11866 case BFD_RELOC_386_TLS_LDM
:
11867 case BFD_RELOC_386_TLS_LDO_32
:
11868 case BFD_RELOC_386_TLS_IE_32
:
11869 case BFD_RELOC_386_TLS_IE
:
11870 case BFD_RELOC_386_TLS_GOTIE
:
11871 case BFD_RELOC_386_TLS_LE_32
:
11872 case BFD_RELOC_386_TLS_LE
:
11873 case BFD_RELOC_386_TLS_GOTDESC
:
11874 case BFD_RELOC_386_TLS_DESC_CALL
:
11875 case BFD_RELOC_X86_64_TLSGD
:
11876 case BFD_RELOC_X86_64_TLSLD
:
11877 case BFD_RELOC_X86_64_DTPOFF32
:
11878 case BFD_RELOC_X86_64_DTPOFF64
:
11879 case BFD_RELOC_X86_64_GOTTPOFF
:
11880 case BFD_RELOC_X86_64_TPOFF32
:
11881 case BFD_RELOC_X86_64_TPOFF64
:
11882 case BFD_RELOC_X86_64_GOTOFF64
:
11883 case BFD_RELOC_X86_64_GOTPC32
:
11884 case BFD_RELOC_X86_64_GOT64
:
11885 case BFD_RELOC_X86_64_GOTPCREL64
:
11886 case BFD_RELOC_X86_64_GOTPC64
:
11887 case BFD_RELOC_X86_64_GOTPLT64
:
11888 case BFD_RELOC_X86_64_PLTOFF64
:
11889 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11890 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11891 case BFD_RELOC_RVA
:
11892 case BFD_RELOC_VTABLE_ENTRY
:
11893 case BFD_RELOC_VTABLE_INHERIT
:
11895 case BFD_RELOC_32_SECREL
:
11897 code
= fixp
->fx_r_type
;
11899 case BFD_RELOC_X86_64_32S
:
11900 if (!fixp
->fx_pcrel
)
11902 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11903 code
= fixp
->fx_r_type
;
11906 /* Fall through. */
11908 if (fixp
->fx_pcrel
)
11910 switch (fixp
->fx_size
)
11913 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11914 _("can not do %d byte pc-relative relocation"),
11916 code
= BFD_RELOC_32_PCREL
;
11918 case 1: code
= BFD_RELOC_8_PCREL
; break;
11919 case 2: code
= BFD_RELOC_16_PCREL
; break;
11920 case 4: code
= BFD_RELOC_32_PCREL
; break;
11922 case 8: code
= BFD_RELOC_64_PCREL
; break;
11928 switch (fixp
->fx_size
)
11931 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11932 _("can not do %d byte relocation"),
11934 code
= BFD_RELOC_32
;
11936 case 1: code
= BFD_RELOC_8
; break;
11937 case 2: code
= BFD_RELOC_16
; break;
11938 case 4: code
= BFD_RELOC_32
; break;
11940 case 8: code
= BFD_RELOC_64
; break;
11947 if ((code
== BFD_RELOC_32
11948 || code
== BFD_RELOC_32_PCREL
11949 || code
== BFD_RELOC_X86_64_32S
)
11951 && fixp
->fx_addsy
== GOT_symbol
)
11954 code
= BFD_RELOC_386_GOTPC
;
11956 code
= BFD_RELOC_X86_64_GOTPC32
;
11958 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11960 && fixp
->fx_addsy
== GOT_symbol
)
11962 code
= BFD_RELOC_X86_64_GOTPC64
;
11965 rel
= XNEW (arelent
);
11966 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11967 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11969 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11971 if (!use_rela_relocations
)
11973 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11974 vtable entry to be used in the relocation's section offset. */
11975 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11976 rel
->address
= fixp
->fx_offset
;
11977 #if defined (OBJ_COFF) && defined (TE_PE)
11978 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11979 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11984 /* Use the rela in 64bit mode. */
11987 if (disallow_64bit_reloc
)
11990 case BFD_RELOC_X86_64_DTPOFF64
:
11991 case BFD_RELOC_X86_64_TPOFF64
:
11992 case BFD_RELOC_64_PCREL
:
11993 case BFD_RELOC_X86_64_GOTOFF64
:
11994 case BFD_RELOC_X86_64_GOT64
:
11995 case BFD_RELOC_X86_64_GOTPCREL64
:
11996 case BFD_RELOC_X86_64_GOTPC64
:
11997 case BFD_RELOC_X86_64_GOTPLT64
:
11998 case BFD_RELOC_X86_64_PLTOFF64
:
11999 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12000 _("cannot represent relocation type %s in x32 mode"),
12001 bfd_get_reloc_code_name (code
));
12007 if (!fixp
->fx_pcrel
)
12008 rel
->addend
= fixp
->fx_offset
;
12012 case BFD_RELOC_X86_64_PLT32
:
12013 case BFD_RELOC_X86_64_GOT32
:
12014 case BFD_RELOC_X86_64_GOTPCREL
:
12015 case BFD_RELOC_X86_64_GOTPCRELX
:
12016 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12017 case BFD_RELOC_X86_64_TLSGD
:
12018 case BFD_RELOC_X86_64_TLSLD
:
12019 case BFD_RELOC_X86_64_GOTTPOFF
:
12020 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12021 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12022 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12025 rel
->addend
= (section
->vma
12027 + fixp
->fx_addnumber
12028 + md_pcrel_from (fixp
));
12033 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12034 if (rel
->howto
== NULL
)
12036 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12037 _("cannot represent relocation type %s"),
12038 bfd_get_reloc_code_name (code
));
12039 /* Set howto to a garbage value so that we can keep going. */
12040 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12041 gas_assert (rel
->howto
!= NULL
);
12047 #include "tc-i386-intel.c"
12050 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12052 int saved_naked_reg
;
12053 char saved_register_dot
;
12055 saved_naked_reg
= allow_naked_reg
;
12056 allow_naked_reg
= 1;
12057 saved_register_dot
= register_chars
['.'];
12058 register_chars
['.'] = '.';
12059 allow_pseudo_reg
= 1;
12060 expression_and_evaluate (exp
);
12061 allow_pseudo_reg
= 0;
12062 register_chars
['.'] = saved_register_dot
;
12063 allow_naked_reg
= saved_naked_reg
;
12065 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12067 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12069 exp
->X_op
= O_constant
;
12070 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12071 .dw2_regnum
[flag_code
>> 1];
12074 exp
->X_op
= O_illegal
;
12079 tc_x86_frame_initial_instructions (void)
12081 static unsigned int sp_regno
[2];
12083 if (!sp_regno
[flag_code
>> 1])
12085 char *saved_input
= input_line_pointer
;
12086 char sp
[][4] = {"esp", "rsp"};
12089 input_line_pointer
= sp
[flag_code
>> 1];
12090 tc_x86_parse_to_dw2regnum (&exp
);
12091 gas_assert (exp
.X_op
== O_constant
);
12092 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12093 input_line_pointer
= saved_input
;
12096 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12097 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12101 x86_dwarf2_addr_size (void)
12103 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12104 if (x86_elf_abi
== X86_64_X32_ABI
)
12107 return bfd_arch_bits_per_address (stdoutput
) / 8;
12111 i386_elf_section_type (const char *str
, size_t len
)
12113 if (flag_code
== CODE_64BIT
12114 && len
== sizeof ("unwind") - 1
12115 && strncmp (str
, "unwind", 6) == 0)
12116 return SHT_X86_64_UNWIND
;
12123 i386_solaris_fix_up_eh_frame (segT sec
)
12125 if (flag_code
== CODE_64BIT
)
12126 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12132 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12136 exp
.X_op
= O_secrel
;
12137 exp
.X_add_symbol
= symbol
;
12138 exp
.X_add_number
= 0;
12139 emit_expr (&exp
, size
);
12143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12144 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12147 x86_64_section_letter (int letter
, const char **ptr_msg
)
12149 if (flag_code
== CODE_64BIT
)
12152 return SHF_X86_64_LARGE
;
12154 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12157 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12162 x86_64_section_word (char *str
, size_t len
)
12164 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12165 return SHF_X86_64_LARGE
;
12171 handle_large_common (int small ATTRIBUTE_UNUSED
)
12173 if (flag_code
!= CODE_64BIT
)
12175 s_comm_internal (0, elf_common_parse
);
12176 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12180 static segT lbss_section
;
12181 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12182 asection
*saved_bss_section
= bss_section
;
12184 if (lbss_section
== NULL
)
12186 flagword applicable
;
12187 segT seg
= now_seg
;
12188 subsegT subseg
= now_subseg
;
12190 /* The .lbss section is for local .largecomm symbols. */
12191 lbss_section
= subseg_new (".lbss", 0);
12192 applicable
= bfd_applicable_section_flags (stdoutput
);
12193 bfd_set_section_flags (stdoutput
, lbss_section
,
12194 applicable
& SEC_ALLOC
);
12195 seg_info (lbss_section
)->bss
= 1;
12197 subseg_set (seg
, subseg
);
12200 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12201 bss_section
= lbss_section
;
12203 s_comm_internal (0, elf_common_parse
);
12205 elf_com_section_ptr
= saved_com_section_ptr
;
12206 bss_section
= saved_bss_section
;
12209 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */