1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* Types of condition jump used by macro-fusion. */
693 mf_jcc_jo
= 0, /* base opcode 0x70 */
694 mf_jcc_jc
, /* base opcode 0x72 */
695 mf_jcc_je
, /* base opcode 0x74 */
696 mf_jcc_jna
, /* base opcode 0x76 */
697 mf_jcc_js
, /* base opcode 0x78 */
698 mf_jcc_jp
, /* base opcode 0x7a */
699 mf_jcc_jl
, /* base opcode 0x7c */
700 mf_jcc_jle
, /* base opcode 0x7e */
703 /* Types of compare flag-modifying insntructions used by macro-fusion. */
706 mf_cmp_test_and
, /* test/cmp */
707 mf_cmp_alu_cmp
, /* add/sub/cmp */
708 mf_cmp_incdec
/* inc/dec */
711 /* The maximum padding size for fused jcc. CMP like instruction can
712 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
714 #define MAX_FUSED_JCC_PADDING_SIZE 20
716 /* The maximum number of prefixes added for an instruction. */
717 static unsigned int align_branch_prefix_size
= 5;
720 1. Clear the REX_W bit with register operand if possible.
721 2. Above plus use 128bit vector instruction to clear the full vector
724 static int optimize
= 0;
727 1. Clear the REX_W bit with register operand if possible.
728 2. Above plus use 128bit vector instruction to clear the full vector
730 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
733 static int optimize_for_space
= 0;
735 /* Register prefix used for error message. */
736 static const char *register_prefix
= "%";
738 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
739 leave, push, and pop instructions so that gcc has the same stack
740 frame as in 32 bit mode. */
741 static char stackop_size
= '\0';
743 /* Non-zero to optimize code alignment. */
744 int optimize_align_code
= 1;
746 /* Non-zero to quieten some warnings. */
747 static int quiet_warnings
= 0;
750 static const char *cpu_arch_name
= NULL
;
751 static char *cpu_sub_arch_name
= NULL
;
753 /* CPU feature flags. */
754 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
756 /* If we have selected a cpu we are generating instructions for. */
757 static int cpu_arch_tune_set
= 0;
759 /* Cpu we are generating instructions for. */
760 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
762 /* CPU feature flags of cpu we are generating instructions for. */
763 static i386_cpu_flags cpu_arch_tune_flags
;
765 /* CPU instruction set architecture used. */
766 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
768 /* CPU feature flags of instruction set architecture used. */
769 i386_cpu_flags cpu_arch_isa_flags
;
771 /* If set, conditional jumps are not automatically promoted to handle
772 larger than a byte offset. */
773 static unsigned int no_cond_jump_promotion
= 0;
775 /* Encode SSE instructions with VEX prefix. */
776 static unsigned int sse2avx
;
778 /* Encode scalar AVX instructions with specific vector length. */
785 /* Encode VEX WIG instructions with specific vex.w. */
792 /* Encode scalar EVEX LIG instructions with specific vector length. */
800 /* Encode EVEX WIG instructions with specific evex.w. */
807 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
808 static enum rc_type evexrcig
= rne
;
810 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
811 static symbolS
*GOT_symbol
;
813 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
814 unsigned int x86_dwarf2_return_column
;
816 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
817 int x86_cie_data_alignment
;
819 /* Interface to relax_segment.
820 There are 3 major relax states for 386 jump insns because the
821 different types of jumps add different sizes to frags when we're
822 figuring out what sort of jump to choose to reach a given label.
824 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
825 branches which are handled by md_estimate_size_before_relax() and
826 i386_generic_table_relax_frag(). */
829 #define UNCOND_JUMP 0
831 #define COND_JUMP86 2
832 #define BRANCH_PADDING 3
833 #define BRANCH_PREFIX 4
834 #define FUSED_JCC_PADDING 5
839 #define SMALL16 (SMALL | CODE16)
841 #define BIG16 (BIG | CODE16)
845 #define INLINE __inline__
851 #define ENCODE_RELAX_STATE(type, size) \
852 ((relax_substateT) (((type) << 2) | (size)))
853 #define TYPE_FROM_RELAX_STATE(s) \
855 #define DISP_SIZE_FROM_RELAX_STATE(s) \
856 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
858 /* This table is used by relax_frag to promote short jumps to long
859 ones where necessary. SMALL (short) jumps may be promoted to BIG
860 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
861 don't allow a short jump in a 32 bit code segment to be promoted to
862 a 16 bit offset jump because it's slower (requires data size
863 prefix), and doesn't work, unless the destination is in the bottom
864 64k of the code segment (The top 16 bits of eip are zeroed). */
866 const relax_typeS md_relax_table
[] =
869 1) most positive reach of this state,
870 2) most negative reach of this state,
871 3) how many bytes this mode will have in the variable part of the frag
872 4) which index into the table to try if we can't fit into this one. */
874 /* UNCOND_JUMP states. */
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
876 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
877 /* dword jmp adds 4 bytes to frag:
878 0 extra opcode bytes, 4 displacement bytes. */
880 /* word jmp adds 2 byte2 to frag:
881 0 extra opcode bytes, 2 displacement bytes. */
884 /* COND_JUMP states. */
885 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
886 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
887 /* dword conditionals adds 5 bytes to frag:
888 1 extra opcode byte, 4 displacement bytes. */
890 /* word conditionals add 3 bytes to frag:
891 1 extra opcode byte, 2 displacement bytes. */
894 /* COND_JUMP86 states. */
895 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
896 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
897 /* dword conditionals adds 5 bytes to frag:
898 1 extra opcode byte, 4 displacement bytes. */
900 /* word conditionals add 4 bytes to frag:
901 1 displacement byte and a 3 byte long branch insn. */
905 static const arch_entry cpu_arch
[] =
907 /* Do not replace the first two entries - i386_target_format()
908 relies on them being there in this order. */
909 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
910 CPU_GENERIC32_FLAGS
, 0 },
911 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
912 CPU_GENERIC64_FLAGS
, 0 },
913 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
915 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
917 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
919 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
921 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
923 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
925 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
927 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
929 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
930 CPU_PENTIUMPRO_FLAGS
, 0 },
931 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
933 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
935 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
937 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
939 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
940 CPU_NOCONA_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
943 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
945 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
946 CPU_CORE2_FLAGS
, 1 },
947 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
948 CPU_CORE2_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
950 CPU_COREI7_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
953 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
955 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
956 CPU_IAMCU_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
959 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
961 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
962 CPU_ATHLON_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
965 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
967 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
969 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
970 CPU_AMDFAM10_FLAGS
, 0 },
971 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
972 CPU_BDVER1_FLAGS
, 0 },
973 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
974 CPU_BDVER2_FLAGS
, 0 },
975 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
976 CPU_BDVER3_FLAGS
, 0 },
977 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
978 CPU_BDVER4_FLAGS
, 0 },
979 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
980 CPU_ZNVER1_FLAGS
, 0 },
981 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
982 CPU_ZNVER2_FLAGS
, 0 },
983 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
984 CPU_BTVER1_FLAGS
, 0 },
985 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
986 CPU_BTVER2_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1001 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1003 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1004 CPU_SSE2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1006 CPU_SSE3_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1010 CPU_SSSE3_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1012 CPU_SSE4_1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1014 CPU_SSE4_2_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1016 CPU_SSE4_2_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1019 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1020 CPU_AVX2_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1022 CPU_AVX512F_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1024 CPU_AVX512CD_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1026 CPU_AVX512ER_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1028 CPU_AVX512PF_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1030 CPU_AVX512DQ_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1032 CPU_AVX512BW_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1034 CPU_AVX512VL_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1037 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1038 CPU_VMFUNC_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1042 CPU_XSAVE_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1044 CPU_XSAVEOPT_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1046 CPU_XSAVEC_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1048 CPU_XSAVES_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1051 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1052 CPU_PCLMUL_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1054 CPU_PCLMUL_FLAGS
, 1 },
1055 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1056 CPU_FSGSBASE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1058 CPU_RDRND_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1060 CPU_F16C_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1062 CPU_BMI2_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1066 CPU_FMA4_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1069 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1071 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1072 CPU_MOVBE_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1074 CPU_CX16_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1077 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1078 CPU_LZCNT_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1080 CPU_POPCNT_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1086 CPU_INVPCID_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1088 CPU_CLFLUSH_FLAGS
, 0 },
1089 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1091 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1092 CPU_SYSCALL_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1094 CPU_RDTSCP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1096 CPU_3DNOW_FLAGS
, 0 },
1097 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1098 CPU_3DNOWA_FLAGS
, 0 },
1099 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1100 CPU_PADLOCK_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1102 CPU_SVME_FLAGS
, 1 },
1103 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1104 CPU_SVME_FLAGS
, 0 },
1105 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1106 CPU_SSE4A_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1109 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1111 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1113 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1115 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1116 CPU_RDSEED_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1118 CPU_PRFCHW_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1120 CPU_SMAP_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1123 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1125 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1126 CPU_CLFLUSHOPT_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1128 CPU_PREFETCHWT1_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1131 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1132 CPU_CLWB_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1134 CPU_AVX512IFMA_FLAGS
, 0 },
1135 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1136 CPU_AVX512VBMI_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1138 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1140 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1142 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1144 CPU_AVX512_VBMI2_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1146 CPU_AVX512_VNNI_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1148 CPU_AVX512_BITALG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1150 CPU_CLZERO_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1152 CPU_MWAITX_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1154 CPU_OSPKE_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1156 CPU_RDPID_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1158 CPU_PTWRITE_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1161 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1162 CPU_SHSTK_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1164 CPU_GFNI_FLAGS
, 0 },
1165 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1166 CPU_VAES_FLAGS
, 0 },
1167 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1168 CPU_VPCLMULQDQ_FLAGS
, 0 },
1169 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1170 CPU_WBNOINVD_FLAGS
, 0 },
1171 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1172 CPU_PCONFIG_FLAGS
, 0 },
1173 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1174 CPU_WAITPKG_FLAGS
, 0 },
1175 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1176 CPU_CLDEMOTE_FLAGS
, 0 },
1177 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1178 CPU_MOVDIRI_FLAGS
, 0 },
1179 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1180 CPU_MOVDIR64B_FLAGS
, 0 },
1181 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1182 CPU_AVX512_BF16_FLAGS
, 0 },
1183 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1184 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1185 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1186 CPU_ENQCMD_FLAGS
, 0 },
1187 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1188 CPU_RDPRU_FLAGS
, 0 },
1189 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1190 CPU_MCOMMIT_FLAGS
, 0 },
1191 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1192 CPU_SEV_ES_FLAGS
, 0 },
1195 static const noarch_entry cpu_noarch
[] =
1197 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1198 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1199 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1200 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1201 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1202 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1203 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1204 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1205 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1206 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1207 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1208 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1209 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1210 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1211 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1212 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1213 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1214 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1215 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1216 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1217 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1218 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1219 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1220 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1221 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1222 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1223 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1224 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1225 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1226 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1227 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1228 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1229 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1230 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1231 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1232 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1233 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1234 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1235 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1239 /* Like s_lcomm_internal in gas/read.c but the alignment string
1240 is allowed to be optional. */
1243 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1250 && *input_line_pointer
== ',')
1252 align
= parse_align (needs_align
- 1);
1254 if (align
== (addressT
) -1)
1269 bss_alloc (symbolP
, size
, align
);
1274 pe_lcomm (int needs_align
)
1276 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1280 const pseudo_typeS md_pseudo_table
[] =
1282 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1283 {"align", s_align_bytes
, 0},
1285 {"align", s_align_ptwo
, 0},
1287 {"arch", set_cpu_arch
, 0},
1291 {"lcomm", pe_lcomm
, 1},
1293 {"ffloat", float_cons
, 'f'},
1294 {"dfloat", float_cons
, 'd'},
1295 {"tfloat", float_cons
, 'x'},
1297 {"slong", signed_cons
, 4},
1298 {"noopt", s_ignore
, 0},
1299 {"optim", s_ignore
, 0},
1300 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1301 {"code16", set_code_flag
, CODE_16BIT
},
1302 {"code32", set_code_flag
, CODE_32BIT
},
1304 {"code64", set_code_flag
, CODE_64BIT
},
1306 {"intel_syntax", set_intel_syntax
, 1},
1307 {"att_syntax", set_intel_syntax
, 0},
1308 {"intel_mnemonic", set_intel_mnemonic
, 1},
1309 {"att_mnemonic", set_intel_mnemonic
, 0},
1310 {"allow_index_reg", set_allow_index_reg
, 1},
1311 {"disallow_index_reg", set_allow_index_reg
, 0},
1312 {"sse_check", set_check
, 0},
1313 {"operand_check", set_check
, 1},
1314 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1315 {"largecomm", handle_large_common
, 0},
1317 {"file", dwarf2_directive_file
, 0},
1318 {"loc", dwarf2_directive_loc
, 0},
1319 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1322 {"secrel32", pe_directive_secrel
, 0},
1327 /* For interface with expression (). */
1328 extern char *input_line_pointer
;
1330 /* Hash table for instruction mnemonic lookup. */
1331 static struct hash_control
*op_hash
;
1333 /* Hash table for register lookup. */
1334 static struct hash_control
*reg_hash
;
1336 /* Various efficient no-op patterns for aligning code labels.
1337 Note: Don't try to assemble the instructions in the comments.
1338 0L and 0w are not legal. */
1339 static const unsigned char f32_1
[] =
1341 static const unsigned char f32_2
[] =
1342 {0x66,0x90}; /* xchg %ax,%ax */
1343 static const unsigned char f32_3
[] =
1344 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1345 static const unsigned char f32_4
[] =
1346 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1347 static const unsigned char f32_6
[] =
1348 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1349 static const unsigned char f32_7
[] =
1350 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1351 static const unsigned char f16_3
[] =
1352 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1353 static const unsigned char f16_4
[] =
1354 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1355 static const unsigned char jump_disp8
[] =
1356 {0xeb}; /* jmp disp8 */
1357 static const unsigned char jump32_disp32
[] =
1358 {0xe9}; /* jmp disp32 */
1359 static const unsigned char jump16_disp32
[] =
1360 {0x66,0xe9}; /* jmp disp32 */
1361 /* 32-bit NOPs patterns. */
1362 static const unsigned char *const f32_patt
[] = {
1363 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1365 /* 16-bit NOPs patterns. */
1366 static const unsigned char *const f16_patt
[] = {
1367 f32_1
, f32_2
, f16_3
, f16_4
1369 /* nopl (%[re]ax) */
1370 static const unsigned char alt_3
[] =
1372 /* nopl 0(%[re]ax) */
1373 static const unsigned char alt_4
[] =
1374 {0x0f,0x1f,0x40,0x00};
1375 /* nopl 0(%[re]ax,%[re]ax,1) */
1376 static const unsigned char alt_5
[] =
1377 {0x0f,0x1f,0x44,0x00,0x00};
1378 /* nopw 0(%[re]ax,%[re]ax,1) */
1379 static const unsigned char alt_6
[] =
1380 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1381 /* nopl 0L(%[re]ax) */
1382 static const unsigned char alt_7
[] =
1383 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1384 /* nopl 0L(%[re]ax,%[re]ax,1) */
1385 static const unsigned char alt_8
[] =
1386 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1387 /* nopw 0L(%[re]ax,%[re]ax,1) */
1388 static const unsigned char alt_9
[] =
1389 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1390 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1391 static const unsigned char alt_10
[] =
1392 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1393 /* data16 nopw %cs:0L(%eax,%eax,1) */
1394 static const unsigned char alt_11
[] =
1395 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1396 /* 32-bit and 64-bit NOPs patterns. */
1397 static const unsigned char *const alt_patt
[] = {
1398 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1399 alt_9
, alt_10
, alt_11
1402 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1403 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1406 i386_output_nops (char *where
, const unsigned char *const *patt
,
1407 int count
, int max_single_nop_size
)
1410 /* Place the longer NOP first. */
1413 const unsigned char *nops
;
1415 if (max_single_nop_size
< 1)
1417 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1418 max_single_nop_size
);
1422 nops
= patt
[max_single_nop_size
- 1];
1424 /* Use the smaller one if the requsted one isn't available. */
1427 max_single_nop_size
--;
1428 nops
= patt
[max_single_nop_size
- 1];
1431 last
= count
% max_single_nop_size
;
1434 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1435 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1439 nops
= patt
[last
- 1];
1442 /* Use the smaller one plus one-byte NOP if the needed one
1445 nops
= patt
[last
- 1];
1446 memcpy (where
+ offset
, nops
, last
);
1447 where
[offset
+ last
] = *patt
[0];
1450 memcpy (where
+ offset
, nops
, last
);
1455 fits_in_imm7 (offsetT num
)
1457 return (num
& 0x7f) == num
;
1461 fits_in_imm31 (offsetT num
)
1463 return (num
& 0x7fffffff) == num
;
1466 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1467 single NOP instruction LIMIT. */
1470 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1472 const unsigned char *const *patt
= NULL
;
1473 int max_single_nop_size
;
1474 /* Maximum number of NOPs before switching to jump over NOPs. */
1475 int max_number_of_nops
;
1477 switch (fragP
->fr_type
)
1482 case rs_machine_dependent
:
1483 /* Allow NOP padding for jumps and calls. */
1484 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1485 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1492 /* We need to decide which NOP sequence to use for 32bit and
1493 64bit. When -mtune= is used:
1495 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1496 PROCESSOR_GENERIC32, f32_patt will be used.
1497 2. For the rest, alt_patt will be used.
1499 When -mtune= isn't used, alt_patt will be used if
1500 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1503 When -march= or .arch is used, we can't use anything beyond
1504 cpu_arch_isa_flags. */
1506 if (flag_code
== CODE_16BIT
)
1509 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1510 /* Limit number of NOPs to 2 in 16-bit mode. */
1511 max_number_of_nops
= 2;
1515 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1517 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1518 switch (cpu_arch_tune
)
1520 case PROCESSOR_UNKNOWN
:
1521 /* We use cpu_arch_isa_flags to check if we SHOULD
1522 optimize with nops. */
1523 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1528 case PROCESSOR_PENTIUM4
:
1529 case PROCESSOR_NOCONA
:
1530 case PROCESSOR_CORE
:
1531 case PROCESSOR_CORE2
:
1532 case PROCESSOR_COREI7
:
1533 case PROCESSOR_L1OM
:
1534 case PROCESSOR_K1OM
:
1535 case PROCESSOR_GENERIC64
:
1537 case PROCESSOR_ATHLON
:
1539 case PROCESSOR_AMDFAM10
:
1541 case PROCESSOR_ZNVER
:
1545 case PROCESSOR_I386
:
1546 case PROCESSOR_I486
:
1547 case PROCESSOR_PENTIUM
:
1548 case PROCESSOR_PENTIUMPRO
:
1549 case PROCESSOR_IAMCU
:
1550 case PROCESSOR_GENERIC32
:
1557 switch (fragP
->tc_frag_data
.tune
)
1559 case PROCESSOR_UNKNOWN
:
1560 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1561 PROCESSOR_UNKNOWN. */
1565 case PROCESSOR_I386
:
1566 case PROCESSOR_I486
:
1567 case PROCESSOR_PENTIUM
:
1568 case PROCESSOR_IAMCU
:
1570 case PROCESSOR_ATHLON
:
1572 case PROCESSOR_AMDFAM10
:
1574 case PROCESSOR_ZNVER
:
1576 case PROCESSOR_GENERIC32
:
1577 /* We use cpu_arch_isa_flags to check if we CAN optimize
1579 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1584 case PROCESSOR_PENTIUMPRO
:
1585 case PROCESSOR_PENTIUM4
:
1586 case PROCESSOR_NOCONA
:
1587 case PROCESSOR_CORE
:
1588 case PROCESSOR_CORE2
:
1589 case PROCESSOR_COREI7
:
1590 case PROCESSOR_L1OM
:
1591 case PROCESSOR_K1OM
:
1592 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1597 case PROCESSOR_GENERIC64
:
1603 if (patt
== f32_patt
)
1605 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1606 /* Limit number of NOPs to 2 for older processors. */
1607 max_number_of_nops
= 2;
1611 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1612 /* Limit number of NOPs to 7 for newer processors. */
1613 max_number_of_nops
= 7;
1618 limit
= max_single_nop_size
;
1620 if (fragP
->fr_type
== rs_fill_nop
)
1622 /* Output NOPs for .nop directive. */
1623 if (limit
> max_single_nop_size
)
1625 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1626 _("invalid single nop size: %d "
1627 "(expect within [0, %d])"),
1628 limit
, max_single_nop_size
);
1632 else if (fragP
->fr_type
!= rs_machine_dependent
)
1633 fragP
->fr_var
= count
;
1635 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1637 /* Generate jump over NOPs. */
1638 offsetT disp
= count
- 2;
1639 if (fits_in_imm7 (disp
))
1641 /* Use "jmp disp8" if possible. */
1643 where
[0] = jump_disp8
[0];
1649 unsigned int size_of_jump
;
1651 if (flag_code
== CODE_16BIT
)
1653 where
[0] = jump16_disp32
[0];
1654 where
[1] = jump16_disp32
[1];
1659 where
[0] = jump32_disp32
[0];
1663 count
-= size_of_jump
+ 4;
1664 if (!fits_in_imm31 (count
))
1666 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1667 _("jump over nop padding out of range"));
1671 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1672 where
+= size_of_jump
+ 4;
1676 /* Generate multiple NOPs. */
1677 i386_output_nops (where
, patt
, count
, limit
);
1681 operand_type_all_zero (const union i386_operand_type
*x
)
1683 switch (ARRAY_SIZE(x
->array
))
1694 return !x
->array
[0];
1701 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1703 switch (ARRAY_SIZE(x
->array
))
1719 x
->bitfield
.class = ClassNone
;
1720 x
->bitfield
.instance
= InstanceNone
;
1724 operand_type_equal (const union i386_operand_type
*x
,
1725 const union i386_operand_type
*y
)
1727 switch (ARRAY_SIZE(x
->array
))
1730 if (x
->array
[2] != y
->array
[2])
1734 if (x
->array
[1] != y
->array
[1])
1738 return x
->array
[0] == y
->array
[0];
1746 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1748 switch (ARRAY_SIZE(x
->array
))
1763 return !x
->array
[0];
1770 cpu_flags_equal (const union i386_cpu_flags
*x
,
1771 const union i386_cpu_flags
*y
)
1773 switch (ARRAY_SIZE(x
->array
))
1776 if (x
->array
[3] != y
->array
[3])
1780 if (x
->array
[2] != y
->array
[2])
1784 if (x
->array
[1] != y
->array
[1])
1788 return x
->array
[0] == y
->array
[0];
1796 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1798 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1799 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1802 static INLINE i386_cpu_flags
1803 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[3] &= y
.array
[3];
1811 x
.array
[2] &= y
.array
[2];
1814 x
.array
[1] &= y
.array
[1];
1817 x
.array
[0] &= y
.array
[0];
1825 static INLINE i386_cpu_flags
1826 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1828 switch (ARRAY_SIZE (x
.array
))
1831 x
.array
[3] |= y
.array
[3];
1834 x
.array
[2] |= y
.array
[2];
1837 x
.array
[1] |= y
.array
[1];
1840 x
.array
[0] |= y
.array
[0];
1848 static INLINE i386_cpu_flags
1849 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1851 switch (ARRAY_SIZE (x
.array
))
1854 x
.array
[3] &= ~y
.array
[3];
1857 x
.array
[2] &= ~y
.array
[2];
1860 x
.array
[1] &= ~y
.array
[1];
1863 x
.array
[0] &= ~y
.array
[0];
1871 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1873 #define CPU_FLAGS_ARCH_MATCH 0x1
1874 #define CPU_FLAGS_64BIT_MATCH 0x2
1876 #define CPU_FLAGS_PERFECT_MATCH \
1877 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1879 /* Return CPU flags match bits. */
1882 cpu_flags_match (const insn_template
*t
)
1884 i386_cpu_flags x
= t
->cpu_flags
;
1885 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1887 x
.bitfield
.cpu64
= 0;
1888 x
.bitfield
.cpuno64
= 0;
1890 if (cpu_flags_all_zero (&x
))
1892 /* This instruction is available on all archs. */
1893 match
|= CPU_FLAGS_ARCH_MATCH
;
1897 /* This instruction is available only on some archs. */
1898 i386_cpu_flags cpu
= cpu_arch_flags
;
1900 /* AVX512VL is no standalone feature - match it and then strip it. */
1901 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1903 x
.bitfield
.cpuavx512vl
= 0;
1905 cpu
= cpu_flags_and (x
, cpu
);
1906 if (!cpu_flags_all_zero (&cpu
))
1908 if (x
.bitfield
.cpuavx
)
1910 /* We need to check a few extra flags with AVX. */
1911 if (cpu
.bitfield
.cpuavx
1912 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1913 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1914 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1915 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1916 match
|= CPU_FLAGS_ARCH_MATCH
;
1918 else if (x
.bitfield
.cpuavx512f
)
1920 /* We need to check a few extra flags with AVX512F. */
1921 if (cpu
.bitfield
.cpuavx512f
1922 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1923 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1924 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1925 match
|= CPU_FLAGS_ARCH_MATCH
;
1928 match
|= CPU_FLAGS_ARCH_MATCH
;
1934 static INLINE i386_operand_type
1935 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1937 if (x
.bitfield
.class != y
.bitfield
.class)
1938 x
.bitfield
.class = ClassNone
;
1939 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1940 x
.bitfield
.instance
= InstanceNone
;
1942 switch (ARRAY_SIZE (x
.array
))
1945 x
.array
[2] &= y
.array
[2];
1948 x
.array
[1] &= y
.array
[1];
1951 x
.array
[0] &= y
.array
[0];
1959 static INLINE i386_operand_type
1960 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1962 gas_assert (y
.bitfield
.class == ClassNone
);
1963 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1965 switch (ARRAY_SIZE (x
.array
))
1968 x
.array
[2] &= ~y
.array
[2];
1971 x
.array
[1] &= ~y
.array
[1];
1974 x
.array
[0] &= ~y
.array
[0];
1982 static INLINE i386_operand_type
1983 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1985 gas_assert (x
.bitfield
.class == ClassNone
||
1986 y
.bitfield
.class == ClassNone
||
1987 x
.bitfield
.class == y
.bitfield
.class);
1988 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1989 y
.bitfield
.instance
== InstanceNone
||
1990 x
.bitfield
.instance
== y
.bitfield
.instance
);
1992 switch (ARRAY_SIZE (x
.array
))
1995 x
.array
[2] |= y
.array
[2];
1998 x
.array
[1] |= y
.array
[1];
2001 x
.array
[0] |= y
.array
[0];
2009 static INLINE i386_operand_type
2010 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2012 gas_assert (y
.bitfield
.class == ClassNone
);
2013 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2015 switch (ARRAY_SIZE (x
.array
))
2018 x
.array
[2] ^= y
.array
[2];
2021 x
.array
[1] ^= y
.array
[1];
2024 x
.array
[0] ^= y
.array
[0];
2032 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2033 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2034 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2035 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2036 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2037 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2038 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2039 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2040 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2041 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2042 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2043 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2044 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2045 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2046 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2047 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2048 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2059 operand_type_check (i386_operand_type t
, enum operand_type c
)
2064 return t
.bitfield
.class == Reg
;
2067 return (t
.bitfield
.imm8
2071 || t
.bitfield
.imm32s
2072 || t
.bitfield
.imm64
);
2075 return (t
.bitfield
.disp8
2076 || t
.bitfield
.disp16
2077 || t
.bitfield
.disp32
2078 || t
.bitfield
.disp32s
2079 || t
.bitfield
.disp64
);
2082 return (t
.bitfield
.disp8
2083 || t
.bitfield
.disp16
2084 || t
.bitfield
.disp32
2085 || t
.bitfield
.disp32s
2086 || t
.bitfield
.disp64
2087 || t
.bitfield
.baseindex
);
2096 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2097 between operand GIVEN and opeand WANTED for instruction template T. */
2100 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2103 return !((i
.types
[given
].bitfield
.byte
2104 && !t
->operand_types
[wanted
].bitfield
.byte
)
2105 || (i
.types
[given
].bitfield
.word
2106 && !t
->operand_types
[wanted
].bitfield
.word
)
2107 || (i
.types
[given
].bitfield
.dword
2108 && !t
->operand_types
[wanted
].bitfield
.dword
)
2109 || (i
.types
[given
].bitfield
.qword
2110 && !t
->operand_types
[wanted
].bitfield
.qword
)
2111 || (i
.types
[given
].bitfield
.tbyte
2112 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2115 /* Return 1 if there is no conflict in SIMD register between operand
2116 GIVEN and opeand WANTED for instruction template T. */
2119 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2122 return !((i
.types
[given
].bitfield
.xmmword
2123 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2124 || (i
.types
[given
].bitfield
.ymmword
2125 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2126 || (i
.types
[given
].bitfield
.zmmword
2127 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2130 /* Return 1 if there is no conflict in any size between operand GIVEN
2131 and opeand WANTED for instruction template T. */
2134 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2137 return (match_operand_size (t
, wanted
, given
)
2138 && !((i
.types
[given
].bitfield
.unspecified
2140 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2141 || (i
.types
[given
].bitfield
.fword
2142 && !t
->operand_types
[wanted
].bitfield
.fword
)
2143 /* For scalar opcode templates to allow register and memory
2144 operands at the same time, some special casing is needed
2145 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2146 down-conversion vpmov*. */
2147 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2148 && !t
->opcode_modifier
.broadcast
2149 && (t
->operand_types
[wanted
].bitfield
.byte
2150 || t
->operand_types
[wanted
].bitfield
.word
2151 || t
->operand_types
[wanted
].bitfield
.dword
2152 || t
->operand_types
[wanted
].bitfield
.qword
))
2153 ? (i
.types
[given
].bitfield
.xmmword
2154 || i
.types
[given
].bitfield
.ymmword
2155 || i
.types
[given
].bitfield
.zmmword
)
2156 : !match_simd_size(t
, wanted
, given
))));
2159 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2160 operands for instruction template T, and it has MATCH_REVERSE set if there
2161 is no size conflict on any operands for the template with operands reversed
2162 (and the template allows for reversing in the first place). */
2164 #define MATCH_STRAIGHT 1
2165 #define MATCH_REVERSE 2
2167 static INLINE
unsigned int
2168 operand_size_match (const insn_template
*t
)
2170 unsigned int j
, match
= MATCH_STRAIGHT
;
2172 /* Don't check non-absolute jump instructions. */
2173 if (t
->opcode_modifier
.jump
2174 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2177 /* Check memory and accumulator operand size. */
2178 for (j
= 0; j
< i
.operands
; j
++)
2180 if (i
.types
[j
].bitfield
.class != Reg
2181 && i
.types
[j
].bitfield
.class != RegSIMD
2182 && t
->opcode_modifier
.anysize
)
2185 if (t
->operand_types
[j
].bitfield
.class == Reg
2186 && !match_operand_size (t
, j
, j
))
2192 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2193 && !match_simd_size (t
, j
, j
))
2199 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2200 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2206 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2213 if (!t
->opcode_modifier
.d
)
2217 i
.error
= operand_size_mismatch
;
2221 /* Check reverse. */
2222 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2224 for (j
= 0; j
< i
.operands
; j
++)
2226 unsigned int given
= i
.operands
- j
- 1;
2228 if (t
->operand_types
[j
].bitfield
.class == Reg
2229 && !match_operand_size (t
, j
, given
))
2232 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2233 && !match_simd_size (t
, j
, given
))
2236 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2237 && (!match_operand_size (t
, j
, given
)
2238 || !match_simd_size (t
, j
, given
)))
2241 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2245 return match
| MATCH_REVERSE
;
2249 operand_type_match (i386_operand_type overlap
,
2250 i386_operand_type given
)
2252 i386_operand_type temp
= overlap
;
2254 temp
.bitfield
.unspecified
= 0;
2255 temp
.bitfield
.byte
= 0;
2256 temp
.bitfield
.word
= 0;
2257 temp
.bitfield
.dword
= 0;
2258 temp
.bitfield
.fword
= 0;
2259 temp
.bitfield
.qword
= 0;
2260 temp
.bitfield
.tbyte
= 0;
2261 temp
.bitfield
.xmmword
= 0;
2262 temp
.bitfield
.ymmword
= 0;
2263 temp
.bitfield
.zmmword
= 0;
2264 if (operand_type_all_zero (&temp
))
2267 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2271 i
.error
= operand_type_mismatch
;
2275 /* If given types g0 and g1 are registers they must be of the same type
2276 unless the expected operand type register overlap is null.
2277 Some Intel syntax memory operand size checking also happens here. */
2280 operand_type_register_match (i386_operand_type g0
,
2281 i386_operand_type t0
,
2282 i386_operand_type g1
,
2283 i386_operand_type t1
)
2285 if (g0
.bitfield
.class != Reg
2286 && g0
.bitfield
.class != RegSIMD
2287 && (!operand_type_check (g0
, anymem
)
2288 || g0
.bitfield
.unspecified
2289 || (t0
.bitfield
.class != Reg
2290 && t0
.bitfield
.class != RegSIMD
)))
2293 if (g1
.bitfield
.class != Reg
2294 && g1
.bitfield
.class != RegSIMD
2295 && (!operand_type_check (g1
, anymem
)
2296 || g1
.bitfield
.unspecified
2297 || (t1
.bitfield
.class != Reg
2298 && t1
.bitfield
.class != RegSIMD
)))
2301 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2302 && g0
.bitfield
.word
== g1
.bitfield
.word
2303 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2304 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2305 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2306 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2307 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2310 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2311 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2312 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2313 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2314 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2315 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2316 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2319 i
.error
= register_type_mismatch
;
2324 static INLINE
unsigned int
2325 register_number (const reg_entry
*r
)
2327 unsigned int nr
= r
->reg_num
;
2329 if (r
->reg_flags
& RegRex
)
2332 if (r
->reg_flags
& RegVRex
)
2338 static INLINE
unsigned int
2339 mode_from_disp_size (i386_operand_type t
)
2341 if (t
.bitfield
.disp8
)
2343 else if (t
.bitfield
.disp16
2344 || t
.bitfield
.disp32
2345 || t
.bitfield
.disp32s
)
2352 fits_in_signed_byte (addressT num
)
2354 return num
+ 0x80 <= 0xff;
2358 fits_in_unsigned_byte (addressT num
)
2364 fits_in_unsigned_word (addressT num
)
2366 return num
<= 0xffff;
2370 fits_in_signed_word (addressT num
)
2372 return num
+ 0x8000 <= 0xffff;
2376 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2381 return num
+ 0x80000000 <= 0xffffffff;
2383 } /* fits_in_signed_long() */
2386 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2391 return num
<= 0xffffffff;
2393 } /* fits_in_unsigned_long() */
2396 fits_in_disp8 (offsetT num
)
2398 int shift
= i
.memshift
;
2404 mask
= (1 << shift
) - 1;
2406 /* Return 0 if NUM isn't properly aligned. */
2410 /* Check if NUM will fit in 8bit after shift. */
2411 return fits_in_signed_byte (num
>> shift
);
2415 fits_in_imm4 (offsetT num
)
2417 return (num
& 0xf) == num
;
2420 static i386_operand_type
2421 smallest_imm_type (offsetT num
)
2423 i386_operand_type t
;
2425 operand_type_set (&t
, 0);
2426 t
.bitfield
.imm64
= 1;
2428 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2430 /* This code is disabled on the 486 because all the Imm1 forms
2431 in the opcode table are slower on the i486. They're the
2432 versions with the implicitly specified single-position
2433 displacement, which has another syntax if you really want to
2435 t
.bitfield
.imm1
= 1;
2436 t
.bitfield
.imm8
= 1;
2437 t
.bitfield
.imm8s
= 1;
2438 t
.bitfield
.imm16
= 1;
2439 t
.bitfield
.imm32
= 1;
2440 t
.bitfield
.imm32s
= 1;
2442 else if (fits_in_signed_byte (num
))
2444 t
.bitfield
.imm8
= 1;
2445 t
.bitfield
.imm8s
= 1;
2446 t
.bitfield
.imm16
= 1;
2447 t
.bitfield
.imm32
= 1;
2448 t
.bitfield
.imm32s
= 1;
2450 else if (fits_in_unsigned_byte (num
))
2452 t
.bitfield
.imm8
= 1;
2453 t
.bitfield
.imm16
= 1;
2454 t
.bitfield
.imm32
= 1;
2455 t
.bitfield
.imm32s
= 1;
2457 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2459 t
.bitfield
.imm16
= 1;
2460 t
.bitfield
.imm32
= 1;
2461 t
.bitfield
.imm32s
= 1;
2463 else if (fits_in_signed_long (num
))
2465 t
.bitfield
.imm32
= 1;
2466 t
.bitfield
.imm32s
= 1;
2468 else if (fits_in_unsigned_long (num
))
2469 t
.bitfield
.imm32
= 1;
2475 offset_in_range (offsetT val
, int size
)
2481 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2482 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2483 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2485 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2491 /* If BFD64, sign extend val for 32bit address mode. */
2492 if (flag_code
!= CODE_64BIT
2493 || i
.prefix
[ADDR_PREFIX
])
2494 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2495 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2498 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2500 char buf1
[40], buf2
[40];
2502 sprint_value (buf1
, val
);
2503 sprint_value (buf2
, val
& mask
);
2504 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2519 a. PREFIX_EXIST if attempting to add a prefix where one from the
2520 same class already exists.
2521 b. PREFIX_LOCK if lock prefix is added.
2522 c. PREFIX_REP if rep/repne prefix is added.
2523 d. PREFIX_DS if ds prefix is added.
2524 e. PREFIX_OTHER if other prefix is added.
2527 static enum PREFIX_GROUP
2528 add_prefix (unsigned int prefix
)
2530 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2533 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2534 && flag_code
== CODE_64BIT
)
2536 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2537 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2538 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2539 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2550 case DS_PREFIX_OPCODE
:
2553 case CS_PREFIX_OPCODE
:
2554 case ES_PREFIX_OPCODE
:
2555 case FS_PREFIX_OPCODE
:
2556 case GS_PREFIX_OPCODE
:
2557 case SS_PREFIX_OPCODE
:
2561 case REPNE_PREFIX_OPCODE
:
2562 case REPE_PREFIX_OPCODE
:
2567 case LOCK_PREFIX_OPCODE
:
2576 case ADDR_PREFIX_OPCODE
:
2580 case DATA_PREFIX_OPCODE
:
2584 if (i
.prefix
[q
] != 0)
2592 i
.prefix
[q
] |= prefix
;
2595 as_bad (_("same type of prefix used twice"));
2601 update_code_flag (int value
, int check
)
2603 PRINTF_LIKE ((*as_error
));
2605 flag_code
= (enum flag_code
) value
;
2606 if (flag_code
== CODE_64BIT
)
2608 cpu_arch_flags
.bitfield
.cpu64
= 1;
2609 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2613 cpu_arch_flags
.bitfield
.cpu64
= 0;
2614 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2616 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2619 as_error
= as_fatal
;
2622 (*as_error
) (_("64bit mode not supported on `%s'."),
2623 cpu_arch_name
? cpu_arch_name
: default_arch
);
2625 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2628 as_error
= as_fatal
;
2631 (*as_error
) (_("32bit mode not supported on `%s'."),
2632 cpu_arch_name
? cpu_arch_name
: default_arch
);
2634 stackop_size
= '\0';
2638 set_code_flag (int value
)
2640 update_code_flag (value
, 0);
2644 set_16bit_gcc_code_flag (int new_code_flag
)
2646 flag_code
= (enum flag_code
) new_code_flag
;
2647 if (flag_code
!= CODE_16BIT
)
2649 cpu_arch_flags
.bitfield
.cpu64
= 0;
2650 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2651 stackop_size
= LONG_MNEM_SUFFIX
;
2655 set_intel_syntax (int syntax_flag
)
2657 /* Find out if register prefixing is specified. */
2658 int ask_naked_reg
= 0;
2661 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2664 int e
= get_symbol_name (&string
);
2666 if (strcmp (string
, "prefix") == 0)
2668 else if (strcmp (string
, "noprefix") == 0)
2671 as_bad (_("bad argument to syntax directive."));
2672 (void) restore_line_pointer (e
);
2674 demand_empty_rest_of_line ();
2676 intel_syntax
= syntax_flag
;
2678 if (ask_naked_reg
== 0)
2679 allow_naked_reg
= (intel_syntax
2680 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2682 allow_naked_reg
= (ask_naked_reg
< 0);
2684 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2686 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2687 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2688 register_prefix
= allow_naked_reg
? "" : "%";
2692 set_intel_mnemonic (int mnemonic_flag
)
2694 intel_mnemonic
= mnemonic_flag
;
2698 set_allow_index_reg (int flag
)
2700 allow_index_reg
= flag
;
2704 set_check (int what
)
2706 enum check_kind
*kind
;
2711 kind
= &operand_check
;
2722 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2725 int e
= get_symbol_name (&string
);
2727 if (strcmp (string
, "none") == 0)
2729 else if (strcmp (string
, "warning") == 0)
2730 *kind
= check_warning
;
2731 else if (strcmp (string
, "error") == 0)
2732 *kind
= check_error
;
2734 as_bad (_("bad argument to %s_check directive."), str
);
2735 (void) restore_line_pointer (e
);
2738 as_bad (_("missing argument for %s_check directive"), str
);
2740 demand_empty_rest_of_line ();
2744 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2745 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2747 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2748 static const char *arch
;
2750 /* Intel LIOM is only supported on ELF. */
2756 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2757 use default_arch. */
2758 arch
= cpu_arch_name
;
2760 arch
= default_arch
;
2763 /* If we are targeting Intel MCU, we must enable it. */
2764 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2765 || new_flag
.bitfield
.cpuiamcu
)
2768 /* If we are targeting Intel L1OM, we must enable it. */
2769 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2770 || new_flag
.bitfield
.cpul1om
)
2773 /* If we are targeting Intel K1OM, we must enable it. */
2774 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2775 || new_flag
.bitfield
.cpuk1om
)
2778 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2783 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2787 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2790 int e
= get_symbol_name (&string
);
2792 i386_cpu_flags flags
;
2794 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2796 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2798 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2802 cpu_arch_name
= cpu_arch
[j
].name
;
2803 cpu_sub_arch_name
= NULL
;
2804 cpu_arch_flags
= cpu_arch
[j
].flags
;
2805 if (flag_code
== CODE_64BIT
)
2807 cpu_arch_flags
.bitfield
.cpu64
= 1;
2808 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2812 cpu_arch_flags
.bitfield
.cpu64
= 0;
2813 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2815 cpu_arch_isa
= cpu_arch
[j
].type
;
2816 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2817 if (!cpu_arch_tune_set
)
2819 cpu_arch_tune
= cpu_arch_isa
;
2820 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2825 flags
= cpu_flags_or (cpu_arch_flags
,
2828 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2830 if (cpu_sub_arch_name
)
2832 char *name
= cpu_sub_arch_name
;
2833 cpu_sub_arch_name
= concat (name
,
2835 (const char *) NULL
);
2839 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2840 cpu_arch_flags
= flags
;
2841 cpu_arch_isa_flags
= flags
;
2845 = cpu_flags_or (cpu_arch_isa_flags
,
2847 (void) restore_line_pointer (e
);
2848 demand_empty_rest_of_line ();
2853 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2855 /* Disable an ISA extension. */
2856 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2857 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2859 flags
= cpu_flags_and_not (cpu_arch_flags
,
2860 cpu_noarch
[j
].flags
);
2861 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2863 if (cpu_sub_arch_name
)
2865 char *name
= cpu_sub_arch_name
;
2866 cpu_sub_arch_name
= concat (name
, string
,
2867 (const char *) NULL
);
2871 cpu_sub_arch_name
= xstrdup (string
);
2872 cpu_arch_flags
= flags
;
2873 cpu_arch_isa_flags
= flags
;
2875 (void) restore_line_pointer (e
);
2876 demand_empty_rest_of_line ();
2880 j
= ARRAY_SIZE (cpu_arch
);
2883 if (j
>= ARRAY_SIZE (cpu_arch
))
2884 as_bad (_("no such architecture: `%s'"), string
);
2886 *input_line_pointer
= e
;
2889 as_bad (_("missing cpu architecture"));
2891 no_cond_jump_promotion
= 0;
2892 if (*input_line_pointer
== ','
2893 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2898 ++input_line_pointer
;
2899 e
= get_symbol_name (&string
);
2901 if (strcmp (string
, "nojumps") == 0)
2902 no_cond_jump_promotion
= 1;
2903 else if (strcmp (string
, "jumps") == 0)
2906 as_bad (_("no such architecture modifier: `%s'"), string
);
2908 (void) restore_line_pointer (e
);
2911 demand_empty_rest_of_line ();
2914 enum bfd_architecture
2917 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2919 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2920 || flag_code
!= CODE_64BIT
)
2921 as_fatal (_("Intel L1OM is 64bit ELF only"));
2922 return bfd_arch_l1om
;
2924 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2926 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2927 || flag_code
!= CODE_64BIT
)
2928 as_fatal (_("Intel K1OM is 64bit ELF only"));
2929 return bfd_arch_k1om
;
2931 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2933 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2934 || flag_code
== CODE_64BIT
)
2935 as_fatal (_("Intel MCU is 32bit ELF only"));
2936 return bfd_arch_iamcu
;
2939 return bfd_arch_i386
;
2945 if (!strncmp (default_arch
, "x86_64", 6))
2947 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2949 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2950 || default_arch
[6] != '\0')
2951 as_fatal (_("Intel L1OM is 64bit ELF only"));
2952 return bfd_mach_l1om
;
2954 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2956 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2957 || default_arch
[6] != '\0')
2958 as_fatal (_("Intel K1OM is 64bit ELF only"));
2959 return bfd_mach_k1om
;
2961 else if (default_arch
[6] == '\0')
2962 return bfd_mach_x86_64
;
2964 return bfd_mach_x64_32
;
2966 else if (!strcmp (default_arch
, "i386")
2967 || !strcmp (default_arch
, "iamcu"))
2969 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2971 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2972 as_fatal (_("Intel MCU is 32bit ELF only"));
2973 return bfd_mach_i386_iamcu
;
2976 return bfd_mach_i386_i386
;
2979 as_fatal (_("unknown architecture"));
2985 const char *hash_err
;
2987 /* Support pseudo prefixes like {disp32}. */
2988 lex_type
['{'] = LEX_BEGIN_NAME
;
2990 /* Initialize op_hash hash table. */
2991 op_hash
= hash_new ();
2994 const insn_template
*optab
;
2995 templates
*core_optab
;
2997 /* Setup for loop. */
2999 core_optab
= XNEW (templates
);
3000 core_optab
->start
= optab
;
3005 if (optab
->name
== NULL
3006 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3008 /* different name --> ship out current template list;
3009 add to hash table; & begin anew. */
3010 core_optab
->end
= optab
;
3011 hash_err
= hash_insert (op_hash
,
3013 (void *) core_optab
);
3016 as_fatal (_("can't hash %s: %s"),
3020 if (optab
->name
== NULL
)
3022 core_optab
= XNEW (templates
);
3023 core_optab
->start
= optab
;
3028 /* Initialize reg_hash hash table. */
3029 reg_hash
= hash_new ();
3031 const reg_entry
*regtab
;
3032 unsigned int regtab_size
= i386_regtab_size
;
3034 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3036 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3038 as_fatal (_("can't hash %s: %s"),
3044 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3049 for (c
= 0; c
< 256; c
++)
3054 mnemonic_chars
[c
] = c
;
3055 register_chars
[c
] = c
;
3056 operand_chars
[c
] = c
;
3058 else if (ISLOWER (c
))
3060 mnemonic_chars
[c
] = c
;
3061 register_chars
[c
] = c
;
3062 operand_chars
[c
] = c
;
3064 else if (ISUPPER (c
))
3066 mnemonic_chars
[c
] = TOLOWER (c
);
3067 register_chars
[c
] = mnemonic_chars
[c
];
3068 operand_chars
[c
] = c
;
3070 else if (c
== '{' || c
== '}')
3072 mnemonic_chars
[c
] = c
;
3073 operand_chars
[c
] = c
;
3076 if (ISALPHA (c
) || ISDIGIT (c
))
3077 identifier_chars
[c
] = c
;
3080 identifier_chars
[c
] = c
;
3081 operand_chars
[c
] = c
;
3086 identifier_chars
['@'] = '@';
3089 identifier_chars
['?'] = '?';
3090 operand_chars
['?'] = '?';
3092 digit_chars
['-'] = '-';
3093 mnemonic_chars
['_'] = '_';
3094 mnemonic_chars
['-'] = '-';
3095 mnemonic_chars
['.'] = '.';
3096 identifier_chars
['_'] = '_';
3097 identifier_chars
['.'] = '.';
3099 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3100 operand_chars
[(unsigned char) *p
] = *p
;
3103 if (flag_code
== CODE_64BIT
)
3105 #if defined (OBJ_COFF) && defined (TE_PE)
3106 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3109 x86_dwarf2_return_column
= 16;
3111 x86_cie_data_alignment
= -8;
3115 x86_dwarf2_return_column
= 8;
3116 x86_cie_data_alignment
= -4;
3119 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3120 can be turned into BRANCH_PREFIX frag. */
3121 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3126 i386_print_statistics (FILE *file
)
3128 hash_print_statistics (file
, "i386 opcode", op_hash
);
3129 hash_print_statistics (file
, "i386 register", reg_hash
);
3134 /* Debugging routines for md_assemble. */
3135 static void pte (insn_template
*);
3136 static void pt (i386_operand_type
);
3137 static void pe (expressionS
*);
3138 static void ps (symbolS
*);
3141 pi (const char *line
, i386_insn
*x
)
3145 fprintf (stdout
, "%s: template ", line
);
3147 fprintf (stdout
, " address: base %s index %s scale %x\n",
3148 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3149 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3150 x
->log2_scale_factor
);
3151 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3152 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3153 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3154 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3155 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3156 (x
->rex
& REX_W
) != 0,
3157 (x
->rex
& REX_R
) != 0,
3158 (x
->rex
& REX_X
) != 0,
3159 (x
->rex
& REX_B
) != 0);
3160 for (j
= 0; j
< x
->operands
; j
++)
3162 fprintf (stdout
, " #%d: ", j
+ 1);
3164 fprintf (stdout
, "\n");
3165 if (x
->types
[j
].bitfield
.class == Reg
3166 || x
->types
[j
].bitfield
.class == RegMMX
3167 || x
->types
[j
].bitfield
.class == RegSIMD
3168 || x
->types
[j
].bitfield
.class == SReg
3169 || x
->types
[j
].bitfield
.class == RegCR
3170 || x
->types
[j
].bitfield
.class == RegDR
3171 || x
->types
[j
].bitfield
.class == RegTR
)
3172 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3173 if (operand_type_check (x
->types
[j
], imm
))
3175 if (operand_type_check (x
->types
[j
], disp
))
3176 pe (x
->op
[j
].disps
);
3181 pte (insn_template
*t
)
3184 fprintf (stdout
, " %d operands ", t
->operands
);
3185 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3186 if (t
->extension_opcode
!= None
)
3187 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3188 if (t
->opcode_modifier
.d
)
3189 fprintf (stdout
, "D");
3190 if (t
->opcode_modifier
.w
)
3191 fprintf (stdout
, "W");
3192 fprintf (stdout
, "\n");
3193 for (j
= 0; j
< t
->operands
; j
++)
3195 fprintf (stdout
, " #%d type ", j
+ 1);
3196 pt (t
->operand_types
[j
]);
3197 fprintf (stdout
, "\n");
3204 fprintf (stdout
, " operation %d\n", e
->X_op
);
3205 fprintf (stdout
, " add_number %ld (%lx)\n",
3206 (long) e
->X_add_number
, (long) e
->X_add_number
);
3207 if (e
->X_add_symbol
)
3209 fprintf (stdout
, " add_symbol ");
3210 ps (e
->X_add_symbol
);
3211 fprintf (stdout
, "\n");
3215 fprintf (stdout
, " op_symbol ");
3216 ps (e
->X_op_symbol
);
3217 fprintf (stdout
, "\n");
3224 fprintf (stdout
, "%s type %s%s",
3226 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3227 segment_name (S_GET_SEGMENT (s
)));
3230 static struct type_name
3232 i386_operand_type mask
;
3235 const type_names
[] =
3237 { OPERAND_TYPE_REG8
, "r8" },
3238 { OPERAND_TYPE_REG16
, "r16" },
3239 { OPERAND_TYPE_REG32
, "r32" },
3240 { OPERAND_TYPE_REG64
, "r64" },
3241 { OPERAND_TYPE_ACC8
, "acc8" },
3242 { OPERAND_TYPE_ACC16
, "acc16" },
3243 { OPERAND_TYPE_ACC32
, "acc32" },
3244 { OPERAND_TYPE_ACC64
, "acc64" },
3245 { OPERAND_TYPE_IMM8
, "i8" },
3246 { OPERAND_TYPE_IMM8
, "i8s" },
3247 { OPERAND_TYPE_IMM16
, "i16" },
3248 { OPERAND_TYPE_IMM32
, "i32" },
3249 { OPERAND_TYPE_IMM32S
, "i32s" },
3250 { OPERAND_TYPE_IMM64
, "i64" },
3251 { OPERAND_TYPE_IMM1
, "i1" },
3252 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3253 { OPERAND_TYPE_DISP8
, "d8" },
3254 { OPERAND_TYPE_DISP16
, "d16" },
3255 { OPERAND_TYPE_DISP32
, "d32" },
3256 { OPERAND_TYPE_DISP32S
, "d32s" },
3257 { OPERAND_TYPE_DISP64
, "d64" },
3258 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3259 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3260 { OPERAND_TYPE_CONTROL
, "control reg" },
3261 { OPERAND_TYPE_TEST
, "test reg" },
3262 { OPERAND_TYPE_DEBUG
, "debug reg" },
3263 { OPERAND_TYPE_FLOATREG
, "FReg" },
3264 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3265 { OPERAND_TYPE_SREG
, "SReg" },
3266 { OPERAND_TYPE_REGMMX
, "rMMX" },
3267 { OPERAND_TYPE_REGXMM
, "rXMM" },
3268 { OPERAND_TYPE_REGYMM
, "rYMM" },
3269 { OPERAND_TYPE_REGZMM
, "rZMM" },
3270 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3274 pt (i386_operand_type t
)
3277 i386_operand_type a
;
3279 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3281 a
= operand_type_and (t
, type_names
[j
].mask
);
3282 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3283 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3288 #endif /* DEBUG386 */
3290 static bfd_reloc_code_real_type
3291 reloc (unsigned int size
,
3294 bfd_reloc_code_real_type other
)
3296 if (other
!= NO_RELOC
)
3298 reloc_howto_type
*rel
;
3303 case BFD_RELOC_X86_64_GOT32
:
3304 return BFD_RELOC_X86_64_GOT64
;
3306 case BFD_RELOC_X86_64_GOTPLT64
:
3307 return BFD_RELOC_X86_64_GOTPLT64
;
3309 case BFD_RELOC_X86_64_PLTOFF64
:
3310 return BFD_RELOC_X86_64_PLTOFF64
;
3312 case BFD_RELOC_X86_64_GOTPC32
:
3313 other
= BFD_RELOC_X86_64_GOTPC64
;
3315 case BFD_RELOC_X86_64_GOTPCREL
:
3316 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3318 case BFD_RELOC_X86_64_TPOFF32
:
3319 other
= BFD_RELOC_X86_64_TPOFF64
;
3321 case BFD_RELOC_X86_64_DTPOFF32
:
3322 other
= BFD_RELOC_X86_64_DTPOFF64
;
3328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3329 if (other
== BFD_RELOC_SIZE32
)
3332 other
= BFD_RELOC_SIZE64
;
3335 as_bad (_("there are no pc-relative size relocations"));
3341 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3342 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3345 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3347 as_bad (_("unknown relocation (%u)"), other
);
3348 else if (size
!= bfd_get_reloc_size (rel
))
3349 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3350 bfd_get_reloc_size (rel
),
3352 else if (pcrel
&& !rel
->pc_relative
)
3353 as_bad (_("non-pc-relative relocation for pc-relative field"));
3354 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3356 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3358 as_bad (_("relocated field and relocation type differ in signedness"));
3367 as_bad (_("there are no unsigned pc-relative relocations"));
3370 case 1: return BFD_RELOC_8_PCREL
;
3371 case 2: return BFD_RELOC_16_PCREL
;
3372 case 4: return BFD_RELOC_32_PCREL
;
3373 case 8: return BFD_RELOC_64_PCREL
;
3375 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3382 case 4: return BFD_RELOC_X86_64_32S
;
3387 case 1: return BFD_RELOC_8
;
3388 case 2: return BFD_RELOC_16
;
3389 case 4: return BFD_RELOC_32
;
3390 case 8: return BFD_RELOC_64
;
3392 as_bad (_("cannot do %s %u byte relocation"),
3393 sign
> 0 ? "signed" : "unsigned", size
);
3399 /* Here we decide which fixups can be adjusted to make them relative to
3400 the beginning of the section instead of the symbol. Basically we need
3401 to make sure that the dynamic relocations are done correctly, so in
3402 some cases we force the original symbol to be used. */
3405 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3407 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3411 /* Don't adjust pc-relative references to merge sections in 64-bit
3413 if (use_rela_relocations
3414 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3418 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3419 and changed later by validate_fix. */
3420 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3421 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3424 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3425 for size relocations. */
3426 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3427 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3428 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3429 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3430 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3431 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3432 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3433 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3434 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3435 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3436 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3437 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3438 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3439 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3440 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3441 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3442 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3443 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3444 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3445 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3446 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3447 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3448 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3449 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3450 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3455 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3456 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3463 intel_float_operand (const char *mnemonic
)
3465 /* Note that the value returned is meaningful only for opcodes with (memory)
3466 operands, hence the code here is free to improperly handle opcodes that
3467 have no operands (for better performance and smaller code). */
3469 if (mnemonic
[0] != 'f')
3470 return 0; /* non-math */
3472 switch (mnemonic
[1])
3474 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3475 the fs segment override prefix not currently handled because no
3476 call path can make opcodes without operands get here */
3478 return 2 /* integer op */;
3480 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3481 return 3; /* fldcw/fldenv */
3484 if (mnemonic
[2] != 'o' /* fnop */)
3485 return 3; /* non-waiting control op */
3488 if (mnemonic
[2] == 's')
3489 return 3; /* frstor/frstpm */
3492 if (mnemonic
[2] == 'a')
3493 return 3; /* fsave */
3494 if (mnemonic
[2] == 't')
3496 switch (mnemonic
[3])
3498 case 'c': /* fstcw */
3499 case 'd': /* fstdw */
3500 case 'e': /* fstenv */
3501 case 's': /* fsts[gw] */
3507 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3508 return 0; /* fxsave/fxrstor are not really math ops */
3515 /* Build the VEX prefix. */
3518 build_vex_prefix (const insn_template
*t
)
3520 unsigned int register_specifier
;
3521 unsigned int implied_prefix
;
3522 unsigned int vector_length
;
3525 /* Check register specifier. */
3526 if (i
.vex
.register_specifier
)
3528 register_specifier
=
3529 ~register_number (i
.vex
.register_specifier
) & 0xf;
3530 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3533 register_specifier
= 0xf;
3535 /* Use 2-byte VEX prefix by swapping destination and source operand
3536 if there are more than 1 register operand. */
3537 if (i
.reg_operands
> 1
3538 && i
.vec_encoding
!= vex_encoding_vex3
3539 && i
.dir_encoding
== dir_encoding_default
3540 && i
.operands
== i
.reg_operands
3541 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3542 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3543 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3546 unsigned int xchg
= i
.operands
- 1;
3547 union i386_op temp_op
;
3548 i386_operand_type temp_type
;
3550 temp_type
= i
.types
[xchg
];
3551 i
.types
[xchg
] = i
.types
[0];
3552 i
.types
[0] = temp_type
;
3553 temp_op
= i
.op
[xchg
];
3554 i
.op
[xchg
] = i
.op
[0];
3557 gas_assert (i
.rm
.mode
== 3);
3561 i
.rm
.regmem
= i
.rm
.reg
;
3564 if (i
.tm
.opcode_modifier
.d
)
3565 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3566 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3567 else /* Use the next insn. */
3571 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3572 are no memory operands and at least 3 register ones. */
3573 if (i
.reg_operands
>= 3
3574 && i
.vec_encoding
!= vex_encoding_vex3
3575 && i
.reg_operands
== i
.operands
- i
.imm_operands
3576 && i
.tm
.opcode_modifier
.vex
3577 && i
.tm
.opcode_modifier
.commutative
3578 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3580 && i
.vex
.register_specifier
3581 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3583 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3584 union i386_op temp_op
;
3585 i386_operand_type temp_type
;
3587 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3588 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3589 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3590 &i
.types
[i
.operands
- 3]));
3591 gas_assert (i
.rm
.mode
== 3);
3593 temp_type
= i
.types
[xchg
];
3594 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3595 i
.types
[xchg
+ 1] = temp_type
;
3596 temp_op
= i
.op
[xchg
];
3597 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3598 i
.op
[xchg
+ 1] = temp_op
;
3601 xchg
= i
.rm
.regmem
| 8;
3602 i
.rm
.regmem
= ~register_specifier
& 0xf;
3603 gas_assert (!(i
.rm
.regmem
& 8));
3604 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3605 register_specifier
= ~xchg
& 0xf;
3608 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3609 vector_length
= avxscalar
;
3610 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3616 /* Determine vector length from the last multi-length vector
3619 for (op
= t
->operands
; op
--;)
3620 if (t
->operand_types
[op
].bitfield
.xmmword
3621 && t
->operand_types
[op
].bitfield
.ymmword
3622 && i
.types
[op
].bitfield
.ymmword
)
3629 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3634 case DATA_PREFIX_OPCODE
:
3637 case REPE_PREFIX_OPCODE
:
3640 case REPNE_PREFIX_OPCODE
:
3647 /* Check the REX.W bit and VEXW. */
3648 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3649 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3650 else if (i
.tm
.opcode_modifier
.vexw
)
3651 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3653 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3655 /* Use 2-byte VEX prefix if possible. */
3657 && i
.vec_encoding
!= vex_encoding_vex3
3658 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3659 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3661 /* 2-byte VEX prefix. */
3665 i
.vex
.bytes
[0] = 0xc5;
3667 /* Check the REX.R bit. */
3668 r
= (i
.rex
& REX_R
) ? 0 : 1;
3669 i
.vex
.bytes
[1] = (r
<< 7
3670 | register_specifier
<< 3
3671 | vector_length
<< 2
3676 /* 3-byte VEX prefix. */
3681 switch (i
.tm
.opcode_modifier
.vexopcode
)
3685 i
.vex
.bytes
[0] = 0xc4;
3689 i
.vex
.bytes
[0] = 0xc4;
3693 i
.vex
.bytes
[0] = 0xc4;
3697 i
.vex
.bytes
[0] = 0x8f;
3701 i
.vex
.bytes
[0] = 0x8f;
3705 i
.vex
.bytes
[0] = 0x8f;
3711 /* The high 3 bits of the second VEX byte are 1's compliment
3712 of RXB bits from REX. */
3713 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3715 i
.vex
.bytes
[2] = (w
<< 7
3716 | register_specifier
<< 3
3717 | vector_length
<< 2
3722 static INLINE bfd_boolean
3723 is_evex_encoding (const insn_template
*t
)
3725 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3726 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3727 || t
->opcode_modifier
.sae
;
3730 static INLINE bfd_boolean
3731 is_any_vex_encoding (const insn_template
*t
)
3733 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3734 || is_evex_encoding (t
);
3737 /* Build the EVEX prefix. */
3740 build_evex_prefix (void)
3742 unsigned int register_specifier
;
3743 unsigned int implied_prefix
;
3745 rex_byte vrex_used
= 0;
3747 /* Check register specifier. */
3748 if (i
.vex
.register_specifier
)
3750 gas_assert ((i
.vrex
& REX_X
) == 0);
3752 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3753 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3754 register_specifier
+= 8;
3755 /* The upper 16 registers are encoded in the fourth byte of the
3757 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3758 i
.vex
.bytes
[3] = 0x8;
3759 register_specifier
= ~register_specifier
& 0xf;
3763 register_specifier
= 0xf;
3765 /* Encode upper 16 vector index register in the fourth byte of
3767 if (!(i
.vrex
& REX_X
))
3768 i
.vex
.bytes
[3] = 0x8;
3773 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3778 case DATA_PREFIX_OPCODE
:
3781 case REPE_PREFIX_OPCODE
:
3784 case REPNE_PREFIX_OPCODE
:
3791 /* 4 byte EVEX prefix. */
3793 i
.vex
.bytes
[0] = 0x62;
3796 switch (i
.tm
.opcode_modifier
.vexopcode
)
3812 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3814 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3816 /* The fifth bit of the second EVEX byte is 1's compliment of the
3817 REX_R bit in VREX. */
3818 if (!(i
.vrex
& REX_R
))
3819 i
.vex
.bytes
[1] |= 0x10;
3823 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3825 /* When all operands are registers, the REX_X bit in REX is not
3826 used. We reuse it to encode the upper 16 registers, which is
3827 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3828 as 1's compliment. */
3829 if ((i
.vrex
& REX_B
))
3832 i
.vex
.bytes
[1] &= ~0x40;
3836 /* EVEX instructions shouldn't need the REX prefix. */
3837 i
.vrex
&= ~vrex_used
;
3838 gas_assert (i
.vrex
== 0);
3840 /* Check the REX.W bit and VEXW. */
3841 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3842 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3843 else if (i
.tm
.opcode_modifier
.vexw
)
3844 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3846 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3848 /* Encode the U bit. */
3849 implied_prefix
|= 0x4;
3851 /* The third byte of the EVEX prefix. */
3852 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3854 /* The fourth byte of the EVEX prefix. */
3855 /* The zeroing-masking bit. */
3856 if (i
.mask
&& i
.mask
->zeroing
)
3857 i
.vex
.bytes
[3] |= 0x80;
3859 /* Don't always set the broadcast bit if there is no RC. */
3862 /* Encode the vector length. */
3863 unsigned int vec_length
;
3865 if (!i
.tm
.opcode_modifier
.evex
3866 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3870 /* Determine vector length from the last multi-length vector
3873 for (op
= i
.operands
; op
--;)
3874 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3875 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3876 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3878 if (i
.types
[op
].bitfield
.zmmword
)
3880 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3883 else if (i
.types
[op
].bitfield
.ymmword
)
3885 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3888 else if (i
.types
[op
].bitfield
.xmmword
)
3890 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3893 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3895 switch (i
.broadcast
->bytes
)
3898 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3901 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3904 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3913 if (op
>= MAX_OPERANDS
)
3917 switch (i
.tm
.opcode_modifier
.evex
)
3919 case EVEXLIG
: /* LL' is ignored */
3920 vec_length
= evexlig
<< 5;
3923 vec_length
= 0 << 5;
3926 vec_length
= 1 << 5;
3929 vec_length
= 2 << 5;
3935 i
.vex
.bytes
[3] |= vec_length
;
3936 /* Encode the broadcast bit. */
3938 i
.vex
.bytes
[3] |= 0x10;
3942 if (i
.rounding
->type
!= saeonly
)
3943 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3945 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3948 if (i
.mask
&& i
.mask
->mask
)
3949 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3953 process_immext (void)
3957 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3958 which is coded in the same place as an 8-bit immediate field
3959 would be. Here we fake an 8-bit immediate operand from the
3960 opcode suffix stored in tm.extension_opcode.
3962 AVX instructions also use this encoding, for some of
3963 3 argument instructions. */
3965 gas_assert (i
.imm_operands
<= 1
3967 || (is_any_vex_encoding (&i
.tm
)
3968 && i
.operands
<= 4)));
3970 exp
= &im_expressions
[i
.imm_operands
++];
3971 i
.op
[i
.operands
].imms
= exp
;
3972 i
.types
[i
.operands
] = imm8
;
3974 exp
->X_op
= O_constant
;
3975 exp
->X_add_number
= i
.tm
.extension_opcode
;
3976 i
.tm
.extension_opcode
= None
;
3983 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3988 as_bad (_("invalid instruction `%s' after `%s'"),
3989 i
.tm
.name
, i
.hle_prefix
);
3992 if (i
.prefix
[LOCK_PREFIX
])
3994 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3998 case HLEPrefixRelease
:
3999 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4001 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4005 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4007 as_bad (_("memory destination needed for instruction `%s'"
4008 " after `xrelease'"), i
.tm
.name
);
4015 /* Try the shortest encoding by shortening operand size. */
4018 optimize_encoding (void)
4022 if (optimize_for_space
4023 && !is_any_vex_encoding (&i
.tm
)
4024 && i
.reg_operands
== 1
4025 && i
.imm_operands
== 1
4026 && !i
.types
[1].bitfield
.byte
4027 && i
.op
[0].imms
->X_op
== O_constant
4028 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4029 && (i
.tm
.base_opcode
== 0xa8
4030 || (i
.tm
.base_opcode
== 0xf6
4031 && i
.tm
.extension_opcode
== 0x0)))
4034 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4036 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4037 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4039 i
.types
[1].bitfield
.byte
= 1;
4040 /* Ignore the suffix. */
4042 /* Convert to byte registers. */
4043 if (i
.types
[1].bitfield
.word
)
4045 else if (i
.types
[1].bitfield
.dword
)
4049 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4054 else if (flag_code
== CODE_64BIT
4055 && !is_any_vex_encoding (&i
.tm
)
4056 && ((i
.types
[1].bitfield
.qword
4057 && i
.reg_operands
== 1
4058 && i
.imm_operands
== 1
4059 && i
.op
[0].imms
->X_op
== O_constant
4060 && ((i
.tm
.base_opcode
== 0xb8
4061 && i
.tm
.extension_opcode
== None
4062 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4063 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4064 && ((i
.tm
.base_opcode
== 0x24
4065 || i
.tm
.base_opcode
== 0xa8)
4066 || (i
.tm
.base_opcode
== 0x80
4067 && i
.tm
.extension_opcode
== 0x4)
4068 || ((i
.tm
.base_opcode
== 0xf6
4069 || (i
.tm
.base_opcode
| 1) == 0xc7)
4070 && i
.tm
.extension_opcode
== 0x0)))
4071 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4072 && i
.tm
.base_opcode
== 0x83
4073 && i
.tm
.extension_opcode
== 0x4)))
4074 || (i
.types
[0].bitfield
.qword
4075 && ((i
.reg_operands
== 2
4076 && i
.op
[0].regs
== i
.op
[1].regs
4077 && (i
.tm
.base_opcode
== 0x30
4078 || i
.tm
.base_opcode
== 0x28))
4079 || (i
.reg_operands
== 1
4081 && i
.tm
.base_opcode
== 0x30)))))
4084 andq $imm31, %r64 -> andl $imm31, %r32
4085 andq $imm7, %r64 -> andl $imm7, %r32
4086 testq $imm31, %r64 -> testl $imm31, %r32
4087 xorq %r64, %r64 -> xorl %r32, %r32
4088 subq %r64, %r64 -> subl %r32, %r32
4089 movq $imm31, %r64 -> movl $imm31, %r32
4090 movq $imm32, %r64 -> movl $imm32, %r32
4092 i
.tm
.opcode_modifier
.norex64
= 1;
4093 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4096 movq $imm31, %r64 -> movl $imm31, %r32
4097 movq $imm32, %r64 -> movl $imm32, %r32
4099 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4100 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4101 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4102 i
.types
[0].bitfield
.imm32
= 1;
4103 i
.types
[0].bitfield
.imm32s
= 0;
4104 i
.types
[0].bitfield
.imm64
= 0;
4105 i
.types
[1].bitfield
.dword
= 1;
4106 i
.types
[1].bitfield
.qword
= 0;
4107 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4110 movq $imm31, %r64 -> movl $imm31, %r32
4112 i
.tm
.base_opcode
= 0xb8;
4113 i
.tm
.extension_opcode
= None
;
4114 i
.tm
.opcode_modifier
.w
= 0;
4115 i
.tm
.opcode_modifier
.modrm
= 0;
4119 else if (optimize
> 1
4120 && !optimize_for_space
4121 && !is_any_vex_encoding (&i
.tm
)
4122 && i
.reg_operands
== 2
4123 && i
.op
[0].regs
== i
.op
[1].regs
4124 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4125 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4126 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4129 andb %rN, %rN -> testb %rN, %rN
4130 andw %rN, %rN -> testw %rN, %rN
4131 andq %rN, %rN -> testq %rN, %rN
4132 orb %rN, %rN -> testb %rN, %rN
4133 orw %rN, %rN -> testw %rN, %rN
4134 orq %rN, %rN -> testq %rN, %rN
4136 and outside of 64-bit mode
4138 andl %rN, %rN -> testl %rN, %rN
4139 orl %rN, %rN -> testl %rN, %rN
4141 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4143 else if (i
.reg_operands
== 3
4144 && i
.op
[0].regs
== i
.op
[1].regs
4145 && !i
.types
[2].bitfield
.xmmword
4146 && (i
.tm
.opcode_modifier
.vex
4147 || ((!i
.mask
|| i
.mask
->zeroing
)
4149 && is_evex_encoding (&i
.tm
)
4150 && (i
.vec_encoding
!= vex_encoding_evex
4151 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4152 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4153 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4154 && i
.types
[2].bitfield
.ymmword
))))
4155 && ((i
.tm
.base_opcode
== 0x55
4156 || i
.tm
.base_opcode
== 0x6655
4157 || i
.tm
.base_opcode
== 0x66df
4158 || i
.tm
.base_opcode
== 0x57
4159 || i
.tm
.base_opcode
== 0x6657
4160 || i
.tm
.base_opcode
== 0x66ef
4161 || i
.tm
.base_opcode
== 0x66f8
4162 || i
.tm
.base_opcode
== 0x66f9
4163 || i
.tm
.base_opcode
== 0x66fa
4164 || i
.tm
.base_opcode
== 0x66fb
4165 || i
.tm
.base_opcode
== 0x42
4166 || i
.tm
.base_opcode
== 0x6642
4167 || i
.tm
.base_opcode
== 0x47
4168 || i
.tm
.base_opcode
== 0x6647)
4169 && i
.tm
.extension_opcode
== None
))
4172 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4174 EVEX VOP %zmmM, %zmmM, %zmmN
4175 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4176 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4177 EVEX VOP %ymmM, %ymmM, %ymmN
4178 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4179 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4180 VEX VOP %ymmM, %ymmM, %ymmN
4181 -> VEX VOP %xmmM, %xmmM, %xmmN
4182 VOP, one of vpandn and vpxor:
4183 VEX VOP %ymmM, %ymmM, %ymmN
4184 -> VEX VOP %xmmM, %xmmM, %xmmN
4185 VOP, one of vpandnd and vpandnq:
4186 EVEX VOP %zmmM, %zmmM, %zmmN
4187 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4188 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4189 EVEX VOP %ymmM, %ymmM, %ymmN
4190 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4191 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4192 VOP, one of vpxord and vpxorq:
4193 EVEX VOP %zmmM, %zmmM, %zmmN
4194 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4195 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4196 EVEX VOP %ymmM, %ymmM, %ymmN
4197 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4198 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4199 VOP, one of kxord and kxorq:
4200 VEX VOP %kM, %kM, %kN
4201 -> VEX kxorw %kM, %kM, %kN
4202 VOP, one of kandnd and kandnq:
4203 VEX VOP %kM, %kM, %kN
4204 -> VEX kandnw %kM, %kM, %kN
4206 if (is_evex_encoding (&i
.tm
))
4208 if (i
.vec_encoding
!= vex_encoding_evex
)
4210 i
.tm
.opcode_modifier
.vex
= VEX128
;
4211 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4212 i
.tm
.opcode_modifier
.evex
= 0;
4214 else if (optimize
> 1)
4215 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4219 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4221 i
.tm
.base_opcode
&= 0xff;
4222 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4225 i
.tm
.opcode_modifier
.vex
= VEX128
;
4227 if (i
.tm
.opcode_modifier
.vex
)
4228 for (j
= 0; j
< 3; j
++)
4230 i
.types
[j
].bitfield
.xmmword
= 1;
4231 i
.types
[j
].bitfield
.ymmword
= 0;
4234 else if (i
.vec_encoding
!= vex_encoding_evex
4235 && !i
.types
[0].bitfield
.zmmword
4236 && !i
.types
[1].bitfield
.zmmword
4239 && is_evex_encoding (&i
.tm
)
4240 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4241 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4242 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4243 || (i
.tm
.base_opcode
& ~4) == 0x66db
4244 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4245 && i
.tm
.extension_opcode
== None
)
4248 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4249 vmovdqu32 and vmovdqu64:
4250 EVEX VOP %xmmM, %xmmN
4251 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4252 EVEX VOP %ymmM, %ymmN
4253 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4255 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4257 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4259 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4261 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4262 VOP, one of vpand, vpandn, vpor, vpxor:
4263 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4264 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4265 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4266 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4267 EVEX VOP{d,q} mem, %xmmM, %xmmN
4268 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4269 EVEX VOP{d,q} mem, %ymmM, %ymmN
4270 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4272 for (j
= 0; j
< i
.operands
; j
++)
4273 if (operand_type_check (i
.types
[j
], disp
)
4274 && i
.op
[j
].disps
->X_op
== O_constant
)
4276 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4277 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4278 bytes, we choose EVEX Disp8 over VEX Disp32. */
4279 int evex_disp8
, vex_disp8
;
4280 unsigned int memshift
= i
.memshift
;
4281 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4283 evex_disp8
= fits_in_disp8 (n
);
4285 vex_disp8
= fits_in_disp8 (n
);
4286 if (evex_disp8
!= vex_disp8
)
4288 i
.memshift
= memshift
;
4292 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4295 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4296 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4297 i
.tm
.opcode_modifier
.vex
4298 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4299 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4300 /* VPAND, VPOR, and VPXOR are commutative. */
4301 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4302 i
.tm
.opcode_modifier
.commutative
= 1;
4303 i
.tm
.opcode_modifier
.evex
= 0;
4304 i
.tm
.opcode_modifier
.masking
= 0;
4305 i
.tm
.opcode_modifier
.broadcast
= 0;
4306 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4309 i
.types
[j
].bitfield
.disp8
4310 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4314 /* This is the guts of the machine-dependent assembler. LINE points to a
4315 machine dependent instruction. This function is supposed to emit
4316 the frags/bytes it assembles to. */
4319 md_assemble (char *line
)
4322 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4323 const insn_template
*t
;
4325 /* Initialize globals. */
4326 memset (&i
, '\0', sizeof (i
));
4327 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4328 i
.reloc
[j
] = NO_RELOC
;
4329 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4330 memset (im_expressions
, '\0', sizeof (im_expressions
));
4331 save_stack_p
= save_stack
;
4333 /* First parse an instruction mnemonic & call i386_operand for the operands.
4334 We assume that the scrubber has arranged it so that line[0] is the valid
4335 start of a (possibly prefixed) mnemonic. */
4337 line
= parse_insn (line
, mnemonic
);
4340 mnem_suffix
= i
.suffix
;
4342 line
= parse_operands (line
, mnemonic
);
4344 xfree (i
.memop1_string
);
4345 i
.memop1_string
= NULL
;
4349 /* Now we've parsed the mnemonic into a set of templates, and have the
4350 operands at hand. */
4352 /* All Intel opcodes have reversed operands except for "bound", "enter",
4353 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4354 intersegment "jmp" and "call" instructions with 2 immediate operands so
4355 that the immediate segment precedes the offset, as it does when in AT&T
4359 && (strcmp (mnemonic
, "bound") != 0)
4360 && (strcmp (mnemonic
, "invlpga") != 0)
4361 && (strncmp (mnemonic
, "monitor", 7) != 0)
4362 && (strncmp (mnemonic
, "mwait", 5) != 0)
4363 && (strcmp (mnemonic
, "tpause") != 0)
4364 && (strcmp (mnemonic
, "umwait") != 0)
4365 && !(operand_type_check (i
.types
[0], imm
)
4366 && operand_type_check (i
.types
[1], imm
)))
4369 /* The order of the immediates should be reversed
4370 for 2 immediates extrq and insertq instructions */
4371 if (i
.imm_operands
== 2
4372 && (strcmp (mnemonic
, "extrq") == 0
4373 || strcmp (mnemonic
, "insertq") == 0))
4374 swap_2_operands (0, 1);
4379 /* Don't optimize displacement for movabs since it only takes 64bit
4382 && i
.disp_encoding
!= disp_encoding_32bit
4383 && (flag_code
!= CODE_64BIT
4384 || strcmp (mnemonic
, "movabs") != 0))
4387 /* Next, we find a template that matches the given insn,
4388 making sure the overlap of the given operands types is consistent
4389 with the template operand types. */
4391 if (!(t
= match_template (mnem_suffix
)))
4394 if (sse_check
!= check_none
4395 && !i
.tm
.opcode_modifier
.noavx
4396 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4397 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4398 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4399 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4400 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4401 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4402 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4403 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4404 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4405 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4406 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4407 || i
.tm
.cpu_flags
.bitfield
.cpusha
4408 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4410 (sse_check
== check_warning
4412 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4415 if (i
.tm
.opcode_modifier
.fwait
)
4416 if (!add_prefix (FWAIT_OPCODE
))
4419 /* Check if REP prefix is OK. */
4420 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4422 as_bad (_("invalid instruction `%s' after `%s'"),
4423 i
.tm
.name
, i
.rep_prefix
);
4427 /* Check for lock without a lockable instruction. Destination operand
4428 must be memory unless it is xchg (0x86). */
4429 if (i
.prefix
[LOCK_PREFIX
]
4430 && (!i
.tm
.opcode_modifier
.islockable
4431 || i
.mem_operands
== 0
4432 || (i
.tm
.base_opcode
!= 0x86
4433 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4435 as_bad (_("expecting lockable instruction after `lock'"));
4439 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4440 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4442 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4446 /* Check if HLE prefix is OK. */
4447 if (i
.hle_prefix
&& !check_hle ())
4450 /* Check BND prefix. */
4451 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4452 as_bad (_("expecting valid branch instruction after `bnd'"));
4454 /* Check NOTRACK prefix. */
4455 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4456 as_bad (_("expecting indirect branch instruction after `notrack'"));
4458 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4460 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4461 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4462 else if (flag_code
!= CODE_16BIT
4463 ? i
.prefix
[ADDR_PREFIX
]
4464 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4465 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4468 /* Insert BND prefix. */
4469 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4471 if (!i
.prefix
[BND_PREFIX
])
4472 add_prefix (BND_PREFIX_OPCODE
);
4473 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4475 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4476 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4480 /* Check string instruction segment overrides. */
4481 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4483 gas_assert (i
.mem_operands
);
4484 if (!check_string ())
4486 i
.disp_operands
= 0;
4489 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4490 optimize_encoding ();
4492 if (!process_suffix ())
4495 /* Update operand types. */
4496 for (j
= 0; j
< i
.operands
; j
++)
4497 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4499 /* Make still unresolved immediate matches conform to size of immediate
4500 given in i.suffix. */
4501 if (!finalize_imm ())
4504 if (i
.types
[0].bitfield
.imm1
)
4505 i
.imm_operands
= 0; /* kludge for shift insns. */
4507 /* We only need to check those implicit registers for instructions
4508 with 3 operands or less. */
4509 if (i
.operands
<= 3)
4510 for (j
= 0; j
< i
.operands
; j
++)
4511 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4512 && !i
.types
[j
].bitfield
.xmmword
)
4515 /* ImmExt should be processed after SSE2AVX. */
4516 if (!i
.tm
.opcode_modifier
.sse2avx
4517 && i
.tm
.opcode_modifier
.immext
)
4520 /* For insns with operands there are more diddles to do to the opcode. */
4523 if (!process_operands ())
4526 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4528 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4529 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4532 if (is_any_vex_encoding (&i
.tm
))
4534 if (!cpu_arch_flags
.bitfield
.cpui286
)
4536 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4541 if (i
.tm
.opcode_modifier
.vex
)
4542 build_vex_prefix (t
);
4544 build_evex_prefix ();
4547 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4548 instructions may define INT_OPCODE as well, so avoid this corner
4549 case for those instructions that use MODRM. */
4550 if (i
.tm
.base_opcode
== INT_OPCODE
4551 && !i
.tm
.opcode_modifier
.modrm
4552 && i
.op
[0].imms
->X_add_number
== 3)
4554 i
.tm
.base_opcode
= INT3_OPCODE
;
4558 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4559 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4560 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4561 && i
.op
[0].disps
->X_op
== O_constant
)
4563 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4564 the absolute address given by the constant. Since ix86 jumps and
4565 calls are pc relative, we need to generate a reloc. */
4566 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4567 i
.op
[0].disps
->X_op
= O_symbol
;
4570 if (i
.tm
.opcode_modifier
.rex64
)
4573 /* For 8 bit registers we need an empty rex prefix. Also if the
4574 instruction already has a prefix, we need to convert old
4575 registers to new ones. */
4577 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4578 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4579 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4580 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4581 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4582 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4587 i
.rex
|= REX_OPCODE
;
4588 for (x
= 0; x
< 2; x
++)
4590 /* Look for 8 bit operand that uses old registers. */
4591 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4592 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4594 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4595 /* In case it is "hi" register, give up. */
4596 if (i
.op
[x
].regs
->reg_num
> 3)
4597 as_bad (_("can't encode register '%s%s' in an "
4598 "instruction requiring REX prefix."),
4599 register_prefix
, i
.op
[x
].regs
->reg_name
);
4601 /* Otherwise it is equivalent to the extended register.
4602 Since the encoding doesn't change this is merely
4603 cosmetic cleanup for debug output. */
4605 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4610 if (i
.rex
== 0 && i
.rex_encoding
)
4612 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4613 that uses legacy register. If it is "hi" register, don't add
4614 the REX_OPCODE byte. */
4616 for (x
= 0; x
< 2; x
++)
4617 if (i
.types
[x
].bitfield
.class == Reg
4618 && i
.types
[x
].bitfield
.byte
4619 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4620 && i
.op
[x
].regs
->reg_num
> 3)
4622 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4623 i
.rex_encoding
= FALSE
;
4632 add_prefix (REX_OPCODE
| i
.rex
);
4634 /* We are ready to output the insn. */
4637 last_insn
.seg
= now_seg
;
4639 if (i
.tm
.opcode_modifier
.isprefix
)
4641 last_insn
.kind
= last_insn_prefix
;
4642 last_insn
.name
= i
.tm
.name
;
4643 last_insn
.file
= as_where (&last_insn
.line
);
4646 last_insn
.kind
= last_insn_other
;
4650 parse_insn (char *line
, char *mnemonic
)
4653 char *token_start
= l
;
4656 const insn_template
*t
;
4662 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4667 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4669 as_bad (_("no such instruction: `%s'"), token_start
);
4674 if (!is_space_char (*l
)
4675 && *l
!= END_OF_INSN
4677 || (*l
!= PREFIX_SEPARATOR
4680 as_bad (_("invalid character %s in mnemonic"),
4681 output_invalid (*l
));
4684 if (token_start
== l
)
4686 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4687 as_bad (_("expecting prefix; got nothing"));
4689 as_bad (_("expecting mnemonic; got nothing"));
4693 /* Look up instruction (or prefix) via hash table. */
4694 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4696 if (*l
!= END_OF_INSN
4697 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4698 && current_templates
4699 && current_templates
->start
->opcode_modifier
.isprefix
)
4701 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4703 as_bad ((flag_code
!= CODE_64BIT
4704 ? _("`%s' is only supported in 64-bit mode")
4705 : _("`%s' is not supported in 64-bit mode")),
4706 current_templates
->start
->name
);
4709 /* If we are in 16-bit mode, do not allow addr16 or data16.
4710 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4711 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4712 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4713 && flag_code
!= CODE_64BIT
4714 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4715 ^ (flag_code
== CODE_16BIT
)))
4717 as_bad (_("redundant %s prefix"),
4718 current_templates
->start
->name
);
4721 if (current_templates
->start
->opcode_length
== 0)
4723 /* Handle pseudo prefixes. */
4724 switch (current_templates
->start
->base_opcode
)
4728 i
.disp_encoding
= disp_encoding_8bit
;
4732 i
.disp_encoding
= disp_encoding_32bit
;
4736 i
.dir_encoding
= dir_encoding_load
;
4740 i
.dir_encoding
= dir_encoding_store
;
4744 i
.vec_encoding
= vex_encoding_vex
;
4748 i
.vec_encoding
= vex_encoding_vex3
;
4752 i
.vec_encoding
= vex_encoding_evex
;
4756 i
.rex_encoding
= TRUE
;
4760 i
.no_optimize
= TRUE
;
4768 /* Add prefix, checking for repeated prefixes. */
4769 switch (add_prefix (current_templates
->start
->base_opcode
))
4774 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4775 i
.notrack_prefix
= current_templates
->start
->name
;
4778 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4779 i
.hle_prefix
= current_templates
->start
->name
;
4780 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4781 i
.bnd_prefix
= current_templates
->start
->name
;
4783 i
.rep_prefix
= current_templates
->start
->name
;
4789 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4796 if (!current_templates
)
4798 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4799 Check if we should swap operand or force 32bit displacement in
4801 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4802 i
.dir_encoding
= dir_encoding_swap
;
4803 else if (mnem_p
- 3 == dot_p
4806 i
.disp_encoding
= disp_encoding_8bit
;
4807 else if (mnem_p
- 4 == dot_p
4811 i
.disp_encoding
= disp_encoding_32bit
;
4816 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4819 if (!current_templates
)
4822 if (mnem_p
> mnemonic
)
4824 /* See if we can get a match by trimming off a suffix. */
4827 case WORD_MNEM_SUFFIX
:
4828 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4829 i
.suffix
= SHORT_MNEM_SUFFIX
;
4832 case BYTE_MNEM_SUFFIX
:
4833 case QWORD_MNEM_SUFFIX
:
4834 i
.suffix
= mnem_p
[-1];
4836 current_templates
= (const templates
*) hash_find (op_hash
,
4839 case SHORT_MNEM_SUFFIX
:
4840 case LONG_MNEM_SUFFIX
:
4843 i
.suffix
= mnem_p
[-1];
4845 current_templates
= (const templates
*) hash_find (op_hash
,
4854 if (intel_float_operand (mnemonic
) == 1)
4855 i
.suffix
= SHORT_MNEM_SUFFIX
;
4857 i
.suffix
= LONG_MNEM_SUFFIX
;
4859 current_templates
= (const templates
*) hash_find (op_hash
,
4866 if (!current_templates
)
4868 as_bad (_("no such instruction: `%s'"), token_start
);
4873 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4874 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4876 /* Check for a branch hint. We allow ",pt" and ",pn" for
4877 predict taken and predict not taken respectively.
4878 I'm not sure that branch hints actually do anything on loop
4879 and jcxz insns (JumpByte) for current Pentium4 chips. They
4880 may work in the future and it doesn't hurt to accept them
4882 if (l
[0] == ',' && l
[1] == 'p')
4886 if (!add_prefix (DS_PREFIX_OPCODE
))
4890 else if (l
[2] == 'n')
4892 if (!add_prefix (CS_PREFIX_OPCODE
))
4898 /* Any other comma loses. */
4901 as_bad (_("invalid character %s in mnemonic"),
4902 output_invalid (*l
));
4906 /* Check if instruction is supported on specified architecture. */
4908 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4910 supported
|= cpu_flags_match (t
);
4911 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4913 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4914 as_warn (_("use .code16 to ensure correct addressing mode"));
4920 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4921 as_bad (flag_code
== CODE_64BIT
4922 ? _("`%s' is not supported in 64-bit mode")
4923 : _("`%s' is only supported in 64-bit mode"),
4924 current_templates
->start
->name
);
4926 as_bad (_("`%s' is not supported on `%s%s'"),
4927 current_templates
->start
->name
,
4928 cpu_arch_name
? cpu_arch_name
: default_arch
,
4929 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4935 parse_operands (char *l
, const char *mnemonic
)
4939 /* 1 if operand is pending after ','. */
4940 unsigned int expecting_operand
= 0;
4942 /* Non-zero if operand parens not balanced. */
4943 unsigned int paren_not_balanced
;
4945 while (*l
!= END_OF_INSN
)
4947 /* Skip optional white space before operand. */
4948 if (is_space_char (*l
))
4950 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4952 as_bad (_("invalid character %s before operand %d"),
4953 output_invalid (*l
),
4957 token_start
= l
; /* After white space. */
4958 paren_not_balanced
= 0;
4959 while (paren_not_balanced
|| *l
!= ',')
4961 if (*l
== END_OF_INSN
)
4963 if (paren_not_balanced
)
4966 as_bad (_("unbalanced parenthesis in operand %d."),
4969 as_bad (_("unbalanced brackets in operand %d."),
4974 break; /* we are done */
4976 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4978 as_bad (_("invalid character %s in operand %d"),
4979 output_invalid (*l
),
4986 ++paren_not_balanced
;
4988 --paren_not_balanced
;
4993 ++paren_not_balanced
;
4995 --paren_not_balanced
;
4999 if (l
!= token_start
)
5000 { /* Yes, we've read in another operand. */
5001 unsigned int operand_ok
;
5002 this_operand
= i
.operands
++;
5003 if (i
.operands
> MAX_OPERANDS
)
5005 as_bad (_("spurious operands; (%d operands/instruction max)"),
5009 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5010 /* Now parse operand adding info to 'i' as we go along. */
5011 END_STRING_AND_SAVE (l
);
5013 if (i
.mem_operands
> 1)
5015 as_bad (_("too many memory references for `%s'"),
5022 i386_intel_operand (token_start
,
5023 intel_float_operand (mnemonic
));
5025 operand_ok
= i386_att_operand (token_start
);
5027 RESTORE_END_STRING (l
);
5033 if (expecting_operand
)
5035 expecting_operand_after_comma
:
5036 as_bad (_("expecting operand after ','; got nothing"));
5041 as_bad (_("expecting operand before ','; got nothing"));
5046 /* Now *l must be either ',' or END_OF_INSN. */
5049 if (*++l
== END_OF_INSN
)
5051 /* Just skip it, if it's \n complain. */
5052 goto expecting_operand_after_comma
;
5054 expecting_operand
= 1;
5061 swap_2_operands (int xchg1
, int xchg2
)
5063 union i386_op temp_op
;
5064 i386_operand_type temp_type
;
5065 unsigned int temp_flags
;
5066 enum bfd_reloc_code_real temp_reloc
;
5068 temp_type
= i
.types
[xchg2
];
5069 i
.types
[xchg2
] = i
.types
[xchg1
];
5070 i
.types
[xchg1
] = temp_type
;
5072 temp_flags
= i
.flags
[xchg2
];
5073 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5074 i
.flags
[xchg1
] = temp_flags
;
5076 temp_op
= i
.op
[xchg2
];
5077 i
.op
[xchg2
] = i
.op
[xchg1
];
5078 i
.op
[xchg1
] = temp_op
;
5080 temp_reloc
= i
.reloc
[xchg2
];
5081 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5082 i
.reloc
[xchg1
] = temp_reloc
;
5086 if (i
.mask
->operand
== xchg1
)
5087 i
.mask
->operand
= xchg2
;
5088 else if (i
.mask
->operand
== xchg2
)
5089 i
.mask
->operand
= xchg1
;
5093 if (i
.broadcast
->operand
== xchg1
)
5094 i
.broadcast
->operand
= xchg2
;
5095 else if (i
.broadcast
->operand
== xchg2
)
5096 i
.broadcast
->operand
= xchg1
;
5100 if (i
.rounding
->operand
== xchg1
)
5101 i
.rounding
->operand
= xchg2
;
5102 else if (i
.rounding
->operand
== xchg2
)
5103 i
.rounding
->operand
= xchg1
;
5108 swap_operands (void)
5114 swap_2_operands (1, i
.operands
- 2);
5118 swap_2_operands (0, i
.operands
- 1);
5124 if (i
.mem_operands
== 2)
5126 const seg_entry
*temp_seg
;
5127 temp_seg
= i
.seg
[0];
5128 i
.seg
[0] = i
.seg
[1];
5129 i
.seg
[1] = temp_seg
;
5133 /* Try to ensure constant immediates are represented in the smallest
5138 char guess_suffix
= 0;
5142 guess_suffix
= i
.suffix
;
5143 else if (i
.reg_operands
)
5145 /* Figure out a suffix from the last register operand specified.
5146 We can't do this properly yet, i.e. excluding special register
5147 instances, but the following works for instructions with
5148 immediates. In any case, we can't set i.suffix yet. */
5149 for (op
= i
.operands
; --op
>= 0;)
5150 if (i
.types
[op
].bitfield
.class != Reg
)
5152 else if (i
.types
[op
].bitfield
.byte
)
5154 guess_suffix
= BYTE_MNEM_SUFFIX
;
5157 else if (i
.types
[op
].bitfield
.word
)
5159 guess_suffix
= WORD_MNEM_SUFFIX
;
5162 else if (i
.types
[op
].bitfield
.dword
)
5164 guess_suffix
= LONG_MNEM_SUFFIX
;
5167 else if (i
.types
[op
].bitfield
.qword
)
5169 guess_suffix
= QWORD_MNEM_SUFFIX
;
5173 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5174 guess_suffix
= WORD_MNEM_SUFFIX
;
5176 for (op
= i
.operands
; --op
>= 0;)
5177 if (operand_type_check (i
.types
[op
], imm
))
5179 switch (i
.op
[op
].imms
->X_op
)
5182 /* If a suffix is given, this operand may be shortened. */
5183 switch (guess_suffix
)
5185 case LONG_MNEM_SUFFIX
:
5186 i
.types
[op
].bitfield
.imm32
= 1;
5187 i
.types
[op
].bitfield
.imm64
= 1;
5189 case WORD_MNEM_SUFFIX
:
5190 i
.types
[op
].bitfield
.imm16
= 1;
5191 i
.types
[op
].bitfield
.imm32
= 1;
5192 i
.types
[op
].bitfield
.imm32s
= 1;
5193 i
.types
[op
].bitfield
.imm64
= 1;
5195 case BYTE_MNEM_SUFFIX
:
5196 i
.types
[op
].bitfield
.imm8
= 1;
5197 i
.types
[op
].bitfield
.imm8s
= 1;
5198 i
.types
[op
].bitfield
.imm16
= 1;
5199 i
.types
[op
].bitfield
.imm32
= 1;
5200 i
.types
[op
].bitfield
.imm32s
= 1;
5201 i
.types
[op
].bitfield
.imm64
= 1;
5205 /* If this operand is at most 16 bits, convert it
5206 to a signed 16 bit number before trying to see
5207 whether it will fit in an even smaller size.
5208 This allows a 16-bit operand such as $0xffe0 to
5209 be recognised as within Imm8S range. */
5210 if ((i
.types
[op
].bitfield
.imm16
)
5211 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5213 i
.op
[op
].imms
->X_add_number
=
5214 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5217 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5218 if ((i
.types
[op
].bitfield
.imm32
)
5219 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5222 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5223 ^ ((offsetT
) 1 << 31))
5224 - ((offsetT
) 1 << 31));
5228 = operand_type_or (i
.types
[op
],
5229 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5231 /* We must avoid matching of Imm32 templates when 64bit
5232 only immediate is available. */
5233 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5234 i
.types
[op
].bitfield
.imm32
= 0;
5241 /* Symbols and expressions. */
5243 /* Convert symbolic operand to proper sizes for matching, but don't
5244 prevent matching a set of insns that only supports sizes other
5245 than those matching the insn suffix. */
5247 i386_operand_type mask
, allowed
;
5248 const insn_template
*t
;
5250 operand_type_set (&mask
, 0);
5251 operand_type_set (&allowed
, 0);
5253 for (t
= current_templates
->start
;
5254 t
< current_templates
->end
;
5257 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5258 allowed
= operand_type_and (allowed
, anyimm
);
5260 switch (guess_suffix
)
5262 case QWORD_MNEM_SUFFIX
:
5263 mask
.bitfield
.imm64
= 1;
5264 mask
.bitfield
.imm32s
= 1;
5266 case LONG_MNEM_SUFFIX
:
5267 mask
.bitfield
.imm32
= 1;
5269 case WORD_MNEM_SUFFIX
:
5270 mask
.bitfield
.imm16
= 1;
5272 case BYTE_MNEM_SUFFIX
:
5273 mask
.bitfield
.imm8
= 1;
5278 allowed
= operand_type_and (mask
, allowed
);
5279 if (!operand_type_all_zero (&allowed
))
5280 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5287 /* Try to use the smallest displacement type too. */
5289 optimize_disp (void)
5293 for (op
= i
.operands
; --op
>= 0;)
5294 if (operand_type_check (i
.types
[op
], disp
))
5296 if (i
.op
[op
].disps
->X_op
== O_constant
)
5298 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5300 if (i
.types
[op
].bitfield
.disp16
5301 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5303 /* If this operand is at most 16 bits, convert
5304 to a signed 16 bit number and don't use 64bit
5306 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5307 i
.types
[op
].bitfield
.disp64
= 0;
5310 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5311 if (i
.types
[op
].bitfield
.disp32
5312 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5314 /* If this operand is at most 32 bits, convert
5315 to a signed 32 bit number and don't use 64bit
5317 op_disp
&= (((offsetT
) 2 << 31) - 1);
5318 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5319 i
.types
[op
].bitfield
.disp64
= 0;
5322 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5324 i
.types
[op
].bitfield
.disp8
= 0;
5325 i
.types
[op
].bitfield
.disp16
= 0;
5326 i
.types
[op
].bitfield
.disp32
= 0;
5327 i
.types
[op
].bitfield
.disp32s
= 0;
5328 i
.types
[op
].bitfield
.disp64
= 0;
5332 else if (flag_code
== CODE_64BIT
)
5334 if (fits_in_signed_long (op_disp
))
5336 i
.types
[op
].bitfield
.disp64
= 0;
5337 i
.types
[op
].bitfield
.disp32s
= 1;
5339 if (i
.prefix
[ADDR_PREFIX
]
5340 && fits_in_unsigned_long (op_disp
))
5341 i
.types
[op
].bitfield
.disp32
= 1;
5343 if ((i
.types
[op
].bitfield
.disp32
5344 || i
.types
[op
].bitfield
.disp32s
5345 || i
.types
[op
].bitfield
.disp16
)
5346 && fits_in_disp8 (op_disp
))
5347 i
.types
[op
].bitfield
.disp8
= 1;
5349 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5350 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5352 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5353 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5354 i
.types
[op
].bitfield
.disp8
= 0;
5355 i
.types
[op
].bitfield
.disp16
= 0;
5356 i
.types
[op
].bitfield
.disp32
= 0;
5357 i
.types
[op
].bitfield
.disp32s
= 0;
5358 i
.types
[op
].bitfield
.disp64
= 0;
5361 /* We only support 64bit displacement on constants. */
5362 i
.types
[op
].bitfield
.disp64
= 0;
5366 /* Return 1 if there is a match in broadcast bytes between operand
5367 GIVEN and instruction template T. */
5370 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5372 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5373 && i
.types
[given
].bitfield
.byte
)
5374 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5375 && i
.types
[given
].bitfield
.word
)
5376 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5377 && i
.types
[given
].bitfield
.dword
)
5378 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5379 && i
.types
[given
].bitfield
.qword
));
5382 /* Check if operands are valid for the instruction. */
5385 check_VecOperands (const insn_template
*t
)
5390 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5391 any one operand are implicity requiring AVX512VL support if the actual
5392 operand size is YMMword or XMMword. Since this function runs after
5393 template matching, there's no need to check for YMMword/XMMword in
5395 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5396 if (!cpu_flags_all_zero (&cpu
)
5397 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5398 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5400 for (op
= 0; op
< t
->operands
; ++op
)
5402 if (t
->operand_types
[op
].bitfield
.zmmword
5403 && (i
.types
[op
].bitfield
.ymmword
5404 || i
.types
[op
].bitfield
.xmmword
))
5406 i
.error
= unsupported
;
5412 /* Without VSIB byte, we can't have a vector register for index. */
5413 if (!t
->opcode_modifier
.vecsib
5415 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5416 || i
.index_reg
->reg_type
.bitfield
.ymmword
5417 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5419 i
.error
= unsupported_vector_index_register
;
5423 /* Check if default mask is allowed. */
5424 if (t
->opcode_modifier
.nodefmask
5425 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5427 i
.error
= no_default_mask
;
5431 /* For VSIB byte, we need a vector register for index, and all vector
5432 registers must be distinct. */
5433 if (t
->opcode_modifier
.vecsib
)
5436 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5437 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5438 || (t
->opcode_modifier
.vecsib
== VecSIB256
5439 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5440 || (t
->opcode_modifier
.vecsib
== VecSIB512
5441 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5443 i
.error
= invalid_vsib_address
;
5447 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5448 if (i
.reg_operands
== 2 && !i
.mask
)
5450 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5451 gas_assert (i
.types
[0].bitfield
.xmmword
5452 || i
.types
[0].bitfield
.ymmword
);
5453 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5454 gas_assert (i
.types
[2].bitfield
.xmmword
5455 || i
.types
[2].bitfield
.ymmword
);
5456 if (operand_check
== check_none
)
5458 if (register_number (i
.op
[0].regs
)
5459 != register_number (i
.index_reg
)
5460 && register_number (i
.op
[2].regs
)
5461 != register_number (i
.index_reg
)
5462 && register_number (i
.op
[0].regs
)
5463 != register_number (i
.op
[2].regs
))
5465 if (operand_check
== check_error
)
5467 i
.error
= invalid_vector_register_set
;
5470 as_warn (_("mask, index, and destination registers should be distinct"));
5472 else if (i
.reg_operands
== 1 && i
.mask
)
5474 if (i
.types
[1].bitfield
.class == RegSIMD
5475 && (i
.types
[1].bitfield
.xmmword
5476 || i
.types
[1].bitfield
.ymmword
5477 || i
.types
[1].bitfield
.zmmword
)
5478 && (register_number (i
.op
[1].regs
)
5479 == register_number (i
.index_reg
)))
5481 if (operand_check
== check_error
)
5483 i
.error
= invalid_vector_register_set
;
5486 if (operand_check
!= check_none
)
5487 as_warn (_("index and destination registers should be distinct"));
5492 /* Check if broadcast is supported by the instruction and is applied
5493 to the memory operand. */
5496 i386_operand_type type
, overlap
;
5498 /* Check if specified broadcast is supported in this instruction,
5499 and its broadcast bytes match the memory operand. */
5500 op
= i
.broadcast
->operand
;
5501 if (!t
->opcode_modifier
.broadcast
5502 || !(i
.flags
[op
] & Operand_Mem
)
5503 || (!i
.types
[op
].bitfield
.unspecified
5504 && !match_broadcast_size (t
, op
)))
5507 i
.error
= unsupported_broadcast
;
5511 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5512 * i
.broadcast
->type
);
5513 operand_type_set (&type
, 0);
5514 switch (i
.broadcast
->bytes
)
5517 type
.bitfield
.word
= 1;
5520 type
.bitfield
.dword
= 1;
5523 type
.bitfield
.qword
= 1;
5526 type
.bitfield
.xmmword
= 1;
5529 type
.bitfield
.ymmword
= 1;
5532 type
.bitfield
.zmmword
= 1;
5538 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5539 if (operand_type_all_zero (&overlap
))
5542 if (t
->opcode_modifier
.checkregsize
)
5546 type
.bitfield
.baseindex
= 1;
5547 for (j
= 0; j
< i
.operands
; ++j
)
5550 && !operand_type_register_match(i
.types
[j
],
5551 t
->operand_types
[j
],
5553 t
->operand_types
[op
]))
5558 /* If broadcast is supported in this instruction, we need to check if
5559 operand of one-element size isn't specified without broadcast. */
5560 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5562 /* Find memory operand. */
5563 for (op
= 0; op
< i
.operands
; op
++)
5564 if (i
.flags
[op
] & Operand_Mem
)
5566 gas_assert (op
< i
.operands
);
5567 /* Check size of the memory operand. */
5568 if (match_broadcast_size (t
, op
))
5570 i
.error
= broadcast_needed
;
5575 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5577 /* Check if requested masking is supported. */
5580 switch (t
->opcode_modifier
.masking
)
5584 case MERGING_MASKING
:
5585 if (i
.mask
->zeroing
)
5588 i
.error
= unsupported_masking
;
5592 case DYNAMIC_MASKING
:
5593 /* Memory destinations allow only merging masking. */
5594 if (i
.mask
->zeroing
&& i
.mem_operands
)
5596 /* Find memory operand. */
5597 for (op
= 0; op
< i
.operands
; op
++)
5598 if (i
.flags
[op
] & Operand_Mem
)
5600 gas_assert (op
< i
.operands
);
5601 if (op
== i
.operands
- 1)
5603 i
.error
= unsupported_masking
;
5613 /* Check if masking is applied to dest operand. */
5614 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5616 i
.error
= mask_not_on_destination
;
5623 if (!t
->opcode_modifier
.sae
5624 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5626 i
.error
= unsupported_rc_sae
;
5629 /* If the instruction has several immediate operands and one of
5630 them is rounding, the rounding operand should be the last
5631 immediate operand. */
5632 if (i
.imm_operands
> 1
5633 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5635 i
.error
= rc_sae_operand_not_last_imm
;
5640 /* Check vector Disp8 operand. */
5641 if (t
->opcode_modifier
.disp8memshift
5642 && i
.disp_encoding
!= disp_encoding_32bit
)
5645 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5646 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5647 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5650 const i386_operand_type
*type
= NULL
;
5653 for (op
= 0; op
< i
.operands
; op
++)
5654 if (i
.flags
[op
] & Operand_Mem
)
5656 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5657 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5658 else if (t
->operand_types
[op
].bitfield
.xmmword
5659 + t
->operand_types
[op
].bitfield
.ymmword
5660 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5661 type
= &t
->operand_types
[op
];
5662 else if (!i
.types
[op
].bitfield
.unspecified
)
5663 type
= &i
.types
[op
];
5665 else if (i
.types
[op
].bitfield
.class == RegSIMD
5666 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5668 if (i
.types
[op
].bitfield
.zmmword
)
5670 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5672 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5678 if (type
->bitfield
.zmmword
)
5680 else if (type
->bitfield
.ymmword
)
5682 else if (type
->bitfield
.xmmword
)
5686 /* For the check in fits_in_disp8(). */
5687 if (i
.memshift
== 0)
5691 for (op
= 0; op
< i
.operands
; op
++)
5692 if (operand_type_check (i
.types
[op
], disp
)
5693 && i
.op
[op
].disps
->X_op
== O_constant
)
5695 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5697 i
.types
[op
].bitfield
.disp8
= 1;
5700 i
.types
[op
].bitfield
.disp8
= 0;
5709 /* Check if operands are valid for the instruction. Update VEX
5713 VEX_check_operands (const insn_template
*t
)
5715 if (i
.vec_encoding
== vex_encoding_evex
)
5717 /* This instruction must be encoded with EVEX prefix. */
5718 if (!is_evex_encoding (t
))
5720 i
.error
= unsupported
;
5726 if (!t
->opcode_modifier
.vex
)
5728 /* This instruction template doesn't have VEX prefix. */
5729 if (i
.vec_encoding
!= vex_encoding_default
)
5731 i
.error
= unsupported
;
5737 /* Check the special Imm4 cases; must be the first operand. */
5738 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5740 if (i
.op
[0].imms
->X_op
!= O_constant
5741 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5747 /* Turn off Imm<N> so that update_imm won't complain. */
5748 operand_type_set (&i
.types
[0], 0);
5754 static const insn_template
*
5755 match_template (char mnem_suffix
)
5757 /* Points to template once we've found it. */
5758 const insn_template
*t
;
5759 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5760 i386_operand_type overlap4
;
5761 unsigned int found_reverse_match
;
5762 i386_opcode_modifier suffix_check
;
5763 i386_operand_type operand_types
[MAX_OPERANDS
];
5764 int addr_prefix_disp
;
5765 unsigned int j
, size_match
, check_register
;
5766 enum i386_error specific_error
= 0;
5768 #if MAX_OPERANDS != 5
5769 # error "MAX_OPERANDS must be 5."
5772 found_reverse_match
= 0;
5773 addr_prefix_disp
= -1;
5775 /* Prepare for mnemonic suffix check. */
5776 memset (&suffix_check
, 0, sizeof (suffix_check
));
5777 switch (mnem_suffix
)
5779 case BYTE_MNEM_SUFFIX
:
5780 suffix_check
.no_bsuf
= 1;
5782 case WORD_MNEM_SUFFIX
:
5783 suffix_check
.no_wsuf
= 1;
5785 case SHORT_MNEM_SUFFIX
:
5786 suffix_check
.no_ssuf
= 1;
5788 case LONG_MNEM_SUFFIX
:
5789 suffix_check
.no_lsuf
= 1;
5791 case QWORD_MNEM_SUFFIX
:
5792 suffix_check
.no_qsuf
= 1;
5795 /* NB: In Intel syntax, normally we can check for memory operand
5796 size when there is no mnemonic suffix. But jmp and call have
5797 2 different encodings with Dword memory operand size, one with
5798 No_ldSuf and the other without. i.suffix is set to
5799 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5800 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5801 suffix_check
.no_ldsuf
= 1;
5804 /* Must have right number of operands. */
5805 i
.error
= number_of_operands_mismatch
;
5807 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5809 addr_prefix_disp
= -1;
5810 found_reverse_match
= 0;
5812 if (i
.operands
!= t
->operands
)
5815 /* Check processor support. */
5816 i
.error
= unsupported
;
5817 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5820 /* Check AT&T mnemonic. */
5821 i
.error
= unsupported_with_intel_mnemonic
;
5822 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5825 /* Check AT&T/Intel syntax. */
5826 i
.error
= unsupported_syntax
;
5827 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5828 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5831 /* Check Intel64/AMD64 ISA. */
5835 /* Default: Don't accept Intel64. */
5836 if (t
->opcode_modifier
.isa64
== INTEL64
)
5840 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5841 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5845 /* -mintel64: Don't accept AMD64. */
5846 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5851 /* Check the suffix. */
5852 i
.error
= invalid_instruction_suffix
;
5853 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5854 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5855 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5856 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5857 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5858 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5861 size_match
= operand_size_match (t
);
5865 /* This is intentionally not
5867 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5869 as the case of a missing * on the operand is accepted (perhaps with
5870 a warning, issued further down). */
5871 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5873 i
.error
= operand_type_mismatch
;
5877 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5878 operand_types
[j
] = t
->operand_types
[j
];
5880 /* In general, don't allow 64-bit operands in 32-bit mode. */
5881 if (i
.suffix
== QWORD_MNEM_SUFFIX
5882 && flag_code
!= CODE_64BIT
5884 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5885 && !t
->opcode_modifier
.broadcast
5886 && !intel_float_operand (t
->name
))
5887 : intel_float_operand (t
->name
) != 2)
5888 && ((operand_types
[0].bitfield
.class != RegMMX
5889 && operand_types
[0].bitfield
.class != RegSIMD
)
5890 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5891 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5892 && (t
->base_opcode
!= 0x0fc7
5893 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5896 /* In general, don't allow 32-bit operands on pre-386. */
5897 else if (i
.suffix
== LONG_MNEM_SUFFIX
5898 && !cpu_arch_flags
.bitfield
.cpui386
5900 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
5901 && !intel_float_operand (t
->name
))
5902 : intel_float_operand (t
->name
) != 2)
5903 && ((operand_types
[0].bitfield
.class != RegMMX
5904 && operand_types
[0].bitfield
.class != RegSIMD
)
5905 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5906 && operand_types
[t
->operands
> 1].bitfield
.class
5910 /* Do not verify operands when there are none. */
5914 /* We've found a match; break out of loop. */
5918 if (!t
->opcode_modifier
.jump
5919 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5921 /* There should be only one Disp operand. */
5922 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5923 if (operand_type_check (operand_types
[j
], disp
))
5925 if (j
< MAX_OPERANDS
)
5927 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5929 addr_prefix_disp
= j
;
5931 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5932 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5936 override
= !override
;
5939 if (operand_types
[j
].bitfield
.disp32
5940 && operand_types
[j
].bitfield
.disp16
)
5942 operand_types
[j
].bitfield
.disp16
= override
;
5943 operand_types
[j
].bitfield
.disp32
= !override
;
5945 operand_types
[j
].bitfield
.disp32s
= 0;
5946 operand_types
[j
].bitfield
.disp64
= 0;
5950 if (operand_types
[j
].bitfield
.disp32s
5951 || operand_types
[j
].bitfield
.disp64
)
5953 operand_types
[j
].bitfield
.disp64
&= !override
;
5954 operand_types
[j
].bitfield
.disp32s
&= !override
;
5955 operand_types
[j
].bitfield
.disp32
= override
;
5957 operand_types
[j
].bitfield
.disp16
= 0;
5963 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5964 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5967 /* We check register size if needed. */
5968 if (t
->opcode_modifier
.checkregsize
)
5970 check_register
= (1 << t
->operands
) - 1;
5972 check_register
&= ~(1 << i
.broadcast
->operand
);
5977 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5978 switch (t
->operands
)
5981 if (!operand_type_match (overlap0
, i
.types
[0]))
5985 /* xchg %eax, %eax is a special case. It is an alias for nop
5986 only in 32bit mode and we can use opcode 0x90. In 64bit
5987 mode, we can't use 0x90 for xchg %eax, %eax since it should
5988 zero-extend %eax to %rax. */
5989 if (flag_code
== CODE_64BIT
5990 && t
->base_opcode
== 0x90
5991 && i
.types
[0].bitfield
.instance
== Accum
5992 && i
.types
[0].bitfield
.dword
5993 && i
.types
[1].bitfield
.instance
== Accum
5994 && i
.types
[1].bitfield
.dword
)
5996 /* xrelease mov %eax, <disp> is another special case. It must not
5997 match the accumulator-only encoding of mov. */
5998 if (flag_code
!= CODE_64BIT
6000 && t
->base_opcode
== 0xa0
6001 && i
.types
[0].bitfield
.instance
== Accum
6002 && (i
.flags
[1] & Operand_Mem
))
6007 if (!(size_match
& MATCH_STRAIGHT
))
6009 /* Reverse direction of operands if swapping is possible in the first
6010 place (operands need to be symmetric) and
6011 - the load form is requested, and the template is a store form,
6012 - the store form is requested, and the template is a load form,
6013 - the non-default (swapped) form is requested. */
6014 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6015 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6016 && !operand_type_all_zero (&overlap1
))
6017 switch (i
.dir_encoding
)
6019 case dir_encoding_load
:
6020 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6021 || t
->opcode_modifier
.regmem
)
6025 case dir_encoding_store
:
6026 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6027 && !t
->opcode_modifier
.regmem
)
6031 case dir_encoding_swap
:
6034 case dir_encoding_default
:
6037 /* If we want store form, we skip the current load. */
6038 if ((i
.dir_encoding
== dir_encoding_store
6039 || i
.dir_encoding
== dir_encoding_swap
)
6040 && i
.mem_operands
== 0
6041 && t
->opcode_modifier
.load
)
6046 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6047 if (!operand_type_match (overlap0
, i
.types
[0])
6048 || !operand_type_match (overlap1
, i
.types
[1])
6049 || ((check_register
& 3) == 3
6050 && !operand_type_register_match (i
.types
[0],
6055 /* Check if other direction is valid ... */
6056 if (!t
->opcode_modifier
.d
)
6060 if (!(size_match
& MATCH_REVERSE
))
6062 /* Try reversing direction of operands. */
6063 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6064 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6065 if (!operand_type_match (overlap0
, i
.types
[0])
6066 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6068 && !operand_type_register_match (i
.types
[0],
6069 operand_types
[i
.operands
- 1],
6070 i
.types
[i
.operands
- 1],
6073 /* Does not match either direction. */
6076 /* found_reverse_match holds which of D or FloatR
6078 if (!t
->opcode_modifier
.d
)
6079 found_reverse_match
= 0;
6080 else if (operand_types
[0].bitfield
.tbyte
)
6081 found_reverse_match
= Opcode_FloatD
;
6082 else if (operand_types
[0].bitfield
.xmmword
6083 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6084 || operand_types
[0].bitfield
.class == RegMMX
6085 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6086 || is_any_vex_encoding(t
))
6087 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6088 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6090 found_reverse_match
= Opcode_D
;
6091 if (t
->opcode_modifier
.floatr
)
6092 found_reverse_match
|= Opcode_FloatR
;
6096 /* Found a forward 2 operand match here. */
6097 switch (t
->operands
)
6100 overlap4
= operand_type_and (i
.types
[4],
6104 overlap3
= operand_type_and (i
.types
[3],
6108 overlap2
= operand_type_and (i
.types
[2],
6113 switch (t
->operands
)
6116 if (!operand_type_match (overlap4
, i
.types
[4])
6117 || !operand_type_register_match (i
.types
[3],
6124 if (!operand_type_match (overlap3
, i
.types
[3])
6125 || ((check_register
& 0xa) == 0xa
6126 && !operand_type_register_match (i
.types
[1],
6130 || ((check_register
& 0xc) == 0xc
6131 && !operand_type_register_match (i
.types
[2],
6138 /* Here we make use of the fact that there are no
6139 reverse match 3 operand instructions. */
6140 if (!operand_type_match (overlap2
, i
.types
[2])
6141 || ((check_register
& 5) == 5
6142 && !operand_type_register_match (i
.types
[0],
6146 || ((check_register
& 6) == 6
6147 && !operand_type_register_match (i
.types
[1],
6155 /* Found either forward/reverse 2, 3 or 4 operand match here:
6156 slip through to break. */
6159 /* Check if vector and VEX operands are valid. */
6160 if (check_VecOperands (t
) || VEX_check_operands (t
))
6162 specific_error
= i
.error
;
6166 /* We've found a match; break out of loop. */
6170 if (t
== current_templates
->end
)
6172 /* We found no match. */
6173 const char *err_msg
;
6174 switch (specific_error
? specific_error
: i
.error
)
6178 case operand_size_mismatch
:
6179 err_msg
= _("operand size mismatch");
6181 case operand_type_mismatch
:
6182 err_msg
= _("operand type mismatch");
6184 case register_type_mismatch
:
6185 err_msg
= _("register type mismatch");
6187 case number_of_operands_mismatch
:
6188 err_msg
= _("number of operands mismatch");
6190 case invalid_instruction_suffix
:
6191 err_msg
= _("invalid instruction suffix");
6194 err_msg
= _("constant doesn't fit in 4 bits");
6196 case unsupported_with_intel_mnemonic
:
6197 err_msg
= _("unsupported with Intel mnemonic");
6199 case unsupported_syntax
:
6200 err_msg
= _("unsupported syntax");
6203 as_bad (_("unsupported instruction `%s'"),
6204 current_templates
->start
->name
);
6206 case invalid_vsib_address
:
6207 err_msg
= _("invalid VSIB address");
6209 case invalid_vector_register_set
:
6210 err_msg
= _("mask, index, and destination registers must be distinct");
6212 case unsupported_vector_index_register
:
6213 err_msg
= _("unsupported vector index register");
6215 case unsupported_broadcast
:
6216 err_msg
= _("unsupported broadcast");
6218 case broadcast_needed
:
6219 err_msg
= _("broadcast is needed for operand of such type");
6221 case unsupported_masking
:
6222 err_msg
= _("unsupported masking");
6224 case mask_not_on_destination
:
6225 err_msg
= _("mask not on destination operand");
6227 case no_default_mask
:
6228 err_msg
= _("default mask isn't allowed");
6230 case unsupported_rc_sae
:
6231 err_msg
= _("unsupported static rounding/sae");
6233 case rc_sae_operand_not_last_imm
:
6235 err_msg
= _("RC/SAE operand must precede immediate operands");
6237 err_msg
= _("RC/SAE operand must follow immediate operands");
6239 case invalid_register_operand
:
6240 err_msg
= _("invalid register operand");
6243 as_bad (_("%s for `%s'"), err_msg
,
6244 current_templates
->start
->name
);
6248 if (!quiet_warnings
)
6251 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6252 as_warn (_("indirect %s without `*'"), t
->name
);
6254 if (t
->opcode_modifier
.isprefix
6255 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6257 /* Warn them that a data or address size prefix doesn't
6258 affect assembly of the next line of code. */
6259 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6263 /* Copy the template we found. */
6266 if (addr_prefix_disp
!= -1)
6267 i
.tm
.operand_types
[addr_prefix_disp
]
6268 = operand_types
[addr_prefix_disp
];
6270 if (found_reverse_match
)
6272 /* If we found a reverse match we must alter the opcode direction
6273 bit and clear/flip the regmem modifier one. found_reverse_match
6274 holds bits to change (different for int & float insns). */
6276 i
.tm
.base_opcode
^= found_reverse_match
;
6278 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6279 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6281 /* Certain SIMD insns have their load forms specified in the opcode
6282 table, and hence we need to _set_ RegMem instead of clearing it.
6283 We need to avoid setting the bit though on insns like KMOVW. */
6284 i
.tm
.opcode_modifier
.regmem
6285 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6286 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6287 && !i
.tm
.opcode_modifier
.regmem
;
6296 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6297 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6299 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6301 as_bad (_("`%s' operand %u must use `%ses' segment"),
6303 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6308 /* There's only ever one segment override allowed per instruction.
6309 This instruction possibly has a legal segment override on the
6310 second operand, so copy the segment to where non-string
6311 instructions store it, allowing common code. */
6312 i
.seg
[op
] = i
.seg
[1];
6318 process_suffix (void)
6320 /* If matched instruction specifies an explicit instruction mnemonic
6322 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6323 i
.suffix
= WORD_MNEM_SUFFIX
;
6324 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6325 i
.suffix
= LONG_MNEM_SUFFIX
;
6326 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6327 i
.suffix
= QWORD_MNEM_SUFFIX
;
6328 else if (i
.reg_operands
6329 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6330 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6332 unsigned int numop
= i
.operands
;
6334 /* movsx/movzx want only their source operand considered here, for the
6335 ambiguity checking below. The suffix will be replaced afterwards
6336 to represent the destination (register). */
6337 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6338 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6341 /* If there's no instruction mnemonic suffix we try to invent one
6342 based on GPR operands. */
6345 /* We take i.suffix from the last register operand specified,
6346 Destination register type is more significant than source
6347 register type. crc32 in SSE4.2 prefers source register
6349 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6352 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6353 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6355 if (i
.types
[op
].bitfield
.class != Reg
)
6357 if (i
.types
[op
].bitfield
.byte
)
6358 i
.suffix
= BYTE_MNEM_SUFFIX
;
6359 else if (i
.types
[op
].bitfield
.word
)
6360 i
.suffix
= WORD_MNEM_SUFFIX
;
6361 else if (i
.types
[op
].bitfield
.dword
)
6362 i
.suffix
= LONG_MNEM_SUFFIX
;
6363 else if (i
.types
[op
].bitfield
.qword
)
6364 i
.suffix
= QWORD_MNEM_SUFFIX
;
6370 /* As an exception, movsx/movzx silently default to a byte source
6372 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6373 && !i
.suffix
&& !intel_syntax
)
6374 i
.suffix
= BYTE_MNEM_SUFFIX
;
6376 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6379 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6380 && i
.tm
.opcode_modifier
.no_bsuf
)
6382 else if (!check_byte_reg ())
6385 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6388 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6389 && i
.tm
.opcode_modifier
.no_lsuf
6390 && !i
.tm
.opcode_modifier
.todword
6391 && !i
.tm
.opcode_modifier
.toqword
)
6393 else if (!check_long_reg ())
6396 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6399 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6400 && i
.tm
.opcode_modifier
.no_qsuf
6401 && !i
.tm
.opcode_modifier
.todword
6402 && !i
.tm
.opcode_modifier
.toqword
)
6404 else if (!check_qword_reg ())
6407 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6410 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6411 && i
.tm
.opcode_modifier
.no_wsuf
)
6413 else if (!check_word_reg ())
6416 else if (intel_syntax
6417 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6418 /* Do nothing if the instruction is going to ignore the prefix. */
6423 /* Undo the movsx/movzx change done above. */
6426 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6429 i
.suffix
= stackop_size
;
6430 if (stackop_size
== LONG_MNEM_SUFFIX
)
6432 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6433 .code16gcc directive to support 16-bit mode with
6434 32-bit address. For IRET without a suffix, generate
6435 16-bit IRET (opcode 0xcf) to return from an interrupt
6437 if (i
.tm
.base_opcode
== 0xcf)
6439 i
.suffix
= WORD_MNEM_SUFFIX
;
6440 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6442 /* Warn about changed behavior for segment register push/pop. */
6443 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6444 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6449 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6450 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6451 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6452 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6453 && i
.tm
.extension_opcode
<= 3)))
6458 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6460 i
.suffix
= QWORD_MNEM_SUFFIX
;
6465 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6466 i
.suffix
= LONG_MNEM_SUFFIX
;
6469 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6470 i
.suffix
= WORD_MNEM_SUFFIX
;
6476 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6477 /* Also cover lret/retf/iret in 64-bit mode. */
6478 || (flag_code
== CODE_64BIT
6479 && !i
.tm
.opcode_modifier
.no_lsuf
6480 && !i
.tm
.opcode_modifier
.no_qsuf
))
6481 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6482 /* Accept FLDENV et al without suffix. */
6483 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6485 unsigned int suffixes
, evex
= 0;
6487 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6488 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6490 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6492 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6494 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6496 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6499 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6500 also suitable for AT&T syntax mode, it was requested that this be
6501 restricted to just Intel syntax. */
6502 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6506 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6508 if (is_evex_encoding (&i
.tm
)
6509 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6511 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6512 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6513 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6514 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6515 if (!i
.tm
.opcode_modifier
.evex
6516 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6517 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6520 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6521 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6522 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6525 /* Any properly sized operand disambiguates the insn. */
6526 if (i
.types
[op
].bitfield
.xmmword
6527 || i
.types
[op
].bitfield
.ymmword
6528 || i
.types
[op
].bitfield
.zmmword
)
6530 suffixes
&= ~(7 << 6);
6535 if ((i
.flags
[op
] & Operand_Mem
)
6536 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6538 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6540 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6542 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6544 if (is_evex_encoding (&i
.tm
))
6550 /* Are multiple suffixes / operand sizes allowed? */
6551 if (suffixes
& (suffixes
- 1))
6554 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6555 || operand_check
== check_error
))
6557 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6560 if (operand_check
== check_error
)
6562 as_bad (_("no instruction mnemonic suffix given and "
6563 "no register operands; can't size `%s'"), i
.tm
.name
);
6566 if (operand_check
== check_warning
)
6567 as_warn (_("%s; using default for `%s'"),
6569 ? _("ambiguous operand size")
6570 : _("no instruction mnemonic suffix given and "
6571 "no register operands"),
6574 if (i
.tm
.opcode_modifier
.floatmf
)
6575 i
.suffix
= SHORT_MNEM_SUFFIX
;
6576 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6577 || (i
.tm
.base_opcode
== 0x63
6578 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6579 /* handled below */;
6581 i
.tm
.opcode_modifier
.evex
= evex
;
6582 else if (flag_code
== CODE_16BIT
)
6583 i
.suffix
= WORD_MNEM_SUFFIX
;
6584 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6585 i
.suffix
= LONG_MNEM_SUFFIX
;
6587 i
.suffix
= QWORD_MNEM_SUFFIX
;
6591 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6592 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6594 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6595 In AT&T syntax, if there is no suffix (warned about above), the default
6596 will be byte extension. */
6597 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6598 i
.tm
.base_opcode
|= 1;
6600 /* For further processing, the suffix should represent the destination
6601 (register). This is already the case when one was used with
6602 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6603 no suffix to begin with. */
6604 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6606 if (i
.types
[1].bitfield
.word
)
6607 i
.suffix
= WORD_MNEM_SUFFIX
;
6608 else if (i
.types
[1].bitfield
.qword
)
6609 i
.suffix
= QWORD_MNEM_SUFFIX
;
6611 i
.suffix
= LONG_MNEM_SUFFIX
;
6613 i
.tm
.opcode_modifier
.w
= 0;
6617 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6618 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6619 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6621 /* Change the opcode based on the operand size given by i.suffix. */
6624 /* Size floating point instruction. */
6625 case LONG_MNEM_SUFFIX
:
6626 if (i
.tm
.opcode_modifier
.floatmf
)
6628 i
.tm
.base_opcode
^= 4;
6632 case WORD_MNEM_SUFFIX
:
6633 case QWORD_MNEM_SUFFIX
:
6634 /* It's not a byte, select word/dword operation. */
6635 if (i
.tm
.opcode_modifier
.w
)
6638 i
.tm
.base_opcode
|= 8;
6640 i
.tm
.base_opcode
|= 1;
6643 case SHORT_MNEM_SUFFIX
:
6644 /* Now select between word & dword operations via the operand
6645 size prefix, except for instructions that will ignore this
6647 if (i
.suffix
!= QWORD_MNEM_SUFFIX
6648 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6649 && !i
.tm
.opcode_modifier
.floatmf
6650 && !is_any_vex_encoding (&i
.tm
)
6651 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6652 || (flag_code
== CODE_64BIT
6653 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6655 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6657 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6658 prefix
= ADDR_PREFIX_OPCODE
;
6660 if (!add_prefix (prefix
))
6664 /* Set mode64 for an operand. */
6665 if (i
.suffix
== QWORD_MNEM_SUFFIX
6666 && flag_code
== CODE_64BIT
6667 && !i
.tm
.opcode_modifier
.norex64
6668 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6670 && ! (i
.operands
== 2
6671 && i
.tm
.base_opcode
== 0x90
6672 && i
.tm
.extension_opcode
== None
6673 && i
.types
[0].bitfield
.instance
== Accum
6674 && i
.types
[0].bitfield
.qword
6675 && i
.types
[1].bitfield
.instance
== Accum
6676 && i
.types
[1].bitfield
.qword
))
6682 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
6684 gas_assert (!i
.suffix
);
6685 gas_assert (i
.reg_operands
);
6687 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6690 /* The address size override prefix changes the size of the
6692 if (flag_code
== CODE_64BIT
6693 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6695 as_bad (_("16-bit addressing unavailable for `%s'"),
6700 if ((flag_code
== CODE_32BIT
6701 ? i
.op
[0].regs
->reg_type
.bitfield
.word
6702 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
6703 && !add_prefix (ADDR_PREFIX_OPCODE
))
6708 /* Check invalid register operand when the address size override
6709 prefix changes the size of register operands. */
6711 enum { need_word
, need_dword
, need_qword
} need
;
6713 if (flag_code
== CODE_32BIT
)
6714 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6715 else if (i
.prefix
[ADDR_PREFIX
])
6718 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6720 for (op
= 0; op
< i
.operands
; op
++)
6722 if (i
.types
[op
].bitfield
.class != Reg
)
6728 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6732 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6736 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
6741 as_bad (_("invalid register operand size for `%s'"),
6752 check_byte_reg (void)
6756 for (op
= i
.operands
; --op
>= 0;)
6758 /* Skip non-register operands. */
6759 if (i
.types
[op
].bitfield
.class != Reg
)
6762 /* If this is an eight bit register, it's OK. If it's the 16 or
6763 32 bit version of an eight bit register, we will just use the
6764 low portion, and that's OK too. */
6765 if (i
.types
[op
].bitfield
.byte
)
6768 /* I/O port address operands are OK too. */
6769 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6770 && i
.tm
.operand_types
[op
].bitfield
.word
)
6773 /* crc32 only wants its source operand checked here. */
6774 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6777 /* Any other register is bad. */
6778 if (i
.types
[op
].bitfield
.class == Reg
6779 || i
.types
[op
].bitfield
.class == RegMMX
6780 || i
.types
[op
].bitfield
.class == RegSIMD
6781 || i
.types
[op
].bitfield
.class == SReg
6782 || i
.types
[op
].bitfield
.class == RegCR
6783 || i
.types
[op
].bitfield
.class == RegDR
6784 || i
.types
[op
].bitfield
.class == RegTR
)
6786 as_bad (_("`%s%s' not allowed with `%s%c'"),
6788 i
.op
[op
].regs
->reg_name
,
6798 check_long_reg (void)
6802 for (op
= i
.operands
; --op
>= 0;)
6803 /* Skip non-register operands. */
6804 if (i
.types
[op
].bitfield
.class != Reg
)
6806 /* Reject eight bit registers, except where the template requires
6807 them. (eg. movzb) */
6808 else if (i
.types
[op
].bitfield
.byte
6809 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6810 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6811 && (i
.tm
.operand_types
[op
].bitfield
.word
6812 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6814 as_bad (_("`%s%s' not allowed with `%s%c'"),
6816 i
.op
[op
].regs
->reg_name
,
6821 /* Error if the e prefix on a general reg is missing. */
6822 else if (i
.types
[op
].bitfield
.word
6823 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6824 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6825 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6827 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6828 register_prefix
, i
.op
[op
].regs
->reg_name
,
6832 /* Warn if the r prefix on a general reg is present. */
6833 else if (i
.types
[op
].bitfield
.qword
6834 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6835 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6836 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6839 && i
.tm
.opcode_modifier
.toqword
6840 && i
.types
[0].bitfield
.class != RegSIMD
)
6842 /* Convert to QWORD. We want REX byte. */
6843 i
.suffix
= QWORD_MNEM_SUFFIX
;
6847 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6848 register_prefix
, i
.op
[op
].regs
->reg_name
,
6857 check_qword_reg (void)
6861 for (op
= i
.operands
; --op
>= 0; )
6862 /* Skip non-register operands. */
6863 if (i
.types
[op
].bitfield
.class != Reg
)
6865 /* Reject eight bit registers, except where the template requires
6866 them. (eg. movzb) */
6867 else if (i
.types
[op
].bitfield
.byte
6868 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6869 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6870 && (i
.tm
.operand_types
[op
].bitfield
.word
6871 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6873 as_bad (_("`%s%s' not allowed with `%s%c'"),
6875 i
.op
[op
].regs
->reg_name
,
6880 /* Warn if the r prefix on a general reg is missing. */
6881 else if ((i
.types
[op
].bitfield
.word
6882 || i
.types
[op
].bitfield
.dword
)
6883 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6884 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6885 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6887 /* Prohibit these changes in the 64bit mode, since the
6888 lowering is more complicated. */
6890 && i
.tm
.opcode_modifier
.todword
6891 && i
.types
[0].bitfield
.class != RegSIMD
)
6893 /* Convert to DWORD. We don't want REX byte. */
6894 i
.suffix
= LONG_MNEM_SUFFIX
;
6898 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6899 register_prefix
, i
.op
[op
].regs
->reg_name
,
6908 check_word_reg (void)
6911 for (op
= i
.operands
; --op
>= 0;)
6912 /* Skip non-register operands. */
6913 if (i
.types
[op
].bitfield
.class != Reg
)
6915 /* Reject eight bit registers, except where the template requires
6916 them. (eg. movzb) */
6917 else if (i
.types
[op
].bitfield
.byte
6918 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6919 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6920 && (i
.tm
.operand_types
[op
].bitfield
.word
6921 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6923 as_bad (_("`%s%s' not allowed with `%s%c'"),
6925 i
.op
[op
].regs
->reg_name
,
6930 /* Error if the e or r prefix on a general reg is present. */
6931 else if ((i
.types
[op
].bitfield
.dword
6932 || i
.types
[op
].bitfield
.qword
)
6933 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6934 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6935 && i
.tm
.operand_types
[op
].bitfield
.word
)
6937 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6938 register_prefix
, i
.op
[op
].regs
->reg_name
,
6946 update_imm (unsigned int j
)
6948 i386_operand_type overlap
= i
.types
[j
];
6949 if ((overlap
.bitfield
.imm8
6950 || overlap
.bitfield
.imm8s
6951 || overlap
.bitfield
.imm16
6952 || overlap
.bitfield
.imm32
6953 || overlap
.bitfield
.imm32s
6954 || overlap
.bitfield
.imm64
)
6955 && !operand_type_equal (&overlap
, &imm8
)
6956 && !operand_type_equal (&overlap
, &imm8s
)
6957 && !operand_type_equal (&overlap
, &imm16
)
6958 && !operand_type_equal (&overlap
, &imm32
)
6959 && !operand_type_equal (&overlap
, &imm32s
)
6960 && !operand_type_equal (&overlap
, &imm64
))
6964 i386_operand_type temp
;
6966 operand_type_set (&temp
, 0);
6967 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6969 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6970 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6972 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6973 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6974 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6976 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6977 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6980 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6983 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6984 || operand_type_equal (&overlap
, &imm16_32
)
6985 || operand_type_equal (&overlap
, &imm16_32s
))
6987 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6992 if (!operand_type_equal (&overlap
, &imm8
)
6993 && !operand_type_equal (&overlap
, &imm8s
)
6994 && !operand_type_equal (&overlap
, &imm16
)
6995 && !operand_type_equal (&overlap
, &imm32
)
6996 && !operand_type_equal (&overlap
, &imm32s
)
6997 && !operand_type_equal (&overlap
, &imm64
))
6999 as_bad (_("no instruction mnemonic suffix given; "
7000 "can't determine immediate size"));
7004 i
.types
[j
] = overlap
;
7014 /* Update the first 2 immediate operands. */
7015 n
= i
.operands
> 2 ? 2 : i
.operands
;
7018 for (j
= 0; j
< n
; j
++)
7019 if (update_imm (j
) == 0)
7022 /* The 3rd operand can't be immediate operand. */
7023 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7030 process_operands (void)
7032 /* Default segment register this instruction will use for memory
7033 accesses. 0 means unknown. This is only for optimizing out
7034 unnecessary segment overrides. */
7035 const seg_entry
*default_seg
= 0;
7037 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7039 unsigned int dupl
= i
.operands
;
7040 unsigned int dest
= dupl
- 1;
7043 /* The destination must be an xmm register. */
7044 gas_assert (i
.reg_operands
7045 && MAX_OPERANDS
> dupl
7046 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7048 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7049 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7051 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7053 /* Keep xmm0 for instructions with VEX prefix and 3
7055 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7056 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7061 /* We remove the first xmm0 and keep the number of
7062 operands unchanged, which in fact duplicates the
7064 for (j
= 1; j
< i
.operands
; j
++)
7066 i
.op
[j
- 1] = i
.op
[j
];
7067 i
.types
[j
- 1] = i
.types
[j
];
7068 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7069 i
.flags
[j
- 1] = i
.flags
[j
];
7073 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7075 gas_assert ((MAX_OPERANDS
- 1) > dupl
7076 && (i
.tm
.opcode_modifier
.vexsources
7079 /* Add the implicit xmm0 for instructions with VEX prefix
7081 for (j
= i
.operands
; j
> 0; j
--)
7083 i
.op
[j
] = i
.op
[j
- 1];
7084 i
.types
[j
] = i
.types
[j
- 1];
7085 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7086 i
.flags
[j
] = i
.flags
[j
- 1];
7089 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7090 i
.types
[0] = regxmm
;
7091 i
.tm
.operand_types
[0] = regxmm
;
7094 i
.reg_operands
+= 2;
7099 i
.op
[dupl
] = i
.op
[dest
];
7100 i
.types
[dupl
] = i
.types
[dest
];
7101 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7102 i
.flags
[dupl
] = i
.flags
[dest
];
7111 i
.op
[dupl
] = i
.op
[dest
];
7112 i
.types
[dupl
] = i
.types
[dest
];
7113 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7114 i
.flags
[dupl
] = i
.flags
[dest
];
7117 if (i
.tm
.opcode_modifier
.immext
)
7120 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7121 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7125 for (j
= 1; j
< i
.operands
; j
++)
7127 i
.op
[j
- 1] = i
.op
[j
];
7128 i
.types
[j
- 1] = i
.types
[j
];
7130 /* We need to adjust fields in i.tm since they are used by
7131 build_modrm_byte. */
7132 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7134 i
.flags
[j
- 1] = i
.flags
[j
];
7141 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7143 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7145 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7146 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7147 regnum
= register_number (i
.op
[1].regs
);
7148 first_reg_in_group
= regnum
& ~3;
7149 last_reg_in_group
= first_reg_in_group
+ 3;
7150 if (regnum
!= first_reg_in_group
)
7151 as_warn (_("source register `%s%s' implicitly denotes"
7152 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7153 register_prefix
, i
.op
[1].regs
->reg_name
,
7154 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7155 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7158 else if (i
.tm
.opcode_modifier
.regkludge
)
7160 /* The imul $imm, %reg instruction is converted into
7161 imul $imm, %reg, %reg, and the clr %reg instruction
7162 is converted into xor %reg, %reg. */
7164 unsigned int first_reg_op
;
7166 if (operand_type_check (i
.types
[0], reg
))
7170 /* Pretend we saw the extra register operand. */
7171 gas_assert (i
.reg_operands
== 1
7172 && i
.op
[first_reg_op
+ 1].regs
== 0);
7173 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7174 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7179 if (i
.tm
.opcode_modifier
.modrm
)
7181 /* The opcode is completed (modulo i.tm.extension_opcode which
7182 must be put into the modrm byte). Now, we make the modrm and
7183 index base bytes based on all the info we've collected. */
7185 default_seg
= build_modrm_byte ();
7187 else if (i
.types
[0].bitfield
.class == SReg
)
7189 if (flag_code
!= CODE_64BIT
7190 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7191 && i
.op
[0].regs
->reg_num
== 1
7192 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7193 && i
.op
[0].regs
->reg_num
< 4)
7195 as_bad (_("you can't `%s %s%s'"),
7196 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7199 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7201 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7202 i
.tm
.opcode_length
= 2;
7204 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7206 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7210 else if (i
.tm
.opcode_modifier
.isstring
)
7212 /* For the string instructions that allow a segment override
7213 on one of their operands, the default segment is ds. */
7216 else if (i
.short_form
)
7218 /* The register or float register operand is in operand
7220 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7222 /* Register goes in low 3 bits of opcode. */
7223 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7224 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7226 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7228 /* Warn about some common errors, but press on regardless.
7229 The first case can be generated by gcc (<= 2.8.1). */
7230 if (i
.operands
== 2)
7232 /* Reversed arguments on faddp, fsubp, etc. */
7233 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7234 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7235 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7239 /* Extraneous `l' suffix on fp insn. */
7240 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7241 register_prefix
, i
.op
[0].regs
->reg_name
);
7246 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7247 && i
.tm
.base_opcode
== 0x8d /* lea */
7248 && !is_any_vex_encoding(&i
.tm
))
7250 if (!quiet_warnings
)
7251 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7255 i
.prefix
[SEG_PREFIX
] = 0;
7259 /* If a segment was explicitly specified, and the specified segment
7260 is neither the default nor the one already recorded from a prefix,
7261 use an opcode prefix to select it. If we never figured out what
7262 the default segment is, then default_seg will be zero at this
7263 point, and the specified segment prefix will always be used. */
7265 && i
.seg
[0] != default_seg
7266 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7268 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7274 static const seg_entry
*
7275 build_modrm_byte (void)
7277 const seg_entry
*default_seg
= 0;
7278 unsigned int source
, dest
;
7281 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7284 unsigned int nds
, reg_slot
;
7287 dest
= i
.operands
- 1;
7290 /* There are 2 kinds of instructions:
7291 1. 5 operands: 4 register operands or 3 register operands
7292 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7293 VexW0 or VexW1. The destination must be either XMM, YMM or
7295 2. 4 operands: 4 register operands or 3 register operands
7296 plus 1 memory operand, with VexXDS. */
7297 gas_assert ((i
.reg_operands
== 4
7298 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7299 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7300 && i
.tm
.opcode_modifier
.vexw
7301 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7303 /* If VexW1 is set, the first non-immediate operand is the source and
7304 the second non-immediate one is encoded in the immediate operand. */
7305 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7307 source
= i
.imm_operands
;
7308 reg_slot
= i
.imm_operands
+ 1;
7312 source
= i
.imm_operands
+ 1;
7313 reg_slot
= i
.imm_operands
;
7316 if (i
.imm_operands
== 0)
7318 /* When there is no immediate operand, generate an 8bit
7319 immediate operand to encode the first operand. */
7320 exp
= &im_expressions
[i
.imm_operands
++];
7321 i
.op
[i
.operands
].imms
= exp
;
7322 i
.types
[i
.operands
] = imm8
;
7325 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7326 exp
->X_op
= O_constant
;
7327 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7328 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7332 gas_assert (i
.imm_operands
== 1);
7333 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7334 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7336 /* Turn on Imm8 again so that output_imm will generate it. */
7337 i
.types
[0].bitfield
.imm8
= 1;
7339 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7340 i
.op
[0].imms
->X_add_number
7341 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7342 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7345 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7346 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7351 /* i.reg_operands MUST be the number of real register operands;
7352 implicit registers do not count. If there are 3 register
7353 operands, it must be a instruction with VexNDS. For a
7354 instruction with VexNDD, the destination register is encoded
7355 in VEX prefix. If there are 4 register operands, it must be
7356 a instruction with VEX prefix and 3 sources. */
7357 if (i
.mem_operands
== 0
7358 && ((i
.reg_operands
== 2
7359 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7360 || (i
.reg_operands
== 3
7361 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7362 || (i
.reg_operands
== 4 && vex_3_sources
)))
7370 /* When there are 3 operands, one of them may be immediate,
7371 which may be the first or the last operand. Otherwise,
7372 the first operand must be shift count register (cl) or it
7373 is an instruction with VexNDS. */
7374 gas_assert (i
.imm_operands
== 1
7375 || (i
.imm_operands
== 0
7376 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7377 || (i
.types
[0].bitfield
.instance
== RegC
7378 && i
.types
[0].bitfield
.byte
))));
7379 if (operand_type_check (i
.types
[0], imm
)
7380 || (i
.types
[0].bitfield
.instance
== RegC
7381 && i
.types
[0].bitfield
.byte
))
7387 /* When there are 4 operands, the first two must be 8bit
7388 immediate operands. The source operand will be the 3rd
7391 For instructions with VexNDS, if the first operand
7392 an imm8, the source operand is the 2nd one. If the last
7393 operand is imm8, the source operand is the first one. */
7394 gas_assert ((i
.imm_operands
== 2
7395 && i
.types
[0].bitfield
.imm8
7396 && i
.types
[1].bitfield
.imm8
)
7397 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7398 && i
.imm_operands
== 1
7399 && (i
.types
[0].bitfield
.imm8
7400 || i
.types
[i
.operands
- 1].bitfield
.imm8
7402 if (i
.imm_operands
== 2)
7406 if (i
.types
[0].bitfield
.imm8
)
7413 if (is_evex_encoding (&i
.tm
))
7415 /* For EVEX instructions, when there are 5 operands, the
7416 first one must be immediate operand. If the second one
7417 is immediate operand, the source operand is the 3th
7418 one. If the last one is immediate operand, the source
7419 operand is the 2nd one. */
7420 gas_assert (i
.imm_operands
== 2
7421 && i
.tm
.opcode_modifier
.sae
7422 && operand_type_check (i
.types
[0], imm
));
7423 if (operand_type_check (i
.types
[1], imm
))
7425 else if (operand_type_check (i
.types
[4], imm
))
7439 /* RC/SAE operand could be between DEST and SRC. That happens
7440 when one operand is GPR and the other one is XMM/YMM/ZMM
7442 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7445 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7447 /* For instructions with VexNDS, the register-only source
7448 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7449 register. It is encoded in VEX prefix. */
7451 i386_operand_type op
;
7454 /* Check register-only source operand when two source
7455 operands are swapped. */
7456 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7457 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7465 op
= i
.tm
.operand_types
[vvvv
];
7466 if ((dest
+ 1) >= i
.operands
7467 || ((op
.bitfield
.class != Reg
7468 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7469 && op
.bitfield
.class != RegSIMD
7470 && !operand_type_equal (&op
, ®mask
)))
7472 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7478 /* One of the register operands will be encoded in the i.rm.reg
7479 field, the other in the combined i.rm.mode and i.rm.regmem
7480 fields. If no form of this instruction supports a memory
7481 destination operand, then we assume the source operand may
7482 sometimes be a memory operand and so we need to store the
7483 destination in the i.rm.reg field. */
7484 if (!i
.tm
.opcode_modifier
.regmem
7485 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7487 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7488 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7489 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7490 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7491 i
.has_regmmx
= TRUE
;
7492 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7493 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7495 if (i
.types
[dest
].bitfield
.zmmword
7496 || i
.types
[source
].bitfield
.zmmword
)
7497 i
.has_regzmm
= TRUE
;
7498 else if (i
.types
[dest
].bitfield
.ymmword
7499 || i
.types
[source
].bitfield
.ymmword
)
7500 i
.has_regymm
= TRUE
;
7502 i
.has_regxmm
= TRUE
;
7504 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7506 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7508 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7510 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7515 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7516 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7517 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7519 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7521 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7523 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7526 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7528 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7531 add_prefix (LOCK_PREFIX_OPCODE
);
7535 { /* If it's not 2 reg operands... */
7540 unsigned int fake_zero_displacement
= 0;
7543 for (op
= 0; op
< i
.operands
; op
++)
7544 if (i
.flags
[op
] & Operand_Mem
)
7546 gas_assert (op
< i
.operands
);
7548 if (i
.tm
.opcode_modifier
.vecsib
)
7550 if (i
.index_reg
->reg_num
== RegIZ
)
7553 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7556 i
.sib
.base
= NO_BASE_REGISTER
;
7557 i
.sib
.scale
= i
.log2_scale_factor
;
7558 i
.types
[op
].bitfield
.disp8
= 0;
7559 i
.types
[op
].bitfield
.disp16
= 0;
7560 i
.types
[op
].bitfield
.disp64
= 0;
7561 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7563 /* Must be 32 bit */
7564 i
.types
[op
].bitfield
.disp32
= 1;
7565 i
.types
[op
].bitfield
.disp32s
= 0;
7569 i
.types
[op
].bitfield
.disp32
= 0;
7570 i
.types
[op
].bitfield
.disp32s
= 1;
7573 i
.sib
.index
= i
.index_reg
->reg_num
;
7574 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7576 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7582 if (i
.base_reg
== 0)
7585 if (!i
.disp_operands
)
7586 fake_zero_displacement
= 1;
7587 if (i
.index_reg
== 0)
7589 i386_operand_type newdisp
;
7591 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7592 /* Operand is just <disp> */
7593 if (flag_code
== CODE_64BIT
)
7595 /* 64bit mode overwrites the 32bit absolute
7596 addressing by RIP relative addressing and
7597 absolute addressing is encoded by one of the
7598 redundant SIB forms. */
7599 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7600 i
.sib
.base
= NO_BASE_REGISTER
;
7601 i
.sib
.index
= NO_INDEX_REGISTER
;
7602 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7604 else if ((flag_code
== CODE_16BIT
)
7605 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7607 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7612 i
.rm
.regmem
= NO_BASE_REGISTER
;
7615 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7616 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7618 else if (!i
.tm
.opcode_modifier
.vecsib
)
7620 /* !i.base_reg && i.index_reg */
7621 if (i
.index_reg
->reg_num
== RegIZ
)
7622 i
.sib
.index
= NO_INDEX_REGISTER
;
7624 i
.sib
.index
= i
.index_reg
->reg_num
;
7625 i
.sib
.base
= NO_BASE_REGISTER
;
7626 i
.sib
.scale
= i
.log2_scale_factor
;
7627 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7628 i
.types
[op
].bitfield
.disp8
= 0;
7629 i
.types
[op
].bitfield
.disp16
= 0;
7630 i
.types
[op
].bitfield
.disp64
= 0;
7631 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7633 /* Must be 32 bit */
7634 i
.types
[op
].bitfield
.disp32
= 1;
7635 i
.types
[op
].bitfield
.disp32s
= 0;
7639 i
.types
[op
].bitfield
.disp32
= 0;
7640 i
.types
[op
].bitfield
.disp32s
= 1;
7642 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7646 /* RIP addressing for 64bit mode. */
7647 else if (i
.base_reg
->reg_num
== RegIP
)
7649 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7650 i
.rm
.regmem
= NO_BASE_REGISTER
;
7651 i
.types
[op
].bitfield
.disp8
= 0;
7652 i
.types
[op
].bitfield
.disp16
= 0;
7653 i
.types
[op
].bitfield
.disp32
= 0;
7654 i
.types
[op
].bitfield
.disp32s
= 1;
7655 i
.types
[op
].bitfield
.disp64
= 0;
7656 i
.flags
[op
] |= Operand_PCrel
;
7657 if (! i
.disp_operands
)
7658 fake_zero_displacement
= 1;
7660 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7662 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7663 switch (i
.base_reg
->reg_num
)
7666 if (i
.index_reg
== 0)
7668 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7669 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7673 if (i
.index_reg
== 0)
7676 if (operand_type_check (i
.types
[op
], disp
) == 0)
7678 /* fake (%bp) into 0(%bp) */
7679 i
.types
[op
].bitfield
.disp8
= 1;
7680 fake_zero_displacement
= 1;
7683 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7684 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7686 default: /* (%si) -> 4 or (%di) -> 5 */
7687 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7689 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7691 else /* i.base_reg and 32/64 bit mode */
7693 if (flag_code
== CODE_64BIT
7694 && operand_type_check (i
.types
[op
], disp
))
7696 i
.types
[op
].bitfield
.disp16
= 0;
7697 i
.types
[op
].bitfield
.disp64
= 0;
7698 if (i
.prefix
[ADDR_PREFIX
] == 0)
7700 i
.types
[op
].bitfield
.disp32
= 0;
7701 i
.types
[op
].bitfield
.disp32s
= 1;
7705 i
.types
[op
].bitfield
.disp32
= 1;
7706 i
.types
[op
].bitfield
.disp32s
= 0;
7710 if (!i
.tm
.opcode_modifier
.vecsib
)
7711 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7712 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7714 i
.sib
.base
= i
.base_reg
->reg_num
;
7715 /* x86-64 ignores REX prefix bit here to avoid decoder
7717 if (!(i
.base_reg
->reg_flags
& RegRex
)
7718 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7719 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7721 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7723 fake_zero_displacement
= 1;
7724 i
.types
[op
].bitfield
.disp8
= 1;
7726 i
.sib
.scale
= i
.log2_scale_factor
;
7727 if (i
.index_reg
== 0)
7729 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7730 /* <disp>(%esp) becomes two byte modrm with no index
7731 register. We've already stored the code for esp
7732 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7733 Any base register besides %esp will not use the
7734 extra modrm byte. */
7735 i
.sib
.index
= NO_INDEX_REGISTER
;
7737 else if (!i
.tm
.opcode_modifier
.vecsib
)
7739 if (i
.index_reg
->reg_num
== RegIZ
)
7740 i
.sib
.index
= NO_INDEX_REGISTER
;
7742 i
.sib
.index
= i
.index_reg
->reg_num
;
7743 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7744 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7749 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7750 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7754 if (!fake_zero_displacement
7758 fake_zero_displacement
= 1;
7759 if (i
.disp_encoding
== disp_encoding_8bit
)
7760 i
.types
[op
].bitfield
.disp8
= 1;
7762 i
.types
[op
].bitfield
.disp32
= 1;
7764 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7768 if (fake_zero_displacement
)
7770 /* Fakes a zero displacement assuming that i.types[op]
7771 holds the correct displacement size. */
7774 gas_assert (i
.op
[op
].disps
== 0);
7775 exp
= &disp_expressions
[i
.disp_operands
++];
7776 i
.op
[op
].disps
= exp
;
7777 exp
->X_op
= O_constant
;
7778 exp
->X_add_number
= 0;
7779 exp
->X_add_symbol
= (symbolS
*) 0;
7780 exp
->X_op_symbol
= (symbolS
*) 0;
7788 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7790 if (operand_type_check (i
.types
[0], imm
))
7791 i
.vex
.register_specifier
= NULL
;
7794 /* VEX.vvvv encodes one of the sources when the first
7795 operand is not an immediate. */
7796 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7797 i
.vex
.register_specifier
= i
.op
[0].regs
;
7799 i
.vex
.register_specifier
= i
.op
[1].regs
;
7802 /* Destination is a XMM register encoded in the ModRM.reg
7804 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7805 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7808 /* ModRM.rm and VEX.B encodes the other source. */
7809 if (!i
.mem_operands
)
7813 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7814 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7816 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7818 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7822 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7824 i
.vex
.register_specifier
= i
.op
[2].regs
;
7825 if (!i
.mem_operands
)
7828 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7829 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7833 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7834 (if any) based on i.tm.extension_opcode. Again, we must be
7835 careful to make sure that segment/control/debug/test/MMX
7836 registers are coded into the i.rm.reg field. */
7837 else if (i
.reg_operands
)
7840 unsigned int vex_reg
= ~0;
7842 for (op
= 0; op
< i
.operands
; op
++)
7844 if (i
.types
[op
].bitfield
.class == Reg
7845 || i
.types
[op
].bitfield
.class == RegBND
7846 || i
.types
[op
].bitfield
.class == RegMask
7847 || i
.types
[op
].bitfield
.class == SReg
7848 || i
.types
[op
].bitfield
.class == RegCR
7849 || i
.types
[op
].bitfield
.class == RegDR
7850 || i
.types
[op
].bitfield
.class == RegTR
)
7852 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7854 if (i
.types
[op
].bitfield
.zmmword
)
7855 i
.has_regzmm
= TRUE
;
7856 else if (i
.types
[op
].bitfield
.ymmword
)
7857 i
.has_regymm
= TRUE
;
7859 i
.has_regxmm
= TRUE
;
7862 if (i
.types
[op
].bitfield
.class == RegMMX
)
7864 i
.has_regmmx
= TRUE
;
7871 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7873 /* For instructions with VexNDS, the register-only
7874 source operand is encoded in VEX prefix. */
7875 gas_assert (mem
!= (unsigned int) ~0);
7880 gas_assert (op
< i
.operands
);
7884 /* Check register-only source operand when two source
7885 operands are swapped. */
7886 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7887 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7891 gas_assert (mem
== (vex_reg
+ 1)
7892 && op
< i
.operands
);
7897 gas_assert (vex_reg
< i
.operands
);
7901 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7903 /* For instructions with VexNDD, the register destination
7904 is encoded in VEX prefix. */
7905 if (i
.mem_operands
== 0)
7907 /* There is no memory operand. */
7908 gas_assert ((op
+ 2) == i
.operands
);
7913 /* There are only 2 non-immediate operands. */
7914 gas_assert (op
< i
.imm_operands
+ 2
7915 && i
.operands
== i
.imm_operands
+ 2);
7916 vex_reg
= i
.imm_operands
+ 1;
7920 gas_assert (op
< i
.operands
);
7922 if (vex_reg
!= (unsigned int) ~0)
7924 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7926 if ((type
->bitfield
.class != Reg
7927 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7928 && type
->bitfield
.class != RegSIMD
7929 && !operand_type_equal (type
, ®mask
))
7932 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7935 /* Don't set OP operand twice. */
7938 /* If there is an extension opcode to put here, the
7939 register number must be put into the regmem field. */
7940 if (i
.tm
.extension_opcode
!= None
)
7942 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7943 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7945 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7950 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7951 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7953 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7958 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7959 must set it to 3 to indicate this is a register operand
7960 in the regmem field. */
7961 if (!i
.mem_operands
)
7965 /* Fill in i.rm.reg field with extension opcode (if any). */
7966 if (i
.tm
.extension_opcode
!= None
)
7967 i
.rm
.reg
= i
.tm
.extension_opcode
;
7973 flip_code16 (unsigned int code16
)
7975 gas_assert (i
.tm
.operands
== 1);
7977 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7978 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7979 || i
.tm
.operand_types
[0].bitfield
.disp32s
7980 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7985 output_branch (void)
7991 relax_substateT subtype
;
7995 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7996 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7999 if (i
.prefix
[DATA_PREFIX
] != 0)
8003 code16
^= flip_code16(code16
);
8005 /* Pentium4 branch hints. */
8006 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8007 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8012 if (i
.prefix
[REX_PREFIX
] != 0)
8018 /* BND prefixed jump. */
8019 if (i
.prefix
[BND_PREFIX
] != 0)
8025 if (i
.prefixes
!= 0)
8026 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8028 /* It's always a symbol; End frag & setup for relax.
8029 Make sure there is enough room in this frag for the largest
8030 instruction we may generate in md_convert_frag. This is 2
8031 bytes for the opcode and room for the prefix and largest
8033 frag_grow (prefix
+ 2 + 4);
8034 /* Prefix and 1 opcode byte go in fr_fix. */
8035 p
= frag_more (prefix
+ 1);
8036 if (i
.prefix
[DATA_PREFIX
] != 0)
8037 *p
++ = DATA_PREFIX_OPCODE
;
8038 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8039 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8040 *p
++ = i
.prefix
[SEG_PREFIX
];
8041 if (i
.prefix
[BND_PREFIX
] != 0)
8042 *p
++ = BND_PREFIX_OPCODE
;
8043 if (i
.prefix
[REX_PREFIX
] != 0)
8044 *p
++ = i
.prefix
[REX_PREFIX
];
8045 *p
= i
.tm
.base_opcode
;
8047 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8048 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8049 else if (cpu_arch_flags
.bitfield
.cpui386
)
8050 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8052 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8055 sym
= i
.op
[0].disps
->X_add_symbol
;
8056 off
= i
.op
[0].disps
->X_add_number
;
8058 if (i
.op
[0].disps
->X_op
!= O_constant
8059 && i
.op
[0].disps
->X_op
!= O_symbol
)
8061 /* Handle complex expressions. */
8062 sym
= make_expr_symbol (i
.op
[0].disps
);
8066 /* 1 possible extra opcode + 4 byte displacement go in var part.
8067 Pass reloc in fr_var. */
8068 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8071 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8072 /* Return TRUE iff PLT32 relocation should be used for branching to
8076 need_plt32_p (symbolS
*s
)
8078 /* PLT32 relocation is ELF only. */
8083 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8084 krtld support it. */
8088 /* Since there is no need to prepare for PLT branch on x86-64, we
8089 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8090 be used as a marker for 32-bit PC-relative branches. */
8094 /* Weak or undefined symbol need PLT32 relocation. */
8095 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8098 /* Non-global symbol doesn't need PLT32 relocation. */
8099 if (! S_IS_EXTERNAL (s
))
8102 /* Other global symbols need PLT32 relocation. NB: Symbol with
8103 non-default visibilities are treated as normal global symbol
8104 so that PLT32 relocation can be used as a marker for 32-bit
8105 PC-relative branches. It is useful for linker relaxation. */
8116 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8118 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8120 /* This is a loop or jecxz type instruction. */
8122 if (i
.prefix
[ADDR_PREFIX
] != 0)
8124 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8127 /* Pentium4 branch hints. */
8128 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8129 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8131 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8140 if (flag_code
== CODE_16BIT
)
8143 if (i
.prefix
[DATA_PREFIX
] != 0)
8145 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8147 code16
^= flip_code16(code16
);
8155 /* BND prefixed jump. */
8156 if (i
.prefix
[BND_PREFIX
] != 0)
8158 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8162 if (i
.prefix
[REX_PREFIX
] != 0)
8164 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8168 if (i
.prefixes
!= 0)
8169 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8171 p
= frag_more (i
.tm
.opcode_length
+ size
);
8172 switch (i
.tm
.opcode_length
)
8175 *p
++ = i
.tm
.base_opcode
>> 8;
8178 *p
++ = i
.tm
.base_opcode
;
8184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8186 && jump_reloc
== NO_RELOC
8187 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8188 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8191 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8193 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8194 i
.op
[0].disps
, 1, jump_reloc
);
8196 /* All jumps handled here are signed, but don't use a signed limit
8197 check for 32 and 16 bit jumps as we want to allow wrap around at
8198 4G and 64k respectively. */
8200 fixP
->fx_signed
= 1;
8204 output_interseg_jump (void)
8212 if (flag_code
== CODE_16BIT
)
8216 if (i
.prefix
[DATA_PREFIX
] != 0)
8223 gas_assert (!i
.prefix
[REX_PREFIX
]);
8229 if (i
.prefixes
!= 0)
8230 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8232 /* 1 opcode; 2 segment; offset */
8233 p
= frag_more (prefix
+ 1 + 2 + size
);
8235 if (i
.prefix
[DATA_PREFIX
] != 0)
8236 *p
++ = DATA_PREFIX_OPCODE
;
8238 if (i
.prefix
[REX_PREFIX
] != 0)
8239 *p
++ = i
.prefix
[REX_PREFIX
];
8241 *p
++ = i
.tm
.base_opcode
;
8242 if (i
.op
[1].imms
->X_op
== O_constant
)
8244 offsetT n
= i
.op
[1].imms
->X_add_number
;
8247 && !fits_in_unsigned_word (n
)
8248 && !fits_in_signed_word (n
))
8250 as_bad (_("16-bit jump out of range"));
8253 md_number_to_chars (p
, n
, size
);
8256 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8257 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8258 if (i
.op
[0].imms
->X_op
!= O_constant
)
8259 as_bad (_("can't handle non absolute segment in `%s'"),
8261 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8264 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8269 asection
*seg
= now_seg
;
8270 subsegT subseg
= now_subseg
;
8272 unsigned int alignment
, align_size_1
;
8273 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8274 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8275 unsigned int padding
;
8277 if (!IS_ELF
|| !x86_used_note
)
8280 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8282 /* The .note.gnu.property section layout:
8284 Field Length Contents
8287 n_descsz 4 The note descriptor size
8288 n_type 4 NT_GNU_PROPERTY_TYPE_0
8290 n_desc n_descsz The program property array
8294 /* Create the .note.gnu.property section. */
8295 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8296 bfd_set_section_flags (sec
,
8303 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8314 bfd_set_section_alignment (sec
, alignment
);
8315 elf_section_type (sec
) = SHT_NOTE
;
8317 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8319 isa_1_descsz_raw
= 4 + 4 + 4;
8320 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8321 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8323 feature_2_descsz_raw
= isa_1_descsz
;
8324 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8326 feature_2_descsz_raw
+= 4 + 4 + 4;
8327 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8328 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8331 descsz
= feature_2_descsz
;
8332 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8333 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8335 /* Write n_namsz. */
8336 md_number_to_chars (p
, (valueT
) 4, 4);
8338 /* Write n_descsz. */
8339 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8342 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8345 memcpy (p
+ 4 * 3, "GNU", 4);
8347 /* Write 4-byte type. */
8348 md_number_to_chars (p
+ 4 * 4,
8349 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8351 /* Write 4-byte data size. */
8352 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8354 /* Write 4-byte data. */
8355 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8357 /* Zero out paddings. */
8358 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8360 memset (p
+ 4 * 7, 0, padding
);
8362 /* Write 4-byte type. */
8363 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8364 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8366 /* Write 4-byte data size. */
8367 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8369 /* Write 4-byte data. */
8370 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8371 (valueT
) x86_feature_2_used
, 4);
8373 /* Zero out paddings. */
8374 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8376 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8378 /* We probably can't restore the current segment, for there likely
8381 subseg_set (seg
, subseg
);
8386 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8387 const char *frag_now_ptr
)
8389 unsigned int len
= 0;
8391 if (start_frag
!= frag_now
)
8393 const fragS
*fr
= start_frag
;
8398 } while (fr
&& fr
!= frag_now
);
8401 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8404 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8405 be macro-fused with conditional jumps.
8406 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8407 or is one of the following format:
8420 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8422 /* No RIP address. */
8423 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8426 /* No VEX/EVEX encoding. */
8427 if (is_any_vex_encoding (&i
.tm
))
8430 /* add, sub without add/sub m, imm. */
8431 if (i
.tm
.base_opcode
<= 5
8432 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8433 || ((i
.tm
.base_opcode
| 3) == 0x83
8434 && (i
.tm
.extension_opcode
== 0x5
8435 || i
.tm
.extension_opcode
== 0x0)))
8437 *mf_cmp_p
= mf_cmp_alu_cmp
;
8438 return !(i
.mem_operands
&& i
.imm_operands
);
8441 /* and without and m, imm. */
8442 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8443 || ((i
.tm
.base_opcode
| 3) == 0x83
8444 && i
.tm
.extension_opcode
== 0x4))
8446 *mf_cmp_p
= mf_cmp_test_and
;
8447 return !(i
.mem_operands
&& i
.imm_operands
);
8450 /* test without test m imm. */
8451 if ((i
.tm
.base_opcode
| 1) == 0x85
8452 || (i
.tm
.base_opcode
| 1) == 0xa9
8453 || ((i
.tm
.base_opcode
| 1) == 0xf7
8454 && i
.tm
.extension_opcode
== 0))
8456 *mf_cmp_p
= mf_cmp_test_and
;
8457 return !(i
.mem_operands
&& i
.imm_operands
);
8460 /* cmp without cmp m, imm. */
8461 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8462 || ((i
.tm
.base_opcode
| 3) == 0x83
8463 && (i
.tm
.extension_opcode
== 0x7)))
8465 *mf_cmp_p
= mf_cmp_alu_cmp
;
8466 return !(i
.mem_operands
&& i
.imm_operands
);
8469 /* inc, dec without inc/dec m. */
8470 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8471 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8472 || ((i
.tm
.base_opcode
| 1) == 0xff
8473 && i
.tm
.extension_opcode
<= 0x1))
8475 *mf_cmp_p
= mf_cmp_incdec
;
8476 return !i
.mem_operands
;
8482 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8485 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8487 /* NB: Don't work with COND_JUMP86 without i386. */
8488 if (!align_branch_power
8489 || now_seg
== absolute_section
8490 || !cpu_arch_flags
.bitfield
.cpui386
8491 || !(align_branch
& align_branch_fused_bit
))
8494 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8496 if (last_insn
.kind
== last_insn_other
8497 || last_insn
.seg
!= now_seg
)
8500 as_warn_where (last_insn
.file
, last_insn
.line
,
8501 _("`%s` skips -malign-branch-boundary on `%s`"),
8502 last_insn
.name
, i
.tm
.name
);
8508 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8511 add_branch_prefix_frag_p (void)
8513 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8514 to PadLock instructions since they include prefixes in opcode. */
8515 if (!align_branch_power
8516 || !align_branch_prefix_size
8517 || now_seg
== absolute_section
8518 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8519 || !cpu_arch_flags
.bitfield
.cpui386
)
8522 /* Don't add prefix if it is a prefix or there is no operand in case
8523 that segment prefix is special. */
8524 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8527 if (last_insn
.kind
== last_insn_other
8528 || last_insn
.seg
!= now_seg
)
8532 as_warn_where (last_insn
.file
, last_insn
.line
,
8533 _("`%s` skips -malign-branch-boundary on `%s`"),
8534 last_insn
.name
, i
.tm
.name
);
8539 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8542 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8543 enum mf_jcc_kind
*mf_jcc_p
)
8547 /* NB: Don't work with COND_JUMP86 without i386. */
8548 if (!align_branch_power
8549 || now_seg
== absolute_section
8550 || !cpu_arch_flags
.bitfield
.cpui386
)
8555 /* Check for jcc and direct jmp. */
8556 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8558 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8560 *branch_p
= align_branch_jmp
;
8561 add_padding
= align_branch
& align_branch_jmp_bit
;
8565 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8566 igore the lowest bit. */
8567 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8568 *branch_p
= align_branch_jcc
;
8569 if ((align_branch
& align_branch_jcc_bit
))
8573 else if (is_any_vex_encoding (&i
.tm
))
8575 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8578 *branch_p
= align_branch_ret
;
8579 if ((align_branch
& align_branch_ret_bit
))
8584 /* Check for indirect jmp, direct and indirect calls. */
8585 if (i
.tm
.base_opcode
== 0xe8)
8588 *branch_p
= align_branch_call
;
8589 if ((align_branch
& align_branch_call_bit
))
8592 else if (i
.tm
.base_opcode
== 0xff
8593 && (i
.tm
.extension_opcode
== 2
8594 || i
.tm
.extension_opcode
== 4))
8596 /* Indirect call and jmp. */
8597 *branch_p
= align_branch_indirect
;
8598 if ((align_branch
& align_branch_indirect_bit
))
8605 && (i
.op
[0].disps
->X_op
== O_symbol
8606 || (i
.op
[0].disps
->X_op
== O_subtract
8607 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8609 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8610 /* No padding to call to global or undefined tls_get_addr. */
8611 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8612 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8618 && last_insn
.kind
!= last_insn_other
8619 && last_insn
.seg
== now_seg
)
8622 as_warn_where (last_insn
.file
, last_insn
.line
,
8623 _("`%s` skips -malign-branch-boundary on `%s`"),
8624 last_insn
.name
, i
.tm
.name
);
8634 fragS
*insn_start_frag
;
8635 offsetT insn_start_off
;
8636 fragS
*fragP
= NULL
;
8637 enum align_branch_kind branch
= align_branch_none
;
8638 /* The initializer is arbitrary just to avoid uninitialized error.
8639 it's actually either assigned in add_branch_padding_frag_p
8640 or never be used. */
8641 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
8643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8644 if (IS_ELF
&& x86_used_note
)
8646 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8647 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8648 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8649 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8650 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8651 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8652 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8653 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8654 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8655 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8656 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8657 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8658 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8659 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8660 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8661 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8662 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8663 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8664 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8665 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8666 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8667 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8668 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8669 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8670 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8671 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8672 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8673 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8674 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8675 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8676 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8677 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8678 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8679 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8680 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8681 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8682 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8683 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8684 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8685 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8686 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8687 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8688 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8689 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8690 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8691 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8692 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8693 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8694 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8695 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8697 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8698 || i
.tm
.cpu_flags
.bitfield
.cpu287
8699 || i
.tm
.cpu_flags
.bitfield
.cpu387
8700 || i
.tm
.cpu_flags
.bitfield
.cpu687
8701 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8702 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8704 || i
.tm
.base_opcode
== 0xf77 /* emms */
8705 || i
.tm
.base_opcode
== 0xf0e /* femms */
8706 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
8707 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
8708 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8710 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8712 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8714 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8715 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8716 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8717 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8718 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8719 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8720 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8721 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8722 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8726 /* Tie dwarf2 debug info to the address at the start of the insn.
8727 We can't do this after the insn has been output as the current
8728 frag may have been closed off. eg. by frag_var. */
8729 dwarf2_emit_insn (0);
8731 insn_start_frag
= frag_now
;
8732 insn_start_off
= frag_now_fix ();
8734 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
8737 /* Branch can be 8 bytes. Leave some room for prefixes. */
8738 unsigned int max_branch_padding_size
= 14;
8740 /* Align section to boundary. */
8741 record_alignment (now_seg
, align_branch_power
);
8743 /* Make room for padding. */
8744 frag_grow (max_branch_padding_size
);
8746 /* Start of the padding. */
8751 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8752 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8755 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
8756 fragP
->tc_frag_data
.branch_type
= branch
;
8757 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8761 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8763 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8764 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8766 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8767 output_interseg_jump ();
8770 /* Output normal instructions here. */
8774 unsigned int prefix
;
8775 enum mf_cmp_kind mf_cmp
;
8778 && (i
.tm
.base_opcode
== 0xfaee8
8779 || i
.tm
.base_opcode
== 0xfaef0
8780 || i
.tm
.base_opcode
== 0xfaef8))
8782 /* Encode lfence, mfence, and sfence as
8783 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8784 offsetT val
= 0x240483f0ULL
;
8786 md_number_to_chars (p
, val
, 5);
8790 /* Some processors fail on LOCK prefix. This options makes
8791 assembler ignore LOCK prefix and serves as a workaround. */
8792 if (omit_lock_prefix
)
8794 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8796 i
.prefix
[LOCK_PREFIX
] = 0;
8800 /* Skip if this is a branch. */
8802 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
8804 /* Make room for padding. */
8805 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8810 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8811 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8814 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
8815 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8816 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8818 else if (add_branch_prefix_frag_p ())
8820 unsigned int max_prefix_size
= align_branch_prefix_size
;
8822 /* Make room for padding. */
8823 frag_grow (max_prefix_size
);
8828 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8829 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8832 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8835 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8836 don't need the explicit prefix. */
8837 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8839 switch (i
.tm
.opcode_length
)
8842 if (i
.tm
.base_opcode
& 0xff000000)
8844 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8845 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8846 || prefix
!= REPE_PREFIX_OPCODE
8847 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8848 add_prefix (prefix
);
8852 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8854 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8855 add_prefix (prefix
);
8861 /* Check for pseudo prefixes. */
8862 as_bad_where (insn_start_frag
->fr_file
,
8863 insn_start_frag
->fr_line
,
8864 _("pseudo prefix without instruction"));
8870 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8871 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8872 R_X86_64_GOTTPOFF relocation so that linker can safely
8873 perform IE->LE optimization. A dummy REX_OPCODE prefix
8874 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8875 relocation for GDesc -> IE/LE optimization. */
8876 if (x86_elf_abi
== X86_64_X32_ABI
8878 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8879 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8880 && i
.prefix
[REX_PREFIX
] == 0)
8881 add_prefix (REX_OPCODE
);
8884 /* The prefix bytes. */
8885 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8887 FRAG_APPEND_1_CHAR (*q
);
8891 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8896 /* REX byte is encoded in VEX prefix. */
8900 FRAG_APPEND_1_CHAR (*q
);
8903 /* There should be no other prefixes for instructions
8908 /* For EVEX instructions i.vrex should become 0 after
8909 build_evex_prefix. For VEX instructions upper 16 registers
8910 aren't available, so VREX should be 0. */
8913 /* Now the VEX prefix. */
8914 p
= frag_more (i
.vex
.length
);
8915 for (j
= 0; j
< i
.vex
.length
; j
++)
8916 p
[j
] = i
.vex
.bytes
[j
];
8919 /* Now the opcode; be careful about word order here! */
8920 if (i
.tm
.opcode_length
== 1)
8922 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8926 switch (i
.tm
.opcode_length
)
8930 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8931 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8935 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8945 /* Put out high byte first: can't use md_number_to_chars! */
8946 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8947 *p
= i
.tm
.base_opcode
& 0xff;
8950 /* Now the modrm byte and sib byte (if present). */
8951 if (i
.tm
.opcode_modifier
.modrm
)
8953 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8956 /* If i.rm.regmem == ESP (4)
8957 && i.rm.mode != (Register mode)
8959 ==> need second modrm byte. */
8960 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8962 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8963 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8965 | i
.sib
.scale
<< 6));
8968 if (i
.disp_operands
)
8969 output_disp (insn_start_frag
, insn_start_off
);
8972 output_imm (insn_start_frag
, insn_start_off
);
8975 * frag_now_fix () returning plain abs_section_offset when we're in the
8976 * absolute section, and abs_section_offset not getting updated as data
8977 * gets added to the frag breaks the logic below.
8979 if (now_seg
!= absolute_section
)
8981 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8983 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8987 /* NB: Don't add prefix with GOTPC relocation since
8988 output_disp() above depends on the fixed encoding
8989 length. Can't add prefix with TLS relocation since
8990 it breaks TLS linker optimization. */
8991 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8992 /* Prefix count on the current instruction. */
8993 unsigned int count
= i
.vex
.length
;
8995 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8996 /* REX byte is encoded in VEX/EVEX prefix. */
8997 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9000 /* Count prefixes for extended opcode maps. */
9002 switch (i
.tm
.opcode_length
)
9005 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9008 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9020 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9029 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9032 /* Set the maximum prefix size in BRANCH_PREFIX
9034 if (fragP
->tc_frag_data
.max_bytes
> max
)
9035 fragP
->tc_frag_data
.max_bytes
= max
;
9036 if (fragP
->tc_frag_data
.max_bytes
> count
)
9037 fragP
->tc_frag_data
.max_bytes
-= count
;
9039 fragP
->tc_frag_data
.max_bytes
= 0;
9043 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9045 unsigned int max_prefix_size
;
9046 if (align_branch_prefix_size
> max
)
9047 max_prefix_size
= max
;
9049 max_prefix_size
= align_branch_prefix_size
;
9050 if (max_prefix_size
> count
)
9051 fragP
->tc_frag_data
.max_prefix_length
9052 = max_prefix_size
- count
;
9055 /* Use existing segment prefix if possible. Use CS
9056 segment prefix in 64-bit mode. In 32-bit mode, use SS
9057 segment prefix with ESP/EBP base register and use DS
9058 segment prefix without ESP/EBP base register. */
9059 if (i
.prefix
[SEG_PREFIX
])
9060 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9061 else if (flag_code
== CODE_64BIT
)
9062 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9064 && (i
.base_reg
->reg_num
== 4
9065 || i
.base_reg
->reg_num
== 5))
9066 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9068 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9073 /* NB: Don't work with COND_JUMP86 without i386. */
9074 if (align_branch_power
9075 && now_seg
!= absolute_section
9076 && cpu_arch_flags
.bitfield
.cpui386
)
9078 /* Terminate each frag so that we can add prefix and check for
9080 frag_wane (frag_now
);
9087 pi ("" /*line*/, &i
);
9089 #endif /* DEBUG386 */
9092 /* Return the size of the displacement operand N. */
9095 disp_size (unsigned int n
)
9099 if (i
.types
[n
].bitfield
.disp64
)
9101 else if (i
.types
[n
].bitfield
.disp8
)
9103 else if (i
.types
[n
].bitfield
.disp16
)
9108 /* Return the size of the immediate operand N. */
9111 imm_size (unsigned int n
)
9114 if (i
.types
[n
].bitfield
.imm64
)
9116 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9118 else if (i
.types
[n
].bitfield
.imm16
)
9124 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9129 for (n
= 0; n
< i
.operands
; n
++)
9131 if (operand_type_check (i
.types
[n
], disp
))
9133 if (i
.op
[n
].disps
->X_op
== O_constant
)
9135 int size
= disp_size (n
);
9136 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9138 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9140 p
= frag_more (size
);
9141 md_number_to_chars (p
, val
, size
);
9145 enum bfd_reloc_code_real reloc_type
;
9146 int size
= disp_size (n
);
9147 int sign
= i
.types
[n
].bitfield
.disp32s
;
9148 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9151 /* We can't have 8 bit displacement here. */
9152 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9154 /* The PC relative address is computed relative
9155 to the instruction boundary, so in case immediate
9156 fields follows, we need to adjust the value. */
9157 if (pcrel
&& i
.imm_operands
)
9162 for (n1
= 0; n1
< i
.operands
; n1
++)
9163 if (operand_type_check (i
.types
[n1
], imm
))
9165 /* Only one immediate is allowed for PC
9166 relative address. */
9167 gas_assert (sz
== 0);
9169 i
.op
[n
].disps
->X_add_number
-= sz
;
9171 /* We should find the immediate. */
9172 gas_assert (sz
!= 0);
9175 p
= frag_more (size
);
9176 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9178 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9179 && (((reloc_type
== BFD_RELOC_32
9180 || reloc_type
== BFD_RELOC_X86_64_32S
9181 || (reloc_type
== BFD_RELOC_64
9183 && (i
.op
[n
].disps
->X_op
== O_symbol
9184 || (i
.op
[n
].disps
->X_op
== O_add
9185 && ((symbol_get_value_expression
9186 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9188 || reloc_type
== BFD_RELOC_32_PCREL
))
9192 reloc_type
= BFD_RELOC_386_GOTPC
;
9193 i
.has_gotpc_tls_reloc
= TRUE
;
9194 i
.op
[n
].imms
->X_add_number
+=
9195 encoding_length (insn_start_frag
, insn_start_off
, p
);
9197 else if (reloc_type
== BFD_RELOC_64
)
9198 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9200 /* Don't do the adjustment for x86-64, as there
9201 the pcrel addressing is relative to the _next_
9202 insn, and that is taken care of in other code. */
9203 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9205 else if (align_branch_power
)
9209 case BFD_RELOC_386_TLS_GD
:
9210 case BFD_RELOC_386_TLS_LDM
:
9211 case BFD_RELOC_386_TLS_IE
:
9212 case BFD_RELOC_386_TLS_IE_32
:
9213 case BFD_RELOC_386_TLS_GOTIE
:
9214 case BFD_RELOC_386_TLS_GOTDESC
:
9215 case BFD_RELOC_386_TLS_DESC_CALL
:
9216 case BFD_RELOC_X86_64_TLSGD
:
9217 case BFD_RELOC_X86_64_TLSLD
:
9218 case BFD_RELOC_X86_64_GOTTPOFF
:
9219 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9220 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9221 i
.has_gotpc_tls_reloc
= TRUE
;
9226 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9227 size
, i
.op
[n
].disps
, pcrel
,
9229 /* Check for "call/jmp *mem", "mov mem, %reg",
9230 "test %reg, mem" and "binop mem, %reg" where binop
9231 is one of adc, add, and, cmp, or, sbb, sub, xor
9232 instructions without data prefix. Always generate
9233 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9234 if (i
.prefix
[DATA_PREFIX
] == 0
9235 && (generate_relax_relocations
9238 && i
.rm
.regmem
== 5))
9240 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9241 && !is_any_vex_encoding(&i
.tm
)
9242 && ((i
.operands
== 1
9243 && i
.tm
.base_opcode
== 0xff
9244 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9246 && (i
.tm
.base_opcode
== 0x8b
9247 || i
.tm
.base_opcode
== 0x85
9248 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9252 fixP
->fx_tcbit
= i
.rex
!= 0;
9254 && (i
.base_reg
->reg_num
== RegIP
))
9255 fixP
->fx_tcbit2
= 1;
9258 fixP
->fx_tcbit2
= 1;
9266 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9271 for (n
= 0; n
< i
.operands
; n
++)
9273 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9274 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9277 if (operand_type_check (i
.types
[n
], imm
))
9279 if (i
.op
[n
].imms
->X_op
== O_constant
)
9281 int size
= imm_size (n
);
9284 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9286 p
= frag_more (size
);
9287 md_number_to_chars (p
, val
, size
);
9291 /* Not absolute_section.
9292 Need a 32-bit fixup (don't support 8bit
9293 non-absolute imms). Try to support other
9295 enum bfd_reloc_code_real reloc_type
;
9296 int size
= imm_size (n
);
9299 if (i
.types
[n
].bitfield
.imm32s
9300 && (i
.suffix
== QWORD_MNEM_SUFFIX
9301 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9306 p
= frag_more (size
);
9307 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9309 /* This is tough to explain. We end up with this one if we
9310 * have operands that look like
9311 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9312 * obtain the absolute address of the GOT, and it is strongly
9313 * preferable from a performance point of view to avoid using
9314 * a runtime relocation for this. The actual sequence of
9315 * instructions often look something like:
9320 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9322 * The call and pop essentially return the absolute address
9323 * of the label .L66 and store it in %ebx. The linker itself
9324 * will ultimately change the first operand of the addl so
9325 * that %ebx points to the GOT, but to keep things simple, the
9326 * .o file must have this operand set so that it generates not
9327 * the absolute address of .L66, but the absolute address of
9328 * itself. This allows the linker itself simply treat a GOTPC
9329 * relocation as asking for a pcrel offset to the GOT to be
9330 * added in, and the addend of the relocation is stored in the
9331 * operand field for the instruction itself.
9333 * Our job here is to fix the operand so that it would add
9334 * the correct offset so that %ebx would point to itself. The
9335 * thing that is tricky is that .-.L66 will point to the
9336 * beginning of the instruction, so we need to further modify
9337 * the operand so that it will point to itself. There are
9338 * other cases where you have something like:
9340 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9342 * and here no correction would be required. Internally in
9343 * the assembler we treat operands of this form as not being
9344 * pcrel since the '.' is explicitly mentioned, and I wonder
9345 * whether it would simplify matters to do it this way. Who
9346 * knows. In earlier versions of the PIC patches, the
9347 * pcrel_adjust field was used to store the correction, but
9348 * since the expression is not pcrel, I felt it would be
9349 * confusing to do it this way. */
9351 if ((reloc_type
== BFD_RELOC_32
9352 || reloc_type
== BFD_RELOC_X86_64_32S
9353 || reloc_type
== BFD_RELOC_64
)
9355 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9356 && (i
.op
[n
].imms
->X_op
== O_symbol
9357 || (i
.op
[n
].imms
->X_op
== O_add
9358 && ((symbol_get_value_expression
9359 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9363 reloc_type
= BFD_RELOC_386_GOTPC
;
9365 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9367 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9368 i
.has_gotpc_tls_reloc
= TRUE
;
9369 i
.op
[n
].imms
->X_add_number
+=
9370 encoding_length (insn_start_frag
, insn_start_off
, p
);
9372 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9373 i
.op
[n
].imms
, 0, reloc_type
);
9379 /* x86_cons_fix_new is called via the expression parsing code when a
9380 reloc is needed. We use this hook to get the correct .got reloc. */
9381 static int cons_sign
= -1;
9384 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9385 expressionS
*exp
, bfd_reloc_code_real_type r
)
9387 r
= reloc (len
, 0, cons_sign
, r
);
9390 if (exp
->X_op
== O_secrel
)
9392 exp
->X_op
= O_symbol
;
9393 r
= BFD_RELOC_32_SECREL
;
9397 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9400 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9401 purpose of the `.dc.a' internal pseudo-op. */
9404 x86_address_bytes (void)
9406 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9408 return stdoutput
->arch_info
->bits_per_address
/ 8;
9411 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9413 # define lex_got(reloc, adjust, types) NULL
9415 /* Parse operands of the form
9416 <symbol>@GOTOFF+<nnn>
9417 and similar .plt or .got references.
9419 If we find one, set up the correct relocation in RELOC and copy the
9420 input string, minus the `@GOTOFF' into a malloc'd buffer for
9421 parsing by the calling routine. Return this buffer, and if ADJUST
9422 is non-null set it to the length of the string we removed from the
9423 input line. Otherwise return NULL. */
9425 lex_got (enum bfd_reloc_code_real
*rel
,
9427 i386_operand_type
*types
)
9429 /* Some of the relocations depend on the size of what field is to
9430 be relocated. But in our callers i386_immediate and i386_displacement
9431 we don't yet know the operand size (this will be set by insn
9432 matching). Hence we record the word32 relocation here,
9433 and adjust the reloc according to the real size in reloc(). */
9434 static const struct {
9437 const enum bfd_reloc_code_real rel
[2];
9438 const i386_operand_type types64
;
9440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9441 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9443 OPERAND_TYPE_IMM32_64
},
9445 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9446 BFD_RELOC_X86_64_PLTOFF64
},
9447 OPERAND_TYPE_IMM64
},
9448 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9449 BFD_RELOC_X86_64_PLT32
},
9450 OPERAND_TYPE_IMM32_32S_DISP32
},
9451 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9452 BFD_RELOC_X86_64_GOTPLT64
},
9453 OPERAND_TYPE_IMM64_DISP64
},
9454 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9455 BFD_RELOC_X86_64_GOTOFF64
},
9456 OPERAND_TYPE_IMM64_DISP64
},
9457 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9458 BFD_RELOC_X86_64_GOTPCREL
},
9459 OPERAND_TYPE_IMM32_32S_DISP32
},
9460 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9461 BFD_RELOC_X86_64_TLSGD
},
9462 OPERAND_TYPE_IMM32_32S_DISP32
},
9463 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9464 _dummy_first_bfd_reloc_code_real
},
9465 OPERAND_TYPE_NONE
},
9466 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9467 BFD_RELOC_X86_64_TLSLD
},
9468 OPERAND_TYPE_IMM32_32S_DISP32
},
9469 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9470 BFD_RELOC_X86_64_GOTTPOFF
},
9471 OPERAND_TYPE_IMM32_32S_DISP32
},
9472 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9473 BFD_RELOC_X86_64_TPOFF32
},
9474 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9475 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9476 _dummy_first_bfd_reloc_code_real
},
9477 OPERAND_TYPE_NONE
},
9478 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9479 BFD_RELOC_X86_64_DTPOFF32
},
9480 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9481 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9482 _dummy_first_bfd_reloc_code_real
},
9483 OPERAND_TYPE_NONE
},
9484 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9485 _dummy_first_bfd_reloc_code_real
},
9486 OPERAND_TYPE_NONE
},
9487 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9488 BFD_RELOC_X86_64_GOT32
},
9489 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9490 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9491 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9492 OPERAND_TYPE_IMM32_32S_DISP32
},
9493 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9494 BFD_RELOC_X86_64_TLSDESC_CALL
},
9495 OPERAND_TYPE_IMM32_32S_DISP32
},
9500 #if defined (OBJ_MAYBE_ELF)
9505 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9506 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9509 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9511 int len
= gotrel
[j
].len
;
9512 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9514 if (gotrel
[j
].rel
[object_64bit
] != 0)
9517 char *tmpbuf
, *past_reloc
;
9519 *rel
= gotrel
[j
].rel
[object_64bit
];
9523 if (flag_code
!= CODE_64BIT
)
9525 types
->bitfield
.imm32
= 1;
9526 types
->bitfield
.disp32
= 1;
9529 *types
= gotrel
[j
].types64
;
9532 if (j
!= 0 && GOT_symbol
== NULL
)
9533 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9535 /* The length of the first part of our input line. */
9536 first
= cp
- input_line_pointer
;
9538 /* The second part goes from after the reloc token until
9539 (and including) an end_of_line char or comma. */
9540 past_reloc
= cp
+ 1 + len
;
9542 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9544 second
= cp
+ 1 - past_reloc
;
9546 /* Allocate and copy string. The trailing NUL shouldn't
9547 be necessary, but be safe. */
9548 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9549 memcpy (tmpbuf
, input_line_pointer
, first
);
9550 if (second
!= 0 && *past_reloc
!= ' ')
9551 /* Replace the relocation token with ' ', so that
9552 errors like foo@GOTOFF1 will be detected. */
9553 tmpbuf
[first
++] = ' ';
9555 /* Increment length by 1 if the relocation token is
9560 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9561 tmpbuf
[first
+ second
] = '\0';
9565 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9566 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9571 /* Might be a symbol version string. Don't as_bad here. */
9580 /* Parse operands of the form
9581 <symbol>@SECREL32+<nnn>
9583 If we find one, set up the correct relocation in RELOC and copy the
9584 input string, minus the `@SECREL32' into a malloc'd buffer for
9585 parsing by the calling routine. Return this buffer, and if ADJUST
9586 is non-null set it to the length of the string we removed from the
9587 input line. Otherwise return NULL.
9589 This function is copied from the ELF version above adjusted for PE targets. */
9592 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9593 int *adjust ATTRIBUTE_UNUSED
,
9594 i386_operand_type
*types
)
9600 const enum bfd_reloc_code_real rel
[2];
9601 const i386_operand_type types64
;
9605 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9606 BFD_RELOC_32_SECREL
},
9607 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9613 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9614 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9617 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9619 int len
= gotrel
[j
].len
;
9621 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9623 if (gotrel
[j
].rel
[object_64bit
] != 0)
9626 char *tmpbuf
, *past_reloc
;
9628 *rel
= gotrel
[j
].rel
[object_64bit
];
9634 if (flag_code
!= CODE_64BIT
)
9636 types
->bitfield
.imm32
= 1;
9637 types
->bitfield
.disp32
= 1;
9640 *types
= gotrel
[j
].types64
;
9643 /* The length of the first part of our input line. */
9644 first
= cp
- input_line_pointer
;
9646 /* The second part goes from after the reloc token until
9647 (and including) an end_of_line char or comma. */
9648 past_reloc
= cp
+ 1 + len
;
9650 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9652 second
= cp
+ 1 - past_reloc
;
9654 /* Allocate and copy string. The trailing NUL shouldn't
9655 be necessary, but be safe. */
9656 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9657 memcpy (tmpbuf
, input_line_pointer
, first
);
9658 if (second
!= 0 && *past_reloc
!= ' ')
9659 /* Replace the relocation token with ' ', so that
9660 errors like foo@SECLREL321 will be detected. */
9661 tmpbuf
[first
++] = ' ';
9662 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9663 tmpbuf
[first
+ second
] = '\0';
9667 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9668 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9673 /* Might be a symbol version string. Don't as_bad here. */
9679 bfd_reloc_code_real_type
9680 x86_cons (expressionS
*exp
, int size
)
9682 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9684 intel_syntax
= -intel_syntax
;
9687 if (size
== 4 || (object_64bit
&& size
== 8))
9689 /* Handle @GOTOFF and the like in an expression. */
9691 char *gotfree_input_line
;
9694 save
= input_line_pointer
;
9695 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9696 if (gotfree_input_line
)
9697 input_line_pointer
= gotfree_input_line
;
9701 if (gotfree_input_line
)
9703 /* expression () has merrily parsed up to the end of line,
9704 or a comma - in the wrong buffer. Transfer how far
9705 input_line_pointer has moved to the right buffer. */
9706 input_line_pointer
= (save
9707 + (input_line_pointer
- gotfree_input_line
)
9709 free (gotfree_input_line
);
9710 if (exp
->X_op
== O_constant
9711 || exp
->X_op
== O_absent
9712 || exp
->X_op
== O_illegal
9713 || exp
->X_op
== O_register
9714 || exp
->X_op
== O_big
)
9716 char c
= *input_line_pointer
;
9717 *input_line_pointer
= 0;
9718 as_bad (_("missing or invalid expression `%s'"), save
);
9719 *input_line_pointer
= c
;
9721 else if ((got_reloc
== BFD_RELOC_386_PLT32
9722 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9723 && exp
->X_op
!= O_symbol
)
9725 char c
= *input_line_pointer
;
9726 *input_line_pointer
= 0;
9727 as_bad (_("invalid PLT expression `%s'"), save
);
9728 *input_line_pointer
= c
;
9735 intel_syntax
= -intel_syntax
;
9738 i386_intel_simplify (exp
);
9744 signed_cons (int size
)
9746 if (flag_code
== CODE_64BIT
)
9754 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9761 if (exp
.X_op
== O_symbol
)
9762 exp
.X_op
= O_secrel
;
9764 emit_expr (&exp
, 4);
9766 while (*input_line_pointer
++ == ',');
9768 input_line_pointer
--;
9769 demand_empty_rest_of_line ();
9773 /* Handle Vector operations. */
9776 check_VecOperations (char *op_string
, char *op_end
)
9778 const reg_entry
*mask
;
9783 && (op_end
== NULL
|| op_string
< op_end
))
9786 if (*op_string
== '{')
9790 /* Check broadcasts. */
9791 if (strncmp (op_string
, "1to", 3) == 0)
9796 goto duplicated_vec_op
;
9799 if (*op_string
== '8')
9801 else if (*op_string
== '4')
9803 else if (*op_string
== '2')
9805 else if (*op_string
== '1'
9806 && *(op_string
+1) == '6')
9813 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9818 broadcast_op
.type
= bcst_type
;
9819 broadcast_op
.operand
= this_operand
;
9820 broadcast_op
.bytes
= 0;
9821 i
.broadcast
= &broadcast_op
;
9823 /* Check masking operation. */
9824 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9826 /* k0 can't be used for write mask. */
9827 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9829 as_bad (_("`%s%s' can't be used for write mask"),
9830 register_prefix
, mask
->reg_name
);
9836 mask_op
.mask
= mask
;
9837 mask_op
.zeroing
= 0;
9838 mask_op
.operand
= this_operand
;
9844 goto duplicated_vec_op
;
9846 i
.mask
->mask
= mask
;
9848 /* Only "{z}" is allowed here. No need to check
9849 zeroing mask explicitly. */
9850 if (i
.mask
->operand
!= this_operand
)
9852 as_bad (_("invalid write mask `%s'"), saved
);
9859 /* Check zeroing-flag for masking operation. */
9860 else if (*op_string
== 'z')
9864 mask_op
.mask
= NULL
;
9865 mask_op
.zeroing
= 1;
9866 mask_op
.operand
= this_operand
;
9871 if (i
.mask
->zeroing
)
9874 as_bad (_("duplicated `%s'"), saved
);
9878 i
.mask
->zeroing
= 1;
9880 /* Only "{%k}" is allowed here. No need to check mask
9881 register explicitly. */
9882 if (i
.mask
->operand
!= this_operand
)
9884 as_bad (_("invalid zeroing-masking `%s'"),
9893 goto unknown_vec_op
;
9895 if (*op_string
!= '}')
9897 as_bad (_("missing `}' in `%s'"), saved
);
9902 /* Strip whitespace since the addition of pseudo prefixes
9903 changed how the scrubber treats '{'. */
9904 if (is_space_char (*op_string
))
9910 /* We don't know this one. */
9911 as_bad (_("unknown vector operation: `%s'"), saved
);
9915 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9917 as_bad (_("zeroing-masking only allowed with write mask"));
9925 i386_immediate (char *imm_start
)
9927 char *save_input_line_pointer
;
9928 char *gotfree_input_line
;
9931 i386_operand_type types
;
9933 operand_type_set (&types
, ~0);
9935 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9937 as_bad (_("at most %d immediate operands are allowed"),
9938 MAX_IMMEDIATE_OPERANDS
);
9942 exp
= &im_expressions
[i
.imm_operands
++];
9943 i
.op
[this_operand
].imms
= exp
;
9945 if (is_space_char (*imm_start
))
9948 save_input_line_pointer
= input_line_pointer
;
9949 input_line_pointer
= imm_start
;
9951 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9952 if (gotfree_input_line
)
9953 input_line_pointer
= gotfree_input_line
;
9955 exp_seg
= expression (exp
);
9959 /* Handle vector operations. */
9960 if (*input_line_pointer
== '{')
9962 input_line_pointer
= check_VecOperations (input_line_pointer
,
9964 if (input_line_pointer
== NULL
)
9968 if (*input_line_pointer
)
9969 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9971 input_line_pointer
= save_input_line_pointer
;
9972 if (gotfree_input_line
)
9974 free (gotfree_input_line
);
9976 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9977 exp
->X_op
= O_illegal
;
9980 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9984 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9985 i386_operand_type types
, const char *imm_start
)
9987 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9990 as_bad (_("missing or invalid immediate expression `%s'"),
9994 else if (exp
->X_op
== O_constant
)
9996 /* Size it properly later. */
9997 i
.types
[this_operand
].bitfield
.imm64
= 1;
9998 /* If not 64bit, sign extend val. */
9999 if (flag_code
!= CODE_64BIT
10000 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10002 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10004 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10005 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10006 && exp_seg
!= absolute_section
10007 && exp_seg
!= text_section
10008 && exp_seg
!= data_section
10009 && exp_seg
!= bss_section
10010 && exp_seg
!= undefined_section
10011 && !bfd_is_com_section (exp_seg
))
10013 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10017 else if (!intel_syntax
&& exp_seg
== reg_section
)
10020 as_bad (_("illegal immediate register operand %s"), imm_start
);
10025 /* This is an address. The size of the address will be
10026 determined later, depending on destination register,
10027 suffix, or the default for the section. */
10028 i
.types
[this_operand
].bitfield
.imm8
= 1;
10029 i
.types
[this_operand
].bitfield
.imm16
= 1;
10030 i
.types
[this_operand
].bitfield
.imm32
= 1;
10031 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10032 i
.types
[this_operand
].bitfield
.imm64
= 1;
10033 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10041 i386_scale (char *scale
)
10044 char *save
= input_line_pointer
;
10046 input_line_pointer
= scale
;
10047 val
= get_absolute_expression ();
10052 i
.log2_scale_factor
= 0;
10055 i
.log2_scale_factor
= 1;
10058 i
.log2_scale_factor
= 2;
10061 i
.log2_scale_factor
= 3;
10065 char sep
= *input_line_pointer
;
10067 *input_line_pointer
= '\0';
10068 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10070 *input_line_pointer
= sep
;
10071 input_line_pointer
= save
;
10075 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10077 as_warn (_("scale factor of %d without an index register"),
10078 1 << i
.log2_scale_factor
);
10079 i
.log2_scale_factor
= 0;
10081 scale
= input_line_pointer
;
10082 input_line_pointer
= save
;
10087 i386_displacement (char *disp_start
, char *disp_end
)
10091 char *save_input_line_pointer
;
10092 char *gotfree_input_line
;
10094 i386_operand_type bigdisp
, types
= anydisp
;
10097 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10099 as_bad (_("at most %d displacement operands are allowed"),
10100 MAX_MEMORY_OPERANDS
);
10104 operand_type_set (&bigdisp
, 0);
10106 || i
.types
[this_operand
].bitfield
.baseindex
10107 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10108 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10110 i386_addressing_mode ();
10111 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10112 if (flag_code
== CODE_64BIT
)
10116 bigdisp
.bitfield
.disp32s
= 1;
10117 bigdisp
.bitfield
.disp64
= 1;
10120 bigdisp
.bitfield
.disp32
= 1;
10122 else if ((flag_code
== CODE_16BIT
) ^ override
)
10123 bigdisp
.bitfield
.disp16
= 1;
10125 bigdisp
.bitfield
.disp32
= 1;
10129 /* For PC-relative branches, the width of the displacement may be
10130 dependent upon data size, but is never dependent upon address size.
10131 Also make sure to not unintentionally match against a non-PC-relative
10132 branch template. */
10133 static templates aux_templates
;
10134 const insn_template
*t
= current_templates
->start
;
10135 bfd_boolean has_intel64
= FALSE
;
10137 aux_templates
.start
= t
;
10138 while (++t
< current_templates
->end
)
10140 if (t
->opcode_modifier
.jump
10141 != current_templates
->start
->opcode_modifier
.jump
)
10143 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10144 has_intel64
= TRUE
;
10146 if (t
< current_templates
->end
)
10148 aux_templates
.end
= t
;
10149 current_templates
= &aux_templates
;
10152 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10153 if (flag_code
== CODE_64BIT
)
10155 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10156 && (!intel64
|| !has_intel64
))
10157 bigdisp
.bitfield
.disp16
= 1;
10159 bigdisp
.bitfield
.disp32s
= 1;
10164 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10166 : LONG_MNEM_SUFFIX
));
10167 bigdisp
.bitfield
.disp32
= 1;
10168 if ((flag_code
== CODE_16BIT
) ^ override
)
10170 bigdisp
.bitfield
.disp32
= 0;
10171 bigdisp
.bitfield
.disp16
= 1;
10175 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10178 exp
= &disp_expressions
[i
.disp_operands
];
10179 i
.op
[this_operand
].disps
= exp
;
10181 save_input_line_pointer
= input_line_pointer
;
10182 input_line_pointer
= disp_start
;
10183 END_STRING_AND_SAVE (disp_end
);
10185 #ifndef GCC_ASM_O_HACK
10186 #define GCC_ASM_O_HACK 0
10189 END_STRING_AND_SAVE (disp_end
+ 1);
10190 if (i
.types
[this_operand
].bitfield
.baseIndex
10191 && displacement_string_end
[-1] == '+')
10193 /* This hack is to avoid a warning when using the "o"
10194 constraint within gcc asm statements.
10197 #define _set_tssldt_desc(n,addr,limit,type) \
10198 __asm__ __volatile__ ( \
10199 "movw %w2,%0\n\t" \
10200 "movw %w1,2+%0\n\t" \
10201 "rorl $16,%1\n\t" \
10202 "movb %b1,4+%0\n\t" \
10203 "movb %4,5+%0\n\t" \
10204 "movb $0,6+%0\n\t" \
10205 "movb %h1,7+%0\n\t" \
10207 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10209 This works great except that the output assembler ends
10210 up looking a bit weird if it turns out that there is
10211 no offset. You end up producing code that looks like:
10224 So here we provide the missing zero. */
10226 *displacement_string_end
= '0';
10229 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10230 if (gotfree_input_line
)
10231 input_line_pointer
= gotfree_input_line
;
10233 exp_seg
= expression (exp
);
10235 SKIP_WHITESPACE ();
10236 if (*input_line_pointer
)
10237 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10239 RESTORE_END_STRING (disp_end
+ 1);
10241 input_line_pointer
= save_input_line_pointer
;
10242 if (gotfree_input_line
)
10244 free (gotfree_input_line
);
10246 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10247 exp
->X_op
= O_illegal
;
10250 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10252 RESTORE_END_STRING (disp_end
);
10258 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10259 i386_operand_type types
, const char *disp_start
)
10261 i386_operand_type bigdisp
;
10264 /* We do this to make sure that the section symbol is in
10265 the symbol table. We will ultimately change the relocation
10266 to be relative to the beginning of the section. */
10267 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10268 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10269 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10271 if (exp
->X_op
!= O_symbol
)
10274 if (S_IS_LOCAL (exp
->X_add_symbol
)
10275 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10276 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10277 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10278 exp
->X_op
= O_subtract
;
10279 exp
->X_op_symbol
= GOT_symbol
;
10280 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10281 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10282 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10283 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10285 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10288 else if (exp
->X_op
== O_absent
10289 || exp
->X_op
== O_illegal
10290 || exp
->X_op
== O_big
)
10293 as_bad (_("missing or invalid displacement expression `%s'"),
10298 else if (flag_code
== CODE_64BIT
10299 && !i
.prefix
[ADDR_PREFIX
]
10300 && exp
->X_op
== O_constant
)
10302 /* Since displacement is signed extended to 64bit, don't allow
10303 disp32 and turn off disp32s if they are out of range. */
10304 i
.types
[this_operand
].bitfield
.disp32
= 0;
10305 if (!fits_in_signed_long (exp
->X_add_number
))
10307 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10308 if (i
.types
[this_operand
].bitfield
.baseindex
)
10310 as_bad (_("0x%lx out range of signed 32bit displacement"),
10311 (long) exp
->X_add_number
);
10317 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10318 else if (exp
->X_op
!= O_constant
10319 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10320 && exp_seg
!= absolute_section
10321 && exp_seg
!= text_section
10322 && exp_seg
!= data_section
10323 && exp_seg
!= bss_section
10324 && exp_seg
!= undefined_section
10325 && !bfd_is_com_section (exp_seg
))
10327 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10332 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10333 /* Constants get taken care of by optimize_disp(). */
10334 && exp
->X_op
!= O_constant
)
10335 i
.types
[this_operand
].bitfield
.disp8
= 1;
10337 /* Check if this is a displacement only operand. */
10338 bigdisp
= i
.types
[this_operand
];
10339 bigdisp
.bitfield
.disp8
= 0;
10340 bigdisp
.bitfield
.disp16
= 0;
10341 bigdisp
.bitfield
.disp32
= 0;
10342 bigdisp
.bitfield
.disp32s
= 0;
10343 bigdisp
.bitfield
.disp64
= 0;
10344 if (operand_type_all_zero (&bigdisp
))
10345 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10351 /* Return the active addressing mode, taking address override and
10352 registers forming the address into consideration. Update the
10353 address override prefix if necessary. */
10355 static enum flag_code
10356 i386_addressing_mode (void)
10358 enum flag_code addr_mode
;
10360 if (i
.prefix
[ADDR_PREFIX
])
10361 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10362 else if (flag_code
== CODE_16BIT
10363 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10364 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10365 from md_assemble() by "is not a valid base/index expression"
10366 when there is a base and/or index. */
10367 && !i
.types
[this_operand
].bitfield
.baseindex
)
10369 /* MPX insn memory operands with neither base nor index must be forced
10370 to use 32-bit addressing in 16-bit mode. */
10371 addr_mode
= CODE_32BIT
;
10372 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10374 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10375 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10379 addr_mode
= flag_code
;
10381 #if INFER_ADDR_PREFIX
10382 if (i
.mem_operands
== 0)
10384 /* Infer address prefix from the first memory operand. */
10385 const reg_entry
*addr_reg
= i
.base_reg
;
10387 if (addr_reg
== NULL
)
10388 addr_reg
= i
.index_reg
;
10392 if (addr_reg
->reg_type
.bitfield
.dword
)
10393 addr_mode
= CODE_32BIT
;
10394 else if (flag_code
!= CODE_64BIT
10395 && addr_reg
->reg_type
.bitfield
.word
)
10396 addr_mode
= CODE_16BIT
;
10398 if (addr_mode
!= flag_code
)
10400 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10402 /* Change the size of any displacement too. At most one
10403 of Disp16 or Disp32 is set.
10404 FIXME. There doesn't seem to be any real need for
10405 separate Disp16 and Disp32 flags. The same goes for
10406 Imm16 and Imm32. Removing them would probably clean
10407 up the code quite a lot. */
10408 if (flag_code
!= CODE_64BIT
10409 && (i
.types
[this_operand
].bitfield
.disp16
10410 || i
.types
[this_operand
].bitfield
.disp32
))
10411 i
.types
[this_operand
]
10412 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10422 /* Make sure the memory operand we've been dealt is valid.
10423 Return 1 on success, 0 on a failure. */
10426 i386_index_check (const char *operand_string
)
10428 const char *kind
= "base/index";
10429 enum flag_code addr_mode
= i386_addressing_mode ();
10431 if (current_templates
->start
->opcode_modifier
.isstring
10432 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10433 && (current_templates
->end
[-1].opcode_modifier
.isstring
10434 || i
.mem_operands
))
10436 /* Memory operands of string insns are special in that they only allow
10437 a single register (rDI, rSI, or rBX) as their memory address. */
10438 const reg_entry
*expected_reg
;
10439 static const char *di_si
[][2] =
10445 static const char *bx
[] = { "ebx", "bx", "rbx" };
10447 kind
= "string address";
10449 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10451 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10452 - IS_STRING_ES_OP0
;
10455 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10456 || ((!i
.mem_operands
!= !intel_syntax
)
10457 && current_templates
->end
[-1].operand_types
[1]
10458 .bitfield
.baseindex
))
10460 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10463 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10465 if (i
.base_reg
!= expected_reg
10467 || operand_type_check (i
.types
[this_operand
], disp
))
10469 /* The second memory operand must have the same size as
10473 && !((addr_mode
== CODE_64BIT
10474 && i
.base_reg
->reg_type
.bitfield
.qword
)
10475 || (addr_mode
== CODE_32BIT
10476 ? i
.base_reg
->reg_type
.bitfield
.dword
10477 : i
.base_reg
->reg_type
.bitfield
.word
)))
10480 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10482 intel_syntax
? '[' : '(',
10484 expected_reg
->reg_name
,
10485 intel_syntax
? ']' : ')');
10492 as_bad (_("`%s' is not a valid %s expression"),
10493 operand_string
, kind
);
10498 if (addr_mode
!= CODE_16BIT
)
10500 /* 32-bit/64-bit checks. */
10502 && ((addr_mode
== CODE_64BIT
10503 ? !i
.base_reg
->reg_type
.bitfield
.qword
10504 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10505 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10506 || i
.base_reg
->reg_num
== RegIZ
))
10508 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10509 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10510 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10511 && ((addr_mode
== CODE_64BIT
10512 ? !i
.index_reg
->reg_type
.bitfield
.qword
10513 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10514 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10517 /* bndmk, bndldx, and bndstx have special restrictions. */
10518 if (current_templates
->start
->base_opcode
== 0xf30f1b
10519 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10521 /* They cannot use RIP-relative addressing. */
10522 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10524 as_bad (_("`%s' cannot be used here"), operand_string
);
10528 /* bndldx and bndstx ignore their scale factor. */
10529 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10530 && i
.log2_scale_factor
)
10531 as_warn (_("register scaling is being ignored here"));
10536 /* 16-bit checks. */
10538 && (!i
.base_reg
->reg_type
.bitfield
.word
10539 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10541 && (!i
.index_reg
->reg_type
.bitfield
.word
10542 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10544 && i
.base_reg
->reg_num
< 6
10545 && i
.index_reg
->reg_num
>= 6
10546 && i
.log2_scale_factor
== 0))))
10553 /* Handle vector immediates. */
10556 RC_SAE_immediate (const char *imm_start
)
10558 unsigned int match_found
, j
;
10559 const char *pstr
= imm_start
;
10567 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10569 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10573 rc_op
.type
= RC_NamesTable
[j
].type
;
10574 rc_op
.operand
= this_operand
;
10575 i
.rounding
= &rc_op
;
10579 as_bad (_("duplicated `%s'"), imm_start
);
10582 pstr
+= RC_NamesTable
[j
].len
;
10590 if (*pstr
++ != '}')
10592 as_bad (_("Missing '}': '%s'"), imm_start
);
10595 /* RC/SAE immediate string should contain nothing more. */;
10598 as_bad (_("Junk after '}': '%s'"), imm_start
);
10602 exp
= &im_expressions
[i
.imm_operands
++];
10603 i
.op
[this_operand
].imms
= exp
;
10605 exp
->X_op
= O_constant
;
10606 exp
->X_add_number
= 0;
10607 exp
->X_add_symbol
= (symbolS
*) 0;
10608 exp
->X_op_symbol
= (symbolS
*) 0;
10610 i
.types
[this_operand
].bitfield
.imm8
= 1;
10614 /* Only string instructions can have a second memory operand, so
10615 reduce current_templates to just those if it contains any. */
10617 maybe_adjust_templates (void)
10619 const insn_template
*t
;
10621 gas_assert (i
.mem_operands
== 1);
10623 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10624 if (t
->opcode_modifier
.isstring
)
10627 if (t
< current_templates
->end
)
10629 static templates aux_templates
;
10630 bfd_boolean recheck
;
10632 aux_templates
.start
= t
;
10633 for (; t
< current_templates
->end
; ++t
)
10634 if (!t
->opcode_modifier
.isstring
)
10636 aux_templates
.end
= t
;
10638 /* Determine whether to re-check the first memory operand. */
10639 recheck
= (aux_templates
.start
!= current_templates
->start
10640 || t
!= current_templates
->end
);
10642 current_templates
= &aux_templates
;
10646 i
.mem_operands
= 0;
10647 if (i
.memop1_string
!= NULL
10648 && i386_index_check (i
.memop1_string
) == 0)
10650 i
.mem_operands
= 1;
10657 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10661 i386_att_operand (char *operand_string
)
10663 const reg_entry
*r
;
10665 char *op_string
= operand_string
;
10667 if (is_space_char (*op_string
))
10670 /* We check for an absolute prefix (differentiating,
10671 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10672 if (*op_string
== ABSOLUTE_PREFIX
)
10675 if (is_space_char (*op_string
))
10677 i
.jumpabsolute
= TRUE
;
10680 /* Check if operand is a register. */
10681 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10683 i386_operand_type temp
;
10685 /* Check for a segment override by searching for ':' after a
10686 segment register. */
10687 op_string
= end_op
;
10688 if (is_space_char (*op_string
))
10690 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10692 switch (r
->reg_num
)
10695 i
.seg
[i
.mem_operands
] = &es
;
10698 i
.seg
[i
.mem_operands
] = &cs
;
10701 i
.seg
[i
.mem_operands
] = &ss
;
10704 i
.seg
[i
.mem_operands
] = &ds
;
10707 i
.seg
[i
.mem_operands
] = &fs
;
10710 i
.seg
[i
.mem_operands
] = &gs
;
10714 /* Skip the ':' and whitespace. */
10716 if (is_space_char (*op_string
))
10719 if (!is_digit_char (*op_string
)
10720 && !is_identifier_char (*op_string
)
10721 && *op_string
!= '('
10722 && *op_string
!= ABSOLUTE_PREFIX
)
10724 as_bad (_("bad memory operand `%s'"), op_string
);
10727 /* Handle case of %es:*foo. */
10728 if (*op_string
== ABSOLUTE_PREFIX
)
10731 if (is_space_char (*op_string
))
10733 i
.jumpabsolute
= TRUE
;
10735 goto do_memory_reference
;
10738 /* Handle vector operations. */
10739 if (*op_string
== '{')
10741 op_string
= check_VecOperations (op_string
, NULL
);
10742 if (op_string
== NULL
)
10748 as_bad (_("junk `%s' after register"), op_string
);
10751 temp
= r
->reg_type
;
10752 temp
.bitfield
.baseindex
= 0;
10753 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10755 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10756 i
.op
[this_operand
].regs
= r
;
10759 else if (*op_string
== REGISTER_PREFIX
)
10761 as_bad (_("bad register name `%s'"), op_string
);
10764 else if (*op_string
== IMMEDIATE_PREFIX
)
10767 if (i
.jumpabsolute
)
10769 as_bad (_("immediate operand illegal with absolute jump"));
10772 if (!i386_immediate (op_string
))
10775 else if (RC_SAE_immediate (operand_string
))
10777 /* If it is a RC or SAE immediate, do nothing. */
10780 else if (is_digit_char (*op_string
)
10781 || is_identifier_char (*op_string
)
10782 || *op_string
== '"'
10783 || *op_string
== '(')
10785 /* This is a memory reference of some sort. */
10788 /* Start and end of displacement string expression (if found). */
10789 char *displacement_string_start
;
10790 char *displacement_string_end
;
10793 do_memory_reference
:
10794 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10796 if ((i
.mem_operands
== 1
10797 && !current_templates
->start
->opcode_modifier
.isstring
)
10798 || i
.mem_operands
== 2)
10800 as_bad (_("too many memory references for `%s'"),
10801 current_templates
->start
->name
);
10805 /* Check for base index form. We detect the base index form by
10806 looking for an ')' at the end of the operand, searching
10807 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10809 base_string
= op_string
+ strlen (op_string
);
10811 /* Handle vector operations. */
10812 vop_start
= strchr (op_string
, '{');
10813 if (vop_start
&& vop_start
< base_string
)
10815 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10817 base_string
= vop_start
;
10821 if (is_space_char (*base_string
))
10824 /* If we only have a displacement, set-up for it to be parsed later. */
10825 displacement_string_start
= op_string
;
10826 displacement_string_end
= base_string
+ 1;
10828 if (*base_string
== ')')
10831 unsigned int parens_balanced
= 1;
10832 /* We've already checked that the number of left & right ()'s are
10833 equal, so this loop will not be infinite. */
10837 if (*base_string
== ')')
10839 if (*base_string
== '(')
10842 while (parens_balanced
);
10844 temp_string
= base_string
;
10846 /* Skip past '(' and whitespace. */
10848 if (is_space_char (*base_string
))
10851 if (*base_string
== ','
10852 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10855 displacement_string_end
= temp_string
;
10857 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10861 base_string
= end_op
;
10862 if (is_space_char (*base_string
))
10866 /* There may be an index reg or scale factor here. */
10867 if (*base_string
== ',')
10870 if (is_space_char (*base_string
))
10873 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10876 base_string
= end_op
;
10877 if (is_space_char (*base_string
))
10879 if (*base_string
== ',')
10882 if (is_space_char (*base_string
))
10885 else if (*base_string
!= ')')
10887 as_bad (_("expecting `,' or `)' "
10888 "after index register in `%s'"),
10893 else if (*base_string
== REGISTER_PREFIX
)
10895 end_op
= strchr (base_string
, ',');
10898 as_bad (_("bad register name `%s'"), base_string
);
10902 /* Check for scale factor. */
10903 if (*base_string
!= ')')
10905 char *end_scale
= i386_scale (base_string
);
10910 base_string
= end_scale
;
10911 if (is_space_char (*base_string
))
10913 if (*base_string
!= ')')
10915 as_bad (_("expecting `)' "
10916 "after scale factor in `%s'"),
10921 else if (!i
.index_reg
)
10923 as_bad (_("expecting index register or scale factor "
10924 "after `,'; got '%c'"),
10929 else if (*base_string
!= ')')
10931 as_bad (_("expecting `,' or `)' "
10932 "after base register in `%s'"),
10937 else if (*base_string
== REGISTER_PREFIX
)
10939 end_op
= strchr (base_string
, ',');
10942 as_bad (_("bad register name `%s'"), base_string
);
10947 /* If there's an expression beginning the operand, parse it,
10948 assuming displacement_string_start and
10949 displacement_string_end are meaningful. */
10950 if (displacement_string_start
!= displacement_string_end
)
10952 if (!i386_displacement (displacement_string_start
,
10953 displacement_string_end
))
10957 /* Special case for (%dx) while doing input/output op. */
10959 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10960 && i
.base_reg
->reg_type
.bitfield
.word
10961 && i
.index_reg
== 0
10962 && i
.log2_scale_factor
== 0
10963 && i
.seg
[i
.mem_operands
] == 0
10964 && !operand_type_check (i
.types
[this_operand
], disp
))
10966 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10970 if (i386_index_check (operand_string
) == 0)
10972 i
.flags
[this_operand
] |= Operand_Mem
;
10973 if (i
.mem_operands
== 0)
10974 i
.memop1_string
= xstrdup (operand_string
);
10979 /* It's not a memory operand; argh! */
10980 as_bad (_("invalid char %s beginning operand %d `%s'"),
10981 output_invalid (*op_string
),
10986 return 1; /* Normal return. */
10989 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10990 that an rs_machine_dependent frag may reach. */
10993 i386_frag_max_var (fragS
*frag
)
10995 /* The only relaxable frags are for jumps.
10996 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10997 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10998 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11003 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11005 /* STT_GNU_IFUNC symbol must go through PLT. */
11006 if ((symbol_get_bfdsym (fr_symbol
)->flags
11007 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11010 if (!S_IS_EXTERNAL (fr_symbol
))
11011 /* Symbol may be weak or local. */
11012 return !S_IS_WEAK (fr_symbol
);
11014 /* Global symbols with non-default visibility can't be preempted. */
11015 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11018 if (fr_var
!= NO_RELOC
)
11019 switch ((enum bfd_reloc_code_real
) fr_var
)
11021 case BFD_RELOC_386_PLT32
:
11022 case BFD_RELOC_X86_64_PLT32
:
11023 /* Symbol with PLT relocation may be preempted. */
11029 /* Global symbols with default visibility in a shared library may be
11030 preempted by another definition. */
11035 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11036 Note also work for Skylake and Cascadelake.
11037 ---------------------------------------------------------------------
11038 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11039 | ------ | ----------- | ------- | -------- |
11041 | Jno | N | N | Y |
11042 | Jc/Jb | Y | N | Y |
11043 | Jae/Jnb | Y | N | Y |
11044 | Je/Jz | Y | Y | Y |
11045 | Jne/Jnz | Y | Y | Y |
11046 | Jna/Jbe | Y | N | Y |
11047 | Ja/Jnbe | Y | N | Y |
11049 | Jns | N | N | Y |
11050 | Jp/Jpe | N | N | Y |
11051 | Jnp/Jpo | N | N | Y |
11052 | Jl/Jnge | Y | Y | Y |
11053 | Jge/Jnl | Y | Y | Y |
11054 | Jle/Jng | Y | Y | Y |
11055 | Jg/Jnle | Y | Y | Y |
11056 --------------------------------------------------------------------- */
11058 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11060 if (mf_cmp
== mf_cmp_alu_cmp
)
11061 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11062 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11063 if (mf_cmp
== mf_cmp_incdec
)
11064 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11065 || mf_jcc
== mf_jcc_jle
);
11066 if (mf_cmp
== mf_cmp_test_and
)
11071 /* Return the next non-empty frag. */
11074 i386_next_non_empty_frag (fragS
*fragP
)
11076 /* There may be a frag with a ".fill 0" when there is no room in
11077 the current frag for frag_grow in output_insn. */
11078 for (fragP
= fragP
->fr_next
;
11080 && fragP
->fr_type
== rs_fill
11081 && fragP
->fr_fix
== 0);
11082 fragP
= fragP
->fr_next
)
11087 /* Return the next jcc frag after BRANCH_PADDING. */
11090 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11092 fragS
*branch_fragP
;
11096 if (pad_fragP
->fr_type
== rs_machine_dependent
11097 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11098 == BRANCH_PADDING
))
11100 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11101 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11103 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11104 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11105 pad_fragP
->tc_frag_data
.mf_type
))
11106 return branch_fragP
;
11112 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11115 i386_classify_machine_dependent_frag (fragS
*fragP
)
11119 fragS
*branch_fragP
;
11121 unsigned int max_prefix_length
;
11123 if (fragP
->tc_frag_data
.classified
)
11126 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11127 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11128 for (next_fragP
= fragP
;
11129 next_fragP
!= NULL
;
11130 next_fragP
= next_fragP
->fr_next
)
11132 next_fragP
->tc_frag_data
.classified
= 1;
11133 if (next_fragP
->fr_type
== rs_machine_dependent
)
11134 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11136 case BRANCH_PADDING
:
11137 /* The BRANCH_PADDING frag must be followed by a branch
11139 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11140 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11142 case FUSED_JCC_PADDING
:
11143 /* Check if this is a fused jcc:
11145 CMP like instruction
11149 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11150 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11151 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11154 /* The BRANCH_PADDING frag is merged with the
11155 FUSED_JCC_PADDING frag. */
11156 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11157 /* CMP like instruction size. */
11158 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11159 frag_wane (pad_fragP
);
11160 /* Skip to branch_fragP. */
11161 next_fragP
= branch_fragP
;
11163 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11165 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11167 next_fragP
->fr_subtype
11168 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11169 next_fragP
->tc_frag_data
.max_bytes
11170 = next_fragP
->tc_frag_data
.max_prefix_length
;
11171 /* This will be updated in the BRANCH_PREFIX scan. */
11172 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11175 frag_wane (next_fragP
);
11180 /* Stop if there is no BRANCH_PREFIX. */
11181 if (!align_branch_prefix_size
)
11184 /* Scan for BRANCH_PREFIX. */
11185 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11187 if (fragP
->fr_type
!= rs_machine_dependent
11188 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11192 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11193 COND_JUMP_PREFIX. */
11194 max_prefix_length
= 0;
11195 for (next_fragP
= fragP
;
11196 next_fragP
!= NULL
;
11197 next_fragP
= next_fragP
->fr_next
)
11199 if (next_fragP
->fr_type
== rs_fill
)
11200 /* Skip rs_fill frags. */
11202 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11203 /* Stop for all other frags. */
11206 /* rs_machine_dependent frags. */
11207 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11210 /* Count BRANCH_PREFIX frags. */
11211 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11213 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11214 frag_wane (next_fragP
);
11218 += next_fragP
->tc_frag_data
.max_bytes
;
11220 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11222 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11223 == FUSED_JCC_PADDING
))
11225 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11226 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11230 /* Stop for other rs_machine_dependent frags. */
11234 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11236 /* Skip to the next frag. */
11237 fragP
= next_fragP
;
11241 /* Compute padding size for
11244 CMP like instruction
11246 COND_JUMP/UNCOND_JUMP
11251 COND_JUMP/UNCOND_JUMP
11255 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11257 unsigned int offset
, size
, padding_size
;
11258 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11260 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11262 address
= fragP
->fr_address
;
11263 address
+= fragP
->fr_fix
;
11265 /* CMP like instrunction size. */
11266 size
= fragP
->tc_frag_data
.cmp_size
;
11268 /* The base size of the branch frag. */
11269 size
+= branch_fragP
->fr_fix
;
11271 /* Add opcode and displacement bytes for the rs_machine_dependent
11273 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11274 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11276 /* Check if branch is within boundary and doesn't end at the last
11278 offset
= address
& ((1U << align_branch_power
) - 1);
11279 if ((offset
+ size
) >= (1U << align_branch_power
))
11280 /* Padding needed to avoid crossing boundary. */
11281 padding_size
= (1U << align_branch_power
) - offset
;
11283 /* No padding needed. */
11286 /* The return value may be saved in tc_frag_data.length which is
11288 if (!fits_in_unsigned_byte (padding_size
))
11291 return padding_size
;
11294 /* i386_generic_table_relax_frag()
11296 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11297 grow/shrink padding to align branch frags. Hand others to
11301 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11303 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11304 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11306 long padding_size
= i386_branch_padding_size (fragP
, 0);
11307 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11309 /* When the BRANCH_PREFIX frag is used, the computed address
11310 must match the actual address and there should be no padding. */
11311 if (fragP
->tc_frag_data
.padding_address
11312 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11316 /* Update the padding size. */
11318 fragP
->tc_frag_data
.length
= padding_size
;
11322 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11324 fragS
*padding_fragP
, *next_fragP
;
11325 long padding_size
, left_size
, last_size
;
11327 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11328 if (!padding_fragP
)
11329 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11330 return (fragP
->tc_frag_data
.length
11331 - fragP
->tc_frag_data
.last_length
);
11333 /* Compute the relative address of the padding frag in the very
11334 first time where the BRANCH_PREFIX frag sizes are zero. */
11335 if (!fragP
->tc_frag_data
.padding_address
)
11336 fragP
->tc_frag_data
.padding_address
11337 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11339 /* First update the last length from the previous interation. */
11340 left_size
= fragP
->tc_frag_data
.prefix_length
;
11341 for (next_fragP
= fragP
;
11342 next_fragP
!= padding_fragP
;
11343 next_fragP
= next_fragP
->fr_next
)
11344 if (next_fragP
->fr_type
== rs_machine_dependent
11345 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11350 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11354 if (max
> left_size
)
11359 next_fragP
->tc_frag_data
.last_length
= size
;
11363 next_fragP
->tc_frag_data
.last_length
= 0;
11366 /* Check the padding size for the padding frag. */
11367 padding_size
= i386_branch_padding_size
11368 (padding_fragP
, (fragP
->fr_address
11369 + fragP
->tc_frag_data
.padding_address
));
11371 last_size
= fragP
->tc_frag_data
.prefix_length
;
11372 /* Check if there is change from the last interation. */
11373 if (padding_size
== last_size
)
11375 /* Update the expected address of the padding frag. */
11376 padding_fragP
->tc_frag_data
.padding_address
11377 = (fragP
->fr_address
+ padding_size
11378 + fragP
->tc_frag_data
.padding_address
);
11382 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11384 /* No padding if there is no sufficient room. Clear the
11385 expected address of the padding frag. */
11386 padding_fragP
->tc_frag_data
.padding_address
= 0;
11390 /* Store the expected address of the padding frag. */
11391 padding_fragP
->tc_frag_data
.padding_address
11392 = (fragP
->fr_address
+ padding_size
11393 + fragP
->tc_frag_data
.padding_address
);
11395 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11397 /* Update the length for the current interation. */
11398 left_size
= padding_size
;
11399 for (next_fragP
= fragP
;
11400 next_fragP
!= padding_fragP
;
11401 next_fragP
= next_fragP
->fr_next
)
11402 if (next_fragP
->fr_type
== rs_machine_dependent
11403 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11408 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11412 if (max
> left_size
)
11417 next_fragP
->tc_frag_data
.length
= size
;
11421 next_fragP
->tc_frag_data
.length
= 0;
11424 return (fragP
->tc_frag_data
.length
11425 - fragP
->tc_frag_data
.last_length
);
11427 return relax_frag (segment
, fragP
, stretch
);
11430 /* md_estimate_size_before_relax()
11432 Called just before relax() for rs_machine_dependent frags. The x86
11433 assembler uses these frags to handle variable size jump
11436 Any symbol that is now undefined will not become defined.
11437 Return the correct fr_subtype in the frag.
11438 Return the initial "guess for variable size of frag" to caller.
11439 The guess is actually the growth beyond the fixed part. Whatever
11440 we do to grow the fixed or variable part contributes to our
11444 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11446 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11447 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11448 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11450 i386_classify_machine_dependent_frag (fragP
);
11451 return fragP
->tc_frag_data
.length
;
11454 /* We've already got fragP->fr_subtype right; all we have to do is
11455 check for un-relaxable symbols. On an ELF system, we can't relax
11456 an externally visible symbol, because it may be overridden by a
11458 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11459 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11461 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11464 #if defined (OBJ_COFF) && defined (TE_PE)
11465 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11466 && S_IS_WEAK (fragP
->fr_symbol
))
11470 /* Symbol is undefined in this segment, or we need to keep a
11471 reloc so that weak symbols can be overridden. */
11472 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11473 enum bfd_reloc_code_real reloc_type
;
11474 unsigned char *opcode
;
11477 if (fragP
->fr_var
!= NO_RELOC
)
11478 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11479 else if (size
== 2)
11480 reloc_type
= BFD_RELOC_16_PCREL
;
11481 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11482 else if (need_plt32_p (fragP
->fr_symbol
))
11483 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11486 reloc_type
= BFD_RELOC_32_PCREL
;
11488 old_fr_fix
= fragP
->fr_fix
;
11489 opcode
= (unsigned char *) fragP
->fr_opcode
;
11491 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11494 /* Make jmp (0xeb) a (d)word displacement jump. */
11496 fragP
->fr_fix
+= size
;
11497 fix_new (fragP
, old_fr_fix
, size
,
11499 fragP
->fr_offset
, 1,
11505 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11507 /* Negate the condition, and branch past an
11508 unconditional jump. */
11511 /* Insert an unconditional jump. */
11513 /* We added two extra opcode bytes, and have a two byte
11515 fragP
->fr_fix
+= 2 + 2;
11516 fix_new (fragP
, old_fr_fix
+ 2, 2,
11518 fragP
->fr_offset
, 1,
11522 /* Fall through. */
11525 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11529 fragP
->fr_fix
+= 1;
11530 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11532 fragP
->fr_offset
, 1,
11533 BFD_RELOC_8_PCREL
);
11534 fixP
->fx_signed
= 1;
11538 /* This changes the byte-displacement jump 0x7N
11539 to the (d)word-displacement jump 0x0f,0x8N. */
11540 opcode
[1] = opcode
[0] + 0x10;
11541 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11542 /* We've added an opcode byte. */
11543 fragP
->fr_fix
+= 1 + size
;
11544 fix_new (fragP
, old_fr_fix
+ 1, size
,
11546 fragP
->fr_offset
, 1,
11551 BAD_CASE (fragP
->fr_subtype
);
11555 return fragP
->fr_fix
- old_fr_fix
;
11558 /* Guess size depending on current relax state. Initially the relax
11559 state will correspond to a short jump and we return 1, because
11560 the variable part of the frag (the branch offset) is one byte
11561 long. However, we can relax a section more than once and in that
11562 case we must either set fr_subtype back to the unrelaxed state,
11563 or return the value for the appropriate branch. */
11564 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11567 /* Called after relax() is finished.
11569 In: Address of frag.
11570 fr_type == rs_machine_dependent.
11571 fr_subtype is what the address relaxed to.
11573 Out: Any fixSs and constants are set up.
11574 Caller will turn frag into a ".space 0". */
11577 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11580 unsigned char *opcode
;
11581 unsigned char *where_to_put_displacement
= NULL
;
11582 offsetT target_address
;
11583 offsetT opcode_address
;
11584 unsigned int extension
= 0;
11585 offsetT displacement_from_opcode_start
;
11587 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11588 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11589 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11591 /* Generate nop padding. */
11592 unsigned int size
= fragP
->tc_frag_data
.length
;
11595 if (size
> fragP
->tc_frag_data
.max_bytes
)
11601 const char *branch
= "branch";
11602 const char *prefix
= "";
11603 fragS
*padding_fragP
;
11604 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11607 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11608 switch (fragP
->tc_frag_data
.default_prefix
)
11613 case CS_PREFIX_OPCODE
:
11616 case DS_PREFIX_OPCODE
:
11619 case ES_PREFIX_OPCODE
:
11622 case FS_PREFIX_OPCODE
:
11625 case GS_PREFIX_OPCODE
:
11628 case SS_PREFIX_OPCODE
:
11633 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11634 "%s within %d-byte boundary\n");
11636 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11637 "align %s within %d-byte boundary\n");
11641 padding_fragP
= fragP
;
11642 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11643 "%s within %d-byte boundary\n");
11647 switch (padding_fragP
->tc_frag_data
.branch_type
)
11649 case align_branch_jcc
:
11652 case align_branch_fused
:
11653 branch
= "fused jcc";
11655 case align_branch_jmp
:
11658 case align_branch_call
:
11661 case align_branch_indirect
:
11662 branch
= "indiret branch";
11664 case align_branch_ret
:
11671 fprintf (stdout
, msg
,
11672 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11673 (long long) fragP
->fr_address
, branch
,
11674 1 << align_branch_power
);
11676 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11677 memset (fragP
->fr_opcode
,
11678 fragP
->tc_frag_data
.default_prefix
, size
);
11680 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11682 fragP
->fr_fix
+= size
;
11687 opcode
= (unsigned char *) fragP
->fr_opcode
;
11689 /* Address we want to reach in file space. */
11690 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11692 /* Address opcode resides at in file space. */
11693 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11695 /* Displacement from opcode start to fill into instruction. */
11696 displacement_from_opcode_start
= target_address
- opcode_address
;
11698 if ((fragP
->fr_subtype
& BIG
) == 0)
11700 /* Don't have to change opcode. */
11701 extension
= 1; /* 1 opcode + 1 displacement */
11702 where_to_put_displacement
= &opcode
[1];
11706 if (no_cond_jump_promotion
11707 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11708 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11709 _("long jump required"));
11711 switch (fragP
->fr_subtype
)
11713 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11714 extension
= 4; /* 1 opcode + 4 displacement */
11716 where_to_put_displacement
= &opcode
[1];
11719 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11720 extension
= 2; /* 1 opcode + 2 displacement */
11722 where_to_put_displacement
= &opcode
[1];
11725 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11726 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11727 extension
= 5; /* 2 opcode + 4 displacement */
11728 opcode
[1] = opcode
[0] + 0x10;
11729 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11730 where_to_put_displacement
= &opcode
[2];
11733 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11734 extension
= 3; /* 2 opcode + 2 displacement */
11735 opcode
[1] = opcode
[0] + 0x10;
11736 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11737 where_to_put_displacement
= &opcode
[2];
11740 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11745 where_to_put_displacement
= &opcode
[3];
11749 BAD_CASE (fragP
->fr_subtype
);
11754 /* If size if less then four we are sure that the operand fits,
11755 but if it's 4, then it could be that the displacement is larger
11757 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11759 && ((addressT
) (displacement_from_opcode_start
- extension
11760 + ((addressT
) 1 << 31))
11761 > (((addressT
) 2 << 31) - 1)))
11763 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11764 _("jump target out of range"));
11765 /* Make us emit 0. */
11766 displacement_from_opcode_start
= extension
;
11768 /* Now put displacement after opcode. */
11769 md_number_to_chars ((char *) where_to_put_displacement
,
11770 (valueT
) (displacement_from_opcode_start
- extension
),
11771 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11772 fragP
->fr_fix
+= extension
;
11775 /* Apply a fixup (fixP) to segment data, once it has been determined
11776 by our caller that we have all the info we need to fix it up.
11778 Parameter valP is the pointer to the value of the bits.
11780 On the 386, immediates, displacements, and data pointers are all in
11781 the same (little-endian) format, so we don't need to care about which
11782 we are handling. */
11785 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11787 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11788 valueT value
= *valP
;
11790 #if !defined (TE_Mach)
11791 if (fixP
->fx_pcrel
)
11793 switch (fixP
->fx_r_type
)
11799 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11802 case BFD_RELOC_X86_64_32S
:
11803 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11806 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11809 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11814 if (fixP
->fx_addsy
!= NULL
11815 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11816 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11817 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11818 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11819 && !use_rela_relocations
)
11821 /* This is a hack. There should be a better way to handle this.
11822 This covers for the fact that bfd_install_relocation will
11823 subtract the current location (for partial_inplace, PC relative
11824 relocations); see more below. */
11828 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11831 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11833 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11836 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11838 if ((sym_seg
== seg
11839 || (symbol_section_p (fixP
->fx_addsy
)
11840 && sym_seg
!= absolute_section
))
11841 && !generic_force_reloc (fixP
))
11843 /* Yes, we add the values in twice. This is because
11844 bfd_install_relocation subtracts them out again. I think
11845 bfd_install_relocation is broken, but I don't dare change
11847 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11851 #if defined (OBJ_COFF) && defined (TE_PE)
11852 /* For some reason, the PE format does not store a
11853 section address offset for a PC relative symbol. */
11854 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11855 || S_IS_WEAK (fixP
->fx_addsy
))
11856 value
+= md_pcrel_from (fixP
);
11859 #if defined (OBJ_COFF) && defined (TE_PE)
11860 if (fixP
->fx_addsy
!= NULL
11861 && S_IS_WEAK (fixP
->fx_addsy
)
11862 /* PR 16858: Do not modify weak function references. */
11863 && ! fixP
->fx_pcrel
)
11865 #if !defined (TE_PEP)
11866 /* For x86 PE weak function symbols are neither PC-relative
11867 nor do they set S_IS_FUNCTION. So the only reliable way
11868 to detect them is to check the flags of their containing
11870 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11871 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11875 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11879 /* Fix a few things - the dynamic linker expects certain values here,
11880 and we must not disappoint it. */
11881 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11882 if (IS_ELF
&& fixP
->fx_addsy
)
11883 switch (fixP
->fx_r_type
)
11885 case BFD_RELOC_386_PLT32
:
11886 case BFD_RELOC_X86_64_PLT32
:
11887 /* Make the jump instruction point to the address of the operand.
11888 At runtime we merely add the offset to the actual PLT entry.
11889 NB: Subtract the offset size only for jump instructions. */
11890 if (fixP
->fx_pcrel
)
11894 case BFD_RELOC_386_TLS_GD
:
11895 case BFD_RELOC_386_TLS_LDM
:
11896 case BFD_RELOC_386_TLS_IE_32
:
11897 case BFD_RELOC_386_TLS_IE
:
11898 case BFD_RELOC_386_TLS_GOTIE
:
11899 case BFD_RELOC_386_TLS_GOTDESC
:
11900 case BFD_RELOC_X86_64_TLSGD
:
11901 case BFD_RELOC_X86_64_TLSLD
:
11902 case BFD_RELOC_X86_64_GOTTPOFF
:
11903 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11904 value
= 0; /* Fully resolved at runtime. No addend. */
11906 case BFD_RELOC_386_TLS_LE
:
11907 case BFD_RELOC_386_TLS_LDO_32
:
11908 case BFD_RELOC_386_TLS_LE_32
:
11909 case BFD_RELOC_X86_64_DTPOFF32
:
11910 case BFD_RELOC_X86_64_DTPOFF64
:
11911 case BFD_RELOC_X86_64_TPOFF32
:
11912 case BFD_RELOC_X86_64_TPOFF64
:
11913 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11916 case BFD_RELOC_386_TLS_DESC_CALL
:
11917 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11918 value
= 0; /* Fully resolved at runtime. No addend. */
11919 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11923 case BFD_RELOC_VTABLE_INHERIT
:
11924 case BFD_RELOC_VTABLE_ENTRY
:
11931 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11933 #endif /* !defined (TE_Mach) */
11935 /* Are we finished with this relocation now? */
11936 if (fixP
->fx_addsy
== NULL
)
11938 #if defined (OBJ_COFF) && defined (TE_PE)
11939 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11942 /* Remember value for tc_gen_reloc. */
11943 fixP
->fx_addnumber
= value
;
11944 /* Clear out the frag for now. */
11948 else if (use_rela_relocations
)
11950 fixP
->fx_no_overflow
= 1;
11951 /* Remember value for tc_gen_reloc. */
11952 fixP
->fx_addnumber
= value
;
11956 md_number_to_chars (p
, value
, fixP
->fx_size
);
11960 md_atof (int type
, char *litP
, int *sizeP
)
11962 /* This outputs the LITTLENUMs in REVERSE order;
11963 in accord with the bigendian 386. */
11964 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11967 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11970 output_invalid (int c
)
11973 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11976 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11977 "(0x%x)", (unsigned char) c
);
11978 return output_invalid_buf
;
11981 /* REG_STRING starts *before* REGISTER_PREFIX. */
11983 static const reg_entry
*
11984 parse_real_register (char *reg_string
, char **end_op
)
11986 char *s
= reg_string
;
11988 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11989 const reg_entry
*r
;
11991 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11992 if (*s
== REGISTER_PREFIX
)
11995 if (is_space_char (*s
))
11998 p
= reg_name_given
;
11999 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12001 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12002 return (const reg_entry
*) NULL
;
12006 /* For naked regs, make sure that we are not dealing with an identifier.
12007 This prevents confusing an identifier like `eax_var' with register
12009 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12010 return (const reg_entry
*) NULL
;
12014 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12016 /* Handle floating point regs, allowing spaces in the (i) part. */
12017 if (r
== i386_regtab
/* %st is first entry of table */)
12019 if (!cpu_arch_flags
.bitfield
.cpu8087
12020 && !cpu_arch_flags
.bitfield
.cpu287
12021 && !cpu_arch_flags
.bitfield
.cpu387
)
12022 return (const reg_entry
*) NULL
;
12024 if (is_space_char (*s
))
12029 if (is_space_char (*s
))
12031 if (*s
>= '0' && *s
<= '7')
12033 int fpr
= *s
- '0';
12035 if (is_space_char (*s
))
12040 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12045 /* We have "%st(" then garbage. */
12046 return (const reg_entry
*) NULL
;
12050 if (r
== NULL
|| allow_pseudo_reg
)
12053 if (operand_type_all_zero (&r
->reg_type
))
12054 return (const reg_entry
*) NULL
;
12056 if ((r
->reg_type
.bitfield
.dword
12057 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12058 || r
->reg_type
.bitfield
.class == RegCR
12059 || r
->reg_type
.bitfield
.class == RegDR
12060 || r
->reg_type
.bitfield
.class == RegTR
)
12061 && !cpu_arch_flags
.bitfield
.cpui386
)
12062 return (const reg_entry
*) NULL
;
12064 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12065 return (const reg_entry
*) NULL
;
12067 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12069 if (r
->reg_type
.bitfield
.zmmword
12070 || r
->reg_type
.bitfield
.class == RegMask
)
12071 return (const reg_entry
*) NULL
;
12073 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12075 if (r
->reg_type
.bitfield
.ymmword
)
12076 return (const reg_entry
*) NULL
;
12078 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12079 return (const reg_entry
*) NULL
;
12083 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12084 return (const reg_entry
*) NULL
;
12086 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12087 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12088 return (const reg_entry
*) NULL
;
12090 /* Upper 16 vector registers are only available with VREX in 64bit
12091 mode, and require EVEX encoding. */
12092 if (r
->reg_flags
& RegVRex
)
12094 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12095 || flag_code
!= CODE_64BIT
)
12096 return (const reg_entry
*) NULL
;
12098 i
.vec_encoding
= vex_encoding_evex
;
12101 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12102 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12103 && flag_code
!= CODE_64BIT
)
12104 return (const reg_entry
*) NULL
;
12106 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12108 return (const reg_entry
*) NULL
;
12113 /* REG_STRING starts *before* REGISTER_PREFIX. */
12115 static const reg_entry
*
12116 parse_register (char *reg_string
, char **end_op
)
12118 const reg_entry
*r
;
12120 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12121 r
= parse_real_register (reg_string
, end_op
);
12126 char *save
= input_line_pointer
;
12130 input_line_pointer
= reg_string
;
12131 c
= get_symbol_name (®_string
);
12132 symbolP
= symbol_find (reg_string
);
12133 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12135 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12137 know (e
->X_op
== O_register
);
12138 know (e
->X_add_number
>= 0
12139 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12140 r
= i386_regtab
+ e
->X_add_number
;
12141 if ((r
->reg_flags
& RegVRex
))
12142 i
.vec_encoding
= vex_encoding_evex
;
12143 *end_op
= input_line_pointer
;
12145 *input_line_pointer
= c
;
12146 input_line_pointer
= save
;
12152 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12154 const reg_entry
*r
;
12155 char *end
= input_line_pointer
;
12158 r
= parse_register (name
, &input_line_pointer
);
12159 if (r
&& end
<= input_line_pointer
)
12161 *nextcharP
= *input_line_pointer
;
12162 *input_line_pointer
= 0;
12163 e
->X_op
= O_register
;
12164 e
->X_add_number
= r
- i386_regtab
;
12167 input_line_pointer
= end
;
12169 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12173 md_operand (expressionS
*e
)
12176 const reg_entry
*r
;
12178 switch (*input_line_pointer
)
12180 case REGISTER_PREFIX
:
12181 r
= parse_real_register (input_line_pointer
, &end
);
12184 e
->X_op
= O_register
;
12185 e
->X_add_number
= r
- i386_regtab
;
12186 input_line_pointer
= end
;
12191 gas_assert (intel_syntax
);
12192 end
= input_line_pointer
++;
12194 if (*input_line_pointer
== ']')
12196 ++input_line_pointer
;
12197 e
->X_op_symbol
= make_expr_symbol (e
);
12198 e
->X_add_symbol
= NULL
;
12199 e
->X_add_number
= 0;
12204 e
->X_op
= O_absent
;
12205 input_line_pointer
= end
;
12212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12213 const char *md_shortopts
= "kVQ:sqnO::";
12215 const char *md_shortopts
= "qnO::";
12218 #define OPTION_32 (OPTION_MD_BASE + 0)
12219 #define OPTION_64 (OPTION_MD_BASE + 1)
12220 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12221 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12222 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12223 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12224 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12225 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12226 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12227 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12228 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12229 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12230 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12231 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12232 #define OPTION_X32 (OPTION_MD_BASE + 14)
12233 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12234 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12235 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12236 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12237 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12238 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12239 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12240 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12241 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12242 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12243 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12244 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12245 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12246 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12247 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12248 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12250 struct option md_longopts
[] =
12252 {"32", no_argument
, NULL
, OPTION_32
},
12253 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12254 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12255 {"64", no_argument
, NULL
, OPTION_64
},
12257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12258 {"x32", no_argument
, NULL
, OPTION_X32
},
12259 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12260 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12262 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12263 {"march", required_argument
, NULL
, OPTION_MARCH
},
12264 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12265 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12266 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12267 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12268 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12269 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12270 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12271 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12272 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12273 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12274 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12275 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12276 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12277 # if defined (TE_PE) || defined (TE_PEP)
12278 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12280 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12281 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12282 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12283 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12284 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12285 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12286 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12287 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12288 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12289 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12290 {NULL
, no_argument
, NULL
, 0}
12292 size_t md_longopts_size
= sizeof (md_longopts
);
12295 md_parse_option (int c
, const char *arg
)
12298 char *arch
, *next
, *saved
, *type
;
12303 optimize_align_code
= 0;
12307 quiet_warnings
= 1;
12310 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12311 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12312 should be emitted or not. FIXME: Not implemented. */
12314 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12318 /* -V: SVR4 argument to print version ID. */
12320 print_version_id ();
12323 /* -k: Ignore for FreeBSD compatibility. */
12328 /* -s: On i386 Solaris, this tells the native assembler to use
12329 .stab instead of .stab.excl. We always use .stab anyhow. */
12332 case OPTION_MSHARED
:
12336 case OPTION_X86_USED_NOTE
:
12337 if (strcasecmp (arg
, "yes") == 0)
12339 else if (strcasecmp (arg
, "no") == 0)
12342 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12347 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12348 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12351 const char **list
, **l
;
12353 list
= bfd_target_list ();
12354 for (l
= list
; *l
!= NULL
; l
++)
12355 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12356 || strcmp (*l
, "coff-x86-64") == 0
12357 || strcmp (*l
, "pe-x86-64") == 0
12358 || strcmp (*l
, "pei-x86-64") == 0
12359 || strcmp (*l
, "mach-o-x86-64") == 0)
12361 default_arch
= "x86_64";
12365 as_fatal (_("no compiled in support for x86_64"));
12371 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12375 const char **list
, **l
;
12377 list
= bfd_target_list ();
12378 for (l
= list
; *l
!= NULL
; l
++)
12379 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12381 default_arch
= "x86_64:32";
12385 as_fatal (_("no compiled in support for 32bit x86_64"));
12389 as_fatal (_("32bit x86_64 is only supported for ELF"));
12394 default_arch
= "i386";
12397 case OPTION_DIVIDE
:
12398 #ifdef SVR4_COMMENT_CHARS
12403 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12405 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12409 i386_comment_chars
= n
;
12415 saved
= xstrdup (arg
);
12417 /* Allow -march=+nosse. */
12423 as_fatal (_("invalid -march= option: `%s'"), arg
);
12424 next
= strchr (arch
, '+');
12427 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12429 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12432 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12435 cpu_arch_name
= cpu_arch
[j
].name
;
12436 cpu_sub_arch_name
= NULL
;
12437 cpu_arch_flags
= cpu_arch
[j
].flags
;
12438 cpu_arch_isa
= cpu_arch
[j
].type
;
12439 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12440 if (!cpu_arch_tune_set
)
12442 cpu_arch_tune
= cpu_arch_isa
;
12443 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12447 else if (*cpu_arch
[j
].name
== '.'
12448 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12450 /* ISA extension. */
12451 i386_cpu_flags flags
;
12453 flags
= cpu_flags_or (cpu_arch_flags
,
12454 cpu_arch
[j
].flags
);
12456 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12458 if (cpu_sub_arch_name
)
12460 char *name
= cpu_sub_arch_name
;
12461 cpu_sub_arch_name
= concat (name
,
12463 (const char *) NULL
);
12467 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12468 cpu_arch_flags
= flags
;
12469 cpu_arch_isa_flags
= flags
;
12473 = cpu_flags_or (cpu_arch_isa_flags
,
12474 cpu_arch
[j
].flags
);
12479 if (j
>= ARRAY_SIZE (cpu_arch
))
12481 /* Disable an ISA extension. */
12482 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12483 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12485 i386_cpu_flags flags
;
12487 flags
= cpu_flags_and_not (cpu_arch_flags
,
12488 cpu_noarch
[j
].flags
);
12489 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12491 if (cpu_sub_arch_name
)
12493 char *name
= cpu_sub_arch_name
;
12494 cpu_sub_arch_name
= concat (arch
,
12495 (const char *) NULL
);
12499 cpu_sub_arch_name
= xstrdup (arch
);
12500 cpu_arch_flags
= flags
;
12501 cpu_arch_isa_flags
= flags
;
12506 if (j
>= ARRAY_SIZE (cpu_noarch
))
12507 j
= ARRAY_SIZE (cpu_arch
);
12510 if (j
>= ARRAY_SIZE (cpu_arch
))
12511 as_fatal (_("invalid -march= option: `%s'"), arg
);
12515 while (next
!= NULL
);
12521 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12522 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12524 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12526 cpu_arch_tune_set
= 1;
12527 cpu_arch_tune
= cpu_arch
[j
].type
;
12528 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12532 if (j
>= ARRAY_SIZE (cpu_arch
))
12533 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12536 case OPTION_MMNEMONIC
:
12537 if (strcasecmp (arg
, "att") == 0)
12538 intel_mnemonic
= 0;
12539 else if (strcasecmp (arg
, "intel") == 0)
12540 intel_mnemonic
= 1;
12542 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12545 case OPTION_MSYNTAX
:
12546 if (strcasecmp (arg
, "att") == 0)
12548 else if (strcasecmp (arg
, "intel") == 0)
12551 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12554 case OPTION_MINDEX_REG
:
12555 allow_index_reg
= 1;
12558 case OPTION_MNAKED_REG
:
12559 allow_naked_reg
= 1;
12562 case OPTION_MSSE2AVX
:
12566 case OPTION_MSSE_CHECK
:
12567 if (strcasecmp (arg
, "error") == 0)
12568 sse_check
= check_error
;
12569 else if (strcasecmp (arg
, "warning") == 0)
12570 sse_check
= check_warning
;
12571 else if (strcasecmp (arg
, "none") == 0)
12572 sse_check
= check_none
;
12574 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12577 case OPTION_MOPERAND_CHECK
:
12578 if (strcasecmp (arg
, "error") == 0)
12579 operand_check
= check_error
;
12580 else if (strcasecmp (arg
, "warning") == 0)
12581 operand_check
= check_warning
;
12582 else if (strcasecmp (arg
, "none") == 0)
12583 operand_check
= check_none
;
12585 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12588 case OPTION_MAVXSCALAR
:
12589 if (strcasecmp (arg
, "128") == 0)
12590 avxscalar
= vex128
;
12591 else if (strcasecmp (arg
, "256") == 0)
12592 avxscalar
= vex256
;
12594 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12597 case OPTION_MVEXWIG
:
12598 if (strcmp (arg
, "0") == 0)
12600 else if (strcmp (arg
, "1") == 0)
12603 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12606 case OPTION_MADD_BND_PREFIX
:
12607 add_bnd_prefix
= 1;
12610 case OPTION_MEVEXLIG
:
12611 if (strcmp (arg
, "128") == 0)
12612 evexlig
= evexl128
;
12613 else if (strcmp (arg
, "256") == 0)
12614 evexlig
= evexl256
;
12615 else if (strcmp (arg
, "512") == 0)
12616 evexlig
= evexl512
;
12618 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12621 case OPTION_MEVEXRCIG
:
12622 if (strcmp (arg
, "rne") == 0)
12624 else if (strcmp (arg
, "rd") == 0)
12626 else if (strcmp (arg
, "ru") == 0)
12628 else if (strcmp (arg
, "rz") == 0)
12631 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12634 case OPTION_MEVEXWIG
:
12635 if (strcmp (arg
, "0") == 0)
12637 else if (strcmp (arg
, "1") == 0)
12640 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12643 # if defined (TE_PE) || defined (TE_PEP)
12644 case OPTION_MBIG_OBJ
:
12649 case OPTION_MOMIT_LOCK_PREFIX
:
12650 if (strcasecmp (arg
, "yes") == 0)
12651 omit_lock_prefix
= 1;
12652 else if (strcasecmp (arg
, "no") == 0)
12653 omit_lock_prefix
= 0;
12655 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12658 case OPTION_MFENCE_AS_LOCK_ADD
:
12659 if (strcasecmp (arg
, "yes") == 0)
12661 else if (strcasecmp (arg
, "no") == 0)
12664 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12667 case OPTION_MRELAX_RELOCATIONS
:
12668 if (strcasecmp (arg
, "yes") == 0)
12669 generate_relax_relocations
= 1;
12670 else if (strcasecmp (arg
, "no") == 0)
12671 generate_relax_relocations
= 0;
12673 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12676 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12679 long int align
= strtoul (arg
, &end
, 0);
12684 align_branch_power
= 0;
12687 else if (align
>= 16)
12690 for (align_power
= 0;
12692 align
>>= 1, align_power
++)
12694 /* Limit alignment power to 31. */
12695 if (align
== 1 && align_power
< 32)
12697 align_branch_power
= align_power
;
12702 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12706 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12709 int align
= strtoul (arg
, &end
, 0);
12710 /* Some processors only support 5 prefixes. */
12711 if (*end
== '\0' && align
>= 0 && align
< 6)
12713 align_branch_prefix_size
= align
;
12716 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12721 case OPTION_MALIGN_BRANCH
:
12723 saved
= xstrdup (arg
);
12727 next
= strchr (type
, '+');
12730 if (strcasecmp (type
, "jcc") == 0)
12731 align_branch
|= align_branch_jcc_bit
;
12732 else if (strcasecmp (type
, "fused") == 0)
12733 align_branch
|= align_branch_fused_bit
;
12734 else if (strcasecmp (type
, "jmp") == 0)
12735 align_branch
|= align_branch_jmp_bit
;
12736 else if (strcasecmp (type
, "call") == 0)
12737 align_branch
|= align_branch_call_bit
;
12738 else if (strcasecmp (type
, "ret") == 0)
12739 align_branch
|= align_branch_ret_bit
;
12740 else if (strcasecmp (type
, "indirect") == 0)
12741 align_branch
|= align_branch_indirect_bit
;
12743 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12746 while (next
!= NULL
);
12750 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12751 align_branch_power
= 5;
12752 align_branch_prefix_size
= 5;
12753 align_branch
= (align_branch_jcc_bit
12754 | align_branch_fused_bit
12755 | align_branch_jmp_bit
);
12758 case OPTION_MAMD64
:
12762 case OPTION_MINTEL64
:
12770 /* Turn off -Os. */
12771 optimize_for_space
= 0;
12773 else if (*arg
== 's')
12775 optimize_for_space
= 1;
12776 /* Turn on all encoding optimizations. */
12777 optimize
= INT_MAX
;
12781 optimize
= atoi (arg
);
12782 /* Turn off -Os. */
12783 optimize_for_space
= 0;
12793 #define MESSAGE_TEMPLATE \
12797 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12798 int *left_p
, const char *name
, int len
)
12800 int size
= sizeof (MESSAGE_TEMPLATE
);
12801 int left
= *left_p
;
12803 /* Reserve 2 spaces for ", " or ",\0" */
12806 /* Check if there is any room. */
12814 p
= mempcpy (p
, name
, len
);
12818 /* Output the current message now and start a new one. */
12821 fprintf (stream
, "%s\n", message
);
12823 left
= size
- (start
- message
) - len
- 2;
12825 gas_assert (left
>= 0);
12827 p
= mempcpy (p
, name
, len
);
12835 show_arch (FILE *stream
, int ext
, int check
)
12837 static char message
[] = MESSAGE_TEMPLATE
;
12838 char *start
= message
+ 27;
12840 int size
= sizeof (MESSAGE_TEMPLATE
);
12847 left
= size
- (start
- message
);
12848 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12850 /* Should it be skipped? */
12851 if (cpu_arch
[j
].skip
)
12854 name
= cpu_arch
[j
].name
;
12855 len
= cpu_arch
[j
].len
;
12858 /* It is an extension. Skip if we aren't asked to show it. */
12869 /* It is an processor. Skip if we show only extension. */
12872 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12874 /* It is an impossible processor - skip. */
12878 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12881 /* Display disabled extensions. */
12883 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12885 name
= cpu_noarch
[j
].name
;
12886 len
= cpu_noarch
[j
].len
;
12887 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12892 fprintf (stream
, "%s\n", message
);
12896 md_show_usage (FILE *stream
)
12898 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12899 fprintf (stream
, _("\
12900 -Qy, -Qn ignored\n\
12901 -V print assembler version number\n\
12904 fprintf (stream
, _("\
12905 -n Do not optimize code alignment\n\
12906 -q quieten some warnings\n"));
12907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12908 fprintf (stream
, _("\
12911 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12912 || defined (TE_PE) || defined (TE_PEP))
12913 fprintf (stream
, _("\
12914 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12916 #ifdef SVR4_COMMENT_CHARS
12917 fprintf (stream
, _("\
12918 --divide do not treat `/' as a comment character\n"));
12920 fprintf (stream
, _("\
12921 --divide ignored\n"));
12923 fprintf (stream
, _("\
12924 -march=CPU[,+EXTENSION...]\n\
12925 generate code for CPU and EXTENSION, CPU is one of:\n"));
12926 show_arch (stream
, 0, 1);
12927 fprintf (stream
, _("\
12928 EXTENSION is combination of:\n"));
12929 show_arch (stream
, 1, 0);
12930 fprintf (stream
, _("\
12931 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12932 show_arch (stream
, 0, 0);
12933 fprintf (stream
, _("\
12934 -msse2avx encode SSE instructions with VEX prefix\n"));
12935 fprintf (stream
, _("\
12936 -msse-check=[none|error|warning] (default: warning)\n\
12937 check SSE instructions\n"));
12938 fprintf (stream
, _("\
12939 -moperand-check=[none|error|warning] (default: warning)\n\
12940 check operand combinations for validity\n"));
12941 fprintf (stream
, _("\
12942 -mavxscalar=[128|256] (default: 128)\n\
12943 encode scalar AVX instructions with specific vector\n\
12945 fprintf (stream
, _("\
12946 -mvexwig=[0|1] (default: 0)\n\
12947 encode VEX instructions with specific VEX.W value\n\
12948 for VEX.W bit ignored instructions\n"));
12949 fprintf (stream
, _("\
12950 -mevexlig=[128|256|512] (default: 128)\n\
12951 encode scalar EVEX instructions with specific vector\n\
12953 fprintf (stream
, _("\
12954 -mevexwig=[0|1] (default: 0)\n\
12955 encode EVEX instructions with specific EVEX.W value\n\
12956 for EVEX.W bit ignored instructions\n"));
12957 fprintf (stream
, _("\
12958 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12959 encode EVEX instructions with specific EVEX.RC value\n\
12960 for SAE-only ignored instructions\n"));
12961 fprintf (stream
, _("\
12962 -mmnemonic=[att|intel] "));
12963 if (SYSV386_COMPAT
)
12964 fprintf (stream
, _("(default: att)\n"));
12966 fprintf (stream
, _("(default: intel)\n"));
12967 fprintf (stream
, _("\
12968 use AT&T/Intel mnemonic\n"));
12969 fprintf (stream
, _("\
12970 -msyntax=[att|intel] (default: att)\n\
12971 use AT&T/Intel syntax\n"));
12972 fprintf (stream
, _("\
12973 -mindex-reg support pseudo index registers\n"));
12974 fprintf (stream
, _("\
12975 -mnaked-reg don't require `%%' prefix for registers\n"));
12976 fprintf (stream
, _("\
12977 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12979 fprintf (stream
, _("\
12980 -mshared disable branch optimization for shared code\n"));
12981 fprintf (stream
, _("\
12982 -mx86-used-note=[no|yes] "));
12983 if (DEFAULT_X86_USED_NOTE
)
12984 fprintf (stream
, _("(default: yes)\n"));
12986 fprintf (stream
, _("(default: no)\n"));
12987 fprintf (stream
, _("\
12988 generate x86 used ISA and feature properties\n"));
12990 #if defined (TE_PE) || defined (TE_PEP)
12991 fprintf (stream
, _("\
12992 -mbig-obj generate big object files\n"));
12994 fprintf (stream
, _("\
12995 -momit-lock-prefix=[no|yes] (default: no)\n\
12996 strip all lock prefixes\n"));
12997 fprintf (stream
, _("\
12998 -mfence-as-lock-add=[no|yes] (default: no)\n\
12999 encode lfence, mfence and sfence as\n\
13000 lock addl $0x0, (%%{re}sp)\n"));
13001 fprintf (stream
, _("\
13002 -mrelax-relocations=[no|yes] "));
13003 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13004 fprintf (stream
, _("(default: yes)\n"));
13006 fprintf (stream
, _("(default: no)\n"));
13007 fprintf (stream
, _("\
13008 generate relax relocations\n"));
13009 fprintf (stream
, _("\
13010 -malign-branch-boundary=NUM (default: 0)\n\
13011 align branches within NUM byte boundary\n"));
13012 fprintf (stream
, _("\
13013 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13014 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13016 specify types of branches to align\n"));
13017 fprintf (stream
, _("\
13018 -malign-branch-prefix-size=NUM (default: 5)\n\
13019 align branches with NUM prefixes per instruction\n"));
13020 fprintf (stream
, _("\
13021 -mbranches-within-32B-boundaries\n\
13022 align branches within 32 byte boundary\n"));
13023 fprintf (stream
, _("\
13024 -mamd64 accept only AMD64 ISA [default]\n"));
13025 fprintf (stream
, _("\
13026 -mintel64 accept only Intel64 ISA\n"));
13029 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13030 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13031 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13033 /* Pick the target format to use. */
13036 i386_target_format (void)
13038 if (!strncmp (default_arch
, "x86_64", 6))
13040 update_code_flag (CODE_64BIT
, 1);
13041 if (default_arch
[6] == '\0')
13042 x86_elf_abi
= X86_64_ABI
;
13044 x86_elf_abi
= X86_64_X32_ABI
;
13046 else if (!strcmp (default_arch
, "i386"))
13047 update_code_flag (CODE_32BIT
, 1);
13048 else if (!strcmp (default_arch
, "iamcu"))
13050 update_code_flag (CODE_32BIT
, 1);
13051 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13053 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13054 cpu_arch_name
= "iamcu";
13055 cpu_sub_arch_name
= NULL
;
13056 cpu_arch_flags
= iamcu_flags
;
13057 cpu_arch_isa
= PROCESSOR_IAMCU
;
13058 cpu_arch_isa_flags
= iamcu_flags
;
13059 if (!cpu_arch_tune_set
)
13061 cpu_arch_tune
= cpu_arch_isa
;
13062 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13065 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13066 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13070 as_fatal (_("unknown architecture"));
13072 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13073 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13074 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13075 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13077 switch (OUTPUT_FLAVOR
)
13079 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13080 case bfd_target_aout_flavour
:
13081 return AOUT_TARGET_FORMAT
;
13083 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13084 # if defined (TE_PE) || defined (TE_PEP)
13085 case bfd_target_coff_flavour
:
13086 if (flag_code
== CODE_64BIT
)
13087 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13090 # elif defined (TE_GO32)
13091 case bfd_target_coff_flavour
:
13092 return "coff-go32";
13094 case bfd_target_coff_flavour
:
13095 return "coff-i386";
13098 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13099 case bfd_target_elf_flavour
:
13101 const char *format
;
13103 switch (x86_elf_abi
)
13106 format
= ELF_TARGET_FORMAT
;
13108 tls_get_addr
= "___tls_get_addr";
13112 use_rela_relocations
= 1;
13115 tls_get_addr
= "__tls_get_addr";
13117 format
= ELF_TARGET_FORMAT64
;
13119 case X86_64_X32_ABI
:
13120 use_rela_relocations
= 1;
13123 tls_get_addr
= "__tls_get_addr";
13125 disallow_64bit_reloc
= 1;
13126 format
= ELF_TARGET_FORMAT32
;
13129 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13131 if (x86_elf_abi
!= X86_64_ABI
)
13132 as_fatal (_("Intel L1OM is 64bit only"));
13133 return ELF_TARGET_L1OM_FORMAT
;
13135 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13137 if (x86_elf_abi
!= X86_64_ABI
)
13138 as_fatal (_("Intel K1OM is 64bit only"));
13139 return ELF_TARGET_K1OM_FORMAT
;
13141 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13143 if (x86_elf_abi
!= I386_ABI
)
13144 as_fatal (_("Intel MCU is 32bit only"));
13145 return ELF_TARGET_IAMCU_FORMAT
;
13151 #if defined (OBJ_MACH_O)
13152 case bfd_target_mach_o_flavour
:
13153 if (flag_code
== CODE_64BIT
)
13155 use_rela_relocations
= 1;
13157 return "mach-o-x86-64";
13160 return "mach-o-i386";
13168 #endif /* OBJ_MAYBE_ more than one */
13171 md_undefined_symbol (char *name
)
13173 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13174 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13175 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13176 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13180 if (symbol_find (name
))
13181 as_bad (_("GOT already in symbol table"));
13182 GOT_symbol
= symbol_new (name
, undefined_section
,
13183 (valueT
) 0, &zero_address_frag
);
13190 /* Round up a section size to the appropriate boundary. */
13193 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13195 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13196 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13198 /* For a.out, force the section size to be aligned. If we don't do
13199 this, BFD will align it for us, but it will not write out the
13200 final bytes of the section. This may be a bug in BFD, but it is
13201 easier to fix it here since that is how the other a.out targets
13205 align
= bfd_section_alignment (segment
);
13206 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13213 /* On the i386, PC-relative offsets are relative to the start of the
13214 next instruction. That is, the address of the offset, plus its
13215 size, since the offset is always the last part of the insn. */
13218 md_pcrel_from (fixS
*fixP
)
13220 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13226 s_bss (int ignore ATTRIBUTE_UNUSED
)
13230 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13232 obj_elf_section_change_hook ();
13234 temp
= get_absolute_expression ();
13235 subseg_set (bss_section
, (subsegT
) temp
);
13236 demand_empty_rest_of_line ();
13241 /* Remember constant directive. */
13244 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13246 if (last_insn
.kind
!= last_insn_directive
13247 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13249 last_insn
.seg
= now_seg
;
13250 last_insn
.kind
= last_insn_directive
;
13251 last_insn
.name
= "constant directive";
13252 last_insn
.file
= as_where (&last_insn
.line
);
13257 i386_validate_fix (fixS
*fixp
)
13259 if (fixp
->fx_subsy
)
13261 if (fixp
->fx_subsy
== GOT_symbol
)
13263 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13268 if (fixp
->fx_tcbit2
)
13269 fixp
->fx_r_type
= (fixp
->fx_tcbit
13270 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13271 : BFD_RELOC_X86_64_GOTPCRELX
);
13274 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13279 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13281 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13283 fixp
->fx_subsy
= 0;
13286 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13287 else if (!object_64bit
)
13289 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13290 && fixp
->fx_tcbit2
)
13291 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13297 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13300 bfd_reloc_code_real_type code
;
13302 switch (fixp
->fx_r_type
)
13304 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13305 case BFD_RELOC_SIZE32
:
13306 case BFD_RELOC_SIZE64
:
13307 if (S_IS_DEFINED (fixp
->fx_addsy
)
13308 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13310 /* Resolve size relocation against local symbol to size of
13311 the symbol plus addend. */
13312 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13313 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13314 && !fits_in_unsigned_long (value
))
13315 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13316 _("symbol size computation overflow"));
13317 fixp
->fx_addsy
= NULL
;
13318 fixp
->fx_subsy
= NULL
;
13319 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13323 /* Fall through. */
13325 case BFD_RELOC_X86_64_PLT32
:
13326 case BFD_RELOC_X86_64_GOT32
:
13327 case BFD_RELOC_X86_64_GOTPCREL
:
13328 case BFD_RELOC_X86_64_GOTPCRELX
:
13329 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13330 case BFD_RELOC_386_PLT32
:
13331 case BFD_RELOC_386_GOT32
:
13332 case BFD_RELOC_386_GOT32X
:
13333 case BFD_RELOC_386_GOTOFF
:
13334 case BFD_RELOC_386_GOTPC
:
13335 case BFD_RELOC_386_TLS_GD
:
13336 case BFD_RELOC_386_TLS_LDM
:
13337 case BFD_RELOC_386_TLS_LDO_32
:
13338 case BFD_RELOC_386_TLS_IE_32
:
13339 case BFD_RELOC_386_TLS_IE
:
13340 case BFD_RELOC_386_TLS_GOTIE
:
13341 case BFD_RELOC_386_TLS_LE_32
:
13342 case BFD_RELOC_386_TLS_LE
:
13343 case BFD_RELOC_386_TLS_GOTDESC
:
13344 case BFD_RELOC_386_TLS_DESC_CALL
:
13345 case BFD_RELOC_X86_64_TLSGD
:
13346 case BFD_RELOC_X86_64_TLSLD
:
13347 case BFD_RELOC_X86_64_DTPOFF32
:
13348 case BFD_RELOC_X86_64_DTPOFF64
:
13349 case BFD_RELOC_X86_64_GOTTPOFF
:
13350 case BFD_RELOC_X86_64_TPOFF32
:
13351 case BFD_RELOC_X86_64_TPOFF64
:
13352 case BFD_RELOC_X86_64_GOTOFF64
:
13353 case BFD_RELOC_X86_64_GOTPC32
:
13354 case BFD_RELOC_X86_64_GOT64
:
13355 case BFD_RELOC_X86_64_GOTPCREL64
:
13356 case BFD_RELOC_X86_64_GOTPC64
:
13357 case BFD_RELOC_X86_64_GOTPLT64
:
13358 case BFD_RELOC_X86_64_PLTOFF64
:
13359 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13360 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13361 case BFD_RELOC_RVA
:
13362 case BFD_RELOC_VTABLE_ENTRY
:
13363 case BFD_RELOC_VTABLE_INHERIT
:
13365 case BFD_RELOC_32_SECREL
:
13367 code
= fixp
->fx_r_type
;
13369 case BFD_RELOC_X86_64_32S
:
13370 if (!fixp
->fx_pcrel
)
13372 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13373 code
= fixp
->fx_r_type
;
13376 /* Fall through. */
13378 if (fixp
->fx_pcrel
)
13380 switch (fixp
->fx_size
)
13383 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13384 _("can not do %d byte pc-relative relocation"),
13386 code
= BFD_RELOC_32_PCREL
;
13388 case 1: code
= BFD_RELOC_8_PCREL
; break;
13389 case 2: code
= BFD_RELOC_16_PCREL
; break;
13390 case 4: code
= BFD_RELOC_32_PCREL
; break;
13392 case 8: code
= BFD_RELOC_64_PCREL
; break;
13398 switch (fixp
->fx_size
)
13401 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13402 _("can not do %d byte relocation"),
13404 code
= BFD_RELOC_32
;
13406 case 1: code
= BFD_RELOC_8
; break;
13407 case 2: code
= BFD_RELOC_16
; break;
13408 case 4: code
= BFD_RELOC_32
; break;
13410 case 8: code
= BFD_RELOC_64
; break;
13417 if ((code
== BFD_RELOC_32
13418 || code
== BFD_RELOC_32_PCREL
13419 || code
== BFD_RELOC_X86_64_32S
)
13421 && fixp
->fx_addsy
== GOT_symbol
)
13424 code
= BFD_RELOC_386_GOTPC
;
13426 code
= BFD_RELOC_X86_64_GOTPC32
;
13428 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13430 && fixp
->fx_addsy
== GOT_symbol
)
13432 code
= BFD_RELOC_X86_64_GOTPC64
;
13435 rel
= XNEW (arelent
);
13436 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13437 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13439 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13441 if (!use_rela_relocations
)
13443 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13444 vtable entry to be used in the relocation's section offset. */
13445 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13446 rel
->address
= fixp
->fx_offset
;
13447 #if defined (OBJ_COFF) && defined (TE_PE)
13448 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13449 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13454 /* Use the rela in 64bit mode. */
13457 if (disallow_64bit_reloc
)
13460 case BFD_RELOC_X86_64_DTPOFF64
:
13461 case BFD_RELOC_X86_64_TPOFF64
:
13462 case BFD_RELOC_64_PCREL
:
13463 case BFD_RELOC_X86_64_GOTOFF64
:
13464 case BFD_RELOC_X86_64_GOT64
:
13465 case BFD_RELOC_X86_64_GOTPCREL64
:
13466 case BFD_RELOC_X86_64_GOTPC64
:
13467 case BFD_RELOC_X86_64_GOTPLT64
:
13468 case BFD_RELOC_X86_64_PLTOFF64
:
13469 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13470 _("cannot represent relocation type %s in x32 mode"),
13471 bfd_get_reloc_code_name (code
));
13477 if (!fixp
->fx_pcrel
)
13478 rel
->addend
= fixp
->fx_offset
;
13482 case BFD_RELOC_X86_64_PLT32
:
13483 case BFD_RELOC_X86_64_GOT32
:
13484 case BFD_RELOC_X86_64_GOTPCREL
:
13485 case BFD_RELOC_X86_64_GOTPCRELX
:
13486 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13487 case BFD_RELOC_X86_64_TLSGD
:
13488 case BFD_RELOC_X86_64_TLSLD
:
13489 case BFD_RELOC_X86_64_GOTTPOFF
:
13490 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13491 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13492 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13495 rel
->addend
= (section
->vma
13497 + fixp
->fx_addnumber
13498 + md_pcrel_from (fixp
));
13503 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13504 if (rel
->howto
== NULL
)
13506 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13507 _("cannot represent relocation type %s"),
13508 bfd_get_reloc_code_name (code
));
13509 /* Set howto to a garbage value so that we can keep going. */
13510 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13511 gas_assert (rel
->howto
!= NULL
);
13517 #include "tc-i386-intel.c"
13520 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13522 int saved_naked_reg
;
13523 char saved_register_dot
;
13525 saved_naked_reg
= allow_naked_reg
;
13526 allow_naked_reg
= 1;
13527 saved_register_dot
= register_chars
['.'];
13528 register_chars
['.'] = '.';
13529 allow_pseudo_reg
= 1;
13530 expression_and_evaluate (exp
);
13531 allow_pseudo_reg
= 0;
13532 register_chars
['.'] = saved_register_dot
;
13533 allow_naked_reg
= saved_naked_reg
;
13535 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13537 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13539 exp
->X_op
= O_constant
;
13540 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13541 .dw2_regnum
[flag_code
>> 1];
13544 exp
->X_op
= O_illegal
;
13549 tc_x86_frame_initial_instructions (void)
13551 static unsigned int sp_regno
[2];
13553 if (!sp_regno
[flag_code
>> 1])
13555 char *saved_input
= input_line_pointer
;
13556 char sp
[][4] = {"esp", "rsp"};
13559 input_line_pointer
= sp
[flag_code
>> 1];
13560 tc_x86_parse_to_dw2regnum (&exp
);
13561 gas_assert (exp
.X_op
== O_constant
);
13562 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13563 input_line_pointer
= saved_input
;
13566 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13567 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13571 x86_dwarf2_addr_size (void)
13573 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13574 if (x86_elf_abi
== X86_64_X32_ABI
)
13577 return bfd_arch_bits_per_address (stdoutput
) / 8;
13581 i386_elf_section_type (const char *str
, size_t len
)
13583 if (flag_code
== CODE_64BIT
13584 && len
== sizeof ("unwind") - 1
13585 && strncmp (str
, "unwind", 6) == 0)
13586 return SHT_X86_64_UNWIND
;
13593 i386_solaris_fix_up_eh_frame (segT sec
)
13595 if (flag_code
== CODE_64BIT
)
13596 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13602 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13606 exp
.X_op
= O_secrel
;
13607 exp
.X_add_symbol
= symbol
;
13608 exp
.X_add_number
= 0;
13609 emit_expr (&exp
, size
);
13613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13614 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13617 x86_64_section_letter (int letter
, const char **ptr_msg
)
13619 if (flag_code
== CODE_64BIT
)
13622 return SHF_X86_64_LARGE
;
13624 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13627 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13632 x86_64_section_word (char *str
, size_t len
)
13634 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13635 return SHF_X86_64_LARGE
;
13641 handle_large_common (int small ATTRIBUTE_UNUSED
)
13643 if (flag_code
!= CODE_64BIT
)
13645 s_comm_internal (0, elf_common_parse
);
13646 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13650 static segT lbss_section
;
13651 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13652 asection
*saved_bss_section
= bss_section
;
13654 if (lbss_section
== NULL
)
13656 flagword applicable
;
13657 segT seg
= now_seg
;
13658 subsegT subseg
= now_subseg
;
13660 /* The .lbss section is for local .largecomm symbols. */
13661 lbss_section
= subseg_new (".lbss", 0);
13662 applicable
= bfd_applicable_section_flags (stdoutput
);
13663 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13664 seg_info (lbss_section
)->bss
= 1;
13666 subseg_set (seg
, subseg
);
13669 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13670 bss_section
= lbss_section
;
13672 s_comm_internal (0, elf_common_parse
);
13674 elf_com_section_ptr
= saved_com_section_ptr
;
13675 bss_section
= saved_bss_section
;
13678 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */