1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands
;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types
[MAX_OPERANDS
];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op
[MAX_OPERANDS
];
311 /* Flags for operands. */
312 unsigned int flags
[MAX_OPERANDS
];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry
*base_reg
;
321 const reg_entry
*index_reg
;
322 unsigned int log2_scale_factor
;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry
*seg
[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes
;
334 unsigned char prefix
[MAX_PREFIXES
];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation
*mask
;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation
*rounding
;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation
*broadcast
;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift
;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default
= 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default
= 0,
372 /* How to encode vector instructions. */
375 vex_encoding_default
= 0,
382 const char *rep_prefix
;
385 const char *hle_prefix
;
387 /* Have BND prefix. */
388 const char *bnd_prefix
;
390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix
;
394 enum i386_error error
;
397 typedef struct _i386_insn i386_insn
;
399 /* Link RC type with corresponding string, that'll be looked for in
408 static const struct RC_name RC_NamesTable
[] =
410 { rne
, STRING_COMMA_LEN ("rn-sae") },
411 { rd
, STRING_COMMA_LEN ("rd-sae") },
412 { ru
, STRING_COMMA_LEN ("ru-sae") },
413 { rz
, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly
, STRING_COMMA_LEN ("sae") },
417 /* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
419 const char extra_symbol_chars
[] = "*%-([{}"
428 #if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
430 && !defined (TE_GNU) \
431 && !defined (TE_LINUX) \
432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars
= "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
445 const char *i386_comment_chars
= "#";
446 #define PREFIX_SEPARATOR '/'
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars
[] = "#/";
459 const char line_separator_chars
[] = ";";
461 /* Chars that can be used to separate mant from exp in floating point
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant
468 const char FLT_CHARS
[] = "fFdDxX";
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars
[256];
472 static char register_chars
[256];
473 static char operand_chars
[256];
474 static char identifier_chars
[256];
475 static char digit_chars
[256];
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack
[32];
493 static char *save_stack_p
;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
499 /* The instruction we're assembling. */
502 /* Possible templates for current insn. */
503 static const templates
*current_templates
;
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
507 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
509 /* Current operand we are working on. */
510 static int this_operand
= -1;
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
520 static enum flag_code flag_code
;
521 static unsigned int object_64bit
;
522 static unsigned int disallow_64bit_reloc
;
523 static int use_rela_relocations
= 0;
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529 /* The ELF ABI to use. */
537 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj
= 0;
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared
= 0;
550 /* 1 for intel syntax,
552 static int intel_syntax
= 0;
554 /* 1 for Intel64 ISA,
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic
= !SYSV386_COMPAT
;
562 /* 1 if support old (<= 2.8.1) versions of gcc. */
563 static int old_gcc
= OLDGCC_COMPAT
;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg
= 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg
= 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix
= 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg
= 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix
= 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence
= 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
592 static enum check_kind
598 sse_check
, operand_check
= check_warning
;
600 /* Register prefix used for error message. */
601 static const char *register_prefix
= "%";
603 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606 static char stackop_size
= '\0';
608 /* Non-zero to optimize code alignment. */
609 int optimize_align_code
= 1;
611 /* Non-zero to quieten some warnings. */
612 static int quiet_warnings
= 0;
615 static const char *cpu_arch_name
= NULL
;
616 static char *cpu_sub_arch_name
= NULL
;
618 /* CPU feature flags. */
619 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
621 /* If we have selected a cpu we are generating instructions for. */
622 static int cpu_arch_tune_set
= 0;
624 /* Cpu we are generating instructions for. */
625 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
627 /* CPU feature flags of cpu we are generating instructions for. */
628 static i386_cpu_flags cpu_arch_tune_flags
;
630 /* CPU instruction set architecture used. */
631 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
633 /* CPU feature flags of instruction set architecture used. */
634 i386_cpu_flags cpu_arch_isa_flags
;
636 /* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638 static unsigned int no_cond_jump_promotion
= 0;
640 /* Encode SSE instructions with VEX prefix. */
641 static unsigned int sse2avx
;
643 /* Encode scalar AVX instructions with specific vector length. */
650 /* Encode scalar EVEX LIG instructions with specific vector length. */
658 /* Encode EVEX WIG instructions with specific evex.w. */
665 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
666 static enum rc_type evexrcig
= rne
;
668 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
669 static symbolS
*GOT_symbol
;
671 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
672 unsigned int x86_dwarf2_return_column
;
674 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675 int x86_cie_data_alignment
;
677 /* Interface to relax_segment.
678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
683 #define UNCOND_JUMP 0
685 #define COND_JUMP86 2
690 #define SMALL16 (SMALL | CODE16)
692 #define BIG16 (BIG | CODE16)
696 #define INLINE __inline__
702 #define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704 #define TYPE_FROM_RELAX_STATE(s) \
706 #define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
709 /* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
717 const relax_typeS md_relax_table
[] =
720 1) most positive reach of this state,
721 2) most negative reach of this state,
722 3) how many bytes this mode will have in the variable part of the frag
723 4) which index into the table to try if we can't fit into this one. */
725 /* UNCOND_JUMP states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
741 /* word conditionals add 3 bytes to frag:
742 1 extra opcode byte, 2 displacement bytes. */
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
756 static const arch_entry cpu_arch
[] =
758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
761 CPU_GENERIC32_FLAGS
, 0 },
762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
763 CPU_GENERIC64_FLAGS
, 0 },
764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
781 CPU_PENTIUMPRO_FLAGS
, 0 },
782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
791 CPU_NOCONA_FLAGS
, 0 },
792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
797 CPU_CORE2_FLAGS
, 1 },
798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
799 CPU_CORE2_FLAGS
, 0 },
800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
801 CPU_COREI7_FLAGS
, 0 },
802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
807 CPU_IAMCU_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
813 CPU_ATHLON_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
821 CPU_AMDFAM10_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
823 CPU_BDVER1_FLAGS
, 0 },
824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
825 CPU_BDVER2_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
827 CPU_BDVER3_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
829 CPU_BDVER4_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
831 CPU_ZNVER1_FLAGS
, 0 },
832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
833 CPU_BTVER1_FLAGS
, 0 },
834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
835 CPU_BTVER2_FLAGS
, 0 },
836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
853 CPU_SSSE3_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
855 CPU_SSE4_1_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
857 CPU_SSE4_2_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
859 CPU_SSE4_2_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
865 CPU_AVX512F_FLAGS
, 0 },
866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
867 CPU_AVX512CD_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
869 CPU_AVX512ER_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
871 CPU_AVX512PF_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
873 CPU_AVX512DQ_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
875 CPU_AVX512BW_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
877 CPU_AVX512VL_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
881 CPU_VMFUNC_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
885 CPU_XSAVE_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
887 CPU_XSAVEOPT_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
889 CPU_XSAVEC_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
891 CPU_XSAVES_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
895 CPU_PCLMUL_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
897 CPU_PCLMUL_FLAGS
, 1 },
898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
899 CPU_FSGSBASE_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
901 CPU_RDRND_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
915 CPU_MOVBE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
921 CPU_LZCNT_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
927 CPU_INVPCID_FLAGS
, 0 },
928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
929 CPU_CLFLUSH_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
933 CPU_SYSCALL_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
935 CPU_RDTSCP_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
937 CPU_3DNOW_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
939 CPU_3DNOWA_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
941 CPU_PADLOCK_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
947 CPU_SSE4A_FLAGS
, 0 },
948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
957 CPU_RDSEED_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
959 CPU_PRFCHW_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
967 CPU_CLFLUSHOPT_FLAGS
, 0 },
968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
969 CPU_PREFETCHWT1_FLAGS
, 0 },
970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
975 CPU_AVX512IFMA_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
977 CPU_AVX512VBMI_FLAGS
, 0 },
978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
979 CPU_AVX512_4FMAPS_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
981 CPU_AVX512_4VNNIW_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
983 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
985 CPU_AVX512_VBMI2_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
987 CPU_AVX512_VNNI_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
989 CPU_AVX512_BITALG_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
991 CPU_CLZERO_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
993 CPU_MWAITX_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
995 CPU_OSPKE_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
997 CPU_RDPID_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
999 CPU_PTWRITE_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
1002 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1003 CPU_GFNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1005 CPU_VAES_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1007 CPU_VPCLMULQDQ_FLAGS
, 0 },
1010 static const noarch_entry cpu_noarch
[] =
1012 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1013 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1014 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1015 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1016 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1017 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1018 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1019 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1020 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1021 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1022 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1023 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1024 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1027 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1028 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1029 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1030 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1031 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1032 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1033 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1034 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1035 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1036 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1037 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1038 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1039 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1040 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1044 /* Like s_lcomm_internal in gas/read.c but the alignment string
1045 is allowed to be optional. */
1048 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1055 && *input_line_pointer
== ',')
1057 align
= parse_align (needs_align
- 1);
1059 if (align
== (addressT
) -1)
1074 bss_alloc (symbolP
, size
, align
);
1079 pe_lcomm (int needs_align
)
1081 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1085 const pseudo_typeS md_pseudo_table
[] =
1087 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1088 {"align", s_align_bytes
, 0},
1090 {"align", s_align_ptwo
, 0},
1092 {"arch", set_cpu_arch
, 0},
1096 {"lcomm", pe_lcomm
, 1},
1098 {"ffloat", float_cons
, 'f'},
1099 {"dfloat", float_cons
, 'd'},
1100 {"tfloat", float_cons
, 'x'},
1102 {"slong", signed_cons
, 4},
1103 {"noopt", s_ignore
, 0},
1104 {"optim", s_ignore
, 0},
1105 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1106 {"code16", set_code_flag
, CODE_16BIT
},
1107 {"code32", set_code_flag
, CODE_32BIT
},
1109 {"code64", set_code_flag
, CODE_64BIT
},
1111 {"intel_syntax", set_intel_syntax
, 1},
1112 {"att_syntax", set_intel_syntax
, 0},
1113 {"intel_mnemonic", set_intel_mnemonic
, 1},
1114 {"att_mnemonic", set_intel_mnemonic
, 0},
1115 {"allow_index_reg", set_allow_index_reg
, 1},
1116 {"disallow_index_reg", set_allow_index_reg
, 0},
1117 {"sse_check", set_check
, 0},
1118 {"operand_check", set_check
, 1},
1119 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1120 {"largecomm", handle_large_common
, 0},
1122 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1123 {"loc", dwarf2_directive_loc
, 0},
1124 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1127 {"secrel32", pe_directive_secrel
, 0},
1132 /* For interface with expression (). */
1133 extern char *input_line_pointer
;
1135 /* Hash table for instruction mnemonic lookup. */
1136 static struct hash_control
*op_hash
;
1138 /* Hash table for register lookup. */
1139 static struct hash_control
*reg_hash
;
1142 i386_align_code (fragS
*fragP
, int count
)
1144 /* Various efficient no-op patterns for aligning code labels.
1145 Note: Don't try to assemble the instructions in the comments.
1146 0L and 0w are not legal. */
1147 static const unsigned char f32_1
[] =
1149 static const unsigned char f32_2
[] =
1150 {0x66,0x90}; /* xchg %ax,%ax */
1151 static const unsigned char f32_3
[] =
1152 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1153 static const unsigned char f32_4
[] =
1154 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1155 static const unsigned char f32_5
[] =
1157 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1158 static const unsigned char f32_6
[] =
1159 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1160 static const unsigned char f32_7
[] =
1161 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1162 static const unsigned char f32_8
[] =
1164 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1165 static const unsigned char f32_9
[] =
1166 {0x89,0xf6, /* movl %esi,%esi */
1167 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1168 static const unsigned char f32_10
[] =
1169 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1171 static const unsigned char f32_11
[] =
1172 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1174 static const unsigned char f32_12
[] =
1175 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1176 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1177 static const unsigned char f32_13
[] =
1178 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1179 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1180 static const unsigned char f32_14
[] =
1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1182 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1183 static const unsigned char f16_3
[] =
1184 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1185 static const unsigned char f16_4
[] =
1186 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1187 static const unsigned char f16_5
[] =
1189 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1190 static const unsigned char f16_6
[] =
1191 {0x89,0xf6, /* mov %si,%si */
1192 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1193 static const unsigned char f16_7
[] =
1194 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1195 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1196 static const unsigned char f16_8
[] =
1197 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1198 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1199 static const unsigned char jump_31
[] =
1200 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1204 static const unsigned char *const f32_patt
[] = {
1205 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1206 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1208 static const unsigned char *const f16_patt
[] = {
1209 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1211 /* nopl (%[re]ax) */
1212 static const unsigned char alt_3
[] =
1214 /* nopl 0(%[re]ax) */
1215 static const unsigned char alt_4
[] =
1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_5
[] =
1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
1221 static const unsigned char alt_6
[] =
1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
1224 static const unsigned char alt_7
[] =
1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_8
[] =
1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_9
[] =
1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1233 static const unsigned char alt_10
[] =
1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 static const unsigned char *const alt_patt
[] = {
1236 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1240 /* Only align for at least a positive non-zero boundary. */
1241 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1244 /* We need to decide which NOP sequence to use for 32bit and
1245 64bit. When -mtune= is used:
1247 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1248 PROCESSOR_GENERIC32, f32_patt will be used.
1249 2. For the rest, alt_patt will be used.
1251 When -mtune= isn't used, alt_patt will be used if
1252 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1255 When -march= or .arch is used, we can't use anything beyond
1256 cpu_arch_isa_flags. */
1258 if (flag_code
== CODE_16BIT
)
1262 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1264 /* Adjust jump offset. */
1265 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1268 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1269 f16_patt
[count
- 1], count
);
1273 const unsigned char *const *patt
= NULL
;
1275 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1277 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1278 switch (cpu_arch_tune
)
1280 case PROCESSOR_UNKNOWN
:
1281 /* We use cpu_arch_isa_flags to check if we SHOULD
1282 optimize with nops. */
1283 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1288 case PROCESSOR_PENTIUM4
:
1289 case PROCESSOR_NOCONA
:
1290 case PROCESSOR_CORE
:
1291 case PROCESSOR_CORE2
:
1292 case PROCESSOR_COREI7
:
1293 case PROCESSOR_L1OM
:
1294 case PROCESSOR_K1OM
:
1295 case PROCESSOR_GENERIC64
:
1297 case PROCESSOR_ATHLON
:
1299 case PROCESSOR_AMDFAM10
:
1301 case PROCESSOR_ZNVER
:
1305 case PROCESSOR_I386
:
1306 case PROCESSOR_I486
:
1307 case PROCESSOR_PENTIUM
:
1308 case PROCESSOR_PENTIUMPRO
:
1309 case PROCESSOR_IAMCU
:
1310 case PROCESSOR_GENERIC32
:
1317 switch (fragP
->tc_frag_data
.tune
)
1319 case PROCESSOR_UNKNOWN
:
1320 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1321 PROCESSOR_UNKNOWN. */
1325 case PROCESSOR_I386
:
1326 case PROCESSOR_I486
:
1327 case PROCESSOR_PENTIUM
:
1328 case PROCESSOR_IAMCU
:
1330 case PROCESSOR_ATHLON
:
1332 case PROCESSOR_AMDFAM10
:
1334 case PROCESSOR_ZNVER
:
1336 case PROCESSOR_GENERIC32
:
1337 /* We use cpu_arch_isa_flags to check if we CAN optimize
1339 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1344 case PROCESSOR_PENTIUMPRO
:
1345 case PROCESSOR_PENTIUM4
:
1346 case PROCESSOR_NOCONA
:
1347 case PROCESSOR_CORE
:
1348 case PROCESSOR_CORE2
:
1349 case PROCESSOR_COREI7
:
1350 case PROCESSOR_L1OM
:
1351 case PROCESSOR_K1OM
:
1352 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1357 case PROCESSOR_GENERIC64
:
1363 if (patt
== f32_patt
)
1365 /* If the padding is less than 15 bytes, we use the normal
1366 ones. Otherwise, we use a jump instruction and adjust
1370 /* For 64bit, the limit is 3 bytes. */
1371 if (flag_code
== CODE_64BIT
1372 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1377 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1378 patt
[count
- 1], count
);
1381 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1383 /* Adjust jump offset. */
1384 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1389 /* Maximum length of an instruction is 10 byte. If the
1390 padding is greater than 10 bytes and we don't use jump,
1391 we have to break it into smaller pieces. */
1392 int padding
= count
;
1393 while (padding
> 10)
1396 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1401 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1402 patt
[padding
- 1], padding
);
1405 fragP
->fr_var
= count
;
1409 operand_type_all_zero (const union i386_operand_type
*x
)
1411 switch (ARRAY_SIZE(x
->array
))
1422 return !x
->array
[0];
1429 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1431 switch (ARRAY_SIZE(x
->array
))
1449 operand_type_equal (const union i386_operand_type
*x
,
1450 const union i386_operand_type
*y
)
1452 switch (ARRAY_SIZE(x
->array
))
1455 if (x
->array
[2] != y
->array
[2])
1459 if (x
->array
[1] != y
->array
[1])
1463 return x
->array
[0] == y
->array
[0];
1471 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1473 switch (ARRAY_SIZE(x
->array
))
1488 return !x
->array
[0];
1495 cpu_flags_equal (const union i386_cpu_flags
*x
,
1496 const union i386_cpu_flags
*y
)
1498 switch (ARRAY_SIZE(x
->array
))
1501 if (x
->array
[3] != y
->array
[3])
1505 if (x
->array
[2] != y
->array
[2])
1509 if (x
->array
[1] != y
->array
[1])
1513 return x
->array
[0] == y
->array
[0];
1521 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1523 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1524 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1527 static INLINE i386_cpu_flags
1528 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1530 switch (ARRAY_SIZE (x
.array
))
1533 x
.array
[3] &= y
.array
[3];
1536 x
.array
[2] &= y
.array
[2];
1539 x
.array
[1] &= y
.array
[1];
1542 x
.array
[0] &= y
.array
[0];
1550 static INLINE i386_cpu_flags
1551 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1553 switch (ARRAY_SIZE (x
.array
))
1556 x
.array
[3] |= y
.array
[3];
1559 x
.array
[2] |= y
.array
[2];
1562 x
.array
[1] |= y
.array
[1];
1565 x
.array
[0] |= y
.array
[0];
1573 static INLINE i386_cpu_flags
1574 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1576 switch (ARRAY_SIZE (x
.array
))
1579 x
.array
[3] &= ~y
.array
[3];
1582 x
.array
[2] &= ~y
.array
[2];
1585 x
.array
[1] &= ~y
.array
[1];
1588 x
.array
[0] &= ~y
.array
[0];
1596 #define CPU_FLAGS_ARCH_MATCH 0x1
1597 #define CPU_FLAGS_64BIT_MATCH 0x2
1598 #define CPU_FLAGS_AES_MATCH 0x4
1599 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1600 #define CPU_FLAGS_AVX_MATCH 0x10
1602 #define CPU_FLAGS_32BIT_MATCH \
1603 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1604 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1605 #define CPU_FLAGS_PERFECT_MATCH \
1606 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1608 /* Return CPU flags match bits. */
1611 cpu_flags_match (const insn_template
*t
)
1613 i386_cpu_flags x
= t
->cpu_flags
;
1614 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1616 x
.bitfield
.cpu64
= 0;
1617 x
.bitfield
.cpuno64
= 0;
1619 if (cpu_flags_all_zero (&x
))
1621 /* This instruction is available on all archs. */
1622 match
|= CPU_FLAGS_32BIT_MATCH
;
1626 /* This instruction is available only on some archs. */
1627 i386_cpu_flags cpu
= cpu_arch_flags
;
1629 cpu
= cpu_flags_and (x
, cpu
);
1630 if (!cpu_flags_all_zero (&cpu
))
1632 if (x
.bitfield
.cpuavx
)
1634 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1635 if (cpu
.bitfield
.cpuavx
)
1637 /* Check SSE2AVX. */
1638 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1640 match
|= (CPU_FLAGS_ARCH_MATCH
1641 | CPU_FLAGS_AVX_MATCH
);
1643 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1644 match
|= CPU_FLAGS_AES_MATCH
;
1646 if (!x
.bitfield
.cpupclmul
1647 || cpu
.bitfield
.cpupclmul
)
1648 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1652 match
|= CPU_FLAGS_ARCH_MATCH
;
1654 else if (x
.bitfield
.cpuavx512vl
)
1656 /* Match AVX512VL. */
1657 if (cpu
.bitfield
.cpuavx512vl
)
1659 /* Need another match. */
1660 cpu
.bitfield
.cpuavx512vl
= 0;
1661 if (!cpu_flags_all_zero (&cpu
))
1662 match
|= CPU_FLAGS_32BIT_MATCH
;
1664 match
|= CPU_FLAGS_ARCH_MATCH
;
1667 match
|= CPU_FLAGS_ARCH_MATCH
;
1670 match
|= CPU_FLAGS_32BIT_MATCH
;
1676 static INLINE i386_operand_type
1677 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1679 switch (ARRAY_SIZE (x
.array
))
1682 x
.array
[2] &= y
.array
[2];
1685 x
.array
[1] &= y
.array
[1];
1688 x
.array
[0] &= y
.array
[0];
1696 static INLINE i386_operand_type
1697 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1699 switch (ARRAY_SIZE (x
.array
))
1702 x
.array
[2] |= y
.array
[2];
1705 x
.array
[1] |= y
.array
[1];
1708 x
.array
[0] |= y
.array
[0];
1716 static INLINE i386_operand_type
1717 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1719 switch (ARRAY_SIZE (x
.array
))
1722 x
.array
[2] ^= y
.array
[2];
1725 x
.array
[1] ^= y
.array
[1];
1728 x
.array
[0] ^= y
.array
[0];
1736 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1737 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1738 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1739 static const i386_operand_type inoutportreg
1740 = OPERAND_TYPE_INOUTPORTREG
;
1741 static const i386_operand_type reg16_inoutportreg
1742 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1743 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1744 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1745 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1746 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1747 static const i386_operand_type anydisp
1748 = OPERAND_TYPE_ANYDISP
;
1749 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1750 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1751 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1752 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1753 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1754 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1755 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1756 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1757 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1758 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1759 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1760 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1761 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1762 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1773 operand_type_check (i386_operand_type t
, enum operand_type c
)
1778 return t
.bitfield
.reg
;
1781 return (t
.bitfield
.imm8
1785 || t
.bitfield
.imm32s
1786 || t
.bitfield
.imm64
);
1789 return (t
.bitfield
.disp8
1790 || t
.bitfield
.disp16
1791 || t
.bitfield
.disp32
1792 || t
.bitfield
.disp32s
1793 || t
.bitfield
.disp64
);
1796 return (t
.bitfield
.disp8
1797 || t
.bitfield
.disp16
1798 || t
.bitfield
.disp32
1799 || t
.bitfield
.disp32s
1800 || t
.bitfield
.disp64
1801 || t
.bitfield
.baseindex
);
1810 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1811 operand J for instruction template T. */
1814 match_reg_size (const insn_template
*t
, unsigned int j
)
1816 return !((i
.types
[j
].bitfield
.byte
1817 && !t
->operand_types
[j
].bitfield
.byte
)
1818 || (i
.types
[j
].bitfield
.word
1819 && !t
->operand_types
[j
].bitfield
.word
)
1820 || (i
.types
[j
].bitfield
.dword
1821 && !t
->operand_types
[j
].bitfield
.dword
)
1822 || (i
.types
[j
].bitfield
.qword
1823 && !t
->operand_types
[j
].bitfield
.qword
));
1826 /* Return 1 if there is no conflict in any size on operand J for
1827 instruction template T. */
1830 match_mem_size (const insn_template
*t
, unsigned int j
)
1832 return (match_reg_size (t
, j
)
1833 && !((i
.types
[j
].bitfield
.unspecified
1835 && !t
->operand_types
[j
].bitfield
.unspecified
)
1836 || (i
.types
[j
].bitfield
.fword
1837 && !t
->operand_types
[j
].bitfield
.fword
)
1838 || (i
.types
[j
].bitfield
.tbyte
1839 && !t
->operand_types
[j
].bitfield
.tbyte
)
1840 || (i
.types
[j
].bitfield
.xmmword
1841 && !t
->operand_types
[j
].bitfield
.xmmword
)
1842 || (i
.types
[j
].bitfield
.ymmword
1843 && !t
->operand_types
[j
].bitfield
.ymmword
)
1844 || (i
.types
[j
].bitfield
.zmmword
1845 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1848 /* Return 1 if there is no size conflict on any operands for
1849 instruction template T. */
1852 operand_size_match (const insn_template
*t
)
1857 /* Don't check jump instructions. */
1858 if (t
->opcode_modifier
.jump
1859 || t
->opcode_modifier
.jumpbyte
1860 || t
->opcode_modifier
.jumpdword
1861 || t
->opcode_modifier
.jumpintersegment
)
1864 /* Check memory and accumulator operand size. */
1865 for (j
= 0; j
< i
.operands
; j
++)
1867 if (!i
.types
[j
].bitfield
.reg
&& t
->operand_types
[j
].bitfield
.anysize
)
1870 if ((t
->operand_types
[j
].bitfield
.reg
1871 || t
->operand_types
[j
].bitfield
.acc
)
1872 && !match_reg_size (t
, j
))
1878 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1887 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1890 i
.error
= operand_size_mismatch
;
1894 /* Check reverse. */
1895 gas_assert (i
.operands
== 2);
1898 for (j
= 0; j
< 2; j
++)
1900 if ((t
->operand_types
[j
].bitfield
.reg
1901 || t
->operand_types
[j
].bitfield
.acc
)
1902 && !match_reg_size (t
, j
? 0 : 1))
1905 if (i
.types
[j
].bitfield
.mem
1906 && !match_mem_size (t
, j
? 0 : 1))
1914 operand_type_match (i386_operand_type overlap
,
1915 i386_operand_type given
)
1917 i386_operand_type temp
= overlap
;
1919 temp
.bitfield
.jumpabsolute
= 0;
1920 temp
.bitfield
.unspecified
= 0;
1921 temp
.bitfield
.byte
= 0;
1922 temp
.bitfield
.word
= 0;
1923 temp
.bitfield
.dword
= 0;
1924 temp
.bitfield
.fword
= 0;
1925 temp
.bitfield
.qword
= 0;
1926 temp
.bitfield
.tbyte
= 0;
1927 temp
.bitfield
.xmmword
= 0;
1928 temp
.bitfield
.ymmword
= 0;
1929 temp
.bitfield
.zmmword
= 0;
1930 if (operand_type_all_zero (&temp
))
1933 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1934 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1938 i
.error
= operand_type_mismatch
;
1942 /* If given types g0 and g1 are registers they must be of the same type
1943 unless the expected operand type register overlap is null. */
1946 operand_type_register_match (i386_operand_type g0
,
1947 i386_operand_type t0
,
1948 i386_operand_type g1
,
1949 i386_operand_type t1
)
1951 if (!operand_type_check (g0
, reg
))
1954 if (!operand_type_check (g1
, reg
))
1957 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
1958 && g0
.bitfield
.word
== g1
.bitfield
.word
1959 && g0
.bitfield
.dword
== g1
.bitfield
.dword
1960 && g0
.bitfield
.qword
== g1
.bitfield
.qword
)
1963 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
1964 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
1965 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
1966 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
))
1969 i
.error
= register_type_mismatch
;
1974 static INLINE
unsigned int
1975 register_number (const reg_entry
*r
)
1977 unsigned int nr
= r
->reg_num
;
1979 if (r
->reg_flags
& RegRex
)
1982 if (r
->reg_flags
& RegVRex
)
1988 static INLINE
unsigned int
1989 mode_from_disp_size (i386_operand_type t
)
1991 if (t
.bitfield
.disp8
)
1993 else if (t
.bitfield
.disp16
1994 || t
.bitfield
.disp32
1995 || t
.bitfield
.disp32s
)
2002 fits_in_signed_byte (addressT num
)
2004 return num
+ 0x80 <= 0xff;
2008 fits_in_unsigned_byte (addressT num
)
2014 fits_in_unsigned_word (addressT num
)
2016 return num
<= 0xffff;
2020 fits_in_signed_word (addressT num
)
2022 return num
+ 0x8000 <= 0xffff;
2026 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2031 return num
+ 0x80000000 <= 0xffffffff;
2033 } /* fits_in_signed_long() */
2036 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2041 return num
<= 0xffffffff;
2043 } /* fits_in_unsigned_long() */
2046 fits_in_disp8 (offsetT num
)
2048 int shift
= i
.memshift
;
2054 mask
= (1 << shift
) - 1;
2056 /* Return 0 if NUM isn't properly aligned. */
2060 /* Check if NUM will fit in 8bit after shift. */
2061 return fits_in_signed_byte (num
>> shift
);
2065 fits_in_imm4 (offsetT num
)
2067 return (num
& 0xf) == num
;
2070 static i386_operand_type
2071 smallest_imm_type (offsetT num
)
2073 i386_operand_type t
;
2075 operand_type_set (&t
, 0);
2076 t
.bitfield
.imm64
= 1;
2078 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2080 /* This code is disabled on the 486 because all the Imm1 forms
2081 in the opcode table are slower on the i486. They're the
2082 versions with the implicitly specified single-position
2083 displacement, which has another syntax if you really want to
2085 t
.bitfield
.imm1
= 1;
2086 t
.bitfield
.imm8
= 1;
2087 t
.bitfield
.imm8s
= 1;
2088 t
.bitfield
.imm16
= 1;
2089 t
.bitfield
.imm32
= 1;
2090 t
.bitfield
.imm32s
= 1;
2092 else if (fits_in_signed_byte (num
))
2094 t
.bitfield
.imm8
= 1;
2095 t
.bitfield
.imm8s
= 1;
2096 t
.bitfield
.imm16
= 1;
2097 t
.bitfield
.imm32
= 1;
2098 t
.bitfield
.imm32s
= 1;
2100 else if (fits_in_unsigned_byte (num
))
2102 t
.bitfield
.imm8
= 1;
2103 t
.bitfield
.imm16
= 1;
2104 t
.bitfield
.imm32
= 1;
2105 t
.bitfield
.imm32s
= 1;
2107 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2109 t
.bitfield
.imm16
= 1;
2110 t
.bitfield
.imm32
= 1;
2111 t
.bitfield
.imm32s
= 1;
2113 else if (fits_in_signed_long (num
))
2115 t
.bitfield
.imm32
= 1;
2116 t
.bitfield
.imm32s
= 1;
2118 else if (fits_in_unsigned_long (num
))
2119 t
.bitfield
.imm32
= 1;
2125 offset_in_range (offsetT val
, int size
)
2131 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2132 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2133 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2135 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2141 /* If BFD64, sign extend val for 32bit address mode. */
2142 if (flag_code
!= CODE_64BIT
2143 || i
.prefix
[ADDR_PREFIX
])
2144 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2145 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2148 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2150 char buf1
[40], buf2
[40];
2152 sprint_value (buf1
, val
);
2153 sprint_value (buf2
, val
& mask
);
2154 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2169 a. PREFIX_EXIST if attempting to add a prefix where one from the
2170 same class already exists.
2171 b. PREFIX_LOCK if lock prefix is added.
2172 c. PREFIX_REP if rep/repne prefix is added.
2173 d. PREFIX_DS if ds prefix is added.
2174 e. PREFIX_OTHER if other prefix is added.
2177 static enum PREFIX_GROUP
2178 add_prefix (unsigned int prefix
)
2180 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2183 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2184 && flag_code
== CODE_64BIT
)
2186 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2187 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2188 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2199 case DS_PREFIX_OPCODE
:
2202 case CS_PREFIX_OPCODE
:
2203 case ES_PREFIX_OPCODE
:
2204 case FS_PREFIX_OPCODE
:
2205 case GS_PREFIX_OPCODE
:
2206 case SS_PREFIX_OPCODE
:
2210 case REPNE_PREFIX_OPCODE
:
2211 case REPE_PREFIX_OPCODE
:
2216 case LOCK_PREFIX_OPCODE
:
2225 case ADDR_PREFIX_OPCODE
:
2229 case DATA_PREFIX_OPCODE
:
2233 if (i
.prefix
[q
] != 0)
2241 i
.prefix
[q
] |= prefix
;
2244 as_bad (_("same type of prefix used twice"));
2250 update_code_flag (int value
, int check
)
2252 PRINTF_LIKE ((*as_error
));
2254 flag_code
= (enum flag_code
) value
;
2255 if (flag_code
== CODE_64BIT
)
2257 cpu_arch_flags
.bitfield
.cpu64
= 1;
2258 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2262 cpu_arch_flags
.bitfield
.cpu64
= 0;
2263 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2265 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2268 as_error
= as_fatal
;
2271 (*as_error
) (_("64bit mode not supported on `%s'."),
2272 cpu_arch_name
? cpu_arch_name
: default_arch
);
2274 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2277 as_error
= as_fatal
;
2280 (*as_error
) (_("32bit mode not supported on `%s'."),
2281 cpu_arch_name
? cpu_arch_name
: default_arch
);
2283 stackop_size
= '\0';
2287 set_code_flag (int value
)
2289 update_code_flag (value
, 0);
2293 set_16bit_gcc_code_flag (int new_code_flag
)
2295 flag_code
= (enum flag_code
) new_code_flag
;
2296 if (flag_code
!= CODE_16BIT
)
2298 cpu_arch_flags
.bitfield
.cpu64
= 0;
2299 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2300 stackop_size
= LONG_MNEM_SUFFIX
;
2304 set_intel_syntax (int syntax_flag
)
2306 /* Find out if register prefixing is specified. */
2307 int ask_naked_reg
= 0;
2310 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2313 int e
= get_symbol_name (&string
);
2315 if (strcmp (string
, "prefix") == 0)
2317 else if (strcmp (string
, "noprefix") == 0)
2320 as_bad (_("bad argument to syntax directive."));
2321 (void) restore_line_pointer (e
);
2323 demand_empty_rest_of_line ();
2325 intel_syntax
= syntax_flag
;
2327 if (ask_naked_reg
== 0)
2328 allow_naked_reg
= (intel_syntax
2329 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2331 allow_naked_reg
= (ask_naked_reg
< 0);
2333 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2335 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2336 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2337 register_prefix
= allow_naked_reg
? "" : "%";
2341 set_intel_mnemonic (int mnemonic_flag
)
2343 intel_mnemonic
= mnemonic_flag
;
2347 set_allow_index_reg (int flag
)
2349 allow_index_reg
= flag
;
2353 set_check (int what
)
2355 enum check_kind
*kind
;
2360 kind
= &operand_check
;
2371 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2374 int e
= get_symbol_name (&string
);
2376 if (strcmp (string
, "none") == 0)
2378 else if (strcmp (string
, "warning") == 0)
2379 *kind
= check_warning
;
2380 else if (strcmp (string
, "error") == 0)
2381 *kind
= check_error
;
2383 as_bad (_("bad argument to %s_check directive."), str
);
2384 (void) restore_line_pointer (e
);
2387 as_bad (_("missing argument for %s_check directive"), str
);
2389 demand_empty_rest_of_line ();
2393 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2394 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2396 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2397 static const char *arch
;
2399 /* Intel LIOM is only supported on ELF. */
2405 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2406 use default_arch. */
2407 arch
= cpu_arch_name
;
2409 arch
= default_arch
;
2412 /* If we are targeting Intel MCU, we must enable it. */
2413 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2414 || new_flag
.bitfield
.cpuiamcu
)
2417 /* If we are targeting Intel L1OM, we must enable it. */
2418 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2419 || new_flag
.bitfield
.cpul1om
)
2422 /* If we are targeting Intel K1OM, we must enable it. */
2423 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2424 || new_flag
.bitfield
.cpuk1om
)
2427 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2432 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2436 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2439 int e
= get_symbol_name (&string
);
2441 i386_cpu_flags flags
;
2443 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2445 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2447 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2451 cpu_arch_name
= cpu_arch
[j
].name
;
2452 cpu_sub_arch_name
= NULL
;
2453 cpu_arch_flags
= cpu_arch
[j
].flags
;
2454 if (flag_code
== CODE_64BIT
)
2456 cpu_arch_flags
.bitfield
.cpu64
= 1;
2457 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2461 cpu_arch_flags
.bitfield
.cpu64
= 0;
2462 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2464 cpu_arch_isa
= cpu_arch
[j
].type
;
2465 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2466 if (!cpu_arch_tune_set
)
2468 cpu_arch_tune
= cpu_arch_isa
;
2469 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2474 flags
= cpu_flags_or (cpu_arch_flags
,
2477 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2479 if (cpu_sub_arch_name
)
2481 char *name
= cpu_sub_arch_name
;
2482 cpu_sub_arch_name
= concat (name
,
2484 (const char *) NULL
);
2488 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2489 cpu_arch_flags
= flags
;
2490 cpu_arch_isa_flags
= flags
;
2492 (void) restore_line_pointer (e
);
2493 demand_empty_rest_of_line ();
2498 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2500 /* Disable an ISA extension. */
2501 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2502 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2504 flags
= cpu_flags_and_not (cpu_arch_flags
,
2505 cpu_noarch
[j
].flags
);
2506 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2508 if (cpu_sub_arch_name
)
2510 char *name
= cpu_sub_arch_name
;
2511 cpu_sub_arch_name
= concat (name
, string
,
2512 (const char *) NULL
);
2516 cpu_sub_arch_name
= xstrdup (string
);
2517 cpu_arch_flags
= flags
;
2518 cpu_arch_isa_flags
= flags
;
2520 (void) restore_line_pointer (e
);
2521 demand_empty_rest_of_line ();
2525 j
= ARRAY_SIZE (cpu_arch
);
2528 if (j
>= ARRAY_SIZE (cpu_arch
))
2529 as_bad (_("no such architecture: `%s'"), string
);
2531 *input_line_pointer
= e
;
2534 as_bad (_("missing cpu architecture"));
2536 no_cond_jump_promotion
= 0;
2537 if (*input_line_pointer
== ','
2538 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2543 ++input_line_pointer
;
2544 e
= get_symbol_name (&string
);
2546 if (strcmp (string
, "nojumps") == 0)
2547 no_cond_jump_promotion
= 1;
2548 else if (strcmp (string
, "jumps") == 0)
2551 as_bad (_("no such architecture modifier: `%s'"), string
);
2553 (void) restore_line_pointer (e
);
2556 demand_empty_rest_of_line ();
2559 enum bfd_architecture
2562 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2564 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2565 || flag_code
!= CODE_64BIT
)
2566 as_fatal (_("Intel L1OM is 64bit ELF only"));
2567 return bfd_arch_l1om
;
2569 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2571 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2572 || flag_code
!= CODE_64BIT
)
2573 as_fatal (_("Intel K1OM is 64bit ELF only"));
2574 return bfd_arch_k1om
;
2576 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2578 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2579 || flag_code
== CODE_64BIT
)
2580 as_fatal (_("Intel MCU is 32bit ELF only"));
2581 return bfd_arch_iamcu
;
2584 return bfd_arch_i386
;
2590 if (!strncmp (default_arch
, "x86_64", 6))
2592 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2594 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2595 || default_arch
[6] != '\0')
2596 as_fatal (_("Intel L1OM is 64bit ELF only"));
2597 return bfd_mach_l1om
;
2599 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2601 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2602 || default_arch
[6] != '\0')
2603 as_fatal (_("Intel K1OM is 64bit ELF only"));
2604 return bfd_mach_k1om
;
2606 else if (default_arch
[6] == '\0')
2607 return bfd_mach_x86_64
;
2609 return bfd_mach_x64_32
;
2611 else if (!strcmp (default_arch
, "i386")
2612 || !strcmp (default_arch
, "iamcu"))
2614 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2616 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2617 as_fatal (_("Intel MCU is 32bit ELF only"));
2618 return bfd_mach_i386_iamcu
;
2621 return bfd_mach_i386_i386
;
2624 as_fatal (_("unknown architecture"));
2630 const char *hash_err
;
2632 /* Support pseudo prefixes like {disp32}. */
2633 lex_type
['{'] = LEX_BEGIN_NAME
;
2635 /* Initialize op_hash hash table. */
2636 op_hash
= hash_new ();
2639 const insn_template
*optab
;
2640 templates
*core_optab
;
2642 /* Setup for loop. */
2644 core_optab
= XNEW (templates
);
2645 core_optab
->start
= optab
;
2650 if (optab
->name
== NULL
2651 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2653 /* different name --> ship out current template list;
2654 add to hash table; & begin anew. */
2655 core_optab
->end
= optab
;
2656 hash_err
= hash_insert (op_hash
,
2658 (void *) core_optab
);
2661 as_fatal (_("can't hash %s: %s"),
2665 if (optab
->name
== NULL
)
2667 core_optab
= XNEW (templates
);
2668 core_optab
->start
= optab
;
2673 /* Initialize reg_hash hash table. */
2674 reg_hash
= hash_new ();
2676 const reg_entry
*regtab
;
2677 unsigned int regtab_size
= i386_regtab_size
;
2679 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2681 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2683 as_fatal (_("can't hash %s: %s"),
2689 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2694 for (c
= 0; c
< 256; c
++)
2699 mnemonic_chars
[c
] = c
;
2700 register_chars
[c
] = c
;
2701 operand_chars
[c
] = c
;
2703 else if (ISLOWER (c
))
2705 mnemonic_chars
[c
] = c
;
2706 register_chars
[c
] = c
;
2707 operand_chars
[c
] = c
;
2709 else if (ISUPPER (c
))
2711 mnemonic_chars
[c
] = TOLOWER (c
);
2712 register_chars
[c
] = mnemonic_chars
[c
];
2713 operand_chars
[c
] = c
;
2715 else if (c
== '{' || c
== '}')
2717 mnemonic_chars
[c
] = c
;
2718 operand_chars
[c
] = c
;
2721 if (ISALPHA (c
) || ISDIGIT (c
))
2722 identifier_chars
[c
] = c
;
2725 identifier_chars
[c
] = c
;
2726 operand_chars
[c
] = c
;
2731 identifier_chars
['@'] = '@';
2734 identifier_chars
['?'] = '?';
2735 operand_chars
['?'] = '?';
2737 digit_chars
['-'] = '-';
2738 mnemonic_chars
['_'] = '_';
2739 mnemonic_chars
['-'] = '-';
2740 mnemonic_chars
['.'] = '.';
2741 identifier_chars
['_'] = '_';
2742 identifier_chars
['.'] = '.';
2744 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2745 operand_chars
[(unsigned char) *p
] = *p
;
2748 if (flag_code
== CODE_64BIT
)
2750 #if defined (OBJ_COFF) && defined (TE_PE)
2751 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2754 x86_dwarf2_return_column
= 16;
2756 x86_cie_data_alignment
= -8;
2760 x86_dwarf2_return_column
= 8;
2761 x86_cie_data_alignment
= -4;
2766 i386_print_statistics (FILE *file
)
2768 hash_print_statistics (file
, "i386 opcode", op_hash
);
2769 hash_print_statistics (file
, "i386 register", reg_hash
);
2774 /* Debugging routines for md_assemble. */
2775 static void pte (insn_template
*);
2776 static void pt (i386_operand_type
);
2777 static void pe (expressionS
*);
2778 static void ps (symbolS
*);
2781 pi (char *line
, i386_insn
*x
)
2785 fprintf (stdout
, "%s: template ", line
);
2787 fprintf (stdout
, " address: base %s index %s scale %x\n",
2788 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2789 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2790 x
->log2_scale_factor
);
2791 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2792 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2793 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2794 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2795 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2796 (x
->rex
& REX_W
) != 0,
2797 (x
->rex
& REX_R
) != 0,
2798 (x
->rex
& REX_X
) != 0,
2799 (x
->rex
& REX_B
) != 0);
2800 for (j
= 0; j
< x
->operands
; j
++)
2802 fprintf (stdout
, " #%d: ", j
+ 1);
2804 fprintf (stdout
, "\n");
2805 if (x
->types
[j
].bitfield
.reg
2806 || x
->types
[j
].bitfield
.regmmx
2807 || x
->types
[j
].bitfield
.regxmm
2808 || x
->types
[j
].bitfield
.regymm
2809 || x
->types
[j
].bitfield
.regzmm
2810 || x
->types
[j
].bitfield
.sreg2
2811 || x
->types
[j
].bitfield
.sreg3
2812 || x
->types
[j
].bitfield
.control
2813 || x
->types
[j
].bitfield
.debug
2814 || x
->types
[j
].bitfield
.test
)
2815 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2816 if (operand_type_check (x
->types
[j
], imm
))
2818 if (operand_type_check (x
->types
[j
], disp
))
2819 pe (x
->op
[j
].disps
);
2824 pte (insn_template
*t
)
2827 fprintf (stdout
, " %d operands ", t
->operands
);
2828 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2829 if (t
->extension_opcode
!= None
)
2830 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2831 if (t
->opcode_modifier
.d
)
2832 fprintf (stdout
, "D");
2833 if (t
->opcode_modifier
.w
)
2834 fprintf (stdout
, "W");
2835 fprintf (stdout
, "\n");
2836 for (j
= 0; j
< t
->operands
; j
++)
2838 fprintf (stdout
, " #%d type ", j
+ 1);
2839 pt (t
->operand_types
[j
]);
2840 fprintf (stdout
, "\n");
2847 fprintf (stdout
, " operation %d\n", e
->X_op
);
2848 fprintf (stdout
, " add_number %ld (%lx)\n",
2849 (long) e
->X_add_number
, (long) e
->X_add_number
);
2850 if (e
->X_add_symbol
)
2852 fprintf (stdout
, " add_symbol ");
2853 ps (e
->X_add_symbol
);
2854 fprintf (stdout
, "\n");
2858 fprintf (stdout
, " op_symbol ");
2859 ps (e
->X_op_symbol
);
2860 fprintf (stdout
, "\n");
2867 fprintf (stdout
, "%s type %s%s",
2869 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2870 segment_name (S_GET_SEGMENT (s
)));
2873 static struct type_name
2875 i386_operand_type mask
;
2878 const type_names
[] =
2880 { OPERAND_TYPE_REG8
, "r8" },
2881 { OPERAND_TYPE_REG16
, "r16" },
2882 { OPERAND_TYPE_REG32
, "r32" },
2883 { OPERAND_TYPE_REG64
, "r64" },
2884 { OPERAND_TYPE_IMM8
, "i8" },
2885 { OPERAND_TYPE_IMM8
, "i8s" },
2886 { OPERAND_TYPE_IMM16
, "i16" },
2887 { OPERAND_TYPE_IMM32
, "i32" },
2888 { OPERAND_TYPE_IMM32S
, "i32s" },
2889 { OPERAND_TYPE_IMM64
, "i64" },
2890 { OPERAND_TYPE_IMM1
, "i1" },
2891 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2892 { OPERAND_TYPE_DISP8
, "d8" },
2893 { OPERAND_TYPE_DISP16
, "d16" },
2894 { OPERAND_TYPE_DISP32
, "d32" },
2895 { OPERAND_TYPE_DISP32S
, "d32s" },
2896 { OPERAND_TYPE_DISP64
, "d64" },
2897 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2898 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2899 { OPERAND_TYPE_CONTROL
, "control reg" },
2900 { OPERAND_TYPE_TEST
, "test reg" },
2901 { OPERAND_TYPE_DEBUG
, "debug reg" },
2902 { OPERAND_TYPE_FLOATREG
, "FReg" },
2903 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2904 { OPERAND_TYPE_SREG2
, "SReg2" },
2905 { OPERAND_TYPE_SREG3
, "SReg3" },
2906 { OPERAND_TYPE_ACC
, "Acc" },
2907 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2908 { OPERAND_TYPE_REGMMX
, "rMMX" },
2909 { OPERAND_TYPE_REGXMM
, "rXMM" },
2910 { OPERAND_TYPE_REGYMM
, "rYMM" },
2911 { OPERAND_TYPE_REGZMM
, "rZMM" },
2912 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2913 { OPERAND_TYPE_ESSEG
, "es" },
2917 pt (i386_operand_type t
)
2920 i386_operand_type a
;
2922 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2924 a
= operand_type_and (t
, type_names
[j
].mask
);
2925 if (!operand_type_all_zero (&a
))
2926 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2931 #endif /* DEBUG386 */
2933 static bfd_reloc_code_real_type
2934 reloc (unsigned int size
,
2937 bfd_reloc_code_real_type other
)
2939 if (other
!= NO_RELOC
)
2941 reloc_howto_type
*rel
;
2946 case BFD_RELOC_X86_64_GOT32
:
2947 return BFD_RELOC_X86_64_GOT64
;
2949 case BFD_RELOC_X86_64_GOTPLT64
:
2950 return BFD_RELOC_X86_64_GOTPLT64
;
2952 case BFD_RELOC_X86_64_PLTOFF64
:
2953 return BFD_RELOC_X86_64_PLTOFF64
;
2955 case BFD_RELOC_X86_64_GOTPC32
:
2956 other
= BFD_RELOC_X86_64_GOTPC64
;
2958 case BFD_RELOC_X86_64_GOTPCREL
:
2959 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2961 case BFD_RELOC_X86_64_TPOFF32
:
2962 other
= BFD_RELOC_X86_64_TPOFF64
;
2964 case BFD_RELOC_X86_64_DTPOFF32
:
2965 other
= BFD_RELOC_X86_64_DTPOFF64
;
2971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2972 if (other
== BFD_RELOC_SIZE32
)
2975 other
= BFD_RELOC_SIZE64
;
2978 as_bad (_("there are no pc-relative size relocations"));
2984 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2985 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2988 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2990 as_bad (_("unknown relocation (%u)"), other
);
2991 else if (size
!= bfd_get_reloc_size (rel
))
2992 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2993 bfd_get_reloc_size (rel
),
2995 else if (pcrel
&& !rel
->pc_relative
)
2996 as_bad (_("non-pc-relative relocation for pc-relative field"));
2997 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2999 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3001 as_bad (_("relocated field and relocation type differ in signedness"));
3010 as_bad (_("there are no unsigned pc-relative relocations"));
3013 case 1: return BFD_RELOC_8_PCREL
;
3014 case 2: return BFD_RELOC_16_PCREL
;
3015 case 4: return BFD_RELOC_32_PCREL
;
3016 case 8: return BFD_RELOC_64_PCREL
;
3018 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3025 case 4: return BFD_RELOC_X86_64_32S
;
3030 case 1: return BFD_RELOC_8
;
3031 case 2: return BFD_RELOC_16
;
3032 case 4: return BFD_RELOC_32
;
3033 case 8: return BFD_RELOC_64
;
3035 as_bad (_("cannot do %s %u byte relocation"),
3036 sign
> 0 ? "signed" : "unsigned", size
);
3042 /* Here we decide which fixups can be adjusted to make them relative to
3043 the beginning of the section instead of the symbol. Basically we need
3044 to make sure that the dynamic relocations are done correctly, so in
3045 some cases we force the original symbol to be used. */
3048 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3054 /* Don't adjust pc-relative references to merge sections in 64-bit
3056 if (use_rela_relocations
3057 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3061 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3062 and changed later by validate_fix. */
3063 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3064 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3067 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3068 for size relocations. */
3069 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3070 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3071 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3072 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3073 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3074 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3075 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3076 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3077 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3078 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3079 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3080 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3081 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3082 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3083 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3084 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3085 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3086 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3087 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3088 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3089 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3090 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3091 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3092 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3093 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3094 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3095 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3096 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3097 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3098 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3099 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3100 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3101 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3108 intel_float_operand (const char *mnemonic
)
3110 /* Note that the value returned is meaningful only for opcodes with (memory)
3111 operands, hence the code here is free to improperly handle opcodes that
3112 have no operands (for better performance and smaller code). */
3114 if (mnemonic
[0] != 'f')
3115 return 0; /* non-math */
3117 switch (mnemonic
[1])
3119 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3120 the fs segment override prefix not currently handled because no
3121 call path can make opcodes without operands get here */
3123 return 2 /* integer op */;
3125 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3126 return 3; /* fldcw/fldenv */
3129 if (mnemonic
[2] != 'o' /* fnop */)
3130 return 3; /* non-waiting control op */
3133 if (mnemonic
[2] == 's')
3134 return 3; /* frstor/frstpm */
3137 if (mnemonic
[2] == 'a')
3138 return 3; /* fsave */
3139 if (mnemonic
[2] == 't')
3141 switch (mnemonic
[3])
3143 case 'c': /* fstcw */
3144 case 'd': /* fstdw */
3145 case 'e': /* fstenv */
3146 case 's': /* fsts[gw] */
3152 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3153 return 0; /* fxsave/fxrstor are not really math ops */
3160 /* Build the VEX prefix. */
3163 build_vex_prefix (const insn_template
*t
)
3165 unsigned int register_specifier
;
3166 unsigned int implied_prefix
;
3167 unsigned int vector_length
;
3169 /* Check register specifier. */
3170 if (i
.vex
.register_specifier
)
3172 register_specifier
=
3173 ~register_number (i
.vex
.register_specifier
) & 0xf;
3174 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3177 register_specifier
= 0xf;
3179 /* Use 2-byte VEX prefix by swapping destination and source
3181 if (i
.vec_encoding
!= vex_encoding_vex3
3182 && i
.dir_encoding
== dir_encoding_default
3183 && i
.operands
== i
.reg_operands
3184 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3185 && i
.tm
.opcode_modifier
.load
3188 unsigned int xchg
= i
.operands
- 1;
3189 union i386_op temp_op
;
3190 i386_operand_type temp_type
;
3192 temp_type
= i
.types
[xchg
];
3193 i
.types
[xchg
] = i
.types
[0];
3194 i
.types
[0] = temp_type
;
3195 temp_op
= i
.op
[xchg
];
3196 i
.op
[xchg
] = i
.op
[0];
3199 gas_assert (i
.rm
.mode
== 3);
3203 i
.rm
.regmem
= i
.rm
.reg
;
3206 /* Use the next insn. */
3210 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3211 vector_length
= avxscalar
;
3213 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3215 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3220 case DATA_PREFIX_OPCODE
:
3223 case REPE_PREFIX_OPCODE
:
3226 case REPNE_PREFIX_OPCODE
:
3233 /* Use 2-byte VEX prefix if possible. */
3234 if (i
.vec_encoding
!= vex_encoding_vex3
3235 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3236 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3237 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3239 /* 2-byte VEX prefix. */
3243 i
.vex
.bytes
[0] = 0xc5;
3245 /* Check the REX.R bit. */
3246 r
= (i
.rex
& REX_R
) ? 0 : 1;
3247 i
.vex
.bytes
[1] = (r
<< 7
3248 | register_specifier
<< 3
3249 | vector_length
<< 2
3254 /* 3-byte VEX prefix. */
3259 switch (i
.tm
.opcode_modifier
.vexopcode
)
3263 i
.vex
.bytes
[0] = 0xc4;
3267 i
.vex
.bytes
[0] = 0xc4;
3271 i
.vex
.bytes
[0] = 0xc4;
3275 i
.vex
.bytes
[0] = 0x8f;
3279 i
.vex
.bytes
[0] = 0x8f;
3283 i
.vex
.bytes
[0] = 0x8f;
3289 /* The high 3 bits of the second VEX byte are 1's compliment
3290 of RXB bits from REX. */
3291 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3293 /* Check the REX.W bit. */
3294 w
= (i
.rex
& REX_W
) ? 1 : 0;
3295 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3298 i
.vex
.bytes
[2] = (w
<< 7
3299 | register_specifier
<< 3
3300 | vector_length
<< 2
3305 /* Build the EVEX prefix. */
3308 build_evex_prefix (void)
3310 unsigned int register_specifier
;
3311 unsigned int implied_prefix
;
3313 rex_byte vrex_used
= 0;
3315 /* Check register specifier. */
3316 if (i
.vex
.register_specifier
)
3318 gas_assert ((i
.vrex
& REX_X
) == 0);
3320 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3321 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3322 register_specifier
+= 8;
3323 /* The upper 16 registers are encoded in the fourth byte of the
3325 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3326 i
.vex
.bytes
[3] = 0x8;
3327 register_specifier
= ~register_specifier
& 0xf;
3331 register_specifier
= 0xf;
3333 /* Encode upper 16 vector index register in the fourth byte of
3335 if (!(i
.vrex
& REX_X
))
3336 i
.vex
.bytes
[3] = 0x8;
3341 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3346 case DATA_PREFIX_OPCODE
:
3349 case REPE_PREFIX_OPCODE
:
3352 case REPNE_PREFIX_OPCODE
:
3359 /* 4 byte EVEX prefix. */
3361 i
.vex
.bytes
[0] = 0x62;
3364 switch (i
.tm
.opcode_modifier
.vexopcode
)
3380 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3382 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3384 /* The fifth bit of the second EVEX byte is 1's compliment of the
3385 REX_R bit in VREX. */
3386 if (!(i
.vrex
& REX_R
))
3387 i
.vex
.bytes
[1] |= 0x10;
3391 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3393 /* When all operands are registers, the REX_X bit in REX is not
3394 used. We reuse it to encode the upper 16 registers, which is
3395 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3396 as 1's compliment. */
3397 if ((i
.vrex
& REX_B
))
3400 i
.vex
.bytes
[1] &= ~0x40;
3404 /* EVEX instructions shouldn't need the REX prefix. */
3405 i
.vrex
&= ~vrex_used
;
3406 gas_assert (i
.vrex
== 0);
3408 /* Check the REX.W bit. */
3409 w
= (i
.rex
& REX_W
) ? 1 : 0;
3410 if (i
.tm
.opcode_modifier
.vexw
)
3412 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3415 /* If w is not set it means we are dealing with WIG instruction. */
3418 if (evexwig
== evexw1
)
3422 /* Encode the U bit. */
3423 implied_prefix
|= 0x4;
3425 /* The third byte of the EVEX prefix. */
3426 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3428 /* The fourth byte of the EVEX prefix. */
3429 /* The zeroing-masking bit. */
3430 if (i
.mask
&& i
.mask
->zeroing
)
3431 i
.vex
.bytes
[3] |= 0x80;
3433 /* Don't always set the broadcast bit if there is no RC. */
3436 /* Encode the vector length. */
3437 unsigned int vec_length
;
3439 switch (i
.tm
.opcode_modifier
.evex
)
3441 case EVEXLIG
: /* LL' is ignored */
3442 vec_length
= evexlig
<< 5;
3445 vec_length
= 0 << 5;
3448 vec_length
= 1 << 5;
3451 vec_length
= 2 << 5;
3457 i
.vex
.bytes
[3] |= vec_length
;
3458 /* Encode the broadcast bit. */
3460 i
.vex
.bytes
[3] |= 0x10;
3464 if (i
.rounding
->type
!= saeonly
)
3465 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3467 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3470 if (i
.mask
&& i
.mask
->mask
)
3471 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3475 process_immext (void)
3479 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3482 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3483 with an opcode suffix which is coded in the same place as an
3484 8-bit immediate field would be.
3485 Here we check those operands and remove them afterwards. */
3488 for (x
= 0; x
< i
.operands
; x
++)
3489 if (register_number (i
.op
[x
].regs
) != x
)
3490 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3491 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3497 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3499 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3500 suffix which is coded in the same place as an 8-bit immediate
3502 Here we check those operands and remove them afterwards. */
3505 if (i
.operands
!= 3)
3508 for (x
= 0; x
< 2; x
++)
3509 if (register_number (i
.op
[x
].regs
) != x
)
3510 goto bad_register_operand
;
3512 /* Check for third operand for mwaitx/monitorx insn. */
3513 if (register_number (i
.op
[x
].regs
)
3514 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3516 bad_register_operand
:
3517 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3518 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3525 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3526 which is coded in the same place as an 8-bit immediate field
3527 would be. Here we fake an 8-bit immediate operand from the
3528 opcode suffix stored in tm.extension_opcode.
3530 AVX instructions also use this encoding, for some of
3531 3 argument instructions. */
3533 gas_assert (i
.imm_operands
<= 1
3535 || ((i
.tm
.opcode_modifier
.vex
3536 || i
.tm
.opcode_modifier
.evex
)
3537 && i
.operands
<= 4)));
3539 exp
= &im_expressions
[i
.imm_operands
++];
3540 i
.op
[i
.operands
].imms
= exp
;
3541 i
.types
[i
.operands
] = imm8
;
3543 exp
->X_op
= O_constant
;
3544 exp
->X_add_number
= i
.tm
.extension_opcode
;
3545 i
.tm
.extension_opcode
= None
;
3552 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3557 as_bad (_("invalid instruction `%s' after `%s'"),
3558 i
.tm
.name
, i
.hle_prefix
);
3561 if (i
.prefix
[LOCK_PREFIX
])
3563 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3567 case HLEPrefixRelease
:
3568 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3570 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3574 if (i
.mem_operands
== 0
3575 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3577 as_bad (_("memory destination needed for instruction `%s'"
3578 " after `xrelease'"), i
.tm
.name
);
3585 /* This is the guts of the machine-dependent assembler. LINE points to a
3586 machine dependent instruction. This function is supposed to emit
3587 the frags/bytes it assembles to. */
3590 md_assemble (char *line
)
3593 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3594 const insn_template
*t
;
3596 /* Initialize globals. */
3597 memset (&i
, '\0', sizeof (i
));
3598 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3599 i
.reloc
[j
] = NO_RELOC
;
3600 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3601 memset (im_expressions
, '\0', sizeof (im_expressions
));
3602 save_stack_p
= save_stack
;
3604 /* First parse an instruction mnemonic & call i386_operand for the operands.
3605 We assume that the scrubber has arranged it so that line[0] is the valid
3606 start of a (possibly prefixed) mnemonic. */
3608 line
= parse_insn (line
, mnemonic
);
3611 mnem_suffix
= i
.suffix
;
3613 line
= parse_operands (line
, mnemonic
);
3615 xfree (i
.memop1_string
);
3616 i
.memop1_string
= NULL
;
3620 /* Now we've parsed the mnemonic into a set of templates, and have the
3621 operands at hand. */
3623 /* All intel opcodes have reversed operands except for "bound" and
3624 "enter". We also don't reverse intersegment "jmp" and "call"
3625 instructions with 2 immediate operands so that the immediate segment
3626 precedes the offset, as it does when in AT&T mode. */
3629 && (strcmp (mnemonic
, "bound") != 0)
3630 && (strcmp (mnemonic
, "invlpga") != 0)
3631 && !(operand_type_check (i
.types
[0], imm
)
3632 && operand_type_check (i
.types
[1], imm
)))
3635 /* The order of the immediates should be reversed
3636 for 2 immediates extrq and insertq instructions */
3637 if (i
.imm_operands
== 2
3638 && (strcmp (mnemonic
, "extrq") == 0
3639 || strcmp (mnemonic
, "insertq") == 0))
3640 swap_2_operands (0, 1);
3645 /* Don't optimize displacement for movabs since it only takes 64bit
3648 && i
.disp_encoding
!= disp_encoding_32bit
3649 && (flag_code
!= CODE_64BIT
3650 || strcmp (mnemonic
, "movabs") != 0))
3653 /* Next, we find a template that matches the given insn,
3654 making sure the overlap of the given operands types is consistent
3655 with the template operand types. */
3657 if (!(t
= match_template (mnem_suffix
)))
3660 if (sse_check
!= check_none
3661 && !i
.tm
.opcode_modifier
.noavx
3662 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3663 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3664 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3665 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3666 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3667 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3669 (sse_check
== check_warning
3671 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3674 /* Zap movzx and movsx suffix. The suffix has been set from
3675 "word ptr" or "byte ptr" on the source operand in Intel syntax
3676 or extracted from mnemonic in AT&T syntax. But we'll use
3677 the destination register to choose the suffix for encoding. */
3678 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3680 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3681 there is no suffix, the default will be byte extension. */
3682 if (i
.reg_operands
!= 2
3685 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3690 if (i
.tm
.opcode_modifier
.fwait
)
3691 if (!add_prefix (FWAIT_OPCODE
))
3694 /* Check if REP prefix is OK. */
3695 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3697 as_bad (_("invalid instruction `%s' after `%s'"),
3698 i
.tm
.name
, i
.rep_prefix
);
3702 /* Check for lock without a lockable instruction. Destination operand
3703 must be memory unless it is xchg (0x86). */
3704 if (i
.prefix
[LOCK_PREFIX
]
3705 && (!i
.tm
.opcode_modifier
.islockable
3706 || i
.mem_operands
== 0
3707 || (i
.tm
.base_opcode
!= 0x86
3708 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3710 as_bad (_("expecting lockable instruction after `lock'"));
3714 /* Check if HLE prefix is OK. */
3715 if (i
.hle_prefix
&& !check_hle ())
3718 /* Check BND prefix. */
3719 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3720 as_bad (_("expecting valid branch instruction after `bnd'"));
3722 /* Check NOTRACK prefix. */
3723 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
3724 as_bad (_("expecting indirect branch instruction after `notrack'"));
3726 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3728 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3729 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3730 else if (flag_code
!= CODE_16BIT
3731 ? i
.prefix
[ADDR_PREFIX
]
3732 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3733 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3736 /* Insert BND prefix. */
3738 && i
.tm
.opcode_modifier
.bndprefixok
3739 && !i
.prefix
[BND_PREFIX
])
3740 add_prefix (BND_PREFIX_OPCODE
);
3742 /* Check string instruction segment overrides. */
3743 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3745 if (!check_string ())
3747 i
.disp_operands
= 0;
3750 if (!process_suffix ())
3753 /* Update operand types. */
3754 for (j
= 0; j
< i
.operands
; j
++)
3755 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3757 /* Make still unresolved immediate matches conform to size of immediate
3758 given in i.suffix. */
3759 if (!finalize_imm ())
3762 if (i
.types
[0].bitfield
.imm1
)
3763 i
.imm_operands
= 0; /* kludge for shift insns. */
3765 /* We only need to check those implicit registers for instructions
3766 with 3 operands or less. */
3767 if (i
.operands
<= 3)
3768 for (j
= 0; j
< i
.operands
; j
++)
3769 if (i
.types
[j
].bitfield
.inoutportreg
3770 || i
.types
[j
].bitfield
.shiftcount
3771 || i
.types
[j
].bitfield
.acc
3772 || i
.types
[j
].bitfield
.floatacc
)
3775 /* ImmExt should be processed after SSE2AVX. */
3776 if (!i
.tm
.opcode_modifier
.sse2avx
3777 && i
.tm
.opcode_modifier
.immext
)
3780 /* For insns with operands there are more diddles to do to the opcode. */
3783 if (!process_operands ())
3786 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3788 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3789 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3792 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3794 if (flag_code
== CODE_16BIT
)
3796 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3801 if (i
.tm
.opcode_modifier
.vex
)
3802 build_vex_prefix (t
);
3804 build_evex_prefix ();
3807 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3808 instructions may define INT_OPCODE as well, so avoid this corner
3809 case for those instructions that use MODRM. */
3810 if (i
.tm
.base_opcode
== INT_OPCODE
3811 && !i
.tm
.opcode_modifier
.modrm
3812 && i
.op
[0].imms
->X_add_number
== 3)
3814 i
.tm
.base_opcode
= INT3_OPCODE
;
3818 if ((i
.tm
.opcode_modifier
.jump
3819 || i
.tm
.opcode_modifier
.jumpbyte
3820 || i
.tm
.opcode_modifier
.jumpdword
)
3821 && i
.op
[0].disps
->X_op
== O_constant
)
3823 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3824 the absolute address given by the constant. Since ix86 jumps and
3825 calls are pc relative, we need to generate a reloc. */
3826 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3827 i
.op
[0].disps
->X_op
= O_symbol
;
3830 if (i
.tm
.opcode_modifier
.rex64
)
3833 /* For 8 bit registers we need an empty rex prefix. Also if the
3834 instruction already has a prefix, we need to convert old
3835 registers to new ones. */
3837 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
3838 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3839 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
3840 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3841 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
3842 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
3847 i
.rex
|= REX_OPCODE
;
3848 for (x
= 0; x
< 2; x
++)
3850 /* Look for 8 bit operand that uses old registers. */
3851 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
3852 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3854 /* In case it is "hi" register, give up. */
3855 if (i
.op
[x
].regs
->reg_num
> 3)
3856 as_bad (_("can't encode register '%s%s' in an "
3857 "instruction requiring REX prefix."),
3858 register_prefix
, i
.op
[x
].regs
->reg_name
);
3860 /* Otherwise it is equivalent to the extended register.
3861 Since the encoding doesn't change this is merely
3862 cosmetic cleanup for debug output. */
3864 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3870 add_prefix (REX_OPCODE
| i
.rex
);
3872 /* We are ready to output the insn. */
3877 parse_insn (char *line
, char *mnemonic
)
3880 char *token_start
= l
;
3883 const insn_template
*t
;
3889 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3894 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3896 as_bad (_("no such instruction: `%s'"), token_start
);
3901 if (!is_space_char (*l
)
3902 && *l
!= END_OF_INSN
3904 || (*l
!= PREFIX_SEPARATOR
3907 as_bad (_("invalid character %s in mnemonic"),
3908 output_invalid (*l
));
3911 if (token_start
== l
)
3913 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3914 as_bad (_("expecting prefix; got nothing"));
3916 as_bad (_("expecting mnemonic; got nothing"));
3920 /* Look up instruction (or prefix) via hash table. */
3921 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3923 if (*l
!= END_OF_INSN
3924 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3925 && current_templates
3926 && current_templates
->start
->opcode_modifier
.isprefix
)
3928 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3930 as_bad ((flag_code
!= CODE_64BIT
3931 ? _("`%s' is only supported in 64-bit mode")
3932 : _("`%s' is not supported in 64-bit mode")),
3933 current_templates
->start
->name
);
3936 /* If we are in 16-bit mode, do not allow addr16 or data16.
3937 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3938 if ((current_templates
->start
->opcode_modifier
.size16
3939 || current_templates
->start
->opcode_modifier
.size32
)
3940 && flag_code
!= CODE_64BIT
3941 && (current_templates
->start
->opcode_modifier
.size32
3942 ^ (flag_code
== CODE_16BIT
)))
3944 as_bad (_("redundant %s prefix"),
3945 current_templates
->start
->name
);
3948 if (current_templates
->start
->opcode_length
== 0)
3950 /* Handle pseudo prefixes. */
3951 switch (current_templates
->start
->base_opcode
)
3955 i
.disp_encoding
= disp_encoding_8bit
;
3959 i
.disp_encoding
= disp_encoding_32bit
;
3963 i
.dir_encoding
= dir_encoding_load
;
3967 i
.dir_encoding
= dir_encoding_store
;
3971 i
.vec_encoding
= vex_encoding_vex2
;
3975 i
.vec_encoding
= vex_encoding_vex3
;
3979 i
.vec_encoding
= vex_encoding_evex
;
3987 /* Add prefix, checking for repeated prefixes. */
3988 switch (add_prefix (current_templates
->start
->base_opcode
))
3993 if (current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
3994 i
.notrack_prefix
= current_templates
->start
->name
;
3997 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3998 i
.hle_prefix
= current_templates
->start
->name
;
3999 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4000 i
.bnd_prefix
= current_templates
->start
->name
;
4002 i
.rep_prefix
= current_templates
->start
->name
;
4008 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4015 if (!current_templates
)
4017 /* Check if we should swap operand or force 32bit displacement in
4019 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4020 i
.dir_encoding
= dir_encoding_store
;
4021 else if (mnem_p
- 3 == dot_p
4024 i
.disp_encoding
= disp_encoding_8bit
;
4025 else if (mnem_p
- 4 == dot_p
4029 i
.disp_encoding
= disp_encoding_32bit
;
4034 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4037 if (!current_templates
)
4040 /* See if we can get a match by trimming off a suffix. */
4043 case WORD_MNEM_SUFFIX
:
4044 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4045 i
.suffix
= SHORT_MNEM_SUFFIX
;
4048 case BYTE_MNEM_SUFFIX
:
4049 case QWORD_MNEM_SUFFIX
:
4050 i
.suffix
= mnem_p
[-1];
4052 current_templates
= (const templates
*) hash_find (op_hash
,
4055 case SHORT_MNEM_SUFFIX
:
4056 case LONG_MNEM_SUFFIX
:
4059 i
.suffix
= mnem_p
[-1];
4061 current_templates
= (const templates
*) hash_find (op_hash
,
4070 if (intel_float_operand (mnemonic
) == 1)
4071 i
.suffix
= SHORT_MNEM_SUFFIX
;
4073 i
.suffix
= LONG_MNEM_SUFFIX
;
4075 current_templates
= (const templates
*) hash_find (op_hash
,
4080 if (!current_templates
)
4082 as_bad (_("no such instruction: `%s'"), token_start
);
4087 if (current_templates
->start
->opcode_modifier
.jump
4088 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4090 /* Check for a branch hint. We allow ",pt" and ",pn" for
4091 predict taken and predict not taken respectively.
4092 I'm not sure that branch hints actually do anything on loop
4093 and jcxz insns (JumpByte) for current Pentium4 chips. They
4094 may work in the future and it doesn't hurt to accept them
4096 if (l
[0] == ',' && l
[1] == 'p')
4100 if (!add_prefix (DS_PREFIX_OPCODE
))
4104 else if (l
[2] == 'n')
4106 if (!add_prefix (CS_PREFIX_OPCODE
))
4112 /* Any other comma loses. */
4115 as_bad (_("invalid character %s in mnemonic"),
4116 output_invalid (*l
));
4120 /* Check if instruction is supported on specified architecture. */
4122 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4124 supported
|= cpu_flags_match (t
);
4125 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4129 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4131 as_bad (flag_code
== CODE_64BIT
4132 ? _("`%s' is not supported in 64-bit mode")
4133 : _("`%s' is only supported in 64-bit mode"),
4134 current_templates
->start
->name
);
4137 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4139 as_bad (_("`%s' is not supported on `%s%s'"),
4140 current_templates
->start
->name
,
4141 cpu_arch_name
? cpu_arch_name
: default_arch
,
4142 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4147 if (!cpu_arch_flags
.bitfield
.cpui386
4148 && (flag_code
!= CODE_16BIT
))
4150 as_warn (_("use .code16 to ensure correct addressing mode"));
4157 parse_operands (char *l
, const char *mnemonic
)
4161 /* 1 if operand is pending after ','. */
4162 unsigned int expecting_operand
= 0;
4164 /* Non-zero if operand parens not balanced. */
4165 unsigned int paren_not_balanced
;
4167 while (*l
!= END_OF_INSN
)
4169 /* Skip optional white space before operand. */
4170 if (is_space_char (*l
))
4172 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4174 as_bad (_("invalid character %s before operand %d"),
4175 output_invalid (*l
),
4179 token_start
= l
; /* After white space. */
4180 paren_not_balanced
= 0;
4181 while (paren_not_balanced
|| *l
!= ',')
4183 if (*l
== END_OF_INSN
)
4185 if (paren_not_balanced
)
4188 as_bad (_("unbalanced parenthesis in operand %d."),
4191 as_bad (_("unbalanced brackets in operand %d."),
4196 break; /* we are done */
4198 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4200 as_bad (_("invalid character %s in operand %d"),
4201 output_invalid (*l
),
4208 ++paren_not_balanced
;
4210 --paren_not_balanced
;
4215 ++paren_not_balanced
;
4217 --paren_not_balanced
;
4221 if (l
!= token_start
)
4222 { /* Yes, we've read in another operand. */
4223 unsigned int operand_ok
;
4224 this_operand
= i
.operands
++;
4225 if (i
.operands
> MAX_OPERANDS
)
4227 as_bad (_("spurious operands; (%d operands/instruction max)"),
4231 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4232 /* Now parse operand adding info to 'i' as we go along. */
4233 END_STRING_AND_SAVE (l
);
4237 i386_intel_operand (token_start
,
4238 intel_float_operand (mnemonic
));
4240 operand_ok
= i386_att_operand (token_start
);
4242 RESTORE_END_STRING (l
);
4248 if (expecting_operand
)
4250 expecting_operand_after_comma
:
4251 as_bad (_("expecting operand after ','; got nothing"));
4256 as_bad (_("expecting operand before ','; got nothing"));
4261 /* Now *l must be either ',' or END_OF_INSN. */
4264 if (*++l
== END_OF_INSN
)
4266 /* Just skip it, if it's \n complain. */
4267 goto expecting_operand_after_comma
;
4269 expecting_operand
= 1;
4276 swap_2_operands (int xchg1
, int xchg2
)
4278 union i386_op temp_op
;
4279 i386_operand_type temp_type
;
4280 enum bfd_reloc_code_real temp_reloc
;
4282 temp_type
= i
.types
[xchg2
];
4283 i
.types
[xchg2
] = i
.types
[xchg1
];
4284 i
.types
[xchg1
] = temp_type
;
4285 temp_op
= i
.op
[xchg2
];
4286 i
.op
[xchg2
] = i
.op
[xchg1
];
4287 i
.op
[xchg1
] = temp_op
;
4288 temp_reloc
= i
.reloc
[xchg2
];
4289 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4290 i
.reloc
[xchg1
] = temp_reloc
;
4294 if (i
.mask
->operand
== xchg1
)
4295 i
.mask
->operand
= xchg2
;
4296 else if (i
.mask
->operand
== xchg2
)
4297 i
.mask
->operand
= xchg1
;
4301 if (i
.broadcast
->operand
== xchg1
)
4302 i
.broadcast
->operand
= xchg2
;
4303 else if (i
.broadcast
->operand
== xchg2
)
4304 i
.broadcast
->operand
= xchg1
;
4308 if (i
.rounding
->operand
== xchg1
)
4309 i
.rounding
->operand
= xchg2
;
4310 else if (i
.rounding
->operand
== xchg2
)
4311 i
.rounding
->operand
= xchg1
;
4316 swap_operands (void)
4322 swap_2_operands (1, i
.operands
- 2);
4326 swap_2_operands (0, i
.operands
- 1);
4332 if (i
.mem_operands
== 2)
4334 const seg_entry
*temp_seg
;
4335 temp_seg
= i
.seg
[0];
4336 i
.seg
[0] = i
.seg
[1];
4337 i
.seg
[1] = temp_seg
;
4341 /* Try to ensure constant immediates are represented in the smallest
4346 char guess_suffix
= 0;
4350 guess_suffix
= i
.suffix
;
4351 else if (i
.reg_operands
)
4353 /* Figure out a suffix from the last register operand specified.
4354 We can't do this properly yet, ie. excluding InOutPortReg,
4355 but the following works for instructions with immediates.
4356 In any case, we can't set i.suffix yet. */
4357 for (op
= i
.operands
; --op
>= 0;)
4358 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4360 guess_suffix
= BYTE_MNEM_SUFFIX
;
4363 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4365 guess_suffix
= WORD_MNEM_SUFFIX
;
4368 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4370 guess_suffix
= LONG_MNEM_SUFFIX
;
4373 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4375 guess_suffix
= QWORD_MNEM_SUFFIX
;
4379 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4380 guess_suffix
= WORD_MNEM_SUFFIX
;
4382 for (op
= i
.operands
; --op
>= 0;)
4383 if (operand_type_check (i
.types
[op
], imm
))
4385 switch (i
.op
[op
].imms
->X_op
)
4388 /* If a suffix is given, this operand may be shortened. */
4389 switch (guess_suffix
)
4391 case LONG_MNEM_SUFFIX
:
4392 i
.types
[op
].bitfield
.imm32
= 1;
4393 i
.types
[op
].bitfield
.imm64
= 1;
4395 case WORD_MNEM_SUFFIX
:
4396 i
.types
[op
].bitfield
.imm16
= 1;
4397 i
.types
[op
].bitfield
.imm32
= 1;
4398 i
.types
[op
].bitfield
.imm32s
= 1;
4399 i
.types
[op
].bitfield
.imm64
= 1;
4401 case BYTE_MNEM_SUFFIX
:
4402 i
.types
[op
].bitfield
.imm8
= 1;
4403 i
.types
[op
].bitfield
.imm8s
= 1;
4404 i
.types
[op
].bitfield
.imm16
= 1;
4405 i
.types
[op
].bitfield
.imm32
= 1;
4406 i
.types
[op
].bitfield
.imm32s
= 1;
4407 i
.types
[op
].bitfield
.imm64
= 1;
4411 /* If this operand is at most 16 bits, convert it
4412 to a signed 16 bit number before trying to see
4413 whether it will fit in an even smaller size.
4414 This allows a 16-bit operand such as $0xffe0 to
4415 be recognised as within Imm8S range. */
4416 if ((i
.types
[op
].bitfield
.imm16
)
4417 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4419 i
.op
[op
].imms
->X_add_number
=
4420 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4423 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4424 if ((i
.types
[op
].bitfield
.imm32
)
4425 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4428 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4429 ^ ((offsetT
) 1 << 31))
4430 - ((offsetT
) 1 << 31));
4434 = operand_type_or (i
.types
[op
],
4435 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4437 /* We must avoid matching of Imm32 templates when 64bit
4438 only immediate is available. */
4439 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4440 i
.types
[op
].bitfield
.imm32
= 0;
4447 /* Symbols and expressions. */
4449 /* Convert symbolic operand to proper sizes for matching, but don't
4450 prevent matching a set of insns that only supports sizes other
4451 than those matching the insn suffix. */
4453 i386_operand_type mask
, allowed
;
4454 const insn_template
*t
;
4456 operand_type_set (&mask
, 0);
4457 operand_type_set (&allowed
, 0);
4459 for (t
= current_templates
->start
;
4460 t
< current_templates
->end
;
4462 allowed
= operand_type_or (allowed
,
4463 t
->operand_types
[op
]);
4464 switch (guess_suffix
)
4466 case QWORD_MNEM_SUFFIX
:
4467 mask
.bitfield
.imm64
= 1;
4468 mask
.bitfield
.imm32s
= 1;
4470 case LONG_MNEM_SUFFIX
:
4471 mask
.bitfield
.imm32
= 1;
4473 case WORD_MNEM_SUFFIX
:
4474 mask
.bitfield
.imm16
= 1;
4476 case BYTE_MNEM_SUFFIX
:
4477 mask
.bitfield
.imm8
= 1;
4482 allowed
= operand_type_and (mask
, allowed
);
4483 if (!operand_type_all_zero (&allowed
))
4484 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4491 /* Try to use the smallest displacement type too. */
4493 optimize_disp (void)
4497 for (op
= i
.operands
; --op
>= 0;)
4498 if (operand_type_check (i
.types
[op
], disp
))
4500 if (i
.op
[op
].disps
->X_op
== O_constant
)
4502 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4504 if (i
.types
[op
].bitfield
.disp16
4505 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4507 /* If this operand is at most 16 bits, convert
4508 to a signed 16 bit number and don't use 64bit
4510 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4511 i
.types
[op
].bitfield
.disp64
= 0;
4514 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4515 if (i
.types
[op
].bitfield
.disp32
4516 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4518 /* If this operand is at most 32 bits, convert
4519 to a signed 32 bit number and don't use 64bit
4521 op_disp
&= (((offsetT
) 2 << 31) - 1);
4522 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4523 i
.types
[op
].bitfield
.disp64
= 0;
4526 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4528 i
.types
[op
].bitfield
.disp8
= 0;
4529 i
.types
[op
].bitfield
.disp16
= 0;
4530 i
.types
[op
].bitfield
.disp32
= 0;
4531 i
.types
[op
].bitfield
.disp32s
= 0;
4532 i
.types
[op
].bitfield
.disp64
= 0;
4536 else if (flag_code
== CODE_64BIT
)
4538 if (fits_in_signed_long (op_disp
))
4540 i
.types
[op
].bitfield
.disp64
= 0;
4541 i
.types
[op
].bitfield
.disp32s
= 1;
4543 if (i
.prefix
[ADDR_PREFIX
]
4544 && fits_in_unsigned_long (op_disp
))
4545 i
.types
[op
].bitfield
.disp32
= 1;
4547 if ((i
.types
[op
].bitfield
.disp32
4548 || i
.types
[op
].bitfield
.disp32s
4549 || i
.types
[op
].bitfield
.disp16
)
4550 && fits_in_disp8 (op_disp
))
4551 i
.types
[op
].bitfield
.disp8
= 1;
4553 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4554 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4556 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4557 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4558 i
.types
[op
].bitfield
.disp8
= 0;
4559 i
.types
[op
].bitfield
.disp16
= 0;
4560 i
.types
[op
].bitfield
.disp32
= 0;
4561 i
.types
[op
].bitfield
.disp32s
= 0;
4562 i
.types
[op
].bitfield
.disp64
= 0;
4565 /* We only support 64bit displacement on constants. */
4566 i
.types
[op
].bitfield
.disp64
= 0;
4570 /* Check if operands are valid for the instruction. */
4573 check_VecOperands (const insn_template
*t
)
4577 /* Without VSIB byte, we can't have a vector register for index. */
4578 if (!t
->opcode_modifier
.vecsib
4580 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4581 || i
.index_reg
->reg_type
.bitfield
.regymm
4582 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4584 i
.error
= unsupported_vector_index_register
;
4588 /* Check if default mask is allowed. */
4589 if (t
->opcode_modifier
.nodefmask
4590 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4592 i
.error
= no_default_mask
;
4596 /* For VSIB byte, we need a vector register for index, and all vector
4597 registers must be distinct. */
4598 if (t
->opcode_modifier
.vecsib
)
4601 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4602 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4603 || (t
->opcode_modifier
.vecsib
== VecSIB256
4604 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4605 || (t
->opcode_modifier
.vecsib
== VecSIB512
4606 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4608 i
.error
= invalid_vsib_address
;
4612 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4613 if (i
.reg_operands
== 2 && !i
.mask
)
4615 gas_assert (i
.types
[0].bitfield
.regxmm
4616 || i
.types
[0].bitfield
.regymm
);
4617 gas_assert (i
.types
[2].bitfield
.regxmm
4618 || i
.types
[2].bitfield
.regymm
);
4619 if (operand_check
== check_none
)
4621 if (register_number (i
.op
[0].regs
)
4622 != register_number (i
.index_reg
)
4623 && register_number (i
.op
[2].regs
)
4624 != register_number (i
.index_reg
)
4625 && register_number (i
.op
[0].regs
)
4626 != register_number (i
.op
[2].regs
))
4628 if (operand_check
== check_error
)
4630 i
.error
= invalid_vector_register_set
;
4633 as_warn (_("mask, index, and destination registers should be distinct"));
4635 else if (i
.reg_operands
== 1 && i
.mask
)
4637 if ((i
.types
[1].bitfield
.regxmm
4638 || i
.types
[1].bitfield
.regymm
4639 || i
.types
[1].bitfield
.regzmm
)
4640 && (register_number (i
.op
[1].regs
)
4641 == register_number (i
.index_reg
)))
4643 if (operand_check
== check_error
)
4645 i
.error
= invalid_vector_register_set
;
4648 if (operand_check
!= check_none
)
4649 as_warn (_("index and destination registers should be distinct"));
4654 /* Check if broadcast is supported by the instruction and is applied
4655 to the memory operand. */
4658 int broadcasted_opnd_size
;
4660 /* Check if specified broadcast is supported in this instruction,
4661 and it's applied to memory operand of DWORD or QWORD type,
4662 depending on VecESize. */
4663 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4664 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4665 || (t
->opcode_modifier
.vecesize
== 0
4666 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4667 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4668 || (t
->opcode_modifier
.vecesize
== 1
4669 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4670 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4673 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4674 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4675 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4676 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4677 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4678 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4679 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4680 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4681 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4685 if ((broadcasted_opnd_size
== 256
4686 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4687 || (broadcasted_opnd_size
== 512
4688 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4691 i
.error
= unsupported_broadcast
;
4695 /* If broadcast is supported in this instruction, we need to check if
4696 operand of one-element size isn't specified without broadcast. */
4697 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4699 /* Find memory operand. */
4700 for (op
= 0; op
< i
.operands
; op
++)
4701 if (operand_type_check (i
.types
[op
], anymem
))
4703 gas_assert (op
< i
.operands
);
4704 /* Check size of the memory operand. */
4705 if ((t
->opcode_modifier
.vecesize
== 0
4706 && i
.types
[op
].bitfield
.dword
)
4707 || (t
->opcode_modifier
.vecesize
== 1
4708 && i
.types
[op
].bitfield
.qword
))
4710 i
.error
= broadcast_needed
;
4715 /* Check if requested masking is supported. */
4717 && (!t
->opcode_modifier
.masking
4719 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4721 i
.error
= unsupported_masking
;
4725 /* Check if masking is applied to dest operand. */
4726 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4728 i
.error
= mask_not_on_destination
;
4735 if ((i
.rounding
->type
!= saeonly
4736 && !t
->opcode_modifier
.staticrounding
)
4737 || (i
.rounding
->type
== saeonly
4738 && (t
->opcode_modifier
.staticrounding
4739 || !t
->opcode_modifier
.sae
)))
4741 i
.error
= unsupported_rc_sae
;
4744 /* If the instruction has several immediate operands and one of
4745 them is rounding, the rounding operand should be the last
4746 immediate operand. */
4747 if (i
.imm_operands
> 1
4748 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4750 i
.error
= rc_sae_operand_not_last_imm
;
4755 /* Check vector Disp8 operand. */
4756 if (t
->opcode_modifier
.disp8memshift
4757 && i
.disp_encoding
!= disp_encoding_32bit
)
4760 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4762 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4764 for (op
= 0; op
< i
.operands
; op
++)
4765 if (operand_type_check (i
.types
[op
], disp
)
4766 && i
.op
[op
].disps
->X_op
== O_constant
)
4768 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
4770 i
.types
[op
].bitfield
.disp8
= 1;
4773 i
.types
[op
].bitfield
.disp8
= 0;
4782 /* Check if operands are valid for the instruction. Update VEX
4786 VEX_check_operands (const insn_template
*t
)
4788 if (i
.vec_encoding
== vex_encoding_evex
)
4790 /* This instruction must be encoded with EVEX prefix. */
4791 if (!t
->opcode_modifier
.evex
)
4793 i
.error
= unsupported
;
4799 if (!t
->opcode_modifier
.vex
)
4801 /* This instruction template doesn't have VEX prefix. */
4802 if (i
.vec_encoding
!= vex_encoding_default
)
4804 i
.error
= unsupported
;
4810 /* Only check VEX_Imm4, which must be the first operand. */
4811 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4813 if (i
.op
[0].imms
->X_op
!= O_constant
4814 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4820 /* Turn off Imm8 so that update_imm won't complain. */
4821 i
.types
[0] = vec_imm4
;
4827 static const insn_template
*
4828 match_template (char mnem_suffix
)
4830 /* Points to template once we've found it. */
4831 const insn_template
*t
;
4832 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4833 i386_operand_type overlap4
;
4834 unsigned int found_reverse_match
;
4835 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4836 i386_operand_type operand_types
[MAX_OPERANDS
];
4837 int addr_prefix_disp
;
4839 unsigned int found_cpu_match
;
4840 unsigned int check_register
;
4841 enum i386_error specific_error
= 0;
4843 #if MAX_OPERANDS != 5
4844 # error "MAX_OPERANDS must be 5."
4847 found_reverse_match
= 0;
4848 addr_prefix_disp
= -1;
4850 memset (&suffix_check
, 0, sizeof (suffix_check
));
4851 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4852 suffix_check
.no_bsuf
= 1;
4853 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4854 suffix_check
.no_wsuf
= 1;
4855 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4856 suffix_check
.no_ssuf
= 1;
4857 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4858 suffix_check
.no_lsuf
= 1;
4859 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4860 suffix_check
.no_qsuf
= 1;
4861 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4862 suffix_check
.no_ldsuf
= 1;
4864 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4867 switch (mnem_suffix
)
4869 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4870 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4871 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4872 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4873 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4877 /* Must have right number of operands. */
4878 i
.error
= number_of_operands_mismatch
;
4880 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4882 addr_prefix_disp
= -1;
4884 if (i
.operands
!= t
->operands
)
4887 /* Check processor support. */
4888 i
.error
= unsupported
;
4889 found_cpu_match
= (cpu_flags_match (t
)
4890 == CPU_FLAGS_PERFECT_MATCH
);
4891 if (!found_cpu_match
)
4894 /* Check old gcc support. */
4895 i
.error
= old_gcc_only
;
4896 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4899 /* Check AT&T mnemonic. */
4900 i
.error
= unsupported_with_intel_mnemonic
;
4901 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4904 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4905 i
.error
= unsupported_syntax
;
4906 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4907 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4908 || (intel64
&& t
->opcode_modifier
.amd64
)
4909 || (!intel64
&& t
->opcode_modifier
.intel64
))
4912 /* Check the suffix, except for some instructions in intel mode. */
4913 i
.error
= invalid_instruction_suffix
;
4914 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4915 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4916 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4917 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4918 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4919 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4920 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4922 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4923 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4924 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4925 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4926 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4927 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4928 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4931 if (!operand_size_match (t
))
4934 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4935 operand_types
[j
] = t
->operand_types
[j
];
4937 /* In general, don't allow 64-bit operands in 32-bit mode. */
4938 if (i
.suffix
== QWORD_MNEM_SUFFIX
4939 && flag_code
!= CODE_64BIT
4941 ? (!t
->opcode_modifier
.ignoresize
4942 && !intel_float_operand (t
->name
))
4943 : intel_float_operand (t
->name
) != 2)
4944 && ((!operand_types
[0].bitfield
.regmmx
4945 && !operand_types
[0].bitfield
.regxmm
4946 && !operand_types
[0].bitfield
.regymm
4947 && !operand_types
[0].bitfield
.regzmm
)
4948 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4949 && !operand_types
[t
->operands
> 1].bitfield
.regxmm
4950 && !operand_types
[t
->operands
> 1].bitfield
.regymm
4951 && !operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4952 && (t
->base_opcode
!= 0x0fc7
4953 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4956 /* In general, don't allow 32-bit operands on pre-386. */
4957 else if (i
.suffix
== LONG_MNEM_SUFFIX
4958 && !cpu_arch_flags
.bitfield
.cpui386
4960 ? (!t
->opcode_modifier
.ignoresize
4961 && !intel_float_operand (t
->name
))
4962 : intel_float_operand (t
->name
) != 2)
4963 && ((!operand_types
[0].bitfield
.regmmx
4964 && !operand_types
[0].bitfield
.regxmm
)
4965 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4966 && !operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4969 /* Do not verify operands when there are none. */
4973 /* We've found a match; break out of loop. */
4977 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4978 into Disp32/Disp16/Disp32 operand. */
4979 if (i
.prefix
[ADDR_PREFIX
] != 0)
4981 /* There should be only one Disp operand. */
4985 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4987 if (operand_types
[j
].bitfield
.disp16
)
4989 addr_prefix_disp
= j
;
4990 operand_types
[j
].bitfield
.disp32
= 1;
4991 operand_types
[j
].bitfield
.disp16
= 0;
4997 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4999 if (operand_types
[j
].bitfield
.disp32
)
5001 addr_prefix_disp
= j
;
5002 operand_types
[j
].bitfield
.disp32
= 0;
5003 operand_types
[j
].bitfield
.disp16
= 1;
5009 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5011 if (operand_types
[j
].bitfield
.disp64
)
5013 addr_prefix_disp
= j
;
5014 operand_types
[j
].bitfield
.disp64
= 0;
5015 operand_types
[j
].bitfield
.disp32
= 1;
5023 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5024 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5027 /* We check register size if needed. */
5028 check_register
= t
->opcode_modifier
.checkregsize
;
5029 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5030 switch (t
->operands
)
5033 if (!operand_type_match (overlap0
, i
.types
[0]))
5037 /* xchg %eax, %eax is a special case. It is an alias for nop
5038 only in 32bit mode and we can use opcode 0x90. In 64bit
5039 mode, we can't use 0x90 for xchg %eax, %eax since it should
5040 zero-extend %eax to %rax. */
5041 if (flag_code
== CODE_64BIT
5042 && t
->base_opcode
== 0x90
5043 && operand_type_equal (&i
.types
[0], &acc32
)
5044 && operand_type_equal (&i
.types
[1], &acc32
))
5046 /* If we want store form, we reverse direction of operands. */
5047 if (i
.dir_encoding
== dir_encoding_store
5048 && t
->opcode_modifier
.d
)
5053 /* If we want store form, we skip the current load. */
5054 if (i
.dir_encoding
== dir_encoding_store
5055 && i
.mem_operands
== 0
5056 && t
->opcode_modifier
.load
)
5061 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5062 if (!operand_type_match (overlap0
, i
.types
[0])
5063 || !operand_type_match (overlap1
, i
.types
[1])
5065 && !operand_type_register_match (i
.types
[0],
5070 /* Check if other direction is valid ... */
5071 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5075 /* Try reversing direction of operands. */
5076 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5077 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5078 if (!operand_type_match (overlap0
, i
.types
[0])
5079 || !operand_type_match (overlap1
, i
.types
[1])
5081 && !operand_type_register_match (i
.types
[0],
5086 /* Does not match either direction. */
5089 /* found_reverse_match holds which of D or FloatDR
5091 if (t
->opcode_modifier
.d
)
5092 found_reverse_match
= Opcode_D
;
5093 else if (t
->opcode_modifier
.floatd
)
5094 found_reverse_match
= Opcode_FloatD
;
5096 found_reverse_match
= 0;
5097 if (t
->opcode_modifier
.floatr
)
5098 found_reverse_match
|= Opcode_FloatR
;
5102 /* Found a forward 2 operand match here. */
5103 switch (t
->operands
)
5106 overlap4
= operand_type_and (i
.types
[4],
5110 overlap3
= operand_type_and (i
.types
[3],
5114 overlap2
= operand_type_and (i
.types
[2],
5119 switch (t
->operands
)
5122 if (!operand_type_match (overlap4
, i
.types
[4])
5123 || !operand_type_register_match (i
.types
[3],
5130 if (!operand_type_match (overlap3
, i
.types
[3])
5132 && !operand_type_register_match (i
.types
[2],
5139 /* Here we make use of the fact that there are no
5140 reverse match 3 operand instructions, and all 3
5141 operand instructions only need to be checked for
5142 register consistency between operands 2 and 3. */
5143 if (!operand_type_match (overlap2
, i
.types
[2])
5145 && !operand_type_register_match (i
.types
[1],
5153 /* Found either forward/reverse 2, 3 or 4 operand match here:
5154 slip through to break. */
5156 if (!found_cpu_match
)
5158 found_reverse_match
= 0;
5162 /* Check if vector and VEX operands are valid. */
5163 if (check_VecOperands (t
) || VEX_check_operands (t
))
5165 specific_error
= i
.error
;
5169 /* We've found a match; break out of loop. */
5173 if (t
== current_templates
->end
)
5175 /* We found no match. */
5176 const char *err_msg
;
5177 switch (specific_error
? specific_error
: i
.error
)
5181 case operand_size_mismatch
:
5182 err_msg
= _("operand size mismatch");
5184 case operand_type_mismatch
:
5185 err_msg
= _("operand type mismatch");
5187 case register_type_mismatch
:
5188 err_msg
= _("register type mismatch");
5190 case number_of_operands_mismatch
:
5191 err_msg
= _("number of operands mismatch");
5193 case invalid_instruction_suffix
:
5194 err_msg
= _("invalid instruction suffix");
5197 err_msg
= _("constant doesn't fit in 4 bits");
5200 err_msg
= _("only supported with old gcc");
5202 case unsupported_with_intel_mnemonic
:
5203 err_msg
= _("unsupported with Intel mnemonic");
5205 case unsupported_syntax
:
5206 err_msg
= _("unsupported syntax");
5209 as_bad (_("unsupported instruction `%s'"),
5210 current_templates
->start
->name
);
5212 case invalid_vsib_address
:
5213 err_msg
= _("invalid VSIB address");
5215 case invalid_vector_register_set
:
5216 err_msg
= _("mask, index, and destination registers must be distinct");
5218 case unsupported_vector_index_register
:
5219 err_msg
= _("unsupported vector index register");
5221 case unsupported_broadcast
:
5222 err_msg
= _("unsupported broadcast");
5224 case broadcast_not_on_src_operand
:
5225 err_msg
= _("broadcast not on source memory operand");
5227 case broadcast_needed
:
5228 err_msg
= _("broadcast is needed for operand of such type");
5230 case unsupported_masking
:
5231 err_msg
= _("unsupported masking");
5233 case mask_not_on_destination
:
5234 err_msg
= _("mask not on destination operand");
5236 case no_default_mask
:
5237 err_msg
= _("default mask isn't allowed");
5239 case unsupported_rc_sae
:
5240 err_msg
= _("unsupported static rounding/sae");
5242 case rc_sae_operand_not_last_imm
:
5244 err_msg
= _("RC/SAE operand must precede immediate operands");
5246 err_msg
= _("RC/SAE operand must follow immediate operands");
5248 case invalid_register_operand
:
5249 err_msg
= _("invalid register operand");
5252 as_bad (_("%s for `%s'"), err_msg
,
5253 current_templates
->start
->name
);
5257 if (!quiet_warnings
)
5260 && (i
.types
[0].bitfield
.jumpabsolute
5261 != operand_types
[0].bitfield
.jumpabsolute
))
5263 as_warn (_("indirect %s without `*'"), t
->name
);
5266 if (t
->opcode_modifier
.isprefix
5267 && t
->opcode_modifier
.ignoresize
)
5269 /* Warn them that a data or address size prefix doesn't
5270 affect assembly of the next line of code. */
5271 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5275 /* Copy the template we found. */
5278 if (addr_prefix_disp
!= -1)
5279 i
.tm
.operand_types
[addr_prefix_disp
]
5280 = operand_types
[addr_prefix_disp
];
5282 if (found_reverse_match
)
5284 /* If we found a reverse match we must alter the opcode
5285 direction bit. found_reverse_match holds bits to change
5286 (different for int & float insns). */
5288 i
.tm
.base_opcode
^= found_reverse_match
;
5290 i
.tm
.operand_types
[0] = operand_types
[1];
5291 i
.tm
.operand_types
[1] = operand_types
[0];
5300 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5301 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5303 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5305 as_bad (_("`%s' operand %d must use `%ses' segment"),
5311 /* There's only ever one segment override allowed per instruction.
5312 This instruction possibly has a legal segment override on the
5313 second operand, so copy the segment to where non-string
5314 instructions store it, allowing common code. */
5315 i
.seg
[0] = i
.seg
[1];
5317 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5319 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5321 as_bad (_("`%s' operand %d must use `%ses' segment"),
5332 process_suffix (void)
5334 /* If matched instruction specifies an explicit instruction mnemonic
5336 if (i
.tm
.opcode_modifier
.size16
)
5337 i
.suffix
= WORD_MNEM_SUFFIX
;
5338 else if (i
.tm
.opcode_modifier
.size32
)
5339 i
.suffix
= LONG_MNEM_SUFFIX
;
5340 else if (i
.tm
.opcode_modifier
.size64
)
5341 i
.suffix
= QWORD_MNEM_SUFFIX
;
5342 else if (i
.reg_operands
)
5344 /* If there's no instruction mnemonic suffix we try to invent one
5345 based on register operands. */
5348 /* We take i.suffix from the last register operand specified,
5349 Destination register type is more significant than source
5350 register type. crc32 in SSE4.2 prefers source register
5352 if (i
.tm
.base_opcode
== 0xf20f38f1)
5354 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5355 i
.suffix
= WORD_MNEM_SUFFIX
;
5356 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5357 i
.suffix
= LONG_MNEM_SUFFIX
;
5358 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5359 i
.suffix
= QWORD_MNEM_SUFFIX
;
5361 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5363 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5364 i
.suffix
= BYTE_MNEM_SUFFIX
;
5371 if (i
.tm
.base_opcode
== 0xf20f38f1
5372 || i
.tm
.base_opcode
== 0xf20f38f0)
5374 /* We have to know the operand size for crc32. */
5375 as_bad (_("ambiguous memory operand size for `%s`"),
5380 for (op
= i
.operands
; --op
>= 0;)
5381 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5382 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5384 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5386 i
.suffix
= BYTE_MNEM_SUFFIX
;
5389 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5391 i
.suffix
= WORD_MNEM_SUFFIX
;
5394 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5396 i
.suffix
= LONG_MNEM_SUFFIX
;
5399 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5401 i
.suffix
= QWORD_MNEM_SUFFIX
;
5407 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5410 && i
.tm
.opcode_modifier
.ignoresize
5411 && i
.tm
.opcode_modifier
.no_bsuf
)
5413 else if (!check_byte_reg ())
5416 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5419 && i
.tm
.opcode_modifier
.ignoresize
5420 && i
.tm
.opcode_modifier
.no_lsuf
)
5422 else if (!check_long_reg ())
5425 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5428 && i
.tm
.opcode_modifier
.ignoresize
5429 && i
.tm
.opcode_modifier
.no_qsuf
)
5431 else if (!check_qword_reg ())
5434 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5437 && i
.tm
.opcode_modifier
.ignoresize
5438 && i
.tm
.opcode_modifier
.no_wsuf
)
5440 else if (!check_word_reg ())
5443 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5444 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5445 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5447 /* Skip if the instruction has x/y/z suffix. match_template
5448 should check if it is a valid suffix. */
5450 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5451 /* Do nothing if the instruction is going to ignore the prefix. */
5456 else if (i
.tm
.opcode_modifier
.defaultsize
5458 /* exclude fldenv/frstor/fsave/fstenv */
5459 && i
.tm
.opcode_modifier
.no_ssuf
)
5461 i
.suffix
= stackop_size
;
5463 else if (intel_syntax
5465 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5466 || i
.tm
.opcode_modifier
.jumpbyte
5467 || i
.tm
.opcode_modifier
.jumpintersegment
5468 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5469 && i
.tm
.extension_opcode
<= 3)))
5474 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5476 i
.suffix
= QWORD_MNEM_SUFFIX
;
5481 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5482 i
.suffix
= LONG_MNEM_SUFFIX
;
5485 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5486 i
.suffix
= WORD_MNEM_SUFFIX
;
5495 if (i
.tm
.opcode_modifier
.w
)
5497 as_bad (_("no instruction mnemonic suffix given and "
5498 "no register operands; can't size instruction"));
5504 unsigned int suffixes
;
5506 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5507 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5509 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5511 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5513 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5515 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5518 /* There are more than suffix matches. */
5519 if (i
.tm
.opcode_modifier
.w
5520 || ((suffixes
& (suffixes
- 1))
5521 && !i
.tm
.opcode_modifier
.defaultsize
5522 && !i
.tm
.opcode_modifier
.ignoresize
))
5524 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5530 /* Change the opcode based on the operand size given by i.suffix;
5531 We don't need to change things for byte insns. */
5534 && i
.suffix
!= BYTE_MNEM_SUFFIX
5535 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5536 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5537 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5539 /* It's not a byte, select word/dword operation. */
5540 if (i
.tm
.opcode_modifier
.w
)
5542 if (i
.tm
.opcode_modifier
.shortform
)
5543 i
.tm
.base_opcode
|= 8;
5545 i
.tm
.base_opcode
|= 1;
5548 /* Now select between word & dword operations via the operand
5549 size prefix, except for instructions that will ignore this
5551 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5553 /* The address size override prefix changes the size of the
5555 if ((flag_code
== CODE_32BIT
5556 && i
.op
->regs
[0].reg_type
.bitfield
.word
)
5557 || (flag_code
!= CODE_32BIT
5558 && i
.op
->regs
[0].reg_type
.bitfield
.dword
))
5559 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5562 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5563 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5564 && !i
.tm
.opcode_modifier
.ignoresize
5565 && !i
.tm
.opcode_modifier
.floatmf
5566 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5567 || (flag_code
== CODE_64BIT
5568 && i
.tm
.opcode_modifier
.jumpbyte
)))
5570 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5572 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5573 prefix
= ADDR_PREFIX_OPCODE
;
5575 if (!add_prefix (prefix
))
5579 /* Set mode64 for an operand. */
5580 if (i
.suffix
== QWORD_MNEM_SUFFIX
5581 && flag_code
== CODE_64BIT
5582 && !i
.tm
.opcode_modifier
.norex64
)
5584 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5585 need rex64. cmpxchg8b is also a special case. */
5586 if (! (i
.operands
== 2
5587 && i
.tm
.base_opcode
== 0x90
5588 && i
.tm
.extension_opcode
== None
5589 && operand_type_equal (&i
.types
[0], &acc64
)
5590 && operand_type_equal (&i
.types
[1], &acc64
))
5591 && ! (i
.operands
== 1
5592 && i
.tm
.base_opcode
== 0xfc7
5593 && i
.tm
.extension_opcode
== 1
5594 && !operand_type_check (i
.types
[0], reg
)
5595 && operand_type_check (i
.types
[0], anymem
)))
5599 /* Size floating point instruction. */
5600 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5601 if (i
.tm
.opcode_modifier
.floatmf
)
5602 i
.tm
.base_opcode
^= 4;
5609 check_byte_reg (void)
5613 for (op
= i
.operands
; --op
>= 0;)
5615 /* Skip non-register operands. */
5616 if (!i
.types
[op
].bitfield
.reg
)
5619 /* If this is an eight bit register, it's OK. If it's the 16 or
5620 32 bit version of an eight bit register, we will just use the
5621 low portion, and that's OK too. */
5622 if (i
.types
[op
].bitfield
.byte
)
5625 /* I/O port address operands are OK too. */
5626 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5629 /* crc32 doesn't generate this warning. */
5630 if (i
.tm
.base_opcode
== 0xf20f38f0)
5633 if ((i
.types
[op
].bitfield
.word
5634 || i
.types
[op
].bitfield
.dword
5635 || i
.types
[op
].bitfield
.qword
)
5636 && i
.op
[op
].regs
->reg_num
< 4
5637 /* Prohibit these changes in 64bit mode, since the lowering
5638 would be more complicated. */
5639 && flag_code
!= CODE_64BIT
)
5641 #if REGISTER_WARNINGS
5642 if (!quiet_warnings
)
5643 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5645 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
5646 ? REGNAM_AL
- REGNAM_AX
5647 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5649 i
.op
[op
].regs
->reg_name
,
5654 /* Any other register is bad. */
5655 if (i
.types
[op
].bitfield
.reg
5656 || i
.types
[op
].bitfield
.regmmx
5657 || i
.types
[op
].bitfield
.regxmm
5658 || i
.types
[op
].bitfield
.regymm
5659 || i
.types
[op
].bitfield
.regzmm
5660 || i
.types
[op
].bitfield
.sreg2
5661 || i
.types
[op
].bitfield
.sreg3
5662 || i
.types
[op
].bitfield
.control
5663 || i
.types
[op
].bitfield
.debug
5664 || i
.types
[op
].bitfield
.test
5665 || i
.types
[op
].bitfield
.floatreg
5666 || i
.types
[op
].bitfield
.floatacc
)
5668 as_bad (_("`%s%s' not allowed with `%s%c'"),
5670 i
.op
[op
].regs
->reg_name
,
5680 check_long_reg (void)
5684 for (op
= i
.operands
; --op
>= 0;)
5685 /* Skip non-register operands. */
5686 if (!i
.types
[op
].bitfield
.reg
)
5688 /* Reject eight bit registers, except where the template requires
5689 them. (eg. movzb) */
5690 else if (i
.types
[op
].bitfield
.byte
5691 && (i
.tm
.operand_types
[op
].bitfield
.reg
5692 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5693 && (i
.tm
.operand_types
[op
].bitfield
.word
5694 || i
.tm
.operand_types
[op
].bitfield
.dword
))
5696 as_bad (_("`%s%s' not allowed with `%s%c'"),
5698 i
.op
[op
].regs
->reg_name
,
5703 /* Warn if the e prefix on a general reg is missing. */
5704 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5705 && i
.types
[op
].bitfield
.word
5706 && (i
.tm
.operand_types
[op
].bitfield
.reg
5707 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5708 && i
.tm
.operand_types
[op
].bitfield
.dword
)
5710 /* Prohibit these changes in the 64bit mode, since the
5711 lowering is more complicated. */
5712 if (flag_code
== CODE_64BIT
)
5714 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5715 register_prefix
, i
.op
[op
].regs
->reg_name
,
5719 #if REGISTER_WARNINGS
5720 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5722 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5723 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5726 /* Warn if the r prefix on a general reg is present. */
5727 else if (i
.types
[op
].bitfield
.qword
5728 && (i
.tm
.operand_types
[op
].bitfield
.reg
5729 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5730 && i
.tm
.operand_types
[op
].bitfield
.dword
)
5733 && i
.tm
.opcode_modifier
.toqword
5734 && !i
.types
[0].bitfield
.regxmm
)
5736 /* Convert to QWORD. We want REX byte. */
5737 i
.suffix
= QWORD_MNEM_SUFFIX
;
5741 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5742 register_prefix
, i
.op
[op
].regs
->reg_name
,
5751 check_qword_reg (void)
5755 for (op
= i
.operands
; --op
>= 0; )
5756 /* Skip non-register operands. */
5757 if (!i
.types
[op
].bitfield
.reg
)
5759 /* Reject eight bit registers, except where the template requires
5760 them. (eg. movzb) */
5761 else if (i
.types
[op
].bitfield
.byte
5762 && (i
.tm
.operand_types
[op
].bitfield
.reg
5763 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5764 && (i
.tm
.operand_types
[op
].bitfield
.word
5765 || i
.tm
.operand_types
[op
].bitfield
.dword
))
5767 as_bad (_("`%s%s' not allowed with `%s%c'"),
5769 i
.op
[op
].regs
->reg_name
,
5774 /* Warn if the r prefix on a general reg is missing. */
5775 else if ((i
.types
[op
].bitfield
.word
5776 || i
.types
[op
].bitfield
.dword
)
5777 && (i
.tm
.operand_types
[op
].bitfield
.reg
5778 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5779 && i
.tm
.operand_types
[op
].bitfield
.qword
)
5781 /* Prohibit these changes in the 64bit mode, since the
5782 lowering is more complicated. */
5784 && i
.tm
.opcode_modifier
.todword
5785 && !i
.types
[0].bitfield
.regxmm
)
5787 /* Convert to DWORD. We don't want REX byte. */
5788 i
.suffix
= LONG_MNEM_SUFFIX
;
5792 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5793 register_prefix
, i
.op
[op
].regs
->reg_name
,
5802 check_word_reg (void)
5805 for (op
= i
.operands
; --op
>= 0;)
5806 /* Skip non-register operands. */
5807 if (!i
.types
[op
].bitfield
.reg
)
5809 /* Reject eight bit registers, except where the template requires
5810 them. (eg. movzb) */
5811 else if (i
.types
[op
].bitfield
.byte
5812 && (i
.tm
.operand_types
[op
].bitfield
.reg
5813 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5814 && (i
.tm
.operand_types
[op
].bitfield
.word
5815 || i
.tm
.operand_types
[op
].bitfield
.dword
))
5817 as_bad (_("`%s%s' not allowed with `%s%c'"),
5819 i
.op
[op
].regs
->reg_name
,
5824 /* Warn if the e or r prefix on a general reg is present. */
5825 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5826 && (i
.types
[op
].bitfield
.dword
5827 || i
.types
[op
].bitfield
.qword
)
5828 && (i
.tm
.operand_types
[op
].bitfield
.reg
5829 || i
.tm
.operand_types
[op
].bitfield
.acc
)
5830 && i
.tm
.operand_types
[op
].bitfield
.word
)
5832 /* Prohibit these changes in the 64bit mode, since the
5833 lowering is more complicated. */
5834 if (flag_code
== CODE_64BIT
)
5836 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5837 register_prefix
, i
.op
[op
].regs
->reg_name
,
5841 #if REGISTER_WARNINGS
5842 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5844 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5845 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5852 update_imm (unsigned int j
)
5854 i386_operand_type overlap
= i
.types
[j
];
5855 if ((overlap
.bitfield
.imm8
5856 || overlap
.bitfield
.imm8s
5857 || overlap
.bitfield
.imm16
5858 || overlap
.bitfield
.imm32
5859 || overlap
.bitfield
.imm32s
5860 || overlap
.bitfield
.imm64
)
5861 && !operand_type_equal (&overlap
, &imm8
)
5862 && !operand_type_equal (&overlap
, &imm8s
)
5863 && !operand_type_equal (&overlap
, &imm16
)
5864 && !operand_type_equal (&overlap
, &imm32
)
5865 && !operand_type_equal (&overlap
, &imm32s
)
5866 && !operand_type_equal (&overlap
, &imm64
))
5870 i386_operand_type temp
;
5872 operand_type_set (&temp
, 0);
5873 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5875 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5876 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5878 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5879 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5880 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5882 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5883 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5886 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5889 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5890 || operand_type_equal (&overlap
, &imm16_32
)
5891 || operand_type_equal (&overlap
, &imm16_32s
))
5893 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5898 if (!operand_type_equal (&overlap
, &imm8
)
5899 && !operand_type_equal (&overlap
, &imm8s
)
5900 && !operand_type_equal (&overlap
, &imm16
)
5901 && !operand_type_equal (&overlap
, &imm32
)
5902 && !operand_type_equal (&overlap
, &imm32s
)
5903 && !operand_type_equal (&overlap
, &imm64
))
5905 as_bad (_("no instruction mnemonic suffix given; "
5906 "can't determine immediate size"));
5910 i
.types
[j
] = overlap
;
5920 /* Update the first 2 immediate operands. */
5921 n
= i
.operands
> 2 ? 2 : i
.operands
;
5924 for (j
= 0; j
< n
; j
++)
5925 if (update_imm (j
) == 0)
5928 /* The 3rd operand can't be immediate operand. */
5929 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5936 bad_implicit_operand (int xmm
)
5938 const char *ireg
= xmm
? "xmm0" : "ymm0";
5941 as_bad (_("the last operand of `%s' must be `%s%s'"),
5942 i
.tm
.name
, register_prefix
, ireg
);
5944 as_bad (_("the first operand of `%s' must be `%s%s'"),
5945 i
.tm
.name
, register_prefix
, ireg
);
5950 process_operands (void)
5952 /* Default segment register this instruction will use for memory
5953 accesses. 0 means unknown. This is only for optimizing out
5954 unnecessary segment overrides. */
5955 const seg_entry
*default_seg
= 0;
5957 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5959 unsigned int dupl
= i
.operands
;
5960 unsigned int dest
= dupl
- 1;
5963 /* The destination must be an xmm register. */
5964 gas_assert (i
.reg_operands
5965 && MAX_OPERANDS
> dupl
5966 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5968 if (i
.tm
.opcode_modifier
.firstxmm0
)
5970 /* The first operand is implicit and must be xmm0. */
5971 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5972 if (register_number (i
.op
[0].regs
) != 0)
5973 return bad_implicit_operand (1);
5975 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5977 /* Keep xmm0 for instructions with VEX prefix and 3
5983 /* We remove the first xmm0 and keep the number of
5984 operands unchanged, which in fact duplicates the
5986 for (j
= 1; j
< i
.operands
; j
++)
5988 i
.op
[j
- 1] = i
.op
[j
];
5989 i
.types
[j
- 1] = i
.types
[j
];
5990 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5994 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5996 gas_assert ((MAX_OPERANDS
- 1) > dupl
5997 && (i
.tm
.opcode_modifier
.vexsources
6000 /* Add the implicit xmm0 for instructions with VEX prefix
6002 for (j
= i
.operands
; j
> 0; j
--)
6004 i
.op
[j
] = i
.op
[j
- 1];
6005 i
.types
[j
] = i
.types
[j
- 1];
6006 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6009 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6010 i
.types
[0] = regxmm
;
6011 i
.tm
.operand_types
[0] = regxmm
;
6014 i
.reg_operands
+= 2;
6019 i
.op
[dupl
] = i
.op
[dest
];
6020 i
.types
[dupl
] = i
.types
[dest
];
6021 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6030 i
.op
[dupl
] = i
.op
[dest
];
6031 i
.types
[dupl
] = i
.types
[dest
];
6032 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6035 if (i
.tm
.opcode_modifier
.immext
)
6038 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6042 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6043 gas_assert (i
.reg_operands
6044 && (operand_type_equal (&i
.types
[0], ®xmm
)
6045 || operand_type_equal (&i
.types
[0], ®ymm
)
6046 || operand_type_equal (&i
.types
[0], ®zmm
)));
6047 if (register_number (i
.op
[0].regs
) != 0)
6048 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6050 for (j
= 1; j
< i
.operands
; j
++)
6052 i
.op
[j
- 1] = i
.op
[j
];
6053 i
.types
[j
- 1] = i
.types
[j
];
6055 /* We need to adjust fields in i.tm since they are used by
6056 build_modrm_byte. */
6057 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6064 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6066 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6067 gas_assert (i
.operands
>= 2
6068 && (operand_type_equal (&i
.types
[1], ®xmm
)
6069 || operand_type_equal (&i
.types
[1], ®ymm
)
6070 || operand_type_equal (&i
.types
[1], ®zmm
)));
6071 unsigned int regnum
= register_number (i
.op
[1].regs
);
6072 unsigned int first_reg_in_group
= regnum
& ~3;
6073 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6074 if (regnum
!= first_reg_in_group
) {
6075 as_warn (_("the second source register `%s%s' implicitly denotes"
6076 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6077 register_prefix
, i
.op
[1].regs
->reg_name
,
6078 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6079 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6083 else if (i
.tm
.opcode_modifier
.regkludge
)
6085 /* The imul $imm, %reg instruction is converted into
6086 imul $imm, %reg, %reg, and the clr %reg instruction
6087 is converted into xor %reg, %reg. */
6089 unsigned int first_reg_op
;
6091 if (operand_type_check (i
.types
[0], reg
))
6095 /* Pretend we saw the extra register operand. */
6096 gas_assert (i
.reg_operands
== 1
6097 && i
.op
[first_reg_op
+ 1].regs
== 0);
6098 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6099 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6104 if (i
.tm
.opcode_modifier
.shortform
)
6106 if (i
.types
[0].bitfield
.sreg2
6107 || i
.types
[0].bitfield
.sreg3
)
6109 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6110 && i
.op
[0].regs
->reg_num
== 1)
6112 as_bad (_("you can't `pop %scs'"), register_prefix
);
6115 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6116 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6121 /* The register or float register operand is in operand
6125 if (i
.types
[0].bitfield
.floatreg
6126 || operand_type_check (i
.types
[0], reg
))
6130 /* Register goes in low 3 bits of opcode. */
6131 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6132 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6134 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6136 /* Warn about some common errors, but press on regardless.
6137 The first case can be generated by gcc (<= 2.8.1). */
6138 if (i
.operands
== 2)
6140 /* Reversed arguments on faddp, fsubp, etc. */
6141 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6142 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6143 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6147 /* Extraneous `l' suffix on fp insn. */
6148 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6149 register_prefix
, i
.op
[0].regs
->reg_name
);
6154 else if (i
.tm
.opcode_modifier
.modrm
)
6156 /* The opcode is completed (modulo i.tm.extension_opcode which
6157 must be put into the modrm byte). Now, we make the modrm and
6158 index base bytes based on all the info we've collected. */
6160 default_seg
= build_modrm_byte ();
6162 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6166 else if (i
.tm
.opcode_modifier
.isstring
)
6168 /* For the string instructions that allow a segment override
6169 on one of their operands, the default segment is ds. */
6173 if (i
.tm
.base_opcode
== 0x8d /* lea */
6176 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6178 /* If a segment was explicitly specified, and the specified segment
6179 is not the default, use an opcode prefix to select it. If we
6180 never figured out what the default segment is, then default_seg
6181 will be zero at this point, and the specified segment prefix will
6183 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6185 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6191 static const seg_entry
*
6192 build_modrm_byte (void)
6194 const seg_entry
*default_seg
= 0;
6195 unsigned int source
, dest
;
6198 /* The first operand of instructions with VEX prefix and 3 sources
6199 must be VEX_Imm4. */
6200 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6203 unsigned int nds
, reg_slot
;
6206 if (i
.tm
.opcode_modifier
.veximmext
6207 && i
.tm
.opcode_modifier
.immext
)
6209 dest
= i
.operands
- 2;
6210 gas_assert (dest
== 3);
6213 dest
= i
.operands
- 1;
6216 /* There are 2 kinds of instructions:
6217 1. 5 operands: 4 register operands or 3 register operands
6218 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6219 VexW0 or VexW1. The destination must be either XMM, YMM or
6221 2. 4 operands: 4 register operands or 3 register operands
6222 plus 1 memory operand, VexXDS, and VexImmExt */
6223 gas_assert ((i
.reg_operands
== 4
6224 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6225 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6226 && (i
.tm
.opcode_modifier
.veximmext
6227 || (i
.imm_operands
== 1
6228 && i
.types
[0].bitfield
.vec_imm4
6229 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6230 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6231 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6232 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6233 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6235 if (i
.imm_operands
== 0)
6237 /* When there is no immediate operand, generate an 8bit
6238 immediate operand to encode the first operand. */
6239 exp
= &im_expressions
[i
.imm_operands
++];
6240 i
.op
[i
.operands
].imms
= exp
;
6241 i
.types
[i
.operands
] = imm8
;
6243 /* If VexW1 is set, the first operand is the source and
6244 the second operand is encoded in the immediate operand. */
6245 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6256 /* FMA swaps REG and NDS. */
6257 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6265 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6267 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6269 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6271 exp
->X_op
= O_constant
;
6272 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6273 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6277 unsigned int imm_slot
;
6279 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6281 /* If VexW0 is set, the third operand is the source and
6282 the second operand is encoded in the immediate
6289 /* VexW1 is set, the second operand is the source and
6290 the third operand is encoded in the immediate
6296 if (i
.tm
.opcode_modifier
.immext
)
6298 /* When ImmExt is set, the immediate byte is the last
6300 imm_slot
= i
.operands
- 1;
6308 /* Turn on Imm8 so that output_imm will generate it. */
6309 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6312 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6314 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6316 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6318 i
.op
[imm_slot
].imms
->X_add_number
6319 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6320 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6323 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6324 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6326 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6328 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6333 /* i.reg_operands MUST be the number of real register operands;
6334 implicit registers do not count. If there are 3 register
6335 operands, it must be a instruction with VexNDS. For a
6336 instruction with VexNDD, the destination register is encoded
6337 in VEX prefix. If there are 4 register operands, it must be
6338 a instruction with VEX prefix and 3 sources. */
6339 if (i
.mem_operands
== 0
6340 && ((i
.reg_operands
== 2
6341 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6342 || (i
.reg_operands
== 3
6343 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6344 || (i
.reg_operands
== 4 && vex_3_sources
)))
6352 /* When there are 3 operands, one of them may be immediate,
6353 which may be the first or the last operand. Otherwise,
6354 the first operand must be shift count register (cl) or it
6355 is an instruction with VexNDS. */
6356 gas_assert (i
.imm_operands
== 1
6357 || (i
.imm_operands
== 0
6358 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6359 || i
.types
[0].bitfield
.shiftcount
)));
6360 if (operand_type_check (i
.types
[0], imm
)
6361 || i
.types
[0].bitfield
.shiftcount
)
6367 /* When there are 4 operands, the first two must be 8bit
6368 immediate operands. The source operand will be the 3rd
6371 For instructions with VexNDS, if the first operand
6372 an imm8, the source operand is the 2nd one. If the last
6373 operand is imm8, the source operand is the first one. */
6374 gas_assert ((i
.imm_operands
== 2
6375 && i
.types
[0].bitfield
.imm8
6376 && i
.types
[1].bitfield
.imm8
)
6377 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6378 && i
.imm_operands
== 1
6379 && (i
.types
[0].bitfield
.imm8
6380 || i
.types
[i
.operands
- 1].bitfield
.imm8
6382 if (i
.imm_operands
== 2)
6386 if (i
.types
[0].bitfield
.imm8
)
6393 if (i
.tm
.opcode_modifier
.evex
)
6395 /* For EVEX instructions, when there are 5 operands, the
6396 first one must be immediate operand. If the second one
6397 is immediate operand, the source operand is the 3th
6398 one. If the last one is immediate operand, the source
6399 operand is the 2nd one. */
6400 gas_assert (i
.imm_operands
== 2
6401 && i
.tm
.opcode_modifier
.sae
6402 && operand_type_check (i
.types
[0], imm
));
6403 if (operand_type_check (i
.types
[1], imm
))
6405 else if (operand_type_check (i
.types
[4], imm
))
6419 /* RC/SAE operand could be between DEST and SRC. That happens
6420 when one operand is GPR and the other one is XMM/YMM/ZMM
6422 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6425 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6427 /* For instructions with VexNDS, the register-only source
6428 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6429 register. It is encoded in VEX prefix. We need to
6430 clear RegMem bit before calling operand_type_equal. */
6432 i386_operand_type op
;
6435 /* Check register-only source operand when two source
6436 operands are swapped. */
6437 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6438 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6446 op
= i
.tm
.operand_types
[vvvv
];
6447 op
.bitfield
.regmem
= 0;
6448 if ((dest
+ 1) >= i
.operands
6449 || ((!op
.bitfield
.reg
6450 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6451 && !operand_type_equal (&op
, ®xmm
)
6452 && !operand_type_equal (&op
, ®ymm
)
6453 && !operand_type_equal (&op
, ®zmm
)
6454 && !operand_type_equal (&op
, ®mask
)))
6456 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6462 /* One of the register operands will be encoded in the i.tm.reg
6463 field, the other in the combined i.tm.mode and i.tm.regmem
6464 fields. If no form of this instruction supports a memory
6465 destination operand, then we assume the source operand may
6466 sometimes be a memory operand and so we need to store the
6467 destination in the i.rm.reg field. */
6468 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6469 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6471 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6472 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6473 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6475 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6477 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6479 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6484 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6485 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6486 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6488 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6490 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6492 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6495 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6497 if (!i
.types
[0].bitfield
.control
6498 && !i
.types
[1].bitfield
.control
)
6500 i
.rex
&= ~(REX_R
| REX_B
);
6501 add_prefix (LOCK_PREFIX_OPCODE
);
6505 { /* If it's not 2 reg operands... */
6510 unsigned int fake_zero_displacement
= 0;
6513 for (op
= 0; op
< i
.operands
; op
++)
6514 if (operand_type_check (i
.types
[op
], anymem
))
6516 gas_assert (op
< i
.operands
);
6518 if (i
.tm
.opcode_modifier
.vecsib
)
6520 if (i
.index_reg
->reg_num
== RegEiz
6521 || i
.index_reg
->reg_num
== RegRiz
)
6524 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6527 i
.sib
.base
= NO_BASE_REGISTER
;
6528 i
.sib
.scale
= i
.log2_scale_factor
;
6529 i
.types
[op
].bitfield
.disp8
= 0;
6530 i
.types
[op
].bitfield
.disp16
= 0;
6531 i
.types
[op
].bitfield
.disp64
= 0;
6532 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6534 /* Must be 32 bit */
6535 i
.types
[op
].bitfield
.disp32
= 1;
6536 i
.types
[op
].bitfield
.disp32s
= 0;
6540 i
.types
[op
].bitfield
.disp32
= 0;
6541 i
.types
[op
].bitfield
.disp32s
= 1;
6544 i
.sib
.index
= i
.index_reg
->reg_num
;
6545 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6547 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6553 if (i
.base_reg
== 0)
6556 if (!i
.disp_operands
)
6557 fake_zero_displacement
= 1;
6558 if (i
.index_reg
== 0)
6560 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6561 /* Operand is just <disp> */
6562 if (flag_code
== CODE_64BIT
)
6564 /* 64bit mode overwrites the 32bit absolute
6565 addressing by RIP relative addressing and
6566 absolute addressing is encoded by one of the
6567 redundant SIB forms. */
6568 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6569 i
.sib
.base
= NO_BASE_REGISTER
;
6570 i
.sib
.index
= NO_INDEX_REGISTER
;
6571 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6572 ? disp32s
: disp32
);
6574 else if ((flag_code
== CODE_16BIT
)
6575 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6577 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6578 i
.types
[op
] = disp16
;
6582 i
.rm
.regmem
= NO_BASE_REGISTER
;
6583 i
.types
[op
] = disp32
;
6586 else if (!i
.tm
.opcode_modifier
.vecsib
)
6588 /* !i.base_reg && i.index_reg */
6589 if (i
.index_reg
->reg_num
== RegEiz
6590 || i
.index_reg
->reg_num
== RegRiz
)
6591 i
.sib
.index
= NO_INDEX_REGISTER
;
6593 i
.sib
.index
= i
.index_reg
->reg_num
;
6594 i
.sib
.base
= NO_BASE_REGISTER
;
6595 i
.sib
.scale
= i
.log2_scale_factor
;
6596 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6597 i
.types
[op
].bitfield
.disp8
= 0;
6598 i
.types
[op
].bitfield
.disp16
= 0;
6599 i
.types
[op
].bitfield
.disp64
= 0;
6600 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6602 /* Must be 32 bit */
6603 i
.types
[op
].bitfield
.disp32
= 1;
6604 i
.types
[op
].bitfield
.disp32s
= 0;
6608 i
.types
[op
].bitfield
.disp32
= 0;
6609 i
.types
[op
].bitfield
.disp32s
= 1;
6611 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6615 /* RIP addressing for 64bit mode. */
6616 else if (i
.base_reg
->reg_num
== RegRip
||
6617 i
.base_reg
->reg_num
== RegEip
)
6619 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6620 i
.rm
.regmem
= NO_BASE_REGISTER
;
6621 i
.types
[op
].bitfield
.disp8
= 0;
6622 i
.types
[op
].bitfield
.disp16
= 0;
6623 i
.types
[op
].bitfield
.disp32
= 0;
6624 i
.types
[op
].bitfield
.disp32s
= 1;
6625 i
.types
[op
].bitfield
.disp64
= 0;
6626 i
.flags
[op
] |= Operand_PCrel
;
6627 if (! i
.disp_operands
)
6628 fake_zero_displacement
= 1;
6630 else if (i
.base_reg
->reg_type
.bitfield
.word
)
6632 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6633 switch (i
.base_reg
->reg_num
)
6636 if (i
.index_reg
== 0)
6638 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6639 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6643 if (i
.index_reg
== 0)
6646 if (operand_type_check (i
.types
[op
], disp
) == 0)
6648 /* fake (%bp) into 0(%bp) */
6649 i
.types
[op
].bitfield
.disp8
= 1;
6650 fake_zero_displacement
= 1;
6653 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6654 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6656 default: /* (%si) -> 4 or (%di) -> 5 */
6657 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6659 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6661 else /* i.base_reg and 32/64 bit mode */
6663 if (flag_code
== CODE_64BIT
6664 && operand_type_check (i
.types
[op
], disp
))
6666 i386_operand_type temp
;
6667 operand_type_set (&temp
, 0);
6668 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6670 if (i
.prefix
[ADDR_PREFIX
] == 0)
6671 i
.types
[op
].bitfield
.disp32s
= 1;
6673 i
.types
[op
].bitfield
.disp32
= 1;
6676 if (!i
.tm
.opcode_modifier
.vecsib
)
6677 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6678 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6680 i
.sib
.base
= i
.base_reg
->reg_num
;
6681 /* x86-64 ignores REX prefix bit here to avoid decoder
6683 if (!(i
.base_reg
->reg_flags
& RegRex
)
6684 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6685 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6687 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6689 fake_zero_displacement
= 1;
6690 i
.types
[op
].bitfield
.disp8
= 1;
6692 i
.sib
.scale
= i
.log2_scale_factor
;
6693 if (i
.index_reg
== 0)
6695 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6696 /* <disp>(%esp) becomes two byte modrm with no index
6697 register. We've already stored the code for esp
6698 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6699 Any base register besides %esp will not use the
6700 extra modrm byte. */
6701 i
.sib
.index
= NO_INDEX_REGISTER
;
6703 else if (!i
.tm
.opcode_modifier
.vecsib
)
6705 if (i
.index_reg
->reg_num
== RegEiz
6706 || i
.index_reg
->reg_num
== RegRiz
)
6707 i
.sib
.index
= NO_INDEX_REGISTER
;
6709 i
.sib
.index
= i
.index_reg
->reg_num
;
6710 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6711 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6716 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6717 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6721 if (!fake_zero_displacement
6725 fake_zero_displacement
= 1;
6726 if (i
.disp_encoding
== disp_encoding_8bit
)
6727 i
.types
[op
].bitfield
.disp8
= 1;
6729 i
.types
[op
].bitfield
.disp32
= 1;
6731 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6735 if (fake_zero_displacement
)
6737 /* Fakes a zero displacement assuming that i.types[op]
6738 holds the correct displacement size. */
6741 gas_assert (i
.op
[op
].disps
== 0);
6742 exp
= &disp_expressions
[i
.disp_operands
++];
6743 i
.op
[op
].disps
= exp
;
6744 exp
->X_op
= O_constant
;
6745 exp
->X_add_number
= 0;
6746 exp
->X_add_symbol
= (symbolS
*) 0;
6747 exp
->X_op_symbol
= (symbolS
*) 0;
6755 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6757 if (operand_type_check (i
.types
[0], imm
))
6758 i
.vex
.register_specifier
= NULL
;
6761 /* VEX.vvvv encodes one of the sources when the first
6762 operand is not an immediate. */
6763 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6764 i
.vex
.register_specifier
= i
.op
[0].regs
;
6766 i
.vex
.register_specifier
= i
.op
[1].regs
;
6769 /* Destination is a XMM register encoded in the ModRM.reg
6771 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6772 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6775 /* ModRM.rm and VEX.B encodes the other source. */
6776 if (!i
.mem_operands
)
6780 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6781 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6783 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6785 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6789 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6791 i
.vex
.register_specifier
= i
.op
[2].regs
;
6792 if (!i
.mem_operands
)
6795 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6796 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6800 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6801 (if any) based on i.tm.extension_opcode. Again, we must be
6802 careful to make sure that segment/control/debug/test/MMX
6803 registers are coded into the i.rm.reg field. */
6804 else if (i
.reg_operands
)
6807 unsigned int vex_reg
= ~0;
6809 for (op
= 0; op
< i
.operands
; op
++)
6810 if (i
.types
[op
].bitfield
.reg
6811 || i
.types
[op
].bitfield
.regmmx
6812 || i
.types
[op
].bitfield
.regxmm
6813 || i
.types
[op
].bitfield
.regymm
6814 || i
.types
[op
].bitfield
.regbnd
6815 || i
.types
[op
].bitfield
.regzmm
6816 || i
.types
[op
].bitfield
.regmask
6817 || i
.types
[op
].bitfield
.sreg2
6818 || i
.types
[op
].bitfield
.sreg3
6819 || i
.types
[op
].bitfield
.control
6820 || i
.types
[op
].bitfield
.debug
6821 || i
.types
[op
].bitfield
.test
)
6826 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6828 /* For instructions with VexNDS, the register-only
6829 source operand is encoded in VEX prefix. */
6830 gas_assert (mem
!= (unsigned int) ~0);
6835 gas_assert (op
< i
.operands
);
6839 /* Check register-only source operand when two source
6840 operands are swapped. */
6841 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6842 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6846 gas_assert (mem
== (vex_reg
+ 1)
6847 && op
< i
.operands
);
6852 gas_assert (vex_reg
< i
.operands
);
6856 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6858 /* For instructions with VexNDD, the register destination
6859 is encoded in VEX prefix. */
6860 if (i
.mem_operands
== 0)
6862 /* There is no memory operand. */
6863 gas_assert ((op
+ 2) == i
.operands
);
6868 /* There are only 2 operands. */
6869 gas_assert (op
< 2 && i
.operands
== 2);
6874 gas_assert (op
< i
.operands
);
6876 if (vex_reg
!= (unsigned int) ~0)
6878 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6880 if ((!type
->bitfield
.reg
6881 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
6882 && !operand_type_equal (type
, ®xmm
)
6883 && !operand_type_equal (type
, ®ymm
)
6884 && !operand_type_equal (type
, ®zmm
)
6885 && !operand_type_equal (type
, ®mask
))
6888 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6891 /* Don't set OP operand twice. */
6894 /* If there is an extension opcode to put here, the
6895 register number must be put into the regmem field. */
6896 if (i
.tm
.extension_opcode
!= None
)
6898 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6899 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6901 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6906 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6907 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6909 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6914 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6915 must set it to 3 to indicate this is a register operand
6916 in the regmem field. */
6917 if (!i
.mem_operands
)
6921 /* Fill in i.rm.reg field with extension opcode (if any). */
6922 if (i
.tm
.extension_opcode
!= None
)
6923 i
.rm
.reg
= i
.tm
.extension_opcode
;
6929 output_branch (void)
6935 relax_substateT subtype
;
6939 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6940 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6943 if (i
.prefix
[DATA_PREFIX
] != 0)
6949 /* Pentium4 branch hints. */
6950 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6951 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6956 if (i
.prefix
[REX_PREFIX
] != 0)
6962 /* BND prefixed jump. */
6963 if (i
.prefix
[BND_PREFIX
] != 0)
6965 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6969 if (i
.prefixes
!= 0 && !intel_syntax
)
6970 as_warn (_("skipping prefixes on this instruction"));
6972 /* It's always a symbol; End frag & setup for relax.
6973 Make sure there is enough room in this frag for the largest
6974 instruction we may generate in md_convert_frag. This is 2
6975 bytes for the opcode and room for the prefix and largest
6977 frag_grow (prefix
+ 2 + 4);
6978 /* Prefix and 1 opcode byte go in fr_fix. */
6979 p
= frag_more (prefix
+ 1);
6980 if (i
.prefix
[DATA_PREFIX
] != 0)
6981 *p
++ = DATA_PREFIX_OPCODE
;
6982 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6983 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6984 *p
++ = i
.prefix
[SEG_PREFIX
];
6985 if (i
.prefix
[REX_PREFIX
] != 0)
6986 *p
++ = i
.prefix
[REX_PREFIX
];
6987 *p
= i
.tm
.base_opcode
;
6989 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6990 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6991 else if (cpu_arch_flags
.bitfield
.cpui386
)
6992 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6994 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6997 sym
= i
.op
[0].disps
->X_add_symbol
;
6998 off
= i
.op
[0].disps
->X_add_number
;
7000 if (i
.op
[0].disps
->X_op
!= O_constant
7001 && i
.op
[0].disps
->X_op
!= O_symbol
)
7003 /* Handle complex expressions. */
7004 sym
= make_expr_symbol (i
.op
[0].disps
);
7008 /* 1 possible extra opcode + 4 byte displacement go in var part.
7009 Pass reloc in fr_var. */
7010 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7020 if (i
.tm
.opcode_modifier
.jumpbyte
)
7022 /* This is a loop or jecxz type instruction. */
7024 if (i
.prefix
[ADDR_PREFIX
] != 0)
7026 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7029 /* Pentium4 branch hints. */
7030 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7031 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7033 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7042 if (flag_code
== CODE_16BIT
)
7045 if (i
.prefix
[DATA_PREFIX
] != 0)
7047 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7057 if (i
.prefix
[REX_PREFIX
] != 0)
7059 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7063 /* BND prefixed jump. */
7064 if (i
.prefix
[BND_PREFIX
] != 0)
7066 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7070 if (i
.prefixes
!= 0 && !intel_syntax
)
7071 as_warn (_("skipping prefixes on this instruction"));
7073 p
= frag_more (i
.tm
.opcode_length
+ size
);
7074 switch (i
.tm
.opcode_length
)
7077 *p
++ = i
.tm
.base_opcode
>> 8;
7080 *p
++ = i
.tm
.base_opcode
;
7086 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7087 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7089 /* All jumps handled here are signed, but don't use a signed limit
7090 check for 32 and 16 bit jumps as we want to allow wrap around at
7091 4G and 64k respectively. */
7093 fixP
->fx_signed
= 1;
7097 output_interseg_jump (void)
7105 if (flag_code
== CODE_16BIT
)
7109 if (i
.prefix
[DATA_PREFIX
] != 0)
7115 if (i
.prefix
[REX_PREFIX
] != 0)
7125 if (i
.prefixes
!= 0 && !intel_syntax
)
7126 as_warn (_("skipping prefixes on this instruction"));
7128 /* 1 opcode; 2 segment; offset */
7129 p
= frag_more (prefix
+ 1 + 2 + size
);
7131 if (i
.prefix
[DATA_PREFIX
] != 0)
7132 *p
++ = DATA_PREFIX_OPCODE
;
7134 if (i
.prefix
[REX_PREFIX
] != 0)
7135 *p
++ = i
.prefix
[REX_PREFIX
];
7137 *p
++ = i
.tm
.base_opcode
;
7138 if (i
.op
[1].imms
->X_op
== O_constant
)
7140 offsetT n
= i
.op
[1].imms
->X_add_number
;
7143 && !fits_in_unsigned_word (n
)
7144 && !fits_in_signed_word (n
))
7146 as_bad (_("16-bit jump out of range"));
7149 md_number_to_chars (p
, n
, size
);
7152 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7153 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7154 if (i
.op
[0].imms
->X_op
!= O_constant
)
7155 as_bad (_("can't handle non absolute segment in `%s'"),
7157 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7163 fragS
*insn_start_frag
;
7164 offsetT insn_start_off
;
7166 /* Tie dwarf2 debug info to the address at the start of the insn.
7167 We can't do this after the insn has been output as the current
7168 frag may have been closed off. eg. by frag_var. */
7169 dwarf2_emit_insn (0);
7171 insn_start_frag
= frag_now
;
7172 insn_start_off
= frag_now_fix ();
7175 if (i
.tm
.opcode_modifier
.jump
)
7177 else if (i
.tm
.opcode_modifier
.jumpbyte
7178 || i
.tm
.opcode_modifier
.jumpdword
)
7180 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7181 output_interseg_jump ();
7184 /* Output normal instructions here. */
7188 unsigned int prefix
;
7191 && i
.tm
.base_opcode
== 0xfae
7193 && i
.imm_operands
== 1
7194 && (i
.op
[0].imms
->X_add_number
== 0xe8
7195 || i
.op
[0].imms
->X_add_number
== 0xf0
7196 || i
.op
[0].imms
->X_add_number
== 0xf8))
7198 /* Encode lfence, mfence, and sfence as
7199 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7200 offsetT val
= 0x240483f0ULL
;
7202 md_number_to_chars (p
, val
, 5);
7206 /* Some processors fail on LOCK prefix. This options makes
7207 assembler ignore LOCK prefix and serves as a workaround. */
7208 if (omit_lock_prefix
)
7210 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7212 i
.prefix
[LOCK_PREFIX
] = 0;
7215 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7216 don't need the explicit prefix. */
7217 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7219 switch (i
.tm
.opcode_length
)
7222 if (i
.tm
.base_opcode
& 0xff000000)
7224 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7229 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7231 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7232 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7235 if (prefix
!= REPE_PREFIX_OPCODE
7236 || (i
.prefix
[REP_PREFIX
]
7237 != REPE_PREFIX_OPCODE
))
7238 add_prefix (prefix
);
7241 add_prefix (prefix
);
7247 /* Check for pseudo prefixes. */
7248 as_bad_where (insn_start_frag
->fr_file
,
7249 insn_start_frag
->fr_line
,
7250 _("pseudo prefix without instruction"));
7256 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7257 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7258 R_X86_64_GOTTPOFF relocation so that linker can safely
7259 perform IE->LE optimization. */
7260 if (x86_elf_abi
== X86_64_X32_ABI
7262 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7263 && i
.prefix
[REX_PREFIX
] == 0)
7264 add_prefix (REX_OPCODE
);
7267 /* The prefix bytes. */
7268 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7270 FRAG_APPEND_1_CHAR (*q
);
7274 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7279 /* REX byte is encoded in VEX prefix. */
7283 FRAG_APPEND_1_CHAR (*q
);
7286 /* There should be no other prefixes for instructions
7291 /* For EVEX instructions i.vrex should become 0 after
7292 build_evex_prefix. For VEX instructions upper 16 registers
7293 aren't available, so VREX should be 0. */
7296 /* Now the VEX prefix. */
7297 p
= frag_more (i
.vex
.length
);
7298 for (j
= 0; j
< i
.vex
.length
; j
++)
7299 p
[j
] = i
.vex
.bytes
[j
];
7302 /* Now the opcode; be careful about word order here! */
7303 if (i
.tm
.opcode_length
== 1)
7305 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7309 switch (i
.tm
.opcode_length
)
7313 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7314 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7318 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7328 /* Put out high byte first: can't use md_number_to_chars! */
7329 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7330 *p
= i
.tm
.base_opcode
& 0xff;
7333 /* Now the modrm byte and sib byte (if present). */
7334 if (i
.tm
.opcode_modifier
.modrm
)
7336 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7339 /* If i.rm.regmem == ESP (4)
7340 && i.rm.mode != (Register mode)
7342 ==> need second modrm byte. */
7343 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7345 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7346 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7348 | i
.sib
.scale
<< 6));
7351 if (i
.disp_operands
)
7352 output_disp (insn_start_frag
, insn_start_off
);
7355 output_imm (insn_start_frag
, insn_start_off
);
7361 pi ("" /*line*/, &i
);
7363 #endif /* DEBUG386 */
7366 /* Return the size of the displacement operand N. */
7369 disp_size (unsigned int n
)
7373 if (i
.types
[n
].bitfield
.disp64
)
7375 else if (i
.types
[n
].bitfield
.disp8
)
7377 else if (i
.types
[n
].bitfield
.disp16
)
7382 /* Return the size of the immediate operand N. */
7385 imm_size (unsigned int n
)
7388 if (i
.types
[n
].bitfield
.imm64
)
7390 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7392 else if (i
.types
[n
].bitfield
.imm16
)
7398 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7403 for (n
= 0; n
< i
.operands
; n
++)
7405 if (operand_type_check (i
.types
[n
], disp
))
7407 if (i
.op
[n
].disps
->X_op
== O_constant
)
7409 int size
= disp_size (n
);
7410 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7412 val
= offset_in_range (val
>> i
.memshift
, size
);
7413 p
= frag_more (size
);
7414 md_number_to_chars (p
, val
, size
);
7418 enum bfd_reloc_code_real reloc_type
;
7419 int size
= disp_size (n
);
7420 int sign
= i
.types
[n
].bitfield
.disp32s
;
7421 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7424 /* We can't have 8 bit displacement here. */
7425 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7427 /* The PC relative address is computed relative
7428 to the instruction boundary, so in case immediate
7429 fields follows, we need to adjust the value. */
7430 if (pcrel
&& i
.imm_operands
)
7435 for (n1
= 0; n1
< i
.operands
; n1
++)
7436 if (operand_type_check (i
.types
[n1
], imm
))
7438 /* Only one immediate is allowed for PC
7439 relative address. */
7440 gas_assert (sz
== 0);
7442 i
.op
[n
].disps
->X_add_number
-= sz
;
7444 /* We should find the immediate. */
7445 gas_assert (sz
!= 0);
7448 p
= frag_more (size
);
7449 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7451 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7452 && (((reloc_type
== BFD_RELOC_32
7453 || reloc_type
== BFD_RELOC_X86_64_32S
7454 || (reloc_type
== BFD_RELOC_64
7456 && (i
.op
[n
].disps
->X_op
== O_symbol
7457 || (i
.op
[n
].disps
->X_op
== O_add
7458 && ((symbol_get_value_expression
7459 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7461 || reloc_type
== BFD_RELOC_32_PCREL
))
7465 if (insn_start_frag
== frag_now
)
7466 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7471 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7472 for (fr
= insn_start_frag
->fr_next
;
7473 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7475 add
+= p
- frag_now
->fr_literal
;
7480 reloc_type
= BFD_RELOC_386_GOTPC
;
7481 i
.op
[n
].imms
->X_add_number
+= add
;
7483 else if (reloc_type
== BFD_RELOC_64
)
7484 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7486 /* Don't do the adjustment for x86-64, as there
7487 the pcrel addressing is relative to the _next_
7488 insn, and that is taken care of in other code. */
7489 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7491 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7492 size
, i
.op
[n
].disps
, pcrel
,
7494 /* Check for "call/jmp *mem", "mov mem, %reg",
7495 "test %reg, mem" and "binop mem, %reg" where binop
7496 is one of adc, add, and, cmp, or, sbb, sub, xor
7497 instructions. Always generate R_386_GOT32X for
7498 "sym*GOT" operand in 32-bit mode. */
7499 if ((generate_relax_relocations
7502 && i
.rm
.regmem
== 5))
7504 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7505 && ((i
.operands
== 1
7506 && i
.tm
.base_opcode
== 0xff
7507 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7509 && (i
.tm
.base_opcode
== 0x8b
7510 || i
.tm
.base_opcode
== 0x85
7511 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7515 fixP
->fx_tcbit
= i
.rex
!= 0;
7517 && (i
.base_reg
->reg_num
== RegRip
7518 || i
.base_reg
->reg_num
== RegEip
))
7519 fixP
->fx_tcbit2
= 1;
7522 fixP
->fx_tcbit2
= 1;
7530 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7535 for (n
= 0; n
< i
.operands
; n
++)
7537 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7538 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7541 if (operand_type_check (i
.types
[n
], imm
))
7543 if (i
.op
[n
].imms
->X_op
== O_constant
)
7545 int size
= imm_size (n
);
7548 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7550 p
= frag_more (size
);
7551 md_number_to_chars (p
, val
, size
);
7555 /* Not absolute_section.
7556 Need a 32-bit fixup (don't support 8bit
7557 non-absolute imms). Try to support other
7559 enum bfd_reloc_code_real reloc_type
;
7560 int size
= imm_size (n
);
7563 if (i
.types
[n
].bitfield
.imm32s
7564 && (i
.suffix
== QWORD_MNEM_SUFFIX
7565 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7570 p
= frag_more (size
);
7571 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7573 /* This is tough to explain. We end up with this one if we
7574 * have operands that look like
7575 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7576 * obtain the absolute address of the GOT, and it is strongly
7577 * preferable from a performance point of view to avoid using
7578 * a runtime relocation for this. The actual sequence of
7579 * instructions often look something like:
7584 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7586 * The call and pop essentially return the absolute address
7587 * of the label .L66 and store it in %ebx. The linker itself
7588 * will ultimately change the first operand of the addl so
7589 * that %ebx points to the GOT, but to keep things simple, the
7590 * .o file must have this operand set so that it generates not
7591 * the absolute address of .L66, but the absolute address of
7592 * itself. This allows the linker itself simply treat a GOTPC
7593 * relocation as asking for a pcrel offset to the GOT to be
7594 * added in, and the addend of the relocation is stored in the
7595 * operand field for the instruction itself.
7597 * Our job here is to fix the operand so that it would add
7598 * the correct offset so that %ebx would point to itself. The
7599 * thing that is tricky is that .-.L66 will point to the
7600 * beginning of the instruction, so we need to further modify
7601 * the operand so that it will point to itself. There are
7602 * other cases where you have something like:
7604 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7606 * and here no correction would be required. Internally in
7607 * the assembler we treat operands of this form as not being
7608 * pcrel since the '.' is explicitly mentioned, and I wonder
7609 * whether it would simplify matters to do it this way. Who
7610 * knows. In earlier versions of the PIC patches, the
7611 * pcrel_adjust field was used to store the correction, but
7612 * since the expression is not pcrel, I felt it would be
7613 * confusing to do it this way. */
7615 if ((reloc_type
== BFD_RELOC_32
7616 || reloc_type
== BFD_RELOC_X86_64_32S
7617 || reloc_type
== BFD_RELOC_64
)
7619 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7620 && (i
.op
[n
].imms
->X_op
== O_symbol
7621 || (i
.op
[n
].imms
->X_op
== O_add
7622 && ((symbol_get_value_expression
7623 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7628 if (insn_start_frag
== frag_now
)
7629 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7634 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7635 for (fr
= insn_start_frag
->fr_next
;
7636 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7638 add
+= p
- frag_now
->fr_literal
;
7642 reloc_type
= BFD_RELOC_386_GOTPC
;
7644 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7646 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7647 i
.op
[n
].imms
->X_add_number
+= add
;
7649 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7650 i
.op
[n
].imms
, 0, reloc_type
);
7656 /* x86_cons_fix_new is called via the expression parsing code when a
7657 reloc is needed. We use this hook to get the correct .got reloc. */
7658 static int cons_sign
= -1;
7661 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7662 expressionS
*exp
, bfd_reloc_code_real_type r
)
7664 r
= reloc (len
, 0, cons_sign
, r
);
7667 if (exp
->X_op
== O_secrel
)
7669 exp
->X_op
= O_symbol
;
7670 r
= BFD_RELOC_32_SECREL
;
7674 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7677 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7678 purpose of the `.dc.a' internal pseudo-op. */
7681 x86_address_bytes (void)
7683 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7685 return stdoutput
->arch_info
->bits_per_address
/ 8;
7688 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7690 # define lex_got(reloc, adjust, types) NULL
7692 /* Parse operands of the form
7693 <symbol>@GOTOFF+<nnn>
7694 and similar .plt or .got references.
7696 If we find one, set up the correct relocation in RELOC and copy the
7697 input string, minus the `@GOTOFF' into a malloc'd buffer for
7698 parsing by the calling routine. Return this buffer, and if ADJUST
7699 is non-null set it to the length of the string we removed from the
7700 input line. Otherwise return NULL. */
7702 lex_got (enum bfd_reloc_code_real
*rel
,
7704 i386_operand_type
*types
)
7706 /* Some of the relocations depend on the size of what field is to
7707 be relocated. But in our callers i386_immediate and i386_displacement
7708 we don't yet know the operand size (this will be set by insn
7709 matching). Hence we record the word32 relocation here,
7710 and adjust the reloc according to the real size in reloc(). */
7711 static const struct {
7714 const enum bfd_reloc_code_real rel
[2];
7715 const i386_operand_type types64
;
7717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7718 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7720 OPERAND_TYPE_IMM32_64
},
7722 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7723 BFD_RELOC_X86_64_PLTOFF64
},
7724 OPERAND_TYPE_IMM64
},
7725 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7726 BFD_RELOC_X86_64_PLT32
},
7727 OPERAND_TYPE_IMM32_32S_DISP32
},
7728 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7729 BFD_RELOC_X86_64_GOTPLT64
},
7730 OPERAND_TYPE_IMM64_DISP64
},
7731 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7732 BFD_RELOC_X86_64_GOTOFF64
},
7733 OPERAND_TYPE_IMM64_DISP64
},
7734 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7735 BFD_RELOC_X86_64_GOTPCREL
},
7736 OPERAND_TYPE_IMM32_32S_DISP32
},
7737 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7738 BFD_RELOC_X86_64_TLSGD
},
7739 OPERAND_TYPE_IMM32_32S_DISP32
},
7740 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7741 _dummy_first_bfd_reloc_code_real
},
7742 OPERAND_TYPE_NONE
},
7743 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7744 BFD_RELOC_X86_64_TLSLD
},
7745 OPERAND_TYPE_IMM32_32S_DISP32
},
7746 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7747 BFD_RELOC_X86_64_GOTTPOFF
},
7748 OPERAND_TYPE_IMM32_32S_DISP32
},
7749 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7750 BFD_RELOC_X86_64_TPOFF32
},
7751 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7752 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7753 _dummy_first_bfd_reloc_code_real
},
7754 OPERAND_TYPE_NONE
},
7755 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7756 BFD_RELOC_X86_64_DTPOFF32
},
7757 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7758 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7759 _dummy_first_bfd_reloc_code_real
},
7760 OPERAND_TYPE_NONE
},
7761 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7762 _dummy_first_bfd_reloc_code_real
},
7763 OPERAND_TYPE_NONE
},
7764 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7765 BFD_RELOC_X86_64_GOT32
},
7766 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7767 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7768 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7769 OPERAND_TYPE_IMM32_32S_DISP32
},
7770 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7771 BFD_RELOC_X86_64_TLSDESC_CALL
},
7772 OPERAND_TYPE_IMM32_32S_DISP32
},
7777 #if defined (OBJ_MAYBE_ELF)
7782 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7783 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7786 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7788 int len
= gotrel
[j
].len
;
7789 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7791 if (gotrel
[j
].rel
[object_64bit
] != 0)
7794 char *tmpbuf
, *past_reloc
;
7796 *rel
= gotrel
[j
].rel
[object_64bit
];
7800 if (flag_code
!= CODE_64BIT
)
7802 types
->bitfield
.imm32
= 1;
7803 types
->bitfield
.disp32
= 1;
7806 *types
= gotrel
[j
].types64
;
7809 if (j
!= 0 && GOT_symbol
== NULL
)
7810 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7812 /* The length of the first part of our input line. */
7813 first
= cp
- input_line_pointer
;
7815 /* The second part goes from after the reloc token until
7816 (and including) an end_of_line char or comma. */
7817 past_reloc
= cp
+ 1 + len
;
7819 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7821 second
= cp
+ 1 - past_reloc
;
7823 /* Allocate and copy string. The trailing NUL shouldn't
7824 be necessary, but be safe. */
7825 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7826 memcpy (tmpbuf
, input_line_pointer
, first
);
7827 if (second
!= 0 && *past_reloc
!= ' ')
7828 /* Replace the relocation token with ' ', so that
7829 errors like foo@GOTOFF1 will be detected. */
7830 tmpbuf
[first
++] = ' ';
7832 /* Increment length by 1 if the relocation token is
7837 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7838 tmpbuf
[first
+ second
] = '\0';
7842 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7843 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7848 /* Might be a symbol version string. Don't as_bad here. */
7857 /* Parse operands of the form
7858 <symbol>@SECREL32+<nnn>
7860 If we find one, set up the correct relocation in RELOC and copy the
7861 input string, minus the `@SECREL32' into a malloc'd buffer for
7862 parsing by the calling routine. Return this buffer, and if ADJUST
7863 is non-null set it to the length of the string we removed from the
7864 input line. Otherwise return NULL.
7866 This function is copied from the ELF version above adjusted for PE targets. */
7869 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7870 int *adjust ATTRIBUTE_UNUSED
,
7871 i386_operand_type
*types
)
7877 const enum bfd_reloc_code_real rel
[2];
7878 const i386_operand_type types64
;
7882 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7883 BFD_RELOC_32_SECREL
},
7884 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7890 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7891 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7894 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7896 int len
= gotrel
[j
].len
;
7898 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7900 if (gotrel
[j
].rel
[object_64bit
] != 0)
7903 char *tmpbuf
, *past_reloc
;
7905 *rel
= gotrel
[j
].rel
[object_64bit
];
7911 if (flag_code
!= CODE_64BIT
)
7913 types
->bitfield
.imm32
= 1;
7914 types
->bitfield
.disp32
= 1;
7917 *types
= gotrel
[j
].types64
;
7920 /* The length of the first part of our input line. */
7921 first
= cp
- input_line_pointer
;
7923 /* The second part goes from after the reloc token until
7924 (and including) an end_of_line char or comma. */
7925 past_reloc
= cp
+ 1 + len
;
7927 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7929 second
= cp
+ 1 - past_reloc
;
7931 /* Allocate and copy string. The trailing NUL shouldn't
7932 be necessary, but be safe. */
7933 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7934 memcpy (tmpbuf
, input_line_pointer
, first
);
7935 if (second
!= 0 && *past_reloc
!= ' ')
7936 /* Replace the relocation token with ' ', so that
7937 errors like foo@SECLREL321 will be detected. */
7938 tmpbuf
[first
++] = ' ';
7939 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7940 tmpbuf
[first
+ second
] = '\0';
7944 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7945 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7950 /* Might be a symbol version string. Don't as_bad here. */
7956 bfd_reloc_code_real_type
7957 x86_cons (expressionS
*exp
, int size
)
7959 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7961 intel_syntax
= -intel_syntax
;
7964 if (size
== 4 || (object_64bit
&& size
== 8))
7966 /* Handle @GOTOFF and the like in an expression. */
7968 char *gotfree_input_line
;
7971 save
= input_line_pointer
;
7972 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7973 if (gotfree_input_line
)
7974 input_line_pointer
= gotfree_input_line
;
7978 if (gotfree_input_line
)
7980 /* expression () has merrily parsed up to the end of line,
7981 or a comma - in the wrong buffer. Transfer how far
7982 input_line_pointer has moved to the right buffer. */
7983 input_line_pointer
= (save
7984 + (input_line_pointer
- gotfree_input_line
)
7986 free (gotfree_input_line
);
7987 if (exp
->X_op
== O_constant
7988 || exp
->X_op
== O_absent
7989 || exp
->X_op
== O_illegal
7990 || exp
->X_op
== O_register
7991 || exp
->X_op
== O_big
)
7993 char c
= *input_line_pointer
;
7994 *input_line_pointer
= 0;
7995 as_bad (_("missing or invalid expression `%s'"), save
);
7996 *input_line_pointer
= c
;
8003 intel_syntax
= -intel_syntax
;
8006 i386_intel_simplify (exp
);
8012 signed_cons (int size
)
8014 if (flag_code
== CODE_64BIT
)
8022 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8029 if (exp
.X_op
== O_symbol
)
8030 exp
.X_op
= O_secrel
;
8032 emit_expr (&exp
, 4);
8034 while (*input_line_pointer
++ == ',');
8036 input_line_pointer
--;
8037 demand_empty_rest_of_line ();
8041 /* Handle Vector operations. */
8044 check_VecOperations (char *op_string
, char *op_end
)
8046 const reg_entry
*mask
;
8051 && (op_end
== NULL
|| op_string
< op_end
))
8054 if (*op_string
== '{')
8058 /* Check broadcasts. */
8059 if (strncmp (op_string
, "1to", 3) == 0)
8064 goto duplicated_vec_op
;
8067 if (*op_string
== '8')
8068 bcst_type
= BROADCAST_1TO8
;
8069 else if (*op_string
== '4')
8070 bcst_type
= BROADCAST_1TO4
;
8071 else if (*op_string
== '2')
8072 bcst_type
= BROADCAST_1TO2
;
8073 else if (*op_string
== '1'
8074 && *(op_string
+1) == '6')
8076 bcst_type
= BROADCAST_1TO16
;
8081 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8086 broadcast_op
.type
= bcst_type
;
8087 broadcast_op
.operand
= this_operand
;
8088 i
.broadcast
= &broadcast_op
;
8090 /* Check masking operation. */
8091 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8093 /* k0 can't be used for write mask. */
8094 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8096 as_bad (_("`%s%s' can't be used for write mask"),
8097 register_prefix
, mask
->reg_name
);
8103 mask_op
.mask
= mask
;
8104 mask_op
.zeroing
= 0;
8105 mask_op
.operand
= this_operand
;
8111 goto duplicated_vec_op
;
8113 i
.mask
->mask
= mask
;
8115 /* Only "{z}" is allowed here. No need to check
8116 zeroing mask explicitly. */
8117 if (i
.mask
->operand
!= this_operand
)
8119 as_bad (_("invalid write mask `%s'"), saved
);
8126 /* Check zeroing-flag for masking operation. */
8127 else if (*op_string
== 'z')
8131 mask_op
.mask
= NULL
;
8132 mask_op
.zeroing
= 1;
8133 mask_op
.operand
= this_operand
;
8138 if (i
.mask
->zeroing
)
8141 as_bad (_("duplicated `%s'"), saved
);
8145 i
.mask
->zeroing
= 1;
8147 /* Only "{%k}" is allowed here. No need to check mask
8148 register explicitly. */
8149 if (i
.mask
->operand
!= this_operand
)
8151 as_bad (_("invalid zeroing-masking `%s'"),
8160 goto unknown_vec_op
;
8162 if (*op_string
!= '}')
8164 as_bad (_("missing `}' in `%s'"), saved
);
8171 /* We don't know this one. */
8172 as_bad (_("unknown vector operation: `%s'"), saved
);
8176 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8178 as_bad (_("zeroing-masking only allowed with write mask"));
8186 i386_immediate (char *imm_start
)
8188 char *save_input_line_pointer
;
8189 char *gotfree_input_line
;
8192 i386_operand_type types
;
8194 operand_type_set (&types
, ~0);
8196 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8198 as_bad (_("at most %d immediate operands are allowed"),
8199 MAX_IMMEDIATE_OPERANDS
);
8203 exp
= &im_expressions
[i
.imm_operands
++];
8204 i
.op
[this_operand
].imms
= exp
;
8206 if (is_space_char (*imm_start
))
8209 save_input_line_pointer
= input_line_pointer
;
8210 input_line_pointer
= imm_start
;
8212 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8213 if (gotfree_input_line
)
8214 input_line_pointer
= gotfree_input_line
;
8216 exp_seg
= expression (exp
);
8220 /* Handle vector operations. */
8221 if (*input_line_pointer
== '{')
8223 input_line_pointer
= check_VecOperations (input_line_pointer
,
8225 if (input_line_pointer
== NULL
)
8229 if (*input_line_pointer
)
8230 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8232 input_line_pointer
= save_input_line_pointer
;
8233 if (gotfree_input_line
)
8235 free (gotfree_input_line
);
8237 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8238 exp
->X_op
= O_illegal
;
8241 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8245 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8246 i386_operand_type types
, const char *imm_start
)
8248 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8251 as_bad (_("missing or invalid immediate expression `%s'"),
8255 else if (exp
->X_op
== O_constant
)
8257 /* Size it properly later. */
8258 i
.types
[this_operand
].bitfield
.imm64
= 1;
8259 /* If not 64bit, sign extend val. */
8260 if (flag_code
!= CODE_64BIT
8261 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8263 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8265 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8266 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8267 && exp_seg
!= absolute_section
8268 && exp_seg
!= text_section
8269 && exp_seg
!= data_section
8270 && exp_seg
!= bss_section
8271 && exp_seg
!= undefined_section
8272 && !bfd_is_com_section (exp_seg
))
8274 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8278 else if (!intel_syntax
&& exp_seg
== reg_section
)
8281 as_bad (_("illegal immediate register operand %s"), imm_start
);
8286 /* This is an address. The size of the address will be
8287 determined later, depending on destination register,
8288 suffix, or the default for the section. */
8289 i
.types
[this_operand
].bitfield
.imm8
= 1;
8290 i
.types
[this_operand
].bitfield
.imm16
= 1;
8291 i
.types
[this_operand
].bitfield
.imm32
= 1;
8292 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8293 i
.types
[this_operand
].bitfield
.imm64
= 1;
8294 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8302 i386_scale (char *scale
)
8305 char *save
= input_line_pointer
;
8307 input_line_pointer
= scale
;
8308 val
= get_absolute_expression ();
8313 i
.log2_scale_factor
= 0;
8316 i
.log2_scale_factor
= 1;
8319 i
.log2_scale_factor
= 2;
8322 i
.log2_scale_factor
= 3;
8326 char sep
= *input_line_pointer
;
8328 *input_line_pointer
= '\0';
8329 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8331 *input_line_pointer
= sep
;
8332 input_line_pointer
= save
;
8336 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8338 as_warn (_("scale factor of %d without an index register"),
8339 1 << i
.log2_scale_factor
);
8340 i
.log2_scale_factor
= 0;
8342 scale
= input_line_pointer
;
8343 input_line_pointer
= save
;
8348 i386_displacement (char *disp_start
, char *disp_end
)
8352 char *save_input_line_pointer
;
8353 char *gotfree_input_line
;
8355 i386_operand_type bigdisp
, types
= anydisp
;
8358 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8360 as_bad (_("at most %d displacement operands are allowed"),
8361 MAX_MEMORY_OPERANDS
);
8365 operand_type_set (&bigdisp
, 0);
8366 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8367 || (!current_templates
->start
->opcode_modifier
.jump
8368 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8370 bigdisp
.bitfield
.disp32
= 1;
8371 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8372 if (flag_code
== CODE_64BIT
)
8376 bigdisp
.bitfield
.disp32s
= 1;
8377 bigdisp
.bitfield
.disp64
= 1;
8380 else if ((flag_code
== CODE_16BIT
) ^ override
)
8382 bigdisp
.bitfield
.disp32
= 0;
8383 bigdisp
.bitfield
.disp16
= 1;
8388 /* For PC-relative branches, the width of the displacement
8389 is dependent upon data size, not address size. */
8390 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8391 if (flag_code
== CODE_64BIT
)
8393 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8394 bigdisp
.bitfield
.disp16
= 1;
8397 bigdisp
.bitfield
.disp32
= 1;
8398 bigdisp
.bitfield
.disp32s
= 1;
8404 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8406 : LONG_MNEM_SUFFIX
));
8407 bigdisp
.bitfield
.disp32
= 1;
8408 if ((flag_code
== CODE_16BIT
) ^ override
)
8410 bigdisp
.bitfield
.disp32
= 0;
8411 bigdisp
.bitfield
.disp16
= 1;
8415 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8418 exp
= &disp_expressions
[i
.disp_operands
];
8419 i
.op
[this_operand
].disps
= exp
;
8421 save_input_line_pointer
= input_line_pointer
;
8422 input_line_pointer
= disp_start
;
8423 END_STRING_AND_SAVE (disp_end
);
8425 #ifndef GCC_ASM_O_HACK
8426 #define GCC_ASM_O_HACK 0
8429 END_STRING_AND_SAVE (disp_end
+ 1);
8430 if (i
.types
[this_operand
].bitfield
.baseIndex
8431 && displacement_string_end
[-1] == '+')
8433 /* This hack is to avoid a warning when using the "o"
8434 constraint within gcc asm statements.
8437 #define _set_tssldt_desc(n,addr,limit,type) \
8438 __asm__ __volatile__ ( \
8440 "movw %w1,2+%0\n\t" \
8442 "movb %b1,4+%0\n\t" \
8443 "movb %4,5+%0\n\t" \
8444 "movb $0,6+%0\n\t" \
8445 "movb %h1,7+%0\n\t" \
8447 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8449 This works great except that the output assembler ends
8450 up looking a bit weird if it turns out that there is
8451 no offset. You end up producing code that looks like:
8464 So here we provide the missing zero. */
8466 *displacement_string_end
= '0';
8469 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8470 if (gotfree_input_line
)
8471 input_line_pointer
= gotfree_input_line
;
8473 exp_seg
= expression (exp
);
8476 if (*input_line_pointer
)
8477 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8479 RESTORE_END_STRING (disp_end
+ 1);
8481 input_line_pointer
= save_input_line_pointer
;
8482 if (gotfree_input_line
)
8484 free (gotfree_input_line
);
8486 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8487 exp
->X_op
= O_illegal
;
8490 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8492 RESTORE_END_STRING (disp_end
);
8498 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8499 i386_operand_type types
, const char *disp_start
)
8501 i386_operand_type bigdisp
;
8504 /* We do this to make sure that the section symbol is in
8505 the symbol table. We will ultimately change the relocation
8506 to be relative to the beginning of the section. */
8507 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8508 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8509 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8511 if (exp
->X_op
!= O_symbol
)
8514 if (S_IS_LOCAL (exp
->X_add_symbol
)
8515 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8516 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8517 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8518 exp
->X_op
= O_subtract
;
8519 exp
->X_op_symbol
= GOT_symbol
;
8520 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8521 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8522 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8523 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8525 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8528 else if (exp
->X_op
== O_absent
8529 || exp
->X_op
== O_illegal
8530 || exp
->X_op
== O_big
)
8533 as_bad (_("missing or invalid displacement expression `%s'"),
8538 else if (flag_code
== CODE_64BIT
8539 && !i
.prefix
[ADDR_PREFIX
]
8540 && exp
->X_op
== O_constant
)
8542 /* Since displacement is signed extended to 64bit, don't allow
8543 disp32 and turn off disp32s if they are out of range. */
8544 i
.types
[this_operand
].bitfield
.disp32
= 0;
8545 if (!fits_in_signed_long (exp
->X_add_number
))
8547 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8548 if (i
.types
[this_operand
].bitfield
.baseindex
)
8550 as_bad (_("0x%lx out range of signed 32bit displacement"),
8551 (long) exp
->X_add_number
);
8557 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8558 else if (exp
->X_op
!= O_constant
8559 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8560 && exp_seg
!= absolute_section
8561 && exp_seg
!= text_section
8562 && exp_seg
!= data_section
8563 && exp_seg
!= bss_section
8564 && exp_seg
!= undefined_section
8565 && !bfd_is_com_section (exp_seg
))
8567 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8572 /* Check if this is a displacement only operand. */
8573 bigdisp
= i
.types
[this_operand
];
8574 bigdisp
.bitfield
.disp8
= 0;
8575 bigdisp
.bitfield
.disp16
= 0;
8576 bigdisp
.bitfield
.disp32
= 0;
8577 bigdisp
.bitfield
.disp32s
= 0;
8578 bigdisp
.bitfield
.disp64
= 0;
8579 if (operand_type_all_zero (&bigdisp
))
8580 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8586 /* Return the active addressing mode, taking address override and
8587 registers forming the address into consideration. Update the
8588 address override prefix if necessary. */
8590 static enum flag_code
8591 i386_addressing_mode (void)
8593 enum flag_code addr_mode
;
8595 if (i
.prefix
[ADDR_PREFIX
])
8596 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8599 addr_mode
= flag_code
;
8601 #if INFER_ADDR_PREFIX
8602 if (i
.mem_operands
== 0)
8604 /* Infer address prefix from the first memory operand. */
8605 const reg_entry
*addr_reg
= i
.base_reg
;
8607 if (addr_reg
== NULL
)
8608 addr_reg
= i
.index_reg
;
8612 if (addr_reg
->reg_num
== RegEip
8613 || addr_reg
->reg_num
== RegEiz
8614 || addr_reg
->reg_type
.bitfield
.dword
)
8615 addr_mode
= CODE_32BIT
;
8616 else if (flag_code
!= CODE_64BIT
8617 && addr_reg
->reg_type
.bitfield
.word
)
8618 addr_mode
= CODE_16BIT
;
8620 if (addr_mode
!= flag_code
)
8622 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8624 /* Change the size of any displacement too. At most one
8625 of Disp16 or Disp32 is set.
8626 FIXME. There doesn't seem to be any real need for
8627 separate Disp16 and Disp32 flags. The same goes for
8628 Imm16 and Imm32. Removing them would probably clean
8629 up the code quite a lot. */
8630 if (flag_code
!= CODE_64BIT
8631 && (i
.types
[this_operand
].bitfield
.disp16
8632 || i
.types
[this_operand
].bitfield
.disp32
))
8633 i
.types
[this_operand
]
8634 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8644 /* Make sure the memory operand we've been dealt is valid.
8645 Return 1 on success, 0 on a failure. */
8648 i386_index_check (const char *operand_string
)
8650 const char *kind
= "base/index";
8651 enum flag_code addr_mode
= i386_addressing_mode ();
8653 if (current_templates
->start
->opcode_modifier
.isstring
8654 && !current_templates
->start
->opcode_modifier
.immext
8655 && (current_templates
->end
[-1].opcode_modifier
.isstring
8658 /* Memory operands of string insns are special in that they only allow
8659 a single register (rDI, rSI, or rBX) as their memory address. */
8660 const reg_entry
*expected_reg
;
8661 static const char *di_si
[][2] =
8667 static const char *bx
[] = { "ebx", "bx", "rbx" };
8669 kind
= "string address";
8671 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8673 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8675 if (!type
.bitfield
.baseindex
8676 || ((!i
.mem_operands
!= !intel_syntax
)
8677 && current_templates
->end
[-1].operand_types
[1]
8678 .bitfield
.baseindex
))
8679 type
= current_templates
->end
[-1].operand_types
[1];
8680 expected_reg
= hash_find (reg_hash
,
8681 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8685 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8687 if (i
.base_reg
!= expected_reg
8689 || operand_type_check (i
.types
[this_operand
], disp
))
8691 /* The second memory operand must have the same size as
8695 && !((addr_mode
== CODE_64BIT
8696 && i
.base_reg
->reg_type
.bitfield
.qword
)
8697 || (addr_mode
== CODE_32BIT
8698 ? i
.base_reg
->reg_type
.bitfield
.dword
8699 : i
.base_reg
->reg_type
.bitfield
.word
)))
8702 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8704 intel_syntax
? '[' : '(',
8706 expected_reg
->reg_name
,
8707 intel_syntax
? ']' : ')');
8714 as_bad (_("`%s' is not a valid %s expression"),
8715 operand_string
, kind
);
8720 if (addr_mode
!= CODE_16BIT
)
8722 /* 32-bit/64-bit checks. */
8724 && (addr_mode
== CODE_64BIT
8725 ? !i
.base_reg
->reg_type
.bitfield
.qword
8726 : !i
.base_reg
->reg_type
.bitfield
.dword
)
8728 || (i
.base_reg
->reg_num
8729 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8731 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8732 && !i
.index_reg
->reg_type
.bitfield
.regymm
8733 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8734 && ((addr_mode
== CODE_64BIT
8735 ? !(i
.index_reg
->reg_type
.bitfield
.qword
8736 || i
.index_reg
->reg_num
== RegRiz
)
8737 : !(i
.index_reg
->reg_type
.bitfield
.dword
8738 || i
.index_reg
->reg_num
== RegEiz
))
8739 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8742 /* bndmk, bndldx, and bndstx have special restrictions. */
8743 if (current_templates
->start
->base_opcode
== 0xf30f1b
8744 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8746 /* They cannot use RIP-relative addressing. */
8747 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8749 as_bad (_("`%s' cannot be used here"), operand_string
);
8753 /* bndldx and bndstx ignore their scale factor. */
8754 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8755 && i
.log2_scale_factor
)
8756 as_warn (_("register scaling is being ignored here"));
8761 /* 16-bit checks. */
8763 && (!i
.base_reg
->reg_type
.bitfield
.word
8764 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8766 && (!i
.index_reg
->reg_type
.bitfield
.word
8767 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8769 && i
.base_reg
->reg_num
< 6
8770 && i
.index_reg
->reg_num
>= 6
8771 && i
.log2_scale_factor
== 0))))
8778 /* Handle vector immediates. */
8781 RC_SAE_immediate (const char *imm_start
)
8783 unsigned int match_found
, j
;
8784 const char *pstr
= imm_start
;
8792 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8794 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8798 rc_op
.type
= RC_NamesTable
[j
].type
;
8799 rc_op
.operand
= this_operand
;
8800 i
.rounding
= &rc_op
;
8804 as_bad (_("duplicated `%s'"), imm_start
);
8807 pstr
+= RC_NamesTable
[j
].len
;
8817 as_bad (_("Missing '}': '%s'"), imm_start
);
8820 /* RC/SAE immediate string should contain nothing more. */;
8823 as_bad (_("Junk after '}': '%s'"), imm_start
);
8827 exp
= &im_expressions
[i
.imm_operands
++];
8828 i
.op
[this_operand
].imms
= exp
;
8830 exp
->X_op
= O_constant
;
8831 exp
->X_add_number
= 0;
8832 exp
->X_add_symbol
= (symbolS
*) 0;
8833 exp
->X_op_symbol
= (symbolS
*) 0;
8835 i
.types
[this_operand
].bitfield
.imm8
= 1;
8839 /* Only string instructions can have a second memory operand, so
8840 reduce current_templates to just those if it contains any. */
8842 maybe_adjust_templates (void)
8844 const insn_template
*t
;
8846 gas_assert (i
.mem_operands
== 1);
8848 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8849 if (t
->opcode_modifier
.isstring
)
8852 if (t
< current_templates
->end
)
8854 static templates aux_templates
;
8855 bfd_boolean recheck
;
8857 aux_templates
.start
= t
;
8858 for (; t
< current_templates
->end
; ++t
)
8859 if (!t
->opcode_modifier
.isstring
)
8861 aux_templates
.end
= t
;
8863 /* Determine whether to re-check the first memory operand. */
8864 recheck
= (aux_templates
.start
!= current_templates
->start
8865 || t
!= current_templates
->end
);
8867 current_templates
= &aux_templates
;
8872 if (i
.memop1_string
!= NULL
8873 && i386_index_check (i
.memop1_string
) == 0)
8882 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8886 i386_att_operand (char *operand_string
)
8890 char *op_string
= operand_string
;
8892 if (is_space_char (*op_string
))
8895 /* We check for an absolute prefix (differentiating,
8896 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8897 if (*op_string
== ABSOLUTE_PREFIX
)
8900 if (is_space_char (*op_string
))
8902 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8905 /* Check if operand is a register. */
8906 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8908 i386_operand_type temp
;
8910 /* Check for a segment override by searching for ':' after a
8911 segment register. */
8913 if (is_space_char (*op_string
))
8915 if (*op_string
== ':'
8916 && (r
->reg_type
.bitfield
.sreg2
8917 || r
->reg_type
.bitfield
.sreg3
))
8922 i
.seg
[i
.mem_operands
] = &es
;
8925 i
.seg
[i
.mem_operands
] = &cs
;
8928 i
.seg
[i
.mem_operands
] = &ss
;
8931 i
.seg
[i
.mem_operands
] = &ds
;
8934 i
.seg
[i
.mem_operands
] = &fs
;
8937 i
.seg
[i
.mem_operands
] = &gs
;
8941 /* Skip the ':' and whitespace. */
8943 if (is_space_char (*op_string
))
8946 if (!is_digit_char (*op_string
)
8947 && !is_identifier_char (*op_string
)
8948 && *op_string
!= '('
8949 && *op_string
!= ABSOLUTE_PREFIX
)
8951 as_bad (_("bad memory operand `%s'"), op_string
);
8954 /* Handle case of %es:*foo. */
8955 if (*op_string
== ABSOLUTE_PREFIX
)
8958 if (is_space_char (*op_string
))
8960 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8962 goto do_memory_reference
;
8965 /* Handle vector operations. */
8966 if (*op_string
== '{')
8968 op_string
= check_VecOperations (op_string
, NULL
);
8969 if (op_string
== NULL
)
8975 as_bad (_("junk `%s' after register"), op_string
);
8979 temp
.bitfield
.baseindex
= 0;
8980 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8982 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8983 i
.op
[this_operand
].regs
= r
;
8986 else if (*op_string
== REGISTER_PREFIX
)
8988 as_bad (_("bad register name `%s'"), op_string
);
8991 else if (*op_string
== IMMEDIATE_PREFIX
)
8994 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8996 as_bad (_("immediate operand illegal with absolute jump"));
8999 if (!i386_immediate (op_string
))
9002 else if (RC_SAE_immediate (operand_string
))
9004 /* If it is a RC or SAE immediate, do nothing. */
9007 else if (is_digit_char (*op_string
)
9008 || is_identifier_char (*op_string
)
9009 || *op_string
== '"'
9010 || *op_string
== '(')
9012 /* This is a memory reference of some sort. */
9015 /* Start and end of displacement string expression (if found). */
9016 char *displacement_string_start
;
9017 char *displacement_string_end
;
9020 do_memory_reference
:
9021 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9023 if ((i
.mem_operands
== 1
9024 && !current_templates
->start
->opcode_modifier
.isstring
)
9025 || i
.mem_operands
== 2)
9027 as_bad (_("too many memory references for `%s'"),
9028 current_templates
->start
->name
);
9032 /* Check for base index form. We detect the base index form by
9033 looking for an ')' at the end of the operand, searching
9034 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9036 base_string
= op_string
+ strlen (op_string
);
9038 /* Handle vector operations. */
9039 vop_start
= strchr (op_string
, '{');
9040 if (vop_start
&& vop_start
< base_string
)
9042 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9044 base_string
= vop_start
;
9048 if (is_space_char (*base_string
))
9051 /* If we only have a displacement, set-up for it to be parsed later. */
9052 displacement_string_start
= op_string
;
9053 displacement_string_end
= base_string
+ 1;
9055 if (*base_string
== ')')
9058 unsigned int parens_balanced
= 1;
9059 /* We've already checked that the number of left & right ()'s are
9060 equal, so this loop will not be infinite. */
9064 if (*base_string
== ')')
9066 if (*base_string
== '(')
9069 while (parens_balanced
);
9071 temp_string
= base_string
;
9073 /* Skip past '(' and whitespace. */
9075 if (is_space_char (*base_string
))
9078 if (*base_string
== ','
9079 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9082 displacement_string_end
= temp_string
;
9084 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9088 base_string
= end_op
;
9089 if (is_space_char (*base_string
))
9093 /* There may be an index reg or scale factor here. */
9094 if (*base_string
== ',')
9097 if (is_space_char (*base_string
))
9100 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9103 base_string
= end_op
;
9104 if (is_space_char (*base_string
))
9106 if (*base_string
== ',')
9109 if (is_space_char (*base_string
))
9112 else if (*base_string
!= ')')
9114 as_bad (_("expecting `,' or `)' "
9115 "after index register in `%s'"),
9120 else if (*base_string
== REGISTER_PREFIX
)
9122 end_op
= strchr (base_string
, ',');
9125 as_bad (_("bad register name `%s'"), base_string
);
9129 /* Check for scale factor. */
9130 if (*base_string
!= ')')
9132 char *end_scale
= i386_scale (base_string
);
9137 base_string
= end_scale
;
9138 if (is_space_char (*base_string
))
9140 if (*base_string
!= ')')
9142 as_bad (_("expecting `)' "
9143 "after scale factor in `%s'"),
9148 else if (!i
.index_reg
)
9150 as_bad (_("expecting index register or scale factor "
9151 "after `,'; got '%c'"),
9156 else if (*base_string
!= ')')
9158 as_bad (_("expecting `,' or `)' "
9159 "after base register in `%s'"),
9164 else if (*base_string
== REGISTER_PREFIX
)
9166 end_op
= strchr (base_string
, ',');
9169 as_bad (_("bad register name `%s'"), base_string
);
9174 /* If there's an expression beginning the operand, parse it,
9175 assuming displacement_string_start and
9176 displacement_string_end are meaningful. */
9177 if (displacement_string_start
!= displacement_string_end
)
9179 if (!i386_displacement (displacement_string_start
,
9180 displacement_string_end
))
9184 /* Special case for (%dx) while doing input/output op. */
9186 && operand_type_equal (&i
.base_reg
->reg_type
,
9187 ®16_inoutportreg
)
9189 && i
.log2_scale_factor
== 0
9190 && i
.seg
[i
.mem_operands
] == 0
9191 && !operand_type_check (i
.types
[this_operand
], disp
))
9193 i
.types
[this_operand
] = inoutportreg
;
9197 if (i386_index_check (operand_string
) == 0)
9199 i
.types
[this_operand
].bitfield
.mem
= 1;
9200 if (i
.mem_operands
== 0)
9201 i
.memop1_string
= xstrdup (operand_string
);
9206 /* It's not a memory operand; argh! */
9207 as_bad (_("invalid char %s beginning operand %d `%s'"),
9208 output_invalid (*op_string
),
9213 return 1; /* Normal return. */
9216 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9217 that an rs_machine_dependent frag may reach. */
9220 i386_frag_max_var (fragS
*frag
)
9222 /* The only relaxable frags are for jumps.
9223 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9224 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9225 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9230 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9232 /* STT_GNU_IFUNC symbol must go through PLT. */
9233 if ((symbol_get_bfdsym (fr_symbol
)->flags
9234 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9237 if (!S_IS_EXTERNAL (fr_symbol
))
9238 /* Symbol may be weak or local. */
9239 return !S_IS_WEAK (fr_symbol
);
9241 /* Global symbols with non-default visibility can't be preempted. */
9242 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9245 if (fr_var
!= NO_RELOC
)
9246 switch ((enum bfd_reloc_code_real
) fr_var
)
9248 case BFD_RELOC_386_PLT32
:
9249 case BFD_RELOC_X86_64_PLT32
:
9250 /* Symbol with PLT relocation may be preempted. */
9256 /* Global symbols with default visibility in a shared library may be
9257 preempted by another definition. */
9262 /* md_estimate_size_before_relax()
9264 Called just before relax() for rs_machine_dependent frags. The x86
9265 assembler uses these frags to handle variable size jump
9268 Any symbol that is now undefined will not become defined.
9269 Return the correct fr_subtype in the frag.
9270 Return the initial "guess for variable size of frag" to caller.
9271 The guess is actually the growth beyond the fixed part. Whatever
9272 we do to grow the fixed or variable part contributes to our
9276 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9278 /* We've already got fragP->fr_subtype right; all we have to do is
9279 check for un-relaxable symbols. On an ELF system, we can't relax
9280 an externally visible symbol, because it may be overridden by a
9282 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9285 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9288 #if defined (OBJ_COFF) && defined (TE_PE)
9289 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9290 && S_IS_WEAK (fragP
->fr_symbol
))
9294 /* Symbol is undefined in this segment, or we need to keep a
9295 reloc so that weak symbols can be overridden. */
9296 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9297 enum bfd_reloc_code_real reloc_type
;
9298 unsigned char *opcode
;
9301 if (fragP
->fr_var
!= NO_RELOC
)
9302 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9304 reloc_type
= BFD_RELOC_16_PCREL
;
9306 reloc_type
= BFD_RELOC_32_PCREL
;
9308 old_fr_fix
= fragP
->fr_fix
;
9309 opcode
= (unsigned char *) fragP
->fr_opcode
;
9311 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9314 /* Make jmp (0xeb) a (d)word displacement jump. */
9316 fragP
->fr_fix
+= size
;
9317 fix_new (fragP
, old_fr_fix
, size
,
9319 fragP
->fr_offset
, 1,
9325 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9327 /* Negate the condition, and branch past an
9328 unconditional jump. */
9331 /* Insert an unconditional jump. */
9333 /* We added two extra opcode bytes, and have a two byte
9335 fragP
->fr_fix
+= 2 + 2;
9336 fix_new (fragP
, old_fr_fix
+ 2, 2,
9338 fragP
->fr_offset
, 1,
9345 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9350 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9352 fragP
->fr_offset
, 1,
9354 fixP
->fx_signed
= 1;
9358 /* This changes the byte-displacement jump 0x7N
9359 to the (d)word-displacement jump 0x0f,0x8N. */
9360 opcode
[1] = opcode
[0] + 0x10;
9361 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9362 /* We've added an opcode byte. */
9363 fragP
->fr_fix
+= 1 + size
;
9364 fix_new (fragP
, old_fr_fix
+ 1, size
,
9366 fragP
->fr_offset
, 1,
9371 BAD_CASE (fragP
->fr_subtype
);
9375 return fragP
->fr_fix
- old_fr_fix
;
9378 /* Guess size depending on current relax state. Initially the relax
9379 state will correspond to a short jump and we return 1, because
9380 the variable part of the frag (the branch offset) is one byte
9381 long. However, we can relax a section more than once and in that
9382 case we must either set fr_subtype back to the unrelaxed state,
9383 or return the value for the appropriate branch. */
9384 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9387 /* Called after relax() is finished.
9389 In: Address of frag.
9390 fr_type == rs_machine_dependent.
9391 fr_subtype is what the address relaxed to.
9393 Out: Any fixSs and constants are set up.
9394 Caller will turn frag into a ".space 0". */
9397 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9400 unsigned char *opcode
;
9401 unsigned char *where_to_put_displacement
= NULL
;
9402 offsetT target_address
;
9403 offsetT opcode_address
;
9404 unsigned int extension
= 0;
9405 offsetT displacement_from_opcode_start
;
9407 opcode
= (unsigned char *) fragP
->fr_opcode
;
9409 /* Address we want to reach in file space. */
9410 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9412 /* Address opcode resides at in file space. */
9413 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9415 /* Displacement from opcode start to fill into instruction. */
9416 displacement_from_opcode_start
= target_address
- opcode_address
;
9418 if ((fragP
->fr_subtype
& BIG
) == 0)
9420 /* Don't have to change opcode. */
9421 extension
= 1; /* 1 opcode + 1 displacement */
9422 where_to_put_displacement
= &opcode
[1];
9426 if (no_cond_jump_promotion
9427 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9428 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9429 _("long jump required"));
9431 switch (fragP
->fr_subtype
)
9433 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9434 extension
= 4; /* 1 opcode + 4 displacement */
9436 where_to_put_displacement
= &opcode
[1];
9439 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9440 extension
= 2; /* 1 opcode + 2 displacement */
9442 where_to_put_displacement
= &opcode
[1];
9445 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9446 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9447 extension
= 5; /* 2 opcode + 4 displacement */
9448 opcode
[1] = opcode
[0] + 0x10;
9449 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9450 where_to_put_displacement
= &opcode
[2];
9453 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9454 extension
= 3; /* 2 opcode + 2 displacement */
9455 opcode
[1] = opcode
[0] + 0x10;
9456 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9457 where_to_put_displacement
= &opcode
[2];
9460 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9465 where_to_put_displacement
= &opcode
[3];
9469 BAD_CASE (fragP
->fr_subtype
);
9474 /* If size if less then four we are sure that the operand fits,
9475 but if it's 4, then it could be that the displacement is larger
9477 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9479 && ((addressT
) (displacement_from_opcode_start
- extension
9480 + ((addressT
) 1 << 31))
9481 > (((addressT
) 2 << 31) - 1)))
9483 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9484 _("jump target out of range"));
9485 /* Make us emit 0. */
9486 displacement_from_opcode_start
= extension
;
9488 /* Now put displacement after opcode. */
9489 md_number_to_chars ((char *) where_to_put_displacement
,
9490 (valueT
) (displacement_from_opcode_start
- extension
),
9491 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9492 fragP
->fr_fix
+= extension
;
9495 /* Apply a fixup (fixP) to segment data, once it has been determined
9496 by our caller that we have all the info we need to fix it up.
9498 Parameter valP is the pointer to the value of the bits.
9500 On the 386, immediates, displacements, and data pointers are all in
9501 the same (little-endian) format, so we don't need to care about which
9505 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9507 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9508 valueT value
= *valP
;
9510 #if !defined (TE_Mach)
9513 switch (fixP
->fx_r_type
)
9519 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9522 case BFD_RELOC_X86_64_32S
:
9523 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9526 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9529 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9534 if (fixP
->fx_addsy
!= NULL
9535 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9536 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9537 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9538 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9539 && !use_rela_relocations
)
9541 /* This is a hack. There should be a better way to handle this.
9542 This covers for the fact that bfd_install_relocation will
9543 subtract the current location (for partial_inplace, PC relative
9544 relocations); see more below. */
9548 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9551 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9556 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9559 || (symbol_section_p (fixP
->fx_addsy
)
9560 && sym_seg
!= absolute_section
))
9561 && !generic_force_reloc (fixP
))
9563 /* Yes, we add the values in twice. This is because
9564 bfd_install_relocation subtracts them out again. I think
9565 bfd_install_relocation is broken, but I don't dare change
9567 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9571 #if defined (OBJ_COFF) && defined (TE_PE)
9572 /* For some reason, the PE format does not store a
9573 section address offset for a PC relative symbol. */
9574 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9575 || S_IS_WEAK (fixP
->fx_addsy
))
9576 value
+= md_pcrel_from (fixP
);
9579 #if defined (OBJ_COFF) && defined (TE_PE)
9580 if (fixP
->fx_addsy
!= NULL
9581 && S_IS_WEAK (fixP
->fx_addsy
)
9582 /* PR 16858: Do not modify weak function references. */
9583 && ! fixP
->fx_pcrel
)
9585 #if !defined (TE_PEP)
9586 /* For x86 PE weak function symbols are neither PC-relative
9587 nor do they set S_IS_FUNCTION. So the only reliable way
9588 to detect them is to check the flags of their containing
9590 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9591 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9595 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9599 /* Fix a few things - the dynamic linker expects certain values here,
9600 and we must not disappoint it. */
9601 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9602 if (IS_ELF
&& fixP
->fx_addsy
)
9603 switch (fixP
->fx_r_type
)
9605 case BFD_RELOC_386_PLT32
:
9606 case BFD_RELOC_X86_64_PLT32
:
9607 /* Make the jump instruction point to the address of the operand. At
9608 runtime we merely add the offset to the actual PLT entry. */
9612 case BFD_RELOC_386_TLS_GD
:
9613 case BFD_RELOC_386_TLS_LDM
:
9614 case BFD_RELOC_386_TLS_IE_32
:
9615 case BFD_RELOC_386_TLS_IE
:
9616 case BFD_RELOC_386_TLS_GOTIE
:
9617 case BFD_RELOC_386_TLS_GOTDESC
:
9618 case BFD_RELOC_X86_64_TLSGD
:
9619 case BFD_RELOC_X86_64_TLSLD
:
9620 case BFD_RELOC_X86_64_GOTTPOFF
:
9621 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9622 value
= 0; /* Fully resolved at runtime. No addend. */
9624 case BFD_RELOC_386_TLS_LE
:
9625 case BFD_RELOC_386_TLS_LDO_32
:
9626 case BFD_RELOC_386_TLS_LE_32
:
9627 case BFD_RELOC_X86_64_DTPOFF32
:
9628 case BFD_RELOC_X86_64_DTPOFF64
:
9629 case BFD_RELOC_X86_64_TPOFF32
:
9630 case BFD_RELOC_X86_64_TPOFF64
:
9631 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9634 case BFD_RELOC_386_TLS_DESC_CALL
:
9635 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9636 value
= 0; /* Fully resolved at runtime. No addend. */
9637 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9641 case BFD_RELOC_VTABLE_INHERIT
:
9642 case BFD_RELOC_VTABLE_ENTRY
:
9649 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9651 #endif /* !defined (TE_Mach) */
9653 /* Are we finished with this relocation now? */
9654 if (fixP
->fx_addsy
== NULL
)
9656 #if defined (OBJ_COFF) && defined (TE_PE)
9657 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9660 /* Remember value for tc_gen_reloc. */
9661 fixP
->fx_addnumber
= value
;
9662 /* Clear out the frag for now. */
9666 else if (use_rela_relocations
)
9668 fixP
->fx_no_overflow
= 1;
9669 /* Remember value for tc_gen_reloc. */
9670 fixP
->fx_addnumber
= value
;
9674 md_number_to_chars (p
, value
, fixP
->fx_size
);
9678 md_atof (int type
, char *litP
, int *sizeP
)
9680 /* This outputs the LITTLENUMs in REVERSE order;
9681 in accord with the bigendian 386. */
9682 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9685 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9688 output_invalid (int c
)
9691 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9694 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9695 "(0x%x)", (unsigned char) c
);
9696 return output_invalid_buf
;
9699 /* REG_STRING starts *before* REGISTER_PREFIX. */
9701 static const reg_entry
*
9702 parse_real_register (char *reg_string
, char **end_op
)
9704 char *s
= reg_string
;
9706 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9709 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9710 if (*s
== REGISTER_PREFIX
)
9713 if (is_space_char (*s
))
9717 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9719 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9720 return (const reg_entry
*) NULL
;
9724 /* For naked regs, make sure that we are not dealing with an identifier.
9725 This prevents confusing an identifier like `eax_var' with register
9727 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9728 return (const reg_entry
*) NULL
;
9732 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9734 /* Handle floating point regs, allowing spaces in the (i) part. */
9735 if (r
== i386_regtab
/* %st is first entry of table */)
9737 if (is_space_char (*s
))
9742 if (is_space_char (*s
))
9744 if (*s
>= '0' && *s
<= '7')
9748 if (is_space_char (*s
))
9753 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9758 /* We have "%st(" then garbage. */
9759 return (const reg_entry
*) NULL
;
9763 if (r
== NULL
|| allow_pseudo_reg
)
9766 if (operand_type_all_zero (&r
->reg_type
))
9767 return (const reg_entry
*) NULL
;
9769 if ((r
->reg_type
.bitfield
.dword
9770 || r
->reg_type
.bitfield
.sreg3
9771 || r
->reg_type
.bitfield
.control
9772 || r
->reg_type
.bitfield
.debug
9773 || r
->reg_type
.bitfield
.test
)
9774 && !cpu_arch_flags
.bitfield
.cpui386
)
9775 return (const reg_entry
*) NULL
;
9777 if (r
->reg_type
.bitfield
.floatreg
9778 && !cpu_arch_flags
.bitfield
.cpu8087
9779 && !cpu_arch_flags
.bitfield
.cpu287
9780 && !cpu_arch_flags
.bitfield
.cpu387
)
9781 return (const reg_entry
*) NULL
;
9783 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9784 return (const reg_entry
*) NULL
;
9786 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9787 return (const reg_entry
*) NULL
;
9789 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9790 return (const reg_entry
*) NULL
;
9792 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9793 return (const reg_entry
*) NULL
;
9795 if (r
->reg_type
.bitfield
.regmask
9796 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9797 return (const reg_entry
*) NULL
;
9799 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9800 if (!allow_index_reg
9801 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9802 return (const reg_entry
*) NULL
;
9804 /* Upper 16 vector register is only available with VREX in 64bit
9806 if ((r
->reg_flags
& RegVRex
))
9808 if (i
.vec_encoding
== vex_encoding_default
)
9809 i
.vec_encoding
= vex_encoding_evex
;
9811 if (!cpu_arch_flags
.bitfield
.cpuvrex
9812 || i
.vec_encoding
!= vex_encoding_evex
9813 || flag_code
!= CODE_64BIT
)
9814 return (const reg_entry
*) NULL
;
9817 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9818 || r
->reg_type
.bitfield
.qword
)
9819 && (!cpu_arch_flags
.bitfield
.cpulm
9820 || !operand_type_equal (&r
->reg_type
, &control
))
9821 && flag_code
!= CODE_64BIT
)
9822 return (const reg_entry
*) NULL
;
9824 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9825 return (const reg_entry
*) NULL
;
9830 /* REG_STRING starts *before* REGISTER_PREFIX. */
9832 static const reg_entry
*
9833 parse_register (char *reg_string
, char **end_op
)
9837 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9838 r
= parse_real_register (reg_string
, end_op
);
9843 char *save
= input_line_pointer
;
9847 input_line_pointer
= reg_string
;
9848 c
= get_symbol_name (®_string
);
9849 symbolP
= symbol_find (reg_string
);
9850 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9852 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9854 know (e
->X_op
== O_register
);
9855 know (e
->X_add_number
>= 0
9856 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9857 r
= i386_regtab
+ e
->X_add_number
;
9858 if ((r
->reg_flags
& RegVRex
))
9859 i
.vec_encoding
= vex_encoding_evex
;
9860 *end_op
= input_line_pointer
;
9862 *input_line_pointer
= c
;
9863 input_line_pointer
= save
;
9869 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9872 char *end
= input_line_pointer
;
9875 r
= parse_register (name
, &input_line_pointer
);
9876 if (r
&& end
<= input_line_pointer
)
9878 *nextcharP
= *input_line_pointer
;
9879 *input_line_pointer
= 0;
9880 e
->X_op
= O_register
;
9881 e
->X_add_number
= r
- i386_regtab
;
9884 input_line_pointer
= end
;
9886 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9890 md_operand (expressionS
*e
)
9895 switch (*input_line_pointer
)
9897 case REGISTER_PREFIX
:
9898 r
= parse_real_register (input_line_pointer
, &end
);
9901 e
->X_op
= O_register
;
9902 e
->X_add_number
= r
- i386_regtab
;
9903 input_line_pointer
= end
;
9908 gas_assert (intel_syntax
);
9909 end
= input_line_pointer
++;
9911 if (*input_line_pointer
== ']')
9913 ++input_line_pointer
;
9914 e
->X_op_symbol
= make_expr_symbol (e
);
9915 e
->X_add_symbol
= NULL
;
9916 e
->X_add_number
= 0;
9922 input_line_pointer
= end
;
9929 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9930 const char *md_shortopts
= "kVQ:sqn";
9932 const char *md_shortopts
= "qn";
9935 #define OPTION_32 (OPTION_MD_BASE + 0)
9936 #define OPTION_64 (OPTION_MD_BASE + 1)
9937 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9938 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9939 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9940 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9941 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9942 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9943 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9944 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9945 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9946 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9947 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9948 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9949 #define OPTION_X32 (OPTION_MD_BASE + 14)
9950 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9951 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9952 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9953 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9954 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9955 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9956 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9957 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9958 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9959 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9960 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9962 struct option md_longopts
[] =
9964 {"32", no_argument
, NULL
, OPTION_32
},
9965 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9966 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9967 {"64", no_argument
, NULL
, OPTION_64
},
9969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9970 {"x32", no_argument
, NULL
, OPTION_X32
},
9971 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9973 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9974 {"march", required_argument
, NULL
, OPTION_MARCH
},
9975 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9976 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9977 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9978 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9979 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9980 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9981 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9982 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9983 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9984 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9985 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9986 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9987 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9988 # if defined (TE_PE) || defined (TE_PEP)
9989 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9991 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9992 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9993 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9994 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9995 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9996 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9997 {NULL
, no_argument
, NULL
, 0}
9999 size_t md_longopts_size
= sizeof (md_longopts
);
10002 md_parse_option (int c
, const char *arg
)
10005 char *arch
, *next
, *saved
;
10010 optimize_align_code
= 0;
10014 quiet_warnings
= 1;
10017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10018 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10019 should be emitted or not. FIXME: Not implemented. */
10023 /* -V: SVR4 argument to print version ID. */
10025 print_version_id ();
10028 /* -k: Ignore for FreeBSD compatibility. */
10033 /* -s: On i386 Solaris, this tells the native assembler to use
10034 .stab instead of .stab.excl. We always use .stab anyhow. */
10037 case OPTION_MSHARED
:
10041 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10042 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10045 const char **list
, **l
;
10047 list
= bfd_target_list ();
10048 for (l
= list
; *l
!= NULL
; l
++)
10049 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10050 || strcmp (*l
, "coff-x86-64") == 0
10051 || strcmp (*l
, "pe-x86-64") == 0
10052 || strcmp (*l
, "pei-x86-64") == 0
10053 || strcmp (*l
, "mach-o-x86-64") == 0)
10055 default_arch
= "x86_64";
10059 as_fatal (_("no compiled in support for x86_64"));
10065 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10069 const char **list
, **l
;
10071 list
= bfd_target_list ();
10072 for (l
= list
; *l
!= NULL
; l
++)
10073 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10075 default_arch
= "x86_64:32";
10079 as_fatal (_("no compiled in support for 32bit x86_64"));
10083 as_fatal (_("32bit x86_64 is only supported for ELF"));
10088 default_arch
= "i386";
10091 case OPTION_DIVIDE
:
10092 #ifdef SVR4_COMMENT_CHARS
10097 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10099 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10103 i386_comment_chars
= n
;
10109 saved
= xstrdup (arg
);
10111 /* Allow -march=+nosse. */
10117 as_fatal (_("invalid -march= option: `%s'"), arg
);
10118 next
= strchr (arch
, '+');
10121 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10123 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10126 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10129 cpu_arch_name
= cpu_arch
[j
].name
;
10130 cpu_sub_arch_name
= NULL
;
10131 cpu_arch_flags
= cpu_arch
[j
].flags
;
10132 cpu_arch_isa
= cpu_arch
[j
].type
;
10133 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10134 if (!cpu_arch_tune_set
)
10136 cpu_arch_tune
= cpu_arch_isa
;
10137 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10141 else if (*cpu_arch
[j
].name
== '.'
10142 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10144 /* ISA extension. */
10145 i386_cpu_flags flags
;
10147 flags
= cpu_flags_or (cpu_arch_flags
,
10148 cpu_arch
[j
].flags
);
10150 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10152 if (cpu_sub_arch_name
)
10154 char *name
= cpu_sub_arch_name
;
10155 cpu_sub_arch_name
= concat (name
,
10157 (const char *) NULL
);
10161 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10162 cpu_arch_flags
= flags
;
10163 cpu_arch_isa_flags
= flags
;
10169 if (j
>= ARRAY_SIZE (cpu_arch
))
10171 /* Disable an ISA extension. */
10172 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10173 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10175 i386_cpu_flags flags
;
10177 flags
= cpu_flags_and_not (cpu_arch_flags
,
10178 cpu_noarch
[j
].flags
);
10179 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10181 if (cpu_sub_arch_name
)
10183 char *name
= cpu_sub_arch_name
;
10184 cpu_sub_arch_name
= concat (arch
,
10185 (const char *) NULL
);
10189 cpu_sub_arch_name
= xstrdup (arch
);
10190 cpu_arch_flags
= flags
;
10191 cpu_arch_isa_flags
= flags
;
10196 if (j
>= ARRAY_SIZE (cpu_noarch
))
10197 j
= ARRAY_SIZE (cpu_arch
);
10200 if (j
>= ARRAY_SIZE (cpu_arch
))
10201 as_fatal (_("invalid -march= option: `%s'"), arg
);
10205 while (next
!= NULL
);
10211 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10212 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10214 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10216 cpu_arch_tune_set
= 1;
10217 cpu_arch_tune
= cpu_arch
[j
].type
;
10218 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10222 if (j
>= ARRAY_SIZE (cpu_arch
))
10223 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10226 case OPTION_MMNEMONIC
:
10227 if (strcasecmp (arg
, "att") == 0)
10228 intel_mnemonic
= 0;
10229 else if (strcasecmp (arg
, "intel") == 0)
10230 intel_mnemonic
= 1;
10232 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10235 case OPTION_MSYNTAX
:
10236 if (strcasecmp (arg
, "att") == 0)
10238 else if (strcasecmp (arg
, "intel") == 0)
10241 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10244 case OPTION_MINDEX_REG
:
10245 allow_index_reg
= 1;
10248 case OPTION_MNAKED_REG
:
10249 allow_naked_reg
= 1;
10252 case OPTION_MOLD_GCC
:
10256 case OPTION_MSSE2AVX
:
10260 case OPTION_MSSE_CHECK
:
10261 if (strcasecmp (arg
, "error") == 0)
10262 sse_check
= check_error
;
10263 else if (strcasecmp (arg
, "warning") == 0)
10264 sse_check
= check_warning
;
10265 else if (strcasecmp (arg
, "none") == 0)
10266 sse_check
= check_none
;
10268 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10271 case OPTION_MOPERAND_CHECK
:
10272 if (strcasecmp (arg
, "error") == 0)
10273 operand_check
= check_error
;
10274 else if (strcasecmp (arg
, "warning") == 0)
10275 operand_check
= check_warning
;
10276 else if (strcasecmp (arg
, "none") == 0)
10277 operand_check
= check_none
;
10279 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10282 case OPTION_MAVXSCALAR
:
10283 if (strcasecmp (arg
, "128") == 0)
10284 avxscalar
= vex128
;
10285 else if (strcasecmp (arg
, "256") == 0)
10286 avxscalar
= vex256
;
10288 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10291 case OPTION_MADD_BND_PREFIX
:
10292 add_bnd_prefix
= 1;
10295 case OPTION_MEVEXLIG
:
10296 if (strcmp (arg
, "128") == 0)
10297 evexlig
= evexl128
;
10298 else if (strcmp (arg
, "256") == 0)
10299 evexlig
= evexl256
;
10300 else if (strcmp (arg
, "512") == 0)
10301 evexlig
= evexl512
;
10303 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10306 case OPTION_MEVEXRCIG
:
10307 if (strcmp (arg
, "rne") == 0)
10309 else if (strcmp (arg
, "rd") == 0)
10311 else if (strcmp (arg
, "ru") == 0)
10313 else if (strcmp (arg
, "rz") == 0)
10316 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10319 case OPTION_MEVEXWIG
:
10320 if (strcmp (arg
, "0") == 0)
10322 else if (strcmp (arg
, "1") == 0)
10325 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10328 # if defined (TE_PE) || defined (TE_PEP)
10329 case OPTION_MBIG_OBJ
:
10334 case OPTION_MOMIT_LOCK_PREFIX
:
10335 if (strcasecmp (arg
, "yes") == 0)
10336 omit_lock_prefix
= 1;
10337 else if (strcasecmp (arg
, "no") == 0)
10338 omit_lock_prefix
= 0;
10340 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10343 case OPTION_MFENCE_AS_LOCK_ADD
:
10344 if (strcasecmp (arg
, "yes") == 0)
10346 else if (strcasecmp (arg
, "no") == 0)
10349 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10352 case OPTION_MRELAX_RELOCATIONS
:
10353 if (strcasecmp (arg
, "yes") == 0)
10354 generate_relax_relocations
= 1;
10355 else if (strcasecmp (arg
, "no") == 0)
10356 generate_relax_relocations
= 0;
10358 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10361 case OPTION_MAMD64
:
10365 case OPTION_MINTEL64
:
10375 #define MESSAGE_TEMPLATE \
10379 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10380 int *left_p
, const char *name
, int len
)
10382 int size
= sizeof (MESSAGE_TEMPLATE
);
10383 int left
= *left_p
;
10385 /* Reserve 2 spaces for ", " or ",\0" */
10388 /* Check if there is any room. */
10396 p
= mempcpy (p
, name
, len
);
10400 /* Output the current message now and start a new one. */
10403 fprintf (stream
, "%s\n", message
);
10405 left
= size
- (start
- message
) - len
- 2;
10407 gas_assert (left
>= 0);
10409 p
= mempcpy (p
, name
, len
);
10417 show_arch (FILE *stream
, int ext
, int check
)
10419 static char message
[] = MESSAGE_TEMPLATE
;
10420 char *start
= message
+ 27;
10422 int size
= sizeof (MESSAGE_TEMPLATE
);
10429 left
= size
- (start
- message
);
10430 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10432 /* Should it be skipped? */
10433 if (cpu_arch
[j
].skip
)
10436 name
= cpu_arch
[j
].name
;
10437 len
= cpu_arch
[j
].len
;
10440 /* It is an extension. Skip if we aren't asked to show it. */
10451 /* It is an processor. Skip if we show only extension. */
10454 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10456 /* It is an impossible processor - skip. */
10460 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10463 /* Display disabled extensions. */
10465 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10467 name
= cpu_noarch
[j
].name
;
10468 len
= cpu_noarch
[j
].len
;
10469 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10474 fprintf (stream
, "%s\n", message
);
10478 md_show_usage (FILE *stream
)
10480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10481 fprintf (stream
, _("\
10483 -V print assembler version number\n\
10486 fprintf (stream
, _("\
10487 -n Do not optimize code alignment\n\
10488 -q quieten some warnings\n"));
10489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10490 fprintf (stream
, _("\
10493 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10494 || defined (TE_PE) || defined (TE_PEP))
10495 fprintf (stream
, _("\
10496 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10498 #ifdef SVR4_COMMENT_CHARS
10499 fprintf (stream
, _("\
10500 --divide do not treat `/' as a comment character\n"));
10502 fprintf (stream
, _("\
10503 --divide ignored\n"));
10505 fprintf (stream
, _("\
10506 -march=CPU[,+EXTENSION...]\n\
10507 generate code for CPU and EXTENSION, CPU is one of:\n"));
10508 show_arch (stream
, 0, 1);
10509 fprintf (stream
, _("\
10510 EXTENSION is combination of:\n"));
10511 show_arch (stream
, 1, 0);
10512 fprintf (stream
, _("\
10513 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10514 show_arch (stream
, 0, 0);
10515 fprintf (stream
, _("\
10516 -msse2avx encode SSE instructions with VEX prefix\n"));
10517 fprintf (stream
, _("\
10518 -msse-check=[none|error|warning]\n\
10519 check SSE instructions\n"));
10520 fprintf (stream
, _("\
10521 -moperand-check=[none|error|warning]\n\
10522 check operand combinations for validity\n"));
10523 fprintf (stream
, _("\
10524 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10526 fprintf (stream
, _("\
10527 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10529 fprintf (stream
, _("\
10530 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10531 for EVEX.W bit ignored instructions\n"));
10532 fprintf (stream
, _("\
10533 -mevexrcig=[rne|rd|ru|rz]\n\
10534 encode EVEX instructions with specific EVEX.RC value\n\
10535 for SAE-only ignored instructions\n"));
10536 fprintf (stream
, _("\
10537 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10538 fprintf (stream
, _("\
10539 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10540 fprintf (stream
, _("\
10541 -mindex-reg support pseudo index registers\n"));
10542 fprintf (stream
, _("\
10543 -mnaked-reg don't require `%%' prefix for registers\n"));
10544 fprintf (stream
, _("\
10545 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10546 fprintf (stream
, _("\
10547 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10548 fprintf (stream
, _("\
10549 -mshared disable branch optimization for shared code\n"));
10550 # if defined (TE_PE) || defined (TE_PEP)
10551 fprintf (stream
, _("\
10552 -mbig-obj generate big object files\n"));
10554 fprintf (stream
, _("\
10555 -momit-lock-prefix=[no|yes]\n\
10556 strip all lock prefixes\n"));
10557 fprintf (stream
, _("\
10558 -mfence-as-lock-add=[no|yes]\n\
10559 encode lfence, mfence and sfence as\n\
10560 lock addl $0x0, (%%{re}sp)\n"));
10561 fprintf (stream
, _("\
10562 -mrelax-relocations=[no|yes]\n\
10563 generate relax relocations\n"));
10564 fprintf (stream
, _("\
10565 -mamd64 accept only AMD64 ISA\n"));
10566 fprintf (stream
, _("\
10567 -mintel64 accept only Intel64 ISA\n"));
10570 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10571 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10572 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10574 /* Pick the target format to use. */
10577 i386_target_format (void)
10579 if (!strncmp (default_arch
, "x86_64", 6))
10581 update_code_flag (CODE_64BIT
, 1);
10582 if (default_arch
[6] == '\0')
10583 x86_elf_abi
= X86_64_ABI
;
10585 x86_elf_abi
= X86_64_X32_ABI
;
10587 else if (!strcmp (default_arch
, "i386"))
10588 update_code_flag (CODE_32BIT
, 1);
10589 else if (!strcmp (default_arch
, "iamcu"))
10591 update_code_flag (CODE_32BIT
, 1);
10592 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10594 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10595 cpu_arch_name
= "iamcu";
10596 cpu_sub_arch_name
= NULL
;
10597 cpu_arch_flags
= iamcu_flags
;
10598 cpu_arch_isa
= PROCESSOR_IAMCU
;
10599 cpu_arch_isa_flags
= iamcu_flags
;
10600 if (!cpu_arch_tune_set
)
10602 cpu_arch_tune
= cpu_arch_isa
;
10603 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10606 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10607 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10611 as_fatal (_("unknown architecture"));
10613 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10614 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10615 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10616 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10618 switch (OUTPUT_FLAVOR
)
10620 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10621 case bfd_target_aout_flavour
:
10622 return AOUT_TARGET_FORMAT
;
10624 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10625 # if defined (TE_PE) || defined (TE_PEP)
10626 case bfd_target_coff_flavour
:
10627 if (flag_code
== CODE_64BIT
)
10628 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10631 # elif defined (TE_GO32)
10632 case bfd_target_coff_flavour
:
10633 return "coff-go32";
10635 case bfd_target_coff_flavour
:
10636 return "coff-i386";
10639 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10640 case bfd_target_elf_flavour
:
10642 const char *format
;
10644 switch (x86_elf_abi
)
10647 format
= ELF_TARGET_FORMAT
;
10650 use_rela_relocations
= 1;
10652 format
= ELF_TARGET_FORMAT64
;
10654 case X86_64_X32_ABI
:
10655 use_rela_relocations
= 1;
10657 disallow_64bit_reloc
= 1;
10658 format
= ELF_TARGET_FORMAT32
;
10661 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10663 if (x86_elf_abi
!= X86_64_ABI
)
10664 as_fatal (_("Intel L1OM is 64bit only"));
10665 return ELF_TARGET_L1OM_FORMAT
;
10667 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10669 if (x86_elf_abi
!= X86_64_ABI
)
10670 as_fatal (_("Intel K1OM is 64bit only"));
10671 return ELF_TARGET_K1OM_FORMAT
;
10673 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10675 if (x86_elf_abi
!= I386_ABI
)
10676 as_fatal (_("Intel MCU is 32bit only"));
10677 return ELF_TARGET_IAMCU_FORMAT
;
10683 #if defined (OBJ_MACH_O)
10684 case bfd_target_mach_o_flavour
:
10685 if (flag_code
== CODE_64BIT
)
10687 use_rela_relocations
= 1;
10689 return "mach-o-x86-64";
10692 return "mach-o-i386";
10700 #endif /* OBJ_MAYBE_ more than one */
10703 md_undefined_symbol (char *name
)
10705 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10706 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10707 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10708 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10712 if (symbol_find (name
))
10713 as_bad (_("GOT already in symbol table"));
10714 GOT_symbol
= symbol_new (name
, undefined_section
,
10715 (valueT
) 0, &zero_address_frag
);
10722 /* Round up a section size to the appropriate boundary. */
10725 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10727 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10728 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10730 /* For a.out, force the section size to be aligned. If we don't do
10731 this, BFD will align it for us, but it will not write out the
10732 final bytes of the section. This may be a bug in BFD, but it is
10733 easier to fix it here since that is how the other a.out targets
10737 align
= bfd_get_section_alignment (stdoutput
, segment
);
10738 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10745 /* On the i386, PC-relative offsets are relative to the start of the
10746 next instruction. That is, the address of the offset, plus its
10747 size, since the offset is always the last part of the insn. */
10750 md_pcrel_from (fixS
*fixP
)
10752 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10758 s_bss (int ignore ATTRIBUTE_UNUSED
)
10762 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10764 obj_elf_section_change_hook ();
10766 temp
= get_absolute_expression ();
10767 subseg_set (bss_section
, (subsegT
) temp
);
10768 demand_empty_rest_of_line ();
10774 i386_validate_fix (fixS
*fixp
)
10776 if (fixp
->fx_subsy
)
10778 if (fixp
->fx_subsy
== GOT_symbol
)
10780 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10784 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10785 if (fixp
->fx_tcbit2
)
10786 fixp
->fx_r_type
= (fixp
->fx_tcbit
10787 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10788 : BFD_RELOC_X86_64_GOTPCRELX
);
10791 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10796 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10798 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10800 fixp
->fx_subsy
= 0;
10803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10804 else if (!object_64bit
)
10806 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10807 && fixp
->fx_tcbit2
)
10808 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10814 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10817 bfd_reloc_code_real_type code
;
10819 switch (fixp
->fx_r_type
)
10821 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10822 case BFD_RELOC_SIZE32
:
10823 case BFD_RELOC_SIZE64
:
10824 if (S_IS_DEFINED (fixp
->fx_addsy
)
10825 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10827 /* Resolve size relocation against local symbol to size of
10828 the symbol plus addend. */
10829 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10830 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10831 && !fits_in_unsigned_long (value
))
10832 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10833 _("symbol size computation overflow"));
10834 fixp
->fx_addsy
= NULL
;
10835 fixp
->fx_subsy
= NULL
;
10836 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10840 /* Fall through. */
10842 case BFD_RELOC_X86_64_PLT32
:
10843 case BFD_RELOC_X86_64_GOT32
:
10844 case BFD_RELOC_X86_64_GOTPCREL
:
10845 case BFD_RELOC_X86_64_GOTPCRELX
:
10846 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10847 case BFD_RELOC_386_PLT32
:
10848 case BFD_RELOC_386_GOT32
:
10849 case BFD_RELOC_386_GOT32X
:
10850 case BFD_RELOC_386_GOTOFF
:
10851 case BFD_RELOC_386_GOTPC
:
10852 case BFD_RELOC_386_TLS_GD
:
10853 case BFD_RELOC_386_TLS_LDM
:
10854 case BFD_RELOC_386_TLS_LDO_32
:
10855 case BFD_RELOC_386_TLS_IE_32
:
10856 case BFD_RELOC_386_TLS_IE
:
10857 case BFD_RELOC_386_TLS_GOTIE
:
10858 case BFD_RELOC_386_TLS_LE_32
:
10859 case BFD_RELOC_386_TLS_LE
:
10860 case BFD_RELOC_386_TLS_GOTDESC
:
10861 case BFD_RELOC_386_TLS_DESC_CALL
:
10862 case BFD_RELOC_X86_64_TLSGD
:
10863 case BFD_RELOC_X86_64_TLSLD
:
10864 case BFD_RELOC_X86_64_DTPOFF32
:
10865 case BFD_RELOC_X86_64_DTPOFF64
:
10866 case BFD_RELOC_X86_64_GOTTPOFF
:
10867 case BFD_RELOC_X86_64_TPOFF32
:
10868 case BFD_RELOC_X86_64_TPOFF64
:
10869 case BFD_RELOC_X86_64_GOTOFF64
:
10870 case BFD_RELOC_X86_64_GOTPC32
:
10871 case BFD_RELOC_X86_64_GOT64
:
10872 case BFD_RELOC_X86_64_GOTPCREL64
:
10873 case BFD_RELOC_X86_64_GOTPC64
:
10874 case BFD_RELOC_X86_64_GOTPLT64
:
10875 case BFD_RELOC_X86_64_PLTOFF64
:
10876 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10877 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10878 case BFD_RELOC_RVA
:
10879 case BFD_RELOC_VTABLE_ENTRY
:
10880 case BFD_RELOC_VTABLE_INHERIT
:
10882 case BFD_RELOC_32_SECREL
:
10884 code
= fixp
->fx_r_type
;
10886 case BFD_RELOC_X86_64_32S
:
10887 if (!fixp
->fx_pcrel
)
10889 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10890 code
= fixp
->fx_r_type
;
10893 /* Fall through. */
10895 if (fixp
->fx_pcrel
)
10897 switch (fixp
->fx_size
)
10900 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10901 _("can not do %d byte pc-relative relocation"),
10903 code
= BFD_RELOC_32_PCREL
;
10905 case 1: code
= BFD_RELOC_8_PCREL
; break;
10906 case 2: code
= BFD_RELOC_16_PCREL
; break;
10907 case 4: code
= BFD_RELOC_32_PCREL
; break;
10909 case 8: code
= BFD_RELOC_64_PCREL
; break;
10915 switch (fixp
->fx_size
)
10918 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10919 _("can not do %d byte relocation"),
10921 code
= BFD_RELOC_32
;
10923 case 1: code
= BFD_RELOC_8
; break;
10924 case 2: code
= BFD_RELOC_16
; break;
10925 case 4: code
= BFD_RELOC_32
; break;
10927 case 8: code
= BFD_RELOC_64
; break;
10934 if ((code
== BFD_RELOC_32
10935 || code
== BFD_RELOC_32_PCREL
10936 || code
== BFD_RELOC_X86_64_32S
)
10938 && fixp
->fx_addsy
== GOT_symbol
)
10941 code
= BFD_RELOC_386_GOTPC
;
10943 code
= BFD_RELOC_X86_64_GOTPC32
;
10945 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10947 && fixp
->fx_addsy
== GOT_symbol
)
10949 code
= BFD_RELOC_X86_64_GOTPC64
;
10952 rel
= XNEW (arelent
);
10953 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10954 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10956 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10958 if (!use_rela_relocations
)
10960 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10961 vtable entry to be used in the relocation's section offset. */
10962 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10963 rel
->address
= fixp
->fx_offset
;
10964 #if defined (OBJ_COFF) && defined (TE_PE)
10965 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10966 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10971 /* Use the rela in 64bit mode. */
10974 if (disallow_64bit_reloc
)
10977 case BFD_RELOC_X86_64_DTPOFF64
:
10978 case BFD_RELOC_X86_64_TPOFF64
:
10979 case BFD_RELOC_64_PCREL
:
10980 case BFD_RELOC_X86_64_GOTOFF64
:
10981 case BFD_RELOC_X86_64_GOT64
:
10982 case BFD_RELOC_X86_64_GOTPCREL64
:
10983 case BFD_RELOC_X86_64_GOTPC64
:
10984 case BFD_RELOC_X86_64_GOTPLT64
:
10985 case BFD_RELOC_X86_64_PLTOFF64
:
10986 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10987 _("cannot represent relocation type %s in x32 mode"),
10988 bfd_get_reloc_code_name (code
));
10994 if (!fixp
->fx_pcrel
)
10995 rel
->addend
= fixp
->fx_offset
;
10999 case BFD_RELOC_X86_64_PLT32
:
11000 case BFD_RELOC_X86_64_GOT32
:
11001 case BFD_RELOC_X86_64_GOTPCREL
:
11002 case BFD_RELOC_X86_64_GOTPCRELX
:
11003 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11004 case BFD_RELOC_X86_64_TLSGD
:
11005 case BFD_RELOC_X86_64_TLSLD
:
11006 case BFD_RELOC_X86_64_GOTTPOFF
:
11007 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11008 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11009 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11012 rel
->addend
= (section
->vma
11014 + fixp
->fx_addnumber
11015 + md_pcrel_from (fixp
));
11020 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11021 if (rel
->howto
== NULL
)
11023 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11024 _("cannot represent relocation type %s"),
11025 bfd_get_reloc_code_name (code
));
11026 /* Set howto to a garbage value so that we can keep going. */
11027 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11028 gas_assert (rel
->howto
!= NULL
);
11034 #include "tc-i386-intel.c"
11037 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11039 int saved_naked_reg
;
11040 char saved_register_dot
;
11042 saved_naked_reg
= allow_naked_reg
;
11043 allow_naked_reg
= 1;
11044 saved_register_dot
= register_chars
['.'];
11045 register_chars
['.'] = '.';
11046 allow_pseudo_reg
= 1;
11047 expression_and_evaluate (exp
);
11048 allow_pseudo_reg
= 0;
11049 register_chars
['.'] = saved_register_dot
;
11050 allow_naked_reg
= saved_naked_reg
;
11052 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11054 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11056 exp
->X_op
= O_constant
;
11057 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11058 .dw2_regnum
[flag_code
>> 1];
11061 exp
->X_op
= O_illegal
;
11066 tc_x86_frame_initial_instructions (void)
11068 static unsigned int sp_regno
[2];
11070 if (!sp_regno
[flag_code
>> 1])
11072 char *saved_input
= input_line_pointer
;
11073 char sp
[][4] = {"esp", "rsp"};
11076 input_line_pointer
= sp
[flag_code
>> 1];
11077 tc_x86_parse_to_dw2regnum (&exp
);
11078 gas_assert (exp
.X_op
== O_constant
);
11079 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11080 input_line_pointer
= saved_input
;
11083 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11084 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11088 x86_dwarf2_addr_size (void)
11090 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11091 if (x86_elf_abi
== X86_64_X32_ABI
)
11094 return bfd_arch_bits_per_address (stdoutput
) / 8;
11098 i386_elf_section_type (const char *str
, size_t len
)
11100 if (flag_code
== CODE_64BIT
11101 && len
== sizeof ("unwind") - 1
11102 && strncmp (str
, "unwind", 6) == 0)
11103 return SHT_X86_64_UNWIND
;
11110 i386_solaris_fix_up_eh_frame (segT sec
)
11112 if (flag_code
== CODE_64BIT
)
11113 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11119 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11123 exp
.X_op
= O_secrel
;
11124 exp
.X_add_symbol
= symbol
;
11125 exp
.X_add_number
= 0;
11126 emit_expr (&exp
, size
);
11130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11131 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11134 x86_64_section_letter (int letter
, const char **ptr_msg
)
11136 if (flag_code
== CODE_64BIT
)
11139 return SHF_X86_64_LARGE
;
11141 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11144 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11149 x86_64_section_word (char *str
, size_t len
)
11151 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11152 return SHF_X86_64_LARGE
;
11158 handle_large_common (int small ATTRIBUTE_UNUSED
)
11160 if (flag_code
!= CODE_64BIT
)
11162 s_comm_internal (0, elf_common_parse
);
11163 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11167 static segT lbss_section
;
11168 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11169 asection
*saved_bss_section
= bss_section
;
11171 if (lbss_section
== NULL
)
11173 flagword applicable
;
11174 segT seg
= now_seg
;
11175 subsegT subseg
= now_subseg
;
11177 /* The .lbss section is for local .largecomm symbols. */
11178 lbss_section
= subseg_new (".lbss", 0);
11179 applicable
= bfd_applicable_section_flags (stdoutput
);
11180 bfd_set_section_flags (stdoutput
, lbss_section
,
11181 applicable
& SEC_ALLOC
);
11182 seg_info (lbss_section
)->bss
= 1;
11184 subseg_set (seg
, subseg
);
11187 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11188 bss_section
= lbss_section
;
11190 s_comm_internal (0, elf_common_parse
);
11192 elf_com_section_ptr
= saved_com_section_ptr
;
11193 bss_section
= saved_bss_section
;
11196 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */