1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
37 /* Default to compress debug sections for Linux. */
38 enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB
;
42 #ifndef REGISTER_WARNINGS
43 #define REGISTER_WARNINGS 1
46 #ifndef INFER_ADDR_PREFIX
47 #define INFER_ADDR_PREFIX 1
51 #define DEFAULT_ARCH "i386"
56 #define INLINE __inline__
62 /* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
72 #define HLE_PREFIX REP_PREFIX
73 #define BND_PREFIX REP_PREFIX
75 #define REX_PREFIX 6 /* must come last. */
76 #define MAX_PREFIXES 7 /* max prefixes per opcode */
78 /* we define the syntax here (modulo base,index,scale syntax) */
79 #define REGISTER_PREFIX '%'
80 #define IMMEDIATE_PREFIX '$'
81 #define ABSOLUTE_PREFIX '*'
83 /* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85 #define WORD_MNEM_SUFFIX 'w'
86 #define BYTE_MNEM_SUFFIX 'b'
87 #define SHORT_MNEM_SUFFIX 's'
88 #define LONG_MNEM_SUFFIX 'l'
89 #define QWORD_MNEM_SUFFIX 'q'
90 #define XMMWORD_MNEM_SUFFIX 'x'
91 #define YMMWORD_MNEM_SUFFIX 'y'
92 #define ZMMWORD_MNEM_SUFFIX 'z'
93 /* Intel Syntax. Use a non-ascii letter since since it never appears
95 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
97 #define END_OF_INSN '\0'
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
108 const insn_template
*start
;
109 const insn_template
*end
;
113 /* 386 operand encoding bytes: see 386 book for details of this. */
116 unsigned int regmem
; /* codes register or memory operand */
117 unsigned int reg
; /* codes register operand (or extended opcode) */
118 unsigned int mode
; /* how to interpret regmem & reg */
122 /* x86-64 extension prefix. */
123 typedef int rex_byte
;
125 /* 386 opcode byte to code indirect addressing. */
134 /* x86 arch names, types and features */
137 const char *name
; /* arch name */
138 unsigned int len
; /* arch string length */
139 enum processor_type type
; /* arch type */
140 i386_cpu_flags flags
; /* cpu feature flags */
141 unsigned int skip
; /* show_arch should skip this. */
142 unsigned int negated
; /* turn off indicated flags. */
146 static void update_code_flag (int, int);
147 static void set_code_flag (int);
148 static void set_16bit_gcc_code_flag (int);
149 static void set_intel_syntax (int);
150 static void set_intel_mnemonic (int);
151 static void set_allow_index_reg (int);
152 static void set_check (int);
153 static void set_cpu_arch (int);
155 static void pe_directive_secrel (int);
157 static void signed_cons (int);
158 static char *output_invalid (int c
);
159 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
161 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
163 static int i386_att_operand (char *);
164 static int i386_intel_operand (char *, int);
165 static int i386_intel_simplify (expressionS
*);
166 static int i386_intel_parse_name (const char *, expressionS
*);
167 static const reg_entry
*parse_register (char *, char **);
168 static char *parse_insn (char *, char *);
169 static char *parse_operands (char *, const char *);
170 static void swap_operands (void);
171 static void swap_2_operands (int, int);
172 static void optimize_imm (void);
173 static void optimize_disp (void);
174 static const insn_template
*match_template (void);
175 static int check_string (void);
176 static int process_suffix (void);
177 static int check_byte_reg (void);
178 static int check_long_reg (void);
179 static int check_qword_reg (void);
180 static int check_word_reg (void);
181 static int finalize_imm (void);
182 static int process_operands (void);
183 static const seg_entry
*build_modrm_byte (void);
184 static void output_insn (void);
185 static void output_imm (fragS
*, offsetT
);
186 static void output_disp (fragS
*, offsetT
);
188 static void s_bss (int);
190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
194 static const char *default_arch
= DEFAULT_ARCH
;
196 /* This struct describes rounding control and SAE in the instruction. */
210 static struct RC_Operation rc_op
;
212 /* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215 struct Mask_Operation
217 const reg_entry
*mask
;
218 unsigned int zeroing
;
219 /* The operand where this operation is associated. */
223 static struct Mask_Operation mask_op
;
225 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
227 struct Broadcast_Operation
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 /* Index of broadcasted operand. */
236 static struct Broadcast_Operation broadcast_op
;
241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes
[4];
244 /* Destination or source register specifier. */
245 const reg_entry
*register_specifier
;
248 /* 'md_assemble ()' gathers together information and puts it into a
255 const reg_entry
*regs
;
260 operand_size_mismatch
,
261 operand_type_mismatch
,
262 register_type_mismatch
,
263 number_of_operands_mismatch
,
264 invalid_instruction_suffix
,
267 unsupported_with_intel_mnemonic
,
270 invalid_vsib_address
,
271 invalid_vector_register_set
,
272 unsupported_vector_index_register
,
273 unsupported_broadcast
,
274 broadcast_not_on_src_operand
,
277 mask_not_on_destination
,
280 rc_sae_operand_not_last_imm
,
281 invalid_register_operand
,
287 /* TM holds the template for the insn were currently assembling. */
290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
294 /* OPERANDS gives the number of given operands. */
295 unsigned int operands
;
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
300 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
302 /* TYPES [i] is the type (see above #defines) which tells us how to
303 use OP[i] for the corresponding operand. */
304 i386_operand_type types
[MAX_OPERANDS
];
306 /* Displacement expression, immediate expression, or register for each
308 union i386_op op
[MAX_OPERANDS
];
310 /* Flags for operands. */
311 unsigned int flags
[MAX_OPERANDS
];
312 #define Operand_PCrel 1
314 /* Relocation type for operand */
315 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry
*base_reg
;
320 const reg_entry
*index_reg
;
321 unsigned int log2_scale_factor
;
323 /* SEG gives the seg_entries of this insn. They are zero unless
324 explicit segment overrides are given. */
325 const seg_entry
*seg
[2];
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Swap operand in encoding. */
353 unsigned int swap_operand
;
355 /* Prefer 8bit or 32bit displacement in encoding. */
358 disp_encoding_default
= 0,
364 const char *rep_prefix
;
367 const char *hle_prefix
;
369 /* Have BND prefix. */
370 const char *bnd_prefix
;
372 /* Need VREX to support upper 16 registers. */
376 enum i386_error error
;
379 typedef struct _i386_insn i386_insn
;
381 /* Link RC type with corresponding string, that'll be looked for in
390 static const struct RC_name RC_NamesTable
[] =
392 { rne
, STRING_COMMA_LEN ("rn-sae") },
393 { rd
, STRING_COMMA_LEN ("rd-sae") },
394 { ru
, STRING_COMMA_LEN ("ru-sae") },
395 { rz
, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly
, STRING_COMMA_LEN ("sae") },
399 /* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
401 const char extra_symbol_chars
[] = "*%-([{"
410 #if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
412 && !defined (TE_GNU) \
413 && !defined (TE_LINUX) \
414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
416 && !defined (TE_FreeBSD) \
417 && !defined (TE_DragonFly) \
418 && !defined (TE_NetBSD)))
419 /* This array holds the chars that always start a comment. If the
420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422 const char *i386_comment_chars
= "#/";
423 #define SVR4_COMMENT_CHARS 1
424 #define PREFIX_SEPARATOR '\\'
427 const char *i386_comment_chars
= "#";
428 #define PREFIX_SEPARATOR '/'
431 /* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
435 first line of the input file. This is because the compiler outputs
436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
438 '/' isn't otherwise defined. */
439 const char line_comment_chars
[] = "#/";
441 const char line_separator_chars
[] = ";";
443 /* Chars that can be used to separate mant from exp in floating point
445 const char EXP_CHARS
[] = "eE";
447 /* Chars that mean this number is a floating point constant
450 const char FLT_CHARS
[] = "fFdDxX";
452 /* Tables for lexical analysis. */
453 static char mnemonic_chars
[256];
454 static char register_chars
[256];
455 static char operand_chars
[256];
456 static char identifier_chars
[256];
457 static char digit_chars
[256];
459 /* Lexical macros. */
460 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461 #define is_operand_char(x) (operand_chars[(unsigned char) x])
462 #define is_register_char(x) (register_chars[(unsigned char) x])
463 #define is_space_char(x) ((x) == ' ')
464 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465 #define is_digit_char(x) (digit_chars[(unsigned char) x])
467 /* All non-digit non-letter characters that may occur in an operand. */
468 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
470 /* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
473 assembler instruction). */
474 static char save_stack
[32];
475 static char *save_stack_p
;
476 #define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478 #define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
481 /* The instruction we're assembling. */
484 /* Possible templates for current insn. */
485 static const templates
*current_templates
;
487 /* Per instruction expressionS buffers: max displacements & immediates. */
488 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
489 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
491 /* Current operand we are working on. */
492 static int this_operand
= -1;
494 /* We support four different modes. FLAG_CODE variable is used to distinguish
502 static enum flag_code flag_code
;
503 static unsigned int object_64bit
;
504 static unsigned int disallow_64bit_reloc
;
505 static int use_rela_relocations
= 0;
507 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
511 /* The ELF ABI to use. */
519 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
522 #if defined (TE_PE) || defined (TE_PEP)
523 /* Use big object file format. */
524 static int use_big_obj
= 0;
527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528 /* 1 if generating code for a shared library. */
529 static int shared
= 0;
532 /* 1 for intel syntax,
534 static int intel_syntax
= 0;
536 /* 1 for intel mnemonic,
537 0 if att mnemonic. */
538 static int intel_mnemonic
= !SYSV386_COMPAT
;
540 /* 1 if support old (<= 2.8.1) versions of gcc. */
541 static int old_gcc
= OLDGCC_COMPAT
;
543 /* 1 if pseudo registers are permitted. */
544 static int allow_pseudo_reg
= 0;
546 /* 1 if register prefix % not required. */
547 static int allow_naked_reg
= 0;
549 /* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
552 static int add_bnd_prefix
= 0;
554 /* 1 if pseudo index register, eiz/riz, is allowed . */
555 static int allow_index_reg
= 0;
557 /* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559 static int omit_lock_prefix
= 0;
561 static enum check_kind
567 sse_check
, operand_check
= check_warning
;
569 /* Register prefix used for error message. */
570 static const char *register_prefix
= "%";
572 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575 static char stackop_size
= '\0';
577 /* Non-zero to optimize code alignment. */
578 int optimize_align_code
= 1;
580 /* Non-zero to quieten some warnings. */
581 static int quiet_warnings
= 0;
584 static const char *cpu_arch_name
= NULL
;
585 static char *cpu_sub_arch_name
= NULL
;
587 /* CPU feature flags. */
588 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
590 /* If we have selected a cpu we are generating instructions for. */
591 static int cpu_arch_tune_set
= 0;
593 /* Cpu we are generating instructions for. */
594 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of cpu we are generating instructions for. */
597 static i386_cpu_flags cpu_arch_tune_flags
;
599 /* CPU instruction set architecture used. */
600 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
602 /* CPU feature flags of instruction set architecture used. */
603 i386_cpu_flags cpu_arch_isa_flags
;
605 /* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607 static unsigned int no_cond_jump_promotion
= 0;
609 /* Encode SSE instructions with VEX prefix. */
610 static unsigned int sse2avx
;
612 /* Encode scalar AVX instructions with specific vector length. */
619 /* Encode scalar EVEX LIG instructions with specific vector length. */
627 /* Encode EVEX WIG instructions with specific evex.w. */
634 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
635 static enum rc_type evexrcig
= rne
;
637 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
638 static symbolS
*GOT_symbol
;
640 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
641 unsigned int x86_dwarf2_return_column
;
643 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644 int x86_cie_data_alignment
;
646 /* Interface to relax_segment.
647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
652 #define UNCOND_JUMP 0
654 #define COND_JUMP86 2
659 #define SMALL16 (SMALL | CODE16)
661 #define BIG16 (BIG | CODE16)
665 #define INLINE __inline__
671 #define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673 #define TYPE_FROM_RELAX_STATE(s) \
675 #define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
678 /* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
686 const relax_typeS md_relax_table
[] =
689 1) most positive reach of this state,
690 2) most negative reach of this state,
691 3) how many bytes this mode will have in the variable part of the frag
692 4) which index into the table to try if we can't fit into this one. */
694 /* UNCOND_JUMP states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
710 /* word conditionals add 3 bytes to frag:
711 1 extra opcode byte, 2 displacement bytes. */
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
725 static const arch_entry cpu_arch
[] =
727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
730 CPU_GENERIC32_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
732 CPU_GENERIC64_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
734 CPU_NONE_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
736 CPU_I186_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
738 CPU_I286_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
740 CPU_I386_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
742 CPU_I486_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
744 CPU_I586_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
746 CPU_I686_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
748 CPU_I586_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
750 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
752 CPU_P2_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
754 CPU_P3_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
756 CPU_P4_FLAGS
, 0, 0 },
757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
760 CPU_NOCONA_FLAGS
, 0, 0 },
761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
762 CPU_CORE_FLAGS
, 1, 0 },
763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
764 CPU_CORE_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
766 CPU_CORE2_FLAGS
, 1, 0 },
767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
768 CPU_CORE2_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
770 CPU_COREI7_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
772 CPU_L1OM_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
774 CPU_K1OM_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
776 CPU_IAMCU_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
778 CPU_K6_FLAGS
, 0, 0 },
779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
780 CPU_K6_2_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
782 CPU_ATHLON_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
784 CPU_K8_FLAGS
, 1, 0 },
785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
786 CPU_K8_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
788 CPU_K8_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
790 CPU_AMDFAM10_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
792 CPU_BDVER1_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
794 CPU_BDVER2_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
796 CPU_BDVER3_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
798 CPU_BDVER4_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
800 CPU_ZNVER1_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
802 CPU_BTVER1_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
804 CPU_BTVER2_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
806 CPU_8087_FLAGS
, 0, 0 },
807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
808 CPU_287_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
810 CPU_387_FLAGS
, 0, 0 },
811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
812 CPU_ANY87_FLAGS
, 0, 1 },
813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
814 CPU_MMX_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
816 CPU_3DNOWA_FLAGS
, 0, 1 },
817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
818 CPU_SSE_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
820 CPU_SSE2_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
822 CPU_SSE3_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
824 CPU_SSSE3_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
826 CPU_SSE4_1_FLAGS
, 0, 0 },
827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
828 CPU_SSE4_2_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
830 CPU_SSE4_2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
832 CPU_ANY_SSE_FLAGS
, 0, 1 },
833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
834 CPU_AVX_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
836 CPU_AVX2_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512F_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512CD_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512ER_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512PF_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
846 CPU_AVX512DQ_FLAGS
, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
848 CPU_AVX512BW_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
850 CPU_AVX512VL_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
852 CPU_ANY_AVX_FLAGS
, 0, 1 },
853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
854 CPU_VMX_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
856 CPU_VMFUNC_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
858 CPU_SMX_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVE_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
862 CPU_XSAVEOPT_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
864 CPU_XSAVEC_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
866 CPU_XSAVES_FLAGS
, 0, 0 },
867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
868 CPU_AES_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
870 CPU_PCLMUL_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
872 CPU_PCLMUL_FLAGS
, 1, 0 },
873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
874 CPU_FSGSBASE_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
876 CPU_RDRND_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
878 CPU_F16C_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
880 CPU_BMI2_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
882 CPU_FMA_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
884 CPU_FMA4_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
886 CPU_XOP_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
888 CPU_LWP_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
890 CPU_MOVBE_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
892 CPU_CX16_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
894 CPU_EPT_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
896 CPU_LZCNT_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
898 CPU_HLE_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
900 CPU_RTM_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
902 CPU_INVPCID_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
904 CPU_CLFLUSH_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
906 CPU_NOP_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
908 CPU_SYSCALL_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
910 CPU_RDTSCP_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
912 CPU_3DNOW_FLAGS
, 0, 0 },
913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
914 CPU_3DNOWA_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
916 CPU_PADLOCK_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
918 CPU_SVME_FLAGS
, 1, 0 },
919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
920 CPU_SVME_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
922 CPU_SSE4A_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
924 CPU_ABM_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
926 CPU_BMI_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
928 CPU_TBM_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
930 CPU_ADX_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
932 CPU_RDSEED_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
934 CPU_PRFCHW_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
936 CPU_SMAP_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
938 CPU_MPX_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
940 CPU_SHA_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
942 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
944 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
946 CPU_SE1_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
948 CPU_CLWB_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
950 CPU_PCOMMIT_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
952 CPU_AVX512IFMA_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
954 CPU_AVX512VBMI_FLAGS
, 0, 0 },
955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
956 CPU_CLZERO_FLAGS
, 0, 0 },
960 /* Like s_lcomm_internal in gas/read.c but the alignment string
961 is allowed to be optional. */
964 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
971 && *input_line_pointer
== ',')
973 align
= parse_align (needs_align
- 1);
975 if (align
== (addressT
) -1)
990 bss_alloc (symbolP
, size
, align
);
995 pe_lcomm (int needs_align
)
997 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1001 const pseudo_typeS md_pseudo_table
[] =
1003 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1004 {"align", s_align_bytes
, 0},
1006 {"align", s_align_ptwo
, 0},
1008 {"arch", set_cpu_arch
, 0},
1012 {"lcomm", pe_lcomm
, 1},
1014 {"ffloat", float_cons
, 'f'},
1015 {"dfloat", float_cons
, 'd'},
1016 {"tfloat", float_cons
, 'x'},
1018 {"slong", signed_cons
, 4},
1019 {"noopt", s_ignore
, 0},
1020 {"optim", s_ignore
, 0},
1021 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1022 {"code16", set_code_flag
, CODE_16BIT
},
1023 {"code32", set_code_flag
, CODE_32BIT
},
1024 {"code64", set_code_flag
, CODE_64BIT
},
1025 {"intel_syntax", set_intel_syntax
, 1},
1026 {"att_syntax", set_intel_syntax
, 0},
1027 {"intel_mnemonic", set_intel_mnemonic
, 1},
1028 {"att_mnemonic", set_intel_mnemonic
, 0},
1029 {"allow_index_reg", set_allow_index_reg
, 1},
1030 {"disallow_index_reg", set_allow_index_reg
, 0},
1031 {"sse_check", set_check
, 0},
1032 {"operand_check", set_check
, 1},
1033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1034 {"largecomm", handle_large_common
, 0},
1036 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1037 {"loc", dwarf2_directive_loc
, 0},
1038 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1041 {"secrel32", pe_directive_secrel
, 0},
1046 /* For interface with expression (). */
1047 extern char *input_line_pointer
;
1049 /* Hash table for instruction mnemonic lookup. */
1050 static struct hash_control
*op_hash
;
1052 /* Hash table for register lookup. */
1053 static struct hash_control
*reg_hash
;
1056 i386_align_code (fragS
*fragP
, int count
)
1058 /* Various efficient no-op patterns for aligning code labels.
1059 Note: Don't try to assemble the instructions in the comments.
1060 0L and 0w are not legal. */
1061 static const char f32_1
[] =
1063 static const char f32_2
[] =
1064 {0x66,0x90}; /* xchg %ax,%ax */
1065 static const char f32_3
[] =
1066 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1067 static const char f32_4
[] =
1068 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1069 static const char f32_5
[] =
1071 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1072 static const char f32_6
[] =
1073 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1074 static const char f32_7
[] =
1075 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1076 static const char f32_8
[] =
1078 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1079 static const char f32_9
[] =
1080 {0x89,0xf6, /* movl %esi,%esi */
1081 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1082 static const char f32_10
[] =
1083 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1084 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1085 static const char f32_11
[] =
1086 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1087 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1088 static const char f32_12
[] =
1089 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1090 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1091 static const char f32_13
[] =
1092 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1093 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1094 static const char f32_14
[] =
1095 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1096 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1097 static const char f16_3
[] =
1098 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1099 static const char f16_4
[] =
1100 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1101 static const char f16_5
[] =
1103 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1104 static const char f16_6
[] =
1105 {0x89,0xf6, /* mov %si,%si */
1106 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1107 static const char f16_7
[] =
1108 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1109 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1110 static const char f16_8
[] =
1111 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1112 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1113 static const char jump_31
[] =
1114 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1115 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1116 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1118 static const char *const f32_patt
[] = {
1119 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1120 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1122 static const char *const f16_patt
[] = {
1123 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1125 /* nopl (%[re]ax) */
1126 static const char alt_3
[] =
1128 /* nopl 0(%[re]ax) */
1129 static const char alt_4
[] =
1130 {0x0f,0x1f,0x40,0x00};
1131 /* nopl 0(%[re]ax,%[re]ax,1) */
1132 static const char alt_5
[] =
1133 {0x0f,0x1f,0x44,0x00,0x00};
1134 /* nopw 0(%[re]ax,%[re]ax,1) */
1135 static const char alt_6
[] =
1136 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1137 /* nopl 0L(%[re]ax) */
1138 static const char alt_7
[] =
1139 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1140 /* nopl 0L(%[re]ax,%[re]ax,1) */
1141 static const char alt_8
[] =
1142 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1143 /* nopw 0L(%[re]ax,%[re]ax,1) */
1144 static const char alt_9
[] =
1145 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1146 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1147 static const char alt_10
[] =
1148 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 static const char *const alt_patt
[] = {
1150 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1154 /* Only align for at least a positive non-zero boundary. */
1155 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1158 /* We need to decide which NOP sequence to use for 32bit and
1159 64bit. When -mtune= is used:
1161 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1162 PROCESSOR_GENERIC32, f32_patt will be used.
1163 2. For the rest, alt_patt will be used.
1165 When -mtune= isn't used, alt_patt will be used if
1166 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1169 When -march= or .arch is used, we can't use anything beyond
1170 cpu_arch_isa_flags. */
1172 if (flag_code
== CODE_16BIT
)
1176 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1178 /* Adjust jump offset. */
1179 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1182 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1183 f16_patt
[count
- 1], count
);
1187 const char *const *patt
= NULL
;
1189 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1191 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1192 switch (cpu_arch_tune
)
1194 case PROCESSOR_UNKNOWN
:
1195 /* We use cpu_arch_isa_flags to check if we SHOULD
1196 optimize with nops. */
1197 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1202 case PROCESSOR_PENTIUM4
:
1203 case PROCESSOR_NOCONA
:
1204 case PROCESSOR_CORE
:
1205 case PROCESSOR_CORE2
:
1206 case PROCESSOR_COREI7
:
1207 case PROCESSOR_L1OM
:
1208 case PROCESSOR_K1OM
:
1209 case PROCESSOR_GENERIC64
:
1211 case PROCESSOR_ATHLON
:
1213 case PROCESSOR_AMDFAM10
:
1215 case PROCESSOR_ZNVER
:
1219 case PROCESSOR_I386
:
1220 case PROCESSOR_I486
:
1221 case PROCESSOR_PENTIUM
:
1222 case PROCESSOR_PENTIUMPRO
:
1223 case PROCESSOR_IAMCU
:
1224 case PROCESSOR_GENERIC32
:
1231 switch (fragP
->tc_frag_data
.tune
)
1233 case PROCESSOR_UNKNOWN
:
1234 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1235 PROCESSOR_UNKNOWN. */
1239 case PROCESSOR_I386
:
1240 case PROCESSOR_I486
:
1241 case PROCESSOR_PENTIUM
:
1242 case PROCESSOR_IAMCU
:
1244 case PROCESSOR_ATHLON
:
1246 case PROCESSOR_AMDFAM10
:
1248 case PROCESSOR_ZNVER
:
1250 case PROCESSOR_GENERIC32
:
1251 /* We use cpu_arch_isa_flags to check if we CAN optimize
1253 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1258 case PROCESSOR_PENTIUMPRO
:
1259 case PROCESSOR_PENTIUM4
:
1260 case PROCESSOR_NOCONA
:
1261 case PROCESSOR_CORE
:
1262 case PROCESSOR_CORE2
:
1263 case PROCESSOR_COREI7
:
1264 case PROCESSOR_L1OM
:
1265 case PROCESSOR_K1OM
:
1266 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1271 case PROCESSOR_GENERIC64
:
1277 if (patt
== f32_patt
)
1279 /* If the padding is less than 15 bytes, we use the normal
1280 ones. Otherwise, we use a jump instruction and adjust
1284 /* For 64bit, the limit is 3 bytes. */
1285 if (flag_code
== CODE_64BIT
1286 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1291 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1292 patt
[count
- 1], count
);
1295 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1297 /* Adjust jump offset. */
1298 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1303 /* Maximum length of an instruction is 10 byte. If the
1304 padding is greater than 10 bytes and we don't use jump,
1305 we have to break it into smaller pieces. */
1306 int padding
= count
;
1307 while (padding
> 10)
1310 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1315 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1316 patt
[padding
- 1], padding
);
1319 fragP
->fr_var
= count
;
1323 operand_type_all_zero (const union i386_operand_type
*x
)
1325 switch (ARRAY_SIZE(x
->array
))
1334 return !x
->array
[0];
1341 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1343 switch (ARRAY_SIZE(x
->array
))
1358 operand_type_equal (const union i386_operand_type
*x
,
1359 const union i386_operand_type
*y
)
1361 switch (ARRAY_SIZE(x
->array
))
1364 if (x
->array
[2] != y
->array
[2])
1367 if (x
->array
[1] != y
->array
[1])
1370 return x
->array
[0] == y
->array
[0];
1378 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1380 switch (ARRAY_SIZE(x
->array
))
1389 return !x
->array
[0];
1396 cpu_flags_equal (const union i386_cpu_flags
*x
,
1397 const union i386_cpu_flags
*y
)
1399 switch (ARRAY_SIZE(x
->array
))
1402 if (x
->array
[2] != y
->array
[2])
1405 if (x
->array
[1] != y
->array
[1])
1408 return x
->array
[0] == y
->array
[0];
1416 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1418 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1419 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1422 static INLINE i386_cpu_flags
1423 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1425 switch (ARRAY_SIZE (x
.array
))
1428 x
.array
[2] &= y
.array
[2];
1430 x
.array
[1] &= y
.array
[1];
1432 x
.array
[0] &= y
.array
[0];
1440 static INLINE i386_cpu_flags
1441 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1443 switch (ARRAY_SIZE (x
.array
))
1446 x
.array
[2] |= y
.array
[2];
1448 x
.array
[1] |= y
.array
[1];
1450 x
.array
[0] |= y
.array
[0];
1458 static INLINE i386_cpu_flags
1459 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1461 switch (ARRAY_SIZE (x
.array
))
1464 x
.array
[2] &= ~y
.array
[2];
1466 x
.array
[1] &= ~y
.array
[1];
1468 x
.array
[0] &= ~y
.array
[0];
1477 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1479 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1481 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1482 i386_cpu_flags compat_flags
;
1483 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1484 return cpu_flags_all_zero (&compat_flags
);
1490 #define CPU_FLAGS_ARCH_MATCH 0x1
1491 #define CPU_FLAGS_64BIT_MATCH 0x2
1492 #define CPU_FLAGS_AES_MATCH 0x4
1493 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1494 #define CPU_FLAGS_AVX_MATCH 0x10
1496 #define CPU_FLAGS_32BIT_MATCH \
1497 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1498 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1499 #define CPU_FLAGS_PERFECT_MATCH \
1500 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1502 /* Return CPU flags match bits. */
1505 cpu_flags_match (const insn_template
*t
)
1507 i386_cpu_flags x
= t
->cpu_flags
;
1508 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1510 x
.bitfield
.cpu64
= 0;
1511 x
.bitfield
.cpuno64
= 0;
1513 if (cpu_flags_all_zero (&x
))
1515 /* This instruction is available on all archs. */
1516 match
|= CPU_FLAGS_32BIT_MATCH
;
1520 /* This instruction is available only on some archs. */
1521 i386_cpu_flags cpu
= cpu_arch_flags
;
1523 cpu
.bitfield
.cpu64
= 0;
1524 cpu
.bitfield
.cpuno64
= 0;
1525 cpu
= cpu_flags_and (x
, cpu
);
1526 if (!cpu_flags_all_zero (&cpu
))
1528 if (x
.bitfield
.cpuavx
)
1530 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1531 if (cpu
.bitfield
.cpuavx
)
1533 /* Check SSE2AVX. */
1534 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1536 match
|= (CPU_FLAGS_ARCH_MATCH
1537 | CPU_FLAGS_AVX_MATCH
);
1539 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1540 match
|= CPU_FLAGS_AES_MATCH
;
1542 if (!x
.bitfield
.cpupclmul
1543 || cpu
.bitfield
.cpupclmul
)
1544 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1548 match
|= CPU_FLAGS_ARCH_MATCH
;
1551 match
|= CPU_FLAGS_32BIT_MATCH
;
1557 static INLINE i386_operand_type
1558 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1560 switch (ARRAY_SIZE (x
.array
))
1563 x
.array
[2] &= y
.array
[2];
1565 x
.array
[1] &= y
.array
[1];
1567 x
.array
[0] &= y
.array
[0];
1575 static INLINE i386_operand_type
1576 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1578 switch (ARRAY_SIZE (x
.array
))
1581 x
.array
[2] |= y
.array
[2];
1583 x
.array
[1] |= y
.array
[1];
1585 x
.array
[0] |= y
.array
[0];
1593 static INLINE i386_operand_type
1594 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1596 switch (ARRAY_SIZE (x
.array
))
1599 x
.array
[2] ^= y
.array
[2];
1601 x
.array
[1] ^= y
.array
[1];
1603 x
.array
[0] ^= y
.array
[0];
1611 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1612 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1613 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1614 static const i386_operand_type inoutportreg
1615 = OPERAND_TYPE_INOUTPORTREG
;
1616 static const i386_operand_type reg16_inoutportreg
1617 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1618 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1619 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1620 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1621 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1622 static const i386_operand_type anydisp
1623 = OPERAND_TYPE_ANYDISP
;
1624 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1625 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1626 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1627 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1628 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1629 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1630 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1631 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1632 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1633 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1634 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1635 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1636 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1637 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1648 operand_type_check (i386_operand_type t
, enum operand_type c
)
1653 return (t
.bitfield
.reg8
1656 || t
.bitfield
.reg64
);
1659 return (t
.bitfield
.imm8
1663 || t
.bitfield
.imm32s
1664 || t
.bitfield
.imm64
);
1667 return (t
.bitfield
.disp8
1668 || t
.bitfield
.disp16
1669 || t
.bitfield
.disp32
1670 || t
.bitfield
.disp32s
1671 || t
.bitfield
.disp64
);
1674 return (t
.bitfield
.disp8
1675 || t
.bitfield
.disp16
1676 || t
.bitfield
.disp32
1677 || t
.bitfield
.disp32s
1678 || t
.bitfield
.disp64
1679 || t
.bitfield
.baseindex
);
1688 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1689 operand J for instruction template T. */
1692 match_reg_size (const insn_template
*t
, unsigned int j
)
1694 return !((i
.types
[j
].bitfield
.byte
1695 && !t
->operand_types
[j
].bitfield
.byte
)
1696 || (i
.types
[j
].bitfield
.word
1697 && !t
->operand_types
[j
].bitfield
.word
)
1698 || (i
.types
[j
].bitfield
.dword
1699 && !t
->operand_types
[j
].bitfield
.dword
)
1700 || (i
.types
[j
].bitfield
.qword
1701 && !t
->operand_types
[j
].bitfield
.qword
));
1704 /* Return 1 if there is no conflict in any size on operand J for
1705 instruction template T. */
1708 match_mem_size (const insn_template
*t
, unsigned int j
)
1710 return (match_reg_size (t
, j
)
1711 && !((i
.types
[j
].bitfield
.unspecified
1713 && !t
->operand_types
[j
].bitfield
.unspecified
)
1714 || (i
.types
[j
].bitfield
.fword
1715 && !t
->operand_types
[j
].bitfield
.fword
)
1716 || (i
.types
[j
].bitfield
.tbyte
1717 && !t
->operand_types
[j
].bitfield
.tbyte
)
1718 || (i
.types
[j
].bitfield
.xmmword
1719 && !t
->operand_types
[j
].bitfield
.xmmword
)
1720 || (i
.types
[j
].bitfield
.ymmword
1721 && !t
->operand_types
[j
].bitfield
.ymmword
)
1722 || (i
.types
[j
].bitfield
.zmmword
1723 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1726 /* Return 1 if there is no size conflict on any operands for
1727 instruction template T. */
1730 operand_size_match (const insn_template
*t
)
1735 /* Don't check jump instructions. */
1736 if (t
->opcode_modifier
.jump
1737 || t
->opcode_modifier
.jumpbyte
1738 || t
->opcode_modifier
.jumpdword
1739 || t
->opcode_modifier
.jumpintersegment
)
1742 /* Check memory and accumulator operand size. */
1743 for (j
= 0; j
< i
.operands
; j
++)
1745 if (t
->operand_types
[j
].bitfield
.anysize
)
1748 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1754 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1763 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1766 i
.error
= operand_size_mismatch
;
1770 /* Check reverse. */
1771 gas_assert (i
.operands
== 2);
1774 for (j
= 0; j
< 2; j
++)
1776 if (t
->operand_types
[j
].bitfield
.acc
1777 && !match_reg_size (t
, j
? 0 : 1))
1780 if (i
.types
[j
].bitfield
.mem
1781 && !match_mem_size (t
, j
? 0 : 1))
1789 operand_type_match (i386_operand_type overlap
,
1790 i386_operand_type given
)
1792 i386_operand_type temp
= overlap
;
1794 temp
.bitfield
.jumpabsolute
= 0;
1795 temp
.bitfield
.unspecified
= 0;
1796 temp
.bitfield
.byte
= 0;
1797 temp
.bitfield
.word
= 0;
1798 temp
.bitfield
.dword
= 0;
1799 temp
.bitfield
.fword
= 0;
1800 temp
.bitfield
.qword
= 0;
1801 temp
.bitfield
.tbyte
= 0;
1802 temp
.bitfield
.xmmword
= 0;
1803 temp
.bitfield
.ymmword
= 0;
1804 temp
.bitfield
.zmmword
= 0;
1805 if (operand_type_all_zero (&temp
))
1808 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1809 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1813 i
.error
= operand_type_mismatch
;
1817 /* If given types g0 and g1 are registers they must be of the same type
1818 unless the expected operand type register overlap is null.
1819 Note that Acc in a template matches every size of reg. */
1822 operand_type_register_match (i386_operand_type m0
,
1823 i386_operand_type g0
,
1824 i386_operand_type t0
,
1825 i386_operand_type m1
,
1826 i386_operand_type g1
,
1827 i386_operand_type t1
)
1829 if (!operand_type_check (g0
, reg
))
1832 if (!operand_type_check (g1
, reg
))
1835 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1836 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1837 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1838 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1841 if (m0
.bitfield
.acc
)
1843 t0
.bitfield
.reg8
= 1;
1844 t0
.bitfield
.reg16
= 1;
1845 t0
.bitfield
.reg32
= 1;
1846 t0
.bitfield
.reg64
= 1;
1849 if (m1
.bitfield
.acc
)
1851 t1
.bitfield
.reg8
= 1;
1852 t1
.bitfield
.reg16
= 1;
1853 t1
.bitfield
.reg32
= 1;
1854 t1
.bitfield
.reg64
= 1;
1857 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1858 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1859 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1860 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1863 i
.error
= register_type_mismatch
;
1868 static INLINE
unsigned int
1869 register_number (const reg_entry
*r
)
1871 unsigned int nr
= r
->reg_num
;
1873 if (r
->reg_flags
& RegRex
)
1879 static INLINE
unsigned int
1880 mode_from_disp_size (i386_operand_type t
)
1882 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1884 else if (t
.bitfield
.disp16
1885 || t
.bitfield
.disp32
1886 || t
.bitfield
.disp32s
)
1893 fits_in_signed_byte (addressT num
)
1895 return num
+ 0x80 <= 0xff;
1899 fits_in_unsigned_byte (addressT num
)
1905 fits_in_unsigned_word (addressT num
)
1907 return num
<= 0xffff;
1911 fits_in_signed_word (addressT num
)
1913 return num
+ 0x8000 <= 0xffff;
1917 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1922 return num
+ 0x80000000 <= 0xffffffff;
1924 } /* fits_in_signed_long() */
1927 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1932 return num
<= 0xffffffff;
1934 } /* fits_in_unsigned_long() */
1937 fits_in_vec_disp8 (offsetT num
)
1939 int shift
= i
.memshift
;
1945 mask
= (1 << shift
) - 1;
1947 /* Return 0 if NUM isn't properly aligned. */
1951 /* Check if NUM will fit in 8bit after shift. */
1952 return fits_in_signed_byte (num
>> shift
);
1956 fits_in_imm4 (offsetT num
)
1958 return (num
& 0xf) == num
;
1961 static i386_operand_type
1962 smallest_imm_type (offsetT num
)
1964 i386_operand_type t
;
1966 operand_type_set (&t
, 0);
1967 t
.bitfield
.imm64
= 1;
1969 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1971 /* This code is disabled on the 486 because all the Imm1 forms
1972 in the opcode table are slower on the i486. They're the
1973 versions with the implicitly specified single-position
1974 displacement, which has another syntax if you really want to
1976 t
.bitfield
.imm1
= 1;
1977 t
.bitfield
.imm8
= 1;
1978 t
.bitfield
.imm8s
= 1;
1979 t
.bitfield
.imm16
= 1;
1980 t
.bitfield
.imm32
= 1;
1981 t
.bitfield
.imm32s
= 1;
1983 else if (fits_in_signed_byte (num
))
1985 t
.bitfield
.imm8
= 1;
1986 t
.bitfield
.imm8s
= 1;
1987 t
.bitfield
.imm16
= 1;
1988 t
.bitfield
.imm32
= 1;
1989 t
.bitfield
.imm32s
= 1;
1991 else if (fits_in_unsigned_byte (num
))
1993 t
.bitfield
.imm8
= 1;
1994 t
.bitfield
.imm16
= 1;
1995 t
.bitfield
.imm32
= 1;
1996 t
.bitfield
.imm32s
= 1;
1998 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2000 t
.bitfield
.imm16
= 1;
2001 t
.bitfield
.imm32
= 1;
2002 t
.bitfield
.imm32s
= 1;
2004 else if (fits_in_signed_long (num
))
2006 t
.bitfield
.imm32
= 1;
2007 t
.bitfield
.imm32s
= 1;
2009 else if (fits_in_unsigned_long (num
))
2010 t
.bitfield
.imm32
= 1;
2016 offset_in_range (offsetT val
, int size
)
2022 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2023 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2024 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2026 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2032 /* If BFD64, sign extend val for 32bit address mode. */
2033 if (flag_code
!= CODE_64BIT
2034 || i
.prefix
[ADDR_PREFIX
])
2035 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2036 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2039 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2041 char buf1
[40], buf2
[40];
2043 sprint_value (buf1
, val
);
2044 sprint_value (buf2
, val
& mask
);
2045 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2059 a. PREFIX_EXIST if attempting to add a prefix where one from the
2060 same class already exists.
2061 b. PREFIX_LOCK if lock prefix is added.
2062 c. PREFIX_REP if rep/repne prefix is added.
2063 d. PREFIX_OTHER if other prefix is added.
2066 static enum PREFIX_GROUP
2067 add_prefix (unsigned int prefix
)
2069 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2072 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2073 && flag_code
== CODE_64BIT
)
2075 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2076 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2077 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2088 case CS_PREFIX_OPCODE
:
2089 case DS_PREFIX_OPCODE
:
2090 case ES_PREFIX_OPCODE
:
2091 case FS_PREFIX_OPCODE
:
2092 case GS_PREFIX_OPCODE
:
2093 case SS_PREFIX_OPCODE
:
2097 case REPNE_PREFIX_OPCODE
:
2098 case REPE_PREFIX_OPCODE
:
2103 case LOCK_PREFIX_OPCODE
:
2112 case ADDR_PREFIX_OPCODE
:
2116 case DATA_PREFIX_OPCODE
:
2120 if (i
.prefix
[q
] != 0)
2128 i
.prefix
[q
] |= prefix
;
2131 as_bad (_("same type of prefix used twice"));
2137 update_code_flag (int value
, int check
)
2139 PRINTF_LIKE ((*as_error
));
2141 flag_code
= (enum flag_code
) value
;
2142 if (flag_code
== CODE_64BIT
)
2144 cpu_arch_flags
.bitfield
.cpu64
= 1;
2145 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2149 cpu_arch_flags
.bitfield
.cpu64
= 0;
2150 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2152 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2155 as_error
= as_fatal
;
2158 (*as_error
) (_("64bit mode not supported on `%s'."),
2159 cpu_arch_name
? cpu_arch_name
: default_arch
);
2161 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2164 as_error
= as_fatal
;
2167 (*as_error
) (_("32bit mode not supported on `%s'."),
2168 cpu_arch_name
? cpu_arch_name
: default_arch
);
2170 stackop_size
= '\0';
2174 set_code_flag (int value
)
2176 update_code_flag (value
, 0);
2180 set_16bit_gcc_code_flag (int new_code_flag
)
2182 flag_code
= (enum flag_code
) new_code_flag
;
2183 if (flag_code
!= CODE_16BIT
)
2185 cpu_arch_flags
.bitfield
.cpu64
= 0;
2186 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2187 stackop_size
= LONG_MNEM_SUFFIX
;
2191 set_intel_syntax (int syntax_flag
)
2193 /* Find out if register prefixing is specified. */
2194 int ask_naked_reg
= 0;
2197 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2199 char *string
= input_line_pointer
;
2200 int e
= get_symbol_end ();
2202 if (strcmp (string
, "prefix") == 0)
2204 else if (strcmp (string
, "noprefix") == 0)
2207 as_bad (_("bad argument to syntax directive."));
2208 *input_line_pointer
= e
;
2210 demand_empty_rest_of_line ();
2212 intel_syntax
= syntax_flag
;
2214 if (ask_naked_reg
== 0)
2215 allow_naked_reg
= (intel_syntax
2216 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2218 allow_naked_reg
= (ask_naked_reg
< 0);
2220 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2222 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2223 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2224 register_prefix
= allow_naked_reg
? "" : "%";
2228 set_intel_mnemonic (int mnemonic_flag
)
2230 intel_mnemonic
= mnemonic_flag
;
2234 set_allow_index_reg (int flag
)
2236 allow_index_reg
= flag
;
2240 set_check (int what
)
2242 enum check_kind
*kind
;
2247 kind
= &operand_check
;
2258 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2260 char *string
= input_line_pointer
;
2261 int e
= get_symbol_end ();
2263 if (strcmp (string
, "none") == 0)
2265 else if (strcmp (string
, "warning") == 0)
2266 *kind
= check_warning
;
2267 else if (strcmp (string
, "error") == 0)
2268 *kind
= check_error
;
2270 as_bad (_("bad argument to %s_check directive."), str
);
2271 *input_line_pointer
= e
;
2274 as_bad (_("missing argument for %s_check directive"), str
);
2276 demand_empty_rest_of_line ();
2280 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2281 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2284 static const char *arch
;
2286 /* Intel LIOM is only supported on ELF. */
2292 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2293 use default_arch. */
2294 arch
= cpu_arch_name
;
2296 arch
= default_arch
;
2299 /* If we are targeting Intel MCU, we must enable it. */
2300 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2301 || new_flag
.bitfield
.cpuiamcu
)
2304 /* If we are targeting Intel L1OM, we must enable it. */
2305 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2306 || new_flag
.bitfield
.cpul1om
)
2309 /* If we are targeting Intel K1OM, we must enable it. */
2310 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2311 || new_flag
.bitfield
.cpuk1om
)
2314 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2319 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2323 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2325 char *string
= input_line_pointer
;
2326 int e
= get_symbol_end ();
2328 i386_cpu_flags flags
;
2330 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2332 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2334 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2338 cpu_arch_name
= cpu_arch
[j
].name
;
2339 cpu_sub_arch_name
= NULL
;
2340 cpu_arch_flags
= cpu_arch
[j
].flags
;
2341 if (flag_code
== CODE_64BIT
)
2343 cpu_arch_flags
.bitfield
.cpu64
= 1;
2344 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2348 cpu_arch_flags
.bitfield
.cpu64
= 0;
2349 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2351 cpu_arch_isa
= cpu_arch
[j
].type
;
2352 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2353 if (!cpu_arch_tune_set
)
2355 cpu_arch_tune
= cpu_arch_isa
;
2356 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2361 if (!cpu_arch
[j
].negated
)
2362 flags
= cpu_flags_or (cpu_arch_flags
,
2365 flags
= cpu_flags_and_not (cpu_arch_flags
,
2368 if (!valid_iamcu_cpu_flags (&flags
))
2369 as_fatal (_("`%s' isn't valid for Intel MCU"),
2371 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2373 if (cpu_sub_arch_name
)
2375 char *name
= cpu_sub_arch_name
;
2376 cpu_sub_arch_name
= concat (name
,
2378 (const char *) NULL
);
2382 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2383 cpu_arch_flags
= flags
;
2384 cpu_arch_isa_flags
= flags
;
2386 *input_line_pointer
= e
;
2387 demand_empty_rest_of_line ();
2391 if (j
>= ARRAY_SIZE (cpu_arch
))
2392 as_bad (_("no such architecture: `%s'"), string
);
2394 *input_line_pointer
= e
;
2397 as_bad (_("missing cpu architecture"));
2399 no_cond_jump_promotion
= 0;
2400 if (*input_line_pointer
== ','
2401 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2403 char *string
= ++input_line_pointer
;
2404 int e
= get_symbol_end ();
2406 if (strcmp (string
, "nojumps") == 0)
2407 no_cond_jump_promotion
= 1;
2408 else if (strcmp (string
, "jumps") == 0)
2411 as_bad (_("no such architecture modifier: `%s'"), string
);
2413 *input_line_pointer
= e
;
2416 demand_empty_rest_of_line ();
2419 enum bfd_architecture
2422 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2424 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2425 || flag_code
!= CODE_64BIT
)
2426 as_fatal (_("Intel L1OM is 64bit ELF only"));
2427 return bfd_arch_l1om
;
2429 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2431 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2432 || flag_code
!= CODE_64BIT
)
2433 as_fatal (_("Intel K1OM is 64bit ELF only"));
2434 return bfd_arch_k1om
;
2436 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2438 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2439 || flag_code
== CODE_64BIT
)
2440 as_fatal (_("Intel MCU is 32bit ELF only"));
2441 return bfd_arch_iamcu
;
2444 return bfd_arch_i386
;
2450 if (!strncmp (default_arch
, "x86_64", 6))
2452 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2454 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2455 || default_arch
[6] != '\0')
2456 as_fatal (_("Intel L1OM is 64bit ELF only"));
2457 return bfd_mach_l1om
;
2459 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2461 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2462 || default_arch
[6] != '\0')
2463 as_fatal (_("Intel K1OM is 64bit ELF only"));
2464 return bfd_mach_k1om
;
2466 else if (default_arch
[6] == '\0')
2467 return bfd_mach_x86_64
;
2469 return bfd_mach_x64_32
;
2471 else if (!strcmp (default_arch
, "i386")
2472 || !strcmp (default_arch
, "iamcu"))
2474 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2476 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2477 as_fatal (_("Intel MCU is 32bit ELF only"));
2478 return bfd_mach_i386_iamcu
;
2481 return bfd_mach_i386_i386
;
2484 as_fatal (_("unknown architecture"));
2490 const char *hash_err
;
2492 /* Initialize op_hash hash table. */
2493 op_hash
= hash_new ();
2496 const insn_template
*optab
;
2497 templates
*core_optab
;
2499 /* Setup for loop. */
2501 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2502 core_optab
->start
= optab
;
2507 if (optab
->name
== NULL
2508 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2510 /* different name --> ship out current template list;
2511 add to hash table; & begin anew. */
2512 core_optab
->end
= optab
;
2513 hash_err
= hash_insert (op_hash
,
2515 (void *) core_optab
);
2518 as_fatal (_("can't hash %s: %s"),
2522 if (optab
->name
== NULL
)
2524 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2525 core_optab
->start
= optab
;
2530 /* Initialize reg_hash hash table. */
2531 reg_hash
= hash_new ();
2533 const reg_entry
*regtab
;
2534 unsigned int regtab_size
= i386_regtab_size
;
2536 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2538 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2540 as_fatal (_("can't hash %s: %s"),
2546 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2551 for (c
= 0; c
< 256; c
++)
2556 mnemonic_chars
[c
] = c
;
2557 register_chars
[c
] = c
;
2558 operand_chars
[c
] = c
;
2560 else if (ISLOWER (c
))
2562 mnemonic_chars
[c
] = c
;
2563 register_chars
[c
] = c
;
2564 operand_chars
[c
] = c
;
2566 else if (ISUPPER (c
))
2568 mnemonic_chars
[c
] = TOLOWER (c
);
2569 register_chars
[c
] = mnemonic_chars
[c
];
2570 operand_chars
[c
] = c
;
2572 else if (c
== '{' || c
== '}')
2573 operand_chars
[c
] = c
;
2575 if (ISALPHA (c
) || ISDIGIT (c
))
2576 identifier_chars
[c
] = c
;
2579 identifier_chars
[c
] = c
;
2580 operand_chars
[c
] = c
;
2585 identifier_chars
['@'] = '@';
2588 identifier_chars
['?'] = '?';
2589 operand_chars
['?'] = '?';
2591 digit_chars
['-'] = '-';
2592 mnemonic_chars
['_'] = '_';
2593 mnemonic_chars
['-'] = '-';
2594 mnemonic_chars
['.'] = '.';
2595 identifier_chars
['_'] = '_';
2596 identifier_chars
['.'] = '.';
2598 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2599 operand_chars
[(unsigned char) *p
] = *p
;
2602 if (flag_code
== CODE_64BIT
)
2604 #if defined (OBJ_COFF) && defined (TE_PE)
2605 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2608 x86_dwarf2_return_column
= 16;
2610 x86_cie_data_alignment
= -8;
2614 x86_dwarf2_return_column
= 8;
2615 x86_cie_data_alignment
= -4;
2620 i386_print_statistics (FILE *file
)
2622 hash_print_statistics (file
, "i386 opcode", op_hash
);
2623 hash_print_statistics (file
, "i386 register", reg_hash
);
2628 /* Debugging routines for md_assemble. */
2629 static void pte (insn_template
*);
2630 static void pt (i386_operand_type
);
2631 static void pe (expressionS
*);
2632 static void ps (symbolS
*);
2635 pi (char *line
, i386_insn
*x
)
2639 fprintf (stdout
, "%s: template ", line
);
2641 fprintf (stdout
, " address: base %s index %s scale %x\n",
2642 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2643 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2644 x
->log2_scale_factor
);
2645 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2646 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2647 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2648 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2649 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2650 (x
->rex
& REX_W
) != 0,
2651 (x
->rex
& REX_R
) != 0,
2652 (x
->rex
& REX_X
) != 0,
2653 (x
->rex
& REX_B
) != 0);
2654 for (j
= 0; j
< x
->operands
; j
++)
2656 fprintf (stdout
, " #%d: ", j
+ 1);
2658 fprintf (stdout
, "\n");
2659 if (x
->types
[j
].bitfield
.reg8
2660 || x
->types
[j
].bitfield
.reg16
2661 || x
->types
[j
].bitfield
.reg32
2662 || x
->types
[j
].bitfield
.reg64
2663 || x
->types
[j
].bitfield
.regmmx
2664 || x
->types
[j
].bitfield
.regxmm
2665 || x
->types
[j
].bitfield
.regymm
2666 || x
->types
[j
].bitfield
.regzmm
2667 || x
->types
[j
].bitfield
.sreg2
2668 || x
->types
[j
].bitfield
.sreg3
2669 || x
->types
[j
].bitfield
.control
2670 || x
->types
[j
].bitfield
.debug
2671 || x
->types
[j
].bitfield
.test
)
2672 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2673 if (operand_type_check (x
->types
[j
], imm
))
2675 if (operand_type_check (x
->types
[j
], disp
))
2676 pe (x
->op
[j
].disps
);
2681 pte (insn_template
*t
)
2684 fprintf (stdout
, " %d operands ", t
->operands
);
2685 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2686 if (t
->extension_opcode
!= None
)
2687 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2688 if (t
->opcode_modifier
.d
)
2689 fprintf (stdout
, "D");
2690 if (t
->opcode_modifier
.w
)
2691 fprintf (stdout
, "W");
2692 fprintf (stdout
, "\n");
2693 for (j
= 0; j
< t
->operands
; j
++)
2695 fprintf (stdout
, " #%d type ", j
+ 1);
2696 pt (t
->operand_types
[j
]);
2697 fprintf (stdout
, "\n");
2704 fprintf (stdout
, " operation %d\n", e
->X_op
);
2705 fprintf (stdout
, " add_number %ld (%lx)\n",
2706 (long) e
->X_add_number
, (long) e
->X_add_number
);
2707 if (e
->X_add_symbol
)
2709 fprintf (stdout
, " add_symbol ");
2710 ps (e
->X_add_symbol
);
2711 fprintf (stdout
, "\n");
2715 fprintf (stdout
, " op_symbol ");
2716 ps (e
->X_op_symbol
);
2717 fprintf (stdout
, "\n");
2724 fprintf (stdout
, "%s type %s%s",
2726 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2727 segment_name (S_GET_SEGMENT (s
)));
2730 static struct type_name
2732 i386_operand_type mask
;
2735 const type_names
[] =
2737 { OPERAND_TYPE_REG8
, "r8" },
2738 { OPERAND_TYPE_REG16
, "r16" },
2739 { OPERAND_TYPE_REG32
, "r32" },
2740 { OPERAND_TYPE_REG64
, "r64" },
2741 { OPERAND_TYPE_IMM8
, "i8" },
2742 { OPERAND_TYPE_IMM8
, "i8s" },
2743 { OPERAND_TYPE_IMM16
, "i16" },
2744 { OPERAND_TYPE_IMM32
, "i32" },
2745 { OPERAND_TYPE_IMM32S
, "i32s" },
2746 { OPERAND_TYPE_IMM64
, "i64" },
2747 { OPERAND_TYPE_IMM1
, "i1" },
2748 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2749 { OPERAND_TYPE_DISP8
, "d8" },
2750 { OPERAND_TYPE_DISP16
, "d16" },
2751 { OPERAND_TYPE_DISP32
, "d32" },
2752 { OPERAND_TYPE_DISP32S
, "d32s" },
2753 { OPERAND_TYPE_DISP64
, "d64" },
2754 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2755 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2756 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2757 { OPERAND_TYPE_CONTROL
, "control reg" },
2758 { OPERAND_TYPE_TEST
, "test reg" },
2759 { OPERAND_TYPE_DEBUG
, "debug reg" },
2760 { OPERAND_TYPE_FLOATREG
, "FReg" },
2761 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2762 { OPERAND_TYPE_SREG2
, "SReg2" },
2763 { OPERAND_TYPE_SREG3
, "SReg3" },
2764 { OPERAND_TYPE_ACC
, "Acc" },
2765 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2766 { OPERAND_TYPE_REGMMX
, "rMMX" },
2767 { OPERAND_TYPE_REGXMM
, "rXMM" },
2768 { OPERAND_TYPE_REGYMM
, "rYMM" },
2769 { OPERAND_TYPE_REGZMM
, "rZMM" },
2770 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2771 { OPERAND_TYPE_ESSEG
, "es" },
2775 pt (i386_operand_type t
)
2778 i386_operand_type a
;
2780 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2782 a
= operand_type_and (t
, type_names
[j
].mask
);
2783 if (!operand_type_all_zero (&a
))
2784 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2789 #endif /* DEBUG386 */
2791 static bfd_reloc_code_real_type
2792 reloc (unsigned int size
,
2795 bfd_reloc_code_real_type other
)
2797 if (other
!= NO_RELOC
)
2799 reloc_howto_type
*rel
;
2804 case BFD_RELOC_X86_64_GOT32
:
2805 return BFD_RELOC_X86_64_GOT64
;
2807 case BFD_RELOC_X86_64_GOTPLT64
:
2808 return BFD_RELOC_X86_64_GOTPLT64
;
2810 case BFD_RELOC_X86_64_PLTOFF64
:
2811 return BFD_RELOC_X86_64_PLTOFF64
;
2813 case BFD_RELOC_X86_64_GOTPC32
:
2814 other
= BFD_RELOC_X86_64_GOTPC64
;
2816 case BFD_RELOC_X86_64_GOTPCREL
:
2817 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2819 case BFD_RELOC_X86_64_TPOFF32
:
2820 other
= BFD_RELOC_X86_64_TPOFF64
;
2822 case BFD_RELOC_X86_64_DTPOFF32
:
2823 other
= BFD_RELOC_X86_64_DTPOFF64
;
2829 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2830 if (other
== BFD_RELOC_SIZE32
)
2833 other
= BFD_RELOC_SIZE64
;
2836 as_bad (_("there are no pc-relative size relocations"));
2842 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2843 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2846 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2848 as_bad (_("unknown relocation (%u)"), other
);
2849 else if (size
!= bfd_get_reloc_size (rel
))
2850 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2851 bfd_get_reloc_size (rel
),
2853 else if (pcrel
&& !rel
->pc_relative
)
2854 as_bad (_("non-pc-relative relocation for pc-relative field"));
2855 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2857 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2859 as_bad (_("relocated field and relocation type differ in signedness"));
2868 as_bad (_("there are no unsigned pc-relative relocations"));
2871 case 1: return BFD_RELOC_8_PCREL
;
2872 case 2: return BFD_RELOC_16_PCREL
;
2873 case 4: return BFD_RELOC_32_PCREL
;
2874 case 8: return BFD_RELOC_64_PCREL
;
2876 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2883 case 4: return BFD_RELOC_X86_64_32S
;
2888 case 1: return BFD_RELOC_8
;
2889 case 2: return BFD_RELOC_16
;
2890 case 4: return BFD_RELOC_32
;
2891 case 8: return BFD_RELOC_64
;
2893 as_bad (_("cannot do %s %u byte relocation"),
2894 sign
> 0 ? "signed" : "unsigned", size
);
2900 /* Here we decide which fixups can be adjusted to make them relative to
2901 the beginning of the section instead of the symbol. Basically we need
2902 to make sure that the dynamic relocations are done correctly, so in
2903 some cases we force the original symbol to be used. */
2906 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2912 /* Don't adjust pc-relative references to merge sections in 64-bit
2914 if (use_rela_relocations
2915 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2919 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2920 and changed later by validate_fix. */
2921 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2922 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2925 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2926 for size relocations. */
2927 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2928 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2929 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2930 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2931 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2932 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2933 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2942 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2943 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2955 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2956 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2963 intel_float_operand (const char *mnemonic
)
2965 /* Note that the value returned is meaningful only for opcodes with (memory)
2966 operands, hence the code here is free to improperly handle opcodes that
2967 have no operands (for better performance and smaller code). */
2969 if (mnemonic
[0] != 'f')
2970 return 0; /* non-math */
2972 switch (mnemonic
[1])
2974 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2975 the fs segment override prefix not currently handled because no
2976 call path can make opcodes without operands get here */
2978 return 2 /* integer op */;
2980 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2981 return 3; /* fldcw/fldenv */
2984 if (mnemonic
[2] != 'o' /* fnop */)
2985 return 3; /* non-waiting control op */
2988 if (mnemonic
[2] == 's')
2989 return 3; /* frstor/frstpm */
2992 if (mnemonic
[2] == 'a')
2993 return 3; /* fsave */
2994 if (mnemonic
[2] == 't')
2996 switch (mnemonic
[3])
2998 case 'c': /* fstcw */
2999 case 'd': /* fstdw */
3000 case 'e': /* fstenv */
3001 case 's': /* fsts[gw] */
3007 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3008 return 0; /* fxsave/fxrstor are not really math ops */
3015 /* Build the VEX prefix. */
3018 build_vex_prefix (const insn_template
*t
)
3020 unsigned int register_specifier
;
3021 unsigned int implied_prefix
;
3022 unsigned int vector_length
;
3024 /* Check register specifier. */
3025 if (i
.vex
.register_specifier
)
3027 register_specifier
=
3028 ~register_number (i
.vex
.register_specifier
) & 0xf;
3029 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3032 register_specifier
= 0xf;
3034 /* Use 2-byte VEX prefix by swappping destination and source
3037 && i
.operands
== i
.reg_operands
3038 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3039 && i
.tm
.opcode_modifier
.s
3042 unsigned int xchg
= i
.operands
- 1;
3043 union i386_op temp_op
;
3044 i386_operand_type temp_type
;
3046 temp_type
= i
.types
[xchg
];
3047 i
.types
[xchg
] = i
.types
[0];
3048 i
.types
[0] = temp_type
;
3049 temp_op
= i
.op
[xchg
];
3050 i
.op
[xchg
] = i
.op
[0];
3053 gas_assert (i
.rm
.mode
== 3);
3057 i
.rm
.regmem
= i
.rm
.reg
;
3060 /* Use the next insn. */
3064 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3065 vector_length
= avxscalar
;
3067 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3069 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3074 case DATA_PREFIX_OPCODE
:
3077 case REPE_PREFIX_OPCODE
:
3080 case REPNE_PREFIX_OPCODE
:
3087 /* Use 2-byte VEX prefix if possible. */
3088 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3089 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3090 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3092 /* 2-byte VEX prefix. */
3096 i
.vex
.bytes
[0] = 0xc5;
3098 /* Check the REX.R bit. */
3099 r
= (i
.rex
& REX_R
) ? 0 : 1;
3100 i
.vex
.bytes
[1] = (r
<< 7
3101 | register_specifier
<< 3
3102 | vector_length
<< 2
3107 /* 3-byte VEX prefix. */
3112 switch (i
.tm
.opcode_modifier
.vexopcode
)
3116 i
.vex
.bytes
[0] = 0xc4;
3120 i
.vex
.bytes
[0] = 0xc4;
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0x8f;
3132 i
.vex
.bytes
[0] = 0x8f;
3136 i
.vex
.bytes
[0] = 0x8f;
3142 /* The high 3 bits of the second VEX byte are 1's compliment
3143 of RXB bits from REX. */
3144 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3146 /* Check the REX.W bit. */
3147 w
= (i
.rex
& REX_W
) ? 1 : 0;
3148 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3151 i
.vex
.bytes
[2] = (w
<< 7
3152 | register_specifier
<< 3
3153 | vector_length
<< 2
3158 /* Build the EVEX prefix. */
3161 build_evex_prefix (void)
3163 unsigned int register_specifier
;
3164 unsigned int implied_prefix
;
3166 rex_byte vrex_used
= 0;
3168 /* Check register specifier. */
3169 if (i
.vex
.register_specifier
)
3171 gas_assert ((i
.vrex
& REX_X
) == 0);
3173 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3174 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3175 register_specifier
+= 8;
3176 /* The upper 16 registers are encoded in the fourth byte of the
3178 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3179 i
.vex
.bytes
[3] = 0x8;
3180 register_specifier
= ~register_specifier
& 0xf;
3184 register_specifier
= 0xf;
3186 /* Encode upper 16 vector index register in the fourth byte of
3188 if (!(i
.vrex
& REX_X
))
3189 i
.vex
.bytes
[3] = 0x8;
3194 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3199 case DATA_PREFIX_OPCODE
:
3202 case REPE_PREFIX_OPCODE
:
3205 case REPNE_PREFIX_OPCODE
:
3212 /* 4 byte EVEX prefix. */
3214 i
.vex
.bytes
[0] = 0x62;
3217 switch (i
.tm
.opcode_modifier
.vexopcode
)
3233 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3235 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3237 /* The fifth bit of the second EVEX byte is 1's compliment of the
3238 REX_R bit in VREX. */
3239 if (!(i
.vrex
& REX_R
))
3240 i
.vex
.bytes
[1] |= 0x10;
3244 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3246 /* When all operands are registers, the REX_X bit in REX is not
3247 used. We reuse it to encode the upper 16 registers, which is
3248 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3249 as 1's compliment. */
3250 if ((i
.vrex
& REX_B
))
3253 i
.vex
.bytes
[1] &= ~0x40;
3257 /* EVEX instructions shouldn't need the REX prefix. */
3258 i
.vrex
&= ~vrex_used
;
3259 gas_assert (i
.vrex
== 0);
3261 /* Check the REX.W bit. */
3262 w
= (i
.rex
& REX_W
) ? 1 : 0;
3263 if (i
.tm
.opcode_modifier
.vexw
)
3265 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3268 /* If w is not set it means we are dealing with WIG instruction. */
3271 if (evexwig
== evexw1
)
3275 /* Encode the U bit. */
3276 implied_prefix
|= 0x4;
3278 /* The third byte of the EVEX prefix. */
3279 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3281 /* The fourth byte of the EVEX prefix. */
3282 /* The zeroing-masking bit. */
3283 if (i
.mask
&& i
.mask
->zeroing
)
3284 i
.vex
.bytes
[3] |= 0x80;
3286 /* Don't always set the broadcast bit if there is no RC. */
3289 /* Encode the vector length. */
3290 unsigned int vec_length
;
3292 switch (i
.tm
.opcode_modifier
.evex
)
3294 case EVEXLIG
: /* LL' is ignored */
3295 vec_length
= evexlig
<< 5;
3298 vec_length
= 0 << 5;
3301 vec_length
= 1 << 5;
3304 vec_length
= 2 << 5;
3310 i
.vex
.bytes
[3] |= vec_length
;
3311 /* Encode the broadcast bit. */
3313 i
.vex
.bytes
[3] |= 0x10;
3317 if (i
.rounding
->type
!= saeonly
)
3318 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3320 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3323 if (i
.mask
&& i
.mask
->mask
)
3324 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3328 process_immext (void)
3332 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3335 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3336 with an opcode suffix which is coded in the same place as an
3337 8-bit immediate field would be.
3338 Here we check those operands and remove them afterwards. */
3341 for (x
= 0; x
< i
.operands
; x
++)
3342 if (register_number (i
.op
[x
].regs
) != x
)
3343 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3344 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3350 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3351 which is coded in the same place as an 8-bit immediate field
3352 would be. Here we fake an 8-bit immediate operand from the
3353 opcode suffix stored in tm.extension_opcode.
3355 AVX instructions also use this encoding, for some of
3356 3 argument instructions. */
3358 gas_assert (i
.imm_operands
<= 1
3360 || ((i
.tm
.opcode_modifier
.vex
3361 || i
.tm
.opcode_modifier
.evex
)
3362 && i
.operands
<= 4)));
3364 exp
= &im_expressions
[i
.imm_operands
++];
3365 i
.op
[i
.operands
].imms
= exp
;
3366 i
.types
[i
.operands
] = imm8
;
3368 exp
->X_op
= O_constant
;
3369 exp
->X_add_number
= i
.tm
.extension_opcode
;
3370 i
.tm
.extension_opcode
= None
;
3377 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3382 as_bad (_("invalid instruction `%s' after `%s'"),
3383 i
.tm
.name
, i
.hle_prefix
);
3386 if (i
.prefix
[LOCK_PREFIX
])
3388 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3392 case HLEPrefixRelease
:
3393 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3395 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3399 if (i
.mem_operands
== 0
3400 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3402 as_bad (_("memory destination needed for instruction `%s'"
3403 " after `xrelease'"), i
.tm
.name
);
3410 /* This is the guts of the machine-dependent assembler. LINE points to a
3411 machine dependent instruction. This function is supposed to emit
3412 the frags/bytes it assembles to. */
3415 md_assemble (char *line
)
3418 char mnemonic
[MAX_MNEM_SIZE
];
3419 const insn_template
*t
;
3421 /* Initialize globals. */
3422 memset (&i
, '\0', sizeof (i
));
3423 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3424 i
.reloc
[j
] = NO_RELOC
;
3425 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3426 memset (im_expressions
, '\0', sizeof (im_expressions
));
3427 save_stack_p
= save_stack
;
3429 /* First parse an instruction mnemonic & call i386_operand for the operands.
3430 We assume that the scrubber has arranged it so that line[0] is the valid
3431 start of a (possibly prefixed) mnemonic. */
3433 line
= parse_insn (line
, mnemonic
);
3437 line
= parse_operands (line
, mnemonic
);
3442 /* Now we've parsed the mnemonic into a set of templates, and have the
3443 operands at hand. */
3445 /* All intel opcodes have reversed operands except for "bound" and
3446 "enter". We also don't reverse intersegment "jmp" and "call"
3447 instructions with 2 immediate operands so that the immediate segment
3448 precedes the offset, as it does when in AT&T mode. */
3451 && (strcmp (mnemonic
, "bound") != 0)
3452 && (strcmp (mnemonic
, "invlpga") != 0)
3453 && !(operand_type_check (i
.types
[0], imm
)
3454 && operand_type_check (i
.types
[1], imm
)))
3457 /* The order of the immediates should be reversed
3458 for 2 immediates extrq and insertq instructions */
3459 if (i
.imm_operands
== 2
3460 && (strcmp (mnemonic
, "extrq") == 0
3461 || strcmp (mnemonic
, "insertq") == 0))
3462 swap_2_operands (0, 1);
3467 /* Don't optimize displacement for movabs since it only takes 64bit
3470 && i
.disp_encoding
!= disp_encoding_32bit
3471 && (flag_code
!= CODE_64BIT
3472 || strcmp (mnemonic
, "movabs") != 0))
3475 /* Next, we find a template that matches the given insn,
3476 making sure the overlap of the given operands types is consistent
3477 with the template operand types. */
3479 if (!(t
= match_template ()))
3482 if (sse_check
!= check_none
3483 && !i
.tm
.opcode_modifier
.noavx
3484 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3485 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3486 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3487 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3488 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3489 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3491 (sse_check
== check_warning
3493 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3496 /* Zap movzx and movsx suffix. The suffix has been set from
3497 "word ptr" or "byte ptr" on the source operand in Intel syntax
3498 or extracted from mnemonic in AT&T syntax. But we'll use
3499 the destination register to choose the suffix for encoding. */
3500 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3502 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3503 there is no suffix, the default will be byte extension. */
3504 if (i
.reg_operands
!= 2
3507 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3512 if (i
.tm
.opcode_modifier
.fwait
)
3513 if (!add_prefix (FWAIT_OPCODE
))
3516 /* Check if REP prefix is OK. */
3517 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3519 as_bad (_("invalid instruction `%s' after `%s'"),
3520 i
.tm
.name
, i
.rep_prefix
);
3524 /* Check for lock without a lockable instruction. Destination operand
3525 must be memory unless it is xchg (0x86). */
3526 if (i
.prefix
[LOCK_PREFIX
]
3527 && (!i
.tm
.opcode_modifier
.islockable
3528 || i
.mem_operands
== 0
3529 || (i
.tm
.base_opcode
!= 0x86
3530 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3532 as_bad (_("expecting lockable instruction after `lock'"));
3536 /* Check if HLE prefix is OK. */
3537 if (i
.hle_prefix
&& !check_hle ())
3540 /* Check BND prefix. */
3541 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3542 as_bad (_("expecting valid branch instruction after `bnd'"));
3544 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3545 && flag_code
== CODE_64BIT
3546 && i
.prefix
[ADDR_PREFIX
])
3547 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3549 /* Insert BND prefix. */
3551 && i
.tm
.opcode_modifier
.bndprefixok
3552 && !i
.prefix
[BND_PREFIX
])
3553 add_prefix (BND_PREFIX_OPCODE
);
3555 /* Check string instruction segment overrides. */
3556 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3558 if (!check_string ())
3560 i
.disp_operands
= 0;
3563 if (!process_suffix ())
3566 /* Update operand types. */
3567 for (j
= 0; j
< i
.operands
; j
++)
3568 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3570 /* Make still unresolved immediate matches conform to size of immediate
3571 given in i.suffix. */
3572 if (!finalize_imm ())
3575 if (i
.types
[0].bitfield
.imm1
)
3576 i
.imm_operands
= 0; /* kludge for shift insns. */
3578 /* We only need to check those implicit registers for instructions
3579 with 3 operands or less. */
3580 if (i
.operands
<= 3)
3581 for (j
= 0; j
< i
.operands
; j
++)
3582 if (i
.types
[j
].bitfield
.inoutportreg
3583 || i
.types
[j
].bitfield
.shiftcount
3584 || i
.types
[j
].bitfield
.acc
3585 || i
.types
[j
].bitfield
.floatacc
)
3588 /* ImmExt should be processed after SSE2AVX. */
3589 if (!i
.tm
.opcode_modifier
.sse2avx
3590 && i
.tm
.opcode_modifier
.immext
)
3593 /* For insns with operands there are more diddles to do to the opcode. */
3596 if (!process_operands ())
3599 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3601 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3602 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3605 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3607 if (flag_code
== CODE_16BIT
)
3609 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3614 if (i
.tm
.opcode_modifier
.vex
)
3615 build_vex_prefix (t
);
3617 build_evex_prefix ();
3620 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3621 instructions may define INT_OPCODE as well, so avoid this corner
3622 case for those instructions that use MODRM. */
3623 if (i
.tm
.base_opcode
== INT_OPCODE
3624 && !i
.tm
.opcode_modifier
.modrm
3625 && i
.op
[0].imms
->X_add_number
== 3)
3627 i
.tm
.base_opcode
= INT3_OPCODE
;
3631 if ((i
.tm
.opcode_modifier
.jump
3632 || i
.tm
.opcode_modifier
.jumpbyte
3633 || i
.tm
.opcode_modifier
.jumpdword
)
3634 && i
.op
[0].disps
->X_op
== O_constant
)
3636 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3637 the absolute address given by the constant. Since ix86 jumps and
3638 calls are pc relative, we need to generate a reloc. */
3639 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3640 i
.op
[0].disps
->X_op
= O_symbol
;
3643 if (i
.tm
.opcode_modifier
.rex64
)
3646 /* For 8 bit registers we need an empty rex prefix. Also if the
3647 instruction already has a prefix, we need to convert old
3648 registers to new ones. */
3650 if ((i
.types
[0].bitfield
.reg8
3651 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3652 || (i
.types
[1].bitfield
.reg8
3653 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3654 || ((i
.types
[0].bitfield
.reg8
3655 || i
.types
[1].bitfield
.reg8
)
3660 i
.rex
|= REX_OPCODE
;
3661 for (x
= 0; x
< 2; x
++)
3663 /* Look for 8 bit operand that uses old registers. */
3664 if (i
.types
[x
].bitfield
.reg8
3665 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3667 /* In case it is "hi" register, give up. */
3668 if (i
.op
[x
].regs
->reg_num
> 3)
3669 as_bad (_("can't encode register '%s%s' in an "
3670 "instruction requiring REX prefix."),
3671 register_prefix
, i
.op
[x
].regs
->reg_name
);
3673 /* Otherwise it is equivalent to the extended register.
3674 Since the encoding doesn't change this is merely
3675 cosmetic cleanup for debug output. */
3677 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3683 add_prefix (REX_OPCODE
| i
.rex
);
3685 /* We are ready to output the insn. */
3690 parse_insn (char *line
, char *mnemonic
)
3693 char *token_start
= l
;
3696 const insn_template
*t
;
3702 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3707 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3709 as_bad (_("no such instruction: `%s'"), token_start
);
3714 if (!is_space_char (*l
)
3715 && *l
!= END_OF_INSN
3717 || (*l
!= PREFIX_SEPARATOR
3720 as_bad (_("invalid character %s in mnemonic"),
3721 output_invalid (*l
));
3724 if (token_start
== l
)
3726 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3727 as_bad (_("expecting prefix; got nothing"));
3729 as_bad (_("expecting mnemonic; got nothing"));
3733 /* Look up instruction (or prefix) via hash table. */
3734 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3736 if (*l
!= END_OF_INSN
3737 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3738 && current_templates
3739 && current_templates
->start
->opcode_modifier
.isprefix
)
3741 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3743 as_bad ((flag_code
!= CODE_64BIT
3744 ? _("`%s' is only supported in 64-bit mode")
3745 : _("`%s' is not supported in 64-bit mode")),
3746 current_templates
->start
->name
);
3749 /* If we are in 16-bit mode, do not allow addr16 or data16.
3750 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3751 if ((current_templates
->start
->opcode_modifier
.size16
3752 || current_templates
->start
->opcode_modifier
.size32
)
3753 && flag_code
!= CODE_64BIT
3754 && (current_templates
->start
->opcode_modifier
.size32
3755 ^ (flag_code
== CODE_16BIT
)))
3757 as_bad (_("redundant %s prefix"),
3758 current_templates
->start
->name
);
3761 /* Add prefix, checking for repeated prefixes. */
3762 switch (add_prefix (current_templates
->start
->base_opcode
))
3767 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3768 i
.hle_prefix
= current_templates
->start
->name
;
3769 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3770 i
.bnd_prefix
= current_templates
->start
->name
;
3772 i
.rep_prefix
= current_templates
->start
->name
;
3777 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3784 if (!current_templates
)
3786 /* Check if we should swap operand or force 32bit displacement in
3788 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3790 else if (mnem_p
- 3 == dot_p
3793 i
.disp_encoding
= disp_encoding_8bit
;
3794 else if (mnem_p
- 4 == dot_p
3798 i
.disp_encoding
= disp_encoding_32bit
;
3803 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3806 if (!current_templates
)
3809 /* See if we can get a match by trimming off a suffix. */
3812 case WORD_MNEM_SUFFIX
:
3813 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3814 i
.suffix
= SHORT_MNEM_SUFFIX
;
3816 case BYTE_MNEM_SUFFIX
:
3817 case QWORD_MNEM_SUFFIX
:
3818 i
.suffix
= mnem_p
[-1];
3820 current_templates
= (const templates
*) hash_find (op_hash
,
3823 case SHORT_MNEM_SUFFIX
:
3824 case LONG_MNEM_SUFFIX
:
3827 i
.suffix
= mnem_p
[-1];
3829 current_templates
= (const templates
*) hash_find (op_hash
,
3838 if (intel_float_operand (mnemonic
) == 1)
3839 i
.suffix
= SHORT_MNEM_SUFFIX
;
3841 i
.suffix
= LONG_MNEM_SUFFIX
;
3843 current_templates
= (const templates
*) hash_find (op_hash
,
3848 if (!current_templates
)
3850 as_bad (_("no such instruction: `%s'"), token_start
);
3855 if (current_templates
->start
->opcode_modifier
.jump
3856 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3858 /* Check for a branch hint. We allow ",pt" and ",pn" for
3859 predict taken and predict not taken respectively.
3860 I'm not sure that branch hints actually do anything on loop
3861 and jcxz insns (JumpByte) for current Pentium4 chips. They
3862 may work in the future and it doesn't hurt to accept them
3864 if (l
[0] == ',' && l
[1] == 'p')
3868 if (!add_prefix (DS_PREFIX_OPCODE
))
3872 else if (l
[2] == 'n')
3874 if (!add_prefix (CS_PREFIX_OPCODE
))
3880 /* Any other comma loses. */
3883 as_bad (_("invalid character %s in mnemonic"),
3884 output_invalid (*l
));
3888 /* Check if instruction is supported on specified architecture. */
3890 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3892 supported
|= cpu_flags_match (t
);
3893 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3897 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3899 as_bad (flag_code
== CODE_64BIT
3900 ? _("`%s' is not supported in 64-bit mode")
3901 : _("`%s' is only supported in 64-bit mode"),
3902 current_templates
->start
->name
);
3905 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3907 as_bad (_("`%s' is not supported on `%s%s'"),
3908 current_templates
->start
->name
,
3909 cpu_arch_name
? cpu_arch_name
: default_arch
,
3910 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3915 if (!cpu_arch_flags
.bitfield
.cpui386
3916 && (flag_code
!= CODE_16BIT
))
3918 as_warn (_("use .code16 to ensure correct addressing mode"));
3925 parse_operands (char *l
, const char *mnemonic
)
3929 /* 1 if operand is pending after ','. */
3930 unsigned int expecting_operand
= 0;
3932 /* Non-zero if operand parens not balanced. */
3933 unsigned int paren_not_balanced
;
3935 while (*l
!= END_OF_INSN
)
3937 /* Skip optional white space before operand. */
3938 if (is_space_char (*l
))
3940 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3942 as_bad (_("invalid character %s before operand %d"),
3943 output_invalid (*l
),
3947 token_start
= l
; /* after white space */
3948 paren_not_balanced
= 0;
3949 while (paren_not_balanced
|| *l
!= ',')
3951 if (*l
== END_OF_INSN
)
3953 if (paren_not_balanced
)
3956 as_bad (_("unbalanced parenthesis in operand %d."),
3959 as_bad (_("unbalanced brackets in operand %d."),
3964 break; /* we are done */
3966 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3968 as_bad (_("invalid character %s in operand %d"),
3969 output_invalid (*l
),
3976 ++paren_not_balanced
;
3978 --paren_not_balanced
;
3983 ++paren_not_balanced
;
3985 --paren_not_balanced
;
3989 if (l
!= token_start
)
3990 { /* Yes, we've read in another operand. */
3991 unsigned int operand_ok
;
3992 this_operand
= i
.operands
++;
3993 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3994 if (i
.operands
> MAX_OPERANDS
)
3996 as_bad (_("spurious operands; (%d operands/instruction max)"),
4000 /* Now parse operand adding info to 'i' as we go along. */
4001 END_STRING_AND_SAVE (l
);
4005 i386_intel_operand (token_start
,
4006 intel_float_operand (mnemonic
));
4008 operand_ok
= i386_att_operand (token_start
);
4010 RESTORE_END_STRING (l
);
4016 if (expecting_operand
)
4018 expecting_operand_after_comma
:
4019 as_bad (_("expecting operand after ','; got nothing"));
4024 as_bad (_("expecting operand before ','; got nothing"));
4029 /* Now *l must be either ',' or END_OF_INSN. */
4032 if (*++l
== END_OF_INSN
)
4034 /* Just skip it, if it's \n complain. */
4035 goto expecting_operand_after_comma
;
4037 expecting_operand
= 1;
4044 swap_2_operands (int xchg1
, int xchg2
)
4046 union i386_op temp_op
;
4047 i386_operand_type temp_type
;
4048 enum bfd_reloc_code_real temp_reloc
;
4050 temp_type
= i
.types
[xchg2
];
4051 i
.types
[xchg2
] = i
.types
[xchg1
];
4052 i
.types
[xchg1
] = temp_type
;
4053 temp_op
= i
.op
[xchg2
];
4054 i
.op
[xchg2
] = i
.op
[xchg1
];
4055 i
.op
[xchg1
] = temp_op
;
4056 temp_reloc
= i
.reloc
[xchg2
];
4057 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4058 i
.reloc
[xchg1
] = temp_reloc
;
4062 if (i
.mask
->operand
== xchg1
)
4063 i
.mask
->operand
= xchg2
;
4064 else if (i
.mask
->operand
== xchg2
)
4065 i
.mask
->operand
= xchg1
;
4069 if (i
.broadcast
->operand
== xchg1
)
4070 i
.broadcast
->operand
= xchg2
;
4071 else if (i
.broadcast
->operand
== xchg2
)
4072 i
.broadcast
->operand
= xchg1
;
4076 if (i
.rounding
->operand
== xchg1
)
4077 i
.rounding
->operand
= xchg2
;
4078 else if (i
.rounding
->operand
== xchg2
)
4079 i
.rounding
->operand
= xchg1
;
4084 swap_operands (void)
4090 swap_2_operands (1, i
.operands
- 2);
4093 swap_2_operands (0, i
.operands
- 1);
4099 if (i
.mem_operands
== 2)
4101 const seg_entry
*temp_seg
;
4102 temp_seg
= i
.seg
[0];
4103 i
.seg
[0] = i
.seg
[1];
4104 i
.seg
[1] = temp_seg
;
4108 /* Try to ensure constant immediates are represented in the smallest
4113 char guess_suffix
= 0;
4117 guess_suffix
= i
.suffix
;
4118 else if (i
.reg_operands
)
4120 /* Figure out a suffix from the last register operand specified.
4121 We can't do this properly yet, ie. excluding InOutPortReg,
4122 but the following works for instructions with immediates.
4123 In any case, we can't set i.suffix yet. */
4124 for (op
= i
.operands
; --op
>= 0;)
4125 if (i
.types
[op
].bitfield
.reg8
)
4127 guess_suffix
= BYTE_MNEM_SUFFIX
;
4130 else if (i
.types
[op
].bitfield
.reg16
)
4132 guess_suffix
= WORD_MNEM_SUFFIX
;
4135 else if (i
.types
[op
].bitfield
.reg32
)
4137 guess_suffix
= LONG_MNEM_SUFFIX
;
4140 else if (i
.types
[op
].bitfield
.reg64
)
4142 guess_suffix
= QWORD_MNEM_SUFFIX
;
4146 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4147 guess_suffix
= WORD_MNEM_SUFFIX
;
4149 for (op
= i
.operands
; --op
>= 0;)
4150 if (operand_type_check (i
.types
[op
], imm
))
4152 switch (i
.op
[op
].imms
->X_op
)
4155 /* If a suffix is given, this operand may be shortened. */
4156 switch (guess_suffix
)
4158 case LONG_MNEM_SUFFIX
:
4159 i
.types
[op
].bitfield
.imm32
= 1;
4160 i
.types
[op
].bitfield
.imm64
= 1;
4162 case WORD_MNEM_SUFFIX
:
4163 i
.types
[op
].bitfield
.imm16
= 1;
4164 i
.types
[op
].bitfield
.imm32
= 1;
4165 i
.types
[op
].bitfield
.imm32s
= 1;
4166 i
.types
[op
].bitfield
.imm64
= 1;
4168 case BYTE_MNEM_SUFFIX
:
4169 i
.types
[op
].bitfield
.imm8
= 1;
4170 i
.types
[op
].bitfield
.imm8s
= 1;
4171 i
.types
[op
].bitfield
.imm16
= 1;
4172 i
.types
[op
].bitfield
.imm32
= 1;
4173 i
.types
[op
].bitfield
.imm32s
= 1;
4174 i
.types
[op
].bitfield
.imm64
= 1;
4178 /* If this operand is at most 16 bits, convert it
4179 to a signed 16 bit number before trying to see
4180 whether it will fit in an even smaller size.
4181 This allows a 16-bit operand such as $0xffe0 to
4182 be recognised as within Imm8S range. */
4183 if ((i
.types
[op
].bitfield
.imm16
)
4184 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4186 i
.op
[op
].imms
->X_add_number
=
4187 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4189 if ((i
.types
[op
].bitfield
.imm32
)
4190 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4193 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4194 ^ ((offsetT
) 1 << 31))
4195 - ((offsetT
) 1 << 31));
4198 = operand_type_or (i
.types
[op
],
4199 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4201 /* We must avoid matching of Imm32 templates when 64bit
4202 only immediate is available. */
4203 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4204 i
.types
[op
].bitfield
.imm32
= 0;
4211 /* Symbols and expressions. */
4213 /* Convert symbolic operand to proper sizes for matching, but don't
4214 prevent matching a set of insns that only supports sizes other
4215 than those matching the insn suffix. */
4217 i386_operand_type mask
, allowed
;
4218 const insn_template
*t
;
4220 operand_type_set (&mask
, 0);
4221 operand_type_set (&allowed
, 0);
4223 for (t
= current_templates
->start
;
4224 t
< current_templates
->end
;
4226 allowed
= operand_type_or (allowed
,
4227 t
->operand_types
[op
]);
4228 switch (guess_suffix
)
4230 case QWORD_MNEM_SUFFIX
:
4231 mask
.bitfield
.imm64
= 1;
4232 mask
.bitfield
.imm32s
= 1;
4234 case LONG_MNEM_SUFFIX
:
4235 mask
.bitfield
.imm32
= 1;
4237 case WORD_MNEM_SUFFIX
:
4238 mask
.bitfield
.imm16
= 1;
4240 case BYTE_MNEM_SUFFIX
:
4241 mask
.bitfield
.imm8
= 1;
4246 allowed
= operand_type_and (mask
, allowed
);
4247 if (!operand_type_all_zero (&allowed
))
4248 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4255 /* Try to use the smallest displacement type too. */
4257 optimize_disp (void)
4261 for (op
= i
.operands
; --op
>= 0;)
4262 if (operand_type_check (i
.types
[op
], disp
))
4264 if (i
.op
[op
].disps
->X_op
== O_constant
)
4266 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4268 if (i
.types
[op
].bitfield
.disp16
4269 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4271 /* If this operand is at most 16 bits, convert
4272 to a signed 16 bit number and don't use 64bit
4274 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4275 i
.types
[op
].bitfield
.disp64
= 0;
4277 if (i
.types
[op
].bitfield
.disp32
4278 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4280 /* If this operand is at most 32 bits, convert
4281 to a signed 32 bit number and don't use 64bit
4283 op_disp
&= (((offsetT
) 2 << 31) - 1);
4284 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4285 i
.types
[op
].bitfield
.disp64
= 0;
4287 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4289 i
.types
[op
].bitfield
.disp8
= 0;
4290 i
.types
[op
].bitfield
.disp16
= 0;
4291 i
.types
[op
].bitfield
.disp32
= 0;
4292 i
.types
[op
].bitfield
.disp32s
= 0;
4293 i
.types
[op
].bitfield
.disp64
= 0;
4297 else if (flag_code
== CODE_64BIT
)
4299 if (fits_in_signed_long (op_disp
))
4301 i
.types
[op
].bitfield
.disp64
= 0;
4302 i
.types
[op
].bitfield
.disp32s
= 1;
4304 if (i
.prefix
[ADDR_PREFIX
]
4305 && fits_in_unsigned_long (op_disp
))
4306 i
.types
[op
].bitfield
.disp32
= 1;
4308 if ((i
.types
[op
].bitfield
.disp32
4309 || i
.types
[op
].bitfield
.disp32s
4310 || i
.types
[op
].bitfield
.disp16
)
4311 && fits_in_signed_byte (op_disp
))
4312 i
.types
[op
].bitfield
.disp8
= 1;
4314 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4315 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4317 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4318 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4319 i
.types
[op
].bitfield
.disp8
= 0;
4320 i
.types
[op
].bitfield
.disp16
= 0;
4321 i
.types
[op
].bitfield
.disp32
= 0;
4322 i
.types
[op
].bitfield
.disp32s
= 0;
4323 i
.types
[op
].bitfield
.disp64
= 0;
4326 /* We only support 64bit displacement on constants. */
4327 i
.types
[op
].bitfield
.disp64
= 0;
4331 /* Check if operands are valid for the instruction. */
4334 check_VecOperands (const insn_template
*t
)
4338 /* Without VSIB byte, we can't have a vector register for index. */
4339 if (!t
->opcode_modifier
.vecsib
4341 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4342 || i
.index_reg
->reg_type
.bitfield
.regymm
4343 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4345 i
.error
= unsupported_vector_index_register
;
4349 /* Check if default mask is allowed. */
4350 if (t
->opcode_modifier
.nodefmask
4351 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4353 i
.error
= no_default_mask
;
4357 /* For VSIB byte, we need a vector register for index, and all vector
4358 registers must be distinct. */
4359 if (t
->opcode_modifier
.vecsib
)
4362 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4363 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4364 || (t
->opcode_modifier
.vecsib
== VecSIB256
4365 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4366 || (t
->opcode_modifier
.vecsib
== VecSIB512
4367 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4369 i
.error
= invalid_vsib_address
;
4373 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4374 if (i
.reg_operands
== 2 && !i
.mask
)
4376 gas_assert (i
.types
[0].bitfield
.regxmm
4377 || i
.types
[0].bitfield
.regymm
);
4378 gas_assert (i
.types
[2].bitfield
.regxmm
4379 || i
.types
[2].bitfield
.regymm
);
4380 if (operand_check
== check_none
)
4382 if (register_number (i
.op
[0].regs
)
4383 != register_number (i
.index_reg
)
4384 && register_number (i
.op
[2].regs
)
4385 != register_number (i
.index_reg
)
4386 && register_number (i
.op
[0].regs
)
4387 != register_number (i
.op
[2].regs
))
4389 if (operand_check
== check_error
)
4391 i
.error
= invalid_vector_register_set
;
4394 as_warn (_("mask, index, and destination registers should be distinct"));
4396 else if (i
.reg_operands
== 1 && i
.mask
)
4398 if ((i
.types
[1].bitfield
.regymm
4399 || i
.types
[1].bitfield
.regzmm
)
4400 && (register_number (i
.op
[1].regs
)
4401 == register_number (i
.index_reg
)))
4403 if (operand_check
== check_error
)
4405 i
.error
= invalid_vector_register_set
;
4408 if (operand_check
!= check_none
)
4409 as_warn (_("index and destination registers should be distinct"));
4414 /* Check if broadcast is supported by the instruction and is applied
4415 to the memory operand. */
4418 int broadcasted_opnd_size
;
4420 /* Check if specified broadcast is supported in this instruction,
4421 and it's applied to memory operand of DWORD or QWORD type,
4422 depending on VecESize. */
4423 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4424 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4425 || (t
->opcode_modifier
.vecesize
== 0
4426 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4427 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4428 || (t
->opcode_modifier
.vecesize
== 1
4429 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4430 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4433 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4434 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4435 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4436 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4437 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4438 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4439 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4440 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4441 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4445 if ((broadcasted_opnd_size
== 256
4446 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4447 || (broadcasted_opnd_size
== 512
4448 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4451 i
.error
= unsupported_broadcast
;
4455 /* If broadcast is supported in this instruction, we need to check if
4456 operand of one-element size isn't specified without broadcast. */
4457 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4459 /* Find memory operand. */
4460 for (op
= 0; op
< i
.operands
; op
++)
4461 if (operand_type_check (i
.types
[op
], anymem
))
4463 gas_assert (op
< i
.operands
);
4464 /* Check size of the memory operand. */
4465 if ((t
->opcode_modifier
.vecesize
== 0
4466 && i
.types
[op
].bitfield
.dword
)
4467 || (t
->opcode_modifier
.vecesize
== 1
4468 && i
.types
[op
].bitfield
.qword
))
4470 i
.error
= broadcast_needed
;
4475 /* Check if requested masking is supported. */
4477 && (!t
->opcode_modifier
.masking
4479 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4481 i
.error
= unsupported_masking
;
4485 /* Check if masking is applied to dest operand. */
4486 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4488 i
.error
= mask_not_on_destination
;
4495 if ((i
.rounding
->type
!= saeonly
4496 && !t
->opcode_modifier
.staticrounding
)
4497 || (i
.rounding
->type
== saeonly
4498 && (t
->opcode_modifier
.staticrounding
4499 || !t
->opcode_modifier
.sae
)))
4501 i
.error
= unsupported_rc_sae
;
4504 /* If the instruction has several immediate operands and one of
4505 them is rounding, the rounding operand should be the last
4506 immediate operand. */
4507 if (i
.imm_operands
> 1
4508 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4510 i
.error
= rc_sae_operand_not_last_imm
;
4515 /* Check vector Disp8 operand. */
4516 if (t
->opcode_modifier
.disp8memshift
)
4519 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4521 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4523 for (op
= 0; op
< i
.operands
; op
++)
4524 if (operand_type_check (i
.types
[op
], disp
)
4525 && i
.op
[op
].disps
->X_op
== O_constant
)
4527 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4528 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4529 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4532 i
.types
[op
].bitfield
.vec_disp8
= 1;
4535 /* Vector insn can only have Vec_Disp8/Disp32 in
4536 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4538 i
.types
[op
].bitfield
.disp8
= 0;
4539 if (flag_code
!= CODE_16BIT
)
4540 i
.types
[op
].bitfield
.disp16
= 0;
4543 else if (flag_code
!= CODE_16BIT
)
4545 /* One form of this instruction supports vector Disp8.
4546 Try vector Disp8 if we need to use Disp32. */
4547 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4549 i
.error
= try_vector_disp8
;
4561 /* Check if operands are valid for the instruction. Update VEX
4565 VEX_check_operands (const insn_template
*t
)
4567 /* VREX is only valid with EVEX prefix. */
4568 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4570 i
.error
= invalid_register_operand
;
4574 if (!t
->opcode_modifier
.vex
)
4577 /* Only check VEX_Imm4, which must be the first operand. */
4578 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4580 if (i
.op
[0].imms
->X_op
!= O_constant
4581 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4587 /* Turn off Imm8 so that update_imm won't complain. */
4588 i
.types
[0] = vec_imm4
;
4594 static const insn_template
*
4595 match_template (void)
4597 /* Points to template once we've found it. */
4598 const insn_template
*t
;
4599 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4600 i386_operand_type overlap4
;
4601 unsigned int found_reverse_match
;
4602 i386_opcode_modifier suffix_check
;
4603 i386_operand_type operand_types
[MAX_OPERANDS
];
4604 int addr_prefix_disp
;
4606 unsigned int found_cpu_match
;
4607 unsigned int check_register
;
4608 enum i386_error specific_error
= 0;
4610 #if MAX_OPERANDS != 5
4611 # error "MAX_OPERANDS must be 5."
4614 found_reverse_match
= 0;
4615 addr_prefix_disp
= -1;
4617 memset (&suffix_check
, 0, sizeof (suffix_check
));
4618 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4619 suffix_check
.no_bsuf
= 1;
4620 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4621 suffix_check
.no_wsuf
= 1;
4622 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4623 suffix_check
.no_ssuf
= 1;
4624 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4625 suffix_check
.no_lsuf
= 1;
4626 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4627 suffix_check
.no_qsuf
= 1;
4628 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4629 suffix_check
.no_ldsuf
= 1;
4631 /* Must have right number of operands. */
4632 i
.error
= number_of_operands_mismatch
;
4634 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4636 addr_prefix_disp
= -1;
4638 if (i
.operands
!= t
->operands
)
4641 /* Check processor support. */
4642 i
.error
= unsupported
;
4643 found_cpu_match
= (cpu_flags_match (t
)
4644 == CPU_FLAGS_PERFECT_MATCH
);
4645 if (!found_cpu_match
)
4648 /* Check old gcc support. */
4649 i
.error
= old_gcc_only
;
4650 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4653 /* Check AT&T mnemonic. */
4654 i
.error
= unsupported_with_intel_mnemonic
;
4655 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4658 /* Check AT&T/Intel syntax. */
4659 i
.error
= unsupported_syntax
;
4660 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4661 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4664 /* Check the suffix, except for some instructions in intel mode. */
4665 i
.error
= invalid_instruction_suffix
;
4666 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4667 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4668 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4669 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4670 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4671 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4672 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4675 if (!operand_size_match (t
))
4678 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4679 operand_types
[j
] = t
->operand_types
[j
];
4681 /* In general, don't allow 64-bit operands in 32-bit mode. */
4682 if (i
.suffix
== QWORD_MNEM_SUFFIX
4683 && flag_code
!= CODE_64BIT
4685 ? (!t
->opcode_modifier
.ignoresize
4686 && !intel_float_operand (t
->name
))
4687 : intel_float_operand (t
->name
) != 2)
4688 && ((!operand_types
[0].bitfield
.regmmx
4689 && !operand_types
[0].bitfield
.regxmm
4690 && !operand_types
[0].bitfield
.regymm
4691 && !operand_types
[0].bitfield
.regzmm
)
4692 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4693 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4694 && operand_types
[t
->operands
> 1].bitfield
.regymm
4695 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4696 && (t
->base_opcode
!= 0x0fc7
4697 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4700 /* In general, don't allow 32-bit operands on pre-386. */
4701 else if (i
.suffix
== LONG_MNEM_SUFFIX
4702 && !cpu_arch_flags
.bitfield
.cpui386
4704 ? (!t
->opcode_modifier
.ignoresize
4705 && !intel_float_operand (t
->name
))
4706 : intel_float_operand (t
->name
) != 2)
4707 && ((!operand_types
[0].bitfield
.regmmx
4708 && !operand_types
[0].bitfield
.regxmm
)
4709 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4710 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4713 /* Do not verify operands when there are none. */
4717 /* We've found a match; break out of loop. */
4721 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4722 into Disp32/Disp16/Disp32 operand. */
4723 if (i
.prefix
[ADDR_PREFIX
] != 0)
4725 /* There should be only one Disp operand. */
4729 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4731 if (operand_types
[j
].bitfield
.disp16
)
4733 addr_prefix_disp
= j
;
4734 operand_types
[j
].bitfield
.disp32
= 1;
4735 operand_types
[j
].bitfield
.disp16
= 0;
4741 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4743 if (operand_types
[j
].bitfield
.disp32
)
4745 addr_prefix_disp
= j
;
4746 operand_types
[j
].bitfield
.disp32
= 0;
4747 operand_types
[j
].bitfield
.disp16
= 1;
4753 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4755 if (operand_types
[j
].bitfield
.disp64
)
4757 addr_prefix_disp
= j
;
4758 operand_types
[j
].bitfield
.disp64
= 0;
4759 operand_types
[j
].bitfield
.disp32
= 1;
4767 /* We check register size if needed. */
4768 check_register
= t
->opcode_modifier
.checkregsize
;
4769 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4770 switch (t
->operands
)
4773 if (!operand_type_match (overlap0
, i
.types
[0]))
4777 /* xchg %eax, %eax is a special case. It is an aliase for nop
4778 only in 32bit mode and we can use opcode 0x90. In 64bit
4779 mode, we can't use 0x90 for xchg %eax, %eax since it should
4780 zero-extend %eax to %rax. */
4781 if (flag_code
== CODE_64BIT
4782 && t
->base_opcode
== 0x90
4783 && operand_type_equal (&i
.types
[0], &acc32
)
4784 && operand_type_equal (&i
.types
[1], &acc32
))
4788 /* If we swap operand in encoding, we either match
4789 the next one or reverse direction of operands. */
4790 if (t
->opcode_modifier
.s
)
4792 else if (t
->opcode_modifier
.d
)
4797 /* If we swap operand in encoding, we match the next one. */
4798 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4802 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4803 if (!operand_type_match (overlap0
, i
.types
[0])
4804 || !operand_type_match (overlap1
, i
.types
[1])
4806 && !operand_type_register_match (overlap0
, i
.types
[0],
4808 overlap1
, i
.types
[1],
4811 /* Check if other direction is valid ... */
4812 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4816 /* Try reversing direction of operands. */
4817 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4818 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4819 if (!operand_type_match (overlap0
, i
.types
[0])
4820 || !operand_type_match (overlap1
, i
.types
[1])
4822 && !operand_type_register_match (overlap0
,
4829 /* Does not match either direction. */
4832 /* found_reverse_match holds which of D or FloatDR
4834 if (t
->opcode_modifier
.d
)
4835 found_reverse_match
= Opcode_D
;
4836 else if (t
->opcode_modifier
.floatd
)
4837 found_reverse_match
= Opcode_FloatD
;
4839 found_reverse_match
= 0;
4840 if (t
->opcode_modifier
.floatr
)
4841 found_reverse_match
|= Opcode_FloatR
;
4845 /* Found a forward 2 operand match here. */
4846 switch (t
->operands
)
4849 overlap4
= operand_type_and (i
.types
[4],
4852 overlap3
= operand_type_and (i
.types
[3],
4855 overlap2
= operand_type_and (i
.types
[2],
4860 switch (t
->operands
)
4863 if (!operand_type_match (overlap4
, i
.types
[4])
4864 || !operand_type_register_match (overlap3
,
4872 if (!operand_type_match (overlap3
, i
.types
[3])
4874 && !operand_type_register_match (overlap2
,
4882 /* Here we make use of the fact that there are no
4883 reverse match 3 operand instructions, and all 3
4884 operand instructions only need to be checked for
4885 register consistency between operands 2 and 3. */
4886 if (!operand_type_match (overlap2
, i
.types
[2])
4888 && !operand_type_register_match (overlap1
,
4898 /* Found either forward/reverse 2, 3 or 4 operand match here:
4899 slip through to break. */
4901 if (!found_cpu_match
)
4903 found_reverse_match
= 0;
4907 /* Check if vector and VEX operands are valid. */
4908 if (check_VecOperands (t
) || VEX_check_operands (t
))
4910 specific_error
= i
.error
;
4914 /* We've found a match; break out of loop. */
4918 if (t
== current_templates
->end
)
4920 /* We found no match. */
4921 const char *err_msg
;
4922 switch (specific_error
? specific_error
: i
.error
)
4926 case operand_size_mismatch
:
4927 err_msg
= _("operand size mismatch");
4929 case operand_type_mismatch
:
4930 err_msg
= _("operand type mismatch");
4932 case register_type_mismatch
:
4933 err_msg
= _("register type mismatch");
4935 case number_of_operands_mismatch
:
4936 err_msg
= _("number of operands mismatch");
4938 case invalid_instruction_suffix
:
4939 err_msg
= _("invalid instruction suffix");
4942 err_msg
= _("constant doesn't fit in 4 bits");
4945 err_msg
= _("only supported with old gcc");
4947 case unsupported_with_intel_mnemonic
:
4948 err_msg
= _("unsupported with Intel mnemonic");
4950 case unsupported_syntax
:
4951 err_msg
= _("unsupported syntax");
4954 as_bad (_("unsupported instruction `%s'"),
4955 current_templates
->start
->name
);
4957 case invalid_vsib_address
:
4958 err_msg
= _("invalid VSIB address");
4960 case invalid_vector_register_set
:
4961 err_msg
= _("mask, index, and destination registers must be distinct");
4963 case unsupported_vector_index_register
:
4964 err_msg
= _("unsupported vector index register");
4966 case unsupported_broadcast
:
4967 err_msg
= _("unsupported broadcast");
4969 case broadcast_not_on_src_operand
:
4970 err_msg
= _("broadcast not on source memory operand");
4972 case broadcast_needed
:
4973 err_msg
= _("broadcast is needed for operand of such type");
4975 case unsupported_masking
:
4976 err_msg
= _("unsupported masking");
4978 case mask_not_on_destination
:
4979 err_msg
= _("mask not on destination operand");
4981 case no_default_mask
:
4982 err_msg
= _("default mask isn't allowed");
4984 case unsupported_rc_sae
:
4985 err_msg
= _("unsupported static rounding/sae");
4987 case rc_sae_operand_not_last_imm
:
4989 err_msg
= _("RC/SAE operand must precede immediate operands");
4991 err_msg
= _("RC/SAE operand must follow immediate operands");
4993 case invalid_register_operand
:
4994 err_msg
= _("invalid register operand");
4997 as_bad (_("%s for `%s'"), err_msg
,
4998 current_templates
->start
->name
);
5002 if (!quiet_warnings
)
5005 && (i
.types
[0].bitfield
.jumpabsolute
5006 != operand_types
[0].bitfield
.jumpabsolute
))
5008 as_warn (_("indirect %s without `*'"), t
->name
);
5011 if (t
->opcode_modifier
.isprefix
5012 && t
->opcode_modifier
.ignoresize
)
5014 /* Warn them that a data or address size prefix doesn't
5015 affect assembly of the next line of code. */
5016 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5020 /* Copy the template we found. */
5023 if (addr_prefix_disp
!= -1)
5024 i
.tm
.operand_types
[addr_prefix_disp
]
5025 = operand_types
[addr_prefix_disp
];
5027 if (found_reverse_match
)
5029 /* If we found a reverse match we must alter the opcode
5030 direction bit. found_reverse_match holds bits to change
5031 (different for int & float insns). */
5033 i
.tm
.base_opcode
^= found_reverse_match
;
5035 i
.tm
.operand_types
[0] = operand_types
[1];
5036 i
.tm
.operand_types
[1] = operand_types
[0];
5045 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5046 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5048 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5050 as_bad (_("`%s' operand %d must use `%ses' segment"),
5056 /* There's only ever one segment override allowed per instruction.
5057 This instruction possibly has a legal segment override on the
5058 second operand, so copy the segment to where non-string
5059 instructions store it, allowing common code. */
5060 i
.seg
[0] = i
.seg
[1];
5062 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5064 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5066 as_bad (_("`%s' operand %d must use `%ses' segment"),
5077 process_suffix (void)
5079 /* If matched instruction specifies an explicit instruction mnemonic
5081 if (i
.tm
.opcode_modifier
.size16
)
5082 i
.suffix
= WORD_MNEM_SUFFIX
;
5083 else if (i
.tm
.opcode_modifier
.size32
)
5084 i
.suffix
= LONG_MNEM_SUFFIX
;
5085 else if (i
.tm
.opcode_modifier
.size64
)
5086 i
.suffix
= QWORD_MNEM_SUFFIX
;
5087 else if (i
.reg_operands
)
5089 /* If there's no instruction mnemonic suffix we try to invent one
5090 based on register operands. */
5093 /* We take i.suffix from the last register operand specified,
5094 Destination register type is more significant than source
5095 register type. crc32 in SSE4.2 prefers source register
5097 if (i
.tm
.base_opcode
== 0xf20f38f1)
5099 if (i
.types
[0].bitfield
.reg16
)
5100 i
.suffix
= WORD_MNEM_SUFFIX
;
5101 else if (i
.types
[0].bitfield
.reg32
)
5102 i
.suffix
= LONG_MNEM_SUFFIX
;
5103 else if (i
.types
[0].bitfield
.reg64
)
5104 i
.suffix
= QWORD_MNEM_SUFFIX
;
5106 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5108 if (i
.types
[0].bitfield
.reg8
)
5109 i
.suffix
= BYTE_MNEM_SUFFIX
;
5116 if (i
.tm
.base_opcode
== 0xf20f38f1
5117 || i
.tm
.base_opcode
== 0xf20f38f0)
5119 /* We have to know the operand size for crc32. */
5120 as_bad (_("ambiguous memory operand size for `%s`"),
5125 for (op
= i
.operands
; --op
>= 0;)
5126 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5128 if (i
.types
[op
].bitfield
.reg8
)
5130 i
.suffix
= BYTE_MNEM_SUFFIX
;
5133 else if (i
.types
[op
].bitfield
.reg16
)
5135 i
.suffix
= WORD_MNEM_SUFFIX
;
5138 else if (i
.types
[op
].bitfield
.reg32
)
5140 i
.suffix
= LONG_MNEM_SUFFIX
;
5143 else if (i
.types
[op
].bitfield
.reg64
)
5145 i
.suffix
= QWORD_MNEM_SUFFIX
;
5151 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5154 && i
.tm
.opcode_modifier
.ignoresize
5155 && i
.tm
.opcode_modifier
.no_bsuf
)
5157 else if (!check_byte_reg ())
5160 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5163 && i
.tm
.opcode_modifier
.ignoresize
5164 && i
.tm
.opcode_modifier
.no_lsuf
)
5166 else if (!check_long_reg ())
5169 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5172 && i
.tm
.opcode_modifier
.ignoresize
5173 && i
.tm
.opcode_modifier
.no_qsuf
)
5175 else if (!check_qword_reg ())
5178 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5181 && i
.tm
.opcode_modifier
.ignoresize
5182 && i
.tm
.opcode_modifier
.no_wsuf
)
5184 else if (!check_word_reg ())
5187 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5188 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5189 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5191 /* Skip if the instruction has x/y/z suffix. match_template
5192 should check if it is a valid suffix. */
5194 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5195 /* Do nothing if the instruction is going to ignore the prefix. */
5200 else if (i
.tm
.opcode_modifier
.defaultsize
5202 /* exclude fldenv/frstor/fsave/fstenv */
5203 && i
.tm
.opcode_modifier
.no_ssuf
)
5205 i
.suffix
= stackop_size
;
5207 else if (intel_syntax
5209 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5210 || i
.tm
.opcode_modifier
.jumpbyte
5211 || i
.tm
.opcode_modifier
.jumpintersegment
5212 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5213 && i
.tm
.extension_opcode
<= 3)))
5218 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5220 i
.suffix
= QWORD_MNEM_SUFFIX
;
5224 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5225 i
.suffix
= LONG_MNEM_SUFFIX
;
5228 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5229 i
.suffix
= WORD_MNEM_SUFFIX
;
5238 if (i
.tm
.opcode_modifier
.w
)
5240 as_bad (_("no instruction mnemonic suffix given and "
5241 "no register operands; can't size instruction"));
5247 unsigned int suffixes
;
5249 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5250 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5252 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5254 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5256 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5258 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5261 /* There are more than suffix matches. */
5262 if (i
.tm
.opcode_modifier
.w
5263 || ((suffixes
& (suffixes
- 1))
5264 && !i
.tm
.opcode_modifier
.defaultsize
5265 && !i
.tm
.opcode_modifier
.ignoresize
))
5267 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5273 /* Change the opcode based on the operand size given by i.suffix;
5274 We don't need to change things for byte insns. */
5277 && i
.suffix
!= BYTE_MNEM_SUFFIX
5278 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5279 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5280 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5282 /* It's not a byte, select word/dword operation. */
5283 if (i
.tm
.opcode_modifier
.w
)
5285 if (i
.tm
.opcode_modifier
.shortform
)
5286 i
.tm
.base_opcode
|= 8;
5288 i
.tm
.base_opcode
|= 1;
5291 /* Now select between word & dword operations via the operand
5292 size prefix, except for instructions that will ignore this
5294 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5296 /* The address size override prefix changes the size of the
5298 if ((flag_code
== CODE_32BIT
5299 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5300 || (flag_code
!= CODE_32BIT
5301 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5302 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5305 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5306 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5307 && !i
.tm
.opcode_modifier
.ignoresize
5308 && !i
.tm
.opcode_modifier
.floatmf
5309 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5310 || (flag_code
== CODE_64BIT
5311 && i
.tm
.opcode_modifier
.jumpbyte
)))
5313 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5315 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5316 prefix
= ADDR_PREFIX_OPCODE
;
5318 if (!add_prefix (prefix
))
5322 /* Set mode64 for an operand. */
5323 if (i
.suffix
== QWORD_MNEM_SUFFIX
5324 && flag_code
== CODE_64BIT
5325 && !i
.tm
.opcode_modifier
.norex64
)
5327 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5328 need rex64. cmpxchg8b is also a special case. */
5329 if (! (i
.operands
== 2
5330 && i
.tm
.base_opcode
== 0x90
5331 && i
.tm
.extension_opcode
== None
5332 && operand_type_equal (&i
.types
[0], &acc64
)
5333 && operand_type_equal (&i
.types
[1], &acc64
))
5334 && ! (i
.operands
== 1
5335 && i
.tm
.base_opcode
== 0xfc7
5336 && i
.tm
.extension_opcode
== 1
5337 && !operand_type_check (i
.types
[0], reg
)
5338 && operand_type_check (i
.types
[0], anymem
)))
5342 /* Size floating point instruction. */
5343 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5344 if (i
.tm
.opcode_modifier
.floatmf
)
5345 i
.tm
.base_opcode
^= 4;
5352 check_byte_reg (void)
5356 for (op
= i
.operands
; --op
>= 0;)
5358 /* If this is an eight bit register, it's OK. If it's the 16 or
5359 32 bit version of an eight bit register, we will just use the
5360 low portion, and that's OK too. */
5361 if (i
.types
[op
].bitfield
.reg8
)
5364 /* I/O port address operands are OK too. */
5365 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5368 /* crc32 doesn't generate this warning. */
5369 if (i
.tm
.base_opcode
== 0xf20f38f0)
5372 if ((i
.types
[op
].bitfield
.reg16
5373 || i
.types
[op
].bitfield
.reg32
5374 || i
.types
[op
].bitfield
.reg64
)
5375 && i
.op
[op
].regs
->reg_num
< 4
5376 /* Prohibit these changes in 64bit mode, since the lowering
5377 would be more complicated. */
5378 && flag_code
!= CODE_64BIT
)
5380 #if REGISTER_WARNINGS
5381 if (!quiet_warnings
)
5382 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5384 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5385 ? REGNAM_AL
- REGNAM_AX
5386 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5388 i
.op
[op
].regs
->reg_name
,
5393 /* Any other register is bad. */
5394 if (i
.types
[op
].bitfield
.reg16
5395 || i
.types
[op
].bitfield
.reg32
5396 || i
.types
[op
].bitfield
.reg64
5397 || i
.types
[op
].bitfield
.regmmx
5398 || i
.types
[op
].bitfield
.regxmm
5399 || i
.types
[op
].bitfield
.regymm
5400 || i
.types
[op
].bitfield
.regzmm
5401 || i
.types
[op
].bitfield
.sreg2
5402 || i
.types
[op
].bitfield
.sreg3
5403 || i
.types
[op
].bitfield
.control
5404 || i
.types
[op
].bitfield
.debug
5405 || i
.types
[op
].bitfield
.test
5406 || i
.types
[op
].bitfield
.floatreg
5407 || i
.types
[op
].bitfield
.floatacc
)
5409 as_bad (_("`%s%s' not allowed with `%s%c'"),
5411 i
.op
[op
].regs
->reg_name
,
5421 check_long_reg (void)
5425 for (op
= i
.operands
; --op
>= 0;)
5426 /* Reject eight bit registers, except where the template requires
5427 them. (eg. movzb) */
5428 if (i
.types
[op
].bitfield
.reg8
5429 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5430 || i
.tm
.operand_types
[op
].bitfield
.reg32
5431 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5433 as_bad (_("`%s%s' not allowed with `%s%c'"),
5435 i
.op
[op
].regs
->reg_name
,
5440 /* Warn if the e prefix on a general reg is missing. */
5441 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5442 && i
.types
[op
].bitfield
.reg16
5443 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5444 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5446 /* Prohibit these changes in the 64bit mode, since the
5447 lowering is more complicated. */
5448 if (flag_code
== CODE_64BIT
)
5450 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5451 register_prefix
, i
.op
[op
].regs
->reg_name
,
5455 #if REGISTER_WARNINGS
5456 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5458 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5459 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5462 /* Warn if the r prefix on a general reg is present. */
5463 else if (i
.types
[op
].bitfield
.reg64
5464 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5465 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5468 && i
.tm
.opcode_modifier
.toqword
5469 && !i
.types
[0].bitfield
.regxmm
)
5471 /* Convert to QWORD. We want REX byte. */
5472 i
.suffix
= QWORD_MNEM_SUFFIX
;
5476 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5477 register_prefix
, i
.op
[op
].regs
->reg_name
,
5486 check_qword_reg (void)
5490 for (op
= i
.operands
; --op
>= 0; )
5491 /* Reject eight bit registers, except where the template requires
5492 them. (eg. movzb) */
5493 if (i
.types
[op
].bitfield
.reg8
5494 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5495 || i
.tm
.operand_types
[op
].bitfield
.reg32
5496 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5498 as_bad (_("`%s%s' not allowed with `%s%c'"),
5500 i
.op
[op
].regs
->reg_name
,
5505 /* Warn if the r prefix on a general reg is missing. */
5506 else if ((i
.types
[op
].bitfield
.reg16
5507 || i
.types
[op
].bitfield
.reg32
)
5508 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5509 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5511 /* Prohibit these changes in the 64bit mode, since the
5512 lowering is more complicated. */
5514 && i
.tm
.opcode_modifier
.todword
5515 && !i
.types
[0].bitfield
.regxmm
)
5517 /* Convert to DWORD. We don't want REX byte. */
5518 i
.suffix
= LONG_MNEM_SUFFIX
;
5522 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5523 register_prefix
, i
.op
[op
].regs
->reg_name
,
5532 check_word_reg (void)
5535 for (op
= i
.operands
; --op
>= 0;)
5536 /* Reject eight bit registers, except where the template requires
5537 them. (eg. movzb) */
5538 if (i
.types
[op
].bitfield
.reg8
5539 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5540 || i
.tm
.operand_types
[op
].bitfield
.reg32
5541 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5543 as_bad (_("`%s%s' not allowed with `%s%c'"),
5545 i
.op
[op
].regs
->reg_name
,
5550 /* Warn if the e or r prefix on a general reg is present. */
5551 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5552 && (i
.types
[op
].bitfield
.reg32
5553 || i
.types
[op
].bitfield
.reg64
)
5554 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5555 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5557 /* Prohibit these changes in the 64bit mode, since the
5558 lowering is more complicated. */
5559 if (flag_code
== CODE_64BIT
)
5561 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5562 register_prefix
, i
.op
[op
].regs
->reg_name
,
5566 #if REGISTER_WARNINGS
5567 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5569 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5570 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5577 update_imm (unsigned int j
)
5579 i386_operand_type overlap
= i
.types
[j
];
5580 if ((overlap
.bitfield
.imm8
5581 || overlap
.bitfield
.imm8s
5582 || overlap
.bitfield
.imm16
5583 || overlap
.bitfield
.imm32
5584 || overlap
.bitfield
.imm32s
5585 || overlap
.bitfield
.imm64
)
5586 && !operand_type_equal (&overlap
, &imm8
)
5587 && !operand_type_equal (&overlap
, &imm8s
)
5588 && !operand_type_equal (&overlap
, &imm16
)
5589 && !operand_type_equal (&overlap
, &imm32
)
5590 && !operand_type_equal (&overlap
, &imm32s
)
5591 && !operand_type_equal (&overlap
, &imm64
))
5595 i386_operand_type temp
;
5597 operand_type_set (&temp
, 0);
5598 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5600 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5601 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5603 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5604 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5605 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5607 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5608 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5611 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5614 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5615 || operand_type_equal (&overlap
, &imm16_32
)
5616 || operand_type_equal (&overlap
, &imm16_32s
))
5618 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5623 if (!operand_type_equal (&overlap
, &imm8
)
5624 && !operand_type_equal (&overlap
, &imm8s
)
5625 && !operand_type_equal (&overlap
, &imm16
)
5626 && !operand_type_equal (&overlap
, &imm32
)
5627 && !operand_type_equal (&overlap
, &imm32s
)
5628 && !operand_type_equal (&overlap
, &imm64
))
5630 as_bad (_("no instruction mnemonic suffix given; "
5631 "can't determine immediate size"));
5635 i
.types
[j
] = overlap
;
5645 /* Update the first 2 immediate operands. */
5646 n
= i
.operands
> 2 ? 2 : i
.operands
;
5649 for (j
= 0; j
< n
; j
++)
5650 if (update_imm (j
) == 0)
5653 /* The 3rd operand can't be immediate operand. */
5654 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5661 bad_implicit_operand (int xmm
)
5663 const char *ireg
= xmm
? "xmm0" : "ymm0";
5666 as_bad (_("the last operand of `%s' must be `%s%s'"),
5667 i
.tm
.name
, register_prefix
, ireg
);
5669 as_bad (_("the first operand of `%s' must be `%s%s'"),
5670 i
.tm
.name
, register_prefix
, ireg
);
5675 process_operands (void)
5677 /* Default segment register this instruction will use for memory
5678 accesses. 0 means unknown. This is only for optimizing out
5679 unnecessary segment overrides. */
5680 const seg_entry
*default_seg
= 0;
5682 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5684 unsigned int dupl
= i
.operands
;
5685 unsigned int dest
= dupl
- 1;
5688 /* The destination must be an xmm register. */
5689 gas_assert (i
.reg_operands
5690 && MAX_OPERANDS
> dupl
5691 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5693 if (i
.tm
.opcode_modifier
.firstxmm0
)
5695 /* The first operand is implicit and must be xmm0. */
5696 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5697 if (register_number (i
.op
[0].regs
) != 0)
5698 return bad_implicit_operand (1);
5700 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5702 /* Keep xmm0 for instructions with VEX prefix and 3
5708 /* We remove the first xmm0 and keep the number of
5709 operands unchanged, which in fact duplicates the
5711 for (j
= 1; j
< i
.operands
; j
++)
5713 i
.op
[j
- 1] = i
.op
[j
];
5714 i
.types
[j
- 1] = i
.types
[j
];
5715 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5719 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5721 gas_assert ((MAX_OPERANDS
- 1) > dupl
5722 && (i
.tm
.opcode_modifier
.vexsources
5725 /* Add the implicit xmm0 for instructions with VEX prefix
5727 for (j
= i
.operands
; j
> 0; j
--)
5729 i
.op
[j
] = i
.op
[j
- 1];
5730 i
.types
[j
] = i
.types
[j
- 1];
5731 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5734 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5735 i
.types
[0] = regxmm
;
5736 i
.tm
.operand_types
[0] = regxmm
;
5739 i
.reg_operands
+= 2;
5744 i
.op
[dupl
] = i
.op
[dest
];
5745 i
.types
[dupl
] = i
.types
[dest
];
5746 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5755 i
.op
[dupl
] = i
.op
[dest
];
5756 i
.types
[dupl
] = i
.types
[dest
];
5757 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5760 if (i
.tm
.opcode_modifier
.immext
)
5763 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5767 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5768 gas_assert (i
.reg_operands
5769 && (operand_type_equal (&i
.types
[0], ®xmm
)
5770 || operand_type_equal (&i
.types
[0], ®ymm
)
5771 || operand_type_equal (&i
.types
[0], ®zmm
)));
5772 if (register_number (i
.op
[0].regs
) != 0)
5773 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5775 for (j
= 1; j
< i
.operands
; j
++)
5777 i
.op
[j
- 1] = i
.op
[j
];
5778 i
.types
[j
- 1] = i
.types
[j
];
5780 /* We need to adjust fields in i.tm since they are used by
5781 build_modrm_byte. */
5782 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5789 else if (i
.tm
.opcode_modifier
.regkludge
)
5791 /* The imul $imm, %reg instruction is converted into
5792 imul $imm, %reg, %reg, and the clr %reg instruction
5793 is converted into xor %reg, %reg. */
5795 unsigned int first_reg_op
;
5797 if (operand_type_check (i
.types
[0], reg
))
5801 /* Pretend we saw the extra register operand. */
5802 gas_assert (i
.reg_operands
== 1
5803 && i
.op
[first_reg_op
+ 1].regs
== 0);
5804 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5805 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5810 if (i
.tm
.opcode_modifier
.shortform
)
5812 if (i
.types
[0].bitfield
.sreg2
5813 || i
.types
[0].bitfield
.sreg3
)
5815 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5816 && i
.op
[0].regs
->reg_num
== 1)
5818 as_bad (_("you can't `pop %scs'"), register_prefix
);
5821 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5822 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5827 /* The register or float register operand is in operand
5831 if (i
.types
[0].bitfield
.floatreg
5832 || operand_type_check (i
.types
[0], reg
))
5836 /* Register goes in low 3 bits of opcode. */
5837 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5838 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5840 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5842 /* Warn about some common errors, but press on regardless.
5843 The first case can be generated by gcc (<= 2.8.1). */
5844 if (i
.operands
== 2)
5846 /* Reversed arguments on faddp, fsubp, etc. */
5847 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5848 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5849 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5853 /* Extraneous `l' suffix on fp insn. */
5854 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5855 register_prefix
, i
.op
[0].regs
->reg_name
);
5860 else if (i
.tm
.opcode_modifier
.modrm
)
5862 /* The opcode is completed (modulo i.tm.extension_opcode which
5863 must be put into the modrm byte). Now, we make the modrm and
5864 index base bytes based on all the info we've collected. */
5866 default_seg
= build_modrm_byte ();
5868 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5872 else if (i
.tm
.opcode_modifier
.isstring
)
5874 /* For the string instructions that allow a segment override
5875 on one of their operands, the default segment is ds. */
5879 if (i
.tm
.base_opcode
== 0x8d /* lea */
5882 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5884 /* If a segment was explicitly specified, and the specified segment
5885 is not the default, use an opcode prefix to select it. If we
5886 never figured out what the default segment is, then default_seg
5887 will be zero at this point, and the specified segment prefix will
5889 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5891 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5897 static const seg_entry
*
5898 build_modrm_byte (void)
5900 const seg_entry
*default_seg
= 0;
5901 unsigned int source
, dest
;
5904 /* The first operand of instructions with VEX prefix and 3 sources
5905 must be VEX_Imm4. */
5906 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5909 unsigned int nds
, reg_slot
;
5912 if (i
.tm
.opcode_modifier
.veximmext
5913 && i
.tm
.opcode_modifier
.immext
)
5915 dest
= i
.operands
- 2;
5916 gas_assert (dest
== 3);
5919 dest
= i
.operands
- 1;
5922 /* There are 2 kinds of instructions:
5923 1. 5 operands: 4 register operands or 3 register operands
5924 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5925 VexW0 or VexW1. The destination must be either XMM, YMM or
5927 2. 4 operands: 4 register operands or 3 register operands
5928 plus 1 memory operand, VexXDS, and VexImmExt */
5929 gas_assert ((i
.reg_operands
== 4
5930 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5931 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5932 && (i
.tm
.opcode_modifier
.veximmext
5933 || (i
.imm_operands
== 1
5934 && i
.types
[0].bitfield
.vec_imm4
5935 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5936 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5937 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5938 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5939 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5941 if (i
.imm_operands
== 0)
5943 /* When there is no immediate operand, generate an 8bit
5944 immediate operand to encode the first operand. */
5945 exp
= &im_expressions
[i
.imm_operands
++];
5946 i
.op
[i
.operands
].imms
= exp
;
5947 i
.types
[i
.operands
] = imm8
;
5949 /* If VexW1 is set, the first operand is the source and
5950 the second operand is encoded in the immediate operand. */
5951 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5962 /* FMA swaps REG and NDS. */
5963 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5971 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5973 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5975 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5977 exp
->X_op
= O_constant
;
5978 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
5979 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
5983 unsigned int imm_slot
;
5985 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5987 /* If VexW0 is set, the third operand is the source and
5988 the second operand is encoded in the immediate
5995 /* VexW1 is set, the second operand is the source and
5996 the third operand is encoded in the immediate
6002 if (i
.tm
.opcode_modifier
.immext
)
6004 /* When ImmExt is set, the immdiate byte is the last
6006 imm_slot
= i
.operands
- 1;
6014 /* Turn on Imm8 so that output_imm will generate it. */
6015 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6018 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6020 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6022 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6024 i
.op
[imm_slot
].imms
->X_add_number
6025 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6026 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6029 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6030 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6032 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6034 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6039 /* i.reg_operands MUST be the number of real register operands;
6040 implicit registers do not count. If there are 3 register
6041 operands, it must be a instruction with VexNDS. For a
6042 instruction with VexNDD, the destination register is encoded
6043 in VEX prefix. If there are 4 register operands, it must be
6044 a instruction with VEX prefix and 3 sources. */
6045 if (i
.mem_operands
== 0
6046 && ((i
.reg_operands
== 2
6047 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6048 || (i
.reg_operands
== 3
6049 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6050 || (i
.reg_operands
== 4 && vex_3_sources
)))
6058 /* When there are 3 operands, one of them may be immediate,
6059 which may be the first or the last operand. Otherwise,
6060 the first operand must be shift count register (cl) or it
6061 is an instruction with VexNDS. */
6062 gas_assert (i
.imm_operands
== 1
6063 || (i
.imm_operands
== 0
6064 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6065 || i
.types
[0].bitfield
.shiftcount
)));
6066 if (operand_type_check (i
.types
[0], imm
)
6067 || i
.types
[0].bitfield
.shiftcount
)
6073 /* When there are 4 operands, the first two must be 8bit
6074 immediate operands. The source operand will be the 3rd
6077 For instructions with VexNDS, if the first operand
6078 an imm8, the source operand is the 2nd one. If the last
6079 operand is imm8, the source operand is the first one. */
6080 gas_assert ((i
.imm_operands
== 2
6081 && i
.types
[0].bitfield
.imm8
6082 && i
.types
[1].bitfield
.imm8
)
6083 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6084 && i
.imm_operands
== 1
6085 && (i
.types
[0].bitfield
.imm8
6086 || i
.types
[i
.operands
- 1].bitfield
.imm8
6088 if (i
.imm_operands
== 2)
6092 if (i
.types
[0].bitfield
.imm8
)
6099 if (i
.tm
.opcode_modifier
.evex
)
6101 /* For EVEX instructions, when there are 5 operands, the
6102 first one must be immediate operand. If the second one
6103 is immediate operand, the source operand is the 3th
6104 one. If the last one is immediate operand, the source
6105 operand is the 2nd one. */
6106 gas_assert (i
.imm_operands
== 2
6107 && i
.tm
.opcode_modifier
.sae
6108 && operand_type_check (i
.types
[0], imm
));
6109 if (operand_type_check (i
.types
[1], imm
))
6111 else if (operand_type_check (i
.types
[4], imm
))
6125 /* RC/SAE operand could be between DEST and SRC. That happens
6126 when one operand is GPR and the other one is XMM/YMM/ZMM
6128 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6131 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6133 /* For instructions with VexNDS, the register-only source
6134 operand must be 32/64bit integer, XMM, YMM or ZMM
6135 register. It is encoded in VEX prefix. We need to
6136 clear RegMem bit before calling operand_type_equal. */
6138 i386_operand_type op
;
6141 /* Check register-only source operand when two source
6142 operands are swapped. */
6143 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6144 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6152 op
= i
.tm
.operand_types
[vvvv
];
6153 op
.bitfield
.regmem
= 0;
6154 if ((dest
+ 1) >= i
.operands
6155 || (!op
.bitfield
.reg32
6156 && op
.bitfield
.reg64
6157 && !operand_type_equal (&op
, ®xmm
)
6158 && !operand_type_equal (&op
, ®ymm
)
6159 && !operand_type_equal (&op
, ®zmm
)
6160 && !operand_type_equal (&op
, ®mask
)))
6162 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6168 /* One of the register operands will be encoded in the i.tm.reg
6169 field, the other in the combined i.tm.mode and i.tm.regmem
6170 fields. If no form of this instruction supports a memory
6171 destination operand, then we assume the source operand may
6172 sometimes be a memory operand and so we need to store the
6173 destination in the i.rm.reg field. */
6174 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6175 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6177 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6178 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6179 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6181 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6183 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6185 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6190 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6191 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6192 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6194 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6196 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6198 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6201 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6203 if (!i
.types
[0].bitfield
.control
6204 && !i
.types
[1].bitfield
.control
)
6206 i
.rex
&= ~(REX_R
| REX_B
);
6207 add_prefix (LOCK_PREFIX_OPCODE
);
6211 { /* If it's not 2 reg operands... */
6216 unsigned int fake_zero_displacement
= 0;
6219 for (op
= 0; op
< i
.operands
; op
++)
6220 if (operand_type_check (i
.types
[op
], anymem
))
6222 gas_assert (op
< i
.operands
);
6224 if (i
.tm
.opcode_modifier
.vecsib
)
6226 if (i
.index_reg
->reg_num
== RegEiz
6227 || i
.index_reg
->reg_num
== RegRiz
)
6230 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6233 i
.sib
.base
= NO_BASE_REGISTER
;
6234 i
.sib
.scale
= i
.log2_scale_factor
;
6235 /* No Vec_Disp8 if there is no base. */
6236 i
.types
[op
].bitfield
.vec_disp8
= 0;
6237 i
.types
[op
].bitfield
.disp8
= 0;
6238 i
.types
[op
].bitfield
.disp16
= 0;
6239 i
.types
[op
].bitfield
.disp64
= 0;
6240 if (flag_code
!= CODE_64BIT
)
6242 /* Must be 32 bit */
6243 i
.types
[op
].bitfield
.disp32
= 1;
6244 i
.types
[op
].bitfield
.disp32s
= 0;
6248 i
.types
[op
].bitfield
.disp32
= 0;
6249 i
.types
[op
].bitfield
.disp32s
= 1;
6252 i
.sib
.index
= i
.index_reg
->reg_num
;
6253 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6255 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6261 if (i
.base_reg
== 0)
6264 if (!i
.disp_operands
)
6266 fake_zero_displacement
= 1;
6267 /* Instructions with VSIB byte need 32bit displacement
6268 if there is no base register. */
6269 if (i
.tm
.opcode_modifier
.vecsib
)
6270 i
.types
[op
].bitfield
.disp32
= 1;
6272 if (i
.index_reg
== 0)
6274 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6275 /* Operand is just <disp> */
6276 if (flag_code
== CODE_64BIT
)
6278 /* 64bit mode overwrites the 32bit absolute
6279 addressing by RIP relative addressing and
6280 absolute addressing is encoded by one of the
6281 redundant SIB forms. */
6282 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6283 i
.sib
.base
= NO_BASE_REGISTER
;
6284 i
.sib
.index
= NO_INDEX_REGISTER
;
6285 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6286 ? disp32s
: disp32
);
6288 else if ((flag_code
== CODE_16BIT
)
6289 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6291 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6292 i
.types
[op
] = disp16
;
6296 i
.rm
.regmem
= NO_BASE_REGISTER
;
6297 i
.types
[op
] = disp32
;
6300 else if (!i
.tm
.opcode_modifier
.vecsib
)
6302 /* !i.base_reg && i.index_reg */
6303 if (i
.index_reg
->reg_num
== RegEiz
6304 || i
.index_reg
->reg_num
== RegRiz
)
6305 i
.sib
.index
= NO_INDEX_REGISTER
;
6307 i
.sib
.index
= i
.index_reg
->reg_num
;
6308 i
.sib
.base
= NO_BASE_REGISTER
;
6309 i
.sib
.scale
= i
.log2_scale_factor
;
6310 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6311 /* No Vec_Disp8 if there is no base. */
6312 i
.types
[op
].bitfield
.vec_disp8
= 0;
6313 i
.types
[op
].bitfield
.disp8
= 0;
6314 i
.types
[op
].bitfield
.disp16
= 0;
6315 i
.types
[op
].bitfield
.disp64
= 0;
6316 if (flag_code
!= CODE_64BIT
)
6318 /* Must be 32 bit */
6319 i
.types
[op
].bitfield
.disp32
= 1;
6320 i
.types
[op
].bitfield
.disp32s
= 0;
6324 i
.types
[op
].bitfield
.disp32
= 0;
6325 i
.types
[op
].bitfield
.disp32s
= 1;
6327 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6331 /* RIP addressing for 64bit mode. */
6332 else if (i
.base_reg
->reg_num
== RegRip
||
6333 i
.base_reg
->reg_num
== RegEip
)
6335 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6336 i
.rm
.regmem
= NO_BASE_REGISTER
;
6337 i
.types
[op
].bitfield
.disp8
= 0;
6338 i
.types
[op
].bitfield
.disp16
= 0;
6339 i
.types
[op
].bitfield
.disp32
= 0;
6340 i
.types
[op
].bitfield
.disp32s
= 1;
6341 i
.types
[op
].bitfield
.disp64
= 0;
6342 i
.types
[op
].bitfield
.vec_disp8
= 0;
6343 i
.flags
[op
] |= Operand_PCrel
;
6344 if (! i
.disp_operands
)
6345 fake_zero_displacement
= 1;
6347 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6349 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6350 switch (i
.base_reg
->reg_num
)
6353 if (i
.index_reg
== 0)
6355 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6356 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6360 if (i
.index_reg
== 0)
6363 if (operand_type_check (i
.types
[op
], disp
) == 0)
6365 /* fake (%bp) into 0(%bp) */
6366 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6367 i
.types
[op
].bitfield
.vec_disp8
= 1;
6369 i
.types
[op
].bitfield
.disp8
= 1;
6370 fake_zero_displacement
= 1;
6373 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6374 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6376 default: /* (%si) -> 4 or (%di) -> 5 */
6377 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6379 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6381 else /* i.base_reg and 32/64 bit mode */
6383 if (flag_code
== CODE_64BIT
6384 && operand_type_check (i
.types
[op
], disp
))
6386 i386_operand_type temp
;
6387 operand_type_set (&temp
, 0);
6388 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6389 temp
.bitfield
.vec_disp8
6390 = i
.types
[op
].bitfield
.vec_disp8
;
6392 if (i
.prefix
[ADDR_PREFIX
] == 0)
6393 i
.types
[op
].bitfield
.disp32s
= 1;
6395 i
.types
[op
].bitfield
.disp32
= 1;
6398 if (!i
.tm
.opcode_modifier
.vecsib
)
6399 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6400 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6402 i
.sib
.base
= i
.base_reg
->reg_num
;
6403 /* x86-64 ignores REX prefix bit here to avoid decoder
6405 if (!(i
.base_reg
->reg_flags
& RegRex
)
6406 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6407 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6409 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6411 fake_zero_displacement
= 1;
6412 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6413 i
.types
[op
].bitfield
.vec_disp8
= 1;
6415 i
.types
[op
].bitfield
.disp8
= 1;
6417 i
.sib
.scale
= i
.log2_scale_factor
;
6418 if (i
.index_reg
== 0)
6420 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6421 /* <disp>(%esp) becomes two byte modrm with no index
6422 register. We've already stored the code for esp
6423 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6424 Any base register besides %esp will not use the
6425 extra modrm byte. */
6426 i
.sib
.index
= NO_INDEX_REGISTER
;
6428 else if (!i
.tm
.opcode_modifier
.vecsib
)
6430 if (i
.index_reg
->reg_num
== RegEiz
6431 || i
.index_reg
->reg_num
== RegRiz
)
6432 i
.sib
.index
= NO_INDEX_REGISTER
;
6434 i
.sib
.index
= i
.index_reg
->reg_num
;
6435 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6436 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6441 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6442 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6446 if (!fake_zero_displacement
6450 fake_zero_displacement
= 1;
6451 if (i
.disp_encoding
== disp_encoding_8bit
)
6452 i
.types
[op
].bitfield
.disp8
= 1;
6454 i
.types
[op
].bitfield
.disp32
= 1;
6456 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6460 if (fake_zero_displacement
)
6462 /* Fakes a zero displacement assuming that i.types[op]
6463 holds the correct displacement size. */
6466 gas_assert (i
.op
[op
].disps
== 0);
6467 exp
= &disp_expressions
[i
.disp_operands
++];
6468 i
.op
[op
].disps
= exp
;
6469 exp
->X_op
= O_constant
;
6470 exp
->X_add_number
= 0;
6471 exp
->X_add_symbol
= (symbolS
*) 0;
6472 exp
->X_op_symbol
= (symbolS
*) 0;
6480 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6482 if (operand_type_check (i
.types
[0], imm
))
6483 i
.vex
.register_specifier
= NULL
;
6486 /* VEX.vvvv encodes one of the sources when the first
6487 operand is not an immediate. */
6488 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6489 i
.vex
.register_specifier
= i
.op
[0].regs
;
6491 i
.vex
.register_specifier
= i
.op
[1].regs
;
6494 /* Destination is a XMM register encoded in the ModRM.reg
6496 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6497 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6500 /* ModRM.rm and VEX.B encodes the other source. */
6501 if (!i
.mem_operands
)
6505 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6506 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6508 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6510 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6514 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6516 i
.vex
.register_specifier
= i
.op
[2].regs
;
6517 if (!i
.mem_operands
)
6520 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6521 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6525 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6526 (if any) based on i.tm.extension_opcode. Again, we must be
6527 careful to make sure that segment/control/debug/test/MMX
6528 registers are coded into the i.rm.reg field. */
6529 else if (i
.reg_operands
)
6532 unsigned int vex_reg
= ~0;
6534 for (op
= 0; op
< i
.operands
; op
++)
6535 if (i
.types
[op
].bitfield
.reg8
6536 || i
.types
[op
].bitfield
.reg16
6537 || i
.types
[op
].bitfield
.reg32
6538 || i
.types
[op
].bitfield
.reg64
6539 || i
.types
[op
].bitfield
.regmmx
6540 || i
.types
[op
].bitfield
.regxmm
6541 || i
.types
[op
].bitfield
.regymm
6542 || i
.types
[op
].bitfield
.regbnd
6543 || i
.types
[op
].bitfield
.regzmm
6544 || i
.types
[op
].bitfield
.regmask
6545 || i
.types
[op
].bitfield
.sreg2
6546 || i
.types
[op
].bitfield
.sreg3
6547 || i
.types
[op
].bitfield
.control
6548 || i
.types
[op
].bitfield
.debug
6549 || i
.types
[op
].bitfield
.test
)
6554 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6556 /* For instructions with VexNDS, the register-only
6557 source operand is encoded in VEX prefix. */
6558 gas_assert (mem
!= (unsigned int) ~0);
6563 gas_assert (op
< i
.operands
);
6567 /* Check register-only source operand when two source
6568 operands are swapped. */
6569 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6570 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6574 gas_assert (mem
== (vex_reg
+ 1)
6575 && op
< i
.operands
);
6580 gas_assert (vex_reg
< i
.operands
);
6584 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6586 /* For instructions with VexNDD, the register destination
6587 is encoded in VEX prefix. */
6588 if (i
.mem_operands
== 0)
6590 /* There is no memory operand. */
6591 gas_assert ((op
+ 2) == i
.operands
);
6596 /* There are only 2 operands. */
6597 gas_assert (op
< 2 && i
.operands
== 2);
6602 gas_assert (op
< i
.operands
);
6604 if (vex_reg
!= (unsigned int) ~0)
6606 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6608 if (type
->bitfield
.reg32
!= 1
6609 && type
->bitfield
.reg64
!= 1
6610 && !operand_type_equal (type
, ®xmm
)
6611 && !operand_type_equal (type
, ®ymm
)
6612 && !operand_type_equal (type
, ®zmm
)
6613 && !operand_type_equal (type
, ®mask
))
6616 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6619 /* Don't set OP operand twice. */
6622 /* If there is an extension opcode to put here, the
6623 register number must be put into the regmem field. */
6624 if (i
.tm
.extension_opcode
!= None
)
6626 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6627 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6629 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6634 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6635 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6637 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6642 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6643 must set it to 3 to indicate this is a register operand
6644 in the regmem field. */
6645 if (!i
.mem_operands
)
6649 /* Fill in i.rm.reg field with extension opcode (if any). */
6650 if (i
.tm
.extension_opcode
!= None
)
6651 i
.rm
.reg
= i
.tm
.extension_opcode
;
6657 output_branch (void)
6663 relax_substateT subtype
;
6667 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6668 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6671 if (i
.prefix
[DATA_PREFIX
] != 0)
6677 /* Pentium4 branch hints. */
6678 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6679 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6684 if (i
.prefix
[REX_PREFIX
] != 0)
6690 /* BND prefixed jump. */
6691 if (i
.prefix
[BND_PREFIX
] != 0)
6693 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6697 if (i
.prefixes
!= 0 && !intel_syntax
)
6698 as_warn (_("skipping prefixes on this instruction"));
6700 /* It's always a symbol; End frag & setup for relax.
6701 Make sure there is enough room in this frag for the largest
6702 instruction we may generate in md_convert_frag. This is 2
6703 bytes for the opcode and room for the prefix and largest
6705 frag_grow (prefix
+ 2 + 4);
6706 /* Prefix and 1 opcode byte go in fr_fix. */
6707 p
= frag_more (prefix
+ 1);
6708 if (i
.prefix
[DATA_PREFIX
] != 0)
6709 *p
++ = DATA_PREFIX_OPCODE
;
6710 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6711 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6712 *p
++ = i
.prefix
[SEG_PREFIX
];
6713 if (i
.prefix
[REX_PREFIX
] != 0)
6714 *p
++ = i
.prefix
[REX_PREFIX
];
6715 *p
= i
.tm
.base_opcode
;
6717 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6718 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6719 else if (cpu_arch_flags
.bitfield
.cpui386
)
6720 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6722 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6725 sym
= i
.op
[0].disps
->X_add_symbol
;
6726 off
= i
.op
[0].disps
->X_add_number
;
6728 if (i
.op
[0].disps
->X_op
!= O_constant
6729 && i
.op
[0].disps
->X_op
!= O_symbol
)
6731 /* Handle complex expressions. */
6732 sym
= make_expr_symbol (i
.op
[0].disps
);
6736 /* 1 possible extra opcode + 4 byte displacement go in var part.
6737 Pass reloc in fr_var. */
6738 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6748 if (i
.tm
.opcode_modifier
.jumpbyte
)
6750 /* This is a loop or jecxz type instruction. */
6752 if (i
.prefix
[ADDR_PREFIX
] != 0)
6754 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6757 /* Pentium4 branch hints. */
6758 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6759 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6761 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6770 if (flag_code
== CODE_16BIT
)
6773 if (i
.prefix
[DATA_PREFIX
] != 0)
6775 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6785 if (i
.prefix
[REX_PREFIX
] != 0)
6787 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6791 /* BND prefixed jump. */
6792 if (i
.prefix
[BND_PREFIX
] != 0)
6794 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6798 if (i
.prefixes
!= 0 && !intel_syntax
)
6799 as_warn (_("skipping prefixes on this instruction"));
6801 p
= frag_more (i
.tm
.opcode_length
+ size
);
6802 switch (i
.tm
.opcode_length
)
6805 *p
++ = i
.tm
.base_opcode
>> 8;
6807 *p
++ = i
.tm
.base_opcode
;
6813 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6814 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6816 /* All jumps handled here are signed, but don't use a signed limit
6817 check for 32 and 16 bit jumps as we want to allow wrap around at
6818 4G and 64k respectively. */
6820 fixP
->fx_signed
= 1;
6824 output_interseg_jump (void)
6832 if (flag_code
== CODE_16BIT
)
6836 if (i
.prefix
[DATA_PREFIX
] != 0)
6842 if (i
.prefix
[REX_PREFIX
] != 0)
6852 if (i
.prefixes
!= 0 && !intel_syntax
)
6853 as_warn (_("skipping prefixes on this instruction"));
6855 /* 1 opcode; 2 segment; offset */
6856 p
= frag_more (prefix
+ 1 + 2 + size
);
6858 if (i
.prefix
[DATA_PREFIX
] != 0)
6859 *p
++ = DATA_PREFIX_OPCODE
;
6861 if (i
.prefix
[REX_PREFIX
] != 0)
6862 *p
++ = i
.prefix
[REX_PREFIX
];
6864 *p
++ = i
.tm
.base_opcode
;
6865 if (i
.op
[1].imms
->X_op
== O_constant
)
6867 offsetT n
= i
.op
[1].imms
->X_add_number
;
6870 && !fits_in_unsigned_word (n
)
6871 && !fits_in_signed_word (n
))
6873 as_bad (_("16-bit jump out of range"));
6876 md_number_to_chars (p
, n
, size
);
6879 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6880 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6881 if (i
.op
[0].imms
->X_op
!= O_constant
)
6882 as_bad (_("can't handle non absolute segment in `%s'"),
6884 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6890 fragS
*insn_start_frag
;
6891 offsetT insn_start_off
;
6893 /* Tie dwarf2 debug info to the address at the start of the insn.
6894 We can't do this after the insn has been output as the current
6895 frag may have been closed off. eg. by frag_var. */
6896 dwarf2_emit_insn (0);
6898 insn_start_frag
= frag_now
;
6899 insn_start_off
= frag_now_fix ();
6902 if (i
.tm
.opcode_modifier
.jump
)
6904 else if (i
.tm
.opcode_modifier
.jumpbyte
6905 || i
.tm
.opcode_modifier
.jumpdword
)
6907 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6908 output_interseg_jump ();
6911 /* Output normal instructions here. */
6915 unsigned int prefix
;
6917 /* Some processors fail on LOCK prefix. This options makes
6918 assembler ignore LOCK prefix and serves as a workaround. */
6919 if (omit_lock_prefix
)
6921 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6923 i
.prefix
[LOCK_PREFIX
] = 0;
6926 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6927 don't need the explicit prefix. */
6928 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6930 switch (i
.tm
.opcode_length
)
6933 if (i
.tm
.base_opcode
& 0xff000000)
6935 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6940 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6942 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6943 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6946 if (prefix
!= REPE_PREFIX_OPCODE
6947 || (i
.prefix
[REP_PREFIX
]
6948 != REPE_PREFIX_OPCODE
))
6949 add_prefix (prefix
);
6952 add_prefix (prefix
);
6961 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6962 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6963 R_X86_64_GOTTPOFF relocation so that linker can safely
6964 perform IE->LE optimization. */
6965 if (x86_elf_abi
== X86_64_X32_ABI
6967 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
6968 && i
.prefix
[REX_PREFIX
] == 0)
6969 add_prefix (REX_OPCODE
);
6972 /* The prefix bytes. */
6973 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6975 FRAG_APPEND_1_CHAR (*q
);
6979 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6984 /* REX byte is encoded in VEX prefix. */
6988 FRAG_APPEND_1_CHAR (*q
);
6991 /* There should be no other prefixes for instructions
6996 /* For EVEX instructions i.vrex should become 0 after
6997 build_evex_prefix. For VEX instructions upper 16 registers
6998 aren't available, so VREX should be 0. */
7001 /* Now the VEX prefix. */
7002 p
= frag_more (i
.vex
.length
);
7003 for (j
= 0; j
< i
.vex
.length
; j
++)
7004 p
[j
] = i
.vex
.bytes
[j
];
7007 /* Now the opcode; be careful about word order here! */
7008 if (i
.tm
.opcode_length
== 1)
7010 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7014 switch (i
.tm
.opcode_length
)
7018 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7019 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7023 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7033 /* Put out high byte first: can't use md_number_to_chars! */
7034 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7035 *p
= i
.tm
.base_opcode
& 0xff;
7038 /* Now the modrm byte and sib byte (if present). */
7039 if (i
.tm
.opcode_modifier
.modrm
)
7041 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7044 /* If i.rm.regmem == ESP (4)
7045 && i.rm.mode != (Register mode)
7047 ==> need second modrm byte. */
7048 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7050 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7051 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7053 | i
.sib
.scale
<< 6));
7056 if (i
.disp_operands
)
7057 output_disp (insn_start_frag
, insn_start_off
);
7060 output_imm (insn_start_frag
, insn_start_off
);
7066 pi ("" /*line*/, &i
);
7068 #endif /* DEBUG386 */
7071 /* Return the size of the displacement operand N. */
7074 disp_size (unsigned int n
)
7078 /* Vec_Disp8 has to be 8bit. */
7079 if (i
.types
[n
].bitfield
.vec_disp8
)
7081 else if (i
.types
[n
].bitfield
.disp64
)
7083 else if (i
.types
[n
].bitfield
.disp8
)
7085 else if (i
.types
[n
].bitfield
.disp16
)
7090 /* Return the size of the immediate operand N. */
7093 imm_size (unsigned int n
)
7096 if (i
.types
[n
].bitfield
.imm64
)
7098 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7100 else if (i
.types
[n
].bitfield
.imm16
)
7106 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7111 for (n
= 0; n
< i
.operands
; n
++)
7113 if (i
.types
[n
].bitfield
.vec_disp8
7114 || operand_type_check (i
.types
[n
], disp
))
7116 if (i
.op
[n
].disps
->X_op
== O_constant
)
7118 int size
= disp_size (n
);
7119 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7121 if (i
.types
[n
].bitfield
.vec_disp8
)
7123 val
= offset_in_range (val
, size
);
7124 p
= frag_more (size
);
7125 md_number_to_chars (p
, val
, size
);
7129 enum bfd_reloc_code_real reloc_type
;
7130 int size
= disp_size (n
);
7131 int sign
= i
.types
[n
].bitfield
.disp32s
;
7132 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7134 /* We can't have 8 bit displacement here. */
7135 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7137 /* The PC relative address is computed relative
7138 to the instruction boundary, so in case immediate
7139 fields follows, we need to adjust the value. */
7140 if (pcrel
&& i
.imm_operands
)
7145 for (n1
= 0; n1
< i
.operands
; n1
++)
7146 if (operand_type_check (i
.types
[n1
], imm
))
7148 /* Only one immediate is allowed for PC
7149 relative address. */
7150 gas_assert (sz
== 0);
7152 i
.op
[n
].disps
->X_add_number
-= sz
;
7154 /* We should find the immediate. */
7155 gas_assert (sz
!= 0);
7158 p
= frag_more (size
);
7159 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7161 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7162 && (((reloc_type
== BFD_RELOC_32
7163 || reloc_type
== BFD_RELOC_X86_64_32S
7164 || (reloc_type
== BFD_RELOC_64
7166 && (i
.op
[n
].disps
->X_op
== O_symbol
7167 || (i
.op
[n
].disps
->X_op
== O_add
7168 && ((symbol_get_value_expression
7169 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7171 || reloc_type
== BFD_RELOC_32_PCREL
))
7175 if (insn_start_frag
== frag_now
)
7176 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7181 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7182 for (fr
= insn_start_frag
->fr_next
;
7183 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7185 add
+= p
- frag_now
->fr_literal
;
7190 reloc_type
= BFD_RELOC_386_GOTPC
;
7191 i
.op
[n
].imms
->X_add_number
+= add
;
7193 else if (reloc_type
== BFD_RELOC_64
)
7194 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7196 /* Don't do the adjustment for x86-64, as there
7197 the pcrel addressing is relative to the _next_
7198 insn, and that is taken care of in other code. */
7199 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7201 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7202 i
.op
[n
].disps
, pcrel
, reloc_type
);
7209 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7214 for (n
= 0; n
< i
.operands
; n
++)
7216 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7217 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7220 if (operand_type_check (i
.types
[n
], imm
))
7222 if (i
.op
[n
].imms
->X_op
== O_constant
)
7224 int size
= imm_size (n
);
7227 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7229 p
= frag_more (size
);
7230 md_number_to_chars (p
, val
, size
);
7234 /* Not absolute_section.
7235 Need a 32-bit fixup (don't support 8bit
7236 non-absolute imms). Try to support other
7238 enum bfd_reloc_code_real reloc_type
;
7239 int size
= imm_size (n
);
7242 if (i
.types
[n
].bitfield
.imm32s
7243 && (i
.suffix
== QWORD_MNEM_SUFFIX
7244 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7249 p
= frag_more (size
);
7250 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7252 /* This is tough to explain. We end up with this one if we
7253 * have operands that look like
7254 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7255 * obtain the absolute address of the GOT, and it is strongly
7256 * preferable from a performance point of view to avoid using
7257 * a runtime relocation for this. The actual sequence of
7258 * instructions often look something like:
7263 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7265 * The call and pop essentially return the absolute address
7266 * of the label .L66 and store it in %ebx. The linker itself
7267 * will ultimately change the first operand of the addl so
7268 * that %ebx points to the GOT, but to keep things simple, the
7269 * .o file must have this operand set so that it generates not
7270 * the absolute address of .L66, but the absolute address of
7271 * itself. This allows the linker itself simply treat a GOTPC
7272 * relocation as asking for a pcrel offset to the GOT to be
7273 * added in, and the addend of the relocation is stored in the
7274 * operand field for the instruction itself.
7276 * Our job here is to fix the operand so that it would add
7277 * the correct offset so that %ebx would point to itself. The
7278 * thing that is tricky is that .-.L66 will point to the
7279 * beginning of the instruction, so we need to further modify
7280 * the operand so that it will point to itself. There are
7281 * other cases where you have something like:
7283 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7285 * and here no correction would be required. Internally in
7286 * the assembler we treat operands of this form as not being
7287 * pcrel since the '.' is explicitly mentioned, and I wonder
7288 * whether it would simplify matters to do it this way. Who
7289 * knows. In earlier versions of the PIC patches, the
7290 * pcrel_adjust field was used to store the correction, but
7291 * since the expression is not pcrel, I felt it would be
7292 * confusing to do it this way. */
7294 if ((reloc_type
== BFD_RELOC_32
7295 || reloc_type
== BFD_RELOC_X86_64_32S
7296 || reloc_type
== BFD_RELOC_64
)
7298 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7299 && (i
.op
[n
].imms
->X_op
== O_symbol
7300 || (i
.op
[n
].imms
->X_op
== O_add
7301 && ((symbol_get_value_expression
7302 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7307 if (insn_start_frag
== frag_now
)
7308 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7313 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7314 for (fr
= insn_start_frag
->fr_next
;
7315 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7317 add
+= p
- frag_now
->fr_literal
;
7321 reloc_type
= BFD_RELOC_386_GOTPC
;
7323 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7325 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7326 i
.op
[n
].imms
->X_add_number
+= add
;
7328 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7329 i
.op
[n
].imms
, 0, reloc_type
);
7335 /* x86_cons_fix_new is called via the expression parsing code when a
7336 reloc is needed. We use this hook to get the correct .got reloc. */
7337 static int cons_sign
= -1;
7340 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7341 expressionS
*exp
, bfd_reloc_code_real_type r
)
7343 r
= reloc (len
, 0, cons_sign
, r
);
7346 if (exp
->X_op
== O_secrel
)
7348 exp
->X_op
= O_symbol
;
7349 r
= BFD_RELOC_32_SECREL
;
7353 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7356 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7357 purpose of the `.dc.a' internal pseudo-op. */
7360 x86_address_bytes (void)
7362 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7364 return stdoutput
->arch_info
->bits_per_address
/ 8;
7367 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7369 # define lex_got(reloc, adjust, types) NULL
7371 /* Parse operands of the form
7372 <symbol>@GOTOFF+<nnn>
7373 and similar .plt or .got references.
7375 If we find one, set up the correct relocation in RELOC and copy the
7376 input string, minus the `@GOTOFF' into a malloc'd buffer for
7377 parsing by the calling routine. Return this buffer, and if ADJUST
7378 is non-null set it to the length of the string we removed from the
7379 input line. Otherwise return NULL. */
7381 lex_got (enum bfd_reloc_code_real
*rel
,
7383 i386_operand_type
*types
)
7385 /* Some of the relocations depend on the size of what field is to
7386 be relocated. But in our callers i386_immediate and i386_displacement
7387 we don't yet know the operand size (this will be set by insn
7388 matching). Hence we record the word32 relocation here,
7389 and adjust the reloc according to the real size in reloc(). */
7390 static const struct {
7393 const enum bfd_reloc_code_real rel
[2];
7394 const i386_operand_type types64
;
7396 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7397 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7399 OPERAND_TYPE_IMM32_64
},
7401 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7402 BFD_RELOC_X86_64_PLTOFF64
},
7403 OPERAND_TYPE_IMM64
},
7404 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7405 BFD_RELOC_X86_64_PLT32
},
7406 OPERAND_TYPE_IMM32_32S_DISP32
},
7407 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7408 BFD_RELOC_X86_64_GOTPLT64
},
7409 OPERAND_TYPE_IMM64_DISP64
},
7410 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7411 BFD_RELOC_X86_64_GOTOFF64
},
7412 OPERAND_TYPE_IMM64_DISP64
},
7413 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7414 BFD_RELOC_X86_64_GOTPCREL
},
7415 OPERAND_TYPE_IMM32_32S_DISP32
},
7416 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7417 BFD_RELOC_X86_64_TLSGD
},
7418 OPERAND_TYPE_IMM32_32S_DISP32
},
7419 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7420 _dummy_first_bfd_reloc_code_real
},
7421 OPERAND_TYPE_NONE
},
7422 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7423 BFD_RELOC_X86_64_TLSLD
},
7424 OPERAND_TYPE_IMM32_32S_DISP32
},
7425 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7426 BFD_RELOC_X86_64_GOTTPOFF
},
7427 OPERAND_TYPE_IMM32_32S_DISP32
},
7428 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7429 BFD_RELOC_X86_64_TPOFF32
},
7430 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7431 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7432 _dummy_first_bfd_reloc_code_real
},
7433 OPERAND_TYPE_NONE
},
7434 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7435 BFD_RELOC_X86_64_DTPOFF32
},
7436 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7437 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7438 _dummy_first_bfd_reloc_code_real
},
7439 OPERAND_TYPE_NONE
},
7440 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7441 _dummy_first_bfd_reloc_code_real
},
7442 OPERAND_TYPE_NONE
},
7443 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7444 BFD_RELOC_X86_64_GOT32
},
7445 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7446 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7447 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7448 OPERAND_TYPE_IMM32_32S_DISP32
},
7449 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7450 BFD_RELOC_X86_64_TLSDESC_CALL
},
7451 OPERAND_TYPE_IMM32_32S_DISP32
},
7456 #if defined (OBJ_MAYBE_ELF)
7461 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7462 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7465 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7467 int len
= gotrel
[j
].len
;
7468 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7470 if (gotrel
[j
].rel
[object_64bit
] != 0)
7473 char *tmpbuf
, *past_reloc
;
7475 *rel
= gotrel
[j
].rel
[object_64bit
];
7479 if (flag_code
!= CODE_64BIT
)
7481 types
->bitfield
.imm32
= 1;
7482 types
->bitfield
.disp32
= 1;
7485 *types
= gotrel
[j
].types64
;
7488 if (j
!= 0 && GOT_symbol
== NULL
)
7489 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7491 /* The length of the first part of our input line. */
7492 first
= cp
- input_line_pointer
;
7494 /* The second part goes from after the reloc token until
7495 (and including) an end_of_line char or comma. */
7496 past_reloc
= cp
+ 1 + len
;
7498 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7500 second
= cp
+ 1 - past_reloc
;
7502 /* Allocate and copy string. The trailing NUL shouldn't
7503 be necessary, but be safe. */
7504 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7505 memcpy (tmpbuf
, input_line_pointer
, first
);
7506 if (second
!= 0 && *past_reloc
!= ' ')
7507 /* Replace the relocation token with ' ', so that
7508 errors like foo@GOTOFF1 will be detected. */
7509 tmpbuf
[first
++] = ' ';
7511 /* Increment length by 1 if the relocation token is
7516 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7517 tmpbuf
[first
+ second
] = '\0';
7521 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7522 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7527 /* Might be a symbol version string. Don't as_bad here. */
7536 /* Parse operands of the form
7537 <symbol>@SECREL32+<nnn>
7539 If we find one, set up the correct relocation in RELOC and copy the
7540 input string, minus the `@SECREL32' into a malloc'd buffer for
7541 parsing by the calling routine. Return this buffer, and if ADJUST
7542 is non-null set it to the length of the string we removed from the
7543 input line. Otherwise return NULL.
7545 This function is copied from the ELF version above adjusted for PE targets. */
7548 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7549 int *adjust ATTRIBUTE_UNUSED
,
7550 i386_operand_type
*types
)
7556 const enum bfd_reloc_code_real rel
[2];
7557 const i386_operand_type types64
;
7561 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7562 BFD_RELOC_32_SECREL
},
7563 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7569 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7570 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7573 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7575 int len
= gotrel
[j
].len
;
7577 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7579 if (gotrel
[j
].rel
[object_64bit
] != 0)
7582 char *tmpbuf
, *past_reloc
;
7584 *rel
= gotrel
[j
].rel
[object_64bit
];
7590 if (flag_code
!= CODE_64BIT
)
7592 types
->bitfield
.imm32
= 1;
7593 types
->bitfield
.disp32
= 1;
7596 *types
= gotrel
[j
].types64
;
7599 /* The length of the first part of our input line. */
7600 first
= cp
- input_line_pointer
;
7602 /* The second part goes from after the reloc token until
7603 (and including) an end_of_line char or comma. */
7604 past_reloc
= cp
+ 1 + len
;
7606 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7608 second
= cp
+ 1 - past_reloc
;
7610 /* Allocate and copy string. The trailing NUL shouldn't
7611 be necessary, but be safe. */
7612 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7613 memcpy (tmpbuf
, input_line_pointer
, first
);
7614 if (second
!= 0 && *past_reloc
!= ' ')
7615 /* Replace the relocation token with ' ', so that
7616 errors like foo@SECLREL321 will be detected. */
7617 tmpbuf
[first
++] = ' ';
7618 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7619 tmpbuf
[first
+ second
] = '\0';
7623 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7624 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7629 /* Might be a symbol version string. Don't as_bad here. */
7635 bfd_reloc_code_real_type
7636 x86_cons (expressionS
*exp
, int size
)
7638 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7640 intel_syntax
= -intel_syntax
;
7643 if (size
== 4 || (object_64bit
&& size
== 8))
7645 /* Handle @GOTOFF and the like in an expression. */
7647 char *gotfree_input_line
;
7650 save
= input_line_pointer
;
7651 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7652 if (gotfree_input_line
)
7653 input_line_pointer
= gotfree_input_line
;
7657 if (gotfree_input_line
)
7659 /* expression () has merrily parsed up to the end of line,
7660 or a comma - in the wrong buffer. Transfer how far
7661 input_line_pointer has moved to the right buffer. */
7662 input_line_pointer
= (save
7663 + (input_line_pointer
- gotfree_input_line
)
7665 free (gotfree_input_line
);
7666 if (exp
->X_op
== O_constant
7667 || exp
->X_op
== O_absent
7668 || exp
->X_op
== O_illegal
7669 || exp
->X_op
== O_register
7670 || exp
->X_op
== O_big
)
7672 char c
= *input_line_pointer
;
7673 *input_line_pointer
= 0;
7674 as_bad (_("missing or invalid expression `%s'"), save
);
7675 *input_line_pointer
= c
;
7682 intel_syntax
= -intel_syntax
;
7685 i386_intel_simplify (exp
);
7691 signed_cons (int size
)
7693 if (flag_code
== CODE_64BIT
)
7701 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7708 if (exp
.X_op
== O_symbol
)
7709 exp
.X_op
= O_secrel
;
7711 emit_expr (&exp
, 4);
7713 while (*input_line_pointer
++ == ',');
7715 input_line_pointer
--;
7716 demand_empty_rest_of_line ();
7720 /* Handle Vector operations. */
7723 check_VecOperations (char *op_string
, char *op_end
)
7725 const reg_entry
*mask
;
7730 && (op_end
== NULL
|| op_string
< op_end
))
7733 if (*op_string
== '{')
7737 /* Check broadcasts. */
7738 if (strncmp (op_string
, "1to", 3) == 0)
7743 goto duplicated_vec_op
;
7746 if (*op_string
== '8')
7747 bcst_type
= BROADCAST_1TO8
;
7748 else if (*op_string
== '4')
7749 bcst_type
= BROADCAST_1TO4
;
7750 else if (*op_string
== '2')
7751 bcst_type
= BROADCAST_1TO2
;
7752 else if (*op_string
== '1'
7753 && *(op_string
+1) == '6')
7755 bcst_type
= BROADCAST_1TO16
;
7760 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7765 broadcast_op
.type
= bcst_type
;
7766 broadcast_op
.operand
= this_operand
;
7767 i
.broadcast
= &broadcast_op
;
7769 /* Check masking operation. */
7770 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7772 /* k0 can't be used for write mask. */
7773 if (mask
->reg_num
== 0)
7775 as_bad (_("`%s' can't be used for write mask"),
7782 mask_op
.mask
= mask
;
7783 mask_op
.zeroing
= 0;
7784 mask_op
.operand
= this_operand
;
7790 goto duplicated_vec_op
;
7792 i
.mask
->mask
= mask
;
7794 /* Only "{z}" is allowed here. No need to check
7795 zeroing mask explicitly. */
7796 if (i
.mask
->operand
!= this_operand
)
7798 as_bad (_("invalid write mask `%s'"), saved
);
7805 /* Check zeroing-flag for masking operation. */
7806 else if (*op_string
== 'z')
7810 mask_op
.mask
= NULL
;
7811 mask_op
.zeroing
= 1;
7812 mask_op
.operand
= this_operand
;
7817 if (i
.mask
->zeroing
)
7820 as_bad (_("duplicated `%s'"), saved
);
7824 i
.mask
->zeroing
= 1;
7826 /* Only "{%k}" is allowed here. No need to check mask
7827 register explicitly. */
7828 if (i
.mask
->operand
!= this_operand
)
7830 as_bad (_("invalid zeroing-masking `%s'"),
7839 goto unknown_vec_op
;
7841 if (*op_string
!= '}')
7843 as_bad (_("missing `}' in `%s'"), saved
);
7850 /* We don't know this one. */
7851 as_bad (_("unknown vector operation: `%s'"), saved
);
7859 i386_immediate (char *imm_start
)
7861 char *save_input_line_pointer
;
7862 char *gotfree_input_line
;
7865 i386_operand_type types
;
7867 operand_type_set (&types
, ~0);
7869 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7871 as_bad (_("at most %d immediate operands are allowed"),
7872 MAX_IMMEDIATE_OPERANDS
);
7876 exp
= &im_expressions
[i
.imm_operands
++];
7877 i
.op
[this_operand
].imms
= exp
;
7879 if (is_space_char (*imm_start
))
7882 save_input_line_pointer
= input_line_pointer
;
7883 input_line_pointer
= imm_start
;
7885 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7886 if (gotfree_input_line
)
7887 input_line_pointer
= gotfree_input_line
;
7889 exp_seg
= expression (exp
);
7893 /* Handle vector operations. */
7894 if (*input_line_pointer
== '{')
7896 input_line_pointer
= check_VecOperations (input_line_pointer
,
7898 if (input_line_pointer
== NULL
)
7902 if (*input_line_pointer
)
7903 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7905 input_line_pointer
= save_input_line_pointer
;
7906 if (gotfree_input_line
)
7908 free (gotfree_input_line
);
7910 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7911 exp
->X_op
= O_illegal
;
7914 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7918 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7919 i386_operand_type types
, const char *imm_start
)
7921 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7924 as_bad (_("missing or invalid immediate expression `%s'"),
7928 else if (exp
->X_op
== O_constant
)
7930 /* Size it properly later. */
7931 i
.types
[this_operand
].bitfield
.imm64
= 1;
7932 /* If not 64bit, sign extend val. */
7933 if (flag_code
!= CODE_64BIT
7934 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7936 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7938 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7939 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7940 && exp_seg
!= absolute_section
7941 && exp_seg
!= text_section
7942 && exp_seg
!= data_section
7943 && exp_seg
!= bss_section
7944 && exp_seg
!= undefined_section
7945 && !bfd_is_com_section (exp_seg
))
7947 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7951 else if (!intel_syntax
&& exp_seg
== reg_section
)
7954 as_bad (_("illegal immediate register operand %s"), imm_start
);
7959 /* This is an address. The size of the address will be
7960 determined later, depending on destination register,
7961 suffix, or the default for the section. */
7962 i
.types
[this_operand
].bitfield
.imm8
= 1;
7963 i
.types
[this_operand
].bitfield
.imm16
= 1;
7964 i
.types
[this_operand
].bitfield
.imm32
= 1;
7965 i
.types
[this_operand
].bitfield
.imm32s
= 1;
7966 i
.types
[this_operand
].bitfield
.imm64
= 1;
7967 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7975 i386_scale (char *scale
)
7978 char *save
= input_line_pointer
;
7980 input_line_pointer
= scale
;
7981 val
= get_absolute_expression ();
7986 i
.log2_scale_factor
= 0;
7989 i
.log2_scale_factor
= 1;
7992 i
.log2_scale_factor
= 2;
7995 i
.log2_scale_factor
= 3;
7999 char sep
= *input_line_pointer
;
8001 *input_line_pointer
= '\0';
8002 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8004 *input_line_pointer
= sep
;
8005 input_line_pointer
= save
;
8009 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8011 as_warn (_("scale factor of %d without an index register"),
8012 1 << i
.log2_scale_factor
);
8013 i
.log2_scale_factor
= 0;
8015 scale
= input_line_pointer
;
8016 input_line_pointer
= save
;
8021 i386_displacement (char *disp_start
, char *disp_end
)
8025 char *save_input_line_pointer
;
8026 char *gotfree_input_line
;
8028 i386_operand_type bigdisp
, types
= anydisp
;
8031 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8033 as_bad (_("at most %d displacement operands are allowed"),
8034 MAX_MEMORY_OPERANDS
);
8038 operand_type_set (&bigdisp
, 0);
8039 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8040 || (!current_templates
->start
->opcode_modifier
.jump
8041 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8043 bigdisp
.bitfield
.disp32
= 1;
8044 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8045 if (flag_code
== CODE_64BIT
)
8049 bigdisp
.bitfield
.disp32s
= 1;
8050 bigdisp
.bitfield
.disp64
= 1;
8053 else if ((flag_code
== CODE_16BIT
) ^ override
)
8055 bigdisp
.bitfield
.disp32
= 0;
8056 bigdisp
.bitfield
.disp16
= 1;
8061 /* For PC-relative branches, the width of the displacement
8062 is dependent upon data size, not address size. */
8063 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8064 if (flag_code
== CODE_64BIT
)
8066 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8067 bigdisp
.bitfield
.disp16
= 1;
8070 bigdisp
.bitfield
.disp32
= 1;
8071 bigdisp
.bitfield
.disp32s
= 1;
8077 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8079 : LONG_MNEM_SUFFIX
));
8080 bigdisp
.bitfield
.disp32
= 1;
8081 if ((flag_code
== CODE_16BIT
) ^ override
)
8083 bigdisp
.bitfield
.disp32
= 0;
8084 bigdisp
.bitfield
.disp16
= 1;
8088 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8091 exp
= &disp_expressions
[i
.disp_operands
];
8092 i
.op
[this_operand
].disps
= exp
;
8094 save_input_line_pointer
= input_line_pointer
;
8095 input_line_pointer
= disp_start
;
8096 END_STRING_AND_SAVE (disp_end
);
8098 #ifndef GCC_ASM_O_HACK
8099 #define GCC_ASM_O_HACK 0
8102 END_STRING_AND_SAVE (disp_end
+ 1);
8103 if (i
.types
[this_operand
].bitfield
.baseIndex
8104 && displacement_string_end
[-1] == '+')
8106 /* This hack is to avoid a warning when using the "o"
8107 constraint within gcc asm statements.
8110 #define _set_tssldt_desc(n,addr,limit,type) \
8111 __asm__ __volatile__ ( \
8113 "movw %w1,2+%0\n\t" \
8115 "movb %b1,4+%0\n\t" \
8116 "movb %4,5+%0\n\t" \
8117 "movb $0,6+%0\n\t" \
8118 "movb %h1,7+%0\n\t" \
8120 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8122 This works great except that the output assembler ends
8123 up looking a bit weird if it turns out that there is
8124 no offset. You end up producing code that looks like:
8137 So here we provide the missing zero. */
8139 *displacement_string_end
= '0';
8142 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8143 if (gotfree_input_line
)
8144 input_line_pointer
= gotfree_input_line
;
8146 exp_seg
= expression (exp
);
8149 if (*input_line_pointer
)
8150 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8152 RESTORE_END_STRING (disp_end
+ 1);
8154 input_line_pointer
= save_input_line_pointer
;
8155 if (gotfree_input_line
)
8157 free (gotfree_input_line
);
8159 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8160 exp
->X_op
= O_illegal
;
8163 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8165 RESTORE_END_STRING (disp_end
);
8171 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8172 i386_operand_type types
, const char *disp_start
)
8174 i386_operand_type bigdisp
;
8177 /* We do this to make sure that the section symbol is in
8178 the symbol table. We will ultimately change the relocation
8179 to be relative to the beginning of the section. */
8180 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8181 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8182 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8184 if (exp
->X_op
!= O_symbol
)
8187 if (S_IS_LOCAL (exp
->X_add_symbol
)
8188 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8189 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8190 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8191 exp
->X_op
= O_subtract
;
8192 exp
->X_op_symbol
= GOT_symbol
;
8193 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8194 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8195 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8196 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8198 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8201 else if (exp
->X_op
== O_absent
8202 || exp
->X_op
== O_illegal
8203 || exp
->X_op
== O_big
)
8206 as_bad (_("missing or invalid displacement expression `%s'"),
8211 else if (flag_code
== CODE_64BIT
8212 && !i
.prefix
[ADDR_PREFIX
]
8213 && exp
->X_op
== O_constant
)
8215 /* Since displacement is signed extended to 64bit, don't allow
8216 disp32 and turn off disp32s if they are out of range. */
8217 i
.types
[this_operand
].bitfield
.disp32
= 0;
8218 if (!fits_in_signed_long (exp
->X_add_number
))
8220 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8221 if (i
.types
[this_operand
].bitfield
.baseindex
)
8223 as_bad (_("0x%lx out range of signed 32bit displacement"),
8224 (long) exp
->X_add_number
);
8230 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8231 else if (exp
->X_op
!= O_constant
8232 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8233 && exp_seg
!= absolute_section
8234 && exp_seg
!= text_section
8235 && exp_seg
!= data_section
8236 && exp_seg
!= bss_section
8237 && exp_seg
!= undefined_section
8238 && !bfd_is_com_section (exp_seg
))
8240 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8245 /* Check if this is a displacement only operand. */
8246 bigdisp
= i
.types
[this_operand
];
8247 bigdisp
.bitfield
.disp8
= 0;
8248 bigdisp
.bitfield
.disp16
= 0;
8249 bigdisp
.bitfield
.disp32
= 0;
8250 bigdisp
.bitfield
.disp32s
= 0;
8251 bigdisp
.bitfield
.disp64
= 0;
8252 if (operand_type_all_zero (&bigdisp
))
8253 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8259 /* Make sure the memory operand we've been dealt is valid.
8260 Return 1 on success, 0 on a failure. */
8263 i386_index_check (const char *operand_string
)
8265 const char *kind
= "base/index";
8266 enum flag_code addr_mode
;
8268 if (i
.prefix
[ADDR_PREFIX
])
8269 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8272 addr_mode
= flag_code
;
8274 #if INFER_ADDR_PREFIX
8275 if (i
.mem_operands
== 0)
8277 /* Infer address prefix from the first memory operand. */
8278 const reg_entry
*addr_reg
= i
.base_reg
;
8280 if (addr_reg
== NULL
)
8281 addr_reg
= i
.index_reg
;
8285 if (addr_reg
->reg_num
== RegEip
8286 || addr_reg
->reg_num
== RegEiz
8287 || addr_reg
->reg_type
.bitfield
.reg32
)
8288 addr_mode
= CODE_32BIT
;
8289 else if (flag_code
!= CODE_64BIT
8290 && addr_reg
->reg_type
.bitfield
.reg16
)
8291 addr_mode
= CODE_16BIT
;
8293 if (addr_mode
!= flag_code
)
8295 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8297 /* Change the size of any displacement too. At most one
8298 of Disp16 or Disp32 is set.
8299 FIXME. There doesn't seem to be any real need for
8300 separate Disp16 and Disp32 flags. The same goes for
8301 Imm16 and Imm32. Removing them would probably clean
8302 up the code quite a lot. */
8303 if (flag_code
!= CODE_64BIT
8304 && (i
.types
[this_operand
].bitfield
.disp16
8305 || i
.types
[this_operand
].bitfield
.disp32
))
8306 i
.types
[this_operand
]
8307 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8314 if (current_templates
->start
->opcode_modifier
.isstring
8315 && !current_templates
->start
->opcode_modifier
.immext
8316 && (current_templates
->end
[-1].opcode_modifier
.isstring
8319 /* Memory operands of string insns are special in that they only allow
8320 a single register (rDI, rSI, or rBX) as their memory address. */
8321 const reg_entry
*expected_reg
;
8322 static const char *di_si
[][2] =
8328 static const char *bx
[] = { "ebx", "bx", "rbx" };
8330 kind
= "string address";
8332 if (current_templates
->start
->opcode_modifier
.w
)
8334 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8336 if (!type
.bitfield
.baseindex
8337 || ((!i
.mem_operands
!= !intel_syntax
)
8338 && current_templates
->end
[-1].operand_types
[1]
8339 .bitfield
.baseindex
))
8340 type
= current_templates
->end
[-1].operand_types
[1];
8341 expected_reg
= hash_find (reg_hash
,
8342 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8346 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8348 if (i
.base_reg
!= expected_reg
8350 || operand_type_check (i
.types
[this_operand
], disp
))
8352 /* The second memory operand must have the same size as
8356 && !((addr_mode
== CODE_64BIT
8357 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8358 || (addr_mode
== CODE_32BIT
8359 ? i
.base_reg
->reg_type
.bitfield
.reg32
8360 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8363 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8365 intel_syntax
? '[' : '(',
8367 expected_reg
->reg_name
,
8368 intel_syntax
? ']' : ')');
8375 as_bad (_("`%s' is not a valid %s expression"),
8376 operand_string
, kind
);
8381 if (addr_mode
!= CODE_16BIT
)
8383 /* 32-bit/64-bit checks. */
8385 && (addr_mode
== CODE_64BIT
8386 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8387 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8389 || (i
.base_reg
->reg_num
8390 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8392 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8393 && !i
.index_reg
->reg_type
.bitfield
.regymm
8394 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8395 && ((addr_mode
== CODE_64BIT
8396 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8397 || i
.index_reg
->reg_num
== RegRiz
)
8398 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8399 || i
.index_reg
->reg_num
== RegEiz
))
8400 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8405 /* 16-bit checks. */
8407 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8408 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8410 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8411 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8413 && i
.base_reg
->reg_num
< 6
8414 && i
.index_reg
->reg_num
>= 6
8415 && i
.log2_scale_factor
== 0))))
8422 /* Handle vector immediates. */
8425 RC_SAE_immediate (const char *imm_start
)
8427 unsigned int match_found
, j
;
8428 const char *pstr
= imm_start
;
8436 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8438 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8442 rc_op
.type
= RC_NamesTable
[j
].type
;
8443 rc_op
.operand
= this_operand
;
8444 i
.rounding
= &rc_op
;
8448 as_bad (_("duplicated `%s'"), imm_start
);
8451 pstr
+= RC_NamesTable
[j
].len
;
8461 as_bad (_("Missing '}': '%s'"), imm_start
);
8464 /* RC/SAE immediate string should contain nothing more. */;
8467 as_bad (_("Junk after '}': '%s'"), imm_start
);
8471 exp
= &im_expressions
[i
.imm_operands
++];
8472 i
.op
[this_operand
].imms
= exp
;
8474 exp
->X_op
= O_constant
;
8475 exp
->X_add_number
= 0;
8476 exp
->X_add_symbol
= (symbolS
*) 0;
8477 exp
->X_op_symbol
= (symbolS
*) 0;
8479 i
.types
[this_operand
].bitfield
.imm8
= 1;
8483 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8487 i386_att_operand (char *operand_string
)
8491 char *op_string
= operand_string
;
8493 if (is_space_char (*op_string
))
8496 /* We check for an absolute prefix (differentiating,
8497 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8498 if (*op_string
== ABSOLUTE_PREFIX
)
8501 if (is_space_char (*op_string
))
8503 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8506 /* Check if operand is a register. */
8507 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8509 i386_operand_type temp
;
8511 /* Check for a segment override by searching for ':' after a
8512 segment register. */
8514 if (is_space_char (*op_string
))
8516 if (*op_string
== ':'
8517 && (r
->reg_type
.bitfield
.sreg2
8518 || r
->reg_type
.bitfield
.sreg3
))
8523 i
.seg
[i
.mem_operands
] = &es
;
8526 i
.seg
[i
.mem_operands
] = &cs
;
8529 i
.seg
[i
.mem_operands
] = &ss
;
8532 i
.seg
[i
.mem_operands
] = &ds
;
8535 i
.seg
[i
.mem_operands
] = &fs
;
8538 i
.seg
[i
.mem_operands
] = &gs
;
8542 /* Skip the ':' and whitespace. */
8544 if (is_space_char (*op_string
))
8547 if (!is_digit_char (*op_string
)
8548 && !is_identifier_char (*op_string
)
8549 && *op_string
!= '('
8550 && *op_string
!= ABSOLUTE_PREFIX
)
8552 as_bad (_("bad memory operand `%s'"), op_string
);
8555 /* Handle case of %es:*foo. */
8556 if (*op_string
== ABSOLUTE_PREFIX
)
8559 if (is_space_char (*op_string
))
8561 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8563 goto do_memory_reference
;
8566 /* Handle vector operations. */
8567 if (*op_string
== '{')
8569 op_string
= check_VecOperations (op_string
, NULL
);
8570 if (op_string
== NULL
)
8576 as_bad (_("junk `%s' after register"), op_string
);
8580 temp
.bitfield
.baseindex
= 0;
8581 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8583 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8584 i
.op
[this_operand
].regs
= r
;
8587 else if (*op_string
== REGISTER_PREFIX
)
8589 as_bad (_("bad register name `%s'"), op_string
);
8592 else if (*op_string
== IMMEDIATE_PREFIX
)
8595 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8597 as_bad (_("immediate operand illegal with absolute jump"));
8600 if (!i386_immediate (op_string
))
8603 else if (RC_SAE_immediate (operand_string
))
8605 /* If it is a RC or SAE immediate, do nothing. */
8608 else if (is_digit_char (*op_string
)
8609 || is_identifier_char (*op_string
)
8610 || *op_string
== '(')
8612 /* This is a memory reference of some sort. */
8615 /* Start and end of displacement string expression (if found). */
8616 char *displacement_string_start
;
8617 char *displacement_string_end
;
8620 do_memory_reference
:
8621 if ((i
.mem_operands
== 1
8622 && !current_templates
->start
->opcode_modifier
.isstring
)
8623 || i
.mem_operands
== 2)
8625 as_bad (_("too many memory references for `%s'"),
8626 current_templates
->start
->name
);
8630 /* Check for base index form. We detect the base index form by
8631 looking for an ')' at the end of the operand, searching
8632 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8634 base_string
= op_string
+ strlen (op_string
);
8636 /* Handle vector operations. */
8637 vop_start
= strchr (op_string
, '{');
8638 if (vop_start
&& vop_start
< base_string
)
8640 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8642 base_string
= vop_start
;
8646 if (is_space_char (*base_string
))
8649 /* If we only have a displacement, set-up for it to be parsed later. */
8650 displacement_string_start
= op_string
;
8651 displacement_string_end
= base_string
+ 1;
8653 if (*base_string
== ')')
8656 unsigned int parens_balanced
= 1;
8657 /* We've already checked that the number of left & right ()'s are
8658 equal, so this loop will not be infinite. */
8662 if (*base_string
== ')')
8664 if (*base_string
== '(')
8667 while (parens_balanced
);
8669 temp_string
= base_string
;
8671 /* Skip past '(' and whitespace. */
8673 if (is_space_char (*base_string
))
8676 if (*base_string
== ','
8677 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8680 displacement_string_end
= temp_string
;
8682 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8686 base_string
= end_op
;
8687 if (is_space_char (*base_string
))
8691 /* There may be an index reg or scale factor here. */
8692 if (*base_string
== ',')
8695 if (is_space_char (*base_string
))
8698 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8701 base_string
= end_op
;
8702 if (is_space_char (*base_string
))
8704 if (*base_string
== ',')
8707 if (is_space_char (*base_string
))
8710 else if (*base_string
!= ')')
8712 as_bad (_("expecting `,' or `)' "
8713 "after index register in `%s'"),
8718 else if (*base_string
== REGISTER_PREFIX
)
8720 end_op
= strchr (base_string
, ',');
8723 as_bad (_("bad register name `%s'"), base_string
);
8727 /* Check for scale factor. */
8728 if (*base_string
!= ')')
8730 char *end_scale
= i386_scale (base_string
);
8735 base_string
= end_scale
;
8736 if (is_space_char (*base_string
))
8738 if (*base_string
!= ')')
8740 as_bad (_("expecting `)' "
8741 "after scale factor in `%s'"),
8746 else if (!i
.index_reg
)
8748 as_bad (_("expecting index register or scale factor "
8749 "after `,'; got '%c'"),
8754 else if (*base_string
!= ')')
8756 as_bad (_("expecting `,' or `)' "
8757 "after base register in `%s'"),
8762 else if (*base_string
== REGISTER_PREFIX
)
8764 end_op
= strchr (base_string
, ',');
8767 as_bad (_("bad register name `%s'"), base_string
);
8772 /* If there's an expression beginning the operand, parse it,
8773 assuming displacement_string_start and
8774 displacement_string_end are meaningful. */
8775 if (displacement_string_start
!= displacement_string_end
)
8777 if (!i386_displacement (displacement_string_start
,
8778 displacement_string_end
))
8782 /* Special case for (%dx) while doing input/output op. */
8784 && operand_type_equal (&i
.base_reg
->reg_type
,
8785 ®16_inoutportreg
)
8787 && i
.log2_scale_factor
== 0
8788 && i
.seg
[i
.mem_operands
] == 0
8789 && !operand_type_check (i
.types
[this_operand
], disp
))
8791 i
.types
[this_operand
] = inoutportreg
;
8795 if (i386_index_check (operand_string
) == 0)
8797 i
.types
[this_operand
].bitfield
.mem
= 1;
8802 /* It's not a memory operand; argh! */
8803 as_bad (_("invalid char %s beginning operand %d `%s'"),
8804 output_invalid (*op_string
),
8809 return 1; /* Normal return. */
8812 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8813 that an rs_machine_dependent frag may reach. */
8816 i386_frag_max_var (fragS
*frag
)
8818 /* The only relaxable frags are for jumps.
8819 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8820 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8821 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8826 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8828 /* STT_GNU_IFUNC symbol must go through PLT. */
8829 if ((symbol_get_bfdsym (fr_symbol
)->flags
8830 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8833 if (!S_IS_EXTERNAL (fr_symbol
))
8834 /* Symbol may be weak or local. */
8835 return !S_IS_WEAK (fr_symbol
);
8837 /* Global symbols with non-default visibility can't be preempted. */
8838 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8841 if (fr_var
!= NO_RELOC
)
8842 switch ((enum bfd_reloc_code_real
) fr_var
)
8844 case BFD_RELOC_386_PLT32
:
8845 case BFD_RELOC_X86_64_PLT32
:
8846 /* Symbol with PLT relocatin may be preempted. */
8852 /* Global symbols with default visibility in a shared library may be
8853 preempted by another definition. */
8858 /* md_estimate_size_before_relax()
8860 Called just before relax() for rs_machine_dependent frags. The x86
8861 assembler uses these frags to handle variable size jump
8864 Any symbol that is now undefined will not become defined.
8865 Return the correct fr_subtype in the frag.
8866 Return the initial "guess for variable size of frag" to caller.
8867 The guess is actually the growth beyond the fixed part. Whatever
8868 we do to grow the fixed or variable part contributes to our
8872 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8874 /* We've already got fragP->fr_subtype right; all we have to do is
8875 check for un-relaxable symbols. On an ELF system, we can't relax
8876 an externally visible symbol, because it may be overridden by a
8878 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8879 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8881 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8884 #if defined (OBJ_COFF) && defined (TE_PE)
8885 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8886 && S_IS_WEAK (fragP
->fr_symbol
))
8890 /* Symbol is undefined in this segment, or we need to keep a
8891 reloc so that weak symbols can be overridden. */
8892 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8893 enum bfd_reloc_code_real reloc_type
;
8894 unsigned char *opcode
;
8897 if (fragP
->fr_var
!= NO_RELOC
)
8898 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8900 reloc_type
= BFD_RELOC_16_PCREL
;
8902 reloc_type
= BFD_RELOC_32_PCREL
;
8904 old_fr_fix
= fragP
->fr_fix
;
8905 opcode
= (unsigned char *) fragP
->fr_opcode
;
8907 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8910 /* Make jmp (0xeb) a (d)word displacement jump. */
8912 fragP
->fr_fix
+= size
;
8913 fix_new (fragP
, old_fr_fix
, size
,
8915 fragP
->fr_offset
, 1,
8921 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8923 /* Negate the condition, and branch past an
8924 unconditional jump. */
8927 /* Insert an unconditional jump. */
8929 /* We added two extra opcode bytes, and have a two byte
8931 fragP
->fr_fix
+= 2 + 2;
8932 fix_new (fragP
, old_fr_fix
+ 2, 2,
8934 fragP
->fr_offset
, 1,
8941 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8946 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8948 fragP
->fr_offset
, 1,
8950 fixP
->fx_signed
= 1;
8954 /* This changes the byte-displacement jump 0x7N
8955 to the (d)word-displacement jump 0x0f,0x8N. */
8956 opcode
[1] = opcode
[0] + 0x10;
8957 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8958 /* We've added an opcode byte. */
8959 fragP
->fr_fix
+= 1 + size
;
8960 fix_new (fragP
, old_fr_fix
+ 1, size
,
8962 fragP
->fr_offset
, 1,
8967 BAD_CASE (fragP
->fr_subtype
);
8971 return fragP
->fr_fix
- old_fr_fix
;
8974 /* Guess size depending on current relax state. Initially the relax
8975 state will correspond to a short jump and we return 1, because
8976 the variable part of the frag (the branch offset) is one byte
8977 long. However, we can relax a section more than once and in that
8978 case we must either set fr_subtype back to the unrelaxed state,
8979 or return the value for the appropriate branch. */
8980 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
8983 /* Called after relax() is finished.
8985 In: Address of frag.
8986 fr_type == rs_machine_dependent.
8987 fr_subtype is what the address relaxed to.
8989 Out: Any fixSs and constants are set up.
8990 Caller will turn frag into a ".space 0". */
8993 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
8996 unsigned char *opcode
;
8997 unsigned char *where_to_put_displacement
= NULL
;
8998 offsetT target_address
;
8999 offsetT opcode_address
;
9000 unsigned int extension
= 0;
9001 offsetT displacement_from_opcode_start
;
9003 opcode
= (unsigned char *) fragP
->fr_opcode
;
9005 /* Address we want to reach in file space. */
9006 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9008 /* Address opcode resides at in file space. */
9009 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9011 /* Displacement from opcode start to fill into instruction. */
9012 displacement_from_opcode_start
= target_address
- opcode_address
;
9014 if ((fragP
->fr_subtype
& BIG
) == 0)
9016 /* Don't have to change opcode. */
9017 extension
= 1; /* 1 opcode + 1 displacement */
9018 where_to_put_displacement
= &opcode
[1];
9022 if (no_cond_jump_promotion
9023 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9024 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9025 _("long jump required"));
9027 switch (fragP
->fr_subtype
)
9029 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9030 extension
= 4; /* 1 opcode + 4 displacement */
9032 where_to_put_displacement
= &opcode
[1];
9035 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9036 extension
= 2; /* 1 opcode + 2 displacement */
9038 where_to_put_displacement
= &opcode
[1];
9041 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9042 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9043 extension
= 5; /* 2 opcode + 4 displacement */
9044 opcode
[1] = opcode
[0] + 0x10;
9045 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9046 where_to_put_displacement
= &opcode
[2];
9049 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9050 extension
= 3; /* 2 opcode + 2 displacement */
9051 opcode
[1] = opcode
[0] + 0x10;
9052 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9053 where_to_put_displacement
= &opcode
[2];
9056 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9061 where_to_put_displacement
= &opcode
[3];
9065 BAD_CASE (fragP
->fr_subtype
);
9070 /* If size if less then four we are sure that the operand fits,
9071 but if it's 4, then it could be that the displacement is larger
9073 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9075 && ((addressT
) (displacement_from_opcode_start
- extension
9076 + ((addressT
) 1 << 31))
9077 > (((addressT
) 2 << 31) - 1)))
9079 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9080 _("jump target out of range"));
9081 /* Make us emit 0. */
9082 displacement_from_opcode_start
= extension
;
9084 /* Now put displacement after opcode. */
9085 md_number_to_chars ((char *) where_to_put_displacement
,
9086 (valueT
) (displacement_from_opcode_start
- extension
),
9087 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9088 fragP
->fr_fix
+= extension
;
9091 /* Apply a fixup (fixP) to segment data, once it has been determined
9092 by our caller that we have all the info we need to fix it up.
9094 Parameter valP is the pointer to the value of the bits.
9096 On the 386, immediates, displacements, and data pointers are all in
9097 the same (little-endian) format, so we don't need to care about which
9101 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9103 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9104 valueT value
= *valP
;
9106 #if !defined (TE_Mach)
9109 switch (fixP
->fx_r_type
)
9115 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9118 case BFD_RELOC_X86_64_32S
:
9119 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9122 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9125 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9130 if (fixP
->fx_addsy
!= NULL
9131 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9132 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9133 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9134 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9135 && !use_rela_relocations
)
9137 /* This is a hack. There should be a better way to handle this.
9138 This covers for the fact that bfd_install_relocation will
9139 subtract the current location (for partial_inplace, PC relative
9140 relocations); see more below. */
9144 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9147 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9152 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9155 || (symbol_section_p (fixP
->fx_addsy
)
9156 && sym_seg
!= absolute_section
))
9157 && !generic_force_reloc (fixP
))
9159 /* Yes, we add the values in twice. This is because
9160 bfd_install_relocation subtracts them out again. I think
9161 bfd_install_relocation is broken, but I don't dare change
9163 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9167 #if defined (OBJ_COFF) && defined (TE_PE)
9168 /* For some reason, the PE format does not store a
9169 section address offset for a PC relative symbol. */
9170 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9171 || S_IS_WEAK (fixP
->fx_addsy
))
9172 value
+= md_pcrel_from (fixP
);
9175 #if defined (OBJ_COFF) && defined (TE_PE)
9176 if (fixP
->fx_addsy
!= NULL
9177 && S_IS_WEAK (fixP
->fx_addsy
)
9178 /* PR 16858: Do not modify weak function references. */
9179 && ! fixP
->fx_pcrel
)
9181 #if !defined (TE_PEP)
9182 /* For x86 PE weak function symbols are neither PC-relative
9183 nor do they set S_IS_FUNCTION. So the only reliable way
9184 to detect them is to check the flags of their containing
9186 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9187 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9191 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9195 /* Fix a few things - the dynamic linker expects certain values here,
9196 and we must not disappoint it. */
9197 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9198 if (IS_ELF
&& fixP
->fx_addsy
)
9199 switch (fixP
->fx_r_type
)
9201 case BFD_RELOC_386_PLT32
:
9202 case BFD_RELOC_X86_64_PLT32
:
9203 /* Make the jump instruction point to the address of the operand. At
9204 runtime we merely add the offset to the actual PLT entry. */
9208 case BFD_RELOC_386_TLS_GD
:
9209 case BFD_RELOC_386_TLS_LDM
:
9210 case BFD_RELOC_386_TLS_IE_32
:
9211 case BFD_RELOC_386_TLS_IE
:
9212 case BFD_RELOC_386_TLS_GOTIE
:
9213 case BFD_RELOC_386_TLS_GOTDESC
:
9214 case BFD_RELOC_X86_64_TLSGD
:
9215 case BFD_RELOC_X86_64_TLSLD
:
9216 case BFD_RELOC_X86_64_GOTTPOFF
:
9217 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9218 value
= 0; /* Fully resolved at runtime. No addend. */
9220 case BFD_RELOC_386_TLS_LE
:
9221 case BFD_RELOC_386_TLS_LDO_32
:
9222 case BFD_RELOC_386_TLS_LE_32
:
9223 case BFD_RELOC_X86_64_DTPOFF32
:
9224 case BFD_RELOC_X86_64_DTPOFF64
:
9225 case BFD_RELOC_X86_64_TPOFF32
:
9226 case BFD_RELOC_X86_64_TPOFF64
:
9227 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9230 case BFD_RELOC_386_TLS_DESC_CALL
:
9231 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9232 value
= 0; /* Fully resolved at runtime. No addend. */
9233 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9237 case BFD_RELOC_386_GOT32
:
9238 case BFD_RELOC_X86_64_GOT32
:
9239 value
= 0; /* Fully resolved at runtime. No addend. */
9242 case BFD_RELOC_VTABLE_INHERIT
:
9243 case BFD_RELOC_VTABLE_ENTRY
:
9250 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9252 #endif /* !defined (TE_Mach) */
9254 /* Are we finished with this relocation now? */
9255 if (fixP
->fx_addsy
== NULL
)
9257 #if defined (OBJ_COFF) && defined (TE_PE)
9258 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9261 /* Remember value for tc_gen_reloc. */
9262 fixP
->fx_addnumber
= value
;
9263 /* Clear out the frag for now. */
9267 else if (use_rela_relocations
)
9269 fixP
->fx_no_overflow
= 1;
9270 /* Remember value for tc_gen_reloc. */
9271 fixP
->fx_addnumber
= value
;
9275 md_number_to_chars (p
, value
, fixP
->fx_size
);
9279 md_atof (int type
, char *litP
, int *sizeP
)
9281 /* This outputs the LITTLENUMs in REVERSE order;
9282 in accord with the bigendian 386. */
9283 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9286 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9289 output_invalid (int c
)
9292 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9295 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9296 "(0x%x)", (unsigned char) c
);
9297 return output_invalid_buf
;
9300 /* REG_STRING starts *before* REGISTER_PREFIX. */
9302 static const reg_entry
*
9303 parse_real_register (char *reg_string
, char **end_op
)
9305 char *s
= reg_string
;
9307 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9310 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9311 if (*s
== REGISTER_PREFIX
)
9314 if (is_space_char (*s
))
9318 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9320 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9321 return (const reg_entry
*) NULL
;
9325 /* For naked regs, make sure that we are not dealing with an identifier.
9326 This prevents confusing an identifier like `eax_var' with register
9328 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9329 return (const reg_entry
*) NULL
;
9333 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9335 /* Handle floating point regs, allowing spaces in the (i) part. */
9336 if (r
== i386_regtab
/* %st is first entry of table */)
9338 if (is_space_char (*s
))
9343 if (is_space_char (*s
))
9345 if (*s
>= '0' && *s
<= '7')
9349 if (is_space_char (*s
))
9354 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9359 /* We have "%st(" then garbage. */
9360 return (const reg_entry
*) NULL
;
9364 if (r
== NULL
|| allow_pseudo_reg
)
9367 if (operand_type_all_zero (&r
->reg_type
))
9368 return (const reg_entry
*) NULL
;
9370 if ((r
->reg_type
.bitfield
.reg32
9371 || r
->reg_type
.bitfield
.sreg3
9372 || r
->reg_type
.bitfield
.control
9373 || r
->reg_type
.bitfield
.debug
9374 || r
->reg_type
.bitfield
.test
)
9375 && !cpu_arch_flags
.bitfield
.cpui386
)
9376 return (const reg_entry
*) NULL
;
9378 if (r
->reg_type
.bitfield
.floatreg
9379 && !cpu_arch_flags
.bitfield
.cpu8087
9380 && !cpu_arch_flags
.bitfield
.cpu287
9381 && !cpu_arch_flags
.bitfield
.cpu387
)
9382 return (const reg_entry
*) NULL
;
9384 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9385 return (const reg_entry
*) NULL
;
9387 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9388 return (const reg_entry
*) NULL
;
9390 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9391 return (const reg_entry
*) NULL
;
9393 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9394 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9395 return (const reg_entry
*) NULL
;
9397 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9398 if (!allow_index_reg
9399 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9400 return (const reg_entry
*) NULL
;
9402 /* Upper 16 vector register is only available with VREX in 64bit
9404 if ((r
->reg_flags
& RegVRex
))
9406 if (!cpu_arch_flags
.bitfield
.cpuvrex
9407 || flag_code
!= CODE_64BIT
)
9408 return (const reg_entry
*) NULL
;
9413 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9414 || r
->reg_type
.bitfield
.reg64
)
9415 && (!cpu_arch_flags
.bitfield
.cpulm
9416 || !operand_type_equal (&r
->reg_type
, &control
))
9417 && flag_code
!= CODE_64BIT
)
9418 return (const reg_entry
*) NULL
;
9420 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9421 return (const reg_entry
*) NULL
;
9426 /* REG_STRING starts *before* REGISTER_PREFIX. */
9428 static const reg_entry
*
9429 parse_register (char *reg_string
, char **end_op
)
9433 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9434 r
= parse_real_register (reg_string
, end_op
);
9439 char *save
= input_line_pointer
;
9443 input_line_pointer
= reg_string
;
9444 c
= get_symbol_end ();
9445 symbolP
= symbol_find (reg_string
);
9446 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9448 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9450 know (e
->X_op
== O_register
);
9451 know (e
->X_add_number
>= 0
9452 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9453 r
= i386_regtab
+ e
->X_add_number
;
9454 if ((r
->reg_flags
& RegVRex
))
9456 *end_op
= input_line_pointer
;
9458 *input_line_pointer
= c
;
9459 input_line_pointer
= save
;
9465 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9468 char *end
= input_line_pointer
;
9471 r
= parse_register (name
, &input_line_pointer
);
9472 if (r
&& end
<= input_line_pointer
)
9474 *nextcharP
= *input_line_pointer
;
9475 *input_line_pointer
= 0;
9476 e
->X_op
= O_register
;
9477 e
->X_add_number
= r
- i386_regtab
;
9480 input_line_pointer
= end
;
9482 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9486 md_operand (expressionS
*e
)
9491 switch (*input_line_pointer
)
9493 case REGISTER_PREFIX
:
9494 r
= parse_real_register (input_line_pointer
, &end
);
9497 e
->X_op
= O_register
;
9498 e
->X_add_number
= r
- i386_regtab
;
9499 input_line_pointer
= end
;
9504 gas_assert (intel_syntax
);
9505 end
= input_line_pointer
++;
9507 if (*input_line_pointer
== ']')
9509 ++input_line_pointer
;
9510 e
->X_op_symbol
= make_expr_symbol (e
);
9511 e
->X_add_symbol
= NULL
;
9512 e
->X_add_number
= 0;
9518 input_line_pointer
= end
;
9525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9526 const char *md_shortopts
= "kVQ:sqn";
9528 const char *md_shortopts
= "qn";
9531 #define OPTION_32 (OPTION_MD_BASE + 0)
9532 #define OPTION_64 (OPTION_MD_BASE + 1)
9533 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9534 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9535 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9536 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9537 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9538 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9539 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9540 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9541 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9542 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9543 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9544 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9545 #define OPTION_X32 (OPTION_MD_BASE + 14)
9546 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9547 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9548 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9549 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9550 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9551 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9552 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9554 struct option md_longopts
[] =
9556 {"32", no_argument
, NULL
, OPTION_32
},
9557 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9558 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9559 {"64", no_argument
, NULL
, OPTION_64
},
9561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9562 {"x32", no_argument
, NULL
, OPTION_X32
},
9563 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9565 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9566 {"march", required_argument
, NULL
, OPTION_MARCH
},
9567 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9568 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9569 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9570 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9571 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9572 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9573 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9574 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9575 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9576 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9577 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9578 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9579 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9580 # if defined (TE_PE) || defined (TE_PEP)
9581 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9583 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9584 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9585 {NULL
, no_argument
, NULL
, 0}
9587 size_t md_longopts_size
= sizeof (md_longopts
);
9590 md_parse_option (int c
, char *arg
)
9598 optimize_align_code
= 0;
9605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9606 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9607 should be emitted or not. FIXME: Not implemented. */
9611 /* -V: SVR4 argument to print version ID. */
9613 print_version_id ();
9616 /* -k: Ignore for FreeBSD compatibility. */
9621 /* -s: On i386 Solaris, this tells the native assembler to use
9622 .stab instead of .stab.excl. We always use .stab anyhow. */
9625 case OPTION_MSHARED
:
9629 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9630 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9633 const char **list
, **l
;
9635 list
= bfd_target_list ();
9636 for (l
= list
; *l
!= NULL
; l
++)
9637 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9638 || strcmp (*l
, "coff-x86-64") == 0
9639 || strcmp (*l
, "pe-x86-64") == 0
9640 || strcmp (*l
, "pei-x86-64") == 0
9641 || strcmp (*l
, "mach-o-x86-64") == 0)
9643 default_arch
= "x86_64";
9647 as_fatal (_("no compiled in support for x86_64"));
9653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9657 const char **list
, **l
;
9659 list
= bfd_target_list ();
9660 for (l
= list
; *l
!= NULL
; l
++)
9661 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9663 default_arch
= "x86_64:32";
9667 as_fatal (_("no compiled in support for 32bit x86_64"));
9671 as_fatal (_("32bit x86_64 is only supported for ELF"));
9676 default_arch
= "i386";
9680 #ifdef SVR4_COMMENT_CHARS
9685 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9687 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9691 i386_comment_chars
= n
;
9697 arch
= xstrdup (arg
);
9701 as_fatal (_("invalid -march= option: `%s'"), arg
);
9702 next
= strchr (arch
, '+');
9705 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9707 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9710 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9713 cpu_arch_name
= cpu_arch
[j
].name
;
9714 cpu_sub_arch_name
= NULL
;
9715 cpu_arch_flags
= cpu_arch
[j
].flags
;
9716 cpu_arch_isa
= cpu_arch
[j
].type
;
9717 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9718 if (!cpu_arch_tune_set
)
9720 cpu_arch_tune
= cpu_arch_isa
;
9721 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9725 else if (*cpu_arch
[j
].name
== '.'
9726 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9728 /* ISA entension. */
9729 i386_cpu_flags flags
;
9731 if (!cpu_arch
[j
].negated
)
9732 flags
= cpu_flags_or (cpu_arch_flags
,
9735 flags
= cpu_flags_and_not (cpu_arch_flags
,
9738 if (!valid_iamcu_cpu_flags (&flags
))
9739 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9740 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9742 if (cpu_sub_arch_name
)
9744 char *name
= cpu_sub_arch_name
;
9745 cpu_sub_arch_name
= concat (name
,
9747 (const char *) NULL
);
9751 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9752 cpu_arch_flags
= flags
;
9753 cpu_arch_isa_flags
= flags
;
9759 if (j
>= ARRAY_SIZE (cpu_arch
))
9760 as_fatal (_("invalid -march= option: `%s'"), arg
);
9764 while (next
!= NULL
);
9769 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9770 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9772 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9774 cpu_arch_tune_set
= 1;
9775 cpu_arch_tune
= cpu_arch
[j
].type
;
9776 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9780 if (j
>= ARRAY_SIZE (cpu_arch
))
9781 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9784 case OPTION_MMNEMONIC
:
9785 if (strcasecmp (arg
, "att") == 0)
9787 else if (strcasecmp (arg
, "intel") == 0)
9790 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9793 case OPTION_MSYNTAX
:
9794 if (strcasecmp (arg
, "att") == 0)
9796 else if (strcasecmp (arg
, "intel") == 0)
9799 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9802 case OPTION_MINDEX_REG
:
9803 allow_index_reg
= 1;
9806 case OPTION_MNAKED_REG
:
9807 allow_naked_reg
= 1;
9810 case OPTION_MOLD_GCC
:
9814 case OPTION_MSSE2AVX
:
9818 case OPTION_MSSE_CHECK
:
9819 if (strcasecmp (arg
, "error") == 0)
9820 sse_check
= check_error
;
9821 else if (strcasecmp (arg
, "warning") == 0)
9822 sse_check
= check_warning
;
9823 else if (strcasecmp (arg
, "none") == 0)
9824 sse_check
= check_none
;
9826 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9829 case OPTION_MOPERAND_CHECK
:
9830 if (strcasecmp (arg
, "error") == 0)
9831 operand_check
= check_error
;
9832 else if (strcasecmp (arg
, "warning") == 0)
9833 operand_check
= check_warning
;
9834 else if (strcasecmp (arg
, "none") == 0)
9835 operand_check
= check_none
;
9837 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9840 case OPTION_MAVXSCALAR
:
9841 if (strcasecmp (arg
, "128") == 0)
9843 else if (strcasecmp (arg
, "256") == 0)
9846 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9849 case OPTION_MADD_BND_PREFIX
:
9853 case OPTION_MEVEXLIG
:
9854 if (strcmp (arg
, "128") == 0)
9856 else if (strcmp (arg
, "256") == 0)
9858 else if (strcmp (arg
, "512") == 0)
9861 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9864 case OPTION_MEVEXRCIG
:
9865 if (strcmp (arg
, "rne") == 0)
9867 else if (strcmp (arg
, "rd") == 0)
9869 else if (strcmp (arg
, "ru") == 0)
9871 else if (strcmp (arg
, "rz") == 0)
9874 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9877 case OPTION_MEVEXWIG
:
9878 if (strcmp (arg
, "0") == 0)
9880 else if (strcmp (arg
, "1") == 0)
9883 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9886 # if defined (TE_PE) || defined (TE_PEP)
9887 case OPTION_MBIG_OBJ
:
9892 case OPTION_OMIT_LOCK_PREFIX
:
9893 if (strcasecmp (arg
, "yes") == 0)
9894 omit_lock_prefix
= 1;
9895 else if (strcasecmp (arg
, "no") == 0)
9896 omit_lock_prefix
= 0;
9898 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9907 #define MESSAGE_TEMPLATE \
9911 show_arch (FILE *stream
, int ext
, int check
)
9913 static char message
[] = MESSAGE_TEMPLATE
;
9914 char *start
= message
+ 27;
9916 int size
= sizeof (MESSAGE_TEMPLATE
);
9923 left
= size
- (start
- message
);
9924 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9926 /* Should it be skipped? */
9927 if (cpu_arch
[j
].skip
)
9930 name
= cpu_arch
[j
].name
;
9931 len
= cpu_arch
[j
].len
;
9934 /* It is an extension. Skip if we aren't asked to show it. */
9945 /* It is an processor. Skip if we show only extension. */
9948 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9950 /* It is an impossible processor - skip. */
9954 /* Reserve 2 spaces for ", " or ",\0" */
9957 /* Check if there is any room. */
9965 p
= mempcpy (p
, name
, len
);
9969 /* Output the current message now and start a new one. */
9972 fprintf (stream
, "%s\n", message
);
9974 left
= size
- (start
- message
) - len
- 2;
9976 gas_assert (left
>= 0);
9978 p
= mempcpy (p
, name
, len
);
9983 fprintf (stream
, "%s\n", message
);
9987 md_show_usage (FILE *stream
)
9989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9990 fprintf (stream
, _("\
9992 -V print assembler version number\n\
9995 fprintf (stream
, _("\
9996 -n Do not optimize code alignment\n\
9997 -q quieten some warnings\n"));
9998 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9999 fprintf (stream
, _("\
10002 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10003 || defined (TE_PE) || defined (TE_PEP))
10004 fprintf (stream
, _("\
10005 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10007 #ifdef SVR4_COMMENT_CHARS
10008 fprintf (stream
, _("\
10009 --divide do not treat `/' as a comment character\n"));
10011 fprintf (stream
, _("\
10012 --divide ignored\n"));
10014 fprintf (stream
, _("\
10015 -march=CPU[,+EXTENSION...]\n\
10016 generate code for CPU and EXTENSION, CPU is one of:\n"));
10017 show_arch (stream
, 0, 1);
10018 fprintf (stream
, _("\
10019 EXTENSION is combination of:\n"));
10020 show_arch (stream
, 1, 0);
10021 fprintf (stream
, _("\
10022 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10023 show_arch (stream
, 0, 0);
10024 fprintf (stream
, _("\
10025 -msse2avx encode SSE instructions with VEX prefix\n"));
10026 fprintf (stream
, _("\
10027 -msse-check=[none|error|warning]\n\
10028 check SSE instructions\n"));
10029 fprintf (stream
, _("\
10030 -moperand-check=[none|error|warning]\n\
10031 check operand combinations for validity\n"));
10032 fprintf (stream
, _("\
10033 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10035 fprintf (stream
, _("\
10036 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10038 fprintf (stream
, _("\
10039 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10040 for EVEX.W bit ignored instructions\n"));
10041 fprintf (stream
, _("\
10042 -mevexrcig=[rne|rd|ru|rz]\n\
10043 encode EVEX instructions with specific EVEX.RC value\n\
10044 for SAE-only ignored instructions\n"));
10045 fprintf (stream
, _("\
10046 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10047 fprintf (stream
, _("\
10048 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10049 fprintf (stream
, _("\
10050 -mindex-reg support pseudo index registers\n"));
10051 fprintf (stream
, _("\
10052 -mnaked-reg don't require `%%' prefix for registers\n"));
10053 fprintf (stream
, _("\
10054 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10055 fprintf (stream
, _("\
10056 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10057 fprintf (stream
, _("\
10058 -mshared disable branch optimization for shared code\n"));
10059 # if defined (TE_PE) || defined (TE_PEP)
10060 fprintf (stream
, _("\
10061 -mbig-obj generate big object files\n"));
10063 fprintf (stream
, _("\
10064 -momit-lock-prefix=[no|yes]\n\
10065 strip all lock prefixes\n"));
10068 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10069 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10070 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10072 /* Pick the target format to use. */
10075 i386_target_format (void)
10077 if (!strncmp (default_arch
, "x86_64", 6))
10079 update_code_flag (CODE_64BIT
, 1);
10080 if (default_arch
[6] == '\0')
10081 x86_elf_abi
= X86_64_ABI
;
10083 x86_elf_abi
= X86_64_X32_ABI
;
10085 else if (!strcmp (default_arch
, "i386"))
10086 update_code_flag (CODE_32BIT
, 1);
10087 else if (!strcmp (default_arch
, "iamcu"))
10089 update_code_flag (CODE_32BIT
, 1);
10090 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10092 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10093 cpu_arch_name
= "iamcu";
10094 cpu_sub_arch_name
= NULL
;
10095 cpu_arch_flags
= iamcu_flags
;
10096 cpu_arch_isa
= PROCESSOR_IAMCU
;
10097 cpu_arch_isa_flags
= iamcu_flags
;
10098 if (!cpu_arch_tune_set
)
10100 cpu_arch_tune
= cpu_arch_isa
;
10101 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10105 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10109 as_fatal (_("unknown architecture"));
10111 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10112 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10113 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10114 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10116 switch (OUTPUT_FLAVOR
)
10118 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10119 case bfd_target_aout_flavour
:
10120 return AOUT_TARGET_FORMAT
;
10122 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10123 # if defined (TE_PE) || defined (TE_PEP)
10124 case bfd_target_coff_flavour
:
10125 if (flag_code
== CODE_64BIT
)
10126 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10129 # elif defined (TE_GO32)
10130 case bfd_target_coff_flavour
:
10131 return "coff-go32";
10133 case bfd_target_coff_flavour
:
10134 return "coff-i386";
10137 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10138 case bfd_target_elf_flavour
:
10140 const char *format
;
10142 switch (x86_elf_abi
)
10145 format
= ELF_TARGET_FORMAT
;
10148 use_rela_relocations
= 1;
10150 format
= ELF_TARGET_FORMAT64
;
10152 case X86_64_X32_ABI
:
10153 use_rela_relocations
= 1;
10155 disallow_64bit_reloc
= 1;
10156 format
= ELF_TARGET_FORMAT32
;
10159 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10161 if (x86_elf_abi
!= X86_64_ABI
)
10162 as_fatal (_("Intel L1OM is 64bit only"));
10163 return ELF_TARGET_L1OM_FORMAT
;
10165 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10167 if (x86_elf_abi
!= X86_64_ABI
)
10168 as_fatal (_("Intel K1OM is 64bit only"));
10169 return ELF_TARGET_K1OM_FORMAT
;
10171 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10173 if (x86_elf_abi
!= I386_ABI
)
10174 as_fatal (_("Intel MCU is 32bit only"));
10175 return ELF_TARGET_IAMCU_FORMAT
;
10181 #if defined (OBJ_MACH_O)
10182 case bfd_target_mach_o_flavour
:
10183 if (flag_code
== CODE_64BIT
)
10185 use_rela_relocations
= 1;
10187 return "mach-o-x86-64";
10190 return "mach-o-i386";
10198 #endif /* OBJ_MAYBE_ more than one */
10201 md_undefined_symbol (char *name
)
10203 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10204 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10205 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10206 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10210 if (symbol_find (name
))
10211 as_bad (_("GOT already in symbol table"));
10212 GOT_symbol
= symbol_new (name
, undefined_section
,
10213 (valueT
) 0, &zero_address_frag
);
10220 /* Round up a section size to the appropriate boundary. */
10223 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10225 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10226 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10228 /* For a.out, force the section size to be aligned. If we don't do
10229 this, BFD will align it for us, but it will not write out the
10230 final bytes of the section. This may be a bug in BFD, but it is
10231 easier to fix it here since that is how the other a.out targets
10235 align
= bfd_get_section_alignment (stdoutput
, segment
);
10236 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10243 /* On the i386, PC-relative offsets are relative to the start of the
10244 next instruction. That is, the address of the offset, plus its
10245 size, since the offset is always the last part of the insn. */
10248 md_pcrel_from (fixS
*fixP
)
10250 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10256 s_bss (int ignore ATTRIBUTE_UNUSED
)
10260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10262 obj_elf_section_change_hook ();
10264 temp
= get_absolute_expression ();
10265 subseg_set (bss_section
, (subsegT
) temp
);
10266 demand_empty_rest_of_line ();
10272 i386_validate_fix (fixS
*fixp
)
10274 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10276 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10280 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10285 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10287 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10289 fixp
->fx_subsy
= 0;
10294 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10297 bfd_reloc_code_real_type code
;
10299 switch (fixp
->fx_r_type
)
10301 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10302 case BFD_RELOC_SIZE32
:
10303 case BFD_RELOC_SIZE64
:
10304 if (S_IS_DEFINED (fixp
->fx_addsy
)
10305 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10307 /* Resolve size relocation against local symbol to size of
10308 the symbol plus addend. */
10309 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10310 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10311 && !fits_in_unsigned_long (value
))
10312 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10313 _("symbol size computation overflow"));
10314 fixp
->fx_addsy
= NULL
;
10315 fixp
->fx_subsy
= NULL
;
10316 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10321 case BFD_RELOC_X86_64_PLT32
:
10322 case BFD_RELOC_X86_64_GOT32
:
10323 case BFD_RELOC_X86_64_GOTPCREL
:
10324 case BFD_RELOC_386_PLT32
:
10325 case BFD_RELOC_386_GOT32
:
10326 case BFD_RELOC_386_GOTOFF
:
10327 case BFD_RELOC_386_GOTPC
:
10328 case BFD_RELOC_386_TLS_GD
:
10329 case BFD_RELOC_386_TLS_LDM
:
10330 case BFD_RELOC_386_TLS_LDO_32
:
10331 case BFD_RELOC_386_TLS_IE_32
:
10332 case BFD_RELOC_386_TLS_IE
:
10333 case BFD_RELOC_386_TLS_GOTIE
:
10334 case BFD_RELOC_386_TLS_LE_32
:
10335 case BFD_RELOC_386_TLS_LE
:
10336 case BFD_RELOC_386_TLS_GOTDESC
:
10337 case BFD_RELOC_386_TLS_DESC_CALL
:
10338 case BFD_RELOC_X86_64_TLSGD
:
10339 case BFD_RELOC_X86_64_TLSLD
:
10340 case BFD_RELOC_X86_64_DTPOFF32
:
10341 case BFD_RELOC_X86_64_DTPOFF64
:
10342 case BFD_RELOC_X86_64_GOTTPOFF
:
10343 case BFD_RELOC_X86_64_TPOFF32
:
10344 case BFD_RELOC_X86_64_TPOFF64
:
10345 case BFD_RELOC_X86_64_GOTOFF64
:
10346 case BFD_RELOC_X86_64_GOTPC32
:
10347 case BFD_RELOC_X86_64_GOT64
:
10348 case BFD_RELOC_X86_64_GOTPCREL64
:
10349 case BFD_RELOC_X86_64_GOTPC64
:
10350 case BFD_RELOC_X86_64_GOTPLT64
:
10351 case BFD_RELOC_X86_64_PLTOFF64
:
10352 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10353 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10354 case BFD_RELOC_RVA
:
10355 case BFD_RELOC_VTABLE_ENTRY
:
10356 case BFD_RELOC_VTABLE_INHERIT
:
10358 case BFD_RELOC_32_SECREL
:
10360 code
= fixp
->fx_r_type
;
10362 case BFD_RELOC_X86_64_32S
:
10363 if (!fixp
->fx_pcrel
)
10365 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10366 code
= fixp
->fx_r_type
;
10370 if (fixp
->fx_pcrel
)
10372 switch (fixp
->fx_size
)
10375 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10376 _("can not do %d byte pc-relative relocation"),
10378 code
= BFD_RELOC_32_PCREL
;
10380 case 1: code
= BFD_RELOC_8_PCREL
; break;
10381 case 2: code
= BFD_RELOC_16_PCREL
; break;
10382 case 4: code
= BFD_RELOC_32_PCREL
; break;
10384 case 8: code
= BFD_RELOC_64_PCREL
; break;
10390 switch (fixp
->fx_size
)
10393 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10394 _("can not do %d byte relocation"),
10396 code
= BFD_RELOC_32
;
10398 case 1: code
= BFD_RELOC_8
; break;
10399 case 2: code
= BFD_RELOC_16
; break;
10400 case 4: code
= BFD_RELOC_32
; break;
10402 case 8: code
= BFD_RELOC_64
; break;
10409 if ((code
== BFD_RELOC_32
10410 || code
== BFD_RELOC_32_PCREL
10411 || code
== BFD_RELOC_X86_64_32S
)
10413 && fixp
->fx_addsy
== GOT_symbol
)
10416 code
= BFD_RELOC_386_GOTPC
;
10418 code
= BFD_RELOC_X86_64_GOTPC32
;
10420 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10422 && fixp
->fx_addsy
== GOT_symbol
)
10424 code
= BFD_RELOC_X86_64_GOTPC64
;
10427 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10428 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10429 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10431 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10433 if (!use_rela_relocations
)
10435 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10436 vtable entry to be used in the relocation's section offset. */
10437 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10438 rel
->address
= fixp
->fx_offset
;
10439 #if defined (OBJ_COFF) && defined (TE_PE)
10440 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10441 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10446 /* Use the rela in 64bit mode. */
10449 if (disallow_64bit_reloc
)
10452 case BFD_RELOC_X86_64_DTPOFF64
:
10453 case BFD_RELOC_X86_64_TPOFF64
:
10454 case BFD_RELOC_64_PCREL
:
10455 case BFD_RELOC_X86_64_GOTOFF64
:
10456 case BFD_RELOC_X86_64_GOT64
:
10457 case BFD_RELOC_X86_64_GOTPCREL64
:
10458 case BFD_RELOC_X86_64_GOTPC64
:
10459 case BFD_RELOC_X86_64_GOTPLT64
:
10460 case BFD_RELOC_X86_64_PLTOFF64
:
10461 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10462 _("cannot represent relocation type %s in x32 mode"),
10463 bfd_get_reloc_code_name (code
));
10469 if (!fixp
->fx_pcrel
)
10470 rel
->addend
= fixp
->fx_offset
;
10474 case BFD_RELOC_X86_64_PLT32
:
10475 case BFD_RELOC_X86_64_GOT32
:
10476 case BFD_RELOC_X86_64_GOTPCREL
:
10477 case BFD_RELOC_X86_64_TLSGD
:
10478 case BFD_RELOC_X86_64_TLSLD
:
10479 case BFD_RELOC_X86_64_GOTTPOFF
:
10480 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10481 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10482 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10485 rel
->addend
= (section
->vma
10487 + fixp
->fx_addnumber
10488 + md_pcrel_from (fixp
));
10493 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10494 if (rel
->howto
== NULL
)
10496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10497 _("cannot represent relocation type %s"),
10498 bfd_get_reloc_code_name (code
));
10499 /* Set howto to a garbage value so that we can keep going. */
10500 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10501 gas_assert (rel
->howto
!= NULL
);
10507 #include "tc-i386-intel.c"
10510 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10512 int saved_naked_reg
;
10513 char saved_register_dot
;
10515 saved_naked_reg
= allow_naked_reg
;
10516 allow_naked_reg
= 1;
10517 saved_register_dot
= register_chars
['.'];
10518 register_chars
['.'] = '.';
10519 allow_pseudo_reg
= 1;
10520 expression_and_evaluate (exp
);
10521 allow_pseudo_reg
= 0;
10522 register_chars
['.'] = saved_register_dot
;
10523 allow_naked_reg
= saved_naked_reg
;
10525 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10527 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10529 exp
->X_op
= O_constant
;
10530 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10531 .dw2_regnum
[flag_code
>> 1];
10534 exp
->X_op
= O_illegal
;
10539 tc_x86_frame_initial_instructions (void)
10541 static unsigned int sp_regno
[2];
10543 if (!sp_regno
[flag_code
>> 1])
10545 char *saved_input
= input_line_pointer
;
10546 char sp
[][4] = {"esp", "rsp"};
10549 input_line_pointer
= sp
[flag_code
>> 1];
10550 tc_x86_parse_to_dw2regnum (&exp
);
10551 gas_assert (exp
.X_op
== O_constant
);
10552 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10553 input_line_pointer
= saved_input
;
10556 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10557 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10561 x86_dwarf2_addr_size (void)
10563 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10564 if (x86_elf_abi
== X86_64_X32_ABI
)
10567 return bfd_arch_bits_per_address (stdoutput
) / 8;
10571 i386_elf_section_type (const char *str
, size_t len
)
10573 if (flag_code
== CODE_64BIT
10574 && len
== sizeof ("unwind") - 1
10575 && strncmp (str
, "unwind", 6) == 0)
10576 return SHT_X86_64_UNWIND
;
10583 i386_solaris_fix_up_eh_frame (segT sec
)
10585 if (flag_code
== CODE_64BIT
)
10586 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10592 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10596 exp
.X_op
= O_secrel
;
10597 exp
.X_add_symbol
= symbol
;
10598 exp
.X_add_number
= 0;
10599 emit_expr (&exp
, size
);
10603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10604 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10607 x86_64_section_letter (int letter
, char **ptr_msg
)
10609 if (flag_code
== CODE_64BIT
)
10612 return SHF_X86_64_LARGE
;
10614 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10617 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10622 x86_64_section_word (char *str
, size_t len
)
10624 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10625 return SHF_X86_64_LARGE
;
10631 handle_large_common (int small ATTRIBUTE_UNUSED
)
10633 if (flag_code
!= CODE_64BIT
)
10635 s_comm_internal (0, elf_common_parse
);
10636 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10640 static segT lbss_section
;
10641 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10642 asection
*saved_bss_section
= bss_section
;
10644 if (lbss_section
== NULL
)
10646 flagword applicable
;
10647 segT seg
= now_seg
;
10648 subsegT subseg
= now_subseg
;
10650 /* The .lbss section is for local .largecomm symbols. */
10651 lbss_section
= subseg_new (".lbss", 0);
10652 applicable
= bfd_applicable_section_flags (stdoutput
);
10653 bfd_set_section_flags (stdoutput
, lbss_section
,
10654 applicable
& SEC_ALLOC
);
10655 seg_info (lbss_section
)->bss
= 1;
10657 subseg_set (seg
, subseg
);
10660 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10661 bss_section
= lbss_section
;
10663 s_comm_internal (0, elf_common_parse
);
10665 elf_com_section_ptr
= saved_com_section_ptr
;
10666 bss_section
= saved_bss_section
;
10669 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */