1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1094 static const noarch_entry cpu_noarch
[] =
1096 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1097 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1098 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1099 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1100 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1101 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1102 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1103 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1106 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1127 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1128 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1129 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1130 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1137 /* Like s_lcomm_internal in gas/read.c but the alignment string
1138 is allowed to be optional. */
1141 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1148 && *input_line_pointer
== ',')
1150 align
= parse_align (needs_align
- 1);
1152 if (align
== (addressT
) -1)
1167 bss_alloc (symbolP
, size
, align
);
1172 pe_lcomm (int needs_align
)
1174 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1178 const pseudo_typeS md_pseudo_table
[] =
1180 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1181 {"align", s_align_bytes
, 0},
1183 {"align", s_align_ptwo
, 0},
1185 {"arch", set_cpu_arch
, 0},
1189 {"lcomm", pe_lcomm
, 1},
1191 {"ffloat", float_cons
, 'f'},
1192 {"dfloat", float_cons
, 'd'},
1193 {"tfloat", float_cons
, 'x'},
1195 {"slong", signed_cons
, 4},
1196 {"noopt", s_ignore
, 0},
1197 {"optim", s_ignore
, 0},
1198 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1199 {"code16", set_code_flag
, CODE_16BIT
},
1200 {"code32", set_code_flag
, CODE_32BIT
},
1202 {"code64", set_code_flag
, CODE_64BIT
},
1204 {"intel_syntax", set_intel_syntax
, 1},
1205 {"att_syntax", set_intel_syntax
, 0},
1206 {"intel_mnemonic", set_intel_mnemonic
, 1},
1207 {"att_mnemonic", set_intel_mnemonic
, 0},
1208 {"allow_index_reg", set_allow_index_reg
, 1},
1209 {"disallow_index_reg", set_allow_index_reg
, 0},
1210 {"sse_check", set_check
, 0},
1211 {"operand_check", set_check
, 1},
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 {"largecomm", handle_large_common
, 0},
1215 {"file", dwarf2_directive_file
, 0},
1216 {"loc", dwarf2_directive_loc
, 0},
1217 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1220 {"secrel32", pe_directive_secrel
, 0},
1225 /* For interface with expression (). */
1226 extern char *input_line_pointer
;
1228 /* Hash table for instruction mnemonic lookup. */
1229 static struct hash_control
*op_hash
;
1231 /* Hash table for register lookup. */
1232 static struct hash_control
*reg_hash
;
1234 /* Various efficient no-op patterns for aligning code labels.
1235 Note: Don't try to assemble the instructions in the comments.
1236 0L and 0w are not legal. */
1237 static const unsigned char f32_1
[] =
1239 static const unsigned char f32_2
[] =
1240 {0x66,0x90}; /* xchg %ax,%ax */
1241 static const unsigned char f32_3
[] =
1242 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1243 static const unsigned char f32_4
[] =
1244 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1245 static const unsigned char f32_6
[] =
1246 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1247 static const unsigned char f32_7
[] =
1248 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1249 static const unsigned char f16_3
[] =
1250 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1251 static const unsigned char f16_4
[] =
1252 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1253 static const unsigned char jump_disp8
[] =
1254 {0xeb}; /* jmp disp8 */
1255 static const unsigned char jump32_disp32
[] =
1256 {0xe9}; /* jmp disp32 */
1257 static const unsigned char jump16_disp32
[] =
1258 {0x66,0xe9}; /* jmp disp32 */
1259 /* 32-bit NOPs patterns. */
1260 static const unsigned char *const f32_patt
[] = {
1261 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1263 /* 16-bit NOPs patterns. */
1264 static const unsigned char *const f16_patt
[] = {
1265 f32_1
, f32_2
, f16_3
, f16_4
1267 /* nopl (%[re]ax) */
1268 static const unsigned char alt_3
[] =
1270 /* nopl 0(%[re]ax) */
1271 static const unsigned char alt_4
[] =
1272 {0x0f,0x1f,0x40,0x00};
1273 /* nopl 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_5
[] =
1275 {0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopw 0(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_6
[] =
1278 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1279 /* nopl 0L(%[re]ax) */
1280 static const unsigned char alt_7
[] =
1281 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1282 /* nopl 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_8
[] =
1284 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw 0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_9
[] =
1287 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_10
[] =
1290 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* data16 nopw %cs:0L(%eax,%eax,1) */
1292 static const unsigned char alt_11
[] =
1293 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1294 /* 32-bit and 64-bit NOPs patterns. */
1295 static const unsigned char *const alt_patt
[] = {
1296 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1297 alt_9
, alt_10
, alt_11
1300 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1301 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1304 i386_output_nops (char *where
, const unsigned char *const *patt
,
1305 int count
, int max_single_nop_size
)
1308 /* Place the longer NOP first. */
1311 const unsigned char *nops
;
1313 if (max_single_nop_size
< 1)
1315 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1316 max_single_nop_size
);
1320 nops
= patt
[max_single_nop_size
- 1];
1322 /* Use the smaller one if the requsted one isn't available. */
1325 max_single_nop_size
--;
1326 nops
= patt
[max_single_nop_size
- 1];
1329 last
= count
% max_single_nop_size
;
1332 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1333 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1337 nops
= patt
[last
- 1];
1340 /* Use the smaller one plus one-byte NOP if the needed one
1343 nops
= patt
[last
- 1];
1344 memcpy (where
+ offset
, nops
, last
);
1345 where
[offset
+ last
] = *patt
[0];
1348 memcpy (where
+ offset
, nops
, last
);
1353 fits_in_imm7 (offsetT num
)
1355 return (num
& 0x7f) == num
;
1359 fits_in_imm31 (offsetT num
)
1361 return (num
& 0x7fffffff) == num
;
1364 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1365 single NOP instruction LIMIT. */
1368 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1370 const unsigned char *const *patt
= NULL
;
1371 int max_single_nop_size
;
1372 /* Maximum number of NOPs before switching to jump over NOPs. */
1373 int max_number_of_nops
;
1375 switch (fragP
->fr_type
)
1384 /* We need to decide which NOP sequence to use for 32bit and
1385 64bit. When -mtune= is used:
1387 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1388 PROCESSOR_GENERIC32, f32_patt will be used.
1389 2. For the rest, alt_patt will be used.
1391 When -mtune= isn't used, alt_patt will be used if
1392 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1395 When -march= or .arch is used, we can't use anything beyond
1396 cpu_arch_isa_flags. */
1398 if (flag_code
== CODE_16BIT
)
1401 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1402 /* Limit number of NOPs to 2 in 16-bit mode. */
1403 max_number_of_nops
= 2;
1407 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1409 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1410 switch (cpu_arch_tune
)
1412 case PROCESSOR_UNKNOWN
:
1413 /* We use cpu_arch_isa_flags to check if we SHOULD
1414 optimize with nops. */
1415 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1420 case PROCESSOR_PENTIUM4
:
1421 case PROCESSOR_NOCONA
:
1422 case PROCESSOR_CORE
:
1423 case PROCESSOR_CORE2
:
1424 case PROCESSOR_COREI7
:
1425 case PROCESSOR_L1OM
:
1426 case PROCESSOR_K1OM
:
1427 case PROCESSOR_GENERIC64
:
1429 case PROCESSOR_ATHLON
:
1431 case PROCESSOR_AMDFAM10
:
1433 case PROCESSOR_ZNVER
:
1437 case PROCESSOR_I386
:
1438 case PROCESSOR_I486
:
1439 case PROCESSOR_PENTIUM
:
1440 case PROCESSOR_PENTIUMPRO
:
1441 case PROCESSOR_IAMCU
:
1442 case PROCESSOR_GENERIC32
:
1449 switch (fragP
->tc_frag_data
.tune
)
1451 case PROCESSOR_UNKNOWN
:
1452 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1453 PROCESSOR_UNKNOWN. */
1457 case PROCESSOR_I386
:
1458 case PROCESSOR_I486
:
1459 case PROCESSOR_PENTIUM
:
1460 case PROCESSOR_IAMCU
:
1462 case PROCESSOR_ATHLON
:
1464 case PROCESSOR_AMDFAM10
:
1466 case PROCESSOR_ZNVER
:
1468 case PROCESSOR_GENERIC32
:
1469 /* We use cpu_arch_isa_flags to check if we CAN optimize
1471 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1476 case PROCESSOR_PENTIUMPRO
:
1477 case PROCESSOR_PENTIUM4
:
1478 case PROCESSOR_NOCONA
:
1479 case PROCESSOR_CORE
:
1480 case PROCESSOR_CORE2
:
1481 case PROCESSOR_COREI7
:
1482 case PROCESSOR_L1OM
:
1483 case PROCESSOR_K1OM
:
1484 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1489 case PROCESSOR_GENERIC64
:
1495 if (patt
== f32_patt
)
1497 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1498 /* Limit number of NOPs to 2 for older processors. */
1499 max_number_of_nops
= 2;
1503 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1504 /* Limit number of NOPs to 7 for newer processors. */
1505 max_number_of_nops
= 7;
1510 limit
= max_single_nop_size
;
1512 if (fragP
->fr_type
== rs_fill_nop
)
1514 /* Output NOPs for .nop directive. */
1515 if (limit
> max_single_nop_size
)
1517 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1518 _("invalid single nop size: %d "
1519 "(expect within [0, %d])"),
1520 limit
, max_single_nop_size
);
1525 fragP
->fr_var
= count
;
1527 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1529 /* Generate jump over NOPs. */
1530 offsetT disp
= count
- 2;
1531 if (fits_in_imm7 (disp
))
1533 /* Use "jmp disp8" if possible. */
1535 where
[0] = jump_disp8
[0];
1541 unsigned int size_of_jump
;
1543 if (flag_code
== CODE_16BIT
)
1545 where
[0] = jump16_disp32
[0];
1546 where
[1] = jump16_disp32
[1];
1551 where
[0] = jump32_disp32
[0];
1555 count
-= size_of_jump
+ 4;
1556 if (!fits_in_imm31 (count
))
1558 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1559 _("jump over nop padding out of range"));
1563 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1564 where
+= size_of_jump
+ 4;
1568 /* Generate multiple NOPs. */
1569 i386_output_nops (where
, patt
, count
, limit
);
1573 operand_type_all_zero (const union i386_operand_type
*x
)
1575 switch (ARRAY_SIZE(x
->array
))
1586 return !x
->array
[0];
1593 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1595 switch (ARRAY_SIZE(x
->array
))
1613 operand_type_equal (const union i386_operand_type
*x
,
1614 const union i386_operand_type
*y
)
1616 switch (ARRAY_SIZE(x
->array
))
1619 if (x
->array
[2] != y
->array
[2])
1623 if (x
->array
[1] != y
->array
[1])
1627 return x
->array
[0] == y
->array
[0];
1635 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1637 switch (ARRAY_SIZE(x
->array
))
1652 return !x
->array
[0];
1659 cpu_flags_equal (const union i386_cpu_flags
*x
,
1660 const union i386_cpu_flags
*y
)
1662 switch (ARRAY_SIZE(x
->array
))
1665 if (x
->array
[3] != y
->array
[3])
1669 if (x
->array
[2] != y
->array
[2])
1673 if (x
->array
[1] != y
->array
[1])
1677 return x
->array
[0] == y
->array
[0];
1685 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1687 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1688 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1691 static INLINE i386_cpu_flags
1692 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1694 switch (ARRAY_SIZE (x
.array
))
1697 x
.array
[3] &= y
.array
[3];
1700 x
.array
[2] &= y
.array
[2];
1703 x
.array
[1] &= y
.array
[1];
1706 x
.array
[0] &= y
.array
[0];
1714 static INLINE i386_cpu_flags
1715 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1717 switch (ARRAY_SIZE (x
.array
))
1720 x
.array
[3] |= y
.array
[3];
1723 x
.array
[2] |= y
.array
[2];
1726 x
.array
[1] |= y
.array
[1];
1729 x
.array
[0] |= y
.array
[0];
1737 static INLINE i386_cpu_flags
1738 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1740 switch (ARRAY_SIZE (x
.array
))
1743 x
.array
[3] &= ~y
.array
[3];
1746 x
.array
[2] &= ~y
.array
[2];
1749 x
.array
[1] &= ~y
.array
[1];
1752 x
.array
[0] &= ~y
.array
[0];
1760 #define CPU_FLAGS_ARCH_MATCH 0x1
1761 #define CPU_FLAGS_64BIT_MATCH 0x2
1763 #define CPU_FLAGS_PERFECT_MATCH \
1764 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1766 /* Return CPU flags match bits. */
1769 cpu_flags_match (const insn_template
*t
)
1771 i386_cpu_flags x
= t
->cpu_flags
;
1772 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1774 x
.bitfield
.cpu64
= 0;
1775 x
.bitfield
.cpuno64
= 0;
1777 if (cpu_flags_all_zero (&x
))
1779 /* This instruction is available on all archs. */
1780 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 /* This instruction is available only on some archs. */
1785 i386_cpu_flags cpu
= cpu_arch_flags
;
1787 /* AVX512VL is no standalone feature - match it and then strip it. */
1788 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1790 x
.bitfield
.cpuavx512vl
= 0;
1792 cpu
= cpu_flags_and (x
, cpu
);
1793 if (!cpu_flags_all_zero (&cpu
))
1795 if (x
.bitfield
.cpuavx
)
1797 /* We need to check a few extra flags with AVX. */
1798 if (cpu
.bitfield
.cpuavx
1799 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1800 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1801 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1802 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1803 match
|= CPU_FLAGS_ARCH_MATCH
;
1805 else if (x
.bitfield
.cpuavx512f
)
1807 /* We need to check a few extra flags with AVX512F. */
1808 if (cpu
.bitfield
.cpuavx512f
1809 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1810 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1811 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 match
|= CPU_FLAGS_ARCH_MATCH
;
1821 static INLINE i386_operand_type
1822 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1824 switch (ARRAY_SIZE (x
.array
))
1827 x
.array
[2] &= y
.array
[2];
1830 x
.array
[1] &= y
.array
[1];
1833 x
.array
[0] &= y
.array
[0];
1841 static INLINE i386_operand_type
1842 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1844 switch (ARRAY_SIZE (x
.array
))
1847 x
.array
[2] &= ~y
.array
[2];
1850 x
.array
[1] &= ~y
.array
[1];
1853 x
.array
[0] &= ~y
.array
[0];
1861 static INLINE i386_operand_type
1862 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[2] |= y
.array
[2];
1870 x
.array
[1] |= y
.array
[1];
1873 x
.array
[0] |= y
.array
[0];
1881 static INLINE i386_operand_type
1882 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1884 switch (ARRAY_SIZE (x
.array
))
1887 x
.array
[2] ^= y
.array
[2];
1890 x
.array
[1] ^= y
.array
[1];
1893 x
.array
[0] ^= y
.array
[0];
1901 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1902 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1903 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1904 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1905 static const i386_operand_type anydisp
1906 = OPERAND_TYPE_ANYDISP
;
1907 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1908 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1909 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1910 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1911 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1912 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1913 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1914 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1915 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1916 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1917 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1918 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1929 operand_type_check (i386_operand_type t
, enum operand_type c
)
1934 return t
.bitfield
.reg
;
1937 return (t
.bitfield
.imm8
1941 || t
.bitfield
.imm32s
1942 || t
.bitfield
.imm64
);
1945 return (t
.bitfield
.disp8
1946 || t
.bitfield
.disp16
1947 || t
.bitfield
.disp32
1948 || t
.bitfield
.disp32s
1949 || t
.bitfield
.disp64
);
1952 return (t
.bitfield
.disp8
1953 || t
.bitfield
.disp16
1954 || t
.bitfield
.disp32
1955 || t
.bitfield
.disp32s
1956 || t
.bitfield
.disp64
1957 || t
.bitfield
.baseindex
);
1966 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1967 between operand GIVEN and opeand WANTED for instruction template T. */
1970 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1973 return !((i
.types
[given
].bitfield
.byte
1974 && !t
->operand_types
[wanted
].bitfield
.byte
)
1975 || (i
.types
[given
].bitfield
.word
1976 && !t
->operand_types
[wanted
].bitfield
.word
)
1977 || (i
.types
[given
].bitfield
.dword
1978 && !t
->operand_types
[wanted
].bitfield
.dword
)
1979 || (i
.types
[given
].bitfield
.qword
1980 && !t
->operand_types
[wanted
].bitfield
.qword
)
1981 || (i
.types
[given
].bitfield
.tbyte
1982 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1985 /* Return 1 if there is no conflict in SIMD register between operand
1986 GIVEN and opeand WANTED for instruction template T. */
1989 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1992 return !((i
.types
[given
].bitfield
.xmmword
1993 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1994 || (i
.types
[given
].bitfield
.ymmword
1995 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1996 || (i
.types
[given
].bitfield
.zmmword
1997 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2000 /* Return 1 if there is no conflict in any size between operand GIVEN
2001 and opeand WANTED for instruction template T. */
2004 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2007 return (match_operand_size (t
, wanted
, given
)
2008 && !((i
.types
[given
].bitfield
.unspecified
2010 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2011 || (i
.types
[given
].bitfield
.fword
2012 && !t
->operand_types
[wanted
].bitfield
.fword
)
2013 /* For scalar opcode templates to allow register and memory
2014 operands at the same time, some special casing is needed
2015 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2016 down-conversion vpmov*. */
2017 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2018 && !t
->opcode_modifier
.broadcast
2019 && (t
->operand_types
[wanted
].bitfield
.byte
2020 || t
->operand_types
[wanted
].bitfield
.word
2021 || t
->operand_types
[wanted
].bitfield
.dword
2022 || t
->operand_types
[wanted
].bitfield
.qword
))
2023 ? (i
.types
[given
].bitfield
.xmmword
2024 || i
.types
[given
].bitfield
.ymmword
2025 || i
.types
[given
].bitfield
.zmmword
)
2026 : !match_simd_size(t
, wanted
, given
))));
2029 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2030 operands for instruction template T, and it has MATCH_REVERSE set if there
2031 is no size conflict on any operands for the template with operands reversed
2032 (and the template allows for reversing in the first place). */
2034 #define MATCH_STRAIGHT 1
2035 #define MATCH_REVERSE 2
2037 static INLINE
unsigned int
2038 operand_size_match (const insn_template
*t
)
2040 unsigned int j
, match
= MATCH_STRAIGHT
;
2042 /* Don't check jump instructions. */
2043 if (t
->opcode_modifier
.jump
2044 || t
->opcode_modifier
.jumpbyte
2045 || t
->opcode_modifier
.jumpdword
2046 || t
->opcode_modifier
.jumpintersegment
)
2049 /* Check memory and accumulator operand size. */
2050 for (j
= 0; j
< i
.operands
; j
++)
2052 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2053 && t
->operand_types
[j
].bitfield
.anysize
)
2056 if (t
->operand_types
[j
].bitfield
.reg
2057 && !match_operand_size (t
, j
, j
))
2063 if (t
->operand_types
[j
].bitfield
.regsimd
2064 && !match_simd_size (t
, j
, j
))
2070 if (t
->operand_types
[j
].bitfield
.acc
2071 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2077 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2084 if (!t
->opcode_modifier
.d
)
2088 i
.error
= operand_size_mismatch
;
2092 /* Check reverse. */
2093 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2095 for (j
= 0; j
< i
.operands
; j
++)
2097 unsigned int given
= i
.operands
- j
- 1;
2099 if (t
->operand_types
[j
].bitfield
.reg
2100 && !match_operand_size (t
, j
, given
))
2103 if (t
->operand_types
[j
].bitfield
.regsimd
2104 && !match_simd_size (t
, j
, given
))
2107 if (t
->operand_types
[j
].bitfield
.acc
2108 && (!match_operand_size (t
, j
, given
)
2109 || !match_simd_size (t
, j
, given
)))
2112 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2116 return match
| MATCH_REVERSE
;
2120 operand_type_match (i386_operand_type overlap
,
2121 i386_operand_type given
)
2123 i386_operand_type temp
= overlap
;
2125 temp
.bitfield
.jumpabsolute
= 0;
2126 temp
.bitfield
.unspecified
= 0;
2127 temp
.bitfield
.byte
= 0;
2128 temp
.bitfield
.word
= 0;
2129 temp
.bitfield
.dword
= 0;
2130 temp
.bitfield
.fword
= 0;
2131 temp
.bitfield
.qword
= 0;
2132 temp
.bitfield
.tbyte
= 0;
2133 temp
.bitfield
.xmmword
= 0;
2134 temp
.bitfield
.ymmword
= 0;
2135 temp
.bitfield
.zmmword
= 0;
2136 if (operand_type_all_zero (&temp
))
2139 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2140 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2144 i
.error
= operand_type_mismatch
;
2148 /* If given types g0 and g1 are registers they must be of the same type
2149 unless the expected operand type register overlap is null.
2150 Memory operand size of certain SIMD instructions is also being checked
2154 operand_type_register_match (i386_operand_type g0
,
2155 i386_operand_type t0
,
2156 i386_operand_type g1
,
2157 i386_operand_type t1
)
2159 if (!g0
.bitfield
.reg
2160 && !g0
.bitfield
.regsimd
2161 && (!operand_type_check (g0
, anymem
)
2162 || g0
.bitfield
.unspecified
2163 || !t0
.bitfield
.regsimd
))
2166 if (!g1
.bitfield
.reg
2167 && !g1
.bitfield
.regsimd
2168 && (!operand_type_check (g1
, anymem
)
2169 || g1
.bitfield
.unspecified
2170 || !t1
.bitfield
.regsimd
))
2173 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2174 && g0
.bitfield
.word
== g1
.bitfield
.word
2175 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2176 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2177 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2178 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2179 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2182 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2183 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2184 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2185 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2186 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2187 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2188 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2191 i
.error
= register_type_mismatch
;
2196 static INLINE
unsigned int
2197 register_number (const reg_entry
*r
)
2199 unsigned int nr
= r
->reg_num
;
2201 if (r
->reg_flags
& RegRex
)
2204 if (r
->reg_flags
& RegVRex
)
2210 static INLINE
unsigned int
2211 mode_from_disp_size (i386_operand_type t
)
2213 if (t
.bitfield
.disp8
)
2215 else if (t
.bitfield
.disp16
2216 || t
.bitfield
.disp32
2217 || t
.bitfield
.disp32s
)
2224 fits_in_signed_byte (addressT num
)
2226 return num
+ 0x80 <= 0xff;
2230 fits_in_unsigned_byte (addressT num
)
2236 fits_in_unsigned_word (addressT num
)
2238 return num
<= 0xffff;
2242 fits_in_signed_word (addressT num
)
2244 return num
+ 0x8000 <= 0xffff;
2248 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2253 return num
+ 0x80000000 <= 0xffffffff;
2255 } /* fits_in_signed_long() */
2258 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2263 return num
<= 0xffffffff;
2265 } /* fits_in_unsigned_long() */
2268 fits_in_disp8 (offsetT num
)
2270 int shift
= i
.memshift
;
2276 mask
= (1 << shift
) - 1;
2278 /* Return 0 if NUM isn't properly aligned. */
2282 /* Check if NUM will fit in 8bit after shift. */
2283 return fits_in_signed_byte (num
>> shift
);
2287 fits_in_imm4 (offsetT num
)
2289 return (num
& 0xf) == num
;
2292 static i386_operand_type
2293 smallest_imm_type (offsetT num
)
2295 i386_operand_type t
;
2297 operand_type_set (&t
, 0);
2298 t
.bitfield
.imm64
= 1;
2300 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2302 /* This code is disabled on the 486 because all the Imm1 forms
2303 in the opcode table are slower on the i486. They're the
2304 versions with the implicitly specified single-position
2305 displacement, which has another syntax if you really want to
2307 t
.bitfield
.imm1
= 1;
2308 t
.bitfield
.imm8
= 1;
2309 t
.bitfield
.imm8s
= 1;
2310 t
.bitfield
.imm16
= 1;
2311 t
.bitfield
.imm32
= 1;
2312 t
.bitfield
.imm32s
= 1;
2314 else if (fits_in_signed_byte (num
))
2316 t
.bitfield
.imm8
= 1;
2317 t
.bitfield
.imm8s
= 1;
2318 t
.bitfield
.imm16
= 1;
2319 t
.bitfield
.imm32
= 1;
2320 t
.bitfield
.imm32s
= 1;
2322 else if (fits_in_unsigned_byte (num
))
2324 t
.bitfield
.imm8
= 1;
2325 t
.bitfield
.imm16
= 1;
2326 t
.bitfield
.imm32
= 1;
2327 t
.bitfield
.imm32s
= 1;
2329 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2331 t
.bitfield
.imm16
= 1;
2332 t
.bitfield
.imm32
= 1;
2333 t
.bitfield
.imm32s
= 1;
2335 else if (fits_in_signed_long (num
))
2337 t
.bitfield
.imm32
= 1;
2338 t
.bitfield
.imm32s
= 1;
2340 else if (fits_in_unsigned_long (num
))
2341 t
.bitfield
.imm32
= 1;
2347 offset_in_range (offsetT val
, int size
)
2353 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2354 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2355 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2357 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2363 /* If BFD64, sign extend val for 32bit address mode. */
2364 if (flag_code
!= CODE_64BIT
2365 || i
.prefix
[ADDR_PREFIX
])
2366 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2367 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2370 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2372 char buf1
[40], buf2
[40];
2374 sprint_value (buf1
, val
);
2375 sprint_value (buf2
, val
& mask
);
2376 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2391 a. PREFIX_EXIST if attempting to add a prefix where one from the
2392 same class already exists.
2393 b. PREFIX_LOCK if lock prefix is added.
2394 c. PREFIX_REP if rep/repne prefix is added.
2395 d. PREFIX_DS if ds prefix is added.
2396 e. PREFIX_OTHER if other prefix is added.
2399 static enum PREFIX_GROUP
2400 add_prefix (unsigned int prefix
)
2402 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2405 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2406 && flag_code
== CODE_64BIT
)
2408 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2409 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2410 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2411 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2422 case DS_PREFIX_OPCODE
:
2425 case CS_PREFIX_OPCODE
:
2426 case ES_PREFIX_OPCODE
:
2427 case FS_PREFIX_OPCODE
:
2428 case GS_PREFIX_OPCODE
:
2429 case SS_PREFIX_OPCODE
:
2433 case REPNE_PREFIX_OPCODE
:
2434 case REPE_PREFIX_OPCODE
:
2439 case LOCK_PREFIX_OPCODE
:
2448 case ADDR_PREFIX_OPCODE
:
2452 case DATA_PREFIX_OPCODE
:
2456 if (i
.prefix
[q
] != 0)
2464 i
.prefix
[q
] |= prefix
;
2467 as_bad (_("same type of prefix used twice"));
2473 update_code_flag (int value
, int check
)
2475 PRINTF_LIKE ((*as_error
));
2477 flag_code
= (enum flag_code
) value
;
2478 if (flag_code
== CODE_64BIT
)
2480 cpu_arch_flags
.bitfield
.cpu64
= 1;
2481 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2485 cpu_arch_flags
.bitfield
.cpu64
= 0;
2486 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2488 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2491 as_error
= as_fatal
;
2494 (*as_error
) (_("64bit mode not supported on `%s'."),
2495 cpu_arch_name
? cpu_arch_name
: default_arch
);
2497 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2500 as_error
= as_fatal
;
2503 (*as_error
) (_("32bit mode not supported on `%s'."),
2504 cpu_arch_name
? cpu_arch_name
: default_arch
);
2506 stackop_size
= '\0';
2510 set_code_flag (int value
)
2512 update_code_flag (value
, 0);
2516 set_16bit_gcc_code_flag (int new_code_flag
)
2518 flag_code
= (enum flag_code
) new_code_flag
;
2519 if (flag_code
!= CODE_16BIT
)
2521 cpu_arch_flags
.bitfield
.cpu64
= 0;
2522 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2523 stackop_size
= LONG_MNEM_SUFFIX
;
2527 set_intel_syntax (int syntax_flag
)
2529 /* Find out if register prefixing is specified. */
2530 int ask_naked_reg
= 0;
2533 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2536 int e
= get_symbol_name (&string
);
2538 if (strcmp (string
, "prefix") == 0)
2540 else if (strcmp (string
, "noprefix") == 0)
2543 as_bad (_("bad argument to syntax directive."));
2544 (void) restore_line_pointer (e
);
2546 demand_empty_rest_of_line ();
2548 intel_syntax
= syntax_flag
;
2550 if (ask_naked_reg
== 0)
2551 allow_naked_reg
= (intel_syntax
2552 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2554 allow_naked_reg
= (ask_naked_reg
< 0);
2556 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2558 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2559 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2560 register_prefix
= allow_naked_reg
? "" : "%";
2564 set_intel_mnemonic (int mnemonic_flag
)
2566 intel_mnemonic
= mnemonic_flag
;
2570 set_allow_index_reg (int flag
)
2572 allow_index_reg
= flag
;
2576 set_check (int what
)
2578 enum check_kind
*kind
;
2583 kind
= &operand_check
;
2594 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2597 int e
= get_symbol_name (&string
);
2599 if (strcmp (string
, "none") == 0)
2601 else if (strcmp (string
, "warning") == 0)
2602 *kind
= check_warning
;
2603 else if (strcmp (string
, "error") == 0)
2604 *kind
= check_error
;
2606 as_bad (_("bad argument to %s_check directive."), str
);
2607 (void) restore_line_pointer (e
);
2610 as_bad (_("missing argument for %s_check directive"), str
);
2612 demand_empty_rest_of_line ();
2616 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2617 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2619 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2620 static const char *arch
;
2622 /* Intel LIOM is only supported on ELF. */
2628 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2629 use default_arch. */
2630 arch
= cpu_arch_name
;
2632 arch
= default_arch
;
2635 /* If we are targeting Intel MCU, we must enable it. */
2636 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2637 || new_flag
.bitfield
.cpuiamcu
)
2640 /* If we are targeting Intel L1OM, we must enable it. */
2641 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2642 || new_flag
.bitfield
.cpul1om
)
2645 /* If we are targeting Intel K1OM, we must enable it. */
2646 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2647 || new_flag
.bitfield
.cpuk1om
)
2650 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2655 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2659 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2662 int e
= get_symbol_name (&string
);
2664 i386_cpu_flags flags
;
2666 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2668 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2670 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2674 cpu_arch_name
= cpu_arch
[j
].name
;
2675 cpu_sub_arch_name
= NULL
;
2676 cpu_arch_flags
= cpu_arch
[j
].flags
;
2677 if (flag_code
== CODE_64BIT
)
2679 cpu_arch_flags
.bitfield
.cpu64
= 1;
2680 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2684 cpu_arch_flags
.bitfield
.cpu64
= 0;
2685 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2687 cpu_arch_isa
= cpu_arch
[j
].type
;
2688 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2689 if (!cpu_arch_tune_set
)
2691 cpu_arch_tune
= cpu_arch_isa
;
2692 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2697 flags
= cpu_flags_or (cpu_arch_flags
,
2700 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2702 if (cpu_sub_arch_name
)
2704 char *name
= cpu_sub_arch_name
;
2705 cpu_sub_arch_name
= concat (name
,
2707 (const char *) NULL
);
2711 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2712 cpu_arch_flags
= flags
;
2713 cpu_arch_isa_flags
= flags
;
2717 = cpu_flags_or (cpu_arch_isa_flags
,
2719 (void) restore_line_pointer (e
);
2720 demand_empty_rest_of_line ();
2725 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2727 /* Disable an ISA extension. */
2728 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2729 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2731 flags
= cpu_flags_and_not (cpu_arch_flags
,
2732 cpu_noarch
[j
].flags
);
2733 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2735 if (cpu_sub_arch_name
)
2737 char *name
= cpu_sub_arch_name
;
2738 cpu_sub_arch_name
= concat (name
, string
,
2739 (const char *) NULL
);
2743 cpu_sub_arch_name
= xstrdup (string
);
2744 cpu_arch_flags
= flags
;
2745 cpu_arch_isa_flags
= flags
;
2747 (void) restore_line_pointer (e
);
2748 demand_empty_rest_of_line ();
2752 j
= ARRAY_SIZE (cpu_arch
);
2755 if (j
>= ARRAY_SIZE (cpu_arch
))
2756 as_bad (_("no such architecture: `%s'"), string
);
2758 *input_line_pointer
= e
;
2761 as_bad (_("missing cpu architecture"));
2763 no_cond_jump_promotion
= 0;
2764 if (*input_line_pointer
== ','
2765 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2770 ++input_line_pointer
;
2771 e
= get_symbol_name (&string
);
2773 if (strcmp (string
, "nojumps") == 0)
2774 no_cond_jump_promotion
= 1;
2775 else if (strcmp (string
, "jumps") == 0)
2778 as_bad (_("no such architecture modifier: `%s'"), string
);
2780 (void) restore_line_pointer (e
);
2783 demand_empty_rest_of_line ();
2786 enum bfd_architecture
2789 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2791 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2792 || flag_code
!= CODE_64BIT
)
2793 as_fatal (_("Intel L1OM is 64bit ELF only"));
2794 return bfd_arch_l1om
;
2796 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2798 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2799 || flag_code
!= CODE_64BIT
)
2800 as_fatal (_("Intel K1OM is 64bit ELF only"));
2801 return bfd_arch_k1om
;
2803 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2805 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2806 || flag_code
== CODE_64BIT
)
2807 as_fatal (_("Intel MCU is 32bit ELF only"));
2808 return bfd_arch_iamcu
;
2811 return bfd_arch_i386
;
2817 if (!strncmp (default_arch
, "x86_64", 6))
2819 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2821 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2822 || default_arch
[6] != '\0')
2823 as_fatal (_("Intel L1OM is 64bit ELF only"));
2824 return bfd_mach_l1om
;
2826 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2828 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2829 || default_arch
[6] != '\0')
2830 as_fatal (_("Intel K1OM is 64bit ELF only"));
2831 return bfd_mach_k1om
;
2833 else if (default_arch
[6] == '\0')
2834 return bfd_mach_x86_64
;
2836 return bfd_mach_x64_32
;
2838 else if (!strcmp (default_arch
, "i386")
2839 || !strcmp (default_arch
, "iamcu"))
2841 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2843 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2844 as_fatal (_("Intel MCU is 32bit ELF only"));
2845 return bfd_mach_i386_iamcu
;
2848 return bfd_mach_i386_i386
;
2851 as_fatal (_("unknown architecture"));
2857 const char *hash_err
;
2859 /* Support pseudo prefixes like {disp32}. */
2860 lex_type
['{'] = LEX_BEGIN_NAME
;
2862 /* Initialize op_hash hash table. */
2863 op_hash
= hash_new ();
2866 const insn_template
*optab
;
2867 templates
*core_optab
;
2869 /* Setup for loop. */
2871 core_optab
= XNEW (templates
);
2872 core_optab
->start
= optab
;
2877 if (optab
->name
== NULL
2878 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2880 /* different name --> ship out current template list;
2881 add to hash table; & begin anew. */
2882 core_optab
->end
= optab
;
2883 hash_err
= hash_insert (op_hash
,
2885 (void *) core_optab
);
2888 as_fatal (_("can't hash %s: %s"),
2892 if (optab
->name
== NULL
)
2894 core_optab
= XNEW (templates
);
2895 core_optab
->start
= optab
;
2900 /* Initialize reg_hash hash table. */
2901 reg_hash
= hash_new ();
2903 const reg_entry
*regtab
;
2904 unsigned int regtab_size
= i386_regtab_size
;
2906 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2908 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2910 as_fatal (_("can't hash %s: %s"),
2916 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2921 for (c
= 0; c
< 256; c
++)
2926 mnemonic_chars
[c
] = c
;
2927 register_chars
[c
] = c
;
2928 operand_chars
[c
] = c
;
2930 else if (ISLOWER (c
))
2932 mnemonic_chars
[c
] = c
;
2933 register_chars
[c
] = c
;
2934 operand_chars
[c
] = c
;
2936 else if (ISUPPER (c
))
2938 mnemonic_chars
[c
] = TOLOWER (c
);
2939 register_chars
[c
] = mnemonic_chars
[c
];
2940 operand_chars
[c
] = c
;
2942 else if (c
== '{' || c
== '}')
2944 mnemonic_chars
[c
] = c
;
2945 operand_chars
[c
] = c
;
2948 if (ISALPHA (c
) || ISDIGIT (c
))
2949 identifier_chars
[c
] = c
;
2952 identifier_chars
[c
] = c
;
2953 operand_chars
[c
] = c
;
2958 identifier_chars
['@'] = '@';
2961 identifier_chars
['?'] = '?';
2962 operand_chars
['?'] = '?';
2964 digit_chars
['-'] = '-';
2965 mnemonic_chars
['_'] = '_';
2966 mnemonic_chars
['-'] = '-';
2967 mnemonic_chars
['.'] = '.';
2968 identifier_chars
['_'] = '_';
2969 identifier_chars
['.'] = '.';
2971 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2972 operand_chars
[(unsigned char) *p
] = *p
;
2975 if (flag_code
== CODE_64BIT
)
2977 #if defined (OBJ_COFF) && defined (TE_PE)
2978 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2981 x86_dwarf2_return_column
= 16;
2983 x86_cie_data_alignment
= -8;
2987 x86_dwarf2_return_column
= 8;
2988 x86_cie_data_alignment
= -4;
2993 i386_print_statistics (FILE *file
)
2995 hash_print_statistics (file
, "i386 opcode", op_hash
);
2996 hash_print_statistics (file
, "i386 register", reg_hash
);
3001 /* Debugging routines for md_assemble. */
3002 static void pte (insn_template
*);
3003 static void pt (i386_operand_type
);
3004 static void pe (expressionS
*);
3005 static void ps (symbolS
*);
3008 pi (const char *line
, i386_insn
*x
)
3012 fprintf (stdout
, "%s: template ", line
);
3014 fprintf (stdout
, " address: base %s index %s scale %x\n",
3015 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3016 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3017 x
->log2_scale_factor
);
3018 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3019 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3020 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3021 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3022 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3023 (x
->rex
& REX_W
) != 0,
3024 (x
->rex
& REX_R
) != 0,
3025 (x
->rex
& REX_X
) != 0,
3026 (x
->rex
& REX_B
) != 0);
3027 for (j
= 0; j
< x
->operands
; j
++)
3029 fprintf (stdout
, " #%d: ", j
+ 1);
3031 fprintf (stdout
, "\n");
3032 if (x
->types
[j
].bitfield
.reg
3033 || x
->types
[j
].bitfield
.regmmx
3034 || x
->types
[j
].bitfield
.regsimd
3035 || x
->types
[j
].bitfield
.sreg2
3036 || x
->types
[j
].bitfield
.sreg3
3037 || x
->types
[j
].bitfield
.control
3038 || x
->types
[j
].bitfield
.debug
3039 || x
->types
[j
].bitfield
.test
)
3040 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3041 if (operand_type_check (x
->types
[j
], imm
))
3043 if (operand_type_check (x
->types
[j
], disp
))
3044 pe (x
->op
[j
].disps
);
3049 pte (insn_template
*t
)
3052 fprintf (stdout
, " %d operands ", t
->operands
);
3053 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3054 if (t
->extension_opcode
!= None
)
3055 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3056 if (t
->opcode_modifier
.d
)
3057 fprintf (stdout
, "D");
3058 if (t
->opcode_modifier
.w
)
3059 fprintf (stdout
, "W");
3060 fprintf (stdout
, "\n");
3061 for (j
= 0; j
< t
->operands
; j
++)
3063 fprintf (stdout
, " #%d type ", j
+ 1);
3064 pt (t
->operand_types
[j
]);
3065 fprintf (stdout
, "\n");
3072 fprintf (stdout
, " operation %d\n", e
->X_op
);
3073 fprintf (stdout
, " add_number %ld (%lx)\n",
3074 (long) e
->X_add_number
, (long) e
->X_add_number
);
3075 if (e
->X_add_symbol
)
3077 fprintf (stdout
, " add_symbol ");
3078 ps (e
->X_add_symbol
);
3079 fprintf (stdout
, "\n");
3083 fprintf (stdout
, " op_symbol ");
3084 ps (e
->X_op_symbol
);
3085 fprintf (stdout
, "\n");
3092 fprintf (stdout
, "%s type %s%s",
3094 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3095 segment_name (S_GET_SEGMENT (s
)));
3098 static struct type_name
3100 i386_operand_type mask
;
3103 const type_names
[] =
3105 { OPERAND_TYPE_REG8
, "r8" },
3106 { OPERAND_TYPE_REG16
, "r16" },
3107 { OPERAND_TYPE_REG32
, "r32" },
3108 { OPERAND_TYPE_REG64
, "r64" },
3109 { OPERAND_TYPE_ACC8
, "acc8" },
3110 { OPERAND_TYPE_ACC16
, "acc16" },
3111 { OPERAND_TYPE_ACC32
, "acc32" },
3112 { OPERAND_TYPE_ACC64
, "acc64" },
3113 { OPERAND_TYPE_IMM8
, "i8" },
3114 { OPERAND_TYPE_IMM8
, "i8s" },
3115 { OPERAND_TYPE_IMM16
, "i16" },
3116 { OPERAND_TYPE_IMM32
, "i32" },
3117 { OPERAND_TYPE_IMM32S
, "i32s" },
3118 { OPERAND_TYPE_IMM64
, "i64" },
3119 { OPERAND_TYPE_IMM1
, "i1" },
3120 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3121 { OPERAND_TYPE_DISP8
, "d8" },
3122 { OPERAND_TYPE_DISP16
, "d16" },
3123 { OPERAND_TYPE_DISP32
, "d32" },
3124 { OPERAND_TYPE_DISP32S
, "d32s" },
3125 { OPERAND_TYPE_DISP64
, "d64" },
3126 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3127 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3128 { OPERAND_TYPE_CONTROL
, "control reg" },
3129 { OPERAND_TYPE_TEST
, "test reg" },
3130 { OPERAND_TYPE_DEBUG
, "debug reg" },
3131 { OPERAND_TYPE_FLOATREG
, "FReg" },
3132 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3133 { OPERAND_TYPE_SREG2
, "SReg2" },
3134 { OPERAND_TYPE_SREG3
, "SReg3" },
3135 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3136 { OPERAND_TYPE_REGMMX
, "rMMX" },
3137 { OPERAND_TYPE_REGXMM
, "rXMM" },
3138 { OPERAND_TYPE_REGYMM
, "rYMM" },
3139 { OPERAND_TYPE_REGZMM
, "rZMM" },
3140 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3141 { OPERAND_TYPE_ESSEG
, "es" },
3145 pt (i386_operand_type t
)
3148 i386_operand_type a
;
3150 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3152 a
= operand_type_and (t
, type_names
[j
].mask
);
3153 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3154 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3159 #endif /* DEBUG386 */
3161 static bfd_reloc_code_real_type
3162 reloc (unsigned int size
,
3165 bfd_reloc_code_real_type other
)
3167 if (other
!= NO_RELOC
)
3169 reloc_howto_type
*rel
;
3174 case BFD_RELOC_X86_64_GOT32
:
3175 return BFD_RELOC_X86_64_GOT64
;
3177 case BFD_RELOC_X86_64_GOTPLT64
:
3178 return BFD_RELOC_X86_64_GOTPLT64
;
3180 case BFD_RELOC_X86_64_PLTOFF64
:
3181 return BFD_RELOC_X86_64_PLTOFF64
;
3183 case BFD_RELOC_X86_64_GOTPC32
:
3184 other
= BFD_RELOC_X86_64_GOTPC64
;
3186 case BFD_RELOC_X86_64_GOTPCREL
:
3187 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3189 case BFD_RELOC_X86_64_TPOFF32
:
3190 other
= BFD_RELOC_X86_64_TPOFF64
;
3192 case BFD_RELOC_X86_64_DTPOFF32
:
3193 other
= BFD_RELOC_X86_64_DTPOFF64
;
3199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3200 if (other
== BFD_RELOC_SIZE32
)
3203 other
= BFD_RELOC_SIZE64
;
3206 as_bad (_("there are no pc-relative size relocations"));
3212 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3213 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3216 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3218 as_bad (_("unknown relocation (%u)"), other
);
3219 else if (size
!= bfd_get_reloc_size (rel
))
3220 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3221 bfd_get_reloc_size (rel
),
3223 else if (pcrel
&& !rel
->pc_relative
)
3224 as_bad (_("non-pc-relative relocation for pc-relative field"));
3225 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3227 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3229 as_bad (_("relocated field and relocation type differ in signedness"));
3238 as_bad (_("there are no unsigned pc-relative relocations"));
3241 case 1: return BFD_RELOC_8_PCREL
;
3242 case 2: return BFD_RELOC_16_PCREL
;
3243 case 4: return BFD_RELOC_32_PCREL
;
3244 case 8: return BFD_RELOC_64_PCREL
;
3246 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3253 case 4: return BFD_RELOC_X86_64_32S
;
3258 case 1: return BFD_RELOC_8
;
3259 case 2: return BFD_RELOC_16
;
3260 case 4: return BFD_RELOC_32
;
3261 case 8: return BFD_RELOC_64
;
3263 as_bad (_("cannot do %s %u byte relocation"),
3264 sign
> 0 ? "signed" : "unsigned", size
);
3270 /* Here we decide which fixups can be adjusted to make them relative to
3271 the beginning of the section instead of the symbol. Basically we need
3272 to make sure that the dynamic relocations are done correctly, so in
3273 some cases we force the original symbol to be used. */
3276 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3278 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3282 /* Don't adjust pc-relative references to merge sections in 64-bit
3284 if (use_rela_relocations
3285 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3289 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3290 and changed later by validate_fix. */
3291 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3292 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3295 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3296 for size relocations. */
3297 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3298 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3299 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3300 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3301 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3302 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3310 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3311 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3312 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3325 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3326 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3327 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3328 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3329 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3336 intel_float_operand (const char *mnemonic
)
3338 /* Note that the value returned is meaningful only for opcodes with (memory)
3339 operands, hence the code here is free to improperly handle opcodes that
3340 have no operands (for better performance and smaller code). */
3342 if (mnemonic
[0] != 'f')
3343 return 0; /* non-math */
3345 switch (mnemonic
[1])
3347 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3348 the fs segment override prefix not currently handled because no
3349 call path can make opcodes without operands get here */
3351 return 2 /* integer op */;
3353 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3354 return 3; /* fldcw/fldenv */
3357 if (mnemonic
[2] != 'o' /* fnop */)
3358 return 3; /* non-waiting control op */
3361 if (mnemonic
[2] == 's')
3362 return 3; /* frstor/frstpm */
3365 if (mnemonic
[2] == 'a')
3366 return 3; /* fsave */
3367 if (mnemonic
[2] == 't')
3369 switch (mnemonic
[3])
3371 case 'c': /* fstcw */
3372 case 'd': /* fstdw */
3373 case 'e': /* fstenv */
3374 case 's': /* fsts[gw] */
3380 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3381 return 0; /* fxsave/fxrstor are not really math ops */
3388 /* Build the VEX prefix. */
3391 build_vex_prefix (const insn_template
*t
)
3393 unsigned int register_specifier
;
3394 unsigned int implied_prefix
;
3395 unsigned int vector_length
;
3398 /* Check register specifier. */
3399 if (i
.vex
.register_specifier
)
3401 register_specifier
=
3402 ~register_number (i
.vex
.register_specifier
) & 0xf;
3403 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3406 register_specifier
= 0xf;
3408 /* Use 2-byte VEX prefix by swapping destination and source operand
3409 if there are more than 1 register operand. */
3410 if (i
.reg_operands
> 1
3411 && i
.vec_encoding
!= vex_encoding_vex3
3412 && i
.dir_encoding
== dir_encoding_default
3413 && i
.operands
== i
.reg_operands
3414 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3415 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3416 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3419 unsigned int xchg
= i
.operands
- 1;
3420 union i386_op temp_op
;
3421 i386_operand_type temp_type
;
3423 temp_type
= i
.types
[xchg
];
3424 i
.types
[xchg
] = i
.types
[0];
3425 i
.types
[0] = temp_type
;
3426 temp_op
= i
.op
[xchg
];
3427 i
.op
[xchg
] = i
.op
[0];
3430 gas_assert (i
.rm
.mode
== 3);
3434 i
.rm
.regmem
= i
.rm
.reg
;
3437 if (i
.tm
.opcode_modifier
.d
)
3438 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3439 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3440 else /* Use the next insn. */
3444 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3445 are no memory operands and at least 3 register ones. */
3446 if (i
.reg_operands
>= 3
3447 && i
.vec_encoding
!= vex_encoding_vex3
3448 && i
.reg_operands
== i
.operands
- i
.imm_operands
3449 && i
.tm
.opcode_modifier
.vex
3450 && i
.tm
.opcode_modifier
.commutative
3451 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3453 && i
.vex
.register_specifier
3454 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3456 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3457 union i386_op temp_op
;
3458 i386_operand_type temp_type
;
3460 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3461 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3462 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3463 &i
.types
[i
.operands
- 3]));
3464 gas_assert (i
.rm
.mode
== 3);
3466 temp_type
= i
.types
[xchg
];
3467 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3468 i
.types
[xchg
+ 1] = temp_type
;
3469 temp_op
= i
.op
[xchg
];
3470 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3471 i
.op
[xchg
+ 1] = temp_op
;
3474 xchg
= i
.rm
.regmem
| 8;
3475 i
.rm
.regmem
= ~register_specifier
& 0xf;
3476 gas_assert (!(i
.rm
.regmem
& 8));
3477 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3478 register_specifier
= ~xchg
& 0xf;
3481 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3482 vector_length
= avxscalar
;
3483 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3489 /* Determine vector length from the last multi-length vector
3492 for (op
= t
->operands
; op
--;)
3493 if (t
->operand_types
[op
].bitfield
.xmmword
3494 && t
->operand_types
[op
].bitfield
.ymmword
3495 && i
.types
[op
].bitfield
.ymmword
)
3502 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3507 case DATA_PREFIX_OPCODE
:
3510 case REPE_PREFIX_OPCODE
:
3513 case REPNE_PREFIX_OPCODE
:
3520 /* Check the REX.W bit and VEXW. */
3521 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3522 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3523 else if (i
.tm
.opcode_modifier
.vexw
)
3524 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3526 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3528 /* Use 2-byte VEX prefix if possible. */
3530 && i
.vec_encoding
!= vex_encoding_vex3
3531 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3532 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3534 /* 2-byte VEX prefix. */
3538 i
.vex
.bytes
[0] = 0xc5;
3540 /* Check the REX.R bit. */
3541 r
= (i
.rex
& REX_R
) ? 0 : 1;
3542 i
.vex
.bytes
[1] = (r
<< 7
3543 | register_specifier
<< 3
3544 | vector_length
<< 2
3549 /* 3-byte VEX prefix. */
3554 switch (i
.tm
.opcode_modifier
.vexopcode
)
3558 i
.vex
.bytes
[0] = 0xc4;
3562 i
.vex
.bytes
[0] = 0xc4;
3566 i
.vex
.bytes
[0] = 0xc4;
3570 i
.vex
.bytes
[0] = 0x8f;
3574 i
.vex
.bytes
[0] = 0x8f;
3578 i
.vex
.bytes
[0] = 0x8f;
3584 /* The high 3 bits of the second VEX byte are 1's compliment
3585 of RXB bits from REX. */
3586 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3588 i
.vex
.bytes
[2] = (w
<< 7
3589 | register_specifier
<< 3
3590 | vector_length
<< 2
3595 static INLINE bfd_boolean
3596 is_evex_encoding (const insn_template
*t
)
3598 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3599 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3600 || t
->opcode_modifier
.sae
;
3603 static INLINE bfd_boolean
3604 is_any_vex_encoding (const insn_template
*t
)
3606 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3607 || is_evex_encoding (t
);
3610 /* Build the EVEX prefix. */
3613 build_evex_prefix (void)
3615 unsigned int register_specifier
;
3616 unsigned int implied_prefix
;
3618 rex_byte vrex_used
= 0;
3620 /* Check register specifier. */
3621 if (i
.vex
.register_specifier
)
3623 gas_assert ((i
.vrex
& REX_X
) == 0);
3625 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3626 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3627 register_specifier
+= 8;
3628 /* The upper 16 registers are encoded in the fourth byte of the
3630 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3631 i
.vex
.bytes
[3] = 0x8;
3632 register_specifier
= ~register_specifier
& 0xf;
3636 register_specifier
= 0xf;
3638 /* Encode upper 16 vector index register in the fourth byte of
3640 if (!(i
.vrex
& REX_X
))
3641 i
.vex
.bytes
[3] = 0x8;
3646 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3651 case DATA_PREFIX_OPCODE
:
3654 case REPE_PREFIX_OPCODE
:
3657 case REPNE_PREFIX_OPCODE
:
3664 /* 4 byte EVEX prefix. */
3666 i
.vex
.bytes
[0] = 0x62;
3669 switch (i
.tm
.opcode_modifier
.vexopcode
)
3685 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3687 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3689 /* The fifth bit of the second EVEX byte is 1's compliment of the
3690 REX_R bit in VREX. */
3691 if (!(i
.vrex
& REX_R
))
3692 i
.vex
.bytes
[1] |= 0x10;
3696 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3698 /* When all operands are registers, the REX_X bit in REX is not
3699 used. We reuse it to encode the upper 16 registers, which is
3700 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3701 as 1's compliment. */
3702 if ((i
.vrex
& REX_B
))
3705 i
.vex
.bytes
[1] &= ~0x40;
3709 /* EVEX instructions shouldn't need the REX prefix. */
3710 i
.vrex
&= ~vrex_used
;
3711 gas_assert (i
.vrex
== 0);
3713 /* Check the REX.W bit and VEXW. */
3714 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3715 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3716 else if (i
.tm
.opcode_modifier
.vexw
)
3717 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3719 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3721 /* Encode the U bit. */
3722 implied_prefix
|= 0x4;
3724 /* The third byte of the EVEX prefix. */
3725 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3727 /* The fourth byte of the EVEX prefix. */
3728 /* The zeroing-masking bit. */
3729 if (i
.mask
&& i
.mask
->zeroing
)
3730 i
.vex
.bytes
[3] |= 0x80;
3732 /* Don't always set the broadcast bit if there is no RC. */
3735 /* Encode the vector length. */
3736 unsigned int vec_length
;
3738 if (!i
.tm
.opcode_modifier
.evex
3739 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3743 /* Determine vector length from the last multi-length vector
3746 for (op
= i
.operands
; op
--;)
3747 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3748 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3749 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3751 if (i
.types
[op
].bitfield
.zmmword
)
3753 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3756 else if (i
.types
[op
].bitfield
.ymmword
)
3758 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3761 else if (i
.types
[op
].bitfield
.xmmword
)
3763 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3766 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3768 switch (i
.broadcast
->bytes
)
3771 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3774 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3777 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3786 if (op
>= MAX_OPERANDS
)
3790 switch (i
.tm
.opcode_modifier
.evex
)
3792 case EVEXLIG
: /* LL' is ignored */
3793 vec_length
= evexlig
<< 5;
3796 vec_length
= 0 << 5;
3799 vec_length
= 1 << 5;
3802 vec_length
= 2 << 5;
3808 i
.vex
.bytes
[3] |= vec_length
;
3809 /* Encode the broadcast bit. */
3811 i
.vex
.bytes
[3] |= 0x10;
3815 if (i
.rounding
->type
!= saeonly
)
3816 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3818 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3821 if (i
.mask
&& i
.mask
->mask
)
3822 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3826 process_immext (void)
3830 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3833 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3834 with an opcode suffix which is coded in the same place as an
3835 8-bit immediate field would be.
3836 Here we check those operands and remove them afterwards. */
3839 for (x
= 0; x
< i
.operands
; x
++)
3840 if (register_number (i
.op
[x
].regs
) != x
)
3841 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3842 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3848 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3850 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3851 suffix which is coded in the same place as an 8-bit immediate
3853 Here we check those operands and remove them afterwards. */
3856 if (i
.operands
!= 3)
3859 for (x
= 0; x
< 2; x
++)
3860 if (register_number (i
.op
[x
].regs
) != x
)
3861 goto bad_register_operand
;
3863 /* Check for third operand for mwaitx/monitorx insn. */
3864 if (register_number (i
.op
[x
].regs
)
3865 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3867 bad_register_operand
:
3868 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3869 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3876 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3877 which is coded in the same place as an 8-bit immediate field
3878 would be. Here we fake an 8-bit immediate operand from the
3879 opcode suffix stored in tm.extension_opcode.
3881 AVX instructions also use this encoding, for some of
3882 3 argument instructions. */
3884 gas_assert (i
.imm_operands
<= 1
3886 || (is_any_vex_encoding (&i
.tm
)
3887 && i
.operands
<= 4)));
3889 exp
= &im_expressions
[i
.imm_operands
++];
3890 i
.op
[i
.operands
].imms
= exp
;
3891 i
.types
[i
.operands
] = imm8
;
3893 exp
->X_op
= O_constant
;
3894 exp
->X_add_number
= i
.tm
.extension_opcode
;
3895 i
.tm
.extension_opcode
= None
;
3902 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3907 as_bad (_("invalid instruction `%s' after `%s'"),
3908 i
.tm
.name
, i
.hle_prefix
);
3911 if (i
.prefix
[LOCK_PREFIX
])
3913 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3917 case HLEPrefixRelease
:
3918 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3920 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3924 if (i
.mem_operands
== 0
3925 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3927 as_bad (_("memory destination needed for instruction `%s'"
3928 " after `xrelease'"), i
.tm
.name
);
3935 /* Try the shortest encoding by shortening operand size. */
3938 optimize_encoding (void)
3942 if (optimize_for_space
3943 && i
.reg_operands
== 1
3944 && i
.imm_operands
== 1
3945 && !i
.types
[1].bitfield
.byte
3946 && i
.op
[0].imms
->X_op
== O_constant
3947 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3948 && ((i
.tm
.base_opcode
== 0xa8
3949 && i
.tm
.extension_opcode
== None
)
3950 || (i
.tm
.base_opcode
== 0xf6
3951 && i
.tm
.extension_opcode
== 0x0)))
3954 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3956 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3957 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3959 i
.types
[1].bitfield
.byte
= 1;
3960 /* Ignore the suffix. */
3962 if (base_regnum
>= 4
3963 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3965 /* Handle SP, BP, SI and DI registers. */
3966 if (i
.types
[1].bitfield
.word
)
3968 else if (i
.types
[1].bitfield
.dword
)
3976 else if (flag_code
== CODE_64BIT
3977 && ((i
.types
[1].bitfield
.qword
3978 && i
.reg_operands
== 1
3979 && i
.imm_operands
== 1
3980 && i
.op
[0].imms
->X_op
== O_constant
3981 && ((i
.tm
.base_opcode
== 0xb0
3982 && i
.tm
.extension_opcode
== None
3983 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3984 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3985 && (((i
.tm
.base_opcode
== 0x24
3986 || i
.tm
.base_opcode
== 0xa8)
3987 && i
.tm
.extension_opcode
== None
)
3988 || (i
.tm
.base_opcode
== 0x80
3989 && i
.tm
.extension_opcode
== 0x4)
3990 || ((i
.tm
.base_opcode
== 0xf6
3991 || i
.tm
.base_opcode
== 0xc6)
3992 && i
.tm
.extension_opcode
== 0x0)))
3993 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3994 && i
.tm
.base_opcode
== 0x83
3995 && i
.tm
.extension_opcode
== 0x4)))
3996 || (i
.types
[0].bitfield
.qword
3997 && ((i
.reg_operands
== 2
3998 && i
.op
[0].regs
== i
.op
[1].regs
3999 && ((i
.tm
.base_opcode
== 0x30
4000 || i
.tm
.base_opcode
== 0x28)
4001 && i
.tm
.extension_opcode
== None
))
4002 || (i
.reg_operands
== 1
4004 && i
.tm
.base_opcode
== 0x30
4005 && i
.tm
.extension_opcode
== None
)))))
4008 andq $imm31, %r64 -> andl $imm31, %r32
4009 andq $imm7, %r64 -> andl $imm7, %r32
4010 testq $imm31, %r64 -> testl $imm31, %r32
4011 xorq %r64, %r64 -> xorl %r32, %r32
4012 subq %r64, %r64 -> subl %r32, %r32
4013 movq $imm31, %r64 -> movl $imm31, %r32
4014 movq $imm32, %r64 -> movl $imm32, %r32
4016 i
.tm
.opcode_modifier
.norex64
= 1;
4017 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
4020 movq $imm31, %r64 -> movl $imm31, %r32
4021 movq $imm32, %r64 -> movl $imm32, %r32
4023 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4024 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4025 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4026 i
.types
[0].bitfield
.imm32
= 1;
4027 i
.types
[0].bitfield
.imm32s
= 0;
4028 i
.types
[0].bitfield
.imm64
= 0;
4029 i
.types
[1].bitfield
.dword
= 1;
4030 i
.types
[1].bitfield
.qword
= 0;
4031 if (i
.tm
.base_opcode
== 0xc6)
4034 movq $imm31, %r64 -> movl $imm31, %r32
4036 i
.tm
.base_opcode
= 0xb0;
4037 i
.tm
.extension_opcode
= None
;
4038 i
.tm
.opcode_modifier
.shortform
= 1;
4039 i
.tm
.opcode_modifier
.modrm
= 0;
4043 else if (i
.reg_operands
== 3
4044 && i
.op
[0].regs
== i
.op
[1].regs
4045 && !i
.types
[2].bitfield
.xmmword
4046 && (i
.tm
.opcode_modifier
.vex
4047 || ((!i
.mask
|| i
.mask
->zeroing
)
4049 && is_evex_encoding (&i
.tm
)
4050 && (i
.vec_encoding
!= vex_encoding_evex
4051 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4052 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4053 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4054 && i
.types
[2].bitfield
.ymmword
))))
4055 && ((i
.tm
.base_opcode
== 0x55
4056 || i
.tm
.base_opcode
== 0x6655
4057 || i
.tm
.base_opcode
== 0x66df
4058 || i
.tm
.base_opcode
== 0x57
4059 || i
.tm
.base_opcode
== 0x6657
4060 || i
.tm
.base_opcode
== 0x66ef
4061 || i
.tm
.base_opcode
== 0x66f8
4062 || i
.tm
.base_opcode
== 0x66f9
4063 || i
.tm
.base_opcode
== 0x66fa
4064 || i
.tm
.base_opcode
== 0x66fb
4065 || i
.tm
.base_opcode
== 0x42
4066 || i
.tm
.base_opcode
== 0x6642
4067 || i
.tm
.base_opcode
== 0x47
4068 || i
.tm
.base_opcode
== 0x6647)
4069 && i
.tm
.extension_opcode
== None
))
4072 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4074 EVEX VOP %zmmM, %zmmM, %zmmN
4075 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4076 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4077 EVEX VOP %ymmM, %ymmM, %ymmN
4078 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4079 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4080 VEX VOP %ymmM, %ymmM, %ymmN
4081 -> VEX VOP %xmmM, %xmmM, %xmmN
4082 VOP, one of vpandn and vpxor:
4083 VEX VOP %ymmM, %ymmM, %ymmN
4084 -> VEX VOP %xmmM, %xmmM, %xmmN
4085 VOP, one of vpandnd and vpandnq:
4086 EVEX VOP %zmmM, %zmmM, %zmmN
4087 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4088 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4089 EVEX VOP %ymmM, %ymmM, %ymmN
4090 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4091 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4092 VOP, one of vpxord and vpxorq:
4093 EVEX VOP %zmmM, %zmmM, %zmmN
4094 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4095 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4096 EVEX VOP %ymmM, %ymmM, %ymmN
4097 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4098 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4099 VOP, one of kxord and kxorq:
4100 VEX VOP %kM, %kM, %kN
4101 -> VEX kxorw %kM, %kM, %kN
4102 VOP, one of kandnd and kandnq:
4103 VEX VOP %kM, %kM, %kN
4104 -> VEX kandnw %kM, %kM, %kN
4106 if (is_evex_encoding (&i
.tm
))
4108 if (i
.vec_encoding
!= vex_encoding_evex
)
4110 i
.tm
.opcode_modifier
.vex
= VEX128
;
4111 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4112 i
.tm
.opcode_modifier
.evex
= 0;
4114 else if (optimize
> 1)
4115 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4119 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4121 i
.tm
.base_opcode
&= 0xff;
4122 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4125 i
.tm
.opcode_modifier
.vex
= VEX128
;
4127 if (i
.tm
.opcode_modifier
.vex
)
4128 for (j
= 0; j
< 3; j
++)
4130 i
.types
[j
].bitfield
.xmmword
= 1;
4131 i
.types
[j
].bitfield
.ymmword
= 0;
4134 else if (i
.vec_encoding
!= vex_encoding_evex
4135 && !i
.types
[0].bitfield
.zmmword
4136 && !i
.types
[1].bitfield
.zmmword
4139 && is_evex_encoding (&i
.tm
)
4140 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4141 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4142 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4143 || (i
.tm
.base_opcode
& ~4) == 0x66db
4144 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4145 && i
.tm
.extension_opcode
== None
)
4148 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4149 vmovdqu32 and vmovdqu64:
4150 EVEX VOP %xmmM, %xmmN
4151 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4152 EVEX VOP %ymmM, %ymmN
4153 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4155 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4157 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4159 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4161 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4162 VOP, one of vpand, vpandn, vpor, vpxor:
4163 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4164 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4165 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4166 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4167 EVEX VOP{d,q} mem, %xmmM, %xmmN
4168 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4169 EVEX VOP{d,q} mem, %ymmM, %ymmN
4170 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4172 for (j
= 0; j
< i
.operands
; j
++)
4173 if (operand_type_check (i
.types
[j
], disp
)
4174 && i
.op
[j
].disps
->X_op
== O_constant
)
4176 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4177 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4178 bytes, we choose EVEX Disp8 over VEX Disp32. */
4179 int evex_disp8
, vex_disp8
;
4180 unsigned int memshift
= i
.memshift
;
4181 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4183 evex_disp8
= fits_in_disp8 (n
);
4185 vex_disp8
= fits_in_disp8 (n
);
4186 if (evex_disp8
!= vex_disp8
)
4188 i
.memshift
= memshift
;
4192 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4195 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4196 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4197 i
.tm
.opcode_modifier
.vex
4198 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4199 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4200 /* VPAND, VPOR, and VPXOR are commutative. */
4201 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4202 i
.tm
.opcode_modifier
.commutative
= 1;
4203 i
.tm
.opcode_modifier
.evex
= 0;
4204 i
.tm
.opcode_modifier
.masking
= 0;
4205 i
.tm
.opcode_modifier
.broadcast
= 0;
4206 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4209 i
.types
[j
].bitfield
.disp8
4210 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4214 /* This is the guts of the machine-dependent assembler. LINE points to a
4215 machine dependent instruction. This function is supposed to emit
4216 the frags/bytes it assembles to. */
4219 md_assemble (char *line
)
4222 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4223 const insn_template
*t
;
4225 /* Initialize globals. */
4226 memset (&i
, '\0', sizeof (i
));
4227 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4228 i
.reloc
[j
] = NO_RELOC
;
4229 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4230 memset (im_expressions
, '\0', sizeof (im_expressions
));
4231 save_stack_p
= save_stack
;
4233 /* First parse an instruction mnemonic & call i386_operand for the operands.
4234 We assume that the scrubber has arranged it so that line[0] is the valid
4235 start of a (possibly prefixed) mnemonic. */
4237 line
= parse_insn (line
, mnemonic
);
4240 mnem_suffix
= i
.suffix
;
4242 line
= parse_operands (line
, mnemonic
);
4244 xfree (i
.memop1_string
);
4245 i
.memop1_string
= NULL
;
4249 /* Now we've parsed the mnemonic into a set of templates, and have the
4250 operands at hand. */
4252 /* All intel opcodes have reversed operands except for "bound" and
4253 "enter". We also don't reverse intersegment "jmp" and "call"
4254 instructions with 2 immediate operands so that the immediate segment
4255 precedes the offset, as it does when in AT&T mode. */
4258 && (strcmp (mnemonic
, "bound") != 0)
4259 && (strcmp (mnemonic
, "invlpga") != 0)
4260 && !(operand_type_check (i
.types
[0], imm
)
4261 && operand_type_check (i
.types
[1], imm
)))
4264 /* The order of the immediates should be reversed
4265 for 2 immediates extrq and insertq instructions */
4266 if (i
.imm_operands
== 2
4267 && (strcmp (mnemonic
, "extrq") == 0
4268 || strcmp (mnemonic
, "insertq") == 0))
4269 swap_2_operands (0, 1);
4274 /* Don't optimize displacement for movabs since it only takes 64bit
4277 && i
.disp_encoding
!= disp_encoding_32bit
4278 && (flag_code
!= CODE_64BIT
4279 || strcmp (mnemonic
, "movabs") != 0))
4282 /* Next, we find a template that matches the given insn,
4283 making sure the overlap of the given operands types is consistent
4284 with the template operand types. */
4286 if (!(t
= match_template (mnem_suffix
)))
4289 if (sse_check
!= check_none
4290 && !i
.tm
.opcode_modifier
.noavx
4291 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4292 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4293 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4294 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4295 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4296 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4297 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4298 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4299 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4300 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4302 (sse_check
== check_warning
4304 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4307 /* Zap movzx and movsx suffix. The suffix has been set from
4308 "word ptr" or "byte ptr" on the source operand in Intel syntax
4309 or extracted from mnemonic in AT&T syntax. But we'll use
4310 the destination register to choose the suffix for encoding. */
4311 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4313 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4314 there is no suffix, the default will be byte extension. */
4315 if (i
.reg_operands
!= 2
4318 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4323 if (i
.tm
.opcode_modifier
.fwait
)
4324 if (!add_prefix (FWAIT_OPCODE
))
4327 /* Check if REP prefix is OK. */
4328 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4330 as_bad (_("invalid instruction `%s' after `%s'"),
4331 i
.tm
.name
, i
.rep_prefix
);
4335 /* Check for lock without a lockable instruction. Destination operand
4336 must be memory unless it is xchg (0x86). */
4337 if (i
.prefix
[LOCK_PREFIX
]
4338 && (!i
.tm
.opcode_modifier
.islockable
4339 || i
.mem_operands
== 0
4340 || (i
.tm
.base_opcode
!= 0x86
4341 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4343 as_bad (_("expecting lockable instruction after `lock'"));
4347 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4348 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4350 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4354 /* Check if HLE prefix is OK. */
4355 if (i
.hle_prefix
&& !check_hle ())
4358 /* Check BND prefix. */
4359 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4360 as_bad (_("expecting valid branch instruction after `bnd'"));
4362 /* Check NOTRACK prefix. */
4363 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4364 as_bad (_("expecting indirect branch instruction after `notrack'"));
4366 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4368 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4369 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4370 else if (flag_code
!= CODE_16BIT
4371 ? i
.prefix
[ADDR_PREFIX
]
4372 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4373 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4376 /* Insert BND prefix. */
4377 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4379 if (!i
.prefix
[BND_PREFIX
])
4380 add_prefix (BND_PREFIX_OPCODE
);
4381 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4383 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4384 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4388 /* Check string instruction segment overrides. */
4389 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4391 if (!check_string ())
4393 i
.disp_operands
= 0;
4396 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4397 optimize_encoding ();
4399 if (!process_suffix ())
4402 /* Update operand types. */
4403 for (j
= 0; j
< i
.operands
; j
++)
4404 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4406 /* Make still unresolved immediate matches conform to size of immediate
4407 given in i.suffix. */
4408 if (!finalize_imm ())
4411 if (i
.types
[0].bitfield
.imm1
)
4412 i
.imm_operands
= 0; /* kludge for shift insns. */
4414 /* We only need to check those implicit registers for instructions
4415 with 3 operands or less. */
4416 if (i
.operands
<= 3)
4417 for (j
= 0; j
< i
.operands
; j
++)
4418 if (i
.types
[j
].bitfield
.inoutportreg
4419 || i
.types
[j
].bitfield
.shiftcount
4420 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4423 /* ImmExt should be processed after SSE2AVX. */
4424 if (!i
.tm
.opcode_modifier
.sse2avx
4425 && i
.tm
.opcode_modifier
.immext
)
4428 /* For insns with operands there are more diddles to do to the opcode. */
4431 if (!process_operands ())
4434 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4436 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4437 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4440 if (is_any_vex_encoding (&i
.tm
))
4442 if (!cpu_arch_flags
.bitfield
.cpui286
)
4444 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4449 if (i
.tm
.opcode_modifier
.vex
)
4450 build_vex_prefix (t
);
4452 build_evex_prefix ();
4455 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4456 instructions may define INT_OPCODE as well, so avoid this corner
4457 case for those instructions that use MODRM. */
4458 if (i
.tm
.base_opcode
== INT_OPCODE
4459 && !i
.tm
.opcode_modifier
.modrm
4460 && i
.op
[0].imms
->X_add_number
== 3)
4462 i
.tm
.base_opcode
= INT3_OPCODE
;
4466 if ((i
.tm
.opcode_modifier
.jump
4467 || i
.tm
.opcode_modifier
.jumpbyte
4468 || i
.tm
.opcode_modifier
.jumpdword
)
4469 && i
.op
[0].disps
->X_op
== O_constant
)
4471 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4472 the absolute address given by the constant. Since ix86 jumps and
4473 calls are pc relative, we need to generate a reloc. */
4474 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4475 i
.op
[0].disps
->X_op
= O_symbol
;
4478 if (i
.tm
.opcode_modifier
.rex64
)
4481 /* For 8 bit registers we need an empty rex prefix. Also if the
4482 instruction already has a prefix, we need to convert old
4483 registers to new ones. */
4485 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4486 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4487 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4488 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4489 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4490 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4495 i
.rex
|= REX_OPCODE
;
4496 for (x
= 0; x
< 2; x
++)
4498 /* Look for 8 bit operand that uses old registers. */
4499 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4500 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4502 /* In case it is "hi" register, give up. */
4503 if (i
.op
[x
].regs
->reg_num
> 3)
4504 as_bad (_("can't encode register '%s%s' in an "
4505 "instruction requiring REX prefix."),
4506 register_prefix
, i
.op
[x
].regs
->reg_name
);
4508 /* Otherwise it is equivalent to the extended register.
4509 Since the encoding doesn't change this is merely
4510 cosmetic cleanup for debug output. */
4512 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4517 if (i
.rex
== 0 && i
.rex_encoding
)
4519 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4520 that uses legacy register. If it is "hi" register, don't add
4521 the REX_OPCODE byte. */
4523 for (x
= 0; x
< 2; x
++)
4524 if (i
.types
[x
].bitfield
.reg
4525 && i
.types
[x
].bitfield
.byte
4526 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4527 && i
.op
[x
].regs
->reg_num
> 3)
4529 i
.rex_encoding
= FALSE
;
4538 add_prefix (REX_OPCODE
| i
.rex
);
4540 /* We are ready to output the insn. */
4545 parse_insn (char *line
, char *mnemonic
)
4548 char *token_start
= l
;
4551 const insn_template
*t
;
4557 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4562 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4564 as_bad (_("no such instruction: `%s'"), token_start
);
4569 if (!is_space_char (*l
)
4570 && *l
!= END_OF_INSN
4572 || (*l
!= PREFIX_SEPARATOR
4575 as_bad (_("invalid character %s in mnemonic"),
4576 output_invalid (*l
));
4579 if (token_start
== l
)
4581 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4582 as_bad (_("expecting prefix; got nothing"));
4584 as_bad (_("expecting mnemonic; got nothing"));
4588 /* Look up instruction (or prefix) via hash table. */
4589 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4591 if (*l
!= END_OF_INSN
4592 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4593 && current_templates
4594 && current_templates
->start
->opcode_modifier
.isprefix
)
4596 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4598 as_bad ((flag_code
!= CODE_64BIT
4599 ? _("`%s' is only supported in 64-bit mode")
4600 : _("`%s' is not supported in 64-bit mode")),
4601 current_templates
->start
->name
);
4604 /* If we are in 16-bit mode, do not allow addr16 or data16.
4605 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4606 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4607 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4608 && flag_code
!= CODE_64BIT
4609 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4610 ^ (flag_code
== CODE_16BIT
)))
4612 as_bad (_("redundant %s prefix"),
4613 current_templates
->start
->name
);
4616 if (current_templates
->start
->opcode_length
== 0)
4618 /* Handle pseudo prefixes. */
4619 switch (current_templates
->start
->base_opcode
)
4623 i
.disp_encoding
= disp_encoding_8bit
;
4627 i
.disp_encoding
= disp_encoding_32bit
;
4631 i
.dir_encoding
= dir_encoding_load
;
4635 i
.dir_encoding
= dir_encoding_store
;
4639 i
.vec_encoding
= vex_encoding_vex2
;
4643 i
.vec_encoding
= vex_encoding_vex3
;
4647 i
.vec_encoding
= vex_encoding_evex
;
4651 i
.rex_encoding
= TRUE
;
4655 i
.no_optimize
= TRUE
;
4663 /* Add prefix, checking for repeated prefixes. */
4664 switch (add_prefix (current_templates
->start
->base_opcode
))
4669 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4670 i
.notrack_prefix
= current_templates
->start
->name
;
4673 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4674 i
.hle_prefix
= current_templates
->start
->name
;
4675 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4676 i
.bnd_prefix
= current_templates
->start
->name
;
4678 i
.rep_prefix
= current_templates
->start
->name
;
4684 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4691 if (!current_templates
)
4693 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4694 Check if we should swap operand or force 32bit displacement in
4696 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4697 i
.dir_encoding
= dir_encoding_swap
;
4698 else if (mnem_p
- 3 == dot_p
4701 i
.disp_encoding
= disp_encoding_8bit
;
4702 else if (mnem_p
- 4 == dot_p
4706 i
.disp_encoding
= disp_encoding_32bit
;
4711 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4714 if (!current_templates
)
4717 if (mnem_p
> mnemonic
)
4719 /* See if we can get a match by trimming off a suffix. */
4722 case WORD_MNEM_SUFFIX
:
4723 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4724 i
.suffix
= SHORT_MNEM_SUFFIX
;
4727 case BYTE_MNEM_SUFFIX
:
4728 case QWORD_MNEM_SUFFIX
:
4729 i
.suffix
= mnem_p
[-1];
4731 current_templates
= (const templates
*) hash_find (op_hash
,
4734 case SHORT_MNEM_SUFFIX
:
4735 case LONG_MNEM_SUFFIX
:
4738 i
.suffix
= mnem_p
[-1];
4740 current_templates
= (const templates
*) hash_find (op_hash
,
4749 if (intel_float_operand (mnemonic
) == 1)
4750 i
.suffix
= SHORT_MNEM_SUFFIX
;
4752 i
.suffix
= LONG_MNEM_SUFFIX
;
4754 current_templates
= (const templates
*) hash_find (op_hash
,
4761 if (!current_templates
)
4763 as_bad (_("no such instruction: `%s'"), token_start
);
4768 if (current_templates
->start
->opcode_modifier
.jump
4769 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4771 /* Check for a branch hint. We allow ",pt" and ",pn" for
4772 predict taken and predict not taken respectively.
4773 I'm not sure that branch hints actually do anything on loop
4774 and jcxz insns (JumpByte) for current Pentium4 chips. They
4775 may work in the future and it doesn't hurt to accept them
4777 if (l
[0] == ',' && l
[1] == 'p')
4781 if (!add_prefix (DS_PREFIX_OPCODE
))
4785 else if (l
[2] == 'n')
4787 if (!add_prefix (CS_PREFIX_OPCODE
))
4793 /* Any other comma loses. */
4796 as_bad (_("invalid character %s in mnemonic"),
4797 output_invalid (*l
));
4801 /* Check if instruction is supported on specified architecture. */
4803 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4805 supported
|= cpu_flags_match (t
);
4806 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4808 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4809 as_warn (_("use .code16 to ensure correct addressing mode"));
4815 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4816 as_bad (flag_code
== CODE_64BIT
4817 ? _("`%s' is not supported in 64-bit mode")
4818 : _("`%s' is only supported in 64-bit mode"),
4819 current_templates
->start
->name
);
4821 as_bad (_("`%s' is not supported on `%s%s'"),
4822 current_templates
->start
->name
,
4823 cpu_arch_name
? cpu_arch_name
: default_arch
,
4824 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4830 parse_operands (char *l
, const char *mnemonic
)
4834 /* 1 if operand is pending after ','. */
4835 unsigned int expecting_operand
= 0;
4837 /* Non-zero if operand parens not balanced. */
4838 unsigned int paren_not_balanced
;
4840 while (*l
!= END_OF_INSN
)
4842 /* Skip optional white space before operand. */
4843 if (is_space_char (*l
))
4845 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4847 as_bad (_("invalid character %s before operand %d"),
4848 output_invalid (*l
),
4852 token_start
= l
; /* After white space. */
4853 paren_not_balanced
= 0;
4854 while (paren_not_balanced
|| *l
!= ',')
4856 if (*l
== END_OF_INSN
)
4858 if (paren_not_balanced
)
4861 as_bad (_("unbalanced parenthesis in operand %d."),
4864 as_bad (_("unbalanced brackets in operand %d."),
4869 break; /* we are done */
4871 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4873 as_bad (_("invalid character %s in operand %d"),
4874 output_invalid (*l
),
4881 ++paren_not_balanced
;
4883 --paren_not_balanced
;
4888 ++paren_not_balanced
;
4890 --paren_not_balanced
;
4894 if (l
!= token_start
)
4895 { /* Yes, we've read in another operand. */
4896 unsigned int operand_ok
;
4897 this_operand
= i
.operands
++;
4898 if (i
.operands
> MAX_OPERANDS
)
4900 as_bad (_("spurious operands; (%d operands/instruction max)"),
4904 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4905 /* Now parse operand adding info to 'i' as we go along. */
4906 END_STRING_AND_SAVE (l
);
4908 if (i
.mem_operands
> 1)
4910 as_bad (_("too many memory references for `%s'"),
4917 i386_intel_operand (token_start
,
4918 intel_float_operand (mnemonic
));
4920 operand_ok
= i386_att_operand (token_start
);
4922 RESTORE_END_STRING (l
);
4928 if (expecting_operand
)
4930 expecting_operand_after_comma
:
4931 as_bad (_("expecting operand after ','; got nothing"));
4936 as_bad (_("expecting operand before ','; got nothing"));
4941 /* Now *l must be either ',' or END_OF_INSN. */
4944 if (*++l
== END_OF_INSN
)
4946 /* Just skip it, if it's \n complain. */
4947 goto expecting_operand_after_comma
;
4949 expecting_operand
= 1;
4956 swap_2_operands (int xchg1
, int xchg2
)
4958 union i386_op temp_op
;
4959 i386_operand_type temp_type
;
4960 unsigned int temp_flags
;
4961 enum bfd_reloc_code_real temp_reloc
;
4963 temp_type
= i
.types
[xchg2
];
4964 i
.types
[xchg2
] = i
.types
[xchg1
];
4965 i
.types
[xchg1
] = temp_type
;
4967 temp_flags
= i
.flags
[xchg2
];
4968 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4969 i
.flags
[xchg1
] = temp_flags
;
4971 temp_op
= i
.op
[xchg2
];
4972 i
.op
[xchg2
] = i
.op
[xchg1
];
4973 i
.op
[xchg1
] = temp_op
;
4975 temp_reloc
= i
.reloc
[xchg2
];
4976 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4977 i
.reloc
[xchg1
] = temp_reloc
;
4981 if (i
.mask
->operand
== xchg1
)
4982 i
.mask
->operand
= xchg2
;
4983 else if (i
.mask
->operand
== xchg2
)
4984 i
.mask
->operand
= xchg1
;
4988 if (i
.broadcast
->operand
== xchg1
)
4989 i
.broadcast
->operand
= xchg2
;
4990 else if (i
.broadcast
->operand
== xchg2
)
4991 i
.broadcast
->operand
= xchg1
;
4995 if (i
.rounding
->operand
== xchg1
)
4996 i
.rounding
->operand
= xchg2
;
4997 else if (i
.rounding
->operand
== xchg2
)
4998 i
.rounding
->operand
= xchg1
;
5003 swap_operands (void)
5009 swap_2_operands (1, i
.operands
- 2);
5013 swap_2_operands (0, i
.operands
- 1);
5019 if (i
.mem_operands
== 2)
5021 const seg_entry
*temp_seg
;
5022 temp_seg
= i
.seg
[0];
5023 i
.seg
[0] = i
.seg
[1];
5024 i
.seg
[1] = temp_seg
;
5028 /* Try to ensure constant immediates are represented in the smallest
5033 char guess_suffix
= 0;
5037 guess_suffix
= i
.suffix
;
5038 else if (i
.reg_operands
)
5040 /* Figure out a suffix from the last register operand specified.
5041 We can't do this properly yet, ie. excluding InOutPortReg,
5042 but the following works for instructions with immediates.
5043 In any case, we can't set i.suffix yet. */
5044 for (op
= i
.operands
; --op
>= 0;)
5045 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5047 guess_suffix
= BYTE_MNEM_SUFFIX
;
5050 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5052 guess_suffix
= WORD_MNEM_SUFFIX
;
5055 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5057 guess_suffix
= LONG_MNEM_SUFFIX
;
5060 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5062 guess_suffix
= QWORD_MNEM_SUFFIX
;
5066 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5067 guess_suffix
= WORD_MNEM_SUFFIX
;
5069 for (op
= i
.operands
; --op
>= 0;)
5070 if (operand_type_check (i
.types
[op
], imm
))
5072 switch (i
.op
[op
].imms
->X_op
)
5075 /* If a suffix is given, this operand may be shortened. */
5076 switch (guess_suffix
)
5078 case LONG_MNEM_SUFFIX
:
5079 i
.types
[op
].bitfield
.imm32
= 1;
5080 i
.types
[op
].bitfield
.imm64
= 1;
5082 case WORD_MNEM_SUFFIX
:
5083 i
.types
[op
].bitfield
.imm16
= 1;
5084 i
.types
[op
].bitfield
.imm32
= 1;
5085 i
.types
[op
].bitfield
.imm32s
= 1;
5086 i
.types
[op
].bitfield
.imm64
= 1;
5088 case BYTE_MNEM_SUFFIX
:
5089 i
.types
[op
].bitfield
.imm8
= 1;
5090 i
.types
[op
].bitfield
.imm8s
= 1;
5091 i
.types
[op
].bitfield
.imm16
= 1;
5092 i
.types
[op
].bitfield
.imm32
= 1;
5093 i
.types
[op
].bitfield
.imm32s
= 1;
5094 i
.types
[op
].bitfield
.imm64
= 1;
5098 /* If this operand is at most 16 bits, convert it
5099 to a signed 16 bit number before trying to see
5100 whether it will fit in an even smaller size.
5101 This allows a 16-bit operand such as $0xffe0 to
5102 be recognised as within Imm8S range. */
5103 if ((i
.types
[op
].bitfield
.imm16
)
5104 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5106 i
.op
[op
].imms
->X_add_number
=
5107 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5110 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5111 if ((i
.types
[op
].bitfield
.imm32
)
5112 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5115 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5116 ^ ((offsetT
) 1 << 31))
5117 - ((offsetT
) 1 << 31));
5121 = operand_type_or (i
.types
[op
],
5122 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5124 /* We must avoid matching of Imm32 templates when 64bit
5125 only immediate is available. */
5126 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5127 i
.types
[op
].bitfield
.imm32
= 0;
5134 /* Symbols and expressions. */
5136 /* Convert symbolic operand to proper sizes for matching, but don't
5137 prevent matching a set of insns that only supports sizes other
5138 than those matching the insn suffix. */
5140 i386_operand_type mask
, allowed
;
5141 const insn_template
*t
;
5143 operand_type_set (&mask
, 0);
5144 operand_type_set (&allowed
, 0);
5146 for (t
= current_templates
->start
;
5147 t
< current_templates
->end
;
5149 allowed
= operand_type_or (allowed
,
5150 t
->operand_types
[op
]);
5151 switch (guess_suffix
)
5153 case QWORD_MNEM_SUFFIX
:
5154 mask
.bitfield
.imm64
= 1;
5155 mask
.bitfield
.imm32s
= 1;
5157 case LONG_MNEM_SUFFIX
:
5158 mask
.bitfield
.imm32
= 1;
5160 case WORD_MNEM_SUFFIX
:
5161 mask
.bitfield
.imm16
= 1;
5163 case BYTE_MNEM_SUFFIX
:
5164 mask
.bitfield
.imm8
= 1;
5169 allowed
= operand_type_and (mask
, allowed
);
5170 if (!operand_type_all_zero (&allowed
))
5171 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5178 /* Try to use the smallest displacement type too. */
5180 optimize_disp (void)
5184 for (op
= i
.operands
; --op
>= 0;)
5185 if (operand_type_check (i
.types
[op
], disp
))
5187 if (i
.op
[op
].disps
->X_op
== O_constant
)
5189 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5191 if (i
.types
[op
].bitfield
.disp16
5192 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5194 /* If this operand is at most 16 bits, convert
5195 to a signed 16 bit number and don't use 64bit
5197 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5198 i
.types
[op
].bitfield
.disp64
= 0;
5201 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5202 if (i
.types
[op
].bitfield
.disp32
5203 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5205 /* If this operand is at most 32 bits, convert
5206 to a signed 32 bit number and don't use 64bit
5208 op_disp
&= (((offsetT
) 2 << 31) - 1);
5209 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5210 i
.types
[op
].bitfield
.disp64
= 0;
5213 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5215 i
.types
[op
].bitfield
.disp8
= 0;
5216 i
.types
[op
].bitfield
.disp16
= 0;
5217 i
.types
[op
].bitfield
.disp32
= 0;
5218 i
.types
[op
].bitfield
.disp32s
= 0;
5219 i
.types
[op
].bitfield
.disp64
= 0;
5223 else if (flag_code
== CODE_64BIT
)
5225 if (fits_in_signed_long (op_disp
))
5227 i
.types
[op
].bitfield
.disp64
= 0;
5228 i
.types
[op
].bitfield
.disp32s
= 1;
5230 if (i
.prefix
[ADDR_PREFIX
]
5231 && fits_in_unsigned_long (op_disp
))
5232 i
.types
[op
].bitfield
.disp32
= 1;
5234 if ((i
.types
[op
].bitfield
.disp32
5235 || i
.types
[op
].bitfield
.disp32s
5236 || i
.types
[op
].bitfield
.disp16
)
5237 && fits_in_disp8 (op_disp
))
5238 i
.types
[op
].bitfield
.disp8
= 1;
5240 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5241 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5243 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5244 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5245 i
.types
[op
].bitfield
.disp8
= 0;
5246 i
.types
[op
].bitfield
.disp16
= 0;
5247 i
.types
[op
].bitfield
.disp32
= 0;
5248 i
.types
[op
].bitfield
.disp32s
= 0;
5249 i
.types
[op
].bitfield
.disp64
= 0;
5252 /* We only support 64bit displacement on constants. */
5253 i
.types
[op
].bitfield
.disp64
= 0;
5257 /* Return 1 if there is a match in broadcast bytes between operand
5258 GIVEN and instruction template T. */
5261 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5263 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5264 && i
.types
[given
].bitfield
.byte
)
5265 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5266 && i
.types
[given
].bitfield
.word
)
5267 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5268 && i
.types
[given
].bitfield
.dword
)
5269 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5270 && i
.types
[given
].bitfield
.qword
));
5273 /* Check if operands are valid for the instruction. */
5276 check_VecOperands (const insn_template
*t
)
5280 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5282 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5283 any one operand are implicity requiring AVX512VL support if the actual
5284 operand size is YMMword or XMMword. Since this function runs after
5285 template matching, there's no need to check for YMMword/XMMword in
5287 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5288 if (!cpu_flags_all_zero (&cpu
)
5289 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5290 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5292 for (op
= 0; op
< t
->operands
; ++op
)
5294 if (t
->operand_types
[op
].bitfield
.zmmword
5295 && (i
.types
[op
].bitfield
.ymmword
5296 || i
.types
[op
].bitfield
.xmmword
))
5298 i
.error
= unsupported
;
5304 /* Without VSIB byte, we can't have a vector register for index. */
5305 if (!t
->opcode_modifier
.vecsib
5307 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5308 || i
.index_reg
->reg_type
.bitfield
.ymmword
5309 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5311 i
.error
= unsupported_vector_index_register
;
5315 /* Check if default mask is allowed. */
5316 if (t
->opcode_modifier
.nodefmask
5317 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5319 i
.error
= no_default_mask
;
5323 /* For VSIB byte, we need a vector register for index, and all vector
5324 registers must be distinct. */
5325 if (t
->opcode_modifier
.vecsib
)
5328 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5329 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5330 || (t
->opcode_modifier
.vecsib
== VecSIB256
5331 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5332 || (t
->opcode_modifier
.vecsib
== VecSIB512
5333 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5335 i
.error
= invalid_vsib_address
;
5339 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5340 if (i
.reg_operands
== 2 && !i
.mask
)
5342 gas_assert (i
.types
[0].bitfield
.regsimd
);
5343 gas_assert (i
.types
[0].bitfield
.xmmword
5344 || i
.types
[0].bitfield
.ymmword
);
5345 gas_assert (i
.types
[2].bitfield
.regsimd
);
5346 gas_assert (i
.types
[2].bitfield
.xmmword
5347 || i
.types
[2].bitfield
.ymmword
);
5348 if (operand_check
== check_none
)
5350 if (register_number (i
.op
[0].regs
)
5351 != register_number (i
.index_reg
)
5352 && register_number (i
.op
[2].regs
)
5353 != register_number (i
.index_reg
)
5354 && register_number (i
.op
[0].regs
)
5355 != register_number (i
.op
[2].regs
))
5357 if (operand_check
== check_error
)
5359 i
.error
= invalid_vector_register_set
;
5362 as_warn (_("mask, index, and destination registers should be distinct"));
5364 else if (i
.reg_operands
== 1 && i
.mask
)
5366 if (i
.types
[1].bitfield
.regsimd
5367 && (i
.types
[1].bitfield
.xmmword
5368 || i
.types
[1].bitfield
.ymmword
5369 || i
.types
[1].bitfield
.zmmword
)
5370 && (register_number (i
.op
[1].regs
)
5371 == register_number (i
.index_reg
)))
5373 if (operand_check
== check_error
)
5375 i
.error
= invalid_vector_register_set
;
5378 if (operand_check
!= check_none
)
5379 as_warn (_("index and destination registers should be distinct"));
5384 /* Check if broadcast is supported by the instruction and is applied
5385 to the memory operand. */
5388 i386_operand_type type
, overlap
;
5390 /* Check if specified broadcast is supported in this instruction,
5391 and its broadcast bytes match the memory operand. */
5392 op
= i
.broadcast
->operand
;
5393 if (!t
->opcode_modifier
.broadcast
5394 || !(i
.flags
[op
] & Operand_Mem
)
5395 || (!i
.types
[op
].bitfield
.unspecified
5396 && !match_broadcast_size (t
, op
)))
5399 i
.error
= unsupported_broadcast
;
5403 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5404 * i
.broadcast
->type
);
5405 operand_type_set (&type
, 0);
5406 switch (i
.broadcast
->bytes
)
5409 type
.bitfield
.word
= 1;
5412 type
.bitfield
.dword
= 1;
5415 type
.bitfield
.qword
= 1;
5418 type
.bitfield
.xmmword
= 1;
5421 type
.bitfield
.ymmword
= 1;
5424 type
.bitfield
.zmmword
= 1;
5430 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5431 if (operand_type_all_zero (&overlap
))
5434 if (t
->opcode_modifier
.checkregsize
)
5438 type
.bitfield
.baseindex
= 1;
5439 for (j
= 0; j
< i
.operands
; ++j
)
5442 && !operand_type_register_match(i
.types
[j
],
5443 t
->operand_types
[j
],
5445 t
->operand_types
[op
]))
5450 /* If broadcast is supported in this instruction, we need to check if
5451 operand of one-element size isn't specified without broadcast. */
5452 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5454 /* Find memory operand. */
5455 for (op
= 0; op
< i
.operands
; op
++)
5456 if (operand_type_check (i
.types
[op
], anymem
))
5458 gas_assert (op
< i
.operands
);
5459 /* Check size of the memory operand. */
5460 if (match_broadcast_size (t
, op
))
5462 i
.error
= broadcast_needed
;
5467 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5469 /* Check if requested masking is supported. */
5472 switch (t
->opcode_modifier
.masking
)
5476 case MERGING_MASKING
:
5477 if (i
.mask
->zeroing
)
5480 i
.error
= unsupported_masking
;
5484 case DYNAMIC_MASKING
:
5485 /* Memory destinations allow only merging masking. */
5486 if (i
.mask
->zeroing
&& i
.mem_operands
)
5488 /* Find memory operand. */
5489 for (op
= 0; op
< i
.operands
; op
++)
5490 if (i
.flags
[op
] & Operand_Mem
)
5492 gas_assert (op
< i
.operands
);
5493 if (op
== i
.operands
- 1)
5495 i
.error
= unsupported_masking
;
5505 /* Check if masking is applied to dest operand. */
5506 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5508 i
.error
= mask_not_on_destination
;
5515 if (!t
->opcode_modifier
.sae
5516 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5518 i
.error
= unsupported_rc_sae
;
5521 /* If the instruction has several immediate operands and one of
5522 them is rounding, the rounding operand should be the last
5523 immediate operand. */
5524 if (i
.imm_operands
> 1
5525 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5527 i
.error
= rc_sae_operand_not_last_imm
;
5532 /* Check vector Disp8 operand. */
5533 if (t
->opcode_modifier
.disp8memshift
5534 && i
.disp_encoding
!= disp_encoding_32bit
)
5537 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5538 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5539 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5542 const i386_operand_type
*type
= NULL
;
5545 for (op
= 0; op
< i
.operands
; op
++)
5546 if (operand_type_check (i
.types
[op
], anymem
))
5548 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5549 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5550 else if (t
->operand_types
[op
].bitfield
.xmmword
5551 + t
->operand_types
[op
].bitfield
.ymmword
5552 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5553 type
= &t
->operand_types
[op
];
5554 else if (!i
.types
[op
].bitfield
.unspecified
)
5555 type
= &i
.types
[op
];
5557 else if (i
.types
[op
].bitfield
.regsimd
5558 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5560 if (i
.types
[op
].bitfield
.zmmword
)
5562 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5564 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5570 if (type
->bitfield
.zmmword
)
5572 else if (type
->bitfield
.ymmword
)
5574 else if (type
->bitfield
.xmmword
)
5578 /* For the check in fits_in_disp8(). */
5579 if (i
.memshift
== 0)
5583 for (op
= 0; op
< i
.operands
; op
++)
5584 if (operand_type_check (i
.types
[op
], disp
)
5585 && i
.op
[op
].disps
->X_op
== O_constant
)
5587 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5589 i
.types
[op
].bitfield
.disp8
= 1;
5592 i
.types
[op
].bitfield
.disp8
= 0;
5601 /* Check if operands are valid for the instruction. Update VEX
5605 VEX_check_operands (const insn_template
*t
)
5607 if (i
.vec_encoding
== vex_encoding_evex
)
5609 /* This instruction must be encoded with EVEX prefix. */
5610 if (!is_evex_encoding (t
))
5612 i
.error
= unsupported
;
5618 if (!t
->opcode_modifier
.vex
)
5620 /* This instruction template doesn't have VEX prefix. */
5621 if (i
.vec_encoding
!= vex_encoding_default
)
5623 i
.error
= unsupported
;
5629 /* Only check VEX_Imm4, which must be the first operand. */
5630 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5632 if (i
.op
[0].imms
->X_op
!= O_constant
5633 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5639 /* Turn off Imm8 so that update_imm won't complain. */
5640 i
.types
[0] = vec_imm4
;
5646 static const insn_template
*
5647 match_template (char mnem_suffix
)
5649 /* Points to template once we've found it. */
5650 const insn_template
*t
;
5651 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5652 i386_operand_type overlap4
;
5653 unsigned int found_reverse_match
;
5654 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5655 i386_operand_type operand_types
[MAX_OPERANDS
];
5656 int addr_prefix_disp
;
5658 unsigned int found_cpu_match
, size_match
;
5659 unsigned int check_register
;
5660 enum i386_error specific_error
= 0;
5662 #if MAX_OPERANDS != 5
5663 # error "MAX_OPERANDS must be 5."
5666 found_reverse_match
= 0;
5667 addr_prefix_disp
= -1;
5669 memset (&suffix_check
, 0, sizeof (suffix_check
));
5670 if (intel_syntax
&& i
.broadcast
)
5672 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5673 suffix_check
.no_bsuf
= 1;
5674 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5675 suffix_check
.no_wsuf
= 1;
5676 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5677 suffix_check
.no_ssuf
= 1;
5678 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5679 suffix_check
.no_lsuf
= 1;
5680 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5681 suffix_check
.no_qsuf
= 1;
5682 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5683 suffix_check
.no_ldsuf
= 1;
5685 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5688 switch (mnem_suffix
)
5690 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5691 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5692 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5693 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5694 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5698 /* Must have right number of operands. */
5699 i
.error
= number_of_operands_mismatch
;
5701 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5703 addr_prefix_disp
= -1;
5704 found_reverse_match
= 0;
5706 if (i
.operands
!= t
->operands
)
5709 /* Check processor support. */
5710 i
.error
= unsupported
;
5711 found_cpu_match
= (cpu_flags_match (t
)
5712 == CPU_FLAGS_PERFECT_MATCH
);
5713 if (!found_cpu_match
)
5716 /* Check AT&T mnemonic. */
5717 i
.error
= unsupported_with_intel_mnemonic
;
5718 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5721 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5722 i
.error
= unsupported_syntax
;
5723 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5724 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5725 || (intel64
&& t
->opcode_modifier
.amd64
)
5726 || (!intel64
&& t
->opcode_modifier
.intel64
))
5729 /* Check the suffix, except for some instructions in intel mode. */
5730 i
.error
= invalid_instruction_suffix
;
5731 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5732 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5733 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5734 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5735 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5736 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5737 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5739 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5740 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5741 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5742 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5743 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5744 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5745 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5748 size_match
= operand_size_match (t
);
5752 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5753 operand_types
[j
] = t
->operand_types
[j
];
5755 /* In general, don't allow 64-bit operands in 32-bit mode. */
5756 if (i
.suffix
== QWORD_MNEM_SUFFIX
5757 && flag_code
!= CODE_64BIT
5759 ? (!t
->opcode_modifier
.ignoresize
5760 && !t
->opcode_modifier
.broadcast
5761 && !intel_float_operand (t
->name
))
5762 : intel_float_operand (t
->name
) != 2)
5763 && ((!operand_types
[0].bitfield
.regmmx
5764 && !operand_types
[0].bitfield
.regsimd
)
5765 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5766 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5767 && (t
->base_opcode
!= 0x0fc7
5768 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5771 /* In general, don't allow 32-bit operands on pre-386. */
5772 else if (i
.suffix
== LONG_MNEM_SUFFIX
5773 && !cpu_arch_flags
.bitfield
.cpui386
5775 ? (!t
->opcode_modifier
.ignoresize
5776 && !intel_float_operand (t
->name
))
5777 : intel_float_operand (t
->name
) != 2)
5778 && ((!operand_types
[0].bitfield
.regmmx
5779 && !operand_types
[0].bitfield
.regsimd
)
5780 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5781 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5784 /* Do not verify operands when there are none. */
5788 /* We've found a match; break out of loop. */
5792 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5793 into Disp32/Disp16/Disp32 operand. */
5794 if (i
.prefix
[ADDR_PREFIX
] != 0)
5796 /* There should be only one Disp operand. */
5800 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5802 if (operand_types
[j
].bitfield
.disp16
)
5804 addr_prefix_disp
= j
;
5805 operand_types
[j
].bitfield
.disp32
= 1;
5806 operand_types
[j
].bitfield
.disp16
= 0;
5812 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5814 if (operand_types
[j
].bitfield
.disp32
)
5816 addr_prefix_disp
= j
;
5817 operand_types
[j
].bitfield
.disp32
= 0;
5818 operand_types
[j
].bitfield
.disp16
= 1;
5824 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5826 if (operand_types
[j
].bitfield
.disp64
)
5828 addr_prefix_disp
= j
;
5829 operand_types
[j
].bitfield
.disp64
= 0;
5830 operand_types
[j
].bitfield
.disp32
= 1;
5838 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5839 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5842 /* We check register size if needed. */
5843 if (t
->opcode_modifier
.checkregsize
)
5845 check_register
= (1 << t
->operands
) - 1;
5847 check_register
&= ~(1 << i
.broadcast
->operand
);
5852 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5853 switch (t
->operands
)
5856 if (!operand_type_match (overlap0
, i
.types
[0]))
5860 /* xchg %eax, %eax is a special case. It is an alias for nop
5861 only in 32bit mode and we can use opcode 0x90. In 64bit
5862 mode, we can't use 0x90 for xchg %eax, %eax since it should
5863 zero-extend %eax to %rax. */
5864 if (flag_code
== CODE_64BIT
5865 && t
->base_opcode
== 0x90
5866 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5867 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5869 /* xrelease mov %eax, <disp> is another special case. It must not
5870 match the accumulator-only encoding of mov. */
5871 if (flag_code
!= CODE_64BIT
5873 && t
->base_opcode
== 0xa0
5874 && i
.types
[0].bitfield
.acc
5875 && operand_type_check (i
.types
[1], anymem
))
5880 if (!(size_match
& MATCH_STRAIGHT
))
5882 /* Reverse direction of operands if swapping is possible in the first
5883 place (operands need to be symmetric) and
5884 - the load form is requested, and the template is a store form,
5885 - the store form is requested, and the template is a load form,
5886 - the non-default (swapped) form is requested. */
5887 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5888 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5889 && !operand_type_all_zero (&overlap1
))
5890 switch (i
.dir_encoding
)
5892 case dir_encoding_load
:
5893 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5894 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5898 case dir_encoding_store
:
5899 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5900 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5904 case dir_encoding_swap
:
5907 case dir_encoding_default
:
5910 /* If we want store form, we skip the current load. */
5911 if ((i
.dir_encoding
== dir_encoding_store
5912 || i
.dir_encoding
== dir_encoding_swap
)
5913 && i
.mem_operands
== 0
5914 && t
->opcode_modifier
.load
)
5919 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5920 if (!operand_type_match (overlap0
, i
.types
[0])
5921 || !operand_type_match (overlap1
, i
.types
[1])
5922 || ((check_register
& 3) == 3
5923 && !operand_type_register_match (i
.types
[0],
5928 /* Check if other direction is valid ... */
5929 if (!t
->opcode_modifier
.d
)
5933 if (!(size_match
& MATCH_REVERSE
))
5935 /* Try reversing direction of operands. */
5936 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5937 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5938 if (!operand_type_match (overlap0
, i
.types
[0])
5939 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5941 && !operand_type_register_match (i
.types
[0],
5942 operand_types
[i
.operands
- 1],
5943 i
.types
[i
.operands
- 1],
5946 /* Does not match either direction. */
5949 /* found_reverse_match holds which of D or FloatR
5951 if (!t
->opcode_modifier
.d
)
5952 found_reverse_match
= 0;
5953 else if (operand_types
[0].bitfield
.tbyte
)
5954 found_reverse_match
= Opcode_FloatD
;
5955 else if (operand_types
[0].bitfield
.xmmword
5956 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5957 || operand_types
[0].bitfield
.regmmx
5958 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5959 || is_any_vex_encoding(t
))
5960 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5961 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5963 found_reverse_match
= Opcode_D
;
5964 if (t
->opcode_modifier
.floatr
)
5965 found_reverse_match
|= Opcode_FloatR
;
5969 /* Found a forward 2 operand match here. */
5970 switch (t
->operands
)
5973 overlap4
= operand_type_and (i
.types
[4],
5977 overlap3
= operand_type_and (i
.types
[3],
5981 overlap2
= operand_type_and (i
.types
[2],
5986 switch (t
->operands
)
5989 if (!operand_type_match (overlap4
, i
.types
[4])
5990 || !operand_type_register_match (i
.types
[3],
5997 if (!operand_type_match (overlap3
, i
.types
[3])
5998 || ((check_register
& 0xa) == 0xa
5999 && !operand_type_register_match (i
.types
[1],
6003 || ((check_register
& 0xc) == 0xc
6004 && !operand_type_register_match (i
.types
[2],
6011 /* Here we make use of the fact that there are no
6012 reverse match 3 operand instructions. */
6013 if (!operand_type_match (overlap2
, i
.types
[2])
6014 || ((check_register
& 5) == 5
6015 && !operand_type_register_match (i
.types
[0],
6019 || ((check_register
& 6) == 6
6020 && !operand_type_register_match (i
.types
[1],
6028 /* Found either forward/reverse 2, 3 or 4 operand match here:
6029 slip through to break. */
6031 if (!found_cpu_match
)
6034 /* Check if vector and VEX operands are valid. */
6035 if (check_VecOperands (t
) || VEX_check_operands (t
))
6037 specific_error
= i
.error
;
6041 /* We've found a match; break out of loop. */
6045 if (t
== current_templates
->end
)
6047 /* We found no match. */
6048 const char *err_msg
;
6049 switch (specific_error
? specific_error
: i
.error
)
6053 case operand_size_mismatch
:
6054 err_msg
= _("operand size mismatch");
6056 case operand_type_mismatch
:
6057 err_msg
= _("operand type mismatch");
6059 case register_type_mismatch
:
6060 err_msg
= _("register type mismatch");
6062 case number_of_operands_mismatch
:
6063 err_msg
= _("number of operands mismatch");
6065 case invalid_instruction_suffix
:
6066 err_msg
= _("invalid instruction suffix");
6069 err_msg
= _("constant doesn't fit in 4 bits");
6071 case unsupported_with_intel_mnemonic
:
6072 err_msg
= _("unsupported with Intel mnemonic");
6074 case unsupported_syntax
:
6075 err_msg
= _("unsupported syntax");
6078 as_bad (_("unsupported instruction `%s'"),
6079 current_templates
->start
->name
);
6081 case invalid_vsib_address
:
6082 err_msg
= _("invalid VSIB address");
6084 case invalid_vector_register_set
:
6085 err_msg
= _("mask, index, and destination registers must be distinct");
6087 case unsupported_vector_index_register
:
6088 err_msg
= _("unsupported vector index register");
6090 case unsupported_broadcast
:
6091 err_msg
= _("unsupported broadcast");
6093 case broadcast_needed
:
6094 err_msg
= _("broadcast is needed for operand of such type");
6096 case unsupported_masking
:
6097 err_msg
= _("unsupported masking");
6099 case mask_not_on_destination
:
6100 err_msg
= _("mask not on destination operand");
6102 case no_default_mask
:
6103 err_msg
= _("default mask isn't allowed");
6105 case unsupported_rc_sae
:
6106 err_msg
= _("unsupported static rounding/sae");
6108 case rc_sae_operand_not_last_imm
:
6110 err_msg
= _("RC/SAE operand must precede immediate operands");
6112 err_msg
= _("RC/SAE operand must follow immediate operands");
6114 case invalid_register_operand
:
6115 err_msg
= _("invalid register operand");
6118 as_bad (_("%s for `%s'"), err_msg
,
6119 current_templates
->start
->name
);
6123 if (!quiet_warnings
)
6126 && (i
.types
[0].bitfield
.jumpabsolute
6127 != operand_types
[0].bitfield
.jumpabsolute
))
6129 as_warn (_("indirect %s without `*'"), t
->name
);
6132 if (t
->opcode_modifier
.isprefix
6133 && t
->opcode_modifier
.ignoresize
)
6135 /* Warn them that a data or address size prefix doesn't
6136 affect assembly of the next line of code. */
6137 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6141 /* Copy the template we found. */
6144 if (addr_prefix_disp
!= -1)
6145 i
.tm
.operand_types
[addr_prefix_disp
]
6146 = operand_types
[addr_prefix_disp
];
6148 if (found_reverse_match
)
6150 /* If we found a reverse match we must alter the opcode
6151 direction bit. found_reverse_match holds bits to change
6152 (different for int & float insns). */
6154 i
.tm
.base_opcode
^= found_reverse_match
;
6156 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6157 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6166 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6167 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6169 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6171 as_bad (_("`%s' operand %d must use `%ses' segment"),
6177 /* There's only ever one segment override allowed per instruction.
6178 This instruction possibly has a legal segment override on the
6179 second operand, so copy the segment to where non-string
6180 instructions store it, allowing common code. */
6181 i
.seg
[0] = i
.seg
[1];
6183 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6185 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6187 as_bad (_("`%s' operand %d must use `%ses' segment"),
6198 process_suffix (void)
6200 /* If matched instruction specifies an explicit instruction mnemonic
6202 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6203 i
.suffix
= WORD_MNEM_SUFFIX
;
6204 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6205 i
.suffix
= LONG_MNEM_SUFFIX
;
6206 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6207 i
.suffix
= QWORD_MNEM_SUFFIX
;
6208 else if (i
.reg_operands
)
6210 /* If there's no instruction mnemonic suffix we try to invent one
6211 based on register operands. */
6214 /* We take i.suffix from the last register operand specified,
6215 Destination register type is more significant than source
6216 register type. crc32 in SSE4.2 prefers source register
6218 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6220 if (i
.types
[0].bitfield
.byte
)
6221 i
.suffix
= BYTE_MNEM_SUFFIX
;
6222 else if (i
.types
[0].bitfield
.word
)
6223 i
.suffix
= WORD_MNEM_SUFFIX
;
6224 else if (i
.types
[0].bitfield
.dword
)
6225 i
.suffix
= LONG_MNEM_SUFFIX
;
6226 else if (i
.types
[0].bitfield
.qword
)
6227 i
.suffix
= QWORD_MNEM_SUFFIX
;
6234 if (i
.tm
.base_opcode
== 0xf20f38f0)
6236 /* We have to know the operand size for crc32. */
6237 as_bad (_("ambiguous memory operand size for `%s`"),
6242 for (op
= i
.operands
; --op
>= 0;)
6243 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6244 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6246 if (!i
.types
[op
].bitfield
.reg
)
6248 if (i
.types
[op
].bitfield
.byte
)
6249 i
.suffix
= BYTE_MNEM_SUFFIX
;
6250 else if (i
.types
[op
].bitfield
.word
)
6251 i
.suffix
= WORD_MNEM_SUFFIX
;
6252 else if (i
.types
[op
].bitfield
.dword
)
6253 i
.suffix
= LONG_MNEM_SUFFIX
;
6254 else if (i
.types
[op
].bitfield
.qword
)
6255 i
.suffix
= QWORD_MNEM_SUFFIX
;
6262 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6265 && i
.tm
.opcode_modifier
.ignoresize
6266 && i
.tm
.opcode_modifier
.no_bsuf
)
6268 else if (!check_byte_reg ())
6271 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6274 && i
.tm
.opcode_modifier
.ignoresize
6275 && i
.tm
.opcode_modifier
.no_lsuf
6276 && !i
.tm
.opcode_modifier
.todword
6277 && !i
.tm
.opcode_modifier
.toqword
)
6279 else if (!check_long_reg ())
6282 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6285 && i
.tm
.opcode_modifier
.ignoresize
6286 && i
.tm
.opcode_modifier
.no_qsuf
6287 && !i
.tm
.opcode_modifier
.todword
6288 && !i
.tm
.opcode_modifier
.toqword
)
6290 else if (!check_qword_reg ())
6293 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6296 && i
.tm
.opcode_modifier
.ignoresize
6297 && i
.tm
.opcode_modifier
.no_wsuf
)
6299 else if (!check_word_reg ())
6302 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6303 /* Do nothing if the instruction is going to ignore the prefix. */
6308 else if (i
.tm
.opcode_modifier
.defaultsize
6310 /* exclude fldenv/frstor/fsave/fstenv */
6311 && i
.tm
.opcode_modifier
.no_ssuf
)
6313 if (stackop_size
== LONG_MNEM_SUFFIX
6314 && i
.tm
.base_opcode
== 0xcf)
6316 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6317 .code16gcc directive to support 16-bit mode with
6318 32-bit address. For IRET without a suffix, generate
6319 16-bit IRET (opcode 0xcf) to return from an interrupt
6321 i
.suffix
= WORD_MNEM_SUFFIX
;
6322 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6325 i
.suffix
= stackop_size
;
6327 else if (intel_syntax
6329 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6330 || i
.tm
.opcode_modifier
.jumpbyte
6331 || i
.tm
.opcode_modifier
.jumpintersegment
6332 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6333 && i
.tm
.extension_opcode
<= 3)))
6338 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6340 i
.suffix
= QWORD_MNEM_SUFFIX
;
6345 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6346 i
.suffix
= LONG_MNEM_SUFFIX
;
6349 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6350 i
.suffix
= WORD_MNEM_SUFFIX
;
6359 if (i
.tm
.opcode_modifier
.w
)
6361 as_bad (_("no instruction mnemonic suffix given and "
6362 "no register operands; can't size instruction"));
6368 unsigned int suffixes
;
6370 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6371 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6373 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6375 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6377 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6379 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6382 /* There are more than suffix matches. */
6383 if (i
.tm
.opcode_modifier
.w
6384 || ((suffixes
& (suffixes
- 1))
6385 && !i
.tm
.opcode_modifier
.defaultsize
6386 && !i
.tm
.opcode_modifier
.ignoresize
))
6388 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6394 /* Change the opcode based on the operand size given by i.suffix. */
6397 /* Size floating point instruction. */
6398 case LONG_MNEM_SUFFIX
:
6399 if (i
.tm
.opcode_modifier
.floatmf
)
6401 i
.tm
.base_opcode
^= 4;
6405 case WORD_MNEM_SUFFIX
:
6406 case QWORD_MNEM_SUFFIX
:
6407 /* It's not a byte, select word/dword operation. */
6408 if (i
.tm
.opcode_modifier
.w
)
6410 if (i
.tm
.opcode_modifier
.shortform
)
6411 i
.tm
.base_opcode
|= 8;
6413 i
.tm
.base_opcode
|= 1;
6416 case SHORT_MNEM_SUFFIX
:
6417 /* Now select between word & dword operations via the operand
6418 size prefix, except for instructions that will ignore this
6420 if (i
.reg_operands
> 0
6421 && i
.types
[0].bitfield
.reg
6422 && i
.tm
.opcode_modifier
.addrprefixopreg
6423 && (i
.tm
.opcode_modifier
.immext
6424 || i
.operands
== 1))
6426 /* The address size override prefix changes the size of the
6428 if ((flag_code
== CODE_32BIT
6429 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6430 || (flag_code
!= CODE_32BIT
6431 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6432 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6435 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6436 && !i
.tm
.opcode_modifier
.ignoresize
6437 && !i
.tm
.opcode_modifier
.floatmf
6438 && !is_any_vex_encoding (&i
.tm
)
6439 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6440 || (flag_code
== CODE_64BIT
6441 && i
.tm
.opcode_modifier
.jumpbyte
)))
6443 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6445 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6446 prefix
= ADDR_PREFIX_OPCODE
;
6448 if (!add_prefix (prefix
))
6452 /* Set mode64 for an operand. */
6453 if (i
.suffix
== QWORD_MNEM_SUFFIX
6454 && flag_code
== CODE_64BIT
6455 && !i
.tm
.opcode_modifier
.norex64
6456 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6458 && ! (i
.operands
== 2
6459 && i
.tm
.base_opcode
== 0x90
6460 && i
.tm
.extension_opcode
== None
6461 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6462 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6468 if (i
.reg_operands
!= 0
6470 && i
.tm
.opcode_modifier
.addrprefixopreg
6471 && !i
.tm
.opcode_modifier
.immext
)
6473 /* Check invalid register operand when the address size override
6474 prefix changes the size of register operands. */
6476 enum { need_word
, need_dword
, need_qword
} need
;
6478 if (flag_code
== CODE_32BIT
)
6479 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6482 if (i
.prefix
[ADDR_PREFIX
])
6485 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6488 for (op
= 0; op
< i
.operands
; op
++)
6489 if (i
.types
[op
].bitfield
.reg
6490 && ((need
== need_word
6491 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6492 || (need
== need_dword
6493 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6494 || (need
== need_qword
6495 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6497 as_bad (_("invalid register operand size for `%s'"),
6507 check_byte_reg (void)
6511 for (op
= i
.operands
; --op
>= 0;)
6513 /* Skip non-register operands. */
6514 if (!i
.types
[op
].bitfield
.reg
)
6517 /* If this is an eight bit register, it's OK. If it's the 16 or
6518 32 bit version of an eight bit register, we will just use the
6519 low portion, and that's OK too. */
6520 if (i
.types
[op
].bitfield
.byte
)
6523 /* I/O port address operands are OK too. */
6524 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6527 /* crc32 doesn't generate this warning. */
6528 if (i
.tm
.base_opcode
== 0xf20f38f0)
6531 if ((i
.types
[op
].bitfield
.word
6532 || i
.types
[op
].bitfield
.dword
6533 || i
.types
[op
].bitfield
.qword
)
6534 && i
.op
[op
].regs
->reg_num
< 4
6535 /* Prohibit these changes in 64bit mode, since the lowering
6536 would be more complicated. */
6537 && flag_code
!= CODE_64BIT
)
6539 #if REGISTER_WARNINGS
6540 if (!quiet_warnings
)
6541 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6543 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6544 ? REGNAM_AL
- REGNAM_AX
6545 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6547 i
.op
[op
].regs
->reg_name
,
6552 /* Any other register is bad. */
6553 if (i
.types
[op
].bitfield
.reg
6554 || i
.types
[op
].bitfield
.regmmx
6555 || i
.types
[op
].bitfield
.regsimd
6556 || i
.types
[op
].bitfield
.sreg2
6557 || i
.types
[op
].bitfield
.sreg3
6558 || i
.types
[op
].bitfield
.control
6559 || i
.types
[op
].bitfield
.debug
6560 || i
.types
[op
].bitfield
.test
)
6562 as_bad (_("`%s%s' not allowed with `%s%c'"),
6564 i
.op
[op
].regs
->reg_name
,
6574 check_long_reg (void)
6578 for (op
= i
.operands
; --op
>= 0;)
6579 /* Skip non-register operands. */
6580 if (!i
.types
[op
].bitfield
.reg
)
6582 /* Reject eight bit registers, except where the template requires
6583 them. (eg. movzb) */
6584 else if (i
.types
[op
].bitfield
.byte
6585 && (i
.tm
.operand_types
[op
].bitfield
.reg
6586 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6587 && (i
.tm
.operand_types
[op
].bitfield
.word
6588 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6590 as_bad (_("`%s%s' not allowed with `%s%c'"),
6592 i
.op
[op
].regs
->reg_name
,
6597 /* Warn if the e prefix on a general reg is missing. */
6598 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6599 && i
.types
[op
].bitfield
.word
6600 && (i
.tm
.operand_types
[op
].bitfield
.reg
6601 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6602 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6604 /* Prohibit these changes in the 64bit mode, since the
6605 lowering is more complicated. */
6606 if (flag_code
== CODE_64BIT
)
6608 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6609 register_prefix
, i
.op
[op
].regs
->reg_name
,
6613 #if REGISTER_WARNINGS
6614 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6616 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6617 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6620 /* Warn if the r prefix on a general reg is present. */
6621 else if (i
.types
[op
].bitfield
.qword
6622 && (i
.tm
.operand_types
[op
].bitfield
.reg
6623 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6624 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6627 && i
.tm
.opcode_modifier
.toqword
6628 && !i
.types
[0].bitfield
.regsimd
)
6630 /* Convert to QWORD. We want REX byte. */
6631 i
.suffix
= QWORD_MNEM_SUFFIX
;
6635 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6636 register_prefix
, i
.op
[op
].regs
->reg_name
,
6645 check_qword_reg (void)
6649 for (op
= i
.operands
; --op
>= 0; )
6650 /* Skip non-register operands. */
6651 if (!i
.types
[op
].bitfield
.reg
)
6653 /* Reject eight bit registers, except where the template requires
6654 them. (eg. movzb) */
6655 else if (i
.types
[op
].bitfield
.byte
6656 && (i
.tm
.operand_types
[op
].bitfield
.reg
6657 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6658 && (i
.tm
.operand_types
[op
].bitfield
.word
6659 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6661 as_bad (_("`%s%s' not allowed with `%s%c'"),
6663 i
.op
[op
].regs
->reg_name
,
6668 /* Warn if the r prefix on a general reg is missing. */
6669 else if ((i
.types
[op
].bitfield
.word
6670 || i
.types
[op
].bitfield
.dword
)
6671 && (i
.tm
.operand_types
[op
].bitfield
.reg
6672 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6673 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6675 /* Prohibit these changes in the 64bit mode, since the
6676 lowering is more complicated. */
6678 && i
.tm
.opcode_modifier
.todword
6679 && !i
.types
[0].bitfield
.regsimd
)
6681 /* Convert to DWORD. We don't want REX byte. */
6682 i
.suffix
= LONG_MNEM_SUFFIX
;
6686 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6687 register_prefix
, i
.op
[op
].regs
->reg_name
,
6696 check_word_reg (void)
6699 for (op
= i
.operands
; --op
>= 0;)
6700 /* Skip non-register operands. */
6701 if (!i
.types
[op
].bitfield
.reg
)
6703 /* Reject eight bit registers, except where the template requires
6704 them. (eg. movzb) */
6705 else if (i
.types
[op
].bitfield
.byte
6706 && (i
.tm
.operand_types
[op
].bitfield
.reg
6707 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6708 && (i
.tm
.operand_types
[op
].bitfield
.word
6709 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6711 as_bad (_("`%s%s' not allowed with `%s%c'"),
6713 i
.op
[op
].regs
->reg_name
,
6718 /* Warn if the e or r prefix on a general reg is present. */
6719 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6720 && (i
.types
[op
].bitfield
.dword
6721 || i
.types
[op
].bitfield
.qword
)
6722 && (i
.tm
.operand_types
[op
].bitfield
.reg
6723 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6724 && i
.tm
.operand_types
[op
].bitfield
.word
)
6726 /* Prohibit these changes in the 64bit mode, since the
6727 lowering is more complicated. */
6728 if (flag_code
== CODE_64BIT
)
6730 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6731 register_prefix
, i
.op
[op
].regs
->reg_name
,
6735 #if REGISTER_WARNINGS
6736 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6738 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6739 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6746 update_imm (unsigned int j
)
6748 i386_operand_type overlap
= i
.types
[j
];
6749 if ((overlap
.bitfield
.imm8
6750 || overlap
.bitfield
.imm8s
6751 || overlap
.bitfield
.imm16
6752 || overlap
.bitfield
.imm32
6753 || overlap
.bitfield
.imm32s
6754 || overlap
.bitfield
.imm64
)
6755 && !operand_type_equal (&overlap
, &imm8
)
6756 && !operand_type_equal (&overlap
, &imm8s
)
6757 && !operand_type_equal (&overlap
, &imm16
)
6758 && !operand_type_equal (&overlap
, &imm32
)
6759 && !operand_type_equal (&overlap
, &imm32s
)
6760 && !operand_type_equal (&overlap
, &imm64
))
6764 i386_operand_type temp
;
6766 operand_type_set (&temp
, 0);
6767 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6769 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6770 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6772 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6773 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6774 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6776 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6777 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6780 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6783 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6784 || operand_type_equal (&overlap
, &imm16_32
)
6785 || operand_type_equal (&overlap
, &imm16_32s
))
6787 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6792 if (!operand_type_equal (&overlap
, &imm8
)
6793 && !operand_type_equal (&overlap
, &imm8s
)
6794 && !operand_type_equal (&overlap
, &imm16
)
6795 && !operand_type_equal (&overlap
, &imm32
)
6796 && !operand_type_equal (&overlap
, &imm32s
)
6797 && !operand_type_equal (&overlap
, &imm64
))
6799 as_bad (_("no instruction mnemonic suffix given; "
6800 "can't determine immediate size"));
6804 i
.types
[j
] = overlap
;
6814 /* Update the first 2 immediate operands. */
6815 n
= i
.operands
> 2 ? 2 : i
.operands
;
6818 for (j
= 0; j
< n
; j
++)
6819 if (update_imm (j
) == 0)
6822 /* The 3rd operand can't be immediate operand. */
6823 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6830 process_operands (void)
6832 /* Default segment register this instruction will use for memory
6833 accesses. 0 means unknown. This is only for optimizing out
6834 unnecessary segment overrides. */
6835 const seg_entry
*default_seg
= 0;
6837 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6839 unsigned int dupl
= i
.operands
;
6840 unsigned int dest
= dupl
- 1;
6843 /* The destination must be an xmm register. */
6844 gas_assert (i
.reg_operands
6845 && MAX_OPERANDS
> dupl
6846 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6848 if (i
.tm
.operand_types
[0].bitfield
.acc
6849 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6851 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6853 /* Keep xmm0 for instructions with VEX prefix and 3
6855 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6856 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6861 /* We remove the first xmm0 and keep the number of
6862 operands unchanged, which in fact duplicates the
6864 for (j
= 1; j
< i
.operands
; j
++)
6866 i
.op
[j
- 1] = i
.op
[j
];
6867 i
.types
[j
- 1] = i
.types
[j
];
6868 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6872 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6874 gas_assert ((MAX_OPERANDS
- 1) > dupl
6875 && (i
.tm
.opcode_modifier
.vexsources
6878 /* Add the implicit xmm0 for instructions with VEX prefix
6880 for (j
= i
.operands
; j
> 0; j
--)
6882 i
.op
[j
] = i
.op
[j
- 1];
6883 i
.types
[j
] = i
.types
[j
- 1];
6884 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6887 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6888 i
.types
[0] = regxmm
;
6889 i
.tm
.operand_types
[0] = regxmm
;
6892 i
.reg_operands
+= 2;
6897 i
.op
[dupl
] = i
.op
[dest
];
6898 i
.types
[dupl
] = i
.types
[dest
];
6899 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6908 i
.op
[dupl
] = i
.op
[dest
];
6909 i
.types
[dupl
] = i
.types
[dest
];
6910 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6913 if (i
.tm
.opcode_modifier
.immext
)
6916 else if (i
.tm
.operand_types
[0].bitfield
.acc
6917 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6921 for (j
= 1; j
< i
.operands
; j
++)
6923 i
.op
[j
- 1] = i
.op
[j
];
6924 i
.types
[j
- 1] = i
.types
[j
];
6926 /* We need to adjust fields in i.tm since they are used by
6927 build_modrm_byte. */
6928 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6935 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6937 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6939 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6940 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6941 regnum
= register_number (i
.op
[1].regs
);
6942 first_reg_in_group
= regnum
& ~3;
6943 last_reg_in_group
= first_reg_in_group
+ 3;
6944 if (regnum
!= first_reg_in_group
)
6945 as_warn (_("source register `%s%s' implicitly denotes"
6946 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6947 register_prefix
, i
.op
[1].regs
->reg_name
,
6948 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6949 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6952 else if (i
.tm
.opcode_modifier
.regkludge
)
6954 /* The imul $imm, %reg instruction is converted into
6955 imul $imm, %reg, %reg, and the clr %reg instruction
6956 is converted into xor %reg, %reg. */
6958 unsigned int first_reg_op
;
6960 if (operand_type_check (i
.types
[0], reg
))
6964 /* Pretend we saw the extra register operand. */
6965 gas_assert (i
.reg_operands
== 1
6966 && i
.op
[first_reg_op
+ 1].regs
== 0);
6967 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6968 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6973 if (i
.tm
.opcode_modifier
.shortform
)
6975 if (i
.types
[0].bitfield
.sreg2
6976 || i
.types
[0].bitfield
.sreg3
)
6978 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6979 && i
.op
[0].regs
->reg_num
== 1)
6981 as_bad (_("you can't `pop %scs'"), register_prefix
);
6984 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6985 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6990 /* The register or float register operand is in operand
6994 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6995 || operand_type_check (i
.types
[0], reg
))
6999 /* Register goes in low 3 bits of opcode. */
7000 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7001 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7003 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7005 /* Warn about some common errors, but press on regardless.
7006 The first case can be generated by gcc (<= 2.8.1). */
7007 if (i
.operands
== 2)
7009 /* Reversed arguments on faddp, fsubp, etc. */
7010 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7011 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7012 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7016 /* Extraneous `l' suffix on fp insn. */
7017 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7018 register_prefix
, i
.op
[0].regs
->reg_name
);
7023 else if (i
.tm
.opcode_modifier
.modrm
)
7025 /* The opcode is completed (modulo i.tm.extension_opcode which
7026 must be put into the modrm byte). Now, we make the modrm and
7027 index base bytes based on all the info we've collected. */
7029 default_seg
= build_modrm_byte ();
7031 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7035 else if (i
.tm
.opcode_modifier
.isstring
)
7037 /* For the string instructions that allow a segment override
7038 on one of their operands, the default segment is ds. */
7042 if (i
.tm
.base_opcode
== 0x8d /* lea */
7045 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7047 /* If a segment was explicitly specified, and the specified segment
7048 is not the default, use an opcode prefix to select it. If we
7049 never figured out what the default segment is, then default_seg
7050 will be zero at this point, and the specified segment prefix will
7052 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7054 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7060 static const seg_entry
*
7061 build_modrm_byte (void)
7063 const seg_entry
*default_seg
= 0;
7064 unsigned int source
, dest
;
7067 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7070 unsigned int nds
, reg_slot
;
7073 dest
= i
.operands
- 1;
7076 /* There are 2 kinds of instructions:
7077 1. 5 operands: 4 register operands or 3 register operands
7078 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7079 VexW0 or VexW1. The destination must be either XMM, YMM or
7081 2. 4 operands: 4 register operands or 3 register operands
7082 plus 1 memory operand, with VexXDS. */
7083 gas_assert ((i
.reg_operands
== 4
7084 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7085 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7086 && i
.tm
.opcode_modifier
.vexw
7087 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7089 /* If VexW1 is set, the first non-immediate operand is the source and
7090 the second non-immediate one is encoded in the immediate operand. */
7091 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7093 source
= i
.imm_operands
;
7094 reg_slot
= i
.imm_operands
+ 1;
7098 source
= i
.imm_operands
+ 1;
7099 reg_slot
= i
.imm_operands
;
7102 if (i
.imm_operands
== 0)
7104 /* When there is no immediate operand, generate an 8bit
7105 immediate operand to encode the first operand. */
7106 exp
= &im_expressions
[i
.imm_operands
++];
7107 i
.op
[i
.operands
].imms
= exp
;
7108 i
.types
[i
.operands
] = imm8
;
7111 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7112 exp
->X_op
= O_constant
;
7113 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7114 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7118 unsigned int imm_slot
;
7120 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7122 if (i
.tm
.opcode_modifier
.immext
)
7124 /* When ImmExt is set, the immediate byte is the last
7126 imm_slot
= i
.operands
- 1;
7134 /* Turn on Imm8 so that output_imm will generate it. */
7135 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7138 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7139 i
.op
[imm_slot
].imms
->X_add_number
7140 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7141 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7144 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7145 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7150 /* i.reg_operands MUST be the number of real register operands;
7151 implicit registers do not count. If there are 3 register
7152 operands, it must be a instruction with VexNDS. For a
7153 instruction with VexNDD, the destination register is encoded
7154 in VEX prefix. If there are 4 register operands, it must be
7155 a instruction with VEX prefix and 3 sources. */
7156 if (i
.mem_operands
== 0
7157 && ((i
.reg_operands
== 2
7158 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7159 || (i
.reg_operands
== 3
7160 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7161 || (i
.reg_operands
== 4 && vex_3_sources
)))
7169 /* When there are 3 operands, one of them may be immediate,
7170 which may be the first or the last operand. Otherwise,
7171 the first operand must be shift count register (cl) or it
7172 is an instruction with VexNDS. */
7173 gas_assert (i
.imm_operands
== 1
7174 || (i
.imm_operands
== 0
7175 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7176 || i
.types
[0].bitfield
.shiftcount
)));
7177 if (operand_type_check (i
.types
[0], imm
)
7178 || i
.types
[0].bitfield
.shiftcount
)
7184 /* When there are 4 operands, the first two must be 8bit
7185 immediate operands. The source operand will be the 3rd
7188 For instructions with VexNDS, if the first operand
7189 an imm8, the source operand is the 2nd one. If the last
7190 operand is imm8, the source operand is the first one. */
7191 gas_assert ((i
.imm_operands
== 2
7192 && i
.types
[0].bitfield
.imm8
7193 && i
.types
[1].bitfield
.imm8
)
7194 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7195 && i
.imm_operands
== 1
7196 && (i
.types
[0].bitfield
.imm8
7197 || i
.types
[i
.operands
- 1].bitfield
.imm8
7199 if (i
.imm_operands
== 2)
7203 if (i
.types
[0].bitfield
.imm8
)
7210 if (is_evex_encoding (&i
.tm
))
7212 /* For EVEX instructions, when there are 5 operands, the
7213 first one must be immediate operand. If the second one
7214 is immediate operand, the source operand is the 3th
7215 one. If the last one is immediate operand, the source
7216 operand is the 2nd one. */
7217 gas_assert (i
.imm_operands
== 2
7218 && i
.tm
.opcode_modifier
.sae
7219 && operand_type_check (i
.types
[0], imm
));
7220 if (operand_type_check (i
.types
[1], imm
))
7222 else if (operand_type_check (i
.types
[4], imm
))
7236 /* RC/SAE operand could be between DEST and SRC. That happens
7237 when one operand is GPR and the other one is XMM/YMM/ZMM
7239 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7242 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7244 /* For instructions with VexNDS, the register-only source
7245 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7246 register. It is encoded in VEX prefix. We need to
7247 clear RegMem bit before calling operand_type_equal. */
7249 i386_operand_type op
;
7252 /* Check register-only source operand when two source
7253 operands are swapped. */
7254 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7255 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7263 op
= i
.tm
.operand_types
[vvvv
];
7264 op
.bitfield
.regmem
= 0;
7265 if ((dest
+ 1) >= i
.operands
7266 || ((!op
.bitfield
.reg
7267 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7268 && !op
.bitfield
.regsimd
7269 && !operand_type_equal (&op
, ®mask
)))
7271 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7277 /* One of the register operands will be encoded in the i.tm.reg
7278 field, the other in the combined i.tm.mode and i.tm.regmem
7279 fields. If no form of this instruction supports a memory
7280 destination operand, then we assume the source operand may
7281 sometimes be a memory operand and so we need to store the
7282 destination in the i.rm.reg field. */
7283 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7284 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7286 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7287 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7288 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7289 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7290 i
.has_regmmx
= TRUE
;
7291 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7292 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7294 if (i
.types
[dest
].bitfield
.zmmword
7295 || i
.types
[source
].bitfield
.zmmword
)
7296 i
.has_regzmm
= TRUE
;
7297 else if (i
.types
[dest
].bitfield
.ymmword
7298 || i
.types
[source
].bitfield
.ymmword
)
7299 i
.has_regymm
= TRUE
;
7301 i
.has_regxmm
= TRUE
;
7303 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7305 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7307 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7309 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7314 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7315 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7316 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7318 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7320 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7322 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7325 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7327 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7330 add_prefix (LOCK_PREFIX_OPCODE
);
7334 { /* If it's not 2 reg operands... */
7339 unsigned int fake_zero_displacement
= 0;
7342 for (op
= 0; op
< i
.operands
; op
++)
7343 if (operand_type_check (i
.types
[op
], anymem
))
7345 gas_assert (op
< i
.operands
);
7347 if (i
.tm
.opcode_modifier
.vecsib
)
7349 if (i
.index_reg
->reg_num
== RegIZ
)
7352 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7355 i
.sib
.base
= NO_BASE_REGISTER
;
7356 i
.sib
.scale
= i
.log2_scale_factor
;
7357 i
.types
[op
].bitfield
.disp8
= 0;
7358 i
.types
[op
].bitfield
.disp16
= 0;
7359 i
.types
[op
].bitfield
.disp64
= 0;
7360 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7362 /* Must be 32 bit */
7363 i
.types
[op
].bitfield
.disp32
= 1;
7364 i
.types
[op
].bitfield
.disp32s
= 0;
7368 i
.types
[op
].bitfield
.disp32
= 0;
7369 i
.types
[op
].bitfield
.disp32s
= 1;
7372 i
.sib
.index
= i
.index_reg
->reg_num
;
7373 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7375 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7381 if (i
.base_reg
== 0)
7384 if (!i
.disp_operands
)
7385 fake_zero_displacement
= 1;
7386 if (i
.index_reg
== 0)
7388 i386_operand_type newdisp
;
7390 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7391 /* Operand is just <disp> */
7392 if (flag_code
== CODE_64BIT
)
7394 /* 64bit mode overwrites the 32bit absolute
7395 addressing by RIP relative addressing and
7396 absolute addressing is encoded by one of the
7397 redundant SIB forms. */
7398 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7399 i
.sib
.base
= NO_BASE_REGISTER
;
7400 i
.sib
.index
= NO_INDEX_REGISTER
;
7401 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7403 else if ((flag_code
== CODE_16BIT
)
7404 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7406 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7411 i
.rm
.regmem
= NO_BASE_REGISTER
;
7414 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7415 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7417 else if (!i
.tm
.opcode_modifier
.vecsib
)
7419 /* !i.base_reg && i.index_reg */
7420 if (i
.index_reg
->reg_num
== RegIZ
)
7421 i
.sib
.index
= NO_INDEX_REGISTER
;
7423 i
.sib
.index
= i
.index_reg
->reg_num
;
7424 i
.sib
.base
= NO_BASE_REGISTER
;
7425 i
.sib
.scale
= i
.log2_scale_factor
;
7426 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7427 i
.types
[op
].bitfield
.disp8
= 0;
7428 i
.types
[op
].bitfield
.disp16
= 0;
7429 i
.types
[op
].bitfield
.disp64
= 0;
7430 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7432 /* Must be 32 bit */
7433 i
.types
[op
].bitfield
.disp32
= 1;
7434 i
.types
[op
].bitfield
.disp32s
= 0;
7438 i
.types
[op
].bitfield
.disp32
= 0;
7439 i
.types
[op
].bitfield
.disp32s
= 1;
7441 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7445 /* RIP addressing for 64bit mode. */
7446 else if (i
.base_reg
->reg_num
== RegIP
)
7448 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7449 i
.rm
.regmem
= NO_BASE_REGISTER
;
7450 i
.types
[op
].bitfield
.disp8
= 0;
7451 i
.types
[op
].bitfield
.disp16
= 0;
7452 i
.types
[op
].bitfield
.disp32
= 0;
7453 i
.types
[op
].bitfield
.disp32s
= 1;
7454 i
.types
[op
].bitfield
.disp64
= 0;
7455 i
.flags
[op
] |= Operand_PCrel
;
7456 if (! i
.disp_operands
)
7457 fake_zero_displacement
= 1;
7459 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7461 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7462 switch (i
.base_reg
->reg_num
)
7465 if (i
.index_reg
== 0)
7467 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7468 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7472 if (i
.index_reg
== 0)
7475 if (operand_type_check (i
.types
[op
], disp
) == 0)
7477 /* fake (%bp) into 0(%bp) */
7478 i
.types
[op
].bitfield
.disp8
= 1;
7479 fake_zero_displacement
= 1;
7482 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7483 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7485 default: /* (%si) -> 4 or (%di) -> 5 */
7486 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7488 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7490 else /* i.base_reg and 32/64 bit mode */
7492 if (flag_code
== CODE_64BIT
7493 && operand_type_check (i
.types
[op
], disp
))
7495 i
.types
[op
].bitfield
.disp16
= 0;
7496 i
.types
[op
].bitfield
.disp64
= 0;
7497 if (i
.prefix
[ADDR_PREFIX
] == 0)
7499 i
.types
[op
].bitfield
.disp32
= 0;
7500 i
.types
[op
].bitfield
.disp32s
= 1;
7504 i
.types
[op
].bitfield
.disp32
= 1;
7505 i
.types
[op
].bitfield
.disp32s
= 0;
7509 if (!i
.tm
.opcode_modifier
.vecsib
)
7510 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7511 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7513 i
.sib
.base
= i
.base_reg
->reg_num
;
7514 /* x86-64 ignores REX prefix bit here to avoid decoder
7516 if (!(i
.base_reg
->reg_flags
& RegRex
)
7517 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7518 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7520 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7522 fake_zero_displacement
= 1;
7523 i
.types
[op
].bitfield
.disp8
= 1;
7525 i
.sib
.scale
= i
.log2_scale_factor
;
7526 if (i
.index_reg
== 0)
7528 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7529 /* <disp>(%esp) becomes two byte modrm with no index
7530 register. We've already stored the code for esp
7531 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7532 Any base register besides %esp will not use the
7533 extra modrm byte. */
7534 i
.sib
.index
= NO_INDEX_REGISTER
;
7536 else if (!i
.tm
.opcode_modifier
.vecsib
)
7538 if (i
.index_reg
->reg_num
== RegIZ
)
7539 i
.sib
.index
= NO_INDEX_REGISTER
;
7541 i
.sib
.index
= i
.index_reg
->reg_num
;
7542 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7543 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7548 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7549 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7553 if (!fake_zero_displacement
7557 fake_zero_displacement
= 1;
7558 if (i
.disp_encoding
== disp_encoding_8bit
)
7559 i
.types
[op
].bitfield
.disp8
= 1;
7561 i
.types
[op
].bitfield
.disp32
= 1;
7563 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7567 if (fake_zero_displacement
)
7569 /* Fakes a zero displacement assuming that i.types[op]
7570 holds the correct displacement size. */
7573 gas_assert (i
.op
[op
].disps
== 0);
7574 exp
= &disp_expressions
[i
.disp_operands
++];
7575 i
.op
[op
].disps
= exp
;
7576 exp
->X_op
= O_constant
;
7577 exp
->X_add_number
= 0;
7578 exp
->X_add_symbol
= (symbolS
*) 0;
7579 exp
->X_op_symbol
= (symbolS
*) 0;
7587 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7589 if (operand_type_check (i
.types
[0], imm
))
7590 i
.vex
.register_specifier
= NULL
;
7593 /* VEX.vvvv encodes one of the sources when the first
7594 operand is not an immediate. */
7595 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7596 i
.vex
.register_specifier
= i
.op
[0].regs
;
7598 i
.vex
.register_specifier
= i
.op
[1].regs
;
7601 /* Destination is a XMM register encoded in the ModRM.reg
7603 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7604 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7607 /* ModRM.rm and VEX.B encodes the other source. */
7608 if (!i
.mem_operands
)
7612 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7613 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7615 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7617 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7621 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7623 i
.vex
.register_specifier
= i
.op
[2].regs
;
7624 if (!i
.mem_operands
)
7627 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7628 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7632 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7633 (if any) based on i.tm.extension_opcode. Again, we must be
7634 careful to make sure that segment/control/debug/test/MMX
7635 registers are coded into the i.rm.reg field. */
7636 else if (i
.reg_operands
)
7639 unsigned int vex_reg
= ~0;
7641 for (op
= 0; op
< i
.operands
; op
++)
7643 if (i
.types
[op
].bitfield
.reg
7644 || i
.types
[op
].bitfield
.regbnd
7645 || i
.types
[op
].bitfield
.regmask
7646 || i
.types
[op
].bitfield
.sreg2
7647 || i
.types
[op
].bitfield
.sreg3
7648 || i
.types
[op
].bitfield
.control
7649 || i
.types
[op
].bitfield
.debug
7650 || i
.types
[op
].bitfield
.test
)
7652 if (i
.types
[op
].bitfield
.regsimd
)
7654 if (i
.types
[op
].bitfield
.zmmword
)
7655 i
.has_regzmm
= TRUE
;
7656 else if (i
.types
[op
].bitfield
.ymmword
)
7657 i
.has_regymm
= TRUE
;
7659 i
.has_regxmm
= TRUE
;
7662 if (i
.types
[op
].bitfield
.regmmx
)
7664 i
.has_regmmx
= TRUE
;
7671 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7673 /* For instructions with VexNDS, the register-only
7674 source operand is encoded in VEX prefix. */
7675 gas_assert (mem
!= (unsigned int) ~0);
7680 gas_assert (op
< i
.operands
);
7684 /* Check register-only source operand when two source
7685 operands are swapped. */
7686 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7687 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7691 gas_assert (mem
== (vex_reg
+ 1)
7692 && op
< i
.operands
);
7697 gas_assert (vex_reg
< i
.operands
);
7701 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7703 /* For instructions with VexNDD, the register destination
7704 is encoded in VEX prefix. */
7705 if (i
.mem_operands
== 0)
7707 /* There is no memory operand. */
7708 gas_assert ((op
+ 2) == i
.operands
);
7713 /* There are only 2 non-immediate operands. */
7714 gas_assert (op
< i
.imm_operands
+ 2
7715 && i
.operands
== i
.imm_operands
+ 2);
7716 vex_reg
= i
.imm_operands
+ 1;
7720 gas_assert (op
< i
.operands
);
7722 if (vex_reg
!= (unsigned int) ~0)
7724 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7726 if ((!type
->bitfield
.reg
7727 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7728 && !type
->bitfield
.regsimd
7729 && !operand_type_equal (type
, ®mask
))
7732 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7735 /* Don't set OP operand twice. */
7738 /* If there is an extension opcode to put here, the
7739 register number must be put into the regmem field. */
7740 if (i
.tm
.extension_opcode
!= None
)
7742 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7743 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7745 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7750 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7751 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7753 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7758 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7759 must set it to 3 to indicate this is a register operand
7760 in the regmem field. */
7761 if (!i
.mem_operands
)
7765 /* Fill in i.rm.reg field with extension opcode (if any). */
7766 if (i
.tm
.extension_opcode
!= None
)
7767 i
.rm
.reg
= i
.tm
.extension_opcode
;
7773 output_branch (void)
7779 relax_substateT subtype
;
7783 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7784 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7787 if (i
.prefix
[DATA_PREFIX
] != 0)
7793 /* Pentium4 branch hints. */
7794 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7795 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7800 if (i
.prefix
[REX_PREFIX
] != 0)
7806 /* BND prefixed jump. */
7807 if (i
.prefix
[BND_PREFIX
] != 0)
7809 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7813 if (i
.prefixes
!= 0 && !intel_syntax
)
7814 as_warn (_("skipping prefixes on this instruction"));
7816 /* It's always a symbol; End frag & setup for relax.
7817 Make sure there is enough room in this frag for the largest
7818 instruction we may generate in md_convert_frag. This is 2
7819 bytes for the opcode and room for the prefix and largest
7821 frag_grow (prefix
+ 2 + 4);
7822 /* Prefix and 1 opcode byte go in fr_fix. */
7823 p
= frag_more (prefix
+ 1);
7824 if (i
.prefix
[DATA_PREFIX
] != 0)
7825 *p
++ = DATA_PREFIX_OPCODE
;
7826 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7827 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7828 *p
++ = i
.prefix
[SEG_PREFIX
];
7829 if (i
.prefix
[REX_PREFIX
] != 0)
7830 *p
++ = i
.prefix
[REX_PREFIX
];
7831 *p
= i
.tm
.base_opcode
;
7833 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7834 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7835 else if (cpu_arch_flags
.bitfield
.cpui386
)
7836 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7838 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7841 sym
= i
.op
[0].disps
->X_add_symbol
;
7842 off
= i
.op
[0].disps
->X_add_number
;
7844 if (i
.op
[0].disps
->X_op
!= O_constant
7845 && i
.op
[0].disps
->X_op
!= O_symbol
)
7847 /* Handle complex expressions. */
7848 sym
= make_expr_symbol (i
.op
[0].disps
);
7852 /* 1 possible extra opcode + 4 byte displacement go in var part.
7853 Pass reloc in fr_var. */
7854 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7857 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7858 /* Return TRUE iff PLT32 relocation should be used for branching to
7862 need_plt32_p (symbolS
*s
)
7864 /* PLT32 relocation is ELF only. */
7869 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7870 krtld support it. */
7874 /* Since there is no need to prepare for PLT branch on x86-64, we
7875 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7876 be used as a marker for 32-bit PC-relative branches. */
7880 /* Weak or undefined symbol need PLT32 relocation. */
7881 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7884 /* Non-global symbol doesn't need PLT32 relocation. */
7885 if (! S_IS_EXTERNAL (s
))
7888 /* Other global symbols need PLT32 relocation. NB: Symbol with
7889 non-default visibilities are treated as normal global symbol
7890 so that PLT32 relocation can be used as a marker for 32-bit
7891 PC-relative branches. It is useful for linker relaxation. */
7902 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7904 if (i
.tm
.opcode_modifier
.jumpbyte
)
7906 /* This is a loop or jecxz type instruction. */
7908 if (i
.prefix
[ADDR_PREFIX
] != 0)
7910 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7913 /* Pentium4 branch hints. */
7914 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7915 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7917 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7926 if (flag_code
== CODE_16BIT
)
7929 if (i
.prefix
[DATA_PREFIX
] != 0)
7931 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7941 if (i
.prefix
[REX_PREFIX
] != 0)
7943 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7947 /* BND prefixed jump. */
7948 if (i
.prefix
[BND_PREFIX
] != 0)
7950 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7954 if (i
.prefixes
!= 0 && !intel_syntax
)
7955 as_warn (_("skipping prefixes on this instruction"));
7957 p
= frag_more (i
.tm
.opcode_length
+ size
);
7958 switch (i
.tm
.opcode_length
)
7961 *p
++ = i
.tm
.base_opcode
>> 8;
7964 *p
++ = i
.tm
.base_opcode
;
7970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7972 && jump_reloc
== NO_RELOC
7973 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7974 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7977 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7979 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7980 i
.op
[0].disps
, 1, jump_reloc
);
7982 /* All jumps handled here are signed, but don't use a signed limit
7983 check for 32 and 16 bit jumps as we want to allow wrap around at
7984 4G and 64k respectively. */
7986 fixP
->fx_signed
= 1;
7990 output_interseg_jump (void)
7998 if (flag_code
== CODE_16BIT
)
8002 if (i
.prefix
[DATA_PREFIX
] != 0)
8008 if (i
.prefix
[REX_PREFIX
] != 0)
8018 if (i
.prefixes
!= 0 && !intel_syntax
)
8019 as_warn (_("skipping prefixes on this instruction"));
8021 /* 1 opcode; 2 segment; offset */
8022 p
= frag_more (prefix
+ 1 + 2 + size
);
8024 if (i
.prefix
[DATA_PREFIX
] != 0)
8025 *p
++ = DATA_PREFIX_OPCODE
;
8027 if (i
.prefix
[REX_PREFIX
] != 0)
8028 *p
++ = i
.prefix
[REX_PREFIX
];
8030 *p
++ = i
.tm
.base_opcode
;
8031 if (i
.op
[1].imms
->X_op
== O_constant
)
8033 offsetT n
= i
.op
[1].imms
->X_add_number
;
8036 && !fits_in_unsigned_word (n
)
8037 && !fits_in_signed_word (n
))
8039 as_bad (_("16-bit jump out of range"));
8042 md_number_to_chars (p
, n
, size
);
8045 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8046 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8047 if (i
.op
[0].imms
->X_op
!= O_constant
)
8048 as_bad (_("can't handle non absolute segment in `%s'"),
8050 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8058 asection
*seg
= now_seg
;
8059 subsegT subseg
= now_subseg
;
8061 unsigned int alignment
, align_size_1
;
8062 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8063 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8064 unsigned int padding
;
8066 if (!IS_ELF
|| !x86_used_note
)
8069 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8071 /* The .note.gnu.property section layout:
8073 Field Length Contents
8076 n_descsz 4 The note descriptor size
8077 n_type 4 NT_GNU_PROPERTY_TYPE_0
8079 n_desc n_descsz The program property array
8083 /* Create the .note.gnu.property section. */
8084 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8085 bfd_set_section_flags (stdoutput
, sec
,
8092 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8103 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8104 elf_section_type (sec
) = SHT_NOTE
;
8106 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8108 isa_1_descsz_raw
= 4 + 4 + 4;
8109 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8110 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8112 feature_2_descsz_raw
= isa_1_descsz
;
8113 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8115 feature_2_descsz_raw
+= 4 + 4 + 4;
8116 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8117 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8120 descsz
= feature_2_descsz
;
8121 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8122 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8124 /* Write n_namsz. */
8125 md_number_to_chars (p
, (valueT
) 4, 4);
8127 /* Write n_descsz. */
8128 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8131 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8134 memcpy (p
+ 4 * 3, "GNU", 4);
8136 /* Write 4-byte type. */
8137 md_number_to_chars (p
+ 4 * 4,
8138 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8140 /* Write 4-byte data size. */
8141 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8143 /* Write 4-byte data. */
8144 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8146 /* Zero out paddings. */
8147 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8149 memset (p
+ 4 * 7, 0, padding
);
8151 /* Write 4-byte type. */
8152 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8153 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8155 /* Write 4-byte data size. */
8156 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8158 /* Write 4-byte data. */
8159 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8160 (valueT
) x86_feature_2_used
, 4);
8162 /* Zero out paddings. */
8163 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8165 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8167 /* We probably can't restore the current segment, for there likely
8170 subseg_set (seg
, subseg
);
8175 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8176 const char *frag_now_ptr
)
8178 unsigned int len
= 0;
8180 if (start_frag
!= frag_now
)
8182 const fragS
*fr
= start_frag
;
8187 } while (fr
&& fr
!= frag_now
);
8190 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8196 fragS
*insn_start_frag
;
8197 offsetT insn_start_off
;
8199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8200 if (IS_ELF
&& x86_used_note
)
8202 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8203 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8204 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8205 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8206 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8207 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8208 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8209 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8210 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8211 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8212 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8213 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8214 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8215 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8216 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8217 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8218 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8219 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8220 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8221 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8222 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8223 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8224 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8225 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8226 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8227 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8228 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8229 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8230 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8231 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8232 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8233 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8234 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8235 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8236 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8237 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8238 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8239 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8240 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8241 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8242 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8243 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8244 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8245 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8246 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8247 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8248 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8249 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8250 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8251 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8253 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8254 || i
.tm
.cpu_flags
.bitfield
.cpu287
8255 || i
.tm
.cpu_flags
.bitfield
.cpu387
8256 || i
.tm
.cpu_flags
.bitfield
.cpu687
8257 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8258 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8259 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8260 Xfence instructions. */
8261 if (i
.tm
.base_opcode
!= 0xf18
8262 && i
.tm
.base_opcode
!= 0xf0d
8263 && i
.tm
.base_opcode
!= 0xfae
8265 || i
.tm
.cpu_flags
.bitfield
.cpummx
8266 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8267 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8268 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8270 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8272 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8274 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8275 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8276 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8277 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8278 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8279 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8280 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8281 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8282 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8286 /* Tie dwarf2 debug info to the address at the start of the insn.
8287 We can't do this after the insn has been output as the current
8288 frag may have been closed off. eg. by frag_var. */
8289 dwarf2_emit_insn (0);
8291 insn_start_frag
= frag_now
;
8292 insn_start_off
= frag_now_fix ();
8295 if (i
.tm
.opcode_modifier
.jump
)
8297 else if (i
.tm
.opcode_modifier
.jumpbyte
8298 || i
.tm
.opcode_modifier
.jumpdword
)
8300 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8301 output_interseg_jump ();
8304 /* Output normal instructions here. */
8308 unsigned int prefix
;
8311 && i
.tm
.base_opcode
== 0xfae
8313 && i
.imm_operands
== 1
8314 && (i
.op
[0].imms
->X_add_number
== 0xe8
8315 || i
.op
[0].imms
->X_add_number
== 0xf0
8316 || i
.op
[0].imms
->X_add_number
== 0xf8))
8318 /* Encode lfence, mfence, and sfence as
8319 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8320 offsetT val
= 0x240483f0ULL
;
8322 md_number_to_chars (p
, val
, 5);
8326 /* Some processors fail on LOCK prefix. This options makes
8327 assembler ignore LOCK prefix and serves as a workaround. */
8328 if (omit_lock_prefix
)
8330 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8332 i
.prefix
[LOCK_PREFIX
] = 0;
8335 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8336 don't need the explicit prefix. */
8337 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8339 switch (i
.tm
.opcode_length
)
8342 if (i
.tm
.base_opcode
& 0xff000000)
8344 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8345 add_prefix (prefix
);
8349 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8351 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8352 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8353 || prefix
!= REPE_PREFIX_OPCODE
8354 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8355 add_prefix (prefix
);
8361 /* Check for pseudo prefixes. */
8362 as_bad_where (insn_start_frag
->fr_file
,
8363 insn_start_frag
->fr_line
,
8364 _("pseudo prefix without instruction"));
8370 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8371 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8372 R_X86_64_GOTTPOFF relocation so that linker can safely
8373 perform IE->LE optimization. */
8374 if (x86_elf_abi
== X86_64_X32_ABI
8376 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8377 && i
.prefix
[REX_PREFIX
] == 0)
8378 add_prefix (REX_OPCODE
);
8381 /* The prefix bytes. */
8382 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8384 FRAG_APPEND_1_CHAR (*q
);
8388 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8393 /* REX byte is encoded in VEX prefix. */
8397 FRAG_APPEND_1_CHAR (*q
);
8400 /* There should be no other prefixes for instructions
8405 /* For EVEX instructions i.vrex should become 0 after
8406 build_evex_prefix. For VEX instructions upper 16 registers
8407 aren't available, so VREX should be 0. */
8410 /* Now the VEX prefix. */
8411 p
= frag_more (i
.vex
.length
);
8412 for (j
= 0; j
< i
.vex
.length
; j
++)
8413 p
[j
] = i
.vex
.bytes
[j
];
8416 /* Now the opcode; be careful about word order here! */
8417 if (i
.tm
.opcode_length
== 1)
8419 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8423 switch (i
.tm
.opcode_length
)
8427 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8428 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8432 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8442 /* Put out high byte first: can't use md_number_to_chars! */
8443 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8444 *p
= i
.tm
.base_opcode
& 0xff;
8447 /* Now the modrm byte and sib byte (if present). */
8448 if (i
.tm
.opcode_modifier
.modrm
)
8450 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8453 /* If i.rm.regmem == ESP (4)
8454 && i.rm.mode != (Register mode)
8456 ==> need second modrm byte. */
8457 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8459 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8460 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8462 | i
.sib
.scale
<< 6));
8465 if (i
.disp_operands
)
8466 output_disp (insn_start_frag
, insn_start_off
);
8469 output_imm (insn_start_frag
, insn_start_off
);
8472 * frag_now_fix () returning plain abs_section_offset when we're in the
8473 * absolute section, and abs_section_offset not getting updated as data
8474 * gets added to the frag breaks the logic below.
8476 if (now_seg
!= absolute_section
)
8478 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8480 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8488 pi ("" /*line*/, &i
);
8490 #endif /* DEBUG386 */
8493 /* Return the size of the displacement operand N. */
8496 disp_size (unsigned int n
)
8500 if (i
.types
[n
].bitfield
.disp64
)
8502 else if (i
.types
[n
].bitfield
.disp8
)
8504 else if (i
.types
[n
].bitfield
.disp16
)
8509 /* Return the size of the immediate operand N. */
8512 imm_size (unsigned int n
)
8515 if (i
.types
[n
].bitfield
.imm64
)
8517 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8519 else if (i
.types
[n
].bitfield
.imm16
)
8525 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8530 for (n
= 0; n
< i
.operands
; n
++)
8532 if (operand_type_check (i
.types
[n
], disp
))
8534 if (i
.op
[n
].disps
->X_op
== O_constant
)
8536 int size
= disp_size (n
);
8537 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8539 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8541 p
= frag_more (size
);
8542 md_number_to_chars (p
, val
, size
);
8546 enum bfd_reloc_code_real reloc_type
;
8547 int size
= disp_size (n
);
8548 int sign
= i
.types
[n
].bitfield
.disp32s
;
8549 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8552 /* We can't have 8 bit displacement here. */
8553 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8555 /* The PC relative address is computed relative
8556 to the instruction boundary, so in case immediate
8557 fields follows, we need to adjust the value. */
8558 if (pcrel
&& i
.imm_operands
)
8563 for (n1
= 0; n1
< i
.operands
; n1
++)
8564 if (operand_type_check (i
.types
[n1
], imm
))
8566 /* Only one immediate is allowed for PC
8567 relative address. */
8568 gas_assert (sz
== 0);
8570 i
.op
[n
].disps
->X_add_number
-= sz
;
8572 /* We should find the immediate. */
8573 gas_assert (sz
!= 0);
8576 p
= frag_more (size
);
8577 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8579 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8580 && (((reloc_type
== BFD_RELOC_32
8581 || reloc_type
== BFD_RELOC_X86_64_32S
8582 || (reloc_type
== BFD_RELOC_64
8584 && (i
.op
[n
].disps
->X_op
== O_symbol
8585 || (i
.op
[n
].disps
->X_op
== O_add
8586 && ((symbol_get_value_expression
8587 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8589 || reloc_type
== BFD_RELOC_32_PCREL
))
8593 reloc_type
= BFD_RELOC_386_GOTPC
;
8594 i
.op
[n
].imms
->X_add_number
+=
8595 encoding_length (insn_start_frag
, insn_start_off
, p
);
8597 else if (reloc_type
== BFD_RELOC_64
)
8598 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8600 /* Don't do the adjustment for x86-64, as there
8601 the pcrel addressing is relative to the _next_
8602 insn, and that is taken care of in other code. */
8603 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8605 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8606 size
, i
.op
[n
].disps
, pcrel
,
8608 /* Check for "call/jmp *mem", "mov mem, %reg",
8609 "test %reg, mem" and "binop mem, %reg" where binop
8610 is one of adc, add, and, cmp, or, sbb, sub, xor
8611 instructions without data prefix. Always generate
8612 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8613 if (i
.prefix
[DATA_PREFIX
] == 0
8614 && (generate_relax_relocations
8617 && i
.rm
.regmem
== 5))
8619 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8620 && ((i
.operands
== 1
8621 && i
.tm
.base_opcode
== 0xff
8622 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8624 && (i
.tm
.base_opcode
== 0x8b
8625 || i
.tm
.base_opcode
== 0x85
8626 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8630 fixP
->fx_tcbit
= i
.rex
!= 0;
8632 && (i
.base_reg
->reg_num
== RegIP
))
8633 fixP
->fx_tcbit2
= 1;
8636 fixP
->fx_tcbit2
= 1;
8644 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8649 for (n
= 0; n
< i
.operands
; n
++)
8651 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8652 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8655 if (operand_type_check (i
.types
[n
], imm
))
8657 if (i
.op
[n
].imms
->X_op
== O_constant
)
8659 int size
= imm_size (n
);
8662 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8664 p
= frag_more (size
);
8665 md_number_to_chars (p
, val
, size
);
8669 /* Not absolute_section.
8670 Need a 32-bit fixup (don't support 8bit
8671 non-absolute imms). Try to support other
8673 enum bfd_reloc_code_real reloc_type
;
8674 int size
= imm_size (n
);
8677 if (i
.types
[n
].bitfield
.imm32s
8678 && (i
.suffix
== QWORD_MNEM_SUFFIX
8679 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8684 p
= frag_more (size
);
8685 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8687 /* This is tough to explain. We end up with this one if we
8688 * have operands that look like
8689 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8690 * obtain the absolute address of the GOT, and it is strongly
8691 * preferable from a performance point of view to avoid using
8692 * a runtime relocation for this. The actual sequence of
8693 * instructions often look something like:
8698 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8700 * The call and pop essentially return the absolute address
8701 * of the label .L66 and store it in %ebx. The linker itself
8702 * will ultimately change the first operand of the addl so
8703 * that %ebx points to the GOT, but to keep things simple, the
8704 * .o file must have this operand set so that it generates not
8705 * the absolute address of .L66, but the absolute address of
8706 * itself. This allows the linker itself simply treat a GOTPC
8707 * relocation as asking for a pcrel offset to the GOT to be
8708 * added in, and the addend of the relocation is stored in the
8709 * operand field for the instruction itself.
8711 * Our job here is to fix the operand so that it would add
8712 * the correct offset so that %ebx would point to itself. The
8713 * thing that is tricky is that .-.L66 will point to the
8714 * beginning of the instruction, so we need to further modify
8715 * the operand so that it will point to itself. There are
8716 * other cases where you have something like:
8718 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8720 * and here no correction would be required. Internally in
8721 * the assembler we treat operands of this form as not being
8722 * pcrel since the '.' is explicitly mentioned, and I wonder
8723 * whether it would simplify matters to do it this way. Who
8724 * knows. In earlier versions of the PIC patches, the
8725 * pcrel_adjust field was used to store the correction, but
8726 * since the expression is not pcrel, I felt it would be
8727 * confusing to do it this way. */
8729 if ((reloc_type
== BFD_RELOC_32
8730 || reloc_type
== BFD_RELOC_X86_64_32S
8731 || reloc_type
== BFD_RELOC_64
)
8733 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8734 && (i
.op
[n
].imms
->X_op
== O_symbol
8735 || (i
.op
[n
].imms
->X_op
== O_add
8736 && ((symbol_get_value_expression
8737 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8741 reloc_type
= BFD_RELOC_386_GOTPC
;
8743 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8745 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8746 i
.op
[n
].imms
->X_add_number
+=
8747 encoding_length (insn_start_frag
, insn_start_off
, p
);
8749 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8750 i
.op
[n
].imms
, 0, reloc_type
);
8756 /* x86_cons_fix_new is called via the expression parsing code when a
8757 reloc is needed. We use this hook to get the correct .got reloc. */
8758 static int cons_sign
= -1;
8761 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8762 expressionS
*exp
, bfd_reloc_code_real_type r
)
8764 r
= reloc (len
, 0, cons_sign
, r
);
8767 if (exp
->X_op
== O_secrel
)
8769 exp
->X_op
= O_symbol
;
8770 r
= BFD_RELOC_32_SECREL
;
8774 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8777 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8778 purpose of the `.dc.a' internal pseudo-op. */
8781 x86_address_bytes (void)
8783 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8785 return stdoutput
->arch_info
->bits_per_address
/ 8;
8788 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8790 # define lex_got(reloc, adjust, types) NULL
8792 /* Parse operands of the form
8793 <symbol>@GOTOFF+<nnn>
8794 and similar .plt or .got references.
8796 If we find one, set up the correct relocation in RELOC and copy the
8797 input string, minus the `@GOTOFF' into a malloc'd buffer for
8798 parsing by the calling routine. Return this buffer, and if ADJUST
8799 is non-null set it to the length of the string we removed from the
8800 input line. Otherwise return NULL. */
8802 lex_got (enum bfd_reloc_code_real
*rel
,
8804 i386_operand_type
*types
)
8806 /* Some of the relocations depend on the size of what field is to
8807 be relocated. But in our callers i386_immediate and i386_displacement
8808 we don't yet know the operand size (this will be set by insn
8809 matching). Hence we record the word32 relocation here,
8810 and adjust the reloc according to the real size in reloc(). */
8811 static const struct {
8814 const enum bfd_reloc_code_real rel
[2];
8815 const i386_operand_type types64
;
8817 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8818 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8820 OPERAND_TYPE_IMM32_64
},
8822 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8823 BFD_RELOC_X86_64_PLTOFF64
},
8824 OPERAND_TYPE_IMM64
},
8825 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8826 BFD_RELOC_X86_64_PLT32
},
8827 OPERAND_TYPE_IMM32_32S_DISP32
},
8828 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8829 BFD_RELOC_X86_64_GOTPLT64
},
8830 OPERAND_TYPE_IMM64_DISP64
},
8831 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8832 BFD_RELOC_X86_64_GOTOFF64
},
8833 OPERAND_TYPE_IMM64_DISP64
},
8834 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8835 BFD_RELOC_X86_64_GOTPCREL
},
8836 OPERAND_TYPE_IMM32_32S_DISP32
},
8837 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8838 BFD_RELOC_X86_64_TLSGD
},
8839 OPERAND_TYPE_IMM32_32S_DISP32
},
8840 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8841 _dummy_first_bfd_reloc_code_real
},
8842 OPERAND_TYPE_NONE
},
8843 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8844 BFD_RELOC_X86_64_TLSLD
},
8845 OPERAND_TYPE_IMM32_32S_DISP32
},
8846 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8847 BFD_RELOC_X86_64_GOTTPOFF
},
8848 OPERAND_TYPE_IMM32_32S_DISP32
},
8849 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8850 BFD_RELOC_X86_64_TPOFF32
},
8851 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8852 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8853 _dummy_first_bfd_reloc_code_real
},
8854 OPERAND_TYPE_NONE
},
8855 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8856 BFD_RELOC_X86_64_DTPOFF32
},
8857 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8858 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8859 _dummy_first_bfd_reloc_code_real
},
8860 OPERAND_TYPE_NONE
},
8861 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8862 _dummy_first_bfd_reloc_code_real
},
8863 OPERAND_TYPE_NONE
},
8864 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8865 BFD_RELOC_X86_64_GOT32
},
8866 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8867 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8868 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8869 OPERAND_TYPE_IMM32_32S_DISP32
},
8870 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8871 BFD_RELOC_X86_64_TLSDESC_CALL
},
8872 OPERAND_TYPE_IMM32_32S_DISP32
},
8877 #if defined (OBJ_MAYBE_ELF)
8882 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8883 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8886 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8888 int len
= gotrel
[j
].len
;
8889 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8891 if (gotrel
[j
].rel
[object_64bit
] != 0)
8894 char *tmpbuf
, *past_reloc
;
8896 *rel
= gotrel
[j
].rel
[object_64bit
];
8900 if (flag_code
!= CODE_64BIT
)
8902 types
->bitfield
.imm32
= 1;
8903 types
->bitfield
.disp32
= 1;
8906 *types
= gotrel
[j
].types64
;
8909 if (j
!= 0 && GOT_symbol
== NULL
)
8910 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8912 /* The length of the first part of our input line. */
8913 first
= cp
- input_line_pointer
;
8915 /* The second part goes from after the reloc token until
8916 (and including) an end_of_line char or comma. */
8917 past_reloc
= cp
+ 1 + len
;
8919 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8921 second
= cp
+ 1 - past_reloc
;
8923 /* Allocate and copy string. The trailing NUL shouldn't
8924 be necessary, but be safe. */
8925 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8926 memcpy (tmpbuf
, input_line_pointer
, first
);
8927 if (second
!= 0 && *past_reloc
!= ' ')
8928 /* Replace the relocation token with ' ', so that
8929 errors like foo@GOTOFF1 will be detected. */
8930 tmpbuf
[first
++] = ' ';
8932 /* Increment length by 1 if the relocation token is
8937 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8938 tmpbuf
[first
+ second
] = '\0';
8942 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8943 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8948 /* Might be a symbol version string. Don't as_bad here. */
8957 /* Parse operands of the form
8958 <symbol>@SECREL32+<nnn>
8960 If we find one, set up the correct relocation in RELOC and copy the
8961 input string, minus the `@SECREL32' into a malloc'd buffer for
8962 parsing by the calling routine. Return this buffer, and if ADJUST
8963 is non-null set it to the length of the string we removed from the
8964 input line. Otherwise return NULL.
8966 This function is copied from the ELF version above adjusted for PE targets. */
8969 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8970 int *adjust ATTRIBUTE_UNUSED
,
8971 i386_operand_type
*types
)
8977 const enum bfd_reloc_code_real rel
[2];
8978 const i386_operand_type types64
;
8982 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8983 BFD_RELOC_32_SECREL
},
8984 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8990 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8991 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8994 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8996 int len
= gotrel
[j
].len
;
8998 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9000 if (gotrel
[j
].rel
[object_64bit
] != 0)
9003 char *tmpbuf
, *past_reloc
;
9005 *rel
= gotrel
[j
].rel
[object_64bit
];
9011 if (flag_code
!= CODE_64BIT
)
9013 types
->bitfield
.imm32
= 1;
9014 types
->bitfield
.disp32
= 1;
9017 *types
= gotrel
[j
].types64
;
9020 /* The length of the first part of our input line. */
9021 first
= cp
- input_line_pointer
;
9023 /* The second part goes from after the reloc token until
9024 (and including) an end_of_line char or comma. */
9025 past_reloc
= cp
+ 1 + len
;
9027 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9029 second
= cp
+ 1 - past_reloc
;
9031 /* Allocate and copy string. The trailing NUL shouldn't
9032 be necessary, but be safe. */
9033 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9034 memcpy (tmpbuf
, input_line_pointer
, first
);
9035 if (second
!= 0 && *past_reloc
!= ' ')
9036 /* Replace the relocation token with ' ', so that
9037 errors like foo@SECLREL321 will be detected. */
9038 tmpbuf
[first
++] = ' ';
9039 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9040 tmpbuf
[first
+ second
] = '\0';
9044 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9045 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9050 /* Might be a symbol version string. Don't as_bad here. */
9056 bfd_reloc_code_real_type
9057 x86_cons (expressionS
*exp
, int size
)
9059 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9061 intel_syntax
= -intel_syntax
;
9064 if (size
== 4 || (object_64bit
&& size
== 8))
9066 /* Handle @GOTOFF and the like in an expression. */
9068 char *gotfree_input_line
;
9071 save
= input_line_pointer
;
9072 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9073 if (gotfree_input_line
)
9074 input_line_pointer
= gotfree_input_line
;
9078 if (gotfree_input_line
)
9080 /* expression () has merrily parsed up to the end of line,
9081 or a comma - in the wrong buffer. Transfer how far
9082 input_line_pointer has moved to the right buffer. */
9083 input_line_pointer
= (save
9084 + (input_line_pointer
- gotfree_input_line
)
9086 free (gotfree_input_line
);
9087 if (exp
->X_op
== O_constant
9088 || exp
->X_op
== O_absent
9089 || exp
->X_op
== O_illegal
9090 || exp
->X_op
== O_register
9091 || exp
->X_op
== O_big
)
9093 char c
= *input_line_pointer
;
9094 *input_line_pointer
= 0;
9095 as_bad (_("missing or invalid expression `%s'"), save
);
9096 *input_line_pointer
= c
;
9098 else if ((got_reloc
== BFD_RELOC_386_PLT32
9099 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9100 && exp
->X_op
!= O_symbol
)
9102 char c
= *input_line_pointer
;
9103 *input_line_pointer
= 0;
9104 as_bad (_("invalid PLT expression `%s'"), save
);
9105 *input_line_pointer
= c
;
9112 intel_syntax
= -intel_syntax
;
9115 i386_intel_simplify (exp
);
9121 signed_cons (int size
)
9123 if (flag_code
== CODE_64BIT
)
9131 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9138 if (exp
.X_op
== O_symbol
)
9139 exp
.X_op
= O_secrel
;
9141 emit_expr (&exp
, 4);
9143 while (*input_line_pointer
++ == ',');
9145 input_line_pointer
--;
9146 demand_empty_rest_of_line ();
9150 /* Handle Vector operations. */
9153 check_VecOperations (char *op_string
, char *op_end
)
9155 const reg_entry
*mask
;
9160 && (op_end
== NULL
|| op_string
< op_end
))
9163 if (*op_string
== '{')
9167 /* Check broadcasts. */
9168 if (strncmp (op_string
, "1to", 3) == 0)
9173 goto duplicated_vec_op
;
9176 if (*op_string
== '8')
9178 else if (*op_string
== '4')
9180 else if (*op_string
== '2')
9182 else if (*op_string
== '1'
9183 && *(op_string
+1) == '6')
9190 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9195 broadcast_op
.type
= bcst_type
;
9196 broadcast_op
.operand
= this_operand
;
9197 broadcast_op
.bytes
= 0;
9198 i
.broadcast
= &broadcast_op
;
9200 /* Check masking operation. */
9201 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9203 /* k0 can't be used for write mask. */
9204 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9206 as_bad (_("`%s%s' can't be used for write mask"),
9207 register_prefix
, mask
->reg_name
);
9213 mask_op
.mask
= mask
;
9214 mask_op
.zeroing
= 0;
9215 mask_op
.operand
= this_operand
;
9221 goto duplicated_vec_op
;
9223 i
.mask
->mask
= mask
;
9225 /* Only "{z}" is allowed here. No need to check
9226 zeroing mask explicitly. */
9227 if (i
.mask
->operand
!= this_operand
)
9229 as_bad (_("invalid write mask `%s'"), saved
);
9236 /* Check zeroing-flag for masking operation. */
9237 else if (*op_string
== 'z')
9241 mask_op
.mask
= NULL
;
9242 mask_op
.zeroing
= 1;
9243 mask_op
.operand
= this_operand
;
9248 if (i
.mask
->zeroing
)
9251 as_bad (_("duplicated `%s'"), saved
);
9255 i
.mask
->zeroing
= 1;
9257 /* Only "{%k}" is allowed here. No need to check mask
9258 register explicitly. */
9259 if (i
.mask
->operand
!= this_operand
)
9261 as_bad (_("invalid zeroing-masking `%s'"),
9270 goto unknown_vec_op
;
9272 if (*op_string
!= '}')
9274 as_bad (_("missing `}' in `%s'"), saved
);
9279 /* Strip whitespace since the addition of pseudo prefixes
9280 changed how the scrubber treats '{'. */
9281 if (is_space_char (*op_string
))
9287 /* We don't know this one. */
9288 as_bad (_("unknown vector operation: `%s'"), saved
);
9292 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9294 as_bad (_("zeroing-masking only allowed with write mask"));
9302 i386_immediate (char *imm_start
)
9304 char *save_input_line_pointer
;
9305 char *gotfree_input_line
;
9308 i386_operand_type types
;
9310 operand_type_set (&types
, ~0);
9312 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9314 as_bad (_("at most %d immediate operands are allowed"),
9315 MAX_IMMEDIATE_OPERANDS
);
9319 exp
= &im_expressions
[i
.imm_operands
++];
9320 i
.op
[this_operand
].imms
= exp
;
9322 if (is_space_char (*imm_start
))
9325 save_input_line_pointer
= input_line_pointer
;
9326 input_line_pointer
= imm_start
;
9328 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9329 if (gotfree_input_line
)
9330 input_line_pointer
= gotfree_input_line
;
9332 exp_seg
= expression (exp
);
9336 /* Handle vector operations. */
9337 if (*input_line_pointer
== '{')
9339 input_line_pointer
= check_VecOperations (input_line_pointer
,
9341 if (input_line_pointer
== NULL
)
9345 if (*input_line_pointer
)
9346 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9348 input_line_pointer
= save_input_line_pointer
;
9349 if (gotfree_input_line
)
9351 free (gotfree_input_line
);
9353 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9354 exp
->X_op
= O_illegal
;
9357 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9361 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9362 i386_operand_type types
, const char *imm_start
)
9364 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9367 as_bad (_("missing or invalid immediate expression `%s'"),
9371 else if (exp
->X_op
== O_constant
)
9373 /* Size it properly later. */
9374 i
.types
[this_operand
].bitfield
.imm64
= 1;
9375 /* If not 64bit, sign extend val. */
9376 if (flag_code
!= CODE_64BIT
9377 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9379 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9381 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9382 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9383 && exp_seg
!= absolute_section
9384 && exp_seg
!= text_section
9385 && exp_seg
!= data_section
9386 && exp_seg
!= bss_section
9387 && exp_seg
!= undefined_section
9388 && !bfd_is_com_section (exp_seg
))
9390 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9394 else if (!intel_syntax
&& exp_seg
== reg_section
)
9397 as_bad (_("illegal immediate register operand %s"), imm_start
);
9402 /* This is an address. The size of the address will be
9403 determined later, depending on destination register,
9404 suffix, or the default for the section. */
9405 i
.types
[this_operand
].bitfield
.imm8
= 1;
9406 i
.types
[this_operand
].bitfield
.imm16
= 1;
9407 i
.types
[this_operand
].bitfield
.imm32
= 1;
9408 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9409 i
.types
[this_operand
].bitfield
.imm64
= 1;
9410 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9418 i386_scale (char *scale
)
9421 char *save
= input_line_pointer
;
9423 input_line_pointer
= scale
;
9424 val
= get_absolute_expression ();
9429 i
.log2_scale_factor
= 0;
9432 i
.log2_scale_factor
= 1;
9435 i
.log2_scale_factor
= 2;
9438 i
.log2_scale_factor
= 3;
9442 char sep
= *input_line_pointer
;
9444 *input_line_pointer
= '\0';
9445 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9447 *input_line_pointer
= sep
;
9448 input_line_pointer
= save
;
9452 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9454 as_warn (_("scale factor of %d without an index register"),
9455 1 << i
.log2_scale_factor
);
9456 i
.log2_scale_factor
= 0;
9458 scale
= input_line_pointer
;
9459 input_line_pointer
= save
;
9464 i386_displacement (char *disp_start
, char *disp_end
)
9468 char *save_input_line_pointer
;
9469 char *gotfree_input_line
;
9471 i386_operand_type bigdisp
, types
= anydisp
;
9474 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9476 as_bad (_("at most %d displacement operands are allowed"),
9477 MAX_MEMORY_OPERANDS
);
9481 operand_type_set (&bigdisp
, 0);
9482 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9483 || (!current_templates
->start
->opcode_modifier
.jump
9484 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9486 bigdisp
.bitfield
.disp32
= 1;
9487 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9488 if (flag_code
== CODE_64BIT
)
9492 bigdisp
.bitfield
.disp32s
= 1;
9493 bigdisp
.bitfield
.disp64
= 1;
9496 else if ((flag_code
== CODE_16BIT
) ^ override
)
9498 bigdisp
.bitfield
.disp32
= 0;
9499 bigdisp
.bitfield
.disp16
= 1;
9504 /* For PC-relative branches, the width of the displacement
9505 is dependent upon data size, not address size. */
9506 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9507 if (flag_code
== CODE_64BIT
)
9509 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9510 bigdisp
.bitfield
.disp16
= 1;
9513 bigdisp
.bitfield
.disp32
= 1;
9514 bigdisp
.bitfield
.disp32s
= 1;
9520 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9522 : LONG_MNEM_SUFFIX
));
9523 bigdisp
.bitfield
.disp32
= 1;
9524 if ((flag_code
== CODE_16BIT
) ^ override
)
9526 bigdisp
.bitfield
.disp32
= 0;
9527 bigdisp
.bitfield
.disp16
= 1;
9531 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9534 exp
= &disp_expressions
[i
.disp_operands
];
9535 i
.op
[this_operand
].disps
= exp
;
9537 save_input_line_pointer
= input_line_pointer
;
9538 input_line_pointer
= disp_start
;
9539 END_STRING_AND_SAVE (disp_end
);
9541 #ifndef GCC_ASM_O_HACK
9542 #define GCC_ASM_O_HACK 0
9545 END_STRING_AND_SAVE (disp_end
+ 1);
9546 if (i
.types
[this_operand
].bitfield
.baseIndex
9547 && displacement_string_end
[-1] == '+')
9549 /* This hack is to avoid a warning when using the "o"
9550 constraint within gcc asm statements.
9553 #define _set_tssldt_desc(n,addr,limit,type) \
9554 __asm__ __volatile__ ( \
9556 "movw %w1,2+%0\n\t" \
9558 "movb %b1,4+%0\n\t" \
9559 "movb %4,5+%0\n\t" \
9560 "movb $0,6+%0\n\t" \
9561 "movb %h1,7+%0\n\t" \
9563 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9565 This works great except that the output assembler ends
9566 up looking a bit weird if it turns out that there is
9567 no offset. You end up producing code that looks like:
9580 So here we provide the missing zero. */
9582 *displacement_string_end
= '0';
9585 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9586 if (gotfree_input_line
)
9587 input_line_pointer
= gotfree_input_line
;
9589 exp_seg
= expression (exp
);
9592 if (*input_line_pointer
)
9593 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9595 RESTORE_END_STRING (disp_end
+ 1);
9597 input_line_pointer
= save_input_line_pointer
;
9598 if (gotfree_input_line
)
9600 free (gotfree_input_line
);
9602 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9603 exp
->X_op
= O_illegal
;
9606 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9608 RESTORE_END_STRING (disp_end
);
9614 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9615 i386_operand_type types
, const char *disp_start
)
9617 i386_operand_type bigdisp
;
9620 /* We do this to make sure that the section symbol is in
9621 the symbol table. We will ultimately change the relocation
9622 to be relative to the beginning of the section. */
9623 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9624 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9625 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9627 if (exp
->X_op
!= O_symbol
)
9630 if (S_IS_LOCAL (exp
->X_add_symbol
)
9631 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9632 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9633 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9634 exp
->X_op
= O_subtract
;
9635 exp
->X_op_symbol
= GOT_symbol
;
9636 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9637 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9638 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9639 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9641 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9644 else if (exp
->X_op
== O_absent
9645 || exp
->X_op
== O_illegal
9646 || exp
->X_op
== O_big
)
9649 as_bad (_("missing or invalid displacement expression `%s'"),
9654 else if (flag_code
== CODE_64BIT
9655 && !i
.prefix
[ADDR_PREFIX
]
9656 && exp
->X_op
== O_constant
)
9658 /* Since displacement is signed extended to 64bit, don't allow
9659 disp32 and turn off disp32s if they are out of range. */
9660 i
.types
[this_operand
].bitfield
.disp32
= 0;
9661 if (!fits_in_signed_long (exp
->X_add_number
))
9663 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9664 if (i
.types
[this_operand
].bitfield
.baseindex
)
9666 as_bad (_("0x%lx out range of signed 32bit displacement"),
9667 (long) exp
->X_add_number
);
9673 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9674 else if (exp
->X_op
!= O_constant
9675 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9676 && exp_seg
!= absolute_section
9677 && exp_seg
!= text_section
9678 && exp_seg
!= data_section
9679 && exp_seg
!= bss_section
9680 && exp_seg
!= undefined_section
9681 && !bfd_is_com_section (exp_seg
))
9683 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9688 /* Check if this is a displacement only operand. */
9689 bigdisp
= i
.types
[this_operand
];
9690 bigdisp
.bitfield
.disp8
= 0;
9691 bigdisp
.bitfield
.disp16
= 0;
9692 bigdisp
.bitfield
.disp32
= 0;
9693 bigdisp
.bitfield
.disp32s
= 0;
9694 bigdisp
.bitfield
.disp64
= 0;
9695 if (operand_type_all_zero (&bigdisp
))
9696 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9702 /* Return the active addressing mode, taking address override and
9703 registers forming the address into consideration. Update the
9704 address override prefix if necessary. */
9706 static enum flag_code
9707 i386_addressing_mode (void)
9709 enum flag_code addr_mode
;
9711 if (i
.prefix
[ADDR_PREFIX
])
9712 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9715 addr_mode
= flag_code
;
9717 #if INFER_ADDR_PREFIX
9718 if (i
.mem_operands
== 0)
9720 /* Infer address prefix from the first memory operand. */
9721 const reg_entry
*addr_reg
= i
.base_reg
;
9723 if (addr_reg
== NULL
)
9724 addr_reg
= i
.index_reg
;
9728 if (addr_reg
->reg_type
.bitfield
.dword
)
9729 addr_mode
= CODE_32BIT
;
9730 else if (flag_code
!= CODE_64BIT
9731 && addr_reg
->reg_type
.bitfield
.word
)
9732 addr_mode
= CODE_16BIT
;
9734 if (addr_mode
!= flag_code
)
9736 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9738 /* Change the size of any displacement too. At most one
9739 of Disp16 or Disp32 is set.
9740 FIXME. There doesn't seem to be any real need for
9741 separate Disp16 and Disp32 flags. The same goes for
9742 Imm16 and Imm32. Removing them would probably clean
9743 up the code quite a lot. */
9744 if (flag_code
!= CODE_64BIT
9745 && (i
.types
[this_operand
].bitfield
.disp16
9746 || i
.types
[this_operand
].bitfield
.disp32
))
9747 i
.types
[this_operand
]
9748 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9758 /* Make sure the memory operand we've been dealt is valid.
9759 Return 1 on success, 0 on a failure. */
9762 i386_index_check (const char *operand_string
)
9764 const char *kind
= "base/index";
9765 enum flag_code addr_mode
= i386_addressing_mode ();
9767 if (current_templates
->start
->opcode_modifier
.isstring
9768 && !current_templates
->start
->opcode_modifier
.immext
9769 && (current_templates
->end
[-1].opcode_modifier
.isstring
9772 /* Memory operands of string insns are special in that they only allow
9773 a single register (rDI, rSI, or rBX) as their memory address. */
9774 const reg_entry
*expected_reg
;
9775 static const char *di_si
[][2] =
9781 static const char *bx
[] = { "ebx", "bx", "rbx" };
9783 kind
= "string address";
9785 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9787 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9789 if (!type
.bitfield
.baseindex
9790 || ((!i
.mem_operands
!= !intel_syntax
)
9791 && current_templates
->end
[-1].operand_types
[1]
9792 .bitfield
.baseindex
))
9793 type
= current_templates
->end
[-1].operand_types
[1];
9794 expected_reg
= hash_find (reg_hash
,
9795 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9799 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9801 if (i
.base_reg
!= expected_reg
9803 || operand_type_check (i
.types
[this_operand
], disp
))
9805 /* The second memory operand must have the same size as
9809 && !((addr_mode
== CODE_64BIT
9810 && i
.base_reg
->reg_type
.bitfield
.qword
)
9811 || (addr_mode
== CODE_32BIT
9812 ? i
.base_reg
->reg_type
.bitfield
.dword
9813 : i
.base_reg
->reg_type
.bitfield
.word
)))
9816 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9818 intel_syntax
? '[' : '(',
9820 expected_reg
->reg_name
,
9821 intel_syntax
? ']' : ')');
9828 as_bad (_("`%s' is not a valid %s expression"),
9829 operand_string
, kind
);
9834 if (addr_mode
!= CODE_16BIT
)
9836 /* 32-bit/64-bit checks. */
9838 && ((addr_mode
== CODE_64BIT
9839 ? !i
.base_reg
->reg_type
.bitfield
.qword
9840 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9841 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9842 || i
.base_reg
->reg_num
== RegIZ
))
9844 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9845 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9846 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9847 && ((addr_mode
== CODE_64BIT
9848 ? !i
.index_reg
->reg_type
.bitfield
.qword
9849 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9850 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9853 /* bndmk, bndldx, and bndstx have special restrictions. */
9854 if (current_templates
->start
->base_opcode
== 0xf30f1b
9855 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9857 /* They cannot use RIP-relative addressing. */
9858 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9860 as_bad (_("`%s' cannot be used here"), operand_string
);
9864 /* bndldx and bndstx ignore their scale factor. */
9865 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9866 && i
.log2_scale_factor
)
9867 as_warn (_("register scaling is being ignored here"));
9872 /* 16-bit checks. */
9874 && (!i
.base_reg
->reg_type
.bitfield
.word
9875 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9877 && (!i
.index_reg
->reg_type
.bitfield
.word
9878 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9880 && i
.base_reg
->reg_num
< 6
9881 && i
.index_reg
->reg_num
>= 6
9882 && i
.log2_scale_factor
== 0))))
9889 /* Handle vector immediates. */
9892 RC_SAE_immediate (const char *imm_start
)
9894 unsigned int match_found
, j
;
9895 const char *pstr
= imm_start
;
9903 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9905 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9909 rc_op
.type
= RC_NamesTable
[j
].type
;
9910 rc_op
.operand
= this_operand
;
9911 i
.rounding
= &rc_op
;
9915 as_bad (_("duplicated `%s'"), imm_start
);
9918 pstr
+= RC_NamesTable
[j
].len
;
9928 as_bad (_("Missing '}': '%s'"), imm_start
);
9931 /* RC/SAE immediate string should contain nothing more. */;
9934 as_bad (_("Junk after '}': '%s'"), imm_start
);
9938 exp
= &im_expressions
[i
.imm_operands
++];
9939 i
.op
[this_operand
].imms
= exp
;
9941 exp
->X_op
= O_constant
;
9942 exp
->X_add_number
= 0;
9943 exp
->X_add_symbol
= (symbolS
*) 0;
9944 exp
->X_op_symbol
= (symbolS
*) 0;
9946 i
.types
[this_operand
].bitfield
.imm8
= 1;
9950 /* Only string instructions can have a second memory operand, so
9951 reduce current_templates to just those if it contains any. */
9953 maybe_adjust_templates (void)
9955 const insn_template
*t
;
9957 gas_assert (i
.mem_operands
== 1);
9959 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9960 if (t
->opcode_modifier
.isstring
)
9963 if (t
< current_templates
->end
)
9965 static templates aux_templates
;
9966 bfd_boolean recheck
;
9968 aux_templates
.start
= t
;
9969 for (; t
< current_templates
->end
; ++t
)
9970 if (!t
->opcode_modifier
.isstring
)
9972 aux_templates
.end
= t
;
9974 /* Determine whether to re-check the first memory operand. */
9975 recheck
= (aux_templates
.start
!= current_templates
->start
9976 || t
!= current_templates
->end
);
9978 current_templates
= &aux_templates
;
9983 if (i
.memop1_string
!= NULL
9984 && i386_index_check (i
.memop1_string
) == 0)
9993 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9997 i386_att_operand (char *operand_string
)
10001 char *op_string
= operand_string
;
10003 if (is_space_char (*op_string
))
10006 /* We check for an absolute prefix (differentiating,
10007 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10008 if (*op_string
== ABSOLUTE_PREFIX
)
10011 if (is_space_char (*op_string
))
10013 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10016 /* Check if operand is a register. */
10017 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10019 i386_operand_type temp
;
10021 /* Check for a segment override by searching for ':' after a
10022 segment register. */
10023 op_string
= end_op
;
10024 if (is_space_char (*op_string
))
10026 if (*op_string
== ':'
10027 && (r
->reg_type
.bitfield
.sreg2
10028 || r
->reg_type
.bitfield
.sreg3
))
10030 switch (r
->reg_num
)
10033 i
.seg
[i
.mem_operands
] = &es
;
10036 i
.seg
[i
.mem_operands
] = &cs
;
10039 i
.seg
[i
.mem_operands
] = &ss
;
10042 i
.seg
[i
.mem_operands
] = &ds
;
10045 i
.seg
[i
.mem_operands
] = &fs
;
10048 i
.seg
[i
.mem_operands
] = &gs
;
10052 /* Skip the ':' and whitespace. */
10054 if (is_space_char (*op_string
))
10057 if (!is_digit_char (*op_string
)
10058 && !is_identifier_char (*op_string
)
10059 && *op_string
!= '('
10060 && *op_string
!= ABSOLUTE_PREFIX
)
10062 as_bad (_("bad memory operand `%s'"), op_string
);
10065 /* Handle case of %es:*foo. */
10066 if (*op_string
== ABSOLUTE_PREFIX
)
10069 if (is_space_char (*op_string
))
10071 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10073 goto do_memory_reference
;
10076 /* Handle vector operations. */
10077 if (*op_string
== '{')
10079 op_string
= check_VecOperations (op_string
, NULL
);
10080 if (op_string
== NULL
)
10086 as_bad (_("junk `%s' after register"), op_string
);
10089 temp
= r
->reg_type
;
10090 temp
.bitfield
.baseindex
= 0;
10091 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10093 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10094 i
.op
[this_operand
].regs
= r
;
10097 else if (*op_string
== REGISTER_PREFIX
)
10099 as_bad (_("bad register name `%s'"), op_string
);
10102 else if (*op_string
== IMMEDIATE_PREFIX
)
10105 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10107 as_bad (_("immediate operand illegal with absolute jump"));
10110 if (!i386_immediate (op_string
))
10113 else if (RC_SAE_immediate (operand_string
))
10115 /* If it is a RC or SAE immediate, do nothing. */
10118 else if (is_digit_char (*op_string
)
10119 || is_identifier_char (*op_string
)
10120 || *op_string
== '"'
10121 || *op_string
== '(')
10123 /* This is a memory reference of some sort. */
10126 /* Start and end of displacement string expression (if found). */
10127 char *displacement_string_start
;
10128 char *displacement_string_end
;
10131 do_memory_reference
:
10132 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10134 if ((i
.mem_operands
== 1
10135 && !current_templates
->start
->opcode_modifier
.isstring
)
10136 || i
.mem_operands
== 2)
10138 as_bad (_("too many memory references for `%s'"),
10139 current_templates
->start
->name
);
10143 /* Check for base index form. We detect the base index form by
10144 looking for an ')' at the end of the operand, searching
10145 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10147 base_string
= op_string
+ strlen (op_string
);
10149 /* Handle vector operations. */
10150 vop_start
= strchr (op_string
, '{');
10151 if (vop_start
&& vop_start
< base_string
)
10153 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10155 base_string
= vop_start
;
10159 if (is_space_char (*base_string
))
10162 /* If we only have a displacement, set-up for it to be parsed later. */
10163 displacement_string_start
= op_string
;
10164 displacement_string_end
= base_string
+ 1;
10166 if (*base_string
== ')')
10169 unsigned int parens_balanced
= 1;
10170 /* We've already checked that the number of left & right ()'s are
10171 equal, so this loop will not be infinite. */
10175 if (*base_string
== ')')
10177 if (*base_string
== '(')
10180 while (parens_balanced
);
10182 temp_string
= base_string
;
10184 /* Skip past '(' and whitespace. */
10186 if (is_space_char (*base_string
))
10189 if (*base_string
== ','
10190 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10193 displacement_string_end
= temp_string
;
10195 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10199 base_string
= end_op
;
10200 if (is_space_char (*base_string
))
10204 /* There may be an index reg or scale factor here. */
10205 if (*base_string
== ',')
10208 if (is_space_char (*base_string
))
10211 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10214 base_string
= end_op
;
10215 if (is_space_char (*base_string
))
10217 if (*base_string
== ',')
10220 if (is_space_char (*base_string
))
10223 else if (*base_string
!= ')')
10225 as_bad (_("expecting `,' or `)' "
10226 "after index register in `%s'"),
10231 else if (*base_string
== REGISTER_PREFIX
)
10233 end_op
= strchr (base_string
, ',');
10236 as_bad (_("bad register name `%s'"), base_string
);
10240 /* Check for scale factor. */
10241 if (*base_string
!= ')')
10243 char *end_scale
= i386_scale (base_string
);
10248 base_string
= end_scale
;
10249 if (is_space_char (*base_string
))
10251 if (*base_string
!= ')')
10253 as_bad (_("expecting `)' "
10254 "after scale factor in `%s'"),
10259 else if (!i
.index_reg
)
10261 as_bad (_("expecting index register or scale factor "
10262 "after `,'; got '%c'"),
10267 else if (*base_string
!= ')')
10269 as_bad (_("expecting `,' or `)' "
10270 "after base register in `%s'"),
10275 else if (*base_string
== REGISTER_PREFIX
)
10277 end_op
= strchr (base_string
, ',');
10280 as_bad (_("bad register name `%s'"), base_string
);
10285 /* If there's an expression beginning the operand, parse it,
10286 assuming displacement_string_start and
10287 displacement_string_end are meaningful. */
10288 if (displacement_string_start
!= displacement_string_end
)
10290 if (!i386_displacement (displacement_string_start
,
10291 displacement_string_end
))
10295 /* Special case for (%dx) while doing input/output op. */
10297 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10298 && i
.index_reg
== 0
10299 && i
.log2_scale_factor
== 0
10300 && i
.seg
[i
.mem_operands
] == 0
10301 && !operand_type_check (i
.types
[this_operand
], disp
))
10303 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10307 if (i386_index_check (operand_string
) == 0)
10309 i
.flags
[this_operand
] |= Operand_Mem
;
10310 if (i
.mem_operands
== 0)
10311 i
.memop1_string
= xstrdup (operand_string
);
10316 /* It's not a memory operand; argh! */
10317 as_bad (_("invalid char %s beginning operand %d `%s'"),
10318 output_invalid (*op_string
),
10323 return 1; /* Normal return. */
10326 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10327 that an rs_machine_dependent frag may reach. */
10330 i386_frag_max_var (fragS
*frag
)
10332 /* The only relaxable frags are for jumps.
10333 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10334 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10335 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10338 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10340 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10342 /* STT_GNU_IFUNC symbol must go through PLT. */
10343 if ((symbol_get_bfdsym (fr_symbol
)->flags
10344 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10347 if (!S_IS_EXTERNAL (fr_symbol
))
10348 /* Symbol may be weak or local. */
10349 return !S_IS_WEAK (fr_symbol
);
10351 /* Global symbols with non-default visibility can't be preempted. */
10352 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10355 if (fr_var
!= NO_RELOC
)
10356 switch ((enum bfd_reloc_code_real
) fr_var
)
10358 case BFD_RELOC_386_PLT32
:
10359 case BFD_RELOC_X86_64_PLT32
:
10360 /* Symbol with PLT relocation may be preempted. */
10366 /* Global symbols with default visibility in a shared library may be
10367 preempted by another definition. */
10372 /* md_estimate_size_before_relax()
10374 Called just before relax() for rs_machine_dependent frags. The x86
10375 assembler uses these frags to handle variable size jump
10378 Any symbol that is now undefined will not become defined.
10379 Return the correct fr_subtype in the frag.
10380 Return the initial "guess for variable size of frag" to caller.
10381 The guess is actually the growth beyond the fixed part. Whatever
10382 we do to grow the fixed or variable part contributes to our
10386 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10388 /* We've already got fragP->fr_subtype right; all we have to do is
10389 check for un-relaxable symbols. On an ELF system, we can't relax
10390 an externally visible symbol, because it may be overridden by a
10392 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10395 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10398 #if defined (OBJ_COFF) && defined (TE_PE)
10399 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10400 && S_IS_WEAK (fragP
->fr_symbol
))
10404 /* Symbol is undefined in this segment, or we need to keep a
10405 reloc so that weak symbols can be overridden. */
10406 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10407 enum bfd_reloc_code_real reloc_type
;
10408 unsigned char *opcode
;
10411 if (fragP
->fr_var
!= NO_RELOC
)
10412 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10413 else if (size
== 2)
10414 reloc_type
= BFD_RELOC_16_PCREL
;
10415 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10416 else if (need_plt32_p (fragP
->fr_symbol
))
10417 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10420 reloc_type
= BFD_RELOC_32_PCREL
;
10422 old_fr_fix
= fragP
->fr_fix
;
10423 opcode
= (unsigned char *) fragP
->fr_opcode
;
10425 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10428 /* Make jmp (0xeb) a (d)word displacement jump. */
10430 fragP
->fr_fix
+= size
;
10431 fix_new (fragP
, old_fr_fix
, size
,
10433 fragP
->fr_offset
, 1,
10439 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10441 /* Negate the condition, and branch past an
10442 unconditional jump. */
10445 /* Insert an unconditional jump. */
10447 /* We added two extra opcode bytes, and have a two byte
10449 fragP
->fr_fix
+= 2 + 2;
10450 fix_new (fragP
, old_fr_fix
+ 2, 2,
10452 fragP
->fr_offset
, 1,
10456 /* Fall through. */
10459 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10463 fragP
->fr_fix
+= 1;
10464 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10466 fragP
->fr_offset
, 1,
10467 BFD_RELOC_8_PCREL
);
10468 fixP
->fx_signed
= 1;
10472 /* This changes the byte-displacement jump 0x7N
10473 to the (d)word-displacement jump 0x0f,0x8N. */
10474 opcode
[1] = opcode
[0] + 0x10;
10475 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10476 /* We've added an opcode byte. */
10477 fragP
->fr_fix
+= 1 + size
;
10478 fix_new (fragP
, old_fr_fix
+ 1, size
,
10480 fragP
->fr_offset
, 1,
10485 BAD_CASE (fragP
->fr_subtype
);
10489 return fragP
->fr_fix
- old_fr_fix
;
10492 /* Guess size depending on current relax state. Initially the relax
10493 state will correspond to a short jump and we return 1, because
10494 the variable part of the frag (the branch offset) is one byte
10495 long. However, we can relax a section more than once and in that
10496 case we must either set fr_subtype back to the unrelaxed state,
10497 or return the value for the appropriate branch. */
10498 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10501 /* Called after relax() is finished.
10503 In: Address of frag.
10504 fr_type == rs_machine_dependent.
10505 fr_subtype is what the address relaxed to.
10507 Out: Any fixSs and constants are set up.
10508 Caller will turn frag into a ".space 0". */
10511 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10514 unsigned char *opcode
;
10515 unsigned char *where_to_put_displacement
= NULL
;
10516 offsetT target_address
;
10517 offsetT opcode_address
;
10518 unsigned int extension
= 0;
10519 offsetT displacement_from_opcode_start
;
10521 opcode
= (unsigned char *) fragP
->fr_opcode
;
10523 /* Address we want to reach in file space. */
10524 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10526 /* Address opcode resides at in file space. */
10527 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10529 /* Displacement from opcode start to fill into instruction. */
10530 displacement_from_opcode_start
= target_address
- opcode_address
;
10532 if ((fragP
->fr_subtype
& BIG
) == 0)
10534 /* Don't have to change opcode. */
10535 extension
= 1; /* 1 opcode + 1 displacement */
10536 where_to_put_displacement
= &opcode
[1];
10540 if (no_cond_jump_promotion
10541 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10542 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10543 _("long jump required"));
10545 switch (fragP
->fr_subtype
)
10547 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10548 extension
= 4; /* 1 opcode + 4 displacement */
10550 where_to_put_displacement
= &opcode
[1];
10553 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10554 extension
= 2; /* 1 opcode + 2 displacement */
10556 where_to_put_displacement
= &opcode
[1];
10559 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10560 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10561 extension
= 5; /* 2 opcode + 4 displacement */
10562 opcode
[1] = opcode
[0] + 0x10;
10563 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10564 where_to_put_displacement
= &opcode
[2];
10567 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10568 extension
= 3; /* 2 opcode + 2 displacement */
10569 opcode
[1] = opcode
[0] + 0x10;
10570 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10571 where_to_put_displacement
= &opcode
[2];
10574 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10579 where_to_put_displacement
= &opcode
[3];
10583 BAD_CASE (fragP
->fr_subtype
);
10588 /* If size if less then four we are sure that the operand fits,
10589 but if it's 4, then it could be that the displacement is larger
10591 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10593 && ((addressT
) (displacement_from_opcode_start
- extension
10594 + ((addressT
) 1 << 31))
10595 > (((addressT
) 2 << 31) - 1)))
10597 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10598 _("jump target out of range"));
10599 /* Make us emit 0. */
10600 displacement_from_opcode_start
= extension
;
10602 /* Now put displacement after opcode. */
10603 md_number_to_chars ((char *) where_to_put_displacement
,
10604 (valueT
) (displacement_from_opcode_start
- extension
),
10605 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10606 fragP
->fr_fix
+= extension
;
10609 /* Apply a fixup (fixP) to segment data, once it has been determined
10610 by our caller that we have all the info we need to fix it up.
10612 Parameter valP is the pointer to the value of the bits.
10614 On the 386, immediates, displacements, and data pointers are all in
10615 the same (little-endian) format, so we don't need to care about which
10616 we are handling. */
10619 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10621 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10622 valueT value
= *valP
;
10624 #if !defined (TE_Mach)
10625 if (fixP
->fx_pcrel
)
10627 switch (fixP
->fx_r_type
)
10633 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10636 case BFD_RELOC_X86_64_32S
:
10637 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10640 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10643 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10648 if (fixP
->fx_addsy
!= NULL
10649 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10650 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10651 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10652 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10653 && !use_rela_relocations
)
10655 /* This is a hack. There should be a better way to handle this.
10656 This covers for the fact that bfd_install_relocation will
10657 subtract the current location (for partial_inplace, PC relative
10658 relocations); see more below. */
10662 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10665 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10670 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10672 if ((sym_seg
== seg
10673 || (symbol_section_p (fixP
->fx_addsy
)
10674 && sym_seg
!= absolute_section
))
10675 && !generic_force_reloc (fixP
))
10677 /* Yes, we add the values in twice. This is because
10678 bfd_install_relocation subtracts them out again. I think
10679 bfd_install_relocation is broken, but I don't dare change
10681 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10685 #if defined (OBJ_COFF) && defined (TE_PE)
10686 /* For some reason, the PE format does not store a
10687 section address offset for a PC relative symbol. */
10688 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10689 || S_IS_WEAK (fixP
->fx_addsy
))
10690 value
+= md_pcrel_from (fixP
);
10693 #if defined (OBJ_COFF) && defined (TE_PE)
10694 if (fixP
->fx_addsy
!= NULL
10695 && S_IS_WEAK (fixP
->fx_addsy
)
10696 /* PR 16858: Do not modify weak function references. */
10697 && ! fixP
->fx_pcrel
)
10699 #if !defined (TE_PEP)
10700 /* For x86 PE weak function symbols are neither PC-relative
10701 nor do they set S_IS_FUNCTION. So the only reliable way
10702 to detect them is to check the flags of their containing
10704 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10705 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10709 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10713 /* Fix a few things - the dynamic linker expects certain values here,
10714 and we must not disappoint it. */
10715 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10716 if (IS_ELF
&& fixP
->fx_addsy
)
10717 switch (fixP
->fx_r_type
)
10719 case BFD_RELOC_386_PLT32
:
10720 case BFD_RELOC_X86_64_PLT32
:
10721 /* Make the jump instruction point to the address of the operand.
10722 At runtime we merely add the offset to the actual PLT entry.
10723 NB: Subtract the offset size only for jump instructions. */
10724 if (fixP
->fx_pcrel
)
10728 case BFD_RELOC_386_TLS_GD
:
10729 case BFD_RELOC_386_TLS_LDM
:
10730 case BFD_RELOC_386_TLS_IE_32
:
10731 case BFD_RELOC_386_TLS_IE
:
10732 case BFD_RELOC_386_TLS_GOTIE
:
10733 case BFD_RELOC_386_TLS_GOTDESC
:
10734 case BFD_RELOC_X86_64_TLSGD
:
10735 case BFD_RELOC_X86_64_TLSLD
:
10736 case BFD_RELOC_X86_64_GOTTPOFF
:
10737 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10738 value
= 0; /* Fully resolved at runtime. No addend. */
10740 case BFD_RELOC_386_TLS_LE
:
10741 case BFD_RELOC_386_TLS_LDO_32
:
10742 case BFD_RELOC_386_TLS_LE_32
:
10743 case BFD_RELOC_X86_64_DTPOFF32
:
10744 case BFD_RELOC_X86_64_DTPOFF64
:
10745 case BFD_RELOC_X86_64_TPOFF32
:
10746 case BFD_RELOC_X86_64_TPOFF64
:
10747 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10750 case BFD_RELOC_386_TLS_DESC_CALL
:
10751 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10752 value
= 0; /* Fully resolved at runtime. No addend. */
10753 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10757 case BFD_RELOC_VTABLE_INHERIT
:
10758 case BFD_RELOC_VTABLE_ENTRY
:
10765 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10767 #endif /* !defined (TE_Mach) */
10769 /* Are we finished with this relocation now? */
10770 if (fixP
->fx_addsy
== NULL
)
10772 #if defined (OBJ_COFF) && defined (TE_PE)
10773 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10776 /* Remember value for tc_gen_reloc. */
10777 fixP
->fx_addnumber
= value
;
10778 /* Clear out the frag for now. */
10782 else if (use_rela_relocations
)
10784 fixP
->fx_no_overflow
= 1;
10785 /* Remember value for tc_gen_reloc. */
10786 fixP
->fx_addnumber
= value
;
10790 md_number_to_chars (p
, value
, fixP
->fx_size
);
10794 md_atof (int type
, char *litP
, int *sizeP
)
10796 /* This outputs the LITTLENUMs in REVERSE order;
10797 in accord with the bigendian 386. */
10798 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10801 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10804 output_invalid (int c
)
10807 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10810 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10811 "(0x%x)", (unsigned char) c
);
10812 return output_invalid_buf
;
10815 /* REG_STRING starts *before* REGISTER_PREFIX. */
10817 static const reg_entry
*
10818 parse_real_register (char *reg_string
, char **end_op
)
10820 char *s
= reg_string
;
10822 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10823 const reg_entry
*r
;
10825 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10826 if (*s
== REGISTER_PREFIX
)
10829 if (is_space_char (*s
))
10832 p
= reg_name_given
;
10833 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10835 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10836 return (const reg_entry
*) NULL
;
10840 /* For naked regs, make sure that we are not dealing with an identifier.
10841 This prevents confusing an identifier like `eax_var' with register
10843 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10844 return (const reg_entry
*) NULL
;
10848 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10850 /* Handle floating point regs, allowing spaces in the (i) part. */
10851 if (r
== i386_regtab
/* %st is first entry of table */)
10853 if (!cpu_arch_flags
.bitfield
.cpu8087
10854 && !cpu_arch_flags
.bitfield
.cpu287
10855 && !cpu_arch_flags
.bitfield
.cpu387
)
10856 return (const reg_entry
*) NULL
;
10858 if (is_space_char (*s
))
10863 if (is_space_char (*s
))
10865 if (*s
>= '0' && *s
<= '7')
10867 int fpr
= *s
- '0';
10869 if (is_space_char (*s
))
10874 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10879 /* We have "%st(" then garbage. */
10880 return (const reg_entry
*) NULL
;
10884 if (r
== NULL
|| allow_pseudo_reg
)
10887 if (operand_type_all_zero (&r
->reg_type
))
10888 return (const reg_entry
*) NULL
;
10890 if ((r
->reg_type
.bitfield
.dword
10891 || r
->reg_type
.bitfield
.sreg3
10892 || r
->reg_type
.bitfield
.control
10893 || r
->reg_type
.bitfield
.debug
10894 || r
->reg_type
.bitfield
.test
)
10895 && !cpu_arch_flags
.bitfield
.cpui386
)
10896 return (const reg_entry
*) NULL
;
10898 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10899 return (const reg_entry
*) NULL
;
10901 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10903 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10904 return (const reg_entry
*) NULL
;
10906 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10908 if (r
->reg_type
.bitfield
.ymmword
)
10909 return (const reg_entry
*) NULL
;
10911 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10912 return (const reg_entry
*) NULL
;
10916 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10917 return (const reg_entry
*) NULL
;
10919 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10920 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10921 return (const reg_entry
*) NULL
;
10923 /* Upper 16 vector registers are only available with VREX in 64bit
10924 mode, and require EVEX encoding. */
10925 if (r
->reg_flags
& RegVRex
)
10927 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10928 || flag_code
!= CODE_64BIT
)
10929 return (const reg_entry
*) NULL
;
10931 i
.vec_encoding
= vex_encoding_evex
;
10934 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10935 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10936 && flag_code
!= CODE_64BIT
)
10937 return (const reg_entry
*) NULL
;
10939 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10940 return (const reg_entry
*) NULL
;
10945 /* REG_STRING starts *before* REGISTER_PREFIX. */
10947 static const reg_entry
*
10948 parse_register (char *reg_string
, char **end_op
)
10950 const reg_entry
*r
;
10952 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10953 r
= parse_real_register (reg_string
, end_op
);
10958 char *save
= input_line_pointer
;
10962 input_line_pointer
= reg_string
;
10963 c
= get_symbol_name (®_string
);
10964 symbolP
= symbol_find (reg_string
);
10965 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10967 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10969 know (e
->X_op
== O_register
);
10970 know (e
->X_add_number
>= 0
10971 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10972 r
= i386_regtab
+ e
->X_add_number
;
10973 if ((r
->reg_flags
& RegVRex
))
10974 i
.vec_encoding
= vex_encoding_evex
;
10975 *end_op
= input_line_pointer
;
10977 *input_line_pointer
= c
;
10978 input_line_pointer
= save
;
10984 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10986 const reg_entry
*r
;
10987 char *end
= input_line_pointer
;
10990 r
= parse_register (name
, &input_line_pointer
);
10991 if (r
&& end
<= input_line_pointer
)
10993 *nextcharP
= *input_line_pointer
;
10994 *input_line_pointer
= 0;
10995 e
->X_op
= O_register
;
10996 e
->X_add_number
= r
- i386_regtab
;
10999 input_line_pointer
= end
;
11001 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11005 md_operand (expressionS
*e
)
11008 const reg_entry
*r
;
11010 switch (*input_line_pointer
)
11012 case REGISTER_PREFIX
:
11013 r
= parse_real_register (input_line_pointer
, &end
);
11016 e
->X_op
= O_register
;
11017 e
->X_add_number
= r
- i386_regtab
;
11018 input_line_pointer
= end
;
11023 gas_assert (intel_syntax
);
11024 end
= input_line_pointer
++;
11026 if (*input_line_pointer
== ']')
11028 ++input_line_pointer
;
11029 e
->X_op_symbol
= make_expr_symbol (e
);
11030 e
->X_add_symbol
= NULL
;
11031 e
->X_add_number
= 0;
11036 e
->X_op
= O_absent
;
11037 input_line_pointer
= end
;
11044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11045 const char *md_shortopts
= "kVQ:sqnO::";
11047 const char *md_shortopts
= "qnO::";
11050 #define OPTION_32 (OPTION_MD_BASE + 0)
11051 #define OPTION_64 (OPTION_MD_BASE + 1)
11052 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11053 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11054 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11055 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11056 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11057 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11058 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11059 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11060 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11061 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11062 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11063 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11064 #define OPTION_X32 (OPTION_MD_BASE + 14)
11065 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11066 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11067 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11068 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11069 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11070 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11071 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11072 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11073 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11074 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11075 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11076 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11078 struct option md_longopts
[] =
11080 {"32", no_argument
, NULL
, OPTION_32
},
11081 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11082 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11083 {"64", no_argument
, NULL
, OPTION_64
},
11085 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11086 {"x32", no_argument
, NULL
, OPTION_X32
},
11087 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11088 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11090 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11091 {"march", required_argument
, NULL
, OPTION_MARCH
},
11092 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11093 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11094 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11095 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11096 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11097 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11098 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11099 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11100 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11101 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11102 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11103 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11104 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11105 # if defined (TE_PE) || defined (TE_PEP)
11106 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11108 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11109 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11110 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11111 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11112 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11113 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11114 {NULL
, no_argument
, NULL
, 0}
11116 size_t md_longopts_size
= sizeof (md_longopts
);
11119 md_parse_option (int c
, const char *arg
)
11122 char *arch
, *next
, *saved
;
11127 optimize_align_code
= 0;
11131 quiet_warnings
= 1;
11134 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11135 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11136 should be emitted or not. FIXME: Not implemented. */
11140 /* -V: SVR4 argument to print version ID. */
11142 print_version_id ();
11145 /* -k: Ignore for FreeBSD compatibility. */
11150 /* -s: On i386 Solaris, this tells the native assembler to use
11151 .stab instead of .stab.excl. We always use .stab anyhow. */
11154 case OPTION_MSHARED
:
11158 case OPTION_X86_USED_NOTE
:
11159 if (strcasecmp (arg
, "yes") == 0)
11161 else if (strcasecmp (arg
, "no") == 0)
11164 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11169 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11170 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11173 const char **list
, **l
;
11175 list
= bfd_target_list ();
11176 for (l
= list
; *l
!= NULL
; l
++)
11177 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11178 || strcmp (*l
, "coff-x86-64") == 0
11179 || strcmp (*l
, "pe-x86-64") == 0
11180 || strcmp (*l
, "pei-x86-64") == 0
11181 || strcmp (*l
, "mach-o-x86-64") == 0)
11183 default_arch
= "x86_64";
11187 as_fatal (_("no compiled in support for x86_64"));
11193 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11197 const char **list
, **l
;
11199 list
= bfd_target_list ();
11200 for (l
= list
; *l
!= NULL
; l
++)
11201 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11203 default_arch
= "x86_64:32";
11207 as_fatal (_("no compiled in support for 32bit x86_64"));
11211 as_fatal (_("32bit x86_64 is only supported for ELF"));
11216 default_arch
= "i386";
11219 case OPTION_DIVIDE
:
11220 #ifdef SVR4_COMMENT_CHARS
11225 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11227 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11231 i386_comment_chars
= n
;
11237 saved
= xstrdup (arg
);
11239 /* Allow -march=+nosse. */
11245 as_fatal (_("invalid -march= option: `%s'"), arg
);
11246 next
= strchr (arch
, '+');
11249 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11251 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11254 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11257 cpu_arch_name
= cpu_arch
[j
].name
;
11258 cpu_sub_arch_name
= NULL
;
11259 cpu_arch_flags
= cpu_arch
[j
].flags
;
11260 cpu_arch_isa
= cpu_arch
[j
].type
;
11261 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11262 if (!cpu_arch_tune_set
)
11264 cpu_arch_tune
= cpu_arch_isa
;
11265 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11269 else if (*cpu_arch
[j
].name
== '.'
11270 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11272 /* ISA extension. */
11273 i386_cpu_flags flags
;
11275 flags
= cpu_flags_or (cpu_arch_flags
,
11276 cpu_arch
[j
].flags
);
11278 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11280 if (cpu_sub_arch_name
)
11282 char *name
= cpu_sub_arch_name
;
11283 cpu_sub_arch_name
= concat (name
,
11285 (const char *) NULL
);
11289 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11290 cpu_arch_flags
= flags
;
11291 cpu_arch_isa_flags
= flags
;
11295 = cpu_flags_or (cpu_arch_isa_flags
,
11296 cpu_arch
[j
].flags
);
11301 if (j
>= ARRAY_SIZE (cpu_arch
))
11303 /* Disable an ISA extension. */
11304 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11305 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11307 i386_cpu_flags flags
;
11309 flags
= cpu_flags_and_not (cpu_arch_flags
,
11310 cpu_noarch
[j
].flags
);
11311 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11313 if (cpu_sub_arch_name
)
11315 char *name
= cpu_sub_arch_name
;
11316 cpu_sub_arch_name
= concat (arch
,
11317 (const char *) NULL
);
11321 cpu_sub_arch_name
= xstrdup (arch
);
11322 cpu_arch_flags
= flags
;
11323 cpu_arch_isa_flags
= flags
;
11328 if (j
>= ARRAY_SIZE (cpu_noarch
))
11329 j
= ARRAY_SIZE (cpu_arch
);
11332 if (j
>= ARRAY_SIZE (cpu_arch
))
11333 as_fatal (_("invalid -march= option: `%s'"), arg
);
11337 while (next
!= NULL
);
11343 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11344 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11346 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11348 cpu_arch_tune_set
= 1;
11349 cpu_arch_tune
= cpu_arch
[j
].type
;
11350 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11354 if (j
>= ARRAY_SIZE (cpu_arch
))
11355 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11358 case OPTION_MMNEMONIC
:
11359 if (strcasecmp (arg
, "att") == 0)
11360 intel_mnemonic
= 0;
11361 else if (strcasecmp (arg
, "intel") == 0)
11362 intel_mnemonic
= 1;
11364 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11367 case OPTION_MSYNTAX
:
11368 if (strcasecmp (arg
, "att") == 0)
11370 else if (strcasecmp (arg
, "intel") == 0)
11373 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11376 case OPTION_MINDEX_REG
:
11377 allow_index_reg
= 1;
11380 case OPTION_MNAKED_REG
:
11381 allow_naked_reg
= 1;
11384 case OPTION_MSSE2AVX
:
11388 case OPTION_MSSE_CHECK
:
11389 if (strcasecmp (arg
, "error") == 0)
11390 sse_check
= check_error
;
11391 else if (strcasecmp (arg
, "warning") == 0)
11392 sse_check
= check_warning
;
11393 else if (strcasecmp (arg
, "none") == 0)
11394 sse_check
= check_none
;
11396 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11399 case OPTION_MOPERAND_CHECK
:
11400 if (strcasecmp (arg
, "error") == 0)
11401 operand_check
= check_error
;
11402 else if (strcasecmp (arg
, "warning") == 0)
11403 operand_check
= check_warning
;
11404 else if (strcasecmp (arg
, "none") == 0)
11405 operand_check
= check_none
;
11407 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11410 case OPTION_MAVXSCALAR
:
11411 if (strcasecmp (arg
, "128") == 0)
11412 avxscalar
= vex128
;
11413 else if (strcasecmp (arg
, "256") == 0)
11414 avxscalar
= vex256
;
11416 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11419 case OPTION_MVEXWIG
:
11420 if (strcmp (arg
, "0") == 0)
11422 else if (strcmp (arg
, "1") == 0)
11425 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11428 case OPTION_MADD_BND_PREFIX
:
11429 add_bnd_prefix
= 1;
11432 case OPTION_MEVEXLIG
:
11433 if (strcmp (arg
, "128") == 0)
11434 evexlig
= evexl128
;
11435 else if (strcmp (arg
, "256") == 0)
11436 evexlig
= evexl256
;
11437 else if (strcmp (arg
, "512") == 0)
11438 evexlig
= evexl512
;
11440 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11443 case OPTION_MEVEXRCIG
:
11444 if (strcmp (arg
, "rne") == 0)
11446 else if (strcmp (arg
, "rd") == 0)
11448 else if (strcmp (arg
, "ru") == 0)
11450 else if (strcmp (arg
, "rz") == 0)
11453 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11456 case OPTION_MEVEXWIG
:
11457 if (strcmp (arg
, "0") == 0)
11459 else if (strcmp (arg
, "1") == 0)
11462 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11465 # if defined (TE_PE) || defined (TE_PEP)
11466 case OPTION_MBIG_OBJ
:
11471 case OPTION_MOMIT_LOCK_PREFIX
:
11472 if (strcasecmp (arg
, "yes") == 0)
11473 omit_lock_prefix
= 1;
11474 else if (strcasecmp (arg
, "no") == 0)
11475 omit_lock_prefix
= 0;
11477 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11480 case OPTION_MFENCE_AS_LOCK_ADD
:
11481 if (strcasecmp (arg
, "yes") == 0)
11483 else if (strcasecmp (arg
, "no") == 0)
11486 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11489 case OPTION_MRELAX_RELOCATIONS
:
11490 if (strcasecmp (arg
, "yes") == 0)
11491 generate_relax_relocations
= 1;
11492 else if (strcasecmp (arg
, "no") == 0)
11493 generate_relax_relocations
= 0;
11495 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11498 case OPTION_MAMD64
:
11502 case OPTION_MINTEL64
:
11510 /* Turn off -Os. */
11511 optimize_for_space
= 0;
11513 else if (*arg
== 's')
11515 optimize_for_space
= 1;
11516 /* Turn on all encoding optimizations. */
11517 optimize
= INT_MAX
;
11521 optimize
= atoi (arg
);
11522 /* Turn off -Os. */
11523 optimize_for_space
= 0;
11533 #define MESSAGE_TEMPLATE \
11537 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11538 int *left_p
, const char *name
, int len
)
11540 int size
= sizeof (MESSAGE_TEMPLATE
);
11541 int left
= *left_p
;
11543 /* Reserve 2 spaces for ", " or ",\0" */
11546 /* Check if there is any room. */
11554 p
= mempcpy (p
, name
, len
);
11558 /* Output the current message now and start a new one. */
11561 fprintf (stream
, "%s\n", message
);
11563 left
= size
- (start
- message
) - len
- 2;
11565 gas_assert (left
>= 0);
11567 p
= mempcpy (p
, name
, len
);
11575 show_arch (FILE *stream
, int ext
, int check
)
11577 static char message
[] = MESSAGE_TEMPLATE
;
11578 char *start
= message
+ 27;
11580 int size
= sizeof (MESSAGE_TEMPLATE
);
11587 left
= size
- (start
- message
);
11588 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11590 /* Should it be skipped? */
11591 if (cpu_arch
[j
].skip
)
11594 name
= cpu_arch
[j
].name
;
11595 len
= cpu_arch
[j
].len
;
11598 /* It is an extension. Skip if we aren't asked to show it. */
11609 /* It is an processor. Skip if we show only extension. */
11612 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11614 /* It is an impossible processor - skip. */
11618 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11621 /* Display disabled extensions. */
11623 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11625 name
= cpu_noarch
[j
].name
;
11626 len
= cpu_noarch
[j
].len
;
11627 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11632 fprintf (stream
, "%s\n", message
);
11636 md_show_usage (FILE *stream
)
11638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11639 fprintf (stream
, _("\
11641 -V print assembler version number\n\
11644 fprintf (stream
, _("\
11645 -n Do not optimize code alignment\n\
11646 -q quieten some warnings\n"));
11647 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11648 fprintf (stream
, _("\
11651 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11652 || defined (TE_PE) || defined (TE_PEP))
11653 fprintf (stream
, _("\
11654 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11656 #ifdef SVR4_COMMENT_CHARS
11657 fprintf (stream
, _("\
11658 --divide do not treat `/' as a comment character\n"));
11660 fprintf (stream
, _("\
11661 --divide ignored\n"));
11663 fprintf (stream
, _("\
11664 -march=CPU[,+EXTENSION...]\n\
11665 generate code for CPU and EXTENSION, CPU is one of:\n"));
11666 show_arch (stream
, 0, 1);
11667 fprintf (stream
, _("\
11668 EXTENSION is combination of:\n"));
11669 show_arch (stream
, 1, 0);
11670 fprintf (stream
, _("\
11671 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11672 show_arch (stream
, 0, 0);
11673 fprintf (stream
, _("\
11674 -msse2avx encode SSE instructions with VEX prefix\n"));
11675 fprintf (stream
, _("\
11676 -msse-check=[none|error|warning] (default: warning)\n\
11677 check SSE instructions\n"));
11678 fprintf (stream
, _("\
11679 -moperand-check=[none|error|warning] (default: warning)\n\
11680 check operand combinations for validity\n"));
11681 fprintf (stream
, _("\
11682 -mavxscalar=[128|256] (default: 128)\n\
11683 encode scalar AVX instructions with specific vector\n\
11685 fprintf (stream
, _("\
11686 -mvexwig=[0|1] (default: 0)\n\
11687 encode VEX instructions with specific VEX.W value\n\
11688 for VEX.W bit ignored instructions\n"));
11689 fprintf (stream
, _("\
11690 -mevexlig=[128|256|512] (default: 128)\n\
11691 encode scalar EVEX instructions with specific vector\n\
11693 fprintf (stream
, _("\
11694 -mevexwig=[0|1] (default: 0)\n\
11695 encode EVEX instructions with specific EVEX.W value\n\
11696 for EVEX.W bit ignored instructions\n"));
11697 fprintf (stream
, _("\
11698 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11699 encode EVEX instructions with specific EVEX.RC value\n\
11700 for SAE-only ignored instructions\n"));
11701 fprintf (stream
, _("\
11702 -mmnemonic=[att|intel] "));
11703 if (SYSV386_COMPAT
)
11704 fprintf (stream
, _("(default: att)\n"));
11706 fprintf (stream
, _("(default: intel)\n"));
11707 fprintf (stream
, _("\
11708 use AT&T/Intel mnemonic\n"));
11709 fprintf (stream
, _("\
11710 -msyntax=[att|intel] (default: att)\n\
11711 use AT&T/Intel syntax\n"));
11712 fprintf (stream
, _("\
11713 -mindex-reg support pseudo index registers\n"));
11714 fprintf (stream
, _("\
11715 -mnaked-reg don't require `%%' prefix for registers\n"));
11716 fprintf (stream
, _("\
11717 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11719 fprintf (stream
, _("\
11720 -mshared disable branch optimization for shared code\n"));
11721 fprintf (stream
, _("\
11722 -mx86-used-note=[no|yes] "));
11723 if (DEFAULT_X86_USED_NOTE
)
11724 fprintf (stream
, _("(default: yes)\n"));
11726 fprintf (stream
, _("(default: no)\n"));
11727 fprintf (stream
, _("\
11728 generate x86 used ISA and feature properties\n"));
11730 #if defined (TE_PE) || defined (TE_PEP)
11731 fprintf (stream
, _("\
11732 -mbig-obj generate big object files\n"));
11734 fprintf (stream
, _("\
11735 -momit-lock-prefix=[no|yes] (default: no)\n\
11736 strip all lock prefixes\n"));
11737 fprintf (stream
, _("\
11738 -mfence-as-lock-add=[no|yes] (default: no)\n\
11739 encode lfence, mfence and sfence as\n\
11740 lock addl $0x0, (%%{re}sp)\n"));
11741 fprintf (stream
, _("\
11742 -mrelax-relocations=[no|yes] "));
11743 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11744 fprintf (stream
, _("(default: yes)\n"));
11746 fprintf (stream
, _("(default: no)\n"));
11747 fprintf (stream
, _("\
11748 generate relax relocations\n"));
11749 fprintf (stream
, _("\
11750 -mamd64 accept only AMD64 ISA [default]\n"));
11751 fprintf (stream
, _("\
11752 -mintel64 accept only Intel64 ISA\n"));
11755 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11756 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11757 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11759 /* Pick the target format to use. */
11762 i386_target_format (void)
11764 if (!strncmp (default_arch
, "x86_64", 6))
11766 update_code_flag (CODE_64BIT
, 1);
11767 if (default_arch
[6] == '\0')
11768 x86_elf_abi
= X86_64_ABI
;
11770 x86_elf_abi
= X86_64_X32_ABI
;
11772 else if (!strcmp (default_arch
, "i386"))
11773 update_code_flag (CODE_32BIT
, 1);
11774 else if (!strcmp (default_arch
, "iamcu"))
11776 update_code_flag (CODE_32BIT
, 1);
11777 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11779 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11780 cpu_arch_name
= "iamcu";
11781 cpu_sub_arch_name
= NULL
;
11782 cpu_arch_flags
= iamcu_flags
;
11783 cpu_arch_isa
= PROCESSOR_IAMCU
;
11784 cpu_arch_isa_flags
= iamcu_flags
;
11785 if (!cpu_arch_tune_set
)
11787 cpu_arch_tune
= cpu_arch_isa
;
11788 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11791 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11792 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11796 as_fatal (_("unknown architecture"));
11798 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11799 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11800 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11801 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11803 switch (OUTPUT_FLAVOR
)
11805 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11806 case bfd_target_aout_flavour
:
11807 return AOUT_TARGET_FORMAT
;
11809 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11810 # if defined (TE_PE) || defined (TE_PEP)
11811 case bfd_target_coff_flavour
:
11812 if (flag_code
== CODE_64BIT
)
11813 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11816 # elif defined (TE_GO32)
11817 case bfd_target_coff_flavour
:
11818 return "coff-go32";
11820 case bfd_target_coff_flavour
:
11821 return "coff-i386";
11824 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11825 case bfd_target_elf_flavour
:
11827 const char *format
;
11829 switch (x86_elf_abi
)
11832 format
= ELF_TARGET_FORMAT
;
11835 use_rela_relocations
= 1;
11837 format
= ELF_TARGET_FORMAT64
;
11839 case X86_64_X32_ABI
:
11840 use_rela_relocations
= 1;
11842 disallow_64bit_reloc
= 1;
11843 format
= ELF_TARGET_FORMAT32
;
11846 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11848 if (x86_elf_abi
!= X86_64_ABI
)
11849 as_fatal (_("Intel L1OM is 64bit only"));
11850 return ELF_TARGET_L1OM_FORMAT
;
11852 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11854 if (x86_elf_abi
!= X86_64_ABI
)
11855 as_fatal (_("Intel K1OM is 64bit only"));
11856 return ELF_TARGET_K1OM_FORMAT
;
11858 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11860 if (x86_elf_abi
!= I386_ABI
)
11861 as_fatal (_("Intel MCU is 32bit only"));
11862 return ELF_TARGET_IAMCU_FORMAT
;
11868 #if defined (OBJ_MACH_O)
11869 case bfd_target_mach_o_flavour
:
11870 if (flag_code
== CODE_64BIT
)
11872 use_rela_relocations
= 1;
11874 return "mach-o-x86-64";
11877 return "mach-o-i386";
11885 #endif /* OBJ_MAYBE_ more than one */
11888 md_undefined_symbol (char *name
)
11890 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11891 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11892 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11893 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11897 if (symbol_find (name
))
11898 as_bad (_("GOT already in symbol table"));
11899 GOT_symbol
= symbol_new (name
, undefined_section
,
11900 (valueT
) 0, &zero_address_frag
);
11907 /* Round up a section size to the appropriate boundary. */
11910 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11912 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11913 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11915 /* For a.out, force the section size to be aligned. If we don't do
11916 this, BFD will align it for us, but it will not write out the
11917 final bytes of the section. This may be a bug in BFD, but it is
11918 easier to fix it here since that is how the other a.out targets
11922 align
= bfd_get_section_alignment (stdoutput
, segment
);
11923 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11930 /* On the i386, PC-relative offsets are relative to the start of the
11931 next instruction. That is, the address of the offset, plus its
11932 size, since the offset is always the last part of the insn. */
11935 md_pcrel_from (fixS
*fixP
)
11937 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11943 s_bss (int ignore ATTRIBUTE_UNUSED
)
11947 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11949 obj_elf_section_change_hook ();
11951 temp
= get_absolute_expression ();
11952 subseg_set (bss_section
, (subsegT
) temp
);
11953 demand_empty_rest_of_line ();
11959 i386_validate_fix (fixS
*fixp
)
11961 if (fixp
->fx_subsy
)
11963 if (fixp
->fx_subsy
== GOT_symbol
)
11965 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11970 if (fixp
->fx_tcbit2
)
11971 fixp
->fx_r_type
= (fixp
->fx_tcbit
11972 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11973 : BFD_RELOC_X86_64_GOTPCRELX
);
11976 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11981 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11983 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11985 fixp
->fx_subsy
= 0;
11988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11989 else if (!object_64bit
)
11991 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11992 && fixp
->fx_tcbit2
)
11993 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11999 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12002 bfd_reloc_code_real_type code
;
12004 switch (fixp
->fx_r_type
)
12006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12007 case BFD_RELOC_SIZE32
:
12008 case BFD_RELOC_SIZE64
:
12009 if (S_IS_DEFINED (fixp
->fx_addsy
)
12010 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12012 /* Resolve size relocation against local symbol to size of
12013 the symbol plus addend. */
12014 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12015 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12016 && !fits_in_unsigned_long (value
))
12017 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12018 _("symbol size computation overflow"));
12019 fixp
->fx_addsy
= NULL
;
12020 fixp
->fx_subsy
= NULL
;
12021 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12025 /* Fall through. */
12027 case BFD_RELOC_X86_64_PLT32
:
12028 case BFD_RELOC_X86_64_GOT32
:
12029 case BFD_RELOC_X86_64_GOTPCREL
:
12030 case BFD_RELOC_X86_64_GOTPCRELX
:
12031 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12032 case BFD_RELOC_386_PLT32
:
12033 case BFD_RELOC_386_GOT32
:
12034 case BFD_RELOC_386_GOT32X
:
12035 case BFD_RELOC_386_GOTOFF
:
12036 case BFD_RELOC_386_GOTPC
:
12037 case BFD_RELOC_386_TLS_GD
:
12038 case BFD_RELOC_386_TLS_LDM
:
12039 case BFD_RELOC_386_TLS_LDO_32
:
12040 case BFD_RELOC_386_TLS_IE_32
:
12041 case BFD_RELOC_386_TLS_IE
:
12042 case BFD_RELOC_386_TLS_GOTIE
:
12043 case BFD_RELOC_386_TLS_LE_32
:
12044 case BFD_RELOC_386_TLS_LE
:
12045 case BFD_RELOC_386_TLS_GOTDESC
:
12046 case BFD_RELOC_386_TLS_DESC_CALL
:
12047 case BFD_RELOC_X86_64_TLSGD
:
12048 case BFD_RELOC_X86_64_TLSLD
:
12049 case BFD_RELOC_X86_64_DTPOFF32
:
12050 case BFD_RELOC_X86_64_DTPOFF64
:
12051 case BFD_RELOC_X86_64_GOTTPOFF
:
12052 case BFD_RELOC_X86_64_TPOFF32
:
12053 case BFD_RELOC_X86_64_TPOFF64
:
12054 case BFD_RELOC_X86_64_GOTOFF64
:
12055 case BFD_RELOC_X86_64_GOTPC32
:
12056 case BFD_RELOC_X86_64_GOT64
:
12057 case BFD_RELOC_X86_64_GOTPCREL64
:
12058 case BFD_RELOC_X86_64_GOTPC64
:
12059 case BFD_RELOC_X86_64_GOTPLT64
:
12060 case BFD_RELOC_X86_64_PLTOFF64
:
12061 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12062 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12063 case BFD_RELOC_RVA
:
12064 case BFD_RELOC_VTABLE_ENTRY
:
12065 case BFD_RELOC_VTABLE_INHERIT
:
12067 case BFD_RELOC_32_SECREL
:
12069 code
= fixp
->fx_r_type
;
12071 case BFD_RELOC_X86_64_32S
:
12072 if (!fixp
->fx_pcrel
)
12074 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12075 code
= fixp
->fx_r_type
;
12078 /* Fall through. */
12080 if (fixp
->fx_pcrel
)
12082 switch (fixp
->fx_size
)
12085 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12086 _("can not do %d byte pc-relative relocation"),
12088 code
= BFD_RELOC_32_PCREL
;
12090 case 1: code
= BFD_RELOC_8_PCREL
; break;
12091 case 2: code
= BFD_RELOC_16_PCREL
; break;
12092 case 4: code
= BFD_RELOC_32_PCREL
; break;
12094 case 8: code
= BFD_RELOC_64_PCREL
; break;
12100 switch (fixp
->fx_size
)
12103 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12104 _("can not do %d byte relocation"),
12106 code
= BFD_RELOC_32
;
12108 case 1: code
= BFD_RELOC_8
; break;
12109 case 2: code
= BFD_RELOC_16
; break;
12110 case 4: code
= BFD_RELOC_32
; break;
12112 case 8: code
= BFD_RELOC_64
; break;
12119 if ((code
== BFD_RELOC_32
12120 || code
== BFD_RELOC_32_PCREL
12121 || code
== BFD_RELOC_X86_64_32S
)
12123 && fixp
->fx_addsy
== GOT_symbol
)
12126 code
= BFD_RELOC_386_GOTPC
;
12128 code
= BFD_RELOC_X86_64_GOTPC32
;
12130 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12132 && fixp
->fx_addsy
== GOT_symbol
)
12134 code
= BFD_RELOC_X86_64_GOTPC64
;
12137 rel
= XNEW (arelent
);
12138 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12139 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12141 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12143 if (!use_rela_relocations
)
12145 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12146 vtable entry to be used in the relocation's section offset. */
12147 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12148 rel
->address
= fixp
->fx_offset
;
12149 #if defined (OBJ_COFF) && defined (TE_PE)
12150 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12151 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12156 /* Use the rela in 64bit mode. */
12159 if (disallow_64bit_reloc
)
12162 case BFD_RELOC_X86_64_DTPOFF64
:
12163 case BFD_RELOC_X86_64_TPOFF64
:
12164 case BFD_RELOC_64_PCREL
:
12165 case BFD_RELOC_X86_64_GOTOFF64
:
12166 case BFD_RELOC_X86_64_GOT64
:
12167 case BFD_RELOC_X86_64_GOTPCREL64
:
12168 case BFD_RELOC_X86_64_GOTPC64
:
12169 case BFD_RELOC_X86_64_GOTPLT64
:
12170 case BFD_RELOC_X86_64_PLTOFF64
:
12171 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12172 _("cannot represent relocation type %s in x32 mode"),
12173 bfd_get_reloc_code_name (code
));
12179 if (!fixp
->fx_pcrel
)
12180 rel
->addend
= fixp
->fx_offset
;
12184 case BFD_RELOC_X86_64_PLT32
:
12185 case BFD_RELOC_X86_64_GOT32
:
12186 case BFD_RELOC_X86_64_GOTPCREL
:
12187 case BFD_RELOC_X86_64_GOTPCRELX
:
12188 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12189 case BFD_RELOC_X86_64_TLSGD
:
12190 case BFD_RELOC_X86_64_TLSLD
:
12191 case BFD_RELOC_X86_64_GOTTPOFF
:
12192 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12193 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12194 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12197 rel
->addend
= (section
->vma
12199 + fixp
->fx_addnumber
12200 + md_pcrel_from (fixp
));
12205 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12206 if (rel
->howto
== NULL
)
12208 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12209 _("cannot represent relocation type %s"),
12210 bfd_get_reloc_code_name (code
));
12211 /* Set howto to a garbage value so that we can keep going. */
12212 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12213 gas_assert (rel
->howto
!= NULL
);
12219 #include "tc-i386-intel.c"
12222 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12224 int saved_naked_reg
;
12225 char saved_register_dot
;
12227 saved_naked_reg
= allow_naked_reg
;
12228 allow_naked_reg
= 1;
12229 saved_register_dot
= register_chars
['.'];
12230 register_chars
['.'] = '.';
12231 allow_pseudo_reg
= 1;
12232 expression_and_evaluate (exp
);
12233 allow_pseudo_reg
= 0;
12234 register_chars
['.'] = saved_register_dot
;
12235 allow_naked_reg
= saved_naked_reg
;
12237 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12239 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12241 exp
->X_op
= O_constant
;
12242 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12243 .dw2_regnum
[flag_code
>> 1];
12246 exp
->X_op
= O_illegal
;
12251 tc_x86_frame_initial_instructions (void)
12253 static unsigned int sp_regno
[2];
12255 if (!sp_regno
[flag_code
>> 1])
12257 char *saved_input
= input_line_pointer
;
12258 char sp
[][4] = {"esp", "rsp"};
12261 input_line_pointer
= sp
[flag_code
>> 1];
12262 tc_x86_parse_to_dw2regnum (&exp
);
12263 gas_assert (exp
.X_op
== O_constant
);
12264 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12265 input_line_pointer
= saved_input
;
12268 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12269 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12273 x86_dwarf2_addr_size (void)
12275 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12276 if (x86_elf_abi
== X86_64_X32_ABI
)
12279 return bfd_arch_bits_per_address (stdoutput
) / 8;
12283 i386_elf_section_type (const char *str
, size_t len
)
12285 if (flag_code
== CODE_64BIT
12286 && len
== sizeof ("unwind") - 1
12287 && strncmp (str
, "unwind", 6) == 0)
12288 return SHT_X86_64_UNWIND
;
12295 i386_solaris_fix_up_eh_frame (segT sec
)
12297 if (flag_code
== CODE_64BIT
)
12298 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12304 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12308 exp
.X_op
= O_secrel
;
12309 exp
.X_add_symbol
= symbol
;
12310 exp
.X_add_number
= 0;
12311 emit_expr (&exp
, size
);
12315 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12316 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12319 x86_64_section_letter (int letter
, const char **ptr_msg
)
12321 if (flag_code
== CODE_64BIT
)
12324 return SHF_X86_64_LARGE
;
12326 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12329 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12334 x86_64_section_word (char *str
, size_t len
)
12336 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12337 return SHF_X86_64_LARGE
;
12343 handle_large_common (int small ATTRIBUTE_UNUSED
)
12345 if (flag_code
!= CODE_64BIT
)
12347 s_comm_internal (0, elf_common_parse
);
12348 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12352 static segT lbss_section
;
12353 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12354 asection
*saved_bss_section
= bss_section
;
12356 if (lbss_section
== NULL
)
12358 flagword applicable
;
12359 segT seg
= now_seg
;
12360 subsegT subseg
= now_subseg
;
12362 /* The .lbss section is for local .largecomm symbols. */
12363 lbss_section
= subseg_new (".lbss", 0);
12364 applicable
= bfd_applicable_section_flags (stdoutput
);
12365 bfd_set_section_flags (stdoutput
, lbss_section
,
12366 applicable
& SEC_ALLOC
);
12367 seg_info (lbss_section
)->bss
= 1;
12369 subseg_set (seg
, subseg
);
12372 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12373 bss_section
= lbss_section
;
12375 s_comm_internal (0, elf_common_parse
);
12377 elf_com_section_ptr
= saved_com_section_ptr
;
12378 bss_section
= saved_bss_section
;
12381 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */