1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 /* 1 if the assembler should encode lfence, mfence, and sfence as
556 "lock addl $0, (%{re}sp)". */
557 static int avoid_fence
= 0;
559 /* 1 if the assembler should generate relax relocations. */
561 static int generate_relax_relocations
562 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
564 static enum check_kind
570 sse_check
, operand_check
= check_warning
;
572 /* Register prefix used for error message. */
573 static const char *register_prefix
= "%";
575 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
576 leave, push, and pop instructions so that gcc has the same stack
577 frame as in 32 bit mode. */
578 static char stackop_size
= '\0';
580 /* Non-zero to optimize code alignment. */
581 int optimize_align_code
= 1;
583 /* Non-zero to quieten some warnings. */
584 static int quiet_warnings
= 0;
587 static const char *cpu_arch_name
= NULL
;
588 static char *cpu_sub_arch_name
= NULL
;
590 /* CPU feature flags. */
591 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
593 /* If we have selected a cpu we are generating instructions for. */
594 static int cpu_arch_tune_set
= 0;
596 /* Cpu we are generating instructions for. */
597 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
599 /* CPU feature flags of cpu we are generating instructions for. */
600 static i386_cpu_flags cpu_arch_tune_flags
;
602 /* CPU instruction set architecture used. */
603 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
605 /* CPU feature flags of instruction set architecture used. */
606 i386_cpu_flags cpu_arch_isa_flags
;
608 /* If set, conditional jumps are not automatically promoted to handle
609 larger than a byte offset. */
610 static unsigned int no_cond_jump_promotion
= 0;
612 /* Encode SSE instructions with VEX prefix. */
613 static unsigned int sse2avx
;
615 /* Encode scalar AVX instructions with specific vector length. */
622 /* Encode scalar EVEX LIG instructions with specific vector length. */
630 /* Encode EVEX WIG instructions with specific evex.w. */
637 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
638 static enum rc_type evexrcig
= rne
;
640 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
641 static symbolS
*GOT_symbol
;
643 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
644 unsigned int x86_dwarf2_return_column
;
646 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
647 int x86_cie_data_alignment
;
649 /* Interface to relax_segment.
650 There are 3 major relax states for 386 jump insns because the
651 different types of jumps add different sizes to frags when we're
652 figuring out what sort of jump to choose to reach a given label. */
655 #define UNCOND_JUMP 0
657 #define COND_JUMP86 2
662 #define SMALL16 (SMALL | CODE16)
664 #define BIG16 (BIG | CODE16)
668 #define INLINE __inline__
674 #define ENCODE_RELAX_STATE(type, size) \
675 ((relax_substateT) (((type) << 2) | (size)))
676 #define TYPE_FROM_RELAX_STATE(s) \
678 #define DISP_SIZE_FROM_RELAX_STATE(s) \
679 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
681 /* This table is used by relax_frag to promote short jumps to long
682 ones where necessary. SMALL (short) jumps may be promoted to BIG
683 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
684 don't allow a short jump in a 32 bit code segment to be promoted to
685 a 16 bit offset jump because it's slower (requires data size
686 prefix), and doesn't work, unless the destination is in the bottom
687 64k of the code segment (The top 16 bits of eip are zeroed). */
689 const relax_typeS md_relax_table
[] =
692 1) most positive reach of this state,
693 2) most negative reach of this state,
694 3) how many bytes this mode will have in the variable part of the frag
695 4) which index into the table to try if we can't fit into this one. */
697 /* UNCOND_JUMP states. */
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
700 /* dword jmp adds 4 bytes to frag:
701 0 extra opcode bytes, 4 displacement bytes. */
703 /* word jmp adds 2 byte2 to frag:
704 0 extra opcode bytes, 2 displacement bytes. */
707 /* COND_JUMP states. */
708 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
710 /* dword conditionals adds 5 bytes to frag:
711 1 extra opcode byte, 4 displacement bytes. */
713 /* word conditionals add 3 bytes to frag:
714 1 extra opcode byte, 2 displacement bytes. */
717 /* COND_JUMP86 states. */
718 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
719 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
720 /* dword conditionals adds 5 bytes to frag:
721 1 extra opcode byte, 4 displacement bytes. */
723 /* word conditionals add 4 bytes to frag:
724 1 displacement byte and a 3 byte long branch insn. */
728 static const arch_entry cpu_arch
[] =
730 /* Do not replace the first two entries - i386_target_format()
731 relies on them being there in this order. */
732 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
733 CPU_GENERIC32_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
735 CPU_GENERIC64_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
737 CPU_NONE_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
739 CPU_I186_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
741 CPU_I286_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
743 CPU_I386_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
745 CPU_I486_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
747 CPU_I586_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
749 CPU_I686_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
751 CPU_I586_FLAGS
, 0, 0 },
752 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
753 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
755 CPU_P2_FLAGS
, 0, 0 },
756 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
757 CPU_P3_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
759 CPU_P4_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
761 CPU_CORE_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
763 CPU_NOCONA_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
765 CPU_CORE_FLAGS
, 1, 0 },
766 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
767 CPU_CORE_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
769 CPU_CORE2_FLAGS
, 1, 0 },
770 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
771 CPU_CORE2_FLAGS
, 0, 0 },
772 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
773 CPU_COREI7_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
775 CPU_L1OM_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
777 CPU_K1OM_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
779 CPU_IAMCU_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
781 CPU_K6_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
783 CPU_K6_2_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
785 CPU_ATHLON_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
787 CPU_K8_FLAGS
, 1, 0 },
788 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
789 CPU_K8_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
791 CPU_K8_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
793 CPU_AMDFAM10_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
795 CPU_BDVER1_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
797 CPU_BDVER2_FLAGS
, 0, 0 },
798 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
799 CPU_BDVER3_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
801 CPU_BDVER4_FLAGS
, 0, 0 },
802 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
803 CPU_ZNVER1_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
805 CPU_BTVER1_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
807 CPU_BTVER2_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
809 CPU_8087_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
811 CPU_287_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
813 CPU_387_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
815 CPU_ANY87_FLAGS
, 0, 1 },
816 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
817 CPU_MMX_FLAGS
, 0, 0 },
818 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
819 CPU_3DNOWA_FLAGS
, 0, 1 },
820 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
821 CPU_SSE_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
823 CPU_SSE2_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
825 CPU_SSE3_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
827 CPU_SSSE3_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
829 CPU_SSE4_1_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
831 CPU_SSE4_2_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
833 CPU_SSE4_2_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
835 CPU_ANY_SSE_FLAGS
, 0, 1 },
836 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
837 CPU_AVX_FLAGS
, 0, 0 },
838 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
839 CPU_AVX2_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
841 CPU_AVX512F_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
843 CPU_AVX512CD_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
845 CPU_AVX512ER_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
847 CPU_AVX512PF_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512DQ_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512BW_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512VL_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
855 CPU_ANY_AVX_FLAGS
, 0, 1 },
856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
857 CPU_VMX_FLAGS
, 0, 0 },
858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
859 CPU_VMFUNC_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
861 CPU_SMX_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
863 CPU_XSAVE_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
865 CPU_XSAVEOPT_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
867 CPU_XSAVEC_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVES_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
871 CPU_AES_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
873 CPU_PCLMUL_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
875 CPU_PCLMUL_FLAGS
, 1, 0 },
876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
877 CPU_FSGSBASE_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
879 CPU_RDRND_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
881 CPU_F16C_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
883 CPU_BMI2_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
885 CPU_FMA_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
887 CPU_FMA4_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
889 CPU_XOP_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
891 CPU_LWP_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
893 CPU_MOVBE_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
895 CPU_CX16_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
897 CPU_EPT_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
899 CPU_LZCNT_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
901 CPU_HLE_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
903 CPU_RTM_FLAGS
, 0, 0 },
904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
905 CPU_INVPCID_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
907 CPU_CLFLUSH_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
909 CPU_NOP_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
911 CPU_SYSCALL_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
913 CPU_RDTSCP_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
915 CPU_3DNOW_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
917 CPU_3DNOWA_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
919 CPU_PADLOCK_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
921 CPU_SVME_FLAGS
, 1, 0 },
922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
923 CPU_SVME_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
925 CPU_SSE4A_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
927 CPU_ABM_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
929 CPU_BMI_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
931 CPU_TBM_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
933 CPU_ADX_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
935 CPU_RDSEED_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
937 CPU_PRFCHW_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
939 CPU_SMAP_FLAGS
, 0, 0 },
940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
941 CPU_MPX_FLAGS
, 0, 0 },
942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
943 CPU_SHA_FLAGS
, 0, 0 },
944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
947 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
949 CPU_SE1_FLAGS
, 0, 0 },
950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
951 CPU_CLWB_FLAGS
, 0, 0 },
952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
953 CPU_PCOMMIT_FLAGS
, 0, 0 },
954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
955 CPU_AVX512IFMA_FLAGS
, 0, 0 },
956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
957 CPU_AVX512VBMI_FLAGS
, 0, 0 },
958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
959 CPU_CLZERO_FLAGS
, 0, 0 },
960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
961 CPU_MWAITX_FLAGS
, 0, 0 },
962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
963 CPU_OSPKE_FLAGS
, 0, 0 },
967 /* Like s_lcomm_internal in gas/read.c but the alignment string
968 is allowed to be optional. */
971 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
978 && *input_line_pointer
== ',')
980 align
= parse_align (needs_align
- 1);
982 if (align
== (addressT
) -1)
997 bss_alloc (symbolP
, size
, align
);
1002 pe_lcomm (int needs_align
)
1004 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1008 const pseudo_typeS md_pseudo_table
[] =
1010 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1011 {"align", s_align_bytes
, 0},
1013 {"align", s_align_ptwo
, 0},
1015 {"arch", set_cpu_arch
, 0},
1019 {"lcomm", pe_lcomm
, 1},
1021 {"ffloat", float_cons
, 'f'},
1022 {"dfloat", float_cons
, 'd'},
1023 {"tfloat", float_cons
, 'x'},
1025 {"slong", signed_cons
, 4},
1026 {"noopt", s_ignore
, 0},
1027 {"optim", s_ignore
, 0},
1028 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1029 {"code16", set_code_flag
, CODE_16BIT
},
1030 {"code32", set_code_flag
, CODE_32BIT
},
1031 {"code64", set_code_flag
, CODE_64BIT
},
1032 {"intel_syntax", set_intel_syntax
, 1},
1033 {"att_syntax", set_intel_syntax
, 0},
1034 {"intel_mnemonic", set_intel_mnemonic
, 1},
1035 {"att_mnemonic", set_intel_mnemonic
, 0},
1036 {"allow_index_reg", set_allow_index_reg
, 1},
1037 {"disallow_index_reg", set_allow_index_reg
, 0},
1038 {"sse_check", set_check
, 0},
1039 {"operand_check", set_check
, 1},
1040 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1041 {"largecomm", handle_large_common
, 0},
1043 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1044 {"loc", dwarf2_directive_loc
, 0},
1045 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1048 {"secrel32", pe_directive_secrel
, 0},
1053 /* For interface with expression (). */
1054 extern char *input_line_pointer
;
1056 /* Hash table for instruction mnemonic lookup. */
1057 static struct hash_control
*op_hash
;
1059 /* Hash table for register lookup. */
1060 static struct hash_control
*reg_hash
;
1063 i386_align_code (fragS
*fragP
, int count
)
1065 /* Various efficient no-op patterns for aligning code labels.
1066 Note: Don't try to assemble the instructions in the comments.
1067 0L and 0w are not legal. */
1068 static const char f32_1
[] =
1070 static const char f32_2
[] =
1071 {0x66,0x90}; /* xchg %ax,%ax */
1072 static const char f32_3
[] =
1073 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1074 static const char f32_4
[] =
1075 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1076 static const char f32_5
[] =
1078 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1079 static const char f32_6
[] =
1080 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1081 static const char f32_7
[] =
1082 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1083 static const char f32_8
[] =
1085 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1086 static const char f32_9
[] =
1087 {0x89,0xf6, /* movl %esi,%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1089 static const char f32_10
[] =
1090 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1092 static const char f32_11
[] =
1093 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1094 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1095 static const char f32_12
[] =
1096 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1097 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1098 static const char f32_13
[] =
1099 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1100 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1101 static const char f32_14
[] =
1102 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1103 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1104 static const char f16_3
[] =
1105 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1106 static const char f16_4
[] =
1107 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1108 static const char f16_5
[] =
1110 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1111 static const char f16_6
[] =
1112 {0x89,0xf6, /* mov %si,%si */
1113 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1114 static const char f16_7
[] =
1115 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1116 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1117 static const char f16_8
[] =
1118 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1119 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1120 static const char jump_31
[] =
1121 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1122 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1123 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1124 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1125 static const char *const f32_patt
[] = {
1126 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1127 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1129 static const char *const f16_patt
[] = {
1130 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1132 /* nopl (%[re]ax) */
1133 static const char alt_3
[] =
1135 /* nopl 0(%[re]ax) */
1136 static const char alt_4
[] =
1137 {0x0f,0x1f,0x40,0x00};
1138 /* nopl 0(%[re]ax,%[re]ax,1) */
1139 static const char alt_5
[] =
1140 {0x0f,0x1f,0x44,0x00,0x00};
1141 /* nopw 0(%[re]ax,%[re]ax,1) */
1142 static const char alt_6
[] =
1143 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1144 /* nopl 0L(%[re]ax) */
1145 static const char alt_7
[] =
1146 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1147 /* nopl 0L(%[re]ax,%[re]ax,1) */
1148 static const char alt_8
[] =
1149 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1150 /* nopw 0L(%[re]ax,%[re]ax,1) */
1151 static const char alt_9
[] =
1152 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1154 static const char alt_10
[] =
1155 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 static const char *const alt_patt
[] = {
1157 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1161 /* Only align for at least a positive non-zero boundary. */
1162 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1165 /* We need to decide which NOP sequence to use for 32bit and
1166 64bit. When -mtune= is used:
1168 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1169 PROCESSOR_GENERIC32, f32_patt will be used.
1170 2. For the rest, alt_patt will be used.
1172 When -mtune= isn't used, alt_patt will be used if
1173 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1176 When -march= or .arch is used, we can't use anything beyond
1177 cpu_arch_isa_flags. */
1179 if (flag_code
== CODE_16BIT
)
1183 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1185 /* Adjust jump offset. */
1186 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1189 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1190 f16_patt
[count
- 1], count
);
1194 const char *const *patt
= NULL
;
1196 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1198 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1199 switch (cpu_arch_tune
)
1201 case PROCESSOR_UNKNOWN
:
1202 /* We use cpu_arch_isa_flags to check if we SHOULD
1203 optimize with nops. */
1204 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1209 case PROCESSOR_PENTIUM4
:
1210 case PROCESSOR_NOCONA
:
1211 case PROCESSOR_CORE
:
1212 case PROCESSOR_CORE2
:
1213 case PROCESSOR_COREI7
:
1214 case PROCESSOR_L1OM
:
1215 case PROCESSOR_K1OM
:
1216 case PROCESSOR_GENERIC64
:
1218 case PROCESSOR_ATHLON
:
1220 case PROCESSOR_AMDFAM10
:
1222 case PROCESSOR_ZNVER
:
1226 case PROCESSOR_I386
:
1227 case PROCESSOR_I486
:
1228 case PROCESSOR_PENTIUM
:
1229 case PROCESSOR_PENTIUMPRO
:
1230 case PROCESSOR_IAMCU
:
1231 case PROCESSOR_GENERIC32
:
1238 switch (fragP
->tc_frag_data
.tune
)
1240 case PROCESSOR_UNKNOWN
:
1241 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1242 PROCESSOR_UNKNOWN. */
1246 case PROCESSOR_I386
:
1247 case PROCESSOR_I486
:
1248 case PROCESSOR_PENTIUM
:
1249 case PROCESSOR_IAMCU
:
1251 case PROCESSOR_ATHLON
:
1253 case PROCESSOR_AMDFAM10
:
1255 case PROCESSOR_ZNVER
:
1257 case PROCESSOR_GENERIC32
:
1258 /* We use cpu_arch_isa_flags to check if we CAN optimize
1260 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1265 case PROCESSOR_PENTIUMPRO
:
1266 case PROCESSOR_PENTIUM4
:
1267 case PROCESSOR_NOCONA
:
1268 case PROCESSOR_CORE
:
1269 case PROCESSOR_CORE2
:
1270 case PROCESSOR_COREI7
:
1271 case PROCESSOR_L1OM
:
1272 case PROCESSOR_K1OM
:
1273 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1278 case PROCESSOR_GENERIC64
:
1284 if (patt
== f32_patt
)
1286 /* If the padding is less than 15 bytes, we use the normal
1287 ones. Otherwise, we use a jump instruction and adjust
1291 /* For 64bit, the limit is 3 bytes. */
1292 if (flag_code
== CODE_64BIT
1293 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1298 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1299 patt
[count
- 1], count
);
1302 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1304 /* Adjust jump offset. */
1305 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1310 /* Maximum length of an instruction is 10 byte. If the
1311 padding is greater than 10 bytes and we don't use jump,
1312 we have to break it into smaller pieces. */
1313 int padding
= count
;
1314 while (padding
> 10)
1317 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1322 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1323 patt
[padding
- 1], padding
);
1326 fragP
->fr_var
= count
;
1330 operand_type_all_zero (const union i386_operand_type
*x
)
1332 switch (ARRAY_SIZE(x
->array
))
1341 return !x
->array
[0];
1348 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1350 switch (ARRAY_SIZE(x
->array
))
1365 operand_type_equal (const union i386_operand_type
*x
,
1366 const union i386_operand_type
*y
)
1368 switch (ARRAY_SIZE(x
->array
))
1371 if (x
->array
[2] != y
->array
[2])
1374 if (x
->array
[1] != y
->array
[1])
1377 return x
->array
[0] == y
->array
[0];
1385 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1387 switch (ARRAY_SIZE(x
->array
))
1396 return !x
->array
[0];
1403 cpu_flags_equal (const union i386_cpu_flags
*x
,
1404 const union i386_cpu_flags
*y
)
1406 switch (ARRAY_SIZE(x
->array
))
1409 if (x
->array
[2] != y
->array
[2])
1412 if (x
->array
[1] != y
->array
[1])
1415 return x
->array
[0] == y
->array
[0];
1423 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1425 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1426 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1429 static INLINE i386_cpu_flags
1430 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1432 switch (ARRAY_SIZE (x
.array
))
1435 x
.array
[2] &= y
.array
[2];
1437 x
.array
[1] &= y
.array
[1];
1439 x
.array
[0] &= y
.array
[0];
1447 static INLINE i386_cpu_flags
1448 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1450 switch (ARRAY_SIZE (x
.array
))
1453 x
.array
[2] |= y
.array
[2];
1455 x
.array
[1] |= y
.array
[1];
1457 x
.array
[0] |= y
.array
[0];
1465 static INLINE i386_cpu_flags
1466 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1468 switch (ARRAY_SIZE (x
.array
))
1471 x
.array
[2] &= ~y
.array
[2];
1473 x
.array
[1] &= ~y
.array
[1];
1475 x
.array
[0] &= ~y
.array
[0];
1484 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1486 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1488 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1489 i386_cpu_flags compat_flags
;
1490 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1491 return cpu_flags_all_zero (&compat_flags
);
1497 #define CPU_FLAGS_ARCH_MATCH 0x1
1498 #define CPU_FLAGS_64BIT_MATCH 0x2
1499 #define CPU_FLAGS_AES_MATCH 0x4
1500 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1501 #define CPU_FLAGS_AVX_MATCH 0x10
1503 #define CPU_FLAGS_32BIT_MATCH \
1504 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1505 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1506 #define CPU_FLAGS_PERFECT_MATCH \
1507 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1509 /* Return CPU flags match bits. */
1512 cpu_flags_match (const insn_template
*t
)
1514 i386_cpu_flags x
= t
->cpu_flags
;
1515 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1517 x
.bitfield
.cpu64
= 0;
1518 x
.bitfield
.cpuno64
= 0;
1520 if (cpu_flags_all_zero (&x
))
1522 /* This instruction is available on all archs. */
1523 match
|= CPU_FLAGS_32BIT_MATCH
;
1527 /* This instruction is available only on some archs. */
1528 i386_cpu_flags cpu
= cpu_arch_flags
;
1530 cpu
.bitfield
.cpu64
= 0;
1531 cpu
.bitfield
.cpuno64
= 0;
1532 cpu
= cpu_flags_and (x
, cpu
);
1533 if (!cpu_flags_all_zero (&cpu
))
1535 if (x
.bitfield
.cpuavx
)
1537 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1538 if (cpu
.bitfield
.cpuavx
)
1540 /* Check SSE2AVX. */
1541 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1543 match
|= (CPU_FLAGS_ARCH_MATCH
1544 | CPU_FLAGS_AVX_MATCH
);
1546 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1547 match
|= CPU_FLAGS_AES_MATCH
;
1549 if (!x
.bitfield
.cpupclmul
1550 || cpu
.bitfield
.cpupclmul
)
1551 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1555 match
|= CPU_FLAGS_ARCH_MATCH
;
1558 match
|= CPU_FLAGS_32BIT_MATCH
;
1564 static INLINE i386_operand_type
1565 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1567 switch (ARRAY_SIZE (x
.array
))
1570 x
.array
[2] &= y
.array
[2];
1572 x
.array
[1] &= y
.array
[1];
1574 x
.array
[0] &= y
.array
[0];
1582 static INLINE i386_operand_type
1583 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1585 switch (ARRAY_SIZE (x
.array
))
1588 x
.array
[2] |= y
.array
[2];
1590 x
.array
[1] |= y
.array
[1];
1592 x
.array
[0] |= y
.array
[0];
1600 static INLINE i386_operand_type
1601 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1603 switch (ARRAY_SIZE (x
.array
))
1606 x
.array
[2] ^= y
.array
[2];
1608 x
.array
[1] ^= y
.array
[1];
1610 x
.array
[0] ^= y
.array
[0];
1618 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1619 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1620 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1621 static const i386_operand_type inoutportreg
1622 = OPERAND_TYPE_INOUTPORTREG
;
1623 static const i386_operand_type reg16_inoutportreg
1624 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1625 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1626 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1627 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1628 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1629 static const i386_operand_type anydisp
1630 = OPERAND_TYPE_ANYDISP
;
1631 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1632 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1633 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1634 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1635 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1636 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1637 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1638 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1639 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1640 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1641 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1642 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1643 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1644 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1655 operand_type_check (i386_operand_type t
, enum operand_type c
)
1660 return (t
.bitfield
.reg8
1663 || t
.bitfield
.reg64
);
1666 return (t
.bitfield
.imm8
1670 || t
.bitfield
.imm32s
1671 || t
.bitfield
.imm64
);
1674 return (t
.bitfield
.disp8
1675 || t
.bitfield
.disp16
1676 || t
.bitfield
.disp32
1677 || t
.bitfield
.disp32s
1678 || t
.bitfield
.disp64
);
1681 return (t
.bitfield
.disp8
1682 || t
.bitfield
.disp16
1683 || t
.bitfield
.disp32
1684 || t
.bitfield
.disp32s
1685 || t
.bitfield
.disp64
1686 || t
.bitfield
.baseindex
);
1695 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1696 operand J for instruction template T. */
1699 match_reg_size (const insn_template
*t
, unsigned int j
)
1701 return !((i
.types
[j
].bitfield
.byte
1702 && !t
->operand_types
[j
].bitfield
.byte
)
1703 || (i
.types
[j
].bitfield
.word
1704 && !t
->operand_types
[j
].bitfield
.word
)
1705 || (i
.types
[j
].bitfield
.dword
1706 && !t
->operand_types
[j
].bitfield
.dword
)
1707 || (i
.types
[j
].bitfield
.qword
1708 && !t
->operand_types
[j
].bitfield
.qword
));
1711 /* Return 1 if there is no conflict in any size on operand J for
1712 instruction template T. */
1715 match_mem_size (const insn_template
*t
, unsigned int j
)
1717 return (match_reg_size (t
, j
)
1718 && !((i
.types
[j
].bitfield
.unspecified
1720 && !t
->operand_types
[j
].bitfield
.unspecified
)
1721 || (i
.types
[j
].bitfield
.fword
1722 && !t
->operand_types
[j
].bitfield
.fword
)
1723 || (i
.types
[j
].bitfield
.tbyte
1724 && !t
->operand_types
[j
].bitfield
.tbyte
)
1725 || (i
.types
[j
].bitfield
.xmmword
1726 && !t
->operand_types
[j
].bitfield
.xmmword
)
1727 || (i
.types
[j
].bitfield
.ymmword
1728 && !t
->operand_types
[j
].bitfield
.ymmword
)
1729 || (i
.types
[j
].bitfield
.zmmword
1730 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1733 /* Return 1 if there is no size conflict on any operands for
1734 instruction template T. */
1737 operand_size_match (const insn_template
*t
)
1742 /* Don't check jump instructions. */
1743 if (t
->opcode_modifier
.jump
1744 || t
->opcode_modifier
.jumpbyte
1745 || t
->opcode_modifier
.jumpdword
1746 || t
->opcode_modifier
.jumpintersegment
)
1749 /* Check memory and accumulator operand size. */
1750 for (j
= 0; j
< i
.operands
; j
++)
1752 if (t
->operand_types
[j
].bitfield
.anysize
)
1755 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1761 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1770 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1773 i
.error
= operand_size_mismatch
;
1777 /* Check reverse. */
1778 gas_assert (i
.operands
== 2);
1781 for (j
= 0; j
< 2; j
++)
1783 if (t
->operand_types
[j
].bitfield
.acc
1784 && !match_reg_size (t
, j
? 0 : 1))
1787 if (i
.types
[j
].bitfield
.mem
1788 && !match_mem_size (t
, j
? 0 : 1))
1796 operand_type_match (i386_operand_type overlap
,
1797 i386_operand_type given
)
1799 i386_operand_type temp
= overlap
;
1801 temp
.bitfield
.jumpabsolute
= 0;
1802 temp
.bitfield
.unspecified
= 0;
1803 temp
.bitfield
.byte
= 0;
1804 temp
.bitfield
.word
= 0;
1805 temp
.bitfield
.dword
= 0;
1806 temp
.bitfield
.fword
= 0;
1807 temp
.bitfield
.qword
= 0;
1808 temp
.bitfield
.tbyte
= 0;
1809 temp
.bitfield
.xmmword
= 0;
1810 temp
.bitfield
.ymmword
= 0;
1811 temp
.bitfield
.zmmword
= 0;
1812 if (operand_type_all_zero (&temp
))
1815 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1816 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1820 i
.error
= operand_type_mismatch
;
1824 /* If given types g0 and g1 are registers they must be of the same type
1825 unless the expected operand type register overlap is null.
1826 Note that Acc in a template matches every size of reg. */
1829 operand_type_register_match (i386_operand_type m0
,
1830 i386_operand_type g0
,
1831 i386_operand_type t0
,
1832 i386_operand_type m1
,
1833 i386_operand_type g1
,
1834 i386_operand_type t1
)
1836 if (!operand_type_check (g0
, reg
))
1839 if (!operand_type_check (g1
, reg
))
1842 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1843 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1844 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1845 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1848 if (m0
.bitfield
.acc
)
1850 t0
.bitfield
.reg8
= 1;
1851 t0
.bitfield
.reg16
= 1;
1852 t0
.bitfield
.reg32
= 1;
1853 t0
.bitfield
.reg64
= 1;
1856 if (m1
.bitfield
.acc
)
1858 t1
.bitfield
.reg8
= 1;
1859 t1
.bitfield
.reg16
= 1;
1860 t1
.bitfield
.reg32
= 1;
1861 t1
.bitfield
.reg64
= 1;
1864 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1865 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1866 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1867 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1870 i
.error
= register_type_mismatch
;
1875 static INLINE
unsigned int
1876 register_number (const reg_entry
*r
)
1878 unsigned int nr
= r
->reg_num
;
1880 if (r
->reg_flags
& RegRex
)
1886 static INLINE
unsigned int
1887 mode_from_disp_size (i386_operand_type t
)
1889 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1891 else if (t
.bitfield
.disp16
1892 || t
.bitfield
.disp32
1893 || t
.bitfield
.disp32s
)
1900 fits_in_signed_byte (addressT num
)
1902 return num
+ 0x80 <= 0xff;
1906 fits_in_unsigned_byte (addressT num
)
1912 fits_in_unsigned_word (addressT num
)
1914 return num
<= 0xffff;
1918 fits_in_signed_word (addressT num
)
1920 return num
+ 0x8000 <= 0xffff;
1924 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1929 return num
+ 0x80000000 <= 0xffffffff;
1931 } /* fits_in_signed_long() */
1934 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1939 return num
<= 0xffffffff;
1941 } /* fits_in_unsigned_long() */
1944 fits_in_vec_disp8 (offsetT num
)
1946 int shift
= i
.memshift
;
1952 mask
= (1 << shift
) - 1;
1954 /* Return 0 if NUM isn't properly aligned. */
1958 /* Check if NUM will fit in 8bit after shift. */
1959 return fits_in_signed_byte (num
>> shift
);
1963 fits_in_imm4 (offsetT num
)
1965 return (num
& 0xf) == num
;
1968 static i386_operand_type
1969 smallest_imm_type (offsetT num
)
1971 i386_operand_type t
;
1973 operand_type_set (&t
, 0);
1974 t
.bitfield
.imm64
= 1;
1976 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1978 /* This code is disabled on the 486 because all the Imm1 forms
1979 in the opcode table are slower on the i486. They're the
1980 versions with the implicitly specified single-position
1981 displacement, which has another syntax if you really want to
1983 t
.bitfield
.imm1
= 1;
1984 t
.bitfield
.imm8
= 1;
1985 t
.bitfield
.imm8s
= 1;
1986 t
.bitfield
.imm16
= 1;
1987 t
.bitfield
.imm32
= 1;
1988 t
.bitfield
.imm32s
= 1;
1990 else if (fits_in_signed_byte (num
))
1992 t
.bitfield
.imm8
= 1;
1993 t
.bitfield
.imm8s
= 1;
1994 t
.bitfield
.imm16
= 1;
1995 t
.bitfield
.imm32
= 1;
1996 t
.bitfield
.imm32s
= 1;
1998 else if (fits_in_unsigned_byte (num
))
2000 t
.bitfield
.imm8
= 1;
2001 t
.bitfield
.imm16
= 1;
2002 t
.bitfield
.imm32
= 1;
2003 t
.bitfield
.imm32s
= 1;
2005 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2007 t
.bitfield
.imm16
= 1;
2008 t
.bitfield
.imm32
= 1;
2009 t
.bitfield
.imm32s
= 1;
2011 else if (fits_in_signed_long (num
))
2013 t
.bitfield
.imm32
= 1;
2014 t
.bitfield
.imm32s
= 1;
2016 else if (fits_in_unsigned_long (num
))
2017 t
.bitfield
.imm32
= 1;
2023 offset_in_range (offsetT val
, int size
)
2029 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2030 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2031 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2033 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2039 /* If BFD64, sign extend val for 32bit address mode. */
2040 if (flag_code
!= CODE_64BIT
2041 || i
.prefix
[ADDR_PREFIX
])
2042 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2043 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2046 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2048 char buf1
[40], buf2
[40];
2050 sprint_value (buf1
, val
);
2051 sprint_value (buf2
, val
& mask
);
2052 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2066 a. PREFIX_EXIST if attempting to add a prefix where one from the
2067 same class already exists.
2068 b. PREFIX_LOCK if lock prefix is added.
2069 c. PREFIX_REP if rep/repne prefix is added.
2070 d. PREFIX_OTHER if other prefix is added.
2073 static enum PREFIX_GROUP
2074 add_prefix (unsigned int prefix
)
2076 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2079 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2080 && flag_code
== CODE_64BIT
)
2082 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2083 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2084 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2095 case CS_PREFIX_OPCODE
:
2096 case DS_PREFIX_OPCODE
:
2097 case ES_PREFIX_OPCODE
:
2098 case FS_PREFIX_OPCODE
:
2099 case GS_PREFIX_OPCODE
:
2100 case SS_PREFIX_OPCODE
:
2104 case REPNE_PREFIX_OPCODE
:
2105 case REPE_PREFIX_OPCODE
:
2110 case LOCK_PREFIX_OPCODE
:
2119 case ADDR_PREFIX_OPCODE
:
2123 case DATA_PREFIX_OPCODE
:
2127 if (i
.prefix
[q
] != 0)
2135 i
.prefix
[q
] |= prefix
;
2138 as_bad (_("same type of prefix used twice"));
2144 update_code_flag (int value
, int check
)
2146 PRINTF_LIKE ((*as_error
));
2148 flag_code
= (enum flag_code
) value
;
2149 if (flag_code
== CODE_64BIT
)
2151 cpu_arch_flags
.bitfield
.cpu64
= 1;
2152 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2156 cpu_arch_flags
.bitfield
.cpu64
= 0;
2157 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2159 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2162 as_error
= as_fatal
;
2165 (*as_error
) (_("64bit mode not supported on `%s'."),
2166 cpu_arch_name
? cpu_arch_name
: default_arch
);
2168 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2171 as_error
= as_fatal
;
2174 (*as_error
) (_("32bit mode not supported on `%s'."),
2175 cpu_arch_name
? cpu_arch_name
: default_arch
);
2177 stackop_size
= '\0';
2181 set_code_flag (int value
)
2183 update_code_flag (value
, 0);
2187 set_16bit_gcc_code_flag (int new_code_flag
)
2189 flag_code
= (enum flag_code
) new_code_flag
;
2190 if (flag_code
!= CODE_16BIT
)
2192 cpu_arch_flags
.bitfield
.cpu64
= 0;
2193 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2194 stackop_size
= LONG_MNEM_SUFFIX
;
2198 set_intel_syntax (int syntax_flag
)
2200 /* Find out if register prefixing is specified. */
2201 int ask_naked_reg
= 0;
2204 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2207 int e
= get_symbol_name (&string
);
2209 if (strcmp (string
, "prefix") == 0)
2211 else if (strcmp (string
, "noprefix") == 0)
2214 as_bad (_("bad argument to syntax directive."));
2215 (void) restore_line_pointer (e
);
2217 demand_empty_rest_of_line ();
2219 intel_syntax
= syntax_flag
;
2221 if (ask_naked_reg
== 0)
2222 allow_naked_reg
= (intel_syntax
2223 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2225 allow_naked_reg
= (ask_naked_reg
< 0);
2227 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2229 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2230 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2231 register_prefix
= allow_naked_reg
? "" : "%";
2235 set_intel_mnemonic (int mnemonic_flag
)
2237 intel_mnemonic
= mnemonic_flag
;
2241 set_allow_index_reg (int flag
)
2243 allow_index_reg
= flag
;
2247 set_check (int what
)
2249 enum check_kind
*kind
;
2254 kind
= &operand_check
;
2265 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2268 int e
= get_symbol_name (&string
);
2270 if (strcmp (string
, "none") == 0)
2272 else if (strcmp (string
, "warning") == 0)
2273 *kind
= check_warning
;
2274 else if (strcmp (string
, "error") == 0)
2275 *kind
= check_error
;
2277 as_bad (_("bad argument to %s_check directive."), str
);
2278 (void) restore_line_pointer (e
);
2281 as_bad (_("missing argument for %s_check directive"), str
);
2283 demand_empty_rest_of_line ();
2287 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2288 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2291 static const char *arch
;
2293 /* Intel LIOM is only supported on ELF. */
2299 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2300 use default_arch. */
2301 arch
= cpu_arch_name
;
2303 arch
= default_arch
;
2306 /* If we are targeting Intel MCU, we must enable it. */
2307 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2308 || new_flag
.bitfield
.cpuiamcu
)
2311 /* If we are targeting Intel L1OM, we must enable it. */
2312 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2313 || new_flag
.bitfield
.cpul1om
)
2316 /* If we are targeting Intel K1OM, we must enable it. */
2317 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2318 || new_flag
.bitfield
.cpuk1om
)
2321 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2326 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2330 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2333 int e
= get_symbol_name (&string
);
2335 i386_cpu_flags flags
;
2337 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2339 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2341 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2345 cpu_arch_name
= cpu_arch
[j
].name
;
2346 cpu_sub_arch_name
= NULL
;
2347 cpu_arch_flags
= cpu_arch
[j
].flags
;
2348 if (flag_code
== CODE_64BIT
)
2350 cpu_arch_flags
.bitfield
.cpu64
= 1;
2351 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2355 cpu_arch_flags
.bitfield
.cpu64
= 0;
2356 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2358 cpu_arch_isa
= cpu_arch
[j
].type
;
2359 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2360 if (!cpu_arch_tune_set
)
2362 cpu_arch_tune
= cpu_arch_isa
;
2363 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2368 if (!cpu_arch
[j
].negated
)
2369 flags
= cpu_flags_or (cpu_arch_flags
,
2372 flags
= cpu_flags_and_not (cpu_arch_flags
,
2375 if (!valid_iamcu_cpu_flags (&flags
))
2376 as_fatal (_("`%s' isn't valid for Intel MCU"),
2378 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2380 if (cpu_sub_arch_name
)
2382 char *name
= cpu_sub_arch_name
;
2383 cpu_sub_arch_name
= concat (name
,
2385 (const char *) NULL
);
2389 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2390 cpu_arch_flags
= flags
;
2391 cpu_arch_isa_flags
= flags
;
2393 (void) restore_line_pointer (e
);
2394 demand_empty_rest_of_line ();
2398 if (j
>= ARRAY_SIZE (cpu_arch
))
2399 as_bad (_("no such architecture: `%s'"), string
);
2401 *input_line_pointer
= e
;
2404 as_bad (_("missing cpu architecture"));
2406 no_cond_jump_promotion
= 0;
2407 if (*input_line_pointer
== ','
2408 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2413 ++input_line_pointer
;
2414 e
= get_symbol_name (&string
);
2416 if (strcmp (string
, "nojumps") == 0)
2417 no_cond_jump_promotion
= 1;
2418 else if (strcmp (string
, "jumps") == 0)
2421 as_bad (_("no such architecture modifier: `%s'"), string
);
2423 (void) restore_line_pointer (e
);
2426 demand_empty_rest_of_line ();
2429 enum bfd_architecture
2432 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2434 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2435 || flag_code
!= CODE_64BIT
)
2436 as_fatal (_("Intel L1OM is 64bit ELF only"));
2437 return bfd_arch_l1om
;
2439 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2441 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2442 || flag_code
!= CODE_64BIT
)
2443 as_fatal (_("Intel K1OM is 64bit ELF only"));
2444 return bfd_arch_k1om
;
2446 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2448 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2449 || flag_code
== CODE_64BIT
)
2450 as_fatal (_("Intel MCU is 32bit ELF only"));
2451 return bfd_arch_iamcu
;
2454 return bfd_arch_i386
;
2460 if (!strncmp (default_arch
, "x86_64", 6))
2462 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2464 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2465 || default_arch
[6] != '\0')
2466 as_fatal (_("Intel L1OM is 64bit ELF only"));
2467 return bfd_mach_l1om
;
2469 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2471 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2472 || default_arch
[6] != '\0')
2473 as_fatal (_("Intel K1OM is 64bit ELF only"));
2474 return bfd_mach_k1om
;
2476 else if (default_arch
[6] == '\0')
2477 return bfd_mach_x86_64
;
2479 return bfd_mach_x64_32
;
2481 else if (!strcmp (default_arch
, "i386")
2482 || !strcmp (default_arch
, "iamcu"))
2484 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2486 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2487 as_fatal (_("Intel MCU is 32bit ELF only"));
2488 return bfd_mach_i386_iamcu
;
2491 return bfd_mach_i386_i386
;
2494 as_fatal (_("unknown architecture"));
2500 const char *hash_err
;
2502 /* Initialize op_hash hash table. */
2503 op_hash
= hash_new ();
2506 const insn_template
*optab
;
2507 templates
*core_optab
;
2509 /* Setup for loop. */
2511 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2512 core_optab
->start
= optab
;
2517 if (optab
->name
== NULL
2518 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2520 /* different name --> ship out current template list;
2521 add to hash table; & begin anew. */
2522 core_optab
->end
= optab
;
2523 hash_err
= hash_insert (op_hash
,
2525 (void *) core_optab
);
2528 as_fatal (_("can't hash %s: %s"),
2532 if (optab
->name
== NULL
)
2534 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2535 core_optab
->start
= optab
;
2540 /* Initialize reg_hash hash table. */
2541 reg_hash
= hash_new ();
2543 const reg_entry
*regtab
;
2544 unsigned int regtab_size
= i386_regtab_size
;
2546 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2548 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2550 as_fatal (_("can't hash %s: %s"),
2556 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2561 for (c
= 0; c
< 256; c
++)
2566 mnemonic_chars
[c
] = c
;
2567 register_chars
[c
] = c
;
2568 operand_chars
[c
] = c
;
2570 else if (ISLOWER (c
))
2572 mnemonic_chars
[c
] = c
;
2573 register_chars
[c
] = c
;
2574 operand_chars
[c
] = c
;
2576 else if (ISUPPER (c
))
2578 mnemonic_chars
[c
] = TOLOWER (c
);
2579 register_chars
[c
] = mnemonic_chars
[c
];
2580 operand_chars
[c
] = c
;
2582 else if (c
== '{' || c
== '}')
2583 operand_chars
[c
] = c
;
2585 if (ISALPHA (c
) || ISDIGIT (c
))
2586 identifier_chars
[c
] = c
;
2589 identifier_chars
[c
] = c
;
2590 operand_chars
[c
] = c
;
2595 identifier_chars
['@'] = '@';
2598 identifier_chars
['?'] = '?';
2599 operand_chars
['?'] = '?';
2601 digit_chars
['-'] = '-';
2602 mnemonic_chars
['_'] = '_';
2603 mnemonic_chars
['-'] = '-';
2604 mnemonic_chars
['.'] = '.';
2605 identifier_chars
['_'] = '_';
2606 identifier_chars
['.'] = '.';
2608 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2609 operand_chars
[(unsigned char) *p
] = *p
;
2612 if (flag_code
== CODE_64BIT
)
2614 #if defined (OBJ_COFF) && defined (TE_PE)
2615 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2618 x86_dwarf2_return_column
= 16;
2620 x86_cie_data_alignment
= -8;
2624 x86_dwarf2_return_column
= 8;
2625 x86_cie_data_alignment
= -4;
2630 i386_print_statistics (FILE *file
)
2632 hash_print_statistics (file
, "i386 opcode", op_hash
);
2633 hash_print_statistics (file
, "i386 register", reg_hash
);
2638 /* Debugging routines for md_assemble. */
2639 static void pte (insn_template
*);
2640 static void pt (i386_operand_type
);
2641 static void pe (expressionS
*);
2642 static void ps (symbolS
*);
2645 pi (char *line
, i386_insn
*x
)
2649 fprintf (stdout
, "%s: template ", line
);
2651 fprintf (stdout
, " address: base %s index %s scale %x\n",
2652 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2653 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2654 x
->log2_scale_factor
);
2655 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2656 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2657 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2658 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2659 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2660 (x
->rex
& REX_W
) != 0,
2661 (x
->rex
& REX_R
) != 0,
2662 (x
->rex
& REX_X
) != 0,
2663 (x
->rex
& REX_B
) != 0);
2664 for (j
= 0; j
< x
->operands
; j
++)
2666 fprintf (stdout
, " #%d: ", j
+ 1);
2668 fprintf (stdout
, "\n");
2669 if (x
->types
[j
].bitfield
.reg8
2670 || x
->types
[j
].bitfield
.reg16
2671 || x
->types
[j
].bitfield
.reg32
2672 || x
->types
[j
].bitfield
.reg64
2673 || x
->types
[j
].bitfield
.regmmx
2674 || x
->types
[j
].bitfield
.regxmm
2675 || x
->types
[j
].bitfield
.regymm
2676 || x
->types
[j
].bitfield
.regzmm
2677 || x
->types
[j
].bitfield
.sreg2
2678 || x
->types
[j
].bitfield
.sreg3
2679 || x
->types
[j
].bitfield
.control
2680 || x
->types
[j
].bitfield
.debug
2681 || x
->types
[j
].bitfield
.test
)
2682 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2683 if (operand_type_check (x
->types
[j
], imm
))
2685 if (operand_type_check (x
->types
[j
], disp
))
2686 pe (x
->op
[j
].disps
);
2691 pte (insn_template
*t
)
2694 fprintf (stdout
, " %d operands ", t
->operands
);
2695 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2696 if (t
->extension_opcode
!= None
)
2697 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2698 if (t
->opcode_modifier
.d
)
2699 fprintf (stdout
, "D");
2700 if (t
->opcode_modifier
.w
)
2701 fprintf (stdout
, "W");
2702 fprintf (stdout
, "\n");
2703 for (j
= 0; j
< t
->operands
; j
++)
2705 fprintf (stdout
, " #%d type ", j
+ 1);
2706 pt (t
->operand_types
[j
]);
2707 fprintf (stdout
, "\n");
2714 fprintf (stdout
, " operation %d\n", e
->X_op
);
2715 fprintf (stdout
, " add_number %ld (%lx)\n",
2716 (long) e
->X_add_number
, (long) e
->X_add_number
);
2717 if (e
->X_add_symbol
)
2719 fprintf (stdout
, " add_symbol ");
2720 ps (e
->X_add_symbol
);
2721 fprintf (stdout
, "\n");
2725 fprintf (stdout
, " op_symbol ");
2726 ps (e
->X_op_symbol
);
2727 fprintf (stdout
, "\n");
2734 fprintf (stdout
, "%s type %s%s",
2736 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2737 segment_name (S_GET_SEGMENT (s
)));
2740 static struct type_name
2742 i386_operand_type mask
;
2745 const type_names
[] =
2747 { OPERAND_TYPE_REG8
, "r8" },
2748 { OPERAND_TYPE_REG16
, "r16" },
2749 { OPERAND_TYPE_REG32
, "r32" },
2750 { OPERAND_TYPE_REG64
, "r64" },
2751 { OPERAND_TYPE_IMM8
, "i8" },
2752 { OPERAND_TYPE_IMM8
, "i8s" },
2753 { OPERAND_TYPE_IMM16
, "i16" },
2754 { OPERAND_TYPE_IMM32
, "i32" },
2755 { OPERAND_TYPE_IMM32S
, "i32s" },
2756 { OPERAND_TYPE_IMM64
, "i64" },
2757 { OPERAND_TYPE_IMM1
, "i1" },
2758 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2759 { OPERAND_TYPE_DISP8
, "d8" },
2760 { OPERAND_TYPE_DISP16
, "d16" },
2761 { OPERAND_TYPE_DISP32
, "d32" },
2762 { OPERAND_TYPE_DISP32S
, "d32s" },
2763 { OPERAND_TYPE_DISP64
, "d64" },
2764 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2765 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2766 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2767 { OPERAND_TYPE_CONTROL
, "control reg" },
2768 { OPERAND_TYPE_TEST
, "test reg" },
2769 { OPERAND_TYPE_DEBUG
, "debug reg" },
2770 { OPERAND_TYPE_FLOATREG
, "FReg" },
2771 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2772 { OPERAND_TYPE_SREG2
, "SReg2" },
2773 { OPERAND_TYPE_SREG3
, "SReg3" },
2774 { OPERAND_TYPE_ACC
, "Acc" },
2775 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2776 { OPERAND_TYPE_REGMMX
, "rMMX" },
2777 { OPERAND_TYPE_REGXMM
, "rXMM" },
2778 { OPERAND_TYPE_REGYMM
, "rYMM" },
2779 { OPERAND_TYPE_REGZMM
, "rZMM" },
2780 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2781 { OPERAND_TYPE_ESSEG
, "es" },
2785 pt (i386_operand_type t
)
2788 i386_operand_type a
;
2790 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2792 a
= operand_type_and (t
, type_names
[j
].mask
);
2793 if (!operand_type_all_zero (&a
))
2794 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2799 #endif /* DEBUG386 */
2801 static bfd_reloc_code_real_type
2802 reloc (unsigned int size
,
2805 bfd_reloc_code_real_type other
)
2807 if (other
!= NO_RELOC
)
2809 reloc_howto_type
*rel
;
2814 case BFD_RELOC_X86_64_GOT32
:
2815 return BFD_RELOC_X86_64_GOT64
;
2817 case BFD_RELOC_X86_64_GOTPLT64
:
2818 return BFD_RELOC_X86_64_GOTPLT64
;
2820 case BFD_RELOC_X86_64_PLTOFF64
:
2821 return BFD_RELOC_X86_64_PLTOFF64
;
2823 case BFD_RELOC_X86_64_GOTPC32
:
2824 other
= BFD_RELOC_X86_64_GOTPC64
;
2826 case BFD_RELOC_X86_64_GOTPCREL
:
2827 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2829 case BFD_RELOC_X86_64_TPOFF32
:
2830 other
= BFD_RELOC_X86_64_TPOFF64
;
2832 case BFD_RELOC_X86_64_DTPOFF32
:
2833 other
= BFD_RELOC_X86_64_DTPOFF64
;
2839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2840 if (other
== BFD_RELOC_SIZE32
)
2843 other
= BFD_RELOC_SIZE64
;
2846 as_bad (_("there are no pc-relative size relocations"));
2852 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2853 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2856 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2858 as_bad (_("unknown relocation (%u)"), other
);
2859 else if (size
!= bfd_get_reloc_size (rel
))
2860 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2861 bfd_get_reloc_size (rel
),
2863 else if (pcrel
&& !rel
->pc_relative
)
2864 as_bad (_("non-pc-relative relocation for pc-relative field"));
2865 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2867 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2869 as_bad (_("relocated field and relocation type differ in signedness"));
2878 as_bad (_("there are no unsigned pc-relative relocations"));
2881 case 1: return BFD_RELOC_8_PCREL
;
2882 case 2: return BFD_RELOC_16_PCREL
;
2883 case 4: return BFD_RELOC_32_PCREL
;
2884 case 8: return BFD_RELOC_64_PCREL
;
2886 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2893 case 4: return BFD_RELOC_X86_64_32S
;
2898 case 1: return BFD_RELOC_8
;
2899 case 2: return BFD_RELOC_16
;
2900 case 4: return BFD_RELOC_32
;
2901 case 8: return BFD_RELOC_64
;
2903 as_bad (_("cannot do %s %u byte relocation"),
2904 sign
> 0 ? "signed" : "unsigned", size
);
2910 /* Here we decide which fixups can be adjusted to make them relative to
2911 the beginning of the section instead of the symbol. Basically we need
2912 to make sure that the dynamic relocations are done correctly, so in
2913 some cases we force the original symbol to be used. */
2916 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2922 /* Don't adjust pc-relative references to merge sections in 64-bit
2924 if (use_rela_relocations
2925 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2929 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2930 and changed later by validate_fix. */
2931 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2932 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2935 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2936 for size relocations. */
2937 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2938 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2939 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2940 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2942 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2944 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2945 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2946 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2947 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2948 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2949 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2950 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2951 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2952 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2959 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2960 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2961 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2962 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2963 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2964 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2965 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2966 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2967 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2968 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2969 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2976 intel_float_operand (const char *mnemonic
)
2978 /* Note that the value returned is meaningful only for opcodes with (memory)
2979 operands, hence the code here is free to improperly handle opcodes that
2980 have no operands (for better performance and smaller code). */
2982 if (mnemonic
[0] != 'f')
2983 return 0; /* non-math */
2985 switch (mnemonic
[1])
2987 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2988 the fs segment override prefix not currently handled because no
2989 call path can make opcodes without operands get here */
2991 return 2 /* integer op */;
2993 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2994 return 3; /* fldcw/fldenv */
2997 if (mnemonic
[2] != 'o' /* fnop */)
2998 return 3; /* non-waiting control op */
3001 if (mnemonic
[2] == 's')
3002 return 3; /* frstor/frstpm */
3005 if (mnemonic
[2] == 'a')
3006 return 3; /* fsave */
3007 if (mnemonic
[2] == 't')
3009 switch (mnemonic
[3])
3011 case 'c': /* fstcw */
3012 case 'd': /* fstdw */
3013 case 'e': /* fstenv */
3014 case 's': /* fsts[gw] */
3020 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3021 return 0; /* fxsave/fxrstor are not really math ops */
3028 /* Build the VEX prefix. */
3031 build_vex_prefix (const insn_template
*t
)
3033 unsigned int register_specifier
;
3034 unsigned int implied_prefix
;
3035 unsigned int vector_length
;
3037 /* Check register specifier. */
3038 if (i
.vex
.register_specifier
)
3040 register_specifier
=
3041 ~register_number (i
.vex
.register_specifier
) & 0xf;
3042 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3045 register_specifier
= 0xf;
3047 /* Use 2-byte VEX prefix by swappping destination and source
3050 && i
.operands
== i
.reg_operands
3051 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3052 && i
.tm
.opcode_modifier
.s
3055 unsigned int xchg
= i
.operands
- 1;
3056 union i386_op temp_op
;
3057 i386_operand_type temp_type
;
3059 temp_type
= i
.types
[xchg
];
3060 i
.types
[xchg
] = i
.types
[0];
3061 i
.types
[0] = temp_type
;
3062 temp_op
= i
.op
[xchg
];
3063 i
.op
[xchg
] = i
.op
[0];
3066 gas_assert (i
.rm
.mode
== 3);
3070 i
.rm
.regmem
= i
.rm
.reg
;
3073 /* Use the next insn. */
3077 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3078 vector_length
= avxscalar
;
3080 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3082 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3087 case DATA_PREFIX_OPCODE
:
3090 case REPE_PREFIX_OPCODE
:
3093 case REPNE_PREFIX_OPCODE
:
3100 /* Use 2-byte VEX prefix if possible. */
3101 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3102 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3103 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3105 /* 2-byte VEX prefix. */
3109 i
.vex
.bytes
[0] = 0xc5;
3111 /* Check the REX.R bit. */
3112 r
= (i
.rex
& REX_R
) ? 0 : 1;
3113 i
.vex
.bytes
[1] = (r
<< 7
3114 | register_specifier
<< 3
3115 | vector_length
<< 2
3120 /* 3-byte VEX prefix. */
3125 switch (i
.tm
.opcode_modifier
.vexopcode
)
3129 i
.vex
.bytes
[0] = 0xc4;
3133 i
.vex
.bytes
[0] = 0xc4;
3137 i
.vex
.bytes
[0] = 0xc4;
3141 i
.vex
.bytes
[0] = 0x8f;
3145 i
.vex
.bytes
[0] = 0x8f;
3149 i
.vex
.bytes
[0] = 0x8f;
3155 /* The high 3 bits of the second VEX byte are 1's compliment
3156 of RXB bits from REX. */
3157 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3159 /* Check the REX.W bit. */
3160 w
= (i
.rex
& REX_W
) ? 1 : 0;
3161 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3164 i
.vex
.bytes
[2] = (w
<< 7
3165 | register_specifier
<< 3
3166 | vector_length
<< 2
3171 /* Build the EVEX prefix. */
3174 build_evex_prefix (void)
3176 unsigned int register_specifier
;
3177 unsigned int implied_prefix
;
3179 rex_byte vrex_used
= 0;
3181 /* Check register specifier. */
3182 if (i
.vex
.register_specifier
)
3184 gas_assert ((i
.vrex
& REX_X
) == 0);
3186 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3187 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3188 register_specifier
+= 8;
3189 /* The upper 16 registers are encoded in the fourth byte of the
3191 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3192 i
.vex
.bytes
[3] = 0x8;
3193 register_specifier
= ~register_specifier
& 0xf;
3197 register_specifier
= 0xf;
3199 /* Encode upper 16 vector index register in the fourth byte of
3201 if (!(i
.vrex
& REX_X
))
3202 i
.vex
.bytes
[3] = 0x8;
3207 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3212 case DATA_PREFIX_OPCODE
:
3215 case REPE_PREFIX_OPCODE
:
3218 case REPNE_PREFIX_OPCODE
:
3225 /* 4 byte EVEX prefix. */
3227 i
.vex
.bytes
[0] = 0x62;
3230 switch (i
.tm
.opcode_modifier
.vexopcode
)
3246 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3248 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3250 /* The fifth bit of the second EVEX byte is 1's compliment of the
3251 REX_R bit in VREX. */
3252 if (!(i
.vrex
& REX_R
))
3253 i
.vex
.bytes
[1] |= 0x10;
3257 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3259 /* When all operands are registers, the REX_X bit in REX is not
3260 used. We reuse it to encode the upper 16 registers, which is
3261 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3262 as 1's compliment. */
3263 if ((i
.vrex
& REX_B
))
3266 i
.vex
.bytes
[1] &= ~0x40;
3270 /* EVEX instructions shouldn't need the REX prefix. */
3271 i
.vrex
&= ~vrex_used
;
3272 gas_assert (i
.vrex
== 0);
3274 /* Check the REX.W bit. */
3275 w
= (i
.rex
& REX_W
) ? 1 : 0;
3276 if (i
.tm
.opcode_modifier
.vexw
)
3278 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3281 /* If w is not set it means we are dealing with WIG instruction. */
3284 if (evexwig
== evexw1
)
3288 /* Encode the U bit. */
3289 implied_prefix
|= 0x4;
3291 /* The third byte of the EVEX prefix. */
3292 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3294 /* The fourth byte of the EVEX prefix. */
3295 /* The zeroing-masking bit. */
3296 if (i
.mask
&& i
.mask
->zeroing
)
3297 i
.vex
.bytes
[3] |= 0x80;
3299 /* Don't always set the broadcast bit if there is no RC. */
3302 /* Encode the vector length. */
3303 unsigned int vec_length
;
3305 switch (i
.tm
.opcode_modifier
.evex
)
3307 case EVEXLIG
: /* LL' is ignored */
3308 vec_length
= evexlig
<< 5;
3311 vec_length
= 0 << 5;
3314 vec_length
= 1 << 5;
3317 vec_length
= 2 << 5;
3323 i
.vex
.bytes
[3] |= vec_length
;
3324 /* Encode the broadcast bit. */
3326 i
.vex
.bytes
[3] |= 0x10;
3330 if (i
.rounding
->type
!= saeonly
)
3331 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3333 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3336 if (i
.mask
&& i
.mask
->mask
)
3337 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3341 process_immext (void)
3345 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3348 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3349 with an opcode suffix which is coded in the same place as an
3350 8-bit immediate field would be.
3351 Here we check those operands and remove them afterwards. */
3354 for (x
= 0; x
< i
.operands
; x
++)
3355 if (register_number (i
.op
[x
].regs
) != x
)
3356 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3357 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3363 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3365 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3366 suffix which is coded in the same place as an 8-bit immediate
3368 Here we check those operands and remove them afterwards. */
3371 if (i
.operands
!= 3)
3374 for (x
= 0; x
< 2; x
++)
3375 if (register_number (i
.op
[x
].regs
) != x
)
3376 goto bad_register_operand
;
3378 /* Check for third operand for mwaitx/monitorx insn. */
3379 if (register_number (i
.op
[x
].regs
)
3380 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3382 bad_register_operand
:
3383 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3384 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3391 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3392 which is coded in the same place as an 8-bit immediate field
3393 would be. Here we fake an 8-bit immediate operand from the
3394 opcode suffix stored in tm.extension_opcode.
3396 AVX instructions also use this encoding, for some of
3397 3 argument instructions. */
3399 gas_assert (i
.imm_operands
<= 1
3401 || ((i
.tm
.opcode_modifier
.vex
3402 || i
.tm
.opcode_modifier
.evex
)
3403 && i
.operands
<= 4)));
3405 exp
= &im_expressions
[i
.imm_operands
++];
3406 i
.op
[i
.operands
].imms
= exp
;
3407 i
.types
[i
.operands
] = imm8
;
3409 exp
->X_op
= O_constant
;
3410 exp
->X_add_number
= i
.tm
.extension_opcode
;
3411 i
.tm
.extension_opcode
= None
;
3418 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3423 as_bad (_("invalid instruction `%s' after `%s'"),
3424 i
.tm
.name
, i
.hle_prefix
);
3427 if (i
.prefix
[LOCK_PREFIX
])
3429 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3433 case HLEPrefixRelease
:
3434 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3436 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3440 if (i
.mem_operands
== 0
3441 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3443 as_bad (_("memory destination needed for instruction `%s'"
3444 " after `xrelease'"), i
.tm
.name
);
3451 /* This is the guts of the machine-dependent assembler. LINE points to a
3452 machine dependent instruction. This function is supposed to emit
3453 the frags/bytes it assembles to. */
3456 md_assemble (char *line
)
3459 char mnemonic
[MAX_MNEM_SIZE
];
3460 const insn_template
*t
;
3462 /* Initialize globals. */
3463 memset (&i
, '\0', sizeof (i
));
3464 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3465 i
.reloc
[j
] = NO_RELOC
;
3466 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3467 memset (im_expressions
, '\0', sizeof (im_expressions
));
3468 save_stack_p
= save_stack
;
3470 /* First parse an instruction mnemonic & call i386_operand for the operands.
3471 We assume that the scrubber has arranged it so that line[0] is the valid
3472 start of a (possibly prefixed) mnemonic. */
3474 line
= parse_insn (line
, mnemonic
);
3478 line
= parse_operands (line
, mnemonic
);
3483 /* Now we've parsed the mnemonic into a set of templates, and have the
3484 operands at hand. */
3486 /* All intel opcodes have reversed operands except for "bound" and
3487 "enter". We also don't reverse intersegment "jmp" and "call"
3488 instructions with 2 immediate operands so that the immediate segment
3489 precedes the offset, as it does when in AT&T mode. */
3492 && (strcmp (mnemonic
, "bound") != 0)
3493 && (strcmp (mnemonic
, "invlpga") != 0)
3494 && !(operand_type_check (i
.types
[0], imm
)
3495 && operand_type_check (i
.types
[1], imm
)))
3498 /* The order of the immediates should be reversed
3499 for 2 immediates extrq and insertq instructions */
3500 if (i
.imm_operands
== 2
3501 && (strcmp (mnemonic
, "extrq") == 0
3502 || strcmp (mnemonic
, "insertq") == 0))
3503 swap_2_operands (0, 1);
3508 /* Don't optimize displacement for movabs since it only takes 64bit
3511 && i
.disp_encoding
!= disp_encoding_32bit
3512 && (flag_code
!= CODE_64BIT
3513 || strcmp (mnemonic
, "movabs") != 0))
3516 /* Next, we find a template that matches the given insn,
3517 making sure the overlap of the given operands types is consistent
3518 with the template operand types. */
3520 if (!(t
= match_template ()))
3523 if (sse_check
!= check_none
3524 && !i
.tm
.opcode_modifier
.noavx
3525 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3526 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3527 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3528 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3529 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3530 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3532 (sse_check
== check_warning
3534 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3537 /* Zap movzx and movsx suffix. The suffix has been set from
3538 "word ptr" or "byte ptr" on the source operand in Intel syntax
3539 or extracted from mnemonic in AT&T syntax. But we'll use
3540 the destination register to choose the suffix for encoding. */
3541 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3543 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3544 there is no suffix, the default will be byte extension. */
3545 if (i
.reg_operands
!= 2
3548 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3553 if (i
.tm
.opcode_modifier
.fwait
)
3554 if (!add_prefix (FWAIT_OPCODE
))
3557 /* Check if REP prefix is OK. */
3558 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3560 as_bad (_("invalid instruction `%s' after `%s'"),
3561 i
.tm
.name
, i
.rep_prefix
);
3565 /* Check for lock without a lockable instruction. Destination operand
3566 must be memory unless it is xchg (0x86). */
3567 if (i
.prefix
[LOCK_PREFIX
]
3568 && (!i
.tm
.opcode_modifier
.islockable
3569 || i
.mem_operands
== 0
3570 || (i
.tm
.base_opcode
!= 0x86
3571 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3573 as_bad (_("expecting lockable instruction after `lock'"));
3577 /* Check if HLE prefix is OK. */
3578 if (i
.hle_prefix
&& !check_hle ())
3581 /* Check BND prefix. */
3582 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3583 as_bad (_("expecting valid branch instruction after `bnd'"));
3585 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3586 && flag_code
== CODE_64BIT
3587 && i
.prefix
[ADDR_PREFIX
])
3588 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3590 /* Insert BND prefix. */
3592 && i
.tm
.opcode_modifier
.bndprefixok
3593 && !i
.prefix
[BND_PREFIX
])
3594 add_prefix (BND_PREFIX_OPCODE
);
3596 /* Check string instruction segment overrides. */
3597 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3599 if (!check_string ())
3601 i
.disp_operands
= 0;
3604 if (!process_suffix ())
3607 /* Update operand types. */
3608 for (j
= 0; j
< i
.operands
; j
++)
3609 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3611 /* Make still unresolved immediate matches conform to size of immediate
3612 given in i.suffix. */
3613 if (!finalize_imm ())
3616 if (i
.types
[0].bitfield
.imm1
)
3617 i
.imm_operands
= 0; /* kludge for shift insns. */
3619 /* We only need to check those implicit registers for instructions
3620 with 3 operands or less. */
3621 if (i
.operands
<= 3)
3622 for (j
= 0; j
< i
.operands
; j
++)
3623 if (i
.types
[j
].bitfield
.inoutportreg
3624 || i
.types
[j
].bitfield
.shiftcount
3625 || i
.types
[j
].bitfield
.acc
3626 || i
.types
[j
].bitfield
.floatacc
)
3629 /* ImmExt should be processed after SSE2AVX. */
3630 if (!i
.tm
.opcode_modifier
.sse2avx
3631 && i
.tm
.opcode_modifier
.immext
)
3634 /* For insns with operands there are more diddles to do to the opcode. */
3637 if (!process_operands ())
3640 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3642 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3643 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3646 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3648 if (flag_code
== CODE_16BIT
)
3650 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3655 if (i
.tm
.opcode_modifier
.vex
)
3656 build_vex_prefix (t
);
3658 build_evex_prefix ();
3661 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3662 instructions may define INT_OPCODE as well, so avoid this corner
3663 case for those instructions that use MODRM. */
3664 if (i
.tm
.base_opcode
== INT_OPCODE
3665 && !i
.tm
.opcode_modifier
.modrm
3666 && i
.op
[0].imms
->X_add_number
== 3)
3668 i
.tm
.base_opcode
= INT3_OPCODE
;
3672 if ((i
.tm
.opcode_modifier
.jump
3673 || i
.tm
.opcode_modifier
.jumpbyte
3674 || i
.tm
.opcode_modifier
.jumpdword
)
3675 && i
.op
[0].disps
->X_op
== O_constant
)
3677 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3678 the absolute address given by the constant. Since ix86 jumps and
3679 calls are pc relative, we need to generate a reloc. */
3680 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3681 i
.op
[0].disps
->X_op
= O_symbol
;
3684 if (i
.tm
.opcode_modifier
.rex64
)
3687 /* For 8 bit registers we need an empty rex prefix. Also if the
3688 instruction already has a prefix, we need to convert old
3689 registers to new ones. */
3691 if ((i
.types
[0].bitfield
.reg8
3692 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3693 || (i
.types
[1].bitfield
.reg8
3694 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3695 || ((i
.types
[0].bitfield
.reg8
3696 || i
.types
[1].bitfield
.reg8
)
3701 i
.rex
|= REX_OPCODE
;
3702 for (x
= 0; x
< 2; x
++)
3704 /* Look for 8 bit operand that uses old registers. */
3705 if (i
.types
[x
].bitfield
.reg8
3706 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3708 /* In case it is "hi" register, give up. */
3709 if (i
.op
[x
].regs
->reg_num
> 3)
3710 as_bad (_("can't encode register '%s%s' in an "
3711 "instruction requiring REX prefix."),
3712 register_prefix
, i
.op
[x
].regs
->reg_name
);
3714 /* Otherwise it is equivalent to the extended register.
3715 Since the encoding doesn't change this is merely
3716 cosmetic cleanup for debug output. */
3718 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3724 add_prefix (REX_OPCODE
| i
.rex
);
3726 /* We are ready to output the insn. */
3731 parse_insn (char *line
, char *mnemonic
)
3734 char *token_start
= l
;
3737 const insn_template
*t
;
3743 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3748 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3750 as_bad (_("no such instruction: `%s'"), token_start
);
3755 if (!is_space_char (*l
)
3756 && *l
!= END_OF_INSN
3758 || (*l
!= PREFIX_SEPARATOR
3761 as_bad (_("invalid character %s in mnemonic"),
3762 output_invalid (*l
));
3765 if (token_start
== l
)
3767 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3768 as_bad (_("expecting prefix; got nothing"));
3770 as_bad (_("expecting mnemonic; got nothing"));
3774 /* Look up instruction (or prefix) via hash table. */
3775 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3777 if (*l
!= END_OF_INSN
3778 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3779 && current_templates
3780 && current_templates
->start
->opcode_modifier
.isprefix
)
3782 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3784 as_bad ((flag_code
!= CODE_64BIT
3785 ? _("`%s' is only supported in 64-bit mode")
3786 : _("`%s' is not supported in 64-bit mode")),
3787 current_templates
->start
->name
);
3790 /* If we are in 16-bit mode, do not allow addr16 or data16.
3791 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3792 if ((current_templates
->start
->opcode_modifier
.size16
3793 || current_templates
->start
->opcode_modifier
.size32
)
3794 && flag_code
!= CODE_64BIT
3795 && (current_templates
->start
->opcode_modifier
.size32
3796 ^ (flag_code
== CODE_16BIT
)))
3798 as_bad (_("redundant %s prefix"),
3799 current_templates
->start
->name
);
3802 /* Add prefix, checking for repeated prefixes. */
3803 switch (add_prefix (current_templates
->start
->base_opcode
))
3808 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3809 i
.hle_prefix
= current_templates
->start
->name
;
3810 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3811 i
.bnd_prefix
= current_templates
->start
->name
;
3813 i
.rep_prefix
= current_templates
->start
->name
;
3818 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3825 if (!current_templates
)
3827 /* Check if we should swap operand or force 32bit displacement in
3829 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3831 else if (mnem_p
- 3 == dot_p
3834 i
.disp_encoding
= disp_encoding_8bit
;
3835 else if (mnem_p
- 4 == dot_p
3839 i
.disp_encoding
= disp_encoding_32bit
;
3844 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3847 if (!current_templates
)
3850 /* See if we can get a match by trimming off a suffix. */
3853 case WORD_MNEM_SUFFIX
:
3854 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3855 i
.suffix
= SHORT_MNEM_SUFFIX
;
3857 case BYTE_MNEM_SUFFIX
:
3858 case QWORD_MNEM_SUFFIX
:
3859 i
.suffix
= mnem_p
[-1];
3861 current_templates
= (const templates
*) hash_find (op_hash
,
3864 case SHORT_MNEM_SUFFIX
:
3865 case LONG_MNEM_SUFFIX
:
3868 i
.suffix
= mnem_p
[-1];
3870 current_templates
= (const templates
*) hash_find (op_hash
,
3879 if (intel_float_operand (mnemonic
) == 1)
3880 i
.suffix
= SHORT_MNEM_SUFFIX
;
3882 i
.suffix
= LONG_MNEM_SUFFIX
;
3884 current_templates
= (const templates
*) hash_find (op_hash
,
3889 if (!current_templates
)
3891 as_bad (_("no such instruction: `%s'"), token_start
);
3896 if (current_templates
->start
->opcode_modifier
.jump
3897 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3899 /* Check for a branch hint. We allow ",pt" and ",pn" for
3900 predict taken and predict not taken respectively.
3901 I'm not sure that branch hints actually do anything on loop
3902 and jcxz insns (JumpByte) for current Pentium4 chips. They
3903 may work in the future and it doesn't hurt to accept them
3905 if (l
[0] == ',' && l
[1] == 'p')
3909 if (!add_prefix (DS_PREFIX_OPCODE
))
3913 else if (l
[2] == 'n')
3915 if (!add_prefix (CS_PREFIX_OPCODE
))
3921 /* Any other comma loses. */
3924 as_bad (_("invalid character %s in mnemonic"),
3925 output_invalid (*l
));
3929 /* Check if instruction is supported on specified architecture. */
3931 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3933 supported
|= cpu_flags_match (t
);
3934 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3938 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3940 as_bad (flag_code
== CODE_64BIT
3941 ? _("`%s' is not supported in 64-bit mode")
3942 : _("`%s' is only supported in 64-bit mode"),
3943 current_templates
->start
->name
);
3946 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3948 as_bad (_("`%s' is not supported on `%s%s'"),
3949 current_templates
->start
->name
,
3950 cpu_arch_name
? cpu_arch_name
: default_arch
,
3951 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3956 if (!cpu_arch_flags
.bitfield
.cpui386
3957 && (flag_code
!= CODE_16BIT
))
3959 as_warn (_("use .code16 to ensure correct addressing mode"));
3966 parse_operands (char *l
, const char *mnemonic
)
3970 /* 1 if operand is pending after ','. */
3971 unsigned int expecting_operand
= 0;
3973 /* Non-zero if operand parens not balanced. */
3974 unsigned int paren_not_balanced
;
3976 while (*l
!= END_OF_INSN
)
3978 /* Skip optional white space before operand. */
3979 if (is_space_char (*l
))
3981 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3983 as_bad (_("invalid character %s before operand %d"),
3984 output_invalid (*l
),
3988 token_start
= l
; /* After white space. */
3989 paren_not_balanced
= 0;
3990 while (paren_not_balanced
|| *l
!= ',')
3992 if (*l
== END_OF_INSN
)
3994 if (paren_not_balanced
)
3997 as_bad (_("unbalanced parenthesis in operand %d."),
4000 as_bad (_("unbalanced brackets in operand %d."),
4005 break; /* we are done */
4007 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4009 as_bad (_("invalid character %s in operand %d"),
4010 output_invalid (*l
),
4017 ++paren_not_balanced
;
4019 --paren_not_balanced
;
4024 ++paren_not_balanced
;
4026 --paren_not_balanced
;
4030 if (l
!= token_start
)
4031 { /* Yes, we've read in another operand. */
4032 unsigned int operand_ok
;
4033 this_operand
= i
.operands
++;
4034 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4035 if (i
.operands
> MAX_OPERANDS
)
4037 as_bad (_("spurious operands; (%d operands/instruction max)"),
4041 /* Now parse operand adding info to 'i' as we go along. */
4042 END_STRING_AND_SAVE (l
);
4046 i386_intel_operand (token_start
,
4047 intel_float_operand (mnemonic
));
4049 operand_ok
= i386_att_operand (token_start
);
4051 RESTORE_END_STRING (l
);
4057 if (expecting_operand
)
4059 expecting_operand_after_comma
:
4060 as_bad (_("expecting operand after ','; got nothing"));
4065 as_bad (_("expecting operand before ','; got nothing"));
4070 /* Now *l must be either ',' or END_OF_INSN. */
4073 if (*++l
== END_OF_INSN
)
4075 /* Just skip it, if it's \n complain. */
4076 goto expecting_operand_after_comma
;
4078 expecting_operand
= 1;
4085 swap_2_operands (int xchg1
, int xchg2
)
4087 union i386_op temp_op
;
4088 i386_operand_type temp_type
;
4089 enum bfd_reloc_code_real temp_reloc
;
4091 temp_type
= i
.types
[xchg2
];
4092 i
.types
[xchg2
] = i
.types
[xchg1
];
4093 i
.types
[xchg1
] = temp_type
;
4094 temp_op
= i
.op
[xchg2
];
4095 i
.op
[xchg2
] = i
.op
[xchg1
];
4096 i
.op
[xchg1
] = temp_op
;
4097 temp_reloc
= i
.reloc
[xchg2
];
4098 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4099 i
.reloc
[xchg1
] = temp_reloc
;
4103 if (i
.mask
->operand
== xchg1
)
4104 i
.mask
->operand
= xchg2
;
4105 else if (i
.mask
->operand
== xchg2
)
4106 i
.mask
->operand
= xchg1
;
4110 if (i
.broadcast
->operand
== xchg1
)
4111 i
.broadcast
->operand
= xchg2
;
4112 else if (i
.broadcast
->operand
== xchg2
)
4113 i
.broadcast
->operand
= xchg1
;
4117 if (i
.rounding
->operand
== xchg1
)
4118 i
.rounding
->operand
= xchg2
;
4119 else if (i
.rounding
->operand
== xchg2
)
4120 i
.rounding
->operand
= xchg1
;
4125 swap_operands (void)
4131 swap_2_operands (1, i
.operands
- 2);
4134 swap_2_operands (0, i
.operands
- 1);
4140 if (i
.mem_operands
== 2)
4142 const seg_entry
*temp_seg
;
4143 temp_seg
= i
.seg
[0];
4144 i
.seg
[0] = i
.seg
[1];
4145 i
.seg
[1] = temp_seg
;
4149 /* Try to ensure constant immediates are represented in the smallest
4154 char guess_suffix
= 0;
4158 guess_suffix
= i
.suffix
;
4159 else if (i
.reg_operands
)
4161 /* Figure out a suffix from the last register operand specified.
4162 We can't do this properly yet, ie. excluding InOutPortReg,
4163 but the following works for instructions with immediates.
4164 In any case, we can't set i.suffix yet. */
4165 for (op
= i
.operands
; --op
>= 0;)
4166 if (i
.types
[op
].bitfield
.reg8
)
4168 guess_suffix
= BYTE_MNEM_SUFFIX
;
4171 else if (i
.types
[op
].bitfield
.reg16
)
4173 guess_suffix
= WORD_MNEM_SUFFIX
;
4176 else if (i
.types
[op
].bitfield
.reg32
)
4178 guess_suffix
= LONG_MNEM_SUFFIX
;
4181 else if (i
.types
[op
].bitfield
.reg64
)
4183 guess_suffix
= QWORD_MNEM_SUFFIX
;
4187 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4188 guess_suffix
= WORD_MNEM_SUFFIX
;
4190 for (op
= i
.operands
; --op
>= 0;)
4191 if (operand_type_check (i
.types
[op
], imm
))
4193 switch (i
.op
[op
].imms
->X_op
)
4196 /* If a suffix is given, this operand may be shortened. */
4197 switch (guess_suffix
)
4199 case LONG_MNEM_SUFFIX
:
4200 i
.types
[op
].bitfield
.imm32
= 1;
4201 i
.types
[op
].bitfield
.imm64
= 1;
4203 case WORD_MNEM_SUFFIX
:
4204 i
.types
[op
].bitfield
.imm16
= 1;
4205 i
.types
[op
].bitfield
.imm32
= 1;
4206 i
.types
[op
].bitfield
.imm32s
= 1;
4207 i
.types
[op
].bitfield
.imm64
= 1;
4209 case BYTE_MNEM_SUFFIX
:
4210 i
.types
[op
].bitfield
.imm8
= 1;
4211 i
.types
[op
].bitfield
.imm8s
= 1;
4212 i
.types
[op
].bitfield
.imm16
= 1;
4213 i
.types
[op
].bitfield
.imm32
= 1;
4214 i
.types
[op
].bitfield
.imm32s
= 1;
4215 i
.types
[op
].bitfield
.imm64
= 1;
4219 /* If this operand is at most 16 bits, convert it
4220 to a signed 16 bit number before trying to see
4221 whether it will fit in an even smaller size.
4222 This allows a 16-bit operand such as $0xffe0 to
4223 be recognised as within Imm8S range. */
4224 if ((i
.types
[op
].bitfield
.imm16
)
4225 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4227 i
.op
[op
].imms
->X_add_number
=
4228 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4231 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4232 if ((i
.types
[op
].bitfield
.imm32
)
4233 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4236 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4237 ^ ((offsetT
) 1 << 31))
4238 - ((offsetT
) 1 << 31));
4242 = operand_type_or (i
.types
[op
],
4243 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4245 /* We must avoid matching of Imm32 templates when 64bit
4246 only immediate is available. */
4247 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4248 i
.types
[op
].bitfield
.imm32
= 0;
4255 /* Symbols and expressions. */
4257 /* Convert symbolic operand to proper sizes for matching, but don't
4258 prevent matching a set of insns that only supports sizes other
4259 than those matching the insn suffix. */
4261 i386_operand_type mask
, allowed
;
4262 const insn_template
*t
;
4264 operand_type_set (&mask
, 0);
4265 operand_type_set (&allowed
, 0);
4267 for (t
= current_templates
->start
;
4268 t
< current_templates
->end
;
4270 allowed
= operand_type_or (allowed
,
4271 t
->operand_types
[op
]);
4272 switch (guess_suffix
)
4274 case QWORD_MNEM_SUFFIX
:
4275 mask
.bitfield
.imm64
= 1;
4276 mask
.bitfield
.imm32s
= 1;
4278 case LONG_MNEM_SUFFIX
:
4279 mask
.bitfield
.imm32
= 1;
4281 case WORD_MNEM_SUFFIX
:
4282 mask
.bitfield
.imm16
= 1;
4284 case BYTE_MNEM_SUFFIX
:
4285 mask
.bitfield
.imm8
= 1;
4290 allowed
= operand_type_and (mask
, allowed
);
4291 if (!operand_type_all_zero (&allowed
))
4292 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4299 /* Try to use the smallest displacement type too. */
4301 optimize_disp (void)
4305 for (op
= i
.operands
; --op
>= 0;)
4306 if (operand_type_check (i
.types
[op
], disp
))
4308 if (i
.op
[op
].disps
->X_op
== O_constant
)
4310 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4312 if (i
.types
[op
].bitfield
.disp16
4313 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4315 /* If this operand is at most 16 bits, convert
4316 to a signed 16 bit number and don't use 64bit
4318 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4319 i
.types
[op
].bitfield
.disp64
= 0;
4322 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4323 if (i
.types
[op
].bitfield
.disp32
4324 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4326 /* If this operand is at most 32 bits, convert
4327 to a signed 32 bit number and don't use 64bit
4329 op_disp
&= (((offsetT
) 2 << 31) - 1);
4330 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4331 i
.types
[op
].bitfield
.disp64
= 0;
4334 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4336 i
.types
[op
].bitfield
.disp8
= 0;
4337 i
.types
[op
].bitfield
.disp16
= 0;
4338 i
.types
[op
].bitfield
.disp32
= 0;
4339 i
.types
[op
].bitfield
.disp32s
= 0;
4340 i
.types
[op
].bitfield
.disp64
= 0;
4344 else if (flag_code
== CODE_64BIT
)
4346 if (fits_in_signed_long (op_disp
))
4348 i
.types
[op
].bitfield
.disp64
= 0;
4349 i
.types
[op
].bitfield
.disp32s
= 1;
4351 if (i
.prefix
[ADDR_PREFIX
]
4352 && fits_in_unsigned_long (op_disp
))
4353 i
.types
[op
].bitfield
.disp32
= 1;
4355 if ((i
.types
[op
].bitfield
.disp32
4356 || i
.types
[op
].bitfield
.disp32s
4357 || i
.types
[op
].bitfield
.disp16
)
4358 && fits_in_signed_byte (op_disp
))
4359 i
.types
[op
].bitfield
.disp8
= 1;
4361 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4362 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4364 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4365 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4366 i
.types
[op
].bitfield
.disp8
= 0;
4367 i
.types
[op
].bitfield
.disp16
= 0;
4368 i
.types
[op
].bitfield
.disp32
= 0;
4369 i
.types
[op
].bitfield
.disp32s
= 0;
4370 i
.types
[op
].bitfield
.disp64
= 0;
4373 /* We only support 64bit displacement on constants. */
4374 i
.types
[op
].bitfield
.disp64
= 0;
4378 /* Check if operands are valid for the instruction. */
4381 check_VecOperands (const insn_template
*t
)
4385 /* Without VSIB byte, we can't have a vector register for index. */
4386 if (!t
->opcode_modifier
.vecsib
4388 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4389 || i
.index_reg
->reg_type
.bitfield
.regymm
4390 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4392 i
.error
= unsupported_vector_index_register
;
4396 /* Check if default mask is allowed. */
4397 if (t
->opcode_modifier
.nodefmask
4398 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4400 i
.error
= no_default_mask
;
4404 /* For VSIB byte, we need a vector register for index, and all vector
4405 registers must be distinct. */
4406 if (t
->opcode_modifier
.vecsib
)
4409 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4410 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4411 || (t
->opcode_modifier
.vecsib
== VecSIB256
4412 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4413 || (t
->opcode_modifier
.vecsib
== VecSIB512
4414 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4416 i
.error
= invalid_vsib_address
;
4420 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4421 if (i
.reg_operands
== 2 && !i
.mask
)
4423 gas_assert (i
.types
[0].bitfield
.regxmm
4424 || i
.types
[0].bitfield
.regymm
);
4425 gas_assert (i
.types
[2].bitfield
.regxmm
4426 || i
.types
[2].bitfield
.regymm
);
4427 if (operand_check
== check_none
)
4429 if (register_number (i
.op
[0].regs
)
4430 != register_number (i
.index_reg
)
4431 && register_number (i
.op
[2].regs
)
4432 != register_number (i
.index_reg
)
4433 && register_number (i
.op
[0].regs
)
4434 != register_number (i
.op
[2].regs
))
4436 if (operand_check
== check_error
)
4438 i
.error
= invalid_vector_register_set
;
4441 as_warn (_("mask, index, and destination registers should be distinct"));
4443 else if (i
.reg_operands
== 1 && i
.mask
)
4445 if ((i
.types
[1].bitfield
.regymm
4446 || i
.types
[1].bitfield
.regzmm
)
4447 && (register_number (i
.op
[1].regs
)
4448 == register_number (i
.index_reg
)))
4450 if (operand_check
== check_error
)
4452 i
.error
= invalid_vector_register_set
;
4455 if (operand_check
!= check_none
)
4456 as_warn (_("index and destination registers should be distinct"));
4461 /* Check if broadcast is supported by the instruction and is applied
4462 to the memory operand. */
4465 int broadcasted_opnd_size
;
4467 /* Check if specified broadcast is supported in this instruction,
4468 and it's applied to memory operand of DWORD or QWORD type,
4469 depending on VecESize. */
4470 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4471 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4472 || (t
->opcode_modifier
.vecesize
== 0
4473 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4474 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4475 || (t
->opcode_modifier
.vecesize
== 1
4476 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4477 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4480 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4481 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4482 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4483 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4484 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4485 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4486 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4487 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4488 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4492 if ((broadcasted_opnd_size
== 256
4493 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4494 || (broadcasted_opnd_size
== 512
4495 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4498 i
.error
= unsupported_broadcast
;
4502 /* If broadcast is supported in this instruction, we need to check if
4503 operand of one-element size isn't specified without broadcast. */
4504 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4506 /* Find memory operand. */
4507 for (op
= 0; op
< i
.operands
; op
++)
4508 if (operand_type_check (i
.types
[op
], anymem
))
4510 gas_assert (op
< i
.operands
);
4511 /* Check size of the memory operand. */
4512 if ((t
->opcode_modifier
.vecesize
== 0
4513 && i
.types
[op
].bitfield
.dword
)
4514 || (t
->opcode_modifier
.vecesize
== 1
4515 && i
.types
[op
].bitfield
.qword
))
4517 i
.error
= broadcast_needed
;
4522 /* Check if requested masking is supported. */
4524 && (!t
->opcode_modifier
.masking
4526 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4528 i
.error
= unsupported_masking
;
4532 /* Check if masking is applied to dest operand. */
4533 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4535 i
.error
= mask_not_on_destination
;
4542 if ((i
.rounding
->type
!= saeonly
4543 && !t
->opcode_modifier
.staticrounding
)
4544 || (i
.rounding
->type
== saeonly
4545 && (t
->opcode_modifier
.staticrounding
4546 || !t
->opcode_modifier
.sae
)))
4548 i
.error
= unsupported_rc_sae
;
4551 /* If the instruction has several immediate operands and one of
4552 them is rounding, the rounding operand should be the last
4553 immediate operand. */
4554 if (i
.imm_operands
> 1
4555 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4557 i
.error
= rc_sae_operand_not_last_imm
;
4562 /* Check vector Disp8 operand. */
4563 if (t
->opcode_modifier
.disp8memshift
)
4566 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4568 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4570 for (op
= 0; op
< i
.operands
; op
++)
4571 if (operand_type_check (i
.types
[op
], disp
)
4572 && i
.op
[op
].disps
->X_op
== O_constant
)
4574 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4575 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4576 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4579 i
.types
[op
].bitfield
.vec_disp8
= 1;
4582 /* Vector insn can only have Vec_Disp8/Disp32 in
4583 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4585 i
.types
[op
].bitfield
.disp8
= 0;
4586 if (flag_code
!= CODE_16BIT
)
4587 i
.types
[op
].bitfield
.disp16
= 0;
4590 else if (flag_code
!= CODE_16BIT
)
4592 /* One form of this instruction supports vector Disp8.
4593 Try vector Disp8 if we need to use Disp32. */
4594 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4596 i
.error
= try_vector_disp8
;
4608 /* Check if operands are valid for the instruction. Update VEX
4612 VEX_check_operands (const insn_template
*t
)
4614 /* VREX is only valid with EVEX prefix. */
4615 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4617 i
.error
= invalid_register_operand
;
4621 if (!t
->opcode_modifier
.vex
)
4624 /* Only check VEX_Imm4, which must be the first operand. */
4625 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4627 if (i
.op
[0].imms
->X_op
!= O_constant
4628 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4634 /* Turn off Imm8 so that update_imm won't complain. */
4635 i
.types
[0] = vec_imm4
;
4641 static const insn_template
*
4642 match_template (void)
4644 /* Points to template once we've found it. */
4645 const insn_template
*t
;
4646 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4647 i386_operand_type overlap4
;
4648 unsigned int found_reverse_match
;
4649 i386_opcode_modifier suffix_check
;
4650 i386_operand_type operand_types
[MAX_OPERANDS
];
4651 int addr_prefix_disp
;
4653 unsigned int found_cpu_match
;
4654 unsigned int check_register
;
4655 enum i386_error specific_error
= 0;
4657 #if MAX_OPERANDS != 5
4658 # error "MAX_OPERANDS must be 5."
4661 found_reverse_match
= 0;
4662 addr_prefix_disp
= -1;
4664 memset (&suffix_check
, 0, sizeof (suffix_check
));
4665 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4666 suffix_check
.no_bsuf
= 1;
4667 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4668 suffix_check
.no_wsuf
= 1;
4669 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4670 suffix_check
.no_ssuf
= 1;
4671 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4672 suffix_check
.no_lsuf
= 1;
4673 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4674 suffix_check
.no_qsuf
= 1;
4675 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4676 suffix_check
.no_ldsuf
= 1;
4678 /* Must have right number of operands. */
4679 i
.error
= number_of_operands_mismatch
;
4681 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4683 addr_prefix_disp
= -1;
4685 if (i
.operands
!= t
->operands
)
4688 /* Check processor support. */
4689 i
.error
= unsupported
;
4690 found_cpu_match
= (cpu_flags_match (t
)
4691 == CPU_FLAGS_PERFECT_MATCH
);
4692 if (!found_cpu_match
)
4695 /* Check old gcc support. */
4696 i
.error
= old_gcc_only
;
4697 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4700 /* Check AT&T mnemonic. */
4701 i
.error
= unsupported_with_intel_mnemonic
;
4702 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4705 /* Check AT&T/Intel syntax. */
4706 i
.error
= unsupported_syntax
;
4707 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4708 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4711 /* Check the suffix, except for some instructions in intel mode. */
4712 i
.error
= invalid_instruction_suffix
;
4713 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4714 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4715 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4716 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4717 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4718 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4719 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4722 if (!operand_size_match (t
))
4725 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4726 operand_types
[j
] = t
->operand_types
[j
];
4728 /* In general, don't allow 64-bit operands in 32-bit mode. */
4729 if (i
.suffix
== QWORD_MNEM_SUFFIX
4730 && flag_code
!= CODE_64BIT
4732 ? (!t
->opcode_modifier
.ignoresize
4733 && !intel_float_operand (t
->name
))
4734 : intel_float_operand (t
->name
) != 2)
4735 && ((!operand_types
[0].bitfield
.regmmx
4736 && !operand_types
[0].bitfield
.regxmm
4737 && !operand_types
[0].bitfield
.regymm
4738 && !operand_types
[0].bitfield
.regzmm
)
4739 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4740 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4741 && operand_types
[t
->operands
> 1].bitfield
.regymm
4742 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4743 && (t
->base_opcode
!= 0x0fc7
4744 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4747 /* In general, don't allow 32-bit operands on pre-386. */
4748 else if (i
.suffix
== LONG_MNEM_SUFFIX
4749 && !cpu_arch_flags
.bitfield
.cpui386
4751 ? (!t
->opcode_modifier
.ignoresize
4752 && !intel_float_operand (t
->name
))
4753 : intel_float_operand (t
->name
) != 2)
4754 && ((!operand_types
[0].bitfield
.regmmx
4755 && !operand_types
[0].bitfield
.regxmm
)
4756 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4757 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4760 /* Do not verify operands when there are none. */
4764 /* We've found a match; break out of loop. */
4768 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4769 into Disp32/Disp16/Disp32 operand. */
4770 if (i
.prefix
[ADDR_PREFIX
] != 0)
4772 /* There should be only one Disp operand. */
4776 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4778 if (operand_types
[j
].bitfield
.disp16
)
4780 addr_prefix_disp
= j
;
4781 operand_types
[j
].bitfield
.disp32
= 1;
4782 operand_types
[j
].bitfield
.disp16
= 0;
4788 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4790 if (operand_types
[j
].bitfield
.disp32
)
4792 addr_prefix_disp
= j
;
4793 operand_types
[j
].bitfield
.disp32
= 0;
4794 operand_types
[j
].bitfield
.disp16
= 1;
4800 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4802 if (operand_types
[j
].bitfield
.disp64
)
4804 addr_prefix_disp
= j
;
4805 operand_types
[j
].bitfield
.disp64
= 0;
4806 operand_types
[j
].bitfield
.disp32
= 1;
4814 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4815 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4818 /* We check register size if needed. */
4819 check_register
= t
->opcode_modifier
.checkregsize
;
4820 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4821 switch (t
->operands
)
4824 if (!operand_type_match (overlap0
, i
.types
[0]))
4828 /* xchg %eax, %eax is a special case. It is an aliase for nop
4829 only in 32bit mode and we can use opcode 0x90. In 64bit
4830 mode, we can't use 0x90 for xchg %eax, %eax since it should
4831 zero-extend %eax to %rax. */
4832 if (flag_code
== CODE_64BIT
4833 && t
->base_opcode
== 0x90
4834 && operand_type_equal (&i
.types
[0], &acc32
)
4835 && operand_type_equal (&i
.types
[1], &acc32
))
4839 /* If we swap operand in encoding, we either match
4840 the next one or reverse direction of operands. */
4841 if (t
->opcode_modifier
.s
)
4843 else if (t
->opcode_modifier
.d
)
4848 /* If we swap operand in encoding, we match the next one. */
4849 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4853 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4854 if (!operand_type_match (overlap0
, i
.types
[0])
4855 || !operand_type_match (overlap1
, i
.types
[1])
4857 && !operand_type_register_match (overlap0
, i
.types
[0],
4859 overlap1
, i
.types
[1],
4862 /* Check if other direction is valid ... */
4863 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4867 /* Try reversing direction of operands. */
4868 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4869 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4870 if (!operand_type_match (overlap0
, i
.types
[0])
4871 || !operand_type_match (overlap1
, i
.types
[1])
4873 && !operand_type_register_match (overlap0
,
4880 /* Does not match either direction. */
4883 /* found_reverse_match holds which of D or FloatDR
4885 if (t
->opcode_modifier
.d
)
4886 found_reverse_match
= Opcode_D
;
4887 else if (t
->opcode_modifier
.floatd
)
4888 found_reverse_match
= Opcode_FloatD
;
4890 found_reverse_match
= 0;
4891 if (t
->opcode_modifier
.floatr
)
4892 found_reverse_match
|= Opcode_FloatR
;
4896 /* Found a forward 2 operand match here. */
4897 switch (t
->operands
)
4900 overlap4
= operand_type_and (i
.types
[4],
4903 overlap3
= operand_type_and (i
.types
[3],
4906 overlap2
= operand_type_and (i
.types
[2],
4911 switch (t
->operands
)
4914 if (!operand_type_match (overlap4
, i
.types
[4])
4915 || !operand_type_register_match (overlap3
,
4923 if (!operand_type_match (overlap3
, i
.types
[3])
4925 && !operand_type_register_match (overlap2
,
4933 /* Here we make use of the fact that there are no
4934 reverse match 3 operand instructions, and all 3
4935 operand instructions only need to be checked for
4936 register consistency between operands 2 and 3. */
4937 if (!operand_type_match (overlap2
, i
.types
[2])
4939 && !operand_type_register_match (overlap1
,
4949 /* Found either forward/reverse 2, 3 or 4 operand match here:
4950 slip through to break. */
4952 if (!found_cpu_match
)
4954 found_reverse_match
= 0;
4958 /* Check if vector and VEX operands are valid. */
4959 if (check_VecOperands (t
) || VEX_check_operands (t
))
4961 specific_error
= i
.error
;
4965 /* We've found a match; break out of loop. */
4969 if (t
== current_templates
->end
)
4971 /* We found no match. */
4972 const char *err_msg
;
4973 switch (specific_error
? specific_error
: i
.error
)
4977 case operand_size_mismatch
:
4978 err_msg
= _("operand size mismatch");
4980 case operand_type_mismatch
:
4981 err_msg
= _("operand type mismatch");
4983 case register_type_mismatch
:
4984 err_msg
= _("register type mismatch");
4986 case number_of_operands_mismatch
:
4987 err_msg
= _("number of operands mismatch");
4989 case invalid_instruction_suffix
:
4990 err_msg
= _("invalid instruction suffix");
4993 err_msg
= _("constant doesn't fit in 4 bits");
4996 err_msg
= _("only supported with old gcc");
4998 case unsupported_with_intel_mnemonic
:
4999 err_msg
= _("unsupported with Intel mnemonic");
5001 case unsupported_syntax
:
5002 err_msg
= _("unsupported syntax");
5005 as_bad (_("unsupported instruction `%s'"),
5006 current_templates
->start
->name
);
5008 case invalid_vsib_address
:
5009 err_msg
= _("invalid VSIB address");
5011 case invalid_vector_register_set
:
5012 err_msg
= _("mask, index, and destination registers must be distinct");
5014 case unsupported_vector_index_register
:
5015 err_msg
= _("unsupported vector index register");
5017 case unsupported_broadcast
:
5018 err_msg
= _("unsupported broadcast");
5020 case broadcast_not_on_src_operand
:
5021 err_msg
= _("broadcast not on source memory operand");
5023 case broadcast_needed
:
5024 err_msg
= _("broadcast is needed for operand of such type");
5026 case unsupported_masking
:
5027 err_msg
= _("unsupported masking");
5029 case mask_not_on_destination
:
5030 err_msg
= _("mask not on destination operand");
5032 case no_default_mask
:
5033 err_msg
= _("default mask isn't allowed");
5035 case unsupported_rc_sae
:
5036 err_msg
= _("unsupported static rounding/sae");
5038 case rc_sae_operand_not_last_imm
:
5040 err_msg
= _("RC/SAE operand must precede immediate operands");
5042 err_msg
= _("RC/SAE operand must follow immediate operands");
5044 case invalid_register_operand
:
5045 err_msg
= _("invalid register operand");
5048 as_bad (_("%s for `%s'"), err_msg
,
5049 current_templates
->start
->name
);
5053 if (!quiet_warnings
)
5056 && (i
.types
[0].bitfield
.jumpabsolute
5057 != operand_types
[0].bitfield
.jumpabsolute
))
5059 as_warn (_("indirect %s without `*'"), t
->name
);
5062 if (t
->opcode_modifier
.isprefix
5063 && t
->opcode_modifier
.ignoresize
)
5065 /* Warn them that a data or address size prefix doesn't
5066 affect assembly of the next line of code. */
5067 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5071 /* Copy the template we found. */
5074 if (addr_prefix_disp
!= -1)
5075 i
.tm
.operand_types
[addr_prefix_disp
]
5076 = operand_types
[addr_prefix_disp
];
5078 if (found_reverse_match
)
5080 /* If we found a reverse match we must alter the opcode
5081 direction bit. found_reverse_match holds bits to change
5082 (different for int & float insns). */
5084 i
.tm
.base_opcode
^= found_reverse_match
;
5086 i
.tm
.operand_types
[0] = operand_types
[1];
5087 i
.tm
.operand_types
[1] = operand_types
[0];
5096 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5097 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5099 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5101 as_bad (_("`%s' operand %d must use `%ses' segment"),
5107 /* There's only ever one segment override allowed per instruction.
5108 This instruction possibly has a legal segment override on the
5109 second operand, so copy the segment to where non-string
5110 instructions store it, allowing common code. */
5111 i
.seg
[0] = i
.seg
[1];
5113 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5115 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5117 as_bad (_("`%s' operand %d must use `%ses' segment"),
5128 process_suffix (void)
5130 /* If matched instruction specifies an explicit instruction mnemonic
5132 if (i
.tm
.opcode_modifier
.size16
)
5133 i
.suffix
= WORD_MNEM_SUFFIX
;
5134 else if (i
.tm
.opcode_modifier
.size32
)
5135 i
.suffix
= LONG_MNEM_SUFFIX
;
5136 else if (i
.tm
.opcode_modifier
.size64
)
5137 i
.suffix
= QWORD_MNEM_SUFFIX
;
5138 else if (i
.reg_operands
)
5140 /* If there's no instruction mnemonic suffix we try to invent one
5141 based on register operands. */
5144 /* We take i.suffix from the last register operand specified,
5145 Destination register type is more significant than source
5146 register type. crc32 in SSE4.2 prefers source register
5148 if (i
.tm
.base_opcode
== 0xf20f38f1)
5150 if (i
.types
[0].bitfield
.reg16
)
5151 i
.suffix
= WORD_MNEM_SUFFIX
;
5152 else if (i
.types
[0].bitfield
.reg32
)
5153 i
.suffix
= LONG_MNEM_SUFFIX
;
5154 else if (i
.types
[0].bitfield
.reg64
)
5155 i
.suffix
= QWORD_MNEM_SUFFIX
;
5157 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5159 if (i
.types
[0].bitfield
.reg8
)
5160 i
.suffix
= BYTE_MNEM_SUFFIX
;
5167 if (i
.tm
.base_opcode
== 0xf20f38f1
5168 || i
.tm
.base_opcode
== 0xf20f38f0)
5170 /* We have to know the operand size for crc32. */
5171 as_bad (_("ambiguous memory operand size for `%s`"),
5176 for (op
= i
.operands
; --op
>= 0;)
5177 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5179 if (i
.types
[op
].bitfield
.reg8
)
5181 i
.suffix
= BYTE_MNEM_SUFFIX
;
5184 else if (i
.types
[op
].bitfield
.reg16
)
5186 i
.suffix
= WORD_MNEM_SUFFIX
;
5189 else if (i
.types
[op
].bitfield
.reg32
)
5191 i
.suffix
= LONG_MNEM_SUFFIX
;
5194 else if (i
.types
[op
].bitfield
.reg64
)
5196 i
.suffix
= QWORD_MNEM_SUFFIX
;
5202 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5205 && i
.tm
.opcode_modifier
.ignoresize
5206 && i
.tm
.opcode_modifier
.no_bsuf
)
5208 else if (!check_byte_reg ())
5211 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5214 && i
.tm
.opcode_modifier
.ignoresize
5215 && i
.tm
.opcode_modifier
.no_lsuf
)
5217 else if (!check_long_reg ())
5220 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5223 && i
.tm
.opcode_modifier
.ignoresize
5224 && i
.tm
.opcode_modifier
.no_qsuf
)
5226 else if (!check_qword_reg ())
5229 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5232 && i
.tm
.opcode_modifier
.ignoresize
5233 && i
.tm
.opcode_modifier
.no_wsuf
)
5235 else if (!check_word_reg ())
5238 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5239 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5240 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5242 /* Skip if the instruction has x/y/z suffix. match_template
5243 should check if it is a valid suffix. */
5245 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5246 /* Do nothing if the instruction is going to ignore the prefix. */
5251 else if (i
.tm
.opcode_modifier
.defaultsize
5253 /* exclude fldenv/frstor/fsave/fstenv */
5254 && i
.tm
.opcode_modifier
.no_ssuf
)
5256 i
.suffix
= stackop_size
;
5258 else if (intel_syntax
5260 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5261 || i
.tm
.opcode_modifier
.jumpbyte
5262 || i
.tm
.opcode_modifier
.jumpintersegment
5263 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5264 && i
.tm
.extension_opcode
<= 3)))
5269 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5271 i
.suffix
= QWORD_MNEM_SUFFIX
;
5275 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5276 i
.suffix
= LONG_MNEM_SUFFIX
;
5279 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5280 i
.suffix
= WORD_MNEM_SUFFIX
;
5289 if (i
.tm
.opcode_modifier
.w
)
5291 as_bad (_("no instruction mnemonic suffix given and "
5292 "no register operands; can't size instruction"));
5298 unsigned int suffixes
;
5300 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5301 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5303 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5305 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5307 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5309 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5312 /* There are more than suffix matches. */
5313 if (i
.tm
.opcode_modifier
.w
5314 || ((suffixes
& (suffixes
- 1))
5315 && !i
.tm
.opcode_modifier
.defaultsize
5316 && !i
.tm
.opcode_modifier
.ignoresize
))
5318 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5324 /* Change the opcode based on the operand size given by i.suffix;
5325 We don't need to change things for byte insns. */
5328 && i
.suffix
!= BYTE_MNEM_SUFFIX
5329 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5330 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5331 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5333 /* It's not a byte, select word/dword operation. */
5334 if (i
.tm
.opcode_modifier
.w
)
5336 if (i
.tm
.opcode_modifier
.shortform
)
5337 i
.tm
.base_opcode
|= 8;
5339 i
.tm
.base_opcode
|= 1;
5342 /* Now select between word & dword operations via the operand
5343 size prefix, except for instructions that will ignore this
5345 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5347 /* The address size override prefix changes the size of the
5349 if ((flag_code
== CODE_32BIT
5350 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5351 || (flag_code
!= CODE_32BIT
5352 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5353 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5356 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5357 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5358 && !i
.tm
.opcode_modifier
.ignoresize
5359 && !i
.tm
.opcode_modifier
.floatmf
5360 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5361 || (flag_code
== CODE_64BIT
5362 && i
.tm
.opcode_modifier
.jumpbyte
)))
5364 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5366 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5367 prefix
= ADDR_PREFIX_OPCODE
;
5369 if (!add_prefix (prefix
))
5373 /* Set mode64 for an operand. */
5374 if (i
.suffix
== QWORD_MNEM_SUFFIX
5375 && flag_code
== CODE_64BIT
5376 && !i
.tm
.opcode_modifier
.norex64
)
5378 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5379 need rex64. cmpxchg8b is also a special case. */
5380 if (! (i
.operands
== 2
5381 && i
.tm
.base_opcode
== 0x90
5382 && i
.tm
.extension_opcode
== None
5383 && operand_type_equal (&i
.types
[0], &acc64
)
5384 && operand_type_equal (&i
.types
[1], &acc64
))
5385 && ! (i
.operands
== 1
5386 && i
.tm
.base_opcode
== 0xfc7
5387 && i
.tm
.extension_opcode
== 1
5388 && !operand_type_check (i
.types
[0], reg
)
5389 && operand_type_check (i
.types
[0], anymem
)))
5393 /* Size floating point instruction. */
5394 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5395 if (i
.tm
.opcode_modifier
.floatmf
)
5396 i
.tm
.base_opcode
^= 4;
5403 check_byte_reg (void)
5407 for (op
= i
.operands
; --op
>= 0;)
5409 /* If this is an eight bit register, it's OK. If it's the 16 or
5410 32 bit version of an eight bit register, we will just use the
5411 low portion, and that's OK too. */
5412 if (i
.types
[op
].bitfield
.reg8
)
5415 /* I/O port address operands are OK too. */
5416 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5419 /* crc32 doesn't generate this warning. */
5420 if (i
.tm
.base_opcode
== 0xf20f38f0)
5423 if ((i
.types
[op
].bitfield
.reg16
5424 || i
.types
[op
].bitfield
.reg32
5425 || i
.types
[op
].bitfield
.reg64
)
5426 && i
.op
[op
].regs
->reg_num
< 4
5427 /* Prohibit these changes in 64bit mode, since the lowering
5428 would be more complicated. */
5429 && flag_code
!= CODE_64BIT
)
5431 #if REGISTER_WARNINGS
5432 if (!quiet_warnings
)
5433 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5435 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5436 ? REGNAM_AL
- REGNAM_AX
5437 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5439 i
.op
[op
].regs
->reg_name
,
5444 /* Any other register is bad. */
5445 if (i
.types
[op
].bitfield
.reg16
5446 || i
.types
[op
].bitfield
.reg32
5447 || i
.types
[op
].bitfield
.reg64
5448 || i
.types
[op
].bitfield
.regmmx
5449 || i
.types
[op
].bitfield
.regxmm
5450 || i
.types
[op
].bitfield
.regymm
5451 || i
.types
[op
].bitfield
.regzmm
5452 || i
.types
[op
].bitfield
.sreg2
5453 || i
.types
[op
].bitfield
.sreg3
5454 || i
.types
[op
].bitfield
.control
5455 || i
.types
[op
].bitfield
.debug
5456 || i
.types
[op
].bitfield
.test
5457 || i
.types
[op
].bitfield
.floatreg
5458 || i
.types
[op
].bitfield
.floatacc
)
5460 as_bad (_("`%s%s' not allowed with `%s%c'"),
5462 i
.op
[op
].regs
->reg_name
,
5472 check_long_reg (void)
5476 for (op
= i
.operands
; --op
>= 0;)
5477 /* Reject eight bit registers, except where the template requires
5478 them. (eg. movzb) */
5479 if (i
.types
[op
].bitfield
.reg8
5480 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5481 || i
.tm
.operand_types
[op
].bitfield
.reg32
5482 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5484 as_bad (_("`%s%s' not allowed with `%s%c'"),
5486 i
.op
[op
].regs
->reg_name
,
5491 /* Warn if the e prefix on a general reg is missing. */
5492 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5493 && i
.types
[op
].bitfield
.reg16
5494 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5495 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5497 /* Prohibit these changes in the 64bit mode, since the
5498 lowering is more complicated. */
5499 if (flag_code
== CODE_64BIT
)
5501 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5502 register_prefix
, i
.op
[op
].regs
->reg_name
,
5506 #if REGISTER_WARNINGS
5507 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5509 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5510 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5513 /* Warn if the r prefix on a general reg is present. */
5514 else if (i
.types
[op
].bitfield
.reg64
5515 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5516 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5519 && i
.tm
.opcode_modifier
.toqword
5520 && !i
.types
[0].bitfield
.regxmm
)
5522 /* Convert to QWORD. We want REX byte. */
5523 i
.suffix
= QWORD_MNEM_SUFFIX
;
5527 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5528 register_prefix
, i
.op
[op
].regs
->reg_name
,
5537 check_qword_reg (void)
5541 for (op
= i
.operands
; --op
>= 0; )
5542 /* Reject eight bit registers, except where the template requires
5543 them. (eg. movzb) */
5544 if (i
.types
[op
].bitfield
.reg8
5545 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5546 || i
.tm
.operand_types
[op
].bitfield
.reg32
5547 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5549 as_bad (_("`%s%s' not allowed with `%s%c'"),
5551 i
.op
[op
].regs
->reg_name
,
5556 /* Warn if the r prefix on a general reg is missing. */
5557 else if ((i
.types
[op
].bitfield
.reg16
5558 || i
.types
[op
].bitfield
.reg32
)
5559 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5560 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5562 /* Prohibit these changes in the 64bit mode, since the
5563 lowering is more complicated. */
5565 && i
.tm
.opcode_modifier
.todword
5566 && !i
.types
[0].bitfield
.regxmm
)
5568 /* Convert to DWORD. We don't want REX byte. */
5569 i
.suffix
= LONG_MNEM_SUFFIX
;
5573 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5574 register_prefix
, i
.op
[op
].regs
->reg_name
,
5583 check_word_reg (void)
5586 for (op
= i
.operands
; --op
>= 0;)
5587 /* Reject eight bit registers, except where the template requires
5588 them. (eg. movzb) */
5589 if (i
.types
[op
].bitfield
.reg8
5590 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5591 || i
.tm
.operand_types
[op
].bitfield
.reg32
5592 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5594 as_bad (_("`%s%s' not allowed with `%s%c'"),
5596 i
.op
[op
].regs
->reg_name
,
5601 /* Warn if the e or r prefix on a general reg is present. */
5602 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5603 && (i
.types
[op
].bitfield
.reg32
5604 || i
.types
[op
].bitfield
.reg64
)
5605 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5606 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5608 /* Prohibit these changes in the 64bit mode, since the
5609 lowering is more complicated. */
5610 if (flag_code
== CODE_64BIT
)
5612 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5613 register_prefix
, i
.op
[op
].regs
->reg_name
,
5617 #if REGISTER_WARNINGS
5618 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5620 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5621 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5628 update_imm (unsigned int j
)
5630 i386_operand_type overlap
= i
.types
[j
];
5631 if ((overlap
.bitfield
.imm8
5632 || overlap
.bitfield
.imm8s
5633 || overlap
.bitfield
.imm16
5634 || overlap
.bitfield
.imm32
5635 || overlap
.bitfield
.imm32s
5636 || overlap
.bitfield
.imm64
)
5637 && !operand_type_equal (&overlap
, &imm8
)
5638 && !operand_type_equal (&overlap
, &imm8s
)
5639 && !operand_type_equal (&overlap
, &imm16
)
5640 && !operand_type_equal (&overlap
, &imm32
)
5641 && !operand_type_equal (&overlap
, &imm32s
)
5642 && !operand_type_equal (&overlap
, &imm64
))
5646 i386_operand_type temp
;
5648 operand_type_set (&temp
, 0);
5649 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5651 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5652 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5654 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5655 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5656 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5658 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5659 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5662 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5665 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5666 || operand_type_equal (&overlap
, &imm16_32
)
5667 || operand_type_equal (&overlap
, &imm16_32s
))
5669 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5674 if (!operand_type_equal (&overlap
, &imm8
)
5675 && !operand_type_equal (&overlap
, &imm8s
)
5676 && !operand_type_equal (&overlap
, &imm16
)
5677 && !operand_type_equal (&overlap
, &imm32
)
5678 && !operand_type_equal (&overlap
, &imm32s
)
5679 && !operand_type_equal (&overlap
, &imm64
))
5681 as_bad (_("no instruction mnemonic suffix given; "
5682 "can't determine immediate size"));
5686 i
.types
[j
] = overlap
;
5696 /* Update the first 2 immediate operands. */
5697 n
= i
.operands
> 2 ? 2 : i
.operands
;
5700 for (j
= 0; j
< n
; j
++)
5701 if (update_imm (j
) == 0)
5704 /* The 3rd operand can't be immediate operand. */
5705 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5712 bad_implicit_operand (int xmm
)
5714 const char *ireg
= xmm
? "xmm0" : "ymm0";
5717 as_bad (_("the last operand of `%s' must be `%s%s'"),
5718 i
.tm
.name
, register_prefix
, ireg
);
5720 as_bad (_("the first operand of `%s' must be `%s%s'"),
5721 i
.tm
.name
, register_prefix
, ireg
);
5726 process_operands (void)
5728 /* Default segment register this instruction will use for memory
5729 accesses. 0 means unknown. This is only for optimizing out
5730 unnecessary segment overrides. */
5731 const seg_entry
*default_seg
= 0;
5733 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5735 unsigned int dupl
= i
.operands
;
5736 unsigned int dest
= dupl
- 1;
5739 /* The destination must be an xmm register. */
5740 gas_assert (i
.reg_operands
5741 && MAX_OPERANDS
> dupl
5742 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5744 if (i
.tm
.opcode_modifier
.firstxmm0
)
5746 /* The first operand is implicit and must be xmm0. */
5747 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5748 if (register_number (i
.op
[0].regs
) != 0)
5749 return bad_implicit_operand (1);
5751 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5753 /* Keep xmm0 for instructions with VEX prefix and 3
5759 /* We remove the first xmm0 and keep the number of
5760 operands unchanged, which in fact duplicates the
5762 for (j
= 1; j
< i
.operands
; j
++)
5764 i
.op
[j
- 1] = i
.op
[j
];
5765 i
.types
[j
- 1] = i
.types
[j
];
5766 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5770 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5772 gas_assert ((MAX_OPERANDS
- 1) > dupl
5773 && (i
.tm
.opcode_modifier
.vexsources
5776 /* Add the implicit xmm0 for instructions with VEX prefix
5778 for (j
= i
.operands
; j
> 0; j
--)
5780 i
.op
[j
] = i
.op
[j
- 1];
5781 i
.types
[j
] = i
.types
[j
- 1];
5782 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5785 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5786 i
.types
[0] = regxmm
;
5787 i
.tm
.operand_types
[0] = regxmm
;
5790 i
.reg_operands
+= 2;
5795 i
.op
[dupl
] = i
.op
[dest
];
5796 i
.types
[dupl
] = i
.types
[dest
];
5797 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5806 i
.op
[dupl
] = i
.op
[dest
];
5807 i
.types
[dupl
] = i
.types
[dest
];
5808 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5811 if (i
.tm
.opcode_modifier
.immext
)
5814 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5818 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5819 gas_assert (i
.reg_operands
5820 && (operand_type_equal (&i
.types
[0], ®xmm
)
5821 || operand_type_equal (&i
.types
[0], ®ymm
)
5822 || operand_type_equal (&i
.types
[0], ®zmm
)));
5823 if (register_number (i
.op
[0].regs
) != 0)
5824 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5826 for (j
= 1; j
< i
.operands
; j
++)
5828 i
.op
[j
- 1] = i
.op
[j
];
5829 i
.types
[j
- 1] = i
.types
[j
];
5831 /* We need to adjust fields in i.tm since they are used by
5832 build_modrm_byte. */
5833 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5840 else if (i
.tm
.opcode_modifier
.regkludge
)
5842 /* The imul $imm, %reg instruction is converted into
5843 imul $imm, %reg, %reg, and the clr %reg instruction
5844 is converted into xor %reg, %reg. */
5846 unsigned int first_reg_op
;
5848 if (operand_type_check (i
.types
[0], reg
))
5852 /* Pretend we saw the extra register operand. */
5853 gas_assert (i
.reg_operands
== 1
5854 && i
.op
[first_reg_op
+ 1].regs
== 0);
5855 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5856 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5861 if (i
.tm
.opcode_modifier
.shortform
)
5863 if (i
.types
[0].bitfield
.sreg2
5864 || i
.types
[0].bitfield
.sreg3
)
5866 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5867 && i
.op
[0].regs
->reg_num
== 1)
5869 as_bad (_("you can't `pop %scs'"), register_prefix
);
5872 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5873 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5878 /* The register or float register operand is in operand
5882 if (i
.types
[0].bitfield
.floatreg
5883 || operand_type_check (i
.types
[0], reg
))
5887 /* Register goes in low 3 bits of opcode. */
5888 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5889 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5891 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5893 /* Warn about some common errors, but press on regardless.
5894 The first case can be generated by gcc (<= 2.8.1). */
5895 if (i
.operands
== 2)
5897 /* Reversed arguments on faddp, fsubp, etc. */
5898 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5899 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5900 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5904 /* Extraneous `l' suffix on fp insn. */
5905 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5906 register_prefix
, i
.op
[0].regs
->reg_name
);
5911 else if (i
.tm
.opcode_modifier
.modrm
)
5913 /* The opcode is completed (modulo i.tm.extension_opcode which
5914 must be put into the modrm byte). Now, we make the modrm and
5915 index base bytes based on all the info we've collected. */
5917 default_seg
= build_modrm_byte ();
5919 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5923 else if (i
.tm
.opcode_modifier
.isstring
)
5925 /* For the string instructions that allow a segment override
5926 on one of their operands, the default segment is ds. */
5930 if (i
.tm
.base_opcode
== 0x8d /* lea */
5933 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5935 /* If a segment was explicitly specified, and the specified segment
5936 is not the default, use an opcode prefix to select it. If we
5937 never figured out what the default segment is, then default_seg
5938 will be zero at this point, and the specified segment prefix will
5940 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5942 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5948 static const seg_entry
*
5949 build_modrm_byte (void)
5951 const seg_entry
*default_seg
= 0;
5952 unsigned int source
, dest
;
5955 /* The first operand of instructions with VEX prefix and 3 sources
5956 must be VEX_Imm4. */
5957 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5960 unsigned int nds
, reg_slot
;
5963 if (i
.tm
.opcode_modifier
.veximmext
5964 && i
.tm
.opcode_modifier
.immext
)
5966 dest
= i
.operands
- 2;
5967 gas_assert (dest
== 3);
5970 dest
= i
.operands
- 1;
5973 /* There are 2 kinds of instructions:
5974 1. 5 operands: 4 register operands or 3 register operands
5975 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5976 VexW0 or VexW1. The destination must be either XMM, YMM or
5978 2. 4 operands: 4 register operands or 3 register operands
5979 plus 1 memory operand, VexXDS, and VexImmExt */
5980 gas_assert ((i
.reg_operands
== 4
5981 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5982 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5983 && (i
.tm
.opcode_modifier
.veximmext
5984 || (i
.imm_operands
== 1
5985 && i
.types
[0].bitfield
.vec_imm4
5986 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5987 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5988 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5989 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5990 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5992 if (i
.imm_operands
== 0)
5994 /* When there is no immediate operand, generate an 8bit
5995 immediate operand to encode the first operand. */
5996 exp
= &im_expressions
[i
.imm_operands
++];
5997 i
.op
[i
.operands
].imms
= exp
;
5998 i
.types
[i
.operands
] = imm8
;
6000 /* If VexW1 is set, the first operand is the source and
6001 the second operand is encoded in the immediate operand. */
6002 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6013 /* FMA swaps REG and NDS. */
6014 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6022 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6024 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6026 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6028 exp
->X_op
= O_constant
;
6029 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6030 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6034 unsigned int imm_slot
;
6036 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6038 /* If VexW0 is set, the third operand is the source and
6039 the second operand is encoded in the immediate
6046 /* VexW1 is set, the second operand is the source and
6047 the third operand is encoded in the immediate
6053 if (i
.tm
.opcode_modifier
.immext
)
6055 /* When ImmExt is set, the immdiate byte is the last
6057 imm_slot
= i
.operands
- 1;
6065 /* Turn on Imm8 so that output_imm will generate it. */
6066 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6069 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6071 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6073 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6075 i
.op
[imm_slot
].imms
->X_add_number
6076 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6077 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6080 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6081 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6083 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6085 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6090 /* i.reg_operands MUST be the number of real register operands;
6091 implicit registers do not count. If there are 3 register
6092 operands, it must be a instruction with VexNDS. For a
6093 instruction with VexNDD, the destination register is encoded
6094 in VEX prefix. If there are 4 register operands, it must be
6095 a instruction with VEX prefix and 3 sources. */
6096 if (i
.mem_operands
== 0
6097 && ((i
.reg_operands
== 2
6098 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6099 || (i
.reg_operands
== 3
6100 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6101 || (i
.reg_operands
== 4 && vex_3_sources
)))
6109 /* When there are 3 operands, one of them may be immediate,
6110 which may be the first or the last operand. Otherwise,
6111 the first operand must be shift count register (cl) or it
6112 is an instruction with VexNDS. */
6113 gas_assert (i
.imm_operands
== 1
6114 || (i
.imm_operands
== 0
6115 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6116 || i
.types
[0].bitfield
.shiftcount
)));
6117 if (operand_type_check (i
.types
[0], imm
)
6118 || i
.types
[0].bitfield
.shiftcount
)
6124 /* When there are 4 operands, the first two must be 8bit
6125 immediate operands. The source operand will be the 3rd
6128 For instructions with VexNDS, if the first operand
6129 an imm8, the source operand is the 2nd one. If the last
6130 operand is imm8, the source operand is the first one. */
6131 gas_assert ((i
.imm_operands
== 2
6132 && i
.types
[0].bitfield
.imm8
6133 && i
.types
[1].bitfield
.imm8
)
6134 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6135 && i
.imm_operands
== 1
6136 && (i
.types
[0].bitfield
.imm8
6137 || i
.types
[i
.operands
- 1].bitfield
.imm8
6139 if (i
.imm_operands
== 2)
6143 if (i
.types
[0].bitfield
.imm8
)
6150 if (i
.tm
.opcode_modifier
.evex
)
6152 /* For EVEX instructions, when there are 5 operands, the
6153 first one must be immediate operand. If the second one
6154 is immediate operand, the source operand is the 3th
6155 one. If the last one is immediate operand, the source
6156 operand is the 2nd one. */
6157 gas_assert (i
.imm_operands
== 2
6158 && i
.tm
.opcode_modifier
.sae
6159 && operand_type_check (i
.types
[0], imm
));
6160 if (operand_type_check (i
.types
[1], imm
))
6162 else if (operand_type_check (i
.types
[4], imm
))
6176 /* RC/SAE operand could be between DEST and SRC. That happens
6177 when one operand is GPR and the other one is XMM/YMM/ZMM
6179 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6182 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6184 /* For instructions with VexNDS, the register-only source
6185 operand must be 32/64bit integer, XMM, YMM or ZMM
6186 register. It is encoded in VEX prefix. We need to
6187 clear RegMem bit before calling operand_type_equal. */
6189 i386_operand_type op
;
6192 /* Check register-only source operand when two source
6193 operands are swapped. */
6194 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6195 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6203 op
= i
.tm
.operand_types
[vvvv
];
6204 op
.bitfield
.regmem
= 0;
6205 if ((dest
+ 1) >= i
.operands
6206 || (!op
.bitfield
.reg32
6207 && op
.bitfield
.reg64
6208 && !operand_type_equal (&op
, ®xmm
)
6209 && !operand_type_equal (&op
, ®ymm
)
6210 && !operand_type_equal (&op
, ®zmm
)
6211 && !operand_type_equal (&op
, ®mask
)))
6213 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6219 /* One of the register operands will be encoded in the i.tm.reg
6220 field, the other in the combined i.tm.mode and i.tm.regmem
6221 fields. If no form of this instruction supports a memory
6222 destination operand, then we assume the source operand may
6223 sometimes be a memory operand and so we need to store the
6224 destination in the i.rm.reg field. */
6225 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6226 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6228 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6229 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6230 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6232 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6234 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6236 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6241 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6242 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6243 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6245 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6247 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6249 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6252 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6254 if (!i
.types
[0].bitfield
.control
6255 && !i
.types
[1].bitfield
.control
)
6257 i
.rex
&= ~(REX_R
| REX_B
);
6258 add_prefix (LOCK_PREFIX_OPCODE
);
6262 { /* If it's not 2 reg operands... */
6267 unsigned int fake_zero_displacement
= 0;
6270 for (op
= 0; op
< i
.operands
; op
++)
6271 if (operand_type_check (i
.types
[op
], anymem
))
6273 gas_assert (op
< i
.operands
);
6275 if (i
.tm
.opcode_modifier
.vecsib
)
6277 if (i
.index_reg
->reg_num
== RegEiz
6278 || i
.index_reg
->reg_num
== RegRiz
)
6281 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6284 i
.sib
.base
= NO_BASE_REGISTER
;
6285 i
.sib
.scale
= i
.log2_scale_factor
;
6286 /* No Vec_Disp8 if there is no base. */
6287 i
.types
[op
].bitfield
.vec_disp8
= 0;
6288 i
.types
[op
].bitfield
.disp8
= 0;
6289 i
.types
[op
].bitfield
.disp16
= 0;
6290 i
.types
[op
].bitfield
.disp64
= 0;
6291 if (flag_code
!= CODE_64BIT
)
6293 /* Must be 32 bit */
6294 i
.types
[op
].bitfield
.disp32
= 1;
6295 i
.types
[op
].bitfield
.disp32s
= 0;
6299 i
.types
[op
].bitfield
.disp32
= 0;
6300 i
.types
[op
].bitfield
.disp32s
= 1;
6303 i
.sib
.index
= i
.index_reg
->reg_num
;
6304 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6306 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6312 if (i
.base_reg
== 0)
6315 if (!i
.disp_operands
)
6317 fake_zero_displacement
= 1;
6318 /* Instructions with VSIB byte need 32bit displacement
6319 if there is no base register. */
6320 if (i
.tm
.opcode_modifier
.vecsib
)
6321 i
.types
[op
].bitfield
.disp32
= 1;
6323 if (i
.index_reg
== 0)
6325 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6326 /* Operand is just <disp> */
6327 if (flag_code
== CODE_64BIT
)
6329 /* 64bit mode overwrites the 32bit absolute
6330 addressing by RIP relative addressing and
6331 absolute addressing is encoded by one of the
6332 redundant SIB forms. */
6333 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6334 i
.sib
.base
= NO_BASE_REGISTER
;
6335 i
.sib
.index
= NO_INDEX_REGISTER
;
6336 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6337 ? disp32s
: disp32
);
6339 else if ((flag_code
== CODE_16BIT
)
6340 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6342 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6343 i
.types
[op
] = disp16
;
6347 i
.rm
.regmem
= NO_BASE_REGISTER
;
6348 i
.types
[op
] = disp32
;
6351 else if (!i
.tm
.opcode_modifier
.vecsib
)
6353 /* !i.base_reg && i.index_reg */
6354 if (i
.index_reg
->reg_num
== RegEiz
6355 || i
.index_reg
->reg_num
== RegRiz
)
6356 i
.sib
.index
= NO_INDEX_REGISTER
;
6358 i
.sib
.index
= i
.index_reg
->reg_num
;
6359 i
.sib
.base
= NO_BASE_REGISTER
;
6360 i
.sib
.scale
= i
.log2_scale_factor
;
6361 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6362 /* No Vec_Disp8 if there is no base. */
6363 i
.types
[op
].bitfield
.vec_disp8
= 0;
6364 i
.types
[op
].bitfield
.disp8
= 0;
6365 i
.types
[op
].bitfield
.disp16
= 0;
6366 i
.types
[op
].bitfield
.disp64
= 0;
6367 if (flag_code
!= CODE_64BIT
)
6369 /* Must be 32 bit */
6370 i
.types
[op
].bitfield
.disp32
= 1;
6371 i
.types
[op
].bitfield
.disp32s
= 0;
6375 i
.types
[op
].bitfield
.disp32
= 0;
6376 i
.types
[op
].bitfield
.disp32s
= 1;
6378 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6382 /* RIP addressing for 64bit mode. */
6383 else if (i
.base_reg
->reg_num
== RegRip
||
6384 i
.base_reg
->reg_num
== RegEip
)
6386 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6387 i
.rm
.regmem
= NO_BASE_REGISTER
;
6388 i
.types
[op
].bitfield
.disp8
= 0;
6389 i
.types
[op
].bitfield
.disp16
= 0;
6390 i
.types
[op
].bitfield
.disp32
= 0;
6391 i
.types
[op
].bitfield
.disp32s
= 1;
6392 i
.types
[op
].bitfield
.disp64
= 0;
6393 i
.types
[op
].bitfield
.vec_disp8
= 0;
6394 i
.flags
[op
] |= Operand_PCrel
;
6395 if (! i
.disp_operands
)
6396 fake_zero_displacement
= 1;
6398 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6400 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6401 switch (i
.base_reg
->reg_num
)
6404 if (i
.index_reg
== 0)
6406 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6407 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6411 if (i
.index_reg
== 0)
6414 if (operand_type_check (i
.types
[op
], disp
) == 0)
6416 /* fake (%bp) into 0(%bp) */
6417 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6418 i
.types
[op
].bitfield
.vec_disp8
= 1;
6420 i
.types
[op
].bitfield
.disp8
= 1;
6421 fake_zero_displacement
= 1;
6424 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6425 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6427 default: /* (%si) -> 4 or (%di) -> 5 */
6428 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6430 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6432 else /* i.base_reg and 32/64 bit mode */
6434 if (flag_code
== CODE_64BIT
6435 && operand_type_check (i
.types
[op
], disp
))
6437 i386_operand_type temp
;
6438 operand_type_set (&temp
, 0);
6439 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6440 temp
.bitfield
.vec_disp8
6441 = i
.types
[op
].bitfield
.vec_disp8
;
6443 if (i
.prefix
[ADDR_PREFIX
] == 0)
6444 i
.types
[op
].bitfield
.disp32s
= 1;
6446 i
.types
[op
].bitfield
.disp32
= 1;
6449 if (!i
.tm
.opcode_modifier
.vecsib
)
6450 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6451 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6453 i
.sib
.base
= i
.base_reg
->reg_num
;
6454 /* x86-64 ignores REX prefix bit here to avoid decoder
6456 if (!(i
.base_reg
->reg_flags
& RegRex
)
6457 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6458 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6460 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6462 fake_zero_displacement
= 1;
6463 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6464 i
.types
[op
].bitfield
.vec_disp8
= 1;
6466 i
.types
[op
].bitfield
.disp8
= 1;
6468 i
.sib
.scale
= i
.log2_scale_factor
;
6469 if (i
.index_reg
== 0)
6471 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6472 /* <disp>(%esp) becomes two byte modrm with no index
6473 register. We've already stored the code for esp
6474 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6475 Any base register besides %esp will not use the
6476 extra modrm byte. */
6477 i
.sib
.index
= NO_INDEX_REGISTER
;
6479 else if (!i
.tm
.opcode_modifier
.vecsib
)
6481 if (i
.index_reg
->reg_num
== RegEiz
6482 || i
.index_reg
->reg_num
== RegRiz
)
6483 i
.sib
.index
= NO_INDEX_REGISTER
;
6485 i
.sib
.index
= i
.index_reg
->reg_num
;
6486 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6487 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6492 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6493 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6497 if (!fake_zero_displacement
6501 fake_zero_displacement
= 1;
6502 if (i
.disp_encoding
== disp_encoding_8bit
)
6503 i
.types
[op
].bitfield
.disp8
= 1;
6505 i
.types
[op
].bitfield
.disp32
= 1;
6507 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6511 if (fake_zero_displacement
)
6513 /* Fakes a zero displacement assuming that i.types[op]
6514 holds the correct displacement size. */
6517 gas_assert (i
.op
[op
].disps
== 0);
6518 exp
= &disp_expressions
[i
.disp_operands
++];
6519 i
.op
[op
].disps
= exp
;
6520 exp
->X_op
= O_constant
;
6521 exp
->X_add_number
= 0;
6522 exp
->X_add_symbol
= (symbolS
*) 0;
6523 exp
->X_op_symbol
= (symbolS
*) 0;
6531 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6533 if (operand_type_check (i
.types
[0], imm
))
6534 i
.vex
.register_specifier
= NULL
;
6537 /* VEX.vvvv encodes one of the sources when the first
6538 operand is not an immediate. */
6539 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6540 i
.vex
.register_specifier
= i
.op
[0].regs
;
6542 i
.vex
.register_specifier
= i
.op
[1].regs
;
6545 /* Destination is a XMM register encoded in the ModRM.reg
6547 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6548 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6551 /* ModRM.rm and VEX.B encodes the other source. */
6552 if (!i
.mem_operands
)
6556 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6557 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6559 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6561 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6565 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6567 i
.vex
.register_specifier
= i
.op
[2].regs
;
6568 if (!i
.mem_operands
)
6571 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6572 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6576 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6577 (if any) based on i.tm.extension_opcode. Again, we must be
6578 careful to make sure that segment/control/debug/test/MMX
6579 registers are coded into the i.rm.reg field. */
6580 else if (i
.reg_operands
)
6583 unsigned int vex_reg
= ~0;
6585 for (op
= 0; op
< i
.operands
; op
++)
6586 if (i
.types
[op
].bitfield
.reg8
6587 || i
.types
[op
].bitfield
.reg16
6588 || i
.types
[op
].bitfield
.reg32
6589 || i
.types
[op
].bitfield
.reg64
6590 || i
.types
[op
].bitfield
.regmmx
6591 || i
.types
[op
].bitfield
.regxmm
6592 || i
.types
[op
].bitfield
.regymm
6593 || i
.types
[op
].bitfield
.regbnd
6594 || i
.types
[op
].bitfield
.regzmm
6595 || i
.types
[op
].bitfield
.regmask
6596 || i
.types
[op
].bitfield
.sreg2
6597 || i
.types
[op
].bitfield
.sreg3
6598 || i
.types
[op
].bitfield
.control
6599 || i
.types
[op
].bitfield
.debug
6600 || i
.types
[op
].bitfield
.test
)
6605 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6607 /* For instructions with VexNDS, the register-only
6608 source operand is encoded in VEX prefix. */
6609 gas_assert (mem
!= (unsigned int) ~0);
6614 gas_assert (op
< i
.operands
);
6618 /* Check register-only source operand when two source
6619 operands are swapped. */
6620 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6621 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6625 gas_assert (mem
== (vex_reg
+ 1)
6626 && op
< i
.operands
);
6631 gas_assert (vex_reg
< i
.operands
);
6635 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6637 /* For instructions with VexNDD, the register destination
6638 is encoded in VEX prefix. */
6639 if (i
.mem_operands
== 0)
6641 /* There is no memory operand. */
6642 gas_assert ((op
+ 2) == i
.operands
);
6647 /* There are only 2 operands. */
6648 gas_assert (op
< 2 && i
.operands
== 2);
6653 gas_assert (op
< i
.operands
);
6655 if (vex_reg
!= (unsigned int) ~0)
6657 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6659 if (type
->bitfield
.reg32
!= 1
6660 && type
->bitfield
.reg64
!= 1
6661 && !operand_type_equal (type
, ®xmm
)
6662 && !operand_type_equal (type
, ®ymm
)
6663 && !operand_type_equal (type
, ®zmm
)
6664 && !operand_type_equal (type
, ®mask
))
6667 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6670 /* Don't set OP operand twice. */
6673 /* If there is an extension opcode to put here, the
6674 register number must be put into the regmem field. */
6675 if (i
.tm
.extension_opcode
!= None
)
6677 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6678 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6680 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6685 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6686 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6688 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6693 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6694 must set it to 3 to indicate this is a register operand
6695 in the regmem field. */
6696 if (!i
.mem_operands
)
6700 /* Fill in i.rm.reg field with extension opcode (if any). */
6701 if (i
.tm
.extension_opcode
!= None
)
6702 i
.rm
.reg
= i
.tm
.extension_opcode
;
6708 output_branch (void)
6714 relax_substateT subtype
;
6718 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6719 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6722 if (i
.prefix
[DATA_PREFIX
] != 0)
6728 /* Pentium4 branch hints. */
6729 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6730 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6735 if (i
.prefix
[REX_PREFIX
] != 0)
6741 /* BND prefixed jump. */
6742 if (i
.prefix
[BND_PREFIX
] != 0)
6744 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6748 if (i
.prefixes
!= 0 && !intel_syntax
)
6749 as_warn (_("skipping prefixes on this instruction"));
6751 /* It's always a symbol; End frag & setup for relax.
6752 Make sure there is enough room in this frag for the largest
6753 instruction we may generate in md_convert_frag. This is 2
6754 bytes for the opcode and room for the prefix and largest
6756 frag_grow (prefix
+ 2 + 4);
6757 /* Prefix and 1 opcode byte go in fr_fix. */
6758 p
= frag_more (prefix
+ 1);
6759 if (i
.prefix
[DATA_PREFIX
] != 0)
6760 *p
++ = DATA_PREFIX_OPCODE
;
6761 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6762 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6763 *p
++ = i
.prefix
[SEG_PREFIX
];
6764 if (i
.prefix
[REX_PREFIX
] != 0)
6765 *p
++ = i
.prefix
[REX_PREFIX
];
6766 *p
= i
.tm
.base_opcode
;
6768 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6769 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6770 else if (cpu_arch_flags
.bitfield
.cpui386
)
6771 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6773 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6776 sym
= i
.op
[0].disps
->X_add_symbol
;
6777 off
= i
.op
[0].disps
->X_add_number
;
6779 if (i
.op
[0].disps
->X_op
!= O_constant
6780 && i
.op
[0].disps
->X_op
!= O_symbol
)
6782 /* Handle complex expressions. */
6783 sym
= make_expr_symbol (i
.op
[0].disps
);
6787 /* 1 possible extra opcode + 4 byte displacement go in var part.
6788 Pass reloc in fr_var. */
6789 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6799 if (i
.tm
.opcode_modifier
.jumpbyte
)
6801 /* This is a loop or jecxz type instruction. */
6803 if (i
.prefix
[ADDR_PREFIX
] != 0)
6805 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6808 /* Pentium4 branch hints. */
6809 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6810 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6812 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6821 if (flag_code
== CODE_16BIT
)
6824 if (i
.prefix
[DATA_PREFIX
] != 0)
6826 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6836 if (i
.prefix
[REX_PREFIX
] != 0)
6838 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6842 /* BND prefixed jump. */
6843 if (i
.prefix
[BND_PREFIX
] != 0)
6845 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6849 if (i
.prefixes
!= 0 && !intel_syntax
)
6850 as_warn (_("skipping prefixes on this instruction"));
6852 p
= frag_more (i
.tm
.opcode_length
+ size
);
6853 switch (i
.tm
.opcode_length
)
6856 *p
++ = i
.tm
.base_opcode
>> 8;
6858 *p
++ = i
.tm
.base_opcode
;
6864 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6865 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6867 /* All jumps handled here are signed, but don't use a signed limit
6868 check for 32 and 16 bit jumps as we want to allow wrap around at
6869 4G and 64k respectively. */
6871 fixP
->fx_signed
= 1;
6875 output_interseg_jump (void)
6883 if (flag_code
== CODE_16BIT
)
6887 if (i
.prefix
[DATA_PREFIX
] != 0)
6893 if (i
.prefix
[REX_PREFIX
] != 0)
6903 if (i
.prefixes
!= 0 && !intel_syntax
)
6904 as_warn (_("skipping prefixes on this instruction"));
6906 /* 1 opcode; 2 segment; offset */
6907 p
= frag_more (prefix
+ 1 + 2 + size
);
6909 if (i
.prefix
[DATA_PREFIX
] != 0)
6910 *p
++ = DATA_PREFIX_OPCODE
;
6912 if (i
.prefix
[REX_PREFIX
] != 0)
6913 *p
++ = i
.prefix
[REX_PREFIX
];
6915 *p
++ = i
.tm
.base_opcode
;
6916 if (i
.op
[1].imms
->X_op
== O_constant
)
6918 offsetT n
= i
.op
[1].imms
->X_add_number
;
6921 && !fits_in_unsigned_word (n
)
6922 && !fits_in_signed_word (n
))
6924 as_bad (_("16-bit jump out of range"));
6927 md_number_to_chars (p
, n
, size
);
6930 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6931 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6932 if (i
.op
[0].imms
->X_op
!= O_constant
)
6933 as_bad (_("can't handle non absolute segment in `%s'"),
6935 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6941 fragS
*insn_start_frag
;
6942 offsetT insn_start_off
;
6944 /* Tie dwarf2 debug info to the address at the start of the insn.
6945 We can't do this after the insn has been output as the current
6946 frag may have been closed off. eg. by frag_var. */
6947 dwarf2_emit_insn (0);
6949 insn_start_frag
= frag_now
;
6950 insn_start_off
= frag_now_fix ();
6953 if (i
.tm
.opcode_modifier
.jump
)
6955 else if (i
.tm
.opcode_modifier
.jumpbyte
6956 || i
.tm
.opcode_modifier
.jumpdword
)
6958 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6959 output_interseg_jump ();
6962 /* Output normal instructions here. */
6966 unsigned int prefix
;
6969 && i
.tm
.base_opcode
== 0xfae
6971 && i
.imm_operands
== 1
6972 && (i
.op
[0].imms
->X_add_number
== 0xe8
6973 || i
.op
[0].imms
->X_add_number
== 0xf0
6974 || i
.op
[0].imms
->X_add_number
== 0xf8))
6976 /* Encode lfence, mfence, and sfence as
6977 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
6978 offsetT val
= 0x240483f0ULL
;
6980 md_number_to_chars (p
, val
, 5);
6984 /* Some processors fail on LOCK prefix. This options makes
6985 assembler ignore LOCK prefix and serves as a workaround. */
6986 if (omit_lock_prefix
)
6988 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6990 i
.prefix
[LOCK_PREFIX
] = 0;
6993 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6994 don't need the explicit prefix. */
6995 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6997 switch (i
.tm
.opcode_length
)
7000 if (i
.tm
.base_opcode
& 0xff000000)
7002 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7007 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7009 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7010 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7013 if (prefix
!= REPE_PREFIX_OPCODE
7014 || (i
.prefix
[REP_PREFIX
]
7015 != REPE_PREFIX_OPCODE
))
7016 add_prefix (prefix
);
7019 add_prefix (prefix
);
7028 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7029 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7030 R_X86_64_GOTTPOFF relocation so that linker can safely
7031 perform IE->LE optimization. */
7032 if (x86_elf_abi
== X86_64_X32_ABI
7034 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7035 && i
.prefix
[REX_PREFIX
] == 0)
7036 add_prefix (REX_OPCODE
);
7039 /* The prefix bytes. */
7040 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7042 FRAG_APPEND_1_CHAR (*q
);
7046 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7051 /* REX byte is encoded in VEX prefix. */
7055 FRAG_APPEND_1_CHAR (*q
);
7058 /* There should be no other prefixes for instructions
7063 /* For EVEX instructions i.vrex should become 0 after
7064 build_evex_prefix. For VEX instructions upper 16 registers
7065 aren't available, so VREX should be 0. */
7068 /* Now the VEX prefix. */
7069 p
= frag_more (i
.vex
.length
);
7070 for (j
= 0; j
< i
.vex
.length
; j
++)
7071 p
[j
] = i
.vex
.bytes
[j
];
7074 /* Now the opcode; be careful about word order here! */
7075 if (i
.tm
.opcode_length
== 1)
7077 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7081 switch (i
.tm
.opcode_length
)
7085 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7086 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7090 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7100 /* Put out high byte first: can't use md_number_to_chars! */
7101 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7102 *p
= i
.tm
.base_opcode
& 0xff;
7105 /* Now the modrm byte and sib byte (if present). */
7106 if (i
.tm
.opcode_modifier
.modrm
)
7108 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7111 /* If i.rm.regmem == ESP (4)
7112 && i.rm.mode != (Register mode)
7114 ==> need second modrm byte. */
7115 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7117 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7118 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7120 | i
.sib
.scale
<< 6));
7123 if (i
.disp_operands
)
7124 output_disp (insn_start_frag
, insn_start_off
);
7127 output_imm (insn_start_frag
, insn_start_off
);
7133 pi ("" /*line*/, &i
);
7135 #endif /* DEBUG386 */
7138 /* Return the size of the displacement operand N. */
7141 disp_size (unsigned int n
)
7145 /* Vec_Disp8 has to be 8bit. */
7146 if (i
.types
[n
].bitfield
.vec_disp8
)
7148 else if (i
.types
[n
].bitfield
.disp64
)
7150 else if (i
.types
[n
].bitfield
.disp8
)
7152 else if (i
.types
[n
].bitfield
.disp16
)
7157 /* Return the size of the immediate operand N. */
7160 imm_size (unsigned int n
)
7163 if (i
.types
[n
].bitfield
.imm64
)
7165 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7167 else if (i
.types
[n
].bitfield
.imm16
)
7173 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7178 for (n
= 0; n
< i
.operands
; n
++)
7180 if (i
.types
[n
].bitfield
.vec_disp8
7181 || operand_type_check (i
.types
[n
], disp
))
7183 if (i
.op
[n
].disps
->X_op
== O_constant
)
7185 int size
= disp_size (n
);
7186 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7188 if (i
.types
[n
].bitfield
.vec_disp8
)
7190 val
= offset_in_range (val
, size
);
7191 p
= frag_more (size
);
7192 md_number_to_chars (p
, val
, size
);
7196 enum bfd_reloc_code_real reloc_type
;
7197 int size
= disp_size (n
);
7198 int sign
= i
.types
[n
].bitfield
.disp32s
;
7199 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7202 /* We can't have 8 bit displacement here. */
7203 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7205 /* The PC relative address is computed relative
7206 to the instruction boundary, so in case immediate
7207 fields follows, we need to adjust the value. */
7208 if (pcrel
&& i
.imm_operands
)
7213 for (n1
= 0; n1
< i
.operands
; n1
++)
7214 if (operand_type_check (i
.types
[n1
], imm
))
7216 /* Only one immediate is allowed for PC
7217 relative address. */
7218 gas_assert (sz
== 0);
7220 i
.op
[n
].disps
->X_add_number
-= sz
;
7222 /* We should find the immediate. */
7223 gas_assert (sz
!= 0);
7226 p
= frag_more (size
);
7227 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7229 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7230 && (((reloc_type
== BFD_RELOC_32
7231 || reloc_type
== BFD_RELOC_X86_64_32S
7232 || (reloc_type
== BFD_RELOC_64
7234 && (i
.op
[n
].disps
->X_op
== O_symbol
7235 || (i
.op
[n
].disps
->X_op
== O_add
7236 && ((symbol_get_value_expression
7237 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7239 || reloc_type
== BFD_RELOC_32_PCREL
))
7243 if (insn_start_frag
== frag_now
)
7244 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7249 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7250 for (fr
= insn_start_frag
->fr_next
;
7251 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7253 add
+= p
- frag_now
->fr_literal
;
7258 reloc_type
= BFD_RELOC_386_GOTPC
;
7259 i
.op
[n
].imms
->X_add_number
+= add
;
7261 else if (reloc_type
== BFD_RELOC_64
)
7262 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7264 /* Don't do the adjustment for x86-64, as there
7265 the pcrel addressing is relative to the _next_
7266 insn, and that is taken care of in other code. */
7267 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7269 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7270 size
, i
.op
[n
].disps
, pcrel
,
7272 /* Check for "call/jmp *mem", "mov mem, %reg",
7273 "test %reg, mem" and "binop mem, %reg" where binop
7274 is one of adc, add, and, cmp, or, sbb, sub, xor
7275 instructions. Always generate R_386_GOT32X for
7276 "sym*GOT" operand in 32-bit mode. */
7277 if ((generate_relax_relocations
7280 && i
.rm
.regmem
== 5))
7282 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7283 && ((i
.operands
== 1
7284 && i
.tm
.base_opcode
== 0xff
7285 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7287 && (i
.tm
.base_opcode
== 0x8b
7288 || i
.tm
.base_opcode
== 0x85
7289 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7293 fixP
->fx_tcbit
= i
.rex
!= 0;
7295 && (i
.base_reg
->reg_num
== RegRip
7296 || i
.base_reg
->reg_num
== RegEip
))
7297 fixP
->fx_tcbit2
= 1;
7300 fixP
->fx_tcbit2
= 1;
7308 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7313 for (n
= 0; n
< i
.operands
; n
++)
7315 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7316 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7319 if (operand_type_check (i
.types
[n
], imm
))
7321 if (i
.op
[n
].imms
->X_op
== O_constant
)
7323 int size
= imm_size (n
);
7326 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7328 p
= frag_more (size
);
7329 md_number_to_chars (p
, val
, size
);
7333 /* Not absolute_section.
7334 Need a 32-bit fixup (don't support 8bit
7335 non-absolute imms). Try to support other
7337 enum bfd_reloc_code_real reloc_type
;
7338 int size
= imm_size (n
);
7341 if (i
.types
[n
].bitfield
.imm32s
7342 && (i
.suffix
== QWORD_MNEM_SUFFIX
7343 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7348 p
= frag_more (size
);
7349 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7351 /* This is tough to explain. We end up with this one if we
7352 * have operands that look like
7353 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7354 * obtain the absolute address of the GOT, and it is strongly
7355 * preferable from a performance point of view to avoid using
7356 * a runtime relocation for this. The actual sequence of
7357 * instructions often look something like:
7362 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7364 * The call and pop essentially return the absolute address
7365 * of the label .L66 and store it in %ebx. The linker itself
7366 * will ultimately change the first operand of the addl so
7367 * that %ebx points to the GOT, but to keep things simple, the
7368 * .o file must have this operand set so that it generates not
7369 * the absolute address of .L66, but the absolute address of
7370 * itself. This allows the linker itself simply treat a GOTPC
7371 * relocation as asking for a pcrel offset to the GOT to be
7372 * added in, and the addend of the relocation is stored in the
7373 * operand field for the instruction itself.
7375 * Our job here is to fix the operand so that it would add
7376 * the correct offset so that %ebx would point to itself. The
7377 * thing that is tricky is that .-.L66 will point to the
7378 * beginning of the instruction, so we need to further modify
7379 * the operand so that it will point to itself. There are
7380 * other cases where you have something like:
7382 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7384 * and here no correction would be required. Internally in
7385 * the assembler we treat operands of this form as not being
7386 * pcrel since the '.' is explicitly mentioned, and I wonder
7387 * whether it would simplify matters to do it this way. Who
7388 * knows. In earlier versions of the PIC patches, the
7389 * pcrel_adjust field was used to store the correction, but
7390 * since the expression is not pcrel, I felt it would be
7391 * confusing to do it this way. */
7393 if ((reloc_type
== BFD_RELOC_32
7394 || reloc_type
== BFD_RELOC_X86_64_32S
7395 || reloc_type
== BFD_RELOC_64
)
7397 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7398 && (i
.op
[n
].imms
->X_op
== O_symbol
7399 || (i
.op
[n
].imms
->X_op
== O_add
7400 && ((symbol_get_value_expression
7401 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7406 if (insn_start_frag
== frag_now
)
7407 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7412 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7413 for (fr
= insn_start_frag
->fr_next
;
7414 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7416 add
+= p
- frag_now
->fr_literal
;
7420 reloc_type
= BFD_RELOC_386_GOTPC
;
7422 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7424 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7425 i
.op
[n
].imms
->X_add_number
+= add
;
7427 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7428 i
.op
[n
].imms
, 0, reloc_type
);
7434 /* x86_cons_fix_new is called via the expression parsing code when a
7435 reloc is needed. We use this hook to get the correct .got reloc. */
7436 static int cons_sign
= -1;
7439 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7440 expressionS
*exp
, bfd_reloc_code_real_type r
)
7442 r
= reloc (len
, 0, cons_sign
, r
);
7445 if (exp
->X_op
== O_secrel
)
7447 exp
->X_op
= O_symbol
;
7448 r
= BFD_RELOC_32_SECREL
;
7452 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7455 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7456 purpose of the `.dc.a' internal pseudo-op. */
7459 x86_address_bytes (void)
7461 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7463 return stdoutput
->arch_info
->bits_per_address
/ 8;
7466 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7468 # define lex_got(reloc, adjust, types) NULL
7470 /* Parse operands of the form
7471 <symbol>@GOTOFF+<nnn>
7472 and similar .plt or .got references.
7474 If we find one, set up the correct relocation in RELOC and copy the
7475 input string, minus the `@GOTOFF' into a malloc'd buffer for
7476 parsing by the calling routine. Return this buffer, and if ADJUST
7477 is non-null set it to the length of the string we removed from the
7478 input line. Otherwise return NULL. */
7480 lex_got (enum bfd_reloc_code_real
*rel
,
7482 i386_operand_type
*types
)
7484 /* Some of the relocations depend on the size of what field is to
7485 be relocated. But in our callers i386_immediate and i386_displacement
7486 we don't yet know the operand size (this will be set by insn
7487 matching). Hence we record the word32 relocation here,
7488 and adjust the reloc according to the real size in reloc(). */
7489 static const struct {
7492 const enum bfd_reloc_code_real rel
[2];
7493 const i386_operand_type types64
;
7495 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7496 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7498 OPERAND_TYPE_IMM32_64
},
7500 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7501 BFD_RELOC_X86_64_PLTOFF64
},
7502 OPERAND_TYPE_IMM64
},
7503 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7504 BFD_RELOC_X86_64_PLT32
},
7505 OPERAND_TYPE_IMM32_32S_DISP32
},
7506 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7507 BFD_RELOC_X86_64_GOTPLT64
},
7508 OPERAND_TYPE_IMM64_DISP64
},
7509 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7510 BFD_RELOC_X86_64_GOTOFF64
},
7511 OPERAND_TYPE_IMM64_DISP64
},
7512 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7513 BFD_RELOC_X86_64_GOTPCREL
},
7514 OPERAND_TYPE_IMM32_32S_DISP32
},
7515 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7516 BFD_RELOC_X86_64_TLSGD
},
7517 OPERAND_TYPE_IMM32_32S_DISP32
},
7518 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7519 _dummy_first_bfd_reloc_code_real
},
7520 OPERAND_TYPE_NONE
},
7521 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7522 BFD_RELOC_X86_64_TLSLD
},
7523 OPERAND_TYPE_IMM32_32S_DISP32
},
7524 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7525 BFD_RELOC_X86_64_GOTTPOFF
},
7526 OPERAND_TYPE_IMM32_32S_DISP32
},
7527 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7528 BFD_RELOC_X86_64_TPOFF32
},
7529 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7530 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7531 _dummy_first_bfd_reloc_code_real
},
7532 OPERAND_TYPE_NONE
},
7533 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7534 BFD_RELOC_X86_64_DTPOFF32
},
7535 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7536 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7537 _dummy_first_bfd_reloc_code_real
},
7538 OPERAND_TYPE_NONE
},
7539 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7540 _dummy_first_bfd_reloc_code_real
},
7541 OPERAND_TYPE_NONE
},
7542 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7543 BFD_RELOC_X86_64_GOT32
},
7544 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7545 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7546 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7547 OPERAND_TYPE_IMM32_32S_DISP32
},
7548 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7549 BFD_RELOC_X86_64_TLSDESC_CALL
},
7550 OPERAND_TYPE_IMM32_32S_DISP32
},
7555 #if defined (OBJ_MAYBE_ELF)
7560 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7561 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7564 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7566 int len
= gotrel
[j
].len
;
7567 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7569 if (gotrel
[j
].rel
[object_64bit
] != 0)
7572 char *tmpbuf
, *past_reloc
;
7574 *rel
= gotrel
[j
].rel
[object_64bit
];
7578 if (flag_code
!= CODE_64BIT
)
7580 types
->bitfield
.imm32
= 1;
7581 types
->bitfield
.disp32
= 1;
7584 *types
= gotrel
[j
].types64
;
7587 if (j
!= 0 && GOT_symbol
== NULL
)
7588 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7590 /* The length of the first part of our input line. */
7591 first
= cp
- input_line_pointer
;
7593 /* The second part goes from after the reloc token until
7594 (and including) an end_of_line char or comma. */
7595 past_reloc
= cp
+ 1 + len
;
7597 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7599 second
= cp
+ 1 - past_reloc
;
7601 /* Allocate and copy string. The trailing NUL shouldn't
7602 be necessary, but be safe. */
7603 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7604 memcpy (tmpbuf
, input_line_pointer
, first
);
7605 if (second
!= 0 && *past_reloc
!= ' ')
7606 /* Replace the relocation token with ' ', so that
7607 errors like foo@GOTOFF1 will be detected. */
7608 tmpbuf
[first
++] = ' ';
7610 /* Increment length by 1 if the relocation token is
7615 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7616 tmpbuf
[first
+ second
] = '\0';
7620 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7621 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7626 /* Might be a symbol version string. Don't as_bad here. */
7635 /* Parse operands of the form
7636 <symbol>@SECREL32+<nnn>
7638 If we find one, set up the correct relocation in RELOC and copy the
7639 input string, minus the `@SECREL32' into a malloc'd buffer for
7640 parsing by the calling routine. Return this buffer, and if ADJUST
7641 is non-null set it to the length of the string we removed from the
7642 input line. Otherwise return NULL.
7644 This function is copied from the ELF version above adjusted for PE targets. */
7647 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7648 int *adjust ATTRIBUTE_UNUSED
,
7649 i386_operand_type
*types
)
7655 const enum bfd_reloc_code_real rel
[2];
7656 const i386_operand_type types64
;
7660 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7661 BFD_RELOC_32_SECREL
},
7662 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7668 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7669 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7672 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7674 int len
= gotrel
[j
].len
;
7676 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7678 if (gotrel
[j
].rel
[object_64bit
] != 0)
7681 char *tmpbuf
, *past_reloc
;
7683 *rel
= gotrel
[j
].rel
[object_64bit
];
7689 if (flag_code
!= CODE_64BIT
)
7691 types
->bitfield
.imm32
= 1;
7692 types
->bitfield
.disp32
= 1;
7695 *types
= gotrel
[j
].types64
;
7698 /* The length of the first part of our input line. */
7699 first
= cp
- input_line_pointer
;
7701 /* The second part goes from after the reloc token until
7702 (and including) an end_of_line char or comma. */
7703 past_reloc
= cp
+ 1 + len
;
7705 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7707 second
= cp
+ 1 - past_reloc
;
7709 /* Allocate and copy string. The trailing NUL shouldn't
7710 be necessary, but be safe. */
7711 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7712 memcpy (tmpbuf
, input_line_pointer
, first
);
7713 if (second
!= 0 && *past_reloc
!= ' ')
7714 /* Replace the relocation token with ' ', so that
7715 errors like foo@SECLREL321 will be detected. */
7716 tmpbuf
[first
++] = ' ';
7717 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7718 tmpbuf
[first
+ second
] = '\0';
7722 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7723 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7728 /* Might be a symbol version string. Don't as_bad here. */
7734 bfd_reloc_code_real_type
7735 x86_cons (expressionS
*exp
, int size
)
7737 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7739 intel_syntax
= -intel_syntax
;
7742 if (size
== 4 || (object_64bit
&& size
== 8))
7744 /* Handle @GOTOFF and the like in an expression. */
7746 char *gotfree_input_line
;
7749 save
= input_line_pointer
;
7750 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7751 if (gotfree_input_line
)
7752 input_line_pointer
= gotfree_input_line
;
7756 if (gotfree_input_line
)
7758 /* expression () has merrily parsed up to the end of line,
7759 or a comma - in the wrong buffer. Transfer how far
7760 input_line_pointer has moved to the right buffer. */
7761 input_line_pointer
= (save
7762 + (input_line_pointer
- gotfree_input_line
)
7764 free (gotfree_input_line
);
7765 if (exp
->X_op
== O_constant
7766 || exp
->X_op
== O_absent
7767 || exp
->X_op
== O_illegal
7768 || exp
->X_op
== O_register
7769 || exp
->X_op
== O_big
)
7771 char c
= *input_line_pointer
;
7772 *input_line_pointer
= 0;
7773 as_bad (_("missing or invalid expression `%s'"), save
);
7774 *input_line_pointer
= c
;
7781 intel_syntax
= -intel_syntax
;
7784 i386_intel_simplify (exp
);
7790 signed_cons (int size
)
7792 if (flag_code
== CODE_64BIT
)
7800 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7807 if (exp
.X_op
== O_symbol
)
7808 exp
.X_op
= O_secrel
;
7810 emit_expr (&exp
, 4);
7812 while (*input_line_pointer
++ == ',');
7814 input_line_pointer
--;
7815 demand_empty_rest_of_line ();
7819 /* Handle Vector operations. */
7822 check_VecOperations (char *op_string
, char *op_end
)
7824 const reg_entry
*mask
;
7829 && (op_end
== NULL
|| op_string
< op_end
))
7832 if (*op_string
== '{')
7836 /* Check broadcasts. */
7837 if (strncmp (op_string
, "1to", 3) == 0)
7842 goto duplicated_vec_op
;
7845 if (*op_string
== '8')
7846 bcst_type
= BROADCAST_1TO8
;
7847 else if (*op_string
== '4')
7848 bcst_type
= BROADCAST_1TO4
;
7849 else if (*op_string
== '2')
7850 bcst_type
= BROADCAST_1TO2
;
7851 else if (*op_string
== '1'
7852 && *(op_string
+1) == '6')
7854 bcst_type
= BROADCAST_1TO16
;
7859 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7864 broadcast_op
.type
= bcst_type
;
7865 broadcast_op
.operand
= this_operand
;
7866 i
.broadcast
= &broadcast_op
;
7868 /* Check masking operation. */
7869 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7871 /* k0 can't be used for write mask. */
7872 if (mask
->reg_num
== 0)
7874 as_bad (_("`%s' can't be used for write mask"),
7881 mask_op
.mask
= mask
;
7882 mask_op
.zeroing
= 0;
7883 mask_op
.operand
= this_operand
;
7889 goto duplicated_vec_op
;
7891 i
.mask
->mask
= mask
;
7893 /* Only "{z}" is allowed here. No need to check
7894 zeroing mask explicitly. */
7895 if (i
.mask
->operand
!= this_operand
)
7897 as_bad (_("invalid write mask `%s'"), saved
);
7904 /* Check zeroing-flag for masking operation. */
7905 else if (*op_string
== 'z')
7909 mask_op
.mask
= NULL
;
7910 mask_op
.zeroing
= 1;
7911 mask_op
.operand
= this_operand
;
7916 if (i
.mask
->zeroing
)
7919 as_bad (_("duplicated `%s'"), saved
);
7923 i
.mask
->zeroing
= 1;
7925 /* Only "{%k}" is allowed here. No need to check mask
7926 register explicitly. */
7927 if (i
.mask
->operand
!= this_operand
)
7929 as_bad (_("invalid zeroing-masking `%s'"),
7938 goto unknown_vec_op
;
7940 if (*op_string
!= '}')
7942 as_bad (_("missing `}' in `%s'"), saved
);
7949 /* We don't know this one. */
7950 as_bad (_("unknown vector operation: `%s'"), saved
);
7958 i386_immediate (char *imm_start
)
7960 char *save_input_line_pointer
;
7961 char *gotfree_input_line
;
7964 i386_operand_type types
;
7966 operand_type_set (&types
, ~0);
7968 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7970 as_bad (_("at most %d immediate operands are allowed"),
7971 MAX_IMMEDIATE_OPERANDS
);
7975 exp
= &im_expressions
[i
.imm_operands
++];
7976 i
.op
[this_operand
].imms
= exp
;
7978 if (is_space_char (*imm_start
))
7981 save_input_line_pointer
= input_line_pointer
;
7982 input_line_pointer
= imm_start
;
7984 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7985 if (gotfree_input_line
)
7986 input_line_pointer
= gotfree_input_line
;
7988 exp_seg
= expression (exp
);
7992 /* Handle vector operations. */
7993 if (*input_line_pointer
== '{')
7995 input_line_pointer
= check_VecOperations (input_line_pointer
,
7997 if (input_line_pointer
== NULL
)
8001 if (*input_line_pointer
)
8002 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8004 input_line_pointer
= save_input_line_pointer
;
8005 if (gotfree_input_line
)
8007 free (gotfree_input_line
);
8009 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8010 exp
->X_op
= O_illegal
;
8013 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8017 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8018 i386_operand_type types
, const char *imm_start
)
8020 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8023 as_bad (_("missing or invalid immediate expression `%s'"),
8027 else if (exp
->X_op
== O_constant
)
8029 /* Size it properly later. */
8030 i
.types
[this_operand
].bitfield
.imm64
= 1;
8031 /* If not 64bit, sign extend val. */
8032 if (flag_code
!= CODE_64BIT
8033 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8035 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8037 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8038 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8039 && exp_seg
!= absolute_section
8040 && exp_seg
!= text_section
8041 && exp_seg
!= data_section
8042 && exp_seg
!= bss_section
8043 && exp_seg
!= undefined_section
8044 && !bfd_is_com_section (exp_seg
))
8046 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8050 else if (!intel_syntax
&& exp_seg
== reg_section
)
8053 as_bad (_("illegal immediate register operand %s"), imm_start
);
8058 /* This is an address. The size of the address will be
8059 determined later, depending on destination register,
8060 suffix, or the default for the section. */
8061 i
.types
[this_operand
].bitfield
.imm8
= 1;
8062 i
.types
[this_operand
].bitfield
.imm16
= 1;
8063 i
.types
[this_operand
].bitfield
.imm32
= 1;
8064 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8065 i
.types
[this_operand
].bitfield
.imm64
= 1;
8066 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8074 i386_scale (char *scale
)
8077 char *save
= input_line_pointer
;
8079 input_line_pointer
= scale
;
8080 val
= get_absolute_expression ();
8085 i
.log2_scale_factor
= 0;
8088 i
.log2_scale_factor
= 1;
8091 i
.log2_scale_factor
= 2;
8094 i
.log2_scale_factor
= 3;
8098 char sep
= *input_line_pointer
;
8100 *input_line_pointer
= '\0';
8101 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8103 *input_line_pointer
= sep
;
8104 input_line_pointer
= save
;
8108 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8110 as_warn (_("scale factor of %d without an index register"),
8111 1 << i
.log2_scale_factor
);
8112 i
.log2_scale_factor
= 0;
8114 scale
= input_line_pointer
;
8115 input_line_pointer
= save
;
8120 i386_displacement (char *disp_start
, char *disp_end
)
8124 char *save_input_line_pointer
;
8125 char *gotfree_input_line
;
8127 i386_operand_type bigdisp
, types
= anydisp
;
8130 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8132 as_bad (_("at most %d displacement operands are allowed"),
8133 MAX_MEMORY_OPERANDS
);
8137 operand_type_set (&bigdisp
, 0);
8138 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8139 || (!current_templates
->start
->opcode_modifier
.jump
8140 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8142 bigdisp
.bitfield
.disp32
= 1;
8143 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8144 if (flag_code
== CODE_64BIT
)
8148 bigdisp
.bitfield
.disp32s
= 1;
8149 bigdisp
.bitfield
.disp64
= 1;
8152 else if ((flag_code
== CODE_16BIT
) ^ override
)
8154 bigdisp
.bitfield
.disp32
= 0;
8155 bigdisp
.bitfield
.disp16
= 1;
8160 /* For PC-relative branches, the width of the displacement
8161 is dependent upon data size, not address size. */
8162 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8163 if (flag_code
== CODE_64BIT
)
8165 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8166 bigdisp
.bitfield
.disp16
= 1;
8169 bigdisp
.bitfield
.disp32
= 1;
8170 bigdisp
.bitfield
.disp32s
= 1;
8176 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8178 : LONG_MNEM_SUFFIX
));
8179 bigdisp
.bitfield
.disp32
= 1;
8180 if ((flag_code
== CODE_16BIT
) ^ override
)
8182 bigdisp
.bitfield
.disp32
= 0;
8183 bigdisp
.bitfield
.disp16
= 1;
8187 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8190 exp
= &disp_expressions
[i
.disp_operands
];
8191 i
.op
[this_operand
].disps
= exp
;
8193 save_input_line_pointer
= input_line_pointer
;
8194 input_line_pointer
= disp_start
;
8195 END_STRING_AND_SAVE (disp_end
);
8197 #ifndef GCC_ASM_O_HACK
8198 #define GCC_ASM_O_HACK 0
8201 END_STRING_AND_SAVE (disp_end
+ 1);
8202 if (i
.types
[this_operand
].bitfield
.baseIndex
8203 && displacement_string_end
[-1] == '+')
8205 /* This hack is to avoid a warning when using the "o"
8206 constraint within gcc asm statements.
8209 #define _set_tssldt_desc(n,addr,limit,type) \
8210 __asm__ __volatile__ ( \
8212 "movw %w1,2+%0\n\t" \
8214 "movb %b1,4+%0\n\t" \
8215 "movb %4,5+%0\n\t" \
8216 "movb $0,6+%0\n\t" \
8217 "movb %h1,7+%0\n\t" \
8219 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8221 This works great except that the output assembler ends
8222 up looking a bit weird if it turns out that there is
8223 no offset. You end up producing code that looks like:
8236 So here we provide the missing zero. */
8238 *displacement_string_end
= '0';
8241 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8242 if (gotfree_input_line
)
8243 input_line_pointer
= gotfree_input_line
;
8245 exp_seg
= expression (exp
);
8248 if (*input_line_pointer
)
8249 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8251 RESTORE_END_STRING (disp_end
+ 1);
8253 input_line_pointer
= save_input_line_pointer
;
8254 if (gotfree_input_line
)
8256 free (gotfree_input_line
);
8258 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8259 exp
->X_op
= O_illegal
;
8262 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8264 RESTORE_END_STRING (disp_end
);
8270 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8271 i386_operand_type types
, const char *disp_start
)
8273 i386_operand_type bigdisp
;
8276 /* We do this to make sure that the section symbol is in
8277 the symbol table. We will ultimately change the relocation
8278 to be relative to the beginning of the section. */
8279 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8280 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8281 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8283 if (exp
->X_op
!= O_symbol
)
8286 if (S_IS_LOCAL (exp
->X_add_symbol
)
8287 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8288 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8289 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8290 exp
->X_op
= O_subtract
;
8291 exp
->X_op_symbol
= GOT_symbol
;
8292 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8293 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8294 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8295 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8297 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8300 else if (exp
->X_op
== O_absent
8301 || exp
->X_op
== O_illegal
8302 || exp
->X_op
== O_big
)
8305 as_bad (_("missing or invalid displacement expression `%s'"),
8310 else if (flag_code
== CODE_64BIT
8311 && !i
.prefix
[ADDR_PREFIX
]
8312 && exp
->X_op
== O_constant
)
8314 /* Since displacement is signed extended to 64bit, don't allow
8315 disp32 and turn off disp32s if they are out of range. */
8316 i
.types
[this_operand
].bitfield
.disp32
= 0;
8317 if (!fits_in_signed_long (exp
->X_add_number
))
8319 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8320 if (i
.types
[this_operand
].bitfield
.baseindex
)
8322 as_bad (_("0x%lx out range of signed 32bit displacement"),
8323 (long) exp
->X_add_number
);
8329 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8330 else if (exp
->X_op
!= O_constant
8331 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8332 && exp_seg
!= absolute_section
8333 && exp_seg
!= text_section
8334 && exp_seg
!= data_section
8335 && exp_seg
!= bss_section
8336 && exp_seg
!= undefined_section
8337 && !bfd_is_com_section (exp_seg
))
8339 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8344 /* Check if this is a displacement only operand. */
8345 bigdisp
= i
.types
[this_operand
];
8346 bigdisp
.bitfield
.disp8
= 0;
8347 bigdisp
.bitfield
.disp16
= 0;
8348 bigdisp
.bitfield
.disp32
= 0;
8349 bigdisp
.bitfield
.disp32s
= 0;
8350 bigdisp
.bitfield
.disp64
= 0;
8351 if (operand_type_all_zero (&bigdisp
))
8352 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8358 /* Make sure the memory operand we've been dealt is valid.
8359 Return 1 on success, 0 on a failure. */
8362 i386_index_check (const char *operand_string
)
8364 const char *kind
= "base/index";
8365 enum flag_code addr_mode
;
8367 if (i
.prefix
[ADDR_PREFIX
])
8368 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8371 addr_mode
= flag_code
;
8373 #if INFER_ADDR_PREFIX
8374 if (i
.mem_operands
== 0)
8376 /* Infer address prefix from the first memory operand. */
8377 const reg_entry
*addr_reg
= i
.base_reg
;
8379 if (addr_reg
== NULL
)
8380 addr_reg
= i
.index_reg
;
8384 if (addr_reg
->reg_num
== RegEip
8385 || addr_reg
->reg_num
== RegEiz
8386 || addr_reg
->reg_type
.bitfield
.reg32
)
8387 addr_mode
= CODE_32BIT
;
8388 else if (flag_code
!= CODE_64BIT
8389 && addr_reg
->reg_type
.bitfield
.reg16
)
8390 addr_mode
= CODE_16BIT
;
8392 if (addr_mode
!= flag_code
)
8394 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8396 /* Change the size of any displacement too. At most one
8397 of Disp16 or Disp32 is set.
8398 FIXME. There doesn't seem to be any real need for
8399 separate Disp16 and Disp32 flags. The same goes for
8400 Imm16 and Imm32. Removing them would probably clean
8401 up the code quite a lot. */
8402 if (flag_code
!= CODE_64BIT
8403 && (i
.types
[this_operand
].bitfield
.disp16
8404 || i
.types
[this_operand
].bitfield
.disp32
))
8405 i
.types
[this_operand
]
8406 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8413 if (current_templates
->start
->opcode_modifier
.isstring
8414 && !current_templates
->start
->opcode_modifier
.immext
8415 && (current_templates
->end
[-1].opcode_modifier
.isstring
8418 /* Memory operands of string insns are special in that they only allow
8419 a single register (rDI, rSI, or rBX) as their memory address. */
8420 const reg_entry
*expected_reg
;
8421 static const char *di_si
[][2] =
8427 static const char *bx
[] = { "ebx", "bx", "rbx" };
8429 kind
= "string address";
8431 if (current_templates
->start
->opcode_modifier
.w
)
8433 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8435 if (!type
.bitfield
.baseindex
8436 || ((!i
.mem_operands
!= !intel_syntax
)
8437 && current_templates
->end
[-1].operand_types
[1]
8438 .bitfield
.baseindex
))
8439 type
= current_templates
->end
[-1].operand_types
[1];
8440 expected_reg
= hash_find (reg_hash
,
8441 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8445 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8447 if (i
.base_reg
!= expected_reg
8449 || operand_type_check (i
.types
[this_operand
], disp
))
8451 /* The second memory operand must have the same size as
8455 && !((addr_mode
== CODE_64BIT
8456 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8457 || (addr_mode
== CODE_32BIT
8458 ? i
.base_reg
->reg_type
.bitfield
.reg32
8459 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8462 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8464 intel_syntax
? '[' : '(',
8466 expected_reg
->reg_name
,
8467 intel_syntax
? ']' : ')');
8474 as_bad (_("`%s' is not a valid %s expression"),
8475 operand_string
, kind
);
8480 if (addr_mode
!= CODE_16BIT
)
8482 /* 32-bit/64-bit checks. */
8484 && (addr_mode
== CODE_64BIT
8485 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8486 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8488 || (i
.base_reg
->reg_num
8489 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8491 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8492 && !i
.index_reg
->reg_type
.bitfield
.regymm
8493 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8494 && ((addr_mode
== CODE_64BIT
8495 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8496 || i
.index_reg
->reg_num
== RegRiz
)
8497 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8498 || i
.index_reg
->reg_num
== RegEiz
))
8499 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8504 /* 16-bit checks. */
8506 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8507 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8509 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8510 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8512 && i
.base_reg
->reg_num
< 6
8513 && i
.index_reg
->reg_num
>= 6
8514 && i
.log2_scale_factor
== 0))))
8521 /* Handle vector immediates. */
8524 RC_SAE_immediate (const char *imm_start
)
8526 unsigned int match_found
, j
;
8527 const char *pstr
= imm_start
;
8535 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8537 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8541 rc_op
.type
= RC_NamesTable
[j
].type
;
8542 rc_op
.operand
= this_operand
;
8543 i
.rounding
= &rc_op
;
8547 as_bad (_("duplicated `%s'"), imm_start
);
8550 pstr
+= RC_NamesTable
[j
].len
;
8560 as_bad (_("Missing '}': '%s'"), imm_start
);
8563 /* RC/SAE immediate string should contain nothing more. */;
8566 as_bad (_("Junk after '}': '%s'"), imm_start
);
8570 exp
= &im_expressions
[i
.imm_operands
++];
8571 i
.op
[this_operand
].imms
= exp
;
8573 exp
->X_op
= O_constant
;
8574 exp
->X_add_number
= 0;
8575 exp
->X_add_symbol
= (symbolS
*) 0;
8576 exp
->X_op_symbol
= (symbolS
*) 0;
8578 i
.types
[this_operand
].bitfield
.imm8
= 1;
8582 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8586 i386_att_operand (char *operand_string
)
8590 char *op_string
= operand_string
;
8592 if (is_space_char (*op_string
))
8595 /* We check for an absolute prefix (differentiating,
8596 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8597 if (*op_string
== ABSOLUTE_PREFIX
)
8600 if (is_space_char (*op_string
))
8602 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8605 /* Check if operand is a register. */
8606 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8608 i386_operand_type temp
;
8610 /* Check for a segment override by searching for ':' after a
8611 segment register. */
8613 if (is_space_char (*op_string
))
8615 if (*op_string
== ':'
8616 && (r
->reg_type
.bitfield
.sreg2
8617 || r
->reg_type
.bitfield
.sreg3
))
8622 i
.seg
[i
.mem_operands
] = &es
;
8625 i
.seg
[i
.mem_operands
] = &cs
;
8628 i
.seg
[i
.mem_operands
] = &ss
;
8631 i
.seg
[i
.mem_operands
] = &ds
;
8634 i
.seg
[i
.mem_operands
] = &fs
;
8637 i
.seg
[i
.mem_operands
] = &gs
;
8641 /* Skip the ':' and whitespace. */
8643 if (is_space_char (*op_string
))
8646 if (!is_digit_char (*op_string
)
8647 && !is_identifier_char (*op_string
)
8648 && *op_string
!= '('
8649 && *op_string
!= ABSOLUTE_PREFIX
)
8651 as_bad (_("bad memory operand `%s'"), op_string
);
8654 /* Handle case of %es:*foo. */
8655 if (*op_string
== ABSOLUTE_PREFIX
)
8658 if (is_space_char (*op_string
))
8660 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8662 goto do_memory_reference
;
8665 /* Handle vector operations. */
8666 if (*op_string
== '{')
8668 op_string
= check_VecOperations (op_string
, NULL
);
8669 if (op_string
== NULL
)
8675 as_bad (_("junk `%s' after register"), op_string
);
8679 temp
.bitfield
.baseindex
= 0;
8680 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8682 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8683 i
.op
[this_operand
].regs
= r
;
8686 else if (*op_string
== REGISTER_PREFIX
)
8688 as_bad (_("bad register name `%s'"), op_string
);
8691 else if (*op_string
== IMMEDIATE_PREFIX
)
8694 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8696 as_bad (_("immediate operand illegal with absolute jump"));
8699 if (!i386_immediate (op_string
))
8702 else if (RC_SAE_immediate (operand_string
))
8704 /* If it is a RC or SAE immediate, do nothing. */
8707 else if (is_digit_char (*op_string
)
8708 || is_identifier_char (*op_string
)
8709 || *op_string
== '"'
8710 || *op_string
== '(')
8712 /* This is a memory reference of some sort. */
8715 /* Start and end of displacement string expression (if found). */
8716 char *displacement_string_start
;
8717 char *displacement_string_end
;
8720 do_memory_reference
:
8721 if ((i
.mem_operands
== 1
8722 && !current_templates
->start
->opcode_modifier
.isstring
)
8723 || i
.mem_operands
== 2)
8725 as_bad (_("too many memory references for `%s'"),
8726 current_templates
->start
->name
);
8730 /* Check for base index form. We detect the base index form by
8731 looking for an ')' at the end of the operand, searching
8732 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8734 base_string
= op_string
+ strlen (op_string
);
8736 /* Handle vector operations. */
8737 vop_start
= strchr (op_string
, '{');
8738 if (vop_start
&& vop_start
< base_string
)
8740 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8742 base_string
= vop_start
;
8746 if (is_space_char (*base_string
))
8749 /* If we only have a displacement, set-up for it to be parsed later. */
8750 displacement_string_start
= op_string
;
8751 displacement_string_end
= base_string
+ 1;
8753 if (*base_string
== ')')
8756 unsigned int parens_balanced
= 1;
8757 /* We've already checked that the number of left & right ()'s are
8758 equal, so this loop will not be infinite. */
8762 if (*base_string
== ')')
8764 if (*base_string
== '(')
8767 while (parens_balanced
);
8769 temp_string
= base_string
;
8771 /* Skip past '(' and whitespace. */
8773 if (is_space_char (*base_string
))
8776 if (*base_string
== ','
8777 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8780 displacement_string_end
= temp_string
;
8782 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8786 base_string
= end_op
;
8787 if (is_space_char (*base_string
))
8791 /* There may be an index reg or scale factor here. */
8792 if (*base_string
== ',')
8795 if (is_space_char (*base_string
))
8798 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8801 base_string
= end_op
;
8802 if (is_space_char (*base_string
))
8804 if (*base_string
== ',')
8807 if (is_space_char (*base_string
))
8810 else if (*base_string
!= ')')
8812 as_bad (_("expecting `,' or `)' "
8813 "after index register in `%s'"),
8818 else if (*base_string
== REGISTER_PREFIX
)
8820 end_op
= strchr (base_string
, ',');
8823 as_bad (_("bad register name `%s'"), base_string
);
8827 /* Check for scale factor. */
8828 if (*base_string
!= ')')
8830 char *end_scale
= i386_scale (base_string
);
8835 base_string
= end_scale
;
8836 if (is_space_char (*base_string
))
8838 if (*base_string
!= ')')
8840 as_bad (_("expecting `)' "
8841 "after scale factor in `%s'"),
8846 else if (!i
.index_reg
)
8848 as_bad (_("expecting index register or scale factor "
8849 "after `,'; got '%c'"),
8854 else if (*base_string
!= ')')
8856 as_bad (_("expecting `,' or `)' "
8857 "after base register in `%s'"),
8862 else if (*base_string
== REGISTER_PREFIX
)
8864 end_op
= strchr (base_string
, ',');
8867 as_bad (_("bad register name `%s'"), base_string
);
8872 /* If there's an expression beginning the operand, parse it,
8873 assuming displacement_string_start and
8874 displacement_string_end are meaningful. */
8875 if (displacement_string_start
!= displacement_string_end
)
8877 if (!i386_displacement (displacement_string_start
,
8878 displacement_string_end
))
8882 /* Special case for (%dx) while doing input/output op. */
8884 && operand_type_equal (&i
.base_reg
->reg_type
,
8885 ®16_inoutportreg
)
8887 && i
.log2_scale_factor
== 0
8888 && i
.seg
[i
.mem_operands
] == 0
8889 && !operand_type_check (i
.types
[this_operand
], disp
))
8891 i
.types
[this_operand
] = inoutportreg
;
8895 if (i386_index_check (operand_string
) == 0)
8897 i
.types
[this_operand
].bitfield
.mem
= 1;
8902 /* It's not a memory operand; argh! */
8903 as_bad (_("invalid char %s beginning operand %d `%s'"),
8904 output_invalid (*op_string
),
8909 return 1; /* Normal return. */
8912 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8913 that an rs_machine_dependent frag may reach. */
8916 i386_frag_max_var (fragS
*frag
)
8918 /* The only relaxable frags are for jumps.
8919 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8920 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8921 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8924 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8926 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8928 /* STT_GNU_IFUNC symbol must go through PLT. */
8929 if ((symbol_get_bfdsym (fr_symbol
)->flags
8930 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8933 if (!S_IS_EXTERNAL (fr_symbol
))
8934 /* Symbol may be weak or local. */
8935 return !S_IS_WEAK (fr_symbol
);
8937 /* Global symbols with non-default visibility can't be preempted. */
8938 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8941 if (fr_var
!= NO_RELOC
)
8942 switch ((enum bfd_reloc_code_real
) fr_var
)
8944 case BFD_RELOC_386_PLT32
:
8945 case BFD_RELOC_X86_64_PLT32
:
8946 /* Symbol with PLT relocatin may be preempted. */
8952 /* Global symbols with default visibility in a shared library may be
8953 preempted by another definition. */
8958 /* md_estimate_size_before_relax()
8960 Called just before relax() for rs_machine_dependent frags. The x86
8961 assembler uses these frags to handle variable size jump
8964 Any symbol that is now undefined will not become defined.
8965 Return the correct fr_subtype in the frag.
8966 Return the initial "guess for variable size of frag" to caller.
8967 The guess is actually the growth beyond the fixed part. Whatever
8968 we do to grow the fixed or variable part contributes to our
8972 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8974 /* We've already got fragP->fr_subtype right; all we have to do is
8975 check for un-relaxable symbols. On an ELF system, we can't relax
8976 an externally visible symbol, because it may be overridden by a
8978 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8979 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8981 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8984 #if defined (OBJ_COFF) && defined (TE_PE)
8985 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8986 && S_IS_WEAK (fragP
->fr_symbol
))
8990 /* Symbol is undefined in this segment, or we need to keep a
8991 reloc so that weak symbols can be overridden. */
8992 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8993 enum bfd_reloc_code_real reloc_type
;
8994 unsigned char *opcode
;
8997 if (fragP
->fr_var
!= NO_RELOC
)
8998 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9000 reloc_type
= BFD_RELOC_16_PCREL
;
9002 reloc_type
= BFD_RELOC_32_PCREL
;
9004 old_fr_fix
= fragP
->fr_fix
;
9005 opcode
= (unsigned char *) fragP
->fr_opcode
;
9007 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9010 /* Make jmp (0xeb) a (d)word displacement jump. */
9012 fragP
->fr_fix
+= size
;
9013 fix_new (fragP
, old_fr_fix
, size
,
9015 fragP
->fr_offset
, 1,
9021 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9023 /* Negate the condition, and branch past an
9024 unconditional jump. */
9027 /* Insert an unconditional jump. */
9029 /* We added two extra opcode bytes, and have a two byte
9031 fragP
->fr_fix
+= 2 + 2;
9032 fix_new (fragP
, old_fr_fix
+ 2, 2,
9034 fragP
->fr_offset
, 1,
9041 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9046 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9048 fragP
->fr_offset
, 1,
9050 fixP
->fx_signed
= 1;
9054 /* This changes the byte-displacement jump 0x7N
9055 to the (d)word-displacement jump 0x0f,0x8N. */
9056 opcode
[1] = opcode
[0] + 0x10;
9057 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9058 /* We've added an opcode byte. */
9059 fragP
->fr_fix
+= 1 + size
;
9060 fix_new (fragP
, old_fr_fix
+ 1, size
,
9062 fragP
->fr_offset
, 1,
9067 BAD_CASE (fragP
->fr_subtype
);
9071 return fragP
->fr_fix
- old_fr_fix
;
9074 /* Guess size depending on current relax state. Initially the relax
9075 state will correspond to a short jump and we return 1, because
9076 the variable part of the frag (the branch offset) is one byte
9077 long. However, we can relax a section more than once and in that
9078 case we must either set fr_subtype back to the unrelaxed state,
9079 or return the value for the appropriate branch. */
9080 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9083 /* Called after relax() is finished.
9085 In: Address of frag.
9086 fr_type == rs_machine_dependent.
9087 fr_subtype is what the address relaxed to.
9089 Out: Any fixSs and constants are set up.
9090 Caller will turn frag into a ".space 0". */
9093 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9096 unsigned char *opcode
;
9097 unsigned char *where_to_put_displacement
= NULL
;
9098 offsetT target_address
;
9099 offsetT opcode_address
;
9100 unsigned int extension
= 0;
9101 offsetT displacement_from_opcode_start
;
9103 opcode
= (unsigned char *) fragP
->fr_opcode
;
9105 /* Address we want to reach in file space. */
9106 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9108 /* Address opcode resides at in file space. */
9109 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9111 /* Displacement from opcode start to fill into instruction. */
9112 displacement_from_opcode_start
= target_address
- opcode_address
;
9114 if ((fragP
->fr_subtype
& BIG
) == 0)
9116 /* Don't have to change opcode. */
9117 extension
= 1; /* 1 opcode + 1 displacement */
9118 where_to_put_displacement
= &opcode
[1];
9122 if (no_cond_jump_promotion
9123 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9124 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9125 _("long jump required"));
9127 switch (fragP
->fr_subtype
)
9129 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9130 extension
= 4; /* 1 opcode + 4 displacement */
9132 where_to_put_displacement
= &opcode
[1];
9135 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9136 extension
= 2; /* 1 opcode + 2 displacement */
9138 where_to_put_displacement
= &opcode
[1];
9141 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9142 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9143 extension
= 5; /* 2 opcode + 4 displacement */
9144 opcode
[1] = opcode
[0] + 0x10;
9145 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9146 where_to_put_displacement
= &opcode
[2];
9149 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9150 extension
= 3; /* 2 opcode + 2 displacement */
9151 opcode
[1] = opcode
[0] + 0x10;
9152 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9153 where_to_put_displacement
= &opcode
[2];
9156 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9161 where_to_put_displacement
= &opcode
[3];
9165 BAD_CASE (fragP
->fr_subtype
);
9170 /* If size if less then four we are sure that the operand fits,
9171 but if it's 4, then it could be that the displacement is larger
9173 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9175 && ((addressT
) (displacement_from_opcode_start
- extension
9176 + ((addressT
) 1 << 31))
9177 > (((addressT
) 2 << 31) - 1)))
9179 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9180 _("jump target out of range"));
9181 /* Make us emit 0. */
9182 displacement_from_opcode_start
= extension
;
9184 /* Now put displacement after opcode. */
9185 md_number_to_chars ((char *) where_to_put_displacement
,
9186 (valueT
) (displacement_from_opcode_start
- extension
),
9187 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9188 fragP
->fr_fix
+= extension
;
9191 /* Apply a fixup (fixP) to segment data, once it has been determined
9192 by our caller that we have all the info we need to fix it up.
9194 Parameter valP is the pointer to the value of the bits.
9196 On the 386, immediates, displacements, and data pointers are all in
9197 the same (little-endian) format, so we don't need to care about which
9201 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9203 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9204 valueT value
= *valP
;
9206 #if !defined (TE_Mach)
9209 switch (fixP
->fx_r_type
)
9215 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9218 case BFD_RELOC_X86_64_32S
:
9219 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9222 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9225 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9230 if (fixP
->fx_addsy
!= NULL
9231 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9232 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9233 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9234 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9235 && !use_rela_relocations
)
9237 /* This is a hack. There should be a better way to handle this.
9238 This covers for the fact that bfd_install_relocation will
9239 subtract the current location (for partial_inplace, PC relative
9240 relocations); see more below. */
9244 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9247 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9249 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9252 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9255 || (symbol_section_p (fixP
->fx_addsy
)
9256 && sym_seg
!= absolute_section
))
9257 && !generic_force_reloc (fixP
))
9259 /* Yes, we add the values in twice. This is because
9260 bfd_install_relocation subtracts them out again. I think
9261 bfd_install_relocation is broken, but I don't dare change
9263 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9267 #if defined (OBJ_COFF) && defined (TE_PE)
9268 /* For some reason, the PE format does not store a
9269 section address offset for a PC relative symbol. */
9270 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9271 || S_IS_WEAK (fixP
->fx_addsy
))
9272 value
+= md_pcrel_from (fixP
);
9275 #if defined (OBJ_COFF) && defined (TE_PE)
9276 if (fixP
->fx_addsy
!= NULL
9277 && S_IS_WEAK (fixP
->fx_addsy
)
9278 /* PR 16858: Do not modify weak function references. */
9279 && ! fixP
->fx_pcrel
)
9281 #if !defined (TE_PEP)
9282 /* For x86 PE weak function symbols are neither PC-relative
9283 nor do they set S_IS_FUNCTION. So the only reliable way
9284 to detect them is to check the flags of their containing
9286 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9287 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9291 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9295 /* Fix a few things - the dynamic linker expects certain values here,
9296 and we must not disappoint it. */
9297 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9298 if (IS_ELF
&& fixP
->fx_addsy
)
9299 switch (fixP
->fx_r_type
)
9301 case BFD_RELOC_386_PLT32
:
9302 case BFD_RELOC_X86_64_PLT32
:
9303 /* Make the jump instruction point to the address of the operand. At
9304 runtime we merely add the offset to the actual PLT entry. */
9308 case BFD_RELOC_386_TLS_GD
:
9309 case BFD_RELOC_386_TLS_LDM
:
9310 case BFD_RELOC_386_TLS_IE_32
:
9311 case BFD_RELOC_386_TLS_IE
:
9312 case BFD_RELOC_386_TLS_GOTIE
:
9313 case BFD_RELOC_386_TLS_GOTDESC
:
9314 case BFD_RELOC_X86_64_TLSGD
:
9315 case BFD_RELOC_X86_64_TLSLD
:
9316 case BFD_RELOC_X86_64_GOTTPOFF
:
9317 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9318 value
= 0; /* Fully resolved at runtime. No addend. */
9320 case BFD_RELOC_386_TLS_LE
:
9321 case BFD_RELOC_386_TLS_LDO_32
:
9322 case BFD_RELOC_386_TLS_LE_32
:
9323 case BFD_RELOC_X86_64_DTPOFF32
:
9324 case BFD_RELOC_X86_64_DTPOFF64
:
9325 case BFD_RELOC_X86_64_TPOFF32
:
9326 case BFD_RELOC_X86_64_TPOFF64
:
9327 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9330 case BFD_RELOC_386_TLS_DESC_CALL
:
9331 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9332 value
= 0; /* Fully resolved at runtime. No addend. */
9333 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9337 case BFD_RELOC_386_GOT32
:
9338 case BFD_RELOC_X86_64_GOT32
:
9339 value
= 0; /* Fully resolved at runtime. No addend. */
9342 case BFD_RELOC_VTABLE_INHERIT
:
9343 case BFD_RELOC_VTABLE_ENTRY
:
9350 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9352 #endif /* !defined (TE_Mach) */
9354 /* Are we finished with this relocation now? */
9355 if (fixP
->fx_addsy
== NULL
)
9357 #if defined (OBJ_COFF) && defined (TE_PE)
9358 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9361 /* Remember value for tc_gen_reloc. */
9362 fixP
->fx_addnumber
= value
;
9363 /* Clear out the frag for now. */
9367 else if (use_rela_relocations
)
9369 fixP
->fx_no_overflow
= 1;
9370 /* Remember value for tc_gen_reloc. */
9371 fixP
->fx_addnumber
= value
;
9375 md_number_to_chars (p
, value
, fixP
->fx_size
);
9379 md_atof (int type
, char *litP
, int *sizeP
)
9381 /* This outputs the LITTLENUMs in REVERSE order;
9382 in accord with the bigendian 386. */
9383 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9386 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9389 output_invalid (int c
)
9392 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9395 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9396 "(0x%x)", (unsigned char) c
);
9397 return output_invalid_buf
;
9400 /* REG_STRING starts *before* REGISTER_PREFIX. */
9402 static const reg_entry
*
9403 parse_real_register (char *reg_string
, char **end_op
)
9405 char *s
= reg_string
;
9407 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9410 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9411 if (*s
== REGISTER_PREFIX
)
9414 if (is_space_char (*s
))
9418 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9420 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9421 return (const reg_entry
*) NULL
;
9425 /* For naked regs, make sure that we are not dealing with an identifier.
9426 This prevents confusing an identifier like `eax_var' with register
9428 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9429 return (const reg_entry
*) NULL
;
9433 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9435 /* Handle floating point regs, allowing spaces in the (i) part. */
9436 if (r
== i386_regtab
/* %st is first entry of table */)
9438 if (is_space_char (*s
))
9443 if (is_space_char (*s
))
9445 if (*s
>= '0' && *s
<= '7')
9449 if (is_space_char (*s
))
9454 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9459 /* We have "%st(" then garbage. */
9460 return (const reg_entry
*) NULL
;
9464 if (r
== NULL
|| allow_pseudo_reg
)
9467 if (operand_type_all_zero (&r
->reg_type
))
9468 return (const reg_entry
*) NULL
;
9470 if ((r
->reg_type
.bitfield
.reg32
9471 || r
->reg_type
.bitfield
.sreg3
9472 || r
->reg_type
.bitfield
.control
9473 || r
->reg_type
.bitfield
.debug
9474 || r
->reg_type
.bitfield
.test
)
9475 && !cpu_arch_flags
.bitfield
.cpui386
)
9476 return (const reg_entry
*) NULL
;
9478 if (r
->reg_type
.bitfield
.floatreg
9479 && !cpu_arch_flags
.bitfield
.cpu8087
9480 && !cpu_arch_flags
.bitfield
.cpu287
9481 && !cpu_arch_flags
.bitfield
.cpu387
)
9482 return (const reg_entry
*) NULL
;
9484 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9485 return (const reg_entry
*) NULL
;
9487 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9488 return (const reg_entry
*) NULL
;
9490 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9491 return (const reg_entry
*) NULL
;
9493 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9494 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9495 return (const reg_entry
*) NULL
;
9497 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9498 if (!allow_index_reg
9499 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9500 return (const reg_entry
*) NULL
;
9502 /* Upper 16 vector register is only available with VREX in 64bit
9504 if ((r
->reg_flags
& RegVRex
))
9506 if (!cpu_arch_flags
.bitfield
.cpuvrex
9507 || flag_code
!= CODE_64BIT
)
9508 return (const reg_entry
*) NULL
;
9513 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9514 || r
->reg_type
.bitfield
.reg64
)
9515 && (!cpu_arch_flags
.bitfield
.cpulm
9516 || !operand_type_equal (&r
->reg_type
, &control
))
9517 && flag_code
!= CODE_64BIT
)
9518 return (const reg_entry
*) NULL
;
9520 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9521 return (const reg_entry
*) NULL
;
9526 /* REG_STRING starts *before* REGISTER_PREFIX. */
9528 static const reg_entry
*
9529 parse_register (char *reg_string
, char **end_op
)
9533 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9534 r
= parse_real_register (reg_string
, end_op
);
9539 char *save
= input_line_pointer
;
9543 input_line_pointer
= reg_string
;
9544 c
= get_symbol_name (®_string
);
9545 symbolP
= symbol_find (reg_string
);
9546 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9548 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9550 know (e
->X_op
== O_register
);
9551 know (e
->X_add_number
>= 0
9552 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9553 r
= i386_regtab
+ e
->X_add_number
;
9554 if ((r
->reg_flags
& RegVRex
))
9556 *end_op
= input_line_pointer
;
9558 *input_line_pointer
= c
;
9559 input_line_pointer
= save
;
9565 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9568 char *end
= input_line_pointer
;
9571 r
= parse_register (name
, &input_line_pointer
);
9572 if (r
&& end
<= input_line_pointer
)
9574 *nextcharP
= *input_line_pointer
;
9575 *input_line_pointer
= 0;
9576 e
->X_op
= O_register
;
9577 e
->X_add_number
= r
- i386_regtab
;
9580 input_line_pointer
= end
;
9582 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9586 md_operand (expressionS
*e
)
9591 switch (*input_line_pointer
)
9593 case REGISTER_PREFIX
:
9594 r
= parse_real_register (input_line_pointer
, &end
);
9597 e
->X_op
= O_register
;
9598 e
->X_add_number
= r
- i386_regtab
;
9599 input_line_pointer
= end
;
9604 gas_assert (intel_syntax
);
9605 end
= input_line_pointer
++;
9607 if (*input_line_pointer
== ']')
9609 ++input_line_pointer
;
9610 e
->X_op_symbol
= make_expr_symbol (e
);
9611 e
->X_add_symbol
= NULL
;
9612 e
->X_add_number
= 0;
9618 input_line_pointer
= end
;
9625 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9626 const char *md_shortopts
= "kVQ:sqn";
9628 const char *md_shortopts
= "qn";
9631 #define OPTION_32 (OPTION_MD_BASE + 0)
9632 #define OPTION_64 (OPTION_MD_BASE + 1)
9633 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9634 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9635 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9636 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9637 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9638 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9639 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9640 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9641 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9642 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9643 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9644 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9645 #define OPTION_X32 (OPTION_MD_BASE + 14)
9646 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9647 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9648 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9649 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9650 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9651 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9652 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9653 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9654 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9655 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9656 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9658 struct option md_longopts
[] =
9660 {"32", no_argument
, NULL
, OPTION_32
},
9661 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9662 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9663 {"64", no_argument
, NULL
, OPTION_64
},
9665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9666 {"x32", no_argument
, NULL
, OPTION_X32
},
9667 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9669 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9670 {"march", required_argument
, NULL
, OPTION_MARCH
},
9671 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9672 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9673 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9674 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9675 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9676 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9677 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9678 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9679 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9680 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9681 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9682 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9683 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9684 # if defined (TE_PE) || defined (TE_PEP)
9685 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9687 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9688 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9689 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9690 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9691 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9692 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9693 {NULL
, no_argument
, NULL
, 0}
9695 size_t md_longopts_size
= sizeof (md_longopts
);
9698 md_parse_option (int c
, char *arg
)
9706 optimize_align_code
= 0;
9713 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9714 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9715 should be emitted or not. FIXME: Not implemented. */
9719 /* -V: SVR4 argument to print version ID. */
9721 print_version_id ();
9724 /* -k: Ignore for FreeBSD compatibility. */
9729 /* -s: On i386 Solaris, this tells the native assembler to use
9730 .stab instead of .stab.excl. We always use .stab anyhow. */
9733 case OPTION_MSHARED
:
9737 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9738 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9741 const char **list
, **l
;
9743 list
= bfd_target_list ();
9744 for (l
= list
; *l
!= NULL
; l
++)
9745 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9746 || strcmp (*l
, "coff-x86-64") == 0
9747 || strcmp (*l
, "pe-x86-64") == 0
9748 || strcmp (*l
, "pei-x86-64") == 0
9749 || strcmp (*l
, "mach-o-x86-64") == 0)
9751 default_arch
= "x86_64";
9755 as_fatal (_("no compiled in support for x86_64"));
9761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9765 const char **list
, **l
;
9767 list
= bfd_target_list ();
9768 for (l
= list
; *l
!= NULL
; l
++)
9769 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9771 default_arch
= "x86_64:32";
9775 as_fatal (_("no compiled in support for 32bit x86_64"));
9779 as_fatal (_("32bit x86_64 is only supported for ELF"));
9784 default_arch
= "i386";
9788 #ifdef SVR4_COMMENT_CHARS
9793 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9795 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9799 i386_comment_chars
= n
;
9805 arch
= xstrdup (arg
);
9809 as_fatal (_("invalid -march= option: `%s'"), arg
);
9810 next
= strchr (arch
, '+');
9813 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9815 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9818 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9821 cpu_arch_name
= cpu_arch
[j
].name
;
9822 cpu_sub_arch_name
= NULL
;
9823 cpu_arch_flags
= cpu_arch
[j
].flags
;
9824 cpu_arch_isa
= cpu_arch
[j
].type
;
9825 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9826 if (!cpu_arch_tune_set
)
9828 cpu_arch_tune
= cpu_arch_isa
;
9829 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9833 else if (*cpu_arch
[j
].name
== '.'
9834 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9836 /* ISA entension. */
9837 i386_cpu_flags flags
;
9839 if (!cpu_arch
[j
].negated
)
9840 flags
= cpu_flags_or (cpu_arch_flags
,
9843 flags
= cpu_flags_and_not (cpu_arch_flags
,
9846 if (!valid_iamcu_cpu_flags (&flags
))
9847 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9848 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9850 if (cpu_sub_arch_name
)
9852 char *name
= cpu_sub_arch_name
;
9853 cpu_sub_arch_name
= concat (name
,
9855 (const char *) NULL
);
9859 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9860 cpu_arch_flags
= flags
;
9861 cpu_arch_isa_flags
= flags
;
9867 if (j
>= ARRAY_SIZE (cpu_arch
))
9868 as_fatal (_("invalid -march= option: `%s'"), arg
);
9872 while (next
!= NULL
);
9877 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9878 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9880 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9882 cpu_arch_tune_set
= 1;
9883 cpu_arch_tune
= cpu_arch
[j
].type
;
9884 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9888 if (j
>= ARRAY_SIZE (cpu_arch
))
9889 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9892 case OPTION_MMNEMONIC
:
9893 if (strcasecmp (arg
, "att") == 0)
9895 else if (strcasecmp (arg
, "intel") == 0)
9898 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9901 case OPTION_MSYNTAX
:
9902 if (strcasecmp (arg
, "att") == 0)
9904 else if (strcasecmp (arg
, "intel") == 0)
9907 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9910 case OPTION_MINDEX_REG
:
9911 allow_index_reg
= 1;
9914 case OPTION_MNAKED_REG
:
9915 allow_naked_reg
= 1;
9918 case OPTION_MOLD_GCC
:
9922 case OPTION_MSSE2AVX
:
9926 case OPTION_MSSE_CHECK
:
9927 if (strcasecmp (arg
, "error") == 0)
9928 sse_check
= check_error
;
9929 else if (strcasecmp (arg
, "warning") == 0)
9930 sse_check
= check_warning
;
9931 else if (strcasecmp (arg
, "none") == 0)
9932 sse_check
= check_none
;
9934 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9937 case OPTION_MOPERAND_CHECK
:
9938 if (strcasecmp (arg
, "error") == 0)
9939 operand_check
= check_error
;
9940 else if (strcasecmp (arg
, "warning") == 0)
9941 operand_check
= check_warning
;
9942 else if (strcasecmp (arg
, "none") == 0)
9943 operand_check
= check_none
;
9945 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9948 case OPTION_MAVXSCALAR
:
9949 if (strcasecmp (arg
, "128") == 0)
9951 else if (strcasecmp (arg
, "256") == 0)
9954 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9957 case OPTION_MADD_BND_PREFIX
:
9961 case OPTION_MEVEXLIG
:
9962 if (strcmp (arg
, "128") == 0)
9964 else if (strcmp (arg
, "256") == 0)
9966 else if (strcmp (arg
, "512") == 0)
9969 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9972 case OPTION_MEVEXRCIG
:
9973 if (strcmp (arg
, "rne") == 0)
9975 else if (strcmp (arg
, "rd") == 0)
9977 else if (strcmp (arg
, "ru") == 0)
9979 else if (strcmp (arg
, "rz") == 0)
9982 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9985 case OPTION_MEVEXWIG
:
9986 if (strcmp (arg
, "0") == 0)
9988 else if (strcmp (arg
, "1") == 0)
9991 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9994 # if defined (TE_PE) || defined (TE_PEP)
9995 case OPTION_MBIG_OBJ
:
10000 case OPTION_MOMIT_LOCK_PREFIX
:
10001 if (strcasecmp (arg
, "yes") == 0)
10002 omit_lock_prefix
= 1;
10003 else if (strcasecmp (arg
, "no") == 0)
10004 omit_lock_prefix
= 0;
10006 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10009 case OPTION_MFENCE_AS_LOCK_ADD
:
10010 if (strcasecmp (arg
, "yes") == 0)
10012 else if (strcasecmp (arg
, "no") == 0)
10015 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10018 case OPTION_MRELAX_RELOCATIONS
:
10019 if (strcasecmp (arg
, "yes") == 0)
10020 generate_relax_relocations
= 1;
10021 else if (strcasecmp (arg
, "no") == 0)
10022 generate_relax_relocations
= 0;
10024 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10027 case OPTION_MAMD64
:
10028 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
10029 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
10030 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
10031 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
10034 case OPTION_MINTEL64
:
10035 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
10036 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
10037 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
10038 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
10047 #define MESSAGE_TEMPLATE \
10051 show_arch (FILE *stream
, int ext
, int check
)
10053 static char message
[] = MESSAGE_TEMPLATE
;
10054 char *start
= message
+ 27;
10056 int size
= sizeof (MESSAGE_TEMPLATE
);
10063 left
= size
- (start
- message
);
10064 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10066 /* Should it be skipped? */
10067 if (cpu_arch
[j
].skip
)
10070 name
= cpu_arch
[j
].name
;
10071 len
= cpu_arch
[j
].len
;
10074 /* It is an extension. Skip if we aren't asked to show it. */
10085 /* It is an processor. Skip if we show only extension. */
10088 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10090 /* It is an impossible processor - skip. */
10094 /* Reserve 2 spaces for ", " or ",\0" */
10097 /* Check if there is any room. */
10105 p
= mempcpy (p
, name
, len
);
10109 /* Output the current message now and start a new one. */
10112 fprintf (stream
, "%s\n", message
);
10114 left
= size
- (start
- message
) - len
- 2;
10116 gas_assert (left
>= 0);
10118 p
= mempcpy (p
, name
, len
);
10123 fprintf (stream
, "%s\n", message
);
10127 md_show_usage (FILE *stream
)
10129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10130 fprintf (stream
, _("\
10132 -V print assembler version number\n\
10135 fprintf (stream
, _("\
10136 -n Do not optimize code alignment\n\
10137 -q quieten some warnings\n"));
10138 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10139 fprintf (stream
, _("\
10142 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10143 || defined (TE_PE) || defined (TE_PEP))
10144 fprintf (stream
, _("\
10145 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10147 #ifdef SVR4_COMMENT_CHARS
10148 fprintf (stream
, _("\
10149 --divide do not treat `/' as a comment character\n"));
10151 fprintf (stream
, _("\
10152 --divide ignored\n"));
10154 fprintf (stream
, _("\
10155 -march=CPU[,+EXTENSION...]\n\
10156 generate code for CPU and EXTENSION, CPU is one of:\n"));
10157 show_arch (stream
, 0, 1);
10158 fprintf (stream
, _("\
10159 EXTENSION is combination of:\n"));
10160 show_arch (stream
, 1, 0);
10161 fprintf (stream
, _("\
10162 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10163 show_arch (stream
, 0, 0);
10164 fprintf (stream
, _("\
10165 -msse2avx encode SSE instructions with VEX prefix\n"));
10166 fprintf (stream
, _("\
10167 -msse-check=[none|error|warning]\n\
10168 check SSE instructions\n"));
10169 fprintf (stream
, _("\
10170 -moperand-check=[none|error|warning]\n\
10171 check operand combinations for validity\n"));
10172 fprintf (stream
, _("\
10173 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10175 fprintf (stream
, _("\
10176 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10178 fprintf (stream
, _("\
10179 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10180 for EVEX.W bit ignored instructions\n"));
10181 fprintf (stream
, _("\
10182 -mevexrcig=[rne|rd|ru|rz]\n\
10183 encode EVEX instructions with specific EVEX.RC value\n\
10184 for SAE-only ignored instructions\n"));
10185 fprintf (stream
, _("\
10186 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10187 fprintf (stream
, _("\
10188 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10189 fprintf (stream
, _("\
10190 -mindex-reg support pseudo index registers\n"));
10191 fprintf (stream
, _("\
10192 -mnaked-reg don't require `%%' prefix for registers\n"));
10193 fprintf (stream
, _("\
10194 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10195 fprintf (stream
, _("\
10196 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10197 fprintf (stream
, _("\
10198 -mshared disable branch optimization for shared code\n"));
10199 # if defined (TE_PE) || defined (TE_PEP)
10200 fprintf (stream
, _("\
10201 -mbig-obj generate big object files\n"));
10203 fprintf (stream
, _("\
10204 -momit-lock-prefix=[no|yes]\n\
10205 strip all lock prefixes\n"));
10206 fprintf (stream
, _("\
10207 -mfence-as-lock-add=[no|yes]\n\
10208 encode lfence, mfence and sfence as\n\
10209 lock addl $0x0, (%%{re}sp)\n"));
10210 fprintf (stream
, _("\
10211 -mrelax-relocations=[no|yes]\n\
10212 generate relax relocations\n"));
10213 fprintf (stream
, _("\
10214 -mamd64 accept only AMD64 ISA\n"));
10215 fprintf (stream
, _("\
10216 -mintel64 accept only Intel64 ISA\n"));
10219 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10220 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10221 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10223 /* Pick the target format to use. */
10226 i386_target_format (void)
10228 if (!strncmp (default_arch
, "x86_64", 6))
10230 update_code_flag (CODE_64BIT
, 1);
10231 if (default_arch
[6] == '\0')
10232 x86_elf_abi
= X86_64_ABI
;
10234 x86_elf_abi
= X86_64_X32_ABI
;
10236 else if (!strcmp (default_arch
, "i386"))
10237 update_code_flag (CODE_32BIT
, 1);
10238 else if (!strcmp (default_arch
, "iamcu"))
10240 update_code_flag (CODE_32BIT
, 1);
10241 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10243 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10244 cpu_arch_name
= "iamcu";
10245 cpu_sub_arch_name
= NULL
;
10246 cpu_arch_flags
= iamcu_flags
;
10247 cpu_arch_isa
= PROCESSOR_IAMCU
;
10248 cpu_arch_isa_flags
= iamcu_flags
;
10249 if (!cpu_arch_tune_set
)
10251 cpu_arch_tune
= cpu_arch_isa
;
10252 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10256 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10260 as_fatal (_("unknown architecture"));
10262 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10263 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10264 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10265 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10267 switch (OUTPUT_FLAVOR
)
10269 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10270 case bfd_target_aout_flavour
:
10271 return AOUT_TARGET_FORMAT
;
10273 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10274 # if defined (TE_PE) || defined (TE_PEP)
10275 case bfd_target_coff_flavour
:
10276 if (flag_code
== CODE_64BIT
)
10277 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10280 # elif defined (TE_GO32)
10281 case bfd_target_coff_flavour
:
10282 return "coff-go32";
10284 case bfd_target_coff_flavour
:
10285 return "coff-i386";
10288 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10289 case bfd_target_elf_flavour
:
10291 const char *format
;
10293 switch (x86_elf_abi
)
10296 format
= ELF_TARGET_FORMAT
;
10299 use_rela_relocations
= 1;
10301 format
= ELF_TARGET_FORMAT64
;
10303 case X86_64_X32_ABI
:
10304 use_rela_relocations
= 1;
10306 disallow_64bit_reloc
= 1;
10307 format
= ELF_TARGET_FORMAT32
;
10310 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10312 if (x86_elf_abi
!= X86_64_ABI
)
10313 as_fatal (_("Intel L1OM is 64bit only"));
10314 return ELF_TARGET_L1OM_FORMAT
;
10316 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10318 if (x86_elf_abi
!= X86_64_ABI
)
10319 as_fatal (_("Intel K1OM is 64bit only"));
10320 return ELF_TARGET_K1OM_FORMAT
;
10322 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10324 if (x86_elf_abi
!= I386_ABI
)
10325 as_fatal (_("Intel MCU is 32bit only"));
10326 return ELF_TARGET_IAMCU_FORMAT
;
10332 #if defined (OBJ_MACH_O)
10333 case bfd_target_mach_o_flavour
:
10334 if (flag_code
== CODE_64BIT
)
10336 use_rela_relocations
= 1;
10338 return "mach-o-x86-64";
10341 return "mach-o-i386";
10349 #endif /* OBJ_MAYBE_ more than one */
10352 md_undefined_symbol (char *name
)
10354 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10355 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10356 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10357 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10361 if (symbol_find (name
))
10362 as_bad (_("GOT already in symbol table"));
10363 GOT_symbol
= symbol_new (name
, undefined_section
,
10364 (valueT
) 0, &zero_address_frag
);
10371 /* Round up a section size to the appropriate boundary. */
10374 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10376 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10377 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10379 /* For a.out, force the section size to be aligned. If we don't do
10380 this, BFD will align it for us, but it will not write out the
10381 final bytes of the section. This may be a bug in BFD, but it is
10382 easier to fix it here since that is how the other a.out targets
10386 align
= bfd_get_section_alignment (stdoutput
, segment
);
10387 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10394 /* On the i386, PC-relative offsets are relative to the start of the
10395 next instruction. That is, the address of the offset, plus its
10396 size, since the offset is always the last part of the insn. */
10399 md_pcrel_from (fixS
*fixP
)
10401 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10407 s_bss (int ignore ATTRIBUTE_UNUSED
)
10411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10413 obj_elf_section_change_hook ();
10415 temp
= get_absolute_expression ();
10416 subseg_set (bss_section
, (subsegT
) temp
);
10417 demand_empty_rest_of_line ();
10423 i386_validate_fix (fixS
*fixp
)
10425 if (fixp
->fx_subsy
)
10427 if (fixp
->fx_subsy
== GOT_symbol
)
10429 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10433 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10434 if (fixp
->fx_tcbit2
)
10435 fixp
->fx_r_type
= (fixp
->fx_tcbit
10436 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10437 : BFD_RELOC_X86_64_GOTPCRELX
);
10440 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10445 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10447 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10449 fixp
->fx_subsy
= 0;
10452 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10453 else if (!object_64bit
)
10455 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10456 && fixp
->fx_tcbit2
)
10457 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10463 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10466 bfd_reloc_code_real_type code
;
10468 switch (fixp
->fx_r_type
)
10470 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10471 case BFD_RELOC_SIZE32
:
10472 case BFD_RELOC_SIZE64
:
10473 if (S_IS_DEFINED (fixp
->fx_addsy
)
10474 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10476 /* Resolve size relocation against local symbol to size of
10477 the symbol plus addend. */
10478 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10479 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10480 && !fits_in_unsigned_long (value
))
10481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10482 _("symbol size computation overflow"));
10483 fixp
->fx_addsy
= NULL
;
10484 fixp
->fx_subsy
= NULL
;
10485 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10490 case BFD_RELOC_X86_64_PLT32
:
10491 case BFD_RELOC_X86_64_GOT32
:
10492 case BFD_RELOC_X86_64_GOTPCREL
:
10493 case BFD_RELOC_X86_64_GOTPCRELX
:
10494 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10495 case BFD_RELOC_386_PLT32
:
10496 case BFD_RELOC_386_GOT32
:
10497 case BFD_RELOC_386_GOT32X
:
10498 case BFD_RELOC_386_GOTOFF
:
10499 case BFD_RELOC_386_GOTPC
:
10500 case BFD_RELOC_386_TLS_GD
:
10501 case BFD_RELOC_386_TLS_LDM
:
10502 case BFD_RELOC_386_TLS_LDO_32
:
10503 case BFD_RELOC_386_TLS_IE_32
:
10504 case BFD_RELOC_386_TLS_IE
:
10505 case BFD_RELOC_386_TLS_GOTIE
:
10506 case BFD_RELOC_386_TLS_LE_32
:
10507 case BFD_RELOC_386_TLS_LE
:
10508 case BFD_RELOC_386_TLS_GOTDESC
:
10509 case BFD_RELOC_386_TLS_DESC_CALL
:
10510 case BFD_RELOC_X86_64_TLSGD
:
10511 case BFD_RELOC_X86_64_TLSLD
:
10512 case BFD_RELOC_X86_64_DTPOFF32
:
10513 case BFD_RELOC_X86_64_DTPOFF64
:
10514 case BFD_RELOC_X86_64_GOTTPOFF
:
10515 case BFD_RELOC_X86_64_TPOFF32
:
10516 case BFD_RELOC_X86_64_TPOFF64
:
10517 case BFD_RELOC_X86_64_GOTOFF64
:
10518 case BFD_RELOC_X86_64_GOTPC32
:
10519 case BFD_RELOC_X86_64_GOT64
:
10520 case BFD_RELOC_X86_64_GOTPCREL64
:
10521 case BFD_RELOC_X86_64_GOTPC64
:
10522 case BFD_RELOC_X86_64_GOTPLT64
:
10523 case BFD_RELOC_X86_64_PLTOFF64
:
10524 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10525 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10526 case BFD_RELOC_RVA
:
10527 case BFD_RELOC_VTABLE_ENTRY
:
10528 case BFD_RELOC_VTABLE_INHERIT
:
10530 case BFD_RELOC_32_SECREL
:
10532 code
= fixp
->fx_r_type
;
10534 case BFD_RELOC_X86_64_32S
:
10535 if (!fixp
->fx_pcrel
)
10537 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10538 code
= fixp
->fx_r_type
;
10542 if (fixp
->fx_pcrel
)
10544 switch (fixp
->fx_size
)
10547 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10548 _("can not do %d byte pc-relative relocation"),
10550 code
= BFD_RELOC_32_PCREL
;
10552 case 1: code
= BFD_RELOC_8_PCREL
; break;
10553 case 2: code
= BFD_RELOC_16_PCREL
; break;
10554 case 4: code
= BFD_RELOC_32_PCREL
; break;
10556 case 8: code
= BFD_RELOC_64_PCREL
; break;
10562 switch (fixp
->fx_size
)
10565 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10566 _("can not do %d byte relocation"),
10568 code
= BFD_RELOC_32
;
10570 case 1: code
= BFD_RELOC_8
; break;
10571 case 2: code
= BFD_RELOC_16
; break;
10572 case 4: code
= BFD_RELOC_32
; break;
10574 case 8: code
= BFD_RELOC_64
; break;
10581 if ((code
== BFD_RELOC_32
10582 || code
== BFD_RELOC_32_PCREL
10583 || code
== BFD_RELOC_X86_64_32S
)
10585 && fixp
->fx_addsy
== GOT_symbol
)
10588 code
= BFD_RELOC_386_GOTPC
;
10590 code
= BFD_RELOC_X86_64_GOTPC32
;
10592 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10594 && fixp
->fx_addsy
== GOT_symbol
)
10596 code
= BFD_RELOC_X86_64_GOTPC64
;
10599 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10600 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10601 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10603 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10605 if (!use_rela_relocations
)
10607 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10608 vtable entry to be used in the relocation's section offset. */
10609 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10610 rel
->address
= fixp
->fx_offset
;
10611 #if defined (OBJ_COFF) && defined (TE_PE)
10612 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10613 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10618 /* Use the rela in 64bit mode. */
10621 if (disallow_64bit_reloc
)
10624 case BFD_RELOC_X86_64_DTPOFF64
:
10625 case BFD_RELOC_X86_64_TPOFF64
:
10626 case BFD_RELOC_64_PCREL
:
10627 case BFD_RELOC_X86_64_GOTOFF64
:
10628 case BFD_RELOC_X86_64_GOT64
:
10629 case BFD_RELOC_X86_64_GOTPCREL64
:
10630 case BFD_RELOC_X86_64_GOTPC64
:
10631 case BFD_RELOC_X86_64_GOTPLT64
:
10632 case BFD_RELOC_X86_64_PLTOFF64
:
10633 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10634 _("cannot represent relocation type %s in x32 mode"),
10635 bfd_get_reloc_code_name (code
));
10641 if (!fixp
->fx_pcrel
)
10642 rel
->addend
= fixp
->fx_offset
;
10646 case BFD_RELOC_X86_64_PLT32
:
10647 case BFD_RELOC_X86_64_GOT32
:
10648 case BFD_RELOC_X86_64_GOTPCREL
:
10649 case BFD_RELOC_X86_64_GOTPCRELX
:
10650 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10651 case BFD_RELOC_X86_64_TLSGD
:
10652 case BFD_RELOC_X86_64_TLSLD
:
10653 case BFD_RELOC_X86_64_GOTTPOFF
:
10654 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10655 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10656 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10659 rel
->addend
= (section
->vma
10661 + fixp
->fx_addnumber
10662 + md_pcrel_from (fixp
));
10667 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10668 if (rel
->howto
== NULL
)
10670 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10671 _("cannot represent relocation type %s"),
10672 bfd_get_reloc_code_name (code
));
10673 /* Set howto to a garbage value so that we can keep going. */
10674 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10675 gas_assert (rel
->howto
!= NULL
);
10681 #include "tc-i386-intel.c"
10684 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10686 int saved_naked_reg
;
10687 char saved_register_dot
;
10689 saved_naked_reg
= allow_naked_reg
;
10690 allow_naked_reg
= 1;
10691 saved_register_dot
= register_chars
['.'];
10692 register_chars
['.'] = '.';
10693 allow_pseudo_reg
= 1;
10694 expression_and_evaluate (exp
);
10695 allow_pseudo_reg
= 0;
10696 register_chars
['.'] = saved_register_dot
;
10697 allow_naked_reg
= saved_naked_reg
;
10699 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10701 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10703 exp
->X_op
= O_constant
;
10704 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10705 .dw2_regnum
[flag_code
>> 1];
10708 exp
->X_op
= O_illegal
;
10713 tc_x86_frame_initial_instructions (void)
10715 static unsigned int sp_regno
[2];
10717 if (!sp_regno
[flag_code
>> 1])
10719 char *saved_input
= input_line_pointer
;
10720 char sp
[][4] = {"esp", "rsp"};
10723 input_line_pointer
= sp
[flag_code
>> 1];
10724 tc_x86_parse_to_dw2regnum (&exp
);
10725 gas_assert (exp
.X_op
== O_constant
);
10726 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10727 input_line_pointer
= saved_input
;
10730 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10731 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10735 x86_dwarf2_addr_size (void)
10737 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10738 if (x86_elf_abi
== X86_64_X32_ABI
)
10741 return bfd_arch_bits_per_address (stdoutput
) / 8;
10745 i386_elf_section_type (const char *str
, size_t len
)
10747 if (flag_code
== CODE_64BIT
10748 && len
== sizeof ("unwind") - 1
10749 && strncmp (str
, "unwind", 6) == 0)
10750 return SHT_X86_64_UNWIND
;
10757 i386_solaris_fix_up_eh_frame (segT sec
)
10759 if (flag_code
== CODE_64BIT
)
10760 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10766 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10770 exp
.X_op
= O_secrel
;
10771 exp
.X_add_symbol
= symbol
;
10772 exp
.X_add_number
= 0;
10773 emit_expr (&exp
, size
);
10777 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10778 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10781 x86_64_section_letter (int letter
, char **ptr_msg
)
10783 if (flag_code
== CODE_64BIT
)
10786 return SHF_X86_64_LARGE
;
10788 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10791 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10796 x86_64_section_word (char *str
, size_t len
)
10798 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10799 return SHF_X86_64_LARGE
;
10805 handle_large_common (int small ATTRIBUTE_UNUSED
)
10807 if (flag_code
!= CODE_64BIT
)
10809 s_comm_internal (0, elf_common_parse
);
10810 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10814 static segT lbss_section
;
10815 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10816 asection
*saved_bss_section
= bss_section
;
10818 if (lbss_section
== NULL
)
10820 flagword applicable
;
10821 segT seg
= now_seg
;
10822 subsegT subseg
= now_subseg
;
10824 /* The .lbss section is for local .largecomm symbols. */
10825 lbss_section
= subseg_new (".lbss", 0);
10826 applicable
= bfd_applicable_section_flags (stdoutput
);
10827 bfd_set_section_flags (stdoutput
, lbss_section
,
10828 applicable
& SEC_ALLOC
);
10829 seg_info (lbss_section
)->bss
= 1;
10831 subseg_set (seg
, subseg
);
10834 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10835 bss_section
= lbss_section
;
10837 s_comm_internal (0, elf_common_parse
);
10839 elf_com_section_ptr
= saved_com_section_ptr
;
10840 bss_section
= saved_bss_section
;
10843 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */