1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used
;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used
;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
200 static const char *default_arch
= DEFAULT_ARCH
;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op
;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry
*mask
;
224 unsigned int zeroing
;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op
;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op
;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes
[4];
253 /* Destination or source register specifier. */
254 const reg_entry
*register_specifier
;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry
*regs
;
269 operand_size_mismatch
,
270 operand_type_mismatch
,
271 register_type_mismatch
,
272 number_of_operands_mismatch
,
273 invalid_instruction_suffix
,
275 unsupported_with_intel_mnemonic
,
278 invalid_vsib_address
,
279 invalid_vector_register_set
,
280 unsupported_vector_index_register
,
281 unsupported_broadcast
,
284 mask_not_on_destination
,
287 rc_sae_operand_not_last_imm
,
288 invalid_register_operand
,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands
;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types
[MAX_OPERANDS
];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op
[MAX_OPERANDS
];
316 /* Flags for operands. */
317 unsigned int flags
[MAX_OPERANDS
];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry
*base_reg
;
327 const reg_entry
*index_reg
;
328 unsigned int log2_scale_factor
;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry
*seg
[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes
;
340 unsigned char prefix
[MAX_PREFIXES
];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx
;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm
;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm
;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm
;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation
*mask
;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation
*rounding
;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation
*broadcast
;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift
;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default
= 0,
383 /* Prefer 8bit or 32bit displacement in encoding. */
386 disp_encoding_default
= 0,
391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding
;
394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize
;
397 /* How to encode vector instructions. */
400 vex_encoding_default
= 0,
407 const char *rep_prefix
;
410 const char *hle_prefix
;
412 /* Have BND prefix. */
413 const char *bnd_prefix
;
415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix
;
419 enum i386_error error
;
422 typedef struct _i386_insn i386_insn
;
424 /* Link RC type with corresponding string, that'll be looked for in
433 static const struct RC_name RC_NamesTable
[] =
435 { rne
, STRING_COMMA_LEN ("rn-sae") },
436 { rd
, STRING_COMMA_LEN ("rd-sae") },
437 { ru
, STRING_COMMA_LEN ("ru-sae") },
438 { rz
, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly
, STRING_COMMA_LEN ("sae") },
442 /* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
444 const char extra_symbol_chars
[] = "*%-([{}"
453 #if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
455 && !defined (TE_GNU) \
456 && !defined (TE_LINUX) \
457 && !defined (TE_NACL) \
458 && !defined (TE_FreeBSD) \
459 && !defined (TE_DragonFly) \
460 && !defined (TE_NetBSD)))
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464 const char *i386_comment_chars
= "#/";
465 #define SVR4_COMMENT_CHARS 1
466 #define PREFIX_SEPARATOR '\\'
469 const char *i386_comment_chars
= "#";
470 #define PREFIX_SEPARATOR '/'
473 /* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
477 first line of the input file. This is because the compiler outputs
478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
480 '/' isn't otherwise defined. */
481 const char line_comment_chars
[] = "#/";
483 const char line_separator_chars
[] = ";";
485 /* Chars that can be used to separate mant from exp in floating point
487 const char EXP_CHARS
[] = "eE";
489 /* Chars that mean this number is a floating point constant
492 const char FLT_CHARS
[] = "fFdDxX";
494 /* Tables for lexical analysis. */
495 static char mnemonic_chars
[256];
496 static char register_chars
[256];
497 static char operand_chars
[256];
498 static char identifier_chars
[256];
499 static char digit_chars
[256];
501 /* Lexical macros. */
502 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503 #define is_operand_char(x) (operand_chars[(unsigned char) x])
504 #define is_register_char(x) (register_chars[(unsigned char) x])
505 #define is_space_char(x) ((x) == ' ')
506 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507 #define is_digit_char(x) (digit_chars[(unsigned char) x])
509 /* All non-digit non-letter characters that may occur in an operand. */
510 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
512 /* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
515 assembler instruction). */
516 static char save_stack
[32];
517 static char *save_stack_p
;
518 #define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520 #define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
523 /* The instruction we're assembling. */
526 /* Possible templates for current insn. */
527 static const templates
*current_templates
;
529 /* Per instruction expressionS buffers: max displacements & immediates. */
530 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
531 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
533 /* Current operand we are working on. */
534 static int this_operand
= -1;
536 /* We support four different modes. FLAG_CODE variable is used to distinguish
544 static enum flag_code flag_code
;
545 static unsigned int object_64bit
;
546 static unsigned int disallow_64bit_reloc
;
547 static int use_rela_relocations
= 0;
549 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
553 /* The ELF ABI to use. */
561 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
564 #if defined (TE_PE) || defined (TE_PEP)
565 /* Use big object file format. */
566 static int use_big_obj
= 0;
569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570 /* 1 if generating code for a shared library. */
571 static int shared
= 0;
574 /* 1 for intel syntax,
576 static int intel_syntax
= 0;
578 /* 1 for Intel64 ISA,
582 /* 1 for intel mnemonic,
583 0 if att mnemonic. */
584 static int intel_mnemonic
= !SYSV386_COMPAT
;
586 /* 1 if pseudo registers are permitted. */
587 static int allow_pseudo_reg
= 0;
589 /* 1 if register prefix % not required. */
590 static int allow_naked_reg
= 0;
592 /* 1 if the assembler should add BND prefix for all control-transferring
593 instructions supporting it, even if this prefix wasn't specified
595 static int add_bnd_prefix
= 0;
597 /* 1 if pseudo index register, eiz/riz, is allowed . */
598 static int allow_index_reg
= 0;
600 /* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602 static int omit_lock_prefix
= 0;
604 /* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606 static int avoid_fence
= 0;
608 /* 1 if the assembler should generate relax relocations. */
610 static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
613 static enum check_kind
619 sse_check
, operand_check
= check_warning
;
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
626 static int optimize
= 0;
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
635 static int optimize_for_space
= 0;
637 /* Register prefix used for error message. */
638 static const char *register_prefix
= "%";
640 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643 static char stackop_size
= '\0';
645 /* Non-zero to optimize code alignment. */
646 int optimize_align_code
= 1;
648 /* Non-zero to quieten some warnings. */
649 static int quiet_warnings
= 0;
652 static const char *cpu_arch_name
= NULL
;
653 static char *cpu_sub_arch_name
= NULL
;
655 /* CPU feature flags. */
656 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
658 /* If we have selected a cpu we are generating instructions for. */
659 static int cpu_arch_tune_set
= 0;
661 /* Cpu we are generating instructions for. */
662 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
664 /* CPU feature flags of cpu we are generating instructions for. */
665 static i386_cpu_flags cpu_arch_tune_flags
;
667 /* CPU instruction set architecture used. */
668 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
670 /* CPU feature flags of instruction set architecture used. */
671 i386_cpu_flags cpu_arch_isa_flags
;
673 /* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675 static unsigned int no_cond_jump_promotion
= 0;
677 /* Encode SSE instructions with VEX prefix. */
678 static unsigned int sse2avx
;
680 /* Encode scalar AVX instructions with specific vector length. */
687 /* Encode scalar EVEX LIG instructions with specific vector length. */
695 /* Encode EVEX WIG instructions with specific evex.w. */
702 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
703 static enum rc_type evexrcig
= rne
;
705 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
706 static symbolS
*GOT_symbol
;
708 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
709 unsigned int x86_dwarf2_return_column
;
711 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
712 int x86_cie_data_alignment
;
714 /* Interface to relax_segment.
715 There are 3 major relax states for 386 jump insns because the
716 different types of jumps add different sizes to frags when we're
717 figuring out what sort of jump to choose to reach a given label. */
720 #define UNCOND_JUMP 0
722 #define COND_JUMP86 2
727 #define SMALL16 (SMALL | CODE16)
729 #define BIG16 (BIG | CODE16)
733 #define INLINE __inline__
739 #define ENCODE_RELAX_STATE(type, size) \
740 ((relax_substateT) (((type) << 2) | (size)))
741 #define TYPE_FROM_RELAX_STATE(s) \
743 #define DISP_SIZE_FROM_RELAX_STATE(s) \
744 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
746 /* This table is used by relax_frag to promote short jumps to long
747 ones where necessary. SMALL (short) jumps may be promoted to BIG
748 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
749 don't allow a short jump in a 32 bit code segment to be promoted to
750 a 16 bit offset jump because it's slower (requires data size
751 prefix), and doesn't work, unless the destination is in the bottom
752 64k of the code segment (The top 16 bits of eip are zeroed). */
754 const relax_typeS md_relax_table
[] =
757 1) most positive reach of this state,
758 2) most negative reach of this state,
759 3) how many bytes this mode will have in the variable part of the frag
760 4) which index into the table to try if we can't fit into this one. */
762 /* UNCOND_JUMP states. */
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
764 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
765 /* dword jmp adds 4 bytes to frag:
766 0 extra opcode bytes, 4 displacement bytes. */
768 /* word jmp adds 2 byte2 to frag:
769 0 extra opcode bytes, 2 displacement bytes. */
772 /* COND_JUMP states. */
773 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
774 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
775 /* dword conditionals adds 5 bytes to frag:
776 1 extra opcode byte, 4 displacement bytes. */
778 /* word conditionals add 3 bytes to frag:
779 1 extra opcode byte, 2 displacement bytes. */
782 /* COND_JUMP86 states. */
783 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
785 /* dword conditionals adds 5 bytes to frag:
786 1 extra opcode byte, 4 displacement bytes. */
788 /* word conditionals add 4 bytes to frag:
789 1 displacement byte and a 3 byte long branch insn. */
793 static const arch_entry cpu_arch
[] =
795 /* Do not replace the first two entries - i386_target_format()
796 relies on them being there in this order. */
797 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
798 CPU_GENERIC32_FLAGS
, 0 },
799 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
800 CPU_GENERIC64_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
803 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
805 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
807 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
809 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
811 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
813 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
815 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
817 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
818 CPU_PENTIUMPRO_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
821 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
823 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
825 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
827 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
828 CPU_NOCONA_FLAGS
, 0 },
829 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
831 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
833 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
834 CPU_CORE2_FLAGS
, 1 },
835 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
836 CPU_CORE2_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
838 CPU_COREI7_FLAGS
, 0 },
839 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
841 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
843 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
844 CPU_IAMCU_FLAGS
, 0 },
845 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
847 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
849 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
850 CPU_ATHLON_FLAGS
, 0 },
851 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
853 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
855 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
857 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
858 CPU_AMDFAM10_FLAGS
, 0 },
859 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
860 CPU_BDVER1_FLAGS
, 0 },
861 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
862 CPU_BDVER2_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
864 CPU_BDVER3_FLAGS
, 0 },
865 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
866 CPU_BDVER4_FLAGS
, 0 },
867 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
868 CPU_ZNVER1_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
870 CPU_ZNVER2_FLAGS
, 0 },
871 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
872 CPU_BTVER1_FLAGS
, 0 },
873 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
874 CPU_BTVER2_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
877 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
879 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
883 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
885 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
887 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
889 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
891 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
896 CPU_SSSE3_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
898 CPU_SSE4_1_FLAGS
, 0 },
899 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
900 CPU_SSE4_2_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
902 CPU_SSE4_2_FLAGS
, 0 },
903 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
908 CPU_AVX512F_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
910 CPU_AVX512CD_FLAGS
, 0 },
911 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
912 CPU_AVX512ER_FLAGS
, 0 },
913 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
914 CPU_AVX512PF_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
916 CPU_AVX512DQ_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
918 CPU_AVX512BW_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
920 CPU_AVX512VL_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
924 CPU_VMFUNC_FLAGS
, 0 },
925 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
928 CPU_XSAVE_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
930 CPU_XSAVEOPT_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
932 CPU_XSAVEC_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
934 CPU_XSAVES_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
938 CPU_PCLMUL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
940 CPU_PCLMUL_FLAGS
, 1 },
941 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
942 CPU_FSGSBASE_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
944 CPU_RDRND_FLAGS
, 0 },
945 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
947 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
949 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
953 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
957 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
958 CPU_MOVBE_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
961 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
964 CPU_LZCNT_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
970 CPU_INVPCID_FLAGS
, 0 },
971 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
972 CPU_CLFLUSH_FLAGS
, 0 },
973 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
976 CPU_SYSCALL_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
978 CPU_RDTSCP_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
980 CPU_3DNOW_FLAGS
, 0 },
981 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
982 CPU_3DNOWA_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
984 CPU_PADLOCK_FLAGS
, 0 },
985 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
989 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
990 CPU_SSE4A_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
999 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1000 CPU_RDSEED_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1002 CPU_PRFCHW_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1004 CPU_SMAP_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1007 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1009 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1010 CPU_CLFLUSHOPT_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1012 CPU_PREFETCHWT1_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1016 CPU_CLWB_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1018 CPU_AVX512IFMA_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1020 CPU_AVX512VBMI_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1022 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1024 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1026 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1028 CPU_AVX512_VBMI2_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1030 CPU_AVX512_VNNI_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1032 CPU_AVX512_BITALG_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1034 CPU_CLZERO_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1036 CPU_MWAITX_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1038 CPU_OSPKE_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1040 CPU_RDPID_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1042 CPU_PTWRITE_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1045 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1046 CPU_SHSTK_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1048 CPU_GFNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1050 CPU_VAES_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1052 CPU_VPCLMULQDQ_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1054 CPU_WBNOINVD_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1056 CPU_PCONFIG_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1058 CPU_WAITPKG_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1060 CPU_CLDEMOTE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1062 CPU_MOVDIRI_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1064 CPU_MOVDIR64B_FLAGS
, 0 },
1067 static const noarch_entry cpu_noarch
[] =
1069 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1070 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1071 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1072 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1073 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1074 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1075 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1076 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1077 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1078 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1079 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1080 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1081 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1082 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1083 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1084 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1085 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1086 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1087 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1088 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1089 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1090 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1091 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1092 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1093 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1094 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1095 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1096 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1097 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1098 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1099 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1100 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1101 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1102 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1103 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1107 /* Like s_lcomm_internal in gas/read.c but the alignment string
1108 is allowed to be optional. */
1111 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1118 && *input_line_pointer
== ',')
1120 align
= parse_align (needs_align
- 1);
1122 if (align
== (addressT
) -1)
1137 bss_alloc (symbolP
, size
, align
);
1142 pe_lcomm (int needs_align
)
1144 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1148 const pseudo_typeS md_pseudo_table
[] =
1150 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1151 {"align", s_align_bytes
, 0},
1153 {"align", s_align_ptwo
, 0},
1155 {"arch", set_cpu_arch
, 0},
1159 {"lcomm", pe_lcomm
, 1},
1161 {"ffloat", float_cons
, 'f'},
1162 {"dfloat", float_cons
, 'd'},
1163 {"tfloat", float_cons
, 'x'},
1165 {"slong", signed_cons
, 4},
1166 {"noopt", s_ignore
, 0},
1167 {"optim", s_ignore
, 0},
1168 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1169 {"code16", set_code_flag
, CODE_16BIT
},
1170 {"code32", set_code_flag
, CODE_32BIT
},
1172 {"code64", set_code_flag
, CODE_64BIT
},
1174 {"intel_syntax", set_intel_syntax
, 1},
1175 {"att_syntax", set_intel_syntax
, 0},
1176 {"intel_mnemonic", set_intel_mnemonic
, 1},
1177 {"att_mnemonic", set_intel_mnemonic
, 0},
1178 {"allow_index_reg", set_allow_index_reg
, 1},
1179 {"disallow_index_reg", set_allow_index_reg
, 0},
1180 {"sse_check", set_check
, 0},
1181 {"operand_check", set_check
, 1},
1182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1183 {"largecomm", handle_large_common
, 0},
1185 {"file", dwarf2_directive_file
, 0},
1186 {"loc", dwarf2_directive_loc
, 0},
1187 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1190 {"secrel32", pe_directive_secrel
, 0},
1195 /* For interface with expression (). */
1196 extern char *input_line_pointer
;
1198 /* Hash table for instruction mnemonic lookup. */
1199 static struct hash_control
*op_hash
;
1201 /* Hash table for register lookup. */
1202 static struct hash_control
*reg_hash
;
1204 /* Various efficient no-op patterns for aligning code labels.
1205 Note: Don't try to assemble the instructions in the comments.
1206 0L and 0w are not legal. */
1207 static const unsigned char f32_1
[] =
1209 static const unsigned char f32_2
[] =
1210 {0x66,0x90}; /* xchg %ax,%ax */
1211 static const unsigned char f32_3
[] =
1212 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1213 static const unsigned char f32_4
[] =
1214 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1215 static const unsigned char f32_6
[] =
1216 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1217 static const unsigned char f32_7
[] =
1218 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1219 static const unsigned char f16_3
[] =
1220 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1221 static const unsigned char f16_4
[] =
1222 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1223 static const unsigned char jump_disp8
[] =
1224 {0xeb}; /* jmp disp8 */
1225 static const unsigned char jump32_disp32
[] =
1226 {0xe9}; /* jmp disp32 */
1227 static const unsigned char jump16_disp32
[] =
1228 {0x66,0xe9}; /* jmp disp32 */
1229 /* 32-bit NOPs patterns. */
1230 static const unsigned char *const f32_patt
[] = {
1231 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1233 /* 16-bit NOPs patterns. */
1234 static const unsigned char *const f16_patt
[] = {
1235 f32_1
, f32_2
, f16_3
, f16_4
1237 /* nopl (%[re]ax) */
1238 static const unsigned char alt_3
[] =
1240 /* nopl 0(%[re]ax) */
1241 static const unsigned char alt_4
[] =
1242 {0x0f,0x1f,0x40,0x00};
1243 /* nopl 0(%[re]ax,%[re]ax,1) */
1244 static const unsigned char alt_5
[] =
1245 {0x0f,0x1f,0x44,0x00,0x00};
1246 /* nopw 0(%[re]ax,%[re]ax,1) */
1247 static const unsigned char alt_6
[] =
1248 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1249 /* nopl 0L(%[re]ax) */
1250 static const unsigned char alt_7
[] =
1251 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1252 /* nopl 0L(%[re]ax,%[re]ax,1) */
1253 static const unsigned char alt_8
[] =
1254 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1255 /* nopw 0L(%[re]ax,%[re]ax,1) */
1256 static const unsigned char alt_9
[] =
1257 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1258 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1259 static const unsigned char alt_10
[] =
1260 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1261 /* data16 nopw %cs:0L(%eax,%eax,1) */
1262 static const unsigned char alt_11
[] =
1263 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1264 /* 32-bit and 64-bit NOPs patterns. */
1265 static const unsigned char *const alt_patt
[] = {
1266 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1267 alt_9
, alt_10
, alt_11
1270 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1271 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1274 i386_output_nops (char *where
, const unsigned char *const *patt
,
1275 int count
, int max_single_nop_size
)
1278 /* Place the longer NOP first. */
1281 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1283 /* Use the smaller one if the requsted one isn't available. */
1286 max_single_nop_size
--;
1287 nops
= patt
[max_single_nop_size
- 1];
1290 last
= count
% max_single_nop_size
;
1293 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1294 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1298 nops
= patt
[last
- 1];
1301 /* Use the smaller one plus one-byte NOP if the needed one
1304 nops
= patt
[last
- 1];
1305 memcpy (where
+ offset
, nops
, last
);
1306 where
[offset
+ last
] = *patt
[0];
1309 memcpy (where
+ offset
, nops
, last
);
1314 fits_in_imm7 (offsetT num
)
1316 return (num
& 0x7f) == num
;
1320 fits_in_imm31 (offsetT num
)
1322 return (num
& 0x7fffffff) == num
;
1325 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1326 single NOP instruction LIMIT. */
1329 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1331 const unsigned char *const *patt
= NULL
;
1332 int max_single_nop_size
;
1333 /* Maximum number of NOPs before switching to jump over NOPs. */
1334 int max_number_of_nops
;
1336 switch (fragP
->fr_type
)
1345 /* We need to decide which NOP sequence to use for 32bit and
1346 64bit. When -mtune= is used:
1348 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1349 PROCESSOR_GENERIC32, f32_patt will be used.
1350 2. For the rest, alt_patt will be used.
1352 When -mtune= isn't used, alt_patt will be used if
1353 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1356 When -march= or .arch is used, we can't use anything beyond
1357 cpu_arch_isa_flags. */
1359 if (flag_code
== CODE_16BIT
)
1362 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1363 /* Limit number of NOPs to 2 in 16-bit mode. */
1364 max_number_of_nops
= 2;
1368 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1370 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1371 switch (cpu_arch_tune
)
1373 case PROCESSOR_UNKNOWN
:
1374 /* We use cpu_arch_isa_flags to check if we SHOULD
1375 optimize with nops. */
1376 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1381 case PROCESSOR_PENTIUM4
:
1382 case PROCESSOR_NOCONA
:
1383 case PROCESSOR_CORE
:
1384 case PROCESSOR_CORE2
:
1385 case PROCESSOR_COREI7
:
1386 case PROCESSOR_L1OM
:
1387 case PROCESSOR_K1OM
:
1388 case PROCESSOR_GENERIC64
:
1390 case PROCESSOR_ATHLON
:
1392 case PROCESSOR_AMDFAM10
:
1394 case PROCESSOR_ZNVER
:
1398 case PROCESSOR_I386
:
1399 case PROCESSOR_I486
:
1400 case PROCESSOR_PENTIUM
:
1401 case PROCESSOR_PENTIUMPRO
:
1402 case PROCESSOR_IAMCU
:
1403 case PROCESSOR_GENERIC32
:
1410 switch (fragP
->tc_frag_data
.tune
)
1412 case PROCESSOR_UNKNOWN
:
1413 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1414 PROCESSOR_UNKNOWN. */
1418 case PROCESSOR_I386
:
1419 case PROCESSOR_I486
:
1420 case PROCESSOR_PENTIUM
:
1421 case PROCESSOR_IAMCU
:
1423 case PROCESSOR_ATHLON
:
1425 case PROCESSOR_AMDFAM10
:
1427 case PROCESSOR_ZNVER
:
1429 case PROCESSOR_GENERIC32
:
1430 /* We use cpu_arch_isa_flags to check if we CAN optimize
1432 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1437 case PROCESSOR_PENTIUMPRO
:
1438 case PROCESSOR_PENTIUM4
:
1439 case PROCESSOR_NOCONA
:
1440 case PROCESSOR_CORE
:
1441 case PROCESSOR_CORE2
:
1442 case PROCESSOR_COREI7
:
1443 case PROCESSOR_L1OM
:
1444 case PROCESSOR_K1OM
:
1445 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1450 case PROCESSOR_GENERIC64
:
1456 if (patt
== f32_patt
)
1458 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1459 /* Limit number of NOPs to 2 for older processors. */
1460 max_number_of_nops
= 2;
1464 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1465 /* Limit number of NOPs to 7 for newer processors. */
1466 max_number_of_nops
= 7;
1471 limit
= max_single_nop_size
;
1473 if (fragP
->fr_type
== rs_fill_nop
)
1475 /* Output NOPs for .nop directive. */
1476 if (limit
> max_single_nop_size
)
1478 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1479 _("invalid single nop size: %d "
1480 "(expect within [0, %d])"),
1481 limit
, max_single_nop_size
);
1486 fragP
->fr_var
= count
;
1488 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1490 /* Generate jump over NOPs. */
1491 offsetT disp
= count
- 2;
1492 if (fits_in_imm7 (disp
))
1494 /* Use "jmp disp8" if possible. */
1496 where
[0] = jump_disp8
[0];
1502 unsigned int size_of_jump
;
1504 if (flag_code
== CODE_16BIT
)
1506 where
[0] = jump16_disp32
[0];
1507 where
[1] = jump16_disp32
[1];
1512 where
[0] = jump32_disp32
[0];
1516 count
-= size_of_jump
+ 4;
1517 if (!fits_in_imm31 (count
))
1519 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1520 _("jump over nop padding out of range"));
1524 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1525 where
+= size_of_jump
+ 4;
1529 /* Generate multiple NOPs. */
1530 i386_output_nops (where
, patt
, count
, limit
);
1534 operand_type_all_zero (const union i386_operand_type
*x
)
1536 switch (ARRAY_SIZE(x
->array
))
1547 return !x
->array
[0];
1554 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1556 switch (ARRAY_SIZE(x
->array
))
1574 operand_type_equal (const union i386_operand_type
*x
,
1575 const union i386_operand_type
*y
)
1577 switch (ARRAY_SIZE(x
->array
))
1580 if (x
->array
[2] != y
->array
[2])
1584 if (x
->array
[1] != y
->array
[1])
1588 return x
->array
[0] == y
->array
[0];
1596 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1598 switch (ARRAY_SIZE(x
->array
))
1613 return !x
->array
[0];
1620 cpu_flags_equal (const union i386_cpu_flags
*x
,
1621 const union i386_cpu_flags
*y
)
1623 switch (ARRAY_SIZE(x
->array
))
1626 if (x
->array
[3] != y
->array
[3])
1630 if (x
->array
[2] != y
->array
[2])
1634 if (x
->array
[1] != y
->array
[1])
1638 return x
->array
[0] == y
->array
[0];
1646 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1648 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1649 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1652 static INLINE i386_cpu_flags
1653 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1655 switch (ARRAY_SIZE (x
.array
))
1658 x
.array
[3] &= y
.array
[3];
1661 x
.array
[2] &= y
.array
[2];
1664 x
.array
[1] &= y
.array
[1];
1667 x
.array
[0] &= y
.array
[0];
1675 static INLINE i386_cpu_flags
1676 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1678 switch (ARRAY_SIZE (x
.array
))
1681 x
.array
[3] |= y
.array
[3];
1684 x
.array
[2] |= y
.array
[2];
1687 x
.array
[1] |= y
.array
[1];
1690 x
.array
[0] |= y
.array
[0];
1698 static INLINE i386_cpu_flags
1699 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1701 switch (ARRAY_SIZE (x
.array
))
1704 x
.array
[3] &= ~y
.array
[3];
1707 x
.array
[2] &= ~y
.array
[2];
1710 x
.array
[1] &= ~y
.array
[1];
1713 x
.array
[0] &= ~y
.array
[0];
1721 #define CPU_FLAGS_ARCH_MATCH 0x1
1722 #define CPU_FLAGS_64BIT_MATCH 0x2
1724 #define CPU_FLAGS_PERFECT_MATCH \
1725 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1727 /* Return CPU flags match bits. */
1730 cpu_flags_match (const insn_template
*t
)
1732 i386_cpu_flags x
= t
->cpu_flags
;
1733 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1735 x
.bitfield
.cpu64
= 0;
1736 x
.bitfield
.cpuno64
= 0;
1738 if (cpu_flags_all_zero (&x
))
1740 /* This instruction is available on all archs. */
1741 match
|= CPU_FLAGS_ARCH_MATCH
;
1745 /* This instruction is available only on some archs. */
1746 i386_cpu_flags cpu
= cpu_arch_flags
;
1748 /* AVX512VL is no standalone feature - match it and then strip it. */
1749 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1751 x
.bitfield
.cpuavx512vl
= 0;
1753 cpu
= cpu_flags_and (x
, cpu
);
1754 if (!cpu_flags_all_zero (&cpu
))
1756 if (x
.bitfield
.cpuavx
)
1758 /* We need to check a few extra flags with AVX. */
1759 if (cpu
.bitfield
.cpuavx
1760 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1761 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1762 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1763 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1764 match
|= CPU_FLAGS_ARCH_MATCH
;
1766 else if (x
.bitfield
.cpuavx512f
)
1768 /* We need to check a few extra flags with AVX512F. */
1769 if (cpu
.bitfield
.cpuavx512f
1770 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1771 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1772 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1773 match
|= CPU_FLAGS_ARCH_MATCH
;
1776 match
|= CPU_FLAGS_ARCH_MATCH
;
1782 static INLINE i386_operand_type
1783 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1785 switch (ARRAY_SIZE (x
.array
))
1788 x
.array
[2] &= y
.array
[2];
1791 x
.array
[1] &= y
.array
[1];
1794 x
.array
[0] &= y
.array
[0];
1802 static INLINE i386_operand_type
1803 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1805 switch (ARRAY_SIZE (x
.array
))
1808 x
.array
[2] &= ~y
.array
[2];
1811 x
.array
[1] &= ~y
.array
[1];
1814 x
.array
[0] &= ~y
.array
[0];
1822 static INLINE i386_operand_type
1823 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1825 switch (ARRAY_SIZE (x
.array
))
1828 x
.array
[2] |= y
.array
[2];
1831 x
.array
[1] |= y
.array
[1];
1834 x
.array
[0] |= y
.array
[0];
1842 static INLINE i386_operand_type
1843 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1845 switch (ARRAY_SIZE (x
.array
))
1848 x
.array
[2] ^= y
.array
[2];
1851 x
.array
[1] ^= y
.array
[1];
1854 x
.array
[0] ^= y
.array
[0];
1862 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1863 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1864 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1865 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1866 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1867 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1868 static const i386_operand_type anydisp
1869 = OPERAND_TYPE_ANYDISP
;
1870 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1871 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1872 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1873 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1874 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1875 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1876 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1877 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1878 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1879 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1880 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1881 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1892 operand_type_check (i386_operand_type t
, enum operand_type c
)
1897 return t
.bitfield
.reg
;
1900 return (t
.bitfield
.imm8
1904 || t
.bitfield
.imm32s
1905 || t
.bitfield
.imm64
);
1908 return (t
.bitfield
.disp8
1909 || t
.bitfield
.disp16
1910 || t
.bitfield
.disp32
1911 || t
.bitfield
.disp32s
1912 || t
.bitfield
.disp64
);
1915 return (t
.bitfield
.disp8
1916 || t
.bitfield
.disp16
1917 || t
.bitfield
.disp32
1918 || t
.bitfield
.disp32s
1919 || t
.bitfield
.disp64
1920 || t
.bitfield
.baseindex
);
1929 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1930 between operand GIVEN and opeand WANTED for instruction template T. */
1933 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1936 return !((i
.types
[given
].bitfield
.byte
1937 && !t
->operand_types
[wanted
].bitfield
.byte
)
1938 || (i
.types
[given
].bitfield
.word
1939 && !t
->operand_types
[wanted
].bitfield
.word
)
1940 || (i
.types
[given
].bitfield
.dword
1941 && !t
->operand_types
[wanted
].bitfield
.dword
)
1942 || (i
.types
[given
].bitfield
.qword
1943 && !t
->operand_types
[wanted
].bitfield
.qword
)
1944 || (i
.types
[given
].bitfield
.tbyte
1945 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1948 /* Return 1 if there is no conflict in SIMD register between operand
1949 GIVEN and opeand WANTED for instruction template T. */
1952 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1955 return !((i
.types
[given
].bitfield
.xmmword
1956 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1957 || (i
.types
[given
].bitfield
.ymmword
1958 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1959 || (i
.types
[given
].bitfield
.zmmword
1960 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1963 /* Return 1 if there is no conflict in any size between operand GIVEN
1964 and opeand WANTED for instruction template T. */
1967 match_mem_size (const insn_template
*t
, unsigned int wanted
,
1970 return (match_operand_size (t
, wanted
, given
)
1971 && !((i
.types
[given
].bitfield
.unspecified
1973 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
1974 || (i
.types
[given
].bitfield
.fword
1975 && !t
->operand_types
[wanted
].bitfield
.fword
)
1976 /* For scalar opcode templates to allow register and memory
1977 operands at the same time, some special casing is needed
1978 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1979 down-conversion vpmov*. */
1980 || ((t
->operand_types
[wanted
].bitfield
.regsimd
1981 && !t
->opcode_modifier
.broadcast
1982 && (t
->operand_types
[wanted
].bitfield
.byte
1983 || t
->operand_types
[wanted
].bitfield
.word
1984 || t
->operand_types
[wanted
].bitfield
.dword
1985 || t
->operand_types
[wanted
].bitfield
.qword
))
1986 ? (i
.types
[given
].bitfield
.xmmword
1987 || i
.types
[given
].bitfield
.ymmword
1988 || i
.types
[given
].bitfield
.zmmword
)
1989 : !match_simd_size(t
, wanted
, given
))));
1992 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1993 operands for instruction template T, and it has MATCH_REVERSE set if there
1994 is no size conflict on any operands for the template with operands reversed
1995 (and the template allows for reversing in the first place). */
1997 #define MATCH_STRAIGHT 1
1998 #define MATCH_REVERSE 2
2000 static INLINE
unsigned int
2001 operand_size_match (const insn_template
*t
)
2003 unsigned int j
, match
= MATCH_STRAIGHT
;
2005 /* Don't check jump instructions. */
2006 if (t
->opcode_modifier
.jump
2007 || t
->opcode_modifier
.jumpbyte
2008 || t
->opcode_modifier
.jumpdword
2009 || t
->opcode_modifier
.jumpintersegment
)
2012 /* Check memory and accumulator operand size. */
2013 for (j
= 0; j
< i
.operands
; j
++)
2015 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2016 && t
->operand_types
[j
].bitfield
.anysize
)
2019 if (t
->operand_types
[j
].bitfield
.reg
2020 && !match_operand_size (t
, j
, j
))
2026 if (t
->operand_types
[j
].bitfield
.regsimd
2027 && !match_simd_size (t
, j
, j
))
2033 if (t
->operand_types
[j
].bitfield
.acc
2034 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2040 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2047 if (!t
->opcode_modifier
.d
)
2051 i
.error
= operand_size_mismatch
;
2055 /* Check reverse. */
2056 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2058 for (j
= 0; j
< i
.operands
; j
++)
2060 unsigned int given
= i
.operands
- j
- 1;
2062 if (t
->operand_types
[j
].bitfield
.reg
2063 && !match_operand_size (t
, j
, given
))
2066 if (t
->operand_types
[j
].bitfield
.regsimd
2067 && !match_simd_size (t
, j
, given
))
2070 if (t
->operand_types
[j
].bitfield
.acc
2071 && (!match_operand_size (t
, j
, given
)
2072 || !match_simd_size (t
, j
, given
)))
2075 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2079 return match
| MATCH_REVERSE
;
2083 operand_type_match (i386_operand_type overlap
,
2084 i386_operand_type given
)
2086 i386_operand_type temp
= overlap
;
2088 temp
.bitfield
.jumpabsolute
= 0;
2089 temp
.bitfield
.unspecified
= 0;
2090 temp
.bitfield
.byte
= 0;
2091 temp
.bitfield
.word
= 0;
2092 temp
.bitfield
.dword
= 0;
2093 temp
.bitfield
.fword
= 0;
2094 temp
.bitfield
.qword
= 0;
2095 temp
.bitfield
.tbyte
= 0;
2096 temp
.bitfield
.xmmword
= 0;
2097 temp
.bitfield
.ymmword
= 0;
2098 temp
.bitfield
.zmmword
= 0;
2099 if (operand_type_all_zero (&temp
))
2102 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2103 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2107 i
.error
= operand_type_mismatch
;
2111 /* If given types g0 and g1 are registers they must be of the same type
2112 unless the expected operand type register overlap is null.
2113 Memory operand size of certain SIMD instructions is also being checked
2117 operand_type_register_match (i386_operand_type g0
,
2118 i386_operand_type t0
,
2119 i386_operand_type g1
,
2120 i386_operand_type t1
)
2122 if (!g0
.bitfield
.reg
2123 && !g0
.bitfield
.regsimd
2124 && (!operand_type_check (g0
, anymem
)
2125 || g0
.bitfield
.unspecified
2126 || !t0
.bitfield
.regsimd
))
2129 if (!g1
.bitfield
.reg
2130 && !g1
.bitfield
.regsimd
2131 && (!operand_type_check (g1
, anymem
)
2132 || g1
.bitfield
.unspecified
2133 || !t1
.bitfield
.regsimd
))
2136 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2137 && g0
.bitfield
.word
== g1
.bitfield
.word
2138 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2139 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2140 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2141 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2142 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2145 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2146 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2147 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2148 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2149 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2150 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2151 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2154 i
.error
= register_type_mismatch
;
2159 static INLINE
unsigned int
2160 register_number (const reg_entry
*r
)
2162 unsigned int nr
= r
->reg_num
;
2164 if (r
->reg_flags
& RegRex
)
2167 if (r
->reg_flags
& RegVRex
)
2173 static INLINE
unsigned int
2174 mode_from_disp_size (i386_operand_type t
)
2176 if (t
.bitfield
.disp8
)
2178 else if (t
.bitfield
.disp16
2179 || t
.bitfield
.disp32
2180 || t
.bitfield
.disp32s
)
2187 fits_in_signed_byte (addressT num
)
2189 return num
+ 0x80 <= 0xff;
2193 fits_in_unsigned_byte (addressT num
)
2199 fits_in_unsigned_word (addressT num
)
2201 return num
<= 0xffff;
2205 fits_in_signed_word (addressT num
)
2207 return num
+ 0x8000 <= 0xffff;
2211 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2216 return num
+ 0x80000000 <= 0xffffffff;
2218 } /* fits_in_signed_long() */
2221 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2226 return num
<= 0xffffffff;
2228 } /* fits_in_unsigned_long() */
2231 fits_in_disp8 (offsetT num
)
2233 int shift
= i
.memshift
;
2239 mask
= (1 << shift
) - 1;
2241 /* Return 0 if NUM isn't properly aligned. */
2245 /* Check if NUM will fit in 8bit after shift. */
2246 return fits_in_signed_byte (num
>> shift
);
2250 fits_in_imm4 (offsetT num
)
2252 return (num
& 0xf) == num
;
2255 static i386_operand_type
2256 smallest_imm_type (offsetT num
)
2258 i386_operand_type t
;
2260 operand_type_set (&t
, 0);
2261 t
.bitfield
.imm64
= 1;
2263 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2265 /* This code is disabled on the 486 because all the Imm1 forms
2266 in the opcode table are slower on the i486. They're the
2267 versions with the implicitly specified single-position
2268 displacement, which has another syntax if you really want to
2270 t
.bitfield
.imm1
= 1;
2271 t
.bitfield
.imm8
= 1;
2272 t
.bitfield
.imm8s
= 1;
2273 t
.bitfield
.imm16
= 1;
2274 t
.bitfield
.imm32
= 1;
2275 t
.bitfield
.imm32s
= 1;
2277 else if (fits_in_signed_byte (num
))
2279 t
.bitfield
.imm8
= 1;
2280 t
.bitfield
.imm8s
= 1;
2281 t
.bitfield
.imm16
= 1;
2282 t
.bitfield
.imm32
= 1;
2283 t
.bitfield
.imm32s
= 1;
2285 else if (fits_in_unsigned_byte (num
))
2287 t
.bitfield
.imm8
= 1;
2288 t
.bitfield
.imm16
= 1;
2289 t
.bitfield
.imm32
= 1;
2290 t
.bitfield
.imm32s
= 1;
2292 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2294 t
.bitfield
.imm16
= 1;
2295 t
.bitfield
.imm32
= 1;
2296 t
.bitfield
.imm32s
= 1;
2298 else if (fits_in_signed_long (num
))
2300 t
.bitfield
.imm32
= 1;
2301 t
.bitfield
.imm32s
= 1;
2303 else if (fits_in_unsigned_long (num
))
2304 t
.bitfield
.imm32
= 1;
2310 offset_in_range (offsetT val
, int size
)
2316 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2317 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2318 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2320 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2326 /* If BFD64, sign extend val for 32bit address mode. */
2327 if (flag_code
!= CODE_64BIT
2328 || i
.prefix
[ADDR_PREFIX
])
2329 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2330 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2333 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2335 char buf1
[40], buf2
[40];
2337 sprint_value (buf1
, val
);
2338 sprint_value (buf2
, val
& mask
);
2339 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2354 a. PREFIX_EXIST if attempting to add a prefix where one from the
2355 same class already exists.
2356 b. PREFIX_LOCK if lock prefix is added.
2357 c. PREFIX_REP if rep/repne prefix is added.
2358 d. PREFIX_DS if ds prefix is added.
2359 e. PREFIX_OTHER if other prefix is added.
2362 static enum PREFIX_GROUP
2363 add_prefix (unsigned int prefix
)
2365 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2368 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2369 && flag_code
== CODE_64BIT
)
2371 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2372 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2373 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2374 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2385 case DS_PREFIX_OPCODE
:
2388 case CS_PREFIX_OPCODE
:
2389 case ES_PREFIX_OPCODE
:
2390 case FS_PREFIX_OPCODE
:
2391 case GS_PREFIX_OPCODE
:
2392 case SS_PREFIX_OPCODE
:
2396 case REPNE_PREFIX_OPCODE
:
2397 case REPE_PREFIX_OPCODE
:
2402 case LOCK_PREFIX_OPCODE
:
2411 case ADDR_PREFIX_OPCODE
:
2415 case DATA_PREFIX_OPCODE
:
2419 if (i
.prefix
[q
] != 0)
2427 i
.prefix
[q
] |= prefix
;
2430 as_bad (_("same type of prefix used twice"));
2436 update_code_flag (int value
, int check
)
2438 PRINTF_LIKE ((*as_error
));
2440 flag_code
= (enum flag_code
) value
;
2441 if (flag_code
== CODE_64BIT
)
2443 cpu_arch_flags
.bitfield
.cpu64
= 1;
2444 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2448 cpu_arch_flags
.bitfield
.cpu64
= 0;
2449 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2451 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2454 as_error
= as_fatal
;
2457 (*as_error
) (_("64bit mode not supported on `%s'."),
2458 cpu_arch_name
? cpu_arch_name
: default_arch
);
2460 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2463 as_error
= as_fatal
;
2466 (*as_error
) (_("32bit mode not supported on `%s'."),
2467 cpu_arch_name
? cpu_arch_name
: default_arch
);
2469 stackop_size
= '\0';
2473 set_code_flag (int value
)
2475 update_code_flag (value
, 0);
2479 set_16bit_gcc_code_flag (int new_code_flag
)
2481 flag_code
= (enum flag_code
) new_code_flag
;
2482 if (flag_code
!= CODE_16BIT
)
2484 cpu_arch_flags
.bitfield
.cpu64
= 0;
2485 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2486 stackop_size
= LONG_MNEM_SUFFIX
;
2490 set_intel_syntax (int syntax_flag
)
2492 /* Find out if register prefixing is specified. */
2493 int ask_naked_reg
= 0;
2496 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2499 int e
= get_symbol_name (&string
);
2501 if (strcmp (string
, "prefix") == 0)
2503 else if (strcmp (string
, "noprefix") == 0)
2506 as_bad (_("bad argument to syntax directive."));
2507 (void) restore_line_pointer (e
);
2509 demand_empty_rest_of_line ();
2511 intel_syntax
= syntax_flag
;
2513 if (ask_naked_reg
== 0)
2514 allow_naked_reg
= (intel_syntax
2515 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2517 allow_naked_reg
= (ask_naked_reg
< 0);
2519 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2521 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2522 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2523 register_prefix
= allow_naked_reg
? "" : "%";
2527 set_intel_mnemonic (int mnemonic_flag
)
2529 intel_mnemonic
= mnemonic_flag
;
2533 set_allow_index_reg (int flag
)
2535 allow_index_reg
= flag
;
2539 set_check (int what
)
2541 enum check_kind
*kind
;
2546 kind
= &operand_check
;
2557 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2560 int e
= get_symbol_name (&string
);
2562 if (strcmp (string
, "none") == 0)
2564 else if (strcmp (string
, "warning") == 0)
2565 *kind
= check_warning
;
2566 else if (strcmp (string
, "error") == 0)
2567 *kind
= check_error
;
2569 as_bad (_("bad argument to %s_check directive."), str
);
2570 (void) restore_line_pointer (e
);
2573 as_bad (_("missing argument for %s_check directive"), str
);
2575 demand_empty_rest_of_line ();
2579 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2580 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2583 static const char *arch
;
2585 /* Intel LIOM is only supported on ELF. */
2591 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2592 use default_arch. */
2593 arch
= cpu_arch_name
;
2595 arch
= default_arch
;
2598 /* If we are targeting Intel MCU, we must enable it. */
2599 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2600 || new_flag
.bitfield
.cpuiamcu
)
2603 /* If we are targeting Intel L1OM, we must enable it. */
2604 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2605 || new_flag
.bitfield
.cpul1om
)
2608 /* If we are targeting Intel K1OM, we must enable it. */
2609 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2610 || new_flag
.bitfield
.cpuk1om
)
2613 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2618 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2622 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2625 int e
= get_symbol_name (&string
);
2627 i386_cpu_flags flags
;
2629 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2631 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2633 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2637 cpu_arch_name
= cpu_arch
[j
].name
;
2638 cpu_sub_arch_name
= NULL
;
2639 cpu_arch_flags
= cpu_arch
[j
].flags
;
2640 if (flag_code
== CODE_64BIT
)
2642 cpu_arch_flags
.bitfield
.cpu64
= 1;
2643 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2647 cpu_arch_flags
.bitfield
.cpu64
= 0;
2648 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2650 cpu_arch_isa
= cpu_arch
[j
].type
;
2651 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2652 if (!cpu_arch_tune_set
)
2654 cpu_arch_tune
= cpu_arch_isa
;
2655 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2660 flags
= cpu_flags_or (cpu_arch_flags
,
2663 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2665 if (cpu_sub_arch_name
)
2667 char *name
= cpu_sub_arch_name
;
2668 cpu_sub_arch_name
= concat (name
,
2670 (const char *) NULL
);
2674 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2675 cpu_arch_flags
= flags
;
2676 cpu_arch_isa_flags
= flags
;
2680 = cpu_flags_or (cpu_arch_isa_flags
,
2682 (void) restore_line_pointer (e
);
2683 demand_empty_rest_of_line ();
2688 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2690 /* Disable an ISA extension. */
2691 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2692 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2694 flags
= cpu_flags_and_not (cpu_arch_flags
,
2695 cpu_noarch
[j
].flags
);
2696 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2698 if (cpu_sub_arch_name
)
2700 char *name
= cpu_sub_arch_name
;
2701 cpu_sub_arch_name
= concat (name
, string
,
2702 (const char *) NULL
);
2706 cpu_sub_arch_name
= xstrdup (string
);
2707 cpu_arch_flags
= flags
;
2708 cpu_arch_isa_flags
= flags
;
2710 (void) restore_line_pointer (e
);
2711 demand_empty_rest_of_line ();
2715 j
= ARRAY_SIZE (cpu_arch
);
2718 if (j
>= ARRAY_SIZE (cpu_arch
))
2719 as_bad (_("no such architecture: `%s'"), string
);
2721 *input_line_pointer
= e
;
2724 as_bad (_("missing cpu architecture"));
2726 no_cond_jump_promotion
= 0;
2727 if (*input_line_pointer
== ','
2728 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2733 ++input_line_pointer
;
2734 e
= get_symbol_name (&string
);
2736 if (strcmp (string
, "nojumps") == 0)
2737 no_cond_jump_promotion
= 1;
2738 else if (strcmp (string
, "jumps") == 0)
2741 as_bad (_("no such architecture modifier: `%s'"), string
);
2743 (void) restore_line_pointer (e
);
2746 demand_empty_rest_of_line ();
2749 enum bfd_architecture
2752 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2754 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2755 || flag_code
!= CODE_64BIT
)
2756 as_fatal (_("Intel L1OM is 64bit ELF only"));
2757 return bfd_arch_l1om
;
2759 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2761 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2762 || flag_code
!= CODE_64BIT
)
2763 as_fatal (_("Intel K1OM is 64bit ELF only"));
2764 return bfd_arch_k1om
;
2766 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2768 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2769 || flag_code
== CODE_64BIT
)
2770 as_fatal (_("Intel MCU is 32bit ELF only"));
2771 return bfd_arch_iamcu
;
2774 return bfd_arch_i386
;
2780 if (!strncmp (default_arch
, "x86_64", 6))
2782 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2784 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2785 || default_arch
[6] != '\0')
2786 as_fatal (_("Intel L1OM is 64bit ELF only"));
2787 return bfd_mach_l1om
;
2789 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2791 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2792 || default_arch
[6] != '\0')
2793 as_fatal (_("Intel K1OM is 64bit ELF only"));
2794 return bfd_mach_k1om
;
2796 else if (default_arch
[6] == '\0')
2797 return bfd_mach_x86_64
;
2799 return bfd_mach_x64_32
;
2801 else if (!strcmp (default_arch
, "i386")
2802 || !strcmp (default_arch
, "iamcu"))
2804 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2806 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2807 as_fatal (_("Intel MCU is 32bit ELF only"));
2808 return bfd_mach_i386_iamcu
;
2811 return bfd_mach_i386_i386
;
2814 as_fatal (_("unknown architecture"));
2820 const char *hash_err
;
2822 /* Support pseudo prefixes like {disp32}. */
2823 lex_type
['{'] = LEX_BEGIN_NAME
;
2825 /* Initialize op_hash hash table. */
2826 op_hash
= hash_new ();
2829 const insn_template
*optab
;
2830 templates
*core_optab
;
2832 /* Setup for loop. */
2834 core_optab
= XNEW (templates
);
2835 core_optab
->start
= optab
;
2840 if (optab
->name
== NULL
2841 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2843 /* different name --> ship out current template list;
2844 add to hash table; & begin anew. */
2845 core_optab
->end
= optab
;
2846 hash_err
= hash_insert (op_hash
,
2848 (void *) core_optab
);
2851 as_fatal (_("can't hash %s: %s"),
2855 if (optab
->name
== NULL
)
2857 core_optab
= XNEW (templates
);
2858 core_optab
->start
= optab
;
2863 /* Initialize reg_hash hash table. */
2864 reg_hash
= hash_new ();
2866 const reg_entry
*regtab
;
2867 unsigned int regtab_size
= i386_regtab_size
;
2869 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2871 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2873 as_fatal (_("can't hash %s: %s"),
2879 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2884 for (c
= 0; c
< 256; c
++)
2889 mnemonic_chars
[c
] = c
;
2890 register_chars
[c
] = c
;
2891 operand_chars
[c
] = c
;
2893 else if (ISLOWER (c
))
2895 mnemonic_chars
[c
] = c
;
2896 register_chars
[c
] = c
;
2897 operand_chars
[c
] = c
;
2899 else if (ISUPPER (c
))
2901 mnemonic_chars
[c
] = TOLOWER (c
);
2902 register_chars
[c
] = mnemonic_chars
[c
];
2903 operand_chars
[c
] = c
;
2905 else if (c
== '{' || c
== '}')
2907 mnemonic_chars
[c
] = c
;
2908 operand_chars
[c
] = c
;
2911 if (ISALPHA (c
) || ISDIGIT (c
))
2912 identifier_chars
[c
] = c
;
2915 identifier_chars
[c
] = c
;
2916 operand_chars
[c
] = c
;
2921 identifier_chars
['@'] = '@';
2924 identifier_chars
['?'] = '?';
2925 operand_chars
['?'] = '?';
2927 digit_chars
['-'] = '-';
2928 mnemonic_chars
['_'] = '_';
2929 mnemonic_chars
['-'] = '-';
2930 mnemonic_chars
['.'] = '.';
2931 identifier_chars
['_'] = '_';
2932 identifier_chars
['.'] = '.';
2934 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2935 operand_chars
[(unsigned char) *p
] = *p
;
2938 if (flag_code
== CODE_64BIT
)
2940 #if defined (OBJ_COFF) && defined (TE_PE)
2941 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2944 x86_dwarf2_return_column
= 16;
2946 x86_cie_data_alignment
= -8;
2950 x86_dwarf2_return_column
= 8;
2951 x86_cie_data_alignment
= -4;
2956 i386_print_statistics (FILE *file
)
2958 hash_print_statistics (file
, "i386 opcode", op_hash
);
2959 hash_print_statistics (file
, "i386 register", reg_hash
);
2964 /* Debugging routines for md_assemble. */
2965 static void pte (insn_template
*);
2966 static void pt (i386_operand_type
);
2967 static void pe (expressionS
*);
2968 static void ps (symbolS
*);
2971 pi (char *line
, i386_insn
*x
)
2975 fprintf (stdout
, "%s: template ", line
);
2977 fprintf (stdout
, " address: base %s index %s scale %x\n",
2978 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2979 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2980 x
->log2_scale_factor
);
2981 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2982 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2983 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2984 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2985 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2986 (x
->rex
& REX_W
) != 0,
2987 (x
->rex
& REX_R
) != 0,
2988 (x
->rex
& REX_X
) != 0,
2989 (x
->rex
& REX_B
) != 0);
2990 for (j
= 0; j
< x
->operands
; j
++)
2992 fprintf (stdout
, " #%d: ", j
+ 1);
2994 fprintf (stdout
, "\n");
2995 if (x
->types
[j
].bitfield
.reg
2996 || x
->types
[j
].bitfield
.regmmx
2997 || x
->types
[j
].bitfield
.regsimd
2998 || x
->types
[j
].bitfield
.sreg2
2999 || x
->types
[j
].bitfield
.sreg3
3000 || x
->types
[j
].bitfield
.control
3001 || x
->types
[j
].bitfield
.debug
3002 || x
->types
[j
].bitfield
.test
)
3003 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3004 if (operand_type_check (x
->types
[j
], imm
))
3006 if (operand_type_check (x
->types
[j
], disp
))
3007 pe (x
->op
[j
].disps
);
3012 pte (insn_template
*t
)
3015 fprintf (stdout
, " %d operands ", t
->operands
);
3016 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3017 if (t
->extension_opcode
!= None
)
3018 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3019 if (t
->opcode_modifier
.d
)
3020 fprintf (stdout
, "D");
3021 if (t
->opcode_modifier
.w
)
3022 fprintf (stdout
, "W");
3023 fprintf (stdout
, "\n");
3024 for (j
= 0; j
< t
->operands
; j
++)
3026 fprintf (stdout
, " #%d type ", j
+ 1);
3027 pt (t
->operand_types
[j
]);
3028 fprintf (stdout
, "\n");
3035 fprintf (stdout
, " operation %d\n", e
->X_op
);
3036 fprintf (stdout
, " add_number %ld (%lx)\n",
3037 (long) e
->X_add_number
, (long) e
->X_add_number
);
3038 if (e
->X_add_symbol
)
3040 fprintf (stdout
, " add_symbol ");
3041 ps (e
->X_add_symbol
);
3042 fprintf (stdout
, "\n");
3046 fprintf (stdout
, " op_symbol ");
3047 ps (e
->X_op_symbol
);
3048 fprintf (stdout
, "\n");
3055 fprintf (stdout
, "%s type %s%s",
3057 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3058 segment_name (S_GET_SEGMENT (s
)));
3061 static struct type_name
3063 i386_operand_type mask
;
3066 const type_names
[] =
3068 { OPERAND_TYPE_REG8
, "r8" },
3069 { OPERAND_TYPE_REG16
, "r16" },
3070 { OPERAND_TYPE_REG32
, "r32" },
3071 { OPERAND_TYPE_REG64
, "r64" },
3072 { OPERAND_TYPE_IMM8
, "i8" },
3073 { OPERAND_TYPE_IMM8
, "i8s" },
3074 { OPERAND_TYPE_IMM16
, "i16" },
3075 { OPERAND_TYPE_IMM32
, "i32" },
3076 { OPERAND_TYPE_IMM32S
, "i32s" },
3077 { OPERAND_TYPE_IMM64
, "i64" },
3078 { OPERAND_TYPE_IMM1
, "i1" },
3079 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3080 { OPERAND_TYPE_DISP8
, "d8" },
3081 { OPERAND_TYPE_DISP16
, "d16" },
3082 { OPERAND_TYPE_DISP32
, "d32" },
3083 { OPERAND_TYPE_DISP32S
, "d32s" },
3084 { OPERAND_TYPE_DISP64
, "d64" },
3085 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3086 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3087 { OPERAND_TYPE_CONTROL
, "control reg" },
3088 { OPERAND_TYPE_TEST
, "test reg" },
3089 { OPERAND_TYPE_DEBUG
, "debug reg" },
3090 { OPERAND_TYPE_FLOATREG
, "FReg" },
3091 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3092 { OPERAND_TYPE_SREG2
, "SReg2" },
3093 { OPERAND_TYPE_SREG3
, "SReg3" },
3094 { OPERAND_TYPE_ACC
, "Acc" },
3095 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3096 { OPERAND_TYPE_REGMMX
, "rMMX" },
3097 { OPERAND_TYPE_REGXMM
, "rXMM" },
3098 { OPERAND_TYPE_REGYMM
, "rYMM" },
3099 { OPERAND_TYPE_REGZMM
, "rZMM" },
3100 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3101 { OPERAND_TYPE_ESSEG
, "es" },
3105 pt (i386_operand_type t
)
3108 i386_operand_type a
;
3110 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3112 a
= operand_type_and (t
, type_names
[j
].mask
);
3113 if (!operand_type_all_zero (&a
))
3114 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3119 #endif /* DEBUG386 */
3121 static bfd_reloc_code_real_type
3122 reloc (unsigned int size
,
3125 bfd_reloc_code_real_type other
)
3127 if (other
!= NO_RELOC
)
3129 reloc_howto_type
*rel
;
3134 case BFD_RELOC_X86_64_GOT32
:
3135 return BFD_RELOC_X86_64_GOT64
;
3137 case BFD_RELOC_X86_64_GOTPLT64
:
3138 return BFD_RELOC_X86_64_GOTPLT64
;
3140 case BFD_RELOC_X86_64_PLTOFF64
:
3141 return BFD_RELOC_X86_64_PLTOFF64
;
3143 case BFD_RELOC_X86_64_GOTPC32
:
3144 other
= BFD_RELOC_X86_64_GOTPC64
;
3146 case BFD_RELOC_X86_64_GOTPCREL
:
3147 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3149 case BFD_RELOC_X86_64_TPOFF32
:
3150 other
= BFD_RELOC_X86_64_TPOFF64
;
3152 case BFD_RELOC_X86_64_DTPOFF32
:
3153 other
= BFD_RELOC_X86_64_DTPOFF64
;
3159 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3160 if (other
== BFD_RELOC_SIZE32
)
3163 other
= BFD_RELOC_SIZE64
;
3166 as_bad (_("there are no pc-relative size relocations"));
3172 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3173 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3176 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3178 as_bad (_("unknown relocation (%u)"), other
);
3179 else if (size
!= bfd_get_reloc_size (rel
))
3180 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3181 bfd_get_reloc_size (rel
),
3183 else if (pcrel
&& !rel
->pc_relative
)
3184 as_bad (_("non-pc-relative relocation for pc-relative field"));
3185 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3187 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3189 as_bad (_("relocated field and relocation type differ in signedness"));
3198 as_bad (_("there are no unsigned pc-relative relocations"));
3201 case 1: return BFD_RELOC_8_PCREL
;
3202 case 2: return BFD_RELOC_16_PCREL
;
3203 case 4: return BFD_RELOC_32_PCREL
;
3204 case 8: return BFD_RELOC_64_PCREL
;
3206 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3213 case 4: return BFD_RELOC_X86_64_32S
;
3218 case 1: return BFD_RELOC_8
;
3219 case 2: return BFD_RELOC_16
;
3220 case 4: return BFD_RELOC_32
;
3221 case 8: return BFD_RELOC_64
;
3223 as_bad (_("cannot do %s %u byte relocation"),
3224 sign
> 0 ? "signed" : "unsigned", size
);
3230 /* Here we decide which fixups can be adjusted to make them relative to
3231 the beginning of the section instead of the symbol. Basically we need
3232 to make sure that the dynamic relocations are done correctly, so in
3233 some cases we force the original symbol to be used. */
3236 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3238 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3242 /* Don't adjust pc-relative references to merge sections in 64-bit
3244 if (use_rela_relocations
3245 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3249 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3250 and changed later by validate_fix. */
3251 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3252 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3255 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3256 for size relocations. */
3257 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3258 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3259 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3260 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3261 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3262 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3263 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3264 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3265 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3266 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3267 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3268 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3269 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3270 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3271 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3272 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3273 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3274 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3275 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3276 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3277 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3278 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3279 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3280 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3281 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3282 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3283 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3284 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3285 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3286 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3287 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3288 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3289 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3296 intel_float_operand (const char *mnemonic
)
3298 /* Note that the value returned is meaningful only for opcodes with (memory)
3299 operands, hence the code here is free to improperly handle opcodes that
3300 have no operands (for better performance and smaller code). */
3302 if (mnemonic
[0] != 'f')
3303 return 0; /* non-math */
3305 switch (mnemonic
[1])
3307 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3308 the fs segment override prefix not currently handled because no
3309 call path can make opcodes without operands get here */
3311 return 2 /* integer op */;
3313 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3314 return 3; /* fldcw/fldenv */
3317 if (mnemonic
[2] != 'o' /* fnop */)
3318 return 3; /* non-waiting control op */
3321 if (mnemonic
[2] == 's')
3322 return 3; /* frstor/frstpm */
3325 if (mnemonic
[2] == 'a')
3326 return 3; /* fsave */
3327 if (mnemonic
[2] == 't')
3329 switch (mnemonic
[3])
3331 case 'c': /* fstcw */
3332 case 'd': /* fstdw */
3333 case 'e': /* fstenv */
3334 case 's': /* fsts[gw] */
3340 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3341 return 0; /* fxsave/fxrstor are not really math ops */
3348 /* Build the VEX prefix. */
3351 build_vex_prefix (const insn_template
*t
)
3353 unsigned int register_specifier
;
3354 unsigned int implied_prefix
;
3355 unsigned int vector_length
;
3357 /* Check register specifier. */
3358 if (i
.vex
.register_specifier
)
3360 register_specifier
=
3361 ~register_number (i
.vex
.register_specifier
) & 0xf;
3362 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3365 register_specifier
= 0xf;
3367 /* Use 2-byte VEX prefix by swapping destination and source
3369 if (i
.vec_encoding
!= vex_encoding_vex3
3370 && i
.dir_encoding
== dir_encoding_default
3371 && i
.operands
== i
.reg_operands
3372 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3373 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3374 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3377 unsigned int xchg
= i
.operands
- 1;
3378 union i386_op temp_op
;
3379 i386_operand_type temp_type
;
3381 temp_type
= i
.types
[xchg
];
3382 i
.types
[xchg
] = i
.types
[0];
3383 i
.types
[0] = temp_type
;
3384 temp_op
= i
.op
[xchg
];
3385 i
.op
[xchg
] = i
.op
[0];
3388 gas_assert (i
.rm
.mode
== 3);
3392 i
.rm
.regmem
= i
.rm
.reg
;
3395 if (i
.tm
.opcode_modifier
.d
)
3396 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3397 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3398 else /* Use the next insn. */
3402 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3403 vector_length
= avxscalar
;
3404 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3410 /* Determine vector length from the last multi-length vector
3413 for (op
= t
->operands
; op
--;)
3414 if (t
->operand_types
[op
].bitfield
.xmmword
3415 && t
->operand_types
[op
].bitfield
.ymmword
3416 && i
.types
[op
].bitfield
.ymmword
)
3423 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3428 case DATA_PREFIX_OPCODE
:
3431 case REPE_PREFIX_OPCODE
:
3434 case REPNE_PREFIX_OPCODE
:
3441 /* Use 2-byte VEX prefix if possible. */
3442 if (i
.vec_encoding
!= vex_encoding_vex3
3443 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3444 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3445 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3447 /* 2-byte VEX prefix. */
3451 i
.vex
.bytes
[0] = 0xc5;
3453 /* Check the REX.R bit. */
3454 r
= (i
.rex
& REX_R
) ? 0 : 1;
3455 i
.vex
.bytes
[1] = (r
<< 7
3456 | register_specifier
<< 3
3457 | vector_length
<< 2
3462 /* 3-byte VEX prefix. */
3467 switch (i
.tm
.opcode_modifier
.vexopcode
)
3471 i
.vex
.bytes
[0] = 0xc4;
3475 i
.vex
.bytes
[0] = 0xc4;
3479 i
.vex
.bytes
[0] = 0xc4;
3483 i
.vex
.bytes
[0] = 0x8f;
3487 i
.vex
.bytes
[0] = 0x8f;
3491 i
.vex
.bytes
[0] = 0x8f;
3497 /* The high 3 bits of the second VEX byte are 1's compliment
3498 of RXB bits from REX. */
3499 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3501 /* Check the REX.W bit. */
3502 w
= (i
.rex
& REX_W
) ? 1 : 0;
3503 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3506 i
.vex
.bytes
[2] = (w
<< 7
3507 | register_specifier
<< 3
3508 | vector_length
<< 2
3513 static INLINE bfd_boolean
3514 is_evex_encoding (const insn_template
*t
)
3516 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3517 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3518 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3521 static INLINE bfd_boolean
3522 is_any_vex_encoding (const insn_template
*t
)
3524 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3525 || is_evex_encoding (t
);
3528 /* Build the EVEX prefix. */
3531 build_evex_prefix (void)
3533 unsigned int register_specifier
;
3534 unsigned int implied_prefix
;
3536 rex_byte vrex_used
= 0;
3538 /* Check register specifier. */
3539 if (i
.vex
.register_specifier
)
3541 gas_assert ((i
.vrex
& REX_X
) == 0);
3543 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3544 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3545 register_specifier
+= 8;
3546 /* The upper 16 registers are encoded in the fourth byte of the
3548 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3549 i
.vex
.bytes
[3] = 0x8;
3550 register_specifier
= ~register_specifier
& 0xf;
3554 register_specifier
= 0xf;
3556 /* Encode upper 16 vector index register in the fourth byte of
3558 if (!(i
.vrex
& REX_X
))
3559 i
.vex
.bytes
[3] = 0x8;
3564 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3569 case DATA_PREFIX_OPCODE
:
3572 case REPE_PREFIX_OPCODE
:
3575 case REPNE_PREFIX_OPCODE
:
3582 /* 4 byte EVEX prefix. */
3584 i
.vex
.bytes
[0] = 0x62;
3587 switch (i
.tm
.opcode_modifier
.vexopcode
)
3603 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3605 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3607 /* The fifth bit of the second EVEX byte is 1's compliment of the
3608 REX_R bit in VREX. */
3609 if (!(i
.vrex
& REX_R
))
3610 i
.vex
.bytes
[1] |= 0x10;
3614 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3616 /* When all operands are registers, the REX_X bit in REX is not
3617 used. We reuse it to encode the upper 16 registers, which is
3618 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3619 as 1's compliment. */
3620 if ((i
.vrex
& REX_B
))
3623 i
.vex
.bytes
[1] &= ~0x40;
3627 /* EVEX instructions shouldn't need the REX prefix. */
3628 i
.vrex
&= ~vrex_used
;
3629 gas_assert (i
.vrex
== 0);
3631 /* Check the REX.W bit. */
3632 w
= (i
.rex
& REX_W
) ? 1 : 0;
3633 if (i
.tm
.opcode_modifier
.vexw
)
3635 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3638 /* If w is not set it means we are dealing with WIG instruction. */
3641 if (evexwig
== evexw1
)
3645 /* Encode the U bit. */
3646 implied_prefix
|= 0x4;
3648 /* The third byte of the EVEX prefix. */
3649 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3651 /* The fourth byte of the EVEX prefix. */
3652 /* The zeroing-masking bit. */
3653 if (i
.mask
&& i
.mask
->zeroing
)
3654 i
.vex
.bytes
[3] |= 0x80;
3656 /* Don't always set the broadcast bit if there is no RC. */
3659 /* Encode the vector length. */
3660 unsigned int vec_length
;
3662 if (!i
.tm
.opcode_modifier
.evex
3663 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3667 /* Determine vector length from the last multi-length vector
3670 for (op
= i
.operands
; op
--;)
3671 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3672 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3673 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3675 if (i
.types
[op
].bitfield
.zmmword
)
3677 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3680 else if (i
.types
[op
].bitfield
.ymmword
)
3682 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3685 else if (i
.types
[op
].bitfield
.xmmword
)
3687 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3690 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3692 switch (i
.broadcast
->bytes
)
3695 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3698 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3701 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3710 if (op
>= MAX_OPERANDS
)
3714 switch (i
.tm
.opcode_modifier
.evex
)
3716 case EVEXLIG
: /* LL' is ignored */
3717 vec_length
= evexlig
<< 5;
3720 vec_length
= 0 << 5;
3723 vec_length
= 1 << 5;
3726 vec_length
= 2 << 5;
3732 i
.vex
.bytes
[3] |= vec_length
;
3733 /* Encode the broadcast bit. */
3735 i
.vex
.bytes
[3] |= 0x10;
3739 if (i
.rounding
->type
!= saeonly
)
3740 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3742 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3745 if (i
.mask
&& i
.mask
->mask
)
3746 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3750 process_immext (void)
3754 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3757 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3758 with an opcode suffix which is coded in the same place as an
3759 8-bit immediate field would be.
3760 Here we check those operands and remove them afterwards. */
3763 for (x
= 0; x
< i
.operands
; x
++)
3764 if (register_number (i
.op
[x
].regs
) != x
)
3765 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3766 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3772 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3774 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3775 suffix which is coded in the same place as an 8-bit immediate
3777 Here we check those operands and remove them afterwards. */
3780 if (i
.operands
!= 3)
3783 for (x
= 0; x
< 2; x
++)
3784 if (register_number (i
.op
[x
].regs
) != x
)
3785 goto bad_register_operand
;
3787 /* Check for third operand for mwaitx/monitorx insn. */
3788 if (register_number (i
.op
[x
].regs
)
3789 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3791 bad_register_operand
:
3792 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3793 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3800 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3801 which is coded in the same place as an 8-bit immediate field
3802 would be. Here we fake an 8-bit immediate operand from the
3803 opcode suffix stored in tm.extension_opcode.
3805 AVX instructions also use this encoding, for some of
3806 3 argument instructions. */
3808 gas_assert (i
.imm_operands
<= 1
3810 || (is_any_vex_encoding (&i
.tm
)
3811 && i
.operands
<= 4)));
3813 exp
= &im_expressions
[i
.imm_operands
++];
3814 i
.op
[i
.operands
].imms
= exp
;
3815 i
.types
[i
.operands
] = imm8
;
3817 exp
->X_op
= O_constant
;
3818 exp
->X_add_number
= i
.tm
.extension_opcode
;
3819 i
.tm
.extension_opcode
= None
;
3826 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3831 as_bad (_("invalid instruction `%s' after `%s'"),
3832 i
.tm
.name
, i
.hle_prefix
);
3835 if (i
.prefix
[LOCK_PREFIX
])
3837 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3841 case HLEPrefixRelease
:
3842 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3844 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3848 if (i
.mem_operands
== 0
3849 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3851 as_bad (_("memory destination needed for instruction `%s'"
3852 " after `xrelease'"), i
.tm
.name
);
3859 /* Try the shortest encoding by shortening operand size. */
3862 optimize_encoding (void)
3866 if (optimize_for_space
3867 && i
.reg_operands
== 1
3868 && i
.imm_operands
== 1
3869 && !i
.types
[1].bitfield
.byte
3870 && i
.op
[0].imms
->X_op
== O_constant
3871 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3872 && ((i
.tm
.base_opcode
== 0xa8
3873 && i
.tm
.extension_opcode
== None
)
3874 || (i
.tm
.base_opcode
== 0xf6
3875 && i
.tm
.extension_opcode
== 0x0)))
3878 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3880 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3881 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3883 i
.types
[1].bitfield
.byte
= 1;
3884 /* Ignore the suffix. */
3886 if (base_regnum
>= 4
3887 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3889 /* Handle SP, BP, SI and DI registers. */
3890 if (i
.types
[1].bitfield
.word
)
3892 else if (i
.types
[1].bitfield
.dword
)
3900 else if (flag_code
== CODE_64BIT
3901 && ((i
.types
[1].bitfield
.qword
3902 && i
.reg_operands
== 1
3903 && i
.imm_operands
== 1
3904 && i
.op
[0].imms
->X_op
== O_constant
3905 && ((i
.tm
.base_opcode
== 0xb0
3906 && i
.tm
.extension_opcode
== None
3907 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3908 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3909 && (((i
.tm
.base_opcode
== 0x24
3910 || i
.tm
.base_opcode
== 0xa8)
3911 && i
.tm
.extension_opcode
== None
)
3912 || (i
.tm
.base_opcode
== 0x80
3913 && i
.tm
.extension_opcode
== 0x4)
3914 || ((i
.tm
.base_opcode
== 0xf6
3915 || i
.tm
.base_opcode
== 0xc6)
3916 && i
.tm
.extension_opcode
== 0x0)))))
3917 || (i
.types
[0].bitfield
.qword
3918 && ((i
.reg_operands
== 2
3919 && i
.op
[0].regs
== i
.op
[1].regs
3920 && ((i
.tm
.base_opcode
== 0x30
3921 || i
.tm
.base_opcode
== 0x28)
3922 && i
.tm
.extension_opcode
== None
))
3923 || (i
.reg_operands
== 1
3925 && i
.tm
.base_opcode
== 0x30
3926 && i
.tm
.extension_opcode
== None
)))))
3929 andq $imm31, %r64 -> andl $imm31, %r32
3930 testq $imm31, %r64 -> testl $imm31, %r32
3931 xorq %r64, %r64 -> xorl %r32, %r32
3932 subq %r64, %r64 -> subl %r32, %r32
3933 movq $imm31, %r64 -> movl $imm31, %r32
3934 movq $imm32, %r64 -> movl $imm32, %r32
3936 i
.tm
.opcode_modifier
.norex64
= 1;
3937 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3940 movq $imm31, %r64 -> movl $imm31, %r32
3941 movq $imm32, %r64 -> movl $imm32, %r32
3943 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3944 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3945 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3946 i
.types
[0].bitfield
.imm32
= 1;
3947 i
.types
[0].bitfield
.imm32s
= 0;
3948 i
.types
[0].bitfield
.imm64
= 0;
3949 i
.types
[1].bitfield
.dword
= 1;
3950 i
.types
[1].bitfield
.qword
= 0;
3951 if (i
.tm
.base_opcode
== 0xc6)
3954 movq $imm31, %r64 -> movl $imm31, %r32
3956 i
.tm
.base_opcode
= 0xb0;
3957 i
.tm
.extension_opcode
= None
;
3958 i
.tm
.opcode_modifier
.shortform
= 1;
3959 i
.tm
.opcode_modifier
.modrm
= 0;
3963 else if (optimize
> 1
3964 && i
.reg_operands
== 3
3965 && i
.op
[0].regs
== i
.op
[1].regs
3966 && !i
.types
[2].bitfield
.xmmword
3967 && (i
.tm
.opcode_modifier
.vex
3968 || ((!i
.mask
|| i
.mask
->zeroing
)
3970 && is_evex_encoding (&i
.tm
)
3971 && (i
.vec_encoding
!= vex_encoding_evex
3972 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3973 || (i
.tm
.operand_types
[2].bitfield
.zmmword
3974 && i
.types
[2].bitfield
.ymmword
)
3975 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3976 && ((i
.tm
.base_opcode
== 0x55
3977 || i
.tm
.base_opcode
== 0x6655
3978 || i
.tm
.base_opcode
== 0x66df
3979 || i
.tm
.base_opcode
== 0x57
3980 || i
.tm
.base_opcode
== 0x6657
3981 || i
.tm
.base_opcode
== 0x66ef
3982 || i
.tm
.base_opcode
== 0x66f8
3983 || i
.tm
.base_opcode
== 0x66f9
3984 || i
.tm
.base_opcode
== 0x66fa
3985 || i
.tm
.base_opcode
== 0x66fb
3986 || i
.tm
.base_opcode
== 0x42
3987 || i
.tm
.base_opcode
== 0x6642
3988 || i
.tm
.base_opcode
== 0x47
3989 || i
.tm
.base_opcode
== 0x6647)
3990 && i
.tm
.extension_opcode
== None
))
3993 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3995 EVEX VOP %zmmM, %zmmM, %zmmN
3996 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3997 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3998 EVEX VOP %ymmM, %ymmM, %ymmN
3999 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4000 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4001 VEX VOP %ymmM, %ymmM, %ymmN
4002 -> VEX VOP %xmmM, %xmmM, %xmmN
4003 VOP, one of vpandn and vpxor:
4004 VEX VOP %ymmM, %ymmM, %ymmN
4005 -> VEX VOP %xmmM, %xmmM, %xmmN
4006 VOP, one of vpandnd and vpandnq:
4007 EVEX VOP %zmmM, %zmmM, %zmmN
4008 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4009 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4010 EVEX VOP %ymmM, %ymmM, %ymmN
4011 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4012 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4013 VOP, one of vpxord and vpxorq:
4014 EVEX VOP %zmmM, %zmmM, %zmmN
4015 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4016 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4017 EVEX VOP %ymmM, %ymmM, %ymmN
4018 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4019 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4020 VOP, one of kxord and kxorq:
4021 VEX VOP %kM, %kM, %kN
4022 -> VEX kxorw %kM, %kM, %kN
4023 VOP, one of kandnd and kandnq:
4024 VEX VOP %kM, %kM, %kN
4025 -> VEX kandnw %kM, %kM, %kN
4027 if (is_evex_encoding (&i
.tm
))
4029 if (i
.vec_encoding
== vex_encoding_evex
)
4030 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4033 i
.tm
.opcode_modifier
.vex
= VEX128
;
4034 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4035 i
.tm
.opcode_modifier
.evex
= 0;
4038 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4040 i
.tm
.base_opcode
&= 0xff;
4041 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4044 i
.tm
.opcode_modifier
.vex
= VEX128
;
4046 if (i
.tm
.opcode_modifier
.vex
)
4047 for (j
= 0; j
< 3; j
++)
4049 i
.types
[j
].bitfield
.xmmword
= 1;
4050 i
.types
[j
].bitfield
.ymmword
= 0;
4055 /* This is the guts of the machine-dependent assembler. LINE points to a
4056 machine dependent instruction. This function is supposed to emit
4057 the frags/bytes it assembles to. */
4060 md_assemble (char *line
)
4063 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4064 const insn_template
*t
;
4066 /* Initialize globals. */
4067 memset (&i
, '\0', sizeof (i
));
4068 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4069 i
.reloc
[j
] = NO_RELOC
;
4070 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4071 memset (im_expressions
, '\0', sizeof (im_expressions
));
4072 save_stack_p
= save_stack
;
4074 /* First parse an instruction mnemonic & call i386_operand for the operands.
4075 We assume that the scrubber has arranged it so that line[0] is the valid
4076 start of a (possibly prefixed) mnemonic. */
4078 line
= parse_insn (line
, mnemonic
);
4081 mnem_suffix
= i
.suffix
;
4083 line
= parse_operands (line
, mnemonic
);
4085 xfree (i
.memop1_string
);
4086 i
.memop1_string
= NULL
;
4090 /* Now we've parsed the mnemonic into a set of templates, and have the
4091 operands at hand. */
4093 /* All intel opcodes have reversed operands except for "bound" and
4094 "enter". We also don't reverse intersegment "jmp" and "call"
4095 instructions with 2 immediate operands so that the immediate segment
4096 precedes the offset, as it does when in AT&T mode. */
4099 && (strcmp (mnemonic
, "bound") != 0)
4100 && (strcmp (mnemonic
, "invlpga") != 0)
4101 && !(operand_type_check (i
.types
[0], imm
)
4102 && operand_type_check (i
.types
[1], imm
)))
4105 /* The order of the immediates should be reversed
4106 for 2 immediates extrq and insertq instructions */
4107 if (i
.imm_operands
== 2
4108 && (strcmp (mnemonic
, "extrq") == 0
4109 || strcmp (mnemonic
, "insertq") == 0))
4110 swap_2_operands (0, 1);
4115 /* Don't optimize displacement for movabs since it only takes 64bit
4118 && i
.disp_encoding
!= disp_encoding_32bit
4119 && (flag_code
!= CODE_64BIT
4120 || strcmp (mnemonic
, "movabs") != 0))
4123 /* Next, we find a template that matches the given insn,
4124 making sure the overlap of the given operands types is consistent
4125 with the template operand types. */
4127 if (!(t
= match_template (mnem_suffix
)))
4130 if (sse_check
!= check_none
4131 && !i
.tm
.opcode_modifier
.noavx
4132 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4133 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4134 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4135 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4136 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4137 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4138 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4139 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4140 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4141 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4143 (sse_check
== check_warning
4145 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4148 /* Zap movzx and movsx suffix. The suffix has been set from
4149 "word ptr" or "byte ptr" on the source operand in Intel syntax
4150 or extracted from mnemonic in AT&T syntax. But we'll use
4151 the destination register to choose the suffix for encoding. */
4152 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4154 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4155 there is no suffix, the default will be byte extension. */
4156 if (i
.reg_operands
!= 2
4159 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4164 if (i
.tm
.opcode_modifier
.fwait
)
4165 if (!add_prefix (FWAIT_OPCODE
))
4168 /* Check if REP prefix is OK. */
4169 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4171 as_bad (_("invalid instruction `%s' after `%s'"),
4172 i
.tm
.name
, i
.rep_prefix
);
4176 /* Check for lock without a lockable instruction. Destination operand
4177 must be memory unless it is xchg (0x86). */
4178 if (i
.prefix
[LOCK_PREFIX
]
4179 && (!i
.tm
.opcode_modifier
.islockable
4180 || i
.mem_operands
== 0
4181 || (i
.tm
.base_opcode
!= 0x86
4182 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4184 as_bad (_("expecting lockable instruction after `lock'"));
4188 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4189 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4191 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4195 /* Check if HLE prefix is OK. */
4196 if (i
.hle_prefix
&& !check_hle ())
4199 /* Check BND prefix. */
4200 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4201 as_bad (_("expecting valid branch instruction after `bnd'"));
4203 /* Check NOTRACK prefix. */
4204 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4205 as_bad (_("expecting indirect branch instruction after `notrack'"));
4207 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4209 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4210 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4211 else if (flag_code
!= CODE_16BIT
4212 ? i
.prefix
[ADDR_PREFIX
]
4213 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4214 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4217 /* Insert BND prefix. */
4218 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4220 if (!i
.prefix
[BND_PREFIX
])
4221 add_prefix (BND_PREFIX_OPCODE
);
4222 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4224 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4225 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4229 /* Check string instruction segment overrides. */
4230 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4232 if (!check_string ())
4234 i
.disp_operands
= 0;
4237 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4238 optimize_encoding ();
4240 if (!process_suffix ())
4243 /* Update operand types. */
4244 for (j
= 0; j
< i
.operands
; j
++)
4245 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4247 /* Make still unresolved immediate matches conform to size of immediate
4248 given in i.suffix. */
4249 if (!finalize_imm ())
4252 if (i
.types
[0].bitfield
.imm1
)
4253 i
.imm_operands
= 0; /* kludge for shift insns. */
4255 /* We only need to check those implicit registers for instructions
4256 with 3 operands or less. */
4257 if (i
.operands
<= 3)
4258 for (j
= 0; j
< i
.operands
; j
++)
4259 if (i
.types
[j
].bitfield
.inoutportreg
4260 || i
.types
[j
].bitfield
.shiftcount
4261 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4264 /* ImmExt should be processed after SSE2AVX. */
4265 if (!i
.tm
.opcode_modifier
.sse2avx
4266 && i
.tm
.opcode_modifier
.immext
)
4269 /* For insns with operands there are more diddles to do to the opcode. */
4272 if (!process_operands ())
4275 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4277 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4278 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4281 if (is_any_vex_encoding (&i
.tm
))
4283 if (flag_code
== CODE_16BIT
)
4285 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4290 if (i
.tm
.opcode_modifier
.vex
)
4291 build_vex_prefix (t
);
4293 build_evex_prefix ();
4296 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4297 instructions may define INT_OPCODE as well, so avoid this corner
4298 case for those instructions that use MODRM. */
4299 if (i
.tm
.base_opcode
== INT_OPCODE
4300 && !i
.tm
.opcode_modifier
.modrm
4301 && i
.op
[0].imms
->X_add_number
== 3)
4303 i
.tm
.base_opcode
= INT3_OPCODE
;
4307 if ((i
.tm
.opcode_modifier
.jump
4308 || i
.tm
.opcode_modifier
.jumpbyte
4309 || i
.tm
.opcode_modifier
.jumpdword
)
4310 && i
.op
[0].disps
->X_op
== O_constant
)
4312 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4313 the absolute address given by the constant. Since ix86 jumps and
4314 calls are pc relative, we need to generate a reloc. */
4315 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4316 i
.op
[0].disps
->X_op
= O_symbol
;
4319 if (i
.tm
.opcode_modifier
.rex64
)
4322 /* For 8 bit registers we need an empty rex prefix. Also if the
4323 instruction already has a prefix, we need to convert old
4324 registers to new ones. */
4326 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4327 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4328 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4329 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4330 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4331 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4336 i
.rex
|= REX_OPCODE
;
4337 for (x
= 0; x
< 2; x
++)
4339 /* Look for 8 bit operand that uses old registers. */
4340 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4341 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4343 /* In case it is "hi" register, give up. */
4344 if (i
.op
[x
].regs
->reg_num
> 3)
4345 as_bad (_("can't encode register '%s%s' in an "
4346 "instruction requiring REX prefix."),
4347 register_prefix
, i
.op
[x
].regs
->reg_name
);
4349 /* Otherwise it is equivalent to the extended register.
4350 Since the encoding doesn't change this is merely
4351 cosmetic cleanup for debug output. */
4353 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4358 if (i
.rex
== 0 && i
.rex_encoding
)
4360 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4361 that uses legacy register. If it is "hi" register, don't add
4362 the REX_OPCODE byte. */
4364 for (x
= 0; x
< 2; x
++)
4365 if (i
.types
[x
].bitfield
.reg
4366 && i
.types
[x
].bitfield
.byte
4367 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4368 && i
.op
[x
].regs
->reg_num
> 3)
4370 i
.rex_encoding
= FALSE
;
4379 add_prefix (REX_OPCODE
| i
.rex
);
4381 /* We are ready to output the insn. */
4386 parse_insn (char *line
, char *mnemonic
)
4389 char *token_start
= l
;
4392 const insn_template
*t
;
4398 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4403 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4405 as_bad (_("no such instruction: `%s'"), token_start
);
4410 if (!is_space_char (*l
)
4411 && *l
!= END_OF_INSN
4413 || (*l
!= PREFIX_SEPARATOR
4416 as_bad (_("invalid character %s in mnemonic"),
4417 output_invalid (*l
));
4420 if (token_start
== l
)
4422 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4423 as_bad (_("expecting prefix; got nothing"));
4425 as_bad (_("expecting mnemonic; got nothing"));
4429 /* Look up instruction (or prefix) via hash table. */
4430 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4432 if (*l
!= END_OF_INSN
4433 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4434 && current_templates
4435 && current_templates
->start
->opcode_modifier
.isprefix
)
4437 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4439 as_bad ((flag_code
!= CODE_64BIT
4440 ? _("`%s' is only supported in 64-bit mode")
4441 : _("`%s' is not supported in 64-bit mode")),
4442 current_templates
->start
->name
);
4445 /* If we are in 16-bit mode, do not allow addr16 or data16.
4446 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4447 if ((current_templates
->start
->opcode_modifier
.size16
4448 || current_templates
->start
->opcode_modifier
.size32
)
4449 && flag_code
!= CODE_64BIT
4450 && (current_templates
->start
->opcode_modifier
.size32
4451 ^ (flag_code
== CODE_16BIT
)))
4453 as_bad (_("redundant %s prefix"),
4454 current_templates
->start
->name
);
4457 if (current_templates
->start
->opcode_length
== 0)
4459 /* Handle pseudo prefixes. */
4460 switch (current_templates
->start
->base_opcode
)
4464 i
.disp_encoding
= disp_encoding_8bit
;
4468 i
.disp_encoding
= disp_encoding_32bit
;
4472 i
.dir_encoding
= dir_encoding_load
;
4476 i
.dir_encoding
= dir_encoding_store
;
4480 i
.vec_encoding
= vex_encoding_vex2
;
4484 i
.vec_encoding
= vex_encoding_vex3
;
4488 i
.vec_encoding
= vex_encoding_evex
;
4492 i
.rex_encoding
= TRUE
;
4496 i
.no_optimize
= TRUE
;
4504 /* Add prefix, checking for repeated prefixes. */
4505 switch (add_prefix (current_templates
->start
->base_opcode
))
4510 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4511 i
.notrack_prefix
= current_templates
->start
->name
;
4514 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4515 i
.hle_prefix
= current_templates
->start
->name
;
4516 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4517 i
.bnd_prefix
= current_templates
->start
->name
;
4519 i
.rep_prefix
= current_templates
->start
->name
;
4525 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4532 if (!current_templates
)
4534 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4535 Check if we should swap operand or force 32bit displacement in
4537 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4538 i
.dir_encoding
= dir_encoding_swap
;
4539 else if (mnem_p
- 3 == dot_p
4542 i
.disp_encoding
= disp_encoding_8bit
;
4543 else if (mnem_p
- 4 == dot_p
4547 i
.disp_encoding
= disp_encoding_32bit
;
4552 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4555 if (!current_templates
)
4558 /* See if we can get a match by trimming off a suffix. */
4561 case WORD_MNEM_SUFFIX
:
4562 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4563 i
.suffix
= SHORT_MNEM_SUFFIX
;
4566 case BYTE_MNEM_SUFFIX
:
4567 case QWORD_MNEM_SUFFIX
:
4568 i
.suffix
= mnem_p
[-1];
4570 current_templates
= (const templates
*) hash_find (op_hash
,
4573 case SHORT_MNEM_SUFFIX
:
4574 case LONG_MNEM_SUFFIX
:
4577 i
.suffix
= mnem_p
[-1];
4579 current_templates
= (const templates
*) hash_find (op_hash
,
4588 if (intel_float_operand (mnemonic
) == 1)
4589 i
.suffix
= SHORT_MNEM_SUFFIX
;
4591 i
.suffix
= LONG_MNEM_SUFFIX
;
4593 current_templates
= (const templates
*) hash_find (op_hash
,
4598 if (!current_templates
)
4600 as_bad (_("no such instruction: `%s'"), token_start
);
4605 if (current_templates
->start
->opcode_modifier
.jump
4606 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4608 /* Check for a branch hint. We allow ",pt" and ",pn" for
4609 predict taken and predict not taken respectively.
4610 I'm not sure that branch hints actually do anything on loop
4611 and jcxz insns (JumpByte) for current Pentium4 chips. They
4612 may work in the future and it doesn't hurt to accept them
4614 if (l
[0] == ',' && l
[1] == 'p')
4618 if (!add_prefix (DS_PREFIX_OPCODE
))
4622 else if (l
[2] == 'n')
4624 if (!add_prefix (CS_PREFIX_OPCODE
))
4630 /* Any other comma loses. */
4633 as_bad (_("invalid character %s in mnemonic"),
4634 output_invalid (*l
));
4638 /* Check if instruction is supported on specified architecture. */
4640 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4642 supported
|= cpu_flags_match (t
);
4643 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4645 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4646 as_warn (_("use .code16 to ensure correct addressing mode"));
4652 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4653 as_bad (flag_code
== CODE_64BIT
4654 ? _("`%s' is not supported in 64-bit mode")
4655 : _("`%s' is only supported in 64-bit mode"),
4656 current_templates
->start
->name
);
4658 as_bad (_("`%s' is not supported on `%s%s'"),
4659 current_templates
->start
->name
,
4660 cpu_arch_name
? cpu_arch_name
: default_arch
,
4661 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4667 parse_operands (char *l
, const char *mnemonic
)
4671 /* 1 if operand is pending after ','. */
4672 unsigned int expecting_operand
= 0;
4674 /* Non-zero if operand parens not balanced. */
4675 unsigned int paren_not_balanced
;
4677 while (*l
!= END_OF_INSN
)
4679 /* Skip optional white space before operand. */
4680 if (is_space_char (*l
))
4682 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4684 as_bad (_("invalid character %s before operand %d"),
4685 output_invalid (*l
),
4689 token_start
= l
; /* After white space. */
4690 paren_not_balanced
= 0;
4691 while (paren_not_balanced
|| *l
!= ',')
4693 if (*l
== END_OF_INSN
)
4695 if (paren_not_balanced
)
4698 as_bad (_("unbalanced parenthesis in operand %d."),
4701 as_bad (_("unbalanced brackets in operand %d."),
4706 break; /* we are done */
4708 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4710 as_bad (_("invalid character %s in operand %d"),
4711 output_invalid (*l
),
4718 ++paren_not_balanced
;
4720 --paren_not_balanced
;
4725 ++paren_not_balanced
;
4727 --paren_not_balanced
;
4731 if (l
!= token_start
)
4732 { /* Yes, we've read in another operand. */
4733 unsigned int operand_ok
;
4734 this_operand
= i
.operands
++;
4735 if (i
.operands
> MAX_OPERANDS
)
4737 as_bad (_("spurious operands; (%d operands/instruction max)"),
4741 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4742 /* Now parse operand adding info to 'i' as we go along. */
4743 END_STRING_AND_SAVE (l
);
4745 if (i
.mem_operands
> 1)
4747 as_bad (_("too many memory references for `%s'"),
4754 i386_intel_operand (token_start
,
4755 intel_float_operand (mnemonic
));
4757 operand_ok
= i386_att_operand (token_start
);
4759 RESTORE_END_STRING (l
);
4765 if (expecting_operand
)
4767 expecting_operand_after_comma
:
4768 as_bad (_("expecting operand after ','; got nothing"));
4773 as_bad (_("expecting operand before ','; got nothing"));
4778 /* Now *l must be either ',' or END_OF_INSN. */
4781 if (*++l
== END_OF_INSN
)
4783 /* Just skip it, if it's \n complain. */
4784 goto expecting_operand_after_comma
;
4786 expecting_operand
= 1;
4793 swap_2_operands (int xchg1
, int xchg2
)
4795 union i386_op temp_op
;
4796 i386_operand_type temp_type
;
4797 unsigned int temp_flags
;
4798 enum bfd_reloc_code_real temp_reloc
;
4800 temp_type
= i
.types
[xchg2
];
4801 i
.types
[xchg2
] = i
.types
[xchg1
];
4802 i
.types
[xchg1
] = temp_type
;
4804 temp_flags
= i
.flags
[xchg2
];
4805 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4806 i
.flags
[xchg1
] = temp_flags
;
4808 temp_op
= i
.op
[xchg2
];
4809 i
.op
[xchg2
] = i
.op
[xchg1
];
4810 i
.op
[xchg1
] = temp_op
;
4812 temp_reloc
= i
.reloc
[xchg2
];
4813 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4814 i
.reloc
[xchg1
] = temp_reloc
;
4818 if (i
.mask
->operand
== xchg1
)
4819 i
.mask
->operand
= xchg2
;
4820 else if (i
.mask
->operand
== xchg2
)
4821 i
.mask
->operand
= xchg1
;
4825 if (i
.broadcast
->operand
== xchg1
)
4826 i
.broadcast
->operand
= xchg2
;
4827 else if (i
.broadcast
->operand
== xchg2
)
4828 i
.broadcast
->operand
= xchg1
;
4832 if (i
.rounding
->operand
== xchg1
)
4833 i
.rounding
->operand
= xchg2
;
4834 else if (i
.rounding
->operand
== xchg2
)
4835 i
.rounding
->operand
= xchg1
;
4840 swap_operands (void)
4846 swap_2_operands (1, i
.operands
- 2);
4850 swap_2_operands (0, i
.operands
- 1);
4856 if (i
.mem_operands
== 2)
4858 const seg_entry
*temp_seg
;
4859 temp_seg
= i
.seg
[0];
4860 i
.seg
[0] = i
.seg
[1];
4861 i
.seg
[1] = temp_seg
;
4865 /* Try to ensure constant immediates are represented in the smallest
4870 char guess_suffix
= 0;
4874 guess_suffix
= i
.suffix
;
4875 else if (i
.reg_operands
)
4877 /* Figure out a suffix from the last register operand specified.
4878 We can't do this properly yet, ie. excluding InOutPortReg,
4879 but the following works for instructions with immediates.
4880 In any case, we can't set i.suffix yet. */
4881 for (op
= i
.operands
; --op
>= 0;)
4882 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4884 guess_suffix
= BYTE_MNEM_SUFFIX
;
4887 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4889 guess_suffix
= WORD_MNEM_SUFFIX
;
4892 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4894 guess_suffix
= LONG_MNEM_SUFFIX
;
4897 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4899 guess_suffix
= QWORD_MNEM_SUFFIX
;
4903 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4904 guess_suffix
= WORD_MNEM_SUFFIX
;
4906 for (op
= i
.operands
; --op
>= 0;)
4907 if (operand_type_check (i
.types
[op
], imm
))
4909 switch (i
.op
[op
].imms
->X_op
)
4912 /* If a suffix is given, this operand may be shortened. */
4913 switch (guess_suffix
)
4915 case LONG_MNEM_SUFFIX
:
4916 i
.types
[op
].bitfield
.imm32
= 1;
4917 i
.types
[op
].bitfield
.imm64
= 1;
4919 case WORD_MNEM_SUFFIX
:
4920 i
.types
[op
].bitfield
.imm16
= 1;
4921 i
.types
[op
].bitfield
.imm32
= 1;
4922 i
.types
[op
].bitfield
.imm32s
= 1;
4923 i
.types
[op
].bitfield
.imm64
= 1;
4925 case BYTE_MNEM_SUFFIX
:
4926 i
.types
[op
].bitfield
.imm8
= 1;
4927 i
.types
[op
].bitfield
.imm8s
= 1;
4928 i
.types
[op
].bitfield
.imm16
= 1;
4929 i
.types
[op
].bitfield
.imm32
= 1;
4930 i
.types
[op
].bitfield
.imm32s
= 1;
4931 i
.types
[op
].bitfield
.imm64
= 1;
4935 /* If this operand is at most 16 bits, convert it
4936 to a signed 16 bit number before trying to see
4937 whether it will fit in an even smaller size.
4938 This allows a 16-bit operand such as $0xffe0 to
4939 be recognised as within Imm8S range. */
4940 if ((i
.types
[op
].bitfield
.imm16
)
4941 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4943 i
.op
[op
].imms
->X_add_number
=
4944 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4947 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4948 if ((i
.types
[op
].bitfield
.imm32
)
4949 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4952 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4953 ^ ((offsetT
) 1 << 31))
4954 - ((offsetT
) 1 << 31));
4958 = operand_type_or (i
.types
[op
],
4959 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4961 /* We must avoid matching of Imm32 templates when 64bit
4962 only immediate is available. */
4963 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4964 i
.types
[op
].bitfield
.imm32
= 0;
4971 /* Symbols and expressions. */
4973 /* Convert symbolic operand to proper sizes for matching, but don't
4974 prevent matching a set of insns that only supports sizes other
4975 than those matching the insn suffix. */
4977 i386_operand_type mask
, allowed
;
4978 const insn_template
*t
;
4980 operand_type_set (&mask
, 0);
4981 operand_type_set (&allowed
, 0);
4983 for (t
= current_templates
->start
;
4984 t
< current_templates
->end
;
4986 allowed
= operand_type_or (allowed
,
4987 t
->operand_types
[op
]);
4988 switch (guess_suffix
)
4990 case QWORD_MNEM_SUFFIX
:
4991 mask
.bitfield
.imm64
= 1;
4992 mask
.bitfield
.imm32s
= 1;
4994 case LONG_MNEM_SUFFIX
:
4995 mask
.bitfield
.imm32
= 1;
4997 case WORD_MNEM_SUFFIX
:
4998 mask
.bitfield
.imm16
= 1;
5000 case BYTE_MNEM_SUFFIX
:
5001 mask
.bitfield
.imm8
= 1;
5006 allowed
= operand_type_and (mask
, allowed
);
5007 if (!operand_type_all_zero (&allowed
))
5008 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5015 /* Try to use the smallest displacement type too. */
5017 optimize_disp (void)
5021 for (op
= i
.operands
; --op
>= 0;)
5022 if (operand_type_check (i
.types
[op
], disp
))
5024 if (i
.op
[op
].disps
->X_op
== O_constant
)
5026 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5028 if (i
.types
[op
].bitfield
.disp16
5029 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5031 /* If this operand is at most 16 bits, convert
5032 to a signed 16 bit number and don't use 64bit
5034 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5035 i
.types
[op
].bitfield
.disp64
= 0;
5038 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5039 if (i
.types
[op
].bitfield
.disp32
5040 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5042 /* If this operand is at most 32 bits, convert
5043 to a signed 32 bit number and don't use 64bit
5045 op_disp
&= (((offsetT
) 2 << 31) - 1);
5046 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5047 i
.types
[op
].bitfield
.disp64
= 0;
5050 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5052 i
.types
[op
].bitfield
.disp8
= 0;
5053 i
.types
[op
].bitfield
.disp16
= 0;
5054 i
.types
[op
].bitfield
.disp32
= 0;
5055 i
.types
[op
].bitfield
.disp32s
= 0;
5056 i
.types
[op
].bitfield
.disp64
= 0;
5060 else if (flag_code
== CODE_64BIT
)
5062 if (fits_in_signed_long (op_disp
))
5064 i
.types
[op
].bitfield
.disp64
= 0;
5065 i
.types
[op
].bitfield
.disp32s
= 1;
5067 if (i
.prefix
[ADDR_PREFIX
]
5068 && fits_in_unsigned_long (op_disp
))
5069 i
.types
[op
].bitfield
.disp32
= 1;
5071 if ((i
.types
[op
].bitfield
.disp32
5072 || i
.types
[op
].bitfield
.disp32s
5073 || i
.types
[op
].bitfield
.disp16
)
5074 && fits_in_disp8 (op_disp
))
5075 i
.types
[op
].bitfield
.disp8
= 1;
5077 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5078 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5080 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5081 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5082 i
.types
[op
].bitfield
.disp8
= 0;
5083 i
.types
[op
].bitfield
.disp16
= 0;
5084 i
.types
[op
].bitfield
.disp32
= 0;
5085 i
.types
[op
].bitfield
.disp32s
= 0;
5086 i
.types
[op
].bitfield
.disp64
= 0;
5089 /* We only support 64bit displacement on constants. */
5090 i
.types
[op
].bitfield
.disp64
= 0;
5094 /* Return 1 if there is a match in broadcast bytes between operand
5095 GIVEN and instruction template T. */
5098 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5100 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5101 && i
.types
[given
].bitfield
.byte
)
5102 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5103 && i
.types
[given
].bitfield
.word
)
5104 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5105 && i
.types
[given
].bitfield
.dword
)
5106 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5107 && i
.types
[given
].bitfield
.qword
));
5110 /* Check if operands are valid for the instruction. */
5113 check_VecOperands (const insn_template
*t
)
5117 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5119 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5120 any one operand are implicity requiring AVX512VL support if the actual
5121 operand size is YMMword or XMMword. Since this function runs after
5122 template matching, there's no need to check for YMMword/XMMword in
5124 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5125 if (!cpu_flags_all_zero (&cpu
)
5126 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5127 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5129 for (op
= 0; op
< t
->operands
; ++op
)
5131 if (t
->operand_types
[op
].bitfield
.zmmword
5132 && (i
.types
[op
].bitfield
.ymmword
5133 || i
.types
[op
].bitfield
.xmmword
))
5135 i
.error
= unsupported
;
5141 /* Without VSIB byte, we can't have a vector register for index. */
5142 if (!t
->opcode_modifier
.vecsib
5144 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5145 || i
.index_reg
->reg_type
.bitfield
.ymmword
5146 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5148 i
.error
= unsupported_vector_index_register
;
5152 /* Check if default mask is allowed. */
5153 if (t
->opcode_modifier
.nodefmask
5154 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5156 i
.error
= no_default_mask
;
5160 /* For VSIB byte, we need a vector register for index, and all vector
5161 registers must be distinct. */
5162 if (t
->opcode_modifier
.vecsib
)
5165 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5166 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5167 || (t
->opcode_modifier
.vecsib
== VecSIB256
5168 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5169 || (t
->opcode_modifier
.vecsib
== VecSIB512
5170 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5172 i
.error
= invalid_vsib_address
;
5176 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5177 if (i
.reg_operands
== 2 && !i
.mask
)
5179 gas_assert (i
.types
[0].bitfield
.regsimd
);
5180 gas_assert (i
.types
[0].bitfield
.xmmword
5181 || i
.types
[0].bitfield
.ymmword
);
5182 gas_assert (i
.types
[2].bitfield
.regsimd
);
5183 gas_assert (i
.types
[2].bitfield
.xmmword
5184 || i
.types
[2].bitfield
.ymmword
);
5185 if (operand_check
== check_none
)
5187 if (register_number (i
.op
[0].regs
)
5188 != register_number (i
.index_reg
)
5189 && register_number (i
.op
[2].regs
)
5190 != register_number (i
.index_reg
)
5191 && register_number (i
.op
[0].regs
)
5192 != register_number (i
.op
[2].regs
))
5194 if (operand_check
== check_error
)
5196 i
.error
= invalid_vector_register_set
;
5199 as_warn (_("mask, index, and destination registers should be distinct"));
5201 else if (i
.reg_operands
== 1 && i
.mask
)
5203 if (i
.types
[1].bitfield
.regsimd
5204 && (i
.types
[1].bitfield
.xmmword
5205 || i
.types
[1].bitfield
.ymmword
5206 || i
.types
[1].bitfield
.zmmword
)
5207 && (register_number (i
.op
[1].regs
)
5208 == register_number (i
.index_reg
)))
5210 if (operand_check
== check_error
)
5212 i
.error
= invalid_vector_register_set
;
5215 if (operand_check
!= check_none
)
5216 as_warn (_("index and destination registers should be distinct"));
5221 /* Check if broadcast is supported by the instruction and is applied
5222 to the memory operand. */
5225 i386_operand_type type
, overlap
;
5227 /* Check if specified broadcast is supported in this instruction,
5228 and its broadcast bytes match the memory operand. */
5229 op
= i
.broadcast
->operand
;
5230 if (!t
->opcode_modifier
.broadcast
5231 || !(i
.flags
[op
] & Operand_Mem
)
5232 || (!i
.types
[op
].bitfield
.unspecified
5233 && !match_broadcast_size (t
, op
)))
5236 i
.error
= unsupported_broadcast
;
5240 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5241 * i
.broadcast
->type
);
5242 operand_type_set (&type
, 0);
5243 switch (i
.broadcast
->bytes
)
5246 type
.bitfield
.word
= 1;
5249 type
.bitfield
.dword
= 1;
5252 type
.bitfield
.qword
= 1;
5255 type
.bitfield
.xmmword
= 1;
5258 type
.bitfield
.ymmword
= 1;
5261 type
.bitfield
.zmmword
= 1;
5267 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5268 if (operand_type_all_zero (&overlap
))
5271 if (t
->opcode_modifier
.checkregsize
)
5275 type
.bitfield
.baseindex
= 1;
5276 for (j
= 0; j
< i
.operands
; ++j
)
5279 && !operand_type_register_match(i
.types
[j
],
5280 t
->operand_types
[j
],
5282 t
->operand_types
[op
]))
5287 /* If broadcast is supported in this instruction, we need to check if
5288 operand of one-element size isn't specified without broadcast. */
5289 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5291 /* Find memory operand. */
5292 for (op
= 0; op
< i
.operands
; op
++)
5293 if (operand_type_check (i
.types
[op
], anymem
))
5295 gas_assert (op
< i
.operands
);
5296 /* Check size of the memory operand. */
5297 if (match_broadcast_size (t
, op
))
5299 i
.error
= broadcast_needed
;
5304 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5306 /* Check if requested masking is supported. */
5309 switch (t
->opcode_modifier
.masking
)
5313 case MERGING_MASKING
:
5314 if (i
.mask
->zeroing
)
5317 i
.error
= unsupported_masking
;
5321 case DYNAMIC_MASKING
:
5322 /* Memory destinations allow only merging masking. */
5323 if (i
.mask
->zeroing
&& i
.mem_operands
)
5325 /* Find memory operand. */
5326 for (op
= 0; op
< i
.operands
; op
++)
5327 if (i
.flags
[op
] & Operand_Mem
)
5329 gas_assert (op
< i
.operands
);
5330 if (op
== i
.operands
- 1)
5332 i
.error
= unsupported_masking
;
5342 /* Check if masking is applied to dest operand. */
5343 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5345 i
.error
= mask_not_on_destination
;
5352 if ((i
.rounding
->type
!= saeonly
5353 && !t
->opcode_modifier
.staticrounding
)
5354 || (i
.rounding
->type
== saeonly
5355 && (t
->opcode_modifier
.staticrounding
5356 || !t
->opcode_modifier
.sae
)))
5358 i
.error
= unsupported_rc_sae
;
5361 /* If the instruction has several immediate operands and one of
5362 them is rounding, the rounding operand should be the last
5363 immediate operand. */
5364 if (i
.imm_operands
> 1
5365 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5367 i
.error
= rc_sae_operand_not_last_imm
;
5372 /* Check vector Disp8 operand. */
5373 if (t
->opcode_modifier
.disp8memshift
5374 && i
.disp_encoding
!= disp_encoding_32bit
)
5377 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5378 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5379 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5382 const i386_operand_type
*type
= NULL
;
5385 for (op
= 0; op
< i
.operands
; op
++)
5386 if (operand_type_check (i
.types
[op
], anymem
))
5388 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5389 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5390 else if (t
->operand_types
[op
].bitfield
.xmmword
5391 + t
->operand_types
[op
].bitfield
.ymmword
5392 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5393 type
= &t
->operand_types
[op
];
5394 else if (!i
.types
[op
].bitfield
.unspecified
)
5395 type
= &i
.types
[op
];
5397 else if (i
.types
[op
].bitfield
.regsimd
5398 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5400 if (i
.types
[op
].bitfield
.zmmword
)
5402 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5404 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5410 if (type
->bitfield
.zmmword
)
5412 else if (type
->bitfield
.ymmword
)
5414 else if (type
->bitfield
.xmmword
)
5418 /* For the check in fits_in_disp8(). */
5419 if (i
.memshift
== 0)
5423 for (op
= 0; op
< i
.operands
; op
++)
5424 if (operand_type_check (i
.types
[op
], disp
)
5425 && i
.op
[op
].disps
->X_op
== O_constant
)
5427 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5429 i
.types
[op
].bitfield
.disp8
= 1;
5432 i
.types
[op
].bitfield
.disp8
= 0;
5441 /* Check if operands are valid for the instruction. Update VEX
5445 VEX_check_operands (const insn_template
*t
)
5447 if (i
.vec_encoding
== vex_encoding_evex
)
5449 /* This instruction must be encoded with EVEX prefix. */
5450 if (!is_evex_encoding (t
))
5452 i
.error
= unsupported
;
5458 if (!t
->opcode_modifier
.vex
)
5460 /* This instruction template doesn't have VEX prefix. */
5461 if (i
.vec_encoding
!= vex_encoding_default
)
5463 i
.error
= unsupported
;
5469 /* Only check VEX_Imm4, which must be the first operand. */
5470 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5472 if (i
.op
[0].imms
->X_op
!= O_constant
5473 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5479 /* Turn off Imm8 so that update_imm won't complain. */
5480 i
.types
[0] = vec_imm4
;
5486 static const insn_template
*
5487 match_template (char mnem_suffix
)
5489 /* Points to template once we've found it. */
5490 const insn_template
*t
;
5491 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5492 i386_operand_type overlap4
;
5493 unsigned int found_reverse_match
;
5494 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5495 i386_operand_type operand_types
[MAX_OPERANDS
];
5496 int addr_prefix_disp
;
5498 unsigned int found_cpu_match
, size_match
;
5499 unsigned int check_register
;
5500 enum i386_error specific_error
= 0;
5502 #if MAX_OPERANDS != 5
5503 # error "MAX_OPERANDS must be 5."
5506 found_reverse_match
= 0;
5507 addr_prefix_disp
= -1;
5509 memset (&suffix_check
, 0, sizeof (suffix_check
));
5510 if (intel_syntax
&& i
.broadcast
)
5512 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5513 suffix_check
.no_bsuf
= 1;
5514 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5515 suffix_check
.no_wsuf
= 1;
5516 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5517 suffix_check
.no_ssuf
= 1;
5518 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5519 suffix_check
.no_lsuf
= 1;
5520 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5521 suffix_check
.no_qsuf
= 1;
5522 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5523 suffix_check
.no_ldsuf
= 1;
5525 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5528 switch (mnem_suffix
)
5530 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5531 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5532 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5533 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5534 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5538 /* Must have right number of operands. */
5539 i
.error
= number_of_operands_mismatch
;
5541 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5543 addr_prefix_disp
= -1;
5544 found_reverse_match
= 0;
5546 if (i
.operands
!= t
->operands
)
5549 /* Check processor support. */
5550 i
.error
= unsupported
;
5551 found_cpu_match
= (cpu_flags_match (t
)
5552 == CPU_FLAGS_PERFECT_MATCH
);
5553 if (!found_cpu_match
)
5556 /* Check AT&T mnemonic. */
5557 i
.error
= unsupported_with_intel_mnemonic
;
5558 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5561 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5562 i
.error
= unsupported_syntax
;
5563 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5564 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5565 || (intel64
&& t
->opcode_modifier
.amd64
)
5566 || (!intel64
&& t
->opcode_modifier
.intel64
))
5569 /* Check the suffix, except for some instructions in intel mode. */
5570 i
.error
= invalid_instruction_suffix
;
5571 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5572 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5573 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5574 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5575 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5576 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5577 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5579 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5580 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5581 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5582 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5583 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5584 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5585 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5588 size_match
= operand_size_match (t
);
5592 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5593 operand_types
[j
] = t
->operand_types
[j
];
5595 /* In general, don't allow 64-bit operands in 32-bit mode. */
5596 if (i
.suffix
== QWORD_MNEM_SUFFIX
5597 && flag_code
!= CODE_64BIT
5599 ? (!t
->opcode_modifier
.ignoresize
5600 && !t
->opcode_modifier
.broadcast
5601 && !intel_float_operand (t
->name
))
5602 : intel_float_operand (t
->name
) != 2)
5603 && ((!operand_types
[0].bitfield
.regmmx
5604 && !operand_types
[0].bitfield
.regsimd
)
5605 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5606 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5607 && (t
->base_opcode
!= 0x0fc7
5608 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5611 /* In general, don't allow 32-bit operands on pre-386. */
5612 else if (i
.suffix
== LONG_MNEM_SUFFIX
5613 && !cpu_arch_flags
.bitfield
.cpui386
5615 ? (!t
->opcode_modifier
.ignoresize
5616 && !intel_float_operand (t
->name
))
5617 : intel_float_operand (t
->name
) != 2)
5618 && ((!operand_types
[0].bitfield
.regmmx
5619 && !operand_types
[0].bitfield
.regsimd
)
5620 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5621 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5624 /* Do not verify operands when there are none. */
5628 /* We've found a match; break out of loop. */
5632 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5633 into Disp32/Disp16/Disp32 operand. */
5634 if (i
.prefix
[ADDR_PREFIX
] != 0)
5636 /* There should be only one Disp operand. */
5640 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5642 if (operand_types
[j
].bitfield
.disp16
)
5644 addr_prefix_disp
= j
;
5645 operand_types
[j
].bitfield
.disp32
= 1;
5646 operand_types
[j
].bitfield
.disp16
= 0;
5652 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5654 if (operand_types
[j
].bitfield
.disp32
)
5656 addr_prefix_disp
= j
;
5657 operand_types
[j
].bitfield
.disp32
= 0;
5658 operand_types
[j
].bitfield
.disp16
= 1;
5664 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5666 if (operand_types
[j
].bitfield
.disp64
)
5668 addr_prefix_disp
= j
;
5669 operand_types
[j
].bitfield
.disp64
= 0;
5670 operand_types
[j
].bitfield
.disp32
= 1;
5678 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5679 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5682 /* We check register size if needed. */
5683 if (t
->opcode_modifier
.checkregsize
)
5685 check_register
= (1 << t
->operands
) - 1;
5687 check_register
&= ~(1 << i
.broadcast
->operand
);
5692 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5693 switch (t
->operands
)
5696 if (!operand_type_match (overlap0
, i
.types
[0]))
5700 /* xchg %eax, %eax is a special case. It is an alias for nop
5701 only in 32bit mode and we can use opcode 0x90. In 64bit
5702 mode, we can't use 0x90 for xchg %eax, %eax since it should
5703 zero-extend %eax to %rax. */
5704 if (flag_code
== CODE_64BIT
5705 && t
->base_opcode
== 0x90
5706 && operand_type_equal (&i
.types
[0], &acc32
)
5707 && operand_type_equal (&i
.types
[1], &acc32
))
5709 /* xrelease mov %eax, <disp> is another special case. It must not
5710 match the accumulator-only encoding of mov. */
5711 if (flag_code
!= CODE_64BIT
5713 && t
->base_opcode
== 0xa0
5714 && i
.types
[0].bitfield
.acc
5715 && operand_type_check (i
.types
[1], anymem
))
5720 if (!(size_match
& MATCH_STRAIGHT
))
5722 /* Reverse direction of operands if swapping is possible in the first
5723 place (operands need to be symmetric) and
5724 - the load form is requested, and the template is a store form,
5725 - the store form is requested, and the template is a load form,
5726 - the non-default (swapped) form is requested. */
5727 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5728 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5729 && !operand_type_all_zero (&overlap1
))
5730 switch (i
.dir_encoding
)
5732 case dir_encoding_load
:
5733 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5734 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5738 case dir_encoding_store
:
5739 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5740 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5744 case dir_encoding_swap
:
5747 case dir_encoding_default
:
5750 /* If we want store form, we skip the current load. */
5751 if ((i
.dir_encoding
== dir_encoding_store
5752 || i
.dir_encoding
== dir_encoding_swap
)
5753 && i
.mem_operands
== 0
5754 && t
->opcode_modifier
.load
)
5759 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5760 if (!operand_type_match (overlap0
, i
.types
[0])
5761 || !operand_type_match (overlap1
, i
.types
[1])
5762 || ((check_register
& 3) == 3
5763 && !operand_type_register_match (i
.types
[0],
5768 /* Check if other direction is valid ... */
5769 if (!t
->opcode_modifier
.d
)
5773 if (!(size_match
& MATCH_REVERSE
))
5775 /* Try reversing direction of operands. */
5776 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5777 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5778 if (!operand_type_match (overlap0
, i
.types
[0])
5779 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5781 && !operand_type_register_match (i
.types
[0],
5782 operand_types
[i
.operands
- 1],
5783 i
.types
[i
.operands
- 1],
5786 /* Does not match either direction. */
5789 /* found_reverse_match holds which of D or FloatR
5791 if (!t
->opcode_modifier
.d
)
5792 found_reverse_match
= 0;
5793 else if (operand_types
[0].bitfield
.tbyte
)
5794 found_reverse_match
= Opcode_FloatD
;
5795 else if (operand_types
[0].bitfield
.xmmword
5796 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5797 || operand_types
[0].bitfield
.regmmx
5798 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5799 || is_any_vex_encoding(t
))
5800 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5801 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5803 found_reverse_match
= Opcode_D
;
5804 if (t
->opcode_modifier
.floatr
)
5805 found_reverse_match
|= Opcode_FloatR
;
5809 /* Found a forward 2 operand match here. */
5810 switch (t
->operands
)
5813 overlap4
= operand_type_and (i
.types
[4],
5817 overlap3
= operand_type_and (i
.types
[3],
5821 overlap2
= operand_type_and (i
.types
[2],
5826 switch (t
->operands
)
5829 if (!operand_type_match (overlap4
, i
.types
[4])
5830 || !operand_type_register_match (i
.types
[3],
5837 if (!operand_type_match (overlap3
, i
.types
[3])
5838 || ((check_register
& 0xa) == 0xa
5839 && !operand_type_register_match (i
.types
[1],
5843 || ((check_register
& 0xc) == 0xc
5844 && !operand_type_register_match (i
.types
[2],
5851 /* Here we make use of the fact that there are no
5852 reverse match 3 operand instructions. */
5853 if (!operand_type_match (overlap2
, i
.types
[2])
5854 || ((check_register
& 5) == 5
5855 && !operand_type_register_match (i
.types
[0],
5859 || ((check_register
& 6) == 6
5860 && !operand_type_register_match (i
.types
[1],
5868 /* Found either forward/reverse 2, 3 or 4 operand match here:
5869 slip through to break. */
5871 if (!found_cpu_match
)
5874 /* Check if vector and VEX operands are valid. */
5875 if (check_VecOperands (t
) || VEX_check_operands (t
))
5877 specific_error
= i
.error
;
5881 /* We've found a match; break out of loop. */
5885 if (t
== current_templates
->end
)
5887 /* We found no match. */
5888 const char *err_msg
;
5889 switch (specific_error
? specific_error
: i
.error
)
5893 case operand_size_mismatch
:
5894 err_msg
= _("operand size mismatch");
5896 case operand_type_mismatch
:
5897 err_msg
= _("operand type mismatch");
5899 case register_type_mismatch
:
5900 err_msg
= _("register type mismatch");
5902 case number_of_operands_mismatch
:
5903 err_msg
= _("number of operands mismatch");
5905 case invalid_instruction_suffix
:
5906 err_msg
= _("invalid instruction suffix");
5909 err_msg
= _("constant doesn't fit in 4 bits");
5911 case unsupported_with_intel_mnemonic
:
5912 err_msg
= _("unsupported with Intel mnemonic");
5914 case unsupported_syntax
:
5915 err_msg
= _("unsupported syntax");
5918 as_bad (_("unsupported instruction `%s'"),
5919 current_templates
->start
->name
);
5921 case invalid_vsib_address
:
5922 err_msg
= _("invalid VSIB address");
5924 case invalid_vector_register_set
:
5925 err_msg
= _("mask, index, and destination registers must be distinct");
5927 case unsupported_vector_index_register
:
5928 err_msg
= _("unsupported vector index register");
5930 case unsupported_broadcast
:
5931 err_msg
= _("unsupported broadcast");
5933 case broadcast_needed
:
5934 err_msg
= _("broadcast is needed for operand of such type");
5936 case unsupported_masking
:
5937 err_msg
= _("unsupported masking");
5939 case mask_not_on_destination
:
5940 err_msg
= _("mask not on destination operand");
5942 case no_default_mask
:
5943 err_msg
= _("default mask isn't allowed");
5945 case unsupported_rc_sae
:
5946 err_msg
= _("unsupported static rounding/sae");
5948 case rc_sae_operand_not_last_imm
:
5950 err_msg
= _("RC/SAE operand must precede immediate operands");
5952 err_msg
= _("RC/SAE operand must follow immediate operands");
5954 case invalid_register_operand
:
5955 err_msg
= _("invalid register operand");
5958 as_bad (_("%s for `%s'"), err_msg
,
5959 current_templates
->start
->name
);
5963 if (!quiet_warnings
)
5966 && (i
.types
[0].bitfield
.jumpabsolute
5967 != operand_types
[0].bitfield
.jumpabsolute
))
5969 as_warn (_("indirect %s without `*'"), t
->name
);
5972 if (t
->opcode_modifier
.isprefix
5973 && t
->opcode_modifier
.ignoresize
)
5975 /* Warn them that a data or address size prefix doesn't
5976 affect assembly of the next line of code. */
5977 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5981 /* Copy the template we found. */
5984 if (addr_prefix_disp
!= -1)
5985 i
.tm
.operand_types
[addr_prefix_disp
]
5986 = operand_types
[addr_prefix_disp
];
5988 if (found_reverse_match
)
5990 /* If we found a reverse match we must alter the opcode
5991 direction bit. found_reverse_match holds bits to change
5992 (different for int & float insns). */
5994 i
.tm
.base_opcode
^= found_reverse_match
;
5996 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
5997 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6006 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6007 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6009 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6011 as_bad (_("`%s' operand %d must use `%ses' segment"),
6017 /* There's only ever one segment override allowed per instruction.
6018 This instruction possibly has a legal segment override on the
6019 second operand, so copy the segment to where non-string
6020 instructions store it, allowing common code. */
6021 i
.seg
[0] = i
.seg
[1];
6023 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6025 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6027 as_bad (_("`%s' operand %d must use `%ses' segment"),
6038 process_suffix (void)
6040 /* If matched instruction specifies an explicit instruction mnemonic
6042 if (i
.tm
.opcode_modifier
.size16
)
6043 i
.suffix
= WORD_MNEM_SUFFIX
;
6044 else if (i
.tm
.opcode_modifier
.size32
)
6045 i
.suffix
= LONG_MNEM_SUFFIX
;
6046 else if (i
.tm
.opcode_modifier
.size64
)
6047 i
.suffix
= QWORD_MNEM_SUFFIX
;
6048 else if (i
.reg_operands
)
6050 /* If there's no instruction mnemonic suffix we try to invent one
6051 based on register operands. */
6054 /* We take i.suffix from the last register operand specified,
6055 Destination register type is more significant than source
6056 register type. crc32 in SSE4.2 prefers source register
6058 if (i
.tm
.base_opcode
== 0xf20f38f1)
6060 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
6061 i
.suffix
= WORD_MNEM_SUFFIX
;
6062 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
6063 i
.suffix
= LONG_MNEM_SUFFIX
;
6064 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
6065 i
.suffix
= QWORD_MNEM_SUFFIX
;
6067 else if (i
.tm
.base_opcode
== 0xf20f38f0)
6069 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
6070 i
.suffix
= BYTE_MNEM_SUFFIX
;
6077 if (i
.tm
.base_opcode
== 0xf20f38f1
6078 || i
.tm
.base_opcode
== 0xf20f38f0)
6080 /* We have to know the operand size for crc32. */
6081 as_bad (_("ambiguous memory operand size for `%s`"),
6086 for (op
= i
.operands
; --op
>= 0;)
6087 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6088 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6090 if (!i
.types
[op
].bitfield
.reg
)
6092 if (i
.types
[op
].bitfield
.byte
)
6093 i
.suffix
= BYTE_MNEM_SUFFIX
;
6094 else if (i
.types
[op
].bitfield
.word
)
6095 i
.suffix
= WORD_MNEM_SUFFIX
;
6096 else if (i
.types
[op
].bitfield
.dword
)
6097 i
.suffix
= LONG_MNEM_SUFFIX
;
6098 else if (i
.types
[op
].bitfield
.qword
)
6099 i
.suffix
= QWORD_MNEM_SUFFIX
;
6106 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6109 && i
.tm
.opcode_modifier
.ignoresize
6110 && i
.tm
.opcode_modifier
.no_bsuf
)
6112 else if (!check_byte_reg ())
6115 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6118 && i
.tm
.opcode_modifier
.ignoresize
6119 && i
.tm
.opcode_modifier
.no_lsuf
6120 && !i
.tm
.opcode_modifier
.todword
6121 && !i
.tm
.opcode_modifier
.toqword
)
6123 else if (!check_long_reg ())
6126 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6129 && i
.tm
.opcode_modifier
.ignoresize
6130 && i
.tm
.opcode_modifier
.no_qsuf
6131 && !i
.tm
.opcode_modifier
.todword
6132 && !i
.tm
.opcode_modifier
.toqword
)
6134 else if (!check_qword_reg ())
6137 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6140 && i
.tm
.opcode_modifier
.ignoresize
6141 && i
.tm
.opcode_modifier
.no_wsuf
)
6143 else if (!check_word_reg ())
6146 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6147 /* Do nothing if the instruction is going to ignore the prefix. */
6152 else if (i
.tm
.opcode_modifier
.defaultsize
6154 /* exclude fldenv/frstor/fsave/fstenv */
6155 && i
.tm
.opcode_modifier
.no_ssuf
)
6157 i
.suffix
= stackop_size
;
6159 else if (intel_syntax
6161 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6162 || i
.tm
.opcode_modifier
.jumpbyte
6163 || i
.tm
.opcode_modifier
.jumpintersegment
6164 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6165 && i
.tm
.extension_opcode
<= 3)))
6170 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6172 i
.suffix
= QWORD_MNEM_SUFFIX
;
6177 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6178 i
.suffix
= LONG_MNEM_SUFFIX
;
6181 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6182 i
.suffix
= WORD_MNEM_SUFFIX
;
6191 if (i
.tm
.opcode_modifier
.w
)
6193 as_bad (_("no instruction mnemonic suffix given and "
6194 "no register operands; can't size instruction"));
6200 unsigned int suffixes
;
6202 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6203 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6205 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6207 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6209 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6211 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6214 /* There are more than suffix matches. */
6215 if (i
.tm
.opcode_modifier
.w
6216 || ((suffixes
& (suffixes
- 1))
6217 && !i
.tm
.opcode_modifier
.defaultsize
6218 && !i
.tm
.opcode_modifier
.ignoresize
))
6220 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6226 /* Change the opcode based on the operand size given by i.suffix. */
6229 /* Size floating point instruction. */
6230 case LONG_MNEM_SUFFIX
:
6231 if (i
.tm
.opcode_modifier
.floatmf
)
6233 i
.tm
.base_opcode
^= 4;
6237 case WORD_MNEM_SUFFIX
:
6238 case QWORD_MNEM_SUFFIX
:
6239 /* It's not a byte, select word/dword operation. */
6240 if (i
.tm
.opcode_modifier
.w
)
6242 if (i
.tm
.opcode_modifier
.shortform
)
6243 i
.tm
.base_opcode
|= 8;
6245 i
.tm
.base_opcode
|= 1;
6248 case SHORT_MNEM_SUFFIX
:
6249 /* Now select between word & dword operations via the operand
6250 size prefix, except for instructions that will ignore this
6252 if (i
.reg_operands
> 0
6253 && i
.types
[0].bitfield
.reg
6254 && i
.tm
.opcode_modifier
.addrprefixopreg
6255 && (i
.tm
.opcode_modifier
.immext
6256 || i
.operands
== 1))
6258 /* The address size override prefix changes the size of the
6260 if ((flag_code
== CODE_32BIT
6261 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6262 || (flag_code
!= CODE_32BIT
6263 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6264 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6267 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6268 && !i
.tm
.opcode_modifier
.ignoresize
6269 && !i
.tm
.opcode_modifier
.floatmf
6270 && !i
.tm
.opcode_modifier
.vex
6271 && !i
.tm
.opcode_modifier
.vexopcode
6272 && !is_evex_encoding (&i
.tm
)
6273 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6274 || (flag_code
== CODE_64BIT
6275 && i
.tm
.opcode_modifier
.jumpbyte
)))
6277 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6279 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6280 prefix
= ADDR_PREFIX_OPCODE
;
6282 if (!add_prefix (prefix
))
6286 /* Set mode64 for an operand. */
6287 if (i
.suffix
== QWORD_MNEM_SUFFIX
6288 && flag_code
== CODE_64BIT
6289 && !i
.tm
.opcode_modifier
.norex64
6290 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6292 && ! (i
.operands
== 2
6293 && i
.tm
.base_opcode
== 0x90
6294 && i
.tm
.extension_opcode
== None
6295 && operand_type_equal (&i
.types
[0], &acc64
)
6296 && operand_type_equal (&i
.types
[1], &acc64
)))
6302 if (i
.reg_operands
!= 0
6304 && i
.tm
.opcode_modifier
.addrprefixopreg
6305 && !i
.tm
.opcode_modifier
.immext
)
6307 /* Check invalid register operand when the address size override
6308 prefix changes the size of register operands. */
6310 enum { need_word
, need_dword
, need_qword
} need
;
6312 if (flag_code
== CODE_32BIT
)
6313 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6316 if (i
.prefix
[ADDR_PREFIX
])
6319 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6322 for (op
= 0; op
< i
.operands
; op
++)
6323 if (i
.types
[op
].bitfield
.reg
6324 && ((need
== need_word
6325 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6326 || (need
== need_dword
6327 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6328 || (need
== need_qword
6329 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6331 as_bad (_("invalid register operand size for `%s'"),
6341 check_byte_reg (void)
6345 for (op
= i
.operands
; --op
>= 0;)
6347 /* Skip non-register operands. */
6348 if (!i
.types
[op
].bitfield
.reg
)
6351 /* If this is an eight bit register, it's OK. If it's the 16 or
6352 32 bit version of an eight bit register, we will just use the
6353 low portion, and that's OK too. */
6354 if (i
.types
[op
].bitfield
.byte
)
6357 /* I/O port address operands are OK too. */
6358 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6361 /* crc32 doesn't generate this warning. */
6362 if (i
.tm
.base_opcode
== 0xf20f38f0)
6365 if ((i
.types
[op
].bitfield
.word
6366 || i
.types
[op
].bitfield
.dword
6367 || i
.types
[op
].bitfield
.qword
)
6368 && i
.op
[op
].regs
->reg_num
< 4
6369 /* Prohibit these changes in 64bit mode, since the lowering
6370 would be more complicated. */
6371 && flag_code
!= CODE_64BIT
)
6373 #if REGISTER_WARNINGS
6374 if (!quiet_warnings
)
6375 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6377 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6378 ? REGNAM_AL
- REGNAM_AX
6379 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6381 i
.op
[op
].regs
->reg_name
,
6386 /* Any other register is bad. */
6387 if (i
.types
[op
].bitfield
.reg
6388 || i
.types
[op
].bitfield
.regmmx
6389 || i
.types
[op
].bitfield
.regsimd
6390 || i
.types
[op
].bitfield
.sreg2
6391 || i
.types
[op
].bitfield
.sreg3
6392 || i
.types
[op
].bitfield
.control
6393 || i
.types
[op
].bitfield
.debug
6394 || i
.types
[op
].bitfield
.test
)
6396 as_bad (_("`%s%s' not allowed with `%s%c'"),
6398 i
.op
[op
].regs
->reg_name
,
6408 check_long_reg (void)
6412 for (op
= i
.operands
; --op
>= 0;)
6413 /* Skip non-register operands. */
6414 if (!i
.types
[op
].bitfield
.reg
)
6416 /* Reject eight bit registers, except where the template requires
6417 them. (eg. movzb) */
6418 else if (i
.types
[op
].bitfield
.byte
6419 && (i
.tm
.operand_types
[op
].bitfield
.reg
6420 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6421 && (i
.tm
.operand_types
[op
].bitfield
.word
6422 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6424 as_bad (_("`%s%s' not allowed with `%s%c'"),
6426 i
.op
[op
].regs
->reg_name
,
6431 /* Warn if the e prefix on a general reg is missing. */
6432 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6433 && i
.types
[op
].bitfield
.word
6434 && (i
.tm
.operand_types
[op
].bitfield
.reg
6435 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6436 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6438 /* Prohibit these changes in the 64bit mode, since the
6439 lowering is more complicated. */
6440 if (flag_code
== CODE_64BIT
)
6442 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6443 register_prefix
, i
.op
[op
].regs
->reg_name
,
6447 #if REGISTER_WARNINGS
6448 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6450 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6451 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6454 /* Warn if the r prefix on a general reg is present. */
6455 else if (i
.types
[op
].bitfield
.qword
6456 && (i
.tm
.operand_types
[op
].bitfield
.reg
6457 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6458 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6461 && i
.tm
.opcode_modifier
.toqword
6462 && !i
.types
[0].bitfield
.regsimd
)
6464 /* Convert to QWORD. We want REX byte. */
6465 i
.suffix
= QWORD_MNEM_SUFFIX
;
6469 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6470 register_prefix
, i
.op
[op
].regs
->reg_name
,
6479 check_qword_reg (void)
6483 for (op
= i
.operands
; --op
>= 0; )
6484 /* Skip non-register operands. */
6485 if (!i
.types
[op
].bitfield
.reg
)
6487 /* Reject eight bit registers, except where the template requires
6488 them. (eg. movzb) */
6489 else if (i
.types
[op
].bitfield
.byte
6490 && (i
.tm
.operand_types
[op
].bitfield
.reg
6491 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6492 && (i
.tm
.operand_types
[op
].bitfield
.word
6493 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6495 as_bad (_("`%s%s' not allowed with `%s%c'"),
6497 i
.op
[op
].regs
->reg_name
,
6502 /* Warn if the r prefix on a general reg is missing. */
6503 else if ((i
.types
[op
].bitfield
.word
6504 || i
.types
[op
].bitfield
.dword
)
6505 && (i
.tm
.operand_types
[op
].bitfield
.reg
6506 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6507 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6509 /* Prohibit these changes in the 64bit mode, since the
6510 lowering is more complicated. */
6512 && i
.tm
.opcode_modifier
.todword
6513 && !i
.types
[0].bitfield
.regsimd
)
6515 /* Convert to DWORD. We don't want REX byte. */
6516 i
.suffix
= LONG_MNEM_SUFFIX
;
6520 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6521 register_prefix
, i
.op
[op
].regs
->reg_name
,
6530 check_word_reg (void)
6533 for (op
= i
.operands
; --op
>= 0;)
6534 /* Skip non-register operands. */
6535 if (!i
.types
[op
].bitfield
.reg
)
6537 /* Reject eight bit registers, except where the template requires
6538 them. (eg. movzb) */
6539 else if (i
.types
[op
].bitfield
.byte
6540 && (i
.tm
.operand_types
[op
].bitfield
.reg
6541 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6542 && (i
.tm
.operand_types
[op
].bitfield
.word
6543 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6545 as_bad (_("`%s%s' not allowed with `%s%c'"),
6547 i
.op
[op
].regs
->reg_name
,
6552 /* Warn if the e or r prefix on a general reg is present. */
6553 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6554 && (i
.types
[op
].bitfield
.dword
6555 || i
.types
[op
].bitfield
.qword
)
6556 && (i
.tm
.operand_types
[op
].bitfield
.reg
6557 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6558 && i
.tm
.operand_types
[op
].bitfield
.word
)
6560 /* Prohibit these changes in the 64bit mode, since the
6561 lowering is more complicated. */
6562 if (flag_code
== CODE_64BIT
)
6564 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6565 register_prefix
, i
.op
[op
].regs
->reg_name
,
6569 #if REGISTER_WARNINGS
6570 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6572 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6573 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6580 update_imm (unsigned int j
)
6582 i386_operand_type overlap
= i
.types
[j
];
6583 if ((overlap
.bitfield
.imm8
6584 || overlap
.bitfield
.imm8s
6585 || overlap
.bitfield
.imm16
6586 || overlap
.bitfield
.imm32
6587 || overlap
.bitfield
.imm32s
6588 || overlap
.bitfield
.imm64
)
6589 && !operand_type_equal (&overlap
, &imm8
)
6590 && !operand_type_equal (&overlap
, &imm8s
)
6591 && !operand_type_equal (&overlap
, &imm16
)
6592 && !operand_type_equal (&overlap
, &imm32
)
6593 && !operand_type_equal (&overlap
, &imm32s
)
6594 && !operand_type_equal (&overlap
, &imm64
))
6598 i386_operand_type temp
;
6600 operand_type_set (&temp
, 0);
6601 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6603 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6604 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6606 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6607 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6608 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6610 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6611 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6614 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6617 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6618 || operand_type_equal (&overlap
, &imm16_32
)
6619 || operand_type_equal (&overlap
, &imm16_32s
))
6621 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6626 if (!operand_type_equal (&overlap
, &imm8
)
6627 && !operand_type_equal (&overlap
, &imm8s
)
6628 && !operand_type_equal (&overlap
, &imm16
)
6629 && !operand_type_equal (&overlap
, &imm32
)
6630 && !operand_type_equal (&overlap
, &imm32s
)
6631 && !operand_type_equal (&overlap
, &imm64
))
6633 as_bad (_("no instruction mnemonic suffix given; "
6634 "can't determine immediate size"));
6638 i
.types
[j
] = overlap
;
6648 /* Update the first 2 immediate operands. */
6649 n
= i
.operands
> 2 ? 2 : i
.operands
;
6652 for (j
= 0; j
< n
; j
++)
6653 if (update_imm (j
) == 0)
6656 /* The 3rd operand can't be immediate operand. */
6657 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6664 process_operands (void)
6666 /* Default segment register this instruction will use for memory
6667 accesses. 0 means unknown. This is only for optimizing out
6668 unnecessary segment overrides. */
6669 const seg_entry
*default_seg
= 0;
6671 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6673 unsigned int dupl
= i
.operands
;
6674 unsigned int dest
= dupl
- 1;
6677 /* The destination must be an xmm register. */
6678 gas_assert (i
.reg_operands
6679 && MAX_OPERANDS
> dupl
6680 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6682 if (i
.tm
.operand_types
[0].bitfield
.acc
6683 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6685 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6687 /* Keep xmm0 for instructions with VEX prefix and 3
6689 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6690 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6695 /* We remove the first xmm0 and keep the number of
6696 operands unchanged, which in fact duplicates the
6698 for (j
= 1; j
< i
.operands
; j
++)
6700 i
.op
[j
- 1] = i
.op
[j
];
6701 i
.types
[j
- 1] = i
.types
[j
];
6702 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6706 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6708 gas_assert ((MAX_OPERANDS
- 1) > dupl
6709 && (i
.tm
.opcode_modifier
.vexsources
6712 /* Add the implicit xmm0 for instructions with VEX prefix
6714 for (j
= i
.operands
; j
> 0; j
--)
6716 i
.op
[j
] = i
.op
[j
- 1];
6717 i
.types
[j
] = i
.types
[j
- 1];
6718 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6721 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6722 i
.types
[0] = regxmm
;
6723 i
.tm
.operand_types
[0] = regxmm
;
6726 i
.reg_operands
+= 2;
6731 i
.op
[dupl
] = i
.op
[dest
];
6732 i
.types
[dupl
] = i
.types
[dest
];
6733 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6742 i
.op
[dupl
] = i
.op
[dest
];
6743 i
.types
[dupl
] = i
.types
[dest
];
6744 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6747 if (i
.tm
.opcode_modifier
.immext
)
6750 else if (i
.tm
.operand_types
[0].bitfield
.acc
6751 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6755 for (j
= 1; j
< i
.operands
; j
++)
6757 i
.op
[j
- 1] = i
.op
[j
];
6758 i
.types
[j
- 1] = i
.types
[j
];
6760 /* We need to adjust fields in i.tm since they are used by
6761 build_modrm_byte. */
6762 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6769 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6771 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6773 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6774 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6775 regnum
= register_number (i
.op
[1].regs
);
6776 first_reg_in_group
= regnum
& ~3;
6777 last_reg_in_group
= first_reg_in_group
+ 3;
6778 if (regnum
!= first_reg_in_group
)
6779 as_warn (_("source register `%s%s' implicitly denotes"
6780 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6781 register_prefix
, i
.op
[1].regs
->reg_name
,
6782 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6783 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6786 else if (i
.tm
.opcode_modifier
.regkludge
)
6788 /* The imul $imm, %reg instruction is converted into
6789 imul $imm, %reg, %reg, and the clr %reg instruction
6790 is converted into xor %reg, %reg. */
6792 unsigned int first_reg_op
;
6794 if (operand_type_check (i
.types
[0], reg
))
6798 /* Pretend we saw the extra register operand. */
6799 gas_assert (i
.reg_operands
== 1
6800 && i
.op
[first_reg_op
+ 1].regs
== 0);
6801 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6802 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6807 if (i
.tm
.opcode_modifier
.shortform
)
6809 if (i
.types
[0].bitfield
.sreg2
6810 || i
.types
[0].bitfield
.sreg3
)
6812 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6813 && i
.op
[0].regs
->reg_num
== 1)
6815 as_bad (_("you can't `pop %scs'"), register_prefix
);
6818 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6819 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6824 /* The register or float register operand is in operand
6828 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6829 || operand_type_check (i
.types
[0], reg
))
6833 /* Register goes in low 3 bits of opcode. */
6834 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6835 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6837 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6839 /* Warn about some common errors, but press on regardless.
6840 The first case can be generated by gcc (<= 2.8.1). */
6841 if (i
.operands
== 2)
6843 /* Reversed arguments on faddp, fsubp, etc. */
6844 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6845 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6846 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6850 /* Extraneous `l' suffix on fp insn. */
6851 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6852 register_prefix
, i
.op
[0].regs
->reg_name
);
6857 else if (i
.tm
.opcode_modifier
.modrm
)
6859 /* The opcode is completed (modulo i.tm.extension_opcode which
6860 must be put into the modrm byte). Now, we make the modrm and
6861 index base bytes based on all the info we've collected. */
6863 default_seg
= build_modrm_byte ();
6865 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6869 else if (i
.tm
.opcode_modifier
.isstring
)
6871 /* For the string instructions that allow a segment override
6872 on one of their operands, the default segment is ds. */
6876 if (i
.tm
.base_opcode
== 0x8d /* lea */
6879 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6881 /* If a segment was explicitly specified, and the specified segment
6882 is not the default, use an opcode prefix to select it. If we
6883 never figured out what the default segment is, then default_seg
6884 will be zero at this point, and the specified segment prefix will
6886 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6888 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6894 static const seg_entry
*
6895 build_modrm_byte (void)
6897 const seg_entry
*default_seg
= 0;
6898 unsigned int source
, dest
;
6901 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6904 unsigned int nds
, reg_slot
;
6907 dest
= i
.operands
- 1;
6910 /* There are 2 kinds of instructions:
6911 1. 5 operands: 4 register operands or 3 register operands
6912 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6913 VexW0 or VexW1. The destination must be either XMM, YMM or
6915 2. 4 operands: 4 register operands or 3 register operands
6916 plus 1 memory operand, with VexXDS. */
6917 gas_assert ((i
.reg_operands
== 4
6918 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6919 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6920 && i
.tm
.opcode_modifier
.vexw
6921 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6923 /* If VexW1 is set, the first non-immediate operand is the source and
6924 the second non-immediate one is encoded in the immediate operand. */
6925 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6927 source
= i
.imm_operands
;
6928 reg_slot
= i
.imm_operands
+ 1;
6932 source
= i
.imm_operands
+ 1;
6933 reg_slot
= i
.imm_operands
;
6936 if (i
.imm_operands
== 0)
6938 /* When there is no immediate operand, generate an 8bit
6939 immediate operand to encode the first operand. */
6940 exp
= &im_expressions
[i
.imm_operands
++];
6941 i
.op
[i
.operands
].imms
= exp
;
6942 i
.types
[i
.operands
] = imm8
;
6945 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6946 exp
->X_op
= O_constant
;
6947 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6948 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6952 unsigned int imm_slot
;
6954 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6956 if (i
.tm
.opcode_modifier
.immext
)
6958 /* When ImmExt is set, the immediate byte is the last
6960 imm_slot
= i
.operands
- 1;
6968 /* Turn on Imm8 so that output_imm will generate it. */
6969 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6972 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6973 i
.op
[imm_slot
].imms
->X_add_number
6974 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6975 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6978 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6979 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6984 /* i.reg_operands MUST be the number of real register operands;
6985 implicit registers do not count. If there are 3 register
6986 operands, it must be a instruction with VexNDS. For a
6987 instruction with VexNDD, the destination register is encoded
6988 in VEX prefix. If there are 4 register operands, it must be
6989 a instruction with VEX prefix and 3 sources. */
6990 if (i
.mem_operands
== 0
6991 && ((i
.reg_operands
== 2
6992 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6993 || (i
.reg_operands
== 3
6994 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6995 || (i
.reg_operands
== 4 && vex_3_sources
)))
7003 /* When there are 3 operands, one of them may be immediate,
7004 which may be the first or the last operand. Otherwise,
7005 the first operand must be shift count register (cl) or it
7006 is an instruction with VexNDS. */
7007 gas_assert (i
.imm_operands
== 1
7008 || (i
.imm_operands
== 0
7009 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7010 || i
.types
[0].bitfield
.shiftcount
)));
7011 if (operand_type_check (i
.types
[0], imm
)
7012 || i
.types
[0].bitfield
.shiftcount
)
7018 /* When there are 4 operands, the first two must be 8bit
7019 immediate operands. The source operand will be the 3rd
7022 For instructions with VexNDS, if the first operand
7023 an imm8, the source operand is the 2nd one. If the last
7024 operand is imm8, the source operand is the first one. */
7025 gas_assert ((i
.imm_operands
== 2
7026 && i
.types
[0].bitfield
.imm8
7027 && i
.types
[1].bitfield
.imm8
)
7028 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7029 && i
.imm_operands
== 1
7030 && (i
.types
[0].bitfield
.imm8
7031 || i
.types
[i
.operands
- 1].bitfield
.imm8
7033 if (i
.imm_operands
== 2)
7037 if (i
.types
[0].bitfield
.imm8
)
7044 if (is_evex_encoding (&i
.tm
))
7046 /* For EVEX instructions, when there are 5 operands, the
7047 first one must be immediate operand. If the second one
7048 is immediate operand, the source operand is the 3th
7049 one. If the last one is immediate operand, the source
7050 operand is the 2nd one. */
7051 gas_assert (i
.imm_operands
== 2
7052 && i
.tm
.opcode_modifier
.sae
7053 && operand_type_check (i
.types
[0], imm
));
7054 if (operand_type_check (i
.types
[1], imm
))
7056 else if (operand_type_check (i
.types
[4], imm
))
7070 /* RC/SAE operand could be between DEST and SRC. That happens
7071 when one operand is GPR and the other one is XMM/YMM/ZMM
7073 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7076 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7078 /* For instructions with VexNDS, the register-only source
7079 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7080 register. It is encoded in VEX prefix. We need to
7081 clear RegMem bit before calling operand_type_equal. */
7083 i386_operand_type op
;
7086 /* Check register-only source operand when two source
7087 operands are swapped. */
7088 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7089 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7097 op
= i
.tm
.operand_types
[vvvv
];
7098 op
.bitfield
.regmem
= 0;
7099 if ((dest
+ 1) >= i
.operands
7100 || ((!op
.bitfield
.reg
7101 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7102 && !op
.bitfield
.regsimd
7103 && !operand_type_equal (&op
, ®mask
)))
7105 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7111 /* One of the register operands will be encoded in the i.tm.reg
7112 field, the other in the combined i.tm.mode and i.tm.regmem
7113 fields. If no form of this instruction supports a memory
7114 destination operand, then we assume the source operand may
7115 sometimes be a memory operand and so we need to store the
7116 destination in the i.rm.reg field. */
7117 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7118 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7120 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7121 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7122 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7123 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7124 i
.has_regmmx
= TRUE
;
7125 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7126 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7128 if (i
.types
[dest
].bitfield
.zmmword
7129 || i
.types
[source
].bitfield
.zmmword
)
7130 i
.has_regzmm
= TRUE
;
7131 else if (i
.types
[dest
].bitfield
.ymmword
7132 || i
.types
[source
].bitfield
.ymmword
)
7133 i
.has_regymm
= TRUE
;
7135 i
.has_regxmm
= TRUE
;
7137 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7139 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7141 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7143 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7148 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7149 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7150 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7152 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7154 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7156 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7159 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7161 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7164 add_prefix (LOCK_PREFIX_OPCODE
);
7168 { /* If it's not 2 reg operands... */
7173 unsigned int fake_zero_displacement
= 0;
7176 for (op
= 0; op
< i
.operands
; op
++)
7177 if (operand_type_check (i
.types
[op
], anymem
))
7179 gas_assert (op
< i
.operands
);
7181 if (i
.tm
.opcode_modifier
.vecsib
)
7183 if (i
.index_reg
->reg_num
== RegIZ
)
7186 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7189 i
.sib
.base
= NO_BASE_REGISTER
;
7190 i
.sib
.scale
= i
.log2_scale_factor
;
7191 i
.types
[op
].bitfield
.disp8
= 0;
7192 i
.types
[op
].bitfield
.disp16
= 0;
7193 i
.types
[op
].bitfield
.disp64
= 0;
7194 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7196 /* Must be 32 bit */
7197 i
.types
[op
].bitfield
.disp32
= 1;
7198 i
.types
[op
].bitfield
.disp32s
= 0;
7202 i
.types
[op
].bitfield
.disp32
= 0;
7203 i
.types
[op
].bitfield
.disp32s
= 1;
7206 i
.sib
.index
= i
.index_reg
->reg_num
;
7207 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7209 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7215 if (i
.base_reg
== 0)
7218 if (!i
.disp_operands
)
7219 fake_zero_displacement
= 1;
7220 if (i
.index_reg
== 0)
7222 i386_operand_type newdisp
;
7224 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7225 /* Operand is just <disp> */
7226 if (flag_code
== CODE_64BIT
)
7228 /* 64bit mode overwrites the 32bit absolute
7229 addressing by RIP relative addressing and
7230 absolute addressing is encoded by one of the
7231 redundant SIB forms. */
7232 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7233 i
.sib
.base
= NO_BASE_REGISTER
;
7234 i
.sib
.index
= NO_INDEX_REGISTER
;
7235 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7237 else if ((flag_code
== CODE_16BIT
)
7238 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7240 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7245 i
.rm
.regmem
= NO_BASE_REGISTER
;
7248 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7249 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7251 else if (!i
.tm
.opcode_modifier
.vecsib
)
7253 /* !i.base_reg && i.index_reg */
7254 if (i
.index_reg
->reg_num
== RegIZ
)
7255 i
.sib
.index
= NO_INDEX_REGISTER
;
7257 i
.sib
.index
= i
.index_reg
->reg_num
;
7258 i
.sib
.base
= NO_BASE_REGISTER
;
7259 i
.sib
.scale
= i
.log2_scale_factor
;
7260 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7261 i
.types
[op
].bitfield
.disp8
= 0;
7262 i
.types
[op
].bitfield
.disp16
= 0;
7263 i
.types
[op
].bitfield
.disp64
= 0;
7264 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7266 /* Must be 32 bit */
7267 i
.types
[op
].bitfield
.disp32
= 1;
7268 i
.types
[op
].bitfield
.disp32s
= 0;
7272 i
.types
[op
].bitfield
.disp32
= 0;
7273 i
.types
[op
].bitfield
.disp32s
= 1;
7275 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7279 /* RIP addressing for 64bit mode. */
7280 else if (i
.base_reg
->reg_num
== RegIP
)
7282 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7283 i
.rm
.regmem
= NO_BASE_REGISTER
;
7284 i
.types
[op
].bitfield
.disp8
= 0;
7285 i
.types
[op
].bitfield
.disp16
= 0;
7286 i
.types
[op
].bitfield
.disp32
= 0;
7287 i
.types
[op
].bitfield
.disp32s
= 1;
7288 i
.types
[op
].bitfield
.disp64
= 0;
7289 i
.flags
[op
] |= Operand_PCrel
;
7290 if (! i
.disp_operands
)
7291 fake_zero_displacement
= 1;
7293 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7295 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7296 switch (i
.base_reg
->reg_num
)
7299 if (i
.index_reg
== 0)
7301 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7302 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7306 if (i
.index_reg
== 0)
7309 if (operand_type_check (i
.types
[op
], disp
) == 0)
7311 /* fake (%bp) into 0(%bp) */
7312 i
.types
[op
].bitfield
.disp8
= 1;
7313 fake_zero_displacement
= 1;
7316 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7317 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7319 default: /* (%si) -> 4 or (%di) -> 5 */
7320 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7322 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7324 else /* i.base_reg and 32/64 bit mode */
7326 if (flag_code
== CODE_64BIT
7327 && operand_type_check (i
.types
[op
], disp
))
7329 i
.types
[op
].bitfield
.disp16
= 0;
7330 i
.types
[op
].bitfield
.disp64
= 0;
7331 if (i
.prefix
[ADDR_PREFIX
] == 0)
7333 i
.types
[op
].bitfield
.disp32
= 0;
7334 i
.types
[op
].bitfield
.disp32s
= 1;
7338 i
.types
[op
].bitfield
.disp32
= 1;
7339 i
.types
[op
].bitfield
.disp32s
= 0;
7343 if (!i
.tm
.opcode_modifier
.vecsib
)
7344 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7345 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7347 i
.sib
.base
= i
.base_reg
->reg_num
;
7348 /* x86-64 ignores REX prefix bit here to avoid decoder
7350 if (!(i
.base_reg
->reg_flags
& RegRex
)
7351 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7352 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7354 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7356 fake_zero_displacement
= 1;
7357 i
.types
[op
].bitfield
.disp8
= 1;
7359 i
.sib
.scale
= i
.log2_scale_factor
;
7360 if (i
.index_reg
== 0)
7362 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7363 /* <disp>(%esp) becomes two byte modrm with no index
7364 register. We've already stored the code for esp
7365 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7366 Any base register besides %esp will not use the
7367 extra modrm byte. */
7368 i
.sib
.index
= NO_INDEX_REGISTER
;
7370 else if (!i
.tm
.opcode_modifier
.vecsib
)
7372 if (i
.index_reg
->reg_num
== RegIZ
)
7373 i
.sib
.index
= NO_INDEX_REGISTER
;
7375 i
.sib
.index
= i
.index_reg
->reg_num
;
7376 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7377 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7382 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7383 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7387 if (!fake_zero_displacement
7391 fake_zero_displacement
= 1;
7392 if (i
.disp_encoding
== disp_encoding_8bit
)
7393 i
.types
[op
].bitfield
.disp8
= 1;
7395 i
.types
[op
].bitfield
.disp32
= 1;
7397 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7401 if (fake_zero_displacement
)
7403 /* Fakes a zero displacement assuming that i.types[op]
7404 holds the correct displacement size. */
7407 gas_assert (i
.op
[op
].disps
== 0);
7408 exp
= &disp_expressions
[i
.disp_operands
++];
7409 i
.op
[op
].disps
= exp
;
7410 exp
->X_op
= O_constant
;
7411 exp
->X_add_number
= 0;
7412 exp
->X_add_symbol
= (symbolS
*) 0;
7413 exp
->X_op_symbol
= (symbolS
*) 0;
7421 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7423 if (operand_type_check (i
.types
[0], imm
))
7424 i
.vex
.register_specifier
= NULL
;
7427 /* VEX.vvvv encodes one of the sources when the first
7428 operand is not an immediate. */
7429 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7430 i
.vex
.register_specifier
= i
.op
[0].regs
;
7432 i
.vex
.register_specifier
= i
.op
[1].regs
;
7435 /* Destination is a XMM register encoded in the ModRM.reg
7437 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7438 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7441 /* ModRM.rm and VEX.B encodes the other source. */
7442 if (!i
.mem_operands
)
7446 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7447 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7449 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7451 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7455 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7457 i
.vex
.register_specifier
= i
.op
[2].regs
;
7458 if (!i
.mem_operands
)
7461 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7462 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7466 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7467 (if any) based on i.tm.extension_opcode. Again, we must be
7468 careful to make sure that segment/control/debug/test/MMX
7469 registers are coded into the i.rm.reg field. */
7470 else if (i
.reg_operands
)
7473 unsigned int vex_reg
= ~0;
7475 for (op
= 0; op
< i
.operands
; op
++)
7477 if (i
.types
[op
].bitfield
.reg
7478 || i
.types
[op
].bitfield
.regbnd
7479 || i
.types
[op
].bitfield
.regmask
7480 || i
.types
[op
].bitfield
.sreg2
7481 || i
.types
[op
].bitfield
.sreg3
7482 || i
.types
[op
].bitfield
.control
7483 || i
.types
[op
].bitfield
.debug
7484 || i
.types
[op
].bitfield
.test
)
7486 if (i
.types
[op
].bitfield
.regsimd
)
7488 if (i
.types
[op
].bitfield
.zmmword
)
7489 i
.has_regzmm
= TRUE
;
7490 else if (i
.types
[op
].bitfield
.ymmword
)
7491 i
.has_regymm
= TRUE
;
7493 i
.has_regxmm
= TRUE
;
7496 if (i
.types
[op
].bitfield
.regmmx
)
7498 i
.has_regmmx
= TRUE
;
7505 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7507 /* For instructions with VexNDS, the register-only
7508 source operand is encoded in VEX prefix. */
7509 gas_assert (mem
!= (unsigned int) ~0);
7514 gas_assert (op
< i
.operands
);
7518 /* Check register-only source operand when two source
7519 operands are swapped. */
7520 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7521 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7525 gas_assert (mem
== (vex_reg
+ 1)
7526 && op
< i
.operands
);
7531 gas_assert (vex_reg
< i
.operands
);
7535 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7537 /* For instructions with VexNDD, the register destination
7538 is encoded in VEX prefix. */
7539 if (i
.mem_operands
== 0)
7541 /* There is no memory operand. */
7542 gas_assert ((op
+ 2) == i
.operands
);
7547 /* There are only 2 non-immediate operands. */
7548 gas_assert (op
< i
.imm_operands
+ 2
7549 && i
.operands
== i
.imm_operands
+ 2);
7550 vex_reg
= i
.imm_operands
+ 1;
7554 gas_assert (op
< i
.operands
);
7556 if (vex_reg
!= (unsigned int) ~0)
7558 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7560 if ((!type
->bitfield
.reg
7561 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7562 && !type
->bitfield
.regsimd
7563 && !operand_type_equal (type
, ®mask
))
7566 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7569 /* Don't set OP operand twice. */
7572 /* If there is an extension opcode to put here, the
7573 register number must be put into the regmem field. */
7574 if (i
.tm
.extension_opcode
!= None
)
7576 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7577 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7579 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7584 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7585 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7587 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7592 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7593 must set it to 3 to indicate this is a register operand
7594 in the regmem field. */
7595 if (!i
.mem_operands
)
7599 /* Fill in i.rm.reg field with extension opcode (if any). */
7600 if (i
.tm
.extension_opcode
!= None
)
7601 i
.rm
.reg
= i
.tm
.extension_opcode
;
7607 output_branch (void)
7613 relax_substateT subtype
;
7617 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7618 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7621 if (i
.prefix
[DATA_PREFIX
] != 0)
7627 /* Pentium4 branch hints. */
7628 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7629 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7634 if (i
.prefix
[REX_PREFIX
] != 0)
7640 /* BND prefixed jump. */
7641 if (i
.prefix
[BND_PREFIX
] != 0)
7643 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7647 if (i
.prefixes
!= 0 && !intel_syntax
)
7648 as_warn (_("skipping prefixes on this instruction"));
7650 /* It's always a symbol; End frag & setup for relax.
7651 Make sure there is enough room in this frag for the largest
7652 instruction we may generate in md_convert_frag. This is 2
7653 bytes for the opcode and room for the prefix and largest
7655 frag_grow (prefix
+ 2 + 4);
7656 /* Prefix and 1 opcode byte go in fr_fix. */
7657 p
= frag_more (prefix
+ 1);
7658 if (i
.prefix
[DATA_PREFIX
] != 0)
7659 *p
++ = DATA_PREFIX_OPCODE
;
7660 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7661 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7662 *p
++ = i
.prefix
[SEG_PREFIX
];
7663 if (i
.prefix
[REX_PREFIX
] != 0)
7664 *p
++ = i
.prefix
[REX_PREFIX
];
7665 *p
= i
.tm
.base_opcode
;
7667 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7668 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7669 else if (cpu_arch_flags
.bitfield
.cpui386
)
7670 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7672 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7675 sym
= i
.op
[0].disps
->X_add_symbol
;
7676 off
= i
.op
[0].disps
->X_add_number
;
7678 if (i
.op
[0].disps
->X_op
!= O_constant
7679 && i
.op
[0].disps
->X_op
!= O_symbol
)
7681 /* Handle complex expressions. */
7682 sym
= make_expr_symbol (i
.op
[0].disps
);
7686 /* 1 possible extra opcode + 4 byte displacement go in var part.
7687 Pass reloc in fr_var. */
7688 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7691 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7692 /* Return TRUE iff PLT32 relocation should be used for branching to
7696 need_plt32_p (symbolS
*s
)
7698 /* PLT32 relocation is ELF only. */
7702 /* Since there is no need to prepare for PLT branch on x86-64, we
7703 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7704 be used as a marker for 32-bit PC-relative branches. */
7708 /* Weak or undefined symbol need PLT32 relocation. */
7709 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7712 /* Non-global symbol doesn't need PLT32 relocation. */
7713 if (! S_IS_EXTERNAL (s
))
7716 /* Other global symbols need PLT32 relocation. NB: Symbol with
7717 non-default visibilities are treated as normal global symbol
7718 so that PLT32 relocation can be used as a marker for 32-bit
7719 PC-relative branches. It is useful for linker relaxation. */
7730 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7732 if (i
.tm
.opcode_modifier
.jumpbyte
)
7734 /* This is a loop or jecxz type instruction. */
7736 if (i
.prefix
[ADDR_PREFIX
] != 0)
7738 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7741 /* Pentium4 branch hints. */
7742 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7743 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7745 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7754 if (flag_code
== CODE_16BIT
)
7757 if (i
.prefix
[DATA_PREFIX
] != 0)
7759 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7769 if (i
.prefix
[REX_PREFIX
] != 0)
7771 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7775 /* BND prefixed jump. */
7776 if (i
.prefix
[BND_PREFIX
] != 0)
7778 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7782 if (i
.prefixes
!= 0 && !intel_syntax
)
7783 as_warn (_("skipping prefixes on this instruction"));
7785 p
= frag_more (i
.tm
.opcode_length
+ size
);
7786 switch (i
.tm
.opcode_length
)
7789 *p
++ = i
.tm
.base_opcode
>> 8;
7792 *p
++ = i
.tm
.base_opcode
;
7798 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7800 && jump_reloc
== NO_RELOC
7801 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7802 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7805 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7807 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7808 i
.op
[0].disps
, 1, jump_reloc
);
7810 /* All jumps handled here are signed, but don't use a signed limit
7811 check for 32 and 16 bit jumps as we want to allow wrap around at
7812 4G and 64k respectively. */
7814 fixP
->fx_signed
= 1;
7818 output_interseg_jump (void)
7826 if (flag_code
== CODE_16BIT
)
7830 if (i
.prefix
[DATA_PREFIX
] != 0)
7836 if (i
.prefix
[REX_PREFIX
] != 0)
7846 if (i
.prefixes
!= 0 && !intel_syntax
)
7847 as_warn (_("skipping prefixes on this instruction"));
7849 /* 1 opcode; 2 segment; offset */
7850 p
= frag_more (prefix
+ 1 + 2 + size
);
7852 if (i
.prefix
[DATA_PREFIX
] != 0)
7853 *p
++ = DATA_PREFIX_OPCODE
;
7855 if (i
.prefix
[REX_PREFIX
] != 0)
7856 *p
++ = i
.prefix
[REX_PREFIX
];
7858 *p
++ = i
.tm
.base_opcode
;
7859 if (i
.op
[1].imms
->X_op
== O_constant
)
7861 offsetT n
= i
.op
[1].imms
->X_add_number
;
7864 && !fits_in_unsigned_word (n
)
7865 && !fits_in_signed_word (n
))
7867 as_bad (_("16-bit jump out of range"));
7870 md_number_to_chars (p
, n
, size
);
7873 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7874 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7875 if (i
.op
[0].imms
->X_op
!= O_constant
)
7876 as_bad (_("can't handle non absolute segment in `%s'"),
7878 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7881 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7886 asection
*seg
= now_seg
;
7887 subsegT subseg
= now_subseg
;
7889 unsigned int alignment
, align_size_1
;
7890 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
7891 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
7892 unsigned int padding
;
7894 if (!IS_ELF
|| !x86_used_note
)
7897 x86_isa_1_used
|= GNU_PROPERTY_X86_UINT32_VALID
;
7898 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
7900 /* The .note.gnu.property section layout:
7902 Field Length Contents
7905 n_descsz 4 The note descriptor size
7906 n_type 4 NT_GNU_PROPERTY_TYPE_0
7908 n_desc n_descsz The program property array
7912 /* Create the .note.gnu.property section. */
7913 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
7914 bfd_set_section_flags (stdoutput
, sec
,
7921 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
7932 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
7933 elf_section_type (sec
) = SHT_NOTE
;
7935 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7937 isa_1_descsz_raw
= 4 + 4 + 4;
7938 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7939 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
7941 feature_2_descsz_raw
= isa_1_descsz
;
7942 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7944 feature_2_descsz_raw
+= 4 + 4 + 4;
7945 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7946 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
7949 descsz
= feature_2_descsz
;
7950 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7951 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
7953 /* Write n_namsz. */
7954 md_number_to_chars (p
, (valueT
) 4, 4);
7956 /* Write n_descsz. */
7957 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
7960 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
7963 memcpy (p
+ 4 * 3, "GNU", 4);
7965 /* Write 4-byte type. */
7966 md_number_to_chars (p
+ 4 * 4,
7967 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
7969 /* Write 4-byte data size. */
7970 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
7972 /* Write 4-byte data. */
7973 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
7975 /* Zero out paddings. */
7976 padding
= isa_1_descsz
- isa_1_descsz_raw
;
7978 memset (p
+ 4 * 7, 0, padding
);
7980 /* Write 4-byte type. */
7981 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
7982 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
7984 /* Write 4-byte data size. */
7985 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
7987 /* Write 4-byte data. */
7988 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
7989 (valueT
) x86_feature_2_used
, 4);
7991 /* Zero out paddings. */
7992 padding
= feature_2_descsz
- feature_2_descsz_raw
;
7994 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
7996 /* We probably can't restore the current segment, for there likely
7999 subseg_set (seg
, subseg
);
8006 fragS
*insn_start_frag
;
8007 offsetT insn_start_off
;
8009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8010 if (IS_ELF
&& x86_used_note
)
8012 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8013 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8014 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8015 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8016 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8017 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8018 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8019 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8020 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8021 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8022 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8023 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8024 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8025 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8026 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8027 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8028 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8029 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8030 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8031 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8032 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8033 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8034 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8035 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8036 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8037 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8038 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8039 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8040 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8041 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8042 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8043 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8044 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8045 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8046 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8047 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8048 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8049 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8050 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8051 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8052 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8053 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8054 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8055 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8056 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8057 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8058 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8059 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8061 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8062 || i
.tm
.cpu_flags
.bitfield
.cpu287
8063 || i
.tm
.cpu_flags
.bitfield
.cpu387
8064 || i
.tm
.cpu_flags
.bitfield
.cpu687
8065 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8066 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8067 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8068 Xfence instructions. */
8069 if (i
.tm
.base_opcode
!= 0xf18
8070 && i
.tm
.base_opcode
!= 0xf0d
8071 && i
.tm
.base_opcode
!= 0xfae
8073 || i
.tm
.cpu_flags
.bitfield
.cpummx
8074 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8075 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8076 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8078 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8080 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8082 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8083 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8084 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8085 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8086 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8087 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8088 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8089 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8090 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8094 /* Tie dwarf2 debug info to the address at the start of the insn.
8095 We can't do this after the insn has been output as the current
8096 frag may have been closed off. eg. by frag_var. */
8097 dwarf2_emit_insn (0);
8099 insn_start_frag
= frag_now
;
8100 insn_start_off
= frag_now_fix ();
8103 if (i
.tm
.opcode_modifier
.jump
)
8105 else if (i
.tm
.opcode_modifier
.jumpbyte
8106 || i
.tm
.opcode_modifier
.jumpdword
)
8108 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8109 output_interseg_jump ();
8112 /* Output normal instructions here. */
8116 unsigned int prefix
;
8119 && i
.tm
.base_opcode
== 0xfae
8121 && i
.imm_operands
== 1
8122 && (i
.op
[0].imms
->X_add_number
== 0xe8
8123 || i
.op
[0].imms
->X_add_number
== 0xf0
8124 || i
.op
[0].imms
->X_add_number
== 0xf8))
8126 /* Encode lfence, mfence, and sfence as
8127 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8128 offsetT val
= 0x240483f0ULL
;
8130 md_number_to_chars (p
, val
, 5);
8134 /* Some processors fail on LOCK prefix. This options makes
8135 assembler ignore LOCK prefix and serves as a workaround. */
8136 if (omit_lock_prefix
)
8138 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8140 i
.prefix
[LOCK_PREFIX
] = 0;
8143 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8144 don't need the explicit prefix. */
8145 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8147 switch (i
.tm
.opcode_length
)
8150 if (i
.tm
.base_opcode
& 0xff000000)
8152 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8153 add_prefix (prefix
);
8157 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8159 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8160 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8161 || prefix
!= REPE_PREFIX_OPCODE
8162 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8163 add_prefix (prefix
);
8169 /* Check for pseudo prefixes. */
8170 as_bad_where (insn_start_frag
->fr_file
,
8171 insn_start_frag
->fr_line
,
8172 _("pseudo prefix without instruction"));
8178 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8179 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8180 R_X86_64_GOTTPOFF relocation so that linker can safely
8181 perform IE->LE optimization. */
8182 if (x86_elf_abi
== X86_64_X32_ABI
8184 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8185 && i
.prefix
[REX_PREFIX
] == 0)
8186 add_prefix (REX_OPCODE
);
8189 /* The prefix bytes. */
8190 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8192 FRAG_APPEND_1_CHAR (*q
);
8196 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8201 /* REX byte is encoded in VEX prefix. */
8205 FRAG_APPEND_1_CHAR (*q
);
8208 /* There should be no other prefixes for instructions
8213 /* For EVEX instructions i.vrex should become 0 after
8214 build_evex_prefix. For VEX instructions upper 16 registers
8215 aren't available, so VREX should be 0. */
8218 /* Now the VEX prefix. */
8219 p
= frag_more (i
.vex
.length
);
8220 for (j
= 0; j
< i
.vex
.length
; j
++)
8221 p
[j
] = i
.vex
.bytes
[j
];
8224 /* Now the opcode; be careful about word order here! */
8225 if (i
.tm
.opcode_length
== 1)
8227 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8231 switch (i
.tm
.opcode_length
)
8235 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8236 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8240 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8250 /* Put out high byte first: can't use md_number_to_chars! */
8251 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8252 *p
= i
.tm
.base_opcode
& 0xff;
8255 /* Now the modrm byte and sib byte (if present). */
8256 if (i
.tm
.opcode_modifier
.modrm
)
8258 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8261 /* If i.rm.regmem == ESP (4)
8262 && i.rm.mode != (Register mode)
8264 ==> need second modrm byte. */
8265 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8267 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8268 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8270 | i
.sib
.scale
<< 6));
8273 if (i
.disp_operands
)
8274 output_disp (insn_start_frag
, insn_start_off
);
8277 output_imm (insn_start_frag
, insn_start_off
);
8283 pi ("" /*line*/, &i
);
8285 #endif /* DEBUG386 */
8288 /* Return the size of the displacement operand N. */
8291 disp_size (unsigned int n
)
8295 if (i
.types
[n
].bitfield
.disp64
)
8297 else if (i
.types
[n
].bitfield
.disp8
)
8299 else if (i
.types
[n
].bitfield
.disp16
)
8304 /* Return the size of the immediate operand N. */
8307 imm_size (unsigned int n
)
8310 if (i
.types
[n
].bitfield
.imm64
)
8312 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8314 else if (i
.types
[n
].bitfield
.imm16
)
8320 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8325 for (n
= 0; n
< i
.operands
; n
++)
8327 if (operand_type_check (i
.types
[n
], disp
))
8329 if (i
.op
[n
].disps
->X_op
== O_constant
)
8331 int size
= disp_size (n
);
8332 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8334 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8336 p
= frag_more (size
);
8337 md_number_to_chars (p
, val
, size
);
8341 enum bfd_reloc_code_real reloc_type
;
8342 int size
= disp_size (n
);
8343 int sign
= i
.types
[n
].bitfield
.disp32s
;
8344 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8347 /* We can't have 8 bit displacement here. */
8348 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8350 /* The PC relative address is computed relative
8351 to the instruction boundary, so in case immediate
8352 fields follows, we need to adjust the value. */
8353 if (pcrel
&& i
.imm_operands
)
8358 for (n1
= 0; n1
< i
.operands
; n1
++)
8359 if (operand_type_check (i
.types
[n1
], imm
))
8361 /* Only one immediate is allowed for PC
8362 relative address. */
8363 gas_assert (sz
== 0);
8365 i
.op
[n
].disps
->X_add_number
-= sz
;
8367 /* We should find the immediate. */
8368 gas_assert (sz
!= 0);
8371 p
= frag_more (size
);
8372 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8374 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8375 && (((reloc_type
== BFD_RELOC_32
8376 || reloc_type
== BFD_RELOC_X86_64_32S
8377 || (reloc_type
== BFD_RELOC_64
8379 && (i
.op
[n
].disps
->X_op
== O_symbol
8380 || (i
.op
[n
].disps
->X_op
== O_add
8381 && ((symbol_get_value_expression
8382 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8384 || reloc_type
== BFD_RELOC_32_PCREL
))
8388 if (insn_start_frag
== frag_now
)
8389 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8394 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8395 for (fr
= insn_start_frag
->fr_next
;
8396 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8398 add
+= p
- frag_now
->fr_literal
;
8403 reloc_type
= BFD_RELOC_386_GOTPC
;
8404 i
.op
[n
].imms
->X_add_number
+= add
;
8406 else if (reloc_type
== BFD_RELOC_64
)
8407 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8409 /* Don't do the adjustment for x86-64, as there
8410 the pcrel addressing is relative to the _next_
8411 insn, and that is taken care of in other code. */
8412 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8414 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8415 size
, i
.op
[n
].disps
, pcrel
,
8417 /* Check for "call/jmp *mem", "mov mem, %reg",
8418 "test %reg, mem" and "binop mem, %reg" where binop
8419 is one of adc, add, and, cmp, or, sbb, sub, xor
8420 instructions. Always generate R_386_GOT32X for
8421 "sym*GOT" operand in 32-bit mode. */
8422 if ((generate_relax_relocations
8425 && i
.rm
.regmem
== 5))
8427 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8428 && ((i
.operands
== 1
8429 && i
.tm
.base_opcode
== 0xff
8430 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8432 && (i
.tm
.base_opcode
== 0x8b
8433 || i
.tm
.base_opcode
== 0x85
8434 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8438 fixP
->fx_tcbit
= i
.rex
!= 0;
8440 && (i
.base_reg
->reg_num
== RegIP
))
8441 fixP
->fx_tcbit2
= 1;
8444 fixP
->fx_tcbit2
= 1;
8452 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8457 for (n
= 0; n
< i
.operands
; n
++)
8459 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8460 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8463 if (operand_type_check (i
.types
[n
], imm
))
8465 if (i
.op
[n
].imms
->X_op
== O_constant
)
8467 int size
= imm_size (n
);
8470 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8472 p
= frag_more (size
);
8473 md_number_to_chars (p
, val
, size
);
8477 /* Not absolute_section.
8478 Need a 32-bit fixup (don't support 8bit
8479 non-absolute imms). Try to support other
8481 enum bfd_reloc_code_real reloc_type
;
8482 int size
= imm_size (n
);
8485 if (i
.types
[n
].bitfield
.imm32s
8486 && (i
.suffix
== QWORD_MNEM_SUFFIX
8487 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8492 p
= frag_more (size
);
8493 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8495 /* This is tough to explain. We end up with this one if we
8496 * have operands that look like
8497 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8498 * obtain the absolute address of the GOT, and it is strongly
8499 * preferable from a performance point of view to avoid using
8500 * a runtime relocation for this. The actual sequence of
8501 * instructions often look something like:
8506 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8508 * The call and pop essentially return the absolute address
8509 * of the label .L66 and store it in %ebx. The linker itself
8510 * will ultimately change the first operand of the addl so
8511 * that %ebx points to the GOT, but to keep things simple, the
8512 * .o file must have this operand set so that it generates not
8513 * the absolute address of .L66, but the absolute address of
8514 * itself. This allows the linker itself simply treat a GOTPC
8515 * relocation as asking for a pcrel offset to the GOT to be
8516 * added in, and the addend of the relocation is stored in the
8517 * operand field for the instruction itself.
8519 * Our job here is to fix the operand so that it would add
8520 * the correct offset so that %ebx would point to itself. The
8521 * thing that is tricky is that .-.L66 will point to the
8522 * beginning of the instruction, so we need to further modify
8523 * the operand so that it will point to itself. There are
8524 * other cases where you have something like:
8526 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8528 * and here no correction would be required. Internally in
8529 * the assembler we treat operands of this form as not being
8530 * pcrel since the '.' is explicitly mentioned, and I wonder
8531 * whether it would simplify matters to do it this way. Who
8532 * knows. In earlier versions of the PIC patches, the
8533 * pcrel_adjust field was used to store the correction, but
8534 * since the expression is not pcrel, I felt it would be
8535 * confusing to do it this way. */
8537 if ((reloc_type
== BFD_RELOC_32
8538 || reloc_type
== BFD_RELOC_X86_64_32S
8539 || reloc_type
== BFD_RELOC_64
)
8541 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8542 && (i
.op
[n
].imms
->X_op
== O_symbol
8543 || (i
.op
[n
].imms
->X_op
== O_add
8544 && ((symbol_get_value_expression
8545 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8550 if (insn_start_frag
== frag_now
)
8551 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8556 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8557 for (fr
= insn_start_frag
->fr_next
;
8558 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8560 add
+= p
- frag_now
->fr_literal
;
8564 reloc_type
= BFD_RELOC_386_GOTPC
;
8566 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8568 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8569 i
.op
[n
].imms
->X_add_number
+= add
;
8571 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8572 i
.op
[n
].imms
, 0, reloc_type
);
8578 /* x86_cons_fix_new is called via the expression parsing code when a
8579 reloc is needed. We use this hook to get the correct .got reloc. */
8580 static int cons_sign
= -1;
8583 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8584 expressionS
*exp
, bfd_reloc_code_real_type r
)
8586 r
= reloc (len
, 0, cons_sign
, r
);
8589 if (exp
->X_op
== O_secrel
)
8591 exp
->X_op
= O_symbol
;
8592 r
= BFD_RELOC_32_SECREL
;
8596 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8599 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8600 purpose of the `.dc.a' internal pseudo-op. */
8603 x86_address_bytes (void)
8605 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8607 return stdoutput
->arch_info
->bits_per_address
/ 8;
8610 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8612 # define lex_got(reloc, adjust, types) NULL
8614 /* Parse operands of the form
8615 <symbol>@GOTOFF+<nnn>
8616 and similar .plt or .got references.
8618 If we find one, set up the correct relocation in RELOC and copy the
8619 input string, minus the `@GOTOFF' into a malloc'd buffer for
8620 parsing by the calling routine. Return this buffer, and if ADJUST
8621 is non-null set it to the length of the string we removed from the
8622 input line. Otherwise return NULL. */
8624 lex_got (enum bfd_reloc_code_real
*rel
,
8626 i386_operand_type
*types
)
8628 /* Some of the relocations depend on the size of what field is to
8629 be relocated. But in our callers i386_immediate and i386_displacement
8630 we don't yet know the operand size (this will be set by insn
8631 matching). Hence we record the word32 relocation here,
8632 and adjust the reloc according to the real size in reloc(). */
8633 static const struct {
8636 const enum bfd_reloc_code_real rel
[2];
8637 const i386_operand_type types64
;
8639 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8640 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8642 OPERAND_TYPE_IMM32_64
},
8644 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8645 BFD_RELOC_X86_64_PLTOFF64
},
8646 OPERAND_TYPE_IMM64
},
8647 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8648 BFD_RELOC_X86_64_PLT32
},
8649 OPERAND_TYPE_IMM32_32S_DISP32
},
8650 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8651 BFD_RELOC_X86_64_GOTPLT64
},
8652 OPERAND_TYPE_IMM64_DISP64
},
8653 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8654 BFD_RELOC_X86_64_GOTOFF64
},
8655 OPERAND_TYPE_IMM64_DISP64
},
8656 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8657 BFD_RELOC_X86_64_GOTPCREL
},
8658 OPERAND_TYPE_IMM32_32S_DISP32
},
8659 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8660 BFD_RELOC_X86_64_TLSGD
},
8661 OPERAND_TYPE_IMM32_32S_DISP32
},
8662 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8663 _dummy_first_bfd_reloc_code_real
},
8664 OPERAND_TYPE_NONE
},
8665 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8666 BFD_RELOC_X86_64_TLSLD
},
8667 OPERAND_TYPE_IMM32_32S_DISP32
},
8668 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8669 BFD_RELOC_X86_64_GOTTPOFF
},
8670 OPERAND_TYPE_IMM32_32S_DISP32
},
8671 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8672 BFD_RELOC_X86_64_TPOFF32
},
8673 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8674 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8675 _dummy_first_bfd_reloc_code_real
},
8676 OPERAND_TYPE_NONE
},
8677 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8678 BFD_RELOC_X86_64_DTPOFF32
},
8679 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8680 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8681 _dummy_first_bfd_reloc_code_real
},
8682 OPERAND_TYPE_NONE
},
8683 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8684 _dummy_first_bfd_reloc_code_real
},
8685 OPERAND_TYPE_NONE
},
8686 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8687 BFD_RELOC_X86_64_GOT32
},
8688 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8689 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8690 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8691 OPERAND_TYPE_IMM32_32S_DISP32
},
8692 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8693 BFD_RELOC_X86_64_TLSDESC_CALL
},
8694 OPERAND_TYPE_IMM32_32S_DISP32
},
8699 #if defined (OBJ_MAYBE_ELF)
8704 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8705 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8708 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8710 int len
= gotrel
[j
].len
;
8711 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8713 if (gotrel
[j
].rel
[object_64bit
] != 0)
8716 char *tmpbuf
, *past_reloc
;
8718 *rel
= gotrel
[j
].rel
[object_64bit
];
8722 if (flag_code
!= CODE_64BIT
)
8724 types
->bitfield
.imm32
= 1;
8725 types
->bitfield
.disp32
= 1;
8728 *types
= gotrel
[j
].types64
;
8731 if (j
!= 0 && GOT_symbol
== NULL
)
8732 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8734 /* The length of the first part of our input line. */
8735 first
= cp
- input_line_pointer
;
8737 /* The second part goes from after the reloc token until
8738 (and including) an end_of_line char or comma. */
8739 past_reloc
= cp
+ 1 + len
;
8741 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8743 second
= cp
+ 1 - past_reloc
;
8745 /* Allocate and copy string. The trailing NUL shouldn't
8746 be necessary, but be safe. */
8747 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8748 memcpy (tmpbuf
, input_line_pointer
, first
);
8749 if (second
!= 0 && *past_reloc
!= ' ')
8750 /* Replace the relocation token with ' ', so that
8751 errors like foo@GOTOFF1 will be detected. */
8752 tmpbuf
[first
++] = ' ';
8754 /* Increment length by 1 if the relocation token is
8759 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8760 tmpbuf
[first
+ second
] = '\0';
8764 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8765 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8770 /* Might be a symbol version string. Don't as_bad here. */
8779 /* Parse operands of the form
8780 <symbol>@SECREL32+<nnn>
8782 If we find one, set up the correct relocation in RELOC and copy the
8783 input string, minus the `@SECREL32' into a malloc'd buffer for
8784 parsing by the calling routine. Return this buffer, and if ADJUST
8785 is non-null set it to the length of the string we removed from the
8786 input line. Otherwise return NULL.
8788 This function is copied from the ELF version above adjusted for PE targets. */
8791 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8792 int *adjust ATTRIBUTE_UNUSED
,
8793 i386_operand_type
*types
)
8799 const enum bfd_reloc_code_real rel
[2];
8800 const i386_operand_type types64
;
8804 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8805 BFD_RELOC_32_SECREL
},
8806 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8812 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8813 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8816 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8818 int len
= gotrel
[j
].len
;
8820 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8822 if (gotrel
[j
].rel
[object_64bit
] != 0)
8825 char *tmpbuf
, *past_reloc
;
8827 *rel
= gotrel
[j
].rel
[object_64bit
];
8833 if (flag_code
!= CODE_64BIT
)
8835 types
->bitfield
.imm32
= 1;
8836 types
->bitfield
.disp32
= 1;
8839 *types
= gotrel
[j
].types64
;
8842 /* The length of the first part of our input line. */
8843 first
= cp
- input_line_pointer
;
8845 /* The second part goes from after the reloc token until
8846 (and including) an end_of_line char or comma. */
8847 past_reloc
= cp
+ 1 + len
;
8849 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8851 second
= cp
+ 1 - past_reloc
;
8853 /* Allocate and copy string. The trailing NUL shouldn't
8854 be necessary, but be safe. */
8855 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8856 memcpy (tmpbuf
, input_line_pointer
, first
);
8857 if (second
!= 0 && *past_reloc
!= ' ')
8858 /* Replace the relocation token with ' ', so that
8859 errors like foo@SECLREL321 will be detected. */
8860 tmpbuf
[first
++] = ' ';
8861 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8862 tmpbuf
[first
+ second
] = '\0';
8866 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8867 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8872 /* Might be a symbol version string. Don't as_bad here. */
8878 bfd_reloc_code_real_type
8879 x86_cons (expressionS
*exp
, int size
)
8881 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8883 intel_syntax
= -intel_syntax
;
8886 if (size
== 4 || (object_64bit
&& size
== 8))
8888 /* Handle @GOTOFF and the like in an expression. */
8890 char *gotfree_input_line
;
8893 save
= input_line_pointer
;
8894 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8895 if (gotfree_input_line
)
8896 input_line_pointer
= gotfree_input_line
;
8900 if (gotfree_input_line
)
8902 /* expression () has merrily parsed up to the end of line,
8903 or a comma - in the wrong buffer. Transfer how far
8904 input_line_pointer has moved to the right buffer. */
8905 input_line_pointer
= (save
8906 + (input_line_pointer
- gotfree_input_line
)
8908 free (gotfree_input_line
);
8909 if (exp
->X_op
== O_constant
8910 || exp
->X_op
== O_absent
8911 || exp
->X_op
== O_illegal
8912 || exp
->X_op
== O_register
8913 || exp
->X_op
== O_big
)
8915 char c
= *input_line_pointer
;
8916 *input_line_pointer
= 0;
8917 as_bad (_("missing or invalid expression `%s'"), save
);
8918 *input_line_pointer
= c
;
8925 intel_syntax
= -intel_syntax
;
8928 i386_intel_simplify (exp
);
8934 signed_cons (int size
)
8936 if (flag_code
== CODE_64BIT
)
8944 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8951 if (exp
.X_op
== O_symbol
)
8952 exp
.X_op
= O_secrel
;
8954 emit_expr (&exp
, 4);
8956 while (*input_line_pointer
++ == ',');
8958 input_line_pointer
--;
8959 demand_empty_rest_of_line ();
8963 /* Handle Vector operations. */
8966 check_VecOperations (char *op_string
, char *op_end
)
8968 const reg_entry
*mask
;
8973 && (op_end
== NULL
|| op_string
< op_end
))
8976 if (*op_string
== '{')
8980 /* Check broadcasts. */
8981 if (strncmp (op_string
, "1to", 3) == 0)
8986 goto duplicated_vec_op
;
8989 if (*op_string
== '8')
8991 else if (*op_string
== '4')
8993 else if (*op_string
== '2')
8995 else if (*op_string
== '1'
8996 && *(op_string
+1) == '6')
9003 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9008 broadcast_op
.type
= bcst_type
;
9009 broadcast_op
.operand
= this_operand
;
9010 broadcast_op
.bytes
= 0;
9011 i
.broadcast
= &broadcast_op
;
9013 /* Check masking operation. */
9014 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9016 /* k0 can't be used for write mask. */
9017 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9019 as_bad (_("`%s%s' can't be used for write mask"),
9020 register_prefix
, mask
->reg_name
);
9026 mask_op
.mask
= mask
;
9027 mask_op
.zeroing
= 0;
9028 mask_op
.operand
= this_operand
;
9034 goto duplicated_vec_op
;
9036 i
.mask
->mask
= mask
;
9038 /* Only "{z}" is allowed here. No need to check
9039 zeroing mask explicitly. */
9040 if (i
.mask
->operand
!= this_operand
)
9042 as_bad (_("invalid write mask `%s'"), saved
);
9049 /* Check zeroing-flag for masking operation. */
9050 else if (*op_string
== 'z')
9054 mask_op
.mask
= NULL
;
9055 mask_op
.zeroing
= 1;
9056 mask_op
.operand
= this_operand
;
9061 if (i
.mask
->zeroing
)
9064 as_bad (_("duplicated `%s'"), saved
);
9068 i
.mask
->zeroing
= 1;
9070 /* Only "{%k}" is allowed here. No need to check mask
9071 register explicitly. */
9072 if (i
.mask
->operand
!= this_operand
)
9074 as_bad (_("invalid zeroing-masking `%s'"),
9083 goto unknown_vec_op
;
9085 if (*op_string
!= '}')
9087 as_bad (_("missing `}' in `%s'"), saved
);
9092 /* Strip whitespace since the addition of pseudo prefixes
9093 changed how the scrubber treats '{'. */
9094 if (is_space_char (*op_string
))
9100 /* We don't know this one. */
9101 as_bad (_("unknown vector operation: `%s'"), saved
);
9105 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9107 as_bad (_("zeroing-masking only allowed with write mask"));
9115 i386_immediate (char *imm_start
)
9117 char *save_input_line_pointer
;
9118 char *gotfree_input_line
;
9121 i386_operand_type types
;
9123 operand_type_set (&types
, ~0);
9125 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9127 as_bad (_("at most %d immediate operands are allowed"),
9128 MAX_IMMEDIATE_OPERANDS
);
9132 exp
= &im_expressions
[i
.imm_operands
++];
9133 i
.op
[this_operand
].imms
= exp
;
9135 if (is_space_char (*imm_start
))
9138 save_input_line_pointer
= input_line_pointer
;
9139 input_line_pointer
= imm_start
;
9141 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9142 if (gotfree_input_line
)
9143 input_line_pointer
= gotfree_input_line
;
9145 exp_seg
= expression (exp
);
9149 /* Handle vector operations. */
9150 if (*input_line_pointer
== '{')
9152 input_line_pointer
= check_VecOperations (input_line_pointer
,
9154 if (input_line_pointer
== NULL
)
9158 if (*input_line_pointer
)
9159 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9161 input_line_pointer
= save_input_line_pointer
;
9162 if (gotfree_input_line
)
9164 free (gotfree_input_line
);
9166 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9167 exp
->X_op
= O_illegal
;
9170 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9174 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9175 i386_operand_type types
, const char *imm_start
)
9177 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9180 as_bad (_("missing or invalid immediate expression `%s'"),
9184 else if (exp
->X_op
== O_constant
)
9186 /* Size it properly later. */
9187 i
.types
[this_operand
].bitfield
.imm64
= 1;
9188 /* If not 64bit, sign extend val. */
9189 if (flag_code
!= CODE_64BIT
9190 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9192 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9194 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9195 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9196 && exp_seg
!= absolute_section
9197 && exp_seg
!= text_section
9198 && exp_seg
!= data_section
9199 && exp_seg
!= bss_section
9200 && exp_seg
!= undefined_section
9201 && !bfd_is_com_section (exp_seg
))
9203 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9207 else if (!intel_syntax
&& exp_seg
== reg_section
)
9210 as_bad (_("illegal immediate register operand %s"), imm_start
);
9215 /* This is an address. The size of the address will be
9216 determined later, depending on destination register,
9217 suffix, or the default for the section. */
9218 i
.types
[this_operand
].bitfield
.imm8
= 1;
9219 i
.types
[this_operand
].bitfield
.imm16
= 1;
9220 i
.types
[this_operand
].bitfield
.imm32
= 1;
9221 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9222 i
.types
[this_operand
].bitfield
.imm64
= 1;
9223 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9231 i386_scale (char *scale
)
9234 char *save
= input_line_pointer
;
9236 input_line_pointer
= scale
;
9237 val
= get_absolute_expression ();
9242 i
.log2_scale_factor
= 0;
9245 i
.log2_scale_factor
= 1;
9248 i
.log2_scale_factor
= 2;
9251 i
.log2_scale_factor
= 3;
9255 char sep
= *input_line_pointer
;
9257 *input_line_pointer
= '\0';
9258 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9260 *input_line_pointer
= sep
;
9261 input_line_pointer
= save
;
9265 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9267 as_warn (_("scale factor of %d without an index register"),
9268 1 << i
.log2_scale_factor
);
9269 i
.log2_scale_factor
= 0;
9271 scale
= input_line_pointer
;
9272 input_line_pointer
= save
;
9277 i386_displacement (char *disp_start
, char *disp_end
)
9281 char *save_input_line_pointer
;
9282 char *gotfree_input_line
;
9284 i386_operand_type bigdisp
, types
= anydisp
;
9287 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9289 as_bad (_("at most %d displacement operands are allowed"),
9290 MAX_MEMORY_OPERANDS
);
9294 operand_type_set (&bigdisp
, 0);
9295 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9296 || (!current_templates
->start
->opcode_modifier
.jump
9297 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9299 bigdisp
.bitfield
.disp32
= 1;
9300 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9301 if (flag_code
== CODE_64BIT
)
9305 bigdisp
.bitfield
.disp32s
= 1;
9306 bigdisp
.bitfield
.disp64
= 1;
9309 else if ((flag_code
== CODE_16BIT
) ^ override
)
9311 bigdisp
.bitfield
.disp32
= 0;
9312 bigdisp
.bitfield
.disp16
= 1;
9317 /* For PC-relative branches, the width of the displacement
9318 is dependent upon data size, not address size. */
9319 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9320 if (flag_code
== CODE_64BIT
)
9322 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9323 bigdisp
.bitfield
.disp16
= 1;
9326 bigdisp
.bitfield
.disp32
= 1;
9327 bigdisp
.bitfield
.disp32s
= 1;
9333 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9335 : LONG_MNEM_SUFFIX
));
9336 bigdisp
.bitfield
.disp32
= 1;
9337 if ((flag_code
== CODE_16BIT
) ^ override
)
9339 bigdisp
.bitfield
.disp32
= 0;
9340 bigdisp
.bitfield
.disp16
= 1;
9344 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9347 exp
= &disp_expressions
[i
.disp_operands
];
9348 i
.op
[this_operand
].disps
= exp
;
9350 save_input_line_pointer
= input_line_pointer
;
9351 input_line_pointer
= disp_start
;
9352 END_STRING_AND_SAVE (disp_end
);
9354 #ifndef GCC_ASM_O_HACK
9355 #define GCC_ASM_O_HACK 0
9358 END_STRING_AND_SAVE (disp_end
+ 1);
9359 if (i
.types
[this_operand
].bitfield
.baseIndex
9360 && displacement_string_end
[-1] == '+')
9362 /* This hack is to avoid a warning when using the "o"
9363 constraint within gcc asm statements.
9366 #define _set_tssldt_desc(n,addr,limit,type) \
9367 __asm__ __volatile__ ( \
9369 "movw %w1,2+%0\n\t" \
9371 "movb %b1,4+%0\n\t" \
9372 "movb %4,5+%0\n\t" \
9373 "movb $0,6+%0\n\t" \
9374 "movb %h1,7+%0\n\t" \
9376 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9378 This works great except that the output assembler ends
9379 up looking a bit weird if it turns out that there is
9380 no offset. You end up producing code that looks like:
9393 So here we provide the missing zero. */
9395 *displacement_string_end
= '0';
9398 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9399 if (gotfree_input_line
)
9400 input_line_pointer
= gotfree_input_line
;
9402 exp_seg
= expression (exp
);
9405 if (*input_line_pointer
)
9406 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9408 RESTORE_END_STRING (disp_end
+ 1);
9410 input_line_pointer
= save_input_line_pointer
;
9411 if (gotfree_input_line
)
9413 free (gotfree_input_line
);
9415 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9416 exp
->X_op
= O_illegal
;
9419 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9421 RESTORE_END_STRING (disp_end
);
9427 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9428 i386_operand_type types
, const char *disp_start
)
9430 i386_operand_type bigdisp
;
9433 /* We do this to make sure that the section symbol is in
9434 the symbol table. We will ultimately change the relocation
9435 to be relative to the beginning of the section. */
9436 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9437 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9438 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9440 if (exp
->X_op
!= O_symbol
)
9443 if (S_IS_LOCAL (exp
->X_add_symbol
)
9444 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9445 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9446 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9447 exp
->X_op
= O_subtract
;
9448 exp
->X_op_symbol
= GOT_symbol
;
9449 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9450 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9451 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9452 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9454 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9457 else if (exp
->X_op
== O_absent
9458 || exp
->X_op
== O_illegal
9459 || exp
->X_op
== O_big
)
9462 as_bad (_("missing or invalid displacement expression `%s'"),
9467 else if (flag_code
== CODE_64BIT
9468 && !i
.prefix
[ADDR_PREFIX
]
9469 && exp
->X_op
== O_constant
)
9471 /* Since displacement is signed extended to 64bit, don't allow
9472 disp32 and turn off disp32s if they are out of range. */
9473 i
.types
[this_operand
].bitfield
.disp32
= 0;
9474 if (!fits_in_signed_long (exp
->X_add_number
))
9476 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9477 if (i
.types
[this_operand
].bitfield
.baseindex
)
9479 as_bad (_("0x%lx out range of signed 32bit displacement"),
9480 (long) exp
->X_add_number
);
9486 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9487 else if (exp
->X_op
!= O_constant
9488 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9489 && exp_seg
!= absolute_section
9490 && exp_seg
!= text_section
9491 && exp_seg
!= data_section
9492 && exp_seg
!= bss_section
9493 && exp_seg
!= undefined_section
9494 && !bfd_is_com_section (exp_seg
))
9496 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9501 /* Check if this is a displacement only operand. */
9502 bigdisp
= i
.types
[this_operand
];
9503 bigdisp
.bitfield
.disp8
= 0;
9504 bigdisp
.bitfield
.disp16
= 0;
9505 bigdisp
.bitfield
.disp32
= 0;
9506 bigdisp
.bitfield
.disp32s
= 0;
9507 bigdisp
.bitfield
.disp64
= 0;
9508 if (operand_type_all_zero (&bigdisp
))
9509 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9515 /* Return the active addressing mode, taking address override and
9516 registers forming the address into consideration. Update the
9517 address override prefix if necessary. */
9519 static enum flag_code
9520 i386_addressing_mode (void)
9522 enum flag_code addr_mode
;
9524 if (i
.prefix
[ADDR_PREFIX
])
9525 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9528 addr_mode
= flag_code
;
9530 #if INFER_ADDR_PREFIX
9531 if (i
.mem_operands
== 0)
9533 /* Infer address prefix from the first memory operand. */
9534 const reg_entry
*addr_reg
= i
.base_reg
;
9536 if (addr_reg
== NULL
)
9537 addr_reg
= i
.index_reg
;
9541 if (addr_reg
->reg_type
.bitfield
.dword
)
9542 addr_mode
= CODE_32BIT
;
9543 else if (flag_code
!= CODE_64BIT
9544 && addr_reg
->reg_type
.bitfield
.word
)
9545 addr_mode
= CODE_16BIT
;
9547 if (addr_mode
!= flag_code
)
9549 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9551 /* Change the size of any displacement too. At most one
9552 of Disp16 or Disp32 is set.
9553 FIXME. There doesn't seem to be any real need for
9554 separate Disp16 and Disp32 flags. The same goes for
9555 Imm16 and Imm32. Removing them would probably clean
9556 up the code quite a lot. */
9557 if (flag_code
!= CODE_64BIT
9558 && (i
.types
[this_operand
].bitfield
.disp16
9559 || i
.types
[this_operand
].bitfield
.disp32
))
9560 i
.types
[this_operand
]
9561 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9571 /* Make sure the memory operand we've been dealt is valid.
9572 Return 1 on success, 0 on a failure. */
9575 i386_index_check (const char *operand_string
)
9577 const char *kind
= "base/index";
9578 enum flag_code addr_mode
= i386_addressing_mode ();
9580 if (current_templates
->start
->opcode_modifier
.isstring
9581 && !current_templates
->start
->opcode_modifier
.immext
9582 && (current_templates
->end
[-1].opcode_modifier
.isstring
9585 /* Memory operands of string insns are special in that they only allow
9586 a single register (rDI, rSI, or rBX) as their memory address. */
9587 const reg_entry
*expected_reg
;
9588 static const char *di_si
[][2] =
9594 static const char *bx
[] = { "ebx", "bx", "rbx" };
9596 kind
= "string address";
9598 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9600 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9602 if (!type
.bitfield
.baseindex
9603 || ((!i
.mem_operands
!= !intel_syntax
)
9604 && current_templates
->end
[-1].operand_types
[1]
9605 .bitfield
.baseindex
))
9606 type
= current_templates
->end
[-1].operand_types
[1];
9607 expected_reg
= hash_find (reg_hash
,
9608 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9612 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9614 if (i
.base_reg
!= expected_reg
9616 || operand_type_check (i
.types
[this_operand
], disp
))
9618 /* The second memory operand must have the same size as
9622 && !((addr_mode
== CODE_64BIT
9623 && i
.base_reg
->reg_type
.bitfield
.qword
)
9624 || (addr_mode
== CODE_32BIT
9625 ? i
.base_reg
->reg_type
.bitfield
.dword
9626 : i
.base_reg
->reg_type
.bitfield
.word
)))
9629 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9631 intel_syntax
? '[' : '(',
9633 expected_reg
->reg_name
,
9634 intel_syntax
? ']' : ')');
9641 as_bad (_("`%s' is not a valid %s expression"),
9642 operand_string
, kind
);
9647 if (addr_mode
!= CODE_16BIT
)
9649 /* 32-bit/64-bit checks. */
9651 && ((addr_mode
== CODE_64BIT
9652 ? !i
.base_reg
->reg_type
.bitfield
.qword
9653 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9654 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9655 || i
.base_reg
->reg_num
== RegIZ
))
9657 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9658 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9659 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9660 && ((addr_mode
== CODE_64BIT
9661 ? !i
.index_reg
->reg_type
.bitfield
.qword
9662 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9663 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9666 /* bndmk, bndldx, and bndstx have special restrictions. */
9667 if (current_templates
->start
->base_opcode
== 0xf30f1b
9668 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9670 /* They cannot use RIP-relative addressing. */
9671 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9673 as_bad (_("`%s' cannot be used here"), operand_string
);
9677 /* bndldx and bndstx ignore their scale factor. */
9678 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9679 && i
.log2_scale_factor
)
9680 as_warn (_("register scaling is being ignored here"));
9685 /* 16-bit checks. */
9687 && (!i
.base_reg
->reg_type
.bitfield
.word
9688 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9690 && (!i
.index_reg
->reg_type
.bitfield
.word
9691 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9693 && i
.base_reg
->reg_num
< 6
9694 && i
.index_reg
->reg_num
>= 6
9695 && i
.log2_scale_factor
== 0))))
9702 /* Handle vector immediates. */
9705 RC_SAE_immediate (const char *imm_start
)
9707 unsigned int match_found
, j
;
9708 const char *pstr
= imm_start
;
9716 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9718 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9722 rc_op
.type
= RC_NamesTable
[j
].type
;
9723 rc_op
.operand
= this_operand
;
9724 i
.rounding
= &rc_op
;
9728 as_bad (_("duplicated `%s'"), imm_start
);
9731 pstr
+= RC_NamesTable
[j
].len
;
9741 as_bad (_("Missing '}': '%s'"), imm_start
);
9744 /* RC/SAE immediate string should contain nothing more. */;
9747 as_bad (_("Junk after '}': '%s'"), imm_start
);
9751 exp
= &im_expressions
[i
.imm_operands
++];
9752 i
.op
[this_operand
].imms
= exp
;
9754 exp
->X_op
= O_constant
;
9755 exp
->X_add_number
= 0;
9756 exp
->X_add_symbol
= (symbolS
*) 0;
9757 exp
->X_op_symbol
= (symbolS
*) 0;
9759 i
.types
[this_operand
].bitfield
.imm8
= 1;
9763 /* Only string instructions can have a second memory operand, so
9764 reduce current_templates to just those if it contains any. */
9766 maybe_adjust_templates (void)
9768 const insn_template
*t
;
9770 gas_assert (i
.mem_operands
== 1);
9772 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9773 if (t
->opcode_modifier
.isstring
)
9776 if (t
< current_templates
->end
)
9778 static templates aux_templates
;
9779 bfd_boolean recheck
;
9781 aux_templates
.start
= t
;
9782 for (; t
< current_templates
->end
; ++t
)
9783 if (!t
->opcode_modifier
.isstring
)
9785 aux_templates
.end
= t
;
9787 /* Determine whether to re-check the first memory operand. */
9788 recheck
= (aux_templates
.start
!= current_templates
->start
9789 || t
!= current_templates
->end
);
9791 current_templates
= &aux_templates
;
9796 if (i
.memop1_string
!= NULL
9797 && i386_index_check (i
.memop1_string
) == 0)
9806 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9810 i386_att_operand (char *operand_string
)
9814 char *op_string
= operand_string
;
9816 if (is_space_char (*op_string
))
9819 /* We check for an absolute prefix (differentiating,
9820 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9821 if (*op_string
== ABSOLUTE_PREFIX
)
9824 if (is_space_char (*op_string
))
9826 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9829 /* Check if operand is a register. */
9830 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9832 i386_operand_type temp
;
9834 /* Check for a segment override by searching for ':' after a
9835 segment register. */
9837 if (is_space_char (*op_string
))
9839 if (*op_string
== ':'
9840 && (r
->reg_type
.bitfield
.sreg2
9841 || r
->reg_type
.bitfield
.sreg3
))
9846 i
.seg
[i
.mem_operands
] = &es
;
9849 i
.seg
[i
.mem_operands
] = &cs
;
9852 i
.seg
[i
.mem_operands
] = &ss
;
9855 i
.seg
[i
.mem_operands
] = &ds
;
9858 i
.seg
[i
.mem_operands
] = &fs
;
9861 i
.seg
[i
.mem_operands
] = &gs
;
9865 /* Skip the ':' and whitespace. */
9867 if (is_space_char (*op_string
))
9870 if (!is_digit_char (*op_string
)
9871 && !is_identifier_char (*op_string
)
9872 && *op_string
!= '('
9873 && *op_string
!= ABSOLUTE_PREFIX
)
9875 as_bad (_("bad memory operand `%s'"), op_string
);
9878 /* Handle case of %es:*foo. */
9879 if (*op_string
== ABSOLUTE_PREFIX
)
9882 if (is_space_char (*op_string
))
9884 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9886 goto do_memory_reference
;
9889 /* Handle vector operations. */
9890 if (*op_string
== '{')
9892 op_string
= check_VecOperations (op_string
, NULL
);
9893 if (op_string
== NULL
)
9899 as_bad (_("junk `%s' after register"), op_string
);
9903 temp
.bitfield
.baseindex
= 0;
9904 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9906 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9907 i
.op
[this_operand
].regs
= r
;
9910 else if (*op_string
== REGISTER_PREFIX
)
9912 as_bad (_("bad register name `%s'"), op_string
);
9915 else if (*op_string
== IMMEDIATE_PREFIX
)
9918 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9920 as_bad (_("immediate operand illegal with absolute jump"));
9923 if (!i386_immediate (op_string
))
9926 else if (RC_SAE_immediate (operand_string
))
9928 /* If it is a RC or SAE immediate, do nothing. */
9931 else if (is_digit_char (*op_string
)
9932 || is_identifier_char (*op_string
)
9933 || *op_string
== '"'
9934 || *op_string
== '(')
9936 /* This is a memory reference of some sort. */
9939 /* Start and end of displacement string expression (if found). */
9940 char *displacement_string_start
;
9941 char *displacement_string_end
;
9944 do_memory_reference
:
9945 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9947 if ((i
.mem_operands
== 1
9948 && !current_templates
->start
->opcode_modifier
.isstring
)
9949 || i
.mem_operands
== 2)
9951 as_bad (_("too many memory references for `%s'"),
9952 current_templates
->start
->name
);
9956 /* Check for base index form. We detect the base index form by
9957 looking for an ')' at the end of the operand, searching
9958 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9960 base_string
= op_string
+ strlen (op_string
);
9962 /* Handle vector operations. */
9963 vop_start
= strchr (op_string
, '{');
9964 if (vop_start
&& vop_start
< base_string
)
9966 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9968 base_string
= vop_start
;
9972 if (is_space_char (*base_string
))
9975 /* If we only have a displacement, set-up for it to be parsed later. */
9976 displacement_string_start
= op_string
;
9977 displacement_string_end
= base_string
+ 1;
9979 if (*base_string
== ')')
9982 unsigned int parens_balanced
= 1;
9983 /* We've already checked that the number of left & right ()'s are
9984 equal, so this loop will not be infinite. */
9988 if (*base_string
== ')')
9990 if (*base_string
== '(')
9993 while (parens_balanced
);
9995 temp_string
= base_string
;
9997 /* Skip past '(' and whitespace. */
9999 if (is_space_char (*base_string
))
10002 if (*base_string
== ','
10003 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10006 displacement_string_end
= temp_string
;
10008 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10012 base_string
= end_op
;
10013 if (is_space_char (*base_string
))
10017 /* There may be an index reg or scale factor here. */
10018 if (*base_string
== ',')
10021 if (is_space_char (*base_string
))
10024 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10027 base_string
= end_op
;
10028 if (is_space_char (*base_string
))
10030 if (*base_string
== ',')
10033 if (is_space_char (*base_string
))
10036 else if (*base_string
!= ')')
10038 as_bad (_("expecting `,' or `)' "
10039 "after index register in `%s'"),
10044 else if (*base_string
== REGISTER_PREFIX
)
10046 end_op
= strchr (base_string
, ',');
10049 as_bad (_("bad register name `%s'"), base_string
);
10053 /* Check for scale factor. */
10054 if (*base_string
!= ')')
10056 char *end_scale
= i386_scale (base_string
);
10061 base_string
= end_scale
;
10062 if (is_space_char (*base_string
))
10064 if (*base_string
!= ')')
10066 as_bad (_("expecting `)' "
10067 "after scale factor in `%s'"),
10072 else if (!i
.index_reg
)
10074 as_bad (_("expecting index register or scale factor "
10075 "after `,'; got '%c'"),
10080 else if (*base_string
!= ')')
10082 as_bad (_("expecting `,' or `)' "
10083 "after base register in `%s'"),
10088 else if (*base_string
== REGISTER_PREFIX
)
10090 end_op
= strchr (base_string
, ',');
10093 as_bad (_("bad register name `%s'"), base_string
);
10098 /* If there's an expression beginning the operand, parse it,
10099 assuming displacement_string_start and
10100 displacement_string_end are meaningful. */
10101 if (displacement_string_start
!= displacement_string_end
)
10103 if (!i386_displacement (displacement_string_start
,
10104 displacement_string_end
))
10108 /* Special case for (%dx) while doing input/output op. */
10110 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10111 && i
.index_reg
== 0
10112 && i
.log2_scale_factor
== 0
10113 && i
.seg
[i
.mem_operands
] == 0
10114 && !operand_type_check (i
.types
[this_operand
], disp
))
10116 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10120 if (i386_index_check (operand_string
) == 0)
10122 i
.flags
[this_operand
] |= Operand_Mem
;
10123 if (i
.mem_operands
== 0)
10124 i
.memop1_string
= xstrdup (operand_string
);
10129 /* It's not a memory operand; argh! */
10130 as_bad (_("invalid char %s beginning operand %d `%s'"),
10131 output_invalid (*op_string
),
10136 return 1; /* Normal return. */
10139 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10140 that an rs_machine_dependent frag may reach. */
10143 i386_frag_max_var (fragS
*frag
)
10145 /* The only relaxable frags are for jumps.
10146 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10147 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10148 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10151 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10153 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10155 /* STT_GNU_IFUNC symbol must go through PLT. */
10156 if ((symbol_get_bfdsym (fr_symbol
)->flags
10157 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10160 if (!S_IS_EXTERNAL (fr_symbol
))
10161 /* Symbol may be weak or local. */
10162 return !S_IS_WEAK (fr_symbol
);
10164 /* Global symbols with non-default visibility can't be preempted. */
10165 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10168 if (fr_var
!= NO_RELOC
)
10169 switch ((enum bfd_reloc_code_real
) fr_var
)
10171 case BFD_RELOC_386_PLT32
:
10172 case BFD_RELOC_X86_64_PLT32
:
10173 /* Symbol with PLT relocation may be preempted. */
10179 /* Global symbols with default visibility in a shared library may be
10180 preempted by another definition. */
10185 /* md_estimate_size_before_relax()
10187 Called just before relax() for rs_machine_dependent frags. The x86
10188 assembler uses these frags to handle variable size jump
10191 Any symbol that is now undefined will not become defined.
10192 Return the correct fr_subtype in the frag.
10193 Return the initial "guess for variable size of frag" to caller.
10194 The guess is actually the growth beyond the fixed part. Whatever
10195 we do to grow the fixed or variable part contributes to our
10199 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10201 /* We've already got fragP->fr_subtype right; all we have to do is
10202 check for un-relaxable symbols. On an ELF system, we can't relax
10203 an externally visible symbol, because it may be overridden by a
10205 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10208 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10211 #if defined (OBJ_COFF) && defined (TE_PE)
10212 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10213 && S_IS_WEAK (fragP
->fr_symbol
))
10217 /* Symbol is undefined in this segment, or we need to keep a
10218 reloc so that weak symbols can be overridden. */
10219 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10220 enum bfd_reloc_code_real reloc_type
;
10221 unsigned char *opcode
;
10224 if (fragP
->fr_var
!= NO_RELOC
)
10225 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10226 else if (size
== 2)
10227 reloc_type
= BFD_RELOC_16_PCREL
;
10228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10229 else if (need_plt32_p (fragP
->fr_symbol
))
10230 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10233 reloc_type
= BFD_RELOC_32_PCREL
;
10235 old_fr_fix
= fragP
->fr_fix
;
10236 opcode
= (unsigned char *) fragP
->fr_opcode
;
10238 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10241 /* Make jmp (0xeb) a (d)word displacement jump. */
10243 fragP
->fr_fix
+= size
;
10244 fix_new (fragP
, old_fr_fix
, size
,
10246 fragP
->fr_offset
, 1,
10252 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10254 /* Negate the condition, and branch past an
10255 unconditional jump. */
10258 /* Insert an unconditional jump. */
10260 /* We added two extra opcode bytes, and have a two byte
10262 fragP
->fr_fix
+= 2 + 2;
10263 fix_new (fragP
, old_fr_fix
+ 2, 2,
10265 fragP
->fr_offset
, 1,
10269 /* Fall through. */
10272 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10276 fragP
->fr_fix
+= 1;
10277 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10279 fragP
->fr_offset
, 1,
10280 BFD_RELOC_8_PCREL
);
10281 fixP
->fx_signed
= 1;
10285 /* This changes the byte-displacement jump 0x7N
10286 to the (d)word-displacement jump 0x0f,0x8N. */
10287 opcode
[1] = opcode
[0] + 0x10;
10288 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10289 /* We've added an opcode byte. */
10290 fragP
->fr_fix
+= 1 + size
;
10291 fix_new (fragP
, old_fr_fix
+ 1, size
,
10293 fragP
->fr_offset
, 1,
10298 BAD_CASE (fragP
->fr_subtype
);
10302 return fragP
->fr_fix
- old_fr_fix
;
10305 /* Guess size depending on current relax state. Initially the relax
10306 state will correspond to a short jump and we return 1, because
10307 the variable part of the frag (the branch offset) is one byte
10308 long. However, we can relax a section more than once and in that
10309 case we must either set fr_subtype back to the unrelaxed state,
10310 or return the value for the appropriate branch. */
10311 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10314 /* Called after relax() is finished.
10316 In: Address of frag.
10317 fr_type == rs_machine_dependent.
10318 fr_subtype is what the address relaxed to.
10320 Out: Any fixSs and constants are set up.
10321 Caller will turn frag into a ".space 0". */
10324 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10327 unsigned char *opcode
;
10328 unsigned char *where_to_put_displacement
= NULL
;
10329 offsetT target_address
;
10330 offsetT opcode_address
;
10331 unsigned int extension
= 0;
10332 offsetT displacement_from_opcode_start
;
10334 opcode
= (unsigned char *) fragP
->fr_opcode
;
10336 /* Address we want to reach in file space. */
10337 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10339 /* Address opcode resides at in file space. */
10340 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10342 /* Displacement from opcode start to fill into instruction. */
10343 displacement_from_opcode_start
= target_address
- opcode_address
;
10345 if ((fragP
->fr_subtype
& BIG
) == 0)
10347 /* Don't have to change opcode. */
10348 extension
= 1; /* 1 opcode + 1 displacement */
10349 where_to_put_displacement
= &opcode
[1];
10353 if (no_cond_jump_promotion
10354 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10355 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10356 _("long jump required"));
10358 switch (fragP
->fr_subtype
)
10360 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10361 extension
= 4; /* 1 opcode + 4 displacement */
10363 where_to_put_displacement
= &opcode
[1];
10366 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10367 extension
= 2; /* 1 opcode + 2 displacement */
10369 where_to_put_displacement
= &opcode
[1];
10372 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10373 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10374 extension
= 5; /* 2 opcode + 4 displacement */
10375 opcode
[1] = opcode
[0] + 0x10;
10376 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10377 where_to_put_displacement
= &opcode
[2];
10380 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10381 extension
= 3; /* 2 opcode + 2 displacement */
10382 opcode
[1] = opcode
[0] + 0x10;
10383 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10384 where_to_put_displacement
= &opcode
[2];
10387 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10392 where_to_put_displacement
= &opcode
[3];
10396 BAD_CASE (fragP
->fr_subtype
);
10401 /* If size if less then four we are sure that the operand fits,
10402 but if it's 4, then it could be that the displacement is larger
10404 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10406 && ((addressT
) (displacement_from_opcode_start
- extension
10407 + ((addressT
) 1 << 31))
10408 > (((addressT
) 2 << 31) - 1)))
10410 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10411 _("jump target out of range"));
10412 /* Make us emit 0. */
10413 displacement_from_opcode_start
= extension
;
10415 /* Now put displacement after opcode. */
10416 md_number_to_chars ((char *) where_to_put_displacement
,
10417 (valueT
) (displacement_from_opcode_start
- extension
),
10418 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10419 fragP
->fr_fix
+= extension
;
10422 /* Apply a fixup (fixP) to segment data, once it has been determined
10423 by our caller that we have all the info we need to fix it up.
10425 Parameter valP is the pointer to the value of the bits.
10427 On the 386, immediates, displacements, and data pointers are all in
10428 the same (little-endian) format, so we don't need to care about which
10429 we are handling. */
10432 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10434 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10435 valueT value
= *valP
;
10437 #if !defined (TE_Mach)
10438 if (fixP
->fx_pcrel
)
10440 switch (fixP
->fx_r_type
)
10446 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10449 case BFD_RELOC_X86_64_32S
:
10450 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10453 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10456 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10461 if (fixP
->fx_addsy
!= NULL
10462 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10463 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10464 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10465 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10466 && !use_rela_relocations
)
10468 /* This is a hack. There should be a better way to handle this.
10469 This covers for the fact that bfd_install_relocation will
10470 subtract the current location (for partial_inplace, PC relative
10471 relocations); see more below. */
10475 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10478 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10483 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10485 if ((sym_seg
== seg
10486 || (symbol_section_p (fixP
->fx_addsy
)
10487 && sym_seg
!= absolute_section
))
10488 && !generic_force_reloc (fixP
))
10490 /* Yes, we add the values in twice. This is because
10491 bfd_install_relocation subtracts them out again. I think
10492 bfd_install_relocation is broken, but I don't dare change
10494 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10498 #if defined (OBJ_COFF) && defined (TE_PE)
10499 /* For some reason, the PE format does not store a
10500 section address offset for a PC relative symbol. */
10501 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10502 || S_IS_WEAK (fixP
->fx_addsy
))
10503 value
+= md_pcrel_from (fixP
);
10506 #if defined (OBJ_COFF) && defined (TE_PE)
10507 if (fixP
->fx_addsy
!= NULL
10508 && S_IS_WEAK (fixP
->fx_addsy
)
10509 /* PR 16858: Do not modify weak function references. */
10510 && ! fixP
->fx_pcrel
)
10512 #if !defined (TE_PEP)
10513 /* For x86 PE weak function symbols are neither PC-relative
10514 nor do they set S_IS_FUNCTION. So the only reliable way
10515 to detect them is to check the flags of their containing
10517 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10518 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10522 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10526 /* Fix a few things - the dynamic linker expects certain values here,
10527 and we must not disappoint it. */
10528 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10529 if (IS_ELF
&& fixP
->fx_addsy
)
10530 switch (fixP
->fx_r_type
)
10532 case BFD_RELOC_386_PLT32
:
10533 case BFD_RELOC_X86_64_PLT32
:
10534 /* Make the jump instruction point to the address of the operand. At
10535 runtime we merely add the offset to the actual PLT entry. */
10539 case BFD_RELOC_386_TLS_GD
:
10540 case BFD_RELOC_386_TLS_LDM
:
10541 case BFD_RELOC_386_TLS_IE_32
:
10542 case BFD_RELOC_386_TLS_IE
:
10543 case BFD_RELOC_386_TLS_GOTIE
:
10544 case BFD_RELOC_386_TLS_GOTDESC
:
10545 case BFD_RELOC_X86_64_TLSGD
:
10546 case BFD_RELOC_X86_64_TLSLD
:
10547 case BFD_RELOC_X86_64_GOTTPOFF
:
10548 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10549 value
= 0; /* Fully resolved at runtime. No addend. */
10551 case BFD_RELOC_386_TLS_LE
:
10552 case BFD_RELOC_386_TLS_LDO_32
:
10553 case BFD_RELOC_386_TLS_LE_32
:
10554 case BFD_RELOC_X86_64_DTPOFF32
:
10555 case BFD_RELOC_X86_64_DTPOFF64
:
10556 case BFD_RELOC_X86_64_TPOFF32
:
10557 case BFD_RELOC_X86_64_TPOFF64
:
10558 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10561 case BFD_RELOC_386_TLS_DESC_CALL
:
10562 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10563 value
= 0; /* Fully resolved at runtime. No addend. */
10564 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10568 case BFD_RELOC_VTABLE_INHERIT
:
10569 case BFD_RELOC_VTABLE_ENTRY
:
10576 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10578 #endif /* !defined (TE_Mach) */
10580 /* Are we finished with this relocation now? */
10581 if (fixP
->fx_addsy
== NULL
)
10583 #if defined (OBJ_COFF) && defined (TE_PE)
10584 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10587 /* Remember value for tc_gen_reloc. */
10588 fixP
->fx_addnumber
= value
;
10589 /* Clear out the frag for now. */
10593 else if (use_rela_relocations
)
10595 fixP
->fx_no_overflow
= 1;
10596 /* Remember value for tc_gen_reloc. */
10597 fixP
->fx_addnumber
= value
;
10601 md_number_to_chars (p
, value
, fixP
->fx_size
);
10605 md_atof (int type
, char *litP
, int *sizeP
)
10607 /* This outputs the LITTLENUMs in REVERSE order;
10608 in accord with the bigendian 386. */
10609 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10612 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10615 output_invalid (int c
)
10618 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10621 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10622 "(0x%x)", (unsigned char) c
);
10623 return output_invalid_buf
;
10626 /* REG_STRING starts *before* REGISTER_PREFIX. */
10628 static const reg_entry
*
10629 parse_real_register (char *reg_string
, char **end_op
)
10631 char *s
= reg_string
;
10633 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10634 const reg_entry
*r
;
10636 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10637 if (*s
== REGISTER_PREFIX
)
10640 if (is_space_char (*s
))
10643 p
= reg_name_given
;
10644 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10646 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10647 return (const reg_entry
*) NULL
;
10651 /* For naked regs, make sure that we are not dealing with an identifier.
10652 This prevents confusing an identifier like `eax_var' with register
10654 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10655 return (const reg_entry
*) NULL
;
10659 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10661 /* Handle floating point regs, allowing spaces in the (i) part. */
10662 if (r
== i386_regtab
/* %st is first entry of table */)
10664 if (!cpu_arch_flags
.bitfield
.cpu8087
10665 && !cpu_arch_flags
.bitfield
.cpu287
10666 && !cpu_arch_flags
.bitfield
.cpu387
)
10667 return (const reg_entry
*) NULL
;
10669 if (is_space_char (*s
))
10674 if (is_space_char (*s
))
10676 if (*s
>= '0' && *s
<= '7')
10678 int fpr
= *s
- '0';
10680 if (is_space_char (*s
))
10685 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10690 /* We have "%st(" then garbage. */
10691 return (const reg_entry
*) NULL
;
10695 if (r
== NULL
|| allow_pseudo_reg
)
10698 if (operand_type_all_zero (&r
->reg_type
))
10699 return (const reg_entry
*) NULL
;
10701 if ((r
->reg_type
.bitfield
.dword
10702 || r
->reg_type
.bitfield
.sreg3
10703 || r
->reg_type
.bitfield
.control
10704 || r
->reg_type
.bitfield
.debug
10705 || r
->reg_type
.bitfield
.test
)
10706 && !cpu_arch_flags
.bitfield
.cpui386
)
10707 return (const reg_entry
*) NULL
;
10709 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10710 return (const reg_entry
*) NULL
;
10712 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10714 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10715 return (const reg_entry
*) NULL
;
10717 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10719 if (r
->reg_type
.bitfield
.ymmword
)
10720 return (const reg_entry
*) NULL
;
10722 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10723 return (const reg_entry
*) NULL
;
10727 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10728 return (const reg_entry
*) NULL
;
10730 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10731 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10732 return (const reg_entry
*) NULL
;
10734 /* Upper 16 vector registers are only available with VREX in 64bit
10735 mode, and require EVEX encoding. */
10736 if (r
->reg_flags
& RegVRex
)
10738 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10739 || flag_code
!= CODE_64BIT
)
10740 return (const reg_entry
*) NULL
;
10742 i
.vec_encoding
= vex_encoding_evex
;
10745 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10746 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10747 && flag_code
!= CODE_64BIT
)
10748 return (const reg_entry
*) NULL
;
10750 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10751 return (const reg_entry
*) NULL
;
10756 /* REG_STRING starts *before* REGISTER_PREFIX. */
10758 static const reg_entry
*
10759 parse_register (char *reg_string
, char **end_op
)
10761 const reg_entry
*r
;
10763 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10764 r
= parse_real_register (reg_string
, end_op
);
10769 char *save
= input_line_pointer
;
10773 input_line_pointer
= reg_string
;
10774 c
= get_symbol_name (®_string
);
10775 symbolP
= symbol_find (reg_string
);
10776 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10778 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10780 know (e
->X_op
== O_register
);
10781 know (e
->X_add_number
>= 0
10782 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10783 r
= i386_regtab
+ e
->X_add_number
;
10784 if ((r
->reg_flags
& RegVRex
))
10785 i
.vec_encoding
= vex_encoding_evex
;
10786 *end_op
= input_line_pointer
;
10788 *input_line_pointer
= c
;
10789 input_line_pointer
= save
;
10795 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10797 const reg_entry
*r
;
10798 char *end
= input_line_pointer
;
10801 r
= parse_register (name
, &input_line_pointer
);
10802 if (r
&& end
<= input_line_pointer
)
10804 *nextcharP
= *input_line_pointer
;
10805 *input_line_pointer
= 0;
10806 e
->X_op
= O_register
;
10807 e
->X_add_number
= r
- i386_regtab
;
10810 input_line_pointer
= end
;
10812 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10816 md_operand (expressionS
*e
)
10819 const reg_entry
*r
;
10821 switch (*input_line_pointer
)
10823 case REGISTER_PREFIX
:
10824 r
= parse_real_register (input_line_pointer
, &end
);
10827 e
->X_op
= O_register
;
10828 e
->X_add_number
= r
- i386_regtab
;
10829 input_line_pointer
= end
;
10834 gas_assert (intel_syntax
);
10835 end
= input_line_pointer
++;
10837 if (*input_line_pointer
== ']')
10839 ++input_line_pointer
;
10840 e
->X_op_symbol
= make_expr_symbol (e
);
10841 e
->X_add_symbol
= NULL
;
10842 e
->X_add_number
= 0;
10847 e
->X_op
= O_absent
;
10848 input_line_pointer
= end
;
10855 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10856 const char *md_shortopts
= "kVQ:sqnO::";
10858 const char *md_shortopts
= "qnO::";
10861 #define OPTION_32 (OPTION_MD_BASE + 0)
10862 #define OPTION_64 (OPTION_MD_BASE + 1)
10863 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10864 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10865 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10866 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10867 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10868 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10869 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10870 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10871 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10872 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10873 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10874 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10875 #define OPTION_X32 (OPTION_MD_BASE + 14)
10876 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10877 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10878 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10879 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10880 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10881 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10882 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10883 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10884 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10885 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10886 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10888 struct option md_longopts
[] =
10890 {"32", no_argument
, NULL
, OPTION_32
},
10891 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10892 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10893 {"64", no_argument
, NULL
, OPTION_64
},
10895 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10896 {"x32", no_argument
, NULL
, OPTION_X32
},
10897 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10898 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
10900 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10901 {"march", required_argument
, NULL
, OPTION_MARCH
},
10902 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10903 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10904 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10905 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10906 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10907 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10908 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10909 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10910 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10911 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10912 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10913 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10914 # if defined (TE_PE) || defined (TE_PEP)
10915 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10917 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10918 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10919 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10920 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10921 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10922 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10923 {NULL
, no_argument
, NULL
, 0}
10925 size_t md_longopts_size
= sizeof (md_longopts
);
10928 md_parse_option (int c
, const char *arg
)
10931 char *arch
, *next
, *saved
;
10936 optimize_align_code
= 0;
10940 quiet_warnings
= 1;
10943 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10944 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10945 should be emitted or not. FIXME: Not implemented. */
10949 /* -V: SVR4 argument to print version ID. */
10951 print_version_id ();
10954 /* -k: Ignore for FreeBSD compatibility. */
10959 /* -s: On i386 Solaris, this tells the native assembler to use
10960 .stab instead of .stab.excl. We always use .stab anyhow. */
10963 case OPTION_MSHARED
:
10967 case OPTION_X86_USED_NOTE
:
10968 if (strcasecmp (arg
, "yes") == 0)
10970 else if (strcasecmp (arg
, "no") == 0)
10973 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
10978 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10979 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10982 const char **list
, **l
;
10984 list
= bfd_target_list ();
10985 for (l
= list
; *l
!= NULL
; l
++)
10986 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10987 || strcmp (*l
, "coff-x86-64") == 0
10988 || strcmp (*l
, "pe-x86-64") == 0
10989 || strcmp (*l
, "pei-x86-64") == 0
10990 || strcmp (*l
, "mach-o-x86-64") == 0)
10992 default_arch
= "x86_64";
10996 as_fatal (_("no compiled in support for x86_64"));
11002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11006 const char **list
, **l
;
11008 list
= bfd_target_list ();
11009 for (l
= list
; *l
!= NULL
; l
++)
11010 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11012 default_arch
= "x86_64:32";
11016 as_fatal (_("no compiled in support for 32bit x86_64"));
11020 as_fatal (_("32bit x86_64 is only supported for ELF"));
11025 default_arch
= "i386";
11028 case OPTION_DIVIDE
:
11029 #ifdef SVR4_COMMENT_CHARS
11034 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11036 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11040 i386_comment_chars
= n
;
11046 saved
= xstrdup (arg
);
11048 /* Allow -march=+nosse. */
11054 as_fatal (_("invalid -march= option: `%s'"), arg
);
11055 next
= strchr (arch
, '+');
11058 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11060 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11063 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11066 cpu_arch_name
= cpu_arch
[j
].name
;
11067 cpu_sub_arch_name
= NULL
;
11068 cpu_arch_flags
= cpu_arch
[j
].flags
;
11069 cpu_arch_isa
= cpu_arch
[j
].type
;
11070 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11071 if (!cpu_arch_tune_set
)
11073 cpu_arch_tune
= cpu_arch_isa
;
11074 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11078 else if (*cpu_arch
[j
].name
== '.'
11079 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11081 /* ISA extension. */
11082 i386_cpu_flags flags
;
11084 flags
= cpu_flags_or (cpu_arch_flags
,
11085 cpu_arch
[j
].flags
);
11087 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11089 if (cpu_sub_arch_name
)
11091 char *name
= cpu_sub_arch_name
;
11092 cpu_sub_arch_name
= concat (name
,
11094 (const char *) NULL
);
11098 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11099 cpu_arch_flags
= flags
;
11100 cpu_arch_isa_flags
= flags
;
11104 = cpu_flags_or (cpu_arch_isa_flags
,
11105 cpu_arch
[j
].flags
);
11110 if (j
>= ARRAY_SIZE (cpu_arch
))
11112 /* Disable an ISA extension. */
11113 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11114 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11116 i386_cpu_flags flags
;
11118 flags
= cpu_flags_and_not (cpu_arch_flags
,
11119 cpu_noarch
[j
].flags
);
11120 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11122 if (cpu_sub_arch_name
)
11124 char *name
= cpu_sub_arch_name
;
11125 cpu_sub_arch_name
= concat (arch
,
11126 (const char *) NULL
);
11130 cpu_sub_arch_name
= xstrdup (arch
);
11131 cpu_arch_flags
= flags
;
11132 cpu_arch_isa_flags
= flags
;
11137 if (j
>= ARRAY_SIZE (cpu_noarch
))
11138 j
= ARRAY_SIZE (cpu_arch
);
11141 if (j
>= ARRAY_SIZE (cpu_arch
))
11142 as_fatal (_("invalid -march= option: `%s'"), arg
);
11146 while (next
!= NULL
);
11152 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11153 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11155 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11157 cpu_arch_tune_set
= 1;
11158 cpu_arch_tune
= cpu_arch
[j
].type
;
11159 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11163 if (j
>= ARRAY_SIZE (cpu_arch
))
11164 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11167 case OPTION_MMNEMONIC
:
11168 if (strcasecmp (arg
, "att") == 0)
11169 intel_mnemonic
= 0;
11170 else if (strcasecmp (arg
, "intel") == 0)
11171 intel_mnemonic
= 1;
11173 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11176 case OPTION_MSYNTAX
:
11177 if (strcasecmp (arg
, "att") == 0)
11179 else if (strcasecmp (arg
, "intel") == 0)
11182 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11185 case OPTION_MINDEX_REG
:
11186 allow_index_reg
= 1;
11189 case OPTION_MNAKED_REG
:
11190 allow_naked_reg
= 1;
11193 case OPTION_MSSE2AVX
:
11197 case OPTION_MSSE_CHECK
:
11198 if (strcasecmp (arg
, "error") == 0)
11199 sse_check
= check_error
;
11200 else if (strcasecmp (arg
, "warning") == 0)
11201 sse_check
= check_warning
;
11202 else if (strcasecmp (arg
, "none") == 0)
11203 sse_check
= check_none
;
11205 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11208 case OPTION_MOPERAND_CHECK
:
11209 if (strcasecmp (arg
, "error") == 0)
11210 operand_check
= check_error
;
11211 else if (strcasecmp (arg
, "warning") == 0)
11212 operand_check
= check_warning
;
11213 else if (strcasecmp (arg
, "none") == 0)
11214 operand_check
= check_none
;
11216 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11219 case OPTION_MAVXSCALAR
:
11220 if (strcasecmp (arg
, "128") == 0)
11221 avxscalar
= vex128
;
11222 else if (strcasecmp (arg
, "256") == 0)
11223 avxscalar
= vex256
;
11225 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11228 case OPTION_MADD_BND_PREFIX
:
11229 add_bnd_prefix
= 1;
11232 case OPTION_MEVEXLIG
:
11233 if (strcmp (arg
, "128") == 0)
11234 evexlig
= evexl128
;
11235 else if (strcmp (arg
, "256") == 0)
11236 evexlig
= evexl256
;
11237 else if (strcmp (arg
, "512") == 0)
11238 evexlig
= evexl512
;
11240 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11243 case OPTION_MEVEXRCIG
:
11244 if (strcmp (arg
, "rne") == 0)
11246 else if (strcmp (arg
, "rd") == 0)
11248 else if (strcmp (arg
, "ru") == 0)
11250 else if (strcmp (arg
, "rz") == 0)
11253 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11256 case OPTION_MEVEXWIG
:
11257 if (strcmp (arg
, "0") == 0)
11259 else if (strcmp (arg
, "1") == 0)
11262 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11265 # if defined (TE_PE) || defined (TE_PEP)
11266 case OPTION_MBIG_OBJ
:
11271 case OPTION_MOMIT_LOCK_PREFIX
:
11272 if (strcasecmp (arg
, "yes") == 0)
11273 omit_lock_prefix
= 1;
11274 else if (strcasecmp (arg
, "no") == 0)
11275 omit_lock_prefix
= 0;
11277 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11280 case OPTION_MFENCE_AS_LOCK_ADD
:
11281 if (strcasecmp (arg
, "yes") == 0)
11283 else if (strcasecmp (arg
, "no") == 0)
11286 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11289 case OPTION_MRELAX_RELOCATIONS
:
11290 if (strcasecmp (arg
, "yes") == 0)
11291 generate_relax_relocations
= 1;
11292 else if (strcasecmp (arg
, "no") == 0)
11293 generate_relax_relocations
= 0;
11295 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11298 case OPTION_MAMD64
:
11302 case OPTION_MINTEL64
:
11310 /* Turn off -Os. */
11311 optimize_for_space
= 0;
11313 else if (*arg
== 's')
11315 optimize_for_space
= 1;
11316 /* Turn on all encoding optimizations. */
11321 optimize
= atoi (arg
);
11322 /* Turn off -Os. */
11323 optimize_for_space
= 0;
11333 #define MESSAGE_TEMPLATE \
11337 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11338 int *left_p
, const char *name
, int len
)
11340 int size
= sizeof (MESSAGE_TEMPLATE
);
11341 int left
= *left_p
;
11343 /* Reserve 2 spaces for ", " or ",\0" */
11346 /* Check if there is any room. */
11354 p
= mempcpy (p
, name
, len
);
11358 /* Output the current message now and start a new one. */
11361 fprintf (stream
, "%s\n", message
);
11363 left
= size
- (start
- message
) - len
- 2;
11365 gas_assert (left
>= 0);
11367 p
= mempcpy (p
, name
, len
);
11375 show_arch (FILE *stream
, int ext
, int check
)
11377 static char message
[] = MESSAGE_TEMPLATE
;
11378 char *start
= message
+ 27;
11380 int size
= sizeof (MESSAGE_TEMPLATE
);
11387 left
= size
- (start
- message
);
11388 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11390 /* Should it be skipped? */
11391 if (cpu_arch
[j
].skip
)
11394 name
= cpu_arch
[j
].name
;
11395 len
= cpu_arch
[j
].len
;
11398 /* It is an extension. Skip if we aren't asked to show it. */
11409 /* It is an processor. Skip if we show only extension. */
11412 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11414 /* It is an impossible processor - skip. */
11418 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11421 /* Display disabled extensions. */
11423 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11425 name
= cpu_noarch
[j
].name
;
11426 len
= cpu_noarch
[j
].len
;
11427 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11432 fprintf (stream
, "%s\n", message
);
11436 md_show_usage (FILE *stream
)
11438 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11439 fprintf (stream
, _("\
11441 -V print assembler version number\n\
11444 fprintf (stream
, _("\
11445 -n Do not optimize code alignment\n\
11446 -q quieten some warnings\n"));
11447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11448 fprintf (stream
, _("\
11451 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11452 || defined (TE_PE) || defined (TE_PEP))
11453 fprintf (stream
, _("\
11454 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11456 #ifdef SVR4_COMMENT_CHARS
11457 fprintf (stream
, _("\
11458 --divide do not treat `/' as a comment character\n"));
11460 fprintf (stream
, _("\
11461 --divide ignored\n"));
11463 fprintf (stream
, _("\
11464 -march=CPU[,+EXTENSION...]\n\
11465 generate code for CPU and EXTENSION, CPU is one of:\n"));
11466 show_arch (stream
, 0, 1);
11467 fprintf (stream
, _("\
11468 EXTENSION is combination of:\n"));
11469 show_arch (stream
, 1, 0);
11470 fprintf (stream
, _("\
11471 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11472 show_arch (stream
, 0, 0);
11473 fprintf (stream
, _("\
11474 -msse2avx encode SSE instructions with VEX prefix\n"));
11475 fprintf (stream
, _("\
11476 -msse-check=[none|error|warning] (default: warning)\n\
11477 check SSE instructions\n"));
11478 fprintf (stream
, _("\
11479 -moperand-check=[none|error|warning] (default: warning)\n\
11480 check operand combinations for validity\n"));
11481 fprintf (stream
, _("\
11482 -mavxscalar=[128|256] (default: 128)\n\
11483 encode scalar AVX instructions with specific vector\n\
11485 fprintf (stream
, _("\
11486 -mevexlig=[128|256|512] (default: 128)\n\
11487 encode scalar EVEX instructions with specific vector\n\
11489 fprintf (stream
, _("\
11490 -mevexwig=[0|1] (default: 0)\n\
11491 encode EVEX instructions with specific EVEX.W value\n\
11492 for EVEX.W bit ignored instructions\n"));
11493 fprintf (stream
, _("\
11494 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11495 encode EVEX instructions with specific EVEX.RC value\n\
11496 for SAE-only ignored instructions\n"));
11497 fprintf (stream
, _("\
11498 -mmnemonic=[att|intel] "));
11499 if (SYSV386_COMPAT
)
11500 fprintf (stream
, _("(default: att)\n"));
11502 fprintf (stream
, _("(default: intel)\n"));
11503 fprintf (stream
, _("\
11504 use AT&T/Intel mnemonic\n"));
11505 fprintf (stream
, _("\
11506 -msyntax=[att|intel] (default: att)\n\
11507 use AT&T/Intel syntax\n"));
11508 fprintf (stream
, _("\
11509 -mindex-reg support pseudo index registers\n"));
11510 fprintf (stream
, _("\
11511 -mnaked-reg don't require `%%' prefix for registers\n"));
11512 fprintf (stream
, _("\
11513 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11514 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11515 fprintf (stream
, _("\
11516 -mshared disable branch optimization for shared code\n"));
11517 fprintf (stream
, _("\
11518 -mx86-used-note=[no|yes] "));
11519 if (DEFAULT_X86_USED_NOTE
)
11520 fprintf (stream
, _("(default: yes)\n"));
11522 fprintf (stream
, _("(default: no)\n"));
11523 fprintf (stream
, _("\
11524 generate x86 used ISA and feature properties\n"));
11526 #if defined (TE_PE) || defined (TE_PEP)
11527 fprintf (stream
, _("\
11528 -mbig-obj generate big object files\n"));
11530 fprintf (stream
, _("\
11531 -momit-lock-prefix=[no|yes] (default: no)\n\
11532 strip all lock prefixes\n"));
11533 fprintf (stream
, _("\
11534 -mfence-as-lock-add=[no|yes] (default: no)\n\
11535 encode lfence, mfence and sfence as\n\
11536 lock addl $0x0, (%%{re}sp)\n"));
11537 fprintf (stream
, _("\
11538 -mrelax-relocations=[no|yes] "));
11539 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11540 fprintf (stream
, _("(default: yes)\n"));
11542 fprintf (stream
, _("(default: no)\n"));
11543 fprintf (stream
, _("\
11544 generate relax relocations\n"));
11545 fprintf (stream
, _("\
11546 -mamd64 accept only AMD64 ISA [default]\n"));
11547 fprintf (stream
, _("\
11548 -mintel64 accept only Intel64 ISA\n"));
11551 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11552 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11553 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11555 /* Pick the target format to use. */
11558 i386_target_format (void)
11560 if (!strncmp (default_arch
, "x86_64", 6))
11562 update_code_flag (CODE_64BIT
, 1);
11563 if (default_arch
[6] == '\0')
11564 x86_elf_abi
= X86_64_ABI
;
11566 x86_elf_abi
= X86_64_X32_ABI
;
11568 else if (!strcmp (default_arch
, "i386"))
11569 update_code_flag (CODE_32BIT
, 1);
11570 else if (!strcmp (default_arch
, "iamcu"))
11572 update_code_flag (CODE_32BIT
, 1);
11573 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11575 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11576 cpu_arch_name
= "iamcu";
11577 cpu_sub_arch_name
= NULL
;
11578 cpu_arch_flags
= iamcu_flags
;
11579 cpu_arch_isa
= PROCESSOR_IAMCU
;
11580 cpu_arch_isa_flags
= iamcu_flags
;
11581 if (!cpu_arch_tune_set
)
11583 cpu_arch_tune
= cpu_arch_isa
;
11584 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11587 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11588 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11592 as_fatal (_("unknown architecture"));
11594 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11595 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11596 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11597 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11599 switch (OUTPUT_FLAVOR
)
11601 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11602 case bfd_target_aout_flavour
:
11603 return AOUT_TARGET_FORMAT
;
11605 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11606 # if defined (TE_PE) || defined (TE_PEP)
11607 case bfd_target_coff_flavour
:
11608 if (flag_code
== CODE_64BIT
)
11609 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11612 # elif defined (TE_GO32)
11613 case bfd_target_coff_flavour
:
11614 return "coff-go32";
11616 case bfd_target_coff_flavour
:
11617 return "coff-i386";
11620 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11621 case bfd_target_elf_flavour
:
11623 const char *format
;
11625 switch (x86_elf_abi
)
11628 format
= ELF_TARGET_FORMAT
;
11631 use_rela_relocations
= 1;
11633 format
= ELF_TARGET_FORMAT64
;
11635 case X86_64_X32_ABI
:
11636 use_rela_relocations
= 1;
11638 disallow_64bit_reloc
= 1;
11639 format
= ELF_TARGET_FORMAT32
;
11642 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11644 if (x86_elf_abi
!= X86_64_ABI
)
11645 as_fatal (_("Intel L1OM is 64bit only"));
11646 return ELF_TARGET_L1OM_FORMAT
;
11648 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11650 if (x86_elf_abi
!= X86_64_ABI
)
11651 as_fatal (_("Intel K1OM is 64bit only"));
11652 return ELF_TARGET_K1OM_FORMAT
;
11654 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11656 if (x86_elf_abi
!= I386_ABI
)
11657 as_fatal (_("Intel MCU is 32bit only"));
11658 return ELF_TARGET_IAMCU_FORMAT
;
11664 #if defined (OBJ_MACH_O)
11665 case bfd_target_mach_o_flavour
:
11666 if (flag_code
== CODE_64BIT
)
11668 use_rela_relocations
= 1;
11670 return "mach-o-x86-64";
11673 return "mach-o-i386";
11681 #endif /* OBJ_MAYBE_ more than one */
11684 md_undefined_symbol (char *name
)
11686 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11687 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11688 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11689 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11693 if (symbol_find (name
))
11694 as_bad (_("GOT already in symbol table"));
11695 GOT_symbol
= symbol_new (name
, undefined_section
,
11696 (valueT
) 0, &zero_address_frag
);
11703 /* Round up a section size to the appropriate boundary. */
11706 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11708 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11709 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11711 /* For a.out, force the section size to be aligned. If we don't do
11712 this, BFD will align it for us, but it will not write out the
11713 final bytes of the section. This may be a bug in BFD, but it is
11714 easier to fix it here since that is how the other a.out targets
11718 align
= bfd_get_section_alignment (stdoutput
, segment
);
11719 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11726 /* On the i386, PC-relative offsets are relative to the start of the
11727 next instruction. That is, the address of the offset, plus its
11728 size, since the offset is always the last part of the insn. */
11731 md_pcrel_from (fixS
*fixP
)
11733 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11739 s_bss (int ignore ATTRIBUTE_UNUSED
)
11743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11745 obj_elf_section_change_hook ();
11747 temp
= get_absolute_expression ();
11748 subseg_set (bss_section
, (subsegT
) temp
);
11749 demand_empty_rest_of_line ();
11755 i386_validate_fix (fixS
*fixp
)
11757 if (fixp
->fx_subsy
)
11759 if (fixp
->fx_subsy
== GOT_symbol
)
11761 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11765 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11766 if (fixp
->fx_tcbit2
)
11767 fixp
->fx_r_type
= (fixp
->fx_tcbit
11768 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11769 : BFD_RELOC_X86_64_GOTPCRELX
);
11772 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11777 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11779 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11781 fixp
->fx_subsy
= 0;
11784 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11785 else if (!object_64bit
)
11787 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11788 && fixp
->fx_tcbit2
)
11789 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11795 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11798 bfd_reloc_code_real_type code
;
11800 switch (fixp
->fx_r_type
)
11802 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11803 case BFD_RELOC_SIZE32
:
11804 case BFD_RELOC_SIZE64
:
11805 if (S_IS_DEFINED (fixp
->fx_addsy
)
11806 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11808 /* Resolve size relocation against local symbol to size of
11809 the symbol plus addend. */
11810 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11811 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11812 && !fits_in_unsigned_long (value
))
11813 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11814 _("symbol size computation overflow"));
11815 fixp
->fx_addsy
= NULL
;
11816 fixp
->fx_subsy
= NULL
;
11817 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11821 /* Fall through. */
11823 case BFD_RELOC_X86_64_PLT32
:
11824 case BFD_RELOC_X86_64_GOT32
:
11825 case BFD_RELOC_X86_64_GOTPCREL
:
11826 case BFD_RELOC_X86_64_GOTPCRELX
:
11827 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11828 case BFD_RELOC_386_PLT32
:
11829 case BFD_RELOC_386_GOT32
:
11830 case BFD_RELOC_386_GOT32X
:
11831 case BFD_RELOC_386_GOTOFF
:
11832 case BFD_RELOC_386_GOTPC
:
11833 case BFD_RELOC_386_TLS_GD
:
11834 case BFD_RELOC_386_TLS_LDM
:
11835 case BFD_RELOC_386_TLS_LDO_32
:
11836 case BFD_RELOC_386_TLS_IE_32
:
11837 case BFD_RELOC_386_TLS_IE
:
11838 case BFD_RELOC_386_TLS_GOTIE
:
11839 case BFD_RELOC_386_TLS_LE_32
:
11840 case BFD_RELOC_386_TLS_LE
:
11841 case BFD_RELOC_386_TLS_GOTDESC
:
11842 case BFD_RELOC_386_TLS_DESC_CALL
:
11843 case BFD_RELOC_X86_64_TLSGD
:
11844 case BFD_RELOC_X86_64_TLSLD
:
11845 case BFD_RELOC_X86_64_DTPOFF32
:
11846 case BFD_RELOC_X86_64_DTPOFF64
:
11847 case BFD_RELOC_X86_64_GOTTPOFF
:
11848 case BFD_RELOC_X86_64_TPOFF32
:
11849 case BFD_RELOC_X86_64_TPOFF64
:
11850 case BFD_RELOC_X86_64_GOTOFF64
:
11851 case BFD_RELOC_X86_64_GOTPC32
:
11852 case BFD_RELOC_X86_64_GOT64
:
11853 case BFD_RELOC_X86_64_GOTPCREL64
:
11854 case BFD_RELOC_X86_64_GOTPC64
:
11855 case BFD_RELOC_X86_64_GOTPLT64
:
11856 case BFD_RELOC_X86_64_PLTOFF64
:
11857 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11858 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11859 case BFD_RELOC_RVA
:
11860 case BFD_RELOC_VTABLE_ENTRY
:
11861 case BFD_RELOC_VTABLE_INHERIT
:
11863 case BFD_RELOC_32_SECREL
:
11865 code
= fixp
->fx_r_type
;
11867 case BFD_RELOC_X86_64_32S
:
11868 if (!fixp
->fx_pcrel
)
11870 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11871 code
= fixp
->fx_r_type
;
11874 /* Fall through. */
11876 if (fixp
->fx_pcrel
)
11878 switch (fixp
->fx_size
)
11881 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11882 _("can not do %d byte pc-relative relocation"),
11884 code
= BFD_RELOC_32_PCREL
;
11886 case 1: code
= BFD_RELOC_8_PCREL
; break;
11887 case 2: code
= BFD_RELOC_16_PCREL
; break;
11888 case 4: code
= BFD_RELOC_32_PCREL
; break;
11890 case 8: code
= BFD_RELOC_64_PCREL
; break;
11896 switch (fixp
->fx_size
)
11899 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11900 _("can not do %d byte relocation"),
11902 code
= BFD_RELOC_32
;
11904 case 1: code
= BFD_RELOC_8
; break;
11905 case 2: code
= BFD_RELOC_16
; break;
11906 case 4: code
= BFD_RELOC_32
; break;
11908 case 8: code
= BFD_RELOC_64
; break;
11915 if ((code
== BFD_RELOC_32
11916 || code
== BFD_RELOC_32_PCREL
11917 || code
== BFD_RELOC_X86_64_32S
)
11919 && fixp
->fx_addsy
== GOT_symbol
)
11922 code
= BFD_RELOC_386_GOTPC
;
11924 code
= BFD_RELOC_X86_64_GOTPC32
;
11926 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11928 && fixp
->fx_addsy
== GOT_symbol
)
11930 code
= BFD_RELOC_X86_64_GOTPC64
;
11933 rel
= XNEW (arelent
);
11934 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11935 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11937 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11939 if (!use_rela_relocations
)
11941 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11942 vtable entry to be used in the relocation's section offset. */
11943 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11944 rel
->address
= fixp
->fx_offset
;
11945 #if defined (OBJ_COFF) && defined (TE_PE)
11946 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11947 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11952 /* Use the rela in 64bit mode. */
11955 if (disallow_64bit_reloc
)
11958 case BFD_RELOC_X86_64_DTPOFF64
:
11959 case BFD_RELOC_X86_64_TPOFF64
:
11960 case BFD_RELOC_64_PCREL
:
11961 case BFD_RELOC_X86_64_GOTOFF64
:
11962 case BFD_RELOC_X86_64_GOT64
:
11963 case BFD_RELOC_X86_64_GOTPCREL64
:
11964 case BFD_RELOC_X86_64_GOTPC64
:
11965 case BFD_RELOC_X86_64_GOTPLT64
:
11966 case BFD_RELOC_X86_64_PLTOFF64
:
11967 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11968 _("cannot represent relocation type %s in x32 mode"),
11969 bfd_get_reloc_code_name (code
));
11975 if (!fixp
->fx_pcrel
)
11976 rel
->addend
= fixp
->fx_offset
;
11980 case BFD_RELOC_X86_64_PLT32
:
11981 case BFD_RELOC_X86_64_GOT32
:
11982 case BFD_RELOC_X86_64_GOTPCREL
:
11983 case BFD_RELOC_X86_64_GOTPCRELX
:
11984 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11985 case BFD_RELOC_X86_64_TLSGD
:
11986 case BFD_RELOC_X86_64_TLSLD
:
11987 case BFD_RELOC_X86_64_GOTTPOFF
:
11988 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11989 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11990 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11993 rel
->addend
= (section
->vma
11995 + fixp
->fx_addnumber
11996 + md_pcrel_from (fixp
));
12001 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12002 if (rel
->howto
== NULL
)
12004 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12005 _("cannot represent relocation type %s"),
12006 bfd_get_reloc_code_name (code
));
12007 /* Set howto to a garbage value so that we can keep going. */
12008 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12009 gas_assert (rel
->howto
!= NULL
);
12015 #include "tc-i386-intel.c"
12018 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12020 int saved_naked_reg
;
12021 char saved_register_dot
;
12023 saved_naked_reg
= allow_naked_reg
;
12024 allow_naked_reg
= 1;
12025 saved_register_dot
= register_chars
['.'];
12026 register_chars
['.'] = '.';
12027 allow_pseudo_reg
= 1;
12028 expression_and_evaluate (exp
);
12029 allow_pseudo_reg
= 0;
12030 register_chars
['.'] = saved_register_dot
;
12031 allow_naked_reg
= saved_naked_reg
;
12033 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12035 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12037 exp
->X_op
= O_constant
;
12038 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12039 .dw2_regnum
[flag_code
>> 1];
12042 exp
->X_op
= O_illegal
;
12047 tc_x86_frame_initial_instructions (void)
12049 static unsigned int sp_regno
[2];
12051 if (!sp_regno
[flag_code
>> 1])
12053 char *saved_input
= input_line_pointer
;
12054 char sp
[][4] = {"esp", "rsp"};
12057 input_line_pointer
= sp
[flag_code
>> 1];
12058 tc_x86_parse_to_dw2regnum (&exp
);
12059 gas_assert (exp
.X_op
== O_constant
);
12060 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12061 input_line_pointer
= saved_input
;
12064 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12065 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12069 x86_dwarf2_addr_size (void)
12071 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12072 if (x86_elf_abi
== X86_64_X32_ABI
)
12075 return bfd_arch_bits_per_address (stdoutput
) / 8;
12079 i386_elf_section_type (const char *str
, size_t len
)
12081 if (flag_code
== CODE_64BIT
12082 && len
== sizeof ("unwind") - 1
12083 && strncmp (str
, "unwind", 6) == 0)
12084 return SHT_X86_64_UNWIND
;
12091 i386_solaris_fix_up_eh_frame (segT sec
)
12093 if (flag_code
== CODE_64BIT
)
12094 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12100 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12104 exp
.X_op
= O_secrel
;
12105 exp
.X_add_symbol
= symbol
;
12106 exp
.X_add_number
= 0;
12107 emit_expr (&exp
, size
);
12111 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12112 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12115 x86_64_section_letter (int letter
, const char **ptr_msg
)
12117 if (flag_code
== CODE_64BIT
)
12120 return SHF_X86_64_LARGE
;
12122 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12125 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12130 x86_64_section_word (char *str
, size_t len
)
12132 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12133 return SHF_X86_64_LARGE
;
12139 handle_large_common (int small ATTRIBUTE_UNUSED
)
12141 if (flag_code
!= CODE_64BIT
)
12143 s_comm_internal (0, elf_common_parse
);
12144 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12148 static segT lbss_section
;
12149 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12150 asection
*saved_bss_section
= bss_section
;
12152 if (lbss_section
== NULL
)
12154 flagword applicable
;
12155 segT seg
= now_seg
;
12156 subsegT subseg
= now_subseg
;
12158 /* The .lbss section is for local .largecomm symbols. */
12159 lbss_section
= subseg_new (".lbss", 0);
12160 applicable
= bfd_applicable_section_flags (stdoutput
);
12161 bfd_set_section_flags (stdoutput
, lbss_section
,
12162 applicable
& SEC_ALLOC
);
12163 seg_info (lbss_section
)->bss
= 1;
12165 subseg_set (seg
, subseg
);
12168 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12169 bss_section
= lbss_section
;
12171 s_comm_internal (0, elf_common_parse
);
12173 elf_com_section_ptr
= saved_com_section_ptr
;
12174 bss_section
= saved_bss_section
;
12177 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */