1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
265 unsupported_with_intel_mnemonic
,
268 invalid_vsib_address
,
269 invalid_vector_register_set
,
270 unsupported_vector_index_register
,
271 unsupported_broadcast
,
272 broadcast_not_on_src_operand
,
275 mask_not_on_destination
,
278 rc_sae_operand_not_last_imm
,
279 invalid_register_operand
,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands
;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types
[MAX_OPERANDS
];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op
[MAX_OPERANDS
];
307 /* Flags for operands. */
308 unsigned int flags
[MAX_OPERANDS
];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry
*base_reg
;
317 const reg_entry
*index_reg
;
318 unsigned int log2_scale_factor
;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry
*seg
[2];
324 /* Copied first memory operand string, for re-checking. */
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes
;
330 unsigned char prefix
[MAX_PREFIXES
];
332 /* RM and SIB are the modrm byte and the sib byte where the
333 addressing modes of this insn are encoded. */
340 /* Masking attributes. */
341 struct Mask_Operation
*mask
;
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation
*rounding
;
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation
*broadcast
;
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift
;
352 /* Prefer load or store in encoding. */
355 dir_encoding_default
= 0,
360 /* Prefer 8bit or 32bit displacement in encoding. */
363 disp_encoding_default
= 0,
368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding
;
371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize
;
374 /* How to encode vector instructions. */
377 vex_encoding_default
= 0,
384 const char *rep_prefix
;
387 const char *hle_prefix
;
389 /* Have BND prefix. */
390 const char *bnd_prefix
;
392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix
;
396 enum i386_error error
;
399 typedef struct _i386_insn i386_insn
;
401 /* Link RC type with corresponding string, that'll be looked for in
410 static const struct RC_name RC_NamesTable
[] =
412 { rne
, STRING_COMMA_LEN ("rn-sae") },
413 { rd
, STRING_COMMA_LEN ("rd-sae") },
414 { ru
, STRING_COMMA_LEN ("ru-sae") },
415 { rz
, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly
, STRING_COMMA_LEN ("sae") },
419 /* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
421 const char extra_symbol_chars
[] = "*%-([{}"
430 #if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
432 && !defined (TE_GNU) \
433 && !defined (TE_LINUX) \
434 && !defined (TE_NACL) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars
= "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
446 const char *i386_comment_chars
= "#";
447 #define PREFIX_SEPARATOR '/'
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars
[] = "#/";
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point
464 const char EXP_CHARS
[] = "eE";
466 /* Chars that mean this number is a floating point constant
469 const char FLT_CHARS
[] = "fFdDxX";
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars
[256];
473 static char register_chars
[256];
474 static char operand_chars
[256];
475 static char identifier_chars
[256];
476 static char digit_chars
[256];
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack
[32];
494 static char *save_stack_p
;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
500 /* The instruction we're assembling. */
503 /* Possible templates for current insn. */
504 static const templates
*current_templates
;
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
508 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
510 /* Current operand we are working on. */
511 static int this_operand
= -1;
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
521 static enum flag_code flag_code
;
522 static unsigned int object_64bit
;
523 static unsigned int disallow_64bit_reloc
;
524 static int use_rela_relocations
= 0;
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
530 /* The ELF ABI to use. */
538 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj
= 0;
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared
= 0;
551 /* 1 for intel syntax,
553 static int intel_syntax
= 0;
555 /* 1 for Intel64 ISA,
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic
= !SYSV386_COMPAT
;
563 /* 1 if pseudo registers are permitted. */
564 static int allow_pseudo_reg
= 0;
566 /* 1 if register prefix % not required. */
567 static int allow_naked_reg
= 0;
569 /* 1 if the assembler should add BND prefix for all control-transferring
570 instructions supporting it, even if this prefix wasn't specified
572 static int add_bnd_prefix
= 0;
574 /* 1 if pseudo index register, eiz/riz, is allowed . */
575 static int allow_index_reg
= 0;
577 /* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579 static int omit_lock_prefix
= 0;
581 /* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583 static int avoid_fence
= 0;
585 /* 1 if the assembler should generate relax relocations. */
587 static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
590 static enum check_kind
596 sse_check
, operand_check
= check_warning
;
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
603 static int optimize
= 0;
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
612 static int optimize_for_space
= 0;
614 /* Register prefix used for error message. */
615 static const char *register_prefix
= "%";
617 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620 static char stackop_size
= '\0';
622 /* Non-zero to optimize code alignment. */
623 int optimize_align_code
= 1;
625 /* Non-zero to quieten some warnings. */
626 static int quiet_warnings
= 0;
629 static const char *cpu_arch_name
= NULL
;
630 static char *cpu_sub_arch_name
= NULL
;
632 /* CPU feature flags. */
633 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
635 /* If we have selected a cpu we are generating instructions for. */
636 static int cpu_arch_tune_set
= 0;
638 /* Cpu we are generating instructions for. */
639 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
641 /* CPU feature flags of cpu we are generating instructions for. */
642 static i386_cpu_flags cpu_arch_tune_flags
;
644 /* CPU instruction set architecture used. */
645 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
647 /* CPU feature flags of instruction set architecture used. */
648 i386_cpu_flags cpu_arch_isa_flags
;
650 /* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652 static unsigned int no_cond_jump_promotion
= 0;
654 /* Encode SSE instructions with VEX prefix. */
655 static unsigned int sse2avx
;
657 /* Encode scalar AVX instructions with specific vector length. */
664 /* Encode scalar EVEX LIG instructions with specific vector length. */
672 /* Encode EVEX WIG instructions with specific evex.w. */
679 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
680 static enum rc_type evexrcig
= rne
;
682 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
683 static symbolS
*GOT_symbol
;
685 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
686 unsigned int x86_dwarf2_return_column
;
688 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689 int x86_cie_data_alignment
;
691 /* Interface to relax_segment.
692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
697 #define UNCOND_JUMP 0
699 #define COND_JUMP86 2
704 #define SMALL16 (SMALL | CODE16)
706 #define BIG16 (BIG | CODE16)
710 #define INLINE __inline__
716 #define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718 #define TYPE_FROM_RELAX_STATE(s) \
720 #define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
723 /* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
731 const relax_typeS md_relax_table
[] =
734 1) most positive reach of this state,
735 2) most negative reach of this state,
736 3) how many bytes this mode will have in the variable part of the frag
737 4) which index into the table to try if we can't fit into this one. */
739 /* UNCOND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 3 bytes to frag:
756 1 extra opcode byte, 2 displacement bytes. */
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
770 static const arch_entry cpu_arch
[] =
772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
775 CPU_GENERIC32_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
777 CPU_GENERIC64_FLAGS
, 0 },
778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
795 CPU_PENTIUMPRO_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
805 CPU_NOCONA_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
811 CPU_CORE2_FLAGS
, 1 },
812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
813 CPU_CORE2_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
815 CPU_COREI7_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
821 CPU_IAMCU_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
827 CPU_ATHLON_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
835 CPU_AMDFAM10_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
837 CPU_BDVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
839 CPU_BDVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
841 CPU_BDVER3_FLAGS
, 0 },
842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
843 CPU_BDVER4_FLAGS
, 0 },
844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
845 CPU_ZNVER1_FLAGS
, 0 },
846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
847 CPU_ZNVER2_FLAGS
, 0 },
848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
849 CPU_BTVER1_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
851 CPU_BTVER2_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
869 CPU_SSSE3_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
871 CPU_SSE4_1_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
873 CPU_SSE4_2_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
875 CPU_SSE4_2_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512F_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
883 CPU_AVX512CD_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
885 CPU_AVX512ER_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
887 CPU_AVX512PF_FLAGS
, 0 },
888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
889 CPU_AVX512DQ_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
891 CPU_AVX512BW_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
893 CPU_AVX512VL_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
897 CPU_VMFUNC_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
901 CPU_XSAVE_FLAGS
, 0 },
902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
903 CPU_XSAVEOPT_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
905 CPU_XSAVEC_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
907 CPU_XSAVES_FLAGS
, 0 },
908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
911 CPU_PCLMUL_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
913 CPU_PCLMUL_FLAGS
, 1 },
914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
915 CPU_FSGSBASE_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
917 CPU_RDRND_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
931 CPU_MOVBE_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
937 CPU_LZCNT_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
943 CPU_INVPCID_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
945 CPU_CLFLUSH_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
949 CPU_SYSCALL_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
951 CPU_RDTSCP_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
953 CPU_3DNOW_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
955 CPU_3DNOWA_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
957 CPU_PADLOCK_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
963 CPU_SSE4A_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
973 CPU_RDSEED_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
975 CPU_PRFCHW_FLAGS
, 0 },
976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
983 CPU_CLFLUSHOPT_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
985 CPU_PREFETCHWT1_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
991 CPU_AVX512IFMA_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
993 CPU_AVX512VBMI_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
995 CPU_AVX512_4FMAPS_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512_4VNNIW_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512_VBMI2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512_VNNI_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512_BITALG_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1007 CPU_CLZERO_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1009 CPU_MWAITX_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1011 CPU_OSPKE_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1013 CPU_RDPID_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1015 CPU_PTWRITE_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1019 CPU_SHSTK_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1021 CPU_GFNI_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1023 CPU_VAES_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1025 CPU_VPCLMULQDQ_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1027 CPU_WBNOINVD_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1029 CPU_PCONFIG_FLAGS
, 0 },
1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1031 CPU_WAITPKG_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1033 CPU_CLDEMOTE_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1035 CPU_MOVDIRI_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1037 CPU_MOVDIR64B_FLAGS
, 0 },
1040 static const noarch_entry cpu_noarch
[] =
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1078 /* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1082 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1089 && *input_line_pointer
== ',')
1091 align
= parse_align (needs_align
- 1);
1093 if (align
== (addressT
) -1)
1108 bss_alloc (symbolP
, size
, align
);
1113 pe_lcomm (int needs_align
)
1115 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1119 const pseudo_typeS md_pseudo_table
[] =
1121 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes
, 0},
1124 {"align", s_align_ptwo
, 0},
1126 {"arch", set_cpu_arch
, 0},
1130 {"lcomm", pe_lcomm
, 1},
1132 {"ffloat", float_cons
, 'f'},
1133 {"dfloat", float_cons
, 'd'},
1134 {"tfloat", float_cons
, 'x'},
1136 {"slong", signed_cons
, 4},
1137 {"noopt", s_ignore
, 0},
1138 {"optim", s_ignore
, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1140 {"code16", set_code_flag
, CODE_16BIT
},
1141 {"code32", set_code_flag
, CODE_32BIT
},
1143 {"code64", set_code_flag
, CODE_64BIT
},
1145 {"intel_syntax", set_intel_syntax
, 1},
1146 {"att_syntax", set_intel_syntax
, 0},
1147 {"intel_mnemonic", set_intel_mnemonic
, 1},
1148 {"att_mnemonic", set_intel_mnemonic
, 0},
1149 {"allow_index_reg", set_allow_index_reg
, 1},
1150 {"disallow_index_reg", set_allow_index_reg
, 0},
1151 {"sse_check", set_check
, 0},
1152 {"operand_check", set_check
, 1},
1153 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common
, 0},
1156 {"file", dwarf2_directive_file
, 0},
1157 {"loc", dwarf2_directive_loc
, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1161 {"secrel32", pe_directive_secrel
, 0},
1166 /* For interface with expression (). */
1167 extern char *input_line_pointer
;
1169 /* Hash table for instruction mnemonic lookup. */
1170 static struct hash_control
*op_hash
;
1172 /* Hash table for register lookup. */
1173 static struct hash_control
*reg_hash
;
1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
1178 static const unsigned char f32_1
[] =
1180 static const unsigned char f32_2
[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182 static const unsigned char f32_3
[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184 static const unsigned char f32_4
[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1186 static const unsigned char f32_6
[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188 static const unsigned char f32_7
[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1190 static const unsigned char f16_3
[] =
1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1192 static const unsigned char f16_4
[] =
1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194 static const unsigned char jump_disp8
[] =
1195 {0xeb}; /* jmp disp8 */
1196 static const unsigned char jump32_disp32
[] =
1197 {0xe9}; /* jmp disp32 */
1198 static const unsigned char jump16_disp32
[] =
1199 {0x66,0xe9}; /* jmp disp32 */
1200 /* 32-bit NOPs patterns. */
1201 static const unsigned char *const f32_patt
[] = {
1202 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1204 /* 16-bit NOPs patterns. */
1205 static const unsigned char *const f16_patt
[] = {
1206 f32_1
, f32_2
, f16_3
, f16_4
1208 /* nopl (%[re]ax) */
1209 static const unsigned char alt_3
[] =
1211 /* nopl 0(%[re]ax) */
1212 static const unsigned char alt_4
[] =
1213 {0x0f,0x1f,0x40,0x00};
1214 /* nopl 0(%[re]ax,%[re]ax,1) */
1215 static const unsigned char alt_5
[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217 /* nopw 0(%[re]ax,%[re]ax,1) */
1218 static const unsigned char alt_6
[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopl 0L(%[re]ax) */
1221 static const unsigned char alt_7
[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223 /* nopl 0L(%[re]ax,%[re]ax,1) */
1224 static const unsigned char alt_8
[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226 /* nopw 0L(%[re]ax,%[re]ax,1) */
1227 static const unsigned char alt_9
[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230 static const unsigned char alt_10
[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* data16 nopw %cs:0L(%eax,%eax,1) */
1233 static const unsigned char alt_11
[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1235 /* 32-bit and 64-bit NOPs patterns. */
1236 static const unsigned char *const alt_patt
[] = {
1237 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1238 alt_9
, alt_10
, alt_11
1241 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1245 i386_output_nops (char *where
, const unsigned char *const *patt
,
1246 int count
, int max_single_nop_size
)
1249 /* Place the longer NOP first. */
1252 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1254 /* Use the smaller one if the requsted one isn't available. */
1257 max_single_nop_size
--;
1258 nops
= patt
[max_single_nop_size
- 1];
1261 last
= count
% max_single_nop_size
;
1264 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1265 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1269 nops
= patt
[last
- 1];
1272 /* Use the smaller one plus one-byte NOP if the needed one
1275 nops
= patt
[last
- 1];
1276 memcpy (where
+ offset
, nops
, last
);
1277 where
[offset
+ last
] = *patt
[0];
1280 memcpy (where
+ offset
, nops
, last
);
1285 fits_in_imm7 (offsetT num
)
1287 return (num
& 0x7f) == num
;
1291 fits_in_imm31 (offsetT num
)
1293 return (num
& 0x7fffffff) == num
;
1296 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1300 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1302 const unsigned char *const *patt
= NULL
;
1303 int max_single_nop_size
;
1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops
;
1307 switch (fragP
->fr_type
)
1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
1321 2. For the rest, alt_patt will be used.
1323 When -mtune= isn't used, alt_patt will be used if
1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1330 if (flag_code
== CODE_16BIT
)
1333 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops
= 2;
1339 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune
)
1344 case PROCESSOR_UNKNOWN
:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
1346 optimize with nops. */
1347 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1352 case PROCESSOR_PENTIUM4
:
1353 case PROCESSOR_NOCONA
:
1354 case PROCESSOR_CORE
:
1355 case PROCESSOR_CORE2
:
1356 case PROCESSOR_COREI7
:
1357 case PROCESSOR_L1OM
:
1358 case PROCESSOR_K1OM
:
1359 case PROCESSOR_GENERIC64
:
1361 case PROCESSOR_ATHLON
:
1363 case PROCESSOR_AMDFAM10
:
1365 case PROCESSOR_ZNVER
:
1369 case PROCESSOR_I386
:
1370 case PROCESSOR_I486
:
1371 case PROCESSOR_PENTIUM
:
1372 case PROCESSOR_PENTIUMPRO
:
1373 case PROCESSOR_IAMCU
:
1374 case PROCESSOR_GENERIC32
:
1381 switch (fragP
->tc_frag_data
.tune
)
1383 case PROCESSOR_UNKNOWN
:
1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1385 PROCESSOR_UNKNOWN. */
1389 case PROCESSOR_I386
:
1390 case PROCESSOR_I486
:
1391 case PROCESSOR_PENTIUM
:
1392 case PROCESSOR_IAMCU
:
1394 case PROCESSOR_ATHLON
:
1396 case PROCESSOR_AMDFAM10
:
1398 case PROCESSOR_ZNVER
:
1400 case PROCESSOR_GENERIC32
:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
1403 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1408 case PROCESSOR_PENTIUMPRO
:
1409 case PROCESSOR_PENTIUM4
:
1410 case PROCESSOR_NOCONA
:
1411 case PROCESSOR_CORE
:
1412 case PROCESSOR_CORE2
:
1413 case PROCESSOR_COREI7
:
1414 case PROCESSOR_L1OM
:
1415 case PROCESSOR_K1OM
:
1416 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1421 case PROCESSOR_GENERIC64
:
1427 if (patt
== f32_patt
)
1429 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops
= 2;
1435 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops
= 7;
1442 limit
= max_single_nop_size
;
1444 if (fragP
->fr_type
== rs_fill_nop
)
1446 /* Output NOPs for .nop directive. */
1447 if (limit
> max_single_nop_size
)
1449 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit
, max_single_nop_size
);
1457 fragP
->fr_var
= count
;
1459 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1461 /* Generate jump over NOPs. */
1462 offsetT disp
= count
- 2;
1463 if (fits_in_imm7 (disp
))
1465 /* Use "jmp disp8" if possible. */
1467 where
[0] = jump_disp8
[0];
1473 unsigned int size_of_jump
;
1475 if (flag_code
== CODE_16BIT
)
1477 where
[0] = jump16_disp32
[0];
1478 where
[1] = jump16_disp32
[1];
1483 where
[0] = jump32_disp32
[0];
1487 count
-= size_of_jump
+ 4;
1488 if (!fits_in_imm31 (count
))
1490 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1491 _("jump over nop padding out of range"));
1495 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1496 where
+= size_of_jump
+ 4;
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where
, patt
, count
, limit
);
1505 operand_type_all_zero (const union i386_operand_type
*x
)
1507 switch (ARRAY_SIZE(x
->array
))
1518 return !x
->array
[0];
1525 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1527 switch (ARRAY_SIZE(x
->array
))
1545 operand_type_equal (const union i386_operand_type
*x
,
1546 const union i386_operand_type
*y
)
1548 switch (ARRAY_SIZE(x
->array
))
1551 if (x
->array
[2] != y
->array
[2])
1555 if (x
->array
[1] != y
->array
[1])
1559 return x
->array
[0] == y
->array
[0];
1567 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1569 switch (ARRAY_SIZE(x
->array
))
1584 return !x
->array
[0];
1591 cpu_flags_equal (const union i386_cpu_flags
*x
,
1592 const union i386_cpu_flags
*y
)
1594 switch (ARRAY_SIZE(x
->array
))
1597 if (x
->array
[3] != y
->array
[3])
1601 if (x
->array
[2] != y
->array
[2])
1605 if (x
->array
[1] != y
->array
[1])
1609 return x
->array
[0] == y
->array
[0];
1617 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1619 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1620 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1623 static INLINE i386_cpu_flags
1624 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1626 switch (ARRAY_SIZE (x
.array
))
1629 x
.array
[3] &= y
.array
[3];
1632 x
.array
[2] &= y
.array
[2];
1635 x
.array
[1] &= y
.array
[1];
1638 x
.array
[0] &= y
.array
[0];
1646 static INLINE i386_cpu_flags
1647 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[3] |= y
.array
[3];
1655 x
.array
[2] |= y
.array
[2];
1658 x
.array
[1] |= y
.array
[1];
1661 x
.array
[0] |= y
.array
[0];
1669 static INLINE i386_cpu_flags
1670 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1672 switch (ARRAY_SIZE (x
.array
))
1675 x
.array
[3] &= ~y
.array
[3];
1678 x
.array
[2] &= ~y
.array
[2];
1681 x
.array
[1] &= ~y
.array
[1];
1684 x
.array
[0] &= ~y
.array
[0];
1692 #define CPU_FLAGS_ARCH_MATCH 0x1
1693 #define CPU_FLAGS_64BIT_MATCH 0x2
1695 #define CPU_FLAGS_PERFECT_MATCH \
1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1698 /* Return CPU flags match bits. */
1701 cpu_flags_match (const insn_template
*t
)
1703 i386_cpu_flags x
= t
->cpu_flags
;
1704 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1706 x
.bitfield
.cpu64
= 0;
1707 x
.bitfield
.cpuno64
= 0;
1709 if (cpu_flags_all_zero (&x
))
1711 /* This instruction is available on all archs. */
1712 match
|= CPU_FLAGS_ARCH_MATCH
;
1716 /* This instruction is available only on some archs. */
1717 i386_cpu_flags cpu
= cpu_arch_flags
;
1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1722 x
.bitfield
.cpuavx512vl
= 0;
1724 cpu
= cpu_flags_and (x
, cpu
);
1725 if (!cpu_flags_all_zero (&cpu
))
1727 if (x
.bitfield
.cpuavx
)
1729 /* We need to check a few extra flags with AVX. */
1730 if (cpu
.bitfield
.cpuavx
1731 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1732 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1733 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1734 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1735 match
|= CPU_FLAGS_ARCH_MATCH
;
1737 else if (x
.bitfield
.cpuavx512f
)
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu
.bitfield
.cpuavx512f
1741 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1742 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1743 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1744 match
|= CPU_FLAGS_ARCH_MATCH
;
1747 match
|= CPU_FLAGS_ARCH_MATCH
;
1753 static INLINE i386_operand_type
1754 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1756 switch (ARRAY_SIZE (x
.array
))
1759 x
.array
[2] &= y
.array
[2];
1762 x
.array
[1] &= y
.array
[1];
1765 x
.array
[0] &= y
.array
[0];
1773 static INLINE i386_operand_type
1774 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[2] &= ~y
.array
[2];
1782 x
.array
[1] &= ~y
.array
[1];
1785 x
.array
[0] &= ~y
.array
[0];
1793 static INLINE i386_operand_type
1794 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1796 switch (ARRAY_SIZE (x
.array
))
1799 x
.array
[2] |= y
.array
[2];
1802 x
.array
[1] |= y
.array
[1];
1805 x
.array
[0] |= y
.array
[0];
1813 static INLINE i386_operand_type
1814 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1816 switch (ARRAY_SIZE (x
.array
))
1819 x
.array
[2] ^= y
.array
[2];
1822 x
.array
[1] ^= y
.array
[1];
1825 x
.array
[0] ^= y
.array
[0];
1833 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1834 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1835 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1836 static const i386_operand_type inoutportreg
1837 = OPERAND_TYPE_INOUTPORTREG
;
1838 static const i386_operand_type reg16_inoutportreg
1839 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1840 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1841 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1842 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1843 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1844 static const i386_operand_type anydisp
1845 = OPERAND_TYPE_ANYDISP
;
1846 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1847 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1848 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1849 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1850 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1851 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1852 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1853 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1854 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1855 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1856 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1857 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1868 operand_type_check (i386_operand_type t
, enum operand_type c
)
1873 return t
.bitfield
.reg
;
1876 return (t
.bitfield
.imm8
1880 || t
.bitfield
.imm32s
1881 || t
.bitfield
.imm64
);
1884 return (t
.bitfield
.disp8
1885 || t
.bitfield
.disp16
1886 || t
.bitfield
.disp32
1887 || t
.bitfield
.disp32s
1888 || t
.bitfield
.disp64
);
1891 return (t
.bitfield
.disp8
1892 || t
.bitfield
.disp16
1893 || t
.bitfield
.disp32
1894 || t
.bitfield
.disp32s
1895 || t
.bitfield
.disp64
1896 || t
.bitfield
.baseindex
);
1905 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1906 operand J for instruction template T. */
1909 match_reg_size (const insn_template
*t
, unsigned int j
)
1911 return !((i
.types
[j
].bitfield
.byte
1912 && !t
->operand_types
[j
].bitfield
.byte
)
1913 || (i
.types
[j
].bitfield
.word
1914 && !t
->operand_types
[j
].bitfield
.word
)
1915 || (i
.types
[j
].bitfield
.dword
1916 && !t
->operand_types
[j
].bitfield
.dword
)
1917 || (i
.types
[j
].bitfield
.qword
1918 && !t
->operand_types
[j
].bitfield
.qword
)
1919 || (i
.types
[j
].bitfield
.tbyte
1920 && !t
->operand_types
[j
].bitfield
.tbyte
));
1923 /* Return 1 if there is no conflict in SIMD register on
1924 operand J for instruction template T. */
1927 match_simd_size (const insn_template
*t
, unsigned int j
)
1929 return !((i
.types
[j
].bitfield
.xmmword
1930 && !t
->operand_types
[j
].bitfield
.xmmword
)
1931 || (i
.types
[j
].bitfield
.ymmword
1932 && !t
->operand_types
[j
].bitfield
.ymmword
)
1933 || (i
.types
[j
].bitfield
.zmmword
1934 && !t
->operand_types
[j
].bitfield
.zmmword
));
1937 /* Return 1 if there is no conflict in any size on operand J for
1938 instruction template T. */
1941 match_mem_size (const insn_template
*t
, unsigned int j
)
1943 return (match_reg_size (t
, j
)
1944 && !((i
.types
[j
].bitfield
.unspecified
1946 && !t
->operand_types
[j
].bitfield
.unspecified
)
1947 || (i
.types
[j
].bitfield
.fword
1948 && !t
->operand_types
[j
].bitfield
.fword
)
1949 /* For scalar opcode templates to allow register and memory
1950 operands at the same time, some special casing is needed
1951 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1952 down-conversion vpmov*. */
1953 || ((t
->operand_types
[j
].bitfield
.regsimd
1954 && !t
->opcode_modifier
.broadcast
1955 && (t
->operand_types
[j
].bitfield
.byte
1956 || t
->operand_types
[j
].bitfield
.word
1957 || t
->operand_types
[j
].bitfield
.dword
1958 || t
->operand_types
[j
].bitfield
.qword
))
1959 ? (i
.types
[j
].bitfield
.xmmword
1960 || i
.types
[j
].bitfield
.ymmword
1961 || i
.types
[j
].bitfield
.zmmword
)
1962 : !match_simd_size(t
, j
))));
1965 /* Return 1 if there is no size conflict on any operands for
1966 instruction template T. */
1969 operand_size_match (const insn_template
*t
)
1974 /* Don't check jump instructions. */
1975 if (t
->opcode_modifier
.jump
1976 || t
->opcode_modifier
.jumpbyte
1977 || t
->opcode_modifier
.jumpdword
1978 || t
->opcode_modifier
.jumpintersegment
)
1981 /* Check memory and accumulator operand size. */
1982 for (j
= 0; j
< i
.operands
; j
++)
1984 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1985 && t
->operand_types
[j
].bitfield
.anysize
)
1988 if (t
->operand_types
[j
].bitfield
.reg
1989 && !match_reg_size (t
, j
))
1995 if (t
->operand_types
[j
].bitfield
.regsimd
1996 && !match_simd_size (t
, j
))
2002 if (t
->operand_types
[j
].bitfield
.acc
2003 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
2009 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2018 else if (!t
->opcode_modifier
.d
)
2021 i
.error
= operand_size_mismatch
;
2025 /* Check reverse. */
2026 gas_assert (i
.operands
== 2);
2029 for (j
= 0; j
< 2; j
++)
2031 if ((t
->operand_types
[j
].bitfield
.reg
2032 || t
->operand_types
[j
].bitfield
.acc
)
2033 && !match_reg_size (t
, j
? 0 : 1))
2036 if (i
.types
[j
].bitfield
.mem
2037 && !match_mem_size (t
, j
? 0 : 1))
2045 operand_type_match (i386_operand_type overlap
,
2046 i386_operand_type given
)
2048 i386_operand_type temp
= overlap
;
2050 temp
.bitfield
.jumpabsolute
= 0;
2051 temp
.bitfield
.unspecified
= 0;
2052 temp
.bitfield
.byte
= 0;
2053 temp
.bitfield
.word
= 0;
2054 temp
.bitfield
.dword
= 0;
2055 temp
.bitfield
.fword
= 0;
2056 temp
.bitfield
.qword
= 0;
2057 temp
.bitfield
.tbyte
= 0;
2058 temp
.bitfield
.xmmword
= 0;
2059 temp
.bitfield
.ymmword
= 0;
2060 temp
.bitfield
.zmmword
= 0;
2061 if (operand_type_all_zero (&temp
))
2064 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2065 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2069 i
.error
= operand_type_mismatch
;
2073 /* If given types g0 and g1 are registers they must be of the same type
2074 unless the expected operand type register overlap is null.
2075 Memory operand size of certain SIMD instructions is also being checked
2079 operand_type_register_match (i386_operand_type g0
,
2080 i386_operand_type t0
,
2081 i386_operand_type g1
,
2082 i386_operand_type t1
)
2084 if (!g0
.bitfield
.reg
2085 && !g0
.bitfield
.regsimd
2086 && (!operand_type_check (g0
, anymem
)
2087 || g0
.bitfield
.unspecified
2088 || !t0
.bitfield
.regsimd
))
2091 if (!g1
.bitfield
.reg
2092 && !g1
.bitfield
.regsimd
2093 && (!operand_type_check (g1
, anymem
)
2094 || g1
.bitfield
.unspecified
2095 || !t1
.bitfield
.regsimd
))
2098 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2099 && g0
.bitfield
.word
== g1
.bitfield
.word
2100 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2101 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2102 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2103 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2104 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2107 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2108 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2109 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2110 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2111 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2112 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2113 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2116 i
.error
= register_type_mismatch
;
2121 static INLINE
unsigned int
2122 register_number (const reg_entry
*r
)
2124 unsigned int nr
= r
->reg_num
;
2126 if (r
->reg_flags
& RegRex
)
2129 if (r
->reg_flags
& RegVRex
)
2135 static INLINE
unsigned int
2136 mode_from_disp_size (i386_operand_type t
)
2138 if (t
.bitfield
.disp8
)
2140 else if (t
.bitfield
.disp16
2141 || t
.bitfield
.disp32
2142 || t
.bitfield
.disp32s
)
2149 fits_in_signed_byte (addressT num
)
2151 return num
+ 0x80 <= 0xff;
2155 fits_in_unsigned_byte (addressT num
)
2161 fits_in_unsigned_word (addressT num
)
2163 return num
<= 0xffff;
2167 fits_in_signed_word (addressT num
)
2169 return num
+ 0x8000 <= 0xffff;
2173 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2178 return num
+ 0x80000000 <= 0xffffffff;
2180 } /* fits_in_signed_long() */
2183 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2188 return num
<= 0xffffffff;
2190 } /* fits_in_unsigned_long() */
2193 fits_in_disp8 (offsetT num
)
2195 int shift
= i
.memshift
;
2201 mask
= (1 << shift
) - 1;
2203 /* Return 0 if NUM isn't properly aligned. */
2207 /* Check if NUM will fit in 8bit after shift. */
2208 return fits_in_signed_byte (num
>> shift
);
2212 fits_in_imm4 (offsetT num
)
2214 return (num
& 0xf) == num
;
2217 static i386_operand_type
2218 smallest_imm_type (offsetT num
)
2220 i386_operand_type t
;
2222 operand_type_set (&t
, 0);
2223 t
.bitfield
.imm64
= 1;
2225 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2227 /* This code is disabled on the 486 because all the Imm1 forms
2228 in the opcode table are slower on the i486. They're the
2229 versions with the implicitly specified single-position
2230 displacement, which has another syntax if you really want to
2232 t
.bitfield
.imm1
= 1;
2233 t
.bitfield
.imm8
= 1;
2234 t
.bitfield
.imm8s
= 1;
2235 t
.bitfield
.imm16
= 1;
2236 t
.bitfield
.imm32
= 1;
2237 t
.bitfield
.imm32s
= 1;
2239 else if (fits_in_signed_byte (num
))
2241 t
.bitfield
.imm8
= 1;
2242 t
.bitfield
.imm8s
= 1;
2243 t
.bitfield
.imm16
= 1;
2244 t
.bitfield
.imm32
= 1;
2245 t
.bitfield
.imm32s
= 1;
2247 else if (fits_in_unsigned_byte (num
))
2249 t
.bitfield
.imm8
= 1;
2250 t
.bitfield
.imm16
= 1;
2251 t
.bitfield
.imm32
= 1;
2252 t
.bitfield
.imm32s
= 1;
2254 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2256 t
.bitfield
.imm16
= 1;
2257 t
.bitfield
.imm32
= 1;
2258 t
.bitfield
.imm32s
= 1;
2260 else if (fits_in_signed_long (num
))
2262 t
.bitfield
.imm32
= 1;
2263 t
.bitfield
.imm32s
= 1;
2265 else if (fits_in_unsigned_long (num
))
2266 t
.bitfield
.imm32
= 1;
2272 offset_in_range (offsetT val
, int size
)
2278 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2279 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2280 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2282 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2288 /* If BFD64, sign extend val for 32bit address mode. */
2289 if (flag_code
!= CODE_64BIT
2290 || i
.prefix
[ADDR_PREFIX
])
2291 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2292 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2295 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2297 char buf1
[40], buf2
[40];
2299 sprint_value (buf1
, val
);
2300 sprint_value (buf2
, val
& mask
);
2301 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2316 a. PREFIX_EXIST if attempting to add a prefix where one from the
2317 same class already exists.
2318 b. PREFIX_LOCK if lock prefix is added.
2319 c. PREFIX_REP if rep/repne prefix is added.
2320 d. PREFIX_DS if ds prefix is added.
2321 e. PREFIX_OTHER if other prefix is added.
2324 static enum PREFIX_GROUP
2325 add_prefix (unsigned int prefix
)
2327 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2330 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2331 && flag_code
== CODE_64BIT
)
2333 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2334 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2335 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2346 case DS_PREFIX_OPCODE
:
2349 case CS_PREFIX_OPCODE
:
2350 case ES_PREFIX_OPCODE
:
2351 case FS_PREFIX_OPCODE
:
2352 case GS_PREFIX_OPCODE
:
2353 case SS_PREFIX_OPCODE
:
2357 case REPNE_PREFIX_OPCODE
:
2358 case REPE_PREFIX_OPCODE
:
2363 case LOCK_PREFIX_OPCODE
:
2372 case ADDR_PREFIX_OPCODE
:
2376 case DATA_PREFIX_OPCODE
:
2380 if (i
.prefix
[q
] != 0)
2388 i
.prefix
[q
] |= prefix
;
2391 as_bad (_("same type of prefix used twice"));
2397 update_code_flag (int value
, int check
)
2399 PRINTF_LIKE ((*as_error
));
2401 flag_code
= (enum flag_code
) value
;
2402 if (flag_code
== CODE_64BIT
)
2404 cpu_arch_flags
.bitfield
.cpu64
= 1;
2405 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2409 cpu_arch_flags
.bitfield
.cpu64
= 0;
2410 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2412 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2415 as_error
= as_fatal
;
2418 (*as_error
) (_("64bit mode not supported on `%s'."),
2419 cpu_arch_name
? cpu_arch_name
: default_arch
);
2421 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2424 as_error
= as_fatal
;
2427 (*as_error
) (_("32bit mode not supported on `%s'."),
2428 cpu_arch_name
? cpu_arch_name
: default_arch
);
2430 stackop_size
= '\0';
2434 set_code_flag (int value
)
2436 update_code_flag (value
, 0);
2440 set_16bit_gcc_code_flag (int new_code_flag
)
2442 flag_code
= (enum flag_code
) new_code_flag
;
2443 if (flag_code
!= CODE_16BIT
)
2445 cpu_arch_flags
.bitfield
.cpu64
= 0;
2446 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2447 stackop_size
= LONG_MNEM_SUFFIX
;
2451 set_intel_syntax (int syntax_flag
)
2453 /* Find out if register prefixing is specified. */
2454 int ask_naked_reg
= 0;
2457 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2460 int e
= get_symbol_name (&string
);
2462 if (strcmp (string
, "prefix") == 0)
2464 else if (strcmp (string
, "noprefix") == 0)
2467 as_bad (_("bad argument to syntax directive."));
2468 (void) restore_line_pointer (e
);
2470 demand_empty_rest_of_line ();
2472 intel_syntax
= syntax_flag
;
2474 if (ask_naked_reg
== 0)
2475 allow_naked_reg
= (intel_syntax
2476 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2478 allow_naked_reg
= (ask_naked_reg
< 0);
2480 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2482 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2483 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2484 register_prefix
= allow_naked_reg
? "" : "%";
2488 set_intel_mnemonic (int mnemonic_flag
)
2490 intel_mnemonic
= mnemonic_flag
;
2494 set_allow_index_reg (int flag
)
2496 allow_index_reg
= flag
;
2500 set_check (int what
)
2502 enum check_kind
*kind
;
2507 kind
= &operand_check
;
2518 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2521 int e
= get_symbol_name (&string
);
2523 if (strcmp (string
, "none") == 0)
2525 else if (strcmp (string
, "warning") == 0)
2526 *kind
= check_warning
;
2527 else if (strcmp (string
, "error") == 0)
2528 *kind
= check_error
;
2530 as_bad (_("bad argument to %s_check directive."), str
);
2531 (void) restore_line_pointer (e
);
2534 as_bad (_("missing argument for %s_check directive"), str
);
2536 demand_empty_rest_of_line ();
2540 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2541 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2543 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2544 static const char *arch
;
2546 /* Intel LIOM is only supported on ELF. */
2552 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2553 use default_arch. */
2554 arch
= cpu_arch_name
;
2556 arch
= default_arch
;
2559 /* If we are targeting Intel MCU, we must enable it. */
2560 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2561 || new_flag
.bitfield
.cpuiamcu
)
2564 /* If we are targeting Intel L1OM, we must enable it. */
2565 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2566 || new_flag
.bitfield
.cpul1om
)
2569 /* If we are targeting Intel K1OM, we must enable it. */
2570 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2571 || new_flag
.bitfield
.cpuk1om
)
2574 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2579 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2583 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2586 int e
= get_symbol_name (&string
);
2588 i386_cpu_flags flags
;
2590 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2592 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2594 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2598 cpu_arch_name
= cpu_arch
[j
].name
;
2599 cpu_sub_arch_name
= NULL
;
2600 cpu_arch_flags
= cpu_arch
[j
].flags
;
2601 if (flag_code
== CODE_64BIT
)
2603 cpu_arch_flags
.bitfield
.cpu64
= 1;
2604 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2608 cpu_arch_flags
.bitfield
.cpu64
= 0;
2609 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2611 cpu_arch_isa
= cpu_arch
[j
].type
;
2612 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2613 if (!cpu_arch_tune_set
)
2615 cpu_arch_tune
= cpu_arch_isa
;
2616 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2621 flags
= cpu_flags_or (cpu_arch_flags
,
2624 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2626 if (cpu_sub_arch_name
)
2628 char *name
= cpu_sub_arch_name
;
2629 cpu_sub_arch_name
= concat (name
,
2631 (const char *) NULL
);
2635 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2636 cpu_arch_flags
= flags
;
2637 cpu_arch_isa_flags
= flags
;
2641 = cpu_flags_or (cpu_arch_isa_flags
,
2643 (void) restore_line_pointer (e
);
2644 demand_empty_rest_of_line ();
2649 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2651 /* Disable an ISA extension. */
2652 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2653 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2655 flags
= cpu_flags_and_not (cpu_arch_flags
,
2656 cpu_noarch
[j
].flags
);
2657 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2659 if (cpu_sub_arch_name
)
2661 char *name
= cpu_sub_arch_name
;
2662 cpu_sub_arch_name
= concat (name
, string
,
2663 (const char *) NULL
);
2667 cpu_sub_arch_name
= xstrdup (string
);
2668 cpu_arch_flags
= flags
;
2669 cpu_arch_isa_flags
= flags
;
2671 (void) restore_line_pointer (e
);
2672 demand_empty_rest_of_line ();
2676 j
= ARRAY_SIZE (cpu_arch
);
2679 if (j
>= ARRAY_SIZE (cpu_arch
))
2680 as_bad (_("no such architecture: `%s'"), string
);
2682 *input_line_pointer
= e
;
2685 as_bad (_("missing cpu architecture"));
2687 no_cond_jump_promotion
= 0;
2688 if (*input_line_pointer
== ','
2689 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2694 ++input_line_pointer
;
2695 e
= get_symbol_name (&string
);
2697 if (strcmp (string
, "nojumps") == 0)
2698 no_cond_jump_promotion
= 1;
2699 else if (strcmp (string
, "jumps") == 0)
2702 as_bad (_("no such architecture modifier: `%s'"), string
);
2704 (void) restore_line_pointer (e
);
2707 demand_empty_rest_of_line ();
2710 enum bfd_architecture
2713 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2715 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2716 || flag_code
!= CODE_64BIT
)
2717 as_fatal (_("Intel L1OM is 64bit ELF only"));
2718 return bfd_arch_l1om
;
2720 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2722 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2723 || flag_code
!= CODE_64BIT
)
2724 as_fatal (_("Intel K1OM is 64bit ELF only"));
2725 return bfd_arch_k1om
;
2727 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2729 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2730 || flag_code
== CODE_64BIT
)
2731 as_fatal (_("Intel MCU is 32bit ELF only"));
2732 return bfd_arch_iamcu
;
2735 return bfd_arch_i386
;
2741 if (!strncmp (default_arch
, "x86_64", 6))
2743 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2745 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2746 || default_arch
[6] != '\0')
2747 as_fatal (_("Intel L1OM is 64bit ELF only"));
2748 return bfd_mach_l1om
;
2750 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2752 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2753 || default_arch
[6] != '\0')
2754 as_fatal (_("Intel K1OM is 64bit ELF only"));
2755 return bfd_mach_k1om
;
2757 else if (default_arch
[6] == '\0')
2758 return bfd_mach_x86_64
;
2760 return bfd_mach_x64_32
;
2762 else if (!strcmp (default_arch
, "i386")
2763 || !strcmp (default_arch
, "iamcu"))
2765 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2767 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2768 as_fatal (_("Intel MCU is 32bit ELF only"));
2769 return bfd_mach_i386_iamcu
;
2772 return bfd_mach_i386_i386
;
2775 as_fatal (_("unknown architecture"));
2781 const char *hash_err
;
2783 /* Support pseudo prefixes like {disp32}. */
2784 lex_type
['{'] = LEX_BEGIN_NAME
;
2786 /* Initialize op_hash hash table. */
2787 op_hash
= hash_new ();
2790 const insn_template
*optab
;
2791 templates
*core_optab
;
2793 /* Setup for loop. */
2795 core_optab
= XNEW (templates
);
2796 core_optab
->start
= optab
;
2801 if (optab
->name
== NULL
2802 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2804 /* different name --> ship out current template list;
2805 add to hash table; & begin anew. */
2806 core_optab
->end
= optab
;
2807 hash_err
= hash_insert (op_hash
,
2809 (void *) core_optab
);
2812 as_fatal (_("can't hash %s: %s"),
2816 if (optab
->name
== NULL
)
2818 core_optab
= XNEW (templates
);
2819 core_optab
->start
= optab
;
2824 /* Initialize reg_hash hash table. */
2825 reg_hash
= hash_new ();
2827 const reg_entry
*regtab
;
2828 unsigned int regtab_size
= i386_regtab_size
;
2830 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2832 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2834 as_fatal (_("can't hash %s: %s"),
2840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2845 for (c
= 0; c
< 256; c
++)
2850 mnemonic_chars
[c
] = c
;
2851 register_chars
[c
] = c
;
2852 operand_chars
[c
] = c
;
2854 else if (ISLOWER (c
))
2856 mnemonic_chars
[c
] = c
;
2857 register_chars
[c
] = c
;
2858 operand_chars
[c
] = c
;
2860 else if (ISUPPER (c
))
2862 mnemonic_chars
[c
] = TOLOWER (c
);
2863 register_chars
[c
] = mnemonic_chars
[c
];
2864 operand_chars
[c
] = c
;
2866 else if (c
== '{' || c
== '}')
2868 mnemonic_chars
[c
] = c
;
2869 operand_chars
[c
] = c
;
2872 if (ISALPHA (c
) || ISDIGIT (c
))
2873 identifier_chars
[c
] = c
;
2876 identifier_chars
[c
] = c
;
2877 operand_chars
[c
] = c
;
2882 identifier_chars
['@'] = '@';
2885 identifier_chars
['?'] = '?';
2886 operand_chars
['?'] = '?';
2888 digit_chars
['-'] = '-';
2889 mnemonic_chars
['_'] = '_';
2890 mnemonic_chars
['-'] = '-';
2891 mnemonic_chars
['.'] = '.';
2892 identifier_chars
['_'] = '_';
2893 identifier_chars
['.'] = '.';
2895 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2896 operand_chars
[(unsigned char) *p
] = *p
;
2899 if (flag_code
== CODE_64BIT
)
2901 #if defined (OBJ_COFF) && defined (TE_PE)
2902 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2905 x86_dwarf2_return_column
= 16;
2907 x86_cie_data_alignment
= -8;
2911 x86_dwarf2_return_column
= 8;
2912 x86_cie_data_alignment
= -4;
2917 i386_print_statistics (FILE *file
)
2919 hash_print_statistics (file
, "i386 opcode", op_hash
);
2920 hash_print_statistics (file
, "i386 register", reg_hash
);
2925 /* Debugging routines for md_assemble. */
2926 static void pte (insn_template
*);
2927 static void pt (i386_operand_type
);
2928 static void pe (expressionS
*);
2929 static void ps (symbolS
*);
2932 pi (char *line
, i386_insn
*x
)
2936 fprintf (stdout
, "%s: template ", line
);
2938 fprintf (stdout
, " address: base %s index %s scale %x\n",
2939 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2940 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2941 x
->log2_scale_factor
);
2942 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2943 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2944 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2945 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2946 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2947 (x
->rex
& REX_W
) != 0,
2948 (x
->rex
& REX_R
) != 0,
2949 (x
->rex
& REX_X
) != 0,
2950 (x
->rex
& REX_B
) != 0);
2951 for (j
= 0; j
< x
->operands
; j
++)
2953 fprintf (stdout
, " #%d: ", j
+ 1);
2955 fprintf (stdout
, "\n");
2956 if (x
->types
[j
].bitfield
.reg
2957 || x
->types
[j
].bitfield
.regmmx
2958 || x
->types
[j
].bitfield
.regsimd
2959 || x
->types
[j
].bitfield
.sreg2
2960 || x
->types
[j
].bitfield
.sreg3
2961 || x
->types
[j
].bitfield
.control
2962 || x
->types
[j
].bitfield
.debug
2963 || x
->types
[j
].bitfield
.test
)
2964 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2965 if (operand_type_check (x
->types
[j
], imm
))
2967 if (operand_type_check (x
->types
[j
], disp
))
2968 pe (x
->op
[j
].disps
);
2973 pte (insn_template
*t
)
2976 fprintf (stdout
, " %d operands ", t
->operands
);
2977 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2978 if (t
->extension_opcode
!= None
)
2979 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2980 if (t
->opcode_modifier
.d
)
2981 fprintf (stdout
, "D");
2982 if (t
->opcode_modifier
.w
)
2983 fprintf (stdout
, "W");
2984 fprintf (stdout
, "\n");
2985 for (j
= 0; j
< t
->operands
; j
++)
2987 fprintf (stdout
, " #%d type ", j
+ 1);
2988 pt (t
->operand_types
[j
]);
2989 fprintf (stdout
, "\n");
2996 fprintf (stdout
, " operation %d\n", e
->X_op
);
2997 fprintf (stdout
, " add_number %ld (%lx)\n",
2998 (long) e
->X_add_number
, (long) e
->X_add_number
);
2999 if (e
->X_add_symbol
)
3001 fprintf (stdout
, " add_symbol ");
3002 ps (e
->X_add_symbol
);
3003 fprintf (stdout
, "\n");
3007 fprintf (stdout
, " op_symbol ");
3008 ps (e
->X_op_symbol
);
3009 fprintf (stdout
, "\n");
3016 fprintf (stdout
, "%s type %s%s",
3018 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3019 segment_name (S_GET_SEGMENT (s
)));
3022 static struct type_name
3024 i386_operand_type mask
;
3027 const type_names
[] =
3029 { OPERAND_TYPE_REG8
, "r8" },
3030 { OPERAND_TYPE_REG16
, "r16" },
3031 { OPERAND_TYPE_REG32
, "r32" },
3032 { OPERAND_TYPE_REG64
, "r64" },
3033 { OPERAND_TYPE_IMM8
, "i8" },
3034 { OPERAND_TYPE_IMM8
, "i8s" },
3035 { OPERAND_TYPE_IMM16
, "i16" },
3036 { OPERAND_TYPE_IMM32
, "i32" },
3037 { OPERAND_TYPE_IMM32S
, "i32s" },
3038 { OPERAND_TYPE_IMM64
, "i64" },
3039 { OPERAND_TYPE_IMM1
, "i1" },
3040 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3041 { OPERAND_TYPE_DISP8
, "d8" },
3042 { OPERAND_TYPE_DISP16
, "d16" },
3043 { OPERAND_TYPE_DISP32
, "d32" },
3044 { OPERAND_TYPE_DISP32S
, "d32s" },
3045 { OPERAND_TYPE_DISP64
, "d64" },
3046 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3047 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3048 { OPERAND_TYPE_CONTROL
, "control reg" },
3049 { OPERAND_TYPE_TEST
, "test reg" },
3050 { OPERAND_TYPE_DEBUG
, "debug reg" },
3051 { OPERAND_TYPE_FLOATREG
, "FReg" },
3052 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3053 { OPERAND_TYPE_SREG2
, "SReg2" },
3054 { OPERAND_TYPE_SREG3
, "SReg3" },
3055 { OPERAND_TYPE_ACC
, "Acc" },
3056 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3057 { OPERAND_TYPE_REGMMX
, "rMMX" },
3058 { OPERAND_TYPE_REGXMM
, "rXMM" },
3059 { OPERAND_TYPE_REGYMM
, "rYMM" },
3060 { OPERAND_TYPE_REGZMM
, "rZMM" },
3061 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3062 { OPERAND_TYPE_ESSEG
, "es" },
3066 pt (i386_operand_type t
)
3069 i386_operand_type a
;
3071 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3073 a
= operand_type_and (t
, type_names
[j
].mask
);
3074 if (!operand_type_all_zero (&a
))
3075 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3080 #endif /* DEBUG386 */
3082 static bfd_reloc_code_real_type
3083 reloc (unsigned int size
,
3086 bfd_reloc_code_real_type other
)
3088 if (other
!= NO_RELOC
)
3090 reloc_howto_type
*rel
;
3095 case BFD_RELOC_X86_64_GOT32
:
3096 return BFD_RELOC_X86_64_GOT64
;
3098 case BFD_RELOC_X86_64_GOTPLT64
:
3099 return BFD_RELOC_X86_64_GOTPLT64
;
3101 case BFD_RELOC_X86_64_PLTOFF64
:
3102 return BFD_RELOC_X86_64_PLTOFF64
;
3104 case BFD_RELOC_X86_64_GOTPC32
:
3105 other
= BFD_RELOC_X86_64_GOTPC64
;
3107 case BFD_RELOC_X86_64_GOTPCREL
:
3108 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3110 case BFD_RELOC_X86_64_TPOFF32
:
3111 other
= BFD_RELOC_X86_64_TPOFF64
;
3113 case BFD_RELOC_X86_64_DTPOFF32
:
3114 other
= BFD_RELOC_X86_64_DTPOFF64
;
3120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3121 if (other
== BFD_RELOC_SIZE32
)
3124 other
= BFD_RELOC_SIZE64
;
3127 as_bad (_("there are no pc-relative size relocations"));
3133 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3134 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3137 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3139 as_bad (_("unknown relocation (%u)"), other
);
3140 else if (size
!= bfd_get_reloc_size (rel
))
3141 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3142 bfd_get_reloc_size (rel
),
3144 else if (pcrel
&& !rel
->pc_relative
)
3145 as_bad (_("non-pc-relative relocation for pc-relative field"));
3146 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3148 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3150 as_bad (_("relocated field and relocation type differ in signedness"));
3159 as_bad (_("there are no unsigned pc-relative relocations"));
3162 case 1: return BFD_RELOC_8_PCREL
;
3163 case 2: return BFD_RELOC_16_PCREL
;
3164 case 4: return BFD_RELOC_32_PCREL
;
3165 case 8: return BFD_RELOC_64_PCREL
;
3167 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3174 case 4: return BFD_RELOC_X86_64_32S
;
3179 case 1: return BFD_RELOC_8
;
3180 case 2: return BFD_RELOC_16
;
3181 case 4: return BFD_RELOC_32
;
3182 case 8: return BFD_RELOC_64
;
3184 as_bad (_("cannot do %s %u byte relocation"),
3185 sign
> 0 ? "signed" : "unsigned", size
);
3191 /* Here we decide which fixups can be adjusted to make them relative to
3192 the beginning of the section instead of the symbol. Basically we need
3193 to make sure that the dynamic relocations are done correctly, so in
3194 some cases we force the original symbol to be used. */
3197 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3203 /* Don't adjust pc-relative references to merge sections in 64-bit
3205 if (use_rela_relocations
3206 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3210 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3211 and changed later by validate_fix. */
3212 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3213 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3216 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3217 for size relocations. */
3218 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3219 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3220 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3221 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3222 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3223 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3224 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3225 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3226 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3227 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3235 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3244 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3245 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3246 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3247 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3248 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3249 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3250 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3257 intel_float_operand (const char *mnemonic
)
3259 /* Note that the value returned is meaningful only for opcodes with (memory)
3260 operands, hence the code here is free to improperly handle opcodes that
3261 have no operands (for better performance and smaller code). */
3263 if (mnemonic
[0] != 'f')
3264 return 0; /* non-math */
3266 switch (mnemonic
[1])
3268 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3269 the fs segment override prefix not currently handled because no
3270 call path can make opcodes without operands get here */
3272 return 2 /* integer op */;
3274 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3275 return 3; /* fldcw/fldenv */
3278 if (mnemonic
[2] != 'o' /* fnop */)
3279 return 3; /* non-waiting control op */
3282 if (mnemonic
[2] == 's')
3283 return 3; /* frstor/frstpm */
3286 if (mnemonic
[2] == 'a')
3287 return 3; /* fsave */
3288 if (mnemonic
[2] == 't')
3290 switch (mnemonic
[3])
3292 case 'c': /* fstcw */
3293 case 'd': /* fstdw */
3294 case 'e': /* fstenv */
3295 case 's': /* fsts[gw] */
3301 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3302 return 0; /* fxsave/fxrstor are not really math ops */
3309 /* Build the VEX prefix. */
3312 build_vex_prefix (const insn_template
*t
)
3314 unsigned int register_specifier
;
3315 unsigned int implied_prefix
;
3316 unsigned int vector_length
;
3318 /* Check register specifier. */
3319 if (i
.vex
.register_specifier
)
3321 register_specifier
=
3322 ~register_number (i
.vex
.register_specifier
) & 0xf;
3323 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3326 register_specifier
= 0xf;
3328 /* Use 2-byte VEX prefix by swapping destination and source
3330 if (i
.vec_encoding
!= vex_encoding_vex3
3331 && i
.dir_encoding
== dir_encoding_default
3332 && i
.operands
== i
.reg_operands
3333 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3334 && i
.tm
.opcode_modifier
.load
3337 unsigned int xchg
= i
.operands
- 1;
3338 union i386_op temp_op
;
3339 i386_operand_type temp_type
;
3341 temp_type
= i
.types
[xchg
];
3342 i
.types
[xchg
] = i
.types
[0];
3343 i
.types
[0] = temp_type
;
3344 temp_op
= i
.op
[xchg
];
3345 i
.op
[xchg
] = i
.op
[0];
3348 gas_assert (i
.rm
.mode
== 3);
3352 i
.rm
.regmem
= i
.rm
.reg
;
3355 /* Use the next insn. */
3359 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3360 vector_length
= avxscalar
;
3361 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3368 for (op
= 0; op
< t
->operands
; ++op
)
3369 if (t
->operand_types
[op
].bitfield
.xmmword
3370 && t
->operand_types
[op
].bitfield
.ymmword
3371 && i
.types
[op
].bitfield
.ymmword
)
3378 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3383 case DATA_PREFIX_OPCODE
:
3386 case REPE_PREFIX_OPCODE
:
3389 case REPNE_PREFIX_OPCODE
:
3396 /* Use 2-byte VEX prefix if possible. */
3397 if (i
.vec_encoding
!= vex_encoding_vex3
3398 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3399 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3400 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3402 /* 2-byte VEX prefix. */
3406 i
.vex
.bytes
[0] = 0xc5;
3408 /* Check the REX.R bit. */
3409 r
= (i
.rex
& REX_R
) ? 0 : 1;
3410 i
.vex
.bytes
[1] = (r
<< 7
3411 | register_specifier
<< 3
3412 | vector_length
<< 2
3417 /* 3-byte VEX prefix. */
3422 switch (i
.tm
.opcode_modifier
.vexopcode
)
3426 i
.vex
.bytes
[0] = 0xc4;
3430 i
.vex
.bytes
[0] = 0xc4;
3434 i
.vex
.bytes
[0] = 0xc4;
3438 i
.vex
.bytes
[0] = 0x8f;
3442 i
.vex
.bytes
[0] = 0x8f;
3446 i
.vex
.bytes
[0] = 0x8f;
3452 /* The high 3 bits of the second VEX byte are 1's compliment
3453 of RXB bits from REX. */
3454 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3456 /* Check the REX.W bit. */
3457 w
= (i
.rex
& REX_W
) ? 1 : 0;
3458 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3461 i
.vex
.bytes
[2] = (w
<< 7
3462 | register_specifier
<< 3
3463 | vector_length
<< 2
3468 static INLINE bfd_boolean
3469 is_evex_encoding (const insn_template
*t
)
3471 return t
->opcode_modifier
.evex
3472 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3473 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3476 /* Build the EVEX prefix. */
3479 build_evex_prefix (void)
3481 unsigned int register_specifier
;
3482 unsigned int implied_prefix
;
3484 rex_byte vrex_used
= 0;
3486 /* Check register specifier. */
3487 if (i
.vex
.register_specifier
)
3489 gas_assert ((i
.vrex
& REX_X
) == 0);
3491 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3492 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3493 register_specifier
+= 8;
3494 /* The upper 16 registers are encoded in the fourth byte of the
3496 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3497 i
.vex
.bytes
[3] = 0x8;
3498 register_specifier
= ~register_specifier
& 0xf;
3502 register_specifier
= 0xf;
3504 /* Encode upper 16 vector index register in the fourth byte of
3506 if (!(i
.vrex
& REX_X
))
3507 i
.vex
.bytes
[3] = 0x8;
3512 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3517 case DATA_PREFIX_OPCODE
:
3520 case REPE_PREFIX_OPCODE
:
3523 case REPNE_PREFIX_OPCODE
:
3530 /* 4 byte EVEX prefix. */
3532 i
.vex
.bytes
[0] = 0x62;
3535 switch (i
.tm
.opcode_modifier
.vexopcode
)
3551 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3553 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3555 /* The fifth bit of the second EVEX byte is 1's compliment of the
3556 REX_R bit in VREX. */
3557 if (!(i
.vrex
& REX_R
))
3558 i
.vex
.bytes
[1] |= 0x10;
3562 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3564 /* When all operands are registers, the REX_X bit in REX is not
3565 used. We reuse it to encode the upper 16 registers, which is
3566 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3567 as 1's compliment. */
3568 if ((i
.vrex
& REX_B
))
3571 i
.vex
.bytes
[1] &= ~0x40;
3575 /* EVEX instructions shouldn't need the REX prefix. */
3576 i
.vrex
&= ~vrex_used
;
3577 gas_assert (i
.vrex
== 0);
3579 /* Check the REX.W bit. */
3580 w
= (i
.rex
& REX_W
) ? 1 : 0;
3581 if (i
.tm
.opcode_modifier
.vexw
)
3583 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3586 /* If w is not set it means we are dealing with WIG instruction. */
3589 if (evexwig
== evexw1
)
3593 /* Encode the U bit. */
3594 implied_prefix
|= 0x4;
3596 /* The third byte of the EVEX prefix. */
3597 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3599 /* The fourth byte of the EVEX prefix. */
3600 /* The zeroing-masking bit. */
3601 if (i
.mask
&& i
.mask
->zeroing
)
3602 i
.vex
.bytes
[3] |= 0x80;
3604 /* Don't always set the broadcast bit if there is no RC. */
3607 /* Encode the vector length. */
3608 unsigned int vec_length
;
3610 if (!i
.tm
.opcode_modifier
.evex
3611 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3616 for (op
= 0; op
< i
.tm
.operands
; ++op
)
3617 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3618 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3619 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3621 if (i
.types
[op
].bitfield
.zmmword
)
3622 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3623 else if (i
.types
[op
].bitfield
.ymmword
)
3624 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3625 else if (i
.types
[op
].bitfield
.xmmword
)
3626 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3633 switch (i
.tm
.opcode_modifier
.evex
)
3635 case EVEXLIG
: /* LL' is ignored */
3636 vec_length
= evexlig
<< 5;
3639 vec_length
= 0 << 5;
3642 vec_length
= 1 << 5;
3645 vec_length
= 2 << 5;
3651 i
.vex
.bytes
[3] |= vec_length
;
3652 /* Encode the broadcast bit. */
3654 i
.vex
.bytes
[3] |= 0x10;
3658 if (i
.rounding
->type
!= saeonly
)
3659 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3661 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3664 if (i
.mask
&& i
.mask
->mask
)
3665 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3669 process_immext (void)
3673 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3676 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3677 with an opcode suffix which is coded in the same place as an
3678 8-bit immediate field would be.
3679 Here we check those operands and remove them afterwards. */
3682 for (x
= 0; x
< i
.operands
; x
++)
3683 if (register_number (i
.op
[x
].regs
) != x
)
3684 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3685 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3691 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3693 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3694 suffix which is coded in the same place as an 8-bit immediate
3696 Here we check those operands and remove them afterwards. */
3699 if (i
.operands
!= 3)
3702 for (x
= 0; x
< 2; x
++)
3703 if (register_number (i
.op
[x
].regs
) != x
)
3704 goto bad_register_operand
;
3706 /* Check for third operand for mwaitx/monitorx insn. */
3707 if (register_number (i
.op
[x
].regs
)
3708 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3710 bad_register_operand
:
3711 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3712 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3719 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3720 which is coded in the same place as an 8-bit immediate field
3721 would be. Here we fake an 8-bit immediate operand from the
3722 opcode suffix stored in tm.extension_opcode.
3724 AVX instructions also use this encoding, for some of
3725 3 argument instructions. */
3727 gas_assert (i
.imm_operands
<= 1
3729 || ((i
.tm
.opcode_modifier
.vex
3730 || i
.tm
.opcode_modifier
.vexopcode
3731 || is_evex_encoding (&i
.tm
))
3732 && i
.operands
<= 4)));
3734 exp
= &im_expressions
[i
.imm_operands
++];
3735 i
.op
[i
.operands
].imms
= exp
;
3736 i
.types
[i
.operands
] = imm8
;
3738 exp
->X_op
= O_constant
;
3739 exp
->X_add_number
= i
.tm
.extension_opcode
;
3740 i
.tm
.extension_opcode
= None
;
3747 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3752 as_bad (_("invalid instruction `%s' after `%s'"),
3753 i
.tm
.name
, i
.hle_prefix
);
3756 if (i
.prefix
[LOCK_PREFIX
])
3758 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3762 case HLEPrefixRelease
:
3763 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3765 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3769 if (i
.mem_operands
== 0
3770 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3772 as_bad (_("memory destination needed for instruction `%s'"
3773 " after `xrelease'"), i
.tm
.name
);
3780 /* Try the shortest encoding by shortening operand size. */
3783 optimize_encoding (void)
3787 if (optimize_for_space
3788 && i
.reg_operands
== 1
3789 && i
.imm_operands
== 1
3790 && !i
.types
[1].bitfield
.byte
3791 && i
.op
[0].imms
->X_op
== O_constant
3792 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3793 && ((i
.tm
.base_opcode
== 0xa8
3794 && i
.tm
.extension_opcode
== None
)
3795 || (i
.tm
.base_opcode
== 0xf6
3796 && i
.tm
.extension_opcode
== 0x0)))
3799 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3801 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3802 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3804 i
.types
[1].bitfield
.byte
= 1;
3805 /* Ignore the suffix. */
3807 if (base_regnum
>= 4
3808 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3810 /* Handle SP, BP, SI and DI registers. */
3811 if (i
.types
[1].bitfield
.word
)
3813 else if (i
.types
[1].bitfield
.dword
)
3821 else if (flag_code
== CODE_64BIT
3822 && ((i
.types
[1].bitfield
.qword
3823 && i
.reg_operands
== 1
3824 && i
.imm_operands
== 1
3825 && i
.op
[0].imms
->X_op
== O_constant
3826 && ((i
.tm
.base_opcode
== 0xb0
3827 && i
.tm
.extension_opcode
== None
3828 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3829 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3830 && (((i
.tm
.base_opcode
== 0x24
3831 || i
.tm
.base_opcode
== 0xa8)
3832 && i
.tm
.extension_opcode
== None
)
3833 || (i
.tm
.base_opcode
== 0x80
3834 && i
.tm
.extension_opcode
== 0x4)
3835 || ((i
.tm
.base_opcode
== 0xf6
3836 || i
.tm
.base_opcode
== 0xc6)
3837 && i
.tm
.extension_opcode
== 0x0)))))
3838 || (i
.types
[0].bitfield
.qword
3839 && ((i
.reg_operands
== 2
3840 && i
.op
[0].regs
== i
.op
[1].regs
3841 && ((i
.tm
.base_opcode
== 0x30
3842 || i
.tm
.base_opcode
== 0x28)
3843 && i
.tm
.extension_opcode
== None
))
3844 || (i
.reg_operands
== 1
3846 && i
.tm
.base_opcode
== 0x30
3847 && i
.tm
.extension_opcode
== None
)))))
3850 andq $imm31, %r64 -> andl $imm31, %r32
3851 testq $imm31, %r64 -> testl $imm31, %r32
3852 xorq %r64, %r64 -> xorl %r32, %r32
3853 subq %r64, %r64 -> subl %r32, %r32
3854 movq $imm31, %r64 -> movl $imm31, %r32
3855 movq $imm32, %r64 -> movl $imm32, %r32
3857 i
.tm
.opcode_modifier
.norex64
= 1;
3858 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3861 movq $imm31, %r64 -> movl $imm31, %r32
3862 movq $imm32, %r64 -> movl $imm32, %r32
3864 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3865 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3866 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3867 i
.types
[0].bitfield
.imm32
= 1;
3868 i
.types
[0].bitfield
.imm32s
= 0;
3869 i
.types
[0].bitfield
.imm64
= 0;
3870 i
.types
[1].bitfield
.dword
= 1;
3871 i
.types
[1].bitfield
.qword
= 0;
3872 if (i
.tm
.base_opcode
== 0xc6)
3875 movq $imm31, %r64 -> movl $imm31, %r32
3877 i
.tm
.base_opcode
= 0xb0;
3878 i
.tm
.extension_opcode
= None
;
3879 i
.tm
.opcode_modifier
.shortform
= 1;
3880 i
.tm
.opcode_modifier
.modrm
= 0;
3884 else if (optimize
> 1
3885 && i
.reg_operands
== 3
3886 && i
.op
[0].regs
== i
.op
[1].regs
3887 && !i
.types
[2].bitfield
.xmmword
3888 && (i
.tm
.opcode_modifier
.vex
3889 || ((!i
.mask
|| i
.mask
->zeroing
)
3891 && is_evex_encoding (&i
.tm
)
3892 && (i
.vec_encoding
!= vex_encoding_evex
3893 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
3894 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
)))
3895 && ((i
.tm
.base_opcode
== 0x55
3896 || i
.tm
.base_opcode
== 0x6655
3897 || i
.tm
.base_opcode
== 0x66df
3898 || i
.tm
.base_opcode
== 0x57
3899 || i
.tm
.base_opcode
== 0x6657
3900 || i
.tm
.base_opcode
== 0x66ef
3901 || i
.tm
.base_opcode
== 0x66f8
3902 || i
.tm
.base_opcode
== 0x66f9
3903 || i
.tm
.base_opcode
== 0x66fa
3904 || i
.tm
.base_opcode
== 0x66fb)
3905 && i
.tm
.extension_opcode
== None
))
3908 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3910 EVEX VOP %zmmM, %zmmM, %zmmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3912 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3913 EVEX VOP %ymmM, %ymmM, %ymmN
3914 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 VEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX VOP %xmmM, %xmmM, %xmmN
3918 VOP, one of vpandn and vpxor:
3919 VEX VOP %ymmM, %ymmM, %ymmN
3920 -> VEX VOP %xmmM, %xmmM, %xmmN
3921 VOP, one of vpandnd and vpandnq:
3922 EVEX VOP %zmmM, %zmmM, %zmmN
3923 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3924 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 EVEX VOP %ymmM, %ymmM, %ymmN
3926 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3927 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 VOP, one of vpxord and vpxorq:
3929 EVEX VOP %zmmM, %zmmM, %zmmN
3930 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3931 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3932 EVEX VOP %ymmM, %ymmM, %ymmN
3933 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3934 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3936 if (is_evex_encoding (&i
.tm
))
3938 if (i
.vec_encoding
== vex_encoding_evex
)
3939 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3942 i
.tm
.opcode_modifier
.vex
= VEX128
;
3943 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3944 i
.tm
.opcode_modifier
.evex
= 0;
3948 i
.tm
.opcode_modifier
.vex
= VEX128
;
3950 if (i
.tm
.opcode_modifier
.vex
)
3951 for (j
= 0; j
< 3; j
++)
3953 i
.types
[j
].bitfield
.xmmword
= 1;
3954 i
.types
[j
].bitfield
.ymmword
= 0;
3959 /* This is the guts of the machine-dependent assembler. LINE points to a
3960 machine dependent instruction. This function is supposed to emit
3961 the frags/bytes it assembles to. */
3964 md_assemble (char *line
)
3967 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3968 const insn_template
*t
;
3970 /* Initialize globals. */
3971 memset (&i
, '\0', sizeof (i
));
3972 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3973 i
.reloc
[j
] = NO_RELOC
;
3974 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3975 memset (im_expressions
, '\0', sizeof (im_expressions
));
3976 save_stack_p
= save_stack
;
3978 /* First parse an instruction mnemonic & call i386_operand for the operands.
3979 We assume that the scrubber has arranged it so that line[0] is the valid
3980 start of a (possibly prefixed) mnemonic. */
3982 line
= parse_insn (line
, mnemonic
);
3985 mnem_suffix
= i
.suffix
;
3987 line
= parse_operands (line
, mnemonic
);
3989 xfree (i
.memop1_string
);
3990 i
.memop1_string
= NULL
;
3994 /* Now we've parsed the mnemonic into a set of templates, and have the
3995 operands at hand. */
3997 /* All intel opcodes have reversed operands except for "bound" and
3998 "enter". We also don't reverse intersegment "jmp" and "call"
3999 instructions with 2 immediate operands so that the immediate segment
4000 precedes the offset, as it does when in AT&T mode. */
4003 && (strcmp (mnemonic
, "bound") != 0)
4004 && (strcmp (mnemonic
, "invlpga") != 0)
4005 && !(operand_type_check (i
.types
[0], imm
)
4006 && operand_type_check (i
.types
[1], imm
)))
4009 /* The order of the immediates should be reversed
4010 for 2 immediates extrq and insertq instructions */
4011 if (i
.imm_operands
== 2
4012 && (strcmp (mnemonic
, "extrq") == 0
4013 || strcmp (mnemonic
, "insertq") == 0))
4014 swap_2_operands (0, 1);
4019 /* Don't optimize displacement for movabs since it only takes 64bit
4022 && i
.disp_encoding
!= disp_encoding_32bit
4023 && (flag_code
!= CODE_64BIT
4024 || strcmp (mnemonic
, "movabs") != 0))
4027 /* Next, we find a template that matches the given insn,
4028 making sure the overlap of the given operands types is consistent
4029 with the template operand types. */
4031 if (!(t
= match_template (mnem_suffix
)))
4034 if (sse_check
!= check_none
4035 && !i
.tm
.opcode_modifier
.noavx
4036 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4037 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4038 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4039 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4040 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4041 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4042 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4043 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4044 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4045 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4047 (sse_check
== check_warning
4049 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4052 /* Zap movzx and movsx suffix. The suffix has been set from
4053 "word ptr" or "byte ptr" on the source operand in Intel syntax
4054 or extracted from mnemonic in AT&T syntax. But we'll use
4055 the destination register to choose the suffix for encoding. */
4056 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4058 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4059 there is no suffix, the default will be byte extension. */
4060 if (i
.reg_operands
!= 2
4063 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4068 if (i
.tm
.opcode_modifier
.fwait
)
4069 if (!add_prefix (FWAIT_OPCODE
))
4072 /* Check if REP prefix is OK. */
4073 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4075 as_bad (_("invalid instruction `%s' after `%s'"),
4076 i
.tm
.name
, i
.rep_prefix
);
4080 /* Check for lock without a lockable instruction. Destination operand
4081 must be memory unless it is xchg (0x86). */
4082 if (i
.prefix
[LOCK_PREFIX
]
4083 && (!i
.tm
.opcode_modifier
.islockable
4084 || i
.mem_operands
== 0
4085 || (i
.tm
.base_opcode
!= 0x86
4086 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4088 as_bad (_("expecting lockable instruction after `lock'"));
4092 /* Check if HLE prefix is OK. */
4093 if (i
.hle_prefix
&& !check_hle ())
4096 /* Check BND prefix. */
4097 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4098 as_bad (_("expecting valid branch instruction after `bnd'"));
4100 /* Check NOTRACK prefix. */
4101 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4102 as_bad (_("expecting indirect branch instruction after `notrack'"));
4104 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4106 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4107 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4108 else if (flag_code
!= CODE_16BIT
4109 ? i
.prefix
[ADDR_PREFIX
]
4110 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4111 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4114 /* Insert BND prefix. */
4116 && i
.tm
.opcode_modifier
.bndprefixok
4117 && !i
.prefix
[BND_PREFIX
])
4118 add_prefix (BND_PREFIX_OPCODE
);
4120 /* Check string instruction segment overrides. */
4121 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4123 if (!check_string ())
4125 i
.disp_operands
= 0;
4128 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4129 optimize_encoding ();
4131 if (!process_suffix ())
4134 /* Update operand types. */
4135 for (j
= 0; j
< i
.operands
; j
++)
4136 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4138 /* Make still unresolved immediate matches conform to size of immediate
4139 given in i.suffix. */
4140 if (!finalize_imm ())
4143 if (i
.types
[0].bitfield
.imm1
)
4144 i
.imm_operands
= 0; /* kludge for shift insns. */
4146 /* We only need to check those implicit registers for instructions
4147 with 3 operands or less. */
4148 if (i
.operands
<= 3)
4149 for (j
= 0; j
< i
.operands
; j
++)
4150 if (i
.types
[j
].bitfield
.inoutportreg
4151 || i
.types
[j
].bitfield
.shiftcount
4152 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4155 /* ImmExt should be processed after SSE2AVX. */
4156 if (!i
.tm
.opcode_modifier
.sse2avx
4157 && i
.tm
.opcode_modifier
.immext
)
4160 /* For insns with operands there are more diddles to do to the opcode. */
4163 if (!process_operands ())
4166 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4168 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4169 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4172 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.vexopcode
4173 || is_evex_encoding (&i
.tm
))
4175 if (flag_code
== CODE_16BIT
)
4177 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4182 if (i
.tm
.opcode_modifier
.vex
)
4183 build_vex_prefix (t
);
4185 build_evex_prefix ();
4188 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4189 instructions may define INT_OPCODE as well, so avoid this corner
4190 case for those instructions that use MODRM. */
4191 if (i
.tm
.base_opcode
== INT_OPCODE
4192 && !i
.tm
.opcode_modifier
.modrm
4193 && i
.op
[0].imms
->X_add_number
== 3)
4195 i
.tm
.base_opcode
= INT3_OPCODE
;
4199 if ((i
.tm
.opcode_modifier
.jump
4200 || i
.tm
.opcode_modifier
.jumpbyte
4201 || i
.tm
.opcode_modifier
.jumpdword
)
4202 && i
.op
[0].disps
->X_op
== O_constant
)
4204 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4205 the absolute address given by the constant. Since ix86 jumps and
4206 calls are pc relative, we need to generate a reloc. */
4207 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4208 i
.op
[0].disps
->X_op
= O_symbol
;
4211 if (i
.tm
.opcode_modifier
.rex64
)
4214 /* For 8 bit registers we need an empty rex prefix. Also if the
4215 instruction already has a prefix, we need to convert old
4216 registers to new ones. */
4218 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4219 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4220 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4221 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4222 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4223 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4228 i
.rex
|= REX_OPCODE
;
4229 for (x
= 0; x
< 2; x
++)
4231 /* Look for 8 bit operand that uses old registers. */
4232 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4233 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4235 /* In case it is "hi" register, give up. */
4236 if (i
.op
[x
].regs
->reg_num
> 3)
4237 as_bad (_("can't encode register '%s%s' in an "
4238 "instruction requiring REX prefix."),
4239 register_prefix
, i
.op
[x
].regs
->reg_name
);
4241 /* Otherwise it is equivalent to the extended register.
4242 Since the encoding doesn't change this is merely
4243 cosmetic cleanup for debug output. */
4245 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4250 if (i
.rex
== 0 && i
.rex_encoding
)
4252 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4253 that uses legacy register. If it is "hi" register, don't add
4254 the REX_OPCODE byte. */
4256 for (x
= 0; x
< 2; x
++)
4257 if (i
.types
[x
].bitfield
.reg
4258 && i
.types
[x
].bitfield
.byte
4259 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4260 && i
.op
[x
].regs
->reg_num
> 3)
4262 i
.rex_encoding
= FALSE
;
4271 add_prefix (REX_OPCODE
| i
.rex
);
4273 /* We are ready to output the insn. */
4278 parse_insn (char *line
, char *mnemonic
)
4281 char *token_start
= l
;
4284 const insn_template
*t
;
4290 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4295 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4297 as_bad (_("no such instruction: `%s'"), token_start
);
4302 if (!is_space_char (*l
)
4303 && *l
!= END_OF_INSN
4305 || (*l
!= PREFIX_SEPARATOR
4308 as_bad (_("invalid character %s in mnemonic"),
4309 output_invalid (*l
));
4312 if (token_start
== l
)
4314 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4315 as_bad (_("expecting prefix; got nothing"));
4317 as_bad (_("expecting mnemonic; got nothing"));
4321 /* Look up instruction (or prefix) via hash table. */
4322 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4324 if (*l
!= END_OF_INSN
4325 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4326 && current_templates
4327 && current_templates
->start
->opcode_modifier
.isprefix
)
4329 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4331 as_bad ((flag_code
!= CODE_64BIT
4332 ? _("`%s' is only supported in 64-bit mode")
4333 : _("`%s' is not supported in 64-bit mode")),
4334 current_templates
->start
->name
);
4337 /* If we are in 16-bit mode, do not allow addr16 or data16.
4338 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4339 if ((current_templates
->start
->opcode_modifier
.size16
4340 || current_templates
->start
->opcode_modifier
.size32
)
4341 && flag_code
!= CODE_64BIT
4342 && (current_templates
->start
->opcode_modifier
.size32
4343 ^ (flag_code
== CODE_16BIT
)))
4345 as_bad (_("redundant %s prefix"),
4346 current_templates
->start
->name
);
4349 if (current_templates
->start
->opcode_length
== 0)
4351 /* Handle pseudo prefixes. */
4352 switch (current_templates
->start
->base_opcode
)
4356 i
.disp_encoding
= disp_encoding_8bit
;
4360 i
.disp_encoding
= disp_encoding_32bit
;
4364 i
.dir_encoding
= dir_encoding_load
;
4368 i
.dir_encoding
= dir_encoding_store
;
4372 i
.vec_encoding
= vex_encoding_vex2
;
4376 i
.vec_encoding
= vex_encoding_vex3
;
4380 i
.vec_encoding
= vex_encoding_evex
;
4384 i
.rex_encoding
= TRUE
;
4388 i
.no_optimize
= TRUE
;
4396 /* Add prefix, checking for repeated prefixes. */
4397 switch (add_prefix (current_templates
->start
->base_opcode
))
4402 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4403 i
.notrack_prefix
= current_templates
->start
->name
;
4406 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4407 i
.hle_prefix
= current_templates
->start
->name
;
4408 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4409 i
.bnd_prefix
= current_templates
->start
->name
;
4411 i
.rep_prefix
= current_templates
->start
->name
;
4417 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4424 if (!current_templates
)
4426 /* Check if we should swap operand or force 32bit displacement in
4428 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4429 i
.dir_encoding
= dir_encoding_store
;
4430 else if (mnem_p
- 3 == dot_p
4433 i
.disp_encoding
= disp_encoding_8bit
;
4434 else if (mnem_p
- 4 == dot_p
4438 i
.disp_encoding
= disp_encoding_32bit
;
4443 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4446 if (!current_templates
)
4449 /* See if we can get a match by trimming off a suffix. */
4452 case WORD_MNEM_SUFFIX
:
4453 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4454 i
.suffix
= SHORT_MNEM_SUFFIX
;
4457 case BYTE_MNEM_SUFFIX
:
4458 case QWORD_MNEM_SUFFIX
:
4459 i
.suffix
= mnem_p
[-1];
4461 current_templates
= (const templates
*) hash_find (op_hash
,
4464 case SHORT_MNEM_SUFFIX
:
4465 case LONG_MNEM_SUFFIX
:
4468 i
.suffix
= mnem_p
[-1];
4470 current_templates
= (const templates
*) hash_find (op_hash
,
4479 if (intel_float_operand (mnemonic
) == 1)
4480 i
.suffix
= SHORT_MNEM_SUFFIX
;
4482 i
.suffix
= LONG_MNEM_SUFFIX
;
4484 current_templates
= (const templates
*) hash_find (op_hash
,
4489 if (!current_templates
)
4491 as_bad (_("no such instruction: `%s'"), token_start
);
4496 if (current_templates
->start
->opcode_modifier
.jump
4497 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4499 /* Check for a branch hint. We allow ",pt" and ",pn" for
4500 predict taken and predict not taken respectively.
4501 I'm not sure that branch hints actually do anything on loop
4502 and jcxz insns (JumpByte) for current Pentium4 chips. They
4503 may work in the future and it doesn't hurt to accept them
4505 if (l
[0] == ',' && l
[1] == 'p')
4509 if (!add_prefix (DS_PREFIX_OPCODE
))
4513 else if (l
[2] == 'n')
4515 if (!add_prefix (CS_PREFIX_OPCODE
))
4521 /* Any other comma loses. */
4524 as_bad (_("invalid character %s in mnemonic"),
4525 output_invalid (*l
));
4529 /* Check if instruction is supported on specified architecture. */
4531 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4533 supported
|= cpu_flags_match (t
);
4534 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4536 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4537 as_warn (_("use .code16 to ensure correct addressing mode"));
4543 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4544 as_bad (flag_code
== CODE_64BIT
4545 ? _("`%s' is not supported in 64-bit mode")
4546 : _("`%s' is only supported in 64-bit mode"),
4547 current_templates
->start
->name
);
4549 as_bad (_("`%s' is not supported on `%s%s'"),
4550 current_templates
->start
->name
,
4551 cpu_arch_name
? cpu_arch_name
: default_arch
,
4552 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4558 parse_operands (char *l
, const char *mnemonic
)
4562 /* 1 if operand is pending after ','. */
4563 unsigned int expecting_operand
= 0;
4565 /* Non-zero if operand parens not balanced. */
4566 unsigned int paren_not_balanced
;
4568 while (*l
!= END_OF_INSN
)
4570 /* Skip optional white space before operand. */
4571 if (is_space_char (*l
))
4573 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4575 as_bad (_("invalid character %s before operand %d"),
4576 output_invalid (*l
),
4580 token_start
= l
; /* After white space. */
4581 paren_not_balanced
= 0;
4582 while (paren_not_balanced
|| *l
!= ',')
4584 if (*l
== END_OF_INSN
)
4586 if (paren_not_balanced
)
4589 as_bad (_("unbalanced parenthesis in operand %d."),
4592 as_bad (_("unbalanced brackets in operand %d."),
4597 break; /* we are done */
4599 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4601 as_bad (_("invalid character %s in operand %d"),
4602 output_invalid (*l
),
4609 ++paren_not_balanced
;
4611 --paren_not_balanced
;
4616 ++paren_not_balanced
;
4618 --paren_not_balanced
;
4622 if (l
!= token_start
)
4623 { /* Yes, we've read in another operand. */
4624 unsigned int operand_ok
;
4625 this_operand
= i
.operands
++;
4626 if (i
.operands
> MAX_OPERANDS
)
4628 as_bad (_("spurious operands; (%d operands/instruction max)"),
4632 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4633 /* Now parse operand adding info to 'i' as we go along. */
4634 END_STRING_AND_SAVE (l
);
4638 i386_intel_operand (token_start
,
4639 intel_float_operand (mnemonic
));
4641 operand_ok
= i386_att_operand (token_start
);
4643 RESTORE_END_STRING (l
);
4649 if (expecting_operand
)
4651 expecting_operand_after_comma
:
4652 as_bad (_("expecting operand after ','; got nothing"));
4657 as_bad (_("expecting operand before ','; got nothing"));
4662 /* Now *l must be either ',' or END_OF_INSN. */
4665 if (*++l
== END_OF_INSN
)
4667 /* Just skip it, if it's \n complain. */
4668 goto expecting_operand_after_comma
;
4670 expecting_operand
= 1;
4677 swap_2_operands (int xchg1
, int xchg2
)
4679 union i386_op temp_op
;
4680 i386_operand_type temp_type
;
4681 enum bfd_reloc_code_real temp_reloc
;
4683 temp_type
= i
.types
[xchg2
];
4684 i
.types
[xchg2
] = i
.types
[xchg1
];
4685 i
.types
[xchg1
] = temp_type
;
4686 temp_op
= i
.op
[xchg2
];
4687 i
.op
[xchg2
] = i
.op
[xchg1
];
4688 i
.op
[xchg1
] = temp_op
;
4689 temp_reloc
= i
.reloc
[xchg2
];
4690 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4691 i
.reloc
[xchg1
] = temp_reloc
;
4695 if (i
.mask
->operand
== xchg1
)
4696 i
.mask
->operand
= xchg2
;
4697 else if (i
.mask
->operand
== xchg2
)
4698 i
.mask
->operand
= xchg1
;
4702 if (i
.broadcast
->operand
== xchg1
)
4703 i
.broadcast
->operand
= xchg2
;
4704 else if (i
.broadcast
->operand
== xchg2
)
4705 i
.broadcast
->operand
= xchg1
;
4709 if (i
.rounding
->operand
== xchg1
)
4710 i
.rounding
->operand
= xchg2
;
4711 else if (i
.rounding
->operand
== xchg2
)
4712 i
.rounding
->operand
= xchg1
;
4717 swap_operands (void)
4723 swap_2_operands (1, i
.operands
- 2);
4727 swap_2_operands (0, i
.operands
- 1);
4733 if (i
.mem_operands
== 2)
4735 const seg_entry
*temp_seg
;
4736 temp_seg
= i
.seg
[0];
4737 i
.seg
[0] = i
.seg
[1];
4738 i
.seg
[1] = temp_seg
;
4742 /* Try to ensure constant immediates are represented in the smallest
4747 char guess_suffix
= 0;
4751 guess_suffix
= i
.suffix
;
4752 else if (i
.reg_operands
)
4754 /* Figure out a suffix from the last register operand specified.
4755 We can't do this properly yet, ie. excluding InOutPortReg,
4756 but the following works for instructions with immediates.
4757 In any case, we can't set i.suffix yet. */
4758 for (op
= i
.operands
; --op
>= 0;)
4759 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4761 guess_suffix
= BYTE_MNEM_SUFFIX
;
4764 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4766 guess_suffix
= WORD_MNEM_SUFFIX
;
4769 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4771 guess_suffix
= LONG_MNEM_SUFFIX
;
4774 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4776 guess_suffix
= QWORD_MNEM_SUFFIX
;
4780 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4781 guess_suffix
= WORD_MNEM_SUFFIX
;
4783 for (op
= i
.operands
; --op
>= 0;)
4784 if (operand_type_check (i
.types
[op
], imm
))
4786 switch (i
.op
[op
].imms
->X_op
)
4789 /* If a suffix is given, this operand may be shortened. */
4790 switch (guess_suffix
)
4792 case LONG_MNEM_SUFFIX
:
4793 i
.types
[op
].bitfield
.imm32
= 1;
4794 i
.types
[op
].bitfield
.imm64
= 1;
4796 case WORD_MNEM_SUFFIX
:
4797 i
.types
[op
].bitfield
.imm16
= 1;
4798 i
.types
[op
].bitfield
.imm32
= 1;
4799 i
.types
[op
].bitfield
.imm32s
= 1;
4800 i
.types
[op
].bitfield
.imm64
= 1;
4802 case BYTE_MNEM_SUFFIX
:
4803 i
.types
[op
].bitfield
.imm8
= 1;
4804 i
.types
[op
].bitfield
.imm8s
= 1;
4805 i
.types
[op
].bitfield
.imm16
= 1;
4806 i
.types
[op
].bitfield
.imm32
= 1;
4807 i
.types
[op
].bitfield
.imm32s
= 1;
4808 i
.types
[op
].bitfield
.imm64
= 1;
4812 /* If this operand is at most 16 bits, convert it
4813 to a signed 16 bit number before trying to see
4814 whether it will fit in an even smaller size.
4815 This allows a 16-bit operand such as $0xffe0 to
4816 be recognised as within Imm8S range. */
4817 if ((i
.types
[op
].bitfield
.imm16
)
4818 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4820 i
.op
[op
].imms
->X_add_number
=
4821 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4824 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4825 if ((i
.types
[op
].bitfield
.imm32
)
4826 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4829 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4830 ^ ((offsetT
) 1 << 31))
4831 - ((offsetT
) 1 << 31));
4835 = operand_type_or (i
.types
[op
],
4836 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4838 /* We must avoid matching of Imm32 templates when 64bit
4839 only immediate is available. */
4840 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4841 i
.types
[op
].bitfield
.imm32
= 0;
4848 /* Symbols and expressions. */
4850 /* Convert symbolic operand to proper sizes for matching, but don't
4851 prevent matching a set of insns that only supports sizes other
4852 than those matching the insn suffix. */
4854 i386_operand_type mask
, allowed
;
4855 const insn_template
*t
;
4857 operand_type_set (&mask
, 0);
4858 operand_type_set (&allowed
, 0);
4860 for (t
= current_templates
->start
;
4861 t
< current_templates
->end
;
4863 allowed
= operand_type_or (allowed
,
4864 t
->operand_types
[op
]);
4865 switch (guess_suffix
)
4867 case QWORD_MNEM_SUFFIX
:
4868 mask
.bitfield
.imm64
= 1;
4869 mask
.bitfield
.imm32s
= 1;
4871 case LONG_MNEM_SUFFIX
:
4872 mask
.bitfield
.imm32
= 1;
4874 case WORD_MNEM_SUFFIX
:
4875 mask
.bitfield
.imm16
= 1;
4877 case BYTE_MNEM_SUFFIX
:
4878 mask
.bitfield
.imm8
= 1;
4883 allowed
= operand_type_and (mask
, allowed
);
4884 if (!operand_type_all_zero (&allowed
))
4885 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4892 /* Try to use the smallest displacement type too. */
4894 optimize_disp (void)
4898 for (op
= i
.operands
; --op
>= 0;)
4899 if (operand_type_check (i
.types
[op
], disp
))
4901 if (i
.op
[op
].disps
->X_op
== O_constant
)
4903 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4905 if (i
.types
[op
].bitfield
.disp16
4906 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4908 /* If this operand is at most 16 bits, convert
4909 to a signed 16 bit number and don't use 64bit
4911 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4912 i
.types
[op
].bitfield
.disp64
= 0;
4915 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4916 if (i
.types
[op
].bitfield
.disp32
4917 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4919 /* If this operand is at most 32 bits, convert
4920 to a signed 32 bit number and don't use 64bit
4922 op_disp
&= (((offsetT
) 2 << 31) - 1);
4923 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4924 i
.types
[op
].bitfield
.disp64
= 0;
4927 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4929 i
.types
[op
].bitfield
.disp8
= 0;
4930 i
.types
[op
].bitfield
.disp16
= 0;
4931 i
.types
[op
].bitfield
.disp32
= 0;
4932 i
.types
[op
].bitfield
.disp32s
= 0;
4933 i
.types
[op
].bitfield
.disp64
= 0;
4937 else if (flag_code
== CODE_64BIT
)
4939 if (fits_in_signed_long (op_disp
))
4941 i
.types
[op
].bitfield
.disp64
= 0;
4942 i
.types
[op
].bitfield
.disp32s
= 1;
4944 if (i
.prefix
[ADDR_PREFIX
]
4945 && fits_in_unsigned_long (op_disp
))
4946 i
.types
[op
].bitfield
.disp32
= 1;
4948 if ((i
.types
[op
].bitfield
.disp32
4949 || i
.types
[op
].bitfield
.disp32s
4950 || i
.types
[op
].bitfield
.disp16
)
4951 && fits_in_disp8 (op_disp
))
4952 i
.types
[op
].bitfield
.disp8
= 1;
4954 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4955 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4957 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4958 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4959 i
.types
[op
].bitfield
.disp8
= 0;
4960 i
.types
[op
].bitfield
.disp16
= 0;
4961 i
.types
[op
].bitfield
.disp32
= 0;
4962 i
.types
[op
].bitfield
.disp32s
= 0;
4963 i
.types
[op
].bitfield
.disp64
= 0;
4966 /* We only support 64bit displacement on constants. */
4967 i
.types
[op
].bitfield
.disp64
= 0;
4971 /* Check if operands are valid for the instruction. */
4974 check_VecOperands (const insn_template
*t
)
4978 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
4980 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4981 any one operand are implicity requiring AVX512VL support if the actual
4982 operand size is YMMword or XMMword. Since this function runs after
4983 template matching, there's no need to check for YMMword/XMMword in
4985 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
4986 if (!cpu_flags_all_zero (&cpu
)
4987 && !t
->cpu_flags
.bitfield
.cpuavx512vl
4988 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
4990 for (op
= 0; op
< t
->operands
; ++op
)
4992 if (t
->operand_types
[op
].bitfield
.zmmword
4993 && (i
.types
[op
].bitfield
.ymmword
4994 || i
.types
[op
].bitfield
.xmmword
))
4996 i
.error
= unsupported
;
5002 /* Without VSIB byte, we can't have a vector register for index. */
5003 if (!t
->opcode_modifier
.vecsib
5005 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5006 || i
.index_reg
->reg_type
.bitfield
.ymmword
5007 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5009 i
.error
= unsupported_vector_index_register
;
5013 /* Check if default mask is allowed. */
5014 if (t
->opcode_modifier
.nodefmask
5015 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5017 i
.error
= no_default_mask
;
5021 /* For VSIB byte, we need a vector register for index, and all vector
5022 registers must be distinct. */
5023 if (t
->opcode_modifier
.vecsib
)
5026 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5027 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5028 || (t
->opcode_modifier
.vecsib
== VecSIB256
5029 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5030 || (t
->opcode_modifier
.vecsib
== VecSIB512
5031 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5033 i
.error
= invalid_vsib_address
;
5037 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5038 if (i
.reg_operands
== 2 && !i
.mask
)
5040 gas_assert (i
.types
[0].bitfield
.regsimd
);
5041 gas_assert (i
.types
[0].bitfield
.xmmword
5042 || i
.types
[0].bitfield
.ymmword
);
5043 gas_assert (i
.types
[2].bitfield
.regsimd
);
5044 gas_assert (i
.types
[2].bitfield
.xmmword
5045 || i
.types
[2].bitfield
.ymmword
);
5046 if (operand_check
== check_none
)
5048 if (register_number (i
.op
[0].regs
)
5049 != register_number (i
.index_reg
)
5050 && register_number (i
.op
[2].regs
)
5051 != register_number (i
.index_reg
)
5052 && register_number (i
.op
[0].regs
)
5053 != register_number (i
.op
[2].regs
))
5055 if (operand_check
== check_error
)
5057 i
.error
= invalid_vector_register_set
;
5060 as_warn (_("mask, index, and destination registers should be distinct"));
5062 else if (i
.reg_operands
== 1 && i
.mask
)
5064 if (i
.types
[1].bitfield
.regsimd
5065 && (i
.types
[1].bitfield
.xmmword
5066 || i
.types
[1].bitfield
.ymmword
5067 || i
.types
[1].bitfield
.zmmword
)
5068 && (register_number (i
.op
[1].regs
)
5069 == register_number (i
.index_reg
)))
5071 if (operand_check
== check_error
)
5073 i
.error
= invalid_vector_register_set
;
5076 if (operand_check
!= check_none
)
5077 as_warn (_("index and destination registers should be distinct"));
5082 /* Check if broadcast is supported by the instruction and is applied
5083 to the memory operand. */
5086 i386_operand_type type
, overlap
;
5088 /* Check if specified broadcast is supported in this instruction,
5089 and it's applied to memory operand of DWORD or QWORD type. */
5090 op
= i
.broadcast
->operand
;
5091 if (!t
->opcode_modifier
.broadcast
5092 || !i
.types
[op
].bitfield
.mem
5093 || (!i
.types
[op
].bitfield
.unspecified
5094 && (t
->operand_types
[op
].bitfield
.dword
5095 ? !i
.types
[op
].bitfield
.dword
5096 : !i
.types
[op
].bitfield
.qword
)))
5099 i
.error
= unsupported_broadcast
;
5103 operand_type_set (&type
, 0);
5104 switch ((t
->operand_types
[op
].bitfield
.dword
? 4 : 8) * i
.broadcast
->type
)
5107 type
.bitfield
.qword
= 1;
5110 type
.bitfield
.xmmword
= 1;
5113 type
.bitfield
.ymmword
= 1;
5116 type
.bitfield
.zmmword
= 1;
5122 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5123 if (operand_type_all_zero (&overlap
))
5126 if (t
->opcode_modifier
.checkregsize
)
5130 type
.bitfield
.baseindex
= 1;
5131 for (j
= 0; j
< i
.operands
; ++j
)
5134 && !operand_type_register_match(i
.types
[j
],
5135 t
->operand_types
[j
],
5137 t
->operand_types
[op
]))
5142 /* If broadcast is supported in this instruction, we need to check if
5143 operand of one-element size isn't specified without broadcast. */
5144 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5146 /* Find memory operand. */
5147 for (op
= 0; op
< i
.operands
; op
++)
5148 if (operand_type_check (i
.types
[op
], anymem
))
5150 gas_assert (op
< i
.operands
);
5151 /* Check size of the memory operand. */
5152 if (t
->operand_types
[op
].bitfield
.dword
5153 ? i
.types
[op
].bitfield
.dword
5154 : i
.types
[op
].bitfield
.qword
)
5156 i
.error
= broadcast_needed
;
5161 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5163 /* Check if requested masking is supported. */
5165 && (!t
->opcode_modifier
.masking
5167 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5169 i
.error
= unsupported_masking
;
5173 /* Check if masking is applied to dest operand. */
5174 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5176 i
.error
= mask_not_on_destination
;
5183 if ((i
.rounding
->type
!= saeonly
5184 && !t
->opcode_modifier
.staticrounding
)
5185 || (i
.rounding
->type
== saeonly
5186 && (t
->opcode_modifier
.staticrounding
5187 || !t
->opcode_modifier
.sae
)))
5189 i
.error
= unsupported_rc_sae
;
5192 /* If the instruction has several immediate operands and one of
5193 them is rounding, the rounding operand should be the last
5194 immediate operand. */
5195 if (i
.imm_operands
> 1
5196 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5198 i
.error
= rc_sae_operand_not_last_imm
;
5203 /* Check vector Disp8 operand. */
5204 if (t
->opcode_modifier
.disp8memshift
5205 && i
.disp_encoding
!= disp_encoding_32bit
)
5208 i
.memshift
= t
->operand_types
[op
].bitfield
.dword
? 2 : 3;
5210 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5212 for (op
= 0; op
< i
.operands
; op
++)
5213 if (operand_type_check (i
.types
[op
], disp
)
5214 && i
.op
[op
].disps
->X_op
== O_constant
)
5216 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5218 i
.types
[op
].bitfield
.disp8
= 1;
5221 i
.types
[op
].bitfield
.disp8
= 0;
5230 /* Check if operands are valid for the instruction. Update VEX
5234 VEX_check_operands (const insn_template
*t
)
5236 if (i
.vec_encoding
== vex_encoding_evex
)
5238 /* This instruction must be encoded with EVEX prefix. */
5239 if (!is_evex_encoding (t
))
5241 i
.error
= unsupported
;
5247 if (!t
->opcode_modifier
.vex
)
5249 /* This instruction template doesn't have VEX prefix. */
5250 if (i
.vec_encoding
!= vex_encoding_default
)
5252 i
.error
= unsupported
;
5258 /* Only check VEX_Imm4, which must be the first operand. */
5259 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5261 if (i
.op
[0].imms
->X_op
!= O_constant
5262 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5268 /* Turn off Imm8 so that update_imm won't complain. */
5269 i
.types
[0] = vec_imm4
;
5275 static const insn_template
*
5276 match_template (char mnem_suffix
)
5278 /* Points to template once we've found it. */
5279 const insn_template
*t
;
5280 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5281 i386_operand_type overlap4
;
5282 unsigned int found_reverse_match
;
5283 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5284 i386_operand_type operand_types
[MAX_OPERANDS
];
5285 int addr_prefix_disp
;
5287 unsigned int found_cpu_match
;
5288 unsigned int check_register
;
5289 enum i386_error specific_error
= 0;
5291 #if MAX_OPERANDS != 5
5292 # error "MAX_OPERANDS must be 5."
5295 found_reverse_match
= 0;
5296 addr_prefix_disp
= -1;
5298 memset (&suffix_check
, 0, sizeof (suffix_check
));
5299 if (intel_syntax
&& i
.broadcast
)
5301 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5302 suffix_check
.no_bsuf
= 1;
5303 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5304 suffix_check
.no_wsuf
= 1;
5305 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5306 suffix_check
.no_ssuf
= 1;
5307 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5308 suffix_check
.no_lsuf
= 1;
5309 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5310 suffix_check
.no_qsuf
= 1;
5311 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5312 suffix_check
.no_ldsuf
= 1;
5314 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5317 switch (mnem_suffix
)
5319 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5320 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5321 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5322 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5323 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5327 /* Must have right number of operands. */
5328 i
.error
= number_of_operands_mismatch
;
5330 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5332 addr_prefix_disp
= -1;
5334 if (i
.operands
!= t
->operands
)
5337 /* Check processor support. */
5338 i
.error
= unsupported
;
5339 found_cpu_match
= (cpu_flags_match (t
)
5340 == CPU_FLAGS_PERFECT_MATCH
);
5341 if (!found_cpu_match
)
5344 /* Check AT&T mnemonic. */
5345 i
.error
= unsupported_with_intel_mnemonic
;
5346 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5349 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5350 i
.error
= unsupported_syntax
;
5351 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5352 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5353 || (intel64
&& t
->opcode_modifier
.amd64
)
5354 || (!intel64
&& t
->opcode_modifier
.intel64
))
5357 /* Check the suffix, except for some instructions in intel mode. */
5358 i
.error
= invalid_instruction_suffix
;
5359 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5360 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5361 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5362 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5363 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5364 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5365 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5367 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5368 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5369 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5370 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5371 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5372 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5373 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5376 if (!operand_size_match (t
))
5379 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5380 operand_types
[j
] = t
->operand_types
[j
];
5382 /* In general, don't allow 64-bit operands in 32-bit mode. */
5383 if (i
.suffix
== QWORD_MNEM_SUFFIX
5384 && flag_code
!= CODE_64BIT
5386 ? (!t
->opcode_modifier
.ignoresize
5387 && !intel_float_operand (t
->name
))
5388 : intel_float_operand (t
->name
) != 2)
5389 && ((!operand_types
[0].bitfield
.regmmx
5390 && !operand_types
[0].bitfield
.regsimd
)
5391 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5392 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5393 && (t
->base_opcode
!= 0x0fc7
5394 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5397 /* In general, don't allow 32-bit operands on pre-386. */
5398 else if (i
.suffix
== LONG_MNEM_SUFFIX
5399 && !cpu_arch_flags
.bitfield
.cpui386
5401 ? (!t
->opcode_modifier
.ignoresize
5402 && !intel_float_operand (t
->name
))
5403 : intel_float_operand (t
->name
) != 2)
5404 && ((!operand_types
[0].bitfield
.regmmx
5405 && !operand_types
[0].bitfield
.regsimd
)
5406 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5407 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5410 /* Do not verify operands when there are none. */
5414 /* We've found a match; break out of loop. */
5418 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5419 into Disp32/Disp16/Disp32 operand. */
5420 if (i
.prefix
[ADDR_PREFIX
] != 0)
5422 /* There should be only one Disp operand. */
5426 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5428 if (operand_types
[j
].bitfield
.disp16
)
5430 addr_prefix_disp
= j
;
5431 operand_types
[j
].bitfield
.disp32
= 1;
5432 operand_types
[j
].bitfield
.disp16
= 0;
5438 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5440 if (operand_types
[j
].bitfield
.disp32
)
5442 addr_prefix_disp
= j
;
5443 operand_types
[j
].bitfield
.disp32
= 0;
5444 operand_types
[j
].bitfield
.disp16
= 1;
5450 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5452 if (operand_types
[j
].bitfield
.disp64
)
5454 addr_prefix_disp
= j
;
5455 operand_types
[j
].bitfield
.disp64
= 0;
5456 operand_types
[j
].bitfield
.disp32
= 1;
5464 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5465 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5468 /* We check register size if needed. */
5469 if (t
->opcode_modifier
.checkregsize
)
5471 check_register
= (1 << t
->operands
) - 1;
5473 check_register
&= ~(1 << i
.broadcast
->operand
);
5478 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5479 switch (t
->operands
)
5482 if (!operand_type_match (overlap0
, i
.types
[0]))
5486 /* xchg %eax, %eax is a special case. It is an alias for nop
5487 only in 32bit mode and we can use opcode 0x90. In 64bit
5488 mode, we can't use 0x90 for xchg %eax, %eax since it should
5489 zero-extend %eax to %rax. */
5490 if (flag_code
== CODE_64BIT
5491 && t
->base_opcode
== 0x90
5492 && operand_type_equal (&i
.types
[0], &acc32
)
5493 && operand_type_equal (&i
.types
[1], &acc32
))
5495 /* xrelease mov %eax, <disp> is another special case. It must not
5496 match the accumulator-only encoding of mov. */
5497 if (flag_code
!= CODE_64BIT
5499 && t
->base_opcode
== 0xa0
5500 && i
.types
[0].bitfield
.acc
5501 && operand_type_check (i
.types
[1], anymem
))
5503 /* If we want store form, we reverse direction of operands. */
5504 if (i
.dir_encoding
== dir_encoding_store
5505 && t
->opcode_modifier
.d
)
5510 /* If we want store form, we skip the current load. */
5511 if (i
.dir_encoding
== dir_encoding_store
5512 && i
.mem_operands
== 0
5513 && t
->opcode_modifier
.load
)
5518 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5519 if (!operand_type_match (overlap0
, i
.types
[0])
5520 || !operand_type_match (overlap1
, i
.types
[1])
5521 || ((check_register
& 3) == 3
5522 && !operand_type_register_match (i
.types
[0],
5527 /* Check if other direction is valid ... */
5528 if (!t
->opcode_modifier
.d
)
5532 /* Try reversing direction of operands. */
5533 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5534 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5535 if (!operand_type_match (overlap0
, i
.types
[0])
5536 || !operand_type_match (overlap1
, i
.types
[1])
5538 && !operand_type_register_match (i
.types
[0],
5543 /* Does not match either direction. */
5546 /* found_reverse_match holds which of D or FloatR
5548 if (!t
->opcode_modifier
.d
)
5549 found_reverse_match
= 0;
5550 else if (operand_types
[0].bitfield
.tbyte
)
5551 found_reverse_match
= Opcode_FloatD
;
5553 found_reverse_match
= Opcode_D
;
5554 if (t
->opcode_modifier
.floatr
)
5555 found_reverse_match
|= Opcode_FloatR
;
5559 /* Found a forward 2 operand match here. */
5560 switch (t
->operands
)
5563 overlap4
= operand_type_and (i
.types
[4],
5567 overlap3
= operand_type_and (i
.types
[3],
5571 overlap2
= operand_type_and (i
.types
[2],
5576 switch (t
->operands
)
5579 if (!operand_type_match (overlap4
, i
.types
[4])
5580 || !operand_type_register_match (i
.types
[3],
5587 if (!operand_type_match (overlap3
, i
.types
[3])
5588 || ((check_register
& 0xa) == 0xa
5589 && !operand_type_register_match (i
.types
[1],
5593 || ((check_register
& 0xc) == 0xc
5594 && !operand_type_register_match (i
.types
[2],
5601 /* Here we make use of the fact that there are no
5602 reverse match 3 operand instructions. */
5603 if (!operand_type_match (overlap2
, i
.types
[2])
5604 || ((check_register
& 5) == 5
5605 && !operand_type_register_match (i
.types
[0],
5609 || ((check_register
& 6) == 6
5610 && !operand_type_register_match (i
.types
[1],
5618 /* Found either forward/reverse 2, 3 or 4 operand match here:
5619 slip through to break. */
5621 if (!found_cpu_match
)
5623 found_reverse_match
= 0;
5627 /* Check if vector and VEX operands are valid. */
5628 if (check_VecOperands (t
) || VEX_check_operands (t
))
5630 specific_error
= i
.error
;
5634 /* We've found a match; break out of loop. */
5638 if (t
== current_templates
->end
)
5640 /* We found no match. */
5641 const char *err_msg
;
5642 switch (specific_error
? specific_error
: i
.error
)
5646 case operand_size_mismatch
:
5647 err_msg
= _("operand size mismatch");
5649 case operand_type_mismatch
:
5650 err_msg
= _("operand type mismatch");
5652 case register_type_mismatch
:
5653 err_msg
= _("register type mismatch");
5655 case number_of_operands_mismatch
:
5656 err_msg
= _("number of operands mismatch");
5658 case invalid_instruction_suffix
:
5659 err_msg
= _("invalid instruction suffix");
5662 err_msg
= _("constant doesn't fit in 4 bits");
5664 case unsupported_with_intel_mnemonic
:
5665 err_msg
= _("unsupported with Intel mnemonic");
5667 case unsupported_syntax
:
5668 err_msg
= _("unsupported syntax");
5671 as_bad (_("unsupported instruction `%s'"),
5672 current_templates
->start
->name
);
5674 case invalid_vsib_address
:
5675 err_msg
= _("invalid VSIB address");
5677 case invalid_vector_register_set
:
5678 err_msg
= _("mask, index, and destination registers must be distinct");
5680 case unsupported_vector_index_register
:
5681 err_msg
= _("unsupported vector index register");
5683 case unsupported_broadcast
:
5684 err_msg
= _("unsupported broadcast");
5686 case broadcast_not_on_src_operand
:
5687 err_msg
= _("broadcast not on source memory operand");
5689 case broadcast_needed
:
5690 err_msg
= _("broadcast is needed for operand of such type");
5692 case unsupported_masking
:
5693 err_msg
= _("unsupported masking");
5695 case mask_not_on_destination
:
5696 err_msg
= _("mask not on destination operand");
5698 case no_default_mask
:
5699 err_msg
= _("default mask isn't allowed");
5701 case unsupported_rc_sae
:
5702 err_msg
= _("unsupported static rounding/sae");
5704 case rc_sae_operand_not_last_imm
:
5706 err_msg
= _("RC/SAE operand must precede immediate operands");
5708 err_msg
= _("RC/SAE operand must follow immediate operands");
5710 case invalid_register_operand
:
5711 err_msg
= _("invalid register operand");
5714 as_bad (_("%s for `%s'"), err_msg
,
5715 current_templates
->start
->name
);
5719 if (!quiet_warnings
)
5722 && (i
.types
[0].bitfield
.jumpabsolute
5723 != operand_types
[0].bitfield
.jumpabsolute
))
5725 as_warn (_("indirect %s without `*'"), t
->name
);
5728 if (t
->opcode_modifier
.isprefix
5729 && t
->opcode_modifier
.ignoresize
)
5731 /* Warn them that a data or address size prefix doesn't
5732 affect assembly of the next line of code. */
5733 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5737 /* Copy the template we found. */
5740 if (addr_prefix_disp
!= -1)
5741 i
.tm
.operand_types
[addr_prefix_disp
]
5742 = operand_types
[addr_prefix_disp
];
5744 if (found_reverse_match
)
5746 /* If we found a reverse match we must alter the opcode
5747 direction bit. found_reverse_match holds bits to change
5748 (different for int & float insns). */
5750 i
.tm
.base_opcode
^= found_reverse_match
;
5752 i
.tm
.operand_types
[0] = operand_types
[1];
5753 i
.tm
.operand_types
[1] = operand_types
[0];
5762 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5763 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5765 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5767 as_bad (_("`%s' operand %d must use `%ses' segment"),
5773 /* There's only ever one segment override allowed per instruction.
5774 This instruction possibly has a legal segment override on the
5775 second operand, so copy the segment to where non-string
5776 instructions store it, allowing common code. */
5777 i
.seg
[0] = i
.seg
[1];
5779 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5781 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5783 as_bad (_("`%s' operand %d must use `%ses' segment"),
5794 process_suffix (void)
5796 /* If matched instruction specifies an explicit instruction mnemonic
5798 if (i
.tm
.opcode_modifier
.size16
)
5799 i
.suffix
= WORD_MNEM_SUFFIX
;
5800 else if (i
.tm
.opcode_modifier
.size32
)
5801 i
.suffix
= LONG_MNEM_SUFFIX
;
5802 else if (i
.tm
.opcode_modifier
.size64
)
5803 i
.suffix
= QWORD_MNEM_SUFFIX
;
5804 else if (i
.reg_operands
)
5806 /* If there's no instruction mnemonic suffix we try to invent one
5807 based on register operands. */
5810 /* We take i.suffix from the last register operand specified,
5811 Destination register type is more significant than source
5812 register type. crc32 in SSE4.2 prefers source register
5814 if (i
.tm
.base_opcode
== 0xf20f38f1)
5816 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5817 i
.suffix
= WORD_MNEM_SUFFIX
;
5818 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5819 i
.suffix
= LONG_MNEM_SUFFIX
;
5820 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5821 i
.suffix
= QWORD_MNEM_SUFFIX
;
5823 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5825 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5826 i
.suffix
= BYTE_MNEM_SUFFIX
;
5833 if (i
.tm
.base_opcode
== 0xf20f38f1
5834 || i
.tm
.base_opcode
== 0xf20f38f0)
5836 /* We have to know the operand size for crc32. */
5837 as_bad (_("ambiguous memory operand size for `%s`"),
5842 for (op
= i
.operands
; --op
>= 0;)
5843 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5844 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5846 if (!i
.types
[op
].bitfield
.reg
)
5848 if (i
.types
[op
].bitfield
.byte
)
5849 i
.suffix
= BYTE_MNEM_SUFFIX
;
5850 else if (i
.types
[op
].bitfield
.word
)
5851 i
.suffix
= WORD_MNEM_SUFFIX
;
5852 else if (i
.types
[op
].bitfield
.dword
)
5853 i
.suffix
= LONG_MNEM_SUFFIX
;
5854 else if (i
.types
[op
].bitfield
.qword
)
5855 i
.suffix
= QWORD_MNEM_SUFFIX
;
5862 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5865 && i
.tm
.opcode_modifier
.ignoresize
5866 && i
.tm
.opcode_modifier
.no_bsuf
)
5868 else if (!check_byte_reg ())
5871 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5874 && i
.tm
.opcode_modifier
.ignoresize
5875 && i
.tm
.opcode_modifier
.no_lsuf
5876 && !i
.tm
.opcode_modifier
.todword
5877 && !i
.tm
.opcode_modifier
.toqword
)
5879 else if (!check_long_reg ())
5882 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5885 && i
.tm
.opcode_modifier
.ignoresize
5886 && i
.tm
.opcode_modifier
.no_qsuf
5887 && !i
.tm
.opcode_modifier
.todword
5888 && !i
.tm
.opcode_modifier
.toqword
)
5890 else if (!check_qword_reg ())
5893 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5896 && i
.tm
.opcode_modifier
.ignoresize
5897 && i
.tm
.opcode_modifier
.no_wsuf
)
5899 else if (!check_word_reg ())
5902 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5903 /* Do nothing if the instruction is going to ignore the prefix. */
5908 else if (i
.tm
.opcode_modifier
.defaultsize
5910 /* exclude fldenv/frstor/fsave/fstenv */
5911 && i
.tm
.opcode_modifier
.no_ssuf
)
5913 i
.suffix
= stackop_size
;
5915 else if (intel_syntax
5917 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5918 || i
.tm
.opcode_modifier
.jumpbyte
5919 || i
.tm
.opcode_modifier
.jumpintersegment
5920 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5921 && i
.tm
.extension_opcode
<= 3)))
5926 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5928 i
.suffix
= QWORD_MNEM_SUFFIX
;
5933 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5934 i
.suffix
= LONG_MNEM_SUFFIX
;
5937 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5938 i
.suffix
= WORD_MNEM_SUFFIX
;
5947 if (i
.tm
.opcode_modifier
.w
)
5949 as_bad (_("no instruction mnemonic suffix given and "
5950 "no register operands; can't size instruction"));
5956 unsigned int suffixes
;
5958 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5959 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5961 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5963 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5965 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5967 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5970 /* There are more than suffix matches. */
5971 if (i
.tm
.opcode_modifier
.w
5972 || ((suffixes
& (suffixes
- 1))
5973 && !i
.tm
.opcode_modifier
.defaultsize
5974 && !i
.tm
.opcode_modifier
.ignoresize
))
5976 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5982 /* Change the opcode based on the operand size given by i.suffix. */
5985 /* Size floating point instruction. */
5986 case LONG_MNEM_SUFFIX
:
5987 if (i
.tm
.opcode_modifier
.floatmf
)
5989 i
.tm
.base_opcode
^= 4;
5993 case WORD_MNEM_SUFFIX
:
5994 case QWORD_MNEM_SUFFIX
:
5995 /* It's not a byte, select word/dword operation. */
5996 if (i
.tm
.opcode_modifier
.w
)
5998 if (i
.tm
.opcode_modifier
.shortform
)
5999 i
.tm
.base_opcode
|= 8;
6001 i
.tm
.base_opcode
|= 1;
6004 case SHORT_MNEM_SUFFIX
:
6005 /* Now select between word & dword operations via the operand
6006 size prefix, except for instructions that will ignore this
6008 if (i
.reg_operands
> 0
6009 && i
.types
[0].bitfield
.reg
6010 && i
.tm
.opcode_modifier
.addrprefixopreg
6011 && (i
.tm
.opcode_modifier
.immext
6012 || i
.operands
== 1))
6014 /* The address size override prefix changes the size of the
6016 if ((flag_code
== CODE_32BIT
6017 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6018 || (flag_code
!= CODE_32BIT
6019 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6020 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6023 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6024 && !i
.tm
.opcode_modifier
.ignoresize
6025 && !i
.tm
.opcode_modifier
.floatmf
6026 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6027 || (flag_code
== CODE_64BIT
6028 && i
.tm
.opcode_modifier
.jumpbyte
)))
6030 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6032 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6033 prefix
= ADDR_PREFIX_OPCODE
;
6035 if (!add_prefix (prefix
))
6039 /* Set mode64 for an operand. */
6040 if (i
.suffix
== QWORD_MNEM_SUFFIX
6041 && flag_code
== CODE_64BIT
6042 && !i
.tm
.opcode_modifier
.norex64
6043 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6045 && ! (i
.operands
== 2
6046 && i
.tm
.base_opcode
== 0x90
6047 && i
.tm
.extension_opcode
== None
6048 && operand_type_equal (&i
.types
[0], &acc64
)
6049 && operand_type_equal (&i
.types
[1], &acc64
)))
6055 if (i
.reg_operands
!= 0
6057 && i
.tm
.opcode_modifier
.addrprefixopreg
6058 && !i
.tm
.opcode_modifier
.immext
)
6060 /* Check invalid register operand when the address size override
6061 prefix changes the size of register operands. */
6063 enum { need_word
, need_dword
, need_qword
} need
;
6065 if (flag_code
== CODE_32BIT
)
6066 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6069 if (i
.prefix
[ADDR_PREFIX
])
6072 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6075 for (op
= 0; op
< i
.operands
; op
++)
6076 if (i
.types
[op
].bitfield
.reg
6077 && ((need
== need_word
6078 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6079 || (need
== need_dword
6080 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6081 || (need
== need_qword
6082 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6084 as_bad (_("invalid register operand size for `%s'"),
6094 check_byte_reg (void)
6098 for (op
= i
.operands
; --op
>= 0;)
6100 /* Skip non-register operands. */
6101 if (!i
.types
[op
].bitfield
.reg
)
6104 /* If this is an eight bit register, it's OK. If it's the 16 or
6105 32 bit version of an eight bit register, we will just use the
6106 low portion, and that's OK too. */
6107 if (i
.types
[op
].bitfield
.byte
)
6110 /* I/O port address operands are OK too. */
6111 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6114 /* crc32 doesn't generate this warning. */
6115 if (i
.tm
.base_opcode
== 0xf20f38f0)
6118 if ((i
.types
[op
].bitfield
.word
6119 || i
.types
[op
].bitfield
.dword
6120 || i
.types
[op
].bitfield
.qword
)
6121 && i
.op
[op
].regs
->reg_num
< 4
6122 /* Prohibit these changes in 64bit mode, since the lowering
6123 would be more complicated. */
6124 && flag_code
!= CODE_64BIT
)
6126 #if REGISTER_WARNINGS
6127 if (!quiet_warnings
)
6128 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6130 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6131 ? REGNAM_AL
- REGNAM_AX
6132 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6134 i
.op
[op
].regs
->reg_name
,
6139 /* Any other register is bad. */
6140 if (i
.types
[op
].bitfield
.reg
6141 || i
.types
[op
].bitfield
.regmmx
6142 || i
.types
[op
].bitfield
.regsimd
6143 || i
.types
[op
].bitfield
.sreg2
6144 || i
.types
[op
].bitfield
.sreg3
6145 || i
.types
[op
].bitfield
.control
6146 || i
.types
[op
].bitfield
.debug
6147 || i
.types
[op
].bitfield
.test
)
6149 as_bad (_("`%s%s' not allowed with `%s%c'"),
6151 i
.op
[op
].regs
->reg_name
,
6161 check_long_reg (void)
6165 for (op
= i
.operands
; --op
>= 0;)
6166 /* Skip non-register operands. */
6167 if (!i
.types
[op
].bitfield
.reg
)
6169 /* Reject eight bit registers, except where the template requires
6170 them. (eg. movzb) */
6171 else if (i
.types
[op
].bitfield
.byte
6172 && (i
.tm
.operand_types
[op
].bitfield
.reg
6173 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6174 && (i
.tm
.operand_types
[op
].bitfield
.word
6175 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6177 as_bad (_("`%s%s' not allowed with `%s%c'"),
6179 i
.op
[op
].regs
->reg_name
,
6184 /* Warn if the e prefix on a general reg is missing. */
6185 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6186 && i
.types
[op
].bitfield
.word
6187 && (i
.tm
.operand_types
[op
].bitfield
.reg
6188 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6189 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6191 /* Prohibit these changes in the 64bit mode, since the
6192 lowering is more complicated. */
6193 if (flag_code
== CODE_64BIT
)
6195 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6196 register_prefix
, i
.op
[op
].regs
->reg_name
,
6200 #if REGISTER_WARNINGS
6201 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6203 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6204 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6207 /* Warn if the r prefix on a general reg is present. */
6208 else if (i
.types
[op
].bitfield
.qword
6209 && (i
.tm
.operand_types
[op
].bitfield
.reg
6210 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6211 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6214 && i
.tm
.opcode_modifier
.toqword
6215 && !i
.types
[0].bitfield
.regsimd
)
6217 /* Convert to QWORD. We want REX byte. */
6218 i
.suffix
= QWORD_MNEM_SUFFIX
;
6222 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6223 register_prefix
, i
.op
[op
].regs
->reg_name
,
6232 check_qword_reg (void)
6236 for (op
= i
.operands
; --op
>= 0; )
6237 /* Skip non-register operands. */
6238 if (!i
.types
[op
].bitfield
.reg
)
6240 /* Reject eight bit registers, except where the template requires
6241 them. (eg. movzb) */
6242 else if (i
.types
[op
].bitfield
.byte
6243 && (i
.tm
.operand_types
[op
].bitfield
.reg
6244 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6245 && (i
.tm
.operand_types
[op
].bitfield
.word
6246 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6248 as_bad (_("`%s%s' not allowed with `%s%c'"),
6250 i
.op
[op
].regs
->reg_name
,
6255 /* Warn if the r prefix on a general reg is missing. */
6256 else if ((i
.types
[op
].bitfield
.word
6257 || i
.types
[op
].bitfield
.dword
)
6258 && (i
.tm
.operand_types
[op
].bitfield
.reg
6259 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6260 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6262 /* Prohibit these changes in the 64bit mode, since the
6263 lowering is more complicated. */
6265 && i
.tm
.opcode_modifier
.todword
6266 && !i
.types
[0].bitfield
.regsimd
)
6268 /* Convert to DWORD. We don't want REX byte. */
6269 i
.suffix
= LONG_MNEM_SUFFIX
;
6273 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6274 register_prefix
, i
.op
[op
].regs
->reg_name
,
6283 check_word_reg (void)
6286 for (op
= i
.operands
; --op
>= 0;)
6287 /* Skip non-register operands. */
6288 if (!i
.types
[op
].bitfield
.reg
)
6290 /* Reject eight bit registers, except where the template requires
6291 them. (eg. movzb) */
6292 else if (i
.types
[op
].bitfield
.byte
6293 && (i
.tm
.operand_types
[op
].bitfield
.reg
6294 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6295 && (i
.tm
.operand_types
[op
].bitfield
.word
6296 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6298 as_bad (_("`%s%s' not allowed with `%s%c'"),
6300 i
.op
[op
].regs
->reg_name
,
6305 /* Warn if the e or r prefix on a general reg is present. */
6306 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6307 && (i
.types
[op
].bitfield
.dword
6308 || i
.types
[op
].bitfield
.qword
)
6309 && (i
.tm
.operand_types
[op
].bitfield
.reg
6310 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6311 && i
.tm
.operand_types
[op
].bitfield
.word
)
6313 /* Prohibit these changes in the 64bit mode, since the
6314 lowering is more complicated. */
6315 if (flag_code
== CODE_64BIT
)
6317 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6318 register_prefix
, i
.op
[op
].regs
->reg_name
,
6322 #if REGISTER_WARNINGS
6323 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6325 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6326 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6333 update_imm (unsigned int j
)
6335 i386_operand_type overlap
= i
.types
[j
];
6336 if ((overlap
.bitfield
.imm8
6337 || overlap
.bitfield
.imm8s
6338 || overlap
.bitfield
.imm16
6339 || overlap
.bitfield
.imm32
6340 || overlap
.bitfield
.imm32s
6341 || overlap
.bitfield
.imm64
)
6342 && !operand_type_equal (&overlap
, &imm8
)
6343 && !operand_type_equal (&overlap
, &imm8s
)
6344 && !operand_type_equal (&overlap
, &imm16
)
6345 && !operand_type_equal (&overlap
, &imm32
)
6346 && !operand_type_equal (&overlap
, &imm32s
)
6347 && !operand_type_equal (&overlap
, &imm64
))
6351 i386_operand_type temp
;
6353 operand_type_set (&temp
, 0);
6354 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6356 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6357 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6359 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6360 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6361 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6363 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6364 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6367 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6370 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6371 || operand_type_equal (&overlap
, &imm16_32
)
6372 || operand_type_equal (&overlap
, &imm16_32s
))
6374 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6379 if (!operand_type_equal (&overlap
, &imm8
)
6380 && !operand_type_equal (&overlap
, &imm8s
)
6381 && !operand_type_equal (&overlap
, &imm16
)
6382 && !operand_type_equal (&overlap
, &imm32
)
6383 && !operand_type_equal (&overlap
, &imm32s
)
6384 && !operand_type_equal (&overlap
, &imm64
))
6386 as_bad (_("no instruction mnemonic suffix given; "
6387 "can't determine immediate size"));
6391 i
.types
[j
] = overlap
;
6401 /* Update the first 2 immediate operands. */
6402 n
= i
.operands
> 2 ? 2 : i
.operands
;
6405 for (j
= 0; j
< n
; j
++)
6406 if (update_imm (j
) == 0)
6409 /* The 3rd operand can't be immediate operand. */
6410 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6417 process_operands (void)
6419 /* Default segment register this instruction will use for memory
6420 accesses. 0 means unknown. This is only for optimizing out
6421 unnecessary segment overrides. */
6422 const seg_entry
*default_seg
= 0;
6424 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6426 unsigned int dupl
= i
.operands
;
6427 unsigned int dest
= dupl
- 1;
6430 /* The destination must be an xmm register. */
6431 gas_assert (i
.reg_operands
6432 && MAX_OPERANDS
> dupl
6433 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6435 if (i
.tm
.operand_types
[0].bitfield
.acc
6436 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6438 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6440 /* Keep xmm0 for instructions with VEX prefix and 3
6442 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6443 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6448 /* We remove the first xmm0 and keep the number of
6449 operands unchanged, which in fact duplicates the
6451 for (j
= 1; j
< i
.operands
; j
++)
6453 i
.op
[j
- 1] = i
.op
[j
];
6454 i
.types
[j
- 1] = i
.types
[j
];
6455 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6459 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6461 gas_assert ((MAX_OPERANDS
- 1) > dupl
6462 && (i
.tm
.opcode_modifier
.vexsources
6465 /* Add the implicit xmm0 for instructions with VEX prefix
6467 for (j
= i
.operands
; j
> 0; j
--)
6469 i
.op
[j
] = i
.op
[j
- 1];
6470 i
.types
[j
] = i
.types
[j
- 1];
6471 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6474 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6475 i
.types
[0] = regxmm
;
6476 i
.tm
.operand_types
[0] = regxmm
;
6479 i
.reg_operands
+= 2;
6484 i
.op
[dupl
] = i
.op
[dest
];
6485 i
.types
[dupl
] = i
.types
[dest
];
6486 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6495 i
.op
[dupl
] = i
.op
[dest
];
6496 i
.types
[dupl
] = i
.types
[dest
];
6497 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6500 if (i
.tm
.opcode_modifier
.immext
)
6503 else if (i
.tm
.operand_types
[0].bitfield
.acc
6504 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6508 for (j
= 1; j
< i
.operands
; j
++)
6510 i
.op
[j
- 1] = i
.op
[j
];
6511 i
.types
[j
- 1] = i
.types
[j
];
6513 /* We need to adjust fields in i.tm since they are used by
6514 build_modrm_byte. */
6515 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6522 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6524 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6526 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6527 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6528 regnum
= register_number (i
.op
[1].regs
);
6529 first_reg_in_group
= regnum
& ~3;
6530 last_reg_in_group
= first_reg_in_group
+ 3;
6531 if (regnum
!= first_reg_in_group
)
6532 as_warn (_("source register `%s%s' implicitly denotes"
6533 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6534 register_prefix
, i
.op
[1].regs
->reg_name
,
6535 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6536 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6539 else if (i
.tm
.opcode_modifier
.regkludge
)
6541 /* The imul $imm, %reg instruction is converted into
6542 imul $imm, %reg, %reg, and the clr %reg instruction
6543 is converted into xor %reg, %reg. */
6545 unsigned int first_reg_op
;
6547 if (operand_type_check (i
.types
[0], reg
))
6551 /* Pretend we saw the extra register operand. */
6552 gas_assert (i
.reg_operands
== 1
6553 && i
.op
[first_reg_op
+ 1].regs
== 0);
6554 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6555 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6560 if (i
.tm
.opcode_modifier
.shortform
)
6562 if (i
.types
[0].bitfield
.sreg2
6563 || i
.types
[0].bitfield
.sreg3
)
6565 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6566 && i
.op
[0].regs
->reg_num
== 1)
6568 as_bad (_("you can't `pop %scs'"), register_prefix
);
6571 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6572 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6577 /* The register or float register operand is in operand
6581 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6582 || operand_type_check (i
.types
[0], reg
))
6586 /* Register goes in low 3 bits of opcode. */
6587 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6588 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6590 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6592 /* Warn about some common errors, but press on regardless.
6593 The first case can be generated by gcc (<= 2.8.1). */
6594 if (i
.operands
== 2)
6596 /* Reversed arguments on faddp, fsubp, etc. */
6597 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6598 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6599 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6603 /* Extraneous `l' suffix on fp insn. */
6604 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6605 register_prefix
, i
.op
[0].regs
->reg_name
);
6610 else if (i
.tm
.opcode_modifier
.modrm
)
6612 /* The opcode is completed (modulo i.tm.extension_opcode which
6613 must be put into the modrm byte). Now, we make the modrm and
6614 index base bytes based on all the info we've collected. */
6616 default_seg
= build_modrm_byte ();
6618 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6622 else if (i
.tm
.opcode_modifier
.isstring
)
6624 /* For the string instructions that allow a segment override
6625 on one of their operands, the default segment is ds. */
6629 if (i
.tm
.base_opcode
== 0x8d /* lea */
6632 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6634 /* If a segment was explicitly specified, and the specified segment
6635 is not the default, use an opcode prefix to select it. If we
6636 never figured out what the default segment is, then default_seg
6637 will be zero at this point, and the specified segment prefix will
6639 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6641 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6647 static const seg_entry
*
6648 build_modrm_byte (void)
6650 const seg_entry
*default_seg
= 0;
6651 unsigned int source
, dest
;
6654 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6657 unsigned int nds
, reg_slot
;
6660 dest
= i
.operands
- 1;
6663 /* There are 2 kinds of instructions:
6664 1. 5 operands: 4 register operands or 3 register operands
6665 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6666 VexW0 or VexW1. The destination must be either XMM, YMM or
6668 2. 4 operands: 4 register operands or 3 register operands
6669 plus 1 memory operand, with VexXDS. */
6670 gas_assert ((i
.reg_operands
== 4
6671 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6672 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6673 && i
.tm
.opcode_modifier
.vexw
6674 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
6676 /* If VexW1 is set, the first non-immediate operand is the source and
6677 the second non-immediate one is encoded in the immediate operand. */
6678 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6680 source
= i
.imm_operands
;
6681 reg_slot
= i
.imm_operands
+ 1;
6685 source
= i
.imm_operands
+ 1;
6686 reg_slot
= i
.imm_operands
;
6689 if (i
.imm_operands
== 0)
6691 /* When there is no immediate operand, generate an 8bit
6692 immediate operand to encode the first operand. */
6693 exp
= &im_expressions
[i
.imm_operands
++];
6694 i
.op
[i
.operands
].imms
= exp
;
6695 i
.types
[i
.operands
] = imm8
;
6698 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6699 exp
->X_op
= O_constant
;
6700 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6701 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6705 unsigned int imm_slot
;
6707 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
6709 if (i
.tm
.opcode_modifier
.immext
)
6711 /* When ImmExt is set, the immediate byte is the last
6713 imm_slot
= i
.operands
- 1;
6721 /* Turn on Imm8 so that output_imm will generate it. */
6722 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6725 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6726 i
.op
[imm_slot
].imms
->X_add_number
6727 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6728 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6731 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6732 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6737 /* i.reg_operands MUST be the number of real register operands;
6738 implicit registers do not count. If there are 3 register
6739 operands, it must be a instruction with VexNDS. For a
6740 instruction with VexNDD, the destination register is encoded
6741 in VEX prefix. If there are 4 register operands, it must be
6742 a instruction with VEX prefix and 3 sources. */
6743 if (i
.mem_operands
== 0
6744 && ((i
.reg_operands
== 2
6745 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6746 || (i
.reg_operands
== 3
6747 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6748 || (i
.reg_operands
== 4 && vex_3_sources
)))
6756 /* When there are 3 operands, one of them may be immediate,
6757 which may be the first or the last operand. Otherwise,
6758 the first operand must be shift count register (cl) or it
6759 is an instruction with VexNDS. */
6760 gas_assert (i
.imm_operands
== 1
6761 || (i
.imm_operands
== 0
6762 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6763 || i
.types
[0].bitfield
.shiftcount
)));
6764 if (operand_type_check (i
.types
[0], imm
)
6765 || i
.types
[0].bitfield
.shiftcount
)
6771 /* When there are 4 operands, the first two must be 8bit
6772 immediate operands. The source operand will be the 3rd
6775 For instructions with VexNDS, if the first operand
6776 an imm8, the source operand is the 2nd one. If the last
6777 operand is imm8, the source operand is the first one. */
6778 gas_assert ((i
.imm_operands
== 2
6779 && i
.types
[0].bitfield
.imm8
6780 && i
.types
[1].bitfield
.imm8
)
6781 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6782 && i
.imm_operands
== 1
6783 && (i
.types
[0].bitfield
.imm8
6784 || i
.types
[i
.operands
- 1].bitfield
.imm8
6786 if (i
.imm_operands
== 2)
6790 if (i
.types
[0].bitfield
.imm8
)
6797 if (is_evex_encoding (&i
.tm
))
6799 /* For EVEX instructions, when there are 5 operands, the
6800 first one must be immediate operand. If the second one
6801 is immediate operand, the source operand is the 3th
6802 one. If the last one is immediate operand, the source
6803 operand is the 2nd one. */
6804 gas_assert (i
.imm_operands
== 2
6805 && i
.tm
.opcode_modifier
.sae
6806 && operand_type_check (i
.types
[0], imm
));
6807 if (operand_type_check (i
.types
[1], imm
))
6809 else if (operand_type_check (i
.types
[4], imm
))
6823 /* RC/SAE operand could be between DEST and SRC. That happens
6824 when one operand is GPR and the other one is XMM/YMM/ZMM
6826 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6829 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6831 /* For instructions with VexNDS, the register-only source
6832 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6833 register. It is encoded in VEX prefix. We need to
6834 clear RegMem bit before calling operand_type_equal. */
6836 i386_operand_type op
;
6839 /* Check register-only source operand when two source
6840 operands are swapped. */
6841 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6842 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6850 op
= i
.tm
.operand_types
[vvvv
];
6851 op
.bitfield
.regmem
= 0;
6852 if ((dest
+ 1) >= i
.operands
6853 || ((!op
.bitfield
.reg
6854 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6855 && !op
.bitfield
.regsimd
6856 && !operand_type_equal (&op
, ®mask
)))
6858 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6864 /* One of the register operands will be encoded in the i.tm.reg
6865 field, the other in the combined i.tm.mode and i.tm.regmem
6866 fields. If no form of this instruction supports a memory
6867 destination operand, then we assume the source operand may
6868 sometimes be a memory operand and so we need to store the
6869 destination in the i.rm.reg field. */
6870 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6871 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6873 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6874 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6875 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6877 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6879 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6881 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6886 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6887 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6888 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6890 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6892 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6894 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6897 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6899 if (!i
.types
[0].bitfield
.control
6900 && !i
.types
[1].bitfield
.control
)
6902 i
.rex
&= ~(REX_R
| REX_B
);
6903 add_prefix (LOCK_PREFIX_OPCODE
);
6907 { /* If it's not 2 reg operands... */
6912 unsigned int fake_zero_displacement
= 0;
6915 for (op
= 0; op
< i
.operands
; op
++)
6916 if (operand_type_check (i
.types
[op
], anymem
))
6918 gas_assert (op
< i
.operands
);
6920 if (i
.tm
.opcode_modifier
.vecsib
)
6922 if (i
.index_reg
->reg_num
== RegEiz
6923 || i
.index_reg
->reg_num
== RegRiz
)
6926 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6929 i
.sib
.base
= NO_BASE_REGISTER
;
6930 i
.sib
.scale
= i
.log2_scale_factor
;
6931 i
.types
[op
].bitfield
.disp8
= 0;
6932 i
.types
[op
].bitfield
.disp16
= 0;
6933 i
.types
[op
].bitfield
.disp64
= 0;
6934 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6936 /* Must be 32 bit */
6937 i
.types
[op
].bitfield
.disp32
= 1;
6938 i
.types
[op
].bitfield
.disp32s
= 0;
6942 i
.types
[op
].bitfield
.disp32
= 0;
6943 i
.types
[op
].bitfield
.disp32s
= 1;
6946 i
.sib
.index
= i
.index_reg
->reg_num
;
6947 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6949 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6955 if (i
.base_reg
== 0)
6958 if (!i
.disp_operands
)
6959 fake_zero_displacement
= 1;
6960 if (i
.index_reg
== 0)
6962 i386_operand_type newdisp
;
6964 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6965 /* Operand is just <disp> */
6966 if (flag_code
== CODE_64BIT
)
6968 /* 64bit mode overwrites the 32bit absolute
6969 addressing by RIP relative addressing and
6970 absolute addressing is encoded by one of the
6971 redundant SIB forms. */
6972 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6973 i
.sib
.base
= NO_BASE_REGISTER
;
6974 i
.sib
.index
= NO_INDEX_REGISTER
;
6975 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6977 else if ((flag_code
== CODE_16BIT
)
6978 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6980 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6985 i
.rm
.regmem
= NO_BASE_REGISTER
;
6988 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6989 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6991 else if (!i
.tm
.opcode_modifier
.vecsib
)
6993 /* !i.base_reg && i.index_reg */
6994 if (i
.index_reg
->reg_num
== RegEiz
6995 || i
.index_reg
->reg_num
== RegRiz
)
6996 i
.sib
.index
= NO_INDEX_REGISTER
;
6998 i
.sib
.index
= i
.index_reg
->reg_num
;
6999 i
.sib
.base
= NO_BASE_REGISTER
;
7000 i
.sib
.scale
= i
.log2_scale_factor
;
7001 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7002 i
.types
[op
].bitfield
.disp8
= 0;
7003 i
.types
[op
].bitfield
.disp16
= 0;
7004 i
.types
[op
].bitfield
.disp64
= 0;
7005 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7007 /* Must be 32 bit */
7008 i
.types
[op
].bitfield
.disp32
= 1;
7009 i
.types
[op
].bitfield
.disp32s
= 0;
7013 i
.types
[op
].bitfield
.disp32
= 0;
7014 i
.types
[op
].bitfield
.disp32s
= 1;
7016 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7020 /* RIP addressing for 64bit mode. */
7021 else if (i
.base_reg
->reg_num
== RegRip
||
7022 i
.base_reg
->reg_num
== RegEip
)
7024 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7025 i
.rm
.regmem
= NO_BASE_REGISTER
;
7026 i
.types
[op
].bitfield
.disp8
= 0;
7027 i
.types
[op
].bitfield
.disp16
= 0;
7028 i
.types
[op
].bitfield
.disp32
= 0;
7029 i
.types
[op
].bitfield
.disp32s
= 1;
7030 i
.types
[op
].bitfield
.disp64
= 0;
7031 i
.flags
[op
] |= Operand_PCrel
;
7032 if (! i
.disp_operands
)
7033 fake_zero_displacement
= 1;
7035 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7037 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7038 switch (i
.base_reg
->reg_num
)
7041 if (i
.index_reg
== 0)
7043 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7044 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7048 if (i
.index_reg
== 0)
7051 if (operand_type_check (i
.types
[op
], disp
) == 0)
7053 /* fake (%bp) into 0(%bp) */
7054 i
.types
[op
].bitfield
.disp8
= 1;
7055 fake_zero_displacement
= 1;
7058 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7059 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7061 default: /* (%si) -> 4 or (%di) -> 5 */
7062 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7064 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7066 else /* i.base_reg and 32/64 bit mode */
7068 if (flag_code
== CODE_64BIT
7069 && operand_type_check (i
.types
[op
], disp
))
7071 i
.types
[op
].bitfield
.disp16
= 0;
7072 i
.types
[op
].bitfield
.disp64
= 0;
7073 if (i
.prefix
[ADDR_PREFIX
] == 0)
7075 i
.types
[op
].bitfield
.disp32
= 0;
7076 i
.types
[op
].bitfield
.disp32s
= 1;
7080 i
.types
[op
].bitfield
.disp32
= 1;
7081 i
.types
[op
].bitfield
.disp32s
= 0;
7085 if (!i
.tm
.opcode_modifier
.vecsib
)
7086 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7087 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7089 i
.sib
.base
= i
.base_reg
->reg_num
;
7090 /* x86-64 ignores REX prefix bit here to avoid decoder
7092 if (!(i
.base_reg
->reg_flags
& RegRex
)
7093 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7094 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7096 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7098 fake_zero_displacement
= 1;
7099 i
.types
[op
].bitfield
.disp8
= 1;
7101 i
.sib
.scale
= i
.log2_scale_factor
;
7102 if (i
.index_reg
== 0)
7104 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7105 /* <disp>(%esp) becomes two byte modrm with no index
7106 register. We've already stored the code for esp
7107 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7108 Any base register besides %esp will not use the
7109 extra modrm byte. */
7110 i
.sib
.index
= NO_INDEX_REGISTER
;
7112 else if (!i
.tm
.opcode_modifier
.vecsib
)
7114 if (i
.index_reg
->reg_num
== RegEiz
7115 || i
.index_reg
->reg_num
== RegRiz
)
7116 i
.sib
.index
= NO_INDEX_REGISTER
;
7118 i
.sib
.index
= i
.index_reg
->reg_num
;
7119 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7120 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7125 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7126 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7130 if (!fake_zero_displacement
7134 fake_zero_displacement
= 1;
7135 if (i
.disp_encoding
== disp_encoding_8bit
)
7136 i
.types
[op
].bitfield
.disp8
= 1;
7138 i
.types
[op
].bitfield
.disp32
= 1;
7140 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7144 if (fake_zero_displacement
)
7146 /* Fakes a zero displacement assuming that i.types[op]
7147 holds the correct displacement size. */
7150 gas_assert (i
.op
[op
].disps
== 0);
7151 exp
= &disp_expressions
[i
.disp_operands
++];
7152 i
.op
[op
].disps
= exp
;
7153 exp
->X_op
= O_constant
;
7154 exp
->X_add_number
= 0;
7155 exp
->X_add_symbol
= (symbolS
*) 0;
7156 exp
->X_op_symbol
= (symbolS
*) 0;
7164 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7166 if (operand_type_check (i
.types
[0], imm
))
7167 i
.vex
.register_specifier
= NULL
;
7170 /* VEX.vvvv encodes one of the sources when the first
7171 operand is not an immediate. */
7172 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7173 i
.vex
.register_specifier
= i
.op
[0].regs
;
7175 i
.vex
.register_specifier
= i
.op
[1].regs
;
7178 /* Destination is a XMM register encoded in the ModRM.reg
7180 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7181 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7184 /* ModRM.rm and VEX.B encodes the other source. */
7185 if (!i
.mem_operands
)
7189 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7190 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7192 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7194 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7198 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7200 i
.vex
.register_specifier
= i
.op
[2].regs
;
7201 if (!i
.mem_operands
)
7204 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7205 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7209 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7210 (if any) based on i.tm.extension_opcode. Again, we must be
7211 careful to make sure that segment/control/debug/test/MMX
7212 registers are coded into the i.rm.reg field. */
7213 else if (i
.reg_operands
)
7216 unsigned int vex_reg
= ~0;
7218 for (op
= 0; op
< i
.operands
; op
++)
7219 if (i
.types
[op
].bitfield
.reg
7220 || i
.types
[op
].bitfield
.regmmx
7221 || i
.types
[op
].bitfield
.regsimd
7222 || i
.types
[op
].bitfield
.regbnd
7223 || i
.types
[op
].bitfield
.regmask
7224 || i
.types
[op
].bitfield
.sreg2
7225 || i
.types
[op
].bitfield
.sreg3
7226 || i
.types
[op
].bitfield
.control
7227 || i
.types
[op
].bitfield
.debug
7228 || i
.types
[op
].bitfield
.test
)
7233 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7235 /* For instructions with VexNDS, the register-only
7236 source operand is encoded in VEX prefix. */
7237 gas_assert (mem
!= (unsigned int) ~0);
7242 gas_assert (op
< i
.operands
);
7246 /* Check register-only source operand when two source
7247 operands are swapped. */
7248 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7249 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7253 gas_assert (mem
== (vex_reg
+ 1)
7254 && op
< i
.operands
);
7259 gas_assert (vex_reg
< i
.operands
);
7263 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7265 /* For instructions with VexNDD, the register destination
7266 is encoded in VEX prefix. */
7267 if (i
.mem_operands
== 0)
7269 /* There is no memory operand. */
7270 gas_assert ((op
+ 2) == i
.operands
);
7275 /* There are only 2 non-immediate operands. */
7276 gas_assert (op
< i
.imm_operands
+ 2
7277 && i
.operands
== i
.imm_operands
+ 2);
7278 vex_reg
= i
.imm_operands
+ 1;
7282 gas_assert (op
< i
.operands
);
7284 if (vex_reg
!= (unsigned int) ~0)
7286 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7288 if ((!type
->bitfield
.reg
7289 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7290 && !type
->bitfield
.regsimd
7291 && !operand_type_equal (type
, ®mask
))
7294 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7297 /* Don't set OP operand twice. */
7300 /* If there is an extension opcode to put here, the
7301 register number must be put into the regmem field. */
7302 if (i
.tm
.extension_opcode
!= None
)
7304 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7305 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7307 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7312 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7313 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7315 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7320 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7321 must set it to 3 to indicate this is a register operand
7322 in the regmem field. */
7323 if (!i
.mem_operands
)
7327 /* Fill in i.rm.reg field with extension opcode (if any). */
7328 if (i
.tm
.extension_opcode
!= None
)
7329 i
.rm
.reg
= i
.tm
.extension_opcode
;
7335 output_branch (void)
7341 relax_substateT subtype
;
7345 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7346 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7349 if (i
.prefix
[DATA_PREFIX
] != 0)
7355 /* Pentium4 branch hints. */
7356 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7357 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7362 if (i
.prefix
[REX_PREFIX
] != 0)
7368 /* BND prefixed jump. */
7369 if (i
.prefix
[BND_PREFIX
] != 0)
7371 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7375 if (i
.prefixes
!= 0 && !intel_syntax
)
7376 as_warn (_("skipping prefixes on this instruction"));
7378 /* It's always a symbol; End frag & setup for relax.
7379 Make sure there is enough room in this frag for the largest
7380 instruction we may generate in md_convert_frag. This is 2
7381 bytes for the opcode and room for the prefix and largest
7383 frag_grow (prefix
+ 2 + 4);
7384 /* Prefix and 1 opcode byte go in fr_fix. */
7385 p
= frag_more (prefix
+ 1);
7386 if (i
.prefix
[DATA_PREFIX
] != 0)
7387 *p
++ = DATA_PREFIX_OPCODE
;
7388 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7389 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7390 *p
++ = i
.prefix
[SEG_PREFIX
];
7391 if (i
.prefix
[REX_PREFIX
] != 0)
7392 *p
++ = i
.prefix
[REX_PREFIX
];
7393 *p
= i
.tm
.base_opcode
;
7395 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7396 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7397 else if (cpu_arch_flags
.bitfield
.cpui386
)
7398 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7400 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7403 sym
= i
.op
[0].disps
->X_add_symbol
;
7404 off
= i
.op
[0].disps
->X_add_number
;
7406 if (i
.op
[0].disps
->X_op
!= O_constant
7407 && i
.op
[0].disps
->X_op
!= O_symbol
)
7409 /* Handle complex expressions. */
7410 sym
= make_expr_symbol (i
.op
[0].disps
);
7414 /* 1 possible extra opcode + 4 byte displacement go in var part.
7415 Pass reloc in fr_var. */
7416 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7420 /* Return TRUE iff PLT32 relocation should be used for branching to
7424 need_plt32_p (symbolS
*s
)
7426 /* PLT32 relocation is ELF only. */
7430 /* Since there is no need to prepare for PLT branch on x86-64, we
7431 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7432 be used as a marker for 32-bit PC-relative branches. */
7436 /* Weak or undefined symbol need PLT32 relocation. */
7437 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7440 /* Non-global symbol doesn't need PLT32 relocation. */
7441 if (! S_IS_EXTERNAL (s
))
7444 /* Other global symbols need PLT32 relocation. NB: Symbol with
7445 non-default visibilities are treated as normal global symbol
7446 so that PLT32 relocation can be used as a marker for 32-bit
7447 PC-relative branches. It is useful for linker relaxation. */
7458 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7460 if (i
.tm
.opcode_modifier
.jumpbyte
)
7462 /* This is a loop or jecxz type instruction. */
7464 if (i
.prefix
[ADDR_PREFIX
] != 0)
7466 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7469 /* Pentium4 branch hints. */
7470 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7471 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7473 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7482 if (flag_code
== CODE_16BIT
)
7485 if (i
.prefix
[DATA_PREFIX
] != 0)
7487 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7497 if (i
.prefix
[REX_PREFIX
] != 0)
7499 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7503 /* BND prefixed jump. */
7504 if (i
.prefix
[BND_PREFIX
] != 0)
7506 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7510 if (i
.prefixes
!= 0 && !intel_syntax
)
7511 as_warn (_("skipping prefixes on this instruction"));
7513 p
= frag_more (i
.tm
.opcode_length
+ size
);
7514 switch (i
.tm
.opcode_length
)
7517 *p
++ = i
.tm
.base_opcode
>> 8;
7520 *p
++ = i
.tm
.base_opcode
;
7526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7528 && jump_reloc
== NO_RELOC
7529 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7530 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7533 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7535 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7536 i
.op
[0].disps
, 1, jump_reloc
);
7538 /* All jumps handled here are signed, but don't use a signed limit
7539 check for 32 and 16 bit jumps as we want to allow wrap around at
7540 4G and 64k respectively. */
7542 fixP
->fx_signed
= 1;
7546 output_interseg_jump (void)
7554 if (flag_code
== CODE_16BIT
)
7558 if (i
.prefix
[DATA_PREFIX
] != 0)
7564 if (i
.prefix
[REX_PREFIX
] != 0)
7574 if (i
.prefixes
!= 0 && !intel_syntax
)
7575 as_warn (_("skipping prefixes on this instruction"));
7577 /* 1 opcode; 2 segment; offset */
7578 p
= frag_more (prefix
+ 1 + 2 + size
);
7580 if (i
.prefix
[DATA_PREFIX
] != 0)
7581 *p
++ = DATA_PREFIX_OPCODE
;
7583 if (i
.prefix
[REX_PREFIX
] != 0)
7584 *p
++ = i
.prefix
[REX_PREFIX
];
7586 *p
++ = i
.tm
.base_opcode
;
7587 if (i
.op
[1].imms
->X_op
== O_constant
)
7589 offsetT n
= i
.op
[1].imms
->X_add_number
;
7592 && !fits_in_unsigned_word (n
)
7593 && !fits_in_signed_word (n
))
7595 as_bad (_("16-bit jump out of range"));
7598 md_number_to_chars (p
, n
, size
);
7601 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7602 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7603 if (i
.op
[0].imms
->X_op
!= O_constant
)
7604 as_bad (_("can't handle non absolute segment in `%s'"),
7606 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7612 fragS
*insn_start_frag
;
7613 offsetT insn_start_off
;
7615 /* Tie dwarf2 debug info to the address at the start of the insn.
7616 We can't do this after the insn has been output as the current
7617 frag may have been closed off. eg. by frag_var. */
7618 dwarf2_emit_insn (0);
7620 insn_start_frag
= frag_now
;
7621 insn_start_off
= frag_now_fix ();
7624 if (i
.tm
.opcode_modifier
.jump
)
7626 else if (i
.tm
.opcode_modifier
.jumpbyte
7627 || i
.tm
.opcode_modifier
.jumpdword
)
7629 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7630 output_interseg_jump ();
7633 /* Output normal instructions here. */
7637 unsigned int prefix
;
7640 && i
.tm
.base_opcode
== 0xfae
7642 && i
.imm_operands
== 1
7643 && (i
.op
[0].imms
->X_add_number
== 0xe8
7644 || i
.op
[0].imms
->X_add_number
== 0xf0
7645 || i
.op
[0].imms
->X_add_number
== 0xf8))
7647 /* Encode lfence, mfence, and sfence as
7648 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7649 offsetT val
= 0x240483f0ULL
;
7651 md_number_to_chars (p
, val
, 5);
7655 /* Some processors fail on LOCK prefix. This options makes
7656 assembler ignore LOCK prefix and serves as a workaround. */
7657 if (omit_lock_prefix
)
7659 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7661 i
.prefix
[LOCK_PREFIX
] = 0;
7664 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7665 don't need the explicit prefix. */
7666 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7668 switch (i
.tm
.opcode_length
)
7671 if (i
.tm
.base_opcode
& 0xff000000)
7673 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7678 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7680 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7681 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7684 if (prefix
!= REPE_PREFIX_OPCODE
7685 || (i
.prefix
[REP_PREFIX
]
7686 != REPE_PREFIX_OPCODE
))
7687 add_prefix (prefix
);
7690 add_prefix (prefix
);
7696 /* Check for pseudo prefixes. */
7697 as_bad_where (insn_start_frag
->fr_file
,
7698 insn_start_frag
->fr_line
,
7699 _("pseudo prefix without instruction"));
7705 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7706 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7707 R_X86_64_GOTTPOFF relocation so that linker can safely
7708 perform IE->LE optimization. */
7709 if (x86_elf_abi
== X86_64_X32_ABI
7711 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7712 && i
.prefix
[REX_PREFIX
] == 0)
7713 add_prefix (REX_OPCODE
);
7716 /* The prefix bytes. */
7717 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7719 FRAG_APPEND_1_CHAR (*q
);
7723 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7728 /* REX byte is encoded in VEX prefix. */
7732 FRAG_APPEND_1_CHAR (*q
);
7735 /* There should be no other prefixes for instructions
7740 /* For EVEX instructions i.vrex should become 0 after
7741 build_evex_prefix. For VEX instructions upper 16 registers
7742 aren't available, so VREX should be 0. */
7745 /* Now the VEX prefix. */
7746 p
= frag_more (i
.vex
.length
);
7747 for (j
= 0; j
< i
.vex
.length
; j
++)
7748 p
[j
] = i
.vex
.bytes
[j
];
7751 /* Now the opcode; be careful about word order here! */
7752 if (i
.tm
.opcode_length
== 1)
7754 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7758 switch (i
.tm
.opcode_length
)
7762 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7763 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7767 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7777 /* Put out high byte first: can't use md_number_to_chars! */
7778 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7779 *p
= i
.tm
.base_opcode
& 0xff;
7782 /* Now the modrm byte and sib byte (if present). */
7783 if (i
.tm
.opcode_modifier
.modrm
)
7785 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7788 /* If i.rm.regmem == ESP (4)
7789 && i.rm.mode != (Register mode)
7791 ==> need second modrm byte. */
7792 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7794 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7795 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7797 | i
.sib
.scale
<< 6));
7800 if (i
.disp_operands
)
7801 output_disp (insn_start_frag
, insn_start_off
);
7804 output_imm (insn_start_frag
, insn_start_off
);
7810 pi ("" /*line*/, &i
);
7812 #endif /* DEBUG386 */
7815 /* Return the size of the displacement operand N. */
7818 disp_size (unsigned int n
)
7822 if (i
.types
[n
].bitfield
.disp64
)
7824 else if (i
.types
[n
].bitfield
.disp8
)
7826 else if (i
.types
[n
].bitfield
.disp16
)
7831 /* Return the size of the immediate operand N. */
7834 imm_size (unsigned int n
)
7837 if (i
.types
[n
].bitfield
.imm64
)
7839 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7841 else if (i
.types
[n
].bitfield
.imm16
)
7847 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7852 for (n
= 0; n
< i
.operands
; n
++)
7854 if (operand_type_check (i
.types
[n
], disp
))
7856 if (i
.op
[n
].disps
->X_op
== O_constant
)
7858 int size
= disp_size (n
);
7859 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7861 val
= offset_in_range (val
>> i
.memshift
, size
);
7862 p
= frag_more (size
);
7863 md_number_to_chars (p
, val
, size
);
7867 enum bfd_reloc_code_real reloc_type
;
7868 int size
= disp_size (n
);
7869 int sign
= i
.types
[n
].bitfield
.disp32s
;
7870 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7873 /* We can't have 8 bit displacement here. */
7874 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7876 /* The PC relative address is computed relative
7877 to the instruction boundary, so in case immediate
7878 fields follows, we need to adjust the value. */
7879 if (pcrel
&& i
.imm_operands
)
7884 for (n1
= 0; n1
< i
.operands
; n1
++)
7885 if (operand_type_check (i
.types
[n1
], imm
))
7887 /* Only one immediate is allowed for PC
7888 relative address. */
7889 gas_assert (sz
== 0);
7891 i
.op
[n
].disps
->X_add_number
-= sz
;
7893 /* We should find the immediate. */
7894 gas_assert (sz
!= 0);
7897 p
= frag_more (size
);
7898 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7900 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7901 && (((reloc_type
== BFD_RELOC_32
7902 || reloc_type
== BFD_RELOC_X86_64_32S
7903 || (reloc_type
== BFD_RELOC_64
7905 && (i
.op
[n
].disps
->X_op
== O_symbol
7906 || (i
.op
[n
].disps
->X_op
== O_add
7907 && ((symbol_get_value_expression
7908 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7910 || reloc_type
== BFD_RELOC_32_PCREL
))
7914 if (insn_start_frag
== frag_now
)
7915 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7920 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7921 for (fr
= insn_start_frag
->fr_next
;
7922 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7924 add
+= p
- frag_now
->fr_literal
;
7929 reloc_type
= BFD_RELOC_386_GOTPC
;
7930 i
.op
[n
].imms
->X_add_number
+= add
;
7932 else if (reloc_type
== BFD_RELOC_64
)
7933 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7935 /* Don't do the adjustment for x86-64, as there
7936 the pcrel addressing is relative to the _next_
7937 insn, and that is taken care of in other code. */
7938 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7940 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7941 size
, i
.op
[n
].disps
, pcrel
,
7943 /* Check for "call/jmp *mem", "mov mem, %reg",
7944 "test %reg, mem" and "binop mem, %reg" where binop
7945 is one of adc, add, and, cmp, or, sbb, sub, xor
7946 instructions. Always generate R_386_GOT32X for
7947 "sym*GOT" operand in 32-bit mode. */
7948 if ((generate_relax_relocations
7951 && i
.rm
.regmem
== 5))
7953 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7954 && ((i
.operands
== 1
7955 && i
.tm
.base_opcode
== 0xff
7956 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7958 && (i
.tm
.base_opcode
== 0x8b
7959 || i
.tm
.base_opcode
== 0x85
7960 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7964 fixP
->fx_tcbit
= i
.rex
!= 0;
7966 && (i
.base_reg
->reg_num
== RegRip
7967 || i
.base_reg
->reg_num
== RegEip
))
7968 fixP
->fx_tcbit2
= 1;
7971 fixP
->fx_tcbit2
= 1;
7979 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7984 for (n
= 0; n
< i
.operands
; n
++)
7986 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7987 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7990 if (operand_type_check (i
.types
[n
], imm
))
7992 if (i
.op
[n
].imms
->X_op
== O_constant
)
7994 int size
= imm_size (n
);
7997 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7999 p
= frag_more (size
);
8000 md_number_to_chars (p
, val
, size
);
8004 /* Not absolute_section.
8005 Need a 32-bit fixup (don't support 8bit
8006 non-absolute imms). Try to support other
8008 enum bfd_reloc_code_real reloc_type
;
8009 int size
= imm_size (n
);
8012 if (i
.types
[n
].bitfield
.imm32s
8013 && (i
.suffix
== QWORD_MNEM_SUFFIX
8014 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8019 p
= frag_more (size
);
8020 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8022 /* This is tough to explain. We end up with this one if we
8023 * have operands that look like
8024 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8025 * obtain the absolute address of the GOT, and it is strongly
8026 * preferable from a performance point of view to avoid using
8027 * a runtime relocation for this. The actual sequence of
8028 * instructions often look something like:
8033 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8035 * The call and pop essentially return the absolute address
8036 * of the label .L66 and store it in %ebx. The linker itself
8037 * will ultimately change the first operand of the addl so
8038 * that %ebx points to the GOT, but to keep things simple, the
8039 * .o file must have this operand set so that it generates not
8040 * the absolute address of .L66, but the absolute address of
8041 * itself. This allows the linker itself simply treat a GOTPC
8042 * relocation as asking for a pcrel offset to the GOT to be
8043 * added in, and the addend of the relocation is stored in the
8044 * operand field for the instruction itself.
8046 * Our job here is to fix the operand so that it would add
8047 * the correct offset so that %ebx would point to itself. The
8048 * thing that is tricky is that .-.L66 will point to the
8049 * beginning of the instruction, so we need to further modify
8050 * the operand so that it will point to itself. There are
8051 * other cases where you have something like:
8053 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8055 * and here no correction would be required. Internally in
8056 * the assembler we treat operands of this form as not being
8057 * pcrel since the '.' is explicitly mentioned, and I wonder
8058 * whether it would simplify matters to do it this way. Who
8059 * knows. In earlier versions of the PIC patches, the
8060 * pcrel_adjust field was used to store the correction, but
8061 * since the expression is not pcrel, I felt it would be
8062 * confusing to do it this way. */
8064 if ((reloc_type
== BFD_RELOC_32
8065 || reloc_type
== BFD_RELOC_X86_64_32S
8066 || reloc_type
== BFD_RELOC_64
)
8068 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8069 && (i
.op
[n
].imms
->X_op
== O_symbol
8070 || (i
.op
[n
].imms
->X_op
== O_add
8071 && ((symbol_get_value_expression
8072 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8077 if (insn_start_frag
== frag_now
)
8078 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8083 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8084 for (fr
= insn_start_frag
->fr_next
;
8085 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8087 add
+= p
- frag_now
->fr_literal
;
8091 reloc_type
= BFD_RELOC_386_GOTPC
;
8093 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8095 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8096 i
.op
[n
].imms
->X_add_number
+= add
;
8098 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8099 i
.op
[n
].imms
, 0, reloc_type
);
8105 /* x86_cons_fix_new is called via the expression parsing code when a
8106 reloc is needed. We use this hook to get the correct .got reloc. */
8107 static int cons_sign
= -1;
8110 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8111 expressionS
*exp
, bfd_reloc_code_real_type r
)
8113 r
= reloc (len
, 0, cons_sign
, r
);
8116 if (exp
->X_op
== O_secrel
)
8118 exp
->X_op
= O_symbol
;
8119 r
= BFD_RELOC_32_SECREL
;
8123 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8126 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8127 purpose of the `.dc.a' internal pseudo-op. */
8130 x86_address_bytes (void)
8132 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8134 return stdoutput
->arch_info
->bits_per_address
/ 8;
8137 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8139 # define lex_got(reloc, adjust, types) NULL
8141 /* Parse operands of the form
8142 <symbol>@GOTOFF+<nnn>
8143 and similar .plt or .got references.
8145 If we find one, set up the correct relocation in RELOC and copy the
8146 input string, minus the `@GOTOFF' into a malloc'd buffer for
8147 parsing by the calling routine. Return this buffer, and if ADJUST
8148 is non-null set it to the length of the string we removed from the
8149 input line. Otherwise return NULL. */
8151 lex_got (enum bfd_reloc_code_real
*rel
,
8153 i386_operand_type
*types
)
8155 /* Some of the relocations depend on the size of what field is to
8156 be relocated. But in our callers i386_immediate and i386_displacement
8157 we don't yet know the operand size (this will be set by insn
8158 matching). Hence we record the word32 relocation here,
8159 and adjust the reloc according to the real size in reloc(). */
8160 static const struct {
8163 const enum bfd_reloc_code_real rel
[2];
8164 const i386_operand_type types64
;
8166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8167 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8169 OPERAND_TYPE_IMM32_64
},
8171 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8172 BFD_RELOC_X86_64_PLTOFF64
},
8173 OPERAND_TYPE_IMM64
},
8174 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8175 BFD_RELOC_X86_64_PLT32
},
8176 OPERAND_TYPE_IMM32_32S_DISP32
},
8177 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8178 BFD_RELOC_X86_64_GOTPLT64
},
8179 OPERAND_TYPE_IMM64_DISP64
},
8180 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8181 BFD_RELOC_X86_64_GOTOFF64
},
8182 OPERAND_TYPE_IMM64_DISP64
},
8183 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8184 BFD_RELOC_X86_64_GOTPCREL
},
8185 OPERAND_TYPE_IMM32_32S_DISP32
},
8186 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8187 BFD_RELOC_X86_64_TLSGD
},
8188 OPERAND_TYPE_IMM32_32S_DISP32
},
8189 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8190 _dummy_first_bfd_reloc_code_real
},
8191 OPERAND_TYPE_NONE
},
8192 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8193 BFD_RELOC_X86_64_TLSLD
},
8194 OPERAND_TYPE_IMM32_32S_DISP32
},
8195 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8196 BFD_RELOC_X86_64_GOTTPOFF
},
8197 OPERAND_TYPE_IMM32_32S_DISP32
},
8198 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8199 BFD_RELOC_X86_64_TPOFF32
},
8200 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8201 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8202 _dummy_first_bfd_reloc_code_real
},
8203 OPERAND_TYPE_NONE
},
8204 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8205 BFD_RELOC_X86_64_DTPOFF32
},
8206 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8207 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8208 _dummy_first_bfd_reloc_code_real
},
8209 OPERAND_TYPE_NONE
},
8210 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8211 _dummy_first_bfd_reloc_code_real
},
8212 OPERAND_TYPE_NONE
},
8213 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8214 BFD_RELOC_X86_64_GOT32
},
8215 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8216 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8217 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8218 OPERAND_TYPE_IMM32_32S_DISP32
},
8219 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8220 BFD_RELOC_X86_64_TLSDESC_CALL
},
8221 OPERAND_TYPE_IMM32_32S_DISP32
},
8226 #if defined (OBJ_MAYBE_ELF)
8231 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8232 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8235 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8237 int len
= gotrel
[j
].len
;
8238 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8240 if (gotrel
[j
].rel
[object_64bit
] != 0)
8243 char *tmpbuf
, *past_reloc
;
8245 *rel
= gotrel
[j
].rel
[object_64bit
];
8249 if (flag_code
!= CODE_64BIT
)
8251 types
->bitfield
.imm32
= 1;
8252 types
->bitfield
.disp32
= 1;
8255 *types
= gotrel
[j
].types64
;
8258 if (j
!= 0 && GOT_symbol
== NULL
)
8259 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8261 /* The length of the first part of our input line. */
8262 first
= cp
- input_line_pointer
;
8264 /* The second part goes from after the reloc token until
8265 (and including) an end_of_line char or comma. */
8266 past_reloc
= cp
+ 1 + len
;
8268 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8270 second
= cp
+ 1 - past_reloc
;
8272 /* Allocate and copy string. The trailing NUL shouldn't
8273 be necessary, but be safe. */
8274 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8275 memcpy (tmpbuf
, input_line_pointer
, first
);
8276 if (second
!= 0 && *past_reloc
!= ' ')
8277 /* Replace the relocation token with ' ', so that
8278 errors like foo@GOTOFF1 will be detected. */
8279 tmpbuf
[first
++] = ' ';
8281 /* Increment length by 1 if the relocation token is
8286 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8287 tmpbuf
[first
+ second
] = '\0';
8291 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8292 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8297 /* Might be a symbol version string. Don't as_bad here. */
8306 /* Parse operands of the form
8307 <symbol>@SECREL32+<nnn>
8309 If we find one, set up the correct relocation in RELOC and copy the
8310 input string, minus the `@SECREL32' into a malloc'd buffer for
8311 parsing by the calling routine. Return this buffer, and if ADJUST
8312 is non-null set it to the length of the string we removed from the
8313 input line. Otherwise return NULL.
8315 This function is copied from the ELF version above adjusted for PE targets. */
8318 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8319 int *adjust ATTRIBUTE_UNUSED
,
8320 i386_operand_type
*types
)
8326 const enum bfd_reloc_code_real rel
[2];
8327 const i386_operand_type types64
;
8331 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8332 BFD_RELOC_32_SECREL
},
8333 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8339 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8340 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8343 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8345 int len
= gotrel
[j
].len
;
8347 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8349 if (gotrel
[j
].rel
[object_64bit
] != 0)
8352 char *tmpbuf
, *past_reloc
;
8354 *rel
= gotrel
[j
].rel
[object_64bit
];
8360 if (flag_code
!= CODE_64BIT
)
8362 types
->bitfield
.imm32
= 1;
8363 types
->bitfield
.disp32
= 1;
8366 *types
= gotrel
[j
].types64
;
8369 /* The length of the first part of our input line. */
8370 first
= cp
- input_line_pointer
;
8372 /* The second part goes from after the reloc token until
8373 (and including) an end_of_line char or comma. */
8374 past_reloc
= cp
+ 1 + len
;
8376 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8378 second
= cp
+ 1 - past_reloc
;
8380 /* Allocate and copy string. The trailing NUL shouldn't
8381 be necessary, but be safe. */
8382 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8383 memcpy (tmpbuf
, input_line_pointer
, first
);
8384 if (second
!= 0 && *past_reloc
!= ' ')
8385 /* Replace the relocation token with ' ', so that
8386 errors like foo@SECLREL321 will be detected. */
8387 tmpbuf
[first
++] = ' ';
8388 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8389 tmpbuf
[first
+ second
] = '\0';
8393 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8394 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8399 /* Might be a symbol version string. Don't as_bad here. */
8405 bfd_reloc_code_real_type
8406 x86_cons (expressionS
*exp
, int size
)
8408 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8410 intel_syntax
= -intel_syntax
;
8413 if (size
== 4 || (object_64bit
&& size
== 8))
8415 /* Handle @GOTOFF and the like in an expression. */
8417 char *gotfree_input_line
;
8420 save
= input_line_pointer
;
8421 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8422 if (gotfree_input_line
)
8423 input_line_pointer
= gotfree_input_line
;
8427 if (gotfree_input_line
)
8429 /* expression () has merrily parsed up to the end of line,
8430 or a comma - in the wrong buffer. Transfer how far
8431 input_line_pointer has moved to the right buffer. */
8432 input_line_pointer
= (save
8433 + (input_line_pointer
- gotfree_input_line
)
8435 free (gotfree_input_line
);
8436 if (exp
->X_op
== O_constant
8437 || exp
->X_op
== O_absent
8438 || exp
->X_op
== O_illegal
8439 || exp
->X_op
== O_register
8440 || exp
->X_op
== O_big
)
8442 char c
= *input_line_pointer
;
8443 *input_line_pointer
= 0;
8444 as_bad (_("missing or invalid expression `%s'"), save
);
8445 *input_line_pointer
= c
;
8452 intel_syntax
= -intel_syntax
;
8455 i386_intel_simplify (exp
);
8461 signed_cons (int size
)
8463 if (flag_code
== CODE_64BIT
)
8471 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8478 if (exp
.X_op
== O_symbol
)
8479 exp
.X_op
= O_secrel
;
8481 emit_expr (&exp
, 4);
8483 while (*input_line_pointer
++ == ',');
8485 input_line_pointer
--;
8486 demand_empty_rest_of_line ();
8490 /* Handle Vector operations. */
8493 check_VecOperations (char *op_string
, char *op_end
)
8495 const reg_entry
*mask
;
8500 && (op_end
== NULL
|| op_string
< op_end
))
8503 if (*op_string
== '{')
8507 /* Check broadcasts. */
8508 if (strncmp (op_string
, "1to", 3) == 0)
8513 goto duplicated_vec_op
;
8516 if (*op_string
== '8')
8518 else if (*op_string
== '4')
8520 else if (*op_string
== '2')
8522 else if (*op_string
== '1'
8523 && *(op_string
+1) == '6')
8530 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8535 broadcast_op
.type
= bcst_type
;
8536 broadcast_op
.operand
= this_operand
;
8537 i
.broadcast
= &broadcast_op
;
8539 /* Check masking operation. */
8540 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8542 /* k0 can't be used for write mask. */
8543 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8545 as_bad (_("`%s%s' can't be used for write mask"),
8546 register_prefix
, mask
->reg_name
);
8552 mask_op
.mask
= mask
;
8553 mask_op
.zeroing
= 0;
8554 mask_op
.operand
= this_operand
;
8560 goto duplicated_vec_op
;
8562 i
.mask
->mask
= mask
;
8564 /* Only "{z}" is allowed here. No need to check
8565 zeroing mask explicitly. */
8566 if (i
.mask
->operand
!= this_operand
)
8568 as_bad (_("invalid write mask `%s'"), saved
);
8575 /* Check zeroing-flag for masking operation. */
8576 else if (*op_string
== 'z')
8580 mask_op
.mask
= NULL
;
8581 mask_op
.zeroing
= 1;
8582 mask_op
.operand
= this_operand
;
8587 if (i
.mask
->zeroing
)
8590 as_bad (_("duplicated `%s'"), saved
);
8594 i
.mask
->zeroing
= 1;
8596 /* Only "{%k}" is allowed here. No need to check mask
8597 register explicitly. */
8598 if (i
.mask
->operand
!= this_operand
)
8600 as_bad (_("invalid zeroing-masking `%s'"),
8609 goto unknown_vec_op
;
8611 if (*op_string
!= '}')
8613 as_bad (_("missing `}' in `%s'"), saved
);
8618 /* Strip whitespace since the addition of pseudo prefixes
8619 changed how the scrubber treats '{'. */
8620 if (is_space_char (*op_string
))
8626 /* We don't know this one. */
8627 as_bad (_("unknown vector operation: `%s'"), saved
);
8631 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8633 as_bad (_("zeroing-masking only allowed with write mask"));
8641 i386_immediate (char *imm_start
)
8643 char *save_input_line_pointer
;
8644 char *gotfree_input_line
;
8647 i386_operand_type types
;
8649 operand_type_set (&types
, ~0);
8651 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8653 as_bad (_("at most %d immediate operands are allowed"),
8654 MAX_IMMEDIATE_OPERANDS
);
8658 exp
= &im_expressions
[i
.imm_operands
++];
8659 i
.op
[this_operand
].imms
= exp
;
8661 if (is_space_char (*imm_start
))
8664 save_input_line_pointer
= input_line_pointer
;
8665 input_line_pointer
= imm_start
;
8667 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8668 if (gotfree_input_line
)
8669 input_line_pointer
= gotfree_input_line
;
8671 exp_seg
= expression (exp
);
8675 /* Handle vector operations. */
8676 if (*input_line_pointer
== '{')
8678 input_line_pointer
= check_VecOperations (input_line_pointer
,
8680 if (input_line_pointer
== NULL
)
8684 if (*input_line_pointer
)
8685 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8687 input_line_pointer
= save_input_line_pointer
;
8688 if (gotfree_input_line
)
8690 free (gotfree_input_line
);
8692 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8693 exp
->X_op
= O_illegal
;
8696 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8700 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8701 i386_operand_type types
, const char *imm_start
)
8703 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8706 as_bad (_("missing or invalid immediate expression `%s'"),
8710 else if (exp
->X_op
== O_constant
)
8712 /* Size it properly later. */
8713 i
.types
[this_operand
].bitfield
.imm64
= 1;
8714 /* If not 64bit, sign extend val. */
8715 if (flag_code
!= CODE_64BIT
8716 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8718 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8720 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8721 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8722 && exp_seg
!= absolute_section
8723 && exp_seg
!= text_section
8724 && exp_seg
!= data_section
8725 && exp_seg
!= bss_section
8726 && exp_seg
!= undefined_section
8727 && !bfd_is_com_section (exp_seg
))
8729 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8733 else if (!intel_syntax
&& exp_seg
== reg_section
)
8736 as_bad (_("illegal immediate register operand %s"), imm_start
);
8741 /* This is an address. The size of the address will be
8742 determined later, depending on destination register,
8743 suffix, or the default for the section. */
8744 i
.types
[this_operand
].bitfield
.imm8
= 1;
8745 i
.types
[this_operand
].bitfield
.imm16
= 1;
8746 i
.types
[this_operand
].bitfield
.imm32
= 1;
8747 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8748 i
.types
[this_operand
].bitfield
.imm64
= 1;
8749 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8757 i386_scale (char *scale
)
8760 char *save
= input_line_pointer
;
8762 input_line_pointer
= scale
;
8763 val
= get_absolute_expression ();
8768 i
.log2_scale_factor
= 0;
8771 i
.log2_scale_factor
= 1;
8774 i
.log2_scale_factor
= 2;
8777 i
.log2_scale_factor
= 3;
8781 char sep
= *input_line_pointer
;
8783 *input_line_pointer
= '\0';
8784 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8786 *input_line_pointer
= sep
;
8787 input_line_pointer
= save
;
8791 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8793 as_warn (_("scale factor of %d without an index register"),
8794 1 << i
.log2_scale_factor
);
8795 i
.log2_scale_factor
= 0;
8797 scale
= input_line_pointer
;
8798 input_line_pointer
= save
;
8803 i386_displacement (char *disp_start
, char *disp_end
)
8807 char *save_input_line_pointer
;
8808 char *gotfree_input_line
;
8810 i386_operand_type bigdisp
, types
= anydisp
;
8813 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8815 as_bad (_("at most %d displacement operands are allowed"),
8816 MAX_MEMORY_OPERANDS
);
8820 operand_type_set (&bigdisp
, 0);
8821 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8822 || (!current_templates
->start
->opcode_modifier
.jump
8823 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8825 bigdisp
.bitfield
.disp32
= 1;
8826 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8827 if (flag_code
== CODE_64BIT
)
8831 bigdisp
.bitfield
.disp32s
= 1;
8832 bigdisp
.bitfield
.disp64
= 1;
8835 else if ((flag_code
== CODE_16BIT
) ^ override
)
8837 bigdisp
.bitfield
.disp32
= 0;
8838 bigdisp
.bitfield
.disp16
= 1;
8843 /* For PC-relative branches, the width of the displacement
8844 is dependent upon data size, not address size. */
8845 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8846 if (flag_code
== CODE_64BIT
)
8848 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8849 bigdisp
.bitfield
.disp16
= 1;
8852 bigdisp
.bitfield
.disp32
= 1;
8853 bigdisp
.bitfield
.disp32s
= 1;
8859 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8861 : LONG_MNEM_SUFFIX
));
8862 bigdisp
.bitfield
.disp32
= 1;
8863 if ((flag_code
== CODE_16BIT
) ^ override
)
8865 bigdisp
.bitfield
.disp32
= 0;
8866 bigdisp
.bitfield
.disp16
= 1;
8870 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8873 exp
= &disp_expressions
[i
.disp_operands
];
8874 i
.op
[this_operand
].disps
= exp
;
8876 save_input_line_pointer
= input_line_pointer
;
8877 input_line_pointer
= disp_start
;
8878 END_STRING_AND_SAVE (disp_end
);
8880 #ifndef GCC_ASM_O_HACK
8881 #define GCC_ASM_O_HACK 0
8884 END_STRING_AND_SAVE (disp_end
+ 1);
8885 if (i
.types
[this_operand
].bitfield
.baseIndex
8886 && displacement_string_end
[-1] == '+')
8888 /* This hack is to avoid a warning when using the "o"
8889 constraint within gcc asm statements.
8892 #define _set_tssldt_desc(n,addr,limit,type) \
8893 __asm__ __volatile__ ( \
8895 "movw %w1,2+%0\n\t" \
8897 "movb %b1,4+%0\n\t" \
8898 "movb %4,5+%0\n\t" \
8899 "movb $0,6+%0\n\t" \
8900 "movb %h1,7+%0\n\t" \
8902 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8904 This works great except that the output assembler ends
8905 up looking a bit weird if it turns out that there is
8906 no offset. You end up producing code that looks like:
8919 So here we provide the missing zero. */
8921 *displacement_string_end
= '0';
8924 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8925 if (gotfree_input_line
)
8926 input_line_pointer
= gotfree_input_line
;
8928 exp_seg
= expression (exp
);
8931 if (*input_line_pointer
)
8932 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8934 RESTORE_END_STRING (disp_end
+ 1);
8936 input_line_pointer
= save_input_line_pointer
;
8937 if (gotfree_input_line
)
8939 free (gotfree_input_line
);
8941 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8942 exp
->X_op
= O_illegal
;
8945 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8947 RESTORE_END_STRING (disp_end
);
8953 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8954 i386_operand_type types
, const char *disp_start
)
8956 i386_operand_type bigdisp
;
8959 /* We do this to make sure that the section symbol is in
8960 the symbol table. We will ultimately change the relocation
8961 to be relative to the beginning of the section. */
8962 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8963 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8964 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8966 if (exp
->X_op
!= O_symbol
)
8969 if (S_IS_LOCAL (exp
->X_add_symbol
)
8970 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8971 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8972 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8973 exp
->X_op
= O_subtract
;
8974 exp
->X_op_symbol
= GOT_symbol
;
8975 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8976 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8977 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8978 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8980 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8983 else if (exp
->X_op
== O_absent
8984 || exp
->X_op
== O_illegal
8985 || exp
->X_op
== O_big
)
8988 as_bad (_("missing or invalid displacement expression `%s'"),
8993 else if (flag_code
== CODE_64BIT
8994 && !i
.prefix
[ADDR_PREFIX
]
8995 && exp
->X_op
== O_constant
)
8997 /* Since displacement is signed extended to 64bit, don't allow
8998 disp32 and turn off disp32s if they are out of range. */
8999 i
.types
[this_operand
].bitfield
.disp32
= 0;
9000 if (!fits_in_signed_long (exp
->X_add_number
))
9002 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9003 if (i
.types
[this_operand
].bitfield
.baseindex
)
9005 as_bad (_("0x%lx out range of signed 32bit displacement"),
9006 (long) exp
->X_add_number
);
9012 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9013 else if (exp
->X_op
!= O_constant
9014 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9015 && exp_seg
!= absolute_section
9016 && exp_seg
!= text_section
9017 && exp_seg
!= data_section
9018 && exp_seg
!= bss_section
9019 && exp_seg
!= undefined_section
9020 && !bfd_is_com_section (exp_seg
))
9022 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9027 /* Check if this is a displacement only operand. */
9028 bigdisp
= i
.types
[this_operand
];
9029 bigdisp
.bitfield
.disp8
= 0;
9030 bigdisp
.bitfield
.disp16
= 0;
9031 bigdisp
.bitfield
.disp32
= 0;
9032 bigdisp
.bitfield
.disp32s
= 0;
9033 bigdisp
.bitfield
.disp64
= 0;
9034 if (operand_type_all_zero (&bigdisp
))
9035 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9041 /* Return the active addressing mode, taking address override and
9042 registers forming the address into consideration. Update the
9043 address override prefix if necessary. */
9045 static enum flag_code
9046 i386_addressing_mode (void)
9048 enum flag_code addr_mode
;
9050 if (i
.prefix
[ADDR_PREFIX
])
9051 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9054 addr_mode
= flag_code
;
9056 #if INFER_ADDR_PREFIX
9057 if (i
.mem_operands
== 0)
9059 /* Infer address prefix from the first memory operand. */
9060 const reg_entry
*addr_reg
= i
.base_reg
;
9062 if (addr_reg
== NULL
)
9063 addr_reg
= i
.index_reg
;
9067 if (addr_reg
->reg_num
== RegEip
9068 || addr_reg
->reg_num
== RegEiz
9069 || addr_reg
->reg_type
.bitfield
.dword
)
9070 addr_mode
= CODE_32BIT
;
9071 else if (flag_code
!= CODE_64BIT
9072 && addr_reg
->reg_type
.bitfield
.word
)
9073 addr_mode
= CODE_16BIT
;
9075 if (addr_mode
!= flag_code
)
9077 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9079 /* Change the size of any displacement too. At most one
9080 of Disp16 or Disp32 is set.
9081 FIXME. There doesn't seem to be any real need for
9082 separate Disp16 and Disp32 flags. The same goes for
9083 Imm16 and Imm32. Removing them would probably clean
9084 up the code quite a lot. */
9085 if (flag_code
!= CODE_64BIT
9086 && (i
.types
[this_operand
].bitfield
.disp16
9087 || i
.types
[this_operand
].bitfield
.disp32
))
9088 i
.types
[this_operand
]
9089 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9099 /* Make sure the memory operand we've been dealt is valid.
9100 Return 1 on success, 0 on a failure. */
9103 i386_index_check (const char *operand_string
)
9105 const char *kind
= "base/index";
9106 enum flag_code addr_mode
= i386_addressing_mode ();
9108 if (current_templates
->start
->opcode_modifier
.isstring
9109 && !current_templates
->start
->opcode_modifier
.immext
9110 && (current_templates
->end
[-1].opcode_modifier
.isstring
9113 /* Memory operands of string insns are special in that they only allow
9114 a single register (rDI, rSI, or rBX) as their memory address. */
9115 const reg_entry
*expected_reg
;
9116 static const char *di_si
[][2] =
9122 static const char *bx
[] = { "ebx", "bx", "rbx" };
9124 kind
= "string address";
9126 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9128 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9130 if (!type
.bitfield
.baseindex
9131 || ((!i
.mem_operands
!= !intel_syntax
)
9132 && current_templates
->end
[-1].operand_types
[1]
9133 .bitfield
.baseindex
))
9134 type
= current_templates
->end
[-1].operand_types
[1];
9135 expected_reg
= hash_find (reg_hash
,
9136 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9140 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9142 if (i
.base_reg
!= expected_reg
9144 || operand_type_check (i
.types
[this_operand
], disp
))
9146 /* The second memory operand must have the same size as
9150 && !((addr_mode
== CODE_64BIT
9151 && i
.base_reg
->reg_type
.bitfield
.qword
)
9152 || (addr_mode
== CODE_32BIT
9153 ? i
.base_reg
->reg_type
.bitfield
.dword
9154 : i
.base_reg
->reg_type
.bitfield
.word
)))
9157 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9159 intel_syntax
? '[' : '(',
9161 expected_reg
->reg_name
,
9162 intel_syntax
? ']' : ')');
9169 as_bad (_("`%s' is not a valid %s expression"),
9170 operand_string
, kind
);
9175 if (addr_mode
!= CODE_16BIT
)
9177 /* 32-bit/64-bit checks. */
9179 && (addr_mode
== CODE_64BIT
9180 ? !i
.base_reg
->reg_type
.bitfield
.qword
9181 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9183 || (i
.base_reg
->reg_num
9184 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9186 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9187 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9188 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9189 && ((addr_mode
== CODE_64BIT
9190 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9191 || i
.index_reg
->reg_num
== RegRiz
)
9192 : !(i
.index_reg
->reg_type
.bitfield
.dword
9193 || i
.index_reg
->reg_num
== RegEiz
))
9194 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9197 /* bndmk, bndldx, and bndstx have special restrictions. */
9198 if (current_templates
->start
->base_opcode
== 0xf30f1b
9199 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9201 /* They cannot use RIP-relative addressing. */
9202 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9204 as_bad (_("`%s' cannot be used here"), operand_string
);
9208 /* bndldx and bndstx ignore their scale factor. */
9209 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9210 && i
.log2_scale_factor
)
9211 as_warn (_("register scaling is being ignored here"));
9216 /* 16-bit checks. */
9218 && (!i
.base_reg
->reg_type
.bitfield
.word
9219 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9221 && (!i
.index_reg
->reg_type
.bitfield
.word
9222 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9224 && i
.base_reg
->reg_num
< 6
9225 && i
.index_reg
->reg_num
>= 6
9226 && i
.log2_scale_factor
== 0))))
9233 /* Handle vector immediates. */
9236 RC_SAE_immediate (const char *imm_start
)
9238 unsigned int match_found
, j
;
9239 const char *pstr
= imm_start
;
9247 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9249 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9253 rc_op
.type
= RC_NamesTable
[j
].type
;
9254 rc_op
.operand
= this_operand
;
9255 i
.rounding
= &rc_op
;
9259 as_bad (_("duplicated `%s'"), imm_start
);
9262 pstr
+= RC_NamesTable
[j
].len
;
9272 as_bad (_("Missing '}': '%s'"), imm_start
);
9275 /* RC/SAE immediate string should contain nothing more. */;
9278 as_bad (_("Junk after '}': '%s'"), imm_start
);
9282 exp
= &im_expressions
[i
.imm_operands
++];
9283 i
.op
[this_operand
].imms
= exp
;
9285 exp
->X_op
= O_constant
;
9286 exp
->X_add_number
= 0;
9287 exp
->X_add_symbol
= (symbolS
*) 0;
9288 exp
->X_op_symbol
= (symbolS
*) 0;
9290 i
.types
[this_operand
].bitfield
.imm8
= 1;
9294 /* Only string instructions can have a second memory operand, so
9295 reduce current_templates to just those if it contains any. */
9297 maybe_adjust_templates (void)
9299 const insn_template
*t
;
9301 gas_assert (i
.mem_operands
== 1);
9303 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9304 if (t
->opcode_modifier
.isstring
)
9307 if (t
< current_templates
->end
)
9309 static templates aux_templates
;
9310 bfd_boolean recheck
;
9312 aux_templates
.start
= t
;
9313 for (; t
< current_templates
->end
; ++t
)
9314 if (!t
->opcode_modifier
.isstring
)
9316 aux_templates
.end
= t
;
9318 /* Determine whether to re-check the first memory operand. */
9319 recheck
= (aux_templates
.start
!= current_templates
->start
9320 || t
!= current_templates
->end
);
9322 current_templates
= &aux_templates
;
9327 if (i
.memop1_string
!= NULL
9328 && i386_index_check (i
.memop1_string
) == 0)
9337 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9341 i386_att_operand (char *operand_string
)
9345 char *op_string
= operand_string
;
9347 if (is_space_char (*op_string
))
9350 /* We check for an absolute prefix (differentiating,
9351 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9352 if (*op_string
== ABSOLUTE_PREFIX
)
9355 if (is_space_char (*op_string
))
9357 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9360 /* Check if operand is a register. */
9361 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9363 i386_operand_type temp
;
9365 /* Check for a segment override by searching for ':' after a
9366 segment register. */
9368 if (is_space_char (*op_string
))
9370 if (*op_string
== ':'
9371 && (r
->reg_type
.bitfield
.sreg2
9372 || r
->reg_type
.bitfield
.sreg3
))
9377 i
.seg
[i
.mem_operands
] = &es
;
9380 i
.seg
[i
.mem_operands
] = &cs
;
9383 i
.seg
[i
.mem_operands
] = &ss
;
9386 i
.seg
[i
.mem_operands
] = &ds
;
9389 i
.seg
[i
.mem_operands
] = &fs
;
9392 i
.seg
[i
.mem_operands
] = &gs
;
9396 /* Skip the ':' and whitespace. */
9398 if (is_space_char (*op_string
))
9401 if (!is_digit_char (*op_string
)
9402 && !is_identifier_char (*op_string
)
9403 && *op_string
!= '('
9404 && *op_string
!= ABSOLUTE_PREFIX
)
9406 as_bad (_("bad memory operand `%s'"), op_string
);
9409 /* Handle case of %es:*foo. */
9410 if (*op_string
== ABSOLUTE_PREFIX
)
9413 if (is_space_char (*op_string
))
9415 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9417 goto do_memory_reference
;
9420 /* Handle vector operations. */
9421 if (*op_string
== '{')
9423 op_string
= check_VecOperations (op_string
, NULL
);
9424 if (op_string
== NULL
)
9430 as_bad (_("junk `%s' after register"), op_string
);
9434 temp
.bitfield
.baseindex
= 0;
9435 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9437 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9438 i
.op
[this_operand
].regs
= r
;
9441 else if (*op_string
== REGISTER_PREFIX
)
9443 as_bad (_("bad register name `%s'"), op_string
);
9446 else if (*op_string
== IMMEDIATE_PREFIX
)
9449 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9451 as_bad (_("immediate operand illegal with absolute jump"));
9454 if (!i386_immediate (op_string
))
9457 else if (RC_SAE_immediate (operand_string
))
9459 /* If it is a RC or SAE immediate, do nothing. */
9462 else if (is_digit_char (*op_string
)
9463 || is_identifier_char (*op_string
)
9464 || *op_string
== '"'
9465 || *op_string
== '(')
9467 /* This is a memory reference of some sort. */
9470 /* Start and end of displacement string expression (if found). */
9471 char *displacement_string_start
;
9472 char *displacement_string_end
;
9475 do_memory_reference
:
9476 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9478 if ((i
.mem_operands
== 1
9479 && !current_templates
->start
->opcode_modifier
.isstring
)
9480 || i
.mem_operands
== 2)
9482 as_bad (_("too many memory references for `%s'"),
9483 current_templates
->start
->name
);
9487 /* Check for base index form. We detect the base index form by
9488 looking for an ')' at the end of the operand, searching
9489 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9491 base_string
= op_string
+ strlen (op_string
);
9493 /* Handle vector operations. */
9494 vop_start
= strchr (op_string
, '{');
9495 if (vop_start
&& vop_start
< base_string
)
9497 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9499 base_string
= vop_start
;
9503 if (is_space_char (*base_string
))
9506 /* If we only have a displacement, set-up for it to be parsed later. */
9507 displacement_string_start
= op_string
;
9508 displacement_string_end
= base_string
+ 1;
9510 if (*base_string
== ')')
9513 unsigned int parens_balanced
= 1;
9514 /* We've already checked that the number of left & right ()'s are
9515 equal, so this loop will not be infinite. */
9519 if (*base_string
== ')')
9521 if (*base_string
== '(')
9524 while (parens_balanced
);
9526 temp_string
= base_string
;
9528 /* Skip past '(' and whitespace. */
9530 if (is_space_char (*base_string
))
9533 if (*base_string
== ','
9534 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9537 displacement_string_end
= temp_string
;
9539 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9543 base_string
= end_op
;
9544 if (is_space_char (*base_string
))
9548 /* There may be an index reg or scale factor here. */
9549 if (*base_string
== ',')
9552 if (is_space_char (*base_string
))
9555 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9558 base_string
= end_op
;
9559 if (is_space_char (*base_string
))
9561 if (*base_string
== ',')
9564 if (is_space_char (*base_string
))
9567 else if (*base_string
!= ')')
9569 as_bad (_("expecting `,' or `)' "
9570 "after index register in `%s'"),
9575 else if (*base_string
== REGISTER_PREFIX
)
9577 end_op
= strchr (base_string
, ',');
9580 as_bad (_("bad register name `%s'"), base_string
);
9584 /* Check for scale factor. */
9585 if (*base_string
!= ')')
9587 char *end_scale
= i386_scale (base_string
);
9592 base_string
= end_scale
;
9593 if (is_space_char (*base_string
))
9595 if (*base_string
!= ')')
9597 as_bad (_("expecting `)' "
9598 "after scale factor in `%s'"),
9603 else if (!i
.index_reg
)
9605 as_bad (_("expecting index register or scale factor "
9606 "after `,'; got '%c'"),
9611 else if (*base_string
!= ')')
9613 as_bad (_("expecting `,' or `)' "
9614 "after base register in `%s'"),
9619 else if (*base_string
== REGISTER_PREFIX
)
9621 end_op
= strchr (base_string
, ',');
9624 as_bad (_("bad register name `%s'"), base_string
);
9629 /* If there's an expression beginning the operand, parse it,
9630 assuming displacement_string_start and
9631 displacement_string_end are meaningful. */
9632 if (displacement_string_start
!= displacement_string_end
)
9634 if (!i386_displacement (displacement_string_start
,
9635 displacement_string_end
))
9639 /* Special case for (%dx) while doing input/output op. */
9641 && operand_type_equal (&i
.base_reg
->reg_type
,
9642 ®16_inoutportreg
)
9644 && i
.log2_scale_factor
== 0
9645 && i
.seg
[i
.mem_operands
] == 0
9646 && !operand_type_check (i
.types
[this_operand
], disp
))
9648 i
.types
[this_operand
] = inoutportreg
;
9652 if (i386_index_check (operand_string
) == 0)
9654 i
.types
[this_operand
].bitfield
.mem
= 1;
9655 if (i
.mem_operands
== 0)
9656 i
.memop1_string
= xstrdup (operand_string
);
9661 /* It's not a memory operand; argh! */
9662 as_bad (_("invalid char %s beginning operand %d `%s'"),
9663 output_invalid (*op_string
),
9668 return 1; /* Normal return. */
9671 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9672 that an rs_machine_dependent frag may reach. */
9675 i386_frag_max_var (fragS
*frag
)
9677 /* The only relaxable frags are for jumps.
9678 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9679 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9680 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9683 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9685 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9687 /* STT_GNU_IFUNC symbol must go through PLT. */
9688 if ((symbol_get_bfdsym (fr_symbol
)->flags
9689 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9692 if (!S_IS_EXTERNAL (fr_symbol
))
9693 /* Symbol may be weak or local. */
9694 return !S_IS_WEAK (fr_symbol
);
9696 /* Global symbols with non-default visibility can't be preempted. */
9697 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9700 if (fr_var
!= NO_RELOC
)
9701 switch ((enum bfd_reloc_code_real
) fr_var
)
9703 case BFD_RELOC_386_PLT32
:
9704 case BFD_RELOC_X86_64_PLT32
:
9705 /* Symbol with PLT relocation may be preempted. */
9711 /* Global symbols with default visibility in a shared library may be
9712 preempted by another definition. */
9717 /* md_estimate_size_before_relax()
9719 Called just before relax() for rs_machine_dependent frags. The x86
9720 assembler uses these frags to handle variable size jump
9723 Any symbol that is now undefined will not become defined.
9724 Return the correct fr_subtype in the frag.
9725 Return the initial "guess for variable size of frag" to caller.
9726 The guess is actually the growth beyond the fixed part. Whatever
9727 we do to grow the fixed or variable part contributes to our
9731 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9733 /* We've already got fragP->fr_subtype right; all we have to do is
9734 check for un-relaxable symbols. On an ELF system, we can't relax
9735 an externally visible symbol, because it may be overridden by a
9737 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9738 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9740 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9743 #if defined (OBJ_COFF) && defined (TE_PE)
9744 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9745 && S_IS_WEAK (fragP
->fr_symbol
))
9749 /* Symbol is undefined in this segment, or we need to keep a
9750 reloc so that weak symbols can be overridden. */
9751 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9752 enum bfd_reloc_code_real reloc_type
;
9753 unsigned char *opcode
;
9756 if (fragP
->fr_var
!= NO_RELOC
)
9757 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9759 reloc_type
= BFD_RELOC_16_PCREL
;
9760 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9761 else if (need_plt32_p (fragP
->fr_symbol
))
9762 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9765 reloc_type
= BFD_RELOC_32_PCREL
;
9767 old_fr_fix
= fragP
->fr_fix
;
9768 opcode
= (unsigned char *) fragP
->fr_opcode
;
9770 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9773 /* Make jmp (0xeb) a (d)word displacement jump. */
9775 fragP
->fr_fix
+= size
;
9776 fix_new (fragP
, old_fr_fix
, size
,
9778 fragP
->fr_offset
, 1,
9784 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9786 /* Negate the condition, and branch past an
9787 unconditional jump. */
9790 /* Insert an unconditional jump. */
9792 /* We added two extra opcode bytes, and have a two byte
9794 fragP
->fr_fix
+= 2 + 2;
9795 fix_new (fragP
, old_fr_fix
+ 2, 2,
9797 fragP
->fr_offset
, 1,
9804 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9809 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9811 fragP
->fr_offset
, 1,
9813 fixP
->fx_signed
= 1;
9817 /* This changes the byte-displacement jump 0x7N
9818 to the (d)word-displacement jump 0x0f,0x8N. */
9819 opcode
[1] = opcode
[0] + 0x10;
9820 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9821 /* We've added an opcode byte. */
9822 fragP
->fr_fix
+= 1 + size
;
9823 fix_new (fragP
, old_fr_fix
+ 1, size
,
9825 fragP
->fr_offset
, 1,
9830 BAD_CASE (fragP
->fr_subtype
);
9834 return fragP
->fr_fix
- old_fr_fix
;
9837 /* Guess size depending on current relax state. Initially the relax
9838 state will correspond to a short jump and we return 1, because
9839 the variable part of the frag (the branch offset) is one byte
9840 long. However, we can relax a section more than once and in that
9841 case we must either set fr_subtype back to the unrelaxed state,
9842 or return the value for the appropriate branch. */
9843 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9846 /* Called after relax() is finished.
9848 In: Address of frag.
9849 fr_type == rs_machine_dependent.
9850 fr_subtype is what the address relaxed to.
9852 Out: Any fixSs and constants are set up.
9853 Caller will turn frag into a ".space 0". */
9856 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9859 unsigned char *opcode
;
9860 unsigned char *where_to_put_displacement
= NULL
;
9861 offsetT target_address
;
9862 offsetT opcode_address
;
9863 unsigned int extension
= 0;
9864 offsetT displacement_from_opcode_start
;
9866 opcode
= (unsigned char *) fragP
->fr_opcode
;
9868 /* Address we want to reach in file space. */
9869 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9871 /* Address opcode resides at in file space. */
9872 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9874 /* Displacement from opcode start to fill into instruction. */
9875 displacement_from_opcode_start
= target_address
- opcode_address
;
9877 if ((fragP
->fr_subtype
& BIG
) == 0)
9879 /* Don't have to change opcode. */
9880 extension
= 1; /* 1 opcode + 1 displacement */
9881 where_to_put_displacement
= &opcode
[1];
9885 if (no_cond_jump_promotion
9886 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9887 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9888 _("long jump required"));
9890 switch (fragP
->fr_subtype
)
9892 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9893 extension
= 4; /* 1 opcode + 4 displacement */
9895 where_to_put_displacement
= &opcode
[1];
9898 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9899 extension
= 2; /* 1 opcode + 2 displacement */
9901 where_to_put_displacement
= &opcode
[1];
9904 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9905 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9906 extension
= 5; /* 2 opcode + 4 displacement */
9907 opcode
[1] = opcode
[0] + 0x10;
9908 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9909 where_to_put_displacement
= &opcode
[2];
9912 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9913 extension
= 3; /* 2 opcode + 2 displacement */
9914 opcode
[1] = opcode
[0] + 0x10;
9915 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9916 where_to_put_displacement
= &opcode
[2];
9919 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9924 where_to_put_displacement
= &opcode
[3];
9928 BAD_CASE (fragP
->fr_subtype
);
9933 /* If size if less then four we are sure that the operand fits,
9934 but if it's 4, then it could be that the displacement is larger
9936 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9938 && ((addressT
) (displacement_from_opcode_start
- extension
9939 + ((addressT
) 1 << 31))
9940 > (((addressT
) 2 << 31) - 1)))
9942 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9943 _("jump target out of range"));
9944 /* Make us emit 0. */
9945 displacement_from_opcode_start
= extension
;
9947 /* Now put displacement after opcode. */
9948 md_number_to_chars ((char *) where_to_put_displacement
,
9949 (valueT
) (displacement_from_opcode_start
- extension
),
9950 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9951 fragP
->fr_fix
+= extension
;
9954 /* Apply a fixup (fixP) to segment data, once it has been determined
9955 by our caller that we have all the info we need to fix it up.
9957 Parameter valP is the pointer to the value of the bits.
9959 On the 386, immediates, displacements, and data pointers are all in
9960 the same (little-endian) format, so we don't need to care about which
9964 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9966 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9967 valueT value
= *valP
;
9969 #if !defined (TE_Mach)
9972 switch (fixP
->fx_r_type
)
9978 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9981 case BFD_RELOC_X86_64_32S
:
9982 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9985 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9988 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9993 if (fixP
->fx_addsy
!= NULL
9994 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9995 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9996 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9997 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9998 && !use_rela_relocations
)
10000 /* This is a hack. There should be a better way to handle this.
10001 This covers for the fact that bfd_install_relocation will
10002 subtract the current location (for partial_inplace, PC relative
10003 relocations); see more below. */
10007 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10010 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10012 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10015 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10017 if ((sym_seg
== seg
10018 || (symbol_section_p (fixP
->fx_addsy
)
10019 && sym_seg
!= absolute_section
))
10020 && !generic_force_reloc (fixP
))
10022 /* Yes, we add the values in twice. This is because
10023 bfd_install_relocation subtracts them out again. I think
10024 bfd_install_relocation is broken, but I don't dare change
10026 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10030 #if defined (OBJ_COFF) && defined (TE_PE)
10031 /* For some reason, the PE format does not store a
10032 section address offset for a PC relative symbol. */
10033 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10034 || S_IS_WEAK (fixP
->fx_addsy
))
10035 value
+= md_pcrel_from (fixP
);
10038 #if defined (OBJ_COFF) && defined (TE_PE)
10039 if (fixP
->fx_addsy
!= NULL
10040 && S_IS_WEAK (fixP
->fx_addsy
)
10041 /* PR 16858: Do not modify weak function references. */
10042 && ! fixP
->fx_pcrel
)
10044 #if !defined (TE_PEP)
10045 /* For x86 PE weak function symbols are neither PC-relative
10046 nor do they set S_IS_FUNCTION. So the only reliable way
10047 to detect them is to check the flags of their containing
10049 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10050 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10054 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10058 /* Fix a few things - the dynamic linker expects certain values here,
10059 and we must not disappoint it. */
10060 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10061 if (IS_ELF
&& fixP
->fx_addsy
)
10062 switch (fixP
->fx_r_type
)
10064 case BFD_RELOC_386_PLT32
:
10065 case BFD_RELOC_X86_64_PLT32
:
10066 /* Make the jump instruction point to the address of the operand. At
10067 runtime we merely add the offset to the actual PLT entry. */
10071 case BFD_RELOC_386_TLS_GD
:
10072 case BFD_RELOC_386_TLS_LDM
:
10073 case BFD_RELOC_386_TLS_IE_32
:
10074 case BFD_RELOC_386_TLS_IE
:
10075 case BFD_RELOC_386_TLS_GOTIE
:
10076 case BFD_RELOC_386_TLS_GOTDESC
:
10077 case BFD_RELOC_X86_64_TLSGD
:
10078 case BFD_RELOC_X86_64_TLSLD
:
10079 case BFD_RELOC_X86_64_GOTTPOFF
:
10080 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10081 value
= 0; /* Fully resolved at runtime. No addend. */
10083 case BFD_RELOC_386_TLS_LE
:
10084 case BFD_RELOC_386_TLS_LDO_32
:
10085 case BFD_RELOC_386_TLS_LE_32
:
10086 case BFD_RELOC_X86_64_DTPOFF32
:
10087 case BFD_RELOC_X86_64_DTPOFF64
:
10088 case BFD_RELOC_X86_64_TPOFF32
:
10089 case BFD_RELOC_X86_64_TPOFF64
:
10090 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10093 case BFD_RELOC_386_TLS_DESC_CALL
:
10094 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10095 value
= 0; /* Fully resolved at runtime. No addend. */
10096 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10100 case BFD_RELOC_VTABLE_INHERIT
:
10101 case BFD_RELOC_VTABLE_ENTRY
:
10108 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10110 #endif /* !defined (TE_Mach) */
10112 /* Are we finished with this relocation now? */
10113 if (fixP
->fx_addsy
== NULL
)
10115 #if defined (OBJ_COFF) && defined (TE_PE)
10116 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10119 /* Remember value for tc_gen_reloc. */
10120 fixP
->fx_addnumber
= value
;
10121 /* Clear out the frag for now. */
10125 else if (use_rela_relocations
)
10127 fixP
->fx_no_overflow
= 1;
10128 /* Remember value for tc_gen_reloc. */
10129 fixP
->fx_addnumber
= value
;
10133 md_number_to_chars (p
, value
, fixP
->fx_size
);
10137 md_atof (int type
, char *litP
, int *sizeP
)
10139 /* This outputs the LITTLENUMs in REVERSE order;
10140 in accord with the bigendian 386. */
10141 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10144 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10147 output_invalid (int c
)
10150 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10153 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10154 "(0x%x)", (unsigned char) c
);
10155 return output_invalid_buf
;
10158 /* REG_STRING starts *before* REGISTER_PREFIX. */
10160 static const reg_entry
*
10161 parse_real_register (char *reg_string
, char **end_op
)
10163 char *s
= reg_string
;
10165 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10166 const reg_entry
*r
;
10168 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10169 if (*s
== REGISTER_PREFIX
)
10172 if (is_space_char (*s
))
10175 p
= reg_name_given
;
10176 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10178 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10179 return (const reg_entry
*) NULL
;
10183 /* For naked regs, make sure that we are not dealing with an identifier.
10184 This prevents confusing an identifier like `eax_var' with register
10186 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10187 return (const reg_entry
*) NULL
;
10191 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10193 /* Handle floating point regs, allowing spaces in the (i) part. */
10194 if (r
== i386_regtab
/* %st is first entry of table */)
10196 if (!cpu_arch_flags
.bitfield
.cpu8087
10197 && !cpu_arch_flags
.bitfield
.cpu287
10198 && !cpu_arch_flags
.bitfield
.cpu387
)
10199 return (const reg_entry
*) NULL
;
10201 if (is_space_char (*s
))
10206 if (is_space_char (*s
))
10208 if (*s
>= '0' && *s
<= '7')
10210 int fpr
= *s
- '0';
10212 if (is_space_char (*s
))
10217 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10222 /* We have "%st(" then garbage. */
10223 return (const reg_entry
*) NULL
;
10227 if (r
== NULL
|| allow_pseudo_reg
)
10230 if (operand_type_all_zero (&r
->reg_type
))
10231 return (const reg_entry
*) NULL
;
10233 if ((r
->reg_type
.bitfield
.dword
10234 || r
->reg_type
.bitfield
.sreg3
10235 || r
->reg_type
.bitfield
.control
10236 || r
->reg_type
.bitfield
.debug
10237 || r
->reg_type
.bitfield
.test
)
10238 && !cpu_arch_flags
.bitfield
.cpui386
)
10239 return (const reg_entry
*) NULL
;
10241 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10242 return (const reg_entry
*) NULL
;
10244 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10246 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10247 return (const reg_entry
*) NULL
;
10249 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10251 if (r
->reg_type
.bitfield
.ymmword
)
10252 return (const reg_entry
*) NULL
;
10254 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10255 return (const reg_entry
*) NULL
;
10259 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10260 return (const reg_entry
*) NULL
;
10262 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10263 if (!allow_index_reg
10264 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10265 return (const reg_entry
*) NULL
;
10267 /* Upper 16 vector registers are only available with VREX in 64bit
10268 mode, and require EVEX encoding. */
10269 if (r
->reg_flags
& RegVRex
)
10271 if (!cpu_arch_flags
.bitfield
.cpuvrex
10272 || flag_code
!= CODE_64BIT
)
10273 return (const reg_entry
*) NULL
;
10275 i
.vec_encoding
= vex_encoding_evex
;
10278 if (((r
->reg_flags
& (RegRex64
| RegRex
))
10279 || r
->reg_type
.bitfield
.qword
)
10280 && (!cpu_arch_flags
.bitfield
.cpulm
10281 || !operand_type_equal (&r
->reg_type
, &control
))
10282 && flag_code
!= CODE_64BIT
)
10283 return (const reg_entry
*) NULL
;
10285 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10286 return (const reg_entry
*) NULL
;
10291 /* REG_STRING starts *before* REGISTER_PREFIX. */
10293 static const reg_entry
*
10294 parse_register (char *reg_string
, char **end_op
)
10296 const reg_entry
*r
;
10298 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10299 r
= parse_real_register (reg_string
, end_op
);
10304 char *save
= input_line_pointer
;
10308 input_line_pointer
= reg_string
;
10309 c
= get_symbol_name (®_string
);
10310 symbolP
= symbol_find (reg_string
);
10311 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10313 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10315 know (e
->X_op
== O_register
);
10316 know (e
->X_add_number
>= 0
10317 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10318 r
= i386_regtab
+ e
->X_add_number
;
10319 if ((r
->reg_flags
& RegVRex
))
10320 i
.vec_encoding
= vex_encoding_evex
;
10321 *end_op
= input_line_pointer
;
10323 *input_line_pointer
= c
;
10324 input_line_pointer
= save
;
10330 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10332 const reg_entry
*r
;
10333 char *end
= input_line_pointer
;
10336 r
= parse_register (name
, &input_line_pointer
);
10337 if (r
&& end
<= input_line_pointer
)
10339 *nextcharP
= *input_line_pointer
;
10340 *input_line_pointer
= 0;
10341 e
->X_op
= O_register
;
10342 e
->X_add_number
= r
- i386_regtab
;
10345 input_line_pointer
= end
;
10347 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10351 md_operand (expressionS
*e
)
10354 const reg_entry
*r
;
10356 switch (*input_line_pointer
)
10358 case REGISTER_PREFIX
:
10359 r
= parse_real_register (input_line_pointer
, &end
);
10362 e
->X_op
= O_register
;
10363 e
->X_add_number
= r
- i386_regtab
;
10364 input_line_pointer
= end
;
10369 gas_assert (intel_syntax
);
10370 end
= input_line_pointer
++;
10372 if (*input_line_pointer
== ']')
10374 ++input_line_pointer
;
10375 e
->X_op_symbol
= make_expr_symbol (e
);
10376 e
->X_add_symbol
= NULL
;
10377 e
->X_add_number
= 0;
10382 e
->X_op
= O_absent
;
10383 input_line_pointer
= end
;
10390 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10391 const char *md_shortopts
= "kVQ:sqnO::";
10393 const char *md_shortopts
= "qnO::";
10396 #define OPTION_32 (OPTION_MD_BASE + 0)
10397 #define OPTION_64 (OPTION_MD_BASE + 1)
10398 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10399 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10400 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10401 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10402 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10403 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10404 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10405 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10406 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10407 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10408 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10409 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10410 #define OPTION_X32 (OPTION_MD_BASE + 14)
10411 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10412 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10413 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10414 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10415 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10416 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10417 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10418 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10419 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10420 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10422 struct option md_longopts
[] =
10424 {"32", no_argument
, NULL
, OPTION_32
},
10425 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10426 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10427 {"64", no_argument
, NULL
, OPTION_64
},
10429 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10430 {"x32", no_argument
, NULL
, OPTION_X32
},
10431 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10433 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10434 {"march", required_argument
, NULL
, OPTION_MARCH
},
10435 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10436 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10437 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10438 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10439 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10440 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10441 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10442 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10443 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10444 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10445 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10446 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10447 # if defined (TE_PE) || defined (TE_PEP)
10448 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10450 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10451 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10452 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10453 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10454 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10455 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10456 {NULL
, no_argument
, NULL
, 0}
10458 size_t md_longopts_size
= sizeof (md_longopts
);
10461 md_parse_option (int c
, const char *arg
)
10464 char *arch
, *next
, *saved
;
10469 optimize_align_code
= 0;
10473 quiet_warnings
= 1;
10476 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10477 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10478 should be emitted or not. FIXME: Not implemented. */
10482 /* -V: SVR4 argument to print version ID. */
10484 print_version_id ();
10487 /* -k: Ignore for FreeBSD compatibility. */
10492 /* -s: On i386 Solaris, this tells the native assembler to use
10493 .stab instead of .stab.excl. We always use .stab anyhow. */
10496 case OPTION_MSHARED
:
10500 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10501 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10504 const char **list
, **l
;
10506 list
= bfd_target_list ();
10507 for (l
= list
; *l
!= NULL
; l
++)
10508 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10509 || strcmp (*l
, "coff-x86-64") == 0
10510 || strcmp (*l
, "pe-x86-64") == 0
10511 || strcmp (*l
, "pei-x86-64") == 0
10512 || strcmp (*l
, "mach-o-x86-64") == 0)
10514 default_arch
= "x86_64";
10518 as_fatal (_("no compiled in support for x86_64"));
10524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10528 const char **list
, **l
;
10530 list
= bfd_target_list ();
10531 for (l
= list
; *l
!= NULL
; l
++)
10532 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10534 default_arch
= "x86_64:32";
10538 as_fatal (_("no compiled in support for 32bit x86_64"));
10542 as_fatal (_("32bit x86_64 is only supported for ELF"));
10547 default_arch
= "i386";
10550 case OPTION_DIVIDE
:
10551 #ifdef SVR4_COMMENT_CHARS
10556 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10558 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10562 i386_comment_chars
= n
;
10568 saved
= xstrdup (arg
);
10570 /* Allow -march=+nosse. */
10576 as_fatal (_("invalid -march= option: `%s'"), arg
);
10577 next
= strchr (arch
, '+');
10580 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10582 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10585 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10588 cpu_arch_name
= cpu_arch
[j
].name
;
10589 cpu_sub_arch_name
= NULL
;
10590 cpu_arch_flags
= cpu_arch
[j
].flags
;
10591 cpu_arch_isa
= cpu_arch
[j
].type
;
10592 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10593 if (!cpu_arch_tune_set
)
10595 cpu_arch_tune
= cpu_arch_isa
;
10596 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10600 else if (*cpu_arch
[j
].name
== '.'
10601 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10603 /* ISA extension. */
10604 i386_cpu_flags flags
;
10606 flags
= cpu_flags_or (cpu_arch_flags
,
10607 cpu_arch
[j
].flags
);
10609 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10611 if (cpu_sub_arch_name
)
10613 char *name
= cpu_sub_arch_name
;
10614 cpu_sub_arch_name
= concat (name
,
10616 (const char *) NULL
);
10620 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10621 cpu_arch_flags
= flags
;
10622 cpu_arch_isa_flags
= flags
;
10626 = cpu_flags_or (cpu_arch_isa_flags
,
10627 cpu_arch
[j
].flags
);
10632 if (j
>= ARRAY_SIZE (cpu_arch
))
10634 /* Disable an ISA extension. */
10635 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10636 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10638 i386_cpu_flags flags
;
10640 flags
= cpu_flags_and_not (cpu_arch_flags
,
10641 cpu_noarch
[j
].flags
);
10642 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10644 if (cpu_sub_arch_name
)
10646 char *name
= cpu_sub_arch_name
;
10647 cpu_sub_arch_name
= concat (arch
,
10648 (const char *) NULL
);
10652 cpu_sub_arch_name
= xstrdup (arch
);
10653 cpu_arch_flags
= flags
;
10654 cpu_arch_isa_flags
= flags
;
10659 if (j
>= ARRAY_SIZE (cpu_noarch
))
10660 j
= ARRAY_SIZE (cpu_arch
);
10663 if (j
>= ARRAY_SIZE (cpu_arch
))
10664 as_fatal (_("invalid -march= option: `%s'"), arg
);
10668 while (next
!= NULL
);
10674 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10675 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10677 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10679 cpu_arch_tune_set
= 1;
10680 cpu_arch_tune
= cpu_arch
[j
].type
;
10681 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10685 if (j
>= ARRAY_SIZE (cpu_arch
))
10686 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10689 case OPTION_MMNEMONIC
:
10690 if (strcasecmp (arg
, "att") == 0)
10691 intel_mnemonic
= 0;
10692 else if (strcasecmp (arg
, "intel") == 0)
10693 intel_mnemonic
= 1;
10695 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10698 case OPTION_MSYNTAX
:
10699 if (strcasecmp (arg
, "att") == 0)
10701 else if (strcasecmp (arg
, "intel") == 0)
10704 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10707 case OPTION_MINDEX_REG
:
10708 allow_index_reg
= 1;
10711 case OPTION_MNAKED_REG
:
10712 allow_naked_reg
= 1;
10715 case OPTION_MSSE2AVX
:
10719 case OPTION_MSSE_CHECK
:
10720 if (strcasecmp (arg
, "error") == 0)
10721 sse_check
= check_error
;
10722 else if (strcasecmp (arg
, "warning") == 0)
10723 sse_check
= check_warning
;
10724 else if (strcasecmp (arg
, "none") == 0)
10725 sse_check
= check_none
;
10727 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10730 case OPTION_MOPERAND_CHECK
:
10731 if (strcasecmp (arg
, "error") == 0)
10732 operand_check
= check_error
;
10733 else if (strcasecmp (arg
, "warning") == 0)
10734 operand_check
= check_warning
;
10735 else if (strcasecmp (arg
, "none") == 0)
10736 operand_check
= check_none
;
10738 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10741 case OPTION_MAVXSCALAR
:
10742 if (strcasecmp (arg
, "128") == 0)
10743 avxscalar
= vex128
;
10744 else if (strcasecmp (arg
, "256") == 0)
10745 avxscalar
= vex256
;
10747 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10750 case OPTION_MADD_BND_PREFIX
:
10751 add_bnd_prefix
= 1;
10754 case OPTION_MEVEXLIG
:
10755 if (strcmp (arg
, "128") == 0)
10756 evexlig
= evexl128
;
10757 else if (strcmp (arg
, "256") == 0)
10758 evexlig
= evexl256
;
10759 else if (strcmp (arg
, "512") == 0)
10760 evexlig
= evexl512
;
10762 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10765 case OPTION_MEVEXRCIG
:
10766 if (strcmp (arg
, "rne") == 0)
10768 else if (strcmp (arg
, "rd") == 0)
10770 else if (strcmp (arg
, "ru") == 0)
10772 else if (strcmp (arg
, "rz") == 0)
10775 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10778 case OPTION_MEVEXWIG
:
10779 if (strcmp (arg
, "0") == 0)
10781 else if (strcmp (arg
, "1") == 0)
10784 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10787 # if defined (TE_PE) || defined (TE_PEP)
10788 case OPTION_MBIG_OBJ
:
10793 case OPTION_MOMIT_LOCK_PREFIX
:
10794 if (strcasecmp (arg
, "yes") == 0)
10795 omit_lock_prefix
= 1;
10796 else if (strcasecmp (arg
, "no") == 0)
10797 omit_lock_prefix
= 0;
10799 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10802 case OPTION_MFENCE_AS_LOCK_ADD
:
10803 if (strcasecmp (arg
, "yes") == 0)
10805 else if (strcasecmp (arg
, "no") == 0)
10808 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10811 case OPTION_MRELAX_RELOCATIONS
:
10812 if (strcasecmp (arg
, "yes") == 0)
10813 generate_relax_relocations
= 1;
10814 else if (strcasecmp (arg
, "no") == 0)
10815 generate_relax_relocations
= 0;
10817 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10820 case OPTION_MAMD64
:
10824 case OPTION_MINTEL64
:
10832 /* Turn off -Os. */
10833 optimize_for_space
= 0;
10835 else if (*arg
== 's')
10837 optimize_for_space
= 1;
10838 /* Turn on all encoding optimizations. */
10843 optimize
= atoi (arg
);
10844 /* Turn off -Os. */
10845 optimize_for_space
= 0;
10855 #define MESSAGE_TEMPLATE \
10859 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10860 int *left_p
, const char *name
, int len
)
10862 int size
= sizeof (MESSAGE_TEMPLATE
);
10863 int left
= *left_p
;
10865 /* Reserve 2 spaces for ", " or ",\0" */
10868 /* Check if there is any room. */
10876 p
= mempcpy (p
, name
, len
);
10880 /* Output the current message now and start a new one. */
10883 fprintf (stream
, "%s\n", message
);
10885 left
= size
- (start
- message
) - len
- 2;
10887 gas_assert (left
>= 0);
10889 p
= mempcpy (p
, name
, len
);
10897 show_arch (FILE *stream
, int ext
, int check
)
10899 static char message
[] = MESSAGE_TEMPLATE
;
10900 char *start
= message
+ 27;
10902 int size
= sizeof (MESSAGE_TEMPLATE
);
10909 left
= size
- (start
- message
);
10910 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10912 /* Should it be skipped? */
10913 if (cpu_arch
[j
].skip
)
10916 name
= cpu_arch
[j
].name
;
10917 len
= cpu_arch
[j
].len
;
10920 /* It is an extension. Skip if we aren't asked to show it. */
10931 /* It is an processor. Skip if we show only extension. */
10934 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10936 /* It is an impossible processor - skip. */
10940 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10943 /* Display disabled extensions. */
10945 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10947 name
= cpu_noarch
[j
].name
;
10948 len
= cpu_noarch
[j
].len
;
10949 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10954 fprintf (stream
, "%s\n", message
);
10958 md_show_usage (FILE *stream
)
10960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10961 fprintf (stream
, _("\
10963 -V print assembler version number\n\
10966 fprintf (stream
, _("\
10967 -n Do not optimize code alignment\n\
10968 -q quieten some warnings\n"));
10969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10970 fprintf (stream
, _("\
10973 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10974 || defined (TE_PE) || defined (TE_PEP))
10975 fprintf (stream
, _("\
10976 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10978 #ifdef SVR4_COMMENT_CHARS
10979 fprintf (stream
, _("\
10980 --divide do not treat `/' as a comment character\n"));
10982 fprintf (stream
, _("\
10983 --divide ignored\n"));
10985 fprintf (stream
, _("\
10986 -march=CPU[,+EXTENSION...]\n\
10987 generate code for CPU and EXTENSION, CPU is one of:\n"));
10988 show_arch (stream
, 0, 1);
10989 fprintf (stream
, _("\
10990 EXTENSION is combination of:\n"));
10991 show_arch (stream
, 1, 0);
10992 fprintf (stream
, _("\
10993 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10994 show_arch (stream
, 0, 0);
10995 fprintf (stream
, _("\
10996 -msse2avx encode SSE instructions with VEX prefix\n"));
10997 fprintf (stream
, _("\
10998 -msse-check=[none|error|warning]\n\
10999 check SSE instructions\n"));
11000 fprintf (stream
, _("\
11001 -moperand-check=[none|error|warning]\n\
11002 check operand combinations for validity\n"));
11003 fprintf (stream
, _("\
11004 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11006 fprintf (stream
, _("\
11007 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11009 fprintf (stream
, _("\
11010 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11011 for EVEX.W bit ignored instructions\n"));
11012 fprintf (stream
, _("\
11013 -mevexrcig=[rne|rd|ru|rz]\n\
11014 encode EVEX instructions with specific EVEX.RC value\n\
11015 for SAE-only ignored instructions\n"));
11016 fprintf (stream
, _("\
11017 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11018 fprintf (stream
, _("\
11019 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11020 fprintf (stream
, _("\
11021 -mindex-reg support pseudo index registers\n"));
11022 fprintf (stream
, _("\
11023 -mnaked-reg don't require `%%' prefix for registers\n"));
11024 fprintf (stream
, _("\
11025 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11026 fprintf (stream
, _("\
11027 -mshared disable branch optimization for shared code\n"));
11028 # if defined (TE_PE) || defined (TE_PEP)
11029 fprintf (stream
, _("\
11030 -mbig-obj generate big object files\n"));
11032 fprintf (stream
, _("\
11033 -momit-lock-prefix=[no|yes]\n\
11034 strip all lock prefixes\n"));
11035 fprintf (stream
, _("\
11036 -mfence-as-lock-add=[no|yes]\n\
11037 encode lfence, mfence and sfence as\n\
11038 lock addl $0x0, (%%{re}sp)\n"));
11039 fprintf (stream
, _("\
11040 -mrelax-relocations=[no|yes]\n\
11041 generate relax relocations\n"));
11042 fprintf (stream
, _("\
11043 -mamd64 accept only AMD64 ISA\n"));
11044 fprintf (stream
, _("\
11045 -mintel64 accept only Intel64 ISA\n"));
11048 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11049 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11050 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11052 /* Pick the target format to use. */
11055 i386_target_format (void)
11057 if (!strncmp (default_arch
, "x86_64", 6))
11059 update_code_flag (CODE_64BIT
, 1);
11060 if (default_arch
[6] == '\0')
11061 x86_elf_abi
= X86_64_ABI
;
11063 x86_elf_abi
= X86_64_X32_ABI
;
11065 else if (!strcmp (default_arch
, "i386"))
11066 update_code_flag (CODE_32BIT
, 1);
11067 else if (!strcmp (default_arch
, "iamcu"))
11069 update_code_flag (CODE_32BIT
, 1);
11070 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11072 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11073 cpu_arch_name
= "iamcu";
11074 cpu_sub_arch_name
= NULL
;
11075 cpu_arch_flags
= iamcu_flags
;
11076 cpu_arch_isa
= PROCESSOR_IAMCU
;
11077 cpu_arch_isa_flags
= iamcu_flags
;
11078 if (!cpu_arch_tune_set
)
11080 cpu_arch_tune
= cpu_arch_isa
;
11081 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11084 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11085 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11089 as_fatal (_("unknown architecture"));
11091 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11092 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11093 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11094 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11096 switch (OUTPUT_FLAVOR
)
11098 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11099 case bfd_target_aout_flavour
:
11100 return AOUT_TARGET_FORMAT
;
11102 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11103 # if defined (TE_PE) || defined (TE_PEP)
11104 case bfd_target_coff_flavour
:
11105 if (flag_code
== CODE_64BIT
)
11106 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11109 # elif defined (TE_GO32)
11110 case bfd_target_coff_flavour
:
11111 return "coff-go32";
11113 case bfd_target_coff_flavour
:
11114 return "coff-i386";
11117 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11118 case bfd_target_elf_flavour
:
11120 const char *format
;
11122 switch (x86_elf_abi
)
11125 format
= ELF_TARGET_FORMAT
;
11128 use_rela_relocations
= 1;
11130 format
= ELF_TARGET_FORMAT64
;
11132 case X86_64_X32_ABI
:
11133 use_rela_relocations
= 1;
11135 disallow_64bit_reloc
= 1;
11136 format
= ELF_TARGET_FORMAT32
;
11139 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11141 if (x86_elf_abi
!= X86_64_ABI
)
11142 as_fatal (_("Intel L1OM is 64bit only"));
11143 return ELF_TARGET_L1OM_FORMAT
;
11145 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11147 if (x86_elf_abi
!= X86_64_ABI
)
11148 as_fatal (_("Intel K1OM is 64bit only"));
11149 return ELF_TARGET_K1OM_FORMAT
;
11151 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11153 if (x86_elf_abi
!= I386_ABI
)
11154 as_fatal (_("Intel MCU is 32bit only"));
11155 return ELF_TARGET_IAMCU_FORMAT
;
11161 #if defined (OBJ_MACH_O)
11162 case bfd_target_mach_o_flavour
:
11163 if (flag_code
== CODE_64BIT
)
11165 use_rela_relocations
= 1;
11167 return "mach-o-x86-64";
11170 return "mach-o-i386";
11178 #endif /* OBJ_MAYBE_ more than one */
11181 md_undefined_symbol (char *name
)
11183 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11184 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11185 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11186 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11190 if (symbol_find (name
))
11191 as_bad (_("GOT already in symbol table"));
11192 GOT_symbol
= symbol_new (name
, undefined_section
,
11193 (valueT
) 0, &zero_address_frag
);
11200 /* Round up a section size to the appropriate boundary. */
11203 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11205 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11206 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11208 /* For a.out, force the section size to be aligned. If we don't do
11209 this, BFD will align it for us, but it will not write out the
11210 final bytes of the section. This may be a bug in BFD, but it is
11211 easier to fix it here since that is how the other a.out targets
11215 align
= bfd_get_section_alignment (stdoutput
, segment
);
11216 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11223 /* On the i386, PC-relative offsets are relative to the start of the
11224 next instruction. That is, the address of the offset, plus its
11225 size, since the offset is always the last part of the insn. */
11228 md_pcrel_from (fixS
*fixP
)
11230 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11236 s_bss (int ignore ATTRIBUTE_UNUSED
)
11240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11242 obj_elf_section_change_hook ();
11244 temp
= get_absolute_expression ();
11245 subseg_set (bss_section
, (subsegT
) temp
);
11246 demand_empty_rest_of_line ();
11252 i386_validate_fix (fixS
*fixp
)
11254 if (fixp
->fx_subsy
)
11256 if (fixp
->fx_subsy
== GOT_symbol
)
11258 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11262 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11263 if (fixp
->fx_tcbit2
)
11264 fixp
->fx_r_type
= (fixp
->fx_tcbit
11265 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11266 : BFD_RELOC_X86_64_GOTPCRELX
);
11269 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11274 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11276 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11278 fixp
->fx_subsy
= 0;
11281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11282 else if (!object_64bit
)
11284 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11285 && fixp
->fx_tcbit2
)
11286 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11292 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11295 bfd_reloc_code_real_type code
;
11297 switch (fixp
->fx_r_type
)
11299 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11300 case BFD_RELOC_SIZE32
:
11301 case BFD_RELOC_SIZE64
:
11302 if (S_IS_DEFINED (fixp
->fx_addsy
)
11303 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11305 /* Resolve size relocation against local symbol to size of
11306 the symbol plus addend. */
11307 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11308 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11309 && !fits_in_unsigned_long (value
))
11310 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11311 _("symbol size computation overflow"));
11312 fixp
->fx_addsy
= NULL
;
11313 fixp
->fx_subsy
= NULL
;
11314 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11318 /* Fall through. */
11320 case BFD_RELOC_X86_64_PLT32
:
11321 case BFD_RELOC_X86_64_GOT32
:
11322 case BFD_RELOC_X86_64_GOTPCREL
:
11323 case BFD_RELOC_X86_64_GOTPCRELX
:
11324 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11325 case BFD_RELOC_386_PLT32
:
11326 case BFD_RELOC_386_GOT32
:
11327 case BFD_RELOC_386_GOT32X
:
11328 case BFD_RELOC_386_GOTOFF
:
11329 case BFD_RELOC_386_GOTPC
:
11330 case BFD_RELOC_386_TLS_GD
:
11331 case BFD_RELOC_386_TLS_LDM
:
11332 case BFD_RELOC_386_TLS_LDO_32
:
11333 case BFD_RELOC_386_TLS_IE_32
:
11334 case BFD_RELOC_386_TLS_IE
:
11335 case BFD_RELOC_386_TLS_GOTIE
:
11336 case BFD_RELOC_386_TLS_LE_32
:
11337 case BFD_RELOC_386_TLS_LE
:
11338 case BFD_RELOC_386_TLS_GOTDESC
:
11339 case BFD_RELOC_386_TLS_DESC_CALL
:
11340 case BFD_RELOC_X86_64_TLSGD
:
11341 case BFD_RELOC_X86_64_TLSLD
:
11342 case BFD_RELOC_X86_64_DTPOFF32
:
11343 case BFD_RELOC_X86_64_DTPOFF64
:
11344 case BFD_RELOC_X86_64_GOTTPOFF
:
11345 case BFD_RELOC_X86_64_TPOFF32
:
11346 case BFD_RELOC_X86_64_TPOFF64
:
11347 case BFD_RELOC_X86_64_GOTOFF64
:
11348 case BFD_RELOC_X86_64_GOTPC32
:
11349 case BFD_RELOC_X86_64_GOT64
:
11350 case BFD_RELOC_X86_64_GOTPCREL64
:
11351 case BFD_RELOC_X86_64_GOTPC64
:
11352 case BFD_RELOC_X86_64_GOTPLT64
:
11353 case BFD_RELOC_X86_64_PLTOFF64
:
11354 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11355 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11356 case BFD_RELOC_RVA
:
11357 case BFD_RELOC_VTABLE_ENTRY
:
11358 case BFD_RELOC_VTABLE_INHERIT
:
11360 case BFD_RELOC_32_SECREL
:
11362 code
= fixp
->fx_r_type
;
11364 case BFD_RELOC_X86_64_32S
:
11365 if (!fixp
->fx_pcrel
)
11367 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11368 code
= fixp
->fx_r_type
;
11371 /* Fall through. */
11373 if (fixp
->fx_pcrel
)
11375 switch (fixp
->fx_size
)
11378 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11379 _("can not do %d byte pc-relative relocation"),
11381 code
= BFD_RELOC_32_PCREL
;
11383 case 1: code
= BFD_RELOC_8_PCREL
; break;
11384 case 2: code
= BFD_RELOC_16_PCREL
; break;
11385 case 4: code
= BFD_RELOC_32_PCREL
; break;
11387 case 8: code
= BFD_RELOC_64_PCREL
; break;
11393 switch (fixp
->fx_size
)
11396 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11397 _("can not do %d byte relocation"),
11399 code
= BFD_RELOC_32
;
11401 case 1: code
= BFD_RELOC_8
; break;
11402 case 2: code
= BFD_RELOC_16
; break;
11403 case 4: code
= BFD_RELOC_32
; break;
11405 case 8: code
= BFD_RELOC_64
; break;
11412 if ((code
== BFD_RELOC_32
11413 || code
== BFD_RELOC_32_PCREL
11414 || code
== BFD_RELOC_X86_64_32S
)
11416 && fixp
->fx_addsy
== GOT_symbol
)
11419 code
= BFD_RELOC_386_GOTPC
;
11421 code
= BFD_RELOC_X86_64_GOTPC32
;
11423 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11425 && fixp
->fx_addsy
== GOT_symbol
)
11427 code
= BFD_RELOC_X86_64_GOTPC64
;
11430 rel
= XNEW (arelent
);
11431 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11432 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11434 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11436 if (!use_rela_relocations
)
11438 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11439 vtable entry to be used in the relocation's section offset. */
11440 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11441 rel
->address
= fixp
->fx_offset
;
11442 #if defined (OBJ_COFF) && defined (TE_PE)
11443 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11444 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11449 /* Use the rela in 64bit mode. */
11452 if (disallow_64bit_reloc
)
11455 case BFD_RELOC_X86_64_DTPOFF64
:
11456 case BFD_RELOC_X86_64_TPOFF64
:
11457 case BFD_RELOC_64_PCREL
:
11458 case BFD_RELOC_X86_64_GOTOFF64
:
11459 case BFD_RELOC_X86_64_GOT64
:
11460 case BFD_RELOC_X86_64_GOTPCREL64
:
11461 case BFD_RELOC_X86_64_GOTPC64
:
11462 case BFD_RELOC_X86_64_GOTPLT64
:
11463 case BFD_RELOC_X86_64_PLTOFF64
:
11464 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11465 _("cannot represent relocation type %s in x32 mode"),
11466 bfd_get_reloc_code_name (code
));
11472 if (!fixp
->fx_pcrel
)
11473 rel
->addend
= fixp
->fx_offset
;
11477 case BFD_RELOC_X86_64_PLT32
:
11478 case BFD_RELOC_X86_64_GOT32
:
11479 case BFD_RELOC_X86_64_GOTPCREL
:
11480 case BFD_RELOC_X86_64_GOTPCRELX
:
11481 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11482 case BFD_RELOC_X86_64_TLSGD
:
11483 case BFD_RELOC_X86_64_TLSLD
:
11484 case BFD_RELOC_X86_64_GOTTPOFF
:
11485 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11486 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11487 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11490 rel
->addend
= (section
->vma
11492 + fixp
->fx_addnumber
11493 + md_pcrel_from (fixp
));
11498 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11499 if (rel
->howto
== NULL
)
11501 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11502 _("cannot represent relocation type %s"),
11503 bfd_get_reloc_code_name (code
));
11504 /* Set howto to a garbage value so that we can keep going. */
11505 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11506 gas_assert (rel
->howto
!= NULL
);
11512 #include "tc-i386-intel.c"
11515 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11517 int saved_naked_reg
;
11518 char saved_register_dot
;
11520 saved_naked_reg
= allow_naked_reg
;
11521 allow_naked_reg
= 1;
11522 saved_register_dot
= register_chars
['.'];
11523 register_chars
['.'] = '.';
11524 allow_pseudo_reg
= 1;
11525 expression_and_evaluate (exp
);
11526 allow_pseudo_reg
= 0;
11527 register_chars
['.'] = saved_register_dot
;
11528 allow_naked_reg
= saved_naked_reg
;
11530 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11532 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11534 exp
->X_op
= O_constant
;
11535 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11536 .dw2_regnum
[flag_code
>> 1];
11539 exp
->X_op
= O_illegal
;
11544 tc_x86_frame_initial_instructions (void)
11546 static unsigned int sp_regno
[2];
11548 if (!sp_regno
[flag_code
>> 1])
11550 char *saved_input
= input_line_pointer
;
11551 char sp
[][4] = {"esp", "rsp"};
11554 input_line_pointer
= sp
[flag_code
>> 1];
11555 tc_x86_parse_to_dw2regnum (&exp
);
11556 gas_assert (exp
.X_op
== O_constant
);
11557 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11558 input_line_pointer
= saved_input
;
11561 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11562 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11566 x86_dwarf2_addr_size (void)
11568 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11569 if (x86_elf_abi
== X86_64_X32_ABI
)
11572 return bfd_arch_bits_per_address (stdoutput
) / 8;
11576 i386_elf_section_type (const char *str
, size_t len
)
11578 if (flag_code
== CODE_64BIT
11579 && len
== sizeof ("unwind") - 1
11580 && strncmp (str
, "unwind", 6) == 0)
11581 return SHT_X86_64_UNWIND
;
11588 i386_solaris_fix_up_eh_frame (segT sec
)
11590 if (flag_code
== CODE_64BIT
)
11591 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11597 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11601 exp
.X_op
= O_secrel
;
11602 exp
.X_add_symbol
= symbol
;
11603 exp
.X_add_number
= 0;
11604 emit_expr (&exp
, size
);
11608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11609 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11612 x86_64_section_letter (int letter
, const char **ptr_msg
)
11614 if (flag_code
== CODE_64BIT
)
11617 return SHF_X86_64_LARGE
;
11619 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11622 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11627 x86_64_section_word (char *str
, size_t len
)
11629 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11630 return SHF_X86_64_LARGE
;
11636 handle_large_common (int small ATTRIBUTE_UNUSED
)
11638 if (flag_code
!= CODE_64BIT
)
11640 s_comm_internal (0, elf_common_parse
);
11641 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11645 static segT lbss_section
;
11646 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11647 asection
*saved_bss_section
= bss_section
;
11649 if (lbss_section
== NULL
)
11651 flagword applicable
;
11652 segT seg
= now_seg
;
11653 subsegT subseg
= now_subseg
;
11655 /* The .lbss section is for local .largecomm symbols. */
11656 lbss_section
= subseg_new (".lbss", 0);
11657 applicable
= bfd_applicable_section_flags (stdoutput
);
11658 bfd_set_section_flags (stdoutput
, lbss_section
,
11659 applicable
& SEC_ALLOC
);
11660 seg_info (lbss_section
)->bss
= 1;
11662 subseg_set (seg
, subseg
);
11665 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11666 bss_section
= lbss_section
;
11668 s_comm_internal (0, elf_common_parse
);
11670 elf_com_section_ptr
= saved_com_section_ptr
;
11671 bss_section
= saved_bss_section
;
11674 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */