1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
102 'templates' is for grouping together 'template' structures for opcodes
103 of the same name. This is only used for storing the insns in the grand
104 ole hash table of insns.
105 The templates themselves start at START and range up to (but not including)
110 const insn_template
*start
;
111 const insn_template
*end
;
115 /* 386 operand encoding bytes: see 386 book for details of this. */
118 unsigned int regmem
; /* codes register or memory operand */
119 unsigned int reg
; /* codes register operand (or extended opcode) */
120 unsigned int mode
; /* how to interpret regmem & reg */
124 /* x86-64 extension prefix. */
125 typedef int rex_byte
;
127 /* 386 opcode byte to code indirect addressing. */
136 /* x86 arch names, types and features */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 enum processor_type type
; /* arch type */
142 i386_cpu_flags flags
; /* cpu feature flags */
143 unsigned int skip
; /* show_arch should skip this. */
147 /* Used to turn off indicated flags. */
150 const char *name
; /* arch name */
151 unsigned int len
; /* arch string length */
152 i386_cpu_flags flags
; /* cpu feature flags */
156 static void update_code_flag (int, int);
157 static void set_code_flag (int);
158 static void set_16bit_gcc_code_flag (int);
159 static void set_intel_syntax (int);
160 static void set_intel_mnemonic (int);
161 static void set_allow_index_reg (int);
162 static void set_check (int);
163 static void set_cpu_arch (int);
165 static void pe_directive_secrel (int);
167 static void signed_cons (int);
168 static char *output_invalid (int c
);
169 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
171 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
173 static int i386_att_operand (char *);
174 static int i386_intel_operand (char *, int);
175 static int i386_intel_simplify (expressionS
*);
176 static int i386_intel_parse_name (const char *, expressionS
*);
177 static const reg_entry
*parse_register (char *, char **);
178 static char *parse_insn (char *, char *);
179 static char *parse_operands (char *, const char *);
180 static void swap_operands (void);
181 static void swap_2_operands (int, int);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Has MMX register operands. */
354 bfd_boolean has_regmmx
;
356 /* Has XMM register operands. */
357 bfd_boolean has_regxmm
;
359 /* Has YMM register operands. */
360 bfd_boolean has_regymm
;
362 /* Has ZMM register operands. */
363 bfd_boolean has_regzmm
;
365 /* RM and SIB are the modrm byte and the sib byte where the
366 addressing modes of this insn are encoded. */
373 /* Masking attributes. */
374 struct Mask_Operation
*mask
;
376 /* Rounding control and SAE attributes. */
377 struct RC_Operation
*rounding
;
379 /* Broadcasting attributes. */
380 struct Broadcast_Operation
*broadcast
;
382 /* Compressed disp8*N attribute. */
383 unsigned int memshift
;
385 /* Prefer load or store in encoding. */
388 dir_encoding_default
= 0,
394 /* Prefer 8bit or 32bit displacement in encoding. */
397 disp_encoding_default
= 0,
402 /* Prefer the REX byte in encoding. */
403 bfd_boolean rex_encoding
;
405 /* Disable instruction size optimization. */
406 bfd_boolean no_optimize
;
408 /* How to encode vector instructions. */
411 vex_encoding_default
= 0,
418 const char *rep_prefix
;
421 const char *hle_prefix
;
423 /* Have BND prefix. */
424 const char *bnd_prefix
;
426 /* Have NOTRACK prefix. */
427 const char *notrack_prefix
;
430 enum i386_error error
;
433 typedef struct _i386_insn i386_insn
;
435 /* Link RC type with corresponding string, that'll be looked for in
444 static const struct RC_name RC_NamesTable
[] =
446 { rne
, STRING_COMMA_LEN ("rn-sae") },
447 { rd
, STRING_COMMA_LEN ("rd-sae") },
448 { ru
, STRING_COMMA_LEN ("ru-sae") },
449 { rz
, STRING_COMMA_LEN ("rz-sae") },
450 { saeonly
, STRING_COMMA_LEN ("sae") },
453 /* List of chars besides those in app.c:symbol_chars that can start an
454 operand. Used to prevent the scrubber eating vital white-space. */
455 const char extra_symbol_chars
[] = "*%-([{}"
464 #if (defined (TE_I386AIX) \
465 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
466 && !defined (TE_GNU) \
467 && !defined (TE_LINUX) \
468 && !defined (TE_NACL) \
469 && !defined (TE_FreeBSD) \
470 && !defined (TE_DragonFly) \
471 && !defined (TE_NetBSD)))
472 /* This array holds the chars that always start a comment. If the
473 pre-processor is disabled, these aren't very useful. The option
474 --divide will remove '/' from this list. */
475 const char *i386_comment_chars
= "#/";
476 #define SVR4_COMMENT_CHARS 1
477 #define PREFIX_SEPARATOR '\\'
480 const char *i386_comment_chars
= "#";
481 #define PREFIX_SEPARATOR '/'
484 /* This array holds the chars that only start a comment at the beginning of
485 a line. If the line seems to have the form '# 123 filename'
486 .line and .file directives will appear in the pre-processed output.
487 Note that input_file.c hand checks for '#' at the beginning of the
488 first line of the input file. This is because the compiler outputs
489 #NO_APP at the beginning of its output.
490 Also note that comments started like this one will always work if
491 '/' isn't otherwise defined. */
492 const char line_comment_chars
[] = "#/";
494 const char line_separator_chars
[] = ";";
496 /* Chars that can be used to separate mant from exp in floating point
498 const char EXP_CHARS
[] = "eE";
500 /* Chars that mean this number is a floating point constant
503 const char FLT_CHARS
[] = "fFdDxX";
505 /* Tables for lexical analysis. */
506 static char mnemonic_chars
[256];
507 static char register_chars
[256];
508 static char operand_chars
[256];
509 static char identifier_chars
[256];
510 static char digit_chars
[256];
512 /* Lexical macros. */
513 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
514 #define is_operand_char(x) (operand_chars[(unsigned char) x])
515 #define is_register_char(x) (register_chars[(unsigned char) x])
516 #define is_space_char(x) ((x) == ' ')
517 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
518 #define is_digit_char(x) (digit_chars[(unsigned char) x])
520 /* All non-digit non-letter characters that may occur in an operand. */
521 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
523 /* md_assemble() always leaves the strings it's passed unaltered. To
524 effect this we maintain a stack of saved characters that we've smashed
525 with '\0's (indicating end of strings for various sub-fields of the
526 assembler instruction). */
527 static char save_stack
[32];
528 static char *save_stack_p
;
529 #define END_STRING_AND_SAVE(s) \
530 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
531 #define RESTORE_END_STRING(s) \
532 do { *(s) = *--save_stack_p; } while (0)
534 /* The instruction we're assembling. */
537 /* Possible templates for current insn. */
538 static const templates
*current_templates
;
540 /* Per instruction expressionS buffers: max displacements & immediates. */
541 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
542 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
544 /* Current operand we are working on. */
545 static int this_operand
= -1;
547 /* We support four different modes. FLAG_CODE variable is used to distinguish
555 static enum flag_code flag_code
;
556 static unsigned int object_64bit
;
557 static unsigned int disallow_64bit_reloc
;
558 static int use_rela_relocations
= 0;
560 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
561 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
562 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
564 /* The ELF ABI to use. */
572 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
575 #if defined (TE_PE) || defined (TE_PEP)
576 /* Use big object file format. */
577 static int use_big_obj
= 0;
580 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
581 /* 1 if generating code for a shared library. */
582 static int shared
= 0;
585 /* 1 for intel syntax,
587 static int intel_syntax
= 0;
589 /* 1 for Intel64 ISA,
593 /* 1 for intel mnemonic,
594 0 if att mnemonic. */
595 static int intel_mnemonic
= !SYSV386_COMPAT
;
597 /* 1 if pseudo registers are permitted. */
598 static int allow_pseudo_reg
= 0;
600 /* 1 if register prefix % not required. */
601 static int allow_naked_reg
= 0;
603 /* 1 if the assembler should add BND prefix for all control-transferring
604 instructions supporting it, even if this prefix wasn't specified
606 static int add_bnd_prefix
= 0;
608 /* 1 if pseudo index register, eiz/riz, is allowed . */
609 static int allow_index_reg
= 0;
611 /* 1 if the assembler should ignore LOCK prefix, even if it was
612 specified explicitly. */
613 static int omit_lock_prefix
= 0;
615 /* 1 if the assembler should encode lfence, mfence, and sfence as
616 "lock addl $0, (%{re}sp)". */
617 static int avoid_fence
= 0;
619 /* 1 if the assembler should generate relax relocations. */
621 static int generate_relax_relocations
622 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
624 static enum check_kind
630 sse_check
, operand_check
= check_warning
;
633 1. Clear the REX_W bit with register operand if possible.
634 2. Above plus use 128bit vector instruction to clear the full vector
637 static int optimize
= 0;
640 1. Clear the REX_W bit with register operand if possible.
641 2. Above plus use 128bit vector instruction to clear the full vector
643 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
646 static int optimize_for_space
= 0;
648 /* Register prefix used for error message. */
649 static const char *register_prefix
= "%";
651 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
652 leave, push, and pop instructions so that gcc has the same stack
653 frame as in 32 bit mode. */
654 static char stackop_size
= '\0';
656 /* Non-zero to optimize code alignment. */
657 int optimize_align_code
= 1;
659 /* Non-zero to quieten some warnings. */
660 static int quiet_warnings
= 0;
663 static const char *cpu_arch_name
= NULL
;
664 static char *cpu_sub_arch_name
= NULL
;
666 /* CPU feature flags. */
667 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
669 /* If we have selected a cpu we are generating instructions for. */
670 static int cpu_arch_tune_set
= 0;
672 /* Cpu we are generating instructions for. */
673 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
675 /* CPU feature flags of cpu we are generating instructions for. */
676 static i386_cpu_flags cpu_arch_tune_flags
;
678 /* CPU instruction set architecture used. */
679 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
681 /* CPU feature flags of instruction set architecture used. */
682 i386_cpu_flags cpu_arch_isa_flags
;
684 /* If set, conditional jumps are not automatically promoted to handle
685 larger than a byte offset. */
686 static unsigned int no_cond_jump_promotion
= 0;
688 /* Encode SSE instructions with VEX prefix. */
689 static unsigned int sse2avx
;
691 /* Encode scalar AVX instructions with specific vector length. */
698 /* Encode VEX WIG instructions with specific vex.w. */
705 /* Encode scalar EVEX LIG instructions with specific vector length. */
713 /* Encode EVEX WIG instructions with specific evex.w. */
720 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
721 static enum rc_type evexrcig
= rne
;
723 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
724 static symbolS
*GOT_symbol
;
726 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
727 unsigned int x86_dwarf2_return_column
;
729 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
730 int x86_cie_data_alignment
;
732 /* Interface to relax_segment.
733 There are 3 major relax states for 386 jump insns because the
734 different types of jumps add different sizes to frags when we're
735 figuring out what sort of jump to choose to reach a given label. */
738 #define UNCOND_JUMP 0
740 #define COND_JUMP86 2
745 #define SMALL16 (SMALL | CODE16)
747 #define BIG16 (BIG | CODE16)
751 #define INLINE __inline__
757 #define ENCODE_RELAX_STATE(type, size) \
758 ((relax_substateT) (((type) << 2) | (size)))
759 #define TYPE_FROM_RELAX_STATE(s) \
761 #define DISP_SIZE_FROM_RELAX_STATE(s) \
762 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
764 /* This table is used by relax_frag to promote short jumps to long
765 ones where necessary. SMALL (short) jumps may be promoted to BIG
766 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
767 don't allow a short jump in a 32 bit code segment to be promoted to
768 a 16 bit offset jump because it's slower (requires data size
769 prefix), and doesn't work, unless the destination is in the bottom
770 64k of the code segment (The top 16 bits of eip are zeroed). */
772 const relax_typeS md_relax_table
[] =
775 1) most positive reach of this state,
776 2) most negative reach of this state,
777 3) how many bytes this mode will have in the variable part of the frag
778 4) which index into the table to try if we can't fit into this one. */
780 /* UNCOND_JUMP states. */
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
783 /* dword jmp adds 4 bytes to frag:
784 0 extra opcode bytes, 4 displacement bytes. */
786 /* word jmp adds 2 byte2 to frag:
787 0 extra opcode bytes, 2 displacement bytes. */
790 /* COND_JUMP states. */
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
792 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
793 /* dword conditionals adds 5 bytes to frag:
794 1 extra opcode byte, 4 displacement bytes. */
796 /* word conditionals add 3 bytes to frag:
797 1 extra opcode byte, 2 displacement bytes. */
800 /* COND_JUMP86 states. */
801 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
802 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
803 /* dword conditionals adds 5 bytes to frag:
804 1 extra opcode byte, 4 displacement bytes. */
806 /* word conditionals add 4 bytes to frag:
807 1 displacement byte and a 3 byte long branch insn. */
811 static const arch_entry cpu_arch
[] =
813 /* Do not replace the first two entries - i386_target_format()
814 relies on them being there in this order. */
815 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
816 CPU_GENERIC32_FLAGS
, 0 },
817 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
818 CPU_GENERIC64_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
821 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
823 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
825 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
827 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
829 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
831 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
833 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
835 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
836 CPU_PENTIUMPRO_FLAGS
, 0 },
837 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
839 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
841 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
843 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
845 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
846 CPU_NOCONA_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
849 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
851 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
852 CPU_CORE2_FLAGS
, 1 },
853 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
854 CPU_CORE2_FLAGS
, 0 },
855 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
856 CPU_COREI7_FLAGS
, 0 },
857 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
859 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
861 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
862 CPU_IAMCU_FLAGS
, 0 },
863 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
865 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
867 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
868 CPU_ATHLON_FLAGS
, 0 },
869 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
871 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
873 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
875 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
876 CPU_AMDFAM10_FLAGS
, 0 },
877 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
878 CPU_BDVER1_FLAGS
, 0 },
879 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
880 CPU_BDVER2_FLAGS
, 0 },
881 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
882 CPU_BDVER3_FLAGS
, 0 },
883 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
884 CPU_BDVER4_FLAGS
, 0 },
885 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
886 CPU_ZNVER1_FLAGS
, 0 },
887 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
888 CPU_ZNVER2_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
890 CPU_BTVER1_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
892 CPU_BTVER2_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
901 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
905 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
907 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
909 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
911 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
914 CPU_SSSE3_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4_1_FLAGS
, 0 },
917 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
918 CPU_SSE4_2_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
920 CPU_SSE4_2_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
926 CPU_AVX512F_FLAGS
, 0 },
927 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
928 CPU_AVX512CD_FLAGS
, 0 },
929 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
930 CPU_AVX512ER_FLAGS
, 0 },
931 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
932 CPU_AVX512PF_FLAGS
, 0 },
933 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
934 CPU_AVX512DQ_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
936 CPU_AVX512BW_FLAGS
, 0 },
937 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
938 CPU_AVX512VL_FLAGS
, 0 },
939 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
941 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
942 CPU_VMFUNC_FLAGS
, 0 },
943 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
946 CPU_XSAVE_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
948 CPU_XSAVEOPT_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
950 CPU_XSAVEC_FLAGS
, 0 },
951 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
952 CPU_XSAVES_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
955 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
956 CPU_PCLMUL_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
958 CPU_PCLMUL_FLAGS
, 1 },
959 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
960 CPU_FSGSBASE_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
962 CPU_RDRND_FLAGS
, 0 },
963 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
976 CPU_MOVBE_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
982 CPU_LZCNT_FLAGS
, 0 },
983 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
987 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
988 CPU_INVPCID_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
990 CPU_CLFLUSH_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
994 CPU_SYSCALL_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
996 CPU_RDTSCP_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
998 CPU_3DNOW_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1000 CPU_3DNOWA_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1002 CPU_PADLOCK_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1004 CPU_SVME_FLAGS
, 1 },
1005 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1006 CPU_SVME_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1008 CPU_SSE4A_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1011 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1015 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1018 CPU_RDSEED_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1020 CPU_PRFCHW_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1022 CPU_SMAP_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1025 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1028 CPU_CLFLUSHOPT_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1030 CPU_PREFETCHWT1_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1033 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1034 CPU_CLWB_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1036 CPU_AVX512IFMA_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1038 CPU_AVX512VBMI_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1040 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1041 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1042 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1044 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1045 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1046 CPU_AVX512_VBMI2_FLAGS
, 0 },
1047 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1048 CPU_AVX512_VNNI_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1050 CPU_AVX512_BITALG_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1052 CPU_CLZERO_FLAGS
, 0 },
1053 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1054 CPU_MWAITX_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1056 CPU_OSPKE_FLAGS
, 0 },
1057 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1058 CPU_RDPID_FLAGS
, 0 },
1059 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1060 CPU_PTWRITE_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1063 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1064 CPU_SHSTK_FLAGS
, 0 },
1065 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1066 CPU_GFNI_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1068 CPU_VAES_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1070 CPU_VPCLMULQDQ_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1072 CPU_WBNOINVD_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1074 CPU_PCONFIG_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1076 CPU_WAITPKG_FLAGS
, 0 },
1077 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1078 CPU_CLDEMOTE_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1080 CPU_MOVDIRI_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1082 CPU_MOVDIR64B_FLAGS
, 0 },
1083 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1084 CPU_AVX512_BF16_FLAGS
, 0 },
1085 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1086 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1087 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1088 CPU_ENQCMD_FLAGS
, 0 },
1091 static const noarch_entry cpu_noarch
[] =
1093 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1094 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1095 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1096 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1097 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1098 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1099 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1100 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1101 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1102 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1103 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1106 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1107 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1108 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1109 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1124 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1125 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1126 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1127 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1128 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1129 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1130 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1134 /* Like s_lcomm_internal in gas/read.c but the alignment string
1135 is allowed to be optional. */
1138 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1145 && *input_line_pointer
== ',')
1147 align
= parse_align (needs_align
- 1);
1149 if (align
== (addressT
) -1)
1164 bss_alloc (symbolP
, size
, align
);
1169 pe_lcomm (int needs_align
)
1171 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1175 const pseudo_typeS md_pseudo_table
[] =
1177 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1178 {"align", s_align_bytes
, 0},
1180 {"align", s_align_ptwo
, 0},
1182 {"arch", set_cpu_arch
, 0},
1186 {"lcomm", pe_lcomm
, 1},
1188 {"ffloat", float_cons
, 'f'},
1189 {"dfloat", float_cons
, 'd'},
1190 {"tfloat", float_cons
, 'x'},
1192 {"slong", signed_cons
, 4},
1193 {"noopt", s_ignore
, 0},
1194 {"optim", s_ignore
, 0},
1195 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1196 {"code16", set_code_flag
, CODE_16BIT
},
1197 {"code32", set_code_flag
, CODE_32BIT
},
1199 {"code64", set_code_flag
, CODE_64BIT
},
1201 {"intel_syntax", set_intel_syntax
, 1},
1202 {"att_syntax", set_intel_syntax
, 0},
1203 {"intel_mnemonic", set_intel_mnemonic
, 1},
1204 {"att_mnemonic", set_intel_mnemonic
, 0},
1205 {"allow_index_reg", set_allow_index_reg
, 1},
1206 {"disallow_index_reg", set_allow_index_reg
, 0},
1207 {"sse_check", set_check
, 0},
1208 {"operand_check", set_check
, 1},
1209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1210 {"largecomm", handle_large_common
, 0},
1212 {"file", dwarf2_directive_file
, 0},
1213 {"loc", dwarf2_directive_loc
, 0},
1214 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1217 {"secrel32", pe_directive_secrel
, 0},
1222 /* For interface with expression (). */
1223 extern char *input_line_pointer
;
1225 /* Hash table for instruction mnemonic lookup. */
1226 static struct hash_control
*op_hash
;
1228 /* Hash table for register lookup. */
1229 static struct hash_control
*reg_hash
;
1231 /* Various efficient no-op patterns for aligning code labels.
1232 Note: Don't try to assemble the instructions in the comments.
1233 0L and 0w are not legal. */
1234 static const unsigned char f32_1
[] =
1236 static const unsigned char f32_2
[] =
1237 {0x66,0x90}; /* xchg %ax,%ax */
1238 static const unsigned char f32_3
[] =
1239 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1240 static const unsigned char f32_4
[] =
1241 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1242 static const unsigned char f32_6
[] =
1243 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1244 static const unsigned char f32_7
[] =
1245 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1246 static const unsigned char f16_3
[] =
1247 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1248 static const unsigned char f16_4
[] =
1249 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1250 static const unsigned char jump_disp8
[] =
1251 {0xeb}; /* jmp disp8 */
1252 static const unsigned char jump32_disp32
[] =
1253 {0xe9}; /* jmp disp32 */
1254 static const unsigned char jump16_disp32
[] =
1255 {0x66,0xe9}; /* jmp disp32 */
1256 /* 32-bit NOPs patterns. */
1257 static const unsigned char *const f32_patt
[] = {
1258 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1260 /* 16-bit NOPs patterns. */
1261 static const unsigned char *const f16_patt
[] = {
1262 f32_1
, f32_2
, f16_3
, f16_4
1264 /* nopl (%[re]ax) */
1265 static const unsigned char alt_3
[] =
1267 /* nopl 0(%[re]ax) */
1268 static const unsigned char alt_4
[] =
1269 {0x0f,0x1f,0x40,0x00};
1270 /* nopl 0(%[re]ax,%[re]ax,1) */
1271 static const unsigned char alt_5
[] =
1272 {0x0f,0x1f,0x44,0x00,0x00};
1273 /* nopw 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_6
[] =
1275 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopl 0L(%[re]ax) */
1277 static const unsigned char alt_7
[] =
1278 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1279 /* nopl 0L(%[re]ax,%[re]ax,1) */
1280 static const unsigned char alt_8
[] =
1281 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1282 /* nopw 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_9
[] =
1284 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_10
[] =
1287 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* data16 nopw %cs:0L(%eax,%eax,1) */
1289 static const unsigned char alt_11
[] =
1290 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* 32-bit and 64-bit NOPs patterns. */
1292 static const unsigned char *const alt_patt
[] = {
1293 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1294 alt_9
, alt_10
, alt_11
1297 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1298 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1301 i386_output_nops (char *where
, const unsigned char *const *patt
,
1302 int count
, int max_single_nop_size
)
1305 /* Place the longer NOP first. */
1308 const unsigned char *nops
;
1310 if (max_single_nop_size
< 1)
1312 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1313 max_single_nop_size
);
1317 nops
= patt
[max_single_nop_size
- 1];
1319 /* Use the smaller one if the requsted one isn't available. */
1322 max_single_nop_size
--;
1323 nops
= patt
[max_single_nop_size
- 1];
1326 last
= count
% max_single_nop_size
;
1329 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1330 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1334 nops
= patt
[last
- 1];
1337 /* Use the smaller one plus one-byte NOP if the needed one
1340 nops
= patt
[last
- 1];
1341 memcpy (where
+ offset
, nops
, last
);
1342 where
[offset
+ last
] = *patt
[0];
1345 memcpy (where
+ offset
, nops
, last
);
1350 fits_in_imm7 (offsetT num
)
1352 return (num
& 0x7f) == num
;
1356 fits_in_imm31 (offsetT num
)
1358 return (num
& 0x7fffffff) == num
;
1361 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1362 single NOP instruction LIMIT. */
1365 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1367 const unsigned char *const *patt
= NULL
;
1368 int max_single_nop_size
;
1369 /* Maximum number of NOPs before switching to jump over NOPs. */
1370 int max_number_of_nops
;
1372 switch (fragP
->fr_type
)
1381 /* We need to decide which NOP sequence to use for 32bit and
1382 64bit. When -mtune= is used:
1384 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1385 PROCESSOR_GENERIC32, f32_patt will be used.
1386 2. For the rest, alt_patt will be used.
1388 When -mtune= isn't used, alt_patt will be used if
1389 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1392 When -march= or .arch is used, we can't use anything beyond
1393 cpu_arch_isa_flags. */
1395 if (flag_code
== CODE_16BIT
)
1398 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1399 /* Limit number of NOPs to 2 in 16-bit mode. */
1400 max_number_of_nops
= 2;
1404 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1406 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1407 switch (cpu_arch_tune
)
1409 case PROCESSOR_UNKNOWN
:
1410 /* We use cpu_arch_isa_flags to check if we SHOULD
1411 optimize with nops. */
1412 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1417 case PROCESSOR_PENTIUM4
:
1418 case PROCESSOR_NOCONA
:
1419 case PROCESSOR_CORE
:
1420 case PROCESSOR_CORE2
:
1421 case PROCESSOR_COREI7
:
1422 case PROCESSOR_L1OM
:
1423 case PROCESSOR_K1OM
:
1424 case PROCESSOR_GENERIC64
:
1426 case PROCESSOR_ATHLON
:
1428 case PROCESSOR_AMDFAM10
:
1430 case PROCESSOR_ZNVER
:
1434 case PROCESSOR_I386
:
1435 case PROCESSOR_I486
:
1436 case PROCESSOR_PENTIUM
:
1437 case PROCESSOR_PENTIUMPRO
:
1438 case PROCESSOR_IAMCU
:
1439 case PROCESSOR_GENERIC32
:
1446 switch (fragP
->tc_frag_data
.tune
)
1448 case PROCESSOR_UNKNOWN
:
1449 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1450 PROCESSOR_UNKNOWN. */
1454 case PROCESSOR_I386
:
1455 case PROCESSOR_I486
:
1456 case PROCESSOR_PENTIUM
:
1457 case PROCESSOR_IAMCU
:
1459 case PROCESSOR_ATHLON
:
1461 case PROCESSOR_AMDFAM10
:
1463 case PROCESSOR_ZNVER
:
1465 case PROCESSOR_GENERIC32
:
1466 /* We use cpu_arch_isa_flags to check if we CAN optimize
1468 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1473 case PROCESSOR_PENTIUMPRO
:
1474 case PROCESSOR_PENTIUM4
:
1475 case PROCESSOR_NOCONA
:
1476 case PROCESSOR_CORE
:
1477 case PROCESSOR_CORE2
:
1478 case PROCESSOR_COREI7
:
1479 case PROCESSOR_L1OM
:
1480 case PROCESSOR_K1OM
:
1481 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1486 case PROCESSOR_GENERIC64
:
1492 if (patt
== f32_patt
)
1494 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1495 /* Limit number of NOPs to 2 for older processors. */
1496 max_number_of_nops
= 2;
1500 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1501 /* Limit number of NOPs to 7 for newer processors. */
1502 max_number_of_nops
= 7;
1507 limit
= max_single_nop_size
;
1509 if (fragP
->fr_type
== rs_fill_nop
)
1511 /* Output NOPs for .nop directive. */
1512 if (limit
> max_single_nop_size
)
1514 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1515 _("invalid single nop size: %d "
1516 "(expect within [0, %d])"),
1517 limit
, max_single_nop_size
);
1522 fragP
->fr_var
= count
;
1524 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1526 /* Generate jump over NOPs. */
1527 offsetT disp
= count
- 2;
1528 if (fits_in_imm7 (disp
))
1530 /* Use "jmp disp8" if possible. */
1532 where
[0] = jump_disp8
[0];
1538 unsigned int size_of_jump
;
1540 if (flag_code
== CODE_16BIT
)
1542 where
[0] = jump16_disp32
[0];
1543 where
[1] = jump16_disp32
[1];
1548 where
[0] = jump32_disp32
[0];
1552 count
-= size_of_jump
+ 4;
1553 if (!fits_in_imm31 (count
))
1555 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1556 _("jump over nop padding out of range"));
1560 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1561 where
+= size_of_jump
+ 4;
1565 /* Generate multiple NOPs. */
1566 i386_output_nops (where
, patt
, count
, limit
);
1570 operand_type_all_zero (const union i386_operand_type
*x
)
1572 switch (ARRAY_SIZE(x
->array
))
1583 return !x
->array
[0];
1590 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1592 switch (ARRAY_SIZE(x
->array
))
1610 operand_type_equal (const union i386_operand_type
*x
,
1611 const union i386_operand_type
*y
)
1613 switch (ARRAY_SIZE(x
->array
))
1616 if (x
->array
[2] != y
->array
[2])
1620 if (x
->array
[1] != y
->array
[1])
1624 return x
->array
[0] == y
->array
[0];
1632 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1634 switch (ARRAY_SIZE(x
->array
))
1649 return !x
->array
[0];
1656 cpu_flags_equal (const union i386_cpu_flags
*x
,
1657 const union i386_cpu_flags
*y
)
1659 switch (ARRAY_SIZE(x
->array
))
1662 if (x
->array
[3] != y
->array
[3])
1666 if (x
->array
[2] != y
->array
[2])
1670 if (x
->array
[1] != y
->array
[1])
1674 return x
->array
[0] == y
->array
[0];
1682 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1684 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1685 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1688 static INLINE i386_cpu_flags
1689 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1691 switch (ARRAY_SIZE (x
.array
))
1694 x
.array
[3] &= y
.array
[3];
1697 x
.array
[2] &= y
.array
[2];
1700 x
.array
[1] &= y
.array
[1];
1703 x
.array
[0] &= y
.array
[0];
1711 static INLINE i386_cpu_flags
1712 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1714 switch (ARRAY_SIZE (x
.array
))
1717 x
.array
[3] |= y
.array
[3];
1720 x
.array
[2] |= y
.array
[2];
1723 x
.array
[1] |= y
.array
[1];
1726 x
.array
[0] |= y
.array
[0];
1734 static INLINE i386_cpu_flags
1735 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1737 switch (ARRAY_SIZE (x
.array
))
1740 x
.array
[3] &= ~y
.array
[3];
1743 x
.array
[2] &= ~y
.array
[2];
1746 x
.array
[1] &= ~y
.array
[1];
1749 x
.array
[0] &= ~y
.array
[0];
1757 #define CPU_FLAGS_ARCH_MATCH 0x1
1758 #define CPU_FLAGS_64BIT_MATCH 0x2
1760 #define CPU_FLAGS_PERFECT_MATCH \
1761 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1763 /* Return CPU flags match bits. */
1766 cpu_flags_match (const insn_template
*t
)
1768 i386_cpu_flags x
= t
->cpu_flags
;
1769 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1771 x
.bitfield
.cpu64
= 0;
1772 x
.bitfield
.cpuno64
= 0;
1774 if (cpu_flags_all_zero (&x
))
1776 /* This instruction is available on all archs. */
1777 match
|= CPU_FLAGS_ARCH_MATCH
;
1781 /* This instruction is available only on some archs. */
1782 i386_cpu_flags cpu
= cpu_arch_flags
;
1784 /* AVX512VL is no standalone feature - match it and then strip it. */
1785 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1787 x
.bitfield
.cpuavx512vl
= 0;
1789 cpu
= cpu_flags_and (x
, cpu
);
1790 if (!cpu_flags_all_zero (&cpu
))
1792 if (x
.bitfield
.cpuavx
)
1794 /* We need to check a few extra flags with AVX. */
1795 if (cpu
.bitfield
.cpuavx
1796 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1797 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1798 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1799 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1800 match
|= CPU_FLAGS_ARCH_MATCH
;
1802 else if (x
.bitfield
.cpuavx512f
)
1804 /* We need to check a few extra flags with AVX512F. */
1805 if (cpu
.bitfield
.cpuavx512f
1806 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1807 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1808 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1809 match
|= CPU_FLAGS_ARCH_MATCH
;
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1818 static INLINE i386_operand_type
1819 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1821 switch (ARRAY_SIZE (x
.array
))
1824 x
.array
[2] &= y
.array
[2];
1827 x
.array
[1] &= y
.array
[1];
1830 x
.array
[0] &= y
.array
[0];
1838 static INLINE i386_operand_type
1839 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1841 switch (ARRAY_SIZE (x
.array
))
1844 x
.array
[2] &= ~y
.array
[2];
1847 x
.array
[1] &= ~y
.array
[1];
1850 x
.array
[0] &= ~y
.array
[0];
1858 static INLINE i386_operand_type
1859 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1861 switch (ARRAY_SIZE (x
.array
))
1864 x
.array
[2] |= y
.array
[2];
1867 x
.array
[1] |= y
.array
[1];
1870 x
.array
[0] |= y
.array
[0];
1878 static INLINE i386_operand_type
1879 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1881 switch (ARRAY_SIZE (x
.array
))
1884 x
.array
[2] ^= y
.array
[2];
1887 x
.array
[1] ^= y
.array
[1];
1890 x
.array
[0] ^= y
.array
[0];
1898 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1899 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1900 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1901 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1902 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1903 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1904 static const i386_operand_type anydisp
1905 = OPERAND_TYPE_ANYDISP
;
1906 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1907 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1908 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1909 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1910 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1911 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1912 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1913 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1914 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1915 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1916 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1917 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1928 operand_type_check (i386_operand_type t
, enum operand_type c
)
1933 return t
.bitfield
.reg
;
1936 return (t
.bitfield
.imm8
1940 || t
.bitfield
.imm32s
1941 || t
.bitfield
.imm64
);
1944 return (t
.bitfield
.disp8
1945 || t
.bitfield
.disp16
1946 || t
.bitfield
.disp32
1947 || t
.bitfield
.disp32s
1948 || t
.bitfield
.disp64
);
1951 return (t
.bitfield
.disp8
1952 || t
.bitfield
.disp16
1953 || t
.bitfield
.disp32
1954 || t
.bitfield
.disp32s
1955 || t
.bitfield
.disp64
1956 || t
.bitfield
.baseindex
);
1965 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1966 between operand GIVEN and opeand WANTED for instruction template T. */
1969 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1972 return !((i
.types
[given
].bitfield
.byte
1973 && !t
->operand_types
[wanted
].bitfield
.byte
)
1974 || (i
.types
[given
].bitfield
.word
1975 && !t
->operand_types
[wanted
].bitfield
.word
)
1976 || (i
.types
[given
].bitfield
.dword
1977 && !t
->operand_types
[wanted
].bitfield
.dword
)
1978 || (i
.types
[given
].bitfield
.qword
1979 && !t
->operand_types
[wanted
].bitfield
.qword
)
1980 || (i
.types
[given
].bitfield
.tbyte
1981 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1984 /* Return 1 if there is no conflict in SIMD register between operand
1985 GIVEN and opeand WANTED for instruction template T. */
1988 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1991 return !((i
.types
[given
].bitfield
.xmmword
1992 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1993 || (i
.types
[given
].bitfield
.ymmword
1994 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1995 || (i
.types
[given
].bitfield
.zmmword
1996 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1999 /* Return 1 if there is no conflict in any size between operand GIVEN
2000 and opeand WANTED for instruction template T. */
2003 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2006 return (match_operand_size (t
, wanted
, given
)
2007 && !((i
.types
[given
].bitfield
.unspecified
2009 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2010 || (i
.types
[given
].bitfield
.fword
2011 && !t
->operand_types
[wanted
].bitfield
.fword
)
2012 /* For scalar opcode templates to allow register and memory
2013 operands at the same time, some special casing is needed
2014 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2015 down-conversion vpmov*. */
2016 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2017 && !t
->opcode_modifier
.broadcast
2018 && (t
->operand_types
[wanted
].bitfield
.byte
2019 || t
->operand_types
[wanted
].bitfield
.word
2020 || t
->operand_types
[wanted
].bitfield
.dword
2021 || t
->operand_types
[wanted
].bitfield
.qword
))
2022 ? (i
.types
[given
].bitfield
.xmmword
2023 || i
.types
[given
].bitfield
.ymmword
2024 || i
.types
[given
].bitfield
.zmmword
)
2025 : !match_simd_size(t
, wanted
, given
))));
2028 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2029 operands for instruction template T, and it has MATCH_REVERSE set if there
2030 is no size conflict on any operands for the template with operands reversed
2031 (and the template allows for reversing in the first place). */
2033 #define MATCH_STRAIGHT 1
2034 #define MATCH_REVERSE 2
2036 static INLINE
unsigned int
2037 operand_size_match (const insn_template
*t
)
2039 unsigned int j
, match
= MATCH_STRAIGHT
;
2041 /* Don't check jump instructions. */
2042 if (t
->opcode_modifier
.jump
2043 || t
->opcode_modifier
.jumpbyte
2044 || t
->opcode_modifier
.jumpdword
2045 || t
->opcode_modifier
.jumpintersegment
)
2048 /* Check memory and accumulator operand size. */
2049 for (j
= 0; j
< i
.operands
; j
++)
2051 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2052 && t
->operand_types
[j
].bitfield
.anysize
)
2055 if (t
->operand_types
[j
].bitfield
.reg
2056 && !match_operand_size (t
, j
, j
))
2062 if (t
->operand_types
[j
].bitfield
.regsimd
2063 && !match_simd_size (t
, j
, j
))
2069 if (t
->operand_types
[j
].bitfield
.acc
2070 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2076 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2083 if (!t
->opcode_modifier
.d
)
2087 i
.error
= operand_size_mismatch
;
2091 /* Check reverse. */
2092 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2094 for (j
= 0; j
< i
.operands
; j
++)
2096 unsigned int given
= i
.operands
- j
- 1;
2098 if (t
->operand_types
[j
].bitfield
.reg
2099 && !match_operand_size (t
, j
, given
))
2102 if (t
->operand_types
[j
].bitfield
.regsimd
2103 && !match_simd_size (t
, j
, given
))
2106 if (t
->operand_types
[j
].bitfield
.acc
2107 && (!match_operand_size (t
, j
, given
)
2108 || !match_simd_size (t
, j
, given
)))
2111 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2115 return match
| MATCH_REVERSE
;
2119 operand_type_match (i386_operand_type overlap
,
2120 i386_operand_type given
)
2122 i386_operand_type temp
= overlap
;
2124 temp
.bitfield
.jumpabsolute
= 0;
2125 temp
.bitfield
.unspecified
= 0;
2126 temp
.bitfield
.byte
= 0;
2127 temp
.bitfield
.word
= 0;
2128 temp
.bitfield
.dword
= 0;
2129 temp
.bitfield
.fword
= 0;
2130 temp
.bitfield
.qword
= 0;
2131 temp
.bitfield
.tbyte
= 0;
2132 temp
.bitfield
.xmmword
= 0;
2133 temp
.bitfield
.ymmword
= 0;
2134 temp
.bitfield
.zmmword
= 0;
2135 if (operand_type_all_zero (&temp
))
2138 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2139 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2143 i
.error
= operand_type_mismatch
;
2147 /* If given types g0 and g1 are registers they must be of the same type
2148 unless the expected operand type register overlap is null.
2149 Memory operand size of certain SIMD instructions is also being checked
2153 operand_type_register_match (i386_operand_type g0
,
2154 i386_operand_type t0
,
2155 i386_operand_type g1
,
2156 i386_operand_type t1
)
2158 if (!g0
.bitfield
.reg
2159 && !g0
.bitfield
.regsimd
2160 && (!operand_type_check (g0
, anymem
)
2161 || g0
.bitfield
.unspecified
2162 || !t0
.bitfield
.regsimd
))
2165 if (!g1
.bitfield
.reg
2166 && !g1
.bitfield
.regsimd
2167 && (!operand_type_check (g1
, anymem
)
2168 || g1
.bitfield
.unspecified
2169 || !t1
.bitfield
.regsimd
))
2172 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2173 && g0
.bitfield
.word
== g1
.bitfield
.word
2174 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2175 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2176 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2177 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2178 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2181 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2182 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2183 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2184 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2185 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2186 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2187 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2190 i
.error
= register_type_mismatch
;
2195 static INLINE
unsigned int
2196 register_number (const reg_entry
*r
)
2198 unsigned int nr
= r
->reg_num
;
2200 if (r
->reg_flags
& RegRex
)
2203 if (r
->reg_flags
& RegVRex
)
2209 static INLINE
unsigned int
2210 mode_from_disp_size (i386_operand_type t
)
2212 if (t
.bitfield
.disp8
)
2214 else if (t
.bitfield
.disp16
2215 || t
.bitfield
.disp32
2216 || t
.bitfield
.disp32s
)
2223 fits_in_signed_byte (addressT num
)
2225 return num
+ 0x80 <= 0xff;
2229 fits_in_unsigned_byte (addressT num
)
2235 fits_in_unsigned_word (addressT num
)
2237 return num
<= 0xffff;
2241 fits_in_signed_word (addressT num
)
2243 return num
+ 0x8000 <= 0xffff;
2247 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2252 return num
+ 0x80000000 <= 0xffffffff;
2254 } /* fits_in_signed_long() */
2257 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2262 return num
<= 0xffffffff;
2264 } /* fits_in_unsigned_long() */
2267 fits_in_disp8 (offsetT num
)
2269 int shift
= i
.memshift
;
2275 mask
= (1 << shift
) - 1;
2277 /* Return 0 if NUM isn't properly aligned. */
2281 /* Check if NUM will fit in 8bit after shift. */
2282 return fits_in_signed_byte (num
>> shift
);
2286 fits_in_imm4 (offsetT num
)
2288 return (num
& 0xf) == num
;
2291 static i386_operand_type
2292 smallest_imm_type (offsetT num
)
2294 i386_operand_type t
;
2296 operand_type_set (&t
, 0);
2297 t
.bitfield
.imm64
= 1;
2299 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2301 /* This code is disabled on the 486 because all the Imm1 forms
2302 in the opcode table are slower on the i486. They're the
2303 versions with the implicitly specified single-position
2304 displacement, which has another syntax if you really want to
2306 t
.bitfield
.imm1
= 1;
2307 t
.bitfield
.imm8
= 1;
2308 t
.bitfield
.imm8s
= 1;
2309 t
.bitfield
.imm16
= 1;
2310 t
.bitfield
.imm32
= 1;
2311 t
.bitfield
.imm32s
= 1;
2313 else if (fits_in_signed_byte (num
))
2315 t
.bitfield
.imm8
= 1;
2316 t
.bitfield
.imm8s
= 1;
2317 t
.bitfield
.imm16
= 1;
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_byte (num
))
2323 t
.bitfield
.imm8
= 1;
2324 t
.bitfield
.imm16
= 1;
2325 t
.bitfield
.imm32
= 1;
2326 t
.bitfield
.imm32s
= 1;
2328 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2330 t
.bitfield
.imm16
= 1;
2331 t
.bitfield
.imm32
= 1;
2332 t
.bitfield
.imm32s
= 1;
2334 else if (fits_in_signed_long (num
))
2336 t
.bitfield
.imm32
= 1;
2337 t
.bitfield
.imm32s
= 1;
2339 else if (fits_in_unsigned_long (num
))
2340 t
.bitfield
.imm32
= 1;
2346 offset_in_range (offsetT val
, int size
)
2352 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2353 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2354 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2356 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2362 /* If BFD64, sign extend val for 32bit address mode. */
2363 if (flag_code
!= CODE_64BIT
2364 || i
.prefix
[ADDR_PREFIX
])
2365 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2366 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2369 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2371 char buf1
[40], buf2
[40];
2373 sprint_value (buf1
, val
);
2374 sprint_value (buf2
, val
& mask
);
2375 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2390 a. PREFIX_EXIST if attempting to add a prefix where one from the
2391 same class already exists.
2392 b. PREFIX_LOCK if lock prefix is added.
2393 c. PREFIX_REP if rep/repne prefix is added.
2394 d. PREFIX_DS if ds prefix is added.
2395 e. PREFIX_OTHER if other prefix is added.
2398 static enum PREFIX_GROUP
2399 add_prefix (unsigned int prefix
)
2401 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2404 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2405 && flag_code
== CODE_64BIT
)
2407 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2408 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2409 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2410 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2421 case DS_PREFIX_OPCODE
:
2424 case CS_PREFIX_OPCODE
:
2425 case ES_PREFIX_OPCODE
:
2426 case FS_PREFIX_OPCODE
:
2427 case GS_PREFIX_OPCODE
:
2428 case SS_PREFIX_OPCODE
:
2432 case REPNE_PREFIX_OPCODE
:
2433 case REPE_PREFIX_OPCODE
:
2438 case LOCK_PREFIX_OPCODE
:
2447 case ADDR_PREFIX_OPCODE
:
2451 case DATA_PREFIX_OPCODE
:
2455 if (i
.prefix
[q
] != 0)
2463 i
.prefix
[q
] |= prefix
;
2466 as_bad (_("same type of prefix used twice"));
2472 update_code_flag (int value
, int check
)
2474 PRINTF_LIKE ((*as_error
));
2476 flag_code
= (enum flag_code
) value
;
2477 if (flag_code
== CODE_64BIT
)
2479 cpu_arch_flags
.bitfield
.cpu64
= 1;
2480 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2484 cpu_arch_flags
.bitfield
.cpu64
= 0;
2485 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2487 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2490 as_error
= as_fatal
;
2493 (*as_error
) (_("64bit mode not supported on `%s'."),
2494 cpu_arch_name
? cpu_arch_name
: default_arch
);
2496 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2499 as_error
= as_fatal
;
2502 (*as_error
) (_("32bit mode not supported on `%s'."),
2503 cpu_arch_name
? cpu_arch_name
: default_arch
);
2505 stackop_size
= '\0';
2509 set_code_flag (int value
)
2511 update_code_flag (value
, 0);
2515 set_16bit_gcc_code_flag (int new_code_flag
)
2517 flag_code
= (enum flag_code
) new_code_flag
;
2518 if (flag_code
!= CODE_16BIT
)
2520 cpu_arch_flags
.bitfield
.cpu64
= 0;
2521 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2522 stackop_size
= LONG_MNEM_SUFFIX
;
2526 set_intel_syntax (int syntax_flag
)
2528 /* Find out if register prefixing is specified. */
2529 int ask_naked_reg
= 0;
2532 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2535 int e
= get_symbol_name (&string
);
2537 if (strcmp (string
, "prefix") == 0)
2539 else if (strcmp (string
, "noprefix") == 0)
2542 as_bad (_("bad argument to syntax directive."));
2543 (void) restore_line_pointer (e
);
2545 demand_empty_rest_of_line ();
2547 intel_syntax
= syntax_flag
;
2549 if (ask_naked_reg
== 0)
2550 allow_naked_reg
= (intel_syntax
2551 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2553 allow_naked_reg
= (ask_naked_reg
< 0);
2555 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2557 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2558 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2559 register_prefix
= allow_naked_reg
? "" : "%";
2563 set_intel_mnemonic (int mnemonic_flag
)
2565 intel_mnemonic
= mnemonic_flag
;
2569 set_allow_index_reg (int flag
)
2571 allow_index_reg
= flag
;
2575 set_check (int what
)
2577 enum check_kind
*kind
;
2582 kind
= &operand_check
;
2593 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2596 int e
= get_symbol_name (&string
);
2598 if (strcmp (string
, "none") == 0)
2600 else if (strcmp (string
, "warning") == 0)
2601 *kind
= check_warning
;
2602 else if (strcmp (string
, "error") == 0)
2603 *kind
= check_error
;
2605 as_bad (_("bad argument to %s_check directive."), str
);
2606 (void) restore_line_pointer (e
);
2609 as_bad (_("missing argument for %s_check directive"), str
);
2611 demand_empty_rest_of_line ();
2615 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2616 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2619 static const char *arch
;
2621 /* Intel LIOM is only supported on ELF. */
2627 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2628 use default_arch. */
2629 arch
= cpu_arch_name
;
2631 arch
= default_arch
;
2634 /* If we are targeting Intel MCU, we must enable it. */
2635 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2636 || new_flag
.bitfield
.cpuiamcu
)
2639 /* If we are targeting Intel L1OM, we must enable it. */
2640 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2641 || new_flag
.bitfield
.cpul1om
)
2644 /* If we are targeting Intel K1OM, we must enable it. */
2645 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2646 || new_flag
.bitfield
.cpuk1om
)
2649 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2654 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2658 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2661 int e
= get_symbol_name (&string
);
2663 i386_cpu_flags flags
;
2665 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2667 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2669 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2673 cpu_arch_name
= cpu_arch
[j
].name
;
2674 cpu_sub_arch_name
= NULL
;
2675 cpu_arch_flags
= cpu_arch
[j
].flags
;
2676 if (flag_code
== CODE_64BIT
)
2678 cpu_arch_flags
.bitfield
.cpu64
= 1;
2679 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2683 cpu_arch_flags
.bitfield
.cpu64
= 0;
2684 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 cpu_arch_isa
= cpu_arch
[j
].type
;
2687 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2688 if (!cpu_arch_tune_set
)
2690 cpu_arch_tune
= cpu_arch_isa
;
2691 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2696 flags
= cpu_flags_or (cpu_arch_flags
,
2699 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2701 if (cpu_sub_arch_name
)
2703 char *name
= cpu_sub_arch_name
;
2704 cpu_sub_arch_name
= concat (name
,
2706 (const char *) NULL
);
2710 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2711 cpu_arch_flags
= flags
;
2712 cpu_arch_isa_flags
= flags
;
2716 = cpu_flags_or (cpu_arch_isa_flags
,
2718 (void) restore_line_pointer (e
);
2719 demand_empty_rest_of_line ();
2724 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2726 /* Disable an ISA extension. */
2727 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2728 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2730 flags
= cpu_flags_and_not (cpu_arch_flags
,
2731 cpu_noarch
[j
].flags
);
2732 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2734 if (cpu_sub_arch_name
)
2736 char *name
= cpu_sub_arch_name
;
2737 cpu_sub_arch_name
= concat (name
, string
,
2738 (const char *) NULL
);
2742 cpu_sub_arch_name
= xstrdup (string
);
2743 cpu_arch_flags
= flags
;
2744 cpu_arch_isa_flags
= flags
;
2746 (void) restore_line_pointer (e
);
2747 demand_empty_rest_of_line ();
2751 j
= ARRAY_SIZE (cpu_arch
);
2754 if (j
>= ARRAY_SIZE (cpu_arch
))
2755 as_bad (_("no such architecture: `%s'"), string
);
2757 *input_line_pointer
= e
;
2760 as_bad (_("missing cpu architecture"));
2762 no_cond_jump_promotion
= 0;
2763 if (*input_line_pointer
== ','
2764 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2769 ++input_line_pointer
;
2770 e
= get_symbol_name (&string
);
2772 if (strcmp (string
, "nojumps") == 0)
2773 no_cond_jump_promotion
= 1;
2774 else if (strcmp (string
, "jumps") == 0)
2777 as_bad (_("no such architecture modifier: `%s'"), string
);
2779 (void) restore_line_pointer (e
);
2782 demand_empty_rest_of_line ();
2785 enum bfd_architecture
2788 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2790 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2791 || flag_code
!= CODE_64BIT
)
2792 as_fatal (_("Intel L1OM is 64bit ELF only"));
2793 return bfd_arch_l1om
;
2795 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2797 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2798 || flag_code
!= CODE_64BIT
)
2799 as_fatal (_("Intel K1OM is 64bit ELF only"));
2800 return bfd_arch_k1om
;
2802 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2804 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2805 || flag_code
== CODE_64BIT
)
2806 as_fatal (_("Intel MCU is 32bit ELF only"));
2807 return bfd_arch_iamcu
;
2810 return bfd_arch_i386
;
2816 if (!strncmp (default_arch
, "x86_64", 6))
2818 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2820 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2821 || default_arch
[6] != '\0')
2822 as_fatal (_("Intel L1OM is 64bit ELF only"));
2823 return bfd_mach_l1om
;
2825 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2827 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2828 || default_arch
[6] != '\0')
2829 as_fatal (_("Intel K1OM is 64bit ELF only"));
2830 return bfd_mach_k1om
;
2832 else if (default_arch
[6] == '\0')
2833 return bfd_mach_x86_64
;
2835 return bfd_mach_x64_32
;
2837 else if (!strcmp (default_arch
, "i386")
2838 || !strcmp (default_arch
, "iamcu"))
2840 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2842 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2843 as_fatal (_("Intel MCU is 32bit ELF only"));
2844 return bfd_mach_i386_iamcu
;
2847 return bfd_mach_i386_i386
;
2850 as_fatal (_("unknown architecture"));
2856 const char *hash_err
;
2858 /* Support pseudo prefixes like {disp32}. */
2859 lex_type
['{'] = LEX_BEGIN_NAME
;
2861 /* Initialize op_hash hash table. */
2862 op_hash
= hash_new ();
2865 const insn_template
*optab
;
2866 templates
*core_optab
;
2868 /* Setup for loop. */
2870 core_optab
= XNEW (templates
);
2871 core_optab
->start
= optab
;
2876 if (optab
->name
== NULL
2877 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2879 /* different name --> ship out current template list;
2880 add to hash table; & begin anew. */
2881 core_optab
->end
= optab
;
2882 hash_err
= hash_insert (op_hash
,
2884 (void *) core_optab
);
2887 as_fatal (_("can't hash %s: %s"),
2891 if (optab
->name
== NULL
)
2893 core_optab
= XNEW (templates
);
2894 core_optab
->start
= optab
;
2899 /* Initialize reg_hash hash table. */
2900 reg_hash
= hash_new ();
2902 const reg_entry
*regtab
;
2903 unsigned int regtab_size
= i386_regtab_size
;
2905 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2907 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2909 as_fatal (_("can't hash %s: %s"),
2915 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2920 for (c
= 0; c
< 256; c
++)
2925 mnemonic_chars
[c
] = c
;
2926 register_chars
[c
] = c
;
2927 operand_chars
[c
] = c
;
2929 else if (ISLOWER (c
))
2931 mnemonic_chars
[c
] = c
;
2932 register_chars
[c
] = c
;
2933 operand_chars
[c
] = c
;
2935 else if (ISUPPER (c
))
2937 mnemonic_chars
[c
] = TOLOWER (c
);
2938 register_chars
[c
] = mnemonic_chars
[c
];
2939 operand_chars
[c
] = c
;
2941 else if (c
== '{' || c
== '}')
2943 mnemonic_chars
[c
] = c
;
2944 operand_chars
[c
] = c
;
2947 if (ISALPHA (c
) || ISDIGIT (c
))
2948 identifier_chars
[c
] = c
;
2951 identifier_chars
[c
] = c
;
2952 operand_chars
[c
] = c
;
2957 identifier_chars
['@'] = '@';
2960 identifier_chars
['?'] = '?';
2961 operand_chars
['?'] = '?';
2963 digit_chars
['-'] = '-';
2964 mnemonic_chars
['_'] = '_';
2965 mnemonic_chars
['-'] = '-';
2966 mnemonic_chars
['.'] = '.';
2967 identifier_chars
['_'] = '_';
2968 identifier_chars
['.'] = '.';
2970 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2971 operand_chars
[(unsigned char) *p
] = *p
;
2974 if (flag_code
== CODE_64BIT
)
2976 #if defined (OBJ_COFF) && defined (TE_PE)
2977 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2980 x86_dwarf2_return_column
= 16;
2982 x86_cie_data_alignment
= -8;
2986 x86_dwarf2_return_column
= 8;
2987 x86_cie_data_alignment
= -4;
2992 i386_print_statistics (FILE *file
)
2994 hash_print_statistics (file
, "i386 opcode", op_hash
);
2995 hash_print_statistics (file
, "i386 register", reg_hash
);
3000 /* Debugging routines for md_assemble. */
3001 static void pte (insn_template
*);
3002 static void pt (i386_operand_type
);
3003 static void pe (expressionS
*);
3004 static void ps (symbolS
*);
3007 pi (char *line
, i386_insn
*x
)
3011 fprintf (stdout
, "%s: template ", line
);
3013 fprintf (stdout
, " address: base %s index %s scale %x\n",
3014 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3015 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3016 x
->log2_scale_factor
);
3017 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3018 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3019 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3020 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3021 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3022 (x
->rex
& REX_W
) != 0,
3023 (x
->rex
& REX_R
) != 0,
3024 (x
->rex
& REX_X
) != 0,
3025 (x
->rex
& REX_B
) != 0);
3026 for (j
= 0; j
< x
->operands
; j
++)
3028 fprintf (stdout
, " #%d: ", j
+ 1);
3030 fprintf (stdout
, "\n");
3031 if (x
->types
[j
].bitfield
.reg
3032 || x
->types
[j
].bitfield
.regmmx
3033 || x
->types
[j
].bitfield
.regsimd
3034 || x
->types
[j
].bitfield
.sreg2
3035 || x
->types
[j
].bitfield
.sreg3
3036 || x
->types
[j
].bitfield
.control
3037 || x
->types
[j
].bitfield
.debug
3038 || x
->types
[j
].bitfield
.test
)
3039 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3040 if (operand_type_check (x
->types
[j
], imm
))
3042 if (operand_type_check (x
->types
[j
], disp
))
3043 pe (x
->op
[j
].disps
);
3048 pte (insn_template
*t
)
3051 fprintf (stdout
, " %d operands ", t
->operands
);
3052 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3053 if (t
->extension_opcode
!= None
)
3054 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3055 if (t
->opcode_modifier
.d
)
3056 fprintf (stdout
, "D");
3057 if (t
->opcode_modifier
.w
)
3058 fprintf (stdout
, "W");
3059 fprintf (stdout
, "\n");
3060 for (j
= 0; j
< t
->operands
; j
++)
3062 fprintf (stdout
, " #%d type ", j
+ 1);
3063 pt (t
->operand_types
[j
]);
3064 fprintf (stdout
, "\n");
3071 fprintf (stdout
, " operation %d\n", e
->X_op
);
3072 fprintf (stdout
, " add_number %ld (%lx)\n",
3073 (long) e
->X_add_number
, (long) e
->X_add_number
);
3074 if (e
->X_add_symbol
)
3076 fprintf (stdout
, " add_symbol ");
3077 ps (e
->X_add_symbol
);
3078 fprintf (stdout
, "\n");
3082 fprintf (stdout
, " op_symbol ");
3083 ps (e
->X_op_symbol
);
3084 fprintf (stdout
, "\n");
3091 fprintf (stdout
, "%s type %s%s",
3093 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3094 segment_name (S_GET_SEGMENT (s
)));
3097 static struct type_name
3099 i386_operand_type mask
;
3102 const type_names
[] =
3104 { OPERAND_TYPE_REG8
, "r8" },
3105 { OPERAND_TYPE_REG16
, "r16" },
3106 { OPERAND_TYPE_REG32
, "r32" },
3107 { OPERAND_TYPE_REG64
, "r64" },
3108 { OPERAND_TYPE_IMM8
, "i8" },
3109 { OPERAND_TYPE_IMM8
, "i8s" },
3110 { OPERAND_TYPE_IMM16
, "i16" },
3111 { OPERAND_TYPE_IMM32
, "i32" },
3112 { OPERAND_TYPE_IMM32S
, "i32s" },
3113 { OPERAND_TYPE_IMM64
, "i64" },
3114 { OPERAND_TYPE_IMM1
, "i1" },
3115 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3116 { OPERAND_TYPE_DISP8
, "d8" },
3117 { OPERAND_TYPE_DISP16
, "d16" },
3118 { OPERAND_TYPE_DISP32
, "d32" },
3119 { OPERAND_TYPE_DISP32S
, "d32s" },
3120 { OPERAND_TYPE_DISP64
, "d64" },
3121 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3122 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3123 { OPERAND_TYPE_CONTROL
, "control reg" },
3124 { OPERAND_TYPE_TEST
, "test reg" },
3125 { OPERAND_TYPE_DEBUG
, "debug reg" },
3126 { OPERAND_TYPE_FLOATREG
, "FReg" },
3127 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3128 { OPERAND_TYPE_SREG2
, "SReg2" },
3129 { OPERAND_TYPE_SREG3
, "SReg3" },
3130 { OPERAND_TYPE_ACC
, "Acc" },
3131 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3132 { OPERAND_TYPE_REGMMX
, "rMMX" },
3133 { OPERAND_TYPE_REGXMM
, "rXMM" },
3134 { OPERAND_TYPE_REGYMM
, "rYMM" },
3135 { OPERAND_TYPE_REGZMM
, "rZMM" },
3136 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3137 { OPERAND_TYPE_ESSEG
, "es" },
3141 pt (i386_operand_type t
)
3144 i386_operand_type a
;
3146 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3148 a
= operand_type_and (t
, type_names
[j
].mask
);
3149 if (!operand_type_all_zero (&a
))
3150 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3155 #endif /* DEBUG386 */
3157 static bfd_reloc_code_real_type
3158 reloc (unsigned int size
,
3161 bfd_reloc_code_real_type other
)
3163 if (other
!= NO_RELOC
)
3165 reloc_howto_type
*rel
;
3170 case BFD_RELOC_X86_64_GOT32
:
3171 return BFD_RELOC_X86_64_GOT64
;
3173 case BFD_RELOC_X86_64_GOTPLT64
:
3174 return BFD_RELOC_X86_64_GOTPLT64
;
3176 case BFD_RELOC_X86_64_PLTOFF64
:
3177 return BFD_RELOC_X86_64_PLTOFF64
;
3179 case BFD_RELOC_X86_64_GOTPC32
:
3180 other
= BFD_RELOC_X86_64_GOTPC64
;
3182 case BFD_RELOC_X86_64_GOTPCREL
:
3183 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3185 case BFD_RELOC_X86_64_TPOFF32
:
3186 other
= BFD_RELOC_X86_64_TPOFF64
;
3188 case BFD_RELOC_X86_64_DTPOFF32
:
3189 other
= BFD_RELOC_X86_64_DTPOFF64
;
3195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3196 if (other
== BFD_RELOC_SIZE32
)
3199 other
= BFD_RELOC_SIZE64
;
3202 as_bad (_("there are no pc-relative size relocations"));
3208 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3209 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3212 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3214 as_bad (_("unknown relocation (%u)"), other
);
3215 else if (size
!= bfd_get_reloc_size (rel
))
3216 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3217 bfd_get_reloc_size (rel
),
3219 else if (pcrel
&& !rel
->pc_relative
)
3220 as_bad (_("non-pc-relative relocation for pc-relative field"));
3221 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3223 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3225 as_bad (_("relocated field and relocation type differ in signedness"));
3234 as_bad (_("there are no unsigned pc-relative relocations"));
3237 case 1: return BFD_RELOC_8_PCREL
;
3238 case 2: return BFD_RELOC_16_PCREL
;
3239 case 4: return BFD_RELOC_32_PCREL
;
3240 case 8: return BFD_RELOC_64_PCREL
;
3242 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3249 case 4: return BFD_RELOC_X86_64_32S
;
3254 case 1: return BFD_RELOC_8
;
3255 case 2: return BFD_RELOC_16
;
3256 case 4: return BFD_RELOC_32
;
3257 case 8: return BFD_RELOC_64
;
3259 as_bad (_("cannot do %s %u byte relocation"),
3260 sign
> 0 ? "signed" : "unsigned", size
);
3266 /* Here we decide which fixups can be adjusted to make them relative to
3267 the beginning of the section instead of the symbol. Basically we need
3268 to make sure that the dynamic relocations are done correctly, so in
3269 some cases we force the original symbol to be used. */
3272 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3278 /* Don't adjust pc-relative references to merge sections in 64-bit
3280 if (use_rela_relocations
3281 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3285 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3286 and changed later by validate_fix. */
3287 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3288 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3291 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3292 for size relocations. */
3293 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3294 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3295 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3296 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3297 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3298 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3299 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3300 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3301 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3302 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3309 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3310 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3311 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3312 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3324 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3325 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3332 intel_float_operand (const char *mnemonic
)
3334 /* Note that the value returned is meaningful only for opcodes with (memory)
3335 operands, hence the code here is free to improperly handle opcodes that
3336 have no operands (for better performance and smaller code). */
3338 if (mnemonic
[0] != 'f')
3339 return 0; /* non-math */
3341 switch (mnemonic
[1])
3343 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3344 the fs segment override prefix not currently handled because no
3345 call path can make opcodes without operands get here */
3347 return 2 /* integer op */;
3349 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3350 return 3; /* fldcw/fldenv */
3353 if (mnemonic
[2] != 'o' /* fnop */)
3354 return 3; /* non-waiting control op */
3357 if (mnemonic
[2] == 's')
3358 return 3; /* frstor/frstpm */
3361 if (mnemonic
[2] == 'a')
3362 return 3; /* fsave */
3363 if (mnemonic
[2] == 't')
3365 switch (mnemonic
[3])
3367 case 'c': /* fstcw */
3368 case 'd': /* fstdw */
3369 case 'e': /* fstenv */
3370 case 's': /* fsts[gw] */
3376 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3377 return 0; /* fxsave/fxrstor are not really math ops */
3384 /* Build the VEX prefix. */
3387 build_vex_prefix (const insn_template
*t
)
3389 unsigned int register_specifier
;
3390 unsigned int implied_prefix
;
3391 unsigned int vector_length
;
3394 /* Check register specifier. */
3395 if (i
.vex
.register_specifier
)
3397 register_specifier
=
3398 ~register_number (i
.vex
.register_specifier
) & 0xf;
3399 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3402 register_specifier
= 0xf;
3404 /* Use 2-byte VEX prefix by swapping destination and source operand
3405 if there are more than 1 register operand. */
3406 if (i
.reg_operands
> 1
3407 && i
.vec_encoding
!= vex_encoding_vex3
3408 && i
.dir_encoding
== dir_encoding_default
3409 && i
.operands
== i
.reg_operands
3410 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3411 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3412 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3415 unsigned int xchg
= i
.operands
- 1;
3416 union i386_op temp_op
;
3417 i386_operand_type temp_type
;
3419 temp_type
= i
.types
[xchg
];
3420 i
.types
[xchg
] = i
.types
[0];
3421 i
.types
[0] = temp_type
;
3422 temp_op
= i
.op
[xchg
];
3423 i
.op
[xchg
] = i
.op
[0];
3426 gas_assert (i
.rm
.mode
== 3);
3430 i
.rm
.regmem
= i
.rm
.reg
;
3433 if (i
.tm
.opcode_modifier
.d
)
3434 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3435 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3436 else /* Use the next insn. */
3440 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3441 vector_length
= avxscalar
;
3442 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3448 /* Determine vector length from the last multi-length vector
3451 for (op
= t
->operands
; op
--;)
3452 if (t
->operand_types
[op
].bitfield
.xmmword
3453 && t
->operand_types
[op
].bitfield
.ymmword
3454 && i
.types
[op
].bitfield
.ymmword
)
3461 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3466 case DATA_PREFIX_OPCODE
:
3469 case REPE_PREFIX_OPCODE
:
3472 case REPNE_PREFIX_OPCODE
:
3479 /* Check the REX.W bit and VEXW. */
3480 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3481 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3482 else if (i
.tm
.opcode_modifier
.vexw
)
3483 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3485 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3487 /* Use 2-byte VEX prefix if possible. */
3489 && i
.vec_encoding
!= vex_encoding_vex3
3490 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3491 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3493 /* 2-byte VEX prefix. */
3497 i
.vex
.bytes
[0] = 0xc5;
3499 /* Check the REX.R bit. */
3500 r
= (i
.rex
& REX_R
) ? 0 : 1;
3501 i
.vex
.bytes
[1] = (r
<< 7
3502 | register_specifier
<< 3
3503 | vector_length
<< 2
3508 /* 3-byte VEX prefix. */
3513 switch (i
.tm
.opcode_modifier
.vexopcode
)
3517 i
.vex
.bytes
[0] = 0xc4;
3521 i
.vex
.bytes
[0] = 0xc4;
3525 i
.vex
.bytes
[0] = 0xc4;
3529 i
.vex
.bytes
[0] = 0x8f;
3533 i
.vex
.bytes
[0] = 0x8f;
3537 i
.vex
.bytes
[0] = 0x8f;
3543 /* The high 3 bits of the second VEX byte are 1's compliment
3544 of RXB bits from REX. */
3545 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3547 i
.vex
.bytes
[2] = (w
<< 7
3548 | register_specifier
<< 3
3549 | vector_length
<< 2
3554 static INLINE bfd_boolean
3555 is_evex_encoding (const insn_template
*t
)
3557 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3558 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3559 || t
->opcode_modifier
.staticrounding
|| t
->opcode_modifier
.sae
;
3562 static INLINE bfd_boolean
3563 is_any_vex_encoding (const insn_template
*t
)
3565 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3566 || is_evex_encoding (t
);
3569 /* Build the EVEX prefix. */
3572 build_evex_prefix (void)
3574 unsigned int register_specifier
;
3575 unsigned int implied_prefix
;
3577 rex_byte vrex_used
= 0;
3579 /* Check register specifier. */
3580 if (i
.vex
.register_specifier
)
3582 gas_assert ((i
.vrex
& REX_X
) == 0);
3584 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3585 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3586 register_specifier
+= 8;
3587 /* The upper 16 registers are encoded in the fourth byte of the
3589 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3590 i
.vex
.bytes
[3] = 0x8;
3591 register_specifier
= ~register_specifier
& 0xf;
3595 register_specifier
= 0xf;
3597 /* Encode upper 16 vector index register in the fourth byte of
3599 if (!(i
.vrex
& REX_X
))
3600 i
.vex
.bytes
[3] = 0x8;
3605 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3610 case DATA_PREFIX_OPCODE
:
3613 case REPE_PREFIX_OPCODE
:
3616 case REPNE_PREFIX_OPCODE
:
3623 /* 4 byte EVEX prefix. */
3625 i
.vex
.bytes
[0] = 0x62;
3628 switch (i
.tm
.opcode_modifier
.vexopcode
)
3644 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3646 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3648 /* The fifth bit of the second EVEX byte is 1's compliment of the
3649 REX_R bit in VREX. */
3650 if (!(i
.vrex
& REX_R
))
3651 i
.vex
.bytes
[1] |= 0x10;
3655 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3657 /* When all operands are registers, the REX_X bit in REX is not
3658 used. We reuse it to encode the upper 16 registers, which is
3659 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3660 as 1's compliment. */
3661 if ((i
.vrex
& REX_B
))
3664 i
.vex
.bytes
[1] &= ~0x40;
3668 /* EVEX instructions shouldn't need the REX prefix. */
3669 i
.vrex
&= ~vrex_used
;
3670 gas_assert (i
.vrex
== 0);
3672 /* Check the REX.W bit and VEXW. */
3673 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3674 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3675 else if (i
.tm
.opcode_modifier
.vexw
)
3676 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3678 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3680 /* Encode the U bit. */
3681 implied_prefix
|= 0x4;
3683 /* The third byte of the EVEX prefix. */
3684 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3686 /* The fourth byte of the EVEX prefix. */
3687 /* The zeroing-masking bit. */
3688 if (i
.mask
&& i
.mask
->zeroing
)
3689 i
.vex
.bytes
[3] |= 0x80;
3691 /* Don't always set the broadcast bit if there is no RC. */
3694 /* Encode the vector length. */
3695 unsigned int vec_length
;
3697 if (!i
.tm
.opcode_modifier
.evex
3698 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3702 /* Determine vector length from the last multi-length vector
3705 for (op
= i
.operands
; op
--;)
3706 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3707 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3708 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3710 if (i
.types
[op
].bitfield
.zmmword
)
3712 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3715 else if (i
.types
[op
].bitfield
.ymmword
)
3717 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3720 else if (i
.types
[op
].bitfield
.xmmword
)
3722 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3725 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3727 switch (i
.broadcast
->bytes
)
3730 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3733 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3736 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3745 if (op
>= MAX_OPERANDS
)
3749 switch (i
.tm
.opcode_modifier
.evex
)
3751 case EVEXLIG
: /* LL' is ignored */
3752 vec_length
= evexlig
<< 5;
3755 vec_length
= 0 << 5;
3758 vec_length
= 1 << 5;
3761 vec_length
= 2 << 5;
3767 i
.vex
.bytes
[3] |= vec_length
;
3768 /* Encode the broadcast bit. */
3770 i
.vex
.bytes
[3] |= 0x10;
3774 if (i
.rounding
->type
!= saeonly
)
3775 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3777 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3780 if (i
.mask
&& i
.mask
->mask
)
3781 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3785 process_immext (void)
3789 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3792 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3793 with an opcode suffix which is coded in the same place as an
3794 8-bit immediate field would be.
3795 Here we check those operands and remove them afterwards. */
3798 for (x
= 0; x
< i
.operands
; x
++)
3799 if (register_number (i
.op
[x
].regs
) != x
)
3800 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3801 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3807 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3809 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3810 suffix which is coded in the same place as an 8-bit immediate
3812 Here we check those operands and remove them afterwards. */
3815 if (i
.operands
!= 3)
3818 for (x
= 0; x
< 2; x
++)
3819 if (register_number (i
.op
[x
].regs
) != x
)
3820 goto bad_register_operand
;
3822 /* Check for third operand for mwaitx/monitorx insn. */
3823 if (register_number (i
.op
[x
].regs
)
3824 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3826 bad_register_operand
:
3827 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3828 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3835 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3836 which is coded in the same place as an 8-bit immediate field
3837 would be. Here we fake an 8-bit immediate operand from the
3838 opcode suffix stored in tm.extension_opcode.
3840 AVX instructions also use this encoding, for some of
3841 3 argument instructions. */
3843 gas_assert (i
.imm_operands
<= 1
3845 || (is_any_vex_encoding (&i
.tm
)
3846 && i
.operands
<= 4)));
3848 exp
= &im_expressions
[i
.imm_operands
++];
3849 i
.op
[i
.operands
].imms
= exp
;
3850 i
.types
[i
.operands
] = imm8
;
3852 exp
->X_op
= O_constant
;
3853 exp
->X_add_number
= i
.tm
.extension_opcode
;
3854 i
.tm
.extension_opcode
= None
;
3861 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3866 as_bad (_("invalid instruction `%s' after `%s'"),
3867 i
.tm
.name
, i
.hle_prefix
);
3870 if (i
.prefix
[LOCK_PREFIX
])
3872 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3876 case HLEPrefixRelease
:
3877 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3879 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3883 if (i
.mem_operands
== 0
3884 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3886 as_bad (_("memory destination needed for instruction `%s'"
3887 " after `xrelease'"), i
.tm
.name
);
3894 /* Try the shortest encoding by shortening operand size. */
3897 optimize_encoding (void)
3901 if (optimize_for_space
3902 && i
.reg_operands
== 1
3903 && i
.imm_operands
== 1
3904 && !i
.types
[1].bitfield
.byte
3905 && i
.op
[0].imms
->X_op
== O_constant
3906 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3907 && ((i
.tm
.base_opcode
== 0xa8
3908 && i
.tm
.extension_opcode
== None
)
3909 || (i
.tm
.base_opcode
== 0xf6
3910 && i
.tm
.extension_opcode
== 0x0)))
3913 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3915 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3916 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3918 i
.types
[1].bitfield
.byte
= 1;
3919 /* Ignore the suffix. */
3921 if (base_regnum
>= 4
3922 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3924 /* Handle SP, BP, SI and DI registers. */
3925 if (i
.types
[1].bitfield
.word
)
3927 else if (i
.types
[1].bitfield
.dword
)
3935 else if (flag_code
== CODE_64BIT
3936 && ((i
.types
[1].bitfield
.qword
3937 && i
.reg_operands
== 1
3938 && i
.imm_operands
== 1
3939 && i
.op
[0].imms
->X_op
== O_constant
3940 && ((i
.tm
.base_opcode
== 0xb0
3941 && i
.tm
.extension_opcode
== None
3942 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3943 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3944 && (((i
.tm
.base_opcode
== 0x24
3945 || i
.tm
.base_opcode
== 0xa8)
3946 && i
.tm
.extension_opcode
== None
)
3947 || (i
.tm
.base_opcode
== 0x80
3948 && i
.tm
.extension_opcode
== 0x4)
3949 || ((i
.tm
.base_opcode
== 0xf6
3950 || i
.tm
.base_opcode
== 0xc6)
3951 && i
.tm
.extension_opcode
== 0x0)))
3952 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3953 && i
.tm
.base_opcode
== 0x83
3954 && i
.tm
.extension_opcode
== 0x4)))
3955 || (i
.types
[0].bitfield
.qword
3956 && ((i
.reg_operands
== 2
3957 && i
.op
[0].regs
== i
.op
[1].regs
3958 && ((i
.tm
.base_opcode
== 0x30
3959 || i
.tm
.base_opcode
== 0x28)
3960 && i
.tm
.extension_opcode
== None
))
3961 || (i
.reg_operands
== 1
3963 && i
.tm
.base_opcode
== 0x30
3964 && i
.tm
.extension_opcode
== None
)))))
3967 andq $imm31, %r64 -> andl $imm31, %r32
3968 andq $imm7, %r64 -> andl $imm7, %r32
3969 testq $imm31, %r64 -> testl $imm31, %r32
3970 xorq %r64, %r64 -> xorl %r32, %r32
3971 subq %r64, %r64 -> subl %r32, %r32
3972 movq $imm31, %r64 -> movl $imm31, %r32
3973 movq $imm32, %r64 -> movl $imm32, %r32
3975 i
.tm
.opcode_modifier
.norex64
= 1;
3976 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3979 movq $imm31, %r64 -> movl $imm31, %r32
3980 movq $imm32, %r64 -> movl $imm32, %r32
3982 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3983 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3984 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3985 i
.types
[0].bitfield
.imm32
= 1;
3986 i
.types
[0].bitfield
.imm32s
= 0;
3987 i
.types
[0].bitfield
.imm64
= 0;
3988 i
.types
[1].bitfield
.dword
= 1;
3989 i
.types
[1].bitfield
.qword
= 0;
3990 if (i
.tm
.base_opcode
== 0xc6)
3993 movq $imm31, %r64 -> movl $imm31, %r32
3995 i
.tm
.base_opcode
= 0xb0;
3996 i
.tm
.extension_opcode
= None
;
3997 i
.tm
.opcode_modifier
.shortform
= 1;
3998 i
.tm
.opcode_modifier
.modrm
= 0;
4002 else if (i
.reg_operands
== 3
4003 && i
.op
[0].regs
== i
.op
[1].regs
4004 && !i
.types
[2].bitfield
.xmmword
4005 && (i
.tm
.opcode_modifier
.vex
4006 || ((!i
.mask
|| i
.mask
->zeroing
)
4008 && is_evex_encoding (&i
.tm
)
4009 && (i
.vec_encoding
!= vex_encoding_evex
4010 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4011 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4012 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4013 && i
.types
[2].bitfield
.ymmword
))))
4014 && ((i
.tm
.base_opcode
== 0x55
4015 || i
.tm
.base_opcode
== 0x6655
4016 || i
.tm
.base_opcode
== 0x66df
4017 || i
.tm
.base_opcode
== 0x57
4018 || i
.tm
.base_opcode
== 0x6657
4019 || i
.tm
.base_opcode
== 0x66ef
4020 || i
.tm
.base_opcode
== 0x66f8
4021 || i
.tm
.base_opcode
== 0x66f9
4022 || i
.tm
.base_opcode
== 0x66fa
4023 || i
.tm
.base_opcode
== 0x66fb
4024 || i
.tm
.base_opcode
== 0x42
4025 || i
.tm
.base_opcode
== 0x6642
4026 || i
.tm
.base_opcode
== 0x47
4027 || i
.tm
.base_opcode
== 0x6647)
4028 && i
.tm
.extension_opcode
== None
))
4031 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4033 EVEX VOP %zmmM, %zmmM, %zmmN
4034 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4035 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4036 EVEX VOP %ymmM, %ymmM, %ymmN
4037 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4038 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4039 VEX VOP %ymmM, %ymmM, %ymmN
4040 -> VEX VOP %xmmM, %xmmM, %xmmN
4041 VOP, one of vpandn and vpxor:
4042 VEX VOP %ymmM, %ymmM, %ymmN
4043 -> VEX VOP %xmmM, %xmmM, %xmmN
4044 VOP, one of vpandnd and vpandnq:
4045 EVEX VOP %zmmM, %zmmM, %zmmN
4046 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4047 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4048 EVEX VOP %ymmM, %ymmM, %ymmN
4049 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4050 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4051 VOP, one of vpxord and vpxorq:
4052 EVEX VOP %zmmM, %zmmM, %zmmN
4053 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4054 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4055 EVEX VOP %ymmM, %ymmM, %ymmN
4056 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4057 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4058 VOP, one of kxord and kxorq:
4059 VEX VOP %kM, %kM, %kN
4060 -> VEX kxorw %kM, %kM, %kN
4061 VOP, one of kandnd and kandnq:
4062 VEX VOP %kM, %kM, %kN
4063 -> VEX kandnw %kM, %kM, %kN
4065 if (is_evex_encoding (&i
.tm
))
4067 if (i
.vec_encoding
!= vex_encoding_evex
)
4069 i
.tm
.opcode_modifier
.vex
= VEX128
;
4070 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4071 i
.tm
.opcode_modifier
.evex
= 0;
4073 else if (optimize
> 1)
4074 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4078 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4080 i
.tm
.base_opcode
&= 0xff;
4081 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4084 i
.tm
.opcode_modifier
.vex
= VEX128
;
4086 if (i
.tm
.opcode_modifier
.vex
)
4087 for (j
= 0; j
< 3; j
++)
4089 i
.types
[j
].bitfield
.xmmword
= 1;
4090 i
.types
[j
].bitfield
.ymmword
= 0;
4093 else if (i
.vec_encoding
!= vex_encoding_evex
4094 && !i
.types
[0].bitfield
.zmmword
4095 && !i
.types
[1].bitfield
.zmmword
4097 && is_evex_encoding (&i
.tm
)
4098 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4099 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4100 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4101 && i
.tm
.extension_opcode
== None
)
4104 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4105 vmovdqu32 and vmovdqu64:
4106 EVEX VOP %xmmM, %xmmN
4107 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4108 EVEX VOP %ymmM, %ymmN
4109 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4111 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4113 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4115 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4117 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4119 for (j
= 0; j
< 2; j
++)
4120 if (operand_type_check (i
.types
[j
], disp
)
4121 && i
.op
[j
].disps
->X_op
== O_constant
)
4123 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4124 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4125 bytes, we choose EVEX Disp8 over VEX Disp32. */
4126 int evex_disp8
, vex_disp8
;
4127 unsigned int memshift
= i
.memshift
;
4128 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4130 evex_disp8
= fits_in_disp8 (n
);
4132 vex_disp8
= fits_in_disp8 (n
);
4133 if (evex_disp8
!= vex_disp8
)
4135 i
.memshift
= memshift
;
4139 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4142 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4143 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4144 i
.tm
.opcode_modifier
.vex
4145 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4146 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4147 i
.tm
.opcode_modifier
.evex
= 0;
4148 i
.tm
.opcode_modifier
.masking
= 0;
4149 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4151 for (j
= 0; j
< 2; j
++)
4152 if (operand_type_check (i
.types
[j
], disp
)
4153 && i
.op
[j
].disps
->X_op
== O_constant
)
4155 i
.types
[j
].bitfield
.disp8
4156 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4162 /* This is the guts of the machine-dependent assembler. LINE points to a
4163 machine dependent instruction. This function is supposed to emit
4164 the frags/bytes it assembles to. */
4167 md_assemble (char *line
)
4170 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4171 const insn_template
*t
;
4173 /* Initialize globals. */
4174 memset (&i
, '\0', sizeof (i
));
4175 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4176 i
.reloc
[j
] = NO_RELOC
;
4177 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4178 memset (im_expressions
, '\0', sizeof (im_expressions
));
4179 save_stack_p
= save_stack
;
4181 /* First parse an instruction mnemonic & call i386_operand for the operands.
4182 We assume that the scrubber has arranged it so that line[0] is the valid
4183 start of a (possibly prefixed) mnemonic. */
4185 line
= parse_insn (line
, mnemonic
);
4188 mnem_suffix
= i
.suffix
;
4190 line
= parse_operands (line
, mnemonic
);
4192 xfree (i
.memop1_string
);
4193 i
.memop1_string
= NULL
;
4197 /* Now we've parsed the mnemonic into a set of templates, and have the
4198 operands at hand. */
4200 /* All intel opcodes have reversed operands except for "bound" and
4201 "enter". We also don't reverse intersegment "jmp" and "call"
4202 instructions with 2 immediate operands so that the immediate segment
4203 precedes the offset, as it does when in AT&T mode. */
4206 && (strcmp (mnemonic
, "bound") != 0)
4207 && (strcmp (mnemonic
, "invlpga") != 0)
4208 && !(operand_type_check (i
.types
[0], imm
)
4209 && operand_type_check (i
.types
[1], imm
)))
4212 /* The order of the immediates should be reversed
4213 for 2 immediates extrq and insertq instructions */
4214 if (i
.imm_operands
== 2
4215 && (strcmp (mnemonic
, "extrq") == 0
4216 || strcmp (mnemonic
, "insertq") == 0))
4217 swap_2_operands (0, 1);
4222 /* Don't optimize displacement for movabs since it only takes 64bit
4225 && i
.disp_encoding
!= disp_encoding_32bit
4226 && (flag_code
!= CODE_64BIT
4227 || strcmp (mnemonic
, "movabs") != 0))
4230 /* Next, we find a template that matches the given insn,
4231 making sure the overlap of the given operands types is consistent
4232 with the template operand types. */
4234 if (!(t
= match_template (mnem_suffix
)))
4237 if (sse_check
!= check_none
4238 && !i
.tm
.opcode_modifier
.noavx
4239 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4240 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4241 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4242 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4243 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4244 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4245 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4246 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4247 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4248 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4250 (sse_check
== check_warning
4252 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4255 /* Zap movzx and movsx suffix. The suffix has been set from
4256 "word ptr" or "byte ptr" on the source operand in Intel syntax
4257 or extracted from mnemonic in AT&T syntax. But we'll use
4258 the destination register to choose the suffix for encoding. */
4259 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4261 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4262 there is no suffix, the default will be byte extension. */
4263 if (i
.reg_operands
!= 2
4266 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4271 if (i
.tm
.opcode_modifier
.fwait
)
4272 if (!add_prefix (FWAIT_OPCODE
))
4275 /* Check if REP prefix is OK. */
4276 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4278 as_bad (_("invalid instruction `%s' after `%s'"),
4279 i
.tm
.name
, i
.rep_prefix
);
4283 /* Check for lock without a lockable instruction. Destination operand
4284 must be memory unless it is xchg (0x86). */
4285 if (i
.prefix
[LOCK_PREFIX
]
4286 && (!i
.tm
.opcode_modifier
.islockable
4287 || i
.mem_operands
== 0
4288 || (i
.tm
.base_opcode
!= 0x86
4289 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4291 as_bad (_("expecting lockable instruction after `lock'"));
4295 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4296 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4298 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4302 /* Check if HLE prefix is OK. */
4303 if (i
.hle_prefix
&& !check_hle ())
4306 /* Check BND prefix. */
4307 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4308 as_bad (_("expecting valid branch instruction after `bnd'"));
4310 /* Check NOTRACK prefix. */
4311 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4312 as_bad (_("expecting indirect branch instruction after `notrack'"));
4314 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4316 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4317 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4318 else if (flag_code
!= CODE_16BIT
4319 ? i
.prefix
[ADDR_PREFIX
]
4320 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4321 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4324 /* Insert BND prefix. */
4325 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4327 if (!i
.prefix
[BND_PREFIX
])
4328 add_prefix (BND_PREFIX_OPCODE
);
4329 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4331 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4332 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4336 /* Check string instruction segment overrides. */
4337 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4339 if (!check_string ())
4341 i
.disp_operands
= 0;
4344 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4345 optimize_encoding ();
4347 if (!process_suffix ())
4350 /* Update operand types. */
4351 for (j
= 0; j
< i
.operands
; j
++)
4352 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4354 /* Make still unresolved immediate matches conform to size of immediate
4355 given in i.suffix. */
4356 if (!finalize_imm ())
4359 if (i
.types
[0].bitfield
.imm1
)
4360 i
.imm_operands
= 0; /* kludge for shift insns. */
4362 /* We only need to check those implicit registers for instructions
4363 with 3 operands or less. */
4364 if (i
.operands
<= 3)
4365 for (j
= 0; j
< i
.operands
; j
++)
4366 if (i
.types
[j
].bitfield
.inoutportreg
4367 || i
.types
[j
].bitfield
.shiftcount
4368 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4371 /* ImmExt should be processed after SSE2AVX. */
4372 if (!i
.tm
.opcode_modifier
.sse2avx
4373 && i
.tm
.opcode_modifier
.immext
)
4376 /* For insns with operands there are more diddles to do to the opcode. */
4379 if (!process_operands ())
4382 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4384 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4385 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4388 if (is_any_vex_encoding (&i
.tm
))
4390 if (flag_code
== CODE_16BIT
)
4392 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4397 if (i
.tm
.opcode_modifier
.vex
)
4398 build_vex_prefix (t
);
4400 build_evex_prefix ();
4403 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4404 instructions may define INT_OPCODE as well, so avoid this corner
4405 case for those instructions that use MODRM. */
4406 if (i
.tm
.base_opcode
== INT_OPCODE
4407 && !i
.tm
.opcode_modifier
.modrm
4408 && i
.op
[0].imms
->X_add_number
== 3)
4410 i
.tm
.base_opcode
= INT3_OPCODE
;
4414 if ((i
.tm
.opcode_modifier
.jump
4415 || i
.tm
.opcode_modifier
.jumpbyte
4416 || i
.tm
.opcode_modifier
.jumpdword
)
4417 && i
.op
[0].disps
->X_op
== O_constant
)
4419 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4420 the absolute address given by the constant. Since ix86 jumps and
4421 calls are pc relative, we need to generate a reloc. */
4422 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4423 i
.op
[0].disps
->X_op
= O_symbol
;
4426 if (i
.tm
.opcode_modifier
.rex64
)
4429 /* For 8 bit registers we need an empty rex prefix. Also if the
4430 instruction already has a prefix, we need to convert old
4431 registers to new ones. */
4433 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4434 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4435 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4436 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4437 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4438 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4443 i
.rex
|= REX_OPCODE
;
4444 for (x
= 0; x
< 2; x
++)
4446 /* Look for 8 bit operand that uses old registers. */
4447 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4448 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4450 /* In case it is "hi" register, give up. */
4451 if (i
.op
[x
].regs
->reg_num
> 3)
4452 as_bad (_("can't encode register '%s%s' in an "
4453 "instruction requiring REX prefix."),
4454 register_prefix
, i
.op
[x
].regs
->reg_name
);
4456 /* Otherwise it is equivalent to the extended register.
4457 Since the encoding doesn't change this is merely
4458 cosmetic cleanup for debug output. */
4460 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4465 if (i
.rex
== 0 && i
.rex_encoding
)
4467 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4468 that uses legacy register. If it is "hi" register, don't add
4469 the REX_OPCODE byte. */
4471 for (x
= 0; x
< 2; x
++)
4472 if (i
.types
[x
].bitfield
.reg
4473 && i
.types
[x
].bitfield
.byte
4474 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4475 && i
.op
[x
].regs
->reg_num
> 3)
4477 i
.rex_encoding
= FALSE
;
4486 add_prefix (REX_OPCODE
| i
.rex
);
4488 /* We are ready to output the insn. */
4493 parse_insn (char *line
, char *mnemonic
)
4496 char *token_start
= l
;
4499 const insn_template
*t
;
4505 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4510 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4512 as_bad (_("no such instruction: `%s'"), token_start
);
4517 if (!is_space_char (*l
)
4518 && *l
!= END_OF_INSN
4520 || (*l
!= PREFIX_SEPARATOR
4523 as_bad (_("invalid character %s in mnemonic"),
4524 output_invalid (*l
));
4527 if (token_start
== l
)
4529 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4530 as_bad (_("expecting prefix; got nothing"));
4532 as_bad (_("expecting mnemonic; got nothing"));
4536 /* Look up instruction (or prefix) via hash table. */
4537 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4539 if (*l
!= END_OF_INSN
4540 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4541 && current_templates
4542 && current_templates
->start
->opcode_modifier
.isprefix
)
4544 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4546 as_bad ((flag_code
!= CODE_64BIT
4547 ? _("`%s' is only supported in 64-bit mode")
4548 : _("`%s' is not supported in 64-bit mode")),
4549 current_templates
->start
->name
);
4552 /* If we are in 16-bit mode, do not allow addr16 or data16.
4553 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4554 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4555 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4556 && flag_code
!= CODE_64BIT
4557 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4558 ^ (flag_code
== CODE_16BIT
)))
4560 as_bad (_("redundant %s prefix"),
4561 current_templates
->start
->name
);
4564 if (current_templates
->start
->opcode_length
== 0)
4566 /* Handle pseudo prefixes. */
4567 switch (current_templates
->start
->base_opcode
)
4571 i
.disp_encoding
= disp_encoding_8bit
;
4575 i
.disp_encoding
= disp_encoding_32bit
;
4579 i
.dir_encoding
= dir_encoding_load
;
4583 i
.dir_encoding
= dir_encoding_store
;
4587 i
.vec_encoding
= vex_encoding_vex2
;
4591 i
.vec_encoding
= vex_encoding_vex3
;
4595 i
.vec_encoding
= vex_encoding_evex
;
4599 i
.rex_encoding
= TRUE
;
4603 i
.no_optimize
= TRUE
;
4611 /* Add prefix, checking for repeated prefixes. */
4612 switch (add_prefix (current_templates
->start
->base_opcode
))
4617 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4618 i
.notrack_prefix
= current_templates
->start
->name
;
4621 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4622 i
.hle_prefix
= current_templates
->start
->name
;
4623 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4624 i
.bnd_prefix
= current_templates
->start
->name
;
4626 i
.rep_prefix
= current_templates
->start
->name
;
4632 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4639 if (!current_templates
)
4641 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4642 Check if we should swap operand or force 32bit displacement in
4644 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4645 i
.dir_encoding
= dir_encoding_swap
;
4646 else if (mnem_p
- 3 == dot_p
4649 i
.disp_encoding
= disp_encoding_8bit
;
4650 else if (mnem_p
- 4 == dot_p
4654 i
.disp_encoding
= disp_encoding_32bit
;
4659 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4662 if (!current_templates
)
4665 if (mnem_p
> mnemonic
)
4667 /* See if we can get a match by trimming off a suffix. */
4670 case WORD_MNEM_SUFFIX
:
4671 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4672 i
.suffix
= SHORT_MNEM_SUFFIX
;
4675 case BYTE_MNEM_SUFFIX
:
4676 case QWORD_MNEM_SUFFIX
:
4677 i
.suffix
= mnem_p
[-1];
4679 current_templates
= (const templates
*) hash_find (op_hash
,
4682 case SHORT_MNEM_SUFFIX
:
4683 case LONG_MNEM_SUFFIX
:
4686 i
.suffix
= mnem_p
[-1];
4688 current_templates
= (const templates
*) hash_find (op_hash
,
4697 if (intel_float_operand (mnemonic
) == 1)
4698 i
.suffix
= SHORT_MNEM_SUFFIX
;
4700 i
.suffix
= LONG_MNEM_SUFFIX
;
4702 current_templates
= (const templates
*) hash_find (op_hash
,
4709 if (!current_templates
)
4711 as_bad (_("no such instruction: `%s'"), token_start
);
4716 if (current_templates
->start
->opcode_modifier
.jump
4717 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4719 /* Check for a branch hint. We allow ",pt" and ",pn" for
4720 predict taken and predict not taken respectively.
4721 I'm not sure that branch hints actually do anything on loop
4722 and jcxz insns (JumpByte) for current Pentium4 chips. They
4723 may work in the future and it doesn't hurt to accept them
4725 if (l
[0] == ',' && l
[1] == 'p')
4729 if (!add_prefix (DS_PREFIX_OPCODE
))
4733 else if (l
[2] == 'n')
4735 if (!add_prefix (CS_PREFIX_OPCODE
))
4741 /* Any other comma loses. */
4744 as_bad (_("invalid character %s in mnemonic"),
4745 output_invalid (*l
));
4749 /* Check if instruction is supported on specified architecture. */
4751 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4753 supported
|= cpu_flags_match (t
);
4754 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4756 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4757 as_warn (_("use .code16 to ensure correct addressing mode"));
4763 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4764 as_bad (flag_code
== CODE_64BIT
4765 ? _("`%s' is not supported in 64-bit mode")
4766 : _("`%s' is only supported in 64-bit mode"),
4767 current_templates
->start
->name
);
4769 as_bad (_("`%s' is not supported on `%s%s'"),
4770 current_templates
->start
->name
,
4771 cpu_arch_name
? cpu_arch_name
: default_arch
,
4772 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4778 parse_operands (char *l
, const char *mnemonic
)
4782 /* 1 if operand is pending after ','. */
4783 unsigned int expecting_operand
= 0;
4785 /* Non-zero if operand parens not balanced. */
4786 unsigned int paren_not_balanced
;
4788 while (*l
!= END_OF_INSN
)
4790 /* Skip optional white space before operand. */
4791 if (is_space_char (*l
))
4793 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4795 as_bad (_("invalid character %s before operand %d"),
4796 output_invalid (*l
),
4800 token_start
= l
; /* After white space. */
4801 paren_not_balanced
= 0;
4802 while (paren_not_balanced
|| *l
!= ',')
4804 if (*l
== END_OF_INSN
)
4806 if (paren_not_balanced
)
4809 as_bad (_("unbalanced parenthesis in operand %d."),
4812 as_bad (_("unbalanced brackets in operand %d."),
4817 break; /* we are done */
4819 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4821 as_bad (_("invalid character %s in operand %d"),
4822 output_invalid (*l
),
4829 ++paren_not_balanced
;
4831 --paren_not_balanced
;
4836 ++paren_not_balanced
;
4838 --paren_not_balanced
;
4842 if (l
!= token_start
)
4843 { /* Yes, we've read in another operand. */
4844 unsigned int operand_ok
;
4845 this_operand
= i
.operands
++;
4846 if (i
.operands
> MAX_OPERANDS
)
4848 as_bad (_("spurious operands; (%d operands/instruction max)"),
4852 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4853 /* Now parse operand adding info to 'i' as we go along. */
4854 END_STRING_AND_SAVE (l
);
4856 if (i
.mem_operands
> 1)
4858 as_bad (_("too many memory references for `%s'"),
4865 i386_intel_operand (token_start
,
4866 intel_float_operand (mnemonic
));
4868 operand_ok
= i386_att_operand (token_start
);
4870 RESTORE_END_STRING (l
);
4876 if (expecting_operand
)
4878 expecting_operand_after_comma
:
4879 as_bad (_("expecting operand after ','; got nothing"));
4884 as_bad (_("expecting operand before ','; got nothing"));
4889 /* Now *l must be either ',' or END_OF_INSN. */
4892 if (*++l
== END_OF_INSN
)
4894 /* Just skip it, if it's \n complain. */
4895 goto expecting_operand_after_comma
;
4897 expecting_operand
= 1;
4904 swap_2_operands (int xchg1
, int xchg2
)
4906 union i386_op temp_op
;
4907 i386_operand_type temp_type
;
4908 unsigned int temp_flags
;
4909 enum bfd_reloc_code_real temp_reloc
;
4911 temp_type
= i
.types
[xchg2
];
4912 i
.types
[xchg2
] = i
.types
[xchg1
];
4913 i
.types
[xchg1
] = temp_type
;
4915 temp_flags
= i
.flags
[xchg2
];
4916 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4917 i
.flags
[xchg1
] = temp_flags
;
4919 temp_op
= i
.op
[xchg2
];
4920 i
.op
[xchg2
] = i
.op
[xchg1
];
4921 i
.op
[xchg1
] = temp_op
;
4923 temp_reloc
= i
.reloc
[xchg2
];
4924 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4925 i
.reloc
[xchg1
] = temp_reloc
;
4929 if (i
.mask
->operand
== xchg1
)
4930 i
.mask
->operand
= xchg2
;
4931 else if (i
.mask
->operand
== xchg2
)
4932 i
.mask
->operand
= xchg1
;
4936 if (i
.broadcast
->operand
== xchg1
)
4937 i
.broadcast
->operand
= xchg2
;
4938 else if (i
.broadcast
->operand
== xchg2
)
4939 i
.broadcast
->operand
= xchg1
;
4943 if (i
.rounding
->operand
== xchg1
)
4944 i
.rounding
->operand
= xchg2
;
4945 else if (i
.rounding
->operand
== xchg2
)
4946 i
.rounding
->operand
= xchg1
;
4951 swap_operands (void)
4957 swap_2_operands (1, i
.operands
- 2);
4961 swap_2_operands (0, i
.operands
- 1);
4967 if (i
.mem_operands
== 2)
4969 const seg_entry
*temp_seg
;
4970 temp_seg
= i
.seg
[0];
4971 i
.seg
[0] = i
.seg
[1];
4972 i
.seg
[1] = temp_seg
;
4976 /* Try to ensure constant immediates are represented in the smallest
4981 char guess_suffix
= 0;
4985 guess_suffix
= i
.suffix
;
4986 else if (i
.reg_operands
)
4988 /* Figure out a suffix from the last register operand specified.
4989 We can't do this properly yet, ie. excluding InOutPortReg,
4990 but the following works for instructions with immediates.
4991 In any case, we can't set i.suffix yet. */
4992 for (op
= i
.operands
; --op
>= 0;)
4993 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4995 guess_suffix
= BYTE_MNEM_SUFFIX
;
4998 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5000 guess_suffix
= WORD_MNEM_SUFFIX
;
5003 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5005 guess_suffix
= LONG_MNEM_SUFFIX
;
5008 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5010 guess_suffix
= QWORD_MNEM_SUFFIX
;
5014 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5015 guess_suffix
= WORD_MNEM_SUFFIX
;
5017 for (op
= i
.operands
; --op
>= 0;)
5018 if (operand_type_check (i
.types
[op
], imm
))
5020 switch (i
.op
[op
].imms
->X_op
)
5023 /* If a suffix is given, this operand may be shortened. */
5024 switch (guess_suffix
)
5026 case LONG_MNEM_SUFFIX
:
5027 i
.types
[op
].bitfield
.imm32
= 1;
5028 i
.types
[op
].bitfield
.imm64
= 1;
5030 case WORD_MNEM_SUFFIX
:
5031 i
.types
[op
].bitfield
.imm16
= 1;
5032 i
.types
[op
].bitfield
.imm32
= 1;
5033 i
.types
[op
].bitfield
.imm32s
= 1;
5034 i
.types
[op
].bitfield
.imm64
= 1;
5036 case BYTE_MNEM_SUFFIX
:
5037 i
.types
[op
].bitfield
.imm8
= 1;
5038 i
.types
[op
].bitfield
.imm8s
= 1;
5039 i
.types
[op
].bitfield
.imm16
= 1;
5040 i
.types
[op
].bitfield
.imm32
= 1;
5041 i
.types
[op
].bitfield
.imm32s
= 1;
5042 i
.types
[op
].bitfield
.imm64
= 1;
5046 /* If this operand is at most 16 bits, convert it
5047 to a signed 16 bit number before trying to see
5048 whether it will fit in an even smaller size.
5049 This allows a 16-bit operand such as $0xffe0 to
5050 be recognised as within Imm8S range. */
5051 if ((i
.types
[op
].bitfield
.imm16
)
5052 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5054 i
.op
[op
].imms
->X_add_number
=
5055 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5058 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5059 if ((i
.types
[op
].bitfield
.imm32
)
5060 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5063 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5064 ^ ((offsetT
) 1 << 31))
5065 - ((offsetT
) 1 << 31));
5069 = operand_type_or (i
.types
[op
],
5070 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5072 /* We must avoid matching of Imm32 templates when 64bit
5073 only immediate is available. */
5074 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5075 i
.types
[op
].bitfield
.imm32
= 0;
5082 /* Symbols and expressions. */
5084 /* Convert symbolic operand to proper sizes for matching, but don't
5085 prevent matching a set of insns that only supports sizes other
5086 than those matching the insn suffix. */
5088 i386_operand_type mask
, allowed
;
5089 const insn_template
*t
;
5091 operand_type_set (&mask
, 0);
5092 operand_type_set (&allowed
, 0);
5094 for (t
= current_templates
->start
;
5095 t
< current_templates
->end
;
5097 allowed
= operand_type_or (allowed
,
5098 t
->operand_types
[op
]);
5099 switch (guess_suffix
)
5101 case QWORD_MNEM_SUFFIX
:
5102 mask
.bitfield
.imm64
= 1;
5103 mask
.bitfield
.imm32s
= 1;
5105 case LONG_MNEM_SUFFIX
:
5106 mask
.bitfield
.imm32
= 1;
5108 case WORD_MNEM_SUFFIX
:
5109 mask
.bitfield
.imm16
= 1;
5111 case BYTE_MNEM_SUFFIX
:
5112 mask
.bitfield
.imm8
= 1;
5117 allowed
= operand_type_and (mask
, allowed
);
5118 if (!operand_type_all_zero (&allowed
))
5119 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5126 /* Try to use the smallest displacement type too. */
5128 optimize_disp (void)
5132 for (op
= i
.operands
; --op
>= 0;)
5133 if (operand_type_check (i
.types
[op
], disp
))
5135 if (i
.op
[op
].disps
->X_op
== O_constant
)
5137 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5139 if (i
.types
[op
].bitfield
.disp16
5140 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5142 /* If this operand is at most 16 bits, convert
5143 to a signed 16 bit number and don't use 64bit
5145 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5146 i
.types
[op
].bitfield
.disp64
= 0;
5149 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5150 if (i
.types
[op
].bitfield
.disp32
5151 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5153 /* If this operand is at most 32 bits, convert
5154 to a signed 32 bit number and don't use 64bit
5156 op_disp
&= (((offsetT
) 2 << 31) - 1);
5157 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5158 i
.types
[op
].bitfield
.disp64
= 0;
5161 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5163 i
.types
[op
].bitfield
.disp8
= 0;
5164 i
.types
[op
].bitfield
.disp16
= 0;
5165 i
.types
[op
].bitfield
.disp32
= 0;
5166 i
.types
[op
].bitfield
.disp32s
= 0;
5167 i
.types
[op
].bitfield
.disp64
= 0;
5171 else if (flag_code
== CODE_64BIT
)
5173 if (fits_in_signed_long (op_disp
))
5175 i
.types
[op
].bitfield
.disp64
= 0;
5176 i
.types
[op
].bitfield
.disp32s
= 1;
5178 if (i
.prefix
[ADDR_PREFIX
]
5179 && fits_in_unsigned_long (op_disp
))
5180 i
.types
[op
].bitfield
.disp32
= 1;
5182 if ((i
.types
[op
].bitfield
.disp32
5183 || i
.types
[op
].bitfield
.disp32s
5184 || i
.types
[op
].bitfield
.disp16
)
5185 && fits_in_disp8 (op_disp
))
5186 i
.types
[op
].bitfield
.disp8
= 1;
5188 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5189 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5191 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5192 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5193 i
.types
[op
].bitfield
.disp8
= 0;
5194 i
.types
[op
].bitfield
.disp16
= 0;
5195 i
.types
[op
].bitfield
.disp32
= 0;
5196 i
.types
[op
].bitfield
.disp32s
= 0;
5197 i
.types
[op
].bitfield
.disp64
= 0;
5200 /* We only support 64bit displacement on constants. */
5201 i
.types
[op
].bitfield
.disp64
= 0;
5205 /* Return 1 if there is a match in broadcast bytes between operand
5206 GIVEN and instruction template T. */
5209 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5211 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5212 && i
.types
[given
].bitfield
.byte
)
5213 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5214 && i
.types
[given
].bitfield
.word
)
5215 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5216 && i
.types
[given
].bitfield
.dword
)
5217 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5218 && i
.types
[given
].bitfield
.qword
));
5221 /* Check if operands are valid for the instruction. */
5224 check_VecOperands (const insn_template
*t
)
5228 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5230 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5231 any one operand are implicity requiring AVX512VL support if the actual
5232 operand size is YMMword or XMMword. Since this function runs after
5233 template matching, there's no need to check for YMMword/XMMword in
5235 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5236 if (!cpu_flags_all_zero (&cpu
)
5237 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5238 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5240 for (op
= 0; op
< t
->operands
; ++op
)
5242 if (t
->operand_types
[op
].bitfield
.zmmword
5243 && (i
.types
[op
].bitfield
.ymmword
5244 || i
.types
[op
].bitfield
.xmmword
))
5246 i
.error
= unsupported
;
5252 /* Without VSIB byte, we can't have a vector register for index. */
5253 if (!t
->opcode_modifier
.vecsib
5255 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5256 || i
.index_reg
->reg_type
.bitfield
.ymmword
5257 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5259 i
.error
= unsupported_vector_index_register
;
5263 /* Check if default mask is allowed. */
5264 if (t
->opcode_modifier
.nodefmask
5265 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5267 i
.error
= no_default_mask
;
5271 /* For VSIB byte, we need a vector register for index, and all vector
5272 registers must be distinct. */
5273 if (t
->opcode_modifier
.vecsib
)
5276 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5277 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5278 || (t
->opcode_modifier
.vecsib
== VecSIB256
5279 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5280 || (t
->opcode_modifier
.vecsib
== VecSIB512
5281 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5283 i
.error
= invalid_vsib_address
;
5287 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5288 if (i
.reg_operands
== 2 && !i
.mask
)
5290 gas_assert (i
.types
[0].bitfield
.regsimd
);
5291 gas_assert (i
.types
[0].bitfield
.xmmword
5292 || i
.types
[0].bitfield
.ymmword
);
5293 gas_assert (i
.types
[2].bitfield
.regsimd
);
5294 gas_assert (i
.types
[2].bitfield
.xmmword
5295 || i
.types
[2].bitfield
.ymmword
);
5296 if (operand_check
== check_none
)
5298 if (register_number (i
.op
[0].regs
)
5299 != register_number (i
.index_reg
)
5300 && register_number (i
.op
[2].regs
)
5301 != register_number (i
.index_reg
)
5302 && register_number (i
.op
[0].regs
)
5303 != register_number (i
.op
[2].regs
))
5305 if (operand_check
== check_error
)
5307 i
.error
= invalid_vector_register_set
;
5310 as_warn (_("mask, index, and destination registers should be distinct"));
5312 else if (i
.reg_operands
== 1 && i
.mask
)
5314 if (i
.types
[1].bitfield
.regsimd
5315 && (i
.types
[1].bitfield
.xmmword
5316 || i
.types
[1].bitfield
.ymmword
5317 || i
.types
[1].bitfield
.zmmword
)
5318 && (register_number (i
.op
[1].regs
)
5319 == register_number (i
.index_reg
)))
5321 if (operand_check
== check_error
)
5323 i
.error
= invalid_vector_register_set
;
5326 if (operand_check
!= check_none
)
5327 as_warn (_("index and destination registers should be distinct"));
5332 /* Check if broadcast is supported by the instruction and is applied
5333 to the memory operand. */
5336 i386_operand_type type
, overlap
;
5338 /* Check if specified broadcast is supported in this instruction,
5339 and its broadcast bytes match the memory operand. */
5340 op
= i
.broadcast
->operand
;
5341 if (!t
->opcode_modifier
.broadcast
5342 || !(i
.flags
[op
] & Operand_Mem
)
5343 || (!i
.types
[op
].bitfield
.unspecified
5344 && !match_broadcast_size (t
, op
)))
5347 i
.error
= unsupported_broadcast
;
5351 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5352 * i
.broadcast
->type
);
5353 operand_type_set (&type
, 0);
5354 switch (i
.broadcast
->bytes
)
5357 type
.bitfield
.word
= 1;
5360 type
.bitfield
.dword
= 1;
5363 type
.bitfield
.qword
= 1;
5366 type
.bitfield
.xmmword
= 1;
5369 type
.bitfield
.ymmword
= 1;
5372 type
.bitfield
.zmmword
= 1;
5378 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5379 if (operand_type_all_zero (&overlap
))
5382 if (t
->opcode_modifier
.checkregsize
)
5386 type
.bitfield
.baseindex
= 1;
5387 for (j
= 0; j
< i
.operands
; ++j
)
5390 && !operand_type_register_match(i
.types
[j
],
5391 t
->operand_types
[j
],
5393 t
->operand_types
[op
]))
5398 /* If broadcast is supported in this instruction, we need to check if
5399 operand of one-element size isn't specified without broadcast. */
5400 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5402 /* Find memory operand. */
5403 for (op
= 0; op
< i
.operands
; op
++)
5404 if (operand_type_check (i
.types
[op
], anymem
))
5406 gas_assert (op
< i
.operands
);
5407 /* Check size of the memory operand. */
5408 if (match_broadcast_size (t
, op
))
5410 i
.error
= broadcast_needed
;
5415 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5417 /* Check if requested masking is supported. */
5420 switch (t
->opcode_modifier
.masking
)
5424 case MERGING_MASKING
:
5425 if (i
.mask
->zeroing
)
5428 i
.error
= unsupported_masking
;
5432 case DYNAMIC_MASKING
:
5433 /* Memory destinations allow only merging masking. */
5434 if (i
.mask
->zeroing
&& i
.mem_operands
)
5436 /* Find memory operand. */
5437 for (op
= 0; op
< i
.operands
; op
++)
5438 if (i
.flags
[op
] & Operand_Mem
)
5440 gas_assert (op
< i
.operands
);
5441 if (op
== i
.operands
- 1)
5443 i
.error
= unsupported_masking
;
5453 /* Check if masking is applied to dest operand. */
5454 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5456 i
.error
= mask_not_on_destination
;
5463 if ((i
.rounding
->type
!= saeonly
5464 && !t
->opcode_modifier
.staticrounding
)
5465 || (i
.rounding
->type
== saeonly
5466 && (t
->opcode_modifier
.staticrounding
5467 || !t
->opcode_modifier
.sae
)))
5469 i
.error
= unsupported_rc_sae
;
5472 /* If the instruction has several immediate operands and one of
5473 them is rounding, the rounding operand should be the last
5474 immediate operand. */
5475 if (i
.imm_operands
> 1
5476 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5478 i
.error
= rc_sae_operand_not_last_imm
;
5483 /* Check vector Disp8 operand. */
5484 if (t
->opcode_modifier
.disp8memshift
5485 && i
.disp_encoding
!= disp_encoding_32bit
)
5488 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5489 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5490 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5493 const i386_operand_type
*type
= NULL
;
5496 for (op
= 0; op
< i
.operands
; op
++)
5497 if (operand_type_check (i
.types
[op
], anymem
))
5499 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5500 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5501 else if (t
->operand_types
[op
].bitfield
.xmmword
5502 + t
->operand_types
[op
].bitfield
.ymmword
5503 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5504 type
= &t
->operand_types
[op
];
5505 else if (!i
.types
[op
].bitfield
.unspecified
)
5506 type
= &i
.types
[op
];
5508 else if (i
.types
[op
].bitfield
.regsimd
5509 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5511 if (i
.types
[op
].bitfield
.zmmword
)
5513 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5515 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5521 if (type
->bitfield
.zmmword
)
5523 else if (type
->bitfield
.ymmword
)
5525 else if (type
->bitfield
.xmmword
)
5529 /* For the check in fits_in_disp8(). */
5530 if (i
.memshift
== 0)
5534 for (op
= 0; op
< i
.operands
; op
++)
5535 if (operand_type_check (i
.types
[op
], disp
)
5536 && i
.op
[op
].disps
->X_op
== O_constant
)
5538 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5540 i
.types
[op
].bitfield
.disp8
= 1;
5543 i
.types
[op
].bitfield
.disp8
= 0;
5552 /* Check if operands are valid for the instruction. Update VEX
5556 VEX_check_operands (const insn_template
*t
)
5558 if (i
.vec_encoding
== vex_encoding_evex
)
5560 /* This instruction must be encoded with EVEX prefix. */
5561 if (!is_evex_encoding (t
))
5563 i
.error
= unsupported
;
5569 if (!t
->opcode_modifier
.vex
)
5571 /* This instruction template doesn't have VEX prefix. */
5572 if (i
.vec_encoding
!= vex_encoding_default
)
5574 i
.error
= unsupported
;
5580 /* Only check VEX_Imm4, which must be the first operand. */
5581 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5583 if (i
.op
[0].imms
->X_op
!= O_constant
5584 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5590 /* Turn off Imm8 so that update_imm won't complain. */
5591 i
.types
[0] = vec_imm4
;
5597 static const insn_template
*
5598 match_template (char mnem_suffix
)
5600 /* Points to template once we've found it. */
5601 const insn_template
*t
;
5602 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5603 i386_operand_type overlap4
;
5604 unsigned int found_reverse_match
;
5605 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5606 i386_operand_type operand_types
[MAX_OPERANDS
];
5607 int addr_prefix_disp
;
5609 unsigned int found_cpu_match
, size_match
;
5610 unsigned int check_register
;
5611 enum i386_error specific_error
= 0;
5613 #if MAX_OPERANDS != 5
5614 # error "MAX_OPERANDS must be 5."
5617 found_reverse_match
= 0;
5618 addr_prefix_disp
= -1;
5620 memset (&suffix_check
, 0, sizeof (suffix_check
));
5621 if (intel_syntax
&& i
.broadcast
)
5623 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5624 suffix_check
.no_bsuf
= 1;
5625 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5626 suffix_check
.no_wsuf
= 1;
5627 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5628 suffix_check
.no_ssuf
= 1;
5629 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5630 suffix_check
.no_lsuf
= 1;
5631 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5632 suffix_check
.no_qsuf
= 1;
5633 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5634 suffix_check
.no_ldsuf
= 1;
5636 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5639 switch (mnem_suffix
)
5641 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5642 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5643 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5644 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5645 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5649 /* Must have right number of operands. */
5650 i
.error
= number_of_operands_mismatch
;
5652 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5654 addr_prefix_disp
= -1;
5655 found_reverse_match
= 0;
5657 if (i
.operands
!= t
->operands
)
5660 /* Check processor support. */
5661 i
.error
= unsupported
;
5662 found_cpu_match
= (cpu_flags_match (t
)
5663 == CPU_FLAGS_PERFECT_MATCH
);
5664 if (!found_cpu_match
)
5667 /* Check AT&T mnemonic. */
5668 i
.error
= unsupported_with_intel_mnemonic
;
5669 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5672 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5673 i
.error
= unsupported_syntax
;
5674 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5675 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5676 || (intel64
&& t
->opcode_modifier
.amd64
)
5677 || (!intel64
&& t
->opcode_modifier
.intel64
))
5680 /* Check the suffix, except for some instructions in intel mode. */
5681 i
.error
= invalid_instruction_suffix
;
5682 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5683 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5684 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5685 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5686 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5687 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5688 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5690 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5691 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5692 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5693 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5694 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5695 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5696 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5699 size_match
= operand_size_match (t
);
5703 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5704 operand_types
[j
] = t
->operand_types
[j
];
5706 /* In general, don't allow 64-bit operands in 32-bit mode. */
5707 if (i
.suffix
== QWORD_MNEM_SUFFIX
5708 && flag_code
!= CODE_64BIT
5710 ? (!t
->opcode_modifier
.ignoresize
5711 && !t
->opcode_modifier
.broadcast
5712 && !intel_float_operand (t
->name
))
5713 : intel_float_operand (t
->name
) != 2)
5714 && ((!operand_types
[0].bitfield
.regmmx
5715 && !operand_types
[0].bitfield
.regsimd
)
5716 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5717 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5718 && (t
->base_opcode
!= 0x0fc7
5719 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5722 /* In general, don't allow 32-bit operands on pre-386. */
5723 else if (i
.suffix
== LONG_MNEM_SUFFIX
5724 && !cpu_arch_flags
.bitfield
.cpui386
5726 ? (!t
->opcode_modifier
.ignoresize
5727 && !intel_float_operand (t
->name
))
5728 : intel_float_operand (t
->name
) != 2)
5729 && ((!operand_types
[0].bitfield
.regmmx
5730 && !operand_types
[0].bitfield
.regsimd
)
5731 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5732 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5735 /* Do not verify operands when there are none. */
5739 /* We've found a match; break out of loop. */
5743 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5744 into Disp32/Disp16/Disp32 operand. */
5745 if (i
.prefix
[ADDR_PREFIX
] != 0)
5747 /* There should be only one Disp operand. */
5751 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5753 if (operand_types
[j
].bitfield
.disp16
)
5755 addr_prefix_disp
= j
;
5756 operand_types
[j
].bitfield
.disp32
= 1;
5757 operand_types
[j
].bitfield
.disp16
= 0;
5763 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5765 if (operand_types
[j
].bitfield
.disp32
)
5767 addr_prefix_disp
= j
;
5768 operand_types
[j
].bitfield
.disp32
= 0;
5769 operand_types
[j
].bitfield
.disp16
= 1;
5775 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5777 if (operand_types
[j
].bitfield
.disp64
)
5779 addr_prefix_disp
= j
;
5780 operand_types
[j
].bitfield
.disp64
= 0;
5781 operand_types
[j
].bitfield
.disp32
= 1;
5789 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5790 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5793 /* We check register size if needed. */
5794 if (t
->opcode_modifier
.checkregsize
)
5796 check_register
= (1 << t
->operands
) - 1;
5798 check_register
&= ~(1 << i
.broadcast
->operand
);
5803 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5804 switch (t
->operands
)
5807 if (!operand_type_match (overlap0
, i
.types
[0]))
5811 /* xchg %eax, %eax is a special case. It is an alias for nop
5812 only in 32bit mode and we can use opcode 0x90. In 64bit
5813 mode, we can't use 0x90 for xchg %eax, %eax since it should
5814 zero-extend %eax to %rax. */
5815 if (flag_code
== CODE_64BIT
5816 && t
->base_opcode
== 0x90
5817 && operand_type_equal (&i
.types
[0], &acc32
)
5818 && operand_type_equal (&i
.types
[1], &acc32
))
5820 /* xrelease mov %eax, <disp> is another special case. It must not
5821 match the accumulator-only encoding of mov. */
5822 if (flag_code
!= CODE_64BIT
5824 && t
->base_opcode
== 0xa0
5825 && i
.types
[0].bitfield
.acc
5826 && operand_type_check (i
.types
[1], anymem
))
5831 if (!(size_match
& MATCH_STRAIGHT
))
5833 /* Reverse direction of operands if swapping is possible in the first
5834 place (operands need to be symmetric) and
5835 - the load form is requested, and the template is a store form,
5836 - the store form is requested, and the template is a load form,
5837 - the non-default (swapped) form is requested. */
5838 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5839 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5840 && !operand_type_all_zero (&overlap1
))
5841 switch (i
.dir_encoding
)
5843 case dir_encoding_load
:
5844 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5845 || operand_types
[i
.operands
- 1].bitfield
.regmem
)
5849 case dir_encoding_store
:
5850 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5851 && !operand_types
[i
.operands
- 1].bitfield
.regmem
)
5855 case dir_encoding_swap
:
5858 case dir_encoding_default
:
5861 /* If we want store form, we skip the current load. */
5862 if ((i
.dir_encoding
== dir_encoding_store
5863 || i
.dir_encoding
== dir_encoding_swap
)
5864 && i
.mem_operands
== 0
5865 && t
->opcode_modifier
.load
)
5870 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5871 if (!operand_type_match (overlap0
, i
.types
[0])
5872 || !operand_type_match (overlap1
, i
.types
[1])
5873 || ((check_register
& 3) == 3
5874 && !operand_type_register_match (i
.types
[0],
5879 /* Check if other direction is valid ... */
5880 if (!t
->opcode_modifier
.d
)
5884 if (!(size_match
& MATCH_REVERSE
))
5886 /* Try reversing direction of operands. */
5887 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5888 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5889 if (!operand_type_match (overlap0
, i
.types
[0])
5890 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5892 && !operand_type_register_match (i
.types
[0],
5893 operand_types
[i
.operands
- 1],
5894 i
.types
[i
.operands
- 1],
5897 /* Does not match either direction. */
5900 /* found_reverse_match holds which of D or FloatR
5902 if (!t
->opcode_modifier
.d
)
5903 found_reverse_match
= 0;
5904 else if (operand_types
[0].bitfield
.tbyte
)
5905 found_reverse_match
= Opcode_FloatD
;
5906 else if (operand_types
[0].bitfield
.xmmword
5907 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5908 || operand_types
[0].bitfield
.regmmx
5909 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5910 || is_any_vex_encoding(t
))
5911 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5912 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5914 found_reverse_match
= Opcode_D
;
5915 if (t
->opcode_modifier
.floatr
)
5916 found_reverse_match
|= Opcode_FloatR
;
5920 /* Found a forward 2 operand match here. */
5921 switch (t
->operands
)
5924 overlap4
= operand_type_and (i
.types
[4],
5928 overlap3
= operand_type_and (i
.types
[3],
5932 overlap2
= operand_type_and (i
.types
[2],
5937 switch (t
->operands
)
5940 if (!operand_type_match (overlap4
, i
.types
[4])
5941 || !operand_type_register_match (i
.types
[3],
5948 if (!operand_type_match (overlap3
, i
.types
[3])
5949 || ((check_register
& 0xa) == 0xa
5950 && !operand_type_register_match (i
.types
[1],
5954 || ((check_register
& 0xc) == 0xc
5955 && !operand_type_register_match (i
.types
[2],
5962 /* Here we make use of the fact that there are no
5963 reverse match 3 operand instructions. */
5964 if (!operand_type_match (overlap2
, i
.types
[2])
5965 || ((check_register
& 5) == 5
5966 && !operand_type_register_match (i
.types
[0],
5970 || ((check_register
& 6) == 6
5971 && !operand_type_register_match (i
.types
[1],
5979 /* Found either forward/reverse 2, 3 or 4 operand match here:
5980 slip through to break. */
5982 if (!found_cpu_match
)
5985 /* Check if vector and VEX operands are valid. */
5986 if (check_VecOperands (t
) || VEX_check_operands (t
))
5988 specific_error
= i
.error
;
5992 /* We've found a match; break out of loop. */
5996 if (t
== current_templates
->end
)
5998 /* We found no match. */
5999 const char *err_msg
;
6000 switch (specific_error
? specific_error
: i
.error
)
6004 case operand_size_mismatch
:
6005 err_msg
= _("operand size mismatch");
6007 case operand_type_mismatch
:
6008 err_msg
= _("operand type mismatch");
6010 case register_type_mismatch
:
6011 err_msg
= _("register type mismatch");
6013 case number_of_operands_mismatch
:
6014 err_msg
= _("number of operands mismatch");
6016 case invalid_instruction_suffix
:
6017 err_msg
= _("invalid instruction suffix");
6020 err_msg
= _("constant doesn't fit in 4 bits");
6022 case unsupported_with_intel_mnemonic
:
6023 err_msg
= _("unsupported with Intel mnemonic");
6025 case unsupported_syntax
:
6026 err_msg
= _("unsupported syntax");
6029 as_bad (_("unsupported instruction `%s'"),
6030 current_templates
->start
->name
);
6032 case invalid_vsib_address
:
6033 err_msg
= _("invalid VSIB address");
6035 case invalid_vector_register_set
:
6036 err_msg
= _("mask, index, and destination registers must be distinct");
6038 case unsupported_vector_index_register
:
6039 err_msg
= _("unsupported vector index register");
6041 case unsupported_broadcast
:
6042 err_msg
= _("unsupported broadcast");
6044 case broadcast_needed
:
6045 err_msg
= _("broadcast is needed for operand of such type");
6047 case unsupported_masking
:
6048 err_msg
= _("unsupported masking");
6050 case mask_not_on_destination
:
6051 err_msg
= _("mask not on destination operand");
6053 case no_default_mask
:
6054 err_msg
= _("default mask isn't allowed");
6056 case unsupported_rc_sae
:
6057 err_msg
= _("unsupported static rounding/sae");
6059 case rc_sae_operand_not_last_imm
:
6061 err_msg
= _("RC/SAE operand must precede immediate operands");
6063 err_msg
= _("RC/SAE operand must follow immediate operands");
6065 case invalid_register_operand
:
6066 err_msg
= _("invalid register operand");
6069 as_bad (_("%s for `%s'"), err_msg
,
6070 current_templates
->start
->name
);
6074 if (!quiet_warnings
)
6077 && (i
.types
[0].bitfield
.jumpabsolute
6078 != operand_types
[0].bitfield
.jumpabsolute
))
6080 as_warn (_("indirect %s without `*'"), t
->name
);
6083 if (t
->opcode_modifier
.isprefix
6084 && t
->opcode_modifier
.ignoresize
)
6086 /* Warn them that a data or address size prefix doesn't
6087 affect assembly of the next line of code. */
6088 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6092 /* Copy the template we found. */
6095 if (addr_prefix_disp
!= -1)
6096 i
.tm
.operand_types
[addr_prefix_disp
]
6097 = operand_types
[addr_prefix_disp
];
6099 if (found_reverse_match
)
6101 /* If we found a reverse match we must alter the opcode
6102 direction bit. found_reverse_match holds bits to change
6103 (different for int & float insns). */
6105 i
.tm
.base_opcode
^= found_reverse_match
;
6107 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6108 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6117 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
6118 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6120 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6122 as_bad (_("`%s' operand %d must use `%ses' segment"),
6128 /* There's only ever one segment override allowed per instruction.
6129 This instruction possibly has a legal segment override on the
6130 second operand, so copy the segment to where non-string
6131 instructions store it, allowing common code. */
6132 i
.seg
[0] = i
.seg
[1];
6134 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6136 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6138 as_bad (_("`%s' operand %d must use `%ses' segment"),
6149 process_suffix (void)
6151 /* If matched instruction specifies an explicit instruction mnemonic
6153 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6154 i
.suffix
= WORD_MNEM_SUFFIX
;
6155 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6156 i
.suffix
= LONG_MNEM_SUFFIX
;
6157 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6158 i
.suffix
= QWORD_MNEM_SUFFIX
;
6159 else if (i
.reg_operands
)
6161 /* If there's no instruction mnemonic suffix we try to invent one
6162 based on register operands. */
6165 /* We take i.suffix from the last register operand specified,
6166 Destination register type is more significant than source
6167 register type. crc32 in SSE4.2 prefers source register
6169 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6171 if (i
.types
[0].bitfield
.byte
)
6172 i
.suffix
= BYTE_MNEM_SUFFIX
;
6173 else if (i
.types
[0].bitfield
.word
)
6174 i
.suffix
= WORD_MNEM_SUFFIX
;
6175 else if (i
.types
[0].bitfield
.dword
)
6176 i
.suffix
= LONG_MNEM_SUFFIX
;
6177 else if (i
.types
[0].bitfield
.qword
)
6178 i
.suffix
= QWORD_MNEM_SUFFIX
;
6185 if (i
.tm
.base_opcode
== 0xf20f38f0)
6187 /* We have to know the operand size for crc32. */
6188 as_bad (_("ambiguous memory operand size for `%s`"),
6193 for (op
= i
.operands
; --op
>= 0;)
6194 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6195 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6197 if (!i
.types
[op
].bitfield
.reg
)
6199 if (i
.types
[op
].bitfield
.byte
)
6200 i
.suffix
= BYTE_MNEM_SUFFIX
;
6201 else if (i
.types
[op
].bitfield
.word
)
6202 i
.suffix
= WORD_MNEM_SUFFIX
;
6203 else if (i
.types
[op
].bitfield
.dword
)
6204 i
.suffix
= LONG_MNEM_SUFFIX
;
6205 else if (i
.types
[op
].bitfield
.qword
)
6206 i
.suffix
= QWORD_MNEM_SUFFIX
;
6213 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6216 && i
.tm
.opcode_modifier
.ignoresize
6217 && i
.tm
.opcode_modifier
.no_bsuf
)
6219 else if (!check_byte_reg ())
6222 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6225 && i
.tm
.opcode_modifier
.ignoresize
6226 && i
.tm
.opcode_modifier
.no_lsuf
6227 && !i
.tm
.opcode_modifier
.todword
6228 && !i
.tm
.opcode_modifier
.toqword
)
6230 else if (!check_long_reg ())
6233 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6236 && i
.tm
.opcode_modifier
.ignoresize
6237 && i
.tm
.opcode_modifier
.no_qsuf
6238 && !i
.tm
.opcode_modifier
.todword
6239 && !i
.tm
.opcode_modifier
.toqword
)
6241 else if (!check_qword_reg ())
6244 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6247 && i
.tm
.opcode_modifier
.ignoresize
6248 && i
.tm
.opcode_modifier
.no_wsuf
)
6250 else if (!check_word_reg ())
6253 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6254 /* Do nothing if the instruction is going to ignore the prefix. */
6259 else if (i
.tm
.opcode_modifier
.defaultsize
6261 /* exclude fldenv/frstor/fsave/fstenv */
6262 && i
.tm
.opcode_modifier
.no_ssuf
)
6264 if (stackop_size
== LONG_MNEM_SUFFIX
6265 && i
.tm
.base_opcode
== 0xcf)
6267 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6268 .code16gcc directive to support 16-bit mode with
6269 32-bit address. For IRET without a suffix, generate
6270 16-bit IRET (opcode 0xcf) to return from an interrupt
6272 i
.suffix
= WORD_MNEM_SUFFIX
;
6273 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6276 i
.suffix
= stackop_size
;
6278 else if (intel_syntax
6280 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6281 || i
.tm
.opcode_modifier
.jumpbyte
6282 || i
.tm
.opcode_modifier
.jumpintersegment
6283 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6284 && i
.tm
.extension_opcode
<= 3)))
6289 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6291 i
.suffix
= QWORD_MNEM_SUFFIX
;
6296 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6297 i
.suffix
= LONG_MNEM_SUFFIX
;
6300 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6301 i
.suffix
= WORD_MNEM_SUFFIX
;
6310 if (i
.tm
.opcode_modifier
.w
)
6312 as_bad (_("no instruction mnemonic suffix given and "
6313 "no register operands; can't size instruction"));
6319 unsigned int suffixes
;
6321 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6322 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6324 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6326 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6328 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6330 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6333 /* There are more than suffix matches. */
6334 if (i
.tm
.opcode_modifier
.w
6335 || ((suffixes
& (suffixes
- 1))
6336 && !i
.tm
.opcode_modifier
.defaultsize
6337 && !i
.tm
.opcode_modifier
.ignoresize
))
6339 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6345 /* Change the opcode based on the operand size given by i.suffix. */
6348 /* Size floating point instruction. */
6349 case LONG_MNEM_SUFFIX
:
6350 if (i
.tm
.opcode_modifier
.floatmf
)
6352 i
.tm
.base_opcode
^= 4;
6356 case WORD_MNEM_SUFFIX
:
6357 case QWORD_MNEM_SUFFIX
:
6358 /* It's not a byte, select word/dword operation. */
6359 if (i
.tm
.opcode_modifier
.w
)
6361 if (i
.tm
.opcode_modifier
.shortform
)
6362 i
.tm
.base_opcode
|= 8;
6364 i
.tm
.base_opcode
|= 1;
6367 case SHORT_MNEM_SUFFIX
:
6368 /* Now select between word & dword operations via the operand
6369 size prefix, except for instructions that will ignore this
6371 if (i
.reg_operands
> 0
6372 && i
.types
[0].bitfield
.reg
6373 && i
.tm
.opcode_modifier
.addrprefixopreg
6374 && (i
.tm
.opcode_modifier
.immext
6375 || i
.operands
== 1))
6377 /* The address size override prefix changes the size of the
6379 if ((flag_code
== CODE_32BIT
6380 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6381 || (flag_code
!= CODE_32BIT
6382 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6383 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6386 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6387 && !i
.tm
.opcode_modifier
.ignoresize
6388 && !i
.tm
.opcode_modifier
.floatmf
6389 && !i
.tm
.opcode_modifier
.vex
6390 && !i
.tm
.opcode_modifier
.vexopcode
6391 && !is_evex_encoding (&i
.tm
)
6392 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6393 || (flag_code
== CODE_64BIT
6394 && i
.tm
.opcode_modifier
.jumpbyte
)))
6396 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6398 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6399 prefix
= ADDR_PREFIX_OPCODE
;
6401 if (!add_prefix (prefix
))
6405 /* Set mode64 for an operand. */
6406 if (i
.suffix
== QWORD_MNEM_SUFFIX
6407 && flag_code
== CODE_64BIT
6408 && !i
.tm
.opcode_modifier
.norex64
6409 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6411 && ! (i
.operands
== 2
6412 && i
.tm
.base_opcode
== 0x90
6413 && i
.tm
.extension_opcode
== None
6414 && operand_type_equal (&i
.types
[0], &acc64
)
6415 && operand_type_equal (&i
.types
[1], &acc64
)))
6421 if (i
.reg_operands
!= 0
6423 && i
.tm
.opcode_modifier
.addrprefixopreg
6424 && !i
.tm
.opcode_modifier
.immext
)
6426 /* Check invalid register operand when the address size override
6427 prefix changes the size of register operands. */
6429 enum { need_word
, need_dword
, need_qword
} need
;
6431 if (flag_code
== CODE_32BIT
)
6432 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6435 if (i
.prefix
[ADDR_PREFIX
])
6438 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6441 for (op
= 0; op
< i
.operands
; op
++)
6442 if (i
.types
[op
].bitfield
.reg
6443 && ((need
== need_word
6444 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6445 || (need
== need_dword
6446 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6447 || (need
== need_qword
6448 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6450 as_bad (_("invalid register operand size for `%s'"),
6460 check_byte_reg (void)
6464 for (op
= i
.operands
; --op
>= 0;)
6466 /* Skip non-register operands. */
6467 if (!i
.types
[op
].bitfield
.reg
)
6470 /* If this is an eight bit register, it's OK. If it's the 16 or
6471 32 bit version of an eight bit register, we will just use the
6472 low portion, and that's OK too. */
6473 if (i
.types
[op
].bitfield
.byte
)
6476 /* I/O port address operands are OK too. */
6477 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6480 /* crc32 doesn't generate this warning. */
6481 if (i
.tm
.base_opcode
== 0xf20f38f0)
6484 if ((i
.types
[op
].bitfield
.word
6485 || i
.types
[op
].bitfield
.dword
6486 || i
.types
[op
].bitfield
.qword
)
6487 && i
.op
[op
].regs
->reg_num
< 4
6488 /* Prohibit these changes in 64bit mode, since the lowering
6489 would be more complicated. */
6490 && flag_code
!= CODE_64BIT
)
6492 #if REGISTER_WARNINGS
6493 if (!quiet_warnings
)
6494 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6496 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6497 ? REGNAM_AL
- REGNAM_AX
6498 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6500 i
.op
[op
].regs
->reg_name
,
6505 /* Any other register is bad. */
6506 if (i
.types
[op
].bitfield
.reg
6507 || i
.types
[op
].bitfield
.regmmx
6508 || i
.types
[op
].bitfield
.regsimd
6509 || i
.types
[op
].bitfield
.sreg2
6510 || i
.types
[op
].bitfield
.sreg3
6511 || i
.types
[op
].bitfield
.control
6512 || i
.types
[op
].bitfield
.debug
6513 || i
.types
[op
].bitfield
.test
)
6515 as_bad (_("`%s%s' not allowed with `%s%c'"),
6517 i
.op
[op
].regs
->reg_name
,
6527 check_long_reg (void)
6531 for (op
= i
.operands
; --op
>= 0;)
6532 /* Skip non-register operands. */
6533 if (!i
.types
[op
].bitfield
.reg
)
6535 /* Reject eight bit registers, except where the template requires
6536 them. (eg. movzb) */
6537 else if (i
.types
[op
].bitfield
.byte
6538 && (i
.tm
.operand_types
[op
].bitfield
.reg
6539 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6540 && (i
.tm
.operand_types
[op
].bitfield
.word
6541 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6543 as_bad (_("`%s%s' not allowed with `%s%c'"),
6545 i
.op
[op
].regs
->reg_name
,
6550 /* Warn if the e prefix on a general reg is missing. */
6551 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6552 && i
.types
[op
].bitfield
.word
6553 && (i
.tm
.operand_types
[op
].bitfield
.reg
6554 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6555 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6557 /* Prohibit these changes in the 64bit mode, since the
6558 lowering is more complicated. */
6559 if (flag_code
== CODE_64BIT
)
6561 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6562 register_prefix
, i
.op
[op
].regs
->reg_name
,
6566 #if REGISTER_WARNINGS
6567 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6569 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6570 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6573 /* Warn if the r prefix on a general reg is present. */
6574 else if (i
.types
[op
].bitfield
.qword
6575 && (i
.tm
.operand_types
[op
].bitfield
.reg
6576 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6577 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6580 && i
.tm
.opcode_modifier
.toqword
6581 && !i
.types
[0].bitfield
.regsimd
)
6583 /* Convert to QWORD. We want REX byte. */
6584 i
.suffix
= QWORD_MNEM_SUFFIX
;
6588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6589 register_prefix
, i
.op
[op
].regs
->reg_name
,
6598 check_qword_reg (void)
6602 for (op
= i
.operands
; --op
>= 0; )
6603 /* Skip non-register operands. */
6604 if (!i
.types
[op
].bitfield
.reg
)
6606 /* Reject eight bit registers, except where the template requires
6607 them. (eg. movzb) */
6608 else if (i
.types
[op
].bitfield
.byte
6609 && (i
.tm
.operand_types
[op
].bitfield
.reg
6610 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6611 && (i
.tm
.operand_types
[op
].bitfield
.word
6612 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6614 as_bad (_("`%s%s' not allowed with `%s%c'"),
6616 i
.op
[op
].regs
->reg_name
,
6621 /* Warn if the r prefix on a general reg is missing. */
6622 else if ((i
.types
[op
].bitfield
.word
6623 || i
.types
[op
].bitfield
.dword
)
6624 && (i
.tm
.operand_types
[op
].bitfield
.reg
6625 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6626 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6628 /* Prohibit these changes in the 64bit mode, since the
6629 lowering is more complicated. */
6631 && i
.tm
.opcode_modifier
.todword
6632 && !i
.types
[0].bitfield
.regsimd
)
6634 /* Convert to DWORD. We don't want REX byte. */
6635 i
.suffix
= LONG_MNEM_SUFFIX
;
6639 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6640 register_prefix
, i
.op
[op
].regs
->reg_name
,
6649 check_word_reg (void)
6652 for (op
= i
.operands
; --op
>= 0;)
6653 /* Skip non-register operands. */
6654 if (!i
.types
[op
].bitfield
.reg
)
6656 /* Reject eight bit registers, except where the template requires
6657 them. (eg. movzb) */
6658 else if (i
.types
[op
].bitfield
.byte
6659 && (i
.tm
.operand_types
[op
].bitfield
.reg
6660 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6661 && (i
.tm
.operand_types
[op
].bitfield
.word
6662 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6664 as_bad (_("`%s%s' not allowed with `%s%c'"),
6666 i
.op
[op
].regs
->reg_name
,
6671 /* Warn if the e or r prefix on a general reg is present. */
6672 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6673 && (i
.types
[op
].bitfield
.dword
6674 || i
.types
[op
].bitfield
.qword
)
6675 && (i
.tm
.operand_types
[op
].bitfield
.reg
6676 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6677 && i
.tm
.operand_types
[op
].bitfield
.word
)
6679 /* Prohibit these changes in the 64bit mode, since the
6680 lowering is more complicated. */
6681 if (flag_code
== CODE_64BIT
)
6683 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6684 register_prefix
, i
.op
[op
].regs
->reg_name
,
6688 #if REGISTER_WARNINGS
6689 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6691 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6692 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6699 update_imm (unsigned int j
)
6701 i386_operand_type overlap
= i
.types
[j
];
6702 if ((overlap
.bitfield
.imm8
6703 || overlap
.bitfield
.imm8s
6704 || overlap
.bitfield
.imm16
6705 || overlap
.bitfield
.imm32
6706 || overlap
.bitfield
.imm32s
6707 || overlap
.bitfield
.imm64
)
6708 && !operand_type_equal (&overlap
, &imm8
)
6709 && !operand_type_equal (&overlap
, &imm8s
)
6710 && !operand_type_equal (&overlap
, &imm16
)
6711 && !operand_type_equal (&overlap
, &imm32
)
6712 && !operand_type_equal (&overlap
, &imm32s
)
6713 && !operand_type_equal (&overlap
, &imm64
))
6717 i386_operand_type temp
;
6719 operand_type_set (&temp
, 0);
6720 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6722 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6723 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6725 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6726 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6727 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6729 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6730 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6733 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6736 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6737 || operand_type_equal (&overlap
, &imm16_32
)
6738 || operand_type_equal (&overlap
, &imm16_32s
))
6740 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6745 if (!operand_type_equal (&overlap
, &imm8
)
6746 && !operand_type_equal (&overlap
, &imm8s
)
6747 && !operand_type_equal (&overlap
, &imm16
)
6748 && !operand_type_equal (&overlap
, &imm32
)
6749 && !operand_type_equal (&overlap
, &imm32s
)
6750 && !operand_type_equal (&overlap
, &imm64
))
6752 as_bad (_("no instruction mnemonic suffix given; "
6753 "can't determine immediate size"));
6757 i
.types
[j
] = overlap
;
6767 /* Update the first 2 immediate operands. */
6768 n
= i
.operands
> 2 ? 2 : i
.operands
;
6771 for (j
= 0; j
< n
; j
++)
6772 if (update_imm (j
) == 0)
6775 /* The 3rd operand can't be immediate operand. */
6776 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6783 process_operands (void)
6785 /* Default segment register this instruction will use for memory
6786 accesses. 0 means unknown. This is only for optimizing out
6787 unnecessary segment overrides. */
6788 const seg_entry
*default_seg
= 0;
6790 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6792 unsigned int dupl
= i
.operands
;
6793 unsigned int dest
= dupl
- 1;
6796 /* The destination must be an xmm register. */
6797 gas_assert (i
.reg_operands
6798 && MAX_OPERANDS
> dupl
6799 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6801 if (i
.tm
.operand_types
[0].bitfield
.acc
6802 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6804 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6806 /* Keep xmm0 for instructions with VEX prefix and 3
6808 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6809 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6814 /* We remove the first xmm0 and keep the number of
6815 operands unchanged, which in fact duplicates the
6817 for (j
= 1; j
< i
.operands
; j
++)
6819 i
.op
[j
- 1] = i
.op
[j
];
6820 i
.types
[j
- 1] = i
.types
[j
];
6821 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6825 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6827 gas_assert ((MAX_OPERANDS
- 1) > dupl
6828 && (i
.tm
.opcode_modifier
.vexsources
6831 /* Add the implicit xmm0 for instructions with VEX prefix
6833 for (j
= i
.operands
; j
> 0; j
--)
6835 i
.op
[j
] = i
.op
[j
- 1];
6836 i
.types
[j
] = i
.types
[j
- 1];
6837 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6840 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6841 i
.types
[0] = regxmm
;
6842 i
.tm
.operand_types
[0] = regxmm
;
6845 i
.reg_operands
+= 2;
6850 i
.op
[dupl
] = i
.op
[dest
];
6851 i
.types
[dupl
] = i
.types
[dest
];
6852 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6861 i
.op
[dupl
] = i
.op
[dest
];
6862 i
.types
[dupl
] = i
.types
[dest
];
6863 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6866 if (i
.tm
.opcode_modifier
.immext
)
6869 else if (i
.tm
.operand_types
[0].bitfield
.acc
6870 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6874 for (j
= 1; j
< i
.operands
; j
++)
6876 i
.op
[j
- 1] = i
.op
[j
];
6877 i
.types
[j
- 1] = i
.types
[j
];
6879 /* We need to adjust fields in i.tm since they are used by
6880 build_modrm_byte. */
6881 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6888 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6890 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6892 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6893 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6894 regnum
= register_number (i
.op
[1].regs
);
6895 first_reg_in_group
= regnum
& ~3;
6896 last_reg_in_group
= first_reg_in_group
+ 3;
6897 if (regnum
!= first_reg_in_group
)
6898 as_warn (_("source register `%s%s' implicitly denotes"
6899 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6900 register_prefix
, i
.op
[1].regs
->reg_name
,
6901 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6902 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6905 else if (i
.tm
.opcode_modifier
.regkludge
)
6907 /* The imul $imm, %reg instruction is converted into
6908 imul $imm, %reg, %reg, and the clr %reg instruction
6909 is converted into xor %reg, %reg. */
6911 unsigned int first_reg_op
;
6913 if (operand_type_check (i
.types
[0], reg
))
6917 /* Pretend we saw the extra register operand. */
6918 gas_assert (i
.reg_operands
== 1
6919 && i
.op
[first_reg_op
+ 1].regs
== 0);
6920 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6921 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6926 if (i
.tm
.opcode_modifier
.shortform
)
6928 if (i
.types
[0].bitfield
.sreg2
6929 || i
.types
[0].bitfield
.sreg3
)
6931 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6932 && i
.op
[0].regs
->reg_num
== 1)
6934 as_bad (_("you can't `pop %scs'"), register_prefix
);
6937 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6938 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6943 /* The register or float register operand is in operand
6947 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6948 || operand_type_check (i
.types
[0], reg
))
6952 /* Register goes in low 3 bits of opcode. */
6953 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6954 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6956 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6958 /* Warn about some common errors, but press on regardless.
6959 The first case can be generated by gcc (<= 2.8.1). */
6960 if (i
.operands
== 2)
6962 /* Reversed arguments on faddp, fsubp, etc. */
6963 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6964 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6965 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6969 /* Extraneous `l' suffix on fp insn. */
6970 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6971 register_prefix
, i
.op
[0].regs
->reg_name
);
6976 else if (i
.tm
.opcode_modifier
.modrm
)
6978 /* The opcode is completed (modulo i.tm.extension_opcode which
6979 must be put into the modrm byte). Now, we make the modrm and
6980 index base bytes based on all the info we've collected. */
6982 default_seg
= build_modrm_byte ();
6984 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6988 else if (i
.tm
.opcode_modifier
.isstring
)
6990 /* For the string instructions that allow a segment override
6991 on one of their operands, the default segment is ds. */
6995 if (i
.tm
.base_opcode
== 0x8d /* lea */
6998 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7000 /* If a segment was explicitly specified, and the specified segment
7001 is not the default, use an opcode prefix to select it. If we
7002 never figured out what the default segment is, then default_seg
7003 will be zero at this point, and the specified segment prefix will
7005 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7007 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7013 static const seg_entry
*
7014 build_modrm_byte (void)
7016 const seg_entry
*default_seg
= 0;
7017 unsigned int source
, dest
;
7020 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7023 unsigned int nds
, reg_slot
;
7026 dest
= i
.operands
- 1;
7029 /* There are 2 kinds of instructions:
7030 1. 5 operands: 4 register operands or 3 register operands
7031 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
7032 VexW0 or VexW1. The destination must be either XMM, YMM or
7034 2. 4 operands: 4 register operands or 3 register operands
7035 plus 1 memory operand, with VexXDS. */
7036 gas_assert ((i
.reg_operands
== 4
7037 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7038 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7039 && i
.tm
.opcode_modifier
.vexw
7040 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7042 /* If VexW1 is set, the first non-immediate operand is the source and
7043 the second non-immediate one is encoded in the immediate operand. */
7044 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7046 source
= i
.imm_operands
;
7047 reg_slot
= i
.imm_operands
+ 1;
7051 source
= i
.imm_operands
+ 1;
7052 reg_slot
= i
.imm_operands
;
7055 if (i
.imm_operands
== 0)
7057 /* When there is no immediate operand, generate an 8bit
7058 immediate operand to encode the first operand. */
7059 exp
= &im_expressions
[i
.imm_operands
++];
7060 i
.op
[i
.operands
].imms
= exp
;
7061 i
.types
[i
.operands
] = imm8
;
7064 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7065 exp
->X_op
= O_constant
;
7066 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7067 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7071 unsigned int imm_slot
;
7073 gas_assert (i
.imm_operands
== 1 && i
.types
[0].bitfield
.vec_imm4
);
7075 if (i
.tm
.opcode_modifier
.immext
)
7077 /* When ImmExt is set, the immediate byte is the last
7079 imm_slot
= i
.operands
- 1;
7087 /* Turn on Imm8 so that output_imm will generate it. */
7088 i
.types
[imm_slot
].bitfield
.imm8
= 1;
7091 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7092 i
.op
[imm_slot
].imms
->X_add_number
7093 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7094 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7097 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7098 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7103 /* i.reg_operands MUST be the number of real register operands;
7104 implicit registers do not count. If there are 3 register
7105 operands, it must be a instruction with VexNDS. For a
7106 instruction with VexNDD, the destination register is encoded
7107 in VEX prefix. If there are 4 register operands, it must be
7108 a instruction with VEX prefix and 3 sources. */
7109 if (i
.mem_operands
== 0
7110 && ((i
.reg_operands
== 2
7111 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7112 || (i
.reg_operands
== 3
7113 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7114 || (i
.reg_operands
== 4 && vex_3_sources
)))
7122 /* When there are 3 operands, one of them may be immediate,
7123 which may be the first or the last operand. Otherwise,
7124 the first operand must be shift count register (cl) or it
7125 is an instruction with VexNDS. */
7126 gas_assert (i
.imm_operands
== 1
7127 || (i
.imm_operands
== 0
7128 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7129 || i
.types
[0].bitfield
.shiftcount
)));
7130 if (operand_type_check (i
.types
[0], imm
)
7131 || i
.types
[0].bitfield
.shiftcount
)
7137 /* When there are 4 operands, the first two must be 8bit
7138 immediate operands. The source operand will be the 3rd
7141 For instructions with VexNDS, if the first operand
7142 an imm8, the source operand is the 2nd one. If the last
7143 operand is imm8, the source operand is the first one. */
7144 gas_assert ((i
.imm_operands
== 2
7145 && i
.types
[0].bitfield
.imm8
7146 && i
.types
[1].bitfield
.imm8
)
7147 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7148 && i
.imm_operands
== 1
7149 && (i
.types
[0].bitfield
.imm8
7150 || i
.types
[i
.operands
- 1].bitfield
.imm8
7152 if (i
.imm_operands
== 2)
7156 if (i
.types
[0].bitfield
.imm8
)
7163 if (is_evex_encoding (&i
.tm
))
7165 /* For EVEX instructions, when there are 5 operands, the
7166 first one must be immediate operand. If the second one
7167 is immediate operand, the source operand is the 3th
7168 one. If the last one is immediate operand, the source
7169 operand is the 2nd one. */
7170 gas_assert (i
.imm_operands
== 2
7171 && i
.tm
.opcode_modifier
.sae
7172 && operand_type_check (i
.types
[0], imm
));
7173 if (operand_type_check (i
.types
[1], imm
))
7175 else if (operand_type_check (i
.types
[4], imm
))
7189 /* RC/SAE operand could be between DEST and SRC. That happens
7190 when one operand is GPR and the other one is XMM/YMM/ZMM
7192 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7195 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7197 /* For instructions with VexNDS, the register-only source
7198 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7199 register. It is encoded in VEX prefix. We need to
7200 clear RegMem bit before calling operand_type_equal. */
7202 i386_operand_type op
;
7205 /* Check register-only source operand when two source
7206 operands are swapped. */
7207 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7208 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7216 op
= i
.tm
.operand_types
[vvvv
];
7217 op
.bitfield
.regmem
= 0;
7218 if ((dest
+ 1) >= i
.operands
7219 || ((!op
.bitfield
.reg
7220 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7221 && !op
.bitfield
.regsimd
7222 && !operand_type_equal (&op
, ®mask
)))
7224 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7230 /* One of the register operands will be encoded in the i.tm.reg
7231 field, the other in the combined i.tm.mode and i.tm.regmem
7232 fields. If no form of this instruction supports a memory
7233 destination operand, then we assume the source operand may
7234 sometimes be a memory operand and so we need to store the
7235 destination in the i.rm.reg field. */
7236 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
7237 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7239 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7240 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7241 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7242 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7243 i
.has_regmmx
= TRUE
;
7244 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7245 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7247 if (i
.types
[dest
].bitfield
.zmmword
7248 || i
.types
[source
].bitfield
.zmmword
)
7249 i
.has_regzmm
= TRUE
;
7250 else if (i
.types
[dest
].bitfield
.ymmword
7251 || i
.types
[source
].bitfield
.ymmword
)
7252 i
.has_regymm
= TRUE
;
7254 i
.has_regxmm
= TRUE
;
7256 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7258 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7260 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7262 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7267 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7268 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7269 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7271 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7273 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7275 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7278 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7280 if (!i
.types
[i
.tm
.operand_types
[0].bitfield
.regmem
].bitfield
.control
)
7283 add_prefix (LOCK_PREFIX_OPCODE
);
7287 { /* If it's not 2 reg operands... */
7292 unsigned int fake_zero_displacement
= 0;
7295 for (op
= 0; op
< i
.operands
; op
++)
7296 if (operand_type_check (i
.types
[op
], anymem
))
7298 gas_assert (op
< i
.operands
);
7300 if (i
.tm
.opcode_modifier
.vecsib
)
7302 if (i
.index_reg
->reg_num
== RegIZ
)
7305 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7308 i
.sib
.base
= NO_BASE_REGISTER
;
7309 i
.sib
.scale
= i
.log2_scale_factor
;
7310 i
.types
[op
].bitfield
.disp8
= 0;
7311 i
.types
[op
].bitfield
.disp16
= 0;
7312 i
.types
[op
].bitfield
.disp64
= 0;
7313 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7315 /* Must be 32 bit */
7316 i
.types
[op
].bitfield
.disp32
= 1;
7317 i
.types
[op
].bitfield
.disp32s
= 0;
7321 i
.types
[op
].bitfield
.disp32
= 0;
7322 i
.types
[op
].bitfield
.disp32s
= 1;
7325 i
.sib
.index
= i
.index_reg
->reg_num
;
7326 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7328 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7334 if (i
.base_reg
== 0)
7337 if (!i
.disp_operands
)
7338 fake_zero_displacement
= 1;
7339 if (i
.index_reg
== 0)
7341 i386_operand_type newdisp
;
7343 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7344 /* Operand is just <disp> */
7345 if (flag_code
== CODE_64BIT
)
7347 /* 64bit mode overwrites the 32bit absolute
7348 addressing by RIP relative addressing and
7349 absolute addressing is encoded by one of the
7350 redundant SIB forms. */
7351 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7352 i
.sib
.base
= NO_BASE_REGISTER
;
7353 i
.sib
.index
= NO_INDEX_REGISTER
;
7354 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7356 else if ((flag_code
== CODE_16BIT
)
7357 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7359 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7364 i
.rm
.regmem
= NO_BASE_REGISTER
;
7367 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7368 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7370 else if (!i
.tm
.opcode_modifier
.vecsib
)
7372 /* !i.base_reg && i.index_reg */
7373 if (i
.index_reg
->reg_num
== RegIZ
)
7374 i
.sib
.index
= NO_INDEX_REGISTER
;
7376 i
.sib
.index
= i
.index_reg
->reg_num
;
7377 i
.sib
.base
= NO_BASE_REGISTER
;
7378 i
.sib
.scale
= i
.log2_scale_factor
;
7379 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7380 i
.types
[op
].bitfield
.disp8
= 0;
7381 i
.types
[op
].bitfield
.disp16
= 0;
7382 i
.types
[op
].bitfield
.disp64
= 0;
7383 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7385 /* Must be 32 bit */
7386 i
.types
[op
].bitfield
.disp32
= 1;
7387 i
.types
[op
].bitfield
.disp32s
= 0;
7391 i
.types
[op
].bitfield
.disp32
= 0;
7392 i
.types
[op
].bitfield
.disp32s
= 1;
7394 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7398 /* RIP addressing for 64bit mode. */
7399 else if (i
.base_reg
->reg_num
== RegIP
)
7401 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7402 i
.rm
.regmem
= NO_BASE_REGISTER
;
7403 i
.types
[op
].bitfield
.disp8
= 0;
7404 i
.types
[op
].bitfield
.disp16
= 0;
7405 i
.types
[op
].bitfield
.disp32
= 0;
7406 i
.types
[op
].bitfield
.disp32s
= 1;
7407 i
.types
[op
].bitfield
.disp64
= 0;
7408 i
.flags
[op
] |= Operand_PCrel
;
7409 if (! i
.disp_operands
)
7410 fake_zero_displacement
= 1;
7412 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7414 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7415 switch (i
.base_reg
->reg_num
)
7418 if (i
.index_reg
== 0)
7420 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7421 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7425 if (i
.index_reg
== 0)
7428 if (operand_type_check (i
.types
[op
], disp
) == 0)
7430 /* fake (%bp) into 0(%bp) */
7431 i
.types
[op
].bitfield
.disp8
= 1;
7432 fake_zero_displacement
= 1;
7435 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7436 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7438 default: /* (%si) -> 4 or (%di) -> 5 */
7439 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7441 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7443 else /* i.base_reg and 32/64 bit mode */
7445 if (flag_code
== CODE_64BIT
7446 && operand_type_check (i
.types
[op
], disp
))
7448 i
.types
[op
].bitfield
.disp16
= 0;
7449 i
.types
[op
].bitfield
.disp64
= 0;
7450 if (i
.prefix
[ADDR_PREFIX
] == 0)
7452 i
.types
[op
].bitfield
.disp32
= 0;
7453 i
.types
[op
].bitfield
.disp32s
= 1;
7457 i
.types
[op
].bitfield
.disp32
= 1;
7458 i
.types
[op
].bitfield
.disp32s
= 0;
7462 if (!i
.tm
.opcode_modifier
.vecsib
)
7463 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7464 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7466 i
.sib
.base
= i
.base_reg
->reg_num
;
7467 /* x86-64 ignores REX prefix bit here to avoid decoder
7469 if (!(i
.base_reg
->reg_flags
& RegRex
)
7470 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7471 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7473 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7475 fake_zero_displacement
= 1;
7476 i
.types
[op
].bitfield
.disp8
= 1;
7478 i
.sib
.scale
= i
.log2_scale_factor
;
7479 if (i
.index_reg
== 0)
7481 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7482 /* <disp>(%esp) becomes two byte modrm with no index
7483 register. We've already stored the code for esp
7484 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7485 Any base register besides %esp will not use the
7486 extra modrm byte. */
7487 i
.sib
.index
= NO_INDEX_REGISTER
;
7489 else if (!i
.tm
.opcode_modifier
.vecsib
)
7491 if (i
.index_reg
->reg_num
== RegIZ
)
7492 i
.sib
.index
= NO_INDEX_REGISTER
;
7494 i
.sib
.index
= i
.index_reg
->reg_num
;
7495 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7496 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7501 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7502 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7506 if (!fake_zero_displacement
7510 fake_zero_displacement
= 1;
7511 if (i
.disp_encoding
== disp_encoding_8bit
)
7512 i
.types
[op
].bitfield
.disp8
= 1;
7514 i
.types
[op
].bitfield
.disp32
= 1;
7516 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7520 if (fake_zero_displacement
)
7522 /* Fakes a zero displacement assuming that i.types[op]
7523 holds the correct displacement size. */
7526 gas_assert (i
.op
[op
].disps
== 0);
7527 exp
= &disp_expressions
[i
.disp_operands
++];
7528 i
.op
[op
].disps
= exp
;
7529 exp
->X_op
= O_constant
;
7530 exp
->X_add_number
= 0;
7531 exp
->X_add_symbol
= (symbolS
*) 0;
7532 exp
->X_op_symbol
= (symbolS
*) 0;
7540 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7542 if (operand_type_check (i
.types
[0], imm
))
7543 i
.vex
.register_specifier
= NULL
;
7546 /* VEX.vvvv encodes one of the sources when the first
7547 operand is not an immediate. */
7548 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7549 i
.vex
.register_specifier
= i
.op
[0].regs
;
7551 i
.vex
.register_specifier
= i
.op
[1].regs
;
7554 /* Destination is a XMM register encoded in the ModRM.reg
7556 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7557 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7560 /* ModRM.rm and VEX.B encodes the other source. */
7561 if (!i
.mem_operands
)
7565 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7566 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7568 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7570 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7574 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7576 i
.vex
.register_specifier
= i
.op
[2].regs
;
7577 if (!i
.mem_operands
)
7580 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7581 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7585 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7586 (if any) based on i.tm.extension_opcode. Again, we must be
7587 careful to make sure that segment/control/debug/test/MMX
7588 registers are coded into the i.rm.reg field. */
7589 else if (i
.reg_operands
)
7592 unsigned int vex_reg
= ~0;
7594 for (op
= 0; op
< i
.operands
; op
++)
7596 if (i
.types
[op
].bitfield
.reg
7597 || i
.types
[op
].bitfield
.regbnd
7598 || i
.types
[op
].bitfield
.regmask
7599 || i
.types
[op
].bitfield
.sreg2
7600 || i
.types
[op
].bitfield
.sreg3
7601 || i
.types
[op
].bitfield
.control
7602 || i
.types
[op
].bitfield
.debug
7603 || i
.types
[op
].bitfield
.test
)
7605 if (i
.types
[op
].bitfield
.regsimd
)
7607 if (i
.types
[op
].bitfield
.zmmword
)
7608 i
.has_regzmm
= TRUE
;
7609 else if (i
.types
[op
].bitfield
.ymmword
)
7610 i
.has_regymm
= TRUE
;
7612 i
.has_regxmm
= TRUE
;
7615 if (i
.types
[op
].bitfield
.regmmx
)
7617 i
.has_regmmx
= TRUE
;
7624 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7626 /* For instructions with VexNDS, the register-only
7627 source operand is encoded in VEX prefix. */
7628 gas_assert (mem
!= (unsigned int) ~0);
7633 gas_assert (op
< i
.operands
);
7637 /* Check register-only source operand when two source
7638 operands are swapped. */
7639 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7640 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7644 gas_assert (mem
== (vex_reg
+ 1)
7645 && op
< i
.operands
);
7650 gas_assert (vex_reg
< i
.operands
);
7654 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7656 /* For instructions with VexNDD, the register destination
7657 is encoded in VEX prefix. */
7658 if (i
.mem_operands
== 0)
7660 /* There is no memory operand. */
7661 gas_assert ((op
+ 2) == i
.operands
);
7666 /* There are only 2 non-immediate operands. */
7667 gas_assert (op
< i
.imm_operands
+ 2
7668 && i
.operands
== i
.imm_operands
+ 2);
7669 vex_reg
= i
.imm_operands
+ 1;
7673 gas_assert (op
< i
.operands
);
7675 if (vex_reg
!= (unsigned int) ~0)
7677 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7679 if ((!type
->bitfield
.reg
7680 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7681 && !type
->bitfield
.regsimd
7682 && !operand_type_equal (type
, ®mask
))
7685 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7688 /* Don't set OP operand twice. */
7691 /* If there is an extension opcode to put here, the
7692 register number must be put into the regmem field. */
7693 if (i
.tm
.extension_opcode
!= None
)
7695 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7696 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7698 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7703 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7704 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7706 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7711 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7712 must set it to 3 to indicate this is a register operand
7713 in the regmem field. */
7714 if (!i
.mem_operands
)
7718 /* Fill in i.rm.reg field with extension opcode (if any). */
7719 if (i
.tm
.extension_opcode
!= None
)
7720 i
.rm
.reg
= i
.tm
.extension_opcode
;
7726 output_branch (void)
7732 relax_substateT subtype
;
7736 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7737 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7740 if (i
.prefix
[DATA_PREFIX
] != 0)
7746 /* Pentium4 branch hints. */
7747 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7748 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7753 if (i
.prefix
[REX_PREFIX
] != 0)
7759 /* BND prefixed jump. */
7760 if (i
.prefix
[BND_PREFIX
] != 0)
7762 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7766 if (i
.prefixes
!= 0 && !intel_syntax
)
7767 as_warn (_("skipping prefixes on this instruction"));
7769 /* It's always a symbol; End frag & setup for relax.
7770 Make sure there is enough room in this frag for the largest
7771 instruction we may generate in md_convert_frag. This is 2
7772 bytes for the opcode and room for the prefix and largest
7774 frag_grow (prefix
+ 2 + 4);
7775 /* Prefix and 1 opcode byte go in fr_fix. */
7776 p
= frag_more (prefix
+ 1);
7777 if (i
.prefix
[DATA_PREFIX
] != 0)
7778 *p
++ = DATA_PREFIX_OPCODE
;
7779 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7780 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7781 *p
++ = i
.prefix
[SEG_PREFIX
];
7782 if (i
.prefix
[REX_PREFIX
] != 0)
7783 *p
++ = i
.prefix
[REX_PREFIX
];
7784 *p
= i
.tm
.base_opcode
;
7786 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7787 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7788 else if (cpu_arch_flags
.bitfield
.cpui386
)
7789 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7791 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7794 sym
= i
.op
[0].disps
->X_add_symbol
;
7795 off
= i
.op
[0].disps
->X_add_number
;
7797 if (i
.op
[0].disps
->X_op
!= O_constant
7798 && i
.op
[0].disps
->X_op
!= O_symbol
)
7800 /* Handle complex expressions. */
7801 sym
= make_expr_symbol (i
.op
[0].disps
);
7805 /* 1 possible extra opcode + 4 byte displacement go in var part.
7806 Pass reloc in fr_var. */
7807 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7811 /* Return TRUE iff PLT32 relocation should be used for branching to
7815 need_plt32_p (symbolS
*s
)
7817 /* PLT32 relocation is ELF only. */
7822 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7823 krtld support it. */
7827 /* Since there is no need to prepare for PLT branch on x86-64, we
7828 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7829 be used as a marker for 32-bit PC-relative branches. */
7833 /* Weak or undefined symbol need PLT32 relocation. */
7834 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7837 /* Non-global symbol doesn't need PLT32 relocation. */
7838 if (! S_IS_EXTERNAL (s
))
7841 /* Other global symbols need PLT32 relocation. NB: Symbol with
7842 non-default visibilities are treated as normal global symbol
7843 so that PLT32 relocation can be used as a marker for 32-bit
7844 PC-relative branches. It is useful for linker relaxation. */
7855 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7857 if (i
.tm
.opcode_modifier
.jumpbyte
)
7859 /* This is a loop or jecxz type instruction. */
7861 if (i
.prefix
[ADDR_PREFIX
] != 0)
7863 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7866 /* Pentium4 branch hints. */
7867 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7868 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7870 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7879 if (flag_code
== CODE_16BIT
)
7882 if (i
.prefix
[DATA_PREFIX
] != 0)
7884 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7894 if (i
.prefix
[REX_PREFIX
] != 0)
7896 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7900 /* BND prefixed jump. */
7901 if (i
.prefix
[BND_PREFIX
] != 0)
7903 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7907 if (i
.prefixes
!= 0 && !intel_syntax
)
7908 as_warn (_("skipping prefixes on this instruction"));
7910 p
= frag_more (i
.tm
.opcode_length
+ size
);
7911 switch (i
.tm
.opcode_length
)
7914 *p
++ = i
.tm
.base_opcode
>> 8;
7917 *p
++ = i
.tm
.base_opcode
;
7923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7925 && jump_reloc
== NO_RELOC
7926 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7927 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7930 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7932 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7933 i
.op
[0].disps
, 1, jump_reloc
);
7935 /* All jumps handled here are signed, but don't use a signed limit
7936 check for 32 and 16 bit jumps as we want to allow wrap around at
7937 4G and 64k respectively. */
7939 fixP
->fx_signed
= 1;
7943 output_interseg_jump (void)
7951 if (flag_code
== CODE_16BIT
)
7955 if (i
.prefix
[DATA_PREFIX
] != 0)
7961 if (i
.prefix
[REX_PREFIX
] != 0)
7971 if (i
.prefixes
!= 0 && !intel_syntax
)
7972 as_warn (_("skipping prefixes on this instruction"));
7974 /* 1 opcode; 2 segment; offset */
7975 p
= frag_more (prefix
+ 1 + 2 + size
);
7977 if (i
.prefix
[DATA_PREFIX
] != 0)
7978 *p
++ = DATA_PREFIX_OPCODE
;
7980 if (i
.prefix
[REX_PREFIX
] != 0)
7981 *p
++ = i
.prefix
[REX_PREFIX
];
7983 *p
++ = i
.tm
.base_opcode
;
7984 if (i
.op
[1].imms
->X_op
== O_constant
)
7986 offsetT n
= i
.op
[1].imms
->X_add_number
;
7989 && !fits_in_unsigned_word (n
)
7990 && !fits_in_signed_word (n
))
7992 as_bad (_("16-bit jump out of range"));
7995 md_number_to_chars (p
, n
, size
);
7998 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7999 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8000 if (i
.op
[0].imms
->X_op
!= O_constant
)
8001 as_bad (_("can't handle non absolute segment in `%s'"),
8003 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8011 asection
*seg
= now_seg
;
8012 subsegT subseg
= now_subseg
;
8014 unsigned int alignment
, align_size_1
;
8015 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8016 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8017 unsigned int padding
;
8019 if (!IS_ELF
|| !x86_used_note
)
8022 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8024 /* The .note.gnu.property section layout:
8026 Field Length Contents
8029 n_descsz 4 The note descriptor size
8030 n_type 4 NT_GNU_PROPERTY_TYPE_0
8032 n_desc n_descsz The program property array
8036 /* Create the .note.gnu.property section. */
8037 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8038 bfd_set_section_flags (stdoutput
, sec
,
8045 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8056 bfd_set_section_alignment (stdoutput
, sec
, alignment
);
8057 elf_section_type (sec
) = SHT_NOTE
;
8059 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8061 isa_1_descsz_raw
= 4 + 4 + 4;
8062 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8063 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8065 feature_2_descsz_raw
= isa_1_descsz
;
8066 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8068 feature_2_descsz_raw
+= 4 + 4 + 4;
8069 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8070 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8073 descsz
= feature_2_descsz
;
8074 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8075 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8077 /* Write n_namsz. */
8078 md_number_to_chars (p
, (valueT
) 4, 4);
8080 /* Write n_descsz. */
8081 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8084 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8087 memcpy (p
+ 4 * 3, "GNU", 4);
8089 /* Write 4-byte type. */
8090 md_number_to_chars (p
+ 4 * 4,
8091 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8093 /* Write 4-byte data size. */
8094 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8096 /* Write 4-byte data. */
8097 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8099 /* Zero out paddings. */
8100 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8102 memset (p
+ 4 * 7, 0, padding
);
8104 /* Write 4-byte type. */
8105 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8106 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8108 /* Write 4-byte data size. */
8109 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8111 /* Write 4-byte data. */
8112 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8113 (valueT
) x86_feature_2_used
, 4);
8115 /* Zero out paddings. */
8116 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8118 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8120 /* We probably can't restore the current segment, for there likely
8123 subseg_set (seg
, subseg
);
8130 fragS
*insn_start_frag
;
8131 offsetT insn_start_off
;
8133 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8134 if (IS_ELF
&& x86_used_note
)
8136 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8137 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8138 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8139 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8140 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8141 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8142 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8143 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8144 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8145 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8146 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8147 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8148 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8149 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8150 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8151 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8152 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8153 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8154 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8155 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8156 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8157 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8158 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8159 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8160 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8161 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8162 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8163 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8164 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8165 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8166 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8167 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8168 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8169 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8170 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8171 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8172 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8173 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8174 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8175 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8176 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8177 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8178 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8179 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8180 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8181 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8182 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8183 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8184 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8185 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8187 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8188 || i
.tm
.cpu_flags
.bitfield
.cpu287
8189 || i
.tm
.cpu_flags
.bitfield
.cpu387
8190 || i
.tm
.cpu_flags
.bitfield
.cpu687
8191 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8192 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8193 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8194 Xfence instructions. */
8195 if (i
.tm
.base_opcode
!= 0xf18
8196 && i
.tm
.base_opcode
!= 0xf0d
8197 && i
.tm
.base_opcode
!= 0xfae
8199 || i
.tm
.cpu_flags
.bitfield
.cpummx
8200 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8201 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8202 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8204 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8206 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8208 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8209 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8210 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8211 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8212 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8213 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8214 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8215 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8216 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8220 /* Tie dwarf2 debug info to the address at the start of the insn.
8221 We can't do this after the insn has been output as the current
8222 frag may have been closed off. eg. by frag_var. */
8223 dwarf2_emit_insn (0);
8225 insn_start_frag
= frag_now
;
8226 insn_start_off
= frag_now_fix ();
8229 if (i
.tm
.opcode_modifier
.jump
)
8231 else if (i
.tm
.opcode_modifier
.jumpbyte
8232 || i
.tm
.opcode_modifier
.jumpdword
)
8234 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8235 output_interseg_jump ();
8238 /* Output normal instructions here. */
8242 unsigned int prefix
;
8245 && i
.tm
.base_opcode
== 0xfae
8247 && i
.imm_operands
== 1
8248 && (i
.op
[0].imms
->X_add_number
== 0xe8
8249 || i
.op
[0].imms
->X_add_number
== 0xf0
8250 || i
.op
[0].imms
->X_add_number
== 0xf8))
8252 /* Encode lfence, mfence, and sfence as
8253 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8254 offsetT val
= 0x240483f0ULL
;
8256 md_number_to_chars (p
, val
, 5);
8260 /* Some processors fail on LOCK prefix. This options makes
8261 assembler ignore LOCK prefix and serves as a workaround. */
8262 if (omit_lock_prefix
)
8264 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8266 i
.prefix
[LOCK_PREFIX
] = 0;
8269 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8270 don't need the explicit prefix. */
8271 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8273 switch (i
.tm
.opcode_length
)
8276 if (i
.tm
.base_opcode
& 0xff000000)
8278 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8279 add_prefix (prefix
);
8283 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8285 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8286 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8287 || prefix
!= REPE_PREFIX_OPCODE
8288 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8289 add_prefix (prefix
);
8295 /* Check for pseudo prefixes. */
8296 as_bad_where (insn_start_frag
->fr_file
,
8297 insn_start_frag
->fr_line
,
8298 _("pseudo prefix without instruction"));
8304 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8305 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8306 R_X86_64_GOTTPOFF relocation so that linker can safely
8307 perform IE->LE optimization. */
8308 if (x86_elf_abi
== X86_64_X32_ABI
8310 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8311 && i
.prefix
[REX_PREFIX
] == 0)
8312 add_prefix (REX_OPCODE
);
8315 /* The prefix bytes. */
8316 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8318 FRAG_APPEND_1_CHAR (*q
);
8322 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8327 /* REX byte is encoded in VEX prefix. */
8331 FRAG_APPEND_1_CHAR (*q
);
8334 /* There should be no other prefixes for instructions
8339 /* For EVEX instructions i.vrex should become 0 after
8340 build_evex_prefix. For VEX instructions upper 16 registers
8341 aren't available, so VREX should be 0. */
8344 /* Now the VEX prefix. */
8345 p
= frag_more (i
.vex
.length
);
8346 for (j
= 0; j
< i
.vex
.length
; j
++)
8347 p
[j
] = i
.vex
.bytes
[j
];
8350 /* Now the opcode; be careful about word order here! */
8351 if (i
.tm
.opcode_length
== 1)
8353 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8357 switch (i
.tm
.opcode_length
)
8361 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8362 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8366 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8376 /* Put out high byte first: can't use md_number_to_chars! */
8377 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8378 *p
= i
.tm
.base_opcode
& 0xff;
8381 /* Now the modrm byte and sib byte (if present). */
8382 if (i
.tm
.opcode_modifier
.modrm
)
8384 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8387 /* If i.rm.regmem == ESP (4)
8388 && i.rm.mode != (Register mode)
8390 ==> need second modrm byte. */
8391 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8393 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8394 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8396 | i
.sib
.scale
<< 6));
8399 if (i
.disp_operands
)
8400 output_disp (insn_start_frag
, insn_start_off
);
8403 output_imm (insn_start_frag
, insn_start_off
);
8409 pi ("" /*line*/, &i
);
8411 #endif /* DEBUG386 */
8414 /* Return the size of the displacement operand N. */
8417 disp_size (unsigned int n
)
8421 if (i
.types
[n
].bitfield
.disp64
)
8423 else if (i
.types
[n
].bitfield
.disp8
)
8425 else if (i
.types
[n
].bitfield
.disp16
)
8430 /* Return the size of the immediate operand N. */
8433 imm_size (unsigned int n
)
8436 if (i
.types
[n
].bitfield
.imm64
)
8438 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8440 else if (i
.types
[n
].bitfield
.imm16
)
8446 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8451 for (n
= 0; n
< i
.operands
; n
++)
8453 if (operand_type_check (i
.types
[n
], disp
))
8455 if (i
.op
[n
].disps
->X_op
== O_constant
)
8457 int size
= disp_size (n
);
8458 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8460 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8462 p
= frag_more (size
);
8463 md_number_to_chars (p
, val
, size
);
8467 enum bfd_reloc_code_real reloc_type
;
8468 int size
= disp_size (n
);
8469 int sign
= i
.types
[n
].bitfield
.disp32s
;
8470 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8473 /* We can't have 8 bit displacement here. */
8474 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8476 /* The PC relative address is computed relative
8477 to the instruction boundary, so in case immediate
8478 fields follows, we need to adjust the value. */
8479 if (pcrel
&& i
.imm_operands
)
8484 for (n1
= 0; n1
< i
.operands
; n1
++)
8485 if (operand_type_check (i
.types
[n1
], imm
))
8487 /* Only one immediate is allowed for PC
8488 relative address. */
8489 gas_assert (sz
== 0);
8491 i
.op
[n
].disps
->X_add_number
-= sz
;
8493 /* We should find the immediate. */
8494 gas_assert (sz
!= 0);
8497 p
= frag_more (size
);
8498 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8500 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8501 && (((reloc_type
== BFD_RELOC_32
8502 || reloc_type
== BFD_RELOC_X86_64_32S
8503 || (reloc_type
== BFD_RELOC_64
8505 && (i
.op
[n
].disps
->X_op
== O_symbol
8506 || (i
.op
[n
].disps
->X_op
== O_add
8507 && ((symbol_get_value_expression
8508 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8510 || reloc_type
== BFD_RELOC_32_PCREL
))
8514 if (insn_start_frag
== frag_now
)
8515 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8520 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8521 for (fr
= insn_start_frag
->fr_next
;
8522 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8524 add
+= p
- frag_now
->fr_literal
;
8529 reloc_type
= BFD_RELOC_386_GOTPC
;
8530 i
.op
[n
].imms
->X_add_number
+= add
;
8532 else if (reloc_type
== BFD_RELOC_64
)
8533 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8535 /* Don't do the adjustment for x86-64, as there
8536 the pcrel addressing is relative to the _next_
8537 insn, and that is taken care of in other code. */
8538 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8540 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8541 size
, i
.op
[n
].disps
, pcrel
,
8543 /* Check for "call/jmp *mem", "mov mem, %reg",
8544 "test %reg, mem" and "binop mem, %reg" where binop
8545 is one of adc, add, and, cmp, or, sbb, sub, xor
8546 instructions without data prefix. Always generate
8547 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8548 if (i
.prefix
[DATA_PREFIX
] == 0
8549 && (generate_relax_relocations
8552 && i
.rm
.regmem
== 5))
8554 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8555 && ((i
.operands
== 1
8556 && i
.tm
.base_opcode
== 0xff
8557 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8559 && (i
.tm
.base_opcode
== 0x8b
8560 || i
.tm
.base_opcode
== 0x85
8561 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8565 fixP
->fx_tcbit
= i
.rex
!= 0;
8567 && (i
.base_reg
->reg_num
== RegIP
))
8568 fixP
->fx_tcbit2
= 1;
8571 fixP
->fx_tcbit2
= 1;
8579 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8584 for (n
= 0; n
< i
.operands
; n
++)
8586 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8587 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8590 if (operand_type_check (i
.types
[n
], imm
))
8592 if (i
.op
[n
].imms
->X_op
== O_constant
)
8594 int size
= imm_size (n
);
8597 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8599 p
= frag_more (size
);
8600 md_number_to_chars (p
, val
, size
);
8604 /* Not absolute_section.
8605 Need a 32-bit fixup (don't support 8bit
8606 non-absolute imms). Try to support other
8608 enum bfd_reloc_code_real reloc_type
;
8609 int size
= imm_size (n
);
8612 if (i
.types
[n
].bitfield
.imm32s
8613 && (i
.suffix
== QWORD_MNEM_SUFFIX
8614 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8619 p
= frag_more (size
);
8620 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8622 /* This is tough to explain. We end up with this one if we
8623 * have operands that look like
8624 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8625 * obtain the absolute address of the GOT, and it is strongly
8626 * preferable from a performance point of view to avoid using
8627 * a runtime relocation for this. The actual sequence of
8628 * instructions often look something like:
8633 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8635 * The call and pop essentially return the absolute address
8636 * of the label .L66 and store it in %ebx. The linker itself
8637 * will ultimately change the first operand of the addl so
8638 * that %ebx points to the GOT, but to keep things simple, the
8639 * .o file must have this operand set so that it generates not
8640 * the absolute address of .L66, but the absolute address of
8641 * itself. This allows the linker itself simply treat a GOTPC
8642 * relocation as asking for a pcrel offset to the GOT to be
8643 * added in, and the addend of the relocation is stored in the
8644 * operand field for the instruction itself.
8646 * Our job here is to fix the operand so that it would add
8647 * the correct offset so that %ebx would point to itself. The
8648 * thing that is tricky is that .-.L66 will point to the
8649 * beginning of the instruction, so we need to further modify
8650 * the operand so that it will point to itself. There are
8651 * other cases where you have something like:
8653 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8655 * and here no correction would be required. Internally in
8656 * the assembler we treat operands of this form as not being
8657 * pcrel since the '.' is explicitly mentioned, and I wonder
8658 * whether it would simplify matters to do it this way. Who
8659 * knows. In earlier versions of the PIC patches, the
8660 * pcrel_adjust field was used to store the correction, but
8661 * since the expression is not pcrel, I felt it would be
8662 * confusing to do it this way. */
8664 if ((reloc_type
== BFD_RELOC_32
8665 || reloc_type
== BFD_RELOC_X86_64_32S
8666 || reloc_type
== BFD_RELOC_64
)
8668 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8669 && (i
.op
[n
].imms
->X_op
== O_symbol
8670 || (i
.op
[n
].imms
->X_op
== O_add
8671 && ((symbol_get_value_expression
8672 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8677 if (insn_start_frag
== frag_now
)
8678 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
8683 add
= insn_start_frag
->fr_fix
- insn_start_off
;
8684 for (fr
= insn_start_frag
->fr_next
;
8685 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
8687 add
+= p
- frag_now
->fr_literal
;
8691 reloc_type
= BFD_RELOC_386_GOTPC
;
8693 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8695 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8696 i
.op
[n
].imms
->X_add_number
+= add
;
8698 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8699 i
.op
[n
].imms
, 0, reloc_type
);
8705 /* x86_cons_fix_new is called via the expression parsing code when a
8706 reloc is needed. We use this hook to get the correct .got reloc. */
8707 static int cons_sign
= -1;
8710 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8711 expressionS
*exp
, bfd_reloc_code_real_type r
)
8713 r
= reloc (len
, 0, cons_sign
, r
);
8716 if (exp
->X_op
== O_secrel
)
8718 exp
->X_op
= O_symbol
;
8719 r
= BFD_RELOC_32_SECREL
;
8723 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8726 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8727 purpose of the `.dc.a' internal pseudo-op. */
8730 x86_address_bytes (void)
8732 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8734 return stdoutput
->arch_info
->bits_per_address
/ 8;
8737 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8739 # define lex_got(reloc, adjust, types) NULL
8741 /* Parse operands of the form
8742 <symbol>@GOTOFF+<nnn>
8743 and similar .plt or .got references.
8745 If we find one, set up the correct relocation in RELOC and copy the
8746 input string, minus the `@GOTOFF' into a malloc'd buffer for
8747 parsing by the calling routine. Return this buffer, and if ADJUST
8748 is non-null set it to the length of the string we removed from the
8749 input line. Otherwise return NULL. */
8751 lex_got (enum bfd_reloc_code_real
*rel
,
8753 i386_operand_type
*types
)
8755 /* Some of the relocations depend on the size of what field is to
8756 be relocated. But in our callers i386_immediate and i386_displacement
8757 we don't yet know the operand size (this will be set by insn
8758 matching). Hence we record the word32 relocation here,
8759 and adjust the reloc according to the real size in reloc(). */
8760 static const struct {
8763 const enum bfd_reloc_code_real rel
[2];
8764 const i386_operand_type types64
;
8766 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8767 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8769 OPERAND_TYPE_IMM32_64
},
8771 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8772 BFD_RELOC_X86_64_PLTOFF64
},
8773 OPERAND_TYPE_IMM64
},
8774 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8775 BFD_RELOC_X86_64_PLT32
},
8776 OPERAND_TYPE_IMM32_32S_DISP32
},
8777 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8778 BFD_RELOC_X86_64_GOTPLT64
},
8779 OPERAND_TYPE_IMM64_DISP64
},
8780 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8781 BFD_RELOC_X86_64_GOTOFF64
},
8782 OPERAND_TYPE_IMM64_DISP64
},
8783 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8784 BFD_RELOC_X86_64_GOTPCREL
},
8785 OPERAND_TYPE_IMM32_32S_DISP32
},
8786 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8787 BFD_RELOC_X86_64_TLSGD
},
8788 OPERAND_TYPE_IMM32_32S_DISP32
},
8789 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8790 _dummy_first_bfd_reloc_code_real
},
8791 OPERAND_TYPE_NONE
},
8792 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8793 BFD_RELOC_X86_64_TLSLD
},
8794 OPERAND_TYPE_IMM32_32S_DISP32
},
8795 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8796 BFD_RELOC_X86_64_GOTTPOFF
},
8797 OPERAND_TYPE_IMM32_32S_DISP32
},
8798 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8799 BFD_RELOC_X86_64_TPOFF32
},
8800 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8801 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8802 _dummy_first_bfd_reloc_code_real
},
8803 OPERAND_TYPE_NONE
},
8804 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8805 BFD_RELOC_X86_64_DTPOFF32
},
8806 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8807 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8808 _dummy_first_bfd_reloc_code_real
},
8809 OPERAND_TYPE_NONE
},
8810 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8811 _dummy_first_bfd_reloc_code_real
},
8812 OPERAND_TYPE_NONE
},
8813 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8814 BFD_RELOC_X86_64_GOT32
},
8815 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8816 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8817 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8818 OPERAND_TYPE_IMM32_32S_DISP32
},
8819 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8820 BFD_RELOC_X86_64_TLSDESC_CALL
},
8821 OPERAND_TYPE_IMM32_32S_DISP32
},
8826 #if defined (OBJ_MAYBE_ELF)
8831 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8832 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8835 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8837 int len
= gotrel
[j
].len
;
8838 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8840 if (gotrel
[j
].rel
[object_64bit
] != 0)
8843 char *tmpbuf
, *past_reloc
;
8845 *rel
= gotrel
[j
].rel
[object_64bit
];
8849 if (flag_code
!= CODE_64BIT
)
8851 types
->bitfield
.imm32
= 1;
8852 types
->bitfield
.disp32
= 1;
8855 *types
= gotrel
[j
].types64
;
8858 if (j
!= 0 && GOT_symbol
== NULL
)
8859 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8861 /* The length of the first part of our input line. */
8862 first
= cp
- input_line_pointer
;
8864 /* The second part goes from after the reloc token until
8865 (and including) an end_of_line char or comma. */
8866 past_reloc
= cp
+ 1 + len
;
8868 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8870 second
= cp
+ 1 - past_reloc
;
8872 /* Allocate and copy string. The trailing NUL shouldn't
8873 be necessary, but be safe. */
8874 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8875 memcpy (tmpbuf
, input_line_pointer
, first
);
8876 if (second
!= 0 && *past_reloc
!= ' ')
8877 /* Replace the relocation token with ' ', so that
8878 errors like foo@GOTOFF1 will be detected. */
8879 tmpbuf
[first
++] = ' ';
8881 /* Increment length by 1 if the relocation token is
8886 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8887 tmpbuf
[first
+ second
] = '\0';
8891 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8892 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8897 /* Might be a symbol version string. Don't as_bad here. */
8906 /* Parse operands of the form
8907 <symbol>@SECREL32+<nnn>
8909 If we find one, set up the correct relocation in RELOC and copy the
8910 input string, minus the `@SECREL32' into a malloc'd buffer for
8911 parsing by the calling routine. Return this buffer, and if ADJUST
8912 is non-null set it to the length of the string we removed from the
8913 input line. Otherwise return NULL.
8915 This function is copied from the ELF version above adjusted for PE targets. */
8918 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8919 int *adjust ATTRIBUTE_UNUSED
,
8920 i386_operand_type
*types
)
8926 const enum bfd_reloc_code_real rel
[2];
8927 const i386_operand_type types64
;
8931 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8932 BFD_RELOC_32_SECREL
},
8933 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8939 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8940 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8943 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8945 int len
= gotrel
[j
].len
;
8947 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8949 if (gotrel
[j
].rel
[object_64bit
] != 0)
8952 char *tmpbuf
, *past_reloc
;
8954 *rel
= gotrel
[j
].rel
[object_64bit
];
8960 if (flag_code
!= CODE_64BIT
)
8962 types
->bitfield
.imm32
= 1;
8963 types
->bitfield
.disp32
= 1;
8966 *types
= gotrel
[j
].types64
;
8969 /* The length of the first part of our input line. */
8970 first
= cp
- input_line_pointer
;
8972 /* The second part goes from after the reloc token until
8973 (and including) an end_of_line char or comma. */
8974 past_reloc
= cp
+ 1 + len
;
8976 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8978 second
= cp
+ 1 - past_reloc
;
8980 /* Allocate and copy string. The trailing NUL shouldn't
8981 be necessary, but be safe. */
8982 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8983 memcpy (tmpbuf
, input_line_pointer
, first
);
8984 if (second
!= 0 && *past_reloc
!= ' ')
8985 /* Replace the relocation token with ' ', so that
8986 errors like foo@SECLREL321 will be detected. */
8987 tmpbuf
[first
++] = ' ';
8988 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8989 tmpbuf
[first
+ second
] = '\0';
8993 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8994 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8999 /* Might be a symbol version string. Don't as_bad here. */
9005 bfd_reloc_code_real_type
9006 x86_cons (expressionS
*exp
, int size
)
9008 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9010 intel_syntax
= -intel_syntax
;
9013 if (size
== 4 || (object_64bit
&& size
== 8))
9015 /* Handle @GOTOFF and the like in an expression. */
9017 char *gotfree_input_line
;
9020 save
= input_line_pointer
;
9021 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9022 if (gotfree_input_line
)
9023 input_line_pointer
= gotfree_input_line
;
9027 if (gotfree_input_line
)
9029 /* expression () has merrily parsed up to the end of line,
9030 or a comma - in the wrong buffer. Transfer how far
9031 input_line_pointer has moved to the right buffer. */
9032 input_line_pointer
= (save
9033 + (input_line_pointer
- gotfree_input_line
)
9035 free (gotfree_input_line
);
9036 if (exp
->X_op
== O_constant
9037 || exp
->X_op
== O_absent
9038 || exp
->X_op
== O_illegal
9039 || exp
->X_op
== O_register
9040 || exp
->X_op
== O_big
)
9042 char c
= *input_line_pointer
;
9043 *input_line_pointer
= 0;
9044 as_bad (_("missing or invalid expression `%s'"), save
);
9045 *input_line_pointer
= c
;
9047 else if ((got_reloc
== BFD_RELOC_386_PLT32
9048 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9049 && exp
->X_op
!= O_symbol
)
9051 char c
= *input_line_pointer
;
9052 *input_line_pointer
= 0;
9053 as_bad (_("invalid PLT expression `%s'"), save
);
9054 *input_line_pointer
= c
;
9061 intel_syntax
= -intel_syntax
;
9064 i386_intel_simplify (exp
);
9070 signed_cons (int size
)
9072 if (flag_code
== CODE_64BIT
)
9080 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9087 if (exp
.X_op
== O_symbol
)
9088 exp
.X_op
= O_secrel
;
9090 emit_expr (&exp
, 4);
9092 while (*input_line_pointer
++ == ',');
9094 input_line_pointer
--;
9095 demand_empty_rest_of_line ();
9099 /* Handle Vector operations. */
9102 check_VecOperations (char *op_string
, char *op_end
)
9104 const reg_entry
*mask
;
9109 && (op_end
== NULL
|| op_string
< op_end
))
9112 if (*op_string
== '{')
9116 /* Check broadcasts. */
9117 if (strncmp (op_string
, "1to", 3) == 0)
9122 goto duplicated_vec_op
;
9125 if (*op_string
== '8')
9127 else if (*op_string
== '4')
9129 else if (*op_string
== '2')
9131 else if (*op_string
== '1'
9132 && *(op_string
+1) == '6')
9139 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9144 broadcast_op
.type
= bcst_type
;
9145 broadcast_op
.operand
= this_operand
;
9146 broadcast_op
.bytes
= 0;
9147 i
.broadcast
= &broadcast_op
;
9149 /* Check masking operation. */
9150 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9152 /* k0 can't be used for write mask. */
9153 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9155 as_bad (_("`%s%s' can't be used for write mask"),
9156 register_prefix
, mask
->reg_name
);
9162 mask_op
.mask
= mask
;
9163 mask_op
.zeroing
= 0;
9164 mask_op
.operand
= this_operand
;
9170 goto duplicated_vec_op
;
9172 i
.mask
->mask
= mask
;
9174 /* Only "{z}" is allowed here. No need to check
9175 zeroing mask explicitly. */
9176 if (i
.mask
->operand
!= this_operand
)
9178 as_bad (_("invalid write mask `%s'"), saved
);
9185 /* Check zeroing-flag for masking operation. */
9186 else if (*op_string
== 'z')
9190 mask_op
.mask
= NULL
;
9191 mask_op
.zeroing
= 1;
9192 mask_op
.operand
= this_operand
;
9197 if (i
.mask
->zeroing
)
9200 as_bad (_("duplicated `%s'"), saved
);
9204 i
.mask
->zeroing
= 1;
9206 /* Only "{%k}" is allowed here. No need to check mask
9207 register explicitly. */
9208 if (i
.mask
->operand
!= this_operand
)
9210 as_bad (_("invalid zeroing-masking `%s'"),
9219 goto unknown_vec_op
;
9221 if (*op_string
!= '}')
9223 as_bad (_("missing `}' in `%s'"), saved
);
9228 /* Strip whitespace since the addition of pseudo prefixes
9229 changed how the scrubber treats '{'. */
9230 if (is_space_char (*op_string
))
9236 /* We don't know this one. */
9237 as_bad (_("unknown vector operation: `%s'"), saved
);
9241 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9243 as_bad (_("zeroing-masking only allowed with write mask"));
9251 i386_immediate (char *imm_start
)
9253 char *save_input_line_pointer
;
9254 char *gotfree_input_line
;
9257 i386_operand_type types
;
9259 operand_type_set (&types
, ~0);
9261 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9263 as_bad (_("at most %d immediate operands are allowed"),
9264 MAX_IMMEDIATE_OPERANDS
);
9268 exp
= &im_expressions
[i
.imm_operands
++];
9269 i
.op
[this_operand
].imms
= exp
;
9271 if (is_space_char (*imm_start
))
9274 save_input_line_pointer
= input_line_pointer
;
9275 input_line_pointer
= imm_start
;
9277 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9278 if (gotfree_input_line
)
9279 input_line_pointer
= gotfree_input_line
;
9281 exp_seg
= expression (exp
);
9285 /* Handle vector operations. */
9286 if (*input_line_pointer
== '{')
9288 input_line_pointer
= check_VecOperations (input_line_pointer
,
9290 if (input_line_pointer
== NULL
)
9294 if (*input_line_pointer
)
9295 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9297 input_line_pointer
= save_input_line_pointer
;
9298 if (gotfree_input_line
)
9300 free (gotfree_input_line
);
9302 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9303 exp
->X_op
= O_illegal
;
9306 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9310 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9311 i386_operand_type types
, const char *imm_start
)
9313 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9316 as_bad (_("missing or invalid immediate expression `%s'"),
9320 else if (exp
->X_op
== O_constant
)
9322 /* Size it properly later. */
9323 i
.types
[this_operand
].bitfield
.imm64
= 1;
9324 /* If not 64bit, sign extend val. */
9325 if (flag_code
!= CODE_64BIT
9326 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9328 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9330 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9331 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9332 && exp_seg
!= absolute_section
9333 && exp_seg
!= text_section
9334 && exp_seg
!= data_section
9335 && exp_seg
!= bss_section
9336 && exp_seg
!= undefined_section
9337 && !bfd_is_com_section (exp_seg
))
9339 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9343 else if (!intel_syntax
&& exp_seg
== reg_section
)
9346 as_bad (_("illegal immediate register operand %s"), imm_start
);
9351 /* This is an address. The size of the address will be
9352 determined later, depending on destination register,
9353 suffix, or the default for the section. */
9354 i
.types
[this_operand
].bitfield
.imm8
= 1;
9355 i
.types
[this_operand
].bitfield
.imm16
= 1;
9356 i
.types
[this_operand
].bitfield
.imm32
= 1;
9357 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9358 i
.types
[this_operand
].bitfield
.imm64
= 1;
9359 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9367 i386_scale (char *scale
)
9370 char *save
= input_line_pointer
;
9372 input_line_pointer
= scale
;
9373 val
= get_absolute_expression ();
9378 i
.log2_scale_factor
= 0;
9381 i
.log2_scale_factor
= 1;
9384 i
.log2_scale_factor
= 2;
9387 i
.log2_scale_factor
= 3;
9391 char sep
= *input_line_pointer
;
9393 *input_line_pointer
= '\0';
9394 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9396 *input_line_pointer
= sep
;
9397 input_line_pointer
= save
;
9401 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9403 as_warn (_("scale factor of %d without an index register"),
9404 1 << i
.log2_scale_factor
);
9405 i
.log2_scale_factor
= 0;
9407 scale
= input_line_pointer
;
9408 input_line_pointer
= save
;
9413 i386_displacement (char *disp_start
, char *disp_end
)
9417 char *save_input_line_pointer
;
9418 char *gotfree_input_line
;
9420 i386_operand_type bigdisp
, types
= anydisp
;
9423 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9425 as_bad (_("at most %d displacement operands are allowed"),
9426 MAX_MEMORY_OPERANDS
);
9430 operand_type_set (&bigdisp
, 0);
9431 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9432 || (!current_templates
->start
->opcode_modifier
.jump
9433 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9435 bigdisp
.bitfield
.disp32
= 1;
9436 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9437 if (flag_code
== CODE_64BIT
)
9441 bigdisp
.bitfield
.disp32s
= 1;
9442 bigdisp
.bitfield
.disp64
= 1;
9445 else if ((flag_code
== CODE_16BIT
) ^ override
)
9447 bigdisp
.bitfield
.disp32
= 0;
9448 bigdisp
.bitfield
.disp16
= 1;
9453 /* For PC-relative branches, the width of the displacement
9454 is dependent upon data size, not address size. */
9455 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9456 if (flag_code
== CODE_64BIT
)
9458 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9459 bigdisp
.bitfield
.disp16
= 1;
9462 bigdisp
.bitfield
.disp32
= 1;
9463 bigdisp
.bitfield
.disp32s
= 1;
9469 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9471 : LONG_MNEM_SUFFIX
));
9472 bigdisp
.bitfield
.disp32
= 1;
9473 if ((flag_code
== CODE_16BIT
) ^ override
)
9475 bigdisp
.bitfield
.disp32
= 0;
9476 bigdisp
.bitfield
.disp16
= 1;
9480 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9483 exp
= &disp_expressions
[i
.disp_operands
];
9484 i
.op
[this_operand
].disps
= exp
;
9486 save_input_line_pointer
= input_line_pointer
;
9487 input_line_pointer
= disp_start
;
9488 END_STRING_AND_SAVE (disp_end
);
9490 #ifndef GCC_ASM_O_HACK
9491 #define GCC_ASM_O_HACK 0
9494 END_STRING_AND_SAVE (disp_end
+ 1);
9495 if (i
.types
[this_operand
].bitfield
.baseIndex
9496 && displacement_string_end
[-1] == '+')
9498 /* This hack is to avoid a warning when using the "o"
9499 constraint within gcc asm statements.
9502 #define _set_tssldt_desc(n,addr,limit,type) \
9503 __asm__ __volatile__ ( \
9505 "movw %w1,2+%0\n\t" \
9507 "movb %b1,4+%0\n\t" \
9508 "movb %4,5+%0\n\t" \
9509 "movb $0,6+%0\n\t" \
9510 "movb %h1,7+%0\n\t" \
9512 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9514 This works great except that the output assembler ends
9515 up looking a bit weird if it turns out that there is
9516 no offset. You end up producing code that looks like:
9529 So here we provide the missing zero. */
9531 *displacement_string_end
= '0';
9534 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9535 if (gotfree_input_line
)
9536 input_line_pointer
= gotfree_input_line
;
9538 exp_seg
= expression (exp
);
9541 if (*input_line_pointer
)
9542 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9544 RESTORE_END_STRING (disp_end
+ 1);
9546 input_line_pointer
= save_input_line_pointer
;
9547 if (gotfree_input_line
)
9549 free (gotfree_input_line
);
9551 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9552 exp
->X_op
= O_illegal
;
9555 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9557 RESTORE_END_STRING (disp_end
);
9563 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9564 i386_operand_type types
, const char *disp_start
)
9566 i386_operand_type bigdisp
;
9569 /* We do this to make sure that the section symbol is in
9570 the symbol table. We will ultimately change the relocation
9571 to be relative to the beginning of the section. */
9572 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9573 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9574 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9576 if (exp
->X_op
!= O_symbol
)
9579 if (S_IS_LOCAL (exp
->X_add_symbol
)
9580 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9581 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9582 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9583 exp
->X_op
= O_subtract
;
9584 exp
->X_op_symbol
= GOT_symbol
;
9585 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9586 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9587 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9588 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9590 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9593 else if (exp
->X_op
== O_absent
9594 || exp
->X_op
== O_illegal
9595 || exp
->X_op
== O_big
)
9598 as_bad (_("missing or invalid displacement expression `%s'"),
9603 else if (flag_code
== CODE_64BIT
9604 && !i
.prefix
[ADDR_PREFIX
]
9605 && exp
->X_op
== O_constant
)
9607 /* Since displacement is signed extended to 64bit, don't allow
9608 disp32 and turn off disp32s if they are out of range. */
9609 i
.types
[this_operand
].bitfield
.disp32
= 0;
9610 if (!fits_in_signed_long (exp
->X_add_number
))
9612 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9613 if (i
.types
[this_operand
].bitfield
.baseindex
)
9615 as_bad (_("0x%lx out range of signed 32bit displacement"),
9616 (long) exp
->X_add_number
);
9622 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9623 else if (exp
->X_op
!= O_constant
9624 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9625 && exp_seg
!= absolute_section
9626 && exp_seg
!= text_section
9627 && exp_seg
!= data_section
9628 && exp_seg
!= bss_section
9629 && exp_seg
!= undefined_section
9630 && !bfd_is_com_section (exp_seg
))
9632 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9637 /* Check if this is a displacement only operand. */
9638 bigdisp
= i
.types
[this_operand
];
9639 bigdisp
.bitfield
.disp8
= 0;
9640 bigdisp
.bitfield
.disp16
= 0;
9641 bigdisp
.bitfield
.disp32
= 0;
9642 bigdisp
.bitfield
.disp32s
= 0;
9643 bigdisp
.bitfield
.disp64
= 0;
9644 if (operand_type_all_zero (&bigdisp
))
9645 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9651 /* Return the active addressing mode, taking address override and
9652 registers forming the address into consideration. Update the
9653 address override prefix if necessary. */
9655 static enum flag_code
9656 i386_addressing_mode (void)
9658 enum flag_code addr_mode
;
9660 if (i
.prefix
[ADDR_PREFIX
])
9661 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9664 addr_mode
= flag_code
;
9666 #if INFER_ADDR_PREFIX
9667 if (i
.mem_operands
== 0)
9669 /* Infer address prefix from the first memory operand. */
9670 const reg_entry
*addr_reg
= i
.base_reg
;
9672 if (addr_reg
== NULL
)
9673 addr_reg
= i
.index_reg
;
9677 if (addr_reg
->reg_type
.bitfield
.dword
)
9678 addr_mode
= CODE_32BIT
;
9679 else if (flag_code
!= CODE_64BIT
9680 && addr_reg
->reg_type
.bitfield
.word
)
9681 addr_mode
= CODE_16BIT
;
9683 if (addr_mode
!= flag_code
)
9685 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9687 /* Change the size of any displacement too. At most one
9688 of Disp16 or Disp32 is set.
9689 FIXME. There doesn't seem to be any real need for
9690 separate Disp16 and Disp32 flags. The same goes for
9691 Imm16 and Imm32. Removing them would probably clean
9692 up the code quite a lot. */
9693 if (flag_code
!= CODE_64BIT
9694 && (i
.types
[this_operand
].bitfield
.disp16
9695 || i
.types
[this_operand
].bitfield
.disp32
))
9696 i
.types
[this_operand
]
9697 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9707 /* Make sure the memory operand we've been dealt is valid.
9708 Return 1 on success, 0 on a failure. */
9711 i386_index_check (const char *operand_string
)
9713 const char *kind
= "base/index";
9714 enum flag_code addr_mode
= i386_addressing_mode ();
9716 if (current_templates
->start
->opcode_modifier
.isstring
9717 && !current_templates
->start
->opcode_modifier
.immext
9718 && (current_templates
->end
[-1].opcode_modifier
.isstring
9721 /* Memory operands of string insns are special in that they only allow
9722 a single register (rDI, rSI, or rBX) as their memory address. */
9723 const reg_entry
*expected_reg
;
9724 static const char *di_si
[][2] =
9730 static const char *bx
[] = { "ebx", "bx", "rbx" };
9732 kind
= "string address";
9734 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9736 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9738 if (!type
.bitfield
.baseindex
9739 || ((!i
.mem_operands
!= !intel_syntax
)
9740 && current_templates
->end
[-1].operand_types
[1]
9741 .bitfield
.baseindex
))
9742 type
= current_templates
->end
[-1].operand_types
[1];
9743 expected_reg
= hash_find (reg_hash
,
9744 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9748 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9750 if (i
.base_reg
!= expected_reg
9752 || operand_type_check (i
.types
[this_operand
], disp
))
9754 /* The second memory operand must have the same size as
9758 && !((addr_mode
== CODE_64BIT
9759 && i
.base_reg
->reg_type
.bitfield
.qword
)
9760 || (addr_mode
== CODE_32BIT
9761 ? i
.base_reg
->reg_type
.bitfield
.dword
9762 : i
.base_reg
->reg_type
.bitfield
.word
)))
9765 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9767 intel_syntax
? '[' : '(',
9769 expected_reg
->reg_name
,
9770 intel_syntax
? ']' : ')');
9777 as_bad (_("`%s' is not a valid %s expression"),
9778 operand_string
, kind
);
9783 if (addr_mode
!= CODE_16BIT
)
9785 /* 32-bit/64-bit checks. */
9787 && ((addr_mode
== CODE_64BIT
9788 ? !i
.base_reg
->reg_type
.bitfield
.qword
9789 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9790 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9791 || i
.base_reg
->reg_num
== RegIZ
))
9793 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9794 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9795 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9796 && ((addr_mode
== CODE_64BIT
9797 ? !i
.index_reg
->reg_type
.bitfield
.qword
9798 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9799 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9802 /* bndmk, bndldx, and bndstx have special restrictions. */
9803 if (current_templates
->start
->base_opcode
== 0xf30f1b
9804 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9806 /* They cannot use RIP-relative addressing. */
9807 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9809 as_bad (_("`%s' cannot be used here"), operand_string
);
9813 /* bndldx and bndstx ignore their scale factor. */
9814 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9815 && i
.log2_scale_factor
)
9816 as_warn (_("register scaling is being ignored here"));
9821 /* 16-bit checks. */
9823 && (!i
.base_reg
->reg_type
.bitfield
.word
9824 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9826 && (!i
.index_reg
->reg_type
.bitfield
.word
9827 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9829 && i
.base_reg
->reg_num
< 6
9830 && i
.index_reg
->reg_num
>= 6
9831 && i
.log2_scale_factor
== 0))))
9838 /* Handle vector immediates. */
9841 RC_SAE_immediate (const char *imm_start
)
9843 unsigned int match_found
, j
;
9844 const char *pstr
= imm_start
;
9852 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9854 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9858 rc_op
.type
= RC_NamesTable
[j
].type
;
9859 rc_op
.operand
= this_operand
;
9860 i
.rounding
= &rc_op
;
9864 as_bad (_("duplicated `%s'"), imm_start
);
9867 pstr
+= RC_NamesTable
[j
].len
;
9877 as_bad (_("Missing '}': '%s'"), imm_start
);
9880 /* RC/SAE immediate string should contain nothing more. */;
9883 as_bad (_("Junk after '}': '%s'"), imm_start
);
9887 exp
= &im_expressions
[i
.imm_operands
++];
9888 i
.op
[this_operand
].imms
= exp
;
9890 exp
->X_op
= O_constant
;
9891 exp
->X_add_number
= 0;
9892 exp
->X_add_symbol
= (symbolS
*) 0;
9893 exp
->X_op_symbol
= (symbolS
*) 0;
9895 i
.types
[this_operand
].bitfield
.imm8
= 1;
9899 /* Only string instructions can have a second memory operand, so
9900 reduce current_templates to just those if it contains any. */
9902 maybe_adjust_templates (void)
9904 const insn_template
*t
;
9906 gas_assert (i
.mem_operands
== 1);
9908 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9909 if (t
->opcode_modifier
.isstring
)
9912 if (t
< current_templates
->end
)
9914 static templates aux_templates
;
9915 bfd_boolean recheck
;
9917 aux_templates
.start
= t
;
9918 for (; t
< current_templates
->end
; ++t
)
9919 if (!t
->opcode_modifier
.isstring
)
9921 aux_templates
.end
= t
;
9923 /* Determine whether to re-check the first memory operand. */
9924 recheck
= (aux_templates
.start
!= current_templates
->start
9925 || t
!= current_templates
->end
);
9927 current_templates
= &aux_templates
;
9932 if (i
.memop1_string
!= NULL
9933 && i386_index_check (i
.memop1_string
) == 0)
9942 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9946 i386_att_operand (char *operand_string
)
9950 char *op_string
= operand_string
;
9952 if (is_space_char (*op_string
))
9955 /* We check for an absolute prefix (differentiating,
9956 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9957 if (*op_string
== ABSOLUTE_PREFIX
)
9960 if (is_space_char (*op_string
))
9962 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9965 /* Check if operand is a register. */
9966 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9968 i386_operand_type temp
;
9970 /* Check for a segment override by searching for ':' after a
9971 segment register. */
9973 if (is_space_char (*op_string
))
9975 if (*op_string
== ':'
9976 && (r
->reg_type
.bitfield
.sreg2
9977 || r
->reg_type
.bitfield
.sreg3
))
9982 i
.seg
[i
.mem_operands
] = &es
;
9985 i
.seg
[i
.mem_operands
] = &cs
;
9988 i
.seg
[i
.mem_operands
] = &ss
;
9991 i
.seg
[i
.mem_operands
] = &ds
;
9994 i
.seg
[i
.mem_operands
] = &fs
;
9997 i
.seg
[i
.mem_operands
] = &gs
;
10001 /* Skip the ':' and whitespace. */
10003 if (is_space_char (*op_string
))
10006 if (!is_digit_char (*op_string
)
10007 && !is_identifier_char (*op_string
)
10008 && *op_string
!= '('
10009 && *op_string
!= ABSOLUTE_PREFIX
)
10011 as_bad (_("bad memory operand `%s'"), op_string
);
10014 /* Handle case of %es:*foo. */
10015 if (*op_string
== ABSOLUTE_PREFIX
)
10018 if (is_space_char (*op_string
))
10020 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10022 goto do_memory_reference
;
10025 /* Handle vector operations. */
10026 if (*op_string
== '{')
10028 op_string
= check_VecOperations (op_string
, NULL
);
10029 if (op_string
== NULL
)
10035 as_bad (_("junk `%s' after register"), op_string
);
10038 temp
= r
->reg_type
;
10039 temp
.bitfield
.baseindex
= 0;
10040 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10042 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10043 i
.op
[this_operand
].regs
= r
;
10046 else if (*op_string
== REGISTER_PREFIX
)
10048 as_bad (_("bad register name `%s'"), op_string
);
10051 else if (*op_string
== IMMEDIATE_PREFIX
)
10054 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10056 as_bad (_("immediate operand illegal with absolute jump"));
10059 if (!i386_immediate (op_string
))
10062 else if (RC_SAE_immediate (operand_string
))
10064 /* If it is a RC or SAE immediate, do nothing. */
10067 else if (is_digit_char (*op_string
)
10068 || is_identifier_char (*op_string
)
10069 || *op_string
== '"'
10070 || *op_string
== '(')
10072 /* This is a memory reference of some sort. */
10075 /* Start and end of displacement string expression (if found). */
10076 char *displacement_string_start
;
10077 char *displacement_string_end
;
10080 do_memory_reference
:
10081 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10083 if ((i
.mem_operands
== 1
10084 && !current_templates
->start
->opcode_modifier
.isstring
)
10085 || i
.mem_operands
== 2)
10087 as_bad (_("too many memory references for `%s'"),
10088 current_templates
->start
->name
);
10092 /* Check for base index form. We detect the base index form by
10093 looking for an ')' at the end of the operand, searching
10094 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10096 base_string
= op_string
+ strlen (op_string
);
10098 /* Handle vector operations. */
10099 vop_start
= strchr (op_string
, '{');
10100 if (vop_start
&& vop_start
< base_string
)
10102 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10104 base_string
= vop_start
;
10108 if (is_space_char (*base_string
))
10111 /* If we only have a displacement, set-up for it to be parsed later. */
10112 displacement_string_start
= op_string
;
10113 displacement_string_end
= base_string
+ 1;
10115 if (*base_string
== ')')
10118 unsigned int parens_balanced
= 1;
10119 /* We've already checked that the number of left & right ()'s are
10120 equal, so this loop will not be infinite. */
10124 if (*base_string
== ')')
10126 if (*base_string
== '(')
10129 while (parens_balanced
);
10131 temp_string
= base_string
;
10133 /* Skip past '(' and whitespace. */
10135 if (is_space_char (*base_string
))
10138 if (*base_string
== ','
10139 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10142 displacement_string_end
= temp_string
;
10144 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10148 base_string
= end_op
;
10149 if (is_space_char (*base_string
))
10153 /* There may be an index reg or scale factor here. */
10154 if (*base_string
== ',')
10157 if (is_space_char (*base_string
))
10160 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10163 base_string
= end_op
;
10164 if (is_space_char (*base_string
))
10166 if (*base_string
== ',')
10169 if (is_space_char (*base_string
))
10172 else if (*base_string
!= ')')
10174 as_bad (_("expecting `,' or `)' "
10175 "after index register in `%s'"),
10180 else if (*base_string
== REGISTER_PREFIX
)
10182 end_op
= strchr (base_string
, ',');
10185 as_bad (_("bad register name `%s'"), base_string
);
10189 /* Check for scale factor. */
10190 if (*base_string
!= ')')
10192 char *end_scale
= i386_scale (base_string
);
10197 base_string
= end_scale
;
10198 if (is_space_char (*base_string
))
10200 if (*base_string
!= ')')
10202 as_bad (_("expecting `)' "
10203 "after scale factor in `%s'"),
10208 else if (!i
.index_reg
)
10210 as_bad (_("expecting index register or scale factor "
10211 "after `,'; got '%c'"),
10216 else if (*base_string
!= ')')
10218 as_bad (_("expecting `,' or `)' "
10219 "after base register in `%s'"),
10224 else if (*base_string
== REGISTER_PREFIX
)
10226 end_op
= strchr (base_string
, ',');
10229 as_bad (_("bad register name `%s'"), base_string
);
10234 /* If there's an expression beginning the operand, parse it,
10235 assuming displacement_string_start and
10236 displacement_string_end are meaningful. */
10237 if (displacement_string_start
!= displacement_string_end
)
10239 if (!i386_displacement (displacement_string_start
,
10240 displacement_string_end
))
10244 /* Special case for (%dx) while doing input/output op. */
10246 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10247 && i
.index_reg
== 0
10248 && i
.log2_scale_factor
== 0
10249 && i
.seg
[i
.mem_operands
] == 0
10250 && !operand_type_check (i
.types
[this_operand
], disp
))
10252 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10256 if (i386_index_check (operand_string
) == 0)
10258 i
.flags
[this_operand
] |= Operand_Mem
;
10259 if (i
.mem_operands
== 0)
10260 i
.memop1_string
= xstrdup (operand_string
);
10265 /* It's not a memory operand; argh! */
10266 as_bad (_("invalid char %s beginning operand %d `%s'"),
10267 output_invalid (*op_string
),
10272 return 1; /* Normal return. */
10275 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10276 that an rs_machine_dependent frag may reach. */
10279 i386_frag_max_var (fragS
*frag
)
10281 /* The only relaxable frags are for jumps.
10282 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10283 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10284 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10287 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10289 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10291 /* STT_GNU_IFUNC symbol must go through PLT. */
10292 if ((symbol_get_bfdsym (fr_symbol
)->flags
10293 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10296 if (!S_IS_EXTERNAL (fr_symbol
))
10297 /* Symbol may be weak or local. */
10298 return !S_IS_WEAK (fr_symbol
);
10300 /* Global symbols with non-default visibility can't be preempted. */
10301 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10304 if (fr_var
!= NO_RELOC
)
10305 switch ((enum bfd_reloc_code_real
) fr_var
)
10307 case BFD_RELOC_386_PLT32
:
10308 case BFD_RELOC_X86_64_PLT32
:
10309 /* Symbol with PLT relocation may be preempted. */
10315 /* Global symbols with default visibility in a shared library may be
10316 preempted by another definition. */
10321 /* md_estimate_size_before_relax()
10323 Called just before relax() for rs_machine_dependent frags. The x86
10324 assembler uses these frags to handle variable size jump
10327 Any symbol that is now undefined will not become defined.
10328 Return the correct fr_subtype in the frag.
10329 Return the initial "guess for variable size of frag" to caller.
10330 The guess is actually the growth beyond the fixed part. Whatever
10331 we do to grow the fixed or variable part contributes to our
10335 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10337 /* We've already got fragP->fr_subtype right; all we have to do is
10338 check for un-relaxable symbols. On an ELF system, we can't relax
10339 an externally visible symbol, because it may be overridden by a
10341 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10342 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10344 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10347 #if defined (OBJ_COFF) && defined (TE_PE)
10348 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10349 && S_IS_WEAK (fragP
->fr_symbol
))
10353 /* Symbol is undefined in this segment, or we need to keep a
10354 reloc so that weak symbols can be overridden. */
10355 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10356 enum bfd_reloc_code_real reloc_type
;
10357 unsigned char *opcode
;
10360 if (fragP
->fr_var
!= NO_RELOC
)
10361 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10362 else if (size
== 2)
10363 reloc_type
= BFD_RELOC_16_PCREL
;
10364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10365 else if (need_plt32_p (fragP
->fr_symbol
))
10366 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10369 reloc_type
= BFD_RELOC_32_PCREL
;
10371 old_fr_fix
= fragP
->fr_fix
;
10372 opcode
= (unsigned char *) fragP
->fr_opcode
;
10374 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10377 /* Make jmp (0xeb) a (d)word displacement jump. */
10379 fragP
->fr_fix
+= size
;
10380 fix_new (fragP
, old_fr_fix
, size
,
10382 fragP
->fr_offset
, 1,
10388 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10390 /* Negate the condition, and branch past an
10391 unconditional jump. */
10394 /* Insert an unconditional jump. */
10396 /* We added two extra opcode bytes, and have a two byte
10398 fragP
->fr_fix
+= 2 + 2;
10399 fix_new (fragP
, old_fr_fix
+ 2, 2,
10401 fragP
->fr_offset
, 1,
10405 /* Fall through. */
10408 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10412 fragP
->fr_fix
+= 1;
10413 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10415 fragP
->fr_offset
, 1,
10416 BFD_RELOC_8_PCREL
);
10417 fixP
->fx_signed
= 1;
10421 /* This changes the byte-displacement jump 0x7N
10422 to the (d)word-displacement jump 0x0f,0x8N. */
10423 opcode
[1] = opcode
[0] + 0x10;
10424 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10425 /* We've added an opcode byte. */
10426 fragP
->fr_fix
+= 1 + size
;
10427 fix_new (fragP
, old_fr_fix
+ 1, size
,
10429 fragP
->fr_offset
, 1,
10434 BAD_CASE (fragP
->fr_subtype
);
10438 return fragP
->fr_fix
- old_fr_fix
;
10441 /* Guess size depending on current relax state. Initially the relax
10442 state will correspond to a short jump and we return 1, because
10443 the variable part of the frag (the branch offset) is one byte
10444 long. However, we can relax a section more than once and in that
10445 case we must either set fr_subtype back to the unrelaxed state,
10446 or return the value for the appropriate branch. */
10447 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10450 /* Called after relax() is finished.
10452 In: Address of frag.
10453 fr_type == rs_machine_dependent.
10454 fr_subtype is what the address relaxed to.
10456 Out: Any fixSs and constants are set up.
10457 Caller will turn frag into a ".space 0". */
10460 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10463 unsigned char *opcode
;
10464 unsigned char *where_to_put_displacement
= NULL
;
10465 offsetT target_address
;
10466 offsetT opcode_address
;
10467 unsigned int extension
= 0;
10468 offsetT displacement_from_opcode_start
;
10470 opcode
= (unsigned char *) fragP
->fr_opcode
;
10472 /* Address we want to reach in file space. */
10473 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10475 /* Address opcode resides at in file space. */
10476 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10478 /* Displacement from opcode start to fill into instruction. */
10479 displacement_from_opcode_start
= target_address
- opcode_address
;
10481 if ((fragP
->fr_subtype
& BIG
) == 0)
10483 /* Don't have to change opcode. */
10484 extension
= 1; /* 1 opcode + 1 displacement */
10485 where_to_put_displacement
= &opcode
[1];
10489 if (no_cond_jump_promotion
10490 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10491 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10492 _("long jump required"));
10494 switch (fragP
->fr_subtype
)
10496 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10497 extension
= 4; /* 1 opcode + 4 displacement */
10499 where_to_put_displacement
= &opcode
[1];
10502 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10503 extension
= 2; /* 1 opcode + 2 displacement */
10505 where_to_put_displacement
= &opcode
[1];
10508 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10509 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10510 extension
= 5; /* 2 opcode + 4 displacement */
10511 opcode
[1] = opcode
[0] + 0x10;
10512 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10513 where_to_put_displacement
= &opcode
[2];
10516 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10517 extension
= 3; /* 2 opcode + 2 displacement */
10518 opcode
[1] = opcode
[0] + 0x10;
10519 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10520 where_to_put_displacement
= &opcode
[2];
10523 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10528 where_to_put_displacement
= &opcode
[3];
10532 BAD_CASE (fragP
->fr_subtype
);
10537 /* If size if less then four we are sure that the operand fits,
10538 but if it's 4, then it could be that the displacement is larger
10540 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10542 && ((addressT
) (displacement_from_opcode_start
- extension
10543 + ((addressT
) 1 << 31))
10544 > (((addressT
) 2 << 31) - 1)))
10546 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10547 _("jump target out of range"));
10548 /* Make us emit 0. */
10549 displacement_from_opcode_start
= extension
;
10551 /* Now put displacement after opcode. */
10552 md_number_to_chars ((char *) where_to_put_displacement
,
10553 (valueT
) (displacement_from_opcode_start
- extension
),
10554 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10555 fragP
->fr_fix
+= extension
;
10558 /* Apply a fixup (fixP) to segment data, once it has been determined
10559 by our caller that we have all the info we need to fix it up.
10561 Parameter valP is the pointer to the value of the bits.
10563 On the 386, immediates, displacements, and data pointers are all in
10564 the same (little-endian) format, so we don't need to care about which
10565 we are handling. */
10568 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10570 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10571 valueT value
= *valP
;
10573 #if !defined (TE_Mach)
10574 if (fixP
->fx_pcrel
)
10576 switch (fixP
->fx_r_type
)
10582 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10585 case BFD_RELOC_X86_64_32S
:
10586 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10589 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10592 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10597 if (fixP
->fx_addsy
!= NULL
10598 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10599 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10600 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10601 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10602 && !use_rela_relocations
)
10604 /* This is a hack. There should be a better way to handle this.
10605 This covers for the fact that bfd_install_relocation will
10606 subtract the current location (for partial_inplace, PC relative
10607 relocations); see more below. */
10611 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10614 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10619 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10621 if ((sym_seg
== seg
10622 || (symbol_section_p (fixP
->fx_addsy
)
10623 && sym_seg
!= absolute_section
))
10624 && !generic_force_reloc (fixP
))
10626 /* Yes, we add the values in twice. This is because
10627 bfd_install_relocation subtracts them out again. I think
10628 bfd_install_relocation is broken, but I don't dare change
10630 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10634 #if defined (OBJ_COFF) && defined (TE_PE)
10635 /* For some reason, the PE format does not store a
10636 section address offset for a PC relative symbol. */
10637 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10638 || S_IS_WEAK (fixP
->fx_addsy
))
10639 value
+= md_pcrel_from (fixP
);
10642 #if defined (OBJ_COFF) && defined (TE_PE)
10643 if (fixP
->fx_addsy
!= NULL
10644 && S_IS_WEAK (fixP
->fx_addsy
)
10645 /* PR 16858: Do not modify weak function references. */
10646 && ! fixP
->fx_pcrel
)
10648 #if !defined (TE_PEP)
10649 /* For x86 PE weak function symbols are neither PC-relative
10650 nor do they set S_IS_FUNCTION. So the only reliable way
10651 to detect them is to check the flags of their containing
10653 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10654 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10658 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10662 /* Fix a few things - the dynamic linker expects certain values here,
10663 and we must not disappoint it. */
10664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10665 if (IS_ELF
&& fixP
->fx_addsy
)
10666 switch (fixP
->fx_r_type
)
10668 case BFD_RELOC_386_PLT32
:
10669 case BFD_RELOC_X86_64_PLT32
:
10670 /* Make the jump instruction point to the address of the operand.
10671 At runtime we merely add the offset to the actual PLT entry.
10672 NB: Subtract the offset size only for jump instructions. */
10673 if (fixP
->fx_pcrel
)
10677 case BFD_RELOC_386_TLS_GD
:
10678 case BFD_RELOC_386_TLS_LDM
:
10679 case BFD_RELOC_386_TLS_IE_32
:
10680 case BFD_RELOC_386_TLS_IE
:
10681 case BFD_RELOC_386_TLS_GOTIE
:
10682 case BFD_RELOC_386_TLS_GOTDESC
:
10683 case BFD_RELOC_X86_64_TLSGD
:
10684 case BFD_RELOC_X86_64_TLSLD
:
10685 case BFD_RELOC_X86_64_GOTTPOFF
:
10686 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10687 value
= 0; /* Fully resolved at runtime. No addend. */
10689 case BFD_RELOC_386_TLS_LE
:
10690 case BFD_RELOC_386_TLS_LDO_32
:
10691 case BFD_RELOC_386_TLS_LE_32
:
10692 case BFD_RELOC_X86_64_DTPOFF32
:
10693 case BFD_RELOC_X86_64_DTPOFF64
:
10694 case BFD_RELOC_X86_64_TPOFF32
:
10695 case BFD_RELOC_X86_64_TPOFF64
:
10696 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10699 case BFD_RELOC_386_TLS_DESC_CALL
:
10700 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10701 value
= 0; /* Fully resolved at runtime. No addend. */
10702 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10706 case BFD_RELOC_VTABLE_INHERIT
:
10707 case BFD_RELOC_VTABLE_ENTRY
:
10714 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10716 #endif /* !defined (TE_Mach) */
10718 /* Are we finished with this relocation now? */
10719 if (fixP
->fx_addsy
== NULL
)
10721 #if defined (OBJ_COFF) && defined (TE_PE)
10722 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10725 /* Remember value for tc_gen_reloc. */
10726 fixP
->fx_addnumber
= value
;
10727 /* Clear out the frag for now. */
10731 else if (use_rela_relocations
)
10733 fixP
->fx_no_overflow
= 1;
10734 /* Remember value for tc_gen_reloc. */
10735 fixP
->fx_addnumber
= value
;
10739 md_number_to_chars (p
, value
, fixP
->fx_size
);
10743 md_atof (int type
, char *litP
, int *sizeP
)
10745 /* This outputs the LITTLENUMs in REVERSE order;
10746 in accord with the bigendian 386. */
10747 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10750 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10753 output_invalid (int c
)
10756 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10759 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10760 "(0x%x)", (unsigned char) c
);
10761 return output_invalid_buf
;
10764 /* REG_STRING starts *before* REGISTER_PREFIX. */
10766 static const reg_entry
*
10767 parse_real_register (char *reg_string
, char **end_op
)
10769 char *s
= reg_string
;
10771 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10772 const reg_entry
*r
;
10774 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10775 if (*s
== REGISTER_PREFIX
)
10778 if (is_space_char (*s
))
10781 p
= reg_name_given
;
10782 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10784 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10785 return (const reg_entry
*) NULL
;
10789 /* For naked regs, make sure that we are not dealing with an identifier.
10790 This prevents confusing an identifier like `eax_var' with register
10792 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10793 return (const reg_entry
*) NULL
;
10797 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10799 /* Handle floating point regs, allowing spaces in the (i) part. */
10800 if (r
== i386_regtab
/* %st is first entry of table */)
10802 if (!cpu_arch_flags
.bitfield
.cpu8087
10803 && !cpu_arch_flags
.bitfield
.cpu287
10804 && !cpu_arch_flags
.bitfield
.cpu387
)
10805 return (const reg_entry
*) NULL
;
10807 if (is_space_char (*s
))
10812 if (is_space_char (*s
))
10814 if (*s
>= '0' && *s
<= '7')
10816 int fpr
= *s
- '0';
10818 if (is_space_char (*s
))
10823 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10828 /* We have "%st(" then garbage. */
10829 return (const reg_entry
*) NULL
;
10833 if (r
== NULL
|| allow_pseudo_reg
)
10836 if (operand_type_all_zero (&r
->reg_type
))
10837 return (const reg_entry
*) NULL
;
10839 if ((r
->reg_type
.bitfield
.dword
10840 || r
->reg_type
.bitfield
.sreg3
10841 || r
->reg_type
.bitfield
.control
10842 || r
->reg_type
.bitfield
.debug
10843 || r
->reg_type
.bitfield
.test
)
10844 && !cpu_arch_flags
.bitfield
.cpui386
)
10845 return (const reg_entry
*) NULL
;
10847 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10848 return (const reg_entry
*) NULL
;
10850 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10852 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10853 return (const reg_entry
*) NULL
;
10855 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10857 if (r
->reg_type
.bitfield
.ymmword
)
10858 return (const reg_entry
*) NULL
;
10860 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10861 return (const reg_entry
*) NULL
;
10865 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10866 return (const reg_entry
*) NULL
;
10868 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10869 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10870 return (const reg_entry
*) NULL
;
10872 /* Upper 16 vector registers are only available with VREX in 64bit
10873 mode, and require EVEX encoding. */
10874 if (r
->reg_flags
& RegVRex
)
10876 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10877 || flag_code
!= CODE_64BIT
)
10878 return (const reg_entry
*) NULL
;
10880 i
.vec_encoding
= vex_encoding_evex
;
10883 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10884 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10885 && flag_code
!= CODE_64BIT
)
10886 return (const reg_entry
*) NULL
;
10888 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10889 return (const reg_entry
*) NULL
;
10894 /* REG_STRING starts *before* REGISTER_PREFIX. */
10896 static const reg_entry
*
10897 parse_register (char *reg_string
, char **end_op
)
10899 const reg_entry
*r
;
10901 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10902 r
= parse_real_register (reg_string
, end_op
);
10907 char *save
= input_line_pointer
;
10911 input_line_pointer
= reg_string
;
10912 c
= get_symbol_name (®_string
);
10913 symbolP
= symbol_find (reg_string
);
10914 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10916 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10918 know (e
->X_op
== O_register
);
10919 know (e
->X_add_number
>= 0
10920 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10921 r
= i386_regtab
+ e
->X_add_number
;
10922 if ((r
->reg_flags
& RegVRex
))
10923 i
.vec_encoding
= vex_encoding_evex
;
10924 *end_op
= input_line_pointer
;
10926 *input_line_pointer
= c
;
10927 input_line_pointer
= save
;
10933 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10935 const reg_entry
*r
;
10936 char *end
= input_line_pointer
;
10939 r
= parse_register (name
, &input_line_pointer
);
10940 if (r
&& end
<= input_line_pointer
)
10942 *nextcharP
= *input_line_pointer
;
10943 *input_line_pointer
= 0;
10944 e
->X_op
= O_register
;
10945 e
->X_add_number
= r
- i386_regtab
;
10948 input_line_pointer
= end
;
10950 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10954 md_operand (expressionS
*e
)
10957 const reg_entry
*r
;
10959 switch (*input_line_pointer
)
10961 case REGISTER_PREFIX
:
10962 r
= parse_real_register (input_line_pointer
, &end
);
10965 e
->X_op
= O_register
;
10966 e
->X_add_number
= r
- i386_regtab
;
10967 input_line_pointer
= end
;
10972 gas_assert (intel_syntax
);
10973 end
= input_line_pointer
++;
10975 if (*input_line_pointer
== ']')
10977 ++input_line_pointer
;
10978 e
->X_op_symbol
= make_expr_symbol (e
);
10979 e
->X_add_symbol
= NULL
;
10980 e
->X_add_number
= 0;
10985 e
->X_op
= O_absent
;
10986 input_line_pointer
= end
;
10993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10994 const char *md_shortopts
= "kVQ:sqnO::";
10996 const char *md_shortopts
= "qnO::";
10999 #define OPTION_32 (OPTION_MD_BASE + 0)
11000 #define OPTION_64 (OPTION_MD_BASE + 1)
11001 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11002 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11003 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11004 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11005 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11006 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11007 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11008 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11009 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11010 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11011 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11012 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11013 #define OPTION_X32 (OPTION_MD_BASE + 14)
11014 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11015 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11016 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11017 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11018 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11019 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11020 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11021 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11022 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11023 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11024 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11025 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11027 struct option md_longopts
[] =
11029 {"32", no_argument
, NULL
, OPTION_32
},
11030 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11031 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11032 {"64", no_argument
, NULL
, OPTION_64
},
11034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11035 {"x32", no_argument
, NULL
, OPTION_X32
},
11036 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11037 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11039 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11040 {"march", required_argument
, NULL
, OPTION_MARCH
},
11041 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11042 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11043 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11044 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11045 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11046 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11047 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11048 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11049 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11050 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11051 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11052 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11053 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11054 # if defined (TE_PE) || defined (TE_PEP)
11055 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11057 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11058 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11059 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11060 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11061 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11062 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11063 {NULL
, no_argument
, NULL
, 0}
11065 size_t md_longopts_size
= sizeof (md_longopts
);
11068 md_parse_option (int c
, const char *arg
)
11071 char *arch
, *next
, *saved
;
11076 optimize_align_code
= 0;
11080 quiet_warnings
= 1;
11083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11084 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11085 should be emitted or not. FIXME: Not implemented. */
11089 /* -V: SVR4 argument to print version ID. */
11091 print_version_id ();
11094 /* -k: Ignore for FreeBSD compatibility. */
11099 /* -s: On i386 Solaris, this tells the native assembler to use
11100 .stab instead of .stab.excl. We always use .stab anyhow. */
11103 case OPTION_MSHARED
:
11107 case OPTION_X86_USED_NOTE
:
11108 if (strcasecmp (arg
, "yes") == 0)
11110 else if (strcasecmp (arg
, "no") == 0)
11113 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11118 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11119 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11122 const char **list
, **l
;
11124 list
= bfd_target_list ();
11125 for (l
= list
; *l
!= NULL
; l
++)
11126 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11127 || strcmp (*l
, "coff-x86-64") == 0
11128 || strcmp (*l
, "pe-x86-64") == 0
11129 || strcmp (*l
, "pei-x86-64") == 0
11130 || strcmp (*l
, "mach-o-x86-64") == 0)
11132 default_arch
= "x86_64";
11136 as_fatal (_("no compiled in support for x86_64"));
11142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11146 const char **list
, **l
;
11148 list
= bfd_target_list ();
11149 for (l
= list
; *l
!= NULL
; l
++)
11150 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11152 default_arch
= "x86_64:32";
11156 as_fatal (_("no compiled in support for 32bit x86_64"));
11160 as_fatal (_("32bit x86_64 is only supported for ELF"));
11165 default_arch
= "i386";
11168 case OPTION_DIVIDE
:
11169 #ifdef SVR4_COMMENT_CHARS
11174 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11176 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11180 i386_comment_chars
= n
;
11186 saved
= xstrdup (arg
);
11188 /* Allow -march=+nosse. */
11194 as_fatal (_("invalid -march= option: `%s'"), arg
);
11195 next
= strchr (arch
, '+');
11198 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11200 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11203 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11206 cpu_arch_name
= cpu_arch
[j
].name
;
11207 cpu_sub_arch_name
= NULL
;
11208 cpu_arch_flags
= cpu_arch
[j
].flags
;
11209 cpu_arch_isa
= cpu_arch
[j
].type
;
11210 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11211 if (!cpu_arch_tune_set
)
11213 cpu_arch_tune
= cpu_arch_isa
;
11214 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11218 else if (*cpu_arch
[j
].name
== '.'
11219 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11221 /* ISA extension. */
11222 i386_cpu_flags flags
;
11224 flags
= cpu_flags_or (cpu_arch_flags
,
11225 cpu_arch
[j
].flags
);
11227 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11229 if (cpu_sub_arch_name
)
11231 char *name
= cpu_sub_arch_name
;
11232 cpu_sub_arch_name
= concat (name
,
11234 (const char *) NULL
);
11238 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11239 cpu_arch_flags
= flags
;
11240 cpu_arch_isa_flags
= flags
;
11244 = cpu_flags_or (cpu_arch_isa_flags
,
11245 cpu_arch
[j
].flags
);
11250 if (j
>= ARRAY_SIZE (cpu_arch
))
11252 /* Disable an ISA extension. */
11253 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11254 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11256 i386_cpu_flags flags
;
11258 flags
= cpu_flags_and_not (cpu_arch_flags
,
11259 cpu_noarch
[j
].flags
);
11260 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11262 if (cpu_sub_arch_name
)
11264 char *name
= cpu_sub_arch_name
;
11265 cpu_sub_arch_name
= concat (arch
,
11266 (const char *) NULL
);
11270 cpu_sub_arch_name
= xstrdup (arch
);
11271 cpu_arch_flags
= flags
;
11272 cpu_arch_isa_flags
= flags
;
11277 if (j
>= ARRAY_SIZE (cpu_noarch
))
11278 j
= ARRAY_SIZE (cpu_arch
);
11281 if (j
>= ARRAY_SIZE (cpu_arch
))
11282 as_fatal (_("invalid -march= option: `%s'"), arg
);
11286 while (next
!= NULL
);
11292 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11293 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11295 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11297 cpu_arch_tune_set
= 1;
11298 cpu_arch_tune
= cpu_arch
[j
].type
;
11299 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11303 if (j
>= ARRAY_SIZE (cpu_arch
))
11304 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11307 case OPTION_MMNEMONIC
:
11308 if (strcasecmp (arg
, "att") == 0)
11309 intel_mnemonic
= 0;
11310 else if (strcasecmp (arg
, "intel") == 0)
11311 intel_mnemonic
= 1;
11313 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11316 case OPTION_MSYNTAX
:
11317 if (strcasecmp (arg
, "att") == 0)
11319 else if (strcasecmp (arg
, "intel") == 0)
11322 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11325 case OPTION_MINDEX_REG
:
11326 allow_index_reg
= 1;
11329 case OPTION_MNAKED_REG
:
11330 allow_naked_reg
= 1;
11333 case OPTION_MSSE2AVX
:
11337 case OPTION_MSSE_CHECK
:
11338 if (strcasecmp (arg
, "error") == 0)
11339 sse_check
= check_error
;
11340 else if (strcasecmp (arg
, "warning") == 0)
11341 sse_check
= check_warning
;
11342 else if (strcasecmp (arg
, "none") == 0)
11343 sse_check
= check_none
;
11345 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11348 case OPTION_MOPERAND_CHECK
:
11349 if (strcasecmp (arg
, "error") == 0)
11350 operand_check
= check_error
;
11351 else if (strcasecmp (arg
, "warning") == 0)
11352 operand_check
= check_warning
;
11353 else if (strcasecmp (arg
, "none") == 0)
11354 operand_check
= check_none
;
11356 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11359 case OPTION_MAVXSCALAR
:
11360 if (strcasecmp (arg
, "128") == 0)
11361 avxscalar
= vex128
;
11362 else if (strcasecmp (arg
, "256") == 0)
11363 avxscalar
= vex256
;
11365 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11368 case OPTION_MVEXWIG
:
11369 if (strcmp (arg
, "0") == 0)
11371 else if (strcmp (arg
, "1") == 0)
11374 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11377 case OPTION_MADD_BND_PREFIX
:
11378 add_bnd_prefix
= 1;
11381 case OPTION_MEVEXLIG
:
11382 if (strcmp (arg
, "128") == 0)
11383 evexlig
= evexl128
;
11384 else if (strcmp (arg
, "256") == 0)
11385 evexlig
= evexl256
;
11386 else if (strcmp (arg
, "512") == 0)
11387 evexlig
= evexl512
;
11389 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11392 case OPTION_MEVEXRCIG
:
11393 if (strcmp (arg
, "rne") == 0)
11395 else if (strcmp (arg
, "rd") == 0)
11397 else if (strcmp (arg
, "ru") == 0)
11399 else if (strcmp (arg
, "rz") == 0)
11402 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11405 case OPTION_MEVEXWIG
:
11406 if (strcmp (arg
, "0") == 0)
11408 else if (strcmp (arg
, "1") == 0)
11411 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11414 # if defined (TE_PE) || defined (TE_PEP)
11415 case OPTION_MBIG_OBJ
:
11420 case OPTION_MOMIT_LOCK_PREFIX
:
11421 if (strcasecmp (arg
, "yes") == 0)
11422 omit_lock_prefix
= 1;
11423 else if (strcasecmp (arg
, "no") == 0)
11424 omit_lock_prefix
= 0;
11426 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11429 case OPTION_MFENCE_AS_LOCK_ADD
:
11430 if (strcasecmp (arg
, "yes") == 0)
11432 else if (strcasecmp (arg
, "no") == 0)
11435 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11438 case OPTION_MRELAX_RELOCATIONS
:
11439 if (strcasecmp (arg
, "yes") == 0)
11440 generate_relax_relocations
= 1;
11441 else if (strcasecmp (arg
, "no") == 0)
11442 generate_relax_relocations
= 0;
11444 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11447 case OPTION_MAMD64
:
11451 case OPTION_MINTEL64
:
11459 /* Turn off -Os. */
11460 optimize_for_space
= 0;
11462 else if (*arg
== 's')
11464 optimize_for_space
= 1;
11465 /* Turn on all encoding optimizations. */
11466 optimize
= INT_MAX
;
11470 optimize
= atoi (arg
);
11471 /* Turn off -Os. */
11472 optimize_for_space
= 0;
11482 #define MESSAGE_TEMPLATE \
11486 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11487 int *left_p
, const char *name
, int len
)
11489 int size
= sizeof (MESSAGE_TEMPLATE
);
11490 int left
= *left_p
;
11492 /* Reserve 2 spaces for ", " or ",\0" */
11495 /* Check if there is any room. */
11503 p
= mempcpy (p
, name
, len
);
11507 /* Output the current message now and start a new one. */
11510 fprintf (stream
, "%s\n", message
);
11512 left
= size
- (start
- message
) - len
- 2;
11514 gas_assert (left
>= 0);
11516 p
= mempcpy (p
, name
, len
);
11524 show_arch (FILE *stream
, int ext
, int check
)
11526 static char message
[] = MESSAGE_TEMPLATE
;
11527 char *start
= message
+ 27;
11529 int size
= sizeof (MESSAGE_TEMPLATE
);
11536 left
= size
- (start
- message
);
11537 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11539 /* Should it be skipped? */
11540 if (cpu_arch
[j
].skip
)
11543 name
= cpu_arch
[j
].name
;
11544 len
= cpu_arch
[j
].len
;
11547 /* It is an extension. Skip if we aren't asked to show it. */
11558 /* It is an processor. Skip if we show only extension. */
11561 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11563 /* It is an impossible processor - skip. */
11567 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11570 /* Display disabled extensions. */
11572 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11574 name
= cpu_noarch
[j
].name
;
11575 len
= cpu_noarch
[j
].len
;
11576 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11581 fprintf (stream
, "%s\n", message
);
11585 md_show_usage (FILE *stream
)
11587 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11588 fprintf (stream
, _("\
11590 -V print assembler version number\n\
11593 fprintf (stream
, _("\
11594 -n Do not optimize code alignment\n\
11595 -q quieten some warnings\n"));
11596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11597 fprintf (stream
, _("\
11600 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11601 || defined (TE_PE) || defined (TE_PEP))
11602 fprintf (stream
, _("\
11603 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11605 #ifdef SVR4_COMMENT_CHARS
11606 fprintf (stream
, _("\
11607 --divide do not treat `/' as a comment character\n"));
11609 fprintf (stream
, _("\
11610 --divide ignored\n"));
11612 fprintf (stream
, _("\
11613 -march=CPU[,+EXTENSION...]\n\
11614 generate code for CPU and EXTENSION, CPU is one of:\n"));
11615 show_arch (stream
, 0, 1);
11616 fprintf (stream
, _("\
11617 EXTENSION is combination of:\n"));
11618 show_arch (stream
, 1, 0);
11619 fprintf (stream
, _("\
11620 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11621 show_arch (stream
, 0, 0);
11622 fprintf (stream
, _("\
11623 -msse2avx encode SSE instructions with VEX prefix\n"));
11624 fprintf (stream
, _("\
11625 -msse-check=[none|error|warning] (default: warning)\n\
11626 check SSE instructions\n"));
11627 fprintf (stream
, _("\
11628 -moperand-check=[none|error|warning] (default: warning)\n\
11629 check operand combinations for validity\n"));
11630 fprintf (stream
, _("\
11631 -mavxscalar=[128|256] (default: 128)\n\
11632 encode scalar AVX instructions with specific vector\n\
11634 fprintf (stream
, _("\
11635 -mvexwig=[0|1] (default: 0)\n\
11636 encode VEX instructions with specific VEX.W value\n\
11637 for VEX.W bit ignored instructions\n"));
11638 fprintf (stream
, _("\
11639 -mevexlig=[128|256|512] (default: 128)\n\
11640 encode scalar EVEX instructions with specific vector\n\
11642 fprintf (stream
, _("\
11643 -mevexwig=[0|1] (default: 0)\n\
11644 encode EVEX instructions with specific EVEX.W value\n\
11645 for EVEX.W bit ignored instructions\n"));
11646 fprintf (stream
, _("\
11647 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11648 encode EVEX instructions with specific EVEX.RC value\n\
11649 for SAE-only ignored instructions\n"));
11650 fprintf (stream
, _("\
11651 -mmnemonic=[att|intel] "));
11652 if (SYSV386_COMPAT
)
11653 fprintf (stream
, _("(default: att)\n"));
11655 fprintf (stream
, _("(default: intel)\n"));
11656 fprintf (stream
, _("\
11657 use AT&T/Intel mnemonic\n"));
11658 fprintf (stream
, _("\
11659 -msyntax=[att|intel] (default: att)\n\
11660 use AT&T/Intel syntax\n"));
11661 fprintf (stream
, _("\
11662 -mindex-reg support pseudo index registers\n"));
11663 fprintf (stream
, _("\
11664 -mnaked-reg don't require `%%' prefix for registers\n"));
11665 fprintf (stream
, _("\
11666 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11668 fprintf (stream
, _("\
11669 -mshared disable branch optimization for shared code\n"));
11670 fprintf (stream
, _("\
11671 -mx86-used-note=[no|yes] "));
11672 if (DEFAULT_X86_USED_NOTE
)
11673 fprintf (stream
, _("(default: yes)\n"));
11675 fprintf (stream
, _("(default: no)\n"));
11676 fprintf (stream
, _("\
11677 generate x86 used ISA and feature properties\n"));
11679 #if defined (TE_PE) || defined (TE_PEP)
11680 fprintf (stream
, _("\
11681 -mbig-obj generate big object files\n"));
11683 fprintf (stream
, _("\
11684 -momit-lock-prefix=[no|yes] (default: no)\n\
11685 strip all lock prefixes\n"));
11686 fprintf (stream
, _("\
11687 -mfence-as-lock-add=[no|yes] (default: no)\n\
11688 encode lfence, mfence and sfence as\n\
11689 lock addl $0x0, (%%{re}sp)\n"));
11690 fprintf (stream
, _("\
11691 -mrelax-relocations=[no|yes] "));
11692 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11693 fprintf (stream
, _("(default: yes)\n"));
11695 fprintf (stream
, _("(default: no)\n"));
11696 fprintf (stream
, _("\
11697 generate relax relocations\n"));
11698 fprintf (stream
, _("\
11699 -mamd64 accept only AMD64 ISA [default]\n"));
11700 fprintf (stream
, _("\
11701 -mintel64 accept only Intel64 ISA\n"));
11704 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11705 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11706 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11708 /* Pick the target format to use. */
11711 i386_target_format (void)
11713 if (!strncmp (default_arch
, "x86_64", 6))
11715 update_code_flag (CODE_64BIT
, 1);
11716 if (default_arch
[6] == '\0')
11717 x86_elf_abi
= X86_64_ABI
;
11719 x86_elf_abi
= X86_64_X32_ABI
;
11721 else if (!strcmp (default_arch
, "i386"))
11722 update_code_flag (CODE_32BIT
, 1);
11723 else if (!strcmp (default_arch
, "iamcu"))
11725 update_code_flag (CODE_32BIT
, 1);
11726 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11728 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11729 cpu_arch_name
= "iamcu";
11730 cpu_sub_arch_name
= NULL
;
11731 cpu_arch_flags
= iamcu_flags
;
11732 cpu_arch_isa
= PROCESSOR_IAMCU
;
11733 cpu_arch_isa_flags
= iamcu_flags
;
11734 if (!cpu_arch_tune_set
)
11736 cpu_arch_tune
= cpu_arch_isa
;
11737 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11740 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11741 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11745 as_fatal (_("unknown architecture"));
11747 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11748 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11749 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11750 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11752 switch (OUTPUT_FLAVOR
)
11754 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11755 case bfd_target_aout_flavour
:
11756 return AOUT_TARGET_FORMAT
;
11758 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11759 # if defined (TE_PE) || defined (TE_PEP)
11760 case bfd_target_coff_flavour
:
11761 if (flag_code
== CODE_64BIT
)
11762 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11765 # elif defined (TE_GO32)
11766 case bfd_target_coff_flavour
:
11767 return "coff-go32";
11769 case bfd_target_coff_flavour
:
11770 return "coff-i386";
11773 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11774 case bfd_target_elf_flavour
:
11776 const char *format
;
11778 switch (x86_elf_abi
)
11781 format
= ELF_TARGET_FORMAT
;
11784 use_rela_relocations
= 1;
11786 format
= ELF_TARGET_FORMAT64
;
11788 case X86_64_X32_ABI
:
11789 use_rela_relocations
= 1;
11791 disallow_64bit_reloc
= 1;
11792 format
= ELF_TARGET_FORMAT32
;
11795 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11797 if (x86_elf_abi
!= X86_64_ABI
)
11798 as_fatal (_("Intel L1OM is 64bit only"));
11799 return ELF_TARGET_L1OM_FORMAT
;
11801 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11803 if (x86_elf_abi
!= X86_64_ABI
)
11804 as_fatal (_("Intel K1OM is 64bit only"));
11805 return ELF_TARGET_K1OM_FORMAT
;
11807 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11809 if (x86_elf_abi
!= I386_ABI
)
11810 as_fatal (_("Intel MCU is 32bit only"));
11811 return ELF_TARGET_IAMCU_FORMAT
;
11817 #if defined (OBJ_MACH_O)
11818 case bfd_target_mach_o_flavour
:
11819 if (flag_code
== CODE_64BIT
)
11821 use_rela_relocations
= 1;
11823 return "mach-o-x86-64";
11826 return "mach-o-i386";
11834 #endif /* OBJ_MAYBE_ more than one */
11837 md_undefined_symbol (char *name
)
11839 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11840 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11841 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11842 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11846 if (symbol_find (name
))
11847 as_bad (_("GOT already in symbol table"));
11848 GOT_symbol
= symbol_new (name
, undefined_section
,
11849 (valueT
) 0, &zero_address_frag
);
11856 /* Round up a section size to the appropriate boundary. */
11859 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11861 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11862 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11864 /* For a.out, force the section size to be aligned. If we don't do
11865 this, BFD will align it for us, but it will not write out the
11866 final bytes of the section. This may be a bug in BFD, but it is
11867 easier to fix it here since that is how the other a.out targets
11871 align
= bfd_get_section_alignment (stdoutput
, segment
);
11872 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11879 /* On the i386, PC-relative offsets are relative to the start of the
11880 next instruction. That is, the address of the offset, plus its
11881 size, since the offset is always the last part of the insn. */
11884 md_pcrel_from (fixS
*fixP
)
11886 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11892 s_bss (int ignore ATTRIBUTE_UNUSED
)
11896 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11898 obj_elf_section_change_hook ();
11900 temp
= get_absolute_expression ();
11901 subseg_set (bss_section
, (subsegT
) temp
);
11902 demand_empty_rest_of_line ();
11908 i386_validate_fix (fixS
*fixp
)
11910 if (fixp
->fx_subsy
)
11912 if (fixp
->fx_subsy
== GOT_symbol
)
11914 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11919 if (fixp
->fx_tcbit2
)
11920 fixp
->fx_r_type
= (fixp
->fx_tcbit
11921 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11922 : BFD_RELOC_X86_64_GOTPCRELX
);
11925 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11930 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11932 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11934 fixp
->fx_subsy
= 0;
11937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11938 else if (!object_64bit
)
11940 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11941 && fixp
->fx_tcbit2
)
11942 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11948 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11951 bfd_reloc_code_real_type code
;
11953 switch (fixp
->fx_r_type
)
11955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11956 case BFD_RELOC_SIZE32
:
11957 case BFD_RELOC_SIZE64
:
11958 if (S_IS_DEFINED (fixp
->fx_addsy
)
11959 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11961 /* Resolve size relocation against local symbol to size of
11962 the symbol plus addend. */
11963 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11964 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11965 && !fits_in_unsigned_long (value
))
11966 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11967 _("symbol size computation overflow"));
11968 fixp
->fx_addsy
= NULL
;
11969 fixp
->fx_subsy
= NULL
;
11970 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11974 /* Fall through. */
11976 case BFD_RELOC_X86_64_PLT32
:
11977 case BFD_RELOC_X86_64_GOT32
:
11978 case BFD_RELOC_X86_64_GOTPCREL
:
11979 case BFD_RELOC_X86_64_GOTPCRELX
:
11980 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11981 case BFD_RELOC_386_PLT32
:
11982 case BFD_RELOC_386_GOT32
:
11983 case BFD_RELOC_386_GOT32X
:
11984 case BFD_RELOC_386_GOTOFF
:
11985 case BFD_RELOC_386_GOTPC
:
11986 case BFD_RELOC_386_TLS_GD
:
11987 case BFD_RELOC_386_TLS_LDM
:
11988 case BFD_RELOC_386_TLS_LDO_32
:
11989 case BFD_RELOC_386_TLS_IE_32
:
11990 case BFD_RELOC_386_TLS_IE
:
11991 case BFD_RELOC_386_TLS_GOTIE
:
11992 case BFD_RELOC_386_TLS_LE_32
:
11993 case BFD_RELOC_386_TLS_LE
:
11994 case BFD_RELOC_386_TLS_GOTDESC
:
11995 case BFD_RELOC_386_TLS_DESC_CALL
:
11996 case BFD_RELOC_X86_64_TLSGD
:
11997 case BFD_RELOC_X86_64_TLSLD
:
11998 case BFD_RELOC_X86_64_DTPOFF32
:
11999 case BFD_RELOC_X86_64_DTPOFF64
:
12000 case BFD_RELOC_X86_64_GOTTPOFF
:
12001 case BFD_RELOC_X86_64_TPOFF32
:
12002 case BFD_RELOC_X86_64_TPOFF64
:
12003 case BFD_RELOC_X86_64_GOTOFF64
:
12004 case BFD_RELOC_X86_64_GOTPC32
:
12005 case BFD_RELOC_X86_64_GOT64
:
12006 case BFD_RELOC_X86_64_GOTPCREL64
:
12007 case BFD_RELOC_X86_64_GOTPC64
:
12008 case BFD_RELOC_X86_64_GOTPLT64
:
12009 case BFD_RELOC_X86_64_PLTOFF64
:
12010 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12011 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12012 case BFD_RELOC_RVA
:
12013 case BFD_RELOC_VTABLE_ENTRY
:
12014 case BFD_RELOC_VTABLE_INHERIT
:
12016 case BFD_RELOC_32_SECREL
:
12018 code
= fixp
->fx_r_type
;
12020 case BFD_RELOC_X86_64_32S
:
12021 if (!fixp
->fx_pcrel
)
12023 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12024 code
= fixp
->fx_r_type
;
12027 /* Fall through. */
12029 if (fixp
->fx_pcrel
)
12031 switch (fixp
->fx_size
)
12034 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12035 _("can not do %d byte pc-relative relocation"),
12037 code
= BFD_RELOC_32_PCREL
;
12039 case 1: code
= BFD_RELOC_8_PCREL
; break;
12040 case 2: code
= BFD_RELOC_16_PCREL
; break;
12041 case 4: code
= BFD_RELOC_32_PCREL
; break;
12043 case 8: code
= BFD_RELOC_64_PCREL
; break;
12049 switch (fixp
->fx_size
)
12052 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12053 _("can not do %d byte relocation"),
12055 code
= BFD_RELOC_32
;
12057 case 1: code
= BFD_RELOC_8
; break;
12058 case 2: code
= BFD_RELOC_16
; break;
12059 case 4: code
= BFD_RELOC_32
; break;
12061 case 8: code
= BFD_RELOC_64
; break;
12068 if ((code
== BFD_RELOC_32
12069 || code
== BFD_RELOC_32_PCREL
12070 || code
== BFD_RELOC_X86_64_32S
)
12072 && fixp
->fx_addsy
== GOT_symbol
)
12075 code
= BFD_RELOC_386_GOTPC
;
12077 code
= BFD_RELOC_X86_64_GOTPC32
;
12079 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12081 && fixp
->fx_addsy
== GOT_symbol
)
12083 code
= BFD_RELOC_X86_64_GOTPC64
;
12086 rel
= XNEW (arelent
);
12087 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12088 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12090 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12092 if (!use_rela_relocations
)
12094 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12095 vtable entry to be used in the relocation's section offset. */
12096 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12097 rel
->address
= fixp
->fx_offset
;
12098 #if defined (OBJ_COFF) && defined (TE_PE)
12099 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12100 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12105 /* Use the rela in 64bit mode. */
12108 if (disallow_64bit_reloc
)
12111 case BFD_RELOC_X86_64_DTPOFF64
:
12112 case BFD_RELOC_X86_64_TPOFF64
:
12113 case BFD_RELOC_64_PCREL
:
12114 case BFD_RELOC_X86_64_GOTOFF64
:
12115 case BFD_RELOC_X86_64_GOT64
:
12116 case BFD_RELOC_X86_64_GOTPCREL64
:
12117 case BFD_RELOC_X86_64_GOTPC64
:
12118 case BFD_RELOC_X86_64_GOTPLT64
:
12119 case BFD_RELOC_X86_64_PLTOFF64
:
12120 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12121 _("cannot represent relocation type %s in x32 mode"),
12122 bfd_get_reloc_code_name (code
));
12128 if (!fixp
->fx_pcrel
)
12129 rel
->addend
= fixp
->fx_offset
;
12133 case BFD_RELOC_X86_64_PLT32
:
12134 case BFD_RELOC_X86_64_GOT32
:
12135 case BFD_RELOC_X86_64_GOTPCREL
:
12136 case BFD_RELOC_X86_64_GOTPCRELX
:
12137 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12138 case BFD_RELOC_X86_64_TLSGD
:
12139 case BFD_RELOC_X86_64_TLSLD
:
12140 case BFD_RELOC_X86_64_GOTTPOFF
:
12141 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12142 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12143 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12146 rel
->addend
= (section
->vma
12148 + fixp
->fx_addnumber
12149 + md_pcrel_from (fixp
));
12154 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12155 if (rel
->howto
== NULL
)
12157 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12158 _("cannot represent relocation type %s"),
12159 bfd_get_reloc_code_name (code
));
12160 /* Set howto to a garbage value so that we can keep going. */
12161 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12162 gas_assert (rel
->howto
!= NULL
);
12168 #include "tc-i386-intel.c"
12171 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12173 int saved_naked_reg
;
12174 char saved_register_dot
;
12176 saved_naked_reg
= allow_naked_reg
;
12177 allow_naked_reg
= 1;
12178 saved_register_dot
= register_chars
['.'];
12179 register_chars
['.'] = '.';
12180 allow_pseudo_reg
= 1;
12181 expression_and_evaluate (exp
);
12182 allow_pseudo_reg
= 0;
12183 register_chars
['.'] = saved_register_dot
;
12184 allow_naked_reg
= saved_naked_reg
;
12186 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12188 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12190 exp
->X_op
= O_constant
;
12191 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12192 .dw2_regnum
[flag_code
>> 1];
12195 exp
->X_op
= O_illegal
;
12200 tc_x86_frame_initial_instructions (void)
12202 static unsigned int sp_regno
[2];
12204 if (!sp_regno
[flag_code
>> 1])
12206 char *saved_input
= input_line_pointer
;
12207 char sp
[][4] = {"esp", "rsp"};
12210 input_line_pointer
= sp
[flag_code
>> 1];
12211 tc_x86_parse_to_dw2regnum (&exp
);
12212 gas_assert (exp
.X_op
== O_constant
);
12213 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12214 input_line_pointer
= saved_input
;
12217 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12218 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12222 x86_dwarf2_addr_size (void)
12224 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12225 if (x86_elf_abi
== X86_64_X32_ABI
)
12228 return bfd_arch_bits_per_address (stdoutput
) / 8;
12232 i386_elf_section_type (const char *str
, size_t len
)
12234 if (flag_code
== CODE_64BIT
12235 && len
== sizeof ("unwind") - 1
12236 && strncmp (str
, "unwind", 6) == 0)
12237 return SHT_X86_64_UNWIND
;
12244 i386_solaris_fix_up_eh_frame (segT sec
)
12246 if (flag_code
== CODE_64BIT
)
12247 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12253 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12257 exp
.X_op
= O_secrel
;
12258 exp
.X_add_symbol
= symbol
;
12259 exp
.X_add_number
= 0;
12260 emit_expr (&exp
, size
);
12264 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12265 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12268 x86_64_section_letter (int letter
, const char **ptr_msg
)
12270 if (flag_code
== CODE_64BIT
)
12273 return SHF_X86_64_LARGE
;
12275 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12278 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12283 x86_64_section_word (char *str
, size_t len
)
12285 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12286 return SHF_X86_64_LARGE
;
12292 handle_large_common (int small ATTRIBUTE_UNUSED
)
12294 if (flag_code
!= CODE_64BIT
)
12296 s_comm_internal (0, elf_common_parse
);
12297 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12301 static segT lbss_section
;
12302 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12303 asection
*saved_bss_section
= bss_section
;
12305 if (lbss_section
== NULL
)
12307 flagword applicable
;
12308 segT seg
= now_seg
;
12309 subsegT subseg
= now_subseg
;
12311 /* The .lbss section is for local .largecomm symbols. */
12312 lbss_section
= subseg_new (".lbss", 0);
12313 applicable
= bfd_applicable_section_flags (stdoutput
);
12314 bfd_set_section_flags (stdoutput
, lbss_section
,
12315 applicable
& SEC_ALLOC
);
12316 seg_info (lbss_section
)->bss
= 1;
12318 subseg_set (seg
, subseg
);
12321 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12322 bss_section
= lbss_section
;
12324 s_comm_internal (0, elf_common_parse
);
12326 elf_com_section_ptr
= saved_com_section_ptr
;
12327 bss_section
= saved_bss_section
;
12330 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */