1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "k6", PROCESSOR_K6
,
582 { "k6_2", PROCESSOR_K6
,
584 { "athlon", PROCESSOR_ATHLON
,
586 { "sledgehammer", PROCESSOR_K8
,
588 { "opteron", PROCESSOR_K8
,
590 { "k8", PROCESSOR_K8
,
592 { "amdfam10", PROCESSOR_AMDFAM10
,
593 CPU_AMDFAM10_FLAGS
},
594 { ".mmx", PROCESSOR_UNKNOWN
,
596 { ".sse", PROCESSOR_UNKNOWN
,
598 { ".sse2", PROCESSOR_UNKNOWN
,
600 { ".sse3", PROCESSOR_UNKNOWN
,
602 { ".ssse3", PROCESSOR_UNKNOWN
,
604 { ".sse4.1", PROCESSOR_UNKNOWN
,
606 { ".sse4.2", PROCESSOR_UNKNOWN
,
608 { ".sse4", PROCESSOR_UNKNOWN
,
610 { ".avx", PROCESSOR_UNKNOWN
,
612 { ".vmx", PROCESSOR_UNKNOWN
,
614 { ".smx", PROCESSOR_UNKNOWN
,
616 { ".xsave", PROCESSOR_UNKNOWN
,
618 { ".aes", PROCESSOR_UNKNOWN
,
620 { ".pclmul", PROCESSOR_UNKNOWN
,
622 { ".clmul", PROCESSOR_UNKNOWN
,
624 { ".fma", PROCESSOR_UNKNOWN
,
626 { ".fma4", PROCESSOR_UNKNOWN
,
628 { ".movbe", PROCESSOR_UNKNOWN
,
630 { ".ept", PROCESSOR_UNKNOWN
,
632 { ".clflush", PROCESSOR_UNKNOWN
,
634 { ".syscall", PROCESSOR_UNKNOWN
,
636 { ".rdtscp", PROCESSOR_UNKNOWN
,
638 { ".3dnow", PROCESSOR_UNKNOWN
,
640 { ".3dnowa", PROCESSOR_UNKNOWN
,
642 { ".padlock", PROCESSOR_UNKNOWN
,
644 { ".pacifica", PROCESSOR_UNKNOWN
,
646 { ".svme", PROCESSOR_UNKNOWN
,
648 { ".sse4a", PROCESSOR_UNKNOWN
,
650 { ".abm", PROCESSOR_UNKNOWN
,
655 /* Like s_lcomm_internal in gas/read.c but the alignment string
656 is allowed to be optional. */
659 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
666 && *input_line_pointer
== ',')
668 align
= parse_align (needs_align
- 1);
670 if (align
== (addressT
) -1)
685 bss_alloc (symbolP
, size
, align
);
690 pe_lcomm (int needs_align
)
692 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
696 const pseudo_typeS md_pseudo_table
[] =
698 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
699 {"align", s_align_bytes
, 0},
701 {"align", s_align_ptwo
, 0},
703 {"arch", set_cpu_arch
, 0},
707 {"lcomm", pe_lcomm
, 1},
709 {"ffloat", float_cons
, 'f'},
710 {"dfloat", float_cons
, 'd'},
711 {"tfloat", float_cons
, 'x'},
713 {"slong", signed_cons
, 4},
714 {"noopt", s_ignore
, 0},
715 {"optim", s_ignore
, 0},
716 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
717 {"code16", set_code_flag
, CODE_16BIT
},
718 {"code32", set_code_flag
, CODE_32BIT
},
719 {"code64", set_code_flag
, CODE_64BIT
},
720 {"intel_syntax", set_intel_syntax
, 1},
721 {"att_syntax", set_intel_syntax
, 0},
722 {"intel_mnemonic", set_intel_mnemonic
, 1},
723 {"att_mnemonic", set_intel_mnemonic
, 0},
724 {"allow_index_reg", set_allow_index_reg
, 1},
725 {"disallow_index_reg", set_allow_index_reg
, 0},
726 {"sse_check", set_sse_check
, 0},
727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
728 {"largecomm", handle_large_common
, 0},
730 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
731 {"loc", dwarf2_directive_loc
, 0},
732 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
735 {"secrel32", pe_directive_secrel
, 0},
740 /* For interface with expression (). */
741 extern char *input_line_pointer
;
743 /* Hash table for instruction mnemonic lookup. */
744 static struct hash_control
*op_hash
;
746 /* Hash table for register lookup. */
747 static struct hash_control
*reg_hash
;
750 i386_align_code (fragS
*fragP
, int count
)
752 /* Various efficient no-op patterns for aligning code labels.
753 Note: Don't try to assemble the instructions in the comments.
754 0L and 0w are not legal. */
755 static const char f32_1
[] =
757 static const char f32_2
[] =
758 {0x66,0x90}; /* xchg %ax,%ax */
759 static const char f32_3
[] =
760 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
761 static const char f32_4
[] =
762 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
763 static const char f32_5
[] =
765 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
766 static const char f32_6
[] =
767 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
768 static const char f32_7
[] =
769 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
770 static const char f32_8
[] =
772 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
773 static const char f32_9
[] =
774 {0x89,0xf6, /* movl %esi,%esi */
775 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
776 static const char f32_10
[] =
777 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
778 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
779 static const char f32_11
[] =
780 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
781 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
782 static const char f32_12
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
784 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
785 static const char f32_13
[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
787 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
788 static const char f32_14
[] =
789 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
790 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
791 static const char f16_3
[] =
792 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
793 static const char f16_4
[] =
794 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
795 static const char f16_5
[] =
797 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
798 static const char f16_6
[] =
799 {0x89,0xf6, /* mov %si,%si */
800 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
801 static const char f16_7
[] =
802 {0x8d,0x74,0x00, /* lea 0(%si),%si */
803 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
804 static const char f16_8
[] =
805 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
806 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
807 static const char jump_31
[] =
808 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
810 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
811 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
812 static const char *const f32_patt
[] = {
813 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
814 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
816 static const char *const f16_patt
[] = {
817 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
820 static const char alt_3
[] =
822 /* nopl 0(%[re]ax) */
823 static const char alt_4
[] =
824 {0x0f,0x1f,0x40,0x00};
825 /* nopl 0(%[re]ax,%[re]ax,1) */
826 static const char alt_5
[] =
827 {0x0f,0x1f,0x44,0x00,0x00};
828 /* nopw 0(%[re]ax,%[re]ax,1) */
829 static const char alt_6
[] =
830 {0x66,0x0f,0x1f,0x44,0x00,0x00};
831 /* nopl 0L(%[re]ax) */
832 static const char alt_7
[] =
833 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
834 /* nopl 0L(%[re]ax,%[re]ax,1) */
835 static const char alt_8
[] =
836 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* nopw 0L(%[re]ax,%[re]ax,1) */
838 static const char alt_9
[] =
839 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
840 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
841 static const char alt_10
[] =
842 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
844 nopw %cs:0L(%[re]ax,%[re]ax,1) */
845 static const char alt_long_11
[] =
847 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
850 nopw %cs:0L(%[re]ax,%[re]ax,1) */
851 static const char alt_long_12
[] =
854 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_13
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_14
[] =
874 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 nopw %cs:0L(%[re]ax,%[re]ax,1) */
881 static const char alt_long_15
[] =
887 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1)
889 nopw 0(%[re]ax,%[re]ax,1) */
890 static const char alt_short_11
[] =
891 {0x0f,0x1f,0x44,0x00,0x00,
892 0x66,0x0f,0x1f,0x44,0x00,0x00};
893 /* nopw 0(%[re]ax,%[re]ax,1)
894 nopw 0(%[re]ax,%[re]ax,1) */
895 static const char alt_short_12
[] =
896 {0x66,0x0f,0x1f,0x44,0x00,0x00,
897 0x66,0x0f,0x1f,0x44,0x00,0x00};
898 /* nopw 0(%[re]ax,%[re]ax,1)
900 static const char alt_short_13
[] =
901 {0x66,0x0f,0x1f,0x44,0x00,0x00,
902 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
905 static const char alt_short_14
[] =
906 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
907 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
909 nopl 0L(%[re]ax,%[re]ax,1) */
910 static const char alt_short_15
[] =
911 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
912 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 static const char *const alt_short_patt
[] = {
914 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
915 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
916 alt_short_14
, alt_short_15
918 static const char *const alt_long_patt
[] = {
919 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
920 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
921 alt_long_14
, alt_long_15
924 /* Only align for at least a positive non-zero boundary. */
925 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
928 /* We need to decide which NOP sequence to use for 32bit and
929 64bit. When -mtune= is used:
931 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
932 PROCESSOR_GENERIC32, f32_patt will be used.
933 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
934 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
935 PROCESSOR_GENERIC64, alt_long_patt will be used.
936 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
937 PROCESSOR_AMDFAM10, alt_short_patt will be used.
939 When -mtune= isn't used, alt_long_patt will be used if
940 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
943 When -march= or .arch is used, we can't use anything beyond
944 cpu_arch_isa_flags. */
946 if (flag_code
== CODE_16BIT
)
950 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
952 /* Adjust jump offset. */
953 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
956 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
957 f16_patt
[count
- 1], count
);
961 const char *const *patt
= NULL
;
963 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
965 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
966 switch (cpu_arch_tune
)
968 case PROCESSOR_UNKNOWN
:
969 /* We use cpu_arch_isa_flags to check if we SHOULD
970 optimize for Cpu686. */
971 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
972 patt
= alt_long_patt
;
976 case PROCESSOR_PENTIUMPRO
:
977 case PROCESSOR_PENTIUM4
:
978 case PROCESSOR_NOCONA
:
980 case PROCESSOR_CORE2
:
981 case PROCESSOR_COREI7
:
982 case PROCESSOR_GENERIC64
:
983 patt
= alt_long_patt
;
986 case PROCESSOR_ATHLON
:
988 case PROCESSOR_AMDFAM10
:
989 patt
= alt_short_patt
;
993 case PROCESSOR_PENTIUM
:
994 case PROCESSOR_GENERIC32
:
1001 switch (fragP
->tc_frag_data
.tune
)
1003 case PROCESSOR_UNKNOWN
:
1004 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1005 PROCESSOR_UNKNOWN. */
1009 case PROCESSOR_I386
:
1010 case PROCESSOR_I486
:
1011 case PROCESSOR_PENTIUM
:
1013 case PROCESSOR_ATHLON
:
1015 case PROCESSOR_AMDFAM10
:
1016 case PROCESSOR_GENERIC32
:
1017 /* We use cpu_arch_isa_flags to check if we CAN optimize
1019 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1020 patt
= alt_short_patt
;
1024 case PROCESSOR_PENTIUMPRO
:
1025 case PROCESSOR_PENTIUM4
:
1026 case PROCESSOR_NOCONA
:
1027 case PROCESSOR_CORE
:
1028 case PROCESSOR_CORE2
:
1029 case PROCESSOR_COREI7
:
1030 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1031 patt
= alt_long_patt
;
1035 case PROCESSOR_GENERIC64
:
1036 patt
= alt_long_patt
;
1041 if (patt
== f32_patt
)
1043 /* If the padding is less than 15 bytes, we use the normal
1044 ones. Otherwise, we use a jump instruction and adjust
1048 /* For 64bit, the limit is 3 bytes. */
1049 if (flag_code
== CODE_64BIT
1050 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1055 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1056 patt
[count
- 1], count
);
1059 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1061 /* Adjust jump offset. */
1062 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1067 /* Maximum length of an instruction is 15 byte. If the
1068 padding is greater than 15 bytes and we don't use jump,
1069 we have to break it into smaller pieces. */
1070 int padding
= count
;
1071 while (padding
> 15)
1074 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1079 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1080 patt
[padding
- 1], padding
);
1083 fragP
->fr_var
= count
;
1087 operand_type_all_zero (const union i386_operand_type
*x
)
1089 switch (ARRAY_SIZE(x
->array
))
1098 return !x
->array
[0];
1105 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1107 switch (ARRAY_SIZE(x
->array
))
1122 operand_type_equal (const union i386_operand_type
*x
,
1123 const union i386_operand_type
*y
)
1125 switch (ARRAY_SIZE(x
->array
))
1128 if (x
->array
[2] != y
->array
[2])
1131 if (x
->array
[1] != y
->array
[1])
1134 return x
->array
[0] == y
->array
[0];
1142 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1144 switch (ARRAY_SIZE(x
->array
))
1153 return !x
->array
[0];
1160 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1162 switch (ARRAY_SIZE(x
->array
))
1177 cpu_flags_equal (const union i386_cpu_flags
*x
,
1178 const union i386_cpu_flags
*y
)
1180 switch (ARRAY_SIZE(x
->array
))
1183 if (x
->array
[2] != y
->array
[2])
1186 if (x
->array
[1] != y
->array
[1])
1189 return x
->array
[0] == y
->array
[0];
1197 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1199 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1200 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1203 static INLINE i386_cpu_flags
1204 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1206 switch (ARRAY_SIZE (x
.array
))
1209 x
.array
[2] &= y
.array
[2];
1211 x
.array
[1] &= y
.array
[1];
1213 x
.array
[0] &= y
.array
[0];
1221 static INLINE i386_cpu_flags
1222 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1224 switch (ARRAY_SIZE (x
.array
))
1227 x
.array
[2] |= y
.array
[2];
1229 x
.array
[1] |= y
.array
[1];
1231 x
.array
[0] |= y
.array
[0];
1239 #define CPU_FLAGS_ARCH_MATCH 0x1
1240 #define CPU_FLAGS_64BIT_MATCH 0x2
1241 #define CPU_FLAGS_AES_MATCH 0x4
1242 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1243 #define CPU_FLAGS_AVX_MATCH 0x10
1245 #define CPU_FLAGS_32BIT_MATCH \
1246 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1247 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1248 #define CPU_FLAGS_PERFECT_MATCH \
1249 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1251 /* Return CPU flags match bits. */
1254 cpu_flags_match (const template *t
)
1256 i386_cpu_flags x
= t
->cpu_flags
;
1257 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1259 x
.bitfield
.cpu64
= 0;
1260 x
.bitfield
.cpuno64
= 0;
1262 if (cpu_flags_all_zero (&x
))
1264 /* This instruction is available on all archs. */
1265 match
|= CPU_FLAGS_32BIT_MATCH
;
1269 /* This instruction is available only on some archs. */
1270 i386_cpu_flags cpu
= cpu_arch_flags
;
1272 cpu
.bitfield
.cpu64
= 0;
1273 cpu
.bitfield
.cpuno64
= 0;
1274 cpu
= cpu_flags_and (x
, cpu
);
1275 if (!cpu_flags_all_zero (&cpu
))
1277 if (x
.bitfield
.cpuavx
)
1279 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1280 if (cpu
.bitfield
.cpuavx
)
1282 /* Check SSE2AVX. */
1283 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1285 match
|= (CPU_FLAGS_ARCH_MATCH
1286 | CPU_FLAGS_AVX_MATCH
);
1288 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1289 match
|= CPU_FLAGS_AES_MATCH
;
1291 if (!x
.bitfield
.cpupclmul
1292 || cpu
.bitfield
.cpupclmul
)
1293 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1297 match
|= CPU_FLAGS_ARCH_MATCH
;
1300 match
|= CPU_FLAGS_32BIT_MATCH
;
1306 static INLINE i386_operand_type
1307 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1309 switch (ARRAY_SIZE (x
.array
))
1312 x
.array
[2] &= y
.array
[2];
1314 x
.array
[1] &= y
.array
[1];
1316 x
.array
[0] &= y
.array
[0];
1324 static INLINE i386_operand_type
1325 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1327 switch (ARRAY_SIZE (x
.array
))
1330 x
.array
[2] |= y
.array
[2];
1332 x
.array
[1] |= y
.array
[1];
1334 x
.array
[0] |= y
.array
[0];
1342 static INLINE i386_operand_type
1343 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1345 switch (ARRAY_SIZE (x
.array
))
1348 x
.array
[2] ^= y
.array
[2];
1350 x
.array
[1] ^= y
.array
[1];
1352 x
.array
[0] ^= y
.array
[0];
1360 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1361 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1362 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1363 static const i386_operand_type inoutportreg
1364 = OPERAND_TYPE_INOUTPORTREG
;
1365 static const i386_operand_type reg16_inoutportreg
1366 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1367 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1368 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1369 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1370 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1371 static const i386_operand_type anydisp
1372 = OPERAND_TYPE_ANYDISP
;
1373 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1374 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1375 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1376 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1377 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1378 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1379 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1380 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1381 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1382 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1383 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1394 operand_type_check (i386_operand_type t
, enum operand_type c
)
1399 return (t
.bitfield
.reg8
1402 || t
.bitfield
.reg64
);
1405 return (t
.bitfield
.imm8
1409 || t
.bitfield
.imm32s
1410 || t
.bitfield
.imm64
);
1413 return (t
.bitfield
.disp8
1414 || t
.bitfield
.disp16
1415 || t
.bitfield
.disp32
1416 || t
.bitfield
.disp32s
1417 || t
.bitfield
.disp64
);
1420 return (t
.bitfield
.disp8
1421 || t
.bitfield
.disp16
1422 || t
.bitfield
.disp32
1423 || t
.bitfield
.disp32s
1424 || t
.bitfield
.disp64
1425 || t
.bitfield
.baseindex
);
1434 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1435 operand J for instruction template T. */
1438 match_reg_size (const template *t
, unsigned int j
)
1440 return !((i
.types
[j
].bitfield
.byte
1441 && !t
->operand_types
[j
].bitfield
.byte
)
1442 || (i
.types
[j
].bitfield
.word
1443 && !t
->operand_types
[j
].bitfield
.word
)
1444 || (i
.types
[j
].bitfield
.dword
1445 && !t
->operand_types
[j
].bitfield
.dword
)
1446 || (i
.types
[j
].bitfield
.qword
1447 && !t
->operand_types
[j
].bitfield
.qword
));
1450 /* Return 1 if there is no conflict in any size on operand J for
1451 instruction template T. */
1454 match_mem_size (const template *t
, unsigned int j
)
1456 return (match_reg_size (t
, j
)
1457 && !((i
.types
[j
].bitfield
.unspecified
1458 && !t
->operand_types
[j
].bitfield
.unspecified
)
1459 || (i
.types
[j
].bitfield
.fword
1460 && !t
->operand_types
[j
].bitfield
.fword
)
1461 || (i
.types
[j
].bitfield
.tbyte
1462 && !t
->operand_types
[j
].bitfield
.tbyte
)
1463 || (i
.types
[j
].bitfield
.xmmword
1464 && !t
->operand_types
[j
].bitfield
.xmmword
)
1465 || (i
.types
[j
].bitfield
.ymmword
1466 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1469 /* Return 1 if there is no size conflict on any operands for
1470 instruction template T. */
1473 operand_size_match (const template *t
)
1478 /* Don't check jump instructions. */
1479 if (t
->opcode_modifier
.jump
1480 || t
->opcode_modifier
.jumpbyte
1481 || t
->opcode_modifier
.jumpdword
1482 || t
->opcode_modifier
.jumpintersegment
)
1485 /* Check memory and accumulator operand size. */
1486 for (j
= 0; j
< i
.operands
; j
++)
1488 if (t
->operand_types
[j
].bitfield
.anysize
)
1491 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1497 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1505 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1508 /* Check reverse. */
1509 gas_assert (i
.operands
== 2);
1512 for (j
= 0; j
< 2; j
++)
1514 if (t
->operand_types
[j
].bitfield
.acc
1515 && !match_reg_size (t
, j
? 0 : 1))
1521 if (i
.types
[j
].bitfield
.mem
1522 && !match_mem_size (t
, j
? 0 : 1))
1533 operand_type_match (i386_operand_type overlap
,
1534 i386_operand_type given
)
1536 i386_operand_type temp
= overlap
;
1538 temp
.bitfield
.jumpabsolute
= 0;
1539 temp
.bitfield
.unspecified
= 0;
1540 temp
.bitfield
.byte
= 0;
1541 temp
.bitfield
.word
= 0;
1542 temp
.bitfield
.dword
= 0;
1543 temp
.bitfield
.fword
= 0;
1544 temp
.bitfield
.qword
= 0;
1545 temp
.bitfield
.tbyte
= 0;
1546 temp
.bitfield
.xmmword
= 0;
1547 temp
.bitfield
.ymmword
= 0;
1548 if (operand_type_all_zero (&temp
))
1551 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1552 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1555 /* If given types g0 and g1 are registers they must be of the same type
1556 unless the expected operand type register overlap is null.
1557 Note that Acc in a template matches every size of reg. */
1560 operand_type_register_match (i386_operand_type m0
,
1561 i386_operand_type g0
,
1562 i386_operand_type t0
,
1563 i386_operand_type m1
,
1564 i386_operand_type g1
,
1565 i386_operand_type t1
)
1567 if (!operand_type_check (g0
, reg
))
1570 if (!operand_type_check (g1
, reg
))
1573 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1574 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1575 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1576 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1579 if (m0
.bitfield
.acc
)
1581 t0
.bitfield
.reg8
= 1;
1582 t0
.bitfield
.reg16
= 1;
1583 t0
.bitfield
.reg32
= 1;
1584 t0
.bitfield
.reg64
= 1;
1587 if (m1
.bitfield
.acc
)
1589 t1
.bitfield
.reg8
= 1;
1590 t1
.bitfield
.reg16
= 1;
1591 t1
.bitfield
.reg32
= 1;
1592 t1
.bitfield
.reg64
= 1;
1595 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1596 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1597 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1598 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1601 static INLINE
unsigned int
1602 mode_from_disp_size (i386_operand_type t
)
1604 if (t
.bitfield
.disp8
)
1606 else if (t
.bitfield
.disp16
1607 || t
.bitfield
.disp32
1608 || t
.bitfield
.disp32s
)
1615 fits_in_signed_byte (offsetT num
)
1617 return (num
>= -128) && (num
<= 127);
1621 fits_in_unsigned_byte (offsetT num
)
1623 return (num
& 0xff) == num
;
1627 fits_in_unsigned_word (offsetT num
)
1629 return (num
& 0xffff) == num
;
1633 fits_in_signed_word (offsetT num
)
1635 return (-32768 <= num
) && (num
<= 32767);
1639 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1644 return (!(((offsetT
) -1 << 31) & num
)
1645 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1647 } /* fits_in_signed_long() */
1650 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1655 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1657 } /* fits_in_unsigned_long() */
1659 static i386_operand_type
1660 smallest_imm_type (offsetT num
)
1662 i386_operand_type t
;
1664 operand_type_set (&t
, 0);
1665 t
.bitfield
.imm64
= 1;
1667 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1669 /* This code is disabled on the 486 because all the Imm1 forms
1670 in the opcode table are slower on the i486. They're the
1671 versions with the implicitly specified single-position
1672 displacement, which has another syntax if you really want to
1674 t
.bitfield
.imm1
= 1;
1675 t
.bitfield
.imm8
= 1;
1676 t
.bitfield
.imm8s
= 1;
1677 t
.bitfield
.imm16
= 1;
1678 t
.bitfield
.imm32
= 1;
1679 t
.bitfield
.imm32s
= 1;
1681 else if (fits_in_signed_byte (num
))
1683 t
.bitfield
.imm8
= 1;
1684 t
.bitfield
.imm8s
= 1;
1685 t
.bitfield
.imm16
= 1;
1686 t
.bitfield
.imm32
= 1;
1687 t
.bitfield
.imm32s
= 1;
1689 else if (fits_in_unsigned_byte (num
))
1691 t
.bitfield
.imm8
= 1;
1692 t
.bitfield
.imm16
= 1;
1693 t
.bitfield
.imm32
= 1;
1694 t
.bitfield
.imm32s
= 1;
1696 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1698 t
.bitfield
.imm16
= 1;
1699 t
.bitfield
.imm32
= 1;
1700 t
.bitfield
.imm32s
= 1;
1702 else if (fits_in_signed_long (num
))
1704 t
.bitfield
.imm32
= 1;
1705 t
.bitfield
.imm32s
= 1;
1707 else if (fits_in_unsigned_long (num
))
1708 t
.bitfield
.imm32
= 1;
1714 offset_in_range (offsetT val
, int size
)
1720 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1721 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1722 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1724 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1729 /* If BFD64, sign extend val. */
1730 if (!use_rela_relocations
)
1731 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1732 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1734 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1736 char buf1
[40], buf2
[40];
1738 sprint_value (buf1
, val
);
1739 sprint_value (buf2
, val
& mask
);
1740 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1745 /* Returns 0 if attempting to add a prefix where one from the same
1746 class already exists, 1 if non rep/repne added, 2 if rep/repne
1749 add_prefix (unsigned int prefix
)
1754 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1755 && flag_code
== CODE_64BIT
)
1757 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1758 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1759 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1770 case CS_PREFIX_OPCODE
:
1771 case DS_PREFIX_OPCODE
:
1772 case ES_PREFIX_OPCODE
:
1773 case FS_PREFIX_OPCODE
:
1774 case GS_PREFIX_OPCODE
:
1775 case SS_PREFIX_OPCODE
:
1779 case REPNE_PREFIX_OPCODE
:
1780 case REPE_PREFIX_OPCODE
:
1783 case LOCK_PREFIX_OPCODE
:
1791 case ADDR_PREFIX_OPCODE
:
1795 case DATA_PREFIX_OPCODE
:
1799 if (i
.prefix
[q
] != 0)
1807 i
.prefix
[q
] |= prefix
;
1810 as_bad (_("same type of prefix used twice"));
1816 set_code_flag (int value
)
1819 if (flag_code
== CODE_64BIT
)
1821 cpu_arch_flags
.bitfield
.cpu64
= 1;
1822 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1826 cpu_arch_flags
.bitfield
.cpu64
= 0;
1827 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1829 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1831 as_bad (_("64bit mode not supported on this CPU."));
1833 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1835 as_bad (_("32bit mode not supported on this CPU."));
1837 stackop_size
= '\0';
1841 set_16bit_gcc_code_flag (int new_code_flag
)
1843 flag_code
= new_code_flag
;
1844 if (flag_code
!= CODE_16BIT
)
1846 cpu_arch_flags
.bitfield
.cpu64
= 0;
1847 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1848 stackop_size
= LONG_MNEM_SUFFIX
;
1852 set_intel_syntax (int syntax_flag
)
1854 /* Find out if register prefixing is specified. */
1855 int ask_naked_reg
= 0;
1858 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1860 char *string
= input_line_pointer
;
1861 int e
= get_symbol_end ();
1863 if (strcmp (string
, "prefix") == 0)
1865 else if (strcmp (string
, "noprefix") == 0)
1868 as_bad (_("bad argument to syntax directive."));
1869 *input_line_pointer
= e
;
1871 demand_empty_rest_of_line ();
1873 intel_syntax
= syntax_flag
;
1875 if (ask_naked_reg
== 0)
1876 allow_naked_reg
= (intel_syntax
1877 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1879 allow_naked_reg
= (ask_naked_reg
< 0);
1881 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1883 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1884 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1885 register_prefix
= allow_naked_reg
? "" : "%";
1889 set_intel_mnemonic (int mnemonic_flag
)
1891 intel_mnemonic
= mnemonic_flag
;
1895 set_allow_index_reg (int flag
)
1897 allow_index_reg
= flag
;
1901 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1905 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1907 char *string
= input_line_pointer
;
1908 int e
= get_symbol_end ();
1910 if (strcmp (string
, "none") == 0)
1911 sse_check
= sse_check_none
;
1912 else if (strcmp (string
, "warning") == 0)
1913 sse_check
= sse_check_warning
;
1914 else if (strcmp (string
, "error") == 0)
1915 sse_check
= sse_check_error
;
1917 as_bad (_("bad argument to sse_check directive."));
1918 *input_line_pointer
= e
;
1921 as_bad (_("missing argument for sse_check directive"));
1923 demand_empty_rest_of_line ();
1927 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1931 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1933 char *string
= input_line_pointer
;
1934 int e
= get_symbol_end ();
1936 i386_cpu_flags flags
;
1938 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1940 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1944 cpu_arch_name
= cpu_arch
[i
].name
;
1945 cpu_sub_arch_name
= NULL
;
1946 cpu_arch_flags
= cpu_arch
[i
].flags
;
1947 if (flag_code
== CODE_64BIT
)
1949 cpu_arch_flags
.bitfield
.cpu64
= 1;
1950 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1954 cpu_arch_flags
.bitfield
.cpu64
= 0;
1955 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1957 cpu_arch_isa
= cpu_arch
[i
].type
;
1958 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1959 if (!cpu_arch_tune_set
)
1961 cpu_arch_tune
= cpu_arch_isa
;
1962 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1967 flags
= cpu_flags_or (cpu_arch_flags
,
1969 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1971 if (cpu_sub_arch_name
)
1973 char *name
= cpu_sub_arch_name
;
1974 cpu_sub_arch_name
= concat (name
,
1976 (const char *) NULL
);
1980 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1981 cpu_arch_flags
= flags
;
1983 *input_line_pointer
= e
;
1984 demand_empty_rest_of_line ();
1988 if (i
>= ARRAY_SIZE (cpu_arch
))
1989 as_bad (_("no such architecture: `%s'"), string
);
1991 *input_line_pointer
= e
;
1994 as_bad (_("missing cpu architecture"));
1996 no_cond_jump_promotion
= 0;
1997 if (*input_line_pointer
== ','
1998 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2000 char *string
= ++input_line_pointer
;
2001 int e
= get_symbol_end ();
2003 if (strcmp (string
, "nojumps") == 0)
2004 no_cond_jump_promotion
= 1;
2005 else if (strcmp (string
, "jumps") == 0)
2008 as_bad (_("no such architecture modifier: `%s'"), string
);
2010 *input_line_pointer
= e
;
2013 demand_empty_rest_of_line ();
2019 if (!strcmp (default_arch
, "x86_64"))
2020 return bfd_mach_x86_64
;
2021 else if (!strcmp (default_arch
, "i386"))
2022 return bfd_mach_i386_i386
;
2024 as_fatal (_("Unknown architecture"));
2030 const char *hash_err
;
2032 /* Initialize op_hash hash table. */
2033 op_hash
= hash_new ();
2036 const template *optab
;
2037 templates
*core_optab
;
2039 /* Setup for loop. */
2041 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2042 core_optab
->start
= optab
;
2047 if (optab
->name
== NULL
2048 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2050 /* different name --> ship out current template list;
2051 add to hash table; & begin anew. */
2052 core_optab
->end
= optab
;
2053 hash_err
= hash_insert (op_hash
,
2055 (void *) core_optab
);
2058 as_fatal (_("Internal Error: Can't hash %s: %s"),
2062 if (optab
->name
== NULL
)
2064 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2065 core_optab
->start
= optab
;
2070 /* Initialize reg_hash hash table. */
2071 reg_hash
= hash_new ();
2073 const reg_entry
*regtab
;
2074 unsigned int regtab_size
= i386_regtab_size
;
2076 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2078 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2080 as_fatal (_("Internal Error: Can't hash %s: %s"),
2086 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2091 for (c
= 0; c
< 256; c
++)
2096 mnemonic_chars
[c
] = c
;
2097 register_chars
[c
] = c
;
2098 operand_chars
[c
] = c
;
2100 else if (ISLOWER (c
))
2102 mnemonic_chars
[c
] = c
;
2103 register_chars
[c
] = c
;
2104 operand_chars
[c
] = c
;
2106 else if (ISUPPER (c
))
2108 mnemonic_chars
[c
] = TOLOWER (c
);
2109 register_chars
[c
] = mnemonic_chars
[c
];
2110 operand_chars
[c
] = c
;
2113 if (ISALPHA (c
) || ISDIGIT (c
))
2114 identifier_chars
[c
] = c
;
2117 identifier_chars
[c
] = c
;
2118 operand_chars
[c
] = c
;
2123 identifier_chars
['@'] = '@';
2126 identifier_chars
['?'] = '?';
2127 operand_chars
['?'] = '?';
2129 digit_chars
['-'] = '-';
2130 mnemonic_chars
['_'] = '_';
2131 mnemonic_chars
['-'] = '-';
2132 mnemonic_chars
['.'] = '.';
2133 identifier_chars
['_'] = '_';
2134 identifier_chars
['.'] = '.';
2136 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2137 operand_chars
[(unsigned char) *p
] = *p
;
2140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2143 record_alignment (text_section
, 2);
2144 record_alignment (data_section
, 2);
2145 record_alignment (bss_section
, 2);
2149 if (flag_code
== CODE_64BIT
)
2151 x86_dwarf2_return_column
= 16;
2152 x86_cie_data_alignment
= -8;
2156 x86_dwarf2_return_column
= 8;
2157 x86_cie_data_alignment
= -4;
2162 i386_print_statistics (FILE *file
)
2164 hash_print_statistics (file
, "i386 opcode", op_hash
);
2165 hash_print_statistics (file
, "i386 register", reg_hash
);
2170 /* Debugging routines for md_assemble. */
2171 static void pte (template *);
2172 static void pt (i386_operand_type
);
2173 static void pe (expressionS
*);
2174 static void ps (symbolS
*);
2177 pi (char *line
, i386_insn
*x
)
2181 fprintf (stdout
, "%s: template ", line
);
2183 fprintf (stdout
, " address: base %s index %s scale %x\n",
2184 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2185 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2186 x
->log2_scale_factor
);
2187 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2188 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2189 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2190 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2191 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2192 (x
->rex
& REX_W
) != 0,
2193 (x
->rex
& REX_R
) != 0,
2194 (x
->rex
& REX_X
) != 0,
2195 (x
->rex
& REX_B
) != 0);
2196 for (i
= 0; i
< x
->operands
; i
++)
2198 fprintf (stdout
, " #%d: ", i
+ 1);
2200 fprintf (stdout
, "\n");
2201 if (x
->types
[i
].bitfield
.reg8
2202 || x
->types
[i
].bitfield
.reg16
2203 || x
->types
[i
].bitfield
.reg32
2204 || x
->types
[i
].bitfield
.reg64
2205 || x
->types
[i
].bitfield
.regmmx
2206 || x
->types
[i
].bitfield
.regxmm
2207 || x
->types
[i
].bitfield
.regymm
2208 || x
->types
[i
].bitfield
.sreg2
2209 || x
->types
[i
].bitfield
.sreg3
2210 || x
->types
[i
].bitfield
.control
2211 || x
->types
[i
].bitfield
.debug
2212 || x
->types
[i
].bitfield
.test
)
2213 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2214 if (operand_type_check (x
->types
[i
], imm
))
2216 if (operand_type_check (x
->types
[i
], disp
))
2217 pe (x
->op
[i
].disps
);
2225 fprintf (stdout
, " %d operands ", t
->operands
);
2226 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2227 if (t
->extension_opcode
!= None
)
2228 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2229 if (t
->opcode_modifier
.d
)
2230 fprintf (stdout
, "D");
2231 if (t
->opcode_modifier
.w
)
2232 fprintf (stdout
, "W");
2233 fprintf (stdout
, "\n");
2234 for (i
= 0; i
< t
->operands
; i
++)
2236 fprintf (stdout
, " #%d type ", i
+ 1);
2237 pt (t
->operand_types
[i
]);
2238 fprintf (stdout
, "\n");
2245 fprintf (stdout
, " operation %d\n", e
->X_op
);
2246 fprintf (stdout
, " add_number %ld (%lx)\n",
2247 (long) e
->X_add_number
, (long) e
->X_add_number
);
2248 if (e
->X_add_symbol
)
2250 fprintf (stdout
, " add_symbol ");
2251 ps (e
->X_add_symbol
);
2252 fprintf (stdout
, "\n");
2256 fprintf (stdout
, " op_symbol ");
2257 ps (e
->X_op_symbol
);
2258 fprintf (stdout
, "\n");
2265 fprintf (stdout
, "%s type %s%s",
2267 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2268 segment_name (S_GET_SEGMENT (s
)));
2271 static struct type_name
2273 i386_operand_type mask
;
2276 const type_names
[] =
2278 { OPERAND_TYPE_REG8
, "r8" },
2279 { OPERAND_TYPE_REG16
, "r16" },
2280 { OPERAND_TYPE_REG32
, "r32" },
2281 { OPERAND_TYPE_REG64
, "r64" },
2282 { OPERAND_TYPE_IMM8
, "i8" },
2283 { OPERAND_TYPE_IMM8
, "i8s" },
2284 { OPERAND_TYPE_IMM16
, "i16" },
2285 { OPERAND_TYPE_IMM32
, "i32" },
2286 { OPERAND_TYPE_IMM32S
, "i32s" },
2287 { OPERAND_TYPE_IMM64
, "i64" },
2288 { OPERAND_TYPE_IMM1
, "i1" },
2289 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2290 { OPERAND_TYPE_DISP8
, "d8" },
2291 { OPERAND_TYPE_DISP16
, "d16" },
2292 { OPERAND_TYPE_DISP32
, "d32" },
2293 { OPERAND_TYPE_DISP32S
, "d32s" },
2294 { OPERAND_TYPE_DISP64
, "d64" },
2295 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2296 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2297 { OPERAND_TYPE_CONTROL
, "control reg" },
2298 { OPERAND_TYPE_TEST
, "test reg" },
2299 { OPERAND_TYPE_DEBUG
, "debug reg" },
2300 { OPERAND_TYPE_FLOATREG
, "FReg" },
2301 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2302 { OPERAND_TYPE_SREG2
, "SReg2" },
2303 { OPERAND_TYPE_SREG3
, "SReg3" },
2304 { OPERAND_TYPE_ACC
, "Acc" },
2305 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2306 { OPERAND_TYPE_REGMMX
, "rMMX" },
2307 { OPERAND_TYPE_REGXMM
, "rXMM" },
2308 { OPERAND_TYPE_REGYMM
, "rYMM" },
2309 { OPERAND_TYPE_ESSEG
, "es" },
2313 pt (i386_operand_type t
)
2316 i386_operand_type a
;
2318 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2320 a
= operand_type_and (t
, type_names
[j
].mask
);
2321 if (!operand_type_all_zero (&a
))
2322 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2327 #endif /* DEBUG386 */
2329 static bfd_reloc_code_real_type
2330 reloc (unsigned int size
,
2333 bfd_reloc_code_real_type other
)
2335 if (other
!= NO_RELOC
)
2337 reloc_howto_type
*reloc
;
2342 case BFD_RELOC_X86_64_GOT32
:
2343 return BFD_RELOC_X86_64_GOT64
;
2345 case BFD_RELOC_X86_64_PLTOFF64
:
2346 return BFD_RELOC_X86_64_PLTOFF64
;
2348 case BFD_RELOC_X86_64_GOTPC32
:
2349 other
= BFD_RELOC_X86_64_GOTPC64
;
2351 case BFD_RELOC_X86_64_GOTPCREL
:
2352 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2354 case BFD_RELOC_X86_64_TPOFF32
:
2355 other
= BFD_RELOC_X86_64_TPOFF64
;
2357 case BFD_RELOC_X86_64_DTPOFF32
:
2358 other
= BFD_RELOC_X86_64_DTPOFF64
;
2364 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2365 if (size
== 4 && flag_code
!= CODE_64BIT
)
2368 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2370 as_bad (_("unknown relocation (%u)"), other
);
2371 else if (size
!= bfd_get_reloc_size (reloc
))
2372 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2373 bfd_get_reloc_size (reloc
),
2375 else if (pcrel
&& !reloc
->pc_relative
)
2376 as_bad (_("non-pc-relative relocation for pc-relative field"));
2377 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2379 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2381 as_bad (_("relocated field and relocation type differ in signedness"));
2390 as_bad (_("there are no unsigned pc-relative relocations"));
2393 case 1: return BFD_RELOC_8_PCREL
;
2394 case 2: return BFD_RELOC_16_PCREL
;
2395 case 4: return BFD_RELOC_32_PCREL
;
2396 case 8: return BFD_RELOC_64_PCREL
;
2398 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2405 case 4: return BFD_RELOC_X86_64_32S
;
2410 case 1: return BFD_RELOC_8
;
2411 case 2: return BFD_RELOC_16
;
2412 case 4: return BFD_RELOC_32
;
2413 case 8: return BFD_RELOC_64
;
2415 as_bad (_("cannot do %s %u byte relocation"),
2416 sign
> 0 ? "signed" : "unsigned", size
);
2422 /* Here we decide which fixups can be adjusted to make them relative to
2423 the beginning of the section instead of the symbol. Basically we need
2424 to make sure that the dynamic relocations are done correctly, so in
2425 some cases we force the original symbol to be used. */
2428 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2434 /* Don't adjust pc-relative references to merge sections in 64-bit
2436 if (use_rela_relocations
2437 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2441 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2442 and changed later by validate_fix. */
2443 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2444 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2447 /* adjust_reloc_syms doesn't know about the GOT. */
2448 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2449 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2450 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2451 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2452 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2453 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2454 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2455 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2456 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2457 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2458 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2459 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2460 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2461 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2462 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2463 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2464 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2465 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2466 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2467 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2468 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2469 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2474 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2475 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2478 if (fixP
->fx_addsy
!= NULL
2479 && symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_GNU_INDIRECT_FUNCTION
)
2486 intel_float_operand (const char *mnemonic
)
2488 /* Note that the value returned is meaningful only for opcodes with (memory)
2489 operands, hence the code here is free to improperly handle opcodes that
2490 have no operands (for better performance and smaller code). */
2492 if (mnemonic
[0] != 'f')
2493 return 0; /* non-math */
2495 switch (mnemonic
[1])
2497 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2498 the fs segment override prefix not currently handled because no
2499 call path can make opcodes without operands get here */
2501 return 2 /* integer op */;
2503 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2504 return 3; /* fldcw/fldenv */
2507 if (mnemonic
[2] != 'o' /* fnop */)
2508 return 3; /* non-waiting control op */
2511 if (mnemonic
[2] == 's')
2512 return 3; /* frstor/frstpm */
2515 if (mnemonic
[2] == 'a')
2516 return 3; /* fsave */
2517 if (mnemonic
[2] == 't')
2519 switch (mnemonic
[3])
2521 case 'c': /* fstcw */
2522 case 'd': /* fstdw */
2523 case 'e': /* fstenv */
2524 case 's': /* fsts[gw] */
2530 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2531 return 0; /* fxsave/fxrstor are not really math ops */
2538 /* Build the VEX prefix. */
2541 build_vex_prefix (const template *t
)
2543 unsigned int register_specifier
;
2544 unsigned int implied_prefix
;
2545 unsigned int vector_length
;
2547 /* Check register specifier. */
2548 if (i
.vex
.register_specifier
)
2550 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2551 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2552 register_specifier
+= 8;
2553 register_specifier
= ~register_specifier
& 0xf;
2556 register_specifier
= 0xf;
2558 /* Use 2-byte VEX prefix by swappping destination and source
2561 && i
.operands
== i
.reg_operands
2562 && i
.tm
.opcode_modifier
.vex0f
2563 && i
.tm
.opcode_modifier
.s
2566 unsigned int xchg
= i
.operands
- 1;
2567 union i386_op temp_op
;
2568 i386_operand_type temp_type
;
2570 temp_type
= i
.types
[xchg
];
2571 i
.types
[xchg
] = i
.types
[0];
2572 i
.types
[0] = temp_type
;
2573 temp_op
= i
.op
[xchg
];
2574 i
.op
[xchg
] = i
.op
[0];
2577 gas_assert (i
.rm
.mode
== 3);
2581 i
.rm
.regmem
= i
.rm
.reg
;
2584 /* Use the next insn. */
2588 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2590 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2595 case DATA_PREFIX_OPCODE
:
2598 case REPE_PREFIX_OPCODE
:
2601 case REPNE_PREFIX_OPCODE
:
2608 /* Use 2-byte VEX prefix if possible. */
2609 if (i
.tm
.opcode_modifier
.vex0f
2610 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2612 /* 2-byte VEX prefix. */
2616 i
.vex
.bytes
[0] = 0xc5;
2618 /* Check the REX.R bit. */
2619 r
= (i
.rex
& REX_R
) ? 0 : 1;
2620 i
.vex
.bytes
[1] = (r
<< 7
2621 | register_specifier
<< 3
2622 | vector_length
<< 2
2627 /* 3-byte VEX prefix. */
2630 if (i
.tm
.opcode_modifier
.vex0f
)
2632 else if (i
.tm
.opcode_modifier
.vex0f38
)
2634 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2640 i
.vex
.bytes
[0] = 0xc4;
2642 /* The high 3 bits of the second VEX byte are 1's compliment
2643 of RXB bits from REX. */
2644 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2646 /* Check the REX.W bit. */
2647 w
= (i
.rex
& REX_W
) ? 1 : 0;
2648 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2653 if (i
.tm
.opcode_modifier
.vexw1
)
2657 i
.vex
.bytes
[2] = (w
<< 7
2658 | register_specifier
<< 3
2659 | vector_length
<< 2
2665 process_immext (void)
2669 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2671 /* SSE3 Instructions have the fixed operands with an opcode
2672 suffix which is coded in the same place as an 8-bit immediate
2673 field would be. Here we check those operands and remove them
2677 for (x
= 0; x
< i
.operands
; x
++)
2678 if (i
.op
[x
].regs
->reg_num
!= x
)
2679 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2680 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2686 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2687 which is coded in the same place as an 8-bit immediate field
2688 would be. Here we fake an 8-bit immediate operand from the
2689 opcode suffix stored in tm.extension_opcode.
2691 AVX instructions also use this encoding, for some of
2692 3 argument instructions. */
2694 gas_assert (i
.imm_operands
== 0
2696 || (i
.tm
.opcode_modifier
.vex
2697 && i
.operands
<= 4)));
2699 exp
= &im_expressions
[i
.imm_operands
++];
2700 i
.op
[i
.operands
].imms
= exp
;
2701 i
.types
[i
.operands
] = imm8
;
2703 exp
->X_op
= O_constant
;
2704 exp
->X_add_number
= i
.tm
.extension_opcode
;
2705 i
.tm
.extension_opcode
= None
;
2708 /* This is the guts of the machine-dependent assembler. LINE points to a
2709 machine dependent instruction. This function is supposed to emit
2710 the frags/bytes it assembles to. */
2713 md_assemble (char *line
)
2716 char mnemonic
[MAX_MNEM_SIZE
];
2719 /* Initialize globals. */
2720 memset (&i
, '\0', sizeof (i
));
2721 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2722 i
.reloc
[j
] = NO_RELOC
;
2723 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2724 memset (im_expressions
, '\0', sizeof (im_expressions
));
2725 save_stack_p
= save_stack
;
2727 /* First parse an instruction mnemonic & call i386_operand for the operands.
2728 We assume that the scrubber has arranged it so that line[0] is the valid
2729 start of a (possibly prefixed) mnemonic. */
2731 line
= parse_insn (line
, mnemonic
);
2735 line
= parse_operands (line
, mnemonic
);
2740 /* Now we've parsed the mnemonic into a set of templates, and have the
2741 operands at hand. */
2743 /* All intel opcodes have reversed operands except for "bound" and
2744 "enter". We also don't reverse intersegment "jmp" and "call"
2745 instructions with 2 immediate operands so that the immediate segment
2746 precedes the offset, as it does when in AT&T mode. */
2749 && (strcmp (mnemonic
, "bound") != 0)
2750 && (strcmp (mnemonic
, "invlpga") != 0)
2751 && !(operand_type_check (i
.types
[0], imm
)
2752 && operand_type_check (i
.types
[1], imm
)))
2755 /* The order of the immediates should be reversed
2756 for 2 immediates extrq and insertq instructions */
2757 if (i
.imm_operands
== 2
2758 && (strcmp (mnemonic
, "extrq") == 0
2759 || strcmp (mnemonic
, "insertq") == 0))
2760 swap_2_operands (0, 1);
2765 /* Don't optimize displacement for movabs since it only takes 64bit
2768 && (flag_code
!= CODE_64BIT
2769 || strcmp (mnemonic
, "movabs") != 0))
2772 /* Next, we find a template that matches the given insn,
2773 making sure the overlap of the given operands types is consistent
2774 with the template operand types. */
2776 if (!(t
= match_template ()))
2779 if (sse_check
!= sse_check_none
2780 && !i
.tm
.opcode_modifier
.noavx
2781 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2782 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2783 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2784 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2785 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2786 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2788 (sse_check
== sse_check_warning
2790 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2793 /* Zap movzx and movsx suffix. The suffix has been set from
2794 "word ptr" or "byte ptr" on the source operand in Intel syntax
2795 or extracted from mnemonic in AT&T syntax. But we'll use
2796 the destination register to choose the suffix for encoding. */
2797 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2799 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2800 there is no suffix, the default will be byte extension. */
2801 if (i
.reg_operands
!= 2
2804 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2809 if (i
.tm
.opcode_modifier
.fwait
)
2810 if (!add_prefix (FWAIT_OPCODE
))
2813 /* Check string instruction segment overrides. */
2814 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2816 if (!check_string ())
2818 i
.disp_operands
= 0;
2821 if (!process_suffix ())
2824 /* Update operand types. */
2825 for (j
= 0; j
< i
.operands
; j
++)
2826 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2828 /* Make still unresolved immediate matches conform to size of immediate
2829 given in i.suffix. */
2830 if (!finalize_imm ())
2833 if (i
.types
[0].bitfield
.imm1
)
2834 i
.imm_operands
= 0; /* kludge for shift insns. */
2836 /* We only need to check those implicit registers for instructions
2837 with 3 operands or less. */
2838 if (i
.operands
<= 3)
2839 for (j
= 0; j
< i
.operands
; j
++)
2840 if (i
.types
[j
].bitfield
.inoutportreg
2841 || i
.types
[j
].bitfield
.shiftcount
2842 || i
.types
[j
].bitfield
.acc
2843 || i
.types
[j
].bitfield
.floatacc
)
2846 /* ImmExt should be processed after SSE2AVX. */
2847 if (!i
.tm
.opcode_modifier
.sse2avx
2848 && i
.tm
.opcode_modifier
.immext
)
2851 /* For insns with operands there are more diddles to do to the opcode. */
2854 if (!process_operands ())
2857 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2859 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2860 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2863 if (i
.tm
.opcode_modifier
.vex
)
2864 build_vex_prefix (t
);
2866 /* Handle conversion of 'int $3' --> special int3 insn. */
2867 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2869 i
.tm
.base_opcode
= INT3_OPCODE
;
2873 if ((i
.tm
.opcode_modifier
.jump
2874 || i
.tm
.opcode_modifier
.jumpbyte
2875 || i
.tm
.opcode_modifier
.jumpdword
)
2876 && i
.op
[0].disps
->X_op
== O_constant
)
2878 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2879 the absolute address given by the constant. Since ix86 jumps and
2880 calls are pc relative, we need to generate a reloc. */
2881 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2882 i
.op
[0].disps
->X_op
= O_symbol
;
2885 if (i
.tm
.opcode_modifier
.rex64
)
2888 /* For 8 bit registers we need an empty rex prefix. Also if the
2889 instruction already has a prefix, we need to convert old
2890 registers to new ones. */
2892 if ((i
.types
[0].bitfield
.reg8
2893 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2894 || (i
.types
[1].bitfield
.reg8
2895 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2896 || ((i
.types
[0].bitfield
.reg8
2897 || i
.types
[1].bitfield
.reg8
)
2902 i
.rex
|= REX_OPCODE
;
2903 for (x
= 0; x
< 2; x
++)
2905 /* Look for 8 bit operand that uses old registers. */
2906 if (i
.types
[x
].bitfield
.reg8
2907 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2909 /* In case it is "hi" register, give up. */
2910 if (i
.op
[x
].regs
->reg_num
> 3)
2911 as_bad (_("can't encode register '%s%s' in an "
2912 "instruction requiring REX prefix."),
2913 register_prefix
, i
.op
[x
].regs
->reg_name
);
2915 /* Otherwise it is equivalent to the extended register.
2916 Since the encoding doesn't change this is merely
2917 cosmetic cleanup for debug output. */
2919 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2925 add_prefix (REX_OPCODE
| i
.rex
);
2927 /* We are ready to output the insn. */
2932 parse_insn (char *line
, char *mnemonic
)
2935 char *token_start
= l
;
2941 /* Non-zero if we found a prefix only acceptable with string insns. */
2942 const char *expecting_string_instruction
= NULL
;
2947 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2952 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2954 as_bad (_("no such instruction: `%s'"), token_start
);
2959 if (!is_space_char (*l
)
2960 && *l
!= END_OF_INSN
2962 || (*l
!= PREFIX_SEPARATOR
2965 as_bad (_("invalid character %s in mnemonic"),
2966 output_invalid (*l
));
2969 if (token_start
== l
)
2971 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2972 as_bad (_("expecting prefix; got nothing"));
2974 as_bad (_("expecting mnemonic; got nothing"));
2978 /* Look up instruction (or prefix) via hash table. */
2979 current_templates
= hash_find (op_hash
, mnemonic
);
2981 if (*l
!= END_OF_INSN
2982 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2983 && current_templates
2984 && current_templates
->start
->opcode_modifier
.isprefix
)
2986 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2988 as_bad ((flag_code
!= CODE_64BIT
2989 ? _("`%s' is only supported in 64-bit mode")
2990 : _("`%s' is not supported in 64-bit mode")),
2991 current_templates
->start
->name
);
2994 /* If we are in 16-bit mode, do not allow addr16 or data16.
2995 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2996 if ((current_templates
->start
->opcode_modifier
.size16
2997 || current_templates
->start
->opcode_modifier
.size32
)
2998 && flag_code
!= CODE_64BIT
2999 && (current_templates
->start
->opcode_modifier
.size32
3000 ^ (flag_code
== CODE_16BIT
)))
3002 as_bad (_("redundant %s prefix"),
3003 current_templates
->start
->name
);
3006 /* Add prefix, checking for repeated prefixes. */
3007 switch (add_prefix (current_templates
->start
->base_opcode
))
3012 expecting_string_instruction
= current_templates
->start
->name
;
3015 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3022 if (!current_templates
)
3024 /* Check if we should swap operand in encoding. */
3025 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3031 current_templates
= hash_find (op_hash
, mnemonic
);
3034 if (!current_templates
)
3037 /* See if we can get a match by trimming off a suffix. */
3040 case WORD_MNEM_SUFFIX
:
3041 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3042 i
.suffix
= SHORT_MNEM_SUFFIX
;
3044 case BYTE_MNEM_SUFFIX
:
3045 case QWORD_MNEM_SUFFIX
:
3046 i
.suffix
= mnem_p
[-1];
3048 current_templates
= hash_find (op_hash
, mnemonic
);
3050 case SHORT_MNEM_SUFFIX
:
3051 case LONG_MNEM_SUFFIX
:
3054 i
.suffix
= mnem_p
[-1];
3056 current_templates
= hash_find (op_hash
, mnemonic
);
3064 if (intel_float_operand (mnemonic
) == 1)
3065 i
.suffix
= SHORT_MNEM_SUFFIX
;
3067 i
.suffix
= LONG_MNEM_SUFFIX
;
3069 current_templates
= hash_find (op_hash
, mnemonic
);
3073 if (!current_templates
)
3075 as_bad (_("no such instruction: `%s'"), token_start
);
3080 if (current_templates
->start
->opcode_modifier
.jump
3081 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3083 /* Check for a branch hint. We allow ",pt" and ",pn" for
3084 predict taken and predict not taken respectively.
3085 I'm not sure that branch hints actually do anything on loop
3086 and jcxz insns (JumpByte) for current Pentium4 chips. They
3087 may work in the future and it doesn't hurt to accept them
3089 if (l
[0] == ',' && l
[1] == 'p')
3093 if (!add_prefix (DS_PREFIX_OPCODE
))
3097 else if (l
[2] == 'n')
3099 if (!add_prefix (CS_PREFIX_OPCODE
))
3105 /* Any other comma loses. */
3108 as_bad (_("invalid character %s in mnemonic"),
3109 output_invalid (*l
));
3113 /* Check if instruction is supported on specified architecture. */
3115 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3117 supported
|= cpu_flags_match (t
);
3118 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3122 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3124 as_bad (flag_code
== CODE_64BIT
3125 ? _("`%s' is not supported in 64-bit mode")
3126 : _("`%s' is only supported in 64-bit mode"),
3127 current_templates
->start
->name
);
3130 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3132 as_bad (_("`%s' is not supported on `%s%s'"),
3133 current_templates
->start
->name
,
3134 cpu_arch_name
? cpu_arch_name
: default_arch
,
3135 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3140 if (!cpu_arch_flags
.bitfield
.cpui386
3141 && (flag_code
!= CODE_16BIT
))
3143 as_warn (_("use .code16 to ensure correct addressing mode"));
3146 /* Check for rep/repne without a string instruction. */
3147 if (expecting_string_instruction
)
3149 static templates override
;
3151 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3152 if (t
->opcode_modifier
.isstring
)
3154 if (t
>= current_templates
->end
)
3156 as_bad (_("expecting string instruction after `%s'"),
3157 expecting_string_instruction
);
3160 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3161 if (!t
->opcode_modifier
.isstring
)
3164 current_templates
= &override
;
3171 parse_operands (char *l
, const char *mnemonic
)
3175 /* 1 if operand is pending after ','. */
3176 unsigned int expecting_operand
= 0;
3178 /* Non-zero if operand parens not balanced. */
3179 unsigned int paren_not_balanced
;
3181 while (*l
!= END_OF_INSN
)
3183 /* Skip optional white space before operand. */
3184 if (is_space_char (*l
))
3186 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3188 as_bad (_("invalid character %s before operand %d"),
3189 output_invalid (*l
),
3193 token_start
= l
; /* after white space */
3194 paren_not_balanced
= 0;
3195 while (paren_not_balanced
|| *l
!= ',')
3197 if (*l
== END_OF_INSN
)
3199 if (paren_not_balanced
)
3202 as_bad (_("unbalanced parenthesis in operand %d."),
3205 as_bad (_("unbalanced brackets in operand %d."),
3210 break; /* we are done */
3212 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3214 as_bad (_("invalid character %s in operand %d"),
3215 output_invalid (*l
),
3222 ++paren_not_balanced
;
3224 --paren_not_balanced
;
3229 ++paren_not_balanced
;
3231 --paren_not_balanced
;
3235 if (l
!= token_start
)
3236 { /* Yes, we've read in another operand. */
3237 unsigned int operand_ok
;
3238 this_operand
= i
.operands
++;
3239 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3240 if (i
.operands
> MAX_OPERANDS
)
3242 as_bad (_("spurious operands; (%d operands/instruction max)"),
3246 /* Now parse operand adding info to 'i' as we go along. */
3247 END_STRING_AND_SAVE (l
);
3251 i386_intel_operand (token_start
,
3252 intel_float_operand (mnemonic
));
3254 operand_ok
= i386_att_operand (token_start
);
3256 RESTORE_END_STRING (l
);
3262 if (expecting_operand
)
3264 expecting_operand_after_comma
:
3265 as_bad (_("expecting operand after ','; got nothing"));
3270 as_bad (_("expecting operand before ','; got nothing"));
3275 /* Now *l must be either ',' or END_OF_INSN. */
3278 if (*++l
== END_OF_INSN
)
3280 /* Just skip it, if it's \n complain. */
3281 goto expecting_operand_after_comma
;
3283 expecting_operand
= 1;
3290 swap_2_operands (int xchg1
, int xchg2
)
3292 union i386_op temp_op
;
3293 i386_operand_type temp_type
;
3294 enum bfd_reloc_code_real temp_reloc
;
3296 temp_type
= i
.types
[xchg2
];
3297 i
.types
[xchg2
] = i
.types
[xchg1
];
3298 i
.types
[xchg1
] = temp_type
;
3299 temp_op
= i
.op
[xchg2
];
3300 i
.op
[xchg2
] = i
.op
[xchg1
];
3301 i
.op
[xchg1
] = temp_op
;
3302 temp_reloc
= i
.reloc
[xchg2
];
3303 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3304 i
.reloc
[xchg1
] = temp_reloc
;
3308 swap_operands (void)
3314 swap_2_operands (1, i
.operands
- 2);
3317 swap_2_operands (0, i
.operands
- 1);
3323 if (i
.mem_operands
== 2)
3325 const seg_entry
*temp_seg
;
3326 temp_seg
= i
.seg
[0];
3327 i
.seg
[0] = i
.seg
[1];
3328 i
.seg
[1] = temp_seg
;
3332 /* Try to ensure constant immediates are represented in the smallest
3337 char guess_suffix
= 0;
3341 guess_suffix
= i
.suffix
;
3342 else if (i
.reg_operands
)
3344 /* Figure out a suffix from the last register operand specified.
3345 We can't do this properly yet, ie. excluding InOutPortReg,
3346 but the following works for instructions with immediates.
3347 In any case, we can't set i.suffix yet. */
3348 for (op
= i
.operands
; --op
>= 0;)
3349 if (i
.types
[op
].bitfield
.reg8
)
3351 guess_suffix
= BYTE_MNEM_SUFFIX
;
3354 else if (i
.types
[op
].bitfield
.reg16
)
3356 guess_suffix
= WORD_MNEM_SUFFIX
;
3359 else if (i
.types
[op
].bitfield
.reg32
)
3361 guess_suffix
= LONG_MNEM_SUFFIX
;
3364 else if (i
.types
[op
].bitfield
.reg64
)
3366 guess_suffix
= QWORD_MNEM_SUFFIX
;
3370 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3371 guess_suffix
= WORD_MNEM_SUFFIX
;
3373 for (op
= i
.operands
; --op
>= 0;)
3374 if (operand_type_check (i
.types
[op
], imm
))
3376 switch (i
.op
[op
].imms
->X_op
)
3379 /* If a suffix is given, this operand may be shortened. */
3380 switch (guess_suffix
)
3382 case LONG_MNEM_SUFFIX
:
3383 i
.types
[op
].bitfield
.imm32
= 1;
3384 i
.types
[op
].bitfield
.imm64
= 1;
3386 case WORD_MNEM_SUFFIX
:
3387 i
.types
[op
].bitfield
.imm16
= 1;
3388 i
.types
[op
].bitfield
.imm32
= 1;
3389 i
.types
[op
].bitfield
.imm32s
= 1;
3390 i
.types
[op
].bitfield
.imm64
= 1;
3392 case BYTE_MNEM_SUFFIX
:
3393 i
.types
[op
].bitfield
.imm8
= 1;
3394 i
.types
[op
].bitfield
.imm8s
= 1;
3395 i
.types
[op
].bitfield
.imm16
= 1;
3396 i
.types
[op
].bitfield
.imm32
= 1;
3397 i
.types
[op
].bitfield
.imm32s
= 1;
3398 i
.types
[op
].bitfield
.imm64
= 1;
3402 /* If this operand is at most 16 bits, convert it
3403 to a signed 16 bit number before trying to see
3404 whether it will fit in an even smaller size.
3405 This allows a 16-bit operand such as $0xffe0 to
3406 be recognised as within Imm8S range. */
3407 if ((i
.types
[op
].bitfield
.imm16
)
3408 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3410 i
.op
[op
].imms
->X_add_number
=
3411 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3413 if ((i
.types
[op
].bitfield
.imm32
)
3414 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3417 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3418 ^ ((offsetT
) 1 << 31))
3419 - ((offsetT
) 1 << 31));
3422 = operand_type_or (i
.types
[op
],
3423 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3425 /* We must avoid matching of Imm32 templates when 64bit
3426 only immediate is available. */
3427 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3428 i
.types
[op
].bitfield
.imm32
= 0;
3435 /* Symbols and expressions. */
3437 /* Convert symbolic operand to proper sizes for matching, but don't
3438 prevent matching a set of insns that only supports sizes other
3439 than those matching the insn suffix. */
3441 i386_operand_type mask
, allowed
;
3444 operand_type_set (&mask
, 0);
3445 operand_type_set (&allowed
, 0);
3447 for (t
= current_templates
->start
;
3448 t
< current_templates
->end
;
3450 allowed
= operand_type_or (allowed
,
3451 t
->operand_types
[op
]);
3452 switch (guess_suffix
)
3454 case QWORD_MNEM_SUFFIX
:
3455 mask
.bitfield
.imm64
= 1;
3456 mask
.bitfield
.imm32s
= 1;
3458 case LONG_MNEM_SUFFIX
:
3459 mask
.bitfield
.imm32
= 1;
3461 case WORD_MNEM_SUFFIX
:
3462 mask
.bitfield
.imm16
= 1;
3464 case BYTE_MNEM_SUFFIX
:
3465 mask
.bitfield
.imm8
= 1;
3470 allowed
= operand_type_and (mask
, allowed
);
3471 if (!operand_type_all_zero (&allowed
))
3472 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3479 /* Try to use the smallest displacement type too. */
3481 optimize_disp (void)
3485 for (op
= i
.operands
; --op
>= 0;)
3486 if (operand_type_check (i
.types
[op
], disp
))
3488 if (i
.op
[op
].disps
->X_op
== O_constant
)
3490 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3492 if (i
.types
[op
].bitfield
.disp16
3493 && (disp
& ~(offsetT
) 0xffff) == 0)
3495 /* If this operand is at most 16 bits, convert
3496 to a signed 16 bit number and don't use 64bit
3498 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3499 i
.types
[op
].bitfield
.disp64
= 0;
3501 if (i
.types
[op
].bitfield
.disp32
3502 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3504 /* If this operand is at most 32 bits, convert
3505 to a signed 32 bit number and don't use 64bit
3507 disp
&= (((offsetT
) 2 << 31) - 1);
3508 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3509 i
.types
[op
].bitfield
.disp64
= 0;
3511 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3513 i
.types
[op
].bitfield
.disp8
= 0;
3514 i
.types
[op
].bitfield
.disp16
= 0;
3515 i
.types
[op
].bitfield
.disp32
= 0;
3516 i
.types
[op
].bitfield
.disp32s
= 0;
3517 i
.types
[op
].bitfield
.disp64
= 0;
3521 else if (flag_code
== CODE_64BIT
)
3523 if (fits_in_signed_long (disp
))
3525 i
.types
[op
].bitfield
.disp64
= 0;
3526 i
.types
[op
].bitfield
.disp32s
= 1;
3528 if (fits_in_unsigned_long (disp
))
3529 i
.types
[op
].bitfield
.disp32
= 1;
3531 if ((i
.types
[op
].bitfield
.disp32
3532 || i
.types
[op
].bitfield
.disp32s
3533 || i
.types
[op
].bitfield
.disp16
)
3534 && fits_in_signed_byte (disp
))
3535 i
.types
[op
].bitfield
.disp8
= 1;
3537 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3538 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3540 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3541 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3542 i
.types
[op
].bitfield
.disp8
= 0;
3543 i
.types
[op
].bitfield
.disp16
= 0;
3544 i
.types
[op
].bitfield
.disp32
= 0;
3545 i
.types
[op
].bitfield
.disp32s
= 0;
3546 i
.types
[op
].bitfield
.disp64
= 0;
3549 /* We only support 64bit displacement on constants. */
3550 i
.types
[op
].bitfield
.disp64
= 0;
3554 static const template *
3555 match_template (void)
3557 /* Points to template once we've found it. */
3559 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3560 i386_operand_type overlap4
;
3561 unsigned int found_reverse_match
;
3562 i386_opcode_modifier suffix_check
;
3563 i386_operand_type operand_types
[MAX_OPERANDS
];
3564 int addr_prefix_disp
;
3566 unsigned int found_cpu_match
;
3567 unsigned int check_register
;
3569 #if MAX_OPERANDS != 5
3570 # error "MAX_OPERANDS must be 5."
3573 found_reverse_match
= 0;
3574 addr_prefix_disp
= -1;
3576 memset (&suffix_check
, 0, sizeof (suffix_check
));
3577 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3578 suffix_check
.no_bsuf
= 1;
3579 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3580 suffix_check
.no_wsuf
= 1;
3581 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3582 suffix_check
.no_ssuf
= 1;
3583 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3584 suffix_check
.no_lsuf
= 1;
3585 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3586 suffix_check
.no_qsuf
= 1;
3587 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3588 suffix_check
.no_ldsuf
= 1;
3590 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3592 addr_prefix_disp
= -1;
3594 /* Must have right number of operands. */
3595 if (i
.operands
!= t
->operands
)
3598 /* Check processor support. */
3599 found_cpu_match
= (cpu_flags_match (t
)
3600 == CPU_FLAGS_PERFECT_MATCH
);
3601 if (!found_cpu_match
)
3604 /* Check old gcc support. */
3605 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3608 /* Check AT&T mnemonic. */
3609 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3612 /* Check AT&T syntax Intel syntax. */
3613 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3614 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3617 /* Check the suffix, except for some instructions in intel mode. */
3618 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3619 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3620 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3621 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3622 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3623 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3624 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3627 if (!operand_size_match (t
))
3630 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3631 operand_types
[j
] = t
->operand_types
[j
];
3633 /* In general, don't allow 64-bit operands in 32-bit mode. */
3634 if (i
.suffix
== QWORD_MNEM_SUFFIX
3635 && flag_code
!= CODE_64BIT
3637 ? (!t
->opcode_modifier
.ignoresize
3638 && !intel_float_operand (t
->name
))
3639 : intel_float_operand (t
->name
) != 2)
3640 && ((!operand_types
[0].bitfield
.regmmx
3641 && !operand_types
[0].bitfield
.regxmm
3642 && !operand_types
[0].bitfield
.regymm
)
3643 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3644 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3645 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3646 && (t
->base_opcode
!= 0x0fc7
3647 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3650 /* In general, don't allow 32-bit operands on pre-386. */
3651 else if (i
.suffix
== LONG_MNEM_SUFFIX
3652 && !cpu_arch_flags
.bitfield
.cpui386
3654 ? (!t
->opcode_modifier
.ignoresize
3655 && !intel_float_operand (t
->name
))
3656 : intel_float_operand (t
->name
) != 2)
3657 && ((!operand_types
[0].bitfield
.regmmx
3658 && !operand_types
[0].bitfield
.regxmm
)
3659 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3660 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3663 /* Do not verify operands when there are none. */
3667 /* We've found a match; break out of loop. */
3671 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3672 into Disp32/Disp16/Disp32 operand. */
3673 if (i
.prefix
[ADDR_PREFIX
] != 0)
3675 /* There should be only one Disp operand. */
3679 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3681 if (operand_types
[j
].bitfield
.disp16
)
3683 addr_prefix_disp
= j
;
3684 operand_types
[j
].bitfield
.disp32
= 1;
3685 operand_types
[j
].bitfield
.disp16
= 0;
3691 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3693 if (operand_types
[j
].bitfield
.disp32
)
3695 addr_prefix_disp
= j
;
3696 operand_types
[j
].bitfield
.disp32
= 0;
3697 operand_types
[j
].bitfield
.disp16
= 1;
3703 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3705 if (operand_types
[j
].bitfield
.disp64
)
3707 addr_prefix_disp
= j
;
3708 operand_types
[j
].bitfield
.disp64
= 0;
3709 operand_types
[j
].bitfield
.disp32
= 1;
3717 /* We check register size only if size of operands can be
3718 encoded the canonical way. */
3719 check_register
= t
->opcode_modifier
.w
;
3720 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3721 switch (t
->operands
)
3724 if (!operand_type_match (overlap0
, i
.types
[0]))
3728 /* xchg %eax, %eax is a special case. It is an aliase for nop
3729 only in 32bit mode and we can use opcode 0x90. In 64bit
3730 mode, we can't use 0x90 for xchg %eax, %eax since it should
3731 zero-extend %eax to %rax. */
3732 if (flag_code
== CODE_64BIT
3733 && t
->base_opcode
== 0x90
3734 && operand_type_equal (&i
.types
[0], &acc32
)
3735 && operand_type_equal (&i
.types
[1], &acc32
))
3739 /* If we swap operand in encoding, we either match
3740 the next one or reverse direction of operands. */
3741 if (t
->opcode_modifier
.s
)
3743 else if (t
->opcode_modifier
.d
)
3748 /* If we swap operand in encoding, we match the next one. */
3749 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3753 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3754 if (!operand_type_match (overlap0
, i
.types
[0])
3755 || !operand_type_match (overlap1
, i
.types
[1])
3757 && !operand_type_register_match (overlap0
, i
.types
[0],
3759 overlap1
, i
.types
[1],
3762 /* Check if other direction is valid ... */
3763 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3767 /* Try reversing direction of operands. */
3768 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3769 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3770 if (!operand_type_match (overlap0
, i
.types
[0])
3771 || !operand_type_match (overlap1
, i
.types
[1])
3773 && !operand_type_register_match (overlap0
,
3780 /* Does not match either direction. */
3783 /* found_reverse_match holds which of D or FloatDR
3785 if (t
->opcode_modifier
.d
)
3786 found_reverse_match
= Opcode_D
;
3787 else if (t
->opcode_modifier
.floatd
)
3788 found_reverse_match
= Opcode_FloatD
;
3790 found_reverse_match
= 0;
3791 if (t
->opcode_modifier
.floatr
)
3792 found_reverse_match
|= Opcode_FloatR
;
3796 /* Found a forward 2 operand match here. */
3797 switch (t
->operands
)
3800 overlap4
= operand_type_and (i
.types
[4],
3803 overlap3
= operand_type_and (i
.types
[3],
3806 overlap2
= operand_type_and (i
.types
[2],
3811 switch (t
->operands
)
3814 if (!operand_type_match (overlap4
, i
.types
[4])
3815 || !operand_type_register_match (overlap3
,
3823 if (!operand_type_match (overlap3
, i
.types
[3])
3825 && !operand_type_register_match (overlap2
,
3833 /* Here we make use of the fact that there are no
3834 reverse match 3 operand instructions, and all 3
3835 operand instructions only need to be checked for
3836 register consistency between operands 2 and 3. */
3837 if (!operand_type_match (overlap2
, i
.types
[2])
3839 && !operand_type_register_match (overlap1
,
3849 /* Found either forward/reverse 2, 3 or 4 operand match here:
3850 slip through to break. */
3852 if (!found_cpu_match
)
3854 found_reverse_match
= 0;
3858 /* We've found a match; break out of loop. */
3862 if (t
== current_templates
->end
)
3864 /* We found no match. */
3866 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3867 current_templates
->start
->name
);
3869 as_bad (_("suffix or operands invalid for `%s'"),
3870 current_templates
->start
->name
);
3874 if (!quiet_warnings
)
3877 && (i
.types
[0].bitfield
.jumpabsolute
3878 != operand_types
[0].bitfield
.jumpabsolute
))
3880 as_warn (_("indirect %s without `*'"), t
->name
);
3883 if (t
->opcode_modifier
.isprefix
3884 && t
->opcode_modifier
.ignoresize
)
3886 /* Warn them that a data or address size prefix doesn't
3887 affect assembly of the next line of code. */
3888 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3892 /* Copy the template we found. */
3895 if (addr_prefix_disp
!= -1)
3896 i
.tm
.operand_types
[addr_prefix_disp
]
3897 = operand_types
[addr_prefix_disp
];
3899 if (found_reverse_match
)
3901 /* If we found a reverse match we must alter the opcode
3902 direction bit. found_reverse_match holds bits to change
3903 (different for int & float insns). */
3905 i
.tm
.base_opcode
^= found_reverse_match
;
3907 i
.tm
.operand_types
[0] = operand_types
[1];
3908 i
.tm
.operand_types
[1] = operand_types
[0];
3917 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3918 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3920 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3922 as_bad (_("`%s' operand %d must use `%ses' segment"),
3928 /* There's only ever one segment override allowed per instruction.
3929 This instruction possibly has a legal segment override on the
3930 second operand, so copy the segment to where non-string
3931 instructions store it, allowing common code. */
3932 i
.seg
[0] = i
.seg
[1];
3934 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3936 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3938 as_bad (_("`%s' operand %d must use `%ses' segment"),
3949 process_suffix (void)
3951 /* If matched instruction specifies an explicit instruction mnemonic
3953 if (i
.tm
.opcode_modifier
.size16
)
3954 i
.suffix
= WORD_MNEM_SUFFIX
;
3955 else if (i
.tm
.opcode_modifier
.size32
)
3956 i
.suffix
= LONG_MNEM_SUFFIX
;
3957 else if (i
.tm
.opcode_modifier
.size64
)
3958 i
.suffix
= QWORD_MNEM_SUFFIX
;
3959 else if (i
.reg_operands
)
3961 /* If there's no instruction mnemonic suffix we try to invent one
3962 based on register operands. */
3965 /* We take i.suffix from the last register operand specified,
3966 Destination register type is more significant than source
3967 register type. crc32 in SSE4.2 prefers source register
3969 if (i
.tm
.base_opcode
== 0xf20f38f1)
3971 if (i
.types
[0].bitfield
.reg16
)
3972 i
.suffix
= WORD_MNEM_SUFFIX
;
3973 else if (i
.types
[0].bitfield
.reg32
)
3974 i
.suffix
= LONG_MNEM_SUFFIX
;
3975 else if (i
.types
[0].bitfield
.reg64
)
3976 i
.suffix
= QWORD_MNEM_SUFFIX
;
3978 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3980 if (i
.types
[0].bitfield
.reg8
)
3981 i
.suffix
= BYTE_MNEM_SUFFIX
;
3988 if (i
.tm
.base_opcode
== 0xf20f38f1
3989 || i
.tm
.base_opcode
== 0xf20f38f0)
3991 /* We have to know the operand size for crc32. */
3992 as_bad (_("ambiguous memory operand size for `%s`"),
3997 for (op
= i
.operands
; --op
>= 0;)
3998 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4000 if (i
.types
[op
].bitfield
.reg8
)
4002 i
.suffix
= BYTE_MNEM_SUFFIX
;
4005 else if (i
.types
[op
].bitfield
.reg16
)
4007 i
.suffix
= WORD_MNEM_SUFFIX
;
4010 else if (i
.types
[op
].bitfield
.reg32
)
4012 i
.suffix
= LONG_MNEM_SUFFIX
;
4015 else if (i
.types
[op
].bitfield
.reg64
)
4017 i
.suffix
= QWORD_MNEM_SUFFIX
;
4023 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4025 if (!check_byte_reg ())
4028 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4030 if (!check_long_reg ())
4033 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4036 && i
.tm
.opcode_modifier
.ignoresize
4037 && i
.tm
.opcode_modifier
.no_qsuf
)
4039 else if (!check_qword_reg ())
4042 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4044 if (!check_word_reg ())
4047 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4048 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4050 /* Skip if the instruction has x/y suffix. match_template
4051 should check if it is a valid suffix. */
4053 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4054 /* Do nothing if the instruction is going to ignore the prefix. */
4059 else if (i
.tm
.opcode_modifier
.defaultsize
4061 /* exclude fldenv/frstor/fsave/fstenv */
4062 && i
.tm
.opcode_modifier
.no_ssuf
)
4064 i
.suffix
= stackop_size
;
4066 else if (intel_syntax
4068 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4069 || i
.tm
.opcode_modifier
.jumpbyte
4070 || i
.tm
.opcode_modifier
.jumpintersegment
4071 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4072 && i
.tm
.extension_opcode
<= 3)))
4077 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4079 i
.suffix
= QWORD_MNEM_SUFFIX
;
4083 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4084 i
.suffix
= LONG_MNEM_SUFFIX
;
4087 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4088 i
.suffix
= WORD_MNEM_SUFFIX
;
4097 if (i
.tm
.opcode_modifier
.w
)
4099 as_bad (_("no instruction mnemonic suffix given and "
4100 "no register operands; can't size instruction"));
4106 unsigned int suffixes
;
4108 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4109 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4111 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4113 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4115 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4117 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4120 /* There are more than suffix matches. */
4121 if (i
.tm
.opcode_modifier
.w
4122 || ((suffixes
& (suffixes
- 1))
4123 && !i
.tm
.opcode_modifier
.defaultsize
4124 && !i
.tm
.opcode_modifier
.ignoresize
))
4126 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4132 /* Change the opcode based on the operand size given by i.suffix;
4133 We don't need to change things for byte insns. */
4136 && i
.suffix
!= BYTE_MNEM_SUFFIX
4137 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4138 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4140 /* It's not a byte, select word/dword operation. */
4141 if (i
.tm
.opcode_modifier
.w
)
4143 if (i
.tm
.opcode_modifier
.shortform
)
4144 i
.tm
.base_opcode
|= 8;
4146 i
.tm
.base_opcode
|= 1;
4149 /* Now select between word & dword operations via the operand
4150 size prefix, except for instructions that will ignore this
4152 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4154 /* The address size override prefix changes the size of the
4156 if ((flag_code
== CODE_32BIT
4157 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4158 || (flag_code
!= CODE_32BIT
4159 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4160 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4163 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4164 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4165 && !i
.tm
.opcode_modifier
.ignoresize
4166 && !i
.tm
.opcode_modifier
.floatmf
4167 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4168 || (flag_code
== CODE_64BIT
4169 && i
.tm
.opcode_modifier
.jumpbyte
)))
4171 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4173 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4174 prefix
= ADDR_PREFIX_OPCODE
;
4176 if (!add_prefix (prefix
))
4180 /* Set mode64 for an operand. */
4181 if (i
.suffix
== QWORD_MNEM_SUFFIX
4182 && flag_code
== CODE_64BIT
4183 && !i
.tm
.opcode_modifier
.norex64
)
4185 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4186 need rex64. cmpxchg8b is also a special case. */
4187 if (! (i
.operands
== 2
4188 && i
.tm
.base_opcode
== 0x90
4189 && i
.tm
.extension_opcode
== None
4190 && operand_type_equal (&i
.types
[0], &acc64
)
4191 && operand_type_equal (&i
.types
[1], &acc64
))
4192 && ! (i
.operands
== 1
4193 && i
.tm
.base_opcode
== 0xfc7
4194 && i
.tm
.extension_opcode
== 1
4195 && !operand_type_check (i
.types
[0], reg
)
4196 && operand_type_check (i
.types
[0], anymem
)))
4200 /* Size floating point instruction. */
4201 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4202 if (i
.tm
.opcode_modifier
.floatmf
)
4203 i
.tm
.base_opcode
^= 4;
4210 check_byte_reg (void)
4214 for (op
= i
.operands
; --op
>= 0;)
4216 /* If this is an eight bit register, it's OK. If it's the 16 or
4217 32 bit version of an eight bit register, we will just use the
4218 low portion, and that's OK too. */
4219 if (i
.types
[op
].bitfield
.reg8
)
4222 /* Don't generate this warning if not needed. */
4223 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4226 /* crc32 doesn't generate this warning. */
4227 if (i
.tm
.base_opcode
== 0xf20f38f0)
4230 if ((i
.types
[op
].bitfield
.reg16
4231 || i
.types
[op
].bitfield
.reg32
4232 || i
.types
[op
].bitfield
.reg64
)
4233 && i
.op
[op
].regs
->reg_num
< 4)
4235 /* Prohibit these changes in the 64bit mode, since the
4236 lowering is more complicated. */
4237 if (flag_code
== CODE_64BIT
4238 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4240 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4241 register_prefix
, i
.op
[op
].regs
->reg_name
,
4245 #if REGISTER_WARNINGS
4247 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4248 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4250 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4251 ? REGNAM_AL
- REGNAM_AX
4252 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4254 i
.op
[op
].regs
->reg_name
,
4259 /* Any other register is bad. */
4260 if (i
.types
[op
].bitfield
.reg16
4261 || i
.types
[op
].bitfield
.reg32
4262 || i
.types
[op
].bitfield
.reg64
4263 || i
.types
[op
].bitfield
.regmmx
4264 || i
.types
[op
].bitfield
.regxmm
4265 || i
.types
[op
].bitfield
.regymm
4266 || i
.types
[op
].bitfield
.sreg2
4267 || i
.types
[op
].bitfield
.sreg3
4268 || i
.types
[op
].bitfield
.control
4269 || i
.types
[op
].bitfield
.debug
4270 || i
.types
[op
].bitfield
.test
4271 || i
.types
[op
].bitfield
.floatreg
4272 || i
.types
[op
].bitfield
.floatacc
)
4274 as_bad (_("`%s%s' not allowed with `%s%c'"),
4276 i
.op
[op
].regs
->reg_name
,
4286 check_long_reg (void)
4290 for (op
= i
.operands
; --op
>= 0;)
4291 /* Reject eight bit registers, except where the template requires
4292 them. (eg. movzb) */
4293 if (i
.types
[op
].bitfield
.reg8
4294 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4295 || i
.tm
.operand_types
[op
].bitfield
.reg32
4296 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4298 as_bad (_("`%s%s' not allowed with `%s%c'"),
4300 i
.op
[op
].regs
->reg_name
,
4305 /* Warn if the e prefix on a general reg is missing. */
4306 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4307 && i
.types
[op
].bitfield
.reg16
4308 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4309 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4311 /* Prohibit these changes in the 64bit mode, since the
4312 lowering is more complicated. */
4313 if (flag_code
== CODE_64BIT
)
4315 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4316 register_prefix
, i
.op
[op
].regs
->reg_name
,
4320 #if REGISTER_WARNINGS
4322 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4324 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4326 i
.op
[op
].regs
->reg_name
,
4330 /* Warn if the r prefix on a general reg is missing. */
4331 else if (i
.types
[op
].bitfield
.reg64
4332 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4333 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4336 && i
.tm
.opcode_modifier
.toqword
4337 && !i
.types
[0].bitfield
.regxmm
)
4339 /* Convert to QWORD. We want REX byte. */
4340 i
.suffix
= QWORD_MNEM_SUFFIX
;
4344 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4345 register_prefix
, i
.op
[op
].regs
->reg_name
,
4354 check_qword_reg (void)
4358 for (op
= i
.operands
; --op
>= 0; )
4359 /* Reject eight bit registers, except where the template requires
4360 them. (eg. movzb) */
4361 if (i
.types
[op
].bitfield
.reg8
4362 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4363 || i
.tm
.operand_types
[op
].bitfield
.reg32
4364 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4366 as_bad (_("`%s%s' not allowed with `%s%c'"),
4368 i
.op
[op
].regs
->reg_name
,
4373 /* Warn if the e prefix on a general reg is missing. */
4374 else if ((i
.types
[op
].bitfield
.reg16
4375 || i
.types
[op
].bitfield
.reg32
)
4376 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4377 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4379 /* Prohibit these changes in the 64bit mode, since the
4380 lowering is more complicated. */
4382 && i
.tm
.opcode_modifier
.todword
4383 && !i
.types
[0].bitfield
.regxmm
)
4385 /* Convert to DWORD. We don't want REX byte. */
4386 i
.suffix
= LONG_MNEM_SUFFIX
;
4390 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4391 register_prefix
, i
.op
[op
].regs
->reg_name
,
4400 check_word_reg (void)
4403 for (op
= i
.operands
; --op
>= 0;)
4404 /* Reject eight bit registers, except where the template requires
4405 them. (eg. movzb) */
4406 if (i
.types
[op
].bitfield
.reg8
4407 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4408 || i
.tm
.operand_types
[op
].bitfield
.reg32
4409 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4411 as_bad (_("`%s%s' not allowed with `%s%c'"),
4413 i
.op
[op
].regs
->reg_name
,
4418 /* Warn if the e prefix on a general reg is present. */
4419 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4420 && i
.types
[op
].bitfield
.reg32
4421 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4422 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4424 /* Prohibit these changes in the 64bit mode, since the
4425 lowering is more complicated. */
4426 if (flag_code
== CODE_64BIT
)
4428 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4429 register_prefix
, i
.op
[op
].regs
->reg_name
,
4434 #if REGISTER_WARNINGS
4435 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4437 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4439 i
.op
[op
].regs
->reg_name
,
4447 update_imm (unsigned int j
)
4449 i386_operand_type overlap
= i
.types
[j
];
4450 if ((overlap
.bitfield
.imm8
4451 || overlap
.bitfield
.imm8s
4452 || overlap
.bitfield
.imm16
4453 || overlap
.bitfield
.imm32
4454 || overlap
.bitfield
.imm32s
4455 || overlap
.bitfield
.imm64
)
4456 && !operand_type_equal (&overlap
, &imm8
)
4457 && !operand_type_equal (&overlap
, &imm8s
)
4458 && !operand_type_equal (&overlap
, &imm16
)
4459 && !operand_type_equal (&overlap
, &imm32
)
4460 && !operand_type_equal (&overlap
, &imm32s
)
4461 && !operand_type_equal (&overlap
, &imm64
))
4465 i386_operand_type temp
;
4467 operand_type_set (&temp
, 0);
4468 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4470 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4471 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4473 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4474 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4475 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4477 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4478 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4481 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4484 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4485 || operand_type_equal (&overlap
, &imm16_32
)
4486 || operand_type_equal (&overlap
, &imm16_32s
))
4488 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4493 if (!operand_type_equal (&overlap
, &imm8
)
4494 && !operand_type_equal (&overlap
, &imm8s
)
4495 && !operand_type_equal (&overlap
, &imm16
)
4496 && !operand_type_equal (&overlap
, &imm32
)
4497 && !operand_type_equal (&overlap
, &imm32s
)
4498 && !operand_type_equal (&overlap
, &imm64
))
4500 as_bad (_("no instruction mnemonic suffix given; "
4501 "can't determine immediate size"));
4505 i
.types
[j
] = overlap
;
4515 /* Update the first 2 immediate operands. */
4516 n
= i
.operands
> 2 ? 2 : i
.operands
;
4519 for (j
= 0; j
< n
; j
++)
4520 if (update_imm (j
) == 0)
4523 /* The 3rd operand can't be immediate operand. */
4524 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4531 bad_implicit_operand (int xmm
)
4533 const char *reg
= xmm
? "xmm0" : "ymm0";
4535 as_bad (_("the last operand of `%s' must be `%s%s'"),
4536 i
.tm
.name
, register_prefix
, reg
);
4538 as_bad (_("the first operand of `%s' must be `%s%s'"),
4539 i
.tm
.name
, register_prefix
, reg
);
4544 process_operands (void)
4546 /* Default segment register this instruction will use for memory
4547 accesses. 0 means unknown. This is only for optimizing out
4548 unnecessary segment overrides. */
4549 const seg_entry
*default_seg
= 0;
4551 if (i
.tm
.opcode_modifier
.sse2avx
4552 && (i
.tm
.opcode_modifier
.vexnds
4553 || i
.tm
.opcode_modifier
.vexndd
))
4555 unsigned int dup
= i
.operands
;
4556 unsigned int dest
= dup
- 1;
4559 /* The destination must be an xmm register. */
4560 gas_assert (i
.reg_operands
4561 && MAX_OPERANDS
> dup
4562 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4564 if (i
.tm
.opcode_modifier
.firstxmm0
)
4566 /* The first operand is implicit and must be xmm0. */
4567 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4568 if (i
.op
[0].regs
->reg_num
!= 0)
4569 return bad_implicit_operand (1);
4571 if (i
.tm
.opcode_modifier
.vex3sources
)
4573 /* Keep xmm0 for instructions with VEX prefix and 3
4579 /* We remove the first xmm0 and keep the number of
4580 operands unchanged, which in fact duplicates the
4582 for (j
= 1; j
< i
.operands
; j
++)
4584 i
.op
[j
- 1] = i
.op
[j
];
4585 i
.types
[j
- 1] = i
.types
[j
];
4586 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4590 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4592 gas_assert ((MAX_OPERANDS
- 1) > dup
4593 && i
.tm
.opcode_modifier
.vex3sources
);
4595 /* Add the implicit xmm0 for instructions with VEX prefix
4597 for (j
= i
.operands
; j
> 0; j
--)
4599 i
.op
[j
] = i
.op
[j
- 1];
4600 i
.types
[j
] = i
.types
[j
- 1];
4601 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4604 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4605 i
.types
[0] = regxmm
;
4606 i
.tm
.operand_types
[0] = regxmm
;
4609 i
.reg_operands
+= 2;
4614 i
.op
[dup
] = i
.op
[dest
];
4615 i
.types
[dup
] = i
.types
[dest
];
4616 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4625 i
.op
[dup
] = i
.op
[dest
];
4626 i
.types
[dup
] = i
.types
[dest
];
4627 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4630 if (i
.tm
.opcode_modifier
.immext
)
4633 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4637 /* The first operand is implicit and must be xmm0/ymm0. */
4638 gas_assert (i
.reg_operands
4639 && (operand_type_equal (&i
.types
[0], ®xmm
)
4640 || operand_type_equal (&i
.types
[0], ®ymm
)));
4641 if (i
.op
[0].regs
->reg_num
!= 0)
4642 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4644 for (j
= 1; j
< i
.operands
; j
++)
4646 i
.op
[j
- 1] = i
.op
[j
];
4647 i
.types
[j
- 1] = i
.types
[j
];
4649 /* We need to adjust fields in i.tm since they are used by
4650 build_modrm_byte. */
4651 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4658 else if (i
.tm
.opcode_modifier
.regkludge
)
4660 /* The imul $imm, %reg instruction is converted into
4661 imul $imm, %reg, %reg, and the clr %reg instruction
4662 is converted into xor %reg, %reg. */
4664 unsigned int first_reg_op
;
4666 if (operand_type_check (i
.types
[0], reg
))
4670 /* Pretend we saw the extra register operand. */
4671 gas_assert (i
.reg_operands
== 1
4672 && i
.op
[first_reg_op
+ 1].regs
== 0);
4673 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4674 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4679 if (i
.tm
.opcode_modifier
.shortform
)
4681 if (i
.types
[0].bitfield
.sreg2
4682 || i
.types
[0].bitfield
.sreg3
)
4684 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4685 && i
.op
[0].regs
->reg_num
== 1)
4687 as_bad (_("you can't `pop %scs'"), register_prefix
);
4690 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4691 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4696 /* The register or float register operand is in operand
4700 if (i
.types
[0].bitfield
.floatreg
4701 || operand_type_check (i
.types
[0], reg
))
4705 /* Register goes in low 3 bits of opcode. */
4706 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4707 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4709 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4711 /* Warn about some common errors, but press on regardless.
4712 The first case can be generated by gcc (<= 2.8.1). */
4713 if (i
.operands
== 2)
4715 /* Reversed arguments on faddp, fsubp, etc. */
4716 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4717 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4718 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4722 /* Extraneous `l' suffix on fp insn. */
4723 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4724 register_prefix
, i
.op
[0].regs
->reg_name
);
4729 else if (i
.tm
.opcode_modifier
.modrm
)
4731 /* The opcode is completed (modulo i.tm.extension_opcode which
4732 must be put into the modrm byte). Now, we make the modrm and
4733 index base bytes based on all the info we've collected. */
4735 default_seg
= build_modrm_byte ();
4737 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4741 else if (i
.tm
.opcode_modifier
.isstring
)
4743 /* For the string instructions that allow a segment override
4744 on one of their operands, the default segment is ds. */
4748 if (i
.tm
.base_opcode
== 0x8d /* lea */
4751 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4753 /* If a segment was explicitly specified, and the specified segment
4754 is not the default, use an opcode prefix to select it. If we
4755 never figured out what the default segment is, then default_seg
4756 will be zero at this point, and the specified segment prefix will
4758 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4760 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4766 static const seg_entry
*
4767 build_modrm_byte (void)
4769 const seg_entry
*default_seg
= 0;
4770 unsigned int source
, dest
;
4773 /* The first operand of instructions with VEX prefix and 3 sources
4774 must be VEX_Imm4. */
4775 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4778 unsigned int nds
, reg
;
4780 if (i
.tm
.opcode_modifier
.veximmext
4781 && i
.tm
.opcode_modifier
.immext
)
4783 dest
= i
.operands
- 2;
4784 gas_assert (dest
== 3);
4787 dest
= i
.operands
- 1;
4790 /* This instruction must have 4 register operands
4791 or 3 register operands plus 1 memory operand.
4792 It must have VexNDS and VexImmExt. */
4793 gas_assert ((i
.reg_operands
== 4
4794 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4795 && i
.tm
.opcode_modifier
.vexnds
4796 && i
.tm
.opcode_modifier
.veximmext
4797 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4798 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4800 /* Generate an 8bit immediate operand to encode the register
4802 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4803 i
.op
[i
.operands
].imms
= exp
;
4804 i
.types
[i
.operands
] = imm8
;
4806 /* If VexW1 is set, the first operand is the source and
4807 the second operand is encoded in the immediate operand. */
4808 if (i
.tm
.opcode_modifier
.vexw1
)
4818 /* FMA4 swaps REG and NDS. */
4819 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4826 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4827 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4829 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4830 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4832 exp
->X_op
= O_constant
;
4834 = ((i
.op
[reg
].regs
->reg_num
4835 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4836 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4841 /* i.reg_operands MUST be the number of real register operands;
4842 implicit registers do not count. If there are 3 register
4843 operands, it must be a instruction with VexNDS. For a
4844 instruction with VexNDD, the destination register is encoded
4845 in VEX prefix. If there are 4 register operands, it must be
4846 a instruction with VEX prefix and 3 sources. */
4847 if (i
.mem_operands
== 0
4848 && ((i
.reg_operands
== 2
4849 && !i
.tm
.opcode_modifier
.vexndd
)
4850 || (i
.reg_operands
== 3
4851 && i
.tm
.opcode_modifier
.vexnds
)
4852 || (i
.reg_operands
== 4 && vex_3_sources
)))
4860 /* When there are 3 operands, one of them may be immediate,
4861 which may be the first or the last operand. Otherwise,
4862 the first operand must be shift count register (cl) or it
4863 is an instruction with VexNDS. */
4864 gas_assert (i
.imm_operands
== 1
4865 || (i
.imm_operands
== 0
4866 && (i
.tm
.opcode_modifier
.vexnds
4867 || i
.types
[0].bitfield
.shiftcount
)));
4868 if (operand_type_check (i
.types
[0], imm
)
4869 || i
.types
[0].bitfield
.shiftcount
)
4875 /* When there are 4 operands, the first two must be 8bit
4876 immediate operands. The source operand will be the 3rd
4879 For instructions with VexNDS, if the first operand
4880 an imm8, the source operand is the 2nd one. If the last
4881 operand is imm8, the source operand is the first one. */
4882 gas_assert ((i
.imm_operands
== 2
4883 && i
.types
[0].bitfield
.imm8
4884 && i
.types
[1].bitfield
.imm8
)
4885 || (i
.tm
.opcode_modifier
.vexnds
4886 && i
.imm_operands
== 1
4887 && (i
.types
[0].bitfield
.imm8
4888 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4889 if (i
.tm
.opcode_modifier
.vexnds
)
4891 if (i
.types
[0].bitfield
.imm8
)
4909 if (i
.tm
.opcode_modifier
.vexnds
)
4911 /* For instructions with VexNDS, the register-only
4912 source operand must be XMM or YMM register. It is
4913 encoded in VEX prefix. We need to clear RegMem bit
4914 before calling operand_type_equal. */
4915 i386_operand_type op
= i
.tm
.operand_types
[dest
];
4916 op
.bitfield
.regmem
= 0;
4917 if ((dest
+ 1) >= i
.operands
4918 || (!operand_type_equal (&op
, ®xmm
)
4919 && !operand_type_equal (&op
, ®ymm
)))
4921 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
4927 /* One of the register operands will be encoded in the i.tm.reg
4928 field, the other in the combined i.tm.mode and i.tm.regmem
4929 fields. If no form of this instruction supports a memory
4930 destination operand, then we assume the source operand may
4931 sometimes be a memory operand and so we need to store the
4932 destination in the i.rm.reg field. */
4933 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4934 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4936 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4937 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4938 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4940 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4945 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4946 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4947 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4949 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4952 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4954 if (!i
.types
[0].bitfield
.control
4955 && !i
.types
[1].bitfield
.control
)
4957 i
.rex
&= ~(REX_R
| REX_B
);
4958 add_prefix (LOCK_PREFIX_OPCODE
);
4962 { /* If it's not 2 reg operands... */
4967 unsigned int fake_zero_displacement
= 0;
4970 for (op
= 0; op
< i
.operands
; op
++)
4971 if (operand_type_check (i
.types
[op
], anymem
))
4973 gas_assert (op
< i
.operands
);
4977 if (i
.base_reg
== 0)
4980 if (!i
.disp_operands
)
4981 fake_zero_displacement
= 1;
4982 if (i
.index_reg
== 0)
4984 /* Operand is just <disp> */
4985 if (flag_code
== CODE_64BIT
)
4987 /* 64bit mode overwrites the 32bit absolute
4988 addressing by RIP relative addressing and
4989 absolute addressing is encoded by one of the
4990 redundant SIB forms. */
4991 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4992 i
.sib
.base
= NO_BASE_REGISTER
;
4993 i
.sib
.index
= NO_INDEX_REGISTER
;
4994 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4995 ? disp32s
: disp32
);
4997 else if ((flag_code
== CODE_16BIT
)
4998 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5000 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5001 i
.types
[op
] = disp16
;
5005 i
.rm
.regmem
= NO_BASE_REGISTER
;
5006 i
.types
[op
] = disp32
;
5009 else /* !i.base_reg && i.index_reg */
5011 if (i
.index_reg
->reg_num
== RegEiz
5012 || i
.index_reg
->reg_num
== RegRiz
)
5013 i
.sib
.index
= NO_INDEX_REGISTER
;
5015 i
.sib
.index
= i
.index_reg
->reg_num
;
5016 i
.sib
.base
= NO_BASE_REGISTER
;
5017 i
.sib
.scale
= i
.log2_scale_factor
;
5018 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5019 i
.types
[op
].bitfield
.disp8
= 0;
5020 i
.types
[op
].bitfield
.disp16
= 0;
5021 i
.types
[op
].bitfield
.disp64
= 0;
5022 if (flag_code
!= CODE_64BIT
)
5024 /* Must be 32 bit */
5025 i
.types
[op
].bitfield
.disp32
= 1;
5026 i
.types
[op
].bitfield
.disp32s
= 0;
5030 i
.types
[op
].bitfield
.disp32
= 0;
5031 i
.types
[op
].bitfield
.disp32s
= 1;
5033 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5037 /* RIP addressing for 64bit mode. */
5038 else if (i
.base_reg
->reg_num
== RegRip
||
5039 i
.base_reg
->reg_num
== RegEip
)
5041 i
.rm
.regmem
= NO_BASE_REGISTER
;
5042 i
.types
[op
].bitfield
.disp8
= 0;
5043 i
.types
[op
].bitfield
.disp16
= 0;
5044 i
.types
[op
].bitfield
.disp32
= 0;
5045 i
.types
[op
].bitfield
.disp32s
= 1;
5046 i
.types
[op
].bitfield
.disp64
= 0;
5047 i
.flags
[op
] |= Operand_PCrel
;
5048 if (! i
.disp_operands
)
5049 fake_zero_displacement
= 1;
5051 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5053 switch (i
.base_reg
->reg_num
)
5056 if (i
.index_reg
== 0)
5058 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5059 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5063 if (i
.index_reg
== 0)
5066 if (operand_type_check (i
.types
[op
], disp
) == 0)
5068 /* fake (%bp) into 0(%bp) */
5069 i
.types
[op
].bitfield
.disp8
= 1;
5070 fake_zero_displacement
= 1;
5073 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5074 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5076 default: /* (%si) -> 4 or (%di) -> 5 */
5077 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5079 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5081 else /* i.base_reg and 32/64 bit mode */
5083 if (flag_code
== CODE_64BIT
5084 && operand_type_check (i
.types
[op
], disp
))
5086 i386_operand_type temp
;
5087 operand_type_set (&temp
, 0);
5088 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5090 if (i
.prefix
[ADDR_PREFIX
] == 0)
5091 i
.types
[op
].bitfield
.disp32s
= 1;
5093 i
.types
[op
].bitfield
.disp32
= 1;
5096 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5097 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5099 i
.sib
.base
= i
.base_reg
->reg_num
;
5100 /* x86-64 ignores REX prefix bit here to avoid decoder
5102 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5105 if (i
.disp_operands
== 0)
5107 fake_zero_displacement
= 1;
5108 i
.types
[op
].bitfield
.disp8
= 1;
5111 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5115 i
.sib
.scale
= i
.log2_scale_factor
;
5116 if (i
.index_reg
== 0)
5118 /* <disp>(%esp) becomes two byte modrm with no index
5119 register. We've already stored the code for esp
5120 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5121 Any base register besides %esp will not use the
5122 extra modrm byte. */
5123 i
.sib
.index
= NO_INDEX_REGISTER
;
5127 if (i
.index_reg
->reg_num
== RegEiz
5128 || i
.index_reg
->reg_num
== RegRiz
)
5129 i
.sib
.index
= NO_INDEX_REGISTER
;
5131 i
.sib
.index
= i
.index_reg
->reg_num
;
5132 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5133 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5138 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5139 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5142 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5145 if (fake_zero_displacement
)
5147 /* Fakes a zero displacement assuming that i.types[op]
5148 holds the correct displacement size. */
5151 gas_assert (i
.op
[op
].disps
== 0);
5152 exp
= &disp_expressions
[i
.disp_operands
++];
5153 i
.op
[op
].disps
= exp
;
5154 exp
->X_op
= O_constant
;
5155 exp
->X_add_number
= 0;
5156 exp
->X_add_symbol
= (symbolS
*) 0;
5157 exp
->X_op_symbol
= (symbolS
*) 0;
5165 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5166 (if any) based on i.tm.extension_opcode. Again, we must be
5167 careful to make sure that segment/control/debug/test/MMX
5168 registers are coded into the i.rm.reg field. */
5172 unsigned int vex_reg
= ~0;
5174 for (op
= 0; op
< i
.operands
; op
++)
5175 if (i
.types
[op
].bitfield
.reg8
5176 || i
.types
[op
].bitfield
.reg16
5177 || i
.types
[op
].bitfield
.reg32
5178 || i
.types
[op
].bitfield
.reg64
5179 || i
.types
[op
].bitfield
.regmmx
5180 || i
.types
[op
].bitfield
.regxmm
5181 || i
.types
[op
].bitfield
.regymm
5182 || i
.types
[op
].bitfield
.sreg2
5183 || i
.types
[op
].bitfield
.sreg3
5184 || i
.types
[op
].bitfield
.control
5185 || i
.types
[op
].bitfield
.debug
5186 || i
.types
[op
].bitfield
.test
)
5191 else if (i
.tm
.opcode_modifier
.vexnds
)
5193 /* For instructions with VexNDS, the register-only
5194 source operand is encoded in VEX prefix. */
5195 gas_assert (mem
!= (unsigned int) ~0);
5200 gas_assert (op
< i
.operands
);
5205 gas_assert (vex_reg
< i
.operands
);
5208 else if (i
.tm
.opcode_modifier
.vexndd
)
5210 /* For instructions with VexNDD, there should be
5211 no memory operand and the register destination
5212 is encoded in VEX prefix. */
5213 gas_assert (i
.mem_operands
== 0
5214 && (op
+ 2) == i
.operands
);
5218 gas_assert (op
< i
.operands
);
5220 if (vex_reg
!= (unsigned int) ~0)
5222 gas_assert (i
.reg_operands
== 2);
5224 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5226 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5229 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5232 /* If there is an extension opcode to put here, the
5233 register number must be put into the regmem field. */
5234 if (i
.tm
.extension_opcode
!= None
)
5236 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5237 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5242 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5243 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5247 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5248 must set it to 3 to indicate this is a register operand
5249 in the regmem field. */
5250 if (!i
.mem_operands
)
5254 /* Fill in i.rm.reg field with extension opcode (if any). */
5255 if (i
.tm
.extension_opcode
!= None
)
5256 i
.rm
.reg
= i
.tm
.extension_opcode
;
5262 output_branch (void)
5267 relax_substateT subtype
;
5272 if (flag_code
== CODE_16BIT
)
5276 if (i
.prefix
[DATA_PREFIX
] != 0)
5282 /* Pentium4 branch hints. */
5283 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5284 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5289 if (i
.prefix
[REX_PREFIX
] != 0)
5295 if (i
.prefixes
!= 0 && !intel_syntax
)
5296 as_warn (_("skipping prefixes on this instruction"));
5298 /* It's always a symbol; End frag & setup for relax.
5299 Make sure there is enough room in this frag for the largest
5300 instruction we may generate in md_convert_frag. This is 2
5301 bytes for the opcode and room for the prefix and largest
5303 frag_grow (prefix
+ 2 + 4);
5304 /* Prefix and 1 opcode byte go in fr_fix. */
5305 p
= frag_more (prefix
+ 1);
5306 if (i
.prefix
[DATA_PREFIX
] != 0)
5307 *p
++ = DATA_PREFIX_OPCODE
;
5308 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5309 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5310 *p
++ = i
.prefix
[SEG_PREFIX
];
5311 if (i
.prefix
[REX_PREFIX
] != 0)
5312 *p
++ = i
.prefix
[REX_PREFIX
];
5313 *p
= i
.tm
.base_opcode
;
5315 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5316 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5317 else if (cpu_arch_flags
.bitfield
.cpui386
)
5318 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5320 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5323 sym
= i
.op
[0].disps
->X_add_symbol
;
5324 off
= i
.op
[0].disps
->X_add_number
;
5326 if (i
.op
[0].disps
->X_op
!= O_constant
5327 && i
.op
[0].disps
->X_op
!= O_symbol
)
5329 /* Handle complex expressions. */
5330 sym
= make_expr_symbol (i
.op
[0].disps
);
5334 /* 1 possible extra opcode + 4 byte displacement go in var part.
5335 Pass reloc in fr_var. */
5336 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5346 if (i
.tm
.opcode_modifier
.jumpbyte
)
5348 /* This is a loop or jecxz type instruction. */
5350 if (i
.prefix
[ADDR_PREFIX
] != 0)
5352 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5355 /* Pentium4 branch hints. */
5356 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5357 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5359 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5368 if (flag_code
== CODE_16BIT
)
5371 if (i
.prefix
[DATA_PREFIX
] != 0)
5373 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5383 if (i
.prefix
[REX_PREFIX
] != 0)
5385 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5389 if (i
.prefixes
!= 0 && !intel_syntax
)
5390 as_warn (_("skipping prefixes on this instruction"));
5392 p
= frag_more (1 + size
);
5393 *p
++ = i
.tm
.base_opcode
;
5395 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5396 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5398 /* All jumps handled here are signed, but don't use a signed limit
5399 check for 32 and 16 bit jumps as we want to allow wrap around at
5400 4G and 64k respectively. */
5402 fixP
->fx_signed
= 1;
5406 output_interseg_jump (void)
5414 if (flag_code
== CODE_16BIT
)
5418 if (i
.prefix
[DATA_PREFIX
] != 0)
5424 if (i
.prefix
[REX_PREFIX
] != 0)
5434 if (i
.prefixes
!= 0 && !intel_syntax
)
5435 as_warn (_("skipping prefixes on this instruction"));
5437 /* 1 opcode; 2 segment; offset */
5438 p
= frag_more (prefix
+ 1 + 2 + size
);
5440 if (i
.prefix
[DATA_PREFIX
] != 0)
5441 *p
++ = DATA_PREFIX_OPCODE
;
5443 if (i
.prefix
[REX_PREFIX
] != 0)
5444 *p
++ = i
.prefix
[REX_PREFIX
];
5446 *p
++ = i
.tm
.base_opcode
;
5447 if (i
.op
[1].imms
->X_op
== O_constant
)
5449 offsetT n
= i
.op
[1].imms
->X_add_number
;
5452 && !fits_in_unsigned_word (n
)
5453 && !fits_in_signed_word (n
))
5455 as_bad (_("16-bit jump out of range"));
5458 md_number_to_chars (p
, n
, size
);
5461 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5462 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5463 if (i
.op
[0].imms
->X_op
!= O_constant
)
5464 as_bad (_("can't handle non absolute segment in `%s'"),
5466 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5472 fragS
*insn_start_frag
;
5473 offsetT insn_start_off
;
5475 /* Tie dwarf2 debug info to the address at the start of the insn.
5476 We can't do this after the insn has been output as the current
5477 frag may have been closed off. eg. by frag_var. */
5478 dwarf2_emit_insn (0);
5480 insn_start_frag
= frag_now
;
5481 insn_start_off
= frag_now_fix ();
5484 if (i
.tm
.opcode_modifier
.jump
)
5486 else if (i
.tm
.opcode_modifier
.jumpbyte
5487 || i
.tm
.opcode_modifier
.jumpdword
)
5489 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5490 output_interseg_jump ();
5493 /* Output normal instructions here. */
5497 unsigned int prefix
;
5499 /* Since the VEX prefix contains the implicit prefix, we don't
5500 need the explicit prefix. */
5501 if (!i
.tm
.opcode_modifier
.vex
)
5503 switch (i
.tm
.opcode_length
)
5506 if (i
.tm
.base_opcode
& 0xff000000)
5508 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5513 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5515 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5516 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5519 if (prefix
!= REPE_PREFIX_OPCODE
5520 || (i
.prefix
[LOCKREP_PREFIX
]
5521 != REPE_PREFIX_OPCODE
))
5522 add_prefix (prefix
);
5525 add_prefix (prefix
);
5534 /* The prefix bytes. */
5535 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5537 FRAG_APPEND_1_CHAR (*q
);
5540 if (i
.tm
.opcode_modifier
.vex
)
5542 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5547 /* REX byte is encoded in VEX prefix. */
5551 FRAG_APPEND_1_CHAR (*q
);
5554 /* There should be no other prefixes for instructions
5559 /* Now the VEX prefix. */
5560 p
= frag_more (i
.vex
.length
);
5561 for (j
= 0; j
< i
.vex
.length
; j
++)
5562 p
[j
] = i
.vex
.bytes
[j
];
5565 /* Now the opcode; be careful about word order here! */
5566 if (i
.tm
.opcode_length
== 1)
5568 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5572 switch (i
.tm
.opcode_length
)
5576 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5586 /* Put out high byte first: can't use md_number_to_chars! */
5587 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5588 *p
= i
.tm
.base_opcode
& 0xff;
5591 /* Now the modrm byte and sib byte (if present). */
5592 if (i
.tm
.opcode_modifier
.modrm
)
5594 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5597 /* If i.rm.regmem == ESP (4)
5598 && i.rm.mode != (Register mode)
5600 ==> need second modrm byte. */
5601 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5603 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5604 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5606 | i
.sib
.scale
<< 6));
5609 if (i
.disp_operands
)
5610 output_disp (insn_start_frag
, insn_start_off
);
5613 output_imm (insn_start_frag
, insn_start_off
);
5619 pi ("" /*line*/, &i
);
5621 #endif /* DEBUG386 */
5624 /* Return the size of the displacement operand N. */
5627 disp_size (unsigned int n
)
5630 if (i
.types
[n
].bitfield
.disp64
)
5632 else if (i
.types
[n
].bitfield
.disp8
)
5634 else if (i
.types
[n
].bitfield
.disp16
)
5639 /* Return the size of the immediate operand N. */
5642 imm_size (unsigned int n
)
5645 if (i
.types
[n
].bitfield
.imm64
)
5647 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5649 else if (i
.types
[n
].bitfield
.imm16
)
5655 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5660 for (n
= 0; n
< i
.operands
; n
++)
5662 if (operand_type_check (i
.types
[n
], disp
))
5664 if (i
.op
[n
].disps
->X_op
== O_constant
)
5666 int size
= disp_size (n
);
5669 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5671 p
= frag_more (size
);
5672 md_number_to_chars (p
, val
, size
);
5676 enum bfd_reloc_code_real reloc_type
;
5677 int size
= disp_size (n
);
5678 int sign
= i
.types
[n
].bitfield
.disp32s
;
5679 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5681 /* We can't have 8 bit displacement here. */
5682 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5684 /* The PC relative address is computed relative
5685 to the instruction boundary, so in case immediate
5686 fields follows, we need to adjust the value. */
5687 if (pcrel
&& i
.imm_operands
)
5692 for (n1
= 0; n1
< i
.operands
; n1
++)
5693 if (operand_type_check (i
.types
[n1
], imm
))
5695 /* Only one immediate is allowed for PC
5696 relative address. */
5697 gas_assert (sz
== 0);
5699 i
.op
[n
].disps
->X_add_number
-= sz
;
5701 /* We should find the immediate. */
5702 gas_assert (sz
!= 0);
5705 p
= frag_more (size
);
5706 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5708 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5709 && (((reloc_type
== BFD_RELOC_32
5710 || reloc_type
== BFD_RELOC_X86_64_32S
5711 || (reloc_type
== BFD_RELOC_64
5713 && (i
.op
[n
].disps
->X_op
== O_symbol
5714 || (i
.op
[n
].disps
->X_op
== O_add
5715 && ((symbol_get_value_expression
5716 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5718 || reloc_type
== BFD_RELOC_32_PCREL
))
5722 if (insn_start_frag
== frag_now
)
5723 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5728 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5729 for (fr
= insn_start_frag
->fr_next
;
5730 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5732 add
+= p
- frag_now
->fr_literal
;
5737 reloc_type
= BFD_RELOC_386_GOTPC
;
5738 i
.op
[n
].imms
->X_add_number
+= add
;
5740 else if (reloc_type
== BFD_RELOC_64
)
5741 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5743 /* Don't do the adjustment for x86-64, as there
5744 the pcrel addressing is relative to the _next_
5745 insn, and that is taken care of in other code. */
5746 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5748 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5749 i
.op
[n
].disps
, pcrel
, reloc_type
);
5756 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5761 for (n
= 0; n
< i
.operands
; n
++)
5763 if (operand_type_check (i
.types
[n
], imm
))
5765 if (i
.op
[n
].imms
->X_op
== O_constant
)
5767 int size
= imm_size (n
);
5770 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5772 p
= frag_more (size
);
5773 md_number_to_chars (p
, val
, size
);
5777 /* Not absolute_section.
5778 Need a 32-bit fixup (don't support 8bit
5779 non-absolute imms). Try to support other
5781 enum bfd_reloc_code_real reloc_type
;
5782 int size
= imm_size (n
);
5785 if (i
.types
[n
].bitfield
.imm32s
5786 && (i
.suffix
== QWORD_MNEM_SUFFIX
5787 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5792 p
= frag_more (size
);
5793 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5795 /* This is tough to explain. We end up with this one if we
5796 * have operands that look like
5797 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5798 * obtain the absolute address of the GOT, and it is strongly
5799 * preferable from a performance point of view to avoid using
5800 * a runtime relocation for this. The actual sequence of
5801 * instructions often look something like:
5806 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5808 * The call and pop essentially return the absolute address
5809 * of the label .L66 and store it in %ebx. The linker itself
5810 * will ultimately change the first operand of the addl so
5811 * that %ebx points to the GOT, but to keep things simple, the
5812 * .o file must have this operand set so that it generates not
5813 * the absolute address of .L66, but the absolute address of
5814 * itself. This allows the linker itself simply treat a GOTPC
5815 * relocation as asking for a pcrel offset to the GOT to be
5816 * added in, and the addend of the relocation is stored in the
5817 * operand field for the instruction itself.
5819 * Our job here is to fix the operand so that it would add
5820 * the correct offset so that %ebx would point to itself. The
5821 * thing that is tricky is that .-.L66 will point to the
5822 * beginning of the instruction, so we need to further modify
5823 * the operand so that it will point to itself. There are
5824 * other cases where you have something like:
5826 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5828 * and here no correction would be required. Internally in
5829 * the assembler we treat operands of this form as not being
5830 * pcrel since the '.' is explicitly mentioned, and I wonder
5831 * whether it would simplify matters to do it this way. Who
5832 * knows. In earlier versions of the PIC patches, the
5833 * pcrel_adjust field was used to store the correction, but
5834 * since the expression is not pcrel, I felt it would be
5835 * confusing to do it this way. */
5837 if ((reloc_type
== BFD_RELOC_32
5838 || reloc_type
== BFD_RELOC_X86_64_32S
5839 || reloc_type
== BFD_RELOC_64
)
5841 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5842 && (i
.op
[n
].imms
->X_op
== O_symbol
5843 || (i
.op
[n
].imms
->X_op
== O_add
5844 && ((symbol_get_value_expression
5845 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5850 if (insn_start_frag
== frag_now
)
5851 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5856 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5857 for (fr
= insn_start_frag
->fr_next
;
5858 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5860 add
+= p
- frag_now
->fr_literal
;
5864 reloc_type
= BFD_RELOC_386_GOTPC
;
5866 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5868 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5869 i
.op
[n
].imms
->X_add_number
+= add
;
5871 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5872 i
.op
[n
].imms
, 0, reloc_type
);
5878 /* x86_cons_fix_new is called via the expression parsing code when a
5879 reloc is needed. We use this hook to get the correct .got reloc. */
5880 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5881 static int cons_sign
= -1;
5884 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5887 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5889 got_reloc
= NO_RELOC
;
5892 if (exp
->X_op
== O_secrel
)
5894 exp
->X_op
= O_symbol
;
5895 r
= BFD_RELOC_32_SECREL
;
5899 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5902 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5903 # define lex_got(reloc, adjust, types) NULL
5905 /* Parse operands of the form
5906 <symbol>@GOTOFF+<nnn>
5907 and similar .plt or .got references.
5909 If we find one, set up the correct relocation in RELOC and copy the
5910 input string, minus the `@GOTOFF' into a malloc'd buffer for
5911 parsing by the calling routine. Return this buffer, and if ADJUST
5912 is non-null set it to the length of the string we removed from the
5913 input line. Otherwise return NULL. */
5915 lex_got (enum bfd_reloc_code_real
*reloc
,
5917 i386_operand_type
*types
)
5919 /* Some of the relocations depend on the size of what field is to
5920 be relocated. But in our callers i386_immediate and i386_displacement
5921 we don't yet know the operand size (this will be set by insn
5922 matching). Hence we record the word32 relocation here,
5923 and adjust the reloc according to the real size in reloc(). */
5924 static const struct {
5926 const enum bfd_reloc_code_real rel
[2];
5927 const i386_operand_type types64
;
5930 BFD_RELOC_X86_64_PLTOFF64
},
5931 OPERAND_TYPE_IMM64
},
5932 { "PLT", { BFD_RELOC_386_PLT32
,
5933 BFD_RELOC_X86_64_PLT32
},
5934 OPERAND_TYPE_IMM32_32S_DISP32
},
5936 BFD_RELOC_X86_64_GOTPLT64
},
5937 OPERAND_TYPE_IMM64_DISP64
},
5938 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5939 BFD_RELOC_X86_64_GOTOFF64
},
5940 OPERAND_TYPE_IMM64_DISP64
},
5942 BFD_RELOC_X86_64_GOTPCREL
},
5943 OPERAND_TYPE_IMM32_32S_DISP32
},
5944 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5945 BFD_RELOC_X86_64_TLSGD
},
5946 OPERAND_TYPE_IMM32_32S_DISP32
},
5947 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5949 OPERAND_TYPE_NONE
},
5951 BFD_RELOC_X86_64_TLSLD
},
5952 OPERAND_TYPE_IMM32_32S_DISP32
},
5953 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5954 BFD_RELOC_X86_64_GOTTPOFF
},
5955 OPERAND_TYPE_IMM32_32S_DISP32
},
5956 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5957 BFD_RELOC_X86_64_TPOFF32
},
5958 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5959 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5961 OPERAND_TYPE_NONE
},
5962 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5963 BFD_RELOC_X86_64_DTPOFF32
},
5965 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5966 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5968 OPERAND_TYPE_NONE
},
5969 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5971 OPERAND_TYPE_NONE
},
5972 { "GOT", { BFD_RELOC_386_GOT32
,
5973 BFD_RELOC_X86_64_GOT32
},
5974 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5975 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5976 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5977 OPERAND_TYPE_IMM32_32S_DISP32
},
5978 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5979 BFD_RELOC_X86_64_TLSDESC_CALL
},
5980 OPERAND_TYPE_IMM32_32S_DISP32
},
5988 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5989 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5992 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5996 len
= strlen (gotrel
[j
].str
);
5997 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5999 if (gotrel
[j
].rel
[object_64bit
] != 0)
6002 char *tmpbuf
, *past_reloc
;
6004 *reloc
= gotrel
[j
].rel
[object_64bit
];
6010 if (flag_code
!= CODE_64BIT
)
6012 types
->bitfield
.imm32
= 1;
6013 types
->bitfield
.disp32
= 1;
6016 *types
= gotrel
[j
].types64
;
6019 if (GOT_symbol
== NULL
)
6020 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6022 /* The length of the first part of our input line. */
6023 first
= cp
- input_line_pointer
;
6025 /* The second part goes from after the reloc token until
6026 (and including) an end_of_line char or comma. */
6027 past_reloc
= cp
+ 1 + len
;
6029 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6031 second
= cp
+ 1 - past_reloc
;
6033 /* Allocate and copy string. The trailing NUL shouldn't
6034 be necessary, but be safe. */
6035 tmpbuf
= xmalloc (first
+ second
+ 2);
6036 memcpy (tmpbuf
, input_line_pointer
, first
);
6037 if (second
!= 0 && *past_reloc
!= ' ')
6038 /* Replace the relocation token with ' ', so that
6039 errors like foo@GOTOFF1 will be detected. */
6040 tmpbuf
[first
++] = ' ';
6041 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6042 tmpbuf
[first
+ second
] = '\0';
6046 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6047 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6052 /* Might be a symbol version string. Don't as_bad here. */
6057 x86_cons (expressionS
*exp
, int size
)
6059 intel_syntax
= -intel_syntax
;
6061 if (size
== 4 || (object_64bit
&& size
== 8))
6063 /* Handle @GOTOFF and the like in an expression. */
6065 char *gotfree_input_line
;
6068 save
= input_line_pointer
;
6069 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6070 if (gotfree_input_line
)
6071 input_line_pointer
= gotfree_input_line
;
6075 if (gotfree_input_line
)
6077 /* expression () has merrily parsed up to the end of line,
6078 or a comma - in the wrong buffer. Transfer how far
6079 input_line_pointer has moved to the right buffer. */
6080 input_line_pointer
= (save
6081 + (input_line_pointer
- gotfree_input_line
)
6083 free (gotfree_input_line
);
6084 if (exp
->X_op
== O_constant
6085 || exp
->X_op
== O_absent
6086 || exp
->X_op
== O_illegal
6087 || exp
->X_op
== O_register
6088 || exp
->X_op
== O_big
)
6090 char c
= *input_line_pointer
;
6091 *input_line_pointer
= 0;
6092 as_bad (_("missing or invalid expression `%s'"), save
);
6093 *input_line_pointer
= c
;
6100 intel_syntax
= -intel_syntax
;
6103 i386_intel_simplify (exp
);
6107 static void signed_cons (int size
)
6109 if (flag_code
== CODE_64BIT
)
6117 pe_directive_secrel (dummy
)
6118 int dummy ATTRIBUTE_UNUSED
;
6125 if (exp
.X_op
== O_symbol
)
6126 exp
.X_op
= O_secrel
;
6128 emit_expr (&exp
, 4);
6130 while (*input_line_pointer
++ == ',');
6132 input_line_pointer
--;
6133 demand_empty_rest_of_line ();
6138 i386_immediate (char *imm_start
)
6140 char *save_input_line_pointer
;
6141 char *gotfree_input_line
;
6144 i386_operand_type types
;
6146 operand_type_set (&types
, ~0);
6148 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6150 as_bad (_("at most %d immediate operands are allowed"),
6151 MAX_IMMEDIATE_OPERANDS
);
6155 exp
= &im_expressions
[i
.imm_operands
++];
6156 i
.op
[this_operand
].imms
= exp
;
6158 if (is_space_char (*imm_start
))
6161 save_input_line_pointer
= input_line_pointer
;
6162 input_line_pointer
= imm_start
;
6164 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6165 if (gotfree_input_line
)
6166 input_line_pointer
= gotfree_input_line
;
6168 exp_seg
= expression (exp
);
6171 if (*input_line_pointer
)
6172 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6174 input_line_pointer
= save_input_line_pointer
;
6175 if (gotfree_input_line
)
6177 free (gotfree_input_line
);
6179 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6180 exp
->X_op
= O_illegal
;
6183 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6187 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6188 i386_operand_type types
, const char *imm_start
)
6190 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6192 as_bad (_("missing or invalid immediate expression `%s'"),
6196 else if (exp
->X_op
== O_constant
)
6198 /* Size it properly later. */
6199 i
.types
[this_operand
].bitfield
.imm64
= 1;
6200 /* If BFD64, sign extend val. */
6201 if (!use_rela_relocations
6202 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6204 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6206 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6207 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6208 && exp_seg
!= absolute_section
6209 && exp_seg
!= text_section
6210 && exp_seg
!= data_section
6211 && exp_seg
!= bss_section
6212 && exp_seg
!= undefined_section
6213 && !bfd_is_com_section (exp_seg
))
6215 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6219 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6221 as_bad (_("illegal immediate register operand %s"), imm_start
);
6226 /* This is an address. The size of the address will be
6227 determined later, depending on destination register,
6228 suffix, or the default for the section. */
6229 i
.types
[this_operand
].bitfield
.imm8
= 1;
6230 i
.types
[this_operand
].bitfield
.imm16
= 1;
6231 i
.types
[this_operand
].bitfield
.imm32
= 1;
6232 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6233 i
.types
[this_operand
].bitfield
.imm64
= 1;
6234 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6242 i386_scale (char *scale
)
6245 char *save
= input_line_pointer
;
6247 input_line_pointer
= scale
;
6248 val
= get_absolute_expression ();
6253 i
.log2_scale_factor
= 0;
6256 i
.log2_scale_factor
= 1;
6259 i
.log2_scale_factor
= 2;
6262 i
.log2_scale_factor
= 3;
6266 char sep
= *input_line_pointer
;
6268 *input_line_pointer
= '\0';
6269 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6271 *input_line_pointer
= sep
;
6272 input_line_pointer
= save
;
6276 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6278 as_warn (_("scale factor of %d without an index register"),
6279 1 << i
.log2_scale_factor
);
6280 i
.log2_scale_factor
= 0;
6282 scale
= input_line_pointer
;
6283 input_line_pointer
= save
;
6288 i386_displacement (char *disp_start
, char *disp_end
)
6292 char *save_input_line_pointer
;
6293 char *gotfree_input_line
;
6295 i386_operand_type bigdisp
, types
= anydisp
;
6298 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6300 as_bad (_("at most %d displacement operands are allowed"),
6301 MAX_MEMORY_OPERANDS
);
6305 operand_type_set (&bigdisp
, 0);
6306 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6307 || (!current_templates
->start
->opcode_modifier
.jump
6308 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6310 bigdisp
.bitfield
.disp32
= 1;
6311 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6312 if (flag_code
== CODE_64BIT
)
6316 bigdisp
.bitfield
.disp32s
= 1;
6317 bigdisp
.bitfield
.disp64
= 1;
6320 else if ((flag_code
== CODE_16BIT
) ^ override
)
6322 bigdisp
.bitfield
.disp32
= 0;
6323 bigdisp
.bitfield
.disp16
= 1;
6328 /* For PC-relative branches, the width of the displacement
6329 is dependent upon data size, not address size. */
6330 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6331 if (flag_code
== CODE_64BIT
)
6333 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6334 bigdisp
.bitfield
.disp16
= 1;
6337 bigdisp
.bitfield
.disp32
= 1;
6338 bigdisp
.bitfield
.disp32s
= 1;
6344 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6346 : LONG_MNEM_SUFFIX
));
6347 bigdisp
.bitfield
.disp32
= 1;
6348 if ((flag_code
== CODE_16BIT
) ^ override
)
6350 bigdisp
.bitfield
.disp32
= 0;
6351 bigdisp
.bitfield
.disp16
= 1;
6355 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6358 exp
= &disp_expressions
[i
.disp_operands
];
6359 i
.op
[this_operand
].disps
= exp
;
6361 save_input_line_pointer
= input_line_pointer
;
6362 input_line_pointer
= disp_start
;
6363 END_STRING_AND_SAVE (disp_end
);
6365 #ifndef GCC_ASM_O_HACK
6366 #define GCC_ASM_O_HACK 0
6369 END_STRING_AND_SAVE (disp_end
+ 1);
6370 if (i
.types
[this_operand
].bitfield
.baseIndex
6371 && displacement_string_end
[-1] == '+')
6373 /* This hack is to avoid a warning when using the "o"
6374 constraint within gcc asm statements.
6377 #define _set_tssldt_desc(n,addr,limit,type) \
6378 __asm__ __volatile__ ( \
6380 "movw %w1,2+%0\n\t" \
6382 "movb %b1,4+%0\n\t" \
6383 "movb %4,5+%0\n\t" \
6384 "movb $0,6+%0\n\t" \
6385 "movb %h1,7+%0\n\t" \
6387 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6389 This works great except that the output assembler ends
6390 up looking a bit weird if it turns out that there is
6391 no offset. You end up producing code that looks like:
6404 So here we provide the missing zero. */
6406 *displacement_string_end
= '0';
6409 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6410 if (gotfree_input_line
)
6411 input_line_pointer
= gotfree_input_line
;
6413 exp_seg
= expression (exp
);
6416 if (*input_line_pointer
)
6417 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6419 RESTORE_END_STRING (disp_end
+ 1);
6421 input_line_pointer
= save_input_line_pointer
;
6422 if (gotfree_input_line
)
6424 free (gotfree_input_line
);
6426 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6427 exp
->X_op
= O_illegal
;
6430 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6432 RESTORE_END_STRING (disp_end
);
6438 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6439 i386_operand_type types
, const char *disp_start
)
6441 i386_operand_type bigdisp
;
6444 /* We do this to make sure that the section symbol is in
6445 the symbol table. We will ultimately change the relocation
6446 to be relative to the beginning of the section. */
6447 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6448 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6449 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6451 if (exp
->X_op
!= O_symbol
)
6454 if (S_IS_LOCAL (exp
->X_add_symbol
)
6455 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6456 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6457 exp
->X_op
= O_subtract
;
6458 exp
->X_op_symbol
= GOT_symbol
;
6459 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6460 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6461 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6462 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6464 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6467 else if (exp
->X_op
== O_absent
6468 || exp
->X_op
== O_illegal
6469 || exp
->X_op
== O_big
)
6472 as_bad (_("missing or invalid displacement expression `%s'"),
6477 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6478 else if (exp
->X_op
!= O_constant
6479 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6480 && exp_seg
!= absolute_section
6481 && exp_seg
!= text_section
6482 && exp_seg
!= data_section
6483 && exp_seg
!= bss_section
6484 && exp_seg
!= undefined_section
6485 && !bfd_is_com_section (exp_seg
))
6487 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6492 /* Check if this is a displacement only operand. */
6493 bigdisp
= i
.types
[this_operand
];
6494 bigdisp
.bitfield
.disp8
= 0;
6495 bigdisp
.bitfield
.disp16
= 0;
6496 bigdisp
.bitfield
.disp32
= 0;
6497 bigdisp
.bitfield
.disp32s
= 0;
6498 bigdisp
.bitfield
.disp64
= 0;
6499 if (operand_type_all_zero (&bigdisp
))
6500 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6506 /* Make sure the memory operand we've been dealt is valid.
6507 Return 1 on success, 0 on a failure. */
6510 i386_index_check (const char *operand_string
)
6513 const char *kind
= "base/index";
6514 #if INFER_ADDR_PREFIX
6520 if (current_templates
->start
->opcode_modifier
.isstring
6521 && !current_templates
->start
->opcode_modifier
.immext
6522 && (current_templates
->end
[-1].opcode_modifier
.isstring
6525 /* Memory operands of string insns are special in that they only allow
6526 a single register (rDI, rSI, or rBX) as their memory address. */
6527 unsigned int expected
;
6529 kind
= "string address";
6531 if (current_templates
->start
->opcode_modifier
.w
)
6533 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6535 if (!type
.bitfield
.baseindex
6536 || ((!i
.mem_operands
!= !intel_syntax
)
6537 && current_templates
->end
[-1].operand_types
[1]
6538 .bitfield
.baseindex
))
6539 type
= current_templates
->end
[-1].operand_types
[1];
6540 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6543 expected
= 3 /* rBX */;
6545 if (!i
.base_reg
|| i
.index_reg
6546 || operand_type_check (i
.types
[this_operand
], disp
))
6548 else if (!(flag_code
== CODE_64BIT
6549 ? i
.prefix
[ADDR_PREFIX
]
6550 ? i
.base_reg
->reg_type
.bitfield
.reg32
6551 : i
.base_reg
->reg_type
.bitfield
.reg64
6552 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6553 ? i
.base_reg
->reg_type
.bitfield
.reg32
6554 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6556 else if (i
.base_reg
->reg_num
!= expected
)
6563 for (j
= 0; j
< i386_regtab_size
; ++j
)
6564 if ((flag_code
== CODE_64BIT
6565 ? i
.prefix
[ADDR_PREFIX
]
6566 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6567 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6568 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6569 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6570 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6571 && i386_regtab
[j
].reg_num
== expected
)
6573 gas_assert (j
< i386_regtab_size
);
6574 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6576 intel_syntax
? '[' : '(',
6578 i386_regtab
[j
].reg_name
,
6579 intel_syntax
? ']' : ')');
6583 else if (flag_code
== CODE_64BIT
)
6586 && ((i
.prefix
[ADDR_PREFIX
] == 0
6587 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6588 || (i
.prefix
[ADDR_PREFIX
]
6589 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6591 || i
.base_reg
->reg_num
!=
6592 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6594 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6595 || (i
.prefix
[ADDR_PREFIX
] == 0
6596 && i
.index_reg
->reg_num
!= RegRiz
6597 && !i
.index_reg
->reg_type
.bitfield
.reg64
6599 || (i
.prefix
[ADDR_PREFIX
]
6600 && i
.index_reg
->reg_num
!= RegEiz
6601 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6606 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6610 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6611 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6613 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6614 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6616 && i
.base_reg
->reg_num
< 6
6617 && i
.index_reg
->reg_num
>= 6
6618 && i
.log2_scale_factor
== 0))))
6625 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6627 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6628 && i
.index_reg
->reg_num
!= RegEiz
)
6629 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6635 #if INFER_ADDR_PREFIX
6636 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6638 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6640 /* Change the size of any displacement too. At most one of
6641 Disp16 or Disp32 is set.
6642 FIXME. There doesn't seem to be any real need for separate
6643 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6644 Removing them would probably clean up the code quite a lot. */
6645 if (flag_code
!= CODE_64BIT
6646 && (i
.types
[this_operand
].bitfield
.disp16
6647 || i
.types
[this_operand
].bitfield
.disp32
))
6648 i
.types
[this_operand
]
6649 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6654 as_bad (_("`%s' is not a valid %s expression"),
6659 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6661 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6662 ? flag_code
== CODE_32BIT
6671 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6675 i386_att_operand (char *operand_string
)
6679 char *op_string
= operand_string
;
6681 if (is_space_char (*op_string
))
6684 /* We check for an absolute prefix (differentiating,
6685 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6686 if (*op_string
== ABSOLUTE_PREFIX
)
6689 if (is_space_char (*op_string
))
6691 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6694 /* Check if operand is a register. */
6695 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6697 i386_operand_type temp
;
6699 /* Check for a segment override by searching for ':' after a
6700 segment register. */
6702 if (is_space_char (*op_string
))
6704 if (*op_string
== ':'
6705 && (r
->reg_type
.bitfield
.sreg2
6706 || r
->reg_type
.bitfield
.sreg3
))
6711 i
.seg
[i
.mem_operands
] = &es
;
6714 i
.seg
[i
.mem_operands
] = &cs
;
6717 i
.seg
[i
.mem_operands
] = &ss
;
6720 i
.seg
[i
.mem_operands
] = &ds
;
6723 i
.seg
[i
.mem_operands
] = &fs
;
6726 i
.seg
[i
.mem_operands
] = &gs
;
6730 /* Skip the ':' and whitespace. */
6732 if (is_space_char (*op_string
))
6735 if (!is_digit_char (*op_string
)
6736 && !is_identifier_char (*op_string
)
6737 && *op_string
!= '('
6738 && *op_string
!= ABSOLUTE_PREFIX
)
6740 as_bad (_("bad memory operand `%s'"), op_string
);
6743 /* Handle case of %es:*foo. */
6744 if (*op_string
== ABSOLUTE_PREFIX
)
6747 if (is_space_char (*op_string
))
6749 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6751 goto do_memory_reference
;
6755 as_bad (_("junk `%s' after register"), op_string
);
6759 temp
.bitfield
.baseindex
= 0;
6760 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6762 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6763 i
.op
[this_operand
].regs
= r
;
6766 else if (*op_string
== REGISTER_PREFIX
)
6768 as_bad (_("bad register name `%s'"), op_string
);
6771 else if (*op_string
== IMMEDIATE_PREFIX
)
6774 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6776 as_bad (_("immediate operand illegal with absolute jump"));
6779 if (!i386_immediate (op_string
))
6782 else if (is_digit_char (*op_string
)
6783 || is_identifier_char (*op_string
)
6784 || *op_string
== '(')
6786 /* This is a memory reference of some sort. */
6789 /* Start and end of displacement string expression (if found). */
6790 char *displacement_string_start
;
6791 char *displacement_string_end
;
6793 do_memory_reference
:
6794 if ((i
.mem_operands
== 1
6795 && !current_templates
->start
->opcode_modifier
.isstring
)
6796 || i
.mem_operands
== 2)
6798 as_bad (_("too many memory references for `%s'"),
6799 current_templates
->start
->name
);
6803 /* Check for base index form. We detect the base index form by
6804 looking for an ')' at the end of the operand, searching
6805 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6807 base_string
= op_string
+ strlen (op_string
);
6810 if (is_space_char (*base_string
))
6813 /* If we only have a displacement, set-up for it to be parsed later. */
6814 displacement_string_start
= op_string
;
6815 displacement_string_end
= base_string
+ 1;
6817 if (*base_string
== ')')
6820 unsigned int parens_balanced
= 1;
6821 /* We've already checked that the number of left & right ()'s are
6822 equal, so this loop will not be infinite. */
6826 if (*base_string
== ')')
6828 if (*base_string
== '(')
6831 while (parens_balanced
);
6833 temp_string
= base_string
;
6835 /* Skip past '(' and whitespace. */
6837 if (is_space_char (*base_string
))
6840 if (*base_string
== ','
6841 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6844 displacement_string_end
= temp_string
;
6846 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6850 base_string
= end_op
;
6851 if (is_space_char (*base_string
))
6855 /* There may be an index reg or scale factor here. */
6856 if (*base_string
== ',')
6859 if (is_space_char (*base_string
))
6862 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6865 base_string
= end_op
;
6866 if (is_space_char (*base_string
))
6868 if (*base_string
== ',')
6871 if (is_space_char (*base_string
))
6874 else if (*base_string
!= ')')
6876 as_bad (_("expecting `,' or `)' "
6877 "after index register in `%s'"),
6882 else if (*base_string
== REGISTER_PREFIX
)
6884 as_bad (_("bad register name `%s'"), base_string
);
6888 /* Check for scale factor. */
6889 if (*base_string
!= ')')
6891 char *end_scale
= i386_scale (base_string
);
6896 base_string
= end_scale
;
6897 if (is_space_char (*base_string
))
6899 if (*base_string
!= ')')
6901 as_bad (_("expecting `)' "
6902 "after scale factor in `%s'"),
6907 else if (!i
.index_reg
)
6909 as_bad (_("expecting index register or scale factor "
6910 "after `,'; got '%c'"),
6915 else if (*base_string
!= ')')
6917 as_bad (_("expecting `,' or `)' "
6918 "after base register in `%s'"),
6923 else if (*base_string
== REGISTER_PREFIX
)
6925 as_bad (_("bad register name `%s'"), base_string
);
6930 /* If there's an expression beginning the operand, parse it,
6931 assuming displacement_string_start and
6932 displacement_string_end are meaningful. */
6933 if (displacement_string_start
!= displacement_string_end
)
6935 if (!i386_displacement (displacement_string_start
,
6936 displacement_string_end
))
6940 /* Special case for (%dx) while doing input/output op. */
6942 && operand_type_equal (&i
.base_reg
->reg_type
,
6943 ®16_inoutportreg
)
6945 && i
.log2_scale_factor
== 0
6946 && i
.seg
[i
.mem_operands
] == 0
6947 && !operand_type_check (i
.types
[this_operand
], disp
))
6949 i
.types
[this_operand
] = inoutportreg
;
6953 if (i386_index_check (operand_string
) == 0)
6955 i
.types
[this_operand
].bitfield
.mem
= 1;
6960 /* It's not a memory operand; argh! */
6961 as_bad (_("invalid char %s beginning operand %d `%s'"),
6962 output_invalid (*op_string
),
6967 return 1; /* Normal return. */
6970 /* md_estimate_size_before_relax()
6972 Called just before relax() for rs_machine_dependent frags. The x86
6973 assembler uses these frags to handle variable size jump
6976 Any symbol that is now undefined will not become defined.
6977 Return the correct fr_subtype in the frag.
6978 Return the initial "guess for variable size of frag" to caller.
6979 The guess is actually the growth beyond the fixed part. Whatever
6980 we do to grow the fixed or variable part contributes to our
6984 md_estimate_size_before_relax (fragP
, segment
)
6988 /* We've already got fragP->fr_subtype right; all we have to do is
6989 check for un-relaxable symbols. On an ELF system, we can't relax
6990 an externally visible symbol, because it may be overridden by a
6992 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6995 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6996 || S_IS_WEAK (fragP
->fr_symbol
)
6997 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
6998 & BSF_GNU_INDIRECT_FUNCTION
))))
7000 #if defined (OBJ_COFF) && defined (TE_PE)
7001 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7002 && S_IS_WEAK (fragP
->fr_symbol
))
7006 /* Symbol is undefined in this segment, or we need to keep a
7007 reloc so that weak symbols can be overridden. */
7008 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7009 enum bfd_reloc_code_real reloc_type
;
7010 unsigned char *opcode
;
7013 if (fragP
->fr_var
!= NO_RELOC
)
7014 reloc_type
= fragP
->fr_var
;
7016 reloc_type
= BFD_RELOC_16_PCREL
;
7018 reloc_type
= BFD_RELOC_32_PCREL
;
7020 old_fr_fix
= fragP
->fr_fix
;
7021 opcode
= (unsigned char *) fragP
->fr_opcode
;
7023 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7026 /* Make jmp (0xeb) a (d)word displacement jump. */
7028 fragP
->fr_fix
+= size
;
7029 fix_new (fragP
, old_fr_fix
, size
,
7031 fragP
->fr_offset
, 1,
7037 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7039 /* Negate the condition, and branch past an
7040 unconditional jump. */
7043 /* Insert an unconditional jump. */
7045 /* We added two extra opcode bytes, and have a two byte
7047 fragP
->fr_fix
+= 2 + 2;
7048 fix_new (fragP
, old_fr_fix
+ 2, 2,
7050 fragP
->fr_offset
, 1,
7057 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7062 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7064 fragP
->fr_offset
, 1,
7066 fixP
->fx_signed
= 1;
7070 /* This changes the byte-displacement jump 0x7N
7071 to the (d)word-displacement jump 0x0f,0x8N. */
7072 opcode
[1] = opcode
[0] + 0x10;
7073 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7074 /* We've added an opcode byte. */
7075 fragP
->fr_fix
+= 1 + size
;
7076 fix_new (fragP
, old_fr_fix
+ 1, size
,
7078 fragP
->fr_offset
, 1,
7083 BAD_CASE (fragP
->fr_subtype
);
7087 return fragP
->fr_fix
- old_fr_fix
;
7090 /* Guess size depending on current relax state. Initially the relax
7091 state will correspond to a short jump and we return 1, because
7092 the variable part of the frag (the branch offset) is one byte
7093 long. However, we can relax a section more than once and in that
7094 case we must either set fr_subtype back to the unrelaxed state,
7095 or return the value for the appropriate branch. */
7096 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7099 /* Called after relax() is finished.
7101 In: Address of frag.
7102 fr_type == rs_machine_dependent.
7103 fr_subtype is what the address relaxed to.
7105 Out: Any fixSs and constants are set up.
7106 Caller will turn frag into a ".space 0". */
7109 md_convert_frag (abfd
, sec
, fragP
)
7110 bfd
*abfd ATTRIBUTE_UNUSED
;
7111 segT sec ATTRIBUTE_UNUSED
;
7114 unsigned char *opcode
;
7115 unsigned char *where_to_put_displacement
= NULL
;
7116 offsetT target_address
;
7117 offsetT opcode_address
;
7118 unsigned int extension
= 0;
7119 offsetT displacement_from_opcode_start
;
7121 opcode
= (unsigned char *) fragP
->fr_opcode
;
7123 /* Address we want to reach in file space. */
7124 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7126 /* Address opcode resides at in file space. */
7127 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7129 /* Displacement from opcode start to fill into instruction. */
7130 displacement_from_opcode_start
= target_address
- opcode_address
;
7132 if ((fragP
->fr_subtype
& BIG
) == 0)
7134 /* Don't have to change opcode. */
7135 extension
= 1; /* 1 opcode + 1 displacement */
7136 where_to_put_displacement
= &opcode
[1];
7140 if (no_cond_jump_promotion
7141 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7142 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7143 _("long jump required"));
7145 switch (fragP
->fr_subtype
)
7147 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7148 extension
= 4; /* 1 opcode + 4 displacement */
7150 where_to_put_displacement
= &opcode
[1];
7153 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7154 extension
= 2; /* 1 opcode + 2 displacement */
7156 where_to_put_displacement
= &opcode
[1];
7159 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7160 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7161 extension
= 5; /* 2 opcode + 4 displacement */
7162 opcode
[1] = opcode
[0] + 0x10;
7163 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7164 where_to_put_displacement
= &opcode
[2];
7167 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7168 extension
= 3; /* 2 opcode + 2 displacement */
7169 opcode
[1] = opcode
[0] + 0x10;
7170 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7171 where_to_put_displacement
= &opcode
[2];
7174 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7179 where_to_put_displacement
= &opcode
[3];
7183 BAD_CASE (fragP
->fr_subtype
);
7188 /* If size if less then four we are sure that the operand fits,
7189 but if it's 4, then it could be that the displacement is larger
7191 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7193 && ((addressT
) (displacement_from_opcode_start
- extension
7194 + ((addressT
) 1 << 31))
7195 > (((addressT
) 2 << 31) - 1)))
7197 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7198 _("jump target out of range"));
7199 /* Make us emit 0. */
7200 displacement_from_opcode_start
= extension
;
7202 /* Now put displacement after opcode. */
7203 md_number_to_chars ((char *) where_to_put_displacement
,
7204 (valueT
) (displacement_from_opcode_start
- extension
),
7205 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7206 fragP
->fr_fix
+= extension
;
7209 /* Apply a fixup (fixS) to segment data, once it has been determined
7210 by our caller that we have all the info we need to fix it up.
7212 On the 386, immediates, displacements, and data pointers are all in
7213 the same (little-endian) format, so we don't need to care about which
7217 md_apply_fix (fixP
, valP
, seg
)
7218 /* The fix we're to put in. */
7220 /* Pointer to the value of the bits. */
7222 /* Segment fix is from. */
7223 segT seg ATTRIBUTE_UNUSED
;
7225 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7226 valueT value
= *valP
;
7228 #if !defined (TE_Mach)
7231 switch (fixP
->fx_r_type
)
7237 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7240 case BFD_RELOC_X86_64_32S
:
7241 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7244 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7247 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7252 if (fixP
->fx_addsy
!= NULL
7253 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7254 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7255 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7256 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7257 && !use_rela_relocations
)
7259 /* This is a hack. There should be a better way to handle this.
7260 This covers for the fact that bfd_install_relocation will
7261 subtract the current location (for partial_inplace, PC relative
7262 relocations); see more below. */
7266 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7269 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7271 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7274 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7277 || (symbol_section_p (fixP
->fx_addsy
)
7278 && sym_seg
!= absolute_section
))
7279 && !TC_FORCE_RELOCATION (fixP
))
7281 /* Yes, we add the values in twice. This is because
7282 bfd_install_relocation subtracts them out again. I think
7283 bfd_install_relocation is broken, but I don't dare change
7285 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7289 #if defined (OBJ_COFF) && defined (TE_PE)
7290 /* For some reason, the PE format does not store a
7291 section address offset for a PC relative symbol. */
7292 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7293 || S_IS_WEAK (fixP
->fx_addsy
))
7294 value
+= md_pcrel_from (fixP
);
7297 #if defined (OBJ_COFF) && defined (TE_PE)
7298 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7300 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7304 /* Fix a few things - the dynamic linker expects certain values here,
7305 and we must not disappoint it. */
7306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7307 if (IS_ELF
&& fixP
->fx_addsy
)
7308 switch (fixP
->fx_r_type
)
7310 case BFD_RELOC_386_PLT32
:
7311 case BFD_RELOC_X86_64_PLT32
:
7312 /* Make the jump instruction point to the address of the operand. At
7313 runtime we merely add the offset to the actual PLT entry. */
7317 case BFD_RELOC_386_TLS_GD
:
7318 case BFD_RELOC_386_TLS_LDM
:
7319 case BFD_RELOC_386_TLS_IE_32
:
7320 case BFD_RELOC_386_TLS_IE
:
7321 case BFD_RELOC_386_TLS_GOTIE
:
7322 case BFD_RELOC_386_TLS_GOTDESC
:
7323 case BFD_RELOC_X86_64_TLSGD
:
7324 case BFD_RELOC_X86_64_TLSLD
:
7325 case BFD_RELOC_X86_64_GOTTPOFF
:
7326 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7327 value
= 0; /* Fully resolved at runtime. No addend. */
7329 case BFD_RELOC_386_TLS_LE
:
7330 case BFD_RELOC_386_TLS_LDO_32
:
7331 case BFD_RELOC_386_TLS_LE_32
:
7332 case BFD_RELOC_X86_64_DTPOFF32
:
7333 case BFD_RELOC_X86_64_DTPOFF64
:
7334 case BFD_RELOC_X86_64_TPOFF32
:
7335 case BFD_RELOC_X86_64_TPOFF64
:
7336 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7339 case BFD_RELOC_386_TLS_DESC_CALL
:
7340 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7341 value
= 0; /* Fully resolved at runtime. No addend. */
7342 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7346 case BFD_RELOC_386_GOT32
:
7347 case BFD_RELOC_X86_64_GOT32
:
7348 value
= 0; /* Fully resolved at runtime. No addend. */
7351 case BFD_RELOC_VTABLE_INHERIT
:
7352 case BFD_RELOC_VTABLE_ENTRY
:
7359 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7361 #endif /* !defined (TE_Mach) */
7363 /* Are we finished with this relocation now? */
7364 if (fixP
->fx_addsy
== NULL
)
7366 #if defined (OBJ_COFF) && defined (TE_PE)
7367 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7370 /* Remember value for tc_gen_reloc. */
7371 fixP
->fx_addnumber
= value
;
7372 /* Clear out the frag for now. */
7376 else if (use_rela_relocations
)
7378 fixP
->fx_no_overflow
= 1;
7379 /* Remember value for tc_gen_reloc. */
7380 fixP
->fx_addnumber
= value
;
7384 md_number_to_chars (p
, value
, fixP
->fx_size
);
7388 md_atof (int type
, char *litP
, int *sizeP
)
7390 /* This outputs the LITTLENUMs in REVERSE order;
7391 in accord with the bigendian 386. */
7392 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7395 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7398 output_invalid (int c
)
7401 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7404 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7405 "(0x%x)", (unsigned char) c
);
7406 return output_invalid_buf
;
7409 /* REG_STRING starts *before* REGISTER_PREFIX. */
7411 static const reg_entry
*
7412 parse_real_register (char *reg_string
, char **end_op
)
7414 char *s
= reg_string
;
7416 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7419 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7420 if (*s
== REGISTER_PREFIX
)
7423 if (is_space_char (*s
))
7427 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7429 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7430 return (const reg_entry
*) NULL
;
7434 /* For naked regs, make sure that we are not dealing with an identifier.
7435 This prevents confusing an identifier like `eax_var' with register
7437 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7438 return (const reg_entry
*) NULL
;
7442 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7444 /* Handle floating point regs, allowing spaces in the (i) part. */
7445 if (r
== i386_regtab
/* %st is first entry of table */)
7447 if (is_space_char (*s
))
7452 if (is_space_char (*s
))
7454 if (*s
>= '0' && *s
<= '7')
7458 if (is_space_char (*s
))
7463 r
= hash_find (reg_hash
, "st(0)");
7468 /* We have "%st(" then garbage. */
7469 return (const reg_entry
*) NULL
;
7473 if (r
== NULL
|| allow_pseudo_reg
)
7476 if (operand_type_all_zero (&r
->reg_type
))
7477 return (const reg_entry
*) NULL
;
7479 if ((r
->reg_type
.bitfield
.reg32
7480 || r
->reg_type
.bitfield
.sreg3
7481 || r
->reg_type
.bitfield
.control
7482 || r
->reg_type
.bitfield
.debug
7483 || r
->reg_type
.bitfield
.test
)
7484 && !cpu_arch_flags
.bitfield
.cpui386
)
7485 return (const reg_entry
*) NULL
;
7487 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7488 return (const reg_entry
*) NULL
;
7490 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7491 return (const reg_entry
*) NULL
;
7493 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7494 return (const reg_entry
*) NULL
;
7496 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7497 if (!allow_index_reg
7498 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7499 return (const reg_entry
*) NULL
;
7501 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7502 || r
->reg_type
.bitfield
.reg64
)
7503 && (!cpu_arch_flags
.bitfield
.cpulm
7504 || !operand_type_equal (&r
->reg_type
, &control
))
7505 && flag_code
!= CODE_64BIT
)
7506 return (const reg_entry
*) NULL
;
7508 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7509 return (const reg_entry
*) NULL
;
7514 /* REG_STRING starts *before* REGISTER_PREFIX. */
7516 static const reg_entry
*
7517 parse_register (char *reg_string
, char **end_op
)
7521 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7522 r
= parse_real_register (reg_string
, end_op
);
7527 char *save
= input_line_pointer
;
7531 input_line_pointer
= reg_string
;
7532 c
= get_symbol_end ();
7533 symbolP
= symbol_find (reg_string
);
7534 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7536 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7538 know (e
->X_op
== O_register
);
7539 know (e
->X_add_number
>= 0
7540 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7541 r
= i386_regtab
+ e
->X_add_number
;
7542 *end_op
= input_line_pointer
;
7544 *input_line_pointer
= c
;
7545 input_line_pointer
= save
;
7551 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7554 char *end
= input_line_pointer
;
7557 r
= parse_register (name
, &input_line_pointer
);
7558 if (r
&& end
<= input_line_pointer
)
7560 *nextcharP
= *input_line_pointer
;
7561 *input_line_pointer
= 0;
7562 e
->X_op
= O_register
;
7563 e
->X_add_number
= r
- i386_regtab
;
7566 input_line_pointer
= end
;
7568 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7572 md_operand (expressionS
*e
)
7577 switch (*input_line_pointer
)
7579 case REGISTER_PREFIX
:
7580 r
= parse_real_register (input_line_pointer
, &end
);
7583 e
->X_op
= O_register
;
7584 e
->X_add_number
= r
- i386_regtab
;
7585 input_line_pointer
= end
;
7590 gas_assert (intel_syntax
);
7591 end
= input_line_pointer
++;
7593 if (*input_line_pointer
== ']')
7595 ++input_line_pointer
;
7596 e
->X_op_symbol
= make_expr_symbol (e
);
7597 e
->X_add_symbol
= NULL
;
7598 e
->X_add_number
= 0;
7604 input_line_pointer
= end
;
7611 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7612 const char *md_shortopts
= "kVQ:sqn";
7614 const char *md_shortopts
= "qn";
7617 #define OPTION_32 (OPTION_MD_BASE + 0)
7618 #define OPTION_64 (OPTION_MD_BASE + 1)
7619 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7620 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7621 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7622 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7623 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7624 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7625 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7626 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7627 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7628 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7630 struct option md_longopts
[] =
7632 {"32", no_argument
, NULL
, OPTION_32
},
7633 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7634 || defined (TE_PE) || defined (TE_PEP))
7635 {"64", no_argument
, NULL
, OPTION_64
},
7637 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7638 {"march", required_argument
, NULL
, OPTION_MARCH
},
7639 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7640 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7641 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7642 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7643 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7644 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7645 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7646 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7647 {NULL
, no_argument
, NULL
, 0}
7649 size_t md_longopts_size
= sizeof (md_longopts
);
7652 md_parse_option (int c
, char *arg
)
7660 optimize_align_code
= 0;
7667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7668 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7669 should be emitted or not. FIXME: Not implemented. */
7673 /* -V: SVR4 argument to print version ID. */
7675 print_version_id ();
7678 /* -k: Ignore for FreeBSD compatibility. */
7683 /* -s: On i386 Solaris, this tells the native assembler to use
7684 .stab instead of .stab.excl. We always use .stab anyhow. */
7687 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7688 || defined (TE_PE) || defined (TE_PEP))
7691 const char **list
, **l
;
7693 list
= bfd_target_list ();
7694 for (l
= list
; *l
!= NULL
; l
++)
7695 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7696 || strcmp (*l
, "coff-x86-64") == 0
7697 || strcmp (*l
, "pe-x86-64") == 0
7698 || strcmp (*l
, "pei-x86-64") == 0)
7700 default_arch
= "x86_64";
7704 as_fatal (_("No compiled in support for x86_64"));
7711 default_arch
= "i386";
7715 #ifdef SVR4_COMMENT_CHARS
7720 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7722 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7726 i386_comment_chars
= n
;
7732 arch
= xstrdup (arg
);
7736 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7737 next
= strchr (arch
, '+');
7740 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7742 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7745 cpu_arch_name
= cpu_arch
[i
].name
;
7746 cpu_sub_arch_name
= NULL
;
7747 cpu_arch_flags
= cpu_arch
[i
].flags
;
7748 cpu_arch_isa
= cpu_arch
[i
].type
;
7749 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7750 if (!cpu_arch_tune_set
)
7752 cpu_arch_tune
= cpu_arch_isa
;
7753 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7757 else if (*cpu_arch
[i
].name
== '.'
7758 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7760 /* ISA entension. */
7761 i386_cpu_flags flags
;
7762 flags
= cpu_flags_or (cpu_arch_flags
,
7764 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7766 if (cpu_sub_arch_name
)
7768 char *name
= cpu_sub_arch_name
;
7769 cpu_sub_arch_name
= concat (name
,
7771 (const char *) NULL
);
7775 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7776 cpu_arch_flags
= flags
;
7782 if (i
>= ARRAY_SIZE (cpu_arch
))
7783 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7787 while (next
!= NULL
);
7792 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7793 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7795 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7797 cpu_arch_tune_set
= 1;
7798 cpu_arch_tune
= cpu_arch
[i
].type
;
7799 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7803 if (i
>= ARRAY_SIZE (cpu_arch
))
7804 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7807 case OPTION_MMNEMONIC
:
7808 if (strcasecmp (arg
, "att") == 0)
7810 else if (strcasecmp (arg
, "intel") == 0)
7813 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7816 case OPTION_MSYNTAX
:
7817 if (strcasecmp (arg
, "att") == 0)
7819 else if (strcasecmp (arg
, "intel") == 0)
7822 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7825 case OPTION_MINDEX_REG
:
7826 allow_index_reg
= 1;
7829 case OPTION_MNAKED_REG
:
7830 allow_naked_reg
= 1;
7833 case OPTION_MOLD_GCC
:
7837 case OPTION_MSSE2AVX
:
7841 case OPTION_MSSE_CHECK
:
7842 if (strcasecmp (arg
, "error") == 0)
7843 sse_check
= sse_check_error
;
7844 else if (strcasecmp (arg
, "warning") == 0)
7845 sse_check
= sse_check_warning
;
7846 else if (strcasecmp (arg
, "none") == 0)
7847 sse_check
= sse_check_none
;
7849 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7859 md_show_usage (stream
)
7862 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7863 fprintf (stream
, _("\
7865 -V print assembler version number\n\
7868 fprintf (stream
, _("\
7869 -n Do not optimize code alignment\n\
7870 -q quieten some warnings\n"));
7871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7872 fprintf (stream
, _("\
7875 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7876 || defined (TE_PE) || defined (TE_PEP))
7877 fprintf (stream
, _("\
7878 --32/--64 generate 32bit/64bit code\n"));
7880 #ifdef SVR4_COMMENT_CHARS
7881 fprintf (stream
, _("\
7882 --divide do not treat `/' as a comment character\n"));
7884 fprintf (stream
, _("\
7885 --divide ignored\n"));
7887 fprintf (stream
, _("\
7888 -march=CPU[,+EXTENSION...]\n\
7889 generate code for CPU and EXTENSION, CPU is one of:\n\
7890 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7891 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7892 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7893 generic32, generic64\n\
7894 EXTENSION is combination of:\n\
7895 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7896 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7897 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
7898 svme, abm, padlock, fma4\n"));
7899 fprintf (stream
, _("\
7900 -mtune=CPU optimize for CPU, CPU is one of:\n\
7901 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7902 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7903 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7904 generic32, generic64\n"));
7905 fprintf (stream
, _("\
7906 -msse2avx encode SSE instructions with VEX prefix\n"));
7907 fprintf (stream
, _("\
7908 -msse-check=[none|error|warning]\n\
7909 check SSE instructions\n"));
7910 fprintf (stream
, _("\
7911 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7912 fprintf (stream
, _("\
7913 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7914 fprintf (stream
, _("\
7915 -mindex-reg support pseudo index registers\n"));
7916 fprintf (stream
, _("\
7917 -mnaked-reg don't require `%%' prefix for registers\n"));
7918 fprintf (stream
, _("\
7919 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7922 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7923 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7924 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
7926 /* Pick the target format to use. */
7929 i386_target_format (void)
7931 if (!strcmp (default_arch
, "x86_64"))
7933 set_code_flag (CODE_64BIT
);
7934 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7936 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7937 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7938 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7939 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7940 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7941 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7942 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
7943 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7944 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7945 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7946 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
7948 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7950 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7951 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7952 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7953 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7954 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7955 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7956 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
7957 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7958 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7959 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7962 else if (!strcmp (default_arch
, "i386"))
7964 set_code_flag (CODE_32BIT
);
7965 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7967 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7968 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7969 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7971 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7973 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7974 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7975 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7979 as_fatal (_("Unknown architecture"));
7980 switch (OUTPUT_FLAVOR
)
7982 #if defined (TE_PE) || defined (TE_PEP)
7983 case bfd_target_coff_flavour
:
7984 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
7986 #ifdef OBJ_MAYBE_AOUT
7987 case bfd_target_aout_flavour
:
7988 return AOUT_TARGET_FORMAT
;
7990 #ifdef OBJ_MAYBE_COFF
7991 case bfd_target_coff_flavour
:
7994 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7995 case bfd_target_elf_flavour
:
7997 if (flag_code
== CODE_64BIT
)
8000 use_rela_relocations
= 1;
8002 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8005 #if defined (OBJ_MACH_O)
8006 case bfd_target_mach_o_flavour
:
8007 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8015 #endif /* OBJ_MAYBE_ more than one */
8017 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8019 i386_elf_emit_arch_note (void)
8021 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8024 asection
*seg
= now_seg
;
8025 subsegT subseg
= now_subseg
;
8026 Elf_Internal_Note i_note
;
8027 Elf_External_Note e_note
;
8028 asection
*note_secp
;
8031 /* Create the .note section. */
8032 note_secp
= subseg_new (".note", 0);
8033 bfd_set_section_flags (stdoutput
,
8035 SEC_HAS_CONTENTS
| SEC_READONLY
);
8037 /* Process the arch string. */
8038 len
= strlen (cpu_arch_name
);
8040 i_note
.namesz
= len
+ 1;
8042 i_note
.type
= NT_ARCH
;
8043 p
= frag_more (sizeof (e_note
.namesz
));
8044 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8045 p
= frag_more (sizeof (e_note
.descsz
));
8046 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8047 p
= frag_more (sizeof (e_note
.type
));
8048 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8049 p
= frag_more (len
+ 1);
8050 strcpy (p
, cpu_arch_name
);
8052 frag_align (2, 0, 0);
8054 subseg_set (seg
, subseg
);
8060 md_undefined_symbol (name
)
8063 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8064 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8065 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8066 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8070 if (symbol_find (name
))
8071 as_bad (_("GOT already in symbol table"));
8072 GOT_symbol
= symbol_new (name
, undefined_section
,
8073 (valueT
) 0, &zero_address_frag
);
8080 /* Round up a section size to the appropriate boundary. */
8083 md_section_align (segment
, size
)
8084 segT segment ATTRIBUTE_UNUSED
;
8087 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8088 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8090 /* For a.out, force the section size to be aligned. If we don't do
8091 this, BFD will align it for us, but it will not write out the
8092 final bytes of the section. This may be a bug in BFD, but it is
8093 easier to fix it here since that is how the other a.out targets
8097 align
= bfd_get_section_alignment (stdoutput
, segment
);
8098 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8105 /* On the i386, PC-relative offsets are relative to the start of the
8106 next instruction. That is, the address of the offset, plus its
8107 size, since the offset is always the last part of the insn. */
8110 md_pcrel_from (fixS
*fixP
)
8112 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8118 s_bss (int ignore ATTRIBUTE_UNUSED
)
8122 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8124 obj_elf_section_change_hook ();
8126 temp
= get_absolute_expression ();
8127 subseg_set (bss_section
, (subsegT
) temp
);
8128 demand_empty_rest_of_line ();
8134 i386_validate_fix (fixS
*fixp
)
8136 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8138 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8142 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8147 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8149 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8156 tc_gen_reloc (section
, fixp
)
8157 asection
*section ATTRIBUTE_UNUSED
;
8161 bfd_reloc_code_real_type code
;
8163 switch (fixp
->fx_r_type
)
8165 case BFD_RELOC_X86_64_PLT32
:
8166 case BFD_RELOC_X86_64_GOT32
:
8167 case BFD_RELOC_X86_64_GOTPCREL
:
8168 case BFD_RELOC_386_PLT32
:
8169 case BFD_RELOC_386_GOT32
:
8170 case BFD_RELOC_386_GOTOFF
:
8171 case BFD_RELOC_386_GOTPC
:
8172 case BFD_RELOC_386_TLS_GD
:
8173 case BFD_RELOC_386_TLS_LDM
:
8174 case BFD_RELOC_386_TLS_LDO_32
:
8175 case BFD_RELOC_386_TLS_IE_32
:
8176 case BFD_RELOC_386_TLS_IE
:
8177 case BFD_RELOC_386_TLS_GOTIE
:
8178 case BFD_RELOC_386_TLS_LE_32
:
8179 case BFD_RELOC_386_TLS_LE
:
8180 case BFD_RELOC_386_TLS_GOTDESC
:
8181 case BFD_RELOC_386_TLS_DESC_CALL
:
8182 case BFD_RELOC_X86_64_TLSGD
:
8183 case BFD_RELOC_X86_64_TLSLD
:
8184 case BFD_RELOC_X86_64_DTPOFF32
:
8185 case BFD_RELOC_X86_64_DTPOFF64
:
8186 case BFD_RELOC_X86_64_GOTTPOFF
:
8187 case BFD_RELOC_X86_64_TPOFF32
:
8188 case BFD_RELOC_X86_64_TPOFF64
:
8189 case BFD_RELOC_X86_64_GOTOFF64
:
8190 case BFD_RELOC_X86_64_GOTPC32
:
8191 case BFD_RELOC_X86_64_GOT64
:
8192 case BFD_RELOC_X86_64_GOTPCREL64
:
8193 case BFD_RELOC_X86_64_GOTPC64
:
8194 case BFD_RELOC_X86_64_GOTPLT64
:
8195 case BFD_RELOC_X86_64_PLTOFF64
:
8196 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8197 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8199 case BFD_RELOC_VTABLE_ENTRY
:
8200 case BFD_RELOC_VTABLE_INHERIT
:
8202 case BFD_RELOC_32_SECREL
:
8204 code
= fixp
->fx_r_type
;
8206 case BFD_RELOC_X86_64_32S
:
8207 if (!fixp
->fx_pcrel
)
8209 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8210 code
= fixp
->fx_r_type
;
8216 switch (fixp
->fx_size
)
8219 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8220 _("can not do %d byte pc-relative relocation"),
8222 code
= BFD_RELOC_32_PCREL
;
8224 case 1: code
= BFD_RELOC_8_PCREL
; break;
8225 case 2: code
= BFD_RELOC_16_PCREL
; break;
8226 case 4: code
= BFD_RELOC_32_PCREL
; break;
8228 case 8: code
= BFD_RELOC_64_PCREL
; break;
8234 switch (fixp
->fx_size
)
8237 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8238 _("can not do %d byte relocation"),
8240 code
= BFD_RELOC_32
;
8242 case 1: code
= BFD_RELOC_8
; break;
8243 case 2: code
= BFD_RELOC_16
; break;
8244 case 4: code
= BFD_RELOC_32
; break;
8246 case 8: code
= BFD_RELOC_64
; break;
8253 if ((code
== BFD_RELOC_32
8254 || code
== BFD_RELOC_32_PCREL
8255 || code
== BFD_RELOC_X86_64_32S
)
8257 && fixp
->fx_addsy
== GOT_symbol
)
8260 code
= BFD_RELOC_386_GOTPC
;
8262 code
= BFD_RELOC_X86_64_GOTPC32
;
8264 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8266 && fixp
->fx_addsy
== GOT_symbol
)
8268 code
= BFD_RELOC_X86_64_GOTPC64
;
8271 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8272 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8273 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8275 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8277 if (!use_rela_relocations
)
8279 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8280 vtable entry to be used in the relocation's section offset. */
8281 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8282 rel
->address
= fixp
->fx_offset
;
8283 #if defined (OBJ_COFF) && defined (TE_PE)
8284 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8285 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8290 /* Use the rela in 64bit mode. */
8293 if (!fixp
->fx_pcrel
)
8294 rel
->addend
= fixp
->fx_offset
;
8298 case BFD_RELOC_X86_64_PLT32
:
8299 case BFD_RELOC_X86_64_GOT32
:
8300 case BFD_RELOC_X86_64_GOTPCREL
:
8301 case BFD_RELOC_X86_64_TLSGD
:
8302 case BFD_RELOC_X86_64_TLSLD
:
8303 case BFD_RELOC_X86_64_GOTTPOFF
:
8304 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8305 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8306 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8309 rel
->addend
= (section
->vma
8311 + fixp
->fx_addnumber
8312 + md_pcrel_from (fixp
));
8317 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8318 if (rel
->howto
== NULL
)
8320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8321 _("cannot represent relocation type %s"),
8322 bfd_get_reloc_code_name (code
));
8323 /* Set howto to a garbage value so that we can keep going. */
8324 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8325 gas_assert (rel
->howto
!= NULL
);
8331 #include "tc-i386-intel.c"
8334 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8336 int saved_naked_reg
;
8337 char saved_register_dot
;
8339 saved_naked_reg
= allow_naked_reg
;
8340 allow_naked_reg
= 1;
8341 saved_register_dot
= register_chars
['.'];
8342 register_chars
['.'] = '.';
8343 allow_pseudo_reg
= 1;
8344 expression_and_evaluate (exp
);
8345 allow_pseudo_reg
= 0;
8346 register_chars
['.'] = saved_register_dot
;
8347 allow_naked_reg
= saved_naked_reg
;
8349 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8351 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8353 exp
->X_op
= O_constant
;
8354 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8355 .dw2_regnum
[flag_code
>> 1];
8358 exp
->X_op
= O_illegal
;
8363 tc_x86_frame_initial_instructions (void)
8365 static unsigned int sp_regno
[2];
8367 if (!sp_regno
[flag_code
>> 1])
8369 char *saved_input
= input_line_pointer
;
8370 char sp
[][4] = {"esp", "rsp"};
8373 input_line_pointer
= sp
[flag_code
>> 1];
8374 tc_x86_parse_to_dw2regnum (&exp
);
8375 gas_assert (exp
.X_op
== O_constant
);
8376 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8377 input_line_pointer
= saved_input
;
8380 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8381 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8385 i386_elf_section_type (const char *str
, size_t len
)
8387 if (flag_code
== CODE_64BIT
8388 && len
== sizeof ("unwind") - 1
8389 && strncmp (str
, "unwind", 6) == 0)
8390 return SHT_X86_64_UNWIND
;
8397 i386_solaris_fix_up_eh_frame (segT sec
)
8399 if (flag_code
== CODE_64BIT
)
8400 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8406 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8410 expr
.X_op
= O_secrel
;
8411 expr
.X_add_symbol
= symbol
;
8412 expr
.X_add_number
= 0;
8413 emit_expr (&expr
, size
);
8417 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8418 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8421 x86_64_section_letter (int letter
, char **ptr_msg
)
8423 if (flag_code
== CODE_64BIT
)
8426 return SHF_X86_64_LARGE
;
8428 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8431 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8436 x86_64_section_word (char *str
, size_t len
)
8438 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8439 return SHF_X86_64_LARGE
;
8445 handle_large_common (int small ATTRIBUTE_UNUSED
)
8447 if (flag_code
!= CODE_64BIT
)
8449 s_comm_internal (0, elf_common_parse
);
8450 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8454 static segT lbss_section
;
8455 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8456 asection
*saved_bss_section
= bss_section
;
8458 if (lbss_section
== NULL
)
8460 flagword applicable
;
8462 subsegT subseg
= now_subseg
;
8464 /* The .lbss section is for local .largecomm symbols. */
8465 lbss_section
= subseg_new (".lbss", 0);
8466 applicable
= bfd_applicable_section_flags (stdoutput
);
8467 bfd_set_section_flags (stdoutput
, lbss_section
,
8468 applicable
& SEC_ALLOC
);
8469 seg_info (lbss_section
)->bss
= 1;
8471 subseg_set (seg
, subseg
);
8474 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8475 bss_section
= lbss_section
;
8477 s_comm_internal (0, elf_common_parse
);
8479 elf_com_section_ptr
= saved_com_section_ptr
;
8480 bss_section
= saved_bss_section
;
8483 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */