1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared
= 0;
526 /* 1 for intel syntax,
528 static int intel_syntax
= 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic
= !SYSV386_COMPAT
;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc
= OLDGCC_COMPAT
;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg
= 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg
= 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix
= 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg
= 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix
= 0;
555 static enum check_kind
561 sse_check
, operand_check
= check_warning
;
563 /* Register prefix used for error message. */
564 static const char *register_prefix
= "%";
566 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569 static char stackop_size
= '\0';
571 /* Non-zero to optimize code alignment. */
572 int optimize_align_code
= 1;
574 /* Non-zero to quieten some warnings. */
575 static int quiet_warnings
= 0;
578 static const char *cpu_arch_name
= NULL
;
579 static char *cpu_sub_arch_name
= NULL
;
581 /* CPU feature flags. */
582 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
584 /* If we have selected a cpu we are generating instructions for. */
585 static int cpu_arch_tune_set
= 0;
587 /* Cpu we are generating instructions for. */
588 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
590 /* CPU feature flags of cpu we are generating instructions for. */
591 static i386_cpu_flags cpu_arch_tune_flags
;
593 /* CPU instruction set architecture used. */
594 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
596 /* CPU feature flags of instruction set architecture used. */
597 i386_cpu_flags cpu_arch_isa_flags
;
599 /* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601 static unsigned int no_cond_jump_promotion
= 0;
603 /* Encode SSE instructions with VEX prefix. */
604 static unsigned int sse2avx
;
606 /* Encode scalar AVX instructions with specific vector length. */
613 /* Encode scalar EVEX LIG instructions with specific vector length. */
621 /* Encode EVEX WIG instructions with specific evex.w. */
628 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
629 static enum rc_type evexrcig
= rne
;
631 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
632 static symbolS
*GOT_symbol
;
634 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
635 unsigned int x86_dwarf2_return_column
;
637 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638 int x86_cie_data_alignment
;
640 /* Interface to relax_segment.
641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
646 #define UNCOND_JUMP 0
648 #define COND_JUMP86 2
653 #define SMALL16 (SMALL | CODE16)
655 #define BIG16 (BIG | CODE16)
659 #define INLINE __inline__
665 #define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667 #define TYPE_FROM_RELAX_STATE(s) \
669 #define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
672 /* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
680 const relax_typeS md_relax_table
[] =
683 1) most positive reach of this state,
684 2) most negative reach of this state,
685 3) how many bytes this mode will have in the variable part of the frag
686 4) which index into the table to try if we can't fit into this one. */
688 /* UNCOND_JUMP states. */
689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
704 /* word conditionals add 3 bytes to frag:
705 1 extra opcode byte, 2 displacement bytes. */
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
719 static const arch_entry cpu_arch
[] =
721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
724 CPU_GENERIC32_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
726 CPU_GENERIC64_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
728 CPU_NONE_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
730 CPU_I186_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
732 CPU_I286_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
734 CPU_I386_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
736 CPU_I486_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
738 CPU_I586_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
740 CPU_I686_FLAGS
, 0, 0 },
741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
742 CPU_I586_FLAGS
, 0, 0 },
743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
744 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
746 CPU_P2_FLAGS
, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
748 CPU_P3_FLAGS
, 0, 0 },
749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
750 CPU_P4_FLAGS
, 0, 0 },
751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
752 CPU_CORE_FLAGS
, 0, 0 },
753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
754 CPU_NOCONA_FLAGS
, 0, 0 },
755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
756 CPU_CORE_FLAGS
, 1, 0 },
757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
758 CPU_CORE_FLAGS
, 0, 0 },
759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
760 CPU_CORE2_FLAGS
, 1, 0 },
761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
762 CPU_CORE2_FLAGS
, 0, 0 },
763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
764 CPU_COREI7_FLAGS
, 0, 0 },
765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
766 CPU_L1OM_FLAGS
, 0, 0 },
767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
768 CPU_K1OM_FLAGS
, 0, 0 },
769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
770 CPU_IAMCU_FLAGS
, 0, 0 },
771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
772 CPU_K6_FLAGS
, 0, 0 },
773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
774 CPU_K6_2_FLAGS
, 0, 0 },
775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
776 CPU_ATHLON_FLAGS
, 0, 0 },
777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
778 CPU_K8_FLAGS
, 1, 0 },
779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
780 CPU_K8_FLAGS
, 0, 0 },
781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
782 CPU_K8_FLAGS
, 0, 0 },
783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
784 CPU_AMDFAM10_FLAGS
, 0, 0 },
785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
786 CPU_BDVER1_FLAGS
, 0, 0 },
787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
788 CPU_BDVER2_FLAGS
, 0, 0 },
789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
790 CPU_BDVER3_FLAGS
, 0, 0 },
791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
792 CPU_BDVER4_FLAGS
, 0, 0 },
793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
794 CPU_ZNVER1_FLAGS
, 0, 0 },
795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
796 CPU_BTVER1_FLAGS
, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
798 CPU_BTVER2_FLAGS
, 0, 0 },
799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
800 CPU_8087_FLAGS
, 0, 0 },
801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
802 CPU_287_FLAGS
, 0, 0 },
803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
804 CPU_387_FLAGS
, 0, 0 },
805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
806 CPU_ANY87_FLAGS
, 0, 1 },
807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
808 CPU_MMX_FLAGS
, 0, 0 },
809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
810 CPU_3DNOWA_FLAGS
, 0, 1 },
811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
812 CPU_SSE_FLAGS
, 0, 0 },
813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
814 CPU_SSE2_FLAGS
, 0, 0 },
815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
816 CPU_SSE3_FLAGS
, 0, 0 },
817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
818 CPU_SSSE3_FLAGS
, 0, 0 },
819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
820 CPU_SSE4_1_FLAGS
, 0, 0 },
821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
822 CPU_SSE4_2_FLAGS
, 0, 0 },
823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
824 CPU_SSE4_2_FLAGS
, 0, 0 },
825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
826 CPU_ANY_SSE_FLAGS
, 0, 1 },
827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
828 CPU_AVX_FLAGS
, 0, 0 },
829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
830 CPU_AVX2_FLAGS
, 0, 0 },
831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
832 CPU_AVX512F_FLAGS
, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
834 CPU_AVX512CD_FLAGS
, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
836 CPU_AVX512ER_FLAGS
, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
838 CPU_AVX512PF_FLAGS
, 0, 0 },
839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
840 CPU_AVX512DQ_FLAGS
, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
842 CPU_AVX512BW_FLAGS
, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
844 CPU_AVX512VL_FLAGS
, 0, 0 },
845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
846 CPU_ANY_AVX_FLAGS
, 0, 1 },
847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
848 CPU_VMX_FLAGS
, 0, 0 },
849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
850 CPU_VMFUNC_FLAGS
, 0, 0 },
851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
852 CPU_SMX_FLAGS
, 0, 0 },
853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
854 CPU_XSAVE_FLAGS
, 0, 0 },
855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
856 CPU_XSAVEOPT_FLAGS
, 0, 0 },
857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
858 CPU_XSAVEC_FLAGS
, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
860 CPU_XSAVES_FLAGS
, 0, 0 },
861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
862 CPU_AES_FLAGS
, 0, 0 },
863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
864 CPU_PCLMUL_FLAGS
, 0, 0 },
865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
866 CPU_PCLMUL_FLAGS
, 1, 0 },
867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
868 CPU_FSGSBASE_FLAGS
, 0, 0 },
869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
870 CPU_RDRND_FLAGS
, 0, 0 },
871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
872 CPU_F16C_FLAGS
, 0, 0 },
873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
874 CPU_BMI2_FLAGS
, 0, 0 },
875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
876 CPU_FMA_FLAGS
, 0, 0 },
877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
878 CPU_FMA4_FLAGS
, 0, 0 },
879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
880 CPU_XOP_FLAGS
, 0, 0 },
881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
882 CPU_LWP_FLAGS
, 0, 0 },
883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
884 CPU_MOVBE_FLAGS
, 0, 0 },
885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
886 CPU_CX16_FLAGS
, 0, 0 },
887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
888 CPU_EPT_FLAGS
, 0, 0 },
889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
890 CPU_LZCNT_FLAGS
, 0, 0 },
891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
892 CPU_HLE_FLAGS
, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
894 CPU_RTM_FLAGS
, 0, 0 },
895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
896 CPU_INVPCID_FLAGS
, 0, 0 },
897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
898 CPU_CLFLUSH_FLAGS
, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
900 CPU_NOP_FLAGS
, 0, 0 },
901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
902 CPU_SYSCALL_FLAGS
, 0, 0 },
903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
904 CPU_RDTSCP_FLAGS
, 0, 0 },
905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
906 CPU_3DNOW_FLAGS
, 0, 0 },
907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
908 CPU_3DNOWA_FLAGS
, 0, 0 },
909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
910 CPU_PADLOCK_FLAGS
, 0, 0 },
911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
912 CPU_SVME_FLAGS
, 1, 0 },
913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
914 CPU_SVME_FLAGS
, 0, 0 },
915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
916 CPU_SSE4A_FLAGS
, 0, 0 },
917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
918 CPU_ABM_FLAGS
, 0, 0 },
919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
920 CPU_BMI_FLAGS
, 0, 0 },
921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
922 CPU_TBM_FLAGS
, 0, 0 },
923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
924 CPU_ADX_FLAGS
, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
926 CPU_RDSEED_FLAGS
, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
928 CPU_PRFCHW_FLAGS
, 0, 0 },
929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
930 CPU_SMAP_FLAGS
, 0, 0 },
931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
932 CPU_MPX_FLAGS
, 0, 0 },
933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
934 CPU_SHA_FLAGS
, 0, 0 },
935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
936 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
938 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
940 CPU_SE1_FLAGS
, 0, 0 },
941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
942 CPU_CLWB_FLAGS
, 0, 0 },
943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
944 CPU_PCOMMIT_FLAGS
, 0, 0 },
945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
946 CPU_AVX512IFMA_FLAGS
, 0, 0 },
947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
948 CPU_AVX512VBMI_FLAGS
, 0, 0 },
949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
950 CPU_CLZERO_FLAGS
, 0, 0 },
951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
952 CPU_MWAITX_FLAGS
, 0, 0 },
953 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
954 CPU_OSPKE_FLAGS
, 0, 0 },
958 /* Like s_lcomm_internal in gas/read.c but the alignment string
959 is allowed to be optional. */
962 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
969 && *input_line_pointer
== ',')
971 align
= parse_align (needs_align
- 1);
973 if (align
== (addressT
) -1)
988 bss_alloc (symbolP
, size
, align
);
993 pe_lcomm (int needs_align
)
995 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
999 const pseudo_typeS md_pseudo_table
[] =
1001 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1002 {"align", s_align_bytes
, 0},
1004 {"align", s_align_ptwo
, 0},
1006 {"arch", set_cpu_arch
, 0},
1010 {"lcomm", pe_lcomm
, 1},
1012 {"ffloat", float_cons
, 'f'},
1013 {"dfloat", float_cons
, 'd'},
1014 {"tfloat", float_cons
, 'x'},
1016 {"slong", signed_cons
, 4},
1017 {"noopt", s_ignore
, 0},
1018 {"optim", s_ignore
, 0},
1019 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1020 {"code16", set_code_flag
, CODE_16BIT
},
1021 {"code32", set_code_flag
, CODE_32BIT
},
1022 {"code64", set_code_flag
, CODE_64BIT
},
1023 {"intel_syntax", set_intel_syntax
, 1},
1024 {"att_syntax", set_intel_syntax
, 0},
1025 {"intel_mnemonic", set_intel_mnemonic
, 1},
1026 {"att_mnemonic", set_intel_mnemonic
, 0},
1027 {"allow_index_reg", set_allow_index_reg
, 1},
1028 {"disallow_index_reg", set_allow_index_reg
, 0},
1029 {"sse_check", set_check
, 0},
1030 {"operand_check", set_check
, 1},
1031 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1032 {"largecomm", handle_large_common
, 0},
1034 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1035 {"loc", dwarf2_directive_loc
, 0},
1036 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1039 {"secrel32", pe_directive_secrel
, 0},
1044 /* For interface with expression (). */
1045 extern char *input_line_pointer
;
1047 /* Hash table for instruction mnemonic lookup. */
1048 static struct hash_control
*op_hash
;
1050 /* Hash table for register lookup. */
1051 static struct hash_control
*reg_hash
;
1054 i386_align_code (fragS
*fragP
, int count
)
1056 /* Various efficient no-op patterns for aligning code labels.
1057 Note: Don't try to assemble the instructions in the comments.
1058 0L and 0w are not legal. */
1059 static const char f32_1
[] =
1061 static const char f32_2
[] =
1062 {0x66,0x90}; /* xchg %ax,%ax */
1063 static const char f32_3
[] =
1064 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1065 static const char f32_4
[] =
1066 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1067 static const char f32_5
[] =
1069 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1070 static const char f32_6
[] =
1071 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1072 static const char f32_7
[] =
1073 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1074 static const char f32_8
[] =
1076 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1077 static const char f32_9
[] =
1078 {0x89,0xf6, /* movl %esi,%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_10
[] =
1081 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1082 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1083 static const char f32_11
[] =
1084 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1085 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1086 static const char f32_12
[] =
1087 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1088 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1089 static const char f32_13
[] =
1090 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1092 static const char f32_14
[] =
1093 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1094 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1095 static const char f16_3
[] =
1096 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1097 static const char f16_4
[] =
1098 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1099 static const char f16_5
[] =
1101 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1102 static const char f16_6
[] =
1103 {0x89,0xf6, /* mov %si,%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1105 static const char f16_7
[] =
1106 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1107 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1108 static const char f16_8
[] =
1109 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1110 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1111 static const char jump_31
[] =
1112 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1114 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1115 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1116 static const char *const f32_patt
[] = {
1117 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1118 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1120 static const char *const f16_patt
[] = {
1121 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1123 /* nopl (%[re]ax) */
1124 static const char alt_3
[] =
1126 /* nopl 0(%[re]ax) */
1127 static const char alt_4
[] =
1128 {0x0f,0x1f,0x40,0x00};
1129 /* nopl 0(%[re]ax,%[re]ax,1) */
1130 static const char alt_5
[] =
1131 {0x0f,0x1f,0x44,0x00,0x00};
1132 /* nopw 0(%[re]ax,%[re]ax,1) */
1133 static const char alt_6
[] =
1134 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1135 /* nopl 0L(%[re]ax) */
1136 static const char alt_7
[] =
1137 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1138 /* nopl 0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_8
[] =
1140 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 /* nopw 0L(%[re]ax,%[re]ax,1) */
1142 static const char alt_9
[] =
1143 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1145 static const char alt_10
[] =
1146 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1147 static const char *const alt_patt
[] = {
1148 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1152 /* Only align for at least a positive non-zero boundary. */
1153 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1156 /* We need to decide which NOP sequence to use for 32bit and
1157 64bit. When -mtune= is used:
1159 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1160 PROCESSOR_GENERIC32, f32_patt will be used.
1161 2. For the rest, alt_patt will be used.
1163 When -mtune= isn't used, alt_patt will be used if
1164 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1167 When -march= or .arch is used, we can't use anything beyond
1168 cpu_arch_isa_flags. */
1170 if (flag_code
== CODE_16BIT
)
1174 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1176 /* Adjust jump offset. */
1177 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1180 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1181 f16_patt
[count
- 1], count
);
1185 const char *const *patt
= NULL
;
1187 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1189 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1190 switch (cpu_arch_tune
)
1192 case PROCESSOR_UNKNOWN
:
1193 /* We use cpu_arch_isa_flags to check if we SHOULD
1194 optimize with nops. */
1195 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1200 case PROCESSOR_PENTIUM4
:
1201 case PROCESSOR_NOCONA
:
1202 case PROCESSOR_CORE
:
1203 case PROCESSOR_CORE2
:
1204 case PROCESSOR_COREI7
:
1205 case PROCESSOR_L1OM
:
1206 case PROCESSOR_K1OM
:
1207 case PROCESSOR_GENERIC64
:
1209 case PROCESSOR_ATHLON
:
1211 case PROCESSOR_AMDFAM10
:
1213 case PROCESSOR_ZNVER
:
1217 case PROCESSOR_I386
:
1218 case PROCESSOR_I486
:
1219 case PROCESSOR_PENTIUM
:
1220 case PROCESSOR_PENTIUMPRO
:
1221 case PROCESSOR_IAMCU
:
1222 case PROCESSOR_GENERIC32
:
1229 switch (fragP
->tc_frag_data
.tune
)
1231 case PROCESSOR_UNKNOWN
:
1232 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1233 PROCESSOR_UNKNOWN. */
1237 case PROCESSOR_I386
:
1238 case PROCESSOR_I486
:
1239 case PROCESSOR_PENTIUM
:
1240 case PROCESSOR_IAMCU
:
1242 case PROCESSOR_ATHLON
:
1244 case PROCESSOR_AMDFAM10
:
1246 case PROCESSOR_ZNVER
:
1248 case PROCESSOR_GENERIC32
:
1249 /* We use cpu_arch_isa_flags to check if we CAN optimize
1251 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1256 case PROCESSOR_PENTIUMPRO
:
1257 case PROCESSOR_PENTIUM4
:
1258 case PROCESSOR_NOCONA
:
1259 case PROCESSOR_CORE
:
1260 case PROCESSOR_CORE2
:
1261 case PROCESSOR_COREI7
:
1262 case PROCESSOR_L1OM
:
1263 case PROCESSOR_K1OM
:
1264 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1269 case PROCESSOR_GENERIC64
:
1275 if (patt
== f32_patt
)
1277 /* If the padding is less than 15 bytes, we use the normal
1278 ones. Otherwise, we use a jump instruction and adjust
1282 /* For 64bit, the limit is 3 bytes. */
1283 if (flag_code
== CODE_64BIT
1284 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1289 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1290 patt
[count
- 1], count
);
1293 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1295 /* Adjust jump offset. */
1296 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1301 /* Maximum length of an instruction is 10 byte. If the
1302 padding is greater than 10 bytes and we don't use jump,
1303 we have to break it into smaller pieces. */
1304 int padding
= count
;
1305 while (padding
> 10)
1308 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1313 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1314 patt
[padding
- 1], padding
);
1317 fragP
->fr_var
= count
;
1321 operand_type_all_zero (const union i386_operand_type
*x
)
1323 switch (ARRAY_SIZE(x
->array
))
1332 return !x
->array
[0];
1339 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1341 switch (ARRAY_SIZE(x
->array
))
1356 operand_type_equal (const union i386_operand_type
*x
,
1357 const union i386_operand_type
*y
)
1359 switch (ARRAY_SIZE(x
->array
))
1362 if (x
->array
[2] != y
->array
[2])
1365 if (x
->array
[1] != y
->array
[1])
1368 return x
->array
[0] == y
->array
[0];
1376 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1378 switch (ARRAY_SIZE(x
->array
))
1387 return !x
->array
[0];
1394 cpu_flags_equal (const union i386_cpu_flags
*x
,
1395 const union i386_cpu_flags
*y
)
1397 switch (ARRAY_SIZE(x
->array
))
1400 if (x
->array
[2] != y
->array
[2])
1403 if (x
->array
[1] != y
->array
[1])
1406 return x
->array
[0] == y
->array
[0];
1414 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1416 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1417 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1420 static INLINE i386_cpu_flags
1421 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1423 switch (ARRAY_SIZE (x
.array
))
1426 x
.array
[2] &= y
.array
[2];
1428 x
.array
[1] &= y
.array
[1];
1430 x
.array
[0] &= y
.array
[0];
1438 static INLINE i386_cpu_flags
1439 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1441 switch (ARRAY_SIZE (x
.array
))
1444 x
.array
[2] |= y
.array
[2];
1446 x
.array
[1] |= y
.array
[1];
1448 x
.array
[0] |= y
.array
[0];
1456 static INLINE i386_cpu_flags
1457 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1459 switch (ARRAY_SIZE (x
.array
))
1462 x
.array
[2] &= ~y
.array
[2];
1464 x
.array
[1] &= ~y
.array
[1];
1466 x
.array
[0] &= ~y
.array
[0];
1475 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1477 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1479 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1480 i386_cpu_flags compat_flags
;
1481 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1482 return cpu_flags_all_zero (&compat_flags
);
1488 #define CPU_FLAGS_ARCH_MATCH 0x1
1489 #define CPU_FLAGS_64BIT_MATCH 0x2
1490 #define CPU_FLAGS_AES_MATCH 0x4
1491 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1492 #define CPU_FLAGS_AVX_MATCH 0x10
1494 #define CPU_FLAGS_32BIT_MATCH \
1495 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1496 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1497 #define CPU_FLAGS_PERFECT_MATCH \
1498 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1500 /* Return CPU flags match bits. */
1503 cpu_flags_match (const insn_template
*t
)
1505 i386_cpu_flags x
= t
->cpu_flags
;
1506 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1508 x
.bitfield
.cpu64
= 0;
1509 x
.bitfield
.cpuno64
= 0;
1511 if (cpu_flags_all_zero (&x
))
1513 /* This instruction is available on all archs. */
1514 match
|= CPU_FLAGS_32BIT_MATCH
;
1518 /* This instruction is available only on some archs. */
1519 i386_cpu_flags cpu
= cpu_arch_flags
;
1521 cpu
.bitfield
.cpu64
= 0;
1522 cpu
.bitfield
.cpuno64
= 0;
1523 cpu
= cpu_flags_and (x
, cpu
);
1524 if (!cpu_flags_all_zero (&cpu
))
1526 if (x
.bitfield
.cpuavx
)
1528 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1529 if (cpu
.bitfield
.cpuavx
)
1531 /* Check SSE2AVX. */
1532 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1534 match
|= (CPU_FLAGS_ARCH_MATCH
1535 | CPU_FLAGS_AVX_MATCH
);
1537 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1538 match
|= CPU_FLAGS_AES_MATCH
;
1540 if (!x
.bitfield
.cpupclmul
1541 || cpu
.bitfield
.cpupclmul
)
1542 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1546 match
|= CPU_FLAGS_ARCH_MATCH
;
1549 match
|= CPU_FLAGS_32BIT_MATCH
;
1555 static INLINE i386_operand_type
1556 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1558 switch (ARRAY_SIZE (x
.array
))
1561 x
.array
[2] &= y
.array
[2];
1563 x
.array
[1] &= y
.array
[1];
1565 x
.array
[0] &= y
.array
[0];
1573 static INLINE i386_operand_type
1574 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1576 switch (ARRAY_SIZE (x
.array
))
1579 x
.array
[2] |= y
.array
[2];
1581 x
.array
[1] |= y
.array
[1];
1583 x
.array
[0] |= y
.array
[0];
1591 static INLINE i386_operand_type
1592 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1594 switch (ARRAY_SIZE (x
.array
))
1597 x
.array
[2] ^= y
.array
[2];
1599 x
.array
[1] ^= y
.array
[1];
1601 x
.array
[0] ^= y
.array
[0];
1609 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1610 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1611 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1612 static const i386_operand_type inoutportreg
1613 = OPERAND_TYPE_INOUTPORTREG
;
1614 static const i386_operand_type reg16_inoutportreg
1615 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1616 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1617 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1618 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1619 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1620 static const i386_operand_type anydisp
1621 = OPERAND_TYPE_ANYDISP
;
1622 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1623 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1624 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1625 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1626 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1627 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1628 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1629 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1630 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1631 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1632 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1633 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1634 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1635 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1646 operand_type_check (i386_operand_type t
, enum operand_type c
)
1651 return (t
.bitfield
.reg8
1654 || t
.bitfield
.reg64
);
1657 return (t
.bitfield
.imm8
1661 || t
.bitfield
.imm32s
1662 || t
.bitfield
.imm64
);
1665 return (t
.bitfield
.disp8
1666 || t
.bitfield
.disp16
1667 || t
.bitfield
.disp32
1668 || t
.bitfield
.disp32s
1669 || t
.bitfield
.disp64
);
1672 return (t
.bitfield
.disp8
1673 || t
.bitfield
.disp16
1674 || t
.bitfield
.disp32
1675 || t
.bitfield
.disp32s
1676 || t
.bitfield
.disp64
1677 || t
.bitfield
.baseindex
);
1686 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1687 operand J for instruction template T. */
1690 match_reg_size (const insn_template
*t
, unsigned int j
)
1692 return !((i
.types
[j
].bitfield
.byte
1693 && !t
->operand_types
[j
].bitfield
.byte
)
1694 || (i
.types
[j
].bitfield
.word
1695 && !t
->operand_types
[j
].bitfield
.word
)
1696 || (i
.types
[j
].bitfield
.dword
1697 && !t
->operand_types
[j
].bitfield
.dword
)
1698 || (i
.types
[j
].bitfield
.qword
1699 && !t
->operand_types
[j
].bitfield
.qword
));
1702 /* Return 1 if there is no conflict in any size on operand J for
1703 instruction template T. */
1706 match_mem_size (const insn_template
*t
, unsigned int j
)
1708 return (match_reg_size (t
, j
)
1709 && !((i
.types
[j
].bitfield
.unspecified
1711 && !t
->operand_types
[j
].bitfield
.unspecified
)
1712 || (i
.types
[j
].bitfield
.fword
1713 && !t
->operand_types
[j
].bitfield
.fword
)
1714 || (i
.types
[j
].bitfield
.tbyte
1715 && !t
->operand_types
[j
].bitfield
.tbyte
)
1716 || (i
.types
[j
].bitfield
.xmmword
1717 && !t
->operand_types
[j
].bitfield
.xmmword
)
1718 || (i
.types
[j
].bitfield
.ymmword
1719 && !t
->operand_types
[j
].bitfield
.ymmword
)
1720 || (i
.types
[j
].bitfield
.zmmword
1721 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1724 /* Return 1 if there is no size conflict on any operands for
1725 instruction template T. */
1728 operand_size_match (const insn_template
*t
)
1733 /* Don't check jump instructions. */
1734 if (t
->opcode_modifier
.jump
1735 || t
->opcode_modifier
.jumpbyte
1736 || t
->opcode_modifier
.jumpdword
1737 || t
->opcode_modifier
.jumpintersegment
)
1740 /* Check memory and accumulator operand size. */
1741 for (j
= 0; j
< i
.operands
; j
++)
1743 if (t
->operand_types
[j
].bitfield
.anysize
)
1746 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1752 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1761 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1764 i
.error
= operand_size_mismatch
;
1768 /* Check reverse. */
1769 gas_assert (i
.operands
== 2);
1772 for (j
= 0; j
< 2; j
++)
1774 if (t
->operand_types
[j
].bitfield
.acc
1775 && !match_reg_size (t
, j
? 0 : 1))
1778 if (i
.types
[j
].bitfield
.mem
1779 && !match_mem_size (t
, j
? 0 : 1))
1787 operand_type_match (i386_operand_type overlap
,
1788 i386_operand_type given
)
1790 i386_operand_type temp
= overlap
;
1792 temp
.bitfield
.jumpabsolute
= 0;
1793 temp
.bitfield
.unspecified
= 0;
1794 temp
.bitfield
.byte
= 0;
1795 temp
.bitfield
.word
= 0;
1796 temp
.bitfield
.dword
= 0;
1797 temp
.bitfield
.fword
= 0;
1798 temp
.bitfield
.qword
= 0;
1799 temp
.bitfield
.tbyte
= 0;
1800 temp
.bitfield
.xmmword
= 0;
1801 temp
.bitfield
.ymmword
= 0;
1802 temp
.bitfield
.zmmword
= 0;
1803 if (operand_type_all_zero (&temp
))
1806 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1807 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1811 i
.error
= operand_type_mismatch
;
1815 /* If given types g0 and g1 are registers they must be of the same type
1816 unless the expected operand type register overlap is null.
1817 Note that Acc in a template matches every size of reg. */
1820 operand_type_register_match (i386_operand_type m0
,
1821 i386_operand_type g0
,
1822 i386_operand_type t0
,
1823 i386_operand_type m1
,
1824 i386_operand_type g1
,
1825 i386_operand_type t1
)
1827 if (!operand_type_check (g0
, reg
))
1830 if (!operand_type_check (g1
, reg
))
1833 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1834 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1835 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1836 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1839 if (m0
.bitfield
.acc
)
1841 t0
.bitfield
.reg8
= 1;
1842 t0
.bitfield
.reg16
= 1;
1843 t0
.bitfield
.reg32
= 1;
1844 t0
.bitfield
.reg64
= 1;
1847 if (m1
.bitfield
.acc
)
1849 t1
.bitfield
.reg8
= 1;
1850 t1
.bitfield
.reg16
= 1;
1851 t1
.bitfield
.reg32
= 1;
1852 t1
.bitfield
.reg64
= 1;
1855 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1856 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1857 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1858 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1861 i
.error
= register_type_mismatch
;
1866 static INLINE
unsigned int
1867 register_number (const reg_entry
*r
)
1869 unsigned int nr
= r
->reg_num
;
1871 if (r
->reg_flags
& RegRex
)
1877 static INLINE
unsigned int
1878 mode_from_disp_size (i386_operand_type t
)
1880 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1882 else if (t
.bitfield
.disp16
1883 || t
.bitfield
.disp32
1884 || t
.bitfield
.disp32s
)
1891 fits_in_signed_byte (addressT num
)
1893 return num
+ 0x80 <= 0xff;
1897 fits_in_unsigned_byte (addressT num
)
1903 fits_in_unsigned_word (addressT num
)
1905 return num
<= 0xffff;
1909 fits_in_signed_word (addressT num
)
1911 return num
+ 0x8000 <= 0xffff;
1915 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1920 return num
+ 0x80000000 <= 0xffffffff;
1922 } /* fits_in_signed_long() */
1925 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1930 return num
<= 0xffffffff;
1932 } /* fits_in_unsigned_long() */
1935 fits_in_vec_disp8 (offsetT num
)
1937 int shift
= i
.memshift
;
1943 mask
= (1 << shift
) - 1;
1945 /* Return 0 if NUM isn't properly aligned. */
1949 /* Check if NUM will fit in 8bit after shift. */
1950 return fits_in_signed_byte (num
>> shift
);
1954 fits_in_imm4 (offsetT num
)
1956 return (num
& 0xf) == num
;
1959 static i386_operand_type
1960 smallest_imm_type (offsetT num
)
1962 i386_operand_type t
;
1964 operand_type_set (&t
, 0);
1965 t
.bitfield
.imm64
= 1;
1967 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1969 /* This code is disabled on the 486 because all the Imm1 forms
1970 in the opcode table are slower on the i486. They're the
1971 versions with the implicitly specified single-position
1972 displacement, which has another syntax if you really want to
1974 t
.bitfield
.imm1
= 1;
1975 t
.bitfield
.imm8
= 1;
1976 t
.bitfield
.imm8s
= 1;
1977 t
.bitfield
.imm16
= 1;
1978 t
.bitfield
.imm32
= 1;
1979 t
.bitfield
.imm32s
= 1;
1981 else if (fits_in_signed_byte (num
))
1983 t
.bitfield
.imm8
= 1;
1984 t
.bitfield
.imm8s
= 1;
1985 t
.bitfield
.imm16
= 1;
1986 t
.bitfield
.imm32
= 1;
1987 t
.bitfield
.imm32s
= 1;
1989 else if (fits_in_unsigned_byte (num
))
1991 t
.bitfield
.imm8
= 1;
1992 t
.bitfield
.imm16
= 1;
1993 t
.bitfield
.imm32
= 1;
1994 t
.bitfield
.imm32s
= 1;
1996 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1998 t
.bitfield
.imm16
= 1;
1999 t
.bitfield
.imm32
= 1;
2000 t
.bitfield
.imm32s
= 1;
2002 else if (fits_in_signed_long (num
))
2004 t
.bitfield
.imm32
= 1;
2005 t
.bitfield
.imm32s
= 1;
2007 else if (fits_in_unsigned_long (num
))
2008 t
.bitfield
.imm32
= 1;
2014 offset_in_range (offsetT val
, int size
)
2020 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2021 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2022 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2024 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2030 /* If BFD64, sign extend val for 32bit address mode. */
2031 if (flag_code
!= CODE_64BIT
2032 || i
.prefix
[ADDR_PREFIX
])
2033 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2034 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2037 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2039 char buf1
[40], buf2
[40];
2041 sprint_value (buf1
, val
);
2042 sprint_value (buf2
, val
& mask
);
2043 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2057 a. PREFIX_EXIST if attempting to add a prefix where one from the
2058 same class already exists.
2059 b. PREFIX_LOCK if lock prefix is added.
2060 c. PREFIX_REP if rep/repne prefix is added.
2061 d. PREFIX_OTHER if other prefix is added.
2064 static enum PREFIX_GROUP
2065 add_prefix (unsigned int prefix
)
2067 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2070 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2071 && flag_code
== CODE_64BIT
)
2073 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2074 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2075 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2086 case CS_PREFIX_OPCODE
:
2087 case DS_PREFIX_OPCODE
:
2088 case ES_PREFIX_OPCODE
:
2089 case FS_PREFIX_OPCODE
:
2090 case GS_PREFIX_OPCODE
:
2091 case SS_PREFIX_OPCODE
:
2095 case REPNE_PREFIX_OPCODE
:
2096 case REPE_PREFIX_OPCODE
:
2101 case LOCK_PREFIX_OPCODE
:
2110 case ADDR_PREFIX_OPCODE
:
2114 case DATA_PREFIX_OPCODE
:
2118 if (i
.prefix
[q
] != 0)
2126 i
.prefix
[q
] |= prefix
;
2129 as_bad (_("same type of prefix used twice"));
2135 update_code_flag (int value
, int check
)
2137 PRINTF_LIKE ((*as_error
));
2139 flag_code
= (enum flag_code
) value
;
2140 if (flag_code
== CODE_64BIT
)
2142 cpu_arch_flags
.bitfield
.cpu64
= 1;
2143 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2147 cpu_arch_flags
.bitfield
.cpu64
= 0;
2148 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2150 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2153 as_error
= as_fatal
;
2156 (*as_error
) (_("64bit mode not supported on `%s'."),
2157 cpu_arch_name
? cpu_arch_name
: default_arch
);
2159 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2162 as_error
= as_fatal
;
2165 (*as_error
) (_("32bit mode not supported on `%s'."),
2166 cpu_arch_name
? cpu_arch_name
: default_arch
);
2168 stackop_size
= '\0';
2172 set_code_flag (int value
)
2174 update_code_flag (value
, 0);
2178 set_16bit_gcc_code_flag (int new_code_flag
)
2180 flag_code
= (enum flag_code
) new_code_flag
;
2181 if (flag_code
!= CODE_16BIT
)
2183 cpu_arch_flags
.bitfield
.cpu64
= 0;
2184 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2185 stackop_size
= LONG_MNEM_SUFFIX
;
2189 set_intel_syntax (int syntax_flag
)
2191 /* Find out if register prefixing is specified. */
2192 int ask_naked_reg
= 0;
2195 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2198 int e
= get_symbol_name (&string
);
2200 if (strcmp (string
, "prefix") == 0)
2202 else if (strcmp (string
, "noprefix") == 0)
2205 as_bad (_("bad argument to syntax directive."));
2206 (void) restore_line_pointer (e
);
2208 demand_empty_rest_of_line ();
2210 intel_syntax
= syntax_flag
;
2212 if (ask_naked_reg
== 0)
2213 allow_naked_reg
= (intel_syntax
2214 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2216 allow_naked_reg
= (ask_naked_reg
< 0);
2218 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2220 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2221 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2222 register_prefix
= allow_naked_reg
? "" : "%";
2226 set_intel_mnemonic (int mnemonic_flag
)
2228 intel_mnemonic
= mnemonic_flag
;
2232 set_allow_index_reg (int flag
)
2234 allow_index_reg
= flag
;
2238 set_check (int what
)
2240 enum check_kind
*kind
;
2245 kind
= &operand_check
;
2256 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2259 int e
= get_symbol_name (&string
);
2261 if (strcmp (string
, "none") == 0)
2263 else if (strcmp (string
, "warning") == 0)
2264 *kind
= check_warning
;
2265 else if (strcmp (string
, "error") == 0)
2266 *kind
= check_error
;
2268 as_bad (_("bad argument to %s_check directive."), str
);
2269 (void) restore_line_pointer (e
);
2272 as_bad (_("missing argument for %s_check directive"), str
);
2274 demand_empty_rest_of_line ();
2278 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2279 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2282 static const char *arch
;
2284 /* Intel LIOM is only supported on ELF. */
2290 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2291 use default_arch. */
2292 arch
= cpu_arch_name
;
2294 arch
= default_arch
;
2297 /* If we are targeting Intel MCU, we must enable it. */
2298 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2299 || new_flag
.bitfield
.cpuiamcu
)
2302 /* If we are targeting Intel L1OM, we must enable it. */
2303 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2304 || new_flag
.bitfield
.cpul1om
)
2307 /* If we are targeting Intel K1OM, we must enable it. */
2308 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2309 || new_flag
.bitfield
.cpuk1om
)
2312 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2317 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2321 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2324 int e
= get_symbol_name (&string
);
2326 i386_cpu_flags flags
;
2328 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2330 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2332 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2336 cpu_arch_name
= cpu_arch
[j
].name
;
2337 cpu_sub_arch_name
= NULL
;
2338 cpu_arch_flags
= cpu_arch
[j
].flags
;
2339 if (flag_code
== CODE_64BIT
)
2341 cpu_arch_flags
.bitfield
.cpu64
= 1;
2342 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2346 cpu_arch_flags
.bitfield
.cpu64
= 0;
2347 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2349 cpu_arch_isa
= cpu_arch
[j
].type
;
2350 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2351 if (!cpu_arch_tune_set
)
2353 cpu_arch_tune
= cpu_arch_isa
;
2354 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2359 if (!cpu_arch
[j
].negated
)
2360 flags
= cpu_flags_or (cpu_arch_flags
,
2363 flags
= cpu_flags_and_not (cpu_arch_flags
,
2366 if (!valid_iamcu_cpu_flags (&flags
))
2367 as_fatal (_("`%s' isn't valid for Intel MCU"),
2369 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2371 if (cpu_sub_arch_name
)
2373 char *name
= cpu_sub_arch_name
;
2374 cpu_sub_arch_name
= concat (name
,
2376 (const char *) NULL
);
2380 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2381 cpu_arch_flags
= flags
;
2382 cpu_arch_isa_flags
= flags
;
2384 (void) restore_line_pointer (e
);
2385 demand_empty_rest_of_line ();
2389 if (j
>= ARRAY_SIZE (cpu_arch
))
2390 as_bad (_("no such architecture: `%s'"), string
);
2392 *input_line_pointer
= e
;
2395 as_bad (_("missing cpu architecture"));
2397 no_cond_jump_promotion
= 0;
2398 if (*input_line_pointer
== ','
2399 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2404 ++input_line_pointer
;
2405 e
= get_symbol_name (&string
);
2407 if (strcmp (string
, "nojumps") == 0)
2408 no_cond_jump_promotion
= 1;
2409 else if (strcmp (string
, "jumps") == 0)
2412 as_bad (_("no such architecture modifier: `%s'"), string
);
2414 (void) restore_line_pointer (e
);
2417 demand_empty_rest_of_line ();
2420 enum bfd_architecture
2423 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2425 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2426 || flag_code
!= CODE_64BIT
)
2427 as_fatal (_("Intel L1OM is 64bit ELF only"));
2428 return bfd_arch_l1om
;
2430 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2432 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2433 || flag_code
!= CODE_64BIT
)
2434 as_fatal (_("Intel K1OM is 64bit ELF only"));
2435 return bfd_arch_k1om
;
2437 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2439 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2440 || flag_code
== CODE_64BIT
)
2441 as_fatal (_("Intel MCU is 32bit ELF only"));
2442 return bfd_arch_iamcu
;
2445 return bfd_arch_i386
;
2451 if (!strncmp (default_arch
, "x86_64", 6))
2453 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2455 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2456 || default_arch
[6] != '\0')
2457 as_fatal (_("Intel L1OM is 64bit ELF only"));
2458 return bfd_mach_l1om
;
2460 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2462 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2463 || default_arch
[6] != '\0')
2464 as_fatal (_("Intel K1OM is 64bit ELF only"));
2465 return bfd_mach_k1om
;
2467 else if (default_arch
[6] == '\0')
2468 return bfd_mach_x86_64
;
2470 return bfd_mach_x64_32
;
2472 else if (!strcmp (default_arch
, "i386")
2473 || !strcmp (default_arch
, "iamcu"))
2475 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2477 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2478 as_fatal (_("Intel MCU is 32bit ELF only"));
2479 return bfd_mach_i386_iamcu
;
2482 return bfd_mach_i386_i386
;
2485 as_fatal (_("unknown architecture"));
2491 const char *hash_err
;
2493 /* Initialize op_hash hash table. */
2494 op_hash
= hash_new ();
2497 const insn_template
*optab
;
2498 templates
*core_optab
;
2500 /* Setup for loop. */
2502 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2503 core_optab
->start
= optab
;
2508 if (optab
->name
== NULL
2509 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2511 /* different name --> ship out current template list;
2512 add to hash table; & begin anew. */
2513 core_optab
->end
= optab
;
2514 hash_err
= hash_insert (op_hash
,
2516 (void *) core_optab
);
2519 as_fatal (_("can't hash %s: %s"),
2523 if (optab
->name
== NULL
)
2525 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2526 core_optab
->start
= optab
;
2531 /* Initialize reg_hash hash table. */
2532 reg_hash
= hash_new ();
2534 const reg_entry
*regtab
;
2535 unsigned int regtab_size
= i386_regtab_size
;
2537 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2539 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2541 as_fatal (_("can't hash %s: %s"),
2547 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2552 for (c
= 0; c
< 256; c
++)
2557 mnemonic_chars
[c
] = c
;
2558 register_chars
[c
] = c
;
2559 operand_chars
[c
] = c
;
2561 else if (ISLOWER (c
))
2563 mnemonic_chars
[c
] = c
;
2564 register_chars
[c
] = c
;
2565 operand_chars
[c
] = c
;
2567 else if (ISUPPER (c
))
2569 mnemonic_chars
[c
] = TOLOWER (c
);
2570 register_chars
[c
] = mnemonic_chars
[c
];
2571 operand_chars
[c
] = c
;
2573 else if (c
== '{' || c
== '}')
2574 operand_chars
[c
] = c
;
2576 if (ISALPHA (c
) || ISDIGIT (c
))
2577 identifier_chars
[c
] = c
;
2580 identifier_chars
[c
] = c
;
2581 operand_chars
[c
] = c
;
2586 identifier_chars
['@'] = '@';
2589 identifier_chars
['?'] = '?';
2590 operand_chars
['?'] = '?';
2592 digit_chars
['-'] = '-';
2593 mnemonic_chars
['_'] = '_';
2594 mnemonic_chars
['-'] = '-';
2595 mnemonic_chars
['.'] = '.';
2596 identifier_chars
['_'] = '_';
2597 identifier_chars
['.'] = '.';
2599 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2600 operand_chars
[(unsigned char) *p
] = *p
;
2603 if (flag_code
== CODE_64BIT
)
2605 #if defined (OBJ_COFF) && defined (TE_PE)
2606 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2609 x86_dwarf2_return_column
= 16;
2611 x86_cie_data_alignment
= -8;
2615 x86_dwarf2_return_column
= 8;
2616 x86_cie_data_alignment
= -4;
2621 i386_print_statistics (FILE *file
)
2623 hash_print_statistics (file
, "i386 opcode", op_hash
);
2624 hash_print_statistics (file
, "i386 register", reg_hash
);
2629 /* Debugging routines for md_assemble. */
2630 static void pte (insn_template
*);
2631 static void pt (i386_operand_type
);
2632 static void pe (expressionS
*);
2633 static void ps (symbolS
*);
2636 pi (char *line
, i386_insn
*x
)
2640 fprintf (stdout
, "%s: template ", line
);
2642 fprintf (stdout
, " address: base %s index %s scale %x\n",
2643 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2644 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2645 x
->log2_scale_factor
);
2646 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2647 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2648 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2649 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2650 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2651 (x
->rex
& REX_W
) != 0,
2652 (x
->rex
& REX_R
) != 0,
2653 (x
->rex
& REX_X
) != 0,
2654 (x
->rex
& REX_B
) != 0);
2655 for (j
= 0; j
< x
->operands
; j
++)
2657 fprintf (stdout
, " #%d: ", j
+ 1);
2659 fprintf (stdout
, "\n");
2660 if (x
->types
[j
].bitfield
.reg8
2661 || x
->types
[j
].bitfield
.reg16
2662 || x
->types
[j
].bitfield
.reg32
2663 || x
->types
[j
].bitfield
.reg64
2664 || x
->types
[j
].bitfield
.regmmx
2665 || x
->types
[j
].bitfield
.regxmm
2666 || x
->types
[j
].bitfield
.regymm
2667 || x
->types
[j
].bitfield
.regzmm
2668 || x
->types
[j
].bitfield
.sreg2
2669 || x
->types
[j
].bitfield
.sreg3
2670 || x
->types
[j
].bitfield
.control
2671 || x
->types
[j
].bitfield
.debug
2672 || x
->types
[j
].bitfield
.test
)
2673 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2674 if (operand_type_check (x
->types
[j
], imm
))
2676 if (operand_type_check (x
->types
[j
], disp
))
2677 pe (x
->op
[j
].disps
);
2682 pte (insn_template
*t
)
2685 fprintf (stdout
, " %d operands ", t
->operands
);
2686 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2687 if (t
->extension_opcode
!= None
)
2688 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2689 if (t
->opcode_modifier
.d
)
2690 fprintf (stdout
, "D");
2691 if (t
->opcode_modifier
.w
)
2692 fprintf (stdout
, "W");
2693 fprintf (stdout
, "\n");
2694 for (j
= 0; j
< t
->operands
; j
++)
2696 fprintf (stdout
, " #%d type ", j
+ 1);
2697 pt (t
->operand_types
[j
]);
2698 fprintf (stdout
, "\n");
2705 fprintf (stdout
, " operation %d\n", e
->X_op
);
2706 fprintf (stdout
, " add_number %ld (%lx)\n",
2707 (long) e
->X_add_number
, (long) e
->X_add_number
);
2708 if (e
->X_add_symbol
)
2710 fprintf (stdout
, " add_symbol ");
2711 ps (e
->X_add_symbol
);
2712 fprintf (stdout
, "\n");
2716 fprintf (stdout
, " op_symbol ");
2717 ps (e
->X_op_symbol
);
2718 fprintf (stdout
, "\n");
2725 fprintf (stdout
, "%s type %s%s",
2727 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2728 segment_name (S_GET_SEGMENT (s
)));
2731 static struct type_name
2733 i386_operand_type mask
;
2736 const type_names
[] =
2738 { OPERAND_TYPE_REG8
, "r8" },
2739 { OPERAND_TYPE_REG16
, "r16" },
2740 { OPERAND_TYPE_REG32
, "r32" },
2741 { OPERAND_TYPE_REG64
, "r64" },
2742 { OPERAND_TYPE_IMM8
, "i8" },
2743 { OPERAND_TYPE_IMM8
, "i8s" },
2744 { OPERAND_TYPE_IMM16
, "i16" },
2745 { OPERAND_TYPE_IMM32
, "i32" },
2746 { OPERAND_TYPE_IMM32S
, "i32s" },
2747 { OPERAND_TYPE_IMM64
, "i64" },
2748 { OPERAND_TYPE_IMM1
, "i1" },
2749 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2750 { OPERAND_TYPE_DISP8
, "d8" },
2751 { OPERAND_TYPE_DISP16
, "d16" },
2752 { OPERAND_TYPE_DISP32
, "d32" },
2753 { OPERAND_TYPE_DISP32S
, "d32s" },
2754 { OPERAND_TYPE_DISP64
, "d64" },
2755 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2756 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2757 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2758 { OPERAND_TYPE_CONTROL
, "control reg" },
2759 { OPERAND_TYPE_TEST
, "test reg" },
2760 { OPERAND_TYPE_DEBUG
, "debug reg" },
2761 { OPERAND_TYPE_FLOATREG
, "FReg" },
2762 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2763 { OPERAND_TYPE_SREG2
, "SReg2" },
2764 { OPERAND_TYPE_SREG3
, "SReg3" },
2765 { OPERAND_TYPE_ACC
, "Acc" },
2766 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2767 { OPERAND_TYPE_REGMMX
, "rMMX" },
2768 { OPERAND_TYPE_REGXMM
, "rXMM" },
2769 { OPERAND_TYPE_REGYMM
, "rYMM" },
2770 { OPERAND_TYPE_REGZMM
, "rZMM" },
2771 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2772 { OPERAND_TYPE_ESSEG
, "es" },
2776 pt (i386_operand_type t
)
2779 i386_operand_type a
;
2781 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2783 a
= operand_type_and (t
, type_names
[j
].mask
);
2784 if (!operand_type_all_zero (&a
))
2785 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2790 #endif /* DEBUG386 */
2792 static bfd_reloc_code_real_type
2793 reloc (unsigned int size
,
2796 bfd_reloc_code_real_type other
)
2798 if (other
!= NO_RELOC
)
2800 reloc_howto_type
*rel
;
2805 case BFD_RELOC_X86_64_GOT32
:
2806 return BFD_RELOC_X86_64_GOT64
;
2808 case BFD_RELOC_X86_64_GOTPLT64
:
2809 return BFD_RELOC_X86_64_GOTPLT64
;
2811 case BFD_RELOC_X86_64_PLTOFF64
:
2812 return BFD_RELOC_X86_64_PLTOFF64
;
2814 case BFD_RELOC_X86_64_GOTPC32
:
2815 other
= BFD_RELOC_X86_64_GOTPC64
;
2817 case BFD_RELOC_X86_64_GOTPCREL
:
2818 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2820 case BFD_RELOC_X86_64_TPOFF32
:
2821 other
= BFD_RELOC_X86_64_TPOFF64
;
2823 case BFD_RELOC_X86_64_DTPOFF32
:
2824 other
= BFD_RELOC_X86_64_DTPOFF64
;
2830 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2831 if (other
== BFD_RELOC_SIZE32
)
2834 other
= BFD_RELOC_SIZE64
;
2837 as_bad (_("there are no pc-relative size relocations"));
2843 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2844 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2847 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2849 as_bad (_("unknown relocation (%u)"), other
);
2850 else if (size
!= bfd_get_reloc_size (rel
))
2851 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2852 bfd_get_reloc_size (rel
),
2854 else if (pcrel
&& !rel
->pc_relative
)
2855 as_bad (_("non-pc-relative relocation for pc-relative field"));
2856 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2858 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2860 as_bad (_("relocated field and relocation type differ in signedness"));
2869 as_bad (_("there are no unsigned pc-relative relocations"));
2872 case 1: return BFD_RELOC_8_PCREL
;
2873 case 2: return BFD_RELOC_16_PCREL
;
2874 case 4: return BFD_RELOC_32_PCREL
;
2875 case 8: return BFD_RELOC_64_PCREL
;
2877 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2884 case 4: return BFD_RELOC_X86_64_32S
;
2889 case 1: return BFD_RELOC_8
;
2890 case 2: return BFD_RELOC_16
;
2891 case 4: return BFD_RELOC_32
;
2892 case 8: return BFD_RELOC_64
;
2894 as_bad (_("cannot do %s %u byte relocation"),
2895 sign
> 0 ? "signed" : "unsigned", size
);
2901 /* Here we decide which fixups can be adjusted to make them relative to
2902 the beginning of the section instead of the symbol. Basically we need
2903 to make sure that the dynamic relocations are done correctly, so in
2904 some cases we force the original symbol to be used. */
2907 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2913 /* Don't adjust pc-relative references to merge sections in 64-bit
2915 if (use_rela_relocations
2916 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2920 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2921 and changed later by validate_fix. */
2922 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2923 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2926 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2927 for size relocations. */
2928 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2929 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2930 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2931 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2932 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2933 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
2934 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2935 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2936 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2937 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2938 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2939 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2940 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2941 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2942 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2943 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2944 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2945 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2946 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2947 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
2948 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
2949 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2950 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2951 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2952 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2953 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2954 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2955 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2956 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2957 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2958 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2959 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2960 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2967 intel_float_operand (const char *mnemonic
)
2969 /* Note that the value returned is meaningful only for opcodes with (memory)
2970 operands, hence the code here is free to improperly handle opcodes that
2971 have no operands (for better performance and smaller code). */
2973 if (mnemonic
[0] != 'f')
2974 return 0; /* non-math */
2976 switch (mnemonic
[1])
2978 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2979 the fs segment override prefix not currently handled because no
2980 call path can make opcodes without operands get here */
2982 return 2 /* integer op */;
2984 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2985 return 3; /* fldcw/fldenv */
2988 if (mnemonic
[2] != 'o' /* fnop */)
2989 return 3; /* non-waiting control op */
2992 if (mnemonic
[2] == 's')
2993 return 3; /* frstor/frstpm */
2996 if (mnemonic
[2] == 'a')
2997 return 3; /* fsave */
2998 if (mnemonic
[2] == 't')
3000 switch (mnemonic
[3])
3002 case 'c': /* fstcw */
3003 case 'd': /* fstdw */
3004 case 'e': /* fstenv */
3005 case 's': /* fsts[gw] */
3011 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3012 return 0; /* fxsave/fxrstor are not really math ops */
3019 /* Build the VEX prefix. */
3022 build_vex_prefix (const insn_template
*t
)
3024 unsigned int register_specifier
;
3025 unsigned int implied_prefix
;
3026 unsigned int vector_length
;
3028 /* Check register specifier. */
3029 if (i
.vex
.register_specifier
)
3031 register_specifier
=
3032 ~register_number (i
.vex
.register_specifier
) & 0xf;
3033 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3036 register_specifier
= 0xf;
3038 /* Use 2-byte VEX prefix by swappping destination and source
3041 && i
.operands
== i
.reg_operands
3042 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3043 && i
.tm
.opcode_modifier
.s
3046 unsigned int xchg
= i
.operands
- 1;
3047 union i386_op temp_op
;
3048 i386_operand_type temp_type
;
3050 temp_type
= i
.types
[xchg
];
3051 i
.types
[xchg
] = i
.types
[0];
3052 i
.types
[0] = temp_type
;
3053 temp_op
= i
.op
[xchg
];
3054 i
.op
[xchg
] = i
.op
[0];
3057 gas_assert (i
.rm
.mode
== 3);
3061 i
.rm
.regmem
= i
.rm
.reg
;
3064 /* Use the next insn. */
3068 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3069 vector_length
= avxscalar
;
3071 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3073 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3078 case DATA_PREFIX_OPCODE
:
3081 case REPE_PREFIX_OPCODE
:
3084 case REPNE_PREFIX_OPCODE
:
3091 /* Use 2-byte VEX prefix if possible. */
3092 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3093 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3094 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3096 /* 2-byte VEX prefix. */
3100 i
.vex
.bytes
[0] = 0xc5;
3102 /* Check the REX.R bit. */
3103 r
= (i
.rex
& REX_R
) ? 0 : 1;
3104 i
.vex
.bytes
[1] = (r
<< 7
3105 | register_specifier
<< 3
3106 | vector_length
<< 2
3111 /* 3-byte VEX prefix. */
3116 switch (i
.tm
.opcode_modifier
.vexopcode
)
3120 i
.vex
.bytes
[0] = 0xc4;
3124 i
.vex
.bytes
[0] = 0xc4;
3128 i
.vex
.bytes
[0] = 0xc4;
3132 i
.vex
.bytes
[0] = 0x8f;
3136 i
.vex
.bytes
[0] = 0x8f;
3140 i
.vex
.bytes
[0] = 0x8f;
3146 /* The high 3 bits of the second VEX byte are 1's compliment
3147 of RXB bits from REX. */
3148 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3150 /* Check the REX.W bit. */
3151 w
= (i
.rex
& REX_W
) ? 1 : 0;
3152 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3155 i
.vex
.bytes
[2] = (w
<< 7
3156 | register_specifier
<< 3
3157 | vector_length
<< 2
3162 /* Build the EVEX prefix. */
3165 build_evex_prefix (void)
3167 unsigned int register_specifier
;
3168 unsigned int implied_prefix
;
3170 rex_byte vrex_used
= 0;
3172 /* Check register specifier. */
3173 if (i
.vex
.register_specifier
)
3175 gas_assert ((i
.vrex
& REX_X
) == 0);
3177 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3178 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3179 register_specifier
+= 8;
3180 /* The upper 16 registers are encoded in the fourth byte of the
3182 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3183 i
.vex
.bytes
[3] = 0x8;
3184 register_specifier
= ~register_specifier
& 0xf;
3188 register_specifier
= 0xf;
3190 /* Encode upper 16 vector index register in the fourth byte of
3192 if (!(i
.vrex
& REX_X
))
3193 i
.vex
.bytes
[3] = 0x8;
3198 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3203 case DATA_PREFIX_OPCODE
:
3206 case REPE_PREFIX_OPCODE
:
3209 case REPNE_PREFIX_OPCODE
:
3216 /* 4 byte EVEX prefix. */
3218 i
.vex
.bytes
[0] = 0x62;
3221 switch (i
.tm
.opcode_modifier
.vexopcode
)
3237 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3239 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3241 /* The fifth bit of the second EVEX byte is 1's compliment of the
3242 REX_R bit in VREX. */
3243 if (!(i
.vrex
& REX_R
))
3244 i
.vex
.bytes
[1] |= 0x10;
3248 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3250 /* When all operands are registers, the REX_X bit in REX is not
3251 used. We reuse it to encode the upper 16 registers, which is
3252 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3253 as 1's compliment. */
3254 if ((i
.vrex
& REX_B
))
3257 i
.vex
.bytes
[1] &= ~0x40;
3261 /* EVEX instructions shouldn't need the REX prefix. */
3262 i
.vrex
&= ~vrex_used
;
3263 gas_assert (i
.vrex
== 0);
3265 /* Check the REX.W bit. */
3266 w
= (i
.rex
& REX_W
) ? 1 : 0;
3267 if (i
.tm
.opcode_modifier
.vexw
)
3269 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3272 /* If w is not set it means we are dealing with WIG instruction. */
3275 if (evexwig
== evexw1
)
3279 /* Encode the U bit. */
3280 implied_prefix
|= 0x4;
3282 /* The third byte of the EVEX prefix. */
3283 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3285 /* The fourth byte of the EVEX prefix. */
3286 /* The zeroing-masking bit. */
3287 if (i
.mask
&& i
.mask
->zeroing
)
3288 i
.vex
.bytes
[3] |= 0x80;
3290 /* Don't always set the broadcast bit if there is no RC. */
3293 /* Encode the vector length. */
3294 unsigned int vec_length
;
3296 switch (i
.tm
.opcode_modifier
.evex
)
3298 case EVEXLIG
: /* LL' is ignored */
3299 vec_length
= evexlig
<< 5;
3302 vec_length
= 0 << 5;
3305 vec_length
= 1 << 5;
3308 vec_length
= 2 << 5;
3314 i
.vex
.bytes
[3] |= vec_length
;
3315 /* Encode the broadcast bit. */
3317 i
.vex
.bytes
[3] |= 0x10;
3321 if (i
.rounding
->type
!= saeonly
)
3322 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3324 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3327 if (i
.mask
&& i
.mask
->mask
)
3328 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3332 process_immext (void)
3336 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3339 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3340 with an opcode suffix which is coded in the same place as an
3341 8-bit immediate field would be.
3342 Here we check those operands and remove them afterwards. */
3345 for (x
= 0; x
< i
.operands
; x
++)
3346 if (register_number (i
.op
[x
].regs
) != x
)
3347 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3348 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3354 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3356 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3357 suffix which is coded in the same place as an 8-bit immediate
3359 Here we check those operands and remove them afterwards. */
3362 if (i
.operands
!= 3)
3365 for (x
= 0; x
< 2; x
++)
3366 if (register_number (i
.op
[x
].regs
) != x
)
3367 goto bad_register_operand
;
3369 /* Check for third operand for mwaitx/monitorx insn. */
3370 if (register_number (i
.op
[x
].regs
)
3371 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3373 bad_register_operand
:
3374 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3375 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3382 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3383 which is coded in the same place as an 8-bit immediate field
3384 would be. Here we fake an 8-bit immediate operand from the
3385 opcode suffix stored in tm.extension_opcode.
3387 AVX instructions also use this encoding, for some of
3388 3 argument instructions. */
3390 gas_assert (i
.imm_operands
<= 1
3392 || ((i
.tm
.opcode_modifier
.vex
3393 || i
.tm
.opcode_modifier
.evex
)
3394 && i
.operands
<= 4)));
3396 exp
= &im_expressions
[i
.imm_operands
++];
3397 i
.op
[i
.operands
].imms
= exp
;
3398 i
.types
[i
.operands
] = imm8
;
3400 exp
->X_op
= O_constant
;
3401 exp
->X_add_number
= i
.tm
.extension_opcode
;
3402 i
.tm
.extension_opcode
= None
;
3409 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3414 as_bad (_("invalid instruction `%s' after `%s'"),
3415 i
.tm
.name
, i
.hle_prefix
);
3418 if (i
.prefix
[LOCK_PREFIX
])
3420 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3424 case HLEPrefixRelease
:
3425 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3427 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3431 if (i
.mem_operands
== 0
3432 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3434 as_bad (_("memory destination needed for instruction `%s'"
3435 " after `xrelease'"), i
.tm
.name
);
3442 /* This is the guts of the machine-dependent assembler. LINE points to a
3443 machine dependent instruction. This function is supposed to emit
3444 the frags/bytes it assembles to. */
3447 md_assemble (char *line
)
3450 char mnemonic
[MAX_MNEM_SIZE
];
3451 const insn_template
*t
;
3453 /* Initialize globals. */
3454 memset (&i
, '\0', sizeof (i
));
3455 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3456 i
.reloc
[j
] = NO_RELOC
;
3457 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3458 memset (im_expressions
, '\0', sizeof (im_expressions
));
3459 save_stack_p
= save_stack
;
3461 /* First parse an instruction mnemonic & call i386_operand for the operands.
3462 We assume that the scrubber has arranged it so that line[0] is the valid
3463 start of a (possibly prefixed) mnemonic. */
3465 line
= parse_insn (line
, mnemonic
);
3469 line
= parse_operands (line
, mnemonic
);
3474 /* Now we've parsed the mnemonic into a set of templates, and have the
3475 operands at hand. */
3477 /* All intel opcodes have reversed operands except for "bound" and
3478 "enter". We also don't reverse intersegment "jmp" and "call"
3479 instructions with 2 immediate operands so that the immediate segment
3480 precedes the offset, as it does when in AT&T mode. */
3483 && (strcmp (mnemonic
, "bound") != 0)
3484 && (strcmp (mnemonic
, "invlpga") != 0)
3485 && !(operand_type_check (i
.types
[0], imm
)
3486 && operand_type_check (i
.types
[1], imm
)))
3489 /* The order of the immediates should be reversed
3490 for 2 immediates extrq and insertq instructions */
3491 if (i
.imm_operands
== 2
3492 && (strcmp (mnemonic
, "extrq") == 0
3493 || strcmp (mnemonic
, "insertq") == 0))
3494 swap_2_operands (0, 1);
3499 /* Don't optimize displacement for movabs since it only takes 64bit
3502 && i
.disp_encoding
!= disp_encoding_32bit
3503 && (flag_code
!= CODE_64BIT
3504 || strcmp (mnemonic
, "movabs") != 0))
3507 /* Next, we find a template that matches the given insn,
3508 making sure the overlap of the given operands types is consistent
3509 with the template operand types. */
3511 if (!(t
= match_template ()))
3514 if (sse_check
!= check_none
3515 && !i
.tm
.opcode_modifier
.noavx
3516 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3517 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3518 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3519 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3520 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3521 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3523 (sse_check
== check_warning
3525 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3528 /* Zap movzx and movsx suffix. The suffix has been set from
3529 "word ptr" or "byte ptr" on the source operand in Intel syntax
3530 or extracted from mnemonic in AT&T syntax. But we'll use
3531 the destination register to choose the suffix for encoding. */
3532 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3534 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3535 there is no suffix, the default will be byte extension. */
3536 if (i
.reg_operands
!= 2
3539 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3544 if (i
.tm
.opcode_modifier
.fwait
)
3545 if (!add_prefix (FWAIT_OPCODE
))
3548 /* Check if REP prefix is OK. */
3549 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3551 as_bad (_("invalid instruction `%s' after `%s'"),
3552 i
.tm
.name
, i
.rep_prefix
);
3556 /* Check for lock without a lockable instruction. Destination operand
3557 must be memory unless it is xchg (0x86). */
3558 if (i
.prefix
[LOCK_PREFIX
]
3559 && (!i
.tm
.opcode_modifier
.islockable
3560 || i
.mem_operands
== 0
3561 || (i
.tm
.base_opcode
!= 0x86
3562 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3564 as_bad (_("expecting lockable instruction after `lock'"));
3568 /* Check if HLE prefix is OK. */
3569 if (i
.hle_prefix
&& !check_hle ())
3572 /* Check BND prefix. */
3573 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3574 as_bad (_("expecting valid branch instruction after `bnd'"));
3576 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3577 && flag_code
== CODE_64BIT
3578 && i
.prefix
[ADDR_PREFIX
])
3579 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3581 /* Insert BND prefix. */
3583 && i
.tm
.opcode_modifier
.bndprefixok
3584 && !i
.prefix
[BND_PREFIX
])
3585 add_prefix (BND_PREFIX_OPCODE
);
3587 /* Check string instruction segment overrides. */
3588 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3590 if (!check_string ())
3592 i
.disp_operands
= 0;
3595 if (!process_suffix ())
3598 /* Update operand types. */
3599 for (j
= 0; j
< i
.operands
; j
++)
3600 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3602 /* Make still unresolved immediate matches conform to size of immediate
3603 given in i.suffix. */
3604 if (!finalize_imm ())
3607 if (i
.types
[0].bitfield
.imm1
)
3608 i
.imm_operands
= 0; /* kludge for shift insns. */
3610 /* We only need to check those implicit registers for instructions
3611 with 3 operands or less. */
3612 if (i
.operands
<= 3)
3613 for (j
= 0; j
< i
.operands
; j
++)
3614 if (i
.types
[j
].bitfield
.inoutportreg
3615 || i
.types
[j
].bitfield
.shiftcount
3616 || i
.types
[j
].bitfield
.acc
3617 || i
.types
[j
].bitfield
.floatacc
)
3620 /* ImmExt should be processed after SSE2AVX. */
3621 if (!i
.tm
.opcode_modifier
.sse2avx
3622 && i
.tm
.opcode_modifier
.immext
)
3625 /* For insns with operands there are more diddles to do to the opcode. */
3628 if (!process_operands ())
3631 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3633 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3634 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3637 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3639 if (flag_code
== CODE_16BIT
)
3641 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3646 if (i
.tm
.opcode_modifier
.vex
)
3647 build_vex_prefix (t
);
3649 build_evex_prefix ();
3652 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3653 instructions may define INT_OPCODE as well, so avoid this corner
3654 case for those instructions that use MODRM. */
3655 if (i
.tm
.base_opcode
== INT_OPCODE
3656 && !i
.tm
.opcode_modifier
.modrm
3657 && i
.op
[0].imms
->X_add_number
== 3)
3659 i
.tm
.base_opcode
= INT3_OPCODE
;
3663 if ((i
.tm
.opcode_modifier
.jump
3664 || i
.tm
.opcode_modifier
.jumpbyte
3665 || i
.tm
.opcode_modifier
.jumpdword
)
3666 && i
.op
[0].disps
->X_op
== O_constant
)
3668 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3669 the absolute address given by the constant. Since ix86 jumps and
3670 calls are pc relative, we need to generate a reloc. */
3671 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3672 i
.op
[0].disps
->X_op
= O_symbol
;
3675 if (i
.tm
.opcode_modifier
.rex64
)
3678 /* For 8 bit registers we need an empty rex prefix. Also if the
3679 instruction already has a prefix, we need to convert old
3680 registers to new ones. */
3682 if ((i
.types
[0].bitfield
.reg8
3683 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3684 || (i
.types
[1].bitfield
.reg8
3685 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3686 || ((i
.types
[0].bitfield
.reg8
3687 || i
.types
[1].bitfield
.reg8
)
3692 i
.rex
|= REX_OPCODE
;
3693 for (x
= 0; x
< 2; x
++)
3695 /* Look for 8 bit operand that uses old registers. */
3696 if (i
.types
[x
].bitfield
.reg8
3697 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3699 /* In case it is "hi" register, give up. */
3700 if (i
.op
[x
].regs
->reg_num
> 3)
3701 as_bad (_("can't encode register '%s%s' in an "
3702 "instruction requiring REX prefix."),
3703 register_prefix
, i
.op
[x
].regs
->reg_name
);
3705 /* Otherwise it is equivalent to the extended register.
3706 Since the encoding doesn't change this is merely
3707 cosmetic cleanup for debug output. */
3709 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3715 add_prefix (REX_OPCODE
| i
.rex
);
3717 /* We are ready to output the insn. */
3722 parse_insn (char *line
, char *mnemonic
)
3725 char *token_start
= l
;
3728 const insn_template
*t
;
3734 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3739 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3741 as_bad (_("no such instruction: `%s'"), token_start
);
3746 if (!is_space_char (*l
)
3747 && *l
!= END_OF_INSN
3749 || (*l
!= PREFIX_SEPARATOR
3752 as_bad (_("invalid character %s in mnemonic"),
3753 output_invalid (*l
));
3756 if (token_start
== l
)
3758 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3759 as_bad (_("expecting prefix; got nothing"));
3761 as_bad (_("expecting mnemonic; got nothing"));
3765 /* Look up instruction (or prefix) via hash table. */
3766 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3768 if (*l
!= END_OF_INSN
3769 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3770 && current_templates
3771 && current_templates
->start
->opcode_modifier
.isprefix
)
3773 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3775 as_bad ((flag_code
!= CODE_64BIT
3776 ? _("`%s' is only supported in 64-bit mode")
3777 : _("`%s' is not supported in 64-bit mode")),
3778 current_templates
->start
->name
);
3781 /* If we are in 16-bit mode, do not allow addr16 or data16.
3782 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3783 if ((current_templates
->start
->opcode_modifier
.size16
3784 || current_templates
->start
->opcode_modifier
.size32
)
3785 && flag_code
!= CODE_64BIT
3786 && (current_templates
->start
->opcode_modifier
.size32
3787 ^ (flag_code
== CODE_16BIT
)))
3789 as_bad (_("redundant %s prefix"),
3790 current_templates
->start
->name
);
3793 /* Add prefix, checking for repeated prefixes. */
3794 switch (add_prefix (current_templates
->start
->base_opcode
))
3799 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3800 i
.hle_prefix
= current_templates
->start
->name
;
3801 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3802 i
.bnd_prefix
= current_templates
->start
->name
;
3804 i
.rep_prefix
= current_templates
->start
->name
;
3809 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3816 if (!current_templates
)
3818 /* Check if we should swap operand or force 32bit displacement in
3820 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3822 else if (mnem_p
- 3 == dot_p
3825 i
.disp_encoding
= disp_encoding_8bit
;
3826 else if (mnem_p
- 4 == dot_p
3830 i
.disp_encoding
= disp_encoding_32bit
;
3835 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3838 if (!current_templates
)
3841 /* See if we can get a match by trimming off a suffix. */
3844 case WORD_MNEM_SUFFIX
:
3845 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3846 i
.suffix
= SHORT_MNEM_SUFFIX
;
3848 case BYTE_MNEM_SUFFIX
:
3849 case QWORD_MNEM_SUFFIX
:
3850 i
.suffix
= mnem_p
[-1];
3852 current_templates
= (const templates
*) hash_find (op_hash
,
3855 case SHORT_MNEM_SUFFIX
:
3856 case LONG_MNEM_SUFFIX
:
3859 i
.suffix
= mnem_p
[-1];
3861 current_templates
= (const templates
*) hash_find (op_hash
,
3870 if (intel_float_operand (mnemonic
) == 1)
3871 i
.suffix
= SHORT_MNEM_SUFFIX
;
3873 i
.suffix
= LONG_MNEM_SUFFIX
;
3875 current_templates
= (const templates
*) hash_find (op_hash
,
3880 if (!current_templates
)
3882 as_bad (_("no such instruction: `%s'"), token_start
);
3887 if (current_templates
->start
->opcode_modifier
.jump
3888 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3890 /* Check for a branch hint. We allow ",pt" and ",pn" for
3891 predict taken and predict not taken respectively.
3892 I'm not sure that branch hints actually do anything on loop
3893 and jcxz insns (JumpByte) for current Pentium4 chips. They
3894 may work in the future and it doesn't hurt to accept them
3896 if (l
[0] == ',' && l
[1] == 'p')
3900 if (!add_prefix (DS_PREFIX_OPCODE
))
3904 else if (l
[2] == 'n')
3906 if (!add_prefix (CS_PREFIX_OPCODE
))
3912 /* Any other comma loses. */
3915 as_bad (_("invalid character %s in mnemonic"),
3916 output_invalid (*l
));
3920 /* Check if instruction is supported on specified architecture. */
3922 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3924 supported
|= cpu_flags_match (t
);
3925 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3929 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3931 as_bad (flag_code
== CODE_64BIT
3932 ? _("`%s' is not supported in 64-bit mode")
3933 : _("`%s' is only supported in 64-bit mode"),
3934 current_templates
->start
->name
);
3937 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3939 as_bad (_("`%s' is not supported on `%s%s'"),
3940 current_templates
->start
->name
,
3941 cpu_arch_name
? cpu_arch_name
: default_arch
,
3942 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3947 if (!cpu_arch_flags
.bitfield
.cpui386
3948 && (flag_code
!= CODE_16BIT
))
3950 as_warn (_("use .code16 to ensure correct addressing mode"));
3957 parse_operands (char *l
, const char *mnemonic
)
3961 /* 1 if operand is pending after ','. */
3962 unsigned int expecting_operand
= 0;
3964 /* Non-zero if operand parens not balanced. */
3965 unsigned int paren_not_balanced
;
3967 while (*l
!= END_OF_INSN
)
3969 /* Skip optional white space before operand. */
3970 if (is_space_char (*l
))
3972 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
3974 as_bad (_("invalid character %s before operand %d"),
3975 output_invalid (*l
),
3979 token_start
= l
; /* After white space. */
3980 paren_not_balanced
= 0;
3981 while (paren_not_balanced
|| *l
!= ',')
3983 if (*l
== END_OF_INSN
)
3985 if (paren_not_balanced
)
3988 as_bad (_("unbalanced parenthesis in operand %d."),
3991 as_bad (_("unbalanced brackets in operand %d."),
3996 break; /* we are done */
3998 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4000 as_bad (_("invalid character %s in operand %d"),
4001 output_invalid (*l
),
4008 ++paren_not_balanced
;
4010 --paren_not_balanced
;
4015 ++paren_not_balanced
;
4017 --paren_not_balanced
;
4021 if (l
!= token_start
)
4022 { /* Yes, we've read in another operand. */
4023 unsigned int operand_ok
;
4024 this_operand
= i
.operands
++;
4025 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4026 if (i
.operands
> MAX_OPERANDS
)
4028 as_bad (_("spurious operands; (%d operands/instruction max)"),
4032 /* Now parse operand adding info to 'i' as we go along. */
4033 END_STRING_AND_SAVE (l
);
4037 i386_intel_operand (token_start
,
4038 intel_float_operand (mnemonic
));
4040 operand_ok
= i386_att_operand (token_start
);
4042 RESTORE_END_STRING (l
);
4048 if (expecting_operand
)
4050 expecting_operand_after_comma
:
4051 as_bad (_("expecting operand after ','; got nothing"));
4056 as_bad (_("expecting operand before ','; got nothing"));
4061 /* Now *l must be either ',' or END_OF_INSN. */
4064 if (*++l
== END_OF_INSN
)
4066 /* Just skip it, if it's \n complain. */
4067 goto expecting_operand_after_comma
;
4069 expecting_operand
= 1;
4076 swap_2_operands (int xchg1
, int xchg2
)
4078 union i386_op temp_op
;
4079 i386_operand_type temp_type
;
4080 enum bfd_reloc_code_real temp_reloc
;
4082 temp_type
= i
.types
[xchg2
];
4083 i
.types
[xchg2
] = i
.types
[xchg1
];
4084 i
.types
[xchg1
] = temp_type
;
4085 temp_op
= i
.op
[xchg2
];
4086 i
.op
[xchg2
] = i
.op
[xchg1
];
4087 i
.op
[xchg1
] = temp_op
;
4088 temp_reloc
= i
.reloc
[xchg2
];
4089 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4090 i
.reloc
[xchg1
] = temp_reloc
;
4094 if (i
.mask
->operand
== xchg1
)
4095 i
.mask
->operand
= xchg2
;
4096 else if (i
.mask
->operand
== xchg2
)
4097 i
.mask
->operand
= xchg1
;
4101 if (i
.broadcast
->operand
== xchg1
)
4102 i
.broadcast
->operand
= xchg2
;
4103 else if (i
.broadcast
->operand
== xchg2
)
4104 i
.broadcast
->operand
= xchg1
;
4108 if (i
.rounding
->operand
== xchg1
)
4109 i
.rounding
->operand
= xchg2
;
4110 else if (i
.rounding
->operand
== xchg2
)
4111 i
.rounding
->operand
= xchg1
;
4116 swap_operands (void)
4122 swap_2_operands (1, i
.operands
- 2);
4125 swap_2_operands (0, i
.operands
- 1);
4131 if (i
.mem_operands
== 2)
4133 const seg_entry
*temp_seg
;
4134 temp_seg
= i
.seg
[0];
4135 i
.seg
[0] = i
.seg
[1];
4136 i
.seg
[1] = temp_seg
;
4140 /* Try to ensure constant immediates are represented in the smallest
4145 char guess_suffix
= 0;
4149 guess_suffix
= i
.suffix
;
4150 else if (i
.reg_operands
)
4152 /* Figure out a suffix from the last register operand specified.
4153 We can't do this properly yet, ie. excluding InOutPortReg,
4154 but the following works for instructions with immediates.
4155 In any case, we can't set i.suffix yet. */
4156 for (op
= i
.operands
; --op
>= 0;)
4157 if (i
.types
[op
].bitfield
.reg8
)
4159 guess_suffix
= BYTE_MNEM_SUFFIX
;
4162 else if (i
.types
[op
].bitfield
.reg16
)
4164 guess_suffix
= WORD_MNEM_SUFFIX
;
4167 else if (i
.types
[op
].bitfield
.reg32
)
4169 guess_suffix
= LONG_MNEM_SUFFIX
;
4172 else if (i
.types
[op
].bitfield
.reg64
)
4174 guess_suffix
= QWORD_MNEM_SUFFIX
;
4178 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4179 guess_suffix
= WORD_MNEM_SUFFIX
;
4181 for (op
= i
.operands
; --op
>= 0;)
4182 if (operand_type_check (i
.types
[op
], imm
))
4184 switch (i
.op
[op
].imms
->X_op
)
4187 /* If a suffix is given, this operand may be shortened. */
4188 switch (guess_suffix
)
4190 case LONG_MNEM_SUFFIX
:
4191 i
.types
[op
].bitfield
.imm32
= 1;
4192 i
.types
[op
].bitfield
.imm64
= 1;
4194 case WORD_MNEM_SUFFIX
:
4195 i
.types
[op
].bitfield
.imm16
= 1;
4196 i
.types
[op
].bitfield
.imm32
= 1;
4197 i
.types
[op
].bitfield
.imm32s
= 1;
4198 i
.types
[op
].bitfield
.imm64
= 1;
4200 case BYTE_MNEM_SUFFIX
:
4201 i
.types
[op
].bitfield
.imm8
= 1;
4202 i
.types
[op
].bitfield
.imm8s
= 1;
4203 i
.types
[op
].bitfield
.imm16
= 1;
4204 i
.types
[op
].bitfield
.imm32
= 1;
4205 i
.types
[op
].bitfield
.imm32s
= 1;
4206 i
.types
[op
].bitfield
.imm64
= 1;
4210 /* If this operand is at most 16 bits, convert it
4211 to a signed 16 bit number before trying to see
4212 whether it will fit in an even smaller size.
4213 This allows a 16-bit operand such as $0xffe0 to
4214 be recognised as within Imm8S range. */
4215 if ((i
.types
[op
].bitfield
.imm16
)
4216 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4218 i
.op
[op
].imms
->X_add_number
=
4219 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4222 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4223 if ((i
.types
[op
].bitfield
.imm32
)
4224 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4227 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4228 ^ ((offsetT
) 1 << 31))
4229 - ((offsetT
) 1 << 31));
4233 = operand_type_or (i
.types
[op
],
4234 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4236 /* We must avoid matching of Imm32 templates when 64bit
4237 only immediate is available. */
4238 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4239 i
.types
[op
].bitfield
.imm32
= 0;
4246 /* Symbols and expressions. */
4248 /* Convert symbolic operand to proper sizes for matching, but don't
4249 prevent matching a set of insns that only supports sizes other
4250 than those matching the insn suffix. */
4252 i386_operand_type mask
, allowed
;
4253 const insn_template
*t
;
4255 operand_type_set (&mask
, 0);
4256 operand_type_set (&allowed
, 0);
4258 for (t
= current_templates
->start
;
4259 t
< current_templates
->end
;
4261 allowed
= operand_type_or (allowed
,
4262 t
->operand_types
[op
]);
4263 switch (guess_suffix
)
4265 case QWORD_MNEM_SUFFIX
:
4266 mask
.bitfield
.imm64
= 1;
4267 mask
.bitfield
.imm32s
= 1;
4269 case LONG_MNEM_SUFFIX
:
4270 mask
.bitfield
.imm32
= 1;
4272 case WORD_MNEM_SUFFIX
:
4273 mask
.bitfield
.imm16
= 1;
4275 case BYTE_MNEM_SUFFIX
:
4276 mask
.bitfield
.imm8
= 1;
4281 allowed
= operand_type_and (mask
, allowed
);
4282 if (!operand_type_all_zero (&allowed
))
4283 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4290 /* Try to use the smallest displacement type too. */
4292 optimize_disp (void)
4296 for (op
= i
.operands
; --op
>= 0;)
4297 if (operand_type_check (i
.types
[op
], disp
))
4299 if (i
.op
[op
].disps
->X_op
== O_constant
)
4301 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4303 if (i
.types
[op
].bitfield
.disp16
4304 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4306 /* If this operand is at most 16 bits, convert
4307 to a signed 16 bit number and don't use 64bit
4309 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4310 i
.types
[op
].bitfield
.disp64
= 0;
4313 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4314 if (i
.types
[op
].bitfield
.disp32
4315 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4317 /* If this operand is at most 32 bits, convert
4318 to a signed 32 bit number and don't use 64bit
4320 op_disp
&= (((offsetT
) 2 << 31) - 1);
4321 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4322 i
.types
[op
].bitfield
.disp64
= 0;
4325 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4327 i
.types
[op
].bitfield
.disp8
= 0;
4328 i
.types
[op
].bitfield
.disp16
= 0;
4329 i
.types
[op
].bitfield
.disp32
= 0;
4330 i
.types
[op
].bitfield
.disp32s
= 0;
4331 i
.types
[op
].bitfield
.disp64
= 0;
4335 else if (flag_code
== CODE_64BIT
)
4337 if (fits_in_signed_long (op_disp
))
4339 i
.types
[op
].bitfield
.disp64
= 0;
4340 i
.types
[op
].bitfield
.disp32s
= 1;
4342 if (i
.prefix
[ADDR_PREFIX
]
4343 && fits_in_unsigned_long (op_disp
))
4344 i
.types
[op
].bitfield
.disp32
= 1;
4346 if ((i
.types
[op
].bitfield
.disp32
4347 || i
.types
[op
].bitfield
.disp32s
4348 || i
.types
[op
].bitfield
.disp16
)
4349 && fits_in_signed_byte (op_disp
))
4350 i
.types
[op
].bitfield
.disp8
= 1;
4352 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4353 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4355 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4356 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4357 i
.types
[op
].bitfield
.disp8
= 0;
4358 i
.types
[op
].bitfield
.disp16
= 0;
4359 i
.types
[op
].bitfield
.disp32
= 0;
4360 i
.types
[op
].bitfield
.disp32s
= 0;
4361 i
.types
[op
].bitfield
.disp64
= 0;
4364 /* We only support 64bit displacement on constants. */
4365 i
.types
[op
].bitfield
.disp64
= 0;
4369 /* Check if operands are valid for the instruction. */
4372 check_VecOperands (const insn_template
*t
)
4376 /* Without VSIB byte, we can't have a vector register for index. */
4377 if (!t
->opcode_modifier
.vecsib
4379 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4380 || i
.index_reg
->reg_type
.bitfield
.regymm
4381 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4383 i
.error
= unsupported_vector_index_register
;
4387 /* Check if default mask is allowed. */
4388 if (t
->opcode_modifier
.nodefmask
4389 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4391 i
.error
= no_default_mask
;
4395 /* For VSIB byte, we need a vector register for index, and all vector
4396 registers must be distinct. */
4397 if (t
->opcode_modifier
.vecsib
)
4400 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4401 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4402 || (t
->opcode_modifier
.vecsib
== VecSIB256
4403 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4404 || (t
->opcode_modifier
.vecsib
== VecSIB512
4405 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4407 i
.error
= invalid_vsib_address
;
4411 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4412 if (i
.reg_operands
== 2 && !i
.mask
)
4414 gas_assert (i
.types
[0].bitfield
.regxmm
4415 || i
.types
[0].bitfield
.regymm
);
4416 gas_assert (i
.types
[2].bitfield
.regxmm
4417 || i
.types
[2].bitfield
.regymm
);
4418 if (operand_check
== check_none
)
4420 if (register_number (i
.op
[0].regs
)
4421 != register_number (i
.index_reg
)
4422 && register_number (i
.op
[2].regs
)
4423 != register_number (i
.index_reg
)
4424 && register_number (i
.op
[0].regs
)
4425 != register_number (i
.op
[2].regs
))
4427 if (operand_check
== check_error
)
4429 i
.error
= invalid_vector_register_set
;
4432 as_warn (_("mask, index, and destination registers should be distinct"));
4434 else if (i
.reg_operands
== 1 && i
.mask
)
4436 if ((i
.types
[1].bitfield
.regymm
4437 || i
.types
[1].bitfield
.regzmm
)
4438 && (register_number (i
.op
[1].regs
)
4439 == register_number (i
.index_reg
)))
4441 if (operand_check
== check_error
)
4443 i
.error
= invalid_vector_register_set
;
4446 if (operand_check
!= check_none
)
4447 as_warn (_("index and destination registers should be distinct"));
4452 /* Check if broadcast is supported by the instruction and is applied
4453 to the memory operand. */
4456 int broadcasted_opnd_size
;
4458 /* Check if specified broadcast is supported in this instruction,
4459 and it's applied to memory operand of DWORD or QWORD type,
4460 depending on VecESize. */
4461 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4462 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4463 || (t
->opcode_modifier
.vecesize
== 0
4464 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4465 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4466 || (t
->opcode_modifier
.vecesize
== 1
4467 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4468 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4471 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4472 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4473 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4474 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4475 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4476 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4477 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4478 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4479 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4483 if ((broadcasted_opnd_size
== 256
4484 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4485 || (broadcasted_opnd_size
== 512
4486 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4489 i
.error
= unsupported_broadcast
;
4493 /* If broadcast is supported in this instruction, we need to check if
4494 operand of one-element size isn't specified without broadcast. */
4495 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4497 /* Find memory operand. */
4498 for (op
= 0; op
< i
.operands
; op
++)
4499 if (operand_type_check (i
.types
[op
], anymem
))
4501 gas_assert (op
< i
.operands
);
4502 /* Check size of the memory operand. */
4503 if ((t
->opcode_modifier
.vecesize
== 0
4504 && i
.types
[op
].bitfield
.dword
)
4505 || (t
->opcode_modifier
.vecesize
== 1
4506 && i
.types
[op
].bitfield
.qword
))
4508 i
.error
= broadcast_needed
;
4513 /* Check if requested masking is supported. */
4515 && (!t
->opcode_modifier
.masking
4517 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4519 i
.error
= unsupported_masking
;
4523 /* Check if masking is applied to dest operand. */
4524 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4526 i
.error
= mask_not_on_destination
;
4533 if ((i
.rounding
->type
!= saeonly
4534 && !t
->opcode_modifier
.staticrounding
)
4535 || (i
.rounding
->type
== saeonly
4536 && (t
->opcode_modifier
.staticrounding
4537 || !t
->opcode_modifier
.sae
)))
4539 i
.error
= unsupported_rc_sae
;
4542 /* If the instruction has several immediate operands and one of
4543 them is rounding, the rounding operand should be the last
4544 immediate operand. */
4545 if (i
.imm_operands
> 1
4546 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4548 i
.error
= rc_sae_operand_not_last_imm
;
4553 /* Check vector Disp8 operand. */
4554 if (t
->opcode_modifier
.disp8memshift
)
4557 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4559 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4561 for (op
= 0; op
< i
.operands
; op
++)
4562 if (operand_type_check (i
.types
[op
], disp
)
4563 && i
.op
[op
].disps
->X_op
== O_constant
)
4565 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4566 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4567 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4570 i
.types
[op
].bitfield
.vec_disp8
= 1;
4573 /* Vector insn can only have Vec_Disp8/Disp32 in
4574 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4576 i
.types
[op
].bitfield
.disp8
= 0;
4577 if (flag_code
!= CODE_16BIT
)
4578 i
.types
[op
].bitfield
.disp16
= 0;
4581 else if (flag_code
!= CODE_16BIT
)
4583 /* One form of this instruction supports vector Disp8.
4584 Try vector Disp8 if we need to use Disp32. */
4585 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4587 i
.error
= try_vector_disp8
;
4599 /* Check if operands are valid for the instruction. Update VEX
4603 VEX_check_operands (const insn_template
*t
)
4605 /* VREX is only valid with EVEX prefix. */
4606 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4608 i
.error
= invalid_register_operand
;
4612 if (!t
->opcode_modifier
.vex
)
4615 /* Only check VEX_Imm4, which must be the first operand. */
4616 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4618 if (i
.op
[0].imms
->X_op
!= O_constant
4619 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4625 /* Turn off Imm8 so that update_imm won't complain. */
4626 i
.types
[0] = vec_imm4
;
4632 static const insn_template
*
4633 match_template (void)
4635 /* Points to template once we've found it. */
4636 const insn_template
*t
;
4637 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4638 i386_operand_type overlap4
;
4639 unsigned int found_reverse_match
;
4640 i386_opcode_modifier suffix_check
;
4641 i386_operand_type operand_types
[MAX_OPERANDS
];
4642 int addr_prefix_disp
;
4644 unsigned int found_cpu_match
;
4645 unsigned int check_register
;
4646 enum i386_error specific_error
= 0;
4648 #if MAX_OPERANDS != 5
4649 # error "MAX_OPERANDS must be 5."
4652 found_reverse_match
= 0;
4653 addr_prefix_disp
= -1;
4655 memset (&suffix_check
, 0, sizeof (suffix_check
));
4656 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4657 suffix_check
.no_bsuf
= 1;
4658 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4659 suffix_check
.no_wsuf
= 1;
4660 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4661 suffix_check
.no_ssuf
= 1;
4662 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4663 suffix_check
.no_lsuf
= 1;
4664 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4665 suffix_check
.no_qsuf
= 1;
4666 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4667 suffix_check
.no_ldsuf
= 1;
4669 /* Must have right number of operands. */
4670 i
.error
= number_of_operands_mismatch
;
4672 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4674 addr_prefix_disp
= -1;
4676 if (i
.operands
!= t
->operands
)
4679 /* Check processor support. */
4680 i
.error
= unsupported
;
4681 found_cpu_match
= (cpu_flags_match (t
)
4682 == CPU_FLAGS_PERFECT_MATCH
);
4683 if (!found_cpu_match
)
4686 /* Check old gcc support. */
4687 i
.error
= old_gcc_only
;
4688 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4691 /* Check AT&T mnemonic. */
4692 i
.error
= unsupported_with_intel_mnemonic
;
4693 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4696 /* Check AT&T/Intel syntax. */
4697 i
.error
= unsupported_syntax
;
4698 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4699 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4702 /* Check the suffix, except for some instructions in intel mode. */
4703 i
.error
= invalid_instruction_suffix
;
4704 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4705 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4706 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4707 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4708 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4709 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4710 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4713 if (!operand_size_match (t
))
4716 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4717 operand_types
[j
] = t
->operand_types
[j
];
4719 /* In general, don't allow 64-bit operands in 32-bit mode. */
4720 if (i
.suffix
== QWORD_MNEM_SUFFIX
4721 && flag_code
!= CODE_64BIT
4723 ? (!t
->opcode_modifier
.ignoresize
4724 && !intel_float_operand (t
->name
))
4725 : intel_float_operand (t
->name
) != 2)
4726 && ((!operand_types
[0].bitfield
.regmmx
4727 && !operand_types
[0].bitfield
.regxmm
4728 && !operand_types
[0].bitfield
.regymm
4729 && !operand_types
[0].bitfield
.regzmm
)
4730 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4731 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4732 && operand_types
[t
->operands
> 1].bitfield
.regymm
4733 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4734 && (t
->base_opcode
!= 0x0fc7
4735 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4738 /* In general, don't allow 32-bit operands on pre-386. */
4739 else if (i
.suffix
== LONG_MNEM_SUFFIX
4740 && !cpu_arch_flags
.bitfield
.cpui386
4742 ? (!t
->opcode_modifier
.ignoresize
4743 && !intel_float_operand (t
->name
))
4744 : intel_float_operand (t
->name
) != 2)
4745 && ((!operand_types
[0].bitfield
.regmmx
4746 && !operand_types
[0].bitfield
.regxmm
)
4747 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4748 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4751 /* Do not verify operands when there are none. */
4755 /* We've found a match; break out of loop. */
4759 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4760 into Disp32/Disp16/Disp32 operand. */
4761 if (i
.prefix
[ADDR_PREFIX
] != 0)
4763 /* There should be only one Disp operand. */
4767 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4769 if (operand_types
[j
].bitfield
.disp16
)
4771 addr_prefix_disp
= j
;
4772 operand_types
[j
].bitfield
.disp32
= 1;
4773 operand_types
[j
].bitfield
.disp16
= 0;
4779 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4781 if (operand_types
[j
].bitfield
.disp32
)
4783 addr_prefix_disp
= j
;
4784 operand_types
[j
].bitfield
.disp32
= 0;
4785 operand_types
[j
].bitfield
.disp16
= 1;
4791 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4793 if (operand_types
[j
].bitfield
.disp64
)
4795 addr_prefix_disp
= j
;
4796 operand_types
[j
].bitfield
.disp64
= 0;
4797 operand_types
[j
].bitfield
.disp32
= 1;
4805 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4806 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4809 /* We check register size if needed. */
4810 check_register
= t
->opcode_modifier
.checkregsize
;
4811 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4812 switch (t
->operands
)
4815 if (!operand_type_match (overlap0
, i
.types
[0]))
4819 /* xchg %eax, %eax is a special case. It is an aliase for nop
4820 only in 32bit mode and we can use opcode 0x90. In 64bit
4821 mode, we can't use 0x90 for xchg %eax, %eax since it should
4822 zero-extend %eax to %rax. */
4823 if (flag_code
== CODE_64BIT
4824 && t
->base_opcode
== 0x90
4825 && operand_type_equal (&i
.types
[0], &acc32
)
4826 && operand_type_equal (&i
.types
[1], &acc32
))
4830 /* If we swap operand in encoding, we either match
4831 the next one or reverse direction of operands. */
4832 if (t
->opcode_modifier
.s
)
4834 else if (t
->opcode_modifier
.d
)
4839 /* If we swap operand in encoding, we match the next one. */
4840 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4844 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4845 if (!operand_type_match (overlap0
, i
.types
[0])
4846 || !operand_type_match (overlap1
, i
.types
[1])
4848 && !operand_type_register_match (overlap0
, i
.types
[0],
4850 overlap1
, i
.types
[1],
4853 /* Check if other direction is valid ... */
4854 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4858 /* Try reversing direction of operands. */
4859 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4860 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4861 if (!operand_type_match (overlap0
, i
.types
[0])
4862 || !operand_type_match (overlap1
, i
.types
[1])
4864 && !operand_type_register_match (overlap0
,
4871 /* Does not match either direction. */
4874 /* found_reverse_match holds which of D or FloatDR
4876 if (t
->opcode_modifier
.d
)
4877 found_reverse_match
= Opcode_D
;
4878 else if (t
->opcode_modifier
.floatd
)
4879 found_reverse_match
= Opcode_FloatD
;
4881 found_reverse_match
= 0;
4882 if (t
->opcode_modifier
.floatr
)
4883 found_reverse_match
|= Opcode_FloatR
;
4887 /* Found a forward 2 operand match here. */
4888 switch (t
->operands
)
4891 overlap4
= operand_type_and (i
.types
[4],
4894 overlap3
= operand_type_and (i
.types
[3],
4897 overlap2
= operand_type_and (i
.types
[2],
4902 switch (t
->operands
)
4905 if (!operand_type_match (overlap4
, i
.types
[4])
4906 || !operand_type_register_match (overlap3
,
4914 if (!operand_type_match (overlap3
, i
.types
[3])
4916 && !operand_type_register_match (overlap2
,
4924 /* Here we make use of the fact that there are no
4925 reverse match 3 operand instructions, and all 3
4926 operand instructions only need to be checked for
4927 register consistency between operands 2 and 3. */
4928 if (!operand_type_match (overlap2
, i
.types
[2])
4930 && !operand_type_register_match (overlap1
,
4940 /* Found either forward/reverse 2, 3 or 4 operand match here:
4941 slip through to break. */
4943 if (!found_cpu_match
)
4945 found_reverse_match
= 0;
4949 /* Check if vector and VEX operands are valid. */
4950 if (check_VecOperands (t
) || VEX_check_operands (t
))
4952 specific_error
= i
.error
;
4956 /* We've found a match; break out of loop. */
4960 if (t
== current_templates
->end
)
4962 /* We found no match. */
4963 const char *err_msg
;
4964 switch (specific_error
? specific_error
: i
.error
)
4968 case operand_size_mismatch
:
4969 err_msg
= _("operand size mismatch");
4971 case operand_type_mismatch
:
4972 err_msg
= _("operand type mismatch");
4974 case register_type_mismatch
:
4975 err_msg
= _("register type mismatch");
4977 case number_of_operands_mismatch
:
4978 err_msg
= _("number of operands mismatch");
4980 case invalid_instruction_suffix
:
4981 err_msg
= _("invalid instruction suffix");
4984 err_msg
= _("constant doesn't fit in 4 bits");
4987 err_msg
= _("only supported with old gcc");
4989 case unsupported_with_intel_mnemonic
:
4990 err_msg
= _("unsupported with Intel mnemonic");
4992 case unsupported_syntax
:
4993 err_msg
= _("unsupported syntax");
4996 as_bad (_("unsupported instruction `%s'"),
4997 current_templates
->start
->name
);
4999 case invalid_vsib_address
:
5000 err_msg
= _("invalid VSIB address");
5002 case invalid_vector_register_set
:
5003 err_msg
= _("mask, index, and destination registers must be distinct");
5005 case unsupported_vector_index_register
:
5006 err_msg
= _("unsupported vector index register");
5008 case unsupported_broadcast
:
5009 err_msg
= _("unsupported broadcast");
5011 case broadcast_not_on_src_operand
:
5012 err_msg
= _("broadcast not on source memory operand");
5014 case broadcast_needed
:
5015 err_msg
= _("broadcast is needed for operand of such type");
5017 case unsupported_masking
:
5018 err_msg
= _("unsupported masking");
5020 case mask_not_on_destination
:
5021 err_msg
= _("mask not on destination operand");
5023 case no_default_mask
:
5024 err_msg
= _("default mask isn't allowed");
5026 case unsupported_rc_sae
:
5027 err_msg
= _("unsupported static rounding/sae");
5029 case rc_sae_operand_not_last_imm
:
5031 err_msg
= _("RC/SAE operand must precede immediate operands");
5033 err_msg
= _("RC/SAE operand must follow immediate operands");
5035 case invalid_register_operand
:
5036 err_msg
= _("invalid register operand");
5039 as_bad (_("%s for `%s'"), err_msg
,
5040 current_templates
->start
->name
);
5044 if (!quiet_warnings
)
5047 && (i
.types
[0].bitfield
.jumpabsolute
5048 != operand_types
[0].bitfield
.jumpabsolute
))
5050 as_warn (_("indirect %s without `*'"), t
->name
);
5053 if (t
->opcode_modifier
.isprefix
5054 && t
->opcode_modifier
.ignoresize
)
5056 /* Warn them that a data or address size prefix doesn't
5057 affect assembly of the next line of code. */
5058 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5062 /* Copy the template we found. */
5065 if (addr_prefix_disp
!= -1)
5066 i
.tm
.operand_types
[addr_prefix_disp
]
5067 = operand_types
[addr_prefix_disp
];
5069 if (found_reverse_match
)
5071 /* If we found a reverse match we must alter the opcode
5072 direction bit. found_reverse_match holds bits to change
5073 (different for int & float insns). */
5075 i
.tm
.base_opcode
^= found_reverse_match
;
5077 i
.tm
.operand_types
[0] = operand_types
[1];
5078 i
.tm
.operand_types
[1] = operand_types
[0];
5087 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5088 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5090 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5092 as_bad (_("`%s' operand %d must use `%ses' segment"),
5098 /* There's only ever one segment override allowed per instruction.
5099 This instruction possibly has a legal segment override on the
5100 second operand, so copy the segment to where non-string
5101 instructions store it, allowing common code. */
5102 i
.seg
[0] = i
.seg
[1];
5104 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5106 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5108 as_bad (_("`%s' operand %d must use `%ses' segment"),
5119 process_suffix (void)
5121 /* If matched instruction specifies an explicit instruction mnemonic
5123 if (i
.tm
.opcode_modifier
.size16
)
5124 i
.suffix
= WORD_MNEM_SUFFIX
;
5125 else if (i
.tm
.opcode_modifier
.size32
)
5126 i
.suffix
= LONG_MNEM_SUFFIX
;
5127 else if (i
.tm
.opcode_modifier
.size64
)
5128 i
.suffix
= QWORD_MNEM_SUFFIX
;
5129 else if (i
.reg_operands
)
5131 /* If there's no instruction mnemonic suffix we try to invent one
5132 based on register operands. */
5135 /* We take i.suffix from the last register operand specified,
5136 Destination register type is more significant than source
5137 register type. crc32 in SSE4.2 prefers source register
5139 if (i
.tm
.base_opcode
== 0xf20f38f1)
5141 if (i
.types
[0].bitfield
.reg16
)
5142 i
.suffix
= WORD_MNEM_SUFFIX
;
5143 else if (i
.types
[0].bitfield
.reg32
)
5144 i
.suffix
= LONG_MNEM_SUFFIX
;
5145 else if (i
.types
[0].bitfield
.reg64
)
5146 i
.suffix
= QWORD_MNEM_SUFFIX
;
5148 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5150 if (i
.types
[0].bitfield
.reg8
)
5151 i
.suffix
= BYTE_MNEM_SUFFIX
;
5158 if (i
.tm
.base_opcode
== 0xf20f38f1
5159 || i
.tm
.base_opcode
== 0xf20f38f0)
5161 /* We have to know the operand size for crc32. */
5162 as_bad (_("ambiguous memory operand size for `%s`"),
5167 for (op
= i
.operands
; --op
>= 0;)
5168 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5170 if (i
.types
[op
].bitfield
.reg8
)
5172 i
.suffix
= BYTE_MNEM_SUFFIX
;
5175 else if (i
.types
[op
].bitfield
.reg16
)
5177 i
.suffix
= WORD_MNEM_SUFFIX
;
5180 else if (i
.types
[op
].bitfield
.reg32
)
5182 i
.suffix
= LONG_MNEM_SUFFIX
;
5185 else if (i
.types
[op
].bitfield
.reg64
)
5187 i
.suffix
= QWORD_MNEM_SUFFIX
;
5193 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5196 && i
.tm
.opcode_modifier
.ignoresize
5197 && i
.tm
.opcode_modifier
.no_bsuf
)
5199 else if (!check_byte_reg ())
5202 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5205 && i
.tm
.opcode_modifier
.ignoresize
5206 && i
.tm
.opcode_modifier
.no_lsuf
)
5208 else if (!check_long_reg ())
5211 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5214 && i
.tm
.opcode_modifier
.ignoresize
5215 && i
.tm
.opcode_modifier
.no_qsuf
)
5217 else if (!check_qword_reg ())
5220 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5223 && i
.tm
.opcode_modifier
.ignoresize
5224 && i
.tm
.opcode_modifier
.no_wsuf
)
5226 else if (!check_word_reg ())
5229 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5230 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5231 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5233 /* Skip if the instruction has x/y/z suffix. match_template
5234 should check if it is a valid suffix. */
5236 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5237 /* Do nothing if the instruction is going to ignore the prefix. */
5242 else if (i
.tm
.opcode_modifier
.defaultsize
5244 /* exclude fldenv/frstor/fsave/fstenv */
5245 && i
.tm
.opcode_modifier
.no_ssuf
)
5247 i
.suffix
= stackop_size
;
5249 else if (intel_syntax
5251 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5252 || i
.tm
.opcode_modifier
.jumpbyte
5253 || i
.tm
.opcode_modifier
.jumpintersegment
5254 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5255 && i
.tm
.extension_opcode
<= 3)))
5260 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5262 i
.suffix
= QWORD_MNEM_SUFFIX
;
5266 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5267 i
.suffix
= LONG_MNEM_SUFFIX
;
5270 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5271 i
.suffix
= WORD_MNEM_SUFFIX
;
5280 if (i
.tm
.opcode_modifier
.w
)
5282 as_bad (_("no instruction mnemonic suffix given and "
5283 "no register operands; can't size instruction"));
5289 unsigned int suffixes
;
5291 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5292 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5294 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5296 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5298 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5300 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5303 /* There are more than suffix matches. */
5304 if (i
.tm
.opcode_modifier
.w
5305 || ((suffixes
& (suffixes
- 1))
5306 && !i
.tm
.opcode_modifier
.defaultsize
5307 && !i
.tm
.opcode_modifier
.ignoresize
))
5309 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5315 /* Change the opcode based on the operand size given by i.suffix;
5316 We don't need to change things for byte insns. */
5319 && i
.suffix
!= BYTE_MNEM_SUFFIX
5320 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5321 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5322 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5324 /* It's not a byte, select word/dword operation. */
5325 if (i
.tm
.opcode_modifier
.w
)
5327 if (i
.tm
.opcode_modifier
.shortform
)
5328 i
.tm
.base_opcode
|= 8;
5330 i
.tm
.base_opcode
|= 1;
5333 /* Now select between word & dword operations via the operand
5334 size prefix, except for instructions that will ignore this
5336 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5338 /* The address size override prefix changes the size of the
5340 if ((flag_code
== CODE_32BIT
5341 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5342 || (flag_code
!= CODE_32BIT
5343 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5344 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5347 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5348 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5349 && !i
.tm
.opcode_modifier
.ignoresize
5350 && !i
.tm
.opcode_modifier
.floatmf
5351 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5352 || (flag_code
== CODE_64BIT
5353 && i
.tm
.opcode_modifier
.jumpbyte
)))
5355 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5357 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5358 prefix
= ADDR_PREFIX_OPCODE
;
5360 if (!add_prefix (prefix
))
5364 /* Set mode64 for an operand. */
5365 if (i
.suffix
== QWORD_MNEM_SUFFIX
5366 && flag_code
== CODE_64BIT
5367 && !i
.tm
.opcode_modifier
.norex64
)
5369 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5370 need rex64. cmpxchg8b is also a special case. */
5371 if (! (i
.operands
== 2
5372 && i
.tm
.base_opcode
== 0x90
5373 && i
.tm
.extension_opcode
== None
5374 && operand_type_equal (&i
.types
[0], &acc64
)
5375 && operand_type_equal (&i
.types
[1], &acc64
))
5376 && ! (i
.operands
== 1
5377 && i
.tm
.base_opcode
== 0xfc7
5378 && i
.tm
.extension_opcode
== 1
5379 && !operand_type_check (i
.types
[0], reg
)
5380 && operand_type_check (i
.types
[0], anymem
)))
5384 /* Size floating point instruction. */
5385 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5386 if (i
.tm
.opcode_modifier
.floatmf
)
5387 i
.tm
.base_opcode
^= 4;
5394 check_byte_reg (void)
5398 for (op
= i
.operands
; --op
>= 0;)
5400 /* If this is an eight bit register, it's OK. If it's the 16 or
5401 32 bit version of an eight bit register, we will just use the
5402 low portion, and that's OK too. */
5403 if (i
.types
[op
].bitfield
.reg8
)
5406 /* I/O port address operands are OK too. */
5407 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5410 /* crc32 doesn't generate this warning. */
5411 if (i
.tm
.base_opcode
== 0xf20f38f0)
5414 if ((i
.types
[op
].bitfield
.reg16
5415 || i
.types
[op
].bitfield
.reg32
5416 || i
.types
[op
].bitfield
.reg64
)
5417 && i
.op
[op
].regs
->reg_num
< 4
5418 /* Prohibit these changes in 64bit mode, since the lowering
5419 would be more complicated. */
5420 && flag_code
!= CODE_64BIT
)
5422 #if REGISTER_WARNINGS
5423 if (!quiet_warnings
)
5424 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5426 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5427 ? REGNAM_AL
- REGNAM_AX
5428 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5430 i
.op
[op
].regs
->reg_name
,
5435 /* Any other register is bad. */
5436 if (i
.types
[op
].bitfield
.reg16
5437 || i
.types
[op
].bitfield
.reg32
5438 || i
.types
[op
].bitfield
.reg64
5439 || i
.types
[op
].bitfield
.regmmx
5440 || i
.types
[op
].bitfield
.regxmm
5441 || i
.types
[op
].bitfield
.regymm
5442 || i
.types
[op
].bitfield
.regzmm
5443 || i
.types
[op
].bitfield
.sreg2
5444 || i
.types
[op
].bitfield
.sreg3
5445 || i
.types
[op
].bitfield
.control
5446 || i
.types
[op
].bitfield
.debug
5447 || i
.types
[op
].bitfield
.test
5448 || i
.types
[op
].bitfield
.floatreg
5449 || i
.types
[op
].bitfield
.floatacc
)
5451 as_bad (_("`%s%s' not allowed with `%s%c'"),
5453 i
.op
[op
].regs
->reg_name
,
5463 check_long_reg (void)
5467 for (op
= i
.operands
; --op
>= 0;)
5468 /* Reject eight bit registers, except where the template requires
5469 them. (eg. movzb) */
5470 if (i
.types
[op
].bitfield
.reg8
5471 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5472 || i
.tm
.operand_types
[op
].bitfield
.reg32
5473 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5475 as_bad (_("`%s%s' not allowed with `%s%c'"),
5477 i
.op
[op
].regs
->reg_name
,
5482 /* Warn if the e prefix on a general reg is missing. */
5483 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5484 && i
.types
[op
].bitfield
.reg16
5485 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5486 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5488 /* Prohibit these changes in the 64bit mode, since the
5489 lowering is more complicated. */
5490 if (flag_code
== CODE_64BIT
)
5492 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5493 register_prefix
, i
.op
[op
].regs
->reg_name
,
5497 #if REGISTER_WARNINGS
5498 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5500 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5501 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5504 /* Warn if the r prefix on a general reg is present. */
5505 else if (i
.types
[op
].bitfield
.reg64
5506 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5507 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5510 && i
.tm
.opcode_modifier
.toqword
5511 && !i
.types
[0].bitfield
.regxmm
)
5513 /* Convert to QWORD. We want REX byte. */
5514 i
.suffix
= QWORD_MNEM_SUFFIX
;
5518 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5519 register_prefix
, i
.op
[op
].regs
->reg_name
,
5528 check_qword_reg (void)
5532 for (op
= i
.operands
; --op
>= 0; )
5533 /* Reject eight bit registers, except where the template requires
5534 them. (eg. movzb) */
5535 if (i
.types
[op
].bitfield
.reg8
5536 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5537 || i
.tm
.operand_types
[op
].bitfield
.reg32
5538 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5540 as_bad (_("`%s%s' not allowed with `%s%c'"),
5542 i
.op
[op
].regs
->reg_name
,
5547 /* Warn if the r prefix on a general reg is missing. */
5548 else if ((i
.types
[op
].bitfield
.reg16
5549 || i
.types
[op
].bitfield
.reg32
)
5550 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5551 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5553 /* Prohibit these changes in the 64bit mode, since the
5554 lowering is more complicated. */
5556 && i
.tm
.opcode_modifier
.todword
5557 && !i
.types
[0].bitfield
.regxmm
)
5559 /* Convert to DWORD. We don't want REX byte. */
5560 i
.suffix
= LONG_MNEM_SUFFIX
;
5564 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5565 register_prefix
, i
.op
[op
].regs
->reg_name
,
5574 check_word_reg (void)
5577 for (op
= i
.operands
; --op
>= 0;)
5578 /* Reject eight bit registers, except where the template requires
5579 them. (eg. movzb) */
5580 if (i
.types
[op
].bitfield
.reg8
5581 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5582 || i
.tm
.operand_types
[op
].bitfield
.reg32
5583 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5585 as_bad (_("`%s%s' not allowed with `%s%c'"),
5587 i
.op
[op
].regs
->reg_name
,
5592 /* Warn if the e or r prefix on a general reg is present. */
5593 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5594 && (i
.types
[op
].bitfield
.reg32
5595 || i
.types
[op
].bitfield
.reg64
)
5596 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5597 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5599 /* Prohibit these changes in the 64bit mode, since the
5600 lowering is more complicated. */
5601 if (flag_code
== CODE_64BIT
)
5603 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5604 register_prefix
, i
.op
[op
].regs
->reg_name
,
5608 #if REGISTER_WARNINGS
5609 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5611 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5612 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5619 update_imm (unsigned int j
)
5621 i386_operand_type overlap
= i
.types
[j
];
5622 if ((overlap
.bitfield
.imm8
5623 || overlap
.bitfield
.imm8s
5624 || overlap
.bitfield
.imm16
5625 || overlap
.bitfield
.imm32
5626 || overlap
.bitfield
.imm32s
5627 || overlap
.bitfield
.imm64
)
5628 && !operand_type_equal (&overlap
, &imm8
)
5629 && !operand_type_equal (&overlap
, &imm8s
)
5630 && !operand_type_equal (&overlap
, &imm16
)
5631 && !operand_type_equal (&overlap
, &imm32
)
5632 && !operand_type_equal (&overlap
, &imm32s
)
5633 && !operand_type_equal (&overlap
, &imm64
))
5637 i386_operand_type temp
;
5639 operand_type_set (&temp
, 0);
5640 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5642 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5643 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5645 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5646 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5647 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5649 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5650 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5653 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5656 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5657 || operand_type_equal (&overlap
, &imm16_32
)
5658 || operand_type_equal (&overlap
, &imm16_32s
))
5660 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5665 if (!operand_type_equal (&overlap
, &imm8
)
5666 && !operand_type_equal (&overlap
, &imm8s
)
5667 && !operand_type_equal (&overlap
, &imm16
)
5668 && !operand_type_equal (&overlap
, &imm32
)
5669 && !operand_type_equal (&overlap
, &imm32s
)
5670 && !operand_type_equal (&overlap
, &imm64
))
5672 as_bad (_("no instruction mnemonic suffix given; "
5673 "can't determine immediate size"));
5677 i
.types
[j
] = overlap
;
5687 /* Update the first 2 immediate operands. */
5688 n
= i
.operands
> 2 ? 2 : i
.operands
;
5691 for (j
= 0; j
< n
; j
++)
5692 if (update_imm (j
) == 0)
5695 /* The 3rd operand can't be immediate operand. */
5696 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5703 bad_implicit_operand (int xmm
)
5705 const char *ireg
= xmm
? "xmm0" : "ymm0";
5708 as_bad (_("the last operand of `%s' must be `%s%s'"),
5709 i
.tm
.name
, register_prefix
, ireg
);
5711 as_bad (_("the first operand of `%s' must be `%s%s'"),
5712 i
.tm
.name
, register_prefix
, ireg
);
5717 process_operands (void)
5719 /* Default segment register this instruction will use for memory
5720 accesses. 0 means unknown. This is only for optimizing out
5721 unnecessary segment overrides. */
5722 const seg_entry
*default_seg
= 0;
5724 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5726 unsigned int dupl
= i
.operands
;
5727 unsigned int dest
= dupl
- 1;
5730 /* The destination must be an xmm register. */
5731 gas_assert (i
.reg_operands
5732 && MAX_OPERANDS
> dupl
5733 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5735 if (i
.tm
.opcode_modifier
.firstxmm0
)
5737 /* The first operand is implicit and must be xmm0. */
5738 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5739 if (register_number (i
.op
[0].regs
) != 0)
5740 return bad_implicit_operand (1);
5742 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5744 /* Keep xmm0 for instructions with VEX prefix and 3
5750 /* We remove the first xmm0 and keep the number of
5751 operands unchanged, which in fact duplicates the
5753 for (j
= 1; j
< i
.operands
; j
++)
5755 i
.op
[j
- 1] = i
.op
[j
];
5756 i
.types
[j
- 1] = i
.types
[j
];
5757 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5761 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5763 gas_assert ((MAX_OPERANDS
- 1) > dupl
5764 && (i
.tm
.opcode_modifier
.vexsources
5767 /* Add the implicit xmm0 for instructions with VEX prefix
5769 for (j
= i
.operands
; j
> 0; j
--)
5771 i
.op
[j
] = i
.op
[j
- 1];
5772 i
.types
[j
] = i
.types
[j
- 1];
5773 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5776 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5777 i
.types
[0] = regxmm
;
5778 i
.tm
.operand_types
[0] = regxmm
;
5781 i
.reg_operands
+= 2;
5786 i
.op
[dupl
] = i
.op
[dest
];
5787 i
.types
[dupl
] = i
.types
[dest
];
5788 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5797 i
.op
[dupl
] = i
.op
[dest
];
5798 i
.types
[dupl
] = i
.types
[dest
];
5799 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5802 if (i
.tm
.opcode_modifier
.immext
)
5805 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5809 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5810 gas_assert (i
.reg_operands
5811 && (operand_type_equal (&i
.types
[0], ®xmm
)
5812 || operand_type_equal (&i
.types
[0], ®ymm
)
5813 || operand_type_equal (&i
.types
[0], ®zmm
)));
5814 if (register_number (i
.op
[0].regs
) != 0)
5815 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5817 for (j
= 1; j
< i
.operands
; j
++)
5819 i
.op
[j
- 1] = i
.op
[j
];
5820 i
.types
[j
- 1] = i
.types
[j
];
5822 /* We need to adjust fields in i.tm since they are used by
5823 build_modrm_byte. */
5824 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5831 else if (i
.tm
.opcode_modifier
.regkludge
)
5833 /* The imul $imm, %reg instruction is converted into
5834 imul $imm, %reg, %reg, and the clr %reg instruction
5835 is converted into xor %reg, %reg. */
5837 unsigned int first_reg_op
;
5839 if (operand_type_check (i
.types
[0], reg
))
5843 /* Pretend we saw the extra register operand. */
5844 gas_assert (i
.reg_operands
== 1
5845 && i
.op
[first_reg_op
+ 1].regs
== 0);
5846 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5847 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5852 if (i
.tm
.opcode_modifier
.shortform
)
5854 if (i
.types
[0].bitfield
.sreg2
5855 || i
.types
[0].bitfield
.sreg3
)
5857 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5858 && i
.op
[0].regs
->reg_num
== 1)
5860 as_bad (_("you can't `pop %scs'"), register_prefix
);
5863 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5864 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5869 /* The register or float register operand is in operand
5873 if (i
.types
[0].bitfield
.floatreg
5874 || operand_type_check (i
.types
[0], reg
))
5878 /* Register goes in low 3 bits of opcode. */
5879 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5880 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5882 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5884 /* Warn about some common errors, but press on regardless.
5885 The first case can be generated by gcc (<= 2.8.1). */
5886 if (i
.operands
== 2)
5888 /* Reversed arguments on faddp, fsubp, etc. */
5889 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5890 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5891 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5895 /* Extraneous `l' suffix on fp insn. */
5896 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5897 register_prefix
, i
.op
[0].regs
->reg_name
);
5902 else if (i
.tm
.opcode_modifier
.modrm
)
5904 /* The opcode is completed (modulo i.tm.extension_opcode which
5905 must be put into the modrm byte). Now, we make the modrm and
5906 index base bytes based on all the info we've collected. */
5908 default_seg
= build_modrm_byte ();
5910 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5914 else if (i
.tm
.opcode_modifier
.isstring
)
5916 /* For the string instructions that allow a segment override
5917 on one of their operands, the default segment is ds. */
5921 if (i
.tm
.base_opcode
== 0x8d /* lea */
5924 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5926 /* If a segment was explicitly specified, and the specified segment
5927 is not the default, use an opcode prefix to select it. If we
5928 never figured out what the default segment is, then default_seg
5929 will be zero at this point, and the specified segment prefix will
5931 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5933 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5939 static const seg_entry
*
5940 build_modrm_byte (void)
5942 const seg_entry
*default_seg
= 0;
5943 unsigned int source
, dest
;
5946 /* The first operand of instructions with VEX prefix and 3 sources
5947 must be VEX_Imm4. */
5948 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5951 unsigned int nds
, reg_slot
;
5954 if (i
.tm
.opcode_modifier
.veximmext
5955 && i
.tm
.opcode_modifier
.immext
)
5957 dest
= i
.operands
- 2;
5958 gas_assert (dest
== 3);
5961 dest
= i
.operands
- 1;
5964 /* There are 2 kinds of instructions:
5965 1. 5 operands: 4 register operands or 3 register operands
5966 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5967 VexW0 or VexW1. The destination must be either XMM, YMM or
5969 2. 4 operands: 4 register operands or 3 register operands
5970 plus 1 memory operand, VexXDS, and VexImmExt */
5971 gas_assert ((i
.reg_operands
== 4
5972 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5973 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5974 && (i
.tm
.opcode_modifier
.veximmext
5975 || (i
.imm_operands
== 1
5976 && i
.types
[0].bitfield
.vec_imm4
5977 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5978 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5979 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5980 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5981 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5983 if (i
.imm_operands
== 0)
5985 /* When there is no immediate operand, generate an 8bit
5986 immediate operand to encode the first operand. */
5987 exp
= &im_expressions
[i
.imm_operands
++];
5988 i
.op
[i
.operands
].imms
= exp
;
5989 i
.types
[i
.operands
] = imm8
;
5991 /* If VexW1 is set, the first operand is the source and
5992 the second operand is encoded in the immediate operand. */
5993 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6004 /* FMA swaps REG and NDS. */
6005 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6013 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6015 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6017 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6019 exp
->X_op
= O_constant
;
6020 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6021 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6025 unsigned int imm_slot
;
6027 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6029 /* If VexW0 is set, the third operand is the source and
6030 the second operand is encoded in the immediate
6037 /* VexW1 is set, the second operand is the source and
6038 the third operand is encoded in the immediate
6044 if (i
.tm
.opcode_modifier
.immext
)
6046 /* When ImmExt is set, the immdiate byte is the last
6048 imm_slot
= i
.operands
- 1;
6056 /* Turn on Imm8 so that output_imm will generate it. */
6057 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6060 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6062 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6064 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6066 i
.op
[imm_slot
].imms
->X_add_number
6067 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6068 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6071 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6072 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6074 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6076 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6081 /* i.reg_operands MUST be the number of real register operands;
6082 implicit registers do not count. If there are 3 register
6083 operands, it must be a instruction with VexNDS. For a
6084 instruction with VexNDD, the destination register is encoded
6085 in VEX prefix. If there are 4 register operands, it must be
6086 a instruction with VEX prefix and 3 sources. */
6087 if (i
.mem_operands
== 0
6088 && ((i
.reg_operands
== 2
6089 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6090 || (i
.reg_operands
== 3
6091 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6092 || (i
.reg_operands
== 4 && vex_3_sources
)))
6100 /* When there are 3 operands, one of them may be immediate,
6101 which may be the first or the last operand. Otherwise,
6102 the first operand must be shift count register (cl) or it
6103 is an instruction with VexNDS. */
6104 gas_assert (i
.imm_operands
== 1
6105 || (i
.imm_operands
== 0
6106 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6107 || i
.types
[0].bitfield
.shiftcount
)));
6108 if (operand_type_check (i
.types
[0], imm
)
6109 || i
.types
[0].bitfield
.shiftcount
)
6115 /* When there are 4 operands, the first two must be 8bit
6116 immediate operands. The source operand will be the 3rd
6119 For instructions with VexNDS, if the first operand
6120 an imm8, the source operand is the 2nd one. If the last
6121 operand is imm8, the source operand is the first one. */
6122 gas_assert ((i
.imm_operands
== 2
6123 && i
.types
[0].bitfield
.imm8
6124 && i
.types
[1].bitfield
.imm8
)
6125 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6126 && i
.imm_operands
== 1
6127 && (i
.types
[0].bitfield
.imm8
6128 || i
.types
[i
.operands
- 1].bitfield
.imm8
6130 if (i
.imm_operands
== 2)
6134 if (i
.types
[0].bitfield
.imm8
)
6141 if (i
.tm
.opcode_modifier
.evex
)
6143 /* For EVEX instructions, when there are 5 operands, the
6144 first one must be immediate operand. If the second one
6145 is immediate operand, the source operand is the 3th
6146 one. If the last one is immediate operand, the source
6147 operand is the 2nd one. */
6148 gas_assert (i
.imm_operands
== 2
6149 && i
.tm
.opcode_modifier
.sae
6150 && operand_type_check (i
.types
[0], imm
));
6151 if (operand_type_check (i
.types
[1], imm
))
6153 else if (operand_type_check (i
.types
[4], imm
))
6167 /* RC/SAE operand could be between DEST and SRC. That happens
6168 when one operand is GPR and the other one is XMM/YMM/ZMM
6170 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6173 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6175 /* For instructions with VexNDS, the register-only source
6176 operand must be 32/64bit integer, XMM, YMM or ZMM
6177 register. It is encoded in VEX prefix. We need to
6178 clear RegMem bit before calling operand_type_equal. */
6180 i386_operand_type op
;
6183 /* Check register-only source operand when two source
6184 operands are swapped. */
6185 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6186 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6194 op
= i
.tm
.operand_types
[vvvv
];
6195 op
.bitfield
.regmem
= 0;
6196 if ((dest
+ 1) >= i
.operands
6197 || (!op
.bitfield
.reg32
6198 && op
.bitfield
.reg64
6199 && !operand_type_equal (&op
, ®xmm
)
6200 && !operand_type_equal (&op
, ®ymm
)
6201 && !operand_type_equal (&op
, ®zmm
)
6202 && !operand_type_equal (&op
, ®mask
)))
6204 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6210 /* One of the register operands will be encoded in the i.tm.reg
6211 field, the other in the combined i.tm.mode and i.tm.regmem
6212 fields. If no form of this instruction supports a memory
6213 destination operand, then we assume the source operand may
6214 sometimes be a memory operand and so we need to store the
6215 destination in the i.rm.reg field. */
6216 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6217 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6219 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6220 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6221 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6223 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6225 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6227 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6232 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6233 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6234 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6236 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6238 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6240 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6243 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6245 if (!i
.types
[0].bitfield
.control
6246 && !i
.types
[1].bitfield
.control
)
6248 i
.rex
&= ~(REX_R
| REX_B
);
6249 add_prefix (LOCK_PREFIX_OPCODE
);
6253 { /* If it's not 2 reg operands... */
6258 unsigned int fake_zero_displacement
= 0;
6261 for (op
= 0; op
< i
.operands
; op
++)
6262 if (operand_type_check (i
.types
[op
], anymem
))
6264 gas_assert (op
< i
.operands
);
6266 if (i
.tm
.opcode_modifier
.vecsib
)
6268 if (i
.index_reg
->reg_num
== RegEiz
6269 || i
.index_reg
->reg_num
== RegRiz
)
6272 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6275 i
.sib
.base
= NO_BASE_REGISTER
;
6276 i
.sib
.scale
= i
.log2_scale_factor
;
6277 /* No Vec_Disp8 if there is no base. */
6278 i
.types
[op
].bitfield
.vec_disp8
= 0;
6279 i
.types
[op
].bitfield
.disp8
= 0;
6280 i
.types
[op
].bitfield
.disp16
= 0;
6281 i
.types
[op
].bitfield
.disp64
= 0;
6282 if (flag_code
!= CODE_64BIT
)
6284 /* Must be 32 bit */
6285 i
.types
[op
].bitfield
.disp32
= 1;
6286 i
.types
[op
].bitfield
.disp32s
= 0;
6290 i
.types
[op
].bitfield
.disp32
= 0;
6291 i
.types
[op
].bitfield
.disp32s
= 1;
6294 i
.sib
.index
= i
.index_reg
->reg_num
;
6295 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6297 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6303 if (i
.base_reg
== 0)
6306 if (!i
.disp_operands
)
6308 fake_zero_displacement
= 1;
6309 /* Instructions with VSIB byte need 32bit displacement
6310 if there is no base register. */
6311 if (i
.tm
.opcode_modifier
.vecsib
)
6312 i
.types
[op
].bitfield
.disp32
= 1;
6314 if (i
.index_reg
== 0)
6316 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6317 /* Operand is just <disp> */
6318 if (flag_code
== CODE_64BIT
)
6320 /* 64bit mode overwrites the 32bit absolute
6321 addressing by RIP relative addressing and
6322 absolute addressing is encoded by one of the
6323 redundant SIB forms. */
6324 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6325 i
.sib
.base
= NO_BASE_REGISTER
;
6326 i
.sib
.index
= NO_INDEX_REGISTER
;
6327 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6328 ? disp32s
: disp32
);
6330 else if ((flag_code
== CODE_16BIT
)
6331 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6333 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6334 i
.types
[op
] = disp16
;
6338 i
.rm
.regmem
= NO_BASE_REGISTER
;
6339 i
.types
[op
] = disp32
;
6342 else if (!i
.tm
.opcode_modifier
.vecsib
)
6344 /* !i.base_reg && i.index_reg */
6345 if (i
.index_reg
->reg_num
== RegEiz
6346 || i
.index_reg
->reg_num
== RegRiz
)
6347 i
.sib
.index
= NO_INDEX_REGISTER
;
6349 i
.sib
.index
= i
.index_reg
->reg_num
;
6350 i
.sib
.base
= NO_BASE_REGISTER
;
6351 i
.sib
.scale
= i
.log2_scale_factor
;
6352 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6353 /* No Vec_Disp8 if there is no base. */
6354 i
.types
[op
].bitfield
.vec_disp8
= 0;
6355 i
.types
[op
].bitfield
.disp8
= 0;
6356 i
.types
[op
].bitfield
.disp16
= 0;
6357 i
.types
[op
].bitfield
.disp64
= 0;
6358 if (flag_code
!= CODE_64BIT
)
6360 /* Must be 32 bit */
6361 i
.types
[op
].bitfield
.disp32
= 1;
6362 i
.types
[op
].bitfield
.disp32s
= 0;
6366 i
.types
[op
].bitfield
.disp32
= 0;
6367 i
.types
[op
].bitfield
.disp32s
= 1;
6369 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6373 /* RIP addressing for 64bit mode. */
6374 else if (i
.base_reg
->reg_num
== RegRip
||
6375 i
.base_reg
->reg_num
== RegEip
)
6377 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6378 i
.rm
.regmem
= NO_BASE_REGISTER
;
6379 i
.types
[op
].bitfield
.disp8
= 0;
6380 i
.types
[op
].bitfield
.disp16
= 0;
6381 i
.types
[op
].bitfield
.disp32
= 0;
6382 i
.types
[op
].bitfield
.disp32s
= 1;
6383 i
.types
[op
].bitfield
.disp64
= 0;
6384 i
.types
[op
].bitfield
.vec_disp8
= 0;
6385 i
.flags
[op
] |= Operand_PCrel
;
6386 if (! i
.disp_operands
)
6387 fake_zero_displacement
= 1;
6389 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6391 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6392 switch (i
.base_reg
->reg_num
)
6395 if (i
.index_reg
== 0)
6397 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6398 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6402 if (i
.index_reg
== 0)
6405 if (operand_type_check (i
.types
[op
], disp
) == 0)
6407 /* fake (%bp) into 0(%bp) */
6408 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6409 i
.types
[op
].bitfield
.vec_disp8
= 1;
6411 i
.types
[op
].bitfield
.disp8
= 1;
6412 fake_zero_displacement
= 1;
6415 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6416 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6418 default: /* (%si) -> 4 or (%di) -> 5 */
6419 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6421 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6423 else /* i.base_reg and 32/64 bit mode */
6425 if (flag_code
== CODE_64BIT
6426 && operand_type_check (i
.types
[op
], disp
))
6428 i386_operand_type temp
;
6429 operand_type_set (&temp
, 0);
6430 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6431 temp
.bitfield
.vec_disp8
6432 = i
.types
[op
].bitfield
.vec_disp8
;
6434 if (i
.prefix
[ADDR_PREFIX
] == 0)
6435 i
.types
[op
].bitfield
.disp32s
= 1;
6437 i
.types
[op
].bitfield
.disp32
= 1;
6440 if (!i
.tm
.opcode_modifier
.vecsib
)
6441 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6442 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6444 i
.sib
.base
= i
.base_reg
->reg_num
;
6445 /* x86-64 ignores REX prefix bit here to avoid decoder
6447 if (!(i
.base_reg
->reg_flags
& RegRex
)
6448 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6449 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6451 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6453 fake_zero_displacement
= 1;
6454 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6455 i
.types
[op
].bitfield
.vec_disp8
= 1;
6457 i
.types
[op
].bitfield
.disp8
= 1;
6459 i
.sib
.scale
= i
.log2_scale_factor
;
6460 if (i
.index_reg
== 0)
6462 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6463 /* <disp>(%esp) becomes two byte modrm with no index
6464 register. We've already stored the code for esp
6465 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6466 Any base register besides %esp will not use the
6467 extra modrm byte. */
6468 i
.sib
.index
= NO_INDEX_REGISTER
;
6470 else if (!i
.tm
.opcode_modifier
.vecsib
)
6472 if (i
.index_reg
->reg_num
== RegEiz
6473 || i
.index_reg
->reg_num
== RegRiz
)
6474 i
.sib
.index
= NO_INDEX_REGISTER
;
6476 i
.sib
.index
= i
.index_reg
->reg_num
;
6477 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6478 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6483 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6484 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6488 if (!fake_zero_displacement
6492 fake_zero_displacement
= 1;
6493 if (i
.disp_encoding
== disp_encoding_8bit
)
6494 i
.types
[op
].bitfield
.disp8
= 1;
6496 i
.types
[op
].bitfield
.disp32
= 1;
6498 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6502 if (fake_zero_displacement
)
6504 /* Fakes a zero displacement assuming that i.types[op]
6505 holds the correct displacement size. */
6508 gas_assert (i
.op
[op
].disps
== 0);
6509 exp
= &disp_expressions
[i
.disp_operands
++];
6510 i
.op
[op
].disps
= exp
;
6511 exp
->X_op
= O_constant
;
6512 exp
->X_add_number
= 0;
6513 exp
->X_add_symbol
= (symbolS
*) 0;
6514 exp
->X_op_symbol
= (symbolS
*) 0;
6522 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6524 if (operand_type_check (i
.types
[0], imm
))
6525 i
.vex
.register_specifier
= NULL
;
6528 /* VEX.vvvv encodes one of the sources when the first
6529 operand is not an immediate. */
6530 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6531 i
.vex
.register_specifier
= i
.op
[0].regs
;
6533 i
.vex
.register_specifier
= i
.op
[1].regs
;
6536 /* Destination is a XMM register encoded in the ModRM.reg
6538 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6539 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6542 /* ModRM.rm and VEX.B encodes the other source. */
6543 if (!i
.mem_operands
)
6547 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6548 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6550 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6552 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6556 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6558 i
.vex
.register_specifier
= i
.op
[2].regs
;
6559 if (!i
.mem_operands
)
6562 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6563 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6567 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6568 (if any) based on i.tm.extension_opcode. Again, we must be
6569 careful to make sure that segment/control/debug/test/MMX
6570 registers are coded into the i.rm.reg field. */
6571 else if (i
.reg_operands
)
6574 unsigned int vex_reg
= ~0;
6576 for (op
= 0; op
< i
.operands
; op
++)
6577 if (i
.types
[op
].bitfield
.reg8
6578 || i
.types
[op
].bitfield
.reg16
6579 || i
.types
[op
].bitfield
.reg32
6580 || i
.types
[op
].bitfield
.reg64
6581 || i
.types
[op
].bitfield
.regmmx
6582 || i
.types
[op
].bitfield
.regxmm
6583 || i
.types
[op
].bitfield
.regymm
6584 || i
.types
[op
].bitfield
.regbnd
6585 || i
.types
[op
].bitfield
.regzmm
6586 || i
.types
[op
].bitfield
.regmask
6587 || i
.types
[op
].bitfield
.sreg2
6588 || i
.types
[op
].bitfield
.sreg3
6589 || i
.types
[op
].bitfield
.control
6590 || i
.types
[op
].bitfield
.debug
6591 || i
.types
[op
].bitfield
.test
)
6596 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6598 /* For instructions with VexNDS, the register-only
6599 source operand is encoded in VEX prefix. */
6600 gas_assert (mem
!= (unsigned int) ~0);
6605 gas_assert (op
< i
.operands
);
6609 /* Check register-only source operand when two source
6610 operands are swapped. */
6611 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6612 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6616 gas_assert (mem
== (vex_reg
+ 1)
6617 && op
< i
.operands
);
6622 gas_assert (vex_reg
< i
.operands
);
6626 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6628 /* For instructions with VexNDD, the register destination
6629 is encoded in VEX prefix. */
6630 if (i
.mem_operands
== 0)
6632 /* There is no memory operand. */
6633 gas_assert ((op
+ 2) == i
.operands
);
6638 /* There are only 2 operands. */
6639 gas_assert (op
< 2 && i
.operands
== 2);
6644 gas_assert (op
< i
.operands
);
6646 if (vex_reg
!= (unsigned int) ~0)
6648 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6650 if (type
->bitfield
.reg32
!= 1
6651 && type
->bitfield
.reg64
!= 1
6652 && !operand_type_equal (type
, ®xmm
)
6653 && !operand_type_equal (type
, ®ymm
)
6654 && !operand_type_equal (type
, ®zmm
)
6655 && !operand_type_equal (type
, ®mask
))
6658 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6661 /* Don't set OP operand twice. */
6664 /* If there is an extension opcode to put here, the
6665 register number must be put into the regmem field. */
6666 if (i
.tm
.extension_opcode
!= None
)
6668 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6669 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6671 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6676 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6677 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6679 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6684 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6685 must set it to 3 to indicate this is a register operand
6686 in the regmem field. */
6687 if (!i
.mem_operands
)
6691 /* Fill in i.rm.reg field with extension opcode (if any). */
6692 if (i
.tm
.extension_opcode
!= None
)
6693 i
.rm
.reg
= i
.tm
.extension_opcode
;
6699 output_branch (void)
6705 relax_substateT subtype
;
6709 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6710 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6713 if (i
.prefix
[DATA_PREFIX
] != 0)
6719 /* Pentium4 branch hints. */
6720 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6721 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6726 if (i
.prefix
[REX_PREFIX
] != 0)
6732 /* BND prefixed jump. */
6733 if (i
.prefix
[BND_PREFIX
] != 0)
6735 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6739 if (i
.prefixes
!= 0 && !intel_syntax
)
6740 as_warn (_("skipping prefixes on this instruction"));
6742 /* It's always a symbol; End frag & setup for relax.
6743 Make sure there is enough room in this frag for the largest
6744 instruction we may generate in md_convert_frag. This is 2
6745 bytes for the opcode and room for the prefix and largest
6747 frag_grow (prefix
+ 2 + 4);
6748 /* Prefix and 1 opcode byte go in fr_fix. */
6749 p
= frag_more (prefix
+ 1);
6750 if (i
.prefix
[DATA_PREFIX
] != 0)
6751 *p
++ = DATA_PREFIX_OPCODE
;
6752 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6753 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6754 *p
++ = i
.prefix
[SEG_PREFIX
];
6755 if (i
.prefix
[REX_PREFIX
] != 0)
6756 *p
++ = i
.prefix
[REX_PREFIX
];
6757 *p
= i
.tm
.base_opcode
;
6759 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6760 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6761 else if (cpu_arch_flags
.bitfield
.cpui386
)
6762 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6764 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6767 sym
= i
.op
[0].disps
->X_add_symbol
;
6768 off
= i
.op
[0].disps
->X_add_number
;
6770 if (i
.op
[0].disps
->X_op
!= O_constant
6771 && i
.op
[0].disps
->X_op
!= O_symbol
)
6773 /* Handle complex expressions. */
6774 sym
= make_expr_symbol (i
.op
[0].disps
);
6778 /* 1 possible extra opcode + 4 byte displacement go in var part.
6779 Pass reloc in fr_var. */
6780 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6790 if (i
.tm
.opcode_modifier
.jumpbyte
)
6792 /* This is a loop or jecxz type instruction. */
6794 if (i
.prefix
[ADDR_PREFIX
] != 0)
6796 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6799 /* Pentium4 branch hints. */
6800 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6801 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6803 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6812 if (flag_code
== CODE_16BIT
)
6815 if (i
.prefix
[DATA_PREFIX
] != 0)
6817 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6827 if (i
.prefix
[REX_PREFIX
] != 0)
6829 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6833 /* BND prefixed jump. */
6834 if (i
.prefix
[BND_PREFIX
] != 0)
6836 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6840 if (i
.prefixes
!= 0 && !intel_syntax
)
6841 as_warn (_("skipping prefixes on this instruction"));
6843 p
= frag_more (i
.tm
.opcode_length
+ size
);
6844 switch (i
.tm
.opcode_length
)
6847 *p
++ = i
.tm
.base_opcode
>> 8;
6849 *p
++ = i
.tm
.base_opcode
;
6855 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6856 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6858 /* All jumps handled here are signed, but don't use a signed limit
6859 check for 32 and 16 bit jumps as we want to allow wrap around at
6860 4G and 64k respectively. */
6862 fixP
->fx_signed
= 1;
6866 output_interseg_jump (void)
6874 if (flag_code
== CODE_16BIT
)
6878 if (i
.prefix
[DATA_PREFIX
] != 0)
6884 if (i
.prefix
[REX_PREFIX
] != 0)
6894 if (i
.prefixes
!= 0 && !intel_syntax
)
6895 as_warn (_("skipping prefixes on this instruction"));
6897 /* 1 opcode; 2 segment; offset */
6898 p
= frag_more (prefix
+ 1 + 2 + size
);
6900 if (i
.prefix
[DATA_PREFIX
] != 0)
6901 *p
++ = DATA_PREFIX_OPCODE
;
6903 if (i
.prefix
[REX_PREFIX
] != 0)
6904 *p
++ = i
.prefix
[REX_PREFIX
];
6906 *p
++ = i
.tm
.base_opcode
;
6907 if (i
.op
[1].imms
->X_op
== O_constant
)
6909 offsetT n
= i
.op
[1].imms
->X_add_number
;
6912 && !fits_in_unsigned_word (n
)
6913 && !fits_in_signed_word (n
))
6915 as_bad (_("16-bit jump out of range"));
6918 md_number_to_chars (p
, n
, size
);
6921 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6922 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6923 if (i
.op
[0].imms
->X_op
!= O_constant
)
6924 as_bad (_("can't handle non absolute segment in `%s'"),
6926 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6932 fragS
*insn_start_frag
;
6933 offsetT insn_start_off
;
6935 /* Tie dwarf2 debug info to the address at the start of the insn.
6936 We can't do this after the insn has been output as the current
6937 frag may have been closed off. eg. by frag_var. */
6938 dwarf2_emit_insn (0);
6940 insn_start_frag
= frag_now
;
6941 insn_start_off
= frag_now_fix ();
6944 if (i
.tm
.opcode_modifier
.jump
)
6946 else if (i
.tm
.opcode_modifier
.jumpbyte
6947 || i
.tm
.opcode_modifier
.jumpdword
)
6949 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6950 output_interseg_jump ();
6953 /* Output normal instructions here. */
6957 unsigned int prefix
;
6959 /* Some processors fail on LOCK prefix. This options makes
6960 assembler ignore LOCK prefix and serves as a workaround. */
6961 if (omit_lock_prefix
)
6963 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6965 i
.prefix
[LOCK_PREFIX
] = 0;
6968 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6969 don't need the explicit prefix. */
6970 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6972 switch (i
.tm
.opcode_length
)
6975 if (i
.tm
.base_opcode
& 0xff000000)
6977 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6982 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6984 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6985 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6988 if (prefix
!= REPE_PREFIX_OPCODE
6989 || (i
.prefix
[REP_PREFIX
]
6990 != REPE_PREFIX_OPCODE
))
6991 add_prefix (prefix
);
6994 add_prefix (prefix
);
7003 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7004 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7005 R_X86_64_GOTTPOFF relocation so that linker can safely
7006 perform IE->LE optimization. */
7007 if (x86_elf_abi
== X86_64_X32_ABI
7009 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7010 && i
.prefix
[REX_PREFIX
] == 0)
7011 add_prefix (REX_OPCODE
);
7014 /* The prefix bytes. */
7015 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7017 FRAG_APPEND_1_CHAR (*q
);
7021 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7026 /* REX byte is encoded in VEX prefix. */
7030 FRAG_APPEND_1_CHAR (*q
);
7033 /* There should be no other prefixes for instructions
7038 /* For EVEX instructions i.vrex should become 0 after
7039 build_evex_prefix. For VEX instructions upper 16 registers
7040 aren't available, so VREX should be 0. */
7043 /* Now the VEX prefix. */
7044 p
= frag_more (i
.vex
.length
);
7045 for (j
= 0; j
< i
.vex
.length
; j
++)
7046 p
[j
] = i
.vex
.bytes
[j
];
7049 /* Now the opcode; be careful about word order here! */
7050 if (i
.tm
.opcode_length
== 1)
7052 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7056 switch (i
.tm
.opcode_length
)
7060 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7061 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7065 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7075 /* Put out high byte first: can't use md_number_to_chars! */
7076 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7077 *p
= i
.tm
.base_opcode
& 0xff;
7080 /* Now the modrm byte and sib byte (if present). */
7081 if (i
.tm
.opcode_modifier
.modrm
)
7083 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7086 /* If i.rm.regmem == ESP (4)
7087 && i.rm.mode != (Register mode)
7089 ==> need second modrm byte. */
7090 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7092 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7093 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7095 | i
.sib
.scale
<< 6));
7098 if (i
.disp_operands
)
7099 output_disp (insn_start_frag
, insn_start_off
);
7102 output_imm (insn_start_frag
, insn_start_off
);
7108 pi ("" /*line*/, &i
);
7110 #endif /* DEBUG386 */
7113 /* Return the size of the displacement operand N. */
7116 disp_size (unsigned int n
)
7120 /* Vec_Disp8 has to be 8bit. */
7121 if (i
.types
[n
].bitfield
.vec_disp8
)
7123 else if (i
.types
[n
].bitfield
.disp64
)
7125 else if (i
.types
[n
].bitfield
.disp8
)
7127 else if (i
.types
[n
].bitfield
.disp16
)
7132 /* Return the size of the immediate operand N. */
7135 imm_size (unsigned int n
)
7138 if (i
.types
[n
].bitfield
.imm64
)
7140 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7142 else if (i
.types
[n
].bitfield
.imm16
)
7148 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7153 for (n
= 0; n
< i
.operands
; n
++)
7155 if (i
.types
[n
].bitfield
.vec_disp8
7156 || operand_type_check (i
.types
[n
], disp
))
7158 if (i
.op
[n
].disps
->X_op
== O_constant
)
7160 int size
= disp_size (n
);
7161 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7163 if (i
.types
[n
].bitfield
.vec_disp8
)
7165 val
= offset_in_range (val
, size
);
7166 p
= frag_more (size
);
7167 md_number_to_chars (p
, val
, size
);
7171 enum bfd_reloc_code_real reloc_type
;
7172 int size
= disp_size (n
);
7173 int sign
= i
.types
[n
].bitfield
.disp32s
;
7174 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7177 /* We can't have 8 bit displacement here. */
7178 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7180 /* The PC relative address is computed relative
7181 to the instruction boundary, so in case immediate
7182 fields follows, we need to adjust the value. */
7183 if (pcrel
&& i
.imm_operands
)
7188 for (n1
= 0; n1
< i
.operands
; n1
++)
7189 if (operand_type_check (i
.types
[n1
], imm
))
7191 /* Only one immediate is allowed for PC
7192 relative address. */
7193 gas_assert (sz
== 0);
7195 i
.op
[n
].disps
->X_add_number
-= sz
;
7197 /* We should find the immediate. */
7198 gas_assert (sz
!= 0);
7201 p
= frag_more (size
);
7202 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7204 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7205 && (((reloc_type
== BFD_RELOC_32
7206 || reloc_type
== BFD_RELOC_X86_64_32S
7207 || (reloc_type
== BFD_RELOC_64
7209 && (i
.op
[n
].disps
->X_op
== O_symbol
7210 || (i
.op
[n
].disps
->X_op
== O_add
7211 && ((symbol_get_value_expression
7212 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7214 || reloc_type
== BFD_RELOC_32_PCREL
))
7218 if (insn_start_frag
== frag_now
)
7219 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7224 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7225 for (fr
= insn_start_frag
->fr_next
;
7226 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7228 add
+= p
- frag_now
->fr_literal
;
7233 reloc_type
= BFD_RELOC_386_GOTPC
;
7234 i
.op
[n
].imms
->X_add_number
+= add
;
7236 else if (reloc_type
== BFD_RELOC_64
)
7237 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7239 /* Don't do the adjustment for x86-64, as there
7240 the pcrel addressing is relative to the _next_
7241 insn, and that is taken care of in other code. */
7242 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7244 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7245 size
, i
.op
[n
].disps
, pcrel
,
7247 /* Check for "call/jmp *mem", "mov mem, %reg",
7248 "test %reg, mem" and "binop mem, %reg" where binop
7249 is one of adc, add, and, cmp, or, sbb, sub, xor
7252 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7253 && ((i
.operands
== 1
7254 && i
.tm
.base_opcode
== 0xff
7255 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7257 && (i
.tm
.base_opcode
== 0x8b
7258 || i
.tm
.base_opcode
== 0x85
7259 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7263 fixP
->fx_tcbit
= i
.rex
!= 0;
7265 && (i
.base_reg
->reg_num
== RegRip
7266 || i
.base_reg
->reg_num
== RegEip
))
7267 fixP
->fx_tcbit2
= 1;
7270 fixP
->fx_tcbit2
= 1;
7278 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7283 for (n
= 0; n
< i
.operands
; n
++)
7285 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7286 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7289 if (operand_type_check (i
.types
[n
], imm
))
7291 if (i
.op
[n
].imms
->X_op
== O_constant
)
7293 int size
= imm_size (n
);
7296 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7298 p
= frag_more (size
);
7299 md_number_to_chars (p
, val
, size
);
7303 /* Not absolute_section.
7304 Need a 32-bit fixup (don't support 8bit
7305 non-absolute imms). Try to support other
7307 enum bfd_reloc_code_real reloc_type
;
7308 int size
= imm_size (n
);
7311 if (i
.types
[n
].bitfield
.imm32s
7312 && (i
.suffix
== QWORD_MNEM_SUFFIX
7313 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7318 p
= frag_more (size
);
7319 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7321 /* This is tough to explain. We end up with this one if we
7322 * have operands that look like
7323 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7324 * obtain the absolute address of the GOT, and it is strongly
7325 * preferable from a performance point of view to avoid using
7326 * a runtime relocation for this. The actual sequence of
7327 * instructions often look something like:
7332 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7334 * The call and pop essentially return the absolute address
7335 * of the label .L66 and store it in %ebx. The linker itself
7336 * will ultimately change the first operand of the addl so
7337 * that %ebx points to the GOT, but to keep things simple, the
7338 * .o file must have this operand set so that it generates not
7339 * the absolute address of .L66, but the absolute address of
7340 * itself. This allows the linker itself simply treat a GOTPC
7341 * relocation as asking for a pcrel offset to the GOT to be
7342 * added in, and the addend of the relocation is stored in the
7343 * operand field for the instruction itself.
7345 * Our job here is to fix the operand so that it would add
7346 * the correct offset so that %ebx would point to itself. The
7347 * thing that is tricky is that .-.L66 will point to the
7348 * beginning of the instruction, so we need to further modify
7349 * the operand so that it will point to itself. There are
7350 * other cases where you have something like:
7352 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7354 * and here no correction would be required. Internally in
7355 * the assembler we treat operands of this form as not being
7356 * pcrel since the '.' is explicitly mentioned, and I wonder
7357 * whether it would simplify matters to do it this way. Who
7358 * knows. In earlier versions of the PIC patches, the
7359 * pcrel_adjust field was used to store the correction, but
7360 * since the expression is not pcrel, I felt it would be
7361 * confusing to do it this way. */
7363 if ((reloc_type
== BFD_RELOC_32
7364 || reloc_type
== BFD_RELOC_X86_64_32S
7365 || reloc_type
== BFD_RELOC_64
)
7367 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7368 && (i
.op
[n
].imms
->X_op
== O_symbol
7369 || (i
.op
[n
].imms
->X_op
== O_add
7370 && ((symbol_get_value_expression
7371 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7376 if (insn_start_frag
== frag_now
)
7377 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7382 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7383 for (fr
= insn_start_frag
->fr_next
;
7384 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7386 add
+= p
- frag_now
->fr_literal
;
7390 reloc_type
= BFD_RELOC_386_GOTPC
;
7392 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7394 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7395 i
.op
[n
].imms
->X_add_number
+= add
;
7397 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7398 i
.op
[n
].imms
, 0, reloc_type
);
7404 /* x86_cons_fix_new is called via the expression parsing code when a
7405 reloc is needed. We use this hook to get the correct .got reloc. */
7406 static int cons_sign
= -1;
7409 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7410 expressionS
*exp
, bfd_reloc_code_real_type r
)
7412 r
= reloc (len
, 0, cons_sign
, r
);
7415 if (exp
->X_op
== O_secrel
)
7417 exp
->X_op
= O_symbol
;
7418 r
= BFD_RELOC_32_SECREL
;
7422 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7425 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7426 purpose of the `.dc.a' internal pseudo-op. */
7429 x86_address_bytes (void)
7431 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7433 return stdoutput
->arch_info
->bits_per_address
/ 8;
7436 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7438 # define lex_got(reloc, adjust, types) NULL
7440 /* Parse operands of the form
7441 <symbol>@GOTOFF+<nnn>
7442 and similar .plt or .got references.
7444 If we find one, set up the correct relocation in RELOC and copy the
7445 input string, minus the `@GOTOFF' into a malloc'd buffer for
7446 parsing by the calling routine. Return this buffer, and if ADJUST
7447 is non-null set it to the length of the string we removed from the
7448 input line. Otherwise return NULL. */
7450 lex_got (enum bfd_reloc_code_real
*rel
,
7452 i386_operand_type
*types
)
7454 /* Some of the relocations depend on the size of what field is to
7455 be relocated. But in our callers i386_immediate and i386_displacement
7456 we don't yet know the operand size (this will be set by insn
7457 matching). Hence we record the word32 relocation here,
7458 and adjust the reloc according to the real size in reloc(). */
7459 static const struct {
7462 const enum bfd_reloc_code_real rel
[2];
7463 const i386_operand_type types64
;
7465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7466 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7468 OPERAND_TYPE_IMM32_64
},
7470 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7471 BFD_RELOC_X86_64_PLTOFF64
},
7472 OPERAND_TYPE_IMM64
},
7473 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7474 BFD_RELOC_X86_64_PLT32
},
7475 OPERAND_TYPE_IMM32_32S_DISP32
},
7476 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7477 BFD_RELOC_X86_64_GOTPLT64
},
7478 OPERAND_TYPE_IMM64_DISP64
},
7479 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7480 BFD_RELOC_X86_64_GOTOFF64
},
7481 OPERAND_TYPE_IMM64_DISP64
},
7482 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7483 BFD_RELOC_X86_64_GOTPCREL
},
7484 OPERAND_TYPE_IMM32_32S_DISP32
},
7485 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7486 BFD_RELOC_X86_64_TLSGD
},
7487 OPERAND_TYPE_IMM32_32S_DISP32
},
7488 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7489 _dummy_first_bfd_reloc_code_real
},
7490 OPERAND_TYPE_NONE
},
7491 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7492 BFD_RELOC_X86_64_TLSLD
},
7493 OPERAND_TYPE_IMM32_32S_DISP32
},
7494 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7495 BFD_RELOC_X86_64_GOTTPOFF
},
7496 OPERAND_TYPE_IMM32_32S_DISP32
},
7497 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7498 BFD_RELOC_X86_64_TPOFF32
},
7499 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7500 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7501 _dummy_first_bfd_reloc_code_real
},
7502 OPERAND_TYPE_NONE
},
7503 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7504 BFD_RELOC_X86_64_DTPOFF32
},
7505 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7506 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7507 _dummy_first_bfd_reloc_code_real
},
7508 OPERAND_TYPE_NONE
},
7509 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7510 _dummy_first_bfd_reloc_code_real
},
7511 OPERAND_TYPE_NONE
},
7512 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7513 BFD_RELOC_X86_64_GOT32
},
7514 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7515 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7516 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7517 OPERAND_TYPE_IMM32_32S_DISP32
},
7518 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7519 BFD_RELOC_X86_64_TLSDESC_CALL
},
7520 OPERAND_TYPE_IMM32_32S_DISP32
},
7525 #if defined (OBJ_MAYBE_ELF)
7530 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7531 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7534 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7536 int len
= gotrel
[j
].len
;
7537 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7539 if (gotrel
[j
].rel
[object_64bit
] != 0)
7542 char *tmpbuf
, *past_reloc
;
7544 *rel
= gotrel
[j
].rel
[object_64bit
];
7548 if (flag_code
!= CODE_64BIT
)
7550 types
->bitfield
.imm32
= 1;
7551 types
->bitfield
.disp32
= 1;
7554 *types
= gotrel
[j
].types64
;
7557 if (j
!= 0 && GOT_symbol
== NULL
)
7558 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7560 /* The length of the first part of our input line. */
7561 first
= cp
- input_line_pointer
;
7563 /* The second part goes from after the reloc token until
7564 (and including) an end_of_line char or comma. */
7565 past_reloc
= cp
+ 1 + len
;
7567 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7569 second
= cp
+ 1 - past_reloc
;
7571 /* Allocate and copy string. The trailing NUL shouldn't
7572 be necessary, but be safe. */
7573 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7574 memcpy (tmpbuf
, input_line_pointer
, first
);
7575 if (second
!= 0 && *past_reloc
!= ' ')
7576 /* Replace the relocation token with ' ', so that
7577 errors like foo@GOTOFF1 will be detected. */
7578 tmpbuf
[first
++] = ' ';
7580 /* Increment length by 1 if the relocation token is
7585 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7586 tmpbuf
[first
+ second
] = '\0';
7590 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7591 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7596 /* Might be a symbol version string. Don't as_bad here. */
7605 /* Parse operands of the form
7606 <symbol>@SECREL32+<nnn>
7608 If we find one, set up the correct relocation in RELOC and copy the
7609 input string, minus the `@SECREL32' into a malloc'd buffer for
7610 parsing by the calling routine. Return this buffer, and if ADJUST
7611 is non-null set it to the length of the string we removed from the
7612 input line. Otherwise return NULL.
7614 This function is copied from the ELF version above adjusted for PE targets. */
7617 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7618 int *adjust ATTRIBUTE_UNUSED
,
7619 i386_operand_type
*types
)
7625 const enum bfd_reloc_code_real rel
[2];
7626 const i386_operand_type types64
;
7630 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7631 BFD_RELOC_32_SECREL
},
7632 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7638 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7639 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7642 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7644 int len
= gotrel
[j
].len
;
7646 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7648 if (gotrel
[j
].rel
[object_64bit
] != 0)
7651 char *tmpbuf
, *past_reloc
;
7653 *rel
= gotrel
[j
].rel
[object_64bit
];
7659 if (flag_code
!= CODE_64BIT
)
7661 types
->bitfield
.imm32
= 1;
7662 types
->bitfield
.disp32
= 1;
7665 *types
= gotrel
[j
].types64
;
7668 /* The length of the first part of our input line. */
7669 first
= cp
- input_line_pointer
;
7671 /* The second part goes from after the reloc token until
7672 (and including) an end_of_line char or comma. */
7673 past_reloc
= cp
+ 1 + len
;
7675 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7677 second
= cp
+ 1 - past_reloc
;
7679 /* Allocate and copy string. The trailing NUL shouldn't
7680 be necessary, but be safe. */
7681 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7682 memcpy (tmpbuf
, input_line_pointer
, first
);
7683 if (second
!= 0 && *past_reloc
!= ' ')
7684 /* Replace the relocation token with ' ', so that
7685 errors like foo@SECLREL321 will be detected. */
7686 tmpbuf
[first
++] = ' ';
7687 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7688 tmpbuf
[first
+ second
] = '\0';
7692 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7693 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7698 /* Might be a symbol version string. Don't as_bad here. */
7704 bfd_reloc_code_real_type
7705 x86_cons (expressionS
*exp
, int size
)
7707 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7709 intel_syntax
= -intel_syntax
;
7712 if (size
== 4 || (object_64bit
&& size
== 8))
7714 /* Handle @GOTOFF and the like in an expression. */
7716 char *gotfree_input_line
;
7719 save
= input_line_pointer
;
7720 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7721 if (gotfree_input_line
)
7722 input_line_pointer
= gotfree_input_line
;
7726 if (gotfree_input_line
)
7728 /* expression () has merrily parsed up to the end of line,
7729 or a comma - in the wrong buffer. Transfer how far
7730 input_line_pointer has moved to the right buffer. */
7731 input_line_pointer
= (save
7732 + (input_line_pointer
- gotfree_input_line
)
7734 free (gotfree_input_line
);
7735 if (exp
->X_op
== O_constant
7736 || exp
->X_op
== O_absent
7737 || exp
->X_op
== O_illegal
7738 || exp
->X_op
== O_register
7739 || exp
->X_op
== O_big
)
7741 char c
= *input_line_pointer
;
7742 *input_line_pointer
= 0;
7743 as_bad (_("missing or invalid expression `%s'"), save
);
7744 *input_line_pointer
= c
;
7751 intel_syntax
= -intel_syntax
;
7754 i386_intel_simplify (exp
);
7760 signed_cons (int size
)
7762 if (flag_code
== CODE_64BIT
)
7770 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7777 if (exp
.X_op
== O_symbol
)
7778 exp
.X_op
= O_secrel
;
7780 emit_expr (&exp
, 4);
7782 while (*input_line_pointer
++ == ',');
7784 input_line_pointer
--;
7785 demand_empty_rest_of_line ();
7789 /* Handle Vector operations. */
7792 check_VecOperations (char *op_string
, char *op_end
)
7794 const reg_entry
*mask
;
7799 && (op_end
== NULL
|| op_string
< op_end
))
7802 if (*op_string
== '{')
7806 /* Check broadcasts. */
7807 if (strncmp (op_string
, "1to", 3) == 0)
7812 goto duplicated_vec_op
;
7815 if (*op_string
== '8')
7816 bcst_type
= BROADCAST_1TO8
;
7817 else if (*op_string
== '4')
7818 bcst_type
= BROADCAST_1TO4
;
7819 else if (*op_string
== '2')
7820 bcst_type
= BROADCAST_1TO2
;
7821 else if (*op_string
== '1'
7822 && *(op_string
+1) == '6')
7824 bcst_type
= BROADCAST_1TO16
;
7829 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7834 broadcast_op
.type
= bcst_type
;
7835 broadcast_op
.operand
= this_operand
;
7836 i
.broadcast
= &broadcast_op
;
7838 /* Check masking operation. */
7839 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7841 /* k0 can't be used for write mask. */
7842 if (mask
->reg_num
== 0)
7844 as_bad (_("`%s' can't be used for write mask"),
7851 mask_op
.mask
= mask
;
7852 mask_op
.zeroing
= 0;
7853 mask_op
.operand
= this_operand
;
7859 goto duplicated_vec_op
;
7861 i
.mask
->mask
= mask
;
7863 /* Only "{z}" is allowed here. No need to check
7864 zeroing mask explicitly. */
7865 if (i
.mask
->operand
!= this_operand
)
7867 as_bad (_("invalid write mask `%s'"), saved
);
7874 /* Check zeroing-flag for masking operation. */
7875 else if (*op_string
== 'z')
7879 mask_op
.mask
= NULL
;
7880 mask_op
.zeroing
= 1;
7881 mask_op
.operand
= this_operand
;
7886 if (i
.mask
->zeroing
)
7889 as_bad (_("duplicated `%s'"), saved
);
7893 i
.mask
->zeroing
= 1;
7895 /* Only "{%k}" is allowed here. No need to check mask
7896 register explicitly. */
7897 if (i
.mask
->operand
!= this_operand
)
7899 as_bad (_("invalid zeroing-masking `%s'"),
7908 goto unknown_vec_op
;
7910 if (*op_string
!= '}')
7912 as_bad (_("missing `}' in `%s'"), saved
);
7919 /* We don't know this one. */
7920 as_bad (_("unknown vector operation: `%s'"), saved
);
7928 i386_immediate (char *imm_start
)
7930 char *save_input_line_pointer
;
7931 char *gotfree_input_line
;
7934 i386_operand_type types
;
7936 operand_type_set (&types
, ~0);
7938 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7940 as_bad (_("at most %d immediate operands are allowed"),
7941 MAX_IMMEDIATE_OPERANDS
);
7945 exp
= &im_expressions
[i
.imm_operands
++];
7946 i
.op
[this_operand
].imms
= exp
;
7948 if (is_space_char (*imm_start
))
7951 save_input_line_pointer
= input_line_pointer
;
7952 input_line_pointer
= imm_start
;
7954 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
7955 if (gotfree_input_line
)
7956 input_line_pointer
= gotfree_input_line
;
7958 exp_seg
= expression (exp
);
7962 /* Handle vector operations. */
7963 if (*input_line_pointer
== '{')
7965 input_line_pointer
= check_VecOperations (input_line_pointer
,
7967 if (input_line_pointer
== NULL
)
7971 if (*input_line_pointer
)
7972 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7974 input_line_pointer
= save_input_line_pointer
;
7975 if (gotfree_input_line
)
7977 free (gotfree_input_line
);
7979 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7980 exp
->X_op
= O_illegal
;
7983 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7987 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7988 i386_operand_type types
, const char *imm_start
)
7990 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7993 as_bad (_("missing or invalid immediate expression `%s'"),
7997 else if (exp
->X_op
== O_constant
)
7999 /* Size it properly later. */
8000 i
.types
[this_operand
].bitfield
.imm64
= 1;
8001 /* If not 64bit, sign extend val. */
8002 if (flag_code
!= CODE_64BIT
8003 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8005 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8007 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8008 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8009 && exp_seg
!= absolute_section
8010 && exp_seg
!= text_section
8011 && exp_seg
!= data_section
8012 && exp_seg
!= bss_section
8013 && exp_seg
!= undefined_section
8014 && !bfd_is_com_section (exp_seg
))
8016 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8020 else if (!intel_syntax
&& exp_seg
== reg_section
)
8023 as_bad (_("illegal immediate register operand %s"), imm_start
);
8028 /* This is an address. The size of the address will be
8029 determined later, depending on destination register,
8030 suffix, or the default for the section. */
8031 i
.types
[this_operand
].bitfield
.imm8
= 1;
8032 i
.types
[this_operand
].bitfield
.imm16
= 1;
8033 i
.types
[this_operand
].bitfield
.imm32
= 1;
8034 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8035 i
.types
[this_operand
].bitfield
.imm64
= 1;
8036 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8044 i386_scale (char *scale
)
8047 char *save
= input_line_pointer
;
8049 input_line_pointer
= scale
;
8050 val
= get_absolute_expression ();
8055 i
.log2_scale_factor
= 0;
8058 i
.log2_scale_factor
= 1;
8061 i
.log2_scale_factor
= 2;
8064 i
.log2_scale_factor
= 3;
8068 char sep
= *input_line_pointer
;
8070 *input_line_pointer
= '\0';
8071 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8073 *input_line_pointer
= sep
;
8074 input_line_pointer
= save
;
8078 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8080 as_warn (_("scale factor of %d without an index register"),
8081 1 << i
.log2_scale_factor
);
8082 i
.log2_scale_factor
= 0;
8084 scale
= input_line_pointer
;
8085 input_line_pointer
= save
;
8090 i386_displacement (char *disp_start
, char *disp_end
)
8094 char *save_input_line_pointer
;
8095 char *gotfree_input_line
;
8097 i386_operand_type bigdisp
, types
= anydisp
;
8100 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8102 as_bad (_("at most %d displacement operands are allowed"),
8103 MAX_MEMORY_OPERANDS
);
8107 operand_type_set (&bigdisp
, 0);
8108 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8109 || (!current_templates
->start
->opcode_modifier
.jump
8110 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8112 bigdisp
.bitfield
.disp32
= 1;
8113 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8114 if (flag_code
== CODE_64BIT
)
8118 bigdisp
.bitfield
.disp32s
= 1;
8119 bigdisp
.bitfield
.disp64
= 1;
8122 else if ((flag_code
== CODE_16BIT
) ^ override
)
8124 bigdisp
.bitfield
.disp32
= 0;
8125 bigdisp
.bitfield
.disp16
= 1;
8130 /* For PC-relative branches, the width of the displacement
8131 is dependent upon data size, not address size. */
8132 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8133 if (flag_code
== CODE_64BIT
)
8135 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8136 bigdisp
.bitfield
.disp16
= 1;
8139 bigdisp
.bitfield
.disp32
= 1;
8140 bigdisp
.bitfield
.disp32s
= 1;
8146 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8148 : LONG_MNEM_SUFFIX
));
8149 bigdisp
.bitfield
.disp32
= 1;
8150 if ((flag_code
== CODE_16BIT
) ^ override
)
8152 bigdisp
.bitfield
.disp32
= 0;
8153 bigdisp
.bitfield
.disp16
= 1;
8157 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8160 exp
= &disp_expressions
[i
.disp_operands
];
8161 i
.op
[this_operand
].disps
= exp
;
8163 save_input_line_pointer
= input_line_pointer
;
8164 input_line_pointer
= disp_start
;
8165 END_STRING_AND_SAVE (disp_end
);
8167 #ifndef GCC_ASM_O_HACK
8168 #define GCC_ASM_O_HACK 0
8171 END_STRING_AND_SAVE (disp_end
+ 1);
8172 if (i
.types
[this_operand
].bitfield
.baseIndex
8173 && displacement_string_end
[-1] == '+')
8175 /* This hack is to avoid a warning when using the "o"
8176 constraint within gcc asm statements.
8179 #define _set_tssldt_desc(n,addr,limit,type) \
8180 __asm__ __volatile__ ( \
8182 "movw %w1,2+%0\n\t" \
8184 "movb %b1,4+%0\n\t" \
8185 "movb %4,5+%0\n\t" \
8186 "movb $0,6+%0\n\t" \
8187 "movb %h1,7+%0\n\t" \
8189 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8191 This works great except that the output assembler ends
8192 up looking a bit weird if it turns out that there is
8193 no offset. You end up producing code that looks like:
8206 So here we provide the missing zero. */
8208 *displacement_string_end
= '0';
8211 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8212 if (gotfree_input_line
)
8213 input_line_pointer
= gotfree_input_line
;
8215 exp_seg
= expression (exp
);
8218 if (*input_line_pointer
)
8219 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8221 RESTORE_END_STRING (disp_end
+ 1);
8223 input_line_pointer
= save_input_line_pointer
;
8224 if (gotfree_input_line
)
8226 free (gotfree_input_line
);
8228 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8229 exp
->X_op
= O_illegal
;
8232 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8234 RESTORE_END_STRING (disp_end
);
8240 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8241 i386_operand_type types
, const char *disp_start
)
8243 i386_operand_type bigdisp
;
8246 /* We do this to make sure that the section symbol is in
8247 the symbol table. We will ultimately change the relocation
8248 to be relative to the beginning of the section. */
8249 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8250 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8251 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8253 if (exp
->X_op
!= O_symbol
)
8256 if (S_IS_LOCAL (exp
->X_add_symbol
)
8257 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8258 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8259 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8260 exp
->X_op
= O_subtract
;
8261 exp
->X_op_symbol
= GOT_symbol
;
8262 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8263 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8264 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8265 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8267 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8270 else if (exp
->X_op
== O_absent
8271 || exp
->X_op
== O_illegal
8272 || exp
->X_op
== O_big
)
8275 as_bad (_("missing or invalid displacement expression `%s'"),
8280 else if (flag_code
== CODE_64BIT
8281 && !i
.prefix
[ADDR_PREFIX
]
8282 && exp
->X_op
== O_constant
)
8284 /* Since displacement is signed extended to 64bit, don't allow
8285 disp32 and turn off disp32s if they are out of range. */
8286 i
.types
[this_operand
].bitfield
.disp32
= 0;
8287 if (!fits_in_signed_long (exp
->X_add_number
))
8289 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8290 if (i
.types
[this_operand
].bitfield
.baseindex
)
8292 as_bad (_("0x%lx out range of signed 32bit displacement"),
8293 (long) exp
->X_add_number
);
8299 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8300 else if (exp
->X_op
!= O_constant
8301 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8302 && exp_seg
!= absolute_section
8303 && exp_seg
!= text_section
8304 && exp_seg
!= data_section
8305 && exp_seg
!= bss_section
8306 && exp_seg
!= undefined_section
8307 && !bfd_is_com_section (exp_seg
))
8309 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8314 /* Check if this is a displacement only operand. */
8315 bigdisp
= i
.types
[this_operand
];
8316 bigdisp
.bitfield
.disp8
= 0;
8317 bigdisp
.bitfield
.disp16
= 0;
8318 bigdisp
.bitfield
.disp32
= 0;
8319 bigdisp
.bitfield
.disp32s
= 0;
8320 bigdisp
.bitfield
.disp64
= 0;
8321 if (operand_type_all_zero (&bigdisp
))
8322 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8328 /* Make sure the memory operand we've been dealt is valid.
8329 Return 1 on success, 0 on a failure. */
8332 i386_index_check (const char *operand_string
)
8334 const char *kind
= "base/index";
8335 enum flag_code addr_mode
;
8337 if (i
.prefix
[ADDR_PREFIX
])
8338 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8341 addr_mode
= flag_code
;
8343 #if INFER_ADDR_PREFIX
8344 if (i
.mem_operands
== 0)
8346 /* Infer address prefix from the first memory operand. */
8347 const reg_entry
*addr_reg
= i
.base_reg
;
8349 if (addr_reg
== NULL
)
8350 addr_reg
= i
.index_reg
;
8354 if (addr_reg
->reg_num
== RegEip
8355 || addr_reg
->reg_num
== RegEiz
8356 || addr_reg
->reg_type
.bitfield
.reg32
)
8357 addr_mode
= CODE_32BIT
;
8358 else if (flag_code
!= CODE_64BIT
8359 && addr_reg
->reg_type
.bitfield
.reg16
)
8360 addr_mode
= CODE_16BIT
;
8362 if (addr_mode
!= flag_code
)
8364 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8366 /* Change the size of any displacement too. At most one
8367 of Disp16 or Disp32 is set.
8368 FIXME. There doesn't seem to be any real need for
8369 separate Disp16 and Disp32 flags. The same goes for
8370 Imm16 and Imm32. Removing them would probably clean
8371 up the code quite a lot. */
8372 if (flag_code
!= CODE_64BIT
8373 && (i
.types
[this_operand
].bitfield
.disp16
8374 || i
.types
[this_operand
].bitfield
.disp32
))
8375 i
.types
[this_operand
]
8376 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8383 if (current_templates
->start
->opcode_modifier
.isstring
8384 && !current_templates
->start
->opcode_modifier
.immext
8385 && (current_templates
->end
[-1].opcode_modifier
.isstring
8388 /* Memory operands of string insns are special in that they only allow
8389 a single register (rDI, rSI, or rBX) as their memory address. */
8390 const reg_entry
*expected_reg
;
8391 static const char *di_si
[][2] =
8397 static const char *bx
[] = { "ebx", "bx", "rbx" };
8399 kind
= "string address";
8401 if (current_templates
->start
->opcode_modifier
.w
)
8403 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8405 if (!type
.bitfield
.baseindex
8406 || ((!i
.mem_operands
!= !intel_syntax
)
8407 && current_templates
->end
[-1].operand_types
[1]
8408 .bitfield
.baseindex
))
8409 type
= current_templates
->end
[-1].operand_types
[1];
8410 expected_reg
= hash_find (reg_hash
,
8411 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8415 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8417 if (i
.base_reg
!= expected_reg
8419 || operand_type_check (i
.types
[this_operand
], disp
))
8421 /* The second memory operand must have the same size as
8425 && !((addr_mode
== CODE_64BIT
8426 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8427 || (addr_mode
== CODE_32BIT
8428 ? i
.base_reg
->reg_type
.bitfield
.reg32
8429 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8432 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8434 intel_syntax
? '[' : '(',
8436 expected_reg
->reg_name
,
8437 intel_syntax
? ']' : ')');
8444 as_bad (_("`%s' is not a valid %s expression"),
8445 operand_string
, kind
);
8450 if (addr_mode
!= CODE_16BIT
)
8452 /* 32-bit/64-bit checks. */
8454 && (addr_mode
== CODE_64BIT
8455 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8456 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8458 || (i
.base_reg
->reg_num
8459 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8461 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8462 && !i
.index_reg
->reg_type
.bitfield
.regymm
8463 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8464 && ((addr_mode
== CODE_64BIT
8465 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8466 || i
.index_reg
->reg_num
== RegRiz
)
8467 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8468 || i
.index_reg
->reg_num
== RegEiz
))
8469 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8474 /* 16-bit checks. */
8476 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8477 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8479 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8480 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8482 && i
.base_reg
->reg_num
< 6
8483 && i
.index_reg
->reg_num
>= 6
8484 && i
.log2_scale_factor
== 0))))
8491 /* Handle vector immediates. */
8494 RC_SAE_immediate (const char *imm_start
)
8496 unsigned int match_found
, j
;
8497 const char *pstr
= imm_start
;
8505 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8507 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8511 rc_op
.type
= RC_NamesTable
[j
].type
;
8512 rc_op
.operand
= this_operand
;
8513 i
.rounding
= &rc_op
;
8517 as_bad (_("duplicated `%s'"), imm_start
);
8520 pstr
+= RC_NamesTable
[j
].len
;
8530 as_bad (_("Missing '}': '%s'"), imm_start
);
8533 /* RC/SAE immediate string should contain nothing more. */;
8536 as_bad (_("Junk after '}': '%s'"), imm_start
);
8540 exp
= &im_expressions
[i
.imm_operands
++];
8541 i
.op
[this_operand
].imms
= exp
;
8543 exp
->X_op
= O_constant
;
8544 exp
->X_add_number
= 0;
8545 exp
->X_add_symbol
= (symbolS
*) 0;
8546 exp
->X_op_symbol
= (symbolS
*) 0;
8548 i
.types
[this_operand
].bitfield
.imm8
= 1;
8552 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8556 i386_att_operand (char *operand_string
)
8560 char *op_string
= operand_string
;
8562 if (is_space_char (*op_string
))
8565 /* We check for an absolute prefix (differentiating,
8566 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8567 if (*op_string
== ABSOLUTE_PREFIX
)
8570 if (is_space_char (*op_string
))
8572 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8575 /* Check if operand is a register. */
8576 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8578 i386_operand_type temp
;
8580 /* Check for a segment override by searching for ':' after a
8581 segment register. */
8583 if (is_space_char (*op_string
))
8585 if (*op_string
== ':'
8586 && (r
->reg_type
.bitfield
.sreg2
8587 || r
->reg_type
.bitfield
.sreg3
))
8592 i
.seg
[i
.mem_operands
] = &es
;
8595 i
.seg
[i
.mem_operands
] = &cs
;
8598 i
.seg
[i
.mem_operands
] = &ss
;
8601 i
.seg
[i
.mem_operands
] = &ds
;
8604 i
.seg
[i
.mem_operands
] = &fs
;
8607 i
.seg
[i
.mem_operands
] = &gs
;
8611 /* Skip the ':' and whitespace. */
8613 if (is_space_char (*op_string
))
8616 if (!is_digit_char (*op_string
)
8617 && !is_identifier_char (*op_string
)
8618 && *op_string
!= '('
8619 && *op_string
!= ABSOLUTE_PREFIX
)
8621 as_bad (_("bad memory operand `%s'"), op_string
);
8624 /* Handle case of %es:*foo. */
8625 if (*op_string
== ABSOLUTE_PREFIX
)
8628 if (is_space_char (*op_string
))
8630 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8632 goto do_memory_reference
;
8635 /* Handle vector operations. */
8636 if (*op_string
== '{')
8638 op_string
= check_VecOperations (op_string
, NULL
);
8639 if (op_string
== NULL
)
8645 as_bad (_("junk `%s' after register"), op_string
);
8649 temp
.bitfield
.baseindex
= 0;
8650 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8652 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8653 i
.op
[this_operand
].regs
= r
;
8656 else if (*op_string
== REGISTER_PREFIX
)
8658 as_bad (_("bad register name `%s'"), op_string
);
8661 else if (*op_string
== IMMEDIATE_PREFIX
)
8664 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8666 as_bad (_("immediate operand illegal with absolute jump"));
8669 if (!i386_immediate (op_string
))
8672 else if (RC_SAE_immediate (operand_string
))
8674 /* If it is a RC or SAE immediate, do nothing. */
8677 else if (is_digit_char (*op_string
)
8678 || is_identifier_char (*op_string
)
8679 || *op_string
== '"'
8680 || *op_string
== '(')
8682 /* This is a memory reference of some sort. */
8685 /* Start and end of displacement string expression (if found). */
8686 char *displacement_string_start
;
8687 char *displacement_string_end
;
8690 do_memory_reference
:
8691 if ((i
.mem_operands
== 1
8692 && !current_templates
->start
->opcode_modifier
.isstring
)
8693 || i
.mem_operands
== 2)
8695 as_bad (_("too many memory references for `%s'"),
8696 current_templates
->start
->name
);
8700 /* Check for base index form. We detect the base index form by
8701 looking for an ')' at the end of the operand, searching
8702 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8704 base_string
= op_string
+ strlen (op_string
);
8706 /* Handle vector operations. */
8707 vop_start
= strchr (op_string
, '{');
8708 if (vop_start
&& vop_start
< base_string
)
8710 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8712 base_string
= vop_start
;
8716 if (is_space_char (*base_string
))
8719 /* If we only have a displacement, set-up for it to be parsed later. */
8720 displacement_string_start
= op_string
;
8721 displacement_string_end
= base_string
+ 1;
8723 if (*base_string
== ')')
8726 unsigned int parens_balanced
= 1;
8727 /* We've already checked that the number of left & right ()'s are
8728 equal, so this loop will not be infinite. */
8732 if (*base_string
== ')')
8734 if (*base_string
== '(')
8737 while (parens_balanced
);
8739 temp_string
= base_string
;
8741 /* Skip past '(' and whitespace. */
8743 if (is_space_char (*base_string
))
8746 if (*base_string
== ','
8747 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8750 displacement_string_end
= temp_string
;
8752 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8756 base_string
= end_op
;
8757 if (is_space_char (*base_string
))
8761 /* There may be an index reg or scale factor here. */
8762 if (*base_string
== ',')
8765 if (is_space_char (*base_string
))
8768 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8771 base_string
= end_op
;
8772 if (is_space_char (*base_string
))
8774 if (*base_string
== ',')
8777 if (is_space_char (*base_string
))
8780 else if (*base_string
!= ')')
8782 as_bad (_("expecting `,' or `)' "
8783 "after index register in `%s'"),
8788 else if (*base_string
== REGISTER_PREFIX
)
8790 end_op
= strchr (base_string
, ',');
8793 as_bad (_("bad register name `%s'"), base_string
);
8797 /* Check for scale factor. */
8798 if (*base_string
!= ')')
8800 char *end_scale
= i386_scale (base_string
);
8805 base_string
= end_scale
;
8806 if (is_space_char (*base_string
))
8808 if (*base_string
!= ')')
8810 as_bad (_("expecting `)' "
8811 "after scale factor in `%s'"),
8816 else if (!i
.index_reg
)
8818 as_bad (_("expecting index register or scale factor "
8819 "after `,'; got '%c'"),
8824 else if (*base_string
!= ')')
8826 as_bad (_("expecting `,' or `)' "
8827 "after base register in `%s'"),
8832 else if (*base_string
== REGISTER_PREFIX
)
8834 end_op
= strchr (base_string
, ',');
8837 as_bad (_("bad register name `%s'"), base_string
);
8842 /* If there's an expression beginning the operand, parse it,
8843 assuming displacement_string_start and
8844 displacement_string_end are meaningful. */
8845 if (displacement_string_start
!= displacement_string_end
)
8847 if (!i386_displacement (displacement_string_start
,
8848 displacement_string_end
))
8852 /* Special case for (%dx) while doing input/output op. */
8854 && operand_type_equal (&i
.base_reg
->reg_type
,
8855 ®16_inoutportreg
)
8857 && i
.log2_scale_factor
== 0
8858 && i
.seg
[i
.mem_operands
] == 0
8859 && !operand_type_check (i
.types
[this_operand
], disp
))
8861 i
.types
[this_operand
] = inoutportreg
;
8865 if (i386_index_check (operand_string
) == 0)
8867 i
.types
[this_operand
].bitfield
.mem
= 1;
8872 /* It's not a memory operand; argh! */
8873 as_bad (_("invalid char %s beginning operand %d `%s'"),
8874 output_invalid (*op_string
),
8879 return 1; /* Normal return. */
8882 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8883 that an rs_machine_dependent frag may reach. */
8886 i386_frag_max_var (fragS
*frag
)
8888 /* The only relaxable frags are for jumps.
8889 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8890 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8891 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8894 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8896 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8898 /* STT_GNU_IFUNC symbol must go through PLT. */
8899 if ((symbol_get_bfdsym (fr_symbol
)->flags
8900 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8903 if (!S_IS_EXTERNAL (fr_symbol
))
8904 /* Symbol may be weak or local. */
8905 return !S_IS_WEAK (fr_symbol
);
8907 /* Global symbols with non-default visibility can't be preempted. */
8908 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
8911 if (fr_var
!= NO_RELOC
)
8912 switch ((enum bfd_reloc_code_real
) fr_var
)
8914 case BFD_RELOC_386_PLT32
:
8915 case BFD_RELOC_X86_64_PLT32
:
8916 /* Symbol with PLT relocatin may be preempted. */
8922 /* Global symbols with default visibility in a shared library may be
8923 preempted by another definition. */
8928 /* md_estimate_size_before_relax()
8930 Called just before relax() for rs_machine_dependent frags. The x86
8931 assembler uses these frags to handle variable size jump
8934 Any symbol that is now undefined will not become defined.
8935 Return the correct fr_subtype in the frag.
8936 Return the initial "guess for variable size of frag" to caller.
8937 The guess is actually the growth beyond the fixed part. Whatever
8938 we do to grow the fixed or variable part contributes to our
8942 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8944 /* We've already got fragP->fr_subtype right; all we have to do is
8945 check for un-relaxable symbols. On an ELF system, we can't relax
8946 an externally visible symbol, because it may be overridden by a
8948 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8951 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
8954 #if defined (OBJ_COFF) && defined (TE_PE)
8955 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8956 && S_IS_WEAK (fragP
->fr_symbol
))
8960 /* Symbol is undefined in this segment, or we need to keep a
8961 reloc so that weak symbols can be overridden. */
8962 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8963 enum bfd_reloc_code_real reloc_type
;
8964 unsigned char *opcode
;
8967 if (fragP
->fr_var
!= NO_RELOC
)
8968 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8970 reloc_type
= BFD_RELOC_16_PCREL
;
8972 reloc_type
= BFD_RELOC_32_PCREL
;
8974 old_fr_fix
= fragP
->fr_fix
;
8975 opcode
= (unsigned char *) fragP
->fr_opcode
;
8977 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8980 /* Make jmp (0xeb) a (d)word displacement jump. */
8982 fragP
->fr_fix
+= size
;
8983 fix_new (fragP
, old_fr_fix
, size
,
8985 fragP
->fr_offset
, 1,
8991 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8993 /* Negate the condition, and branch past an
8994 unconditional jump. */
8997 /* Insert an unconditional jump. */
8999 /* We added two extra opcode bytes, and have a two byte
9001 fragP
->fr_fix
+= 2 + 2;
9002 fix_new (fragP
, old_fr_fix
+ 2, 2,
9004 fragP
->fr_offset
, 1,
9011 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9016 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9018 fragP
->fr_offset
, 1,
9020 fixP
->fx_signed
= 1;
9024 /* This changes the byte-displacement jump 0x7N
9025 to the (d)word-displacement jump 0x0f,0x8N. */
9026 opcode
[1] = opcode
[0] + 0x10;
9027 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9028 /* We've added an opcode byte. */
9029 fragP
->fr_fix
+= 1 + size
;
9030 fix_new (fragP
, old_fr_fix
+ 1, size
,
9032 fragP
->fr_offset
, 1,
9037 BAD_CASE (fragP
->fr_subtype
);
9041 return fragP
->fr_fix
- old_fr_fix
;
9044 /* Guess size depending on current relax state. Initially the relax
9045 state will correspond to a short jump and we return 1, because
9046 the variable part of the frag (the branch offset) is one byte
9047 long. However, we can relax a section more than once and in that
9048 case we must either set fr_subtype back to the unrelaxed state,
9049 or return the value for the appropriate branch. */
9050 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9053 /* Called after relax() is finished.
9055 In: Address of frag.
9056 fr_type == rs_machine_dependent.
9057 fr_subtype is what the address relaxed to.
9059 Out: Any fixSs and constants are set up.
9060 Caller will turn frag into a ".space 0". */
9063 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9066 unsigned char *opcode
;
9067 unsigned char *where_to_put_displacement
= NULL
;
9068 offsetT target_address
;
9069 offsetT opcode_address
;
9070 unsigned int extension
= 0;
9071 offsetT displacement_from_opcode_start
;
9073 opcode
= (unsigned char *) fragP
->fr_opcode
;
9075 /* Address we want to reach in file space. */
9076 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9078 /* Address opcode resides at in file space. */
9079 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9081 /* Displacement from opcode start to fill into instruction. */
9082 displacement_from_opcode_start
= target_address
- opcode_address
;
9084 if ((fragP
->fr_subtype
& BIG
) == 0)
9086 /* Don't have to change opcode. */
9087 extension
= 1; /* 1 opcode + 1 displacement */
9088 where_to_put_displacement
= &opcode
[1];
9092 if (no_cond_jump_promotion
9093 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9094 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9095 _("long jump required"));
9097 switch (fragP
->fr_subtype
)
9099 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9100 extension
= 4; /* 1 opcode + 4 displacement */
9102 where_to_put_displacement
= &opcode
[1];
9105 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9106 extension
= 2; /* 1 opcode + 2 displacement */
9108 where_to_put_displacement
= &opcode
[1];
9111 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9112 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9113 extension
= 5; /* 2 opcode + 4 displacement */
9114 opcode
[1] = opcode
[0] + 0x10;
9115 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9116 where_to_put_displacement
= &opcode
[2];
9119 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9120 extension
= 3; /* 2 opcode + 2 displacement */
9121 opcode
[1] = opcode
[0] + 0x10;
9122 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9123 where_to_put_displacement
= &opcode
[2];
9126 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9131 where_to_put_displacement
= &opcode
[3];
9135 BAD_CASE (fragP
->fr_subtype
);
9140 /* If size if less then four we are sure that the operand fits,
9141 but if it's 4, then it could be that the displacement is larger
9143 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9145 && ((addressT
) (displacement_from_opcode_start
- extension
9146 + ((addressT
) 1 << 31))
9147 > (((addressT
) 2 << 31) - 1)))
9149 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9150 _("jump target out of range"));
9151 /* Make us emit 0. */
9152 displacement_from_opcode_start
= extension
;
9154 /* Now put displacement after opcode. */
9155 md_number_to_chars ((char *) where_to_put_displacement
,
9156 (valueT
) (displacement_from_opcode_start
- extension
),
9157 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9158 fragP
->fr_fix
+= extension
;
9161 /* Apply a fixup (fixP) to segment data, once it has been determined
9162 by our caller that we have all the info we need to fix it up.
9164 Parameter valP is the pointer to the value of the bits.
9166 On the 386, immediates, displacements, and data pointers are all in
9167 the same (little-endian) format, so we don't need to care about which
9171 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9173 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9174 valueT value
= *valP
;
9176 #if !defined (TE_Mach)
9179 switch (fixP
->fx_r_type
)
9185 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9188 case BFD_RELOC_X86_64_32S
:
9189 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9192 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9195 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9200 if (fixP
->fx_addsy
!= NULL
9201 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9202 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9203 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9204 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9205 && !use_rela_relocations
)
9207 /* This is a hack. There should be a better way to handle this.
9208 This covers for the fact that bfd_install_relocation will
9209 subtract the current location (for partial_inplace, PC relative
9210 relocations); see more below. */
9214 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9217 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9222 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9225 || (symbol_section_p (fixP
->fx_addsy
)
9226 && sym_seg
!= absolute_section
))
9227 && !generic_force_reloc (fixP
))
9229 /* Yes, we add the values in twice. This is because
9230 bfd_install_relocation subtracts them out again. I think
9231 bfd_install_relocation is broken, but I don't dare change
9233 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9237 #if defined (OBJ_COFF) && defined (TE_PE)
9238 /* For some reason, the PE format does not store a
9239 section address offset for a PC relative symbol. */
9240 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9241 || S_IS_WEAK (fixP
->fx_addsy
))
9242 value
+= md_pcrel_from (fixP
);
9245 #if defined (OBJ_COFF) && defined (TE_PE)
9246 if (fixP
->fx_addsy
!= NULL
9247 && S_IS_WEAK (fixP
->fx_addsy
)
9248 /* PR 16858: Do not modify weak function references. */
9249 && ! fixP
->fx_pcrel
)
9251 #if !defined (TE_PEP)
9252 /* For x86 PE weak function symbols are neither PC-relative
9253 nor do they set S_IS_FUNCTION. So the only reliable way
9254 to detect them is to check the flags of their containing
9256 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9257 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9261 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9265 /* Fix a few things - the dynamic linker expects certain values here,
9266 and we must not disappoint it. */
9267 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9268 if (IS_ELF
&& fixP
->fx_addsy
)
9269 switch (fixP
->fx_r_type
)
9271 case BFD_RELOC_386_PLT32
:
9272 case BFD_RELOC_X86_64_PLT32
:
9273 /* Make the jump instruction point to the address of the operand. At
9274 runtime we merely add the offset to the actual PLT entry. */
9278 case BFD_RELOC_386_TLS_GD
:
9279 case BFD_RELOC_386_TLS_LDM
:
9280 case BFD_RELOC_386_TLS_IE_32
:
9281 case BFD_RELOC_386_TLS_IE
:
9282 case BFD_RELOC_386_TLS_GOTIE
:
9283 case BFD_RELOC_386_TLS_GOTDESC
:
9284 case BFD_RELOC_X86_64_TLSGD
:
9285 case BFD_RELOC_X86_64_TLSLD
:
9286 case BFD_RELOC_X86_64_GOTTPOFF
:
9287 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9288 value
= 0; /* Fully resolved at runtime. No addend. */
9290 case BFD_RELOC_386_TLS_LE
:
9291 case BFD_RELOC_386_TLS_LDO_32
:
9292 case BFD_RELOC_386_TLS_LE_32
:
9293 case BFD_RELOC_X86_64_DTPOFF32
:
9294 case BFD_RELOC_X86_64_DTPOFF64
:
9295 case BFD_RELOC_X86_64_TPOFF32
:
9296 case BFD_RELOC_X86_64_TPOFF64
:
9297 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9300 case BFD_RELOC_386_TLS_DESC_CALL
:
9301 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9302 value
= 0; /* Fully resolved at runtime. No addend. */
9303 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9307 case BFD_RELOC_386_GOT32
:
9308 case BFD_RELOC_X86_64_GOT32
:
9309 value
= 0; /* Fully resolved at runtime. No addend. */
9312 case BFD_RELOC_VTABLE_INHERIT
:
9313 case BFD_RELOC_VTABLE_ENTRY
:
9320 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9322 #endif /* !defined (TE_Mach) */
9324 /* Are we finished with this relocation now? */
9325 if (fixP
->fx_addsy
== NULL
)
9327 #if defined (OBJ_COFF) && defined (TE_PE)
9328 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9331 /* Remember value for tc_gen_reloc. */
9332 fixP
->fx_addnumber
= value
;
9333 /* Clear out the frag for now. */
9337 else if (use_rela_relocations
)
9339 fixP
->fx_no_overflow
= 1;
9340 /* Remember value for tc_gen_reloc. */
9341 fixP
->fx_addnumber
= value
;
9345 md_number_to_chars (p
, value
, fixP
->fx_size
);
9349 md_atof (int type
, char *litP
, int *sizeP
)
9351 /* This outputs the LITTLENUMs in REVERSE order;
9352 in accord with the bigendian 386. */
9353 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9356 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9359 output_invalid (int c
)
9362 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9365 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9366 "(0x%x)", (unsigned char) c
);
9367 return output_invalid_buf
;
9370 /* REG_STRING starts *before* REGISTER_PREFIX. */
9372 static const reg_entry
*
9373 parse_real_register (char *reg_string
, char **end_op
)
9375 char *s
= reg_string
;
9377 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9380 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9381 if (*s
== REGISTER_PREFIX
)
9384 if (is_space_char (*s
))
9388 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9390 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9391 return (const reg_entry
*) NULL
;
9395 /* For naked regs, make sure that we are not dealing with an identifier.
9396 This prevents confusing an identifier like `eax_var' with register
9398 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9399 return (const reg_entry
*) NULL
;
9403 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9405 /* Handle floating point regs, allowing spaces in the (i) part. */
9406 if (r
== i386_regtab
/* %st is first entry of table */)
9408 if (is_space_char (*s
))
9413 if (is_space_char (*s
))
9415 if (*s
>= '0' && *s
<= '7')
9419 if (is_space_char (*s
))
9424 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9429 /* We have "%st(" then garbage. */
9430 return (const reg_entry
*) NULL
;
9434 if (r
== NULL
|| allow_pseudo_reg
)
9437 if (operand_type_all_zero (&r
->reg_type
))
9438 return (const reg_entry
*) NULL
;
9440 if ((r
->reg_type
.bitfield
.reg32
9441 || r
->reg_type
.bitfield
.sreg3
9442 || r
->reg_type
.bitfield
.control
9443 || r
->reg_type
.bitfield
.debug
9444 || r
->reg_type
.bitfield
.test
)
9445 && !cpu_arch_flags
.bitfield
.cpui386
)
9446 return (const reg_entry
*) NULL
;
9448 if (r
->reg_type
.bitfield
.floatreg
9449 && !cpu_arch_flags
.bitfield
.cpu8087
9450 && !cpu_arch_flags
.bitfield
.cpu287
9451 && !cpu_arch_flags
.bitfield
.cpu387
)
9452 return (const reg_entry
*) NULL
;
9454 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9455 return (const reg_entry
*) NULL
;
9457 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9458 return (const reg_entry
*) NULL
;
9460 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9461 return (const reg_entry
*) NULL
;
9463 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9464 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9465 return (const reg_entry
*) NULL
;
9467 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9468 if (!allow_index_reg
9469 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9470 return (const reg_entry
*) NULL
;
9472 /* Upper 16 vector register is only available with VREX in 64bit
9474 if ((r
->reg_flags
& RegVRex
))
9476 if (!cpu_arch_flags
.bitfield
.cpuvrex
9477 || flag_code
!= CODE_64BIT
)
9478 return (const reg_entry
*) NULL
;
9483 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9484 || r
->reg_type
.bitfield
.reg64
)
9485 && (!cpu_arch_flags
.bitfield
.cpulm
9486 || !operand_type_equal (&r
->reg_type
, &control
))
9487 && flag_code
!= CODE_64BIT
)
9488 return (const reg_entry
*) NULL
;
9490 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9491 return (const reg_entry
*) NULL
;
9496 /* REG_STRING starts *before* REGISTER_PREFIX. */
9498 static const reg_entry
*
9499 parse_register (char *reg_string
, char **end_op
)
9503 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9504 r
= parse_real_register (reg_string
, end_op
);
9509 char *save
= input_line_pointer
;
9513 input_line_pointer
= reg_string
;
9514 c
= get_symbol_name (®_string
);
9515 symbolP
= symbol_find (reg_string
);
9516 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9518 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9520 know (e
->X_op
== O_register
);
9521 know (e
->X_add_number
>= 0
9522 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9523 r
= i386_regtab
+ e
->X_add_number
;
9524 if ((r
->reg_flags
& RegVRex
))
9526 *end_op
= input_line_pointer
;
9528 *input_line_pointer
= c
;
9529 input_line_pointer
= save
;
9535 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9538 char *end
= input_line_pointer
;
9541 r
= parse_register (name
, &input_line_pointer
);
9542 if (r
&& end
<= input_line_pointer
)
9544 *nextcharP
= *input_line_pointer
;
9545 *input_line_pointer
= 0;
9546 e
->X_op
= O_register
;
9547 e
->X_add_number
= r
- i386_regtab
;
9550 input_line_pointer
= end
;
9552 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9556 md_operand (expressionS
*e
)
9561 switch (*input_line_pointer
)
9563 case REGISTER_PREFIX
:
9564 r
= parse_real_register (input_line_pointer
, &end
);
9567 e
->X_op
= O_register
;
9568 e
->X_add_number
= r
- i386_regtab
;
9569 input_line_pointer
= end
;
9574 gas_assert (intel_syntax
);
9575 end
= input_line_pointer
++;
9577 if (*input_line_pointer
== ']')
9579 ++input_line_pointer
;
9580 e
->X_op_symbol
= make_expr_symbol (e
);
9581 e
->X_add_symbol
= NULL
;
9582 e
->X_add_number
= 0;
9588 input_line_pointer
= end
;
9595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9596 const char *md_shortopts
= "kVQ:sqn";
9598 const char *md_shortopts
= "qn";
9601 #define OPTION_32 (OPTION_MD_BASE + 0)
9602 #define OPTION_64 (OPTION_MD_BASE + 1)
9603 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9604 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9605 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9606 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9607 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9608 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9609 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9610 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9611 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9612 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9613 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9614 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9615 #define OPTION_X32 (OPTION_MD_BASE + 14)
9616 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9617 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9618 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9619 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9620 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9621 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9622 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9623 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9624 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9626 struct option md_longopts
[] =
9628 {"32", no_argument
, NULL
, OPTION_32
},
9629 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9630 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9631 {"64", no_argument
, NULL
, OPTION_64
},
9633 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9634 {"x32", no_argument
, NULL
, OPTION_X32
},
9635 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9637 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9638 {"march", required_argument
, NULL
, OPTION_MARCH
},
9639 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9640 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9641 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9642 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9643 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9644 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9645 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9646 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9647 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9648 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9649 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9650 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9651 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9652 # if defined (TE_PE) || defined (TE_PEP)
9653 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9655 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9656 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9657 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9658 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9659 {NULL
, no_argument
, NULL
, 0}
9661 size_t md_longopts_size
= sizeof (md_longopts
);
9664 md_parse_option (int c
, char *arg
)
9672 optimize_align_code
= 0;
9679 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9680 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9681 should be emitted or not. FIXME: Not implemented. */
9685 /* -V: SVR4 argument to print version ID. */
9687 print_version_id ();
9690 /* -k: Ignore for FreeBSD compatibility. */
9695 /* -s: On i386 Solaris, this tells the native assembler to use
9696 .stab instead of .stab.excl. We always use .stab anyhow. */
9699 case OPTION_MSHARED
:
9703 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9704 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9707 const char **list
, **l
;
9709 list
= bfd_target_list ();
9710 for (l
= list
; *l
!= NULL
; l
++)
9711 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9712 || strcmp (*l
, "coff-x86-64") == 0
9713 || strcmp (*l
, "pe-x86-64") == 0
9714 || strcmp (*l
, "pei-x86-64") == 0
9715 || strcmp (*l
, "mach-o-x86-64") == 0)
9717 default_arch
= "x86_64";
9721 as_fatal (_("no compiled in support for x86_64"));
9727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9731 const char **list
, **l
;
9733 list
= bfd_target_list ();
9734 for (l
= list
; *l
!= NULL
; l
++)
9735 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9737 default_arch
= "x86_64:32";
9741 as_fatal (_("no compiled in support for 32bit x86_64"));
9745 as_fatal (_("32bit x86_64 is only supported for ELF"));
9750 default_arch
= "i386";
9754 #ifdef SVR4_COMMENT_CHARS
9759 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9761 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9765 i386_comment_chars
= n
;
9771 arch
= xstrdup (arg
);
9775 as_fatal (_("invalid -march= option: `%s'"), arg
);
9776 next
= strchr (arch
, '+');
9779 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9781 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9784 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9787 cpu_arch_name
= cpu_arch
[j
].name
;
9788 cpu_sub_arch_name
= NULL
;
9789 cpu_arch_flags
= cpu_arch
[j
].flags
;
9790 cpu_arch_isa
= cpu_arch
[j
].type
;
9791 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9792 if (!cpu_arch_tune_set
)
9794 cpu_arch_tune
= cpu_arch_isa
;
9795 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9799 else if (*cpu_arch
[j
].name
== '.'
9800 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9802 /* ISA entension. */
9803 i386_cpu_flags flags
;
9805 if (!cpu_arch
[j
].negated
)
9806 flags
= cpu_flags_or (cpu_arch_flags
,
9809 flags
= cpu_flags_and_not (cpu_arch_flags
,
9812 if (!valid_iamcu_cpu_flags (&flags
))
9813 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9814 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9816 if (cpu_sub_arch_name
)
9818 char *name
= cpu_sub_arch_name
;
9819 cpu_sub_arch_name
= concat (name
,
9821 (const char *) NULL
);
9825 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9826 cpu_arch_flags
= flags
;
9827 cpu_arch_isa_flags
= flags
;
9833 if (j
>= ARRAY_SIZE (cpu_arch
))
9834 as_fatal (_("invalid -march= option: `%s'"), arg
);
9838 while (next
!= NULL
);
9843 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9844 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9846 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9848 cpu_arch_tune_set
= 1;
9849 cpu_arch_tune
= cpu_arch
[j
].type
;
9850 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9854 if (j
>= ARRAY_SIZE (cpu_arch
))
9855 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9858 case OPTION_MMNEMONIC
:
9859 if (strcasecmp (arg
, "att") == 0)
9861 else if (strcasecmp (arg
, "intel") == 0)
9864 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9867 case OPTION_MSYNTAX
:
9868 if (strcasecmp (arg
, "att") == 0)
9870 else if (strcasecmp (arg
, "intel") == 0)
9873 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9876 case OPTION_MINDEX_REG
:
9877 allow_index_reg
= 1;
9880 case OPTION_MNAKED_REG
:
9881 allow_naked_reg
= 1;
9884 case OPTION_MOLD_GCC
:
9888 case OPTION_MSSE2AVX
:
9892 case OPTION_MSSE_CHECK
:
9893 if (strcasecmp (arg
, "error") == 0)
9894 sse_check
= check_error
;
9895 else if (strcasecmp (arg
, "warning") == 0)
9896 sse_check
= check_warning
;
9897 else if (strcasecmp (arg
, "none") == 0)
9898 sse_check
= check_none
;
9900 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9903 case OPTION_MOPERAND_CHECK
:
9904 if (strcasecmp (arg
, "error") == 0)
9905 operand_check
= check_error
;
9906 else if (strcasecmp (arg
, "warning") == 0)
9907 operand_check
= check_warning
;
9908 else if (strcasecmp (arg
, "none") == 0)
9909 operand_check
= check_none
;
9911 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9914 case OPTION_MAVXSCALAR
:
9915 if (strcasecmp (arg
, "128") == 0)
9917 else if (strcasecmp (arg
, "256") == 0)
9920 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9923 case OPTION_MADD_BND_PREFIX
:
9927 case OPTION_MEVEXLIG
:
9928 if (strcmp (arg
, "128") == 0)
9930 else if (strcmp (arg
, "256") == 0)
9932 else if (strcmp (arg
, "512") == 0)
9935 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9938 case OPTION_MEVEXRCIG
:
9939 if (strcmp (arg
, "rne") == 0)
9941 else if (strcmp (arg
, "rd") == 0)
9943 else if (strcmp (arg
, "ru") == 0)
9945 else if (strcmp (arg
, "rz") == 0)
9948 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9951 case OPTION_MEVEXWIG
:
9952 if (strcmp (arg
, "0") == 0)
9954 else if (strcmp (arg
, "1") == 0)
9957 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9960 # if defined (TE_PE) || defined (TE_PEP)
9961 case OPTION_MBIG_OBJ
:
9966 case OPTION_OMIT_LOCK_PREFIX
:
9967 if (strcasecmp (arg
, "yes") == 0)
9968 omit_lock_prefix
= 1;
9969 else if (strcasecmp (arg
, "no") == 0)
9970 omit_lock_prefix
= 0;
9972 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9976 cpu_arch_flags
.bitfield
.cpuamd64
= 1;
9977 cpu_arch_flags
.bitfield
.cpuintel64
= 0;
9978 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 1;
9979 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 0;
9982 case OPTION_MINTEL64
:
9983 cpu_arch_flags
.bitfield
.cpuamd64
= 0;
9984 cpu_arch_flags
.bitfield
.cpuintel64
= 1;
9985 cpu_arch_isa_flags
.bitfield
.cpuamd64
= 0;
9986 cpu_arch_isa_flags
.bitfield
.cpuintel64
= 1;
9995 #define MESSAGE_TEMPLATE \
9999 show_arch (FILE *stream
, int ext
, int check
)
10001 static char message
[] = MESSAGE_TEMPLATE
;
10002 char *start
= message
+ 27;
10004 int size
= sizeof (MESSAGE_TEMPLATE
);
10011 left
= size
- (start
- message
);
10012 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10014 /* Should it be skipped? */
10015 if (cpu_arch
[j
].skip
)
10018 name
= cpu_arch
[j
].name
;
10019 len
= cpu_arch
[j
].len
;
10022 /* It is an extension. Skip if we aren't asked to show it. */
10033 /* It is an processor. Skip if we show only extension. */
10036 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10038 /* It is an impossible processor - skip. */
10042 /* Reserve 2 spaces for ", " or ",\0" */
10045 /* Check if there is any room. */
10053 p
= mempcpy (p
, name
, len
);
10057 /* Output the current message now and start a new one. */
10060 fprintf (stream
, "%s\n", message
);
10062 left
= size
- (start
- message
) - len
- 2;
10064 gas_assert (left
>= 0);
10066 p
= mempcpy (p
, name
, len
);
10071 fprintf (stream
, "%s\n", message
);
10075 md_show_usage (FILE *stream
)
10077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078 fprintf (stream
, _("\
10080 -V print assembler version number\n\
10083 fprintf (stream
, _("\
10084 -n Do not optimize code alignment\n\
10085 -q quieten some warnings\n"));
10086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10087 fprintf (stream
, _("\
10090 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10091 || defined (TE_PE) || defined (TE_PEP))
10092 fprintf (stream
, _("\
10093 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10095 #ifdef SVR4_COMMENT_CHARS
10096 fprintf (stream
, _("\
10097 --divide do not treat `/' as a comment character\n"));
10099 fprintf (stream
, _("\
10100 --divide ignored\n"));
10102 fprintf (stream
, _("\
10103 -march=CPU[,+EXTENSION...]\n\
10104 generate code for CPU and EXTENSION, CPU is one of:\n"));
10105 show_arch (stream
, 0, 1);
10106 fprintf (stream
, _("\
10107 EXTENSION is combination of:\n"));
10108 show_arch (stream
, 1, 0);
10109 fprintf (stream
, _("\
10110 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10111 show_arch (stream
, 0, 0);
10112 fprintf (stream
, _("\
10113 -msse2avx encode SSE instructions with VEX prefix\n"));
10114 fprintf (stream
, _("\
10115 -msse-check=[none|error|warning]\n\
10116 check SSE instructions\n"));
10117 fprintf (stream
, _("\
10118 -moperand-check=[none|error|warning]\n\
10119 check operand combinations for validity\n"));
10120 fprintf (stream
, _("\
10121 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10123 fprintf (stream
, _("\
10124 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10126 fprintf (stream
, _("\
10127 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10128 for EVEX.W bit ignored instructions\n"));
10129 fprintf (stream
, _("\
10130 -mevexrcig=[rne|rd|ru|rz]\n\
10131 encode EVEX instructions with specific EVEX.RC value\n\
10132 for SAE-only ignored instructions\n"));
10133 fprintf (stream
, _("\
10134 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10135 fprintf (stream
, _("\
10136 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10137 fprintf (stream
, _("\
10138 -mindex-reg support pseudo index registers\n"));
10139 fprintf (stream
, _("\
10140 -mnaked-reg don't require `%%' prefix for registers\n"));
10141 fprintf (stream
, _("\
10142 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10143 fprintf (stream
, _("\
10144 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10145 fprintf (stream
, _("\
10146 -mshared disable branch optimization for shared code\n"));
10147 # if defined (TE_PE) || defined (TE_PEP)
10148 fprintf (stream
, _("\
10149 -mbig-obj generate big object files\n"));
10151 fprintf (stream
, _("\
10152 -momit-lock-prefix=[no|yes]\n\
10153 strip all lock prefixes\n"));
10154 fprintf (stream
, _("\
10155 -mamd64 accept only AMD64 ISA\n"));
10156 fprintf (stream
, _("\
10157 -mintel64 accept only Intel64 ISA\n"));
10160 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10161 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10162 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10164 /* Pick the target format to use. */
10167 i386_target_format (void)
10169 if (!strncmp (default_arch
, "x86_64", 6))
10171 update_code_flag (CODE_64BIT
, 1);
10172 if (default_arch
[6] == '\0')
10173 x86_elf_abi
= X86_64_ABI
;
10175 x86_elf_abi
= X86_64_X32_ABI
;
10177 else if (!strcmp (default_arch
, "i386"))
10178 update_code_flag (CODE_32BIT
, 1);
10179 else if (!strcmp (default_arch
, "iamcu"))
10181 update_code_flag (CODE_32BIT
, 1);
10182 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10184 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10185 cpu_arch_name
= "iamcu";
10186 cpu_sub_arch_name
= NULL
;
10187 cpu_arch_flags
= iamcu_flags
;
10188 cpu_arch_isa
= PROCESSOR_IAMCU
;
10189 cpu_arch_isa_flags
= iamcu_flags
;
10190 if (!cpu_arch_tune_set
)
10192 cpu_arch_tune
= cpu_arch_isa
;
10193 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10197 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10201 as_fatal (_("unknown architecture"));
10203 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10204 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10205 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10206 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10208 switch (OUTPUT_FLAVOR
)
10210 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10211 case bfd_target_aout_flavour
:
10212 return AOUT_TARGET_FORMAT
;
10214 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10215 # if defined (TE_PE) || defined (TE_PEP)
10216 case bfd_target_coff_flavour
:
10217 if (flag_code
== CODE_64BIT
)
10218 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10221 # elif defined (TE_GO32)
10222 case bfd_target_coff_flavour
:
10223 return "coff-go32";
10225 case bfd_target_coff_flavour
:
10226 return "coff-i386";
10229 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10230 case bfd_target_elf_flavour
:
10232 const char *format
;
10234 switch (x86_elf_abi
)
10237 format
= ELF_TARGET_FORMAT
;
10240 use_rela_relocations
= 1;
10242 format
= ELF_TARGET_FORMAT64
;
10244 case X86_64_X32_ABI
:
10245 use_rela_relocations
= 1;
10247 disallow_64bit_reloc
= 1;
10248 format
= ELF_TARGET_FORMAT32
;
10251 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10253 if (x86_elf_abi
!= X86_64_ABI
)
10254 as_fatal (_("Intel L1OM is 64bit only"));
10255 return ELF_TARGET_L1OM_FORMAT
;
10257 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10259 if (x86_elf_abi
!= X86_64_ABI
)
10260 as_fatal (_("Intel K1OM is 64bit only"));
10261 return ELF_TARGET_K1OM_FORMAT
;
10263 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10265 if (x86_elf_abi
!= I386_ABI
)
10266 as_fatal (_("Intel MCU is 32bit only"));
10267 return ELF_TARGET_IAMCU_FORMAT
;
10273 #if defined (OBJ_MACH_O)
10274 case bfd_target_mach_o_flavour
:
10275 if (flag_code
== CODE_64BIT
)
10277 use_rela_relocations
= 1;
10279 return "mach-o-x86-64";
10282 return "mach-o-i386";
10290 #endif /* OBJ_MAYBE_ more than one */
10293 md_undefined_symbol (char *name
)
10295 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10296 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10297 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10298 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10302 if (symbol_find (name
))
10303 as_bad (_("GOT already in symbol table"));
10304 GOT_symbol
= symbol_new (name
, undefined_section
,
10305 (valueT
) 0, &zero_address_frag
);
10312 /* Round up a section size to the appropriate boundary. */
10315 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10317 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10318 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10320 /* For a.out, force the section size to be aligned. If we don't do
10321 this, BFD will align it for us, but it will not write out the
10322 final bytes of the section. This may be a bug in BFD, but it is
10323 easier to fix it here since that is how the other a.out targets
10327 align
= bfd_get_section_alignment (stdoutput
, segment
);
10328 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10335 /* On the i386, PC-relative offsets are relative to the start of the
10336 next instruction. That is, the address of the offset, plus its
10337 size, since the offset is always the last part of the insn. */
10340 md_pcrel_from (fixS
*fixP
)
10342 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10348 s_bss (int ignore ATTRIBUTE_UNUSED
)
10352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10354 obj_elf_section_change_hook ();
10356 temp
= get_absolute_expression ();
10357 subseg_set (bss_section
, (subsegT
) temp
);
10358 demand_empty_rest_of_line ();
10364 i386_validate_fix (fixS
*fixp
)
10366 if (fixp
->fx_subsy
)
10368 if (fixp
->fx_subsy
== GOT_symbol
)
10370 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10375 if (fixp
->fx_tcbit2
)
10376 fixp
->fx_r_type
= (fixp
->fx_tcbit
10377 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10378 : BFD_RELOC_X86_64_GOTPCRELX
);
10381 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10386 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10388 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10390 fixp
->fx_subsy
= 0;
10393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10394 else if (!object_64bit
)
10396 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10397 && fixp
->fx_tcbit2
)
10398 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10404 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10407 bfd_reloc_code_real_type code
;
10409 switch (fixp
->fx_r_type
)
10411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10412 case BFD_RELOC_SIZE32
:
10413 case BFD_RELOC_SIZE64
:
10414 if (S_IS_DEFINED (fixp
->fx_addsy
)
10415 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10417 /* Resolve size relocation against local symbol to size of
10418 the symbol plus addend. */
10419 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10420 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10421 && !fits_in_unsigned_long (value
))
10422 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10423 _("symbol size computation overflow"));
10424 fixp
->fx_addsy
= NULL
;
10425 fixp
->fx_subsy
= NULL
;
10426 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10431 case BFD_RELOC_X86_64_PLT32
:
10432 case BFD_RELOC_X86_64_GOT32
:
10433 case BFD_RELOC_X86_64_GOTPCREL
:
10434 case BFD_RELOC_X86_64_GOTPCRELX
:
10435 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10436 case BFD_RELOC_386_PLT32
:
10437 case BFD_RELOC_386_GOT32
:
10438 case BFD_RELOC_386_GOT32X
:
10439 case BFD_RELOC_386_GOTOFF
:
10440 case BFD_RELOC_386_GOTPC
:
10441 case BFD_RELOC_386_TLS_GD
:
10442 case BFD_RELOC_386_TLS_LDM
:
10443 case BFD_RELOC_386_TLS_LDO_32
:
10444 case BFD_RELOC_386_TLS_IE_32
:
10445 case BFD_RELOC_386_TLS_IE
:
10446 case BFD_RELOC_386_TLS_GOTIE
:
10447 case BFD_RELOC_386_TLS_LE_32
:
10448 case BFD_RELOC_386_TLS_LE
:
10449 case BFD_RELOC_386_TLS_GOTDESC
:
10450 case BFD_RELOC_386_TLS_DESC_CALL
:
10451 case BFD_RELOC_X86_64_TLSGD
:
10452 case BFD_RELOC_X86_64_TLSLD
:
10453 case BFD_RELOC_X86_64_DTPOFF32
:
10454 case BFD_RELOC_X86_64_DTPOFF64
:
10455 case BFD_RELOC_X86_64_GOTTPOFF
:
10456 case BFD_RELOC_X86_64_TPOFF32
:
10457 case BFD_RELOC_X86_64_TPOFF64
:
10458 case BFD_RELOC_X86_64_GOTOFF64
:
10459 case BFD_RELOC_X86_64_GOTPC32
:
10460 case BFD_RELOC_X86_64_GOT64
:
10461 case BFD_RELOC_X86_64_GOTPCREL64
:
10462 case BFD_RELOC_X86_64_GOTPC64
:
10463 case BFD_RELOC_X86_64_GOTPLT64
:
10464 case BFD_RELOC_X86_64_PLTOFF64
:
10465 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10466 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10467 case BFD_RELOC_RVA
:
10468 case BFD_RELOC_VTABLE_ENTRY
:
10469 case BFD_RELOC_VTABLE_INHERIT
:
10471 case BFD_RELOC_32_SECREL
:
10473 code
= fixp
->fx_r_type
;
10475 case BFD_RELOC_X86_64_32S
:
10476 if (!fixp
->fx_pcrel
)
10478 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10479 code
= fixp
->fx_r_type
;
10483 if (fixp
->fx_pcrel
)
10485 switch (fixp
->fx_size
)
10488 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10489 _("can not do %d byte pc-relative relocation"),
10491 code
= BFD_RELOC_32_PCREL
;
10493 case 1: code
= BFD_RELOC_8_PCREL
; break;
10494 case 2: code
= BFD_RELOC_16_PCREL
; break;
10495 case 4: code
= BFD_RELOC_32_PCREL
; break;
10497 case 8: code
= BFD_RELOC_64_PCREL
; break;
10503 switch (fixp
->fx_size
)
10506 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10507 _("can not do %d byte relocation"),
10509 code
= BFD_RELOC_32
;
10511 case 1: code
= BFD_RELOC_8
; break;
10512 case 2: code
= BFD_RELOC_16
; break;
10513 case 4: code
= BFD_RELOC_32
; break;
10515 case 8: code
= BFD_RELOC_64
; break;
10522 if ((code
== BFD_RELOC_32
10523 || code
== BFD_RELOC_32_PCREL
10524 || code
== BFD_RELOC_X86_64_32S
)
10526 && fixp
->fx_addsy
== GOT_symbol
)
10529 code
= BFD_RELOC_386_GOTPC
;
10531 code
= BFD_RELOC_X86_64_GOTPC32
;
10533 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10535 && fixp
->fx_addsy
== GOT_symbol
)
10537 code
= BFD_RELOC_X86_64_GOTPC64
;
10540 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10541 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10542 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10544 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10546 if (!use_rela_relocations
)
10548 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10549 vtable entry to be used in the relocation's section offset. */
10550 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10551 rel
->address
= fixp
->fx_offset
;
10552 #if defined (OBJ_COFF) && defined (TE_PE)
10553 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10554 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10559 /* Use the rela in 64bit mode. */
10562 if (disallow_64bit_reloc
)
10565 case BFD_RELOC_X86_64_DTPOFF64
:
10566 case BFD_RELOC_X86_64_TPOFF64
:
10567 case BFD_RELOC_64_PCREL
:
10568 case BFD_RELOC_X86_64_GOTOFF64
:
10569 case BFD_RELOC_X86_64_GOT64
:
10570 case BFD_RELOC_X86_64_GOTPCREL64
:
10571 case BFD_RELOC_X86_64_GOTPC64
:
10572 case BFD_RELOC_X86_64_GOTPLT64
:
10573 case BFD_RELOC_X86_64_PLTOFF64
:
10574 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10575 _("cannot represent relocation type %s in x32 mode"),
10576 bfd_get_reloc_code_name (code
));
10582 if (!fixp
->fx_pcrel
)
10583 rel
->addend
= fixp
->fx_offset
;
10587 case BFD_RELOC_X86_64_PLT32
:
10588 case BFD_RELOC_X86_64_GOT32
:
10589 case BFD_RELOC_X86_64_GOTPCREL
:
10590 case BFD_RELOC_X86_64_GOTPCRELX
:
10591 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10592 case BFD_RELOC_X86_64_TLSGD
:
10593 case BFD_RELOC_X86_64_TLSLD
:
10594 case BFD_RELOC_X86_64_GOTTPOFF
:
10595 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10596 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10597 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10600 rel
->addend
= (section
->vma
10602 + fixp
->fx_addnumber
10603 + md_pcrel_from (fixp
));
10608 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10609 if (rel
->howto
== NULL
)
10611 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10612 _("cannot represent relocation type %s"),
10613 bfd_get_reloc_code_name (code
));
10614 /* Set howto to a garbage value so that we can keep going. */
10615 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10616 gas_assert (rel
->howto
!= NULL
);
10622 #include "tc-i386-intel.c"
10625 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10627 int saved_naked_reg
;
10628 char saved_register_dot
;
10630 saved_naked_reg
= allow_naked_reg
;
10631 allow_naked_reg
= 1;
10632 saved_register_dot
= register_chars
['.'];
10633 register_chars
['.'] = '.';
10634 allow_pseudo_reg
= 1;
10635 expression_and_evaluate (exp
);
10636 allow_pseudo_reg
= 0;
10637 register_chars
['.'] = saved_register_dot
;
10638 allow_naked_reg
= saved_naked_reg
;
10640 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10642 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10644 exp
->X_op
= O_constant
;
10645 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10646 .dw2_regnum
[flag_code
>> 1];
10649 exp
->X_op
= O_illegal
;
10654 tc_x86_frame_initial_instructions (void)
10656 static unsigned int sp_regno
[2];
10658 if (!sp_regno
[flag_code
>> 1])
10660 char *saved_input
= input_line_pointer
;
10661 char sp
[][4] = {"esp", "rsp"};
10664 input_line_pointer
= sp
[flag_code
>> 1];
10665 tc_x86_parse_to_dw2regnum (&exp
);
10666 gas_assert (exp
.X_op
== O_constant
);
10667 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10668 input_line_pointer
= saved_input
;
10671 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10672 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10676 x86_dwarf2_addr_size (void)
10678 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10679 if (x86_elf_abi
== X86_64_X32_ABI
)
10682 return bfd_arch_bits_per_address (stdoutput
) / 8;
10686 i386_elf_section_type (const char *str
, size_t len
)
10688 if (flag_code
== CODE_64BIT
10689 && len
== sizeof ("unwind") - 1
10690 && strncmp (str
, "unwind", 6) == 0)
10691 return SHT_X86_64_UNWIND
;
10698 i386_solaris_fix_up_eh_frame (segT sec
)
10700 if (flag_code
== CODE_64BIT
)
10701 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10707 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10711 exp
.X_op
= O_secrel
;
10712 exp
.X_add_symbol
= symbol
;
10713 exp
.X_add_number
= 0;
10714 emit_expr (&exp
, size
);
10718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10719 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10722 x86_64_section_letter (int letter
, char **ptr_msg
)
10724 if (flag_code
== CODE_64BIT
)
10727 return SHF_X86_64_LARGE
;
10729 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10732 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10737 x86_64_section_word (char *str
, size_t len
)
10739 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10740 return SHF_X86_64_LARGE
;
10746 handle_large_common (int small ATTRIBUTE_UNUSED
)
10748 if (flag_code
!= CODE_64BIT
)
10750 s_comm_internal (0, elf_common_parse
);
10751 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10755 static segT lbss_section
;
10756 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10757 asection
*saved_bss_section
= bss_section
;
10759 if (lbss_section
== NULL
)
10761 flagword applicable
;
10762 segT seg
= now_seg
;
10763 subsegT subseg
= now_subseg
;
10765 /* The .lbss section is for local .largecomm symbols. */
10766 lbss_section
= subseg_new (".lbss", 0);
10767 applicable
= bfd_applicable_section_flags (stdoutput
);
10768 bfd_set_section_flags (stdoutput
, lbss_section
,
10769 applicable
& SEC_ALLOC
);
10770 seg_info (lbss_section
)->bss
= 1;
10772 subseg_set (seg
, subseg
);
10775 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10776 bss_section
= lbss_section
;
10778 s_comm_internal (0, elf_common_parse
);
10780 elf_com_section_ptr
= saved_com_section_ptr
;
10781 bss_section
= saved_bss_section
;
10784 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */