1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static int match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "k6", PROCESSOR_K6
,
605 { "k6_2", PROCESSOR_K6
,
607 { "athlon", PROCESSOR_ATHLON
,
609 { "sledgehammer", PROCESSOR_K8
,
611 { "opteron", PROCESSOR_K8
,
613 { "k8", PROCESSOR_K8
,
615 { "amdfam10", PROCESSOR_AMDFAM10
,
616 CPU_AMDFAM10_FLAGS
},
617 { ".mmx", PROCESSOR_UNKNOWN
,
619 { ".sse", PROCESSOR_UNKNOWN
,
621 { ".sse2", PROCESSOR_UNKNOWN
,
623 { ".sse3", PROCESSOR_UNKNOWN
,
625 { ".ssse3", PROCESSOR_UNKNOWN
,
627 { ".sse4.1", PROCESSOR_UNKNOWN
,
629 { ".sse4.2", PROCESSOR_UNKNOWN
,
631 { ".sse4", PROCESSOR_UNKNOWN
,
633 { ".avx", PROCESSOR_UNKNOWN
,
635 { ".vmx", PROCESSOR_UNKNOWN
,
637 { ".smx", PROCESSOR_UNKNOWN
,
639 { ".xsave", PROCESSOR_UNKNOWN
,
641 { ".aes", PROCESSOR_UNKNOWN
,
643 { ".pclmul", PROCESSOR_UNKNOWN
,
645 { ".clmul", PROCESSOR_UNKNOWN
,
647 { ".fma", PROCESSOR_UNKNOWN
,
649 { ".movbe", PROCESSOR_UNKNOWN
,
651 { ".ept", PROCESSOR_UNKNOWN
,
653 { ".3dnow", PROCESSOR_UNKNOWN
,
655 { ".3dnowa", PROCESSOR_UNKNOWN
,
657 { ".padlock", PROCESSOR_UNKNOWN
,
659 { ".pacifica", PROCESSOR_UNKNOWN
,
661 { ".svme", PROCESSOR_UNKNOWN
,
663 { ".sse4a", PROCESSOR_UNKNOWN
,
665 { ".abm", PROCESSOR_UNKNOWN
,
667 { ".sse5", PROCESSOR_UNKNOWN
,
672 /* Like s_lcomm_internal in gas/read.c but the alignment string
673 is allowed to be optional. */
676 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
683 && *input_line_pointer
== ',')
685 align
= parse_align (needs_align
- 1);
687 if (align
== (addressT
) -1)
702 bss_alloc (symbolP
, size
, align
);
707 pe_lcomm (int needs_align
)
709 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
713 const pseudo_typeS md_pseudo_table
[] =
715 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
716 {"align", s_align_bytes
, 0},
718 {"align", s_align_ptwo
, 0},
720 {"arch", set_cpu_arch
, 0},
724 {"lcomm", pe_lcomm
, 1},
726 {"ffloat", float_cons
, 'f'},
727 {"dfloat", float_cons
, 'd'},
728 {"tfloat", float_cons
, 'x'},
730 {"slong", signed_cons
, 4},
731 {"noopt", s_ignore
, 0},
732 {"optim", s_ignore
, 0},
733 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
734 {"code16", set_code_flag
, CODE_16BIT
},
735 {"code32", set_code_flag
, CODE_32BIT
},
736 {"code64", set_code_flag
, CODE_64BIT
},
737 {"intel_syntax", set_intel_syntax
, 1},
738 {"att_syntax", set_intel_syntax
, 0},
739 {"intel_mnemonic", set_intel_mnemonic
, 1},
740 {"att_mnemonic", set_intel_mnemonic
, 0},
741 {"allow_index_reg", set_allow_index_reg
, 1},
742 {"disallow_index_reg", set_allow_index_reg
, 0},
743 {"sse_check", set_sse_check
, 0},
744 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
745 {"largecomm", handle_large_common
, 0},
747 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
748 {"loc", dwarf2_directive_loc
, 0},
749 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
752 {"secrel32", pe_directive_secrel
, 0},
757 /* For interface with expression (). */
758 extern char *input_line_pointer
;
760 /* Hash table for instruction mnemonic lookup. */
761 static struct hash_control
*op_hash
;
763 /* Hash table for register lookup. */
764 static struct hash_control
*reg_hash
;
767 i386_align_code (fragS
*fragP
, int count
)
769 /* Various efficient no-op patterns for aligning code labels.
770 Note: Don't try to assemble the instructions in the comments.
771 0L and 0w are not legal. */
772 static const char f32_1
[] =
774 static const char f32_2
[] =
775 {0x66,0x90}; /* xchg %ax,%ax */
776 static const char f32_3
[] =
777 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
778 static const char f32_4
[] =
779 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_5
[] =
782 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
783 static const char f32_6
[] =
784 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
785 static const char f32_7
[] =
786 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_8
[] =
789 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
790 static const char f32_9
[] =
791 {0x89,0xf6, /* movl %esi,%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_10
[] =
794 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_11
[] =
797 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_12
[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
802 static const char f32_13
[] =
803 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_14
[] =
806 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
807 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
808 static const char f16_3
[] =
809 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
810 static const char f16_4
[] =
811 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_5
[] =
814 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
815 static const char f16_6
[] =
816 {0x89,0xf6, /* mov %si,%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_7
[] =
819 {0x8d,0x74,0x00, /* lea 0(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
821 static const char f16_8
[] =
822 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char jump_31
[] =
825 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
829 static const char *const f32_patt
[] = {
830 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
831 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
833 static const char *const f16_patt
[] = {
834 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
837 static const char alt_3
[] =
839 /* nopl 0(%[re]ax) */
840 static const char alt_4
[] =
841 {0x0f,0x1f,0x40,0x00};
842 /* nopl 0(%[re]ax,%[re]ax,1) */
843 static const char alt_5
[] =
844 {0x0f,0x1f,0x44,0x00,0x00};
845 /* nopw 0(%[re]ax,%[re]ax,1) */
846 static const char alt_6
[] =
847 {0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopl 0L(%[re]ax) */
849 static const char alt_7
[] =
850 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
851 /* nopl 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_8
[] =
853 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw 0L(%[re]ax,%[re]ax,1) */
855 static const char alt_9
[] =
856 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_10
[] =
859 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
861 nopw %cs:0L(%[re]ax,%[re]ax,1) */
862 static const char alt_long_11
[] =
864 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_12
[] =
871 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_13
[] =
880 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
885 nopw %cs:0L(%[re]ax,%[re]ax,1) */
886 static const char alt_long_14
[] =
891 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
897 nopw %cs:0L(%[re]ax,%[re]ax,1) */
898 static const char alt_long_15
[] =
904 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 /* nopl 0(%[re]ax,%[re]ax,1)
906 nopw 0(%[re]ax,%[re]ax,1) */
907 static const char alt_short_11
[] =
908 {0x0f,0x1f,0x44,0x00,0x00,
909 0x66,0x0f,0x1f,0x44,0x00,0x00};
910 /* nopw 0(%[re]ax,%[re]ax,1)
911 nopw 0(%[re]ax,%[re]ax,1) */
912 static const char alt_short_12
[] =
913 {0x66,0x0f,0x1f,0x44,0x00,0x00,
914 0x66,0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1)
917 static const char alt_short_13
[] =
918 {0x66,0x0f,0x1f,0x44,0x00,0x00,
919 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
922 static const char alt_short_14
[] =
923 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
924 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 nopl 0L(%[re]ax,%[re]ax,1) */
927 static const char alt_short_15
[] =
928 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
929 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 static const char *const alt_short_patt
[] = {
931 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
932 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
933 alt_short_14
, alt_short_15
935 static const char *const alt_long_patt
[] = {
936 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
937 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
938 alt_long_14
, alt_long_15
941 /* Only align for at least a positive non-zero boundary. */
942 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
945 /* We need to decide which NOP sequence to use for 32bit and
946 64bit. When -mtune= is used:
948 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
949 PROCESSOR_GENERIC32, f32_patt will be used.
950 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
951 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
952 alt_long_patt will be used.
953 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
954 PROCESSOR_AMDFAM10, alt_short_patt will be used.
956 When -mtune= isn't used, alt_long_patt will be used if
957 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
960 When -march= or .arch is used, we can't use anything beyond
961 cpu_arch_isa_flags. */
963 if (flag_code
== CODE_16BIT
)
967 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
969 /* Adjust jump offset. */
970 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
973 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
974 f16_patt
[count
- 1], count
);
978 const char *const *patt
= NULL
;
980 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
982 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
983 switch (cpu_arch_tune
)
985 case PROCESSOR_UNKNOWN
:
986 /* We use cpu_arch_isa_flags to check if we SHOULD
987 optimize for Cpu686. */
988 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
989 patt
= alt_long_patt
;
993 case PROCESSOR_PENTIUMPRO
:
994 case PROCESSOR_PENTIUM4
:
995 case PROCESSOR_NOCONA
:
997 case PROCESSOR_CORE2
:
998 case PROCESSOR_GENERIC64
:
999 patt
= alt_long_patt
;
1002 case PROCESSOR_ATHLON
:
1004 case PROCESSOR_AMDFAM10
:
1005 patt
= alt_short_patt
;
1007 case PROCESSOR_I386
:
1008 case PROCESSOR_I486
:
1009 case PROCESSOR_PENTIUM
:
1010 case PROCESSOR_GENERIC32
:
1017 switch (fragP
->tc_frag_data
.tune
)
1019 case PROCESSOR_UNKNOWN
:
1020 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1021 PROCESSOR_UNKNOWN. */
1025 case PROCESSOR_I386
:
1026 case PROCESSOR_I486
:
1027 case PROCESSOR_PENTIUM
:
1029 case PROCESSOR_ATHLON
:
1031 case PROCESSOR_AMDFAM10
:
1032 case PROCESSOR_GENERIC32
:
1033 /* We use cpu_arch_isa_flags to check if we CAN optimize
1035 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1036 patt
= alt_short_patt
;
1040 case PROCESSOR_PENTIUMPRO
:
1041 case PROCESSOR_PENTIUM4
:
1042 case PROCESSOR_NOCONA
:
1043 case PROCESSOR_CORE
:
1044 case PROCESSOR_CORE2
:
1045 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1046 patt
= alt_long_patt
;
1050 case PROCESSOR_GENERIC64
:
1051 patt
= alt_long_patt
;
1056 if (patt
== f32_patt
)
1058 /* If the padding is less than 15 bytes, we use the normal
1059 ones. Otherwise, we use a jump instruction and adjust
1062 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1063 patt
[count
- 1], count
);
1066 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1068 /* Adjust jump offset. */
1069 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1074 /* Maximum length of an instruction is 15 byte. If the
1075 padding is greater than 15 bytes and we don't use jump,
1076 we have to break it into smaller pieces. */
1077 int padding
= count
;
1078 while (padding
> 15)
1081 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1086 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1087 patt
[padding
- 1], padding
);
1090 fragP
->fr_var
= count
;
1094 operand_type_all_zero (const union i386_operand_type
*x
)
1096 switch (ARRAY_SIZE(x
->array
))
1105 return !x
->array
[0];
1112 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1114 switch (ARRAY_SIZE(x
->array
))
1129 operand_type_equal (const union i386_operand_type
*x
,
1130 const union i386_operand_type
*y
)
1132 switch (ARRAY_SIZE(x
->array
))
1135 if (x
->array
[2] != y
->array
[2])
1138 if (x
->array
[1] != y
->array
[1])
1141 return x
->array
[0] == y
->array
[0];
1149 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1151 switch (ARRAY_SIZE(x
->array
))
1160 return !x
->array
[0];
1167 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1169 switch (ARRAY_SIZE(x
->array
))
1184 cpu_flags_equal (const union i386_cpu_flags
*x
,
1185 const union i386_cpu_flags
*y
)
1187 switch (ARRAY_SIZE(x
->array
))
1190 if (x
->array
[2] != y
->array
[2])
1193 if (x
->array
[1] != y
->array
[1])
1196 return x
->array
[0] == y
->array
[0];
1204 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1206 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1207 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1210 static INLINE i386_cpu_flags
1211 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1213 switch (ARRAY_SIZE (x
.array
))
1216 x
.array
[2] &= y
.array
[2];
1218 x
.array
[1] &= y
.array
[1];
1220 x
.array
[0] &= y
.array
[0];
1228 static INLINE i386_cpu_flags
1229 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1231 switch (ARRAY_SIZE (x
.array
))
1234 x
.array
[2] |= y
.array
[2];
1236 x
.array
[1] |= y
.array
[1];
1238 x
.array
[0] |= y
.array
[0];
1246 #define CPU_FLAGS_ARCH_MATCH 0x1
1247 #define CPU_FLAGS_64BIT_MATCH 0x2
1248 #define CPU_FLAGS_AES_MATCH 0x4
1249 #define CPU_FLAGS_AVX_MATCH 0x8
1251 #define CPU_FLAGS_32BIT_MATCH \
1252 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
1253 #define CPU_FLAGS_PERFECT_MATCH \
1254 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1256 /* Return CPU flags match bits. */
1259 cpu_flags_match (const template *t
)
1261 i386_cpu_flags x
= t
->cpu_flags
;
1262 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1264 x
.bitfield
.cpu64
= 0;
1265 x
.bitfield
.cpuno64
= 0;
1267 if (cpu_flags_all_zero (&x
))
1269 /* This instruction is available on all archs. */
1270 match
|= CPU_FLAGS_32BIT_MATCH
;
1274 /* This instruction is available only on some archs. */
1275 i386_cpu_flags cpu
= cpu_arch_flags
;
1277 cpu
.bitfield
.cpu64
= 0;
1278 cpu
.bitfield
.cpuno64
= 0;
1279 cpu
= cpu_flags_and (x
, cpu
);
1280 if (!cpu_flags_all_zero (&cpu
))
1282 if (x
.bitfield
.cpuavx
)
1284 /* We only need to check AES/SSE2AVX with AVX. */
1285 if (cpu
.bitfield
.cpuavx
)
1287 /* Check SSE2AVX. */
1288 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1290 match
|= (CPU_FLAGS_ARCH_MATCH
1291 | CPU_FLAGS_AVX_MATCH
);
1293 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1294 match
|= CPU_FLAGS_AES_MATCH
;
1298 match
|= CPU_FLAGS_ARCH_MATCH
;
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1307 static INLINE i386_operand_type
1308 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1310 switch (ARRAY_SIZE (x
.array
))
1313 x
.array
[2] &= y
.array
[2];
1315 x
.array
[1] &= y
.array
[1];
1317 x
.array
[0] &= y
.array
[0];
1325 static INLINE i386_operand_type
1326 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1328 switch (ARRAY_SIZE (x
.array
))
1331 x
.array
[2] |= y
.array
[2];
1333 x
.array
[1] |= y
.array
[1];
1335 x
.array
[0] |= y
.array
[0];
1343 static INLINE i386_operand_type
1344 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1346 switch (ARRAY_SIZE (x
.array
))
1349 x
.array
[2] ^= y
.array
[2];
1351 x
.array
[1] ^= y
.array
[1];
1353 x
.array
[0] ^= y
.array
[0];
1361 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1362 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1363 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1364 static const i386_operand_type inoutportreg
1365 = OPERAND_TYPE_INOUTPORTREG
;
1366 static const i386_operand_type reg16_inoutportreg
1367 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1368 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1369 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1370 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1371 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1372 static const i386_operand_type anydisp
1373 = OPERAND_TYPE_ANYDISP
;
1374 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1375 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1376 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1377 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1378 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1379 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1380 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1381 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1382 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1383 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1384 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1385 static const i386_operand_type vex_imm4
= OPERAND_TYPE_VEX_IMM4
;
1396 operand_type_check (i386_operand_type t
, enum operand_type c
)
1401 return (t
.bitfield
.reg8
1404 || t
.bitfield
.reg64
);
1407 return (t
.bitfield
.imm8
1411 || t
.bitfield
.imm32s
1412 || t
.bitfield
.imm64
);
1415 return (t
.bitfield
.disp8
1416 || t
.bitfield
.disp16
1417 || t
.bitfield
.disp32
1418 || t
.bitfield
.disp32s
1419 || t
.bitfield
.disp64
);
1422 return (t
.bitfield
.disp8
1423 || t
.bitfield
.disp16
1424 || t
.bitfield
.disp32
1425 || t
.bitfield
.disp32s
1426 || t
.bitfield
.disp64
1427 || t
.bitfield
.baseindex
);
1436 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1437 operand J for instruction template T. */
1440 match_reg_size (const template *t
, unsigned int j
)
1442 return !((i
.types
[j
].bitfield
.byte
1443 && !t
->operand_types
[j
].bitfield
.byte
)
1444 || (i
.types
[j
].bitfield
.word
1445 && !t
->operand_types
[j
].bitfield
.word
)
1446 || (i
.types
[j
].bitfield
.dword
1447 && !t
->operand_types
[j
].bitfield
.dword
)
1448 || (i
.types
[j
].bitfield
.qword
1449 && !t
->operand_types
[j
].bitfield
.qword
));
1452 /* Return 1 if there is no conflict in any size on operand J for
1453 instruction template T. */
1456 match_mem_size (const template *t
, unsigned int j
)
1458 return (match_reg_size (t
, j
)
1459 && !((i
.types
[j
].bitfield
.unspecified
1460 && !t
->operand_types
[j
].bitfield
.unspecified
)
1461 || (i
.types
[j
].bitfield
.fword
1462 && !t
->operand_types
[j
].bitfield
.fword
)
1463 || (i
.types
[j
].bitfield
.tbyte
1464 && !t
->operand_types
[j
].bitfield
.tbyte
)
1465 || (i
.types
[j
].bitfield
.xmmword
1466 && !t
->operand_types
[j
].bitfield
.xmmword
)
1467 || (i
.types
[j
].bitfield
.ymmword
1468 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1471 /* Return 1 if there is no size conflict on any operands for
1472 instruction template T. */
1475 operand_size_match (const template *t
)
1480 /* Don't check jump instructions. */
1481 if (t
->opcode_modifier
.jump
1482 || t
->opcode_modifier
.jumpbyte
1483 || t
->opcode_modifier
.jumpdword
1484 || t
->opcode_modifier
.jumpintersegment
)
1487 /* Check memory and accumulator operand size. */
1488 for (j
= 0; j
< i
.operands
; j
++)
1490 if (t
->operand_types
[j
].bitfield
.anysize
)
1493 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1499 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1507 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1510 /* Check reverse. */
1511 assert (i
.operands
== 2);
1514 for (j
= 0; j
< 2; j
++)
1516 if (t
->operand_types
[j
].bitfield
.acc
1517 && !match_reg_size (t
, j
? 0 : 1))
1523 if (i
.types
[j
].bitfield
.mem
1524 && !match_mem_size (t
, j
? 0 : 1))
1535 operand_type_match (i386_operand_type overlap
,
1536 i386_operand_type given
)
1538 i386_operand_type temp
= overlap
;
1540 temp
.bitfield
.jumpabsolute
= 0;
1541 temp
.bitfield
.unspecified
= 0;
1542 temp
.bitfield
.byte
= 0;
1543 temp
.bitfield
.word
= 0;
1544 temp
.bitfield
.dword
= 0;
1545 temp
.bitfield
.fword
= 0;
1546 temp
.bitfield
.qword
= 0;
1547 temp
.bitfield
.tbyte
= 0;
1548 temp
.bitfield
.xmmword
= 0;
1549 temp
.bitfield
.ymmword
= 0;
1550 if (operand_type_all_zero (&temp
))
1553 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1554 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1557 /* If given types g0 and g1 are registers they must be of the same type
1558 unless the expected operand type register overlap is null.
1559 Note that Acc in a template matches every size of reg. */
1562 operand_type_register_match (i386_operand_type m0
,
1563 i386_operand_type g0
,
1564 i386_operand_type t0
,
1565 i386_operand_type m1
,
1566 i386_operand_type g1
,
1567 i386_operand_type t1
)
1569 if (!operand_type_check (g0
, reg
))
1572 if (!operand_type_check (g1
, reg
))
1575 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1576 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1577 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1578 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1581 if (m0
.bitfield
.acc
)
1583 t0
.bitfield
.reg8
= 1;
1584 t0
.bitfield
.reg16
= 1;
1585 t0
.bitfield
.reg32
= 1;
1586 t0
.bitfield
.reg64
= 1;
1589 if (m1
.bitfield
.acc
)
1591 t1
.bitfield
.reg8
= 1;
1592 t1
.bitfield
.reg16
= 1;
1593 t1
.bitfield
.reg32
= 1;
1594 t1
.bitfield
.reg64
= 1;
1597 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1598 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1599 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1600 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1603 static INLINE
unsigned int
1604 mode_from_disp_size (i386_operand_type t
)
1606 if (t
.bitfield
.disp8
)
1608 else if (t
.bitfield
.disp16
1609 || t
.bitfield
.disp32
1610 || t
.bitfield
.disp32s
)
1617 fits_in_signed_byte (offsetT num
)
1619 return (num
>= -128) && (num
<= 127);
1623 fits_in_unsigned_byte (offsetT num
)
1625 return (num
& 0xff) == num
;
1629 fits_in_unsigned_word (offsetT num
)
1631 return (num
& 0xffff) == num
;
1635 fits_in_signed_word (offsetT num
)
1637 return (-32768 <= num
) && (num
<= 32767);
1641 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1646 return (!(((offsetT
) -1 << 31) & num
)
1647 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1649 } /* fits_in_signed_long() */
1652 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1657 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1659 } /* fits_in_unsigned_long() */
1662 fits_in_imm4 (offsetT num
)
1664 return (num
& 0xf) == num
;
1667 static i386_operand_type
1668 smallest_imm_type (offsetT num
)
1670 i386_operand_type t
;
1672 operand_type_set (&t
, 0);
1673 t
.bitfield
.imm64
= 1;
1675 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1677 /* This code is disabled on the 486 because all the Imm1 forms
1678 in the opcode table are slower on the i486. They're the
1679 versions with the implicitly specified single-position
1680 displacement, which has another syntax if you really want to
1682 t
.bitfield
.imm1
= 1;
1683 t
.bitfield
.imm8
= 1;
1684 t
.bitfield
.imm8s
= 1;
1685 t
.bitfield
.imm16
= 1;
1686 t
.bitfield
.imm32
= 1;
1687 t
.bitfield
.imm32s
= 1;
1689 else if (fits_in_signed_byte (num
))
1691 t
.bitfield
.imm8
= 1;
1692 t
.bitfield
.imm8s
= 1;
1693 t
.bitfield
.imm16
= 1;
1694 t
.bitfield
.imm32
= 1;
1695 t
.bitfield
.imm32s
= 1;
1697 else if (fits_in_unsigned_byte (num
))
1699 t
.bitfield
.imm8
= 1;
1700 t
.bitfield
.imm16
= 1;
1701 t
.bitfield
.imm32
= 1;
1702 t
.bitfield
.imm32s
= 1;
1704 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1706 t
.bitfield
.imm16
= 1;
1707 t
.bitfield
.imm32
= 1;
1708 t
.bitfield
.imm32s
= 1;
1710 else if (fits_in_signed_long (num
))
1712 t
.bitfield
.imm32
= 1;
1713 t
.bitfield
.imm32s
= 1;
1715 else if (fits_in_unsigned_long (num
))
1716 t
.bitfield
.imm32
= 1;
1722 offset_in_range (offsetT val
, int size
)
1728 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1729 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1730 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1732 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1737 /* If BFD64, sign extend val. */
1738 if (!use_rela_relocations
)
1739 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1740 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1742 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1744 char buf1
[40], buf2
[40];
1746 sprint_value (buf1
, val
);
1747 sprint_value (buf2
, val
& mask
);
1748 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1753 /* Returns 0 if attempting to add a prefix where one from the same
1754 class already exists, 1 if non rep/repne added, 2 if rep/repne
1757 add_prefix (unsigned int prefix
)
1762 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1763 && flag_code
== CODE_64BIT
)
1765 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1766 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1767 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1778 case CS_PREFIX_OPCODE
:
1779 case DS_PREFIX_OPCODE
:
1780 case ES_PREFIX_OPCODE
:
1781 case FS_PREFIX_OPCODE
:
1782 case GS_PREFIX_OPCODE
:
1783 case SS_PREFIX_OPCODE
:
1787 case REPNE_PREFIX_OPCODE
:
1788 case REPE_PREFIX_OPCODE
:
1791 case LOCK_PREFIX_OPCODE
:
1799 case ADDR_PREFIX_OPCODE
:
1803 case DATA_PREFIX_OPCODE
:
1807 if (i
.prefix
[q
] != 0)
1815 i
.prefix
[q
] |= prefix
;
1818 as_bad (_("same type of prefix used twice"));
1824 set_code_flag (int value
)
1827 if (flag_code
== CODE_64BIT
)
1829 cpu_arch_flags
.bitfield
.cpu64
= 1;
1830 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1834 cpu_arch_flags
.bitfield
.cpu64
= 0;
1835 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1837 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1839 as_bad (_("64bit mode not supported on this CPU."));
1841 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1843 as_bad (_("32bit mode not supported on this CPU."));
1845 stackop_size
= '\0';
1849 set_16bit_gcc_code_flag (int new_code_flag
)
1851 flag_code
= new_code_flag
;
1852 if (flag_code
!= CODE_16BIT
)
1854 cpu_arch_flags
.bitfield
.cpu64
= 0;
1855 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1856 stackop_size
= LONG_MNEM_SUFFIX
;
1860 set_intel_syntax (int syntax_flag
)
1862 /* Find out if register prefixing is specified. */
1863 int ask_naked_reg
= 0;
1866 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1868 char *string
= input_line_pointer
;
1869 int e
= get_symbol_end ();
1871 if (strcmp (string
, "prefix") == 0)
1873 else if (strcmp (string
, "noprefix") == 0)
1876 as_bad (_("bad argument to syntax directive."));
1877 *input_line_pointer
= e
;
1879 demand_empty_rest_of_line ();
1881 intel_syntax
= syntax_flag
;
1883 if (ask_naked_reg
== 0)
1884 allow_naked_reg
= (intel_syntax
1885 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1887 allow_naked_reg
= (ask_naked_reg
< 0);
1889 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1890 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1891 register_prefix
= allow_naked_reg
? "" : "%";
1895 set_intel_mnemonic (int mnemonic_flag
)
1897 intel_mnemonic
= mnemonic_flag
;
1901 set_allow_index_reg (int flag
)
1903 allow_index_reg
= flag
;
1907 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1911 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1913 char *string
= input_line_pointer
;
1914 int e
= get_symbol_end ();
1916 if (strcmp (string
, "none") == 0)
1917 sse_check
= sse_check_none
;
1918 else if (strcmp (string
, "warning") == 0)
1919 sse_check
= sse_check_warning
;
1920 else if (strcmp (string
, "error") == 0)
1921 sse_check
= sse_check_error
;
1923 as_bad (_("bad argument to sse_check directive."));
1924 *input_line_pointer
= e
;
1927 as_bad (_("missing argument for sse_check directive"));
1929 demand_empty_rest_of_line ();
1933 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1937 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1939 char *string
= input_line_pointer
;
1940 int e
= get_symbol_end ();
1942 i386_cpu_flags flags
;
1944 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1946 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1950 cpu_arch_name
= cpu_arch
[i
].name
;
1951 cpu_sub_arch_name
= NULL
;
1952 cpu_arch_flags
= cpu_arch
[i
].flags
;
1953 if (flag_code
== CODE_64BIT
)
1955 cpu_arch_flags
.bitfield
.cpu64
= 1;
1956 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1960 cpu_arch_flags
.bitfield
.cpu64
= 0;
1961 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1963 cpu_arch_isa
= cpu_arch
[i
].type
;
1964 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1965 if (!cpu_arch_tune_set
)
1967 cpu_arch_tune
= cpu_arch_isa
;
1968 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1973 flags
= cpu_flags_or (cpu_arch_flags
,
1975 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1977 if (cpu_sub_arch_name
)
1979 char *name
= cpu_sub_arch_name
;
1980 cpu_sub_arch_name
= concat (name
,
1982 (const char *) NULL
);
1986 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1987 cpu_arch_flags
= flags
;
1989 *input_line_pointer
= e
;
1990 demand_empty_rest_of_line ();
1994 if (i
>= ARRAY_SIZE (cpu_arch
))
1995 as_bad (_("no such architecture: `%s'"), string
);
1997 *input_line_pointer
= e
;
2000 as_bad (_("missing cpu architecture"));
2002 no_cond_jump_promotion
= 0;
2003 if (*input_line_pointer
== ','
2004 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2006 char *string
= ++input_line_pointer
;
2007 int e
= get_symbol_end ();
2009 if (strcmp (string
, "nojumps") == 0)
2010 no_cond_jump_promotion
= 1;
2011 else if (strcmp (string
, "jumps") == 0)
2014 as_bad (_("no such architecture modifier: `%s'"), string
);
2016 *input_line_pointer
= e
;
2019 demand_empty_rest_of_line ();
2025 if (!strcmp (default_arch
, "x86_64"))
2026 return bfd_mach_x86_64
;
2027 else if (!strcmp (default_arch
, "i386"))
2028 return bfd_mach_i386_i386
;
2030 as_fatal (_("Unknown architecture"));
2036 const char *hash_err
;
2038 /* Initialize op_hash hash table. */
2039 op_hash
= hash_new ();
2042 const template *optab
;
2043 templates
*core_optab
;
2045 /* Setup for loop. */
2047 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2048 core_optab
->start
= optab
;
2053 if (optab
->name
== NULL
2054 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2056 /* different name --> ship out current template list;
2057 add to hash table; & begin anew. */
2058 core_optab
->end
= optab
;
2059 hash_err
= hash_insert (op_hash
,
2061 (void *) core_optab
);
2064 as_fatal (_("Internal Error: Can't hash %s: %s"),
2068 if (optab
->name
== NULL
)
2070 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2071 core_optab
->start
= optab
;
2076 /* Initialize reg_hash hash table. */
2077 reg_hash
= hash_new ();
2079 const reg_entry
*regtab
;
2080 unsigned int regtab_size
= i386_regtab_size
;
2082 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2084 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2086 as_fatal (_("Internal Error: Can't hash %s: %s"),
2092 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2097 for (c
= 0; c
< 256; c
++)
2102 mnemonic_chars
[c
] = c
;
2103 register_chars
[c
] = c
;
2104 operand_chars
[c
] = c
;
2106 else if (ISLOWER (c
))
2108 mnemonic_chars
[c
] = c
;
2109 register_chars
[c
] = c
;
2110 operand_chars
[c
] = c
;
2112 else if (ISUPPER (c
))
2114 mnemonic_chars
[c
] = TOLOWER (c
);
2115 register_chars
[c
] = mnemonic_chars
[c
];
2116 operand_chars
[c
] = c
;
2119 if (ISALPHA (c
) || ISDIGIT (c
))
2120 identifier_chars
[c
] = c
;
2123 identifier_chars
[c
] = c
;
2124 operand_chars
[c
] = c
;
2129 identifier_chars
['@'] = '@';
2132 identifier_chars
['?'] = '?';
2133 operand_chars
['?'] = '?';
2135 digit_chars
['-'] = '-';
2136 mnemonic_chars
['_'] = '_';
2137 mnemonic_chars
['-'] = '-';
2138 mnemonic_chars
['.'] = '.';
2139 identifier_chars
['_'] = '_';
2140 identifier_chars
['.'] = '.';
2142 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2143 operand_chars
[(unsigned char) *p
] = *p
;
2146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2149 record_alignment (text_section
, 2);
2150 record_alignment (data_section
, 2);
2151 record_alignment (bss_section
, 2);
2155 if (flag_code
== CODE_64BIT
)
2157 x86_dwarf2_return_column
= 16;
2158 x86_cie_data_alignment
= -8;
2162 x86_dwarf2_return_column
= 8;
2163 x86_cie_data_alignment
= -4;
2168 i386_print_statistics (FILE *file
)
2170 hash_print_statistics (file
, "i386 opcode", op_hash
);
2171 hash_print_statistics (file
, "i386 register", reg_hash
);
2176 /* Debugging routines for md_assemble. */
2177 static void pte (template *);
2178 static void pt (i386_operand_type
);
2179 static void pe (expressionS
*);
2180 static void ps (symbolS
*);
2183 pi (char *line
, i386_insn
*x
)
2187 fprintf (stdout
, "%s: template ", line
);
2189 fprintf (stdout
, " address: base %s index %s scale %x\n",
2190 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2191 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2192 x
->log2_scale_factor
);
2193 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2194 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2195 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2196 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2197 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2198 (x
->rex
& REX_W
) != 0,
2199 (x
->rex
& REX_R
) != 0,
2200 (x
->rex
& REX_X
) != 0,
2201 (x
->rex
& REX_B
) != 0);
2202 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2203 x
->drex
.reg
, x
->drex
.rex
);
2204 for (i
= 0; i
< x
->operands
; i
++)
2206 fprintf (stdout
, " #%d: ", i
+ 1);
2208 fprintf (stdout
, "\n");
2209 if (x
->types
[i
].bitfield
.reg8
2210 || x
->types
[i
].bitfield
.reg16
2211 || x
->types
[i
].bitfield
.reg32
2212 || x
->types
[i
].bitfield
.reg64
2213 || x
->types
[i
].bitfield
.regmmx
2214 || x
->types
[i
].bitfield
.regxmm
2215 || x
->types
[i
].bitfield
.regymm
2216 || x
->types
[i
].bitfield
.sreg2
2217 || x
->types
[i
].bitfield
.sreg3
2218 || x
->types
[i
].bitfield
.control
2219 || x
->types
[i
].bitfield
.debug
2220 || x
->types
[i
].bitfield
.test
)
2221 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2222 if (operand_type_check (x
->types
[i
], imm
))
2224 if (operand_type_check (x
->types
[i
], disp
))
2225 pe (x
->op
[i
].disps
);
2233 fprintf (stdout
, " %d operands ", t
->operands
);
2234 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2235 if (t
->extension_opcode
!= None
)
2236 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2237 if (t
->opcode_modifier
.d
)
2238 fprintf (stdout
, "D");
2239 if (t
->opcode_modifier
.w
)
2240 fprintf (stdout
, "W");
2241 fprintf (stdout
, "\n");
2242 for (i
= 0; i
< t
->operands
; i
++)
2244 fprintf (stdout
, " #%d type ", i
+ 1);
2245 pt (t
->operand_types
[i
]);
2246 fprintf (stdout
, "\n");
2253 fprintf (stdout
, " operation %d\n", e
->X_op
);
2254 fprintf (stdout
, " add_number %ld (%lx)\n",
2255 (long) e
->X_add_number
, (long) e
->X_add_number
);
2256 if (e
->X_add_symbol
)
2258 fprintf (stdout
, " add_symbol ");
2259 ps (e
->X_add_symbol
);
2260 fprintf (stdout
, "\n");
2264 fprintf (stdout
, " op_symbol ");
2265 ps (e
->X_op_symbol
);
2266 fprintf (stdout
, "\n");
2273 fprintf (stdout
, "%s type %s%s",
2275 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2276 segment_name (S_GET_SEGMENT (s
)));
2279 static struct type_name
2281 i386_operand_type mask
;
2284 const type_names
[] =
2286 { OPERAND_TYPE_REG8
, "r8" },
2287 { OPERAND_TYPE_REG16
, "r16" },
2288 { OPERAND_TYPE_REG32
, "r32" },
2289 { OPERAND_TYPE_REG64
, "r64" },
2290 { OPERAND_TYPE_IMM8
, "i8" },
2291 { OPERAND_TYPE_IMM8
, "i8s" },
2292 { OPERAND_TYPE_IMM16
, "i16" },
2293 { OPERAND_TYPE_IMM32
, "i32" },
2294 { OPERAND_TYPE_IMM32S
, "i32s" },
2295 { OPERAND_TYPE_IMM64
, "i64" },
2296 { OPERAND_TYPE_IMM1
, "i1" },
2297 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2298 { OPERAND_TYPE_DISP8
, "d8" },
2299 { OPERAND_TYPE_DISP16
, "d16" },
2300 { OPERAND_TYPE_DISP32
, "d32" },
2301 { OPERAND_TYPE_DISP32S
, "d32s" },
2302 { OPERAND_TYPE_DISP64
, "d64" },
2303 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2304 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2305 { OPERAND_TYPE_CONTROL
, "control reg" },
2306 { OPERAND_TYPE_TEST
, "test reg" },
2307 { OPERAND_TYPE_DEBUG
, "debug reg" },
2308 { OPERAND_TYPE_FLOATREG
, "FReg" },
2309 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2310 { OPERAND_TYPE_SREG2
, "SReg2" },
2311 { OPERAND_TYPE_SREG3
, "SReg3" },
2312 { OPERAND_TYPE_ACC
, "Acc" },
2313 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2314 { OPERAND_TYPE_REGMMX
, "rMMX" },
2315 { OPERAND_TYPE_REGXMM
, "rXMM" },
2316 { OPERAND_TYPE_ESSEG
, "es" },
2317 { OPERAND_TYPE_VEX_IMM4
, "VEX i4" },
2321 pt (i386_operand_type t
)
2324 i386_operand_type a
;
2326 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2328 a
= operand_type_and (t
, type_names
[j
].mask
);
2329 if (!UINTS_ALL_ZERO (a
))
2330 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2335 #endif /* DEBUG386 */
2337 static bfd_reloc_code_real_type
2338 reloc (unsigned int size
,
2341 bfd_reloc_code_real_type other
)
2343 if (other
!= NO_RELOC
)
2345 reloc_howto_type
*reloc
;
2350 case BFD_RELOC_X86_64_GOT32
:
2351 return BFD_RELOC_X86_64_GOT64
;
2353 case BFD_RELOC_X86_64_PLTOFF64
:
2354 return BFD_RELOC_X86_64_PLTOFF64
;
2356 case BFD_RELOC_X86_64_GOTPC32
:
2357 other
= BFD_RELOC_X86_64_GOTPC64
;
2359 case BFD_RELOC_X86_64_GOTPCREL
:
2360 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2362 case BFD_RELOC_X86_64_TPOFF32
:
2363 other
= BFD_RELOC_X86_64_TPOFF64
;
2365 case BFD_RELOC_X86_64_DTPOFF32
:
2366 other
= BFD_RELOC_X86_64_DTPOFF64
;
2372 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2373 if (size
== 4 && flag_code
!= CODE_64BIT
)
2376 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2378 as_bad (_("unknown relocation (%u)"), other
);
2379 else if (size
!= bfd_get_reloc_size (reloc
))
2380 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2381 bfd_get_reloc_size (reloc
),
2383 else if (pcrel
&& !reloc
->pc_relative
)
2384 as_bad (_("non-pc-relative relocation for pc-relative field"));
2385 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2387 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2389 as_bad (_("relocated field and relocation type differ in signedness"));
2398 as_bad (_("there are no unsigned pc-relative relocations"));
2401 case 1: return BFD_RELOC_8_PCREL
;
2402 case 2: return BFD_RELOC_16_PCREL
;
2403 case 4: return BFD_RELOC_32_PCREL
;
2404 case 8: return BFD_RELOC_64_PCREL
;
2406 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2413 case 4: return BFD_RELOC_X86_64_32S
;
2418 case 1: return BFD_RELOC_8
;
2419 case 2: return BFD_RELOC_16
;
2420 case 4: return BFD_RELOC_32
;
2421 case 8: return BFD_RELOC_64
;
2423 as_bad (_("cannot do %s %u byte relocation"),
2424 sign
> 0 ? "signed" : "unsigned", size
);
2428 return BFD_RELOC_NONE
;
2431 /* Here we decide which fixups can be adjusted to make them relative to
2432 the beginning of the section instead of the symbol. Basically we need
2433 to make sure that the dynamic relocations are done correctly, so in
2434 some cases we force the original symbol to be used. */
2437 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2443 /* Don't adjust pc-relative references to merge sections in 64-bit
2445 if (use_rela_relocations
2446 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2450 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2451 and changed later by validate_fix. */
2452 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2453 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2456 /* adjust_reloc_syms doesn't know about the GOT. */
2457 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2458 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2459 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2460 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2461 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2462 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2463 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2470 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2471 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2472 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2473 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2483 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2484 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2491 intel_float_operand (const char *mnemonic
)
2493 /* Note that the value returned is meaningful only for opcodes with (memory)
2494 operands, hence the code here is free to improperly handle opcodes that
2495 have no operands (for better performance and smaller code). */
2497 if (mnemonic
[0] != 'f')
2498 return 0; /* non-math */
2500 switch (mnemonic
[1])
2502 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2503 the fs segment override prefix not currently handled because no
2504 call path can make opcodes without operands get here */
2506 return 2 /* integer op */;
2508 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2509 return 3; /* fldcw/fldenv */
2512 if (mnemonic
[2] != 'o' /* fnop */)
2513 return 3; /* non-waiting control op */
2516 if (mnemonic
[2] == 's')
2517 return 3; /* frstor/frstpm */
2520 if (mnemonic
[2] == 'a')
2521 return 3; /* fsave */
2522 if (mnemonic
[2] == 't')
2524 switch (mnemonic
[3])
2526 case 'c': /* fstcw */
2527 case 'd': /* fstdw */
2528 case 'e': /* fstenv */
2529 case 's': /* fsts[gw] */
2535 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2536 return 0; /* fxsave/fxrstor are not really math ops */
2543 /* Build the VEX prefix. */
2546 build_vex_prefix (void)
2548 unsigned int register_specifier
;
2549 unsigned int implied_prefix
;
2550 unsigned int vector_length
;
2552 /* Check register specifier. */
2553 if (i
.vex
.register_specifier
)
2555 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2556 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2557 register_specifier
+= 8;
2558 register_specifier
= ~register_specifier
& 0xf;
2561 register_specifier
= 0xf;
2563 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2565 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2570 case DATA_PREFIX_OPCODE
:
2573 case REPE_PREFIX_OPCODE
:
2576 case REPNE_PREFIX_OPCODE
:
2583 /* Use 2-byte VEX prefix if possible. */
2584 if (i
.tm
.opcode_modifier
.vex0f
2585 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2587 /* 2-byte VEX prefix. */
2591 i
.vex
.bytes
[0] = 0xc5;
2593 /* Check the REX.R bit. */
2594 r
= (i
.rex
& REX_R
) ? 0 : 1;
2595 i
.vex
.bytes
[1] = (r
<< 7
2596 | register_specifier
<< 3
2597 | vector_length
<< 2
2602 /* 3-byte VEX prefix. */
2605 if (i
.tm
.opcode_modifier
.vex0f
)
2607 else if (i
.tm
.opcode_modifier
.vex0f38
)
2609 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2615 i
.vex
.bytes
[0] = 0xc4;
2617 /* The high 3 bits of the second VEX byte are 1's compliment
2618 of RXB bits from REX. */
2619 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2621 /* Check the REX.W bit. */
2622 w
= (i
.rex
& REX_W
) ? 1 : 0;
2623 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2628 if (i
.tm
.opcode_modifier
.vexw1
)
2632 i
.vex
.bytes
[2] = (w
<< 7
2633 | register_specifier
<< 3
2634 | vector_length
<< 2
2640 process_immext (void)
2644 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2646 /* SSE3 Instructions have the fixed operands with an opcode
2647 suffix which is coded in the same place as an 8-bit immediate
2648 field would be. Here we check those operands and remove them
2652 for (x
= 0; x
< i
.operands
; x
++)
2653 if (i
.op
[x
].regs
->reg_num
!= x
)
2654 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2655 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2661 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2662 which is coded in the same place as an 8-bit immediate field
2663 would be. Here we fake an 8-bit immediate operand from the
2664 opcode suffix stored in tm.extension_opcode.
2666 SSE5 and AVX instructions also use this encoding, for some of
2667 3 argument instructions. */
2669 assert (i
.imm_operands
== 0
2671 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2673 || (i
.tm
.opcode_modifier
.vex
2674 && i
.operands
<= 4)));
2676 exp
= &im_expressions
[i
.imm_operands
++];
2677 i
.op
[i
.operands
].imms
= exp
;
2678 i
.types
[i
.operands
] = imm8
;
2680 exp
->X_op
= O_constant
;
2681 exp
->X_add_number
= i
.tm
.extension_opcode
;
2682 i
.tm
.extension_opcode
= None
;
2685 /* This is the guts of the machine-dependent assembler. LINE points to a
2686 machine dependent instruction. This function is supposed to emit
2687 the frags/bytes it assembles to. */
2690 md_assemble (char *line
)
2693 char mnemonic
[MAX_MNEM_SIZE
];
2695 /* Initialize globals. */
2696 memset (&i
, '\0', sizeof (i
));
2697 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2698 i
.reloc
[j
] = NO_RELOC
;
2699 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2700 memset (im_expressions
, '\0', sizeof (im_expressions
));
2701 save_stack_p
= save_stack
;
2703 /* First parse an instruction mnemonic & call i386_operand for the operands.
2704 We assume that the scrubber has arranged it so that line[0] is the valid
2705 start of a (possibly prefixed) mnemonic. */
2707 line
= parse_insn (line
, mnemonic
);
2711 line
= parse_operands (line
, mnemonic
);
2715 /* Now we've parsed the mnemonic into a set of templates, and have the
2716 operands at hand. */
2718 /* All intel opcodes have reversed operands except for "bound" and
2719 "enter". We also don't reverse intersegment "jmp" and "call"
2720 instructions with 2 immediate operands so that the immediate segment
2721 precedes the offset, as it does when in AT&T mode. */
2724 && (strcmp (mnemonic
, "bound") != 0)
2725 && (strcmp (mnemonic
, "invlpga") != 0)
2726 && !(operand_type_check (i
.types
[0], imm
)
2727 && operand_type_check (i
.types
[1], imm
)))
2730 /* The order of the immediates should be reversed
2731 for 2 immediates extrq and insertq instructions */
2732 if (i
.imm_operands
== 2
2733 && (strcmp (mnemonic
, "extrq") == 0
2734 || strcmp (mnemonic
, "insertq") == 0))
2735 swap_2_operands (0, 1);
2740 /* Don't optimize displacement for movabs since it only takes 64bit
2743 && (flag_code
!= CODE_64BIT
2744 || strcmp (mnemonic
, "movabs") != 0))
2747 /* Next, we find a template that matches the given insn,
2748 making sure the overlap of the given operands types is consistent
2749 with the template operand types. */
2751 if (!match_template ())
2754 if (sse_check
!= sse_check_none
2755 && !i
.tm
.opcode_modifier
.noavx
2756 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2757 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2758 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2759 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2760 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2761 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2763 (sse_check
== sse_check_warning
2765 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2768 /* Zap movzx and movsx suffix. The suffix has been set from
2769 "word ptr" or "byte ptr" on the source operand in Intel syntax
2770 or extracted from mnemonic in AT&T syntax. But we'll use
2771 the destination register to choose the suffix for encoding. */
2772 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2774 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2775 there is no suffix, the default will be byte extension. */
2776 if (i
.reg_operands
!= 2
2779 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2784 if (i
.tm
.opcode_modifier
.fwait
)
2785 if (!add_prefix (FWAIT_OPCODE
))
2788 /* Check string instruction segment overrides. */
2789 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2791 if (!check_string ())
2793 i
.disp_operands
= 0;
2796 if (!process_suffix ())
2799 /* Make still unresolved immediate matches conform to size of immediate
2800 given in i.suffix. */
2801 if (!finalize_imm ())
2804 if (i
.types
[0].bitfield
.imm1
)
2805 i
.imm_operands
= 0; /* kludge for shift insns. */
2807 for (j
= 0; j
< 3; j
++)
2808 if (i
.types
[j
].bitfield
.inoutportreg
2809 || i
.types
[j
].bitfield
.shiftcount
2810 || i
.types
[j
].bitfield
.acc
2811 || i
.types
[j
].bitfield
.floatacc
)
2814 /* ImmExt should be processed after SSE2AVX. */
2815 if (!i
.tm
.opcode_modifier
.sse2avx
2816 && i
.tm
.opcode_modifier
.immext
)
2819 /* For insns with operands there are more diddles to do to the opcode. */
2822 if (!process_operands ())
2825 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2827 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2828 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2831 if (i
.tm
.opcode_modifier
.vex
)
2832 build_vex_prefix ();
2834 /* Handle conversion of 'int $3' --> special int3 insn. */
2835 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2837 i
.tm
.base_opcode
= INT3_OPCODE
;
2841 if ((i
.tm
.opcode_modifier
.jump
2842 || i
.tm
.opcode_modifier
.jumpbyte
2843 || i
.tm
.opcode_modifier
.jumpdword
)
2844 && i
.op
[0].disps
->X_op
== O_constant
)
2846 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2847 the absolute address given by the constant. Since ix86 jumps and
2848 calls are pc relative, we need to generate a reloc. */
2849 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2850 i
.op
[0].disps
->X_op
= O_symbol
;
2853 if (i
.tm
.opcode_modifier
.rex64
)
2856 /* For 8 bit registers we need an empty rex prefix. Also if the
2857 instruction already has a prefix, we need to convert old
2858 registers to new ones. */
2860 if ((i
.types
[0].bitfield
.reg8
2861 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2862 || (i
.types
[1].bitfield
.reg8
2863 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2864 || ((i
.types
[0].bitfield
.reg8
2865 || i
.types
[1].bitfield
.reg8
)
2870 i
.rex
|= REX_OPCODE
;
2871 for (x
= 0; x
< 2; x
++)
2873 /* Look for 8 bit operand that uses old registers. */
2874 if (i
.types
[x
].bitfield
.reg8
2875 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2877 /* In case it is "hi" register, give up. */
2878 if (i
.op
[x
].regs
->reg_num
> 3)
2879 as_bad (_("can't encode register '%s%s' in an "
2880 "instruction requiring REX prefix."),
2881 register_prefix
, i
.op
[x
].regs
->reg_name
);
2883 /* Otherwise it is equivalent to the extended register.
2884 Since the encoding doesn't change this is merely
2885 cosmetic cleanup for debug output. */
2887 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2892 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2894 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2899 else if (i
.rex
!= 0)
2900 add_prefix (REX_OPCODE
| i
.rex
);
2902 /* We are ready to output the insn. */
2907 parse_insn (char *line
, char *mnemonic
)
2910 char *token_start
= l
;
2916 /* Non-zero if we found a prefix only acceptable with string insns. */
2917 const char *expecting_string_instruction
= NULL
;
2922 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2927 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2929 as_bad (_("no such instruction: `%s'"), token_start
);
2934 if (!is_space_char (*l
)
2935 && *l
!= END_OF_INSN
2937 || (*l
!= PREFIX_SEPARATOR
2940 as_bad (_("invalid character %s in mnemonic"),
2941 output_invalid (*l
));
2944 if (token_start
== l
)
2946 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2947 as_bad (_("expecting prefix; got nothing"));
2949 as_bad (_("expecting mnemonic; got nothing"));
2953 /* Look up instruction (or prefix) via hash table. */
2954 current_templates
= hash_find (op_hash
, mnemonic
);
2956 if (*l
!= END_OF_INSN
2957 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2958 && current_templates
2959 && current_templates
->start
->opcode_modifier
.isprefix
)
2961 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2963 as_bad ((flag_code
!= CODE_64BIT
2964 ? _("`%s' is only supported in 64-bit mode")
2965 : _("`%s' is not supported in 64-bit mode")),
2966 current_templates
->start
->name
);
2969 /* If we are in 16-bit mode, do not allow addr16 or data16.
2970 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2971 if ((current_templates
->start
->opcode_modifier
.size16
2972 || current_templates
->start
->opcode_modifier
.size32
)
2973 && flag_code
!= CODE_64BIT
2974 && (current_templates
->start
->opcode_modifier
.size32
2975 ^ (flag_code
== CODE_16BIT
)))
2977 as_bad (_("redundant %s prefix"),
2978 current_templates
->start
->name
);
2981 /* Add prefix, checking for repeated prefixes. */
2982 switch (add_prefix (current_templates
->start
->base_opcode
))
2987 expecting_string_instruction
= current_templates
->start
->name
;
2990 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2997 if (!current_templates
)
2999 /* Check if we should swap operand in encoding. */
3000 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3006 current_templates
= hash_find (op_hash
, mnemonic
);
3009 if (!current_templates
)
3012 /* See if we can get a match by trimming off a suffix. */
3015 case WORD_MNEM_SUFFIX
:
3016 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3017 i
.suffix
= SHORT_MNEM_SUFFIX
;
3019 case BYTE_MNEM_SUFFIX
:
3020 case QWORD_MNEM_SUFFIX
:
3021 i
.suffix
= mnem_p
[-1];
3023 current_templates
= hash_find (op_hash
, mnemonic
);
3025 case SHORT_MNEM_SUFFIX
:
3026 case LONG_MNEM_SUFFIX
:
3029 i
.suffix
= mnem_p
[-1];
3031 current_templates
= hash_find (op_hash
, mnemonic
);
3039 if (intel_float_operand (mnemonic
) == 1)
3040 i
.suffix
= SHORT_MNEM_SUFFIX
;
3042 i
.suffix
= LONG_MNEM_SUFFIX
;
3044 current_templates
= hash_find (op_hash
, mnemonic
);
3048 if (!current_templates
)
3050 as_bad (_("no such instruction: `%s'"), token_start
);
3055 if (current_templates
->start
->opcode_modifier
.jump
3056 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3058 /* Check for a branch hint. We allow ",pt" and ",pn" for
3059 predict taken and predict not taken respectively.
3060 I'm not sure that branch hints actually do anything on loop
3061 and jcxz insns (JumpByte) for current Pentium4 chips. They
3062 may work in the future and it doesn't hurt to accept them
3064 if (l
[0] == ',' && l
[1] == 'p')
3068 if (!add_prefix (DS_PREFIX_OPCODE
))
3072 else if (l
[2] == 'n')
3074 if (!add_prefix (CS_PREFIX_OPCODE
))
3080 /* Any other comma loses. */
3083 as_bad (_("invalid character %s in mnemonic"),
3084 output_invalid (*l
));
3088 /* Check if instruction is supported on specified architecture. */
3090 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3092 supported
|= cpu_flags_match (t
);
3093 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3097 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3099 as_bad (flag_code
== CODE_64BIT
3100 ? _("`%s' is not supported in 64-bit mode")
3101 : _("`%s' is only supported in 64-bit mode"),
3102 current_templates
->start
->name
);
3105 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3107 as_bad (_("`%s' is not supported on `%s%s'"),
3108 current_templates
->start
->name
, cpu_arch_name
,
3109 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3114 if (!cpu_arch_flags
.bitfield
.cpui386
3115 && (flag_code
!= CODE_16BIT
))
3117 as_warn (_("use .code16 to ensure correct addressing mode"));
3120 /* Check for rep/repne without a string instruction. */
3121 if (expecting_string_instruction
)
3123 static templates override
;
3125 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3126 if (t
->opcode_modifier
.isstring
)
3128 if (t
>= current_templates
->end
)
3130 as_bad (_("expecting string instruction after `%s'"),
3131 expecting_string_instruction
);
3134 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3135 if (!t
->opcode_modifier
.isstring
)
3138 current_templates
= &override
;
3145 parse_operands (char *l
, const char *mnemonic
)
3149 /* 1 if operand is pending after ','. */
3150 unsigned int expecting_operand
= 0;
3152 /* Non-zero if operand parens not balanced. */
3153 unsigned int paren_not_balanced
;
3155 while (*l
!= END_OF_INSN
)
3157 /* Skip optional white space before operand. */
3158 if (is_space_char (*l
))
3160 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3162 as_bad (_("invalid character %s before operand %d"),
3163 output_invalid (*l
),
3167 token_start
= l
; /* after white space */
3168 paren_not_balanced
= 0;
3169 while (paren_not_balanced
|| *l
!= ',')
3171 if (*l
== END_OF_INSN
)
3173 if (paren_not_balanced
)
3176 as_bad (_("unbalanced parenthesis in operand %d."),
3179 as_bad (_("unbalanced brackets in operand %d."),
3184 break; /* we are done */
3186 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3188 as_bad (_("invalid character %s in operand %d"),
3189 output_invalid (*l
),
3196 ++paren_not_balanced
;
3198 --paren_not_balanced
;
3203 ++paren_not_balanced
;
3205 --paren_not_balanced
;
3209 if (l
!= token_start
)
3210 { /* Yes, we've read in another operand. */
3211 unsigned int operand_ok
;
3212 this_operand
= i
.operands
++;
3213 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3214 if (i
.operands
> MAX_OPERANDS
)
3216 as_bad (_("spurious operands; (%d operands/instruction max)"),
3220 /* Now parse operand adding info to 'i' as we go along. */
3221 END_STRING_AND_SAVE (l
);
3225 i386_intel_operand (token_start
,
3226 intel_float_operand (mnemonic
));
3228 operand_ok
= i386_att_operand (token_start
);
3230 RESTORE_END_STRING (l
);
3236 if (expecting_operand
)
3238 expecting_operand_after_comma
:
3239 as_bad (_("expecting operand after ','; got nothing"));
3244 as_bad (_("expecting operand before ','; got nothing"));
3249 /* Now *l must be either ',' or END_OF_INSN. */
3252 if (*++l
== END_OF_INSN
)
3254 /* Just skip it, if it's \n complain. */
3255 goto expecting_operand_after_comma
;
3257 expecting_operand
= 1;
3264 swap_2_operands (int xchg1
, int xchg2
)
3266 union i386_op temp_op
;
3267 i386_operand_type temp_type
;
3268 enum bfd_reloc_code_real temp_reloc
;
3270 temp_type
= i
.types
[xchg2
];
3271 i
.types
[xchg2
] = i
.types
[xchg1
];
3272 i
.types
[xchg1
] = temp_type
;
3273 temp_op
= i
.op
[xchg2
];
3274 i
.op
[xchg2
] = i
.op
[xchg1
];
3275 i
.op
[xchg1
] = temp_op
;
3276 temp_reloc
= i
.reloc
[xchg2
];
3277 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3278 i
.reloc
[xchg1
] = temp_reloc
;
3282 swap_operands (void)
3288 swap_2_operands (1, i
.operands
- 2);
3291 swap_2_operands (0, i
.operands
- 1);
3297 if (i
.mem_operands
== 2)
3299 const seg_entry
*temp_seg
;
3300 temp_seg
= i
.seg
[0];
3301 i
.seg
[0] = i
.seg
[1];
3302 i
.seg
[1] = temp_seg
;
3306 /* Try to ensure constant immediates are represented in the smallest
3311 char guess_suffix
= 0;
3315 guess_suffix
= i
.suffix
;
3316 else if (i
.reg_operands
)
3318 /* Figure out a suffix from the last register operand specified.
3319 We can't do this properly yet, ie. excluding InOutPortReg,
3320 but the following works for instructions with immediates.
3321 In any case, we can't set i.suffix yet. */
3322 for (op
= i
.operands
; --op
>= 0;)
3323 if (i
.types
[op
].bitfield
.reg8
)
3325 guess_suffix
= BYTE_MNEM_SUFFIX
;
3328 else if (i
.types
[op
].bitfield
.reg16
)
3330 guess_suffix
= WORD_MNEM_SUFFIX
;
3333 else if (i
.types
[op
].bitfield
.reg32
)
3335 guess_suffix
= LONG_MNEM_SUFFIX
;
3338 else if (i
.types
[op
].bitfield
.reg64
)
3340 guess_suffix
= QWORD_MNEM_SUFFIX
;
3344 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3345 guess_suffix
= WORD_MNEM_SUFFIX
;
3347 for (op
= i
.operands
; --op
>= 0;)
3348 if (operand_type_check (i
.types
[op
], imm
))
3350 switch (i
.op
[op
].imms
->X_op
)
3353 /* If a suffix is given, this operand may be shortened. */
3354 switch (guess_suffix
)
3356 case LONG_MNEM_SUFFIX
:
3357 i
.types
[op
].bitfield
.imm32
= 1;
3358 i
.types
[op
].bitfield
.imm64
= 1;
3360 case WORD_MNEM_SUFFIX
:
3361 i
.types
[op
].bitfield
.imm16
= 1;
3362 i
.types
[op
].bitfield
.imm32
= 1;
3363 i
.types
[op
].bitfield
.imm32s
= 1;
3364 i
.types
[op
].bitfield
.imm64
= 1;
3366 case BYTE_MNEM_SUFFIX
:
3367 i
.types
[op
].bitfield
.imm8
= 1;
3368 i
.types
[op
].bitfield
.imm8s
= 1;
3369 i
.types
[op
].bitfield
.imm16
= 1;
3370 i
.types
[op
].bitfield
.imm32
= 1;
3371 i
.types
[op
].bitfield
.imm32s
= 1;
3372 i
.types
[op
].bitfield
.imm64
= 1;
3376 /* If this operand is at most 16 bits, convert it
3377 to a signed 16 bit number before trying to see
3378 whether it will fit in an even smaller size.
3379 This allows a 16-bit operand such as $0xffe0 to
3380 be recognised as within Imm8S range. */
3381 if ((i
.types
[op
].bitfield
.imm16
)
3382 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3384 i
.op
[op
].imms
->X_add_number
=
3385 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3387 if ((i
.types
[op
].bitfield
.imm32
)
3388 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3391 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3392 ^ ((offsetT
) 1 << 31))
3393 - ((offsetT
) 1 << 31));
3396 = operand_type_or (i
.types
[op
],
3397 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3399 /* We must avoid matching of Imm32 templates when 64bit
3400 only immediate is available. */
3401 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3402 i
.types
[op
].bitfield
.imm32
= 0;
3409 /* Symbols and expressions. */
3411 /* Convert symbolic operand to proper sizes for matching, but don't
3412 prevent matching a set of insns that only supports sizes other
3413 than those matching the insn suffix. */
3415 i386_operand_type mask
, allowed
;
3418 operand_type_set (&mask
, 0);
3419 operand_type_set (&allowed
, 0);
3421 for (t
= current_templates
->start
;
3422 t
< current_templates
->end
;
3424 allowed
= operand_type_or (allowed
,
3425 t
->operand_types
[op
]);
3426 switch (guess_suffix
)
3428 case QWORD_MNEM_SUFFIX
:
3429 mask
.bitfield
.imm64
= 1;
3430 mask
.bitfield
.imm32s
= 1;
3432 case LONG_MNEM_SUFFIX
:
3433 mask
.bitfield
.imm32
= 1;
3435 case WORD_MNEM_SUFFIX
:
3436 mask
.bitfield
.imm16
= 1;
3438 case BYTE_MNEM_SUFFIX
:
3439 mask
.bitfield
.imm8
= 1;
3444 allowed
= operand_type_and (mask
, allowed
);
3445 if (!operand_type_all_zero (&allowed
))
3446 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3453 /* Try to use the smallest displacement type too. */
3455 optimize_disp (void)
3459 for (op
= i
.operands
; --op
>= 0;)
3460 if (operand_type_check (i
.types
[op
], disp
))
3462 if (i
.op
[op
].disps
->X_op
== O_constant
)
3464 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3466 if (i
.types
[op
].bitfield
.disp16
3467 && (disp
& ~(offsetT
) 0xffff) == 0)
3469 /* If this operand is at most 16 bits, convert
3470 to a signed 16 bit number and don't use 64bit
3472 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3473 i
.types
[op
].bitfield
.disp64
= 0;
3475 if (i
.types
[op
].bitfield
.disp32
3476 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3478 /* If this operand is at most 32 bits, convert
3479 to a signed 32 bit number and don't use 64bit
3481 disp
&= (((offsetT
) 2 << 31) - 1);
3482 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3483 i
.types
[op
].bitfield
.disp64
= 0;
3485 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3487 i
.types
[op
].bitfield
.disp8
= 0;
3488 i
.types
[op
].bitfield
.disp16
= 0;
3489 i
.types
[op
].bitfield
.disp32
= 0;
3490 i
.types
[op
].bitfield
.disp32s
= 0;
3491 i
.types
[op
].bitfield
.disp64
= 0;
3495 else if (flag_code
== CODE_64BIT
)
3497 if (fits_in_signed_long (disp
))
3499 i
.types
[op
].bitfield
.disp64
= 0;
3500 i
.types
[op
].bitfield
.disp32s
= 1;
3502 if (fits_in_unsigned_long (disp
))
3503 i
.types
[op
].bitfield
.disp32
= 1;
3505 if ((i
.types
[op
].bitfield
.disp32
3506 || i
.types
[op
].bitfield
.disp32s
3507 || i
.types
[op
].bitfield
.disp16
)
3508 && fits_in_signed_byte (disp
))
3509 i
.types
[op
].bitfield
.disp8
= 1;
3511 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3512 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3514 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3515 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3516 i
.types
[op
].bitfield
.disp8
= 0;
3517 i
.types
[op
].bitfield
.disp16
= 0;
3518 i
.types
[op
].bitfield
.disp32
= 0;
3519 i
.types
[op
].bitfield
.disp32s
= 0;
3520 i
.types
[op
].bitfield
.disp64
= 0;
3523 /* We only support 64bit displacement on constants. */
3524 i
.types
[op
].bitfield
.disp64
= 0;
3528 /* Check if operands are valid for the instrucrtion. Update VEX
3532 VEX_check_operands (const template *t
)
3534 if (!t
->opcode_modifier
.vex
)
3537 /* Only check VEX_Imm4, which must be the first operand. */
3538 if (t
->operand_types
[0].bitfield
.vex_imm4
)
3540 if (i
.op
[0].imms
->X_op
!= O_constant
3541 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3544 /* Turn off Imm8 so that update_imm won't complain. */
3545 i
.types
[0] = vex_imm4
;
3552 match_template (void)
3554 /* Points to template once we've found it. */
3556 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3557 i386_operand_type overlap4
;
3558 unsigned int found_reverse_match
;
3559 i386_opcode_modifier suffix_check
;
3560 i386_operand_type operand_types
[MAX_OPERANDS
];
3561 int addr_prefix_disp
;
3563 unsigned int found_cpu_match
;
3564 unsigned int check_register
;
3566 #if MAX_OPERANDS != 5
3567 # error "MAX_OPERANDS must be 5."
3570 found_reverse_match
= 0;
3571 addr_prefix_disp
= -1;
3573 memset (&suffix_check
, 0, sizeof (suffix_check
));
3574 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3575 suffix_check
.no_bsuf
= 1;
3576 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3577 suffix_check
.no_wsuf
= 1;
3578 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3579 suffix_check
.no_ssuf
= 1;
3580 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3581 suffix_check
.no_lsuf
= 1;
3582 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3583 suffix_check
.no_qsuf
= 1;
3584 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3585 suffix_check
.no_ldsuf
= 1;
3587 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3589 addr_prefix_disp
= -1;
3591 /* Must have right number of operands. */
3592 if (i
.operands
!= t
->operands
)
3595 /* Check processor support. */
3596 found_cpu_match
= (cpu_flags_match (t
)
3597 == CPU_FLAGS_PERFECT_MATCH
);
3598 if (!found_cpu_match
)
3601 /* Check old gcc support. */
3602 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3605 /* Check AT&T mnemonic. */
3606 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3609 /* Check AT&T syntax Intel syntax. */
3610 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3611 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3614 /* Check the suffix, except for some instructions in intel mode. */
3615 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3616 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3617 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3618 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3619 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3620 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3621 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3624 if (!operand_size_match (t
))
3627 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3628 operand_types
[j
] = t
->operand_types
[j
];
3630 /* In general, don't allow 64-bit operands in 32-bit mode. */
3631 if (i
.suffix
== QWORD_MNEM_SUFFIX
3632 && flag_code
!= CODE_64BIT
3634 ? (!t
->opcode_modifier
.ignoresize
3635 && !intel_float_operand (t
->name
))
3636 : intel_float_operand (t
->name
) != 2)
3637 && ((!operand_types
[0].bitfield
.regmmx
3638 && !operand_types
[0].bitfield
.regxmm
3639 && !operand_types
[0].bitfield
.regymm
)
3640 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3641 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3642 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3643 && (t
->base_opcode
!= 0x0fc7
3644 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3647 /* In general, don't allow 32-bit operands on pre-386. */
3648 else if (i
.suffix
== LONG_MNEM_SUFFIX
3649 && !cpu_arch_flags
.bitfield
.cpui386
3651 ? (!t
->opcode_modifier
.ignoresize
3652 && !intel_float_operand (t
->name
))
3653 : intel_float_operand (t
->name
) != 2)
3654 && ((!operand_types
[0].bitfield
.regmmx
3655 && !operand_types
[0].bitfield
.regxmm
)
3656 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3657 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3660 /* Do not verify operands when there are none. */
3664 /* We've found a match; break out of loop. */
3668 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3669 into Disp32/Disp16/Disp32 operand. */
3670 if (i
.prefix
[ADDR_PREFIX
] != 0)
3672 /* There should be only one Disp operand. */
3676 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3678 if (operand_types
[j
].bitfield
.disp16
)
3680 addr_prefix_disp
= j
;
3681 operand_types
[j
].bitfield
.disp32
= 1;
3682 operand_types
[j
].bitfield
.disp16
= 0;
3688 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3690 if (operand_types
[j
].bitfield
.disp32
)
3692 addr_prefix_disp
= j
;
3693 operand_types
[j
].bitfield
.disp32
= 0;
3694 operand_types
[j
].bitfield
.disp16
= 1;
3700 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3702 if (operand_types
[j
].bitfield
.disp64
)
3704 addr_prefix_disp
= j
;
3705 operand_types
[j
].bitfield
.disp64
= 0;
3706 operand_types
[j
].bitfield
.disp32
= 1;
3714 /* We check register size only if size of operands can be
3715 encoded the canonical way. */
3716 check_register
= t
->opcode_modifier
.w
;
3717 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3718 switch (t
->operands
)
3721 if (!operand_type_match (overlap0
, i
.types
[0]))
3725 /* xchg %eax, %eax is a special case. It is an aliase for nop
3726 only in 32bit mode and we can use opcode 0x90. In 64bit
3727 mode, we can't use 0x90 for xchg %eax, %eax since it should
3728 zero-extend %eax to %rax. */
3729 if (flag_code
== CODE_64BIT
3730 && t
->base_opcode
== 0x90
3731 && operand_type_equal (&i
.types
[0], &acc32
)
3732 && operand_type_equal (&i
.types
[1], &acc32
))
3736 /* If we swap operand in encoding, we either match
3737 the next one or reverse direction of operands. */
3738 if (t
->opcode_modifier
.s
)
3740 else if (t
->opcode_modifier
.d
)
3747 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3748 if (!operand_type_match (overlap0
, i
.types
[0])
3749 || !operand_type_match (overlap1
, i
.types
[1])
3751 && !operand_type_register_match (overlap0
, i
.types
[0],
3753 overlap1
, i
.types
[1],
3756 /* Check if other direction is valid ... */
3757 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3761 /* Try reversing direction of operands. */
3762 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3763 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3764 if (!operand_type_match (overlap0
, i
.types
[0])
3765 || !operand_type_match (overlap1
, i
.types
[1])
3767 && !operand_type_register_match (overlap0
,
3774 /* Does not match either direction. */
3777 /* found_reverse_match holds which of D or FloatDR
3779 if (t
->opcode_modifier
.d
)
3780 found_reverse_match
= Opcode_D
;
3781 else if (t
->opcode_modifier
.floatd
)
3782 found_reverse_match
= Opcode_FloatD
;
3784 found_reverse_match
= 0;
3785 if (t
->opcode_modifier
.floatr
)
3786 found_reverse_match
|= Opcode_FloatR
;
3790 /* Found a forward 2 operand match here. */
3791 switch (t
->operands
)
3794 overlap4
= operand_type_and (i
.types
[4],
3797 overlap3
= operand_type_and (i
.types
[3],
3800 overlap2
= operand_type_and (i
.types
[2],
3805 switch (t
->operands
)
3808 if (!operand_type_match (overlap4
, i
.types
[4])
3809 || !operand_type_register_match (overlap3
,
3817 if (!operand_type_match (overlap3
, i
.types
[3])
3819 && !operand_type_register_match (overlap2
,
3827 /* Here we make use of the fact that there are no
3828 reverse match 3 operand instructions, and all 3
3829 operand instructions only need to be checked for
3830 register consistency between operands 2 and 3. */
3831 if (!operand_type_match (overlap2
, i
.types
[2])
3833 && !operand_type_register_match (overlap1
,
3843 /* Found either forward/reverse 2, 3 or 4 operand match here:
3844 slip through to break. */
3846 if (!found_cpu_match
)
3848 found_reverse_match
= 0;
3852 /* Check if VEX operands are valid. */
3853 if (VEX_check_operands (t
))
3856 /* We've found a match; break out of loop. */
3860 if (t
== current_templates
->end
)
3862 /* We found no match. */
3864 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3865 current_templates
->start
->name
);
3867 as_bad (_("suffix or operands invalid for `%s'"),
3868 current_templates
->start
->name
);
3872 if (!quiet_warnings
)
3875 && (i
.types
[0].bitfield
.jumpabsolute
3876 != operand_types
[0].bitfield
.jumpabsolute
))
3878 as_warn (_("indirect %s without `*'"), t
->name
);
3881 if (t
->opcode_modifier
.isprefix
3882 && t
->opcode_modifier
.ignoresize
)
3884 /* Warn them that a data or address size prefix doesn't
3885 affect assembly of the next line of code. */
3886 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3890 /* Copy the template we found. */
3893 if (addr_prefix_disp
!= -1)
3894 i
.tm
.operand_types
[addr_prefix_disp
]
3895 = operand_types
[addr_prefix_disp
];
3897 if (found_reverse_match
)
3899 /* If we found a reverse match we must alter the opcode
3900 direction bit. found_reverse_match holds bits to change
3901 (different for int & float insns). */
3903 i
.tm
.base_opcode
^= found_reverse_match
;
3905 i
.tm
.operand_types
[0] = operand_types
[1];
3906 i
.tm
.operand_types
[1] = operand_types
[0];
3915 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3916 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3918 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3920 as_bad (_("`%s' operand %d must use `%ses' segment"),
3926 /* There's only ever one segment override allowed per instruction.
3927 This instruction possibly has a legal segment override on the
3928 second operand, so copy the segment to where non-string
3929 instructions store it, allowing common code. */
3930 i
.seg
[0] = i
.seg
[1];
3932 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3934 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3936 as_bad (_("`%s' operand %d must use `%ses' segment"),
3947 process_suffix (void)
3949 /* If matched instruction specifies an explicit instruction mnemonic
3951 if (i
.tm
.opcode_modifier
.size16
)
3952 i
.suffix
= WORD_MNEM_SUFFIX
;
3953 else if (i
.tm
.opcode_modifier
.size32
)
3954 i
.suffix
= LONG_MNEM_SUFFIX
;
3955 else if (i
.tm
.opcode_modifier
.size64
)
3956 i
.suffix
= QWORD_MNEM_SUFFIX
;
3957 else if (i
.reg_operands
)
3959 /* If there's no instruction mnemonic suffix we try to invent one
3960 based on register operands. */
3963 /* We take i.suffix from the last register operand specified,
3964 Destination register type is more significant than source
3965 register type. crc32 in SSE4.2 prefers source register
3967 if (i
.tm
.base_opcode
== 0xf20f38f1)
3969 if (i
.types
[0].bitfield
.reg16
)
3970 i
.suffix
= WORD_MNEM_SUFFIX
;
3971 else if (i
.types
[0].bitfield
.reg32
)
3972 i
.suffix
= LONG_MNEM_SUFFIX
;
3973 else if (i
.types
[0].bitfield
.reg64
)
3974 i
.suffix
= QWORD_MNEM_SUFFIX
;
3976 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3978 if (i
.types
[0].bitfield
.reg8
)
3979 i
.suffix
= BYTE_MNEM_SUFFIX
;
3986 if (i
.tm
.base_opcode
== 0xf20f38f1
3987 || i
.tm
.base_opcode
== 0xf20f38f0)
3989 /* We have to know the operand size for crc32. */
3990 as_bad (_("ambiguous memory operand size for `%s`"),
3995 for (op
= i
.operands
; --op
>= 0;)
3996 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3998 if (i
.types
[op
].bitfield
.reg8
)
4000 i
.suffix
= BYTE_MNEM_SUFFIX
;
4003 else if (i
.types
[op
].bitfield
.reg16
)
4005 i
.suffix
= WORD_MNEM_SUFFIX
;
4008 else if (i
.types
[op
].bitfield
.reg32
)
4010 i
.suffix
= LONG_MNEM_SUFFIX
;
4013 else if (i
.types
[op
].bitfield
.reg64
)
4015 i
.suffix
= QWORD_MNEM_SUFFIX
;
4021 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4023 if (!check_byte_reg ())
4026 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4028 if (!check_long_reg ())
4031 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4034 && i
.tm
.opcode_modifier
.ignoresize
4035 && i
.tm
.opcode_modifier
.no_qsuf
)
4037 else if (!check_qword_reg ())
4040 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4042 if (!check_word_reg ())
4045 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4046 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4048 /* Skip if the instruction has x/y suffix. match_template
4049 should check if it is a valid suffix. */
4051 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4052 /* Do nothing if the instruction is going to ignore the prefix. */
4057 else if (i
.tm
.opcode_modifier
.defaultsize
4059 /* exclude fldenv/frstor/fsave/fstenv */
4060 && i
.tm
.opcode_modifier
.no_ssuf
)
4062 i
.suffix
= stackop_size
;
4064 else if (intel_syntax
4066 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4067 || i
.tm
.opcode_modifier
.jumpbyte
4068 || i
.tm
.opcode_modifier
.jumpintersegment
4069 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4070 && i
.tm
.extension_opcode
<= 3)))
4075 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4077 i
.suffix
= QWORD_MNEM_SUFFIX
;
4081 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4082 i
.suffix
= LONG_MNEM_SUFFIX
;
4085 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4086 i
.suffix
= WORD_MNEM_SUFFIX
;
4095 if (i
.tm
.opcode_modifier
.w
)
4097 as_bad (_("no instruction mnemonic suffix given and "
4098 "no register operands; can't size instruction"));
4104 unsigned int suffixes
;
4106 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4107 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4109 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4111 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4113 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4115 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4118 /* There are more than suffix matches. */
4119 if (i
.tm
.opcode_modifier
.w
4120 || ((suffixes
& (suffixes
- 1))
4121 && !i
.tm
.opcode_modifier
.defaultsize
4122 && !i
.tm
.opcode_modifier
.ignoresize
))
4124 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4130 /* Change the opcode based on the operand size given by i.suffix;
4131 We don't need to change things for byte insns. */
4134 && i
.suffix
!= BYTE_MNEM_SUFFIX
4135 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4136 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4138 /* It's not a byte, select word/dword operation. */
4139 if (i
.tm
.opcode_modifier
.w
)
4141 if (i
.tm
.opcode_modifier
.shortform
)
4142 i
.tm
.base_opcode
|= 8;
4144 i
.tm
.base_opcode
|= 1;
4147 /* Now select between word & dword operations via the operand
4148 size prefix, except for instructions that will ignore this
4150 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4152 /* The address size override prefix changes the size of the
4154 if ((flag_code
== CODE_32BIT
4155 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4156 || (flag_code
!= CODE_32BIT
4157 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4158 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4161 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4162 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4163 && !i
.tm
.opcode_modifier
.ignoresize
4164 && !i
.tm
.opcode_modifier
.floatmf
4165 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4166 || (flag_code
== CODE_64BIT
4167 && i
.tm
.opcode_modifier
.jumpbyte
)))
4169 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4171 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4172 prefix
= ADDR_PREFIX_OPCODE
;
4174 if (!add_prefix (prefix
))
4178 /* Set mode64 for an operand. */
4179 if (i
.suffix
== QWORD_MNEM_SUFFIX
4180 && flag_code
== CODE_64BIT
4181 && !i
.tm
.opcode_modifier
.norex64
)
4183 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4184 need rex64. cmpxchg8b is also a special case. */
4185 if (! (i
.operands
== 2
4186 && i
.tm
.base_opcode
== 0x90
4187 && i
.tm
.extension_opcode
== None
4188 && operand_type_equal (&i
.types
[0], &acc64
)
4189 && operand_type_equal (&i
.types
[1], &acc64
))
4190 && ! (i
.operands
== 1
4191 && i
.tm
.base_opcode
== 0xfc7
4192 && i
.tm
.extension_opcode
== 1
4193 && !operand_type_check (i
.types
[0], reg
)
4194 && operand_type_check (i
.types
[0], anymem
)))
4198 /* Size floating point instruction. */
4199 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4200 if (i
.tm
.opcode_modifier
.floatmf
)
4201 i
.tm
.base_opcode
^= 4;
4208 check_byte_reg (void)
4212 for (op
= i
.operands
; --op
>= 0;)
4214 /* If this is an eight bit register, it's OK. If it's the 16 or
4215 32 bit version of an eight bit register, we will just use the
4216 low portion, and that's OK too. */
4217 if (i
.types
[op
].bitfield
.reg8
)
4220 /* Don't generate this warning if not needed. */
4221 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4224 /* crc32 doesn't generate this warning. */
4225 if (i
.tm
.base_opcode
== 0xf20f38f0)
4228 if ((i
.types
[op
].bitfield
.reg16
4229 || i
.types
[op
].bitfield
.reg32
4230 || i
.types
[op
].bitfield
.reg64
)
4231 && i
.op
[op
].regs
->reg_num
< 4)
4233 /* Prohibit these changes in the 64bit mode, since the
4234 lowering is more complicated. */
4235 if (flag_code
== CODE_64BIT
4236 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4238 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4239 register_prefix
, i
.op
[op
].regs
->reg_name
,
4243 #if REGISTER_WARNINGS
4245 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4246 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4248 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4249 ? REGNAM_AL
- REGNAM_AX
4250 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4252 i
.op
[op
].regs
->reg_name
,
4257 /* Any other register is bad. */
4258 if (i
.types
[op
].bitfield
.reg16
4259 || i
.types
[op
].bitfield
.reg32
4260 || i
.types
[op
].bitfield
.reg64
4261 || i
.types
[op
].bitfield
.regmmx
4262 || i
.types
[op
].bitfield
.regxmm
4263 || i
.types
[op
].bitfield
.regymm
4264 || i
.types
[op
].bitfield
.sreg2
4265 || i
.types
[op
].bitfield
.sreg3
4266 || i
.types
[op
].bitfield
.control
4267 || i
.types
[op
].bitfield
.debug
4268 || i
.types
[op
].bitfield
.test
4269 || i
.types
[op
].bitfield
.floatreg
4270 || i
.types
[op
].bitfield
.floatacc
)
4272 as_bad (_("`%s%s' not allowed with `%s%c'"),
4274 i
.op
[op
].regs
->reg_name
,
4284 check_long_reg (void)
4288 for (op
= i
.operands
; --op
>= 0;)
4289 /* Reject eight bit registers, except where the template requires
4290 them. (eg. movzb) */
4291 if (i
.types
[op
].bitfield
.reg8
4292 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4293 || i
.tm
.operand_types
[op
].bitfield
.reg32
4294 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4296 as_bad (_("`%s%s' not allowed with `%s%c'"),
4298 i
.op
[op
].regs
->reg_name
,
4303 /* Warn if the e prefix on a general reg is missing. */
4304 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4305 && i
.types
[op
].bitfield
.reg16
4306 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4307 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4309 /* Prohibit these changes in the 64bit mode, since the
4310 lowering is more complicated. */
4311 if (flag_code
== CODE_64BIT
)
4313 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4314 register_prefix
, i
.op
[op
].regs
->reg_name
,
4318 #if REGISTER_WARNINGS
4320 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4322 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4324 i
.op
[op
].regs
->reg_name
,
4328 /* Warn if the r prefix on a general reg is missing. */
4329 else if (i
.types
[op
].bitfield
.reg64
4330 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4331 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4334 && i
.tm
.opcode_modifier
.toqword
4335 && !i
.types
[0].bitfield
.regxmm
)
4337 /* Convert to QWORD. We want REX byte. */
4338 i
.suffix
= QWORD_MNEM_SUFFIX
;
4342 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4343 register_prefix
, i
.op
[op
].regs
->reg_name
,
4352 check_qword_reg (void)
4356 for (op
= i
.operands
; --op
>= 0; )
4357 /* Reject eight bit registers, except where the template requires
4358 them. (eg. movzb) */
4359 if (i
.types
[op
].bitfield
.reg8
4360 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4361 || i
.tm
.operand_types
[op
].bitfield
.reg32
4362 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4364 as_bad (_("`%s%s' not allowed with `%s%c'"),
4366 i
.op
[op
].regs
->reg_name
,
4371 /* Warn if the e prefix on a general reg is missing. */
4372 else if ((i
.types
[op
].bitfield
.reg16
4373 || i
.types
[op
].bitfield
.reg32
)
4374 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4375 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4377 /* Prohibit these changes in the 64bit mode, since the
4378 lowering is more complicated. */
4380 && i
.tm
.opcode_modifier
.todword
4381 && !i
.types
[0].bitfield
.regxmm
)
4383 /* Convert to DWORD. We don't want REX byte. */
4384 i
.suffix
= LONG_MNEM_SUFFIX
;
4388 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4389 register_prefix
, i
.op
[op
].regs
->reg_name
,
4398 check_word_reg (void)
4401 for (op
= i
.operands
; --op
>= 0;)
4402 /* Reject eight bit registers, except where the template requires
4403 them. (eg. movzb) */
4404 if (i
.types
[op
].bitfield
.reg8
4405 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4406 || i
.tm
.operand_types
[op
].bitfield
.reg32
4407 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4409 as_bad (_("`%s%s' not allowed with `%s%c'"),
4411 i
.op
[op
].regs
->reg_name
,
4416 /* Warn if the e prefix on a general reg is present. */
4417 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4418 && i
.types
[op
].bitfield
.reg32
4419 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4420 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4422 /* Prohibit these changes in the 64bit mode, since the
4423 lowering is more complicated. */
4424 if (flag_code
== CODE_64BIT
)
4426 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4427 register_prefix
, i
.op
[op
].regs
->reg_name
,
4432 #if REGISTER_WARNINGS
4433 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4435 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4437 i
.op
[op
].regs
->reg_name
,
4445 update_imm (unsigned int j
)
4447 i386_operand_type overlap
;
4449 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4450 if ((overlap
.bitfield
.imm8
4451 || overlap
.bitfield
.imm8s
4452 || overlap
.bitfield
.imm16
4453 || overlap
.bitfield
.imm32
4454 || overlap
.bitfield
.imm32s
4455 || overlap
.bitfield
.imm64
)
4456 && !operand_type_equal (&overlap
, &imm8
)
4457 && !operand_type_equal (&overlap
, &imm8s
)
4458 && !operand_type_equal (&overlap
, &imm16
)
4459 && !operand_type_equal (&overlap
, &imm32
)
4460 && !operand_type_equal (&overlap
, &imm32s
)
4461 && !operand_type_equal (&overlap
, &imm64
))
4465 i386_operand_type temp
;
4467 operand_type_set (&temp
, 0);
4468 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4470 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4471 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4473 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4474 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4475 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4477 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4478 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4481 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4484 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4485 || operand_type_equal (&overlap
, &imm16_32
)
4486 || operand_type_equal (&overlap
, &imm16_32s
))
4488 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4493 if (!operand_type_equal (&overlap
, &imm8
)
4494 && !operand_type_equal (&overlap
, &imm8s
)
4495 && !operand_type_equal (&overlap
, &imm16
)
4496 && !operand_type_equal (&overlap
, &imm32
)
4497 && !operand_type_equal (&overlap
, &imm32s
)
4498 && !operand_type_equal (&overlap
, &imm64
))
4500 as_bad (_("no instruction mnemonic suffix given; "
4501 "can't determine immediate size"));
4505 i
.types
[j
] = overlap
;
4515 for (j
= 0; j
< 2; j
++)
4516 if (update_imm (j
) == 0)
4519 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4520 assert (operand_type_check (i
.types
[2], imm
) == 0);
4528 i
.drex
.modrm_reg
= 0;
4529 i
.drex
.modrm_regmem
= 0;
4531 /* SSE5 4 operand instructions must have the destination the same as
4532 one of the inputs. Figure out the destination register and cache
4533 it away in the drex field, and remember which fields to use for
4535 if (i
.tm
.opcode_modifier
.drex
4536 && i
.tm
.opcode_modifier
.drexv
4539 i
.tm
.extension_opcode
= None
;
4541 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4542 if (i
.types
[0].bitfield
.regxmm
!= 0
4543 && i
.types
[1].bitfield
.regxmm
!= 0
4544 && i
.types
[2].bitfield
.regxmm
!= 0
4545 && i
.types
[3].bitfield
.regxmm
!= 0
4546 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4547 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4549 /* Clear the arguments that are stored in drex. */
4550 operand_type_set (&i
.types
[0], 0);
4551 operand_type_set (&i
.types
[3], 0);
4552 i
.reg_operands
-= 2;
4554 /* There are two different ways to encode a 4 operand
4555 instruction with all registers that uses OC1 set to
4556 0 or 1. Favor setting OC1 to 0 since this mimics the
4557 actions of other SSE5 assemblers. Use modrm encoding 2
4558 for register/register. Include the high order bit that
4559 is normally stored in the REX byte in the register
4561 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4562 i
.drex
.modrm_reg
= 2;
4563 i
.drex
.modrm_regmem
= 1;
4564 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4565 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4568 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4569 else if (i
.types
[0].bitfield
.regxmm
!= 0
4570 && i
.types
[1].bitfield
.regxmm
!= 0
4571 && (i
.types
[2].bitfield
.regxmm
4572 || operand_type_check (i
.types
[2], anymem
))
4573 && i
.types
[3].bitfield
.regxmm
!= 0
4574 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4575 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4577 /* clear the arguments that are stored in drex */
4578 operand_type_set (&i
.types
[0], 0);
4579 operand_type_set (&i
.types
[3], 0);
4580 i
.reg_operands
-= 2;
4582 /* Specify the modrm encoding for memory addressing. Include
4583 the high order bit that is normally stored in the REX byte
4584 in the register field. */
4585 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4586 i
.drex
.modrm_reg
= 1;
4587 i
.drex
.modrm_regmem
= 2;
4588 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4589 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4592 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4593 else if (i
.types
[0].bitfield
.regxmm
!= 0
4594 && operand_type_check (i
.types
[1], anymem
) != 0
4595 && i
.types
[2].bitfield
.regxmm
!= 0
4596 && i
.types
[3].bitfield
.regxmm
!= 0
4597 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4598 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4600 /* Clear the arguments that are stored in drex. */
4601 operand_type_set (&i
.types
[0], 0);
4602 operand_type_set (&i
.types
[3], 0);
4603 i
.reg_operands
-= 2;
4605 /* Specify the modrm encoding for memory addressing. Include
4606 the high order bit that is normally stored in the REX byte
4607 in the register field. */
4608 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4609 i
.drex
.modrm_reg
= 2;
4610 i
.drex
.modrm_regmem
= 1;
4611 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4612 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4615 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4616 else if (i
.types
[0].bitfield
.regxmm
!= 0
4617 && i
.types
[1].bitfield
.regxmm
!= 0
4618 && i
.types
[2].bitfield
.regxmm
!= 0
4619 && i
.types
[3].bitfield
.regxmm
!= 0
4620 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4621 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4623 /* clear the arguments that are stored in drex */
4624 operand_type_set (&i
.types
[2], 0);
4625 operand_type_set (&i
.types
[3], 0);
4626 i
.reg_operands
-= 2;
4628 /* There are two different ways to encode a 4 operand
4629 instruction with all registers that uses OC1 set to
4630 0 or 1. Favor setting OC1 to 0 since this mimics the
4631 actions of other SSE5 assemblers. Use modrm encoding
4632 2 for register/register. Include the high order bit that
4633 is normally stored in the REX byte in the register
4635 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4636 i
.drex
.modrm_reg
= 1;
4637 i
.drex
.modrm_regmem
= 0;
4639 /* Remember the register, including the upper bits */
4640 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4641 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4644 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4645 else if (i
.types
[0].bitfield
.regxmm
!= 0
4646 && (i
.types
[1].bitfield
.regxmm
4647 || operand_type_check (i
.types
[1], anymem
))
4648 && i
.types
[2].bitfield
.regxmm
!= 0
4649 && i
.types
[3].bitfield
.regxmm
!= 0
4650 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4651 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4653 /* Clear the arguments that are stored in drex. */
4654 operand_type_set (&i
.types
[2], 0);
4655 operand_type_set (&i
.types
[3], 0);
4656 i
.reg_operands
-= 2;
4658 /* Specify the modrm encoding and remember the register
4659 including the bits normally stored in the REX byte. */
4660 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4661 i
.drex
.modrm_reg
= 0;
4662 i
.drex
.modrm_regmem
= 1;
4663 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4664 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4667 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4668 else if (operand_type_check (i
.types
[0], anymem
) != 0
4669 && i
.types
[1].bitfield
.regxmm
!= 0
4670 && i
.types
[2].bitfield
.regxmm
!= 0
4671 && i
.types
[3].bitfield
.regxmm
!= 0
4672 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4673 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4675 /* clear the arguments that are stored in drex */
4676 operand_type_set (&i
.types
[2], 0);
4677 operand_type_set (&i
.types
[3], 0);
4678 i
.reg_operands
-= 2;
4680 /* Specify the modrm encoding and remember the register
4681 including the bits normally stored in the REX byte. */
4682 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4683 i
.drex
.modrm_reg
= 1;
4684 i
.drex
.modrm_regmem
= 0;
4685 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4686 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4690 as_bad (_("Incorrect operands for the '%s' instruction"),
4694 /* SSE5 instructions with the DREX byte where the only memory operand
4695 is in the 2nd argument, and the first and last xmm register must
4696 match, and is encoded in the DREX byte. */
4697 else if (i
.tm
.opcode_modifier
.drex
4698 && !i
.tm
.opcode_modifier
.drexv
4701 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4702 if (i
.types
[0].bitfield
.regxmm
!= 0
4703 && (i
.types
[1].bitfield
.regxmm
4704 || operand_type_check(i
.types
[1], anymem
))
4705 && i
.types
[2].bitfield
.regxmm
!= 0
4706 && i
.types
[3].bitfield
.regxmm
!= 0
4707 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4708 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4710 /* clear the arguments that are stored in drex */
4711 operand_type_set (&i
.types
[0], 0);
4712 operand_type_set (&i
.types
[3], 0);
4713 i
.reg_operands
-= 2;
4715 /* Specify the modrm encoding and remember the register
4716 including the high bit normally stored in the REX
4718 i
.drex
.modrm_reg
= 2;
4719 i
.drex
.modrm_regmem
= 1;
4720 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4721 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4725 as_bad (_("Incorrect operands for the '%s' instruction"),
4729 /* SSE5 3 operand instructions that the result is a register, being
4730 either operand can be a memory operand, using OC0 to note which
4731 one is the memory. */
4732 else if (i
.tm
.opcode_modifier
.drex
4733 && i
.tm
.opcode_modifier
.drexv
4736 i
.tm
.extension_opcode
= None
;
4738 /* Case 1: 3 operand insn, src1 = register. */
4739 if (i
.types
[0].bitfield
.regxmm
!= 0
4740 && i
.types
[1].bitfield
.regxmm
!= 0
4741 && i
.types
[2].bitfield
.regxmm
!= 0)
4743 /* Clear the arguments that are stored in drex. */
4744 operand_type_set (&i
.types
[2], 0);
4747 /* Specify the modrm encoding and remember the register
4748 including the high bit normally stored in the REX byte. */
4749 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4750 i
.drex
.modrm_reg
= 1;
4751 i
.drex
.modrm_regmem
= 0;
4752 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4753 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4756 /* Case 2: 3 operand insn, src1 = memory. */
4757 else if (operand_type_check (i
.types
[0], anymem
) != 0
4758 && i
.types
[1].bitfield
.regxmm
!= 0
4759 && i
.types
[2].bitfield
.regxmm
!= 0)
4761 /* Clear the arguments that are stored in drex. */
4762 operand_type_set (&i
.types
[2], 0);
4765 /* Specify the modrm encoding and remember the register
4766 including the high bit normally stored in the REX
4768 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4769 i
.drex
.modrm_reg
= 1;
4770 i
.drex
.modrm_regmem
= 0;
4771 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4772 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4775 /* Case 3: 3 operand insn, src2 = memory. */
4776 else if (i
.types
[0].bitfield
.regxmm
!= 0
4777 && operand_type_check (i
.types
[1], anymem
) != 0
4778 && i
.types
[2].bitfield
.regxmm
!= 0)
4780 /* Clear the arguments that are stored in drex. */
4781 operand_type_set (&i
.types
[2], 0);
4784 /* Specify the modrm encoding and remember the register
4785 including the high bit normally stored in the REX byte. */
4786 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4787 i
.drex
.modrm_reg
= 0;
4788 i
.drex
.modrm_regmem
= 1;
4789 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4790 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4794 as_bad (_("Incorrect operands for the '%s' instruction"),
4798 /* SSE5 4 operand instructions that are the comparison instructions
4799 where the first operand is the immediate value of the comparison
4801 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4803 /* Case 1: 4 operand insn, src1 = reg/memory. */
4804 if (operand_type_check (i
.types
[0], imm
) != 0
4805 && (i
.types
[1].bitfield
.regxmm
4806 || operand_type_check (i
.types
[1], anymem
))
4807 && i
.types
[2].bitfield
.regxmm
!= 0
4808 && i
.types
[3].bitfield
.regxmm
!= 0)
4810 /* clear the arguments that are stored in drex */
4811 operand_type_set (&i
.types
[3], 0);
4814 /* Specify the modrm encoding and remember the register
4815 including the high bit normally stored in the REX byte. */
4816 i
.drex
.modrm_reg
= 2;
4817 i
.drex
.modrm_regmem
= 1;
4818 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4819 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4822 /* Case 2: 3 operand insn with ImmExt that places the
4823 opcode_extension as an immediate argument. This is used for
4824 all of the varients of comparison that supplies the appropriate
4825 value as part of the instruction. */
4826 else if ((i
.types
[0].bitfield
.regxmm
4827 || operand_type_check (i
.types
[0], anymem
))
4828 && i
.types
[1].bitfield
.regxmm
!= 0
4829 && i
.types
[2].bitfield
.regxmm
!= 0
4830 && operand_type_check (i
.types
[3], imm
) != 0)
4832 /* clear the arguments that are stored in drex */
4833 operand_type_set (&i
.types
[2], 0);
4836 /* Specify the modrm encoding and remember the register
4837 including the high bit normally stored in the REX byte. */
4838 i
.drex
.modrm_reg
= 1;
4839 i
.drex
.modrm_regmem
= 0;
4840 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4841 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4845 as_bad (_("Incorrect operands for the '%s' instruction"),
4849 else if (i
.tm
.opcode_modifier
.drex
4850 || i
.tm
.opcode_modifier
.drexv
4851 || i
.tm
.opcode_modifier
.drexc
)
4852 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4856 bad_implicit_operand (int xmm
)
4858 const char *reg
= xmm
? "xmm0" : "ymm0";
4860 as_bad (_("the last operand of `%s' must be `%s%s'"),
4861 i
.tm
.name
, register_prefix
, reg
);
4863 as_bad (_("the first operand of `%s' must be `%s%s'"),
4864 i
.tm
.name
, register_prefix
, reg
);
4869 process_operands (void)
4871 /* Default segment register this instruction will use for memory
4872 accesses. 0 means unknown. This is only for optimizing out
4873 unnecessary segment overrides. */
4874 const seg_entry
*default_seg
= 0;
4876 /* Handle all of the DREX munging that SSE5 needs. */
4877 if (i
.tm
.opcode_modifier
.drex
4878 || i
.tm
.opcode_modifier
.drexv
4879 || i
.tm
.opcode_modifier
.drexc
)
4882 if (i
.tm
.opcode_modifier
.sse2avx
4883 && (i
.tm
.opcode_modifier
.vexnds
4884 || i
.tm
.opcode_modifier
.vexndd
))
4886 unsigned int dup
= i
.operands
;
4887 unsigned int dest
= dup
- 1;
4890 /* The destination must be an xmm register. */
4891 assert (i
.reg_operands
4892 && MAX_OPERANDS
> dup
4893 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4895 if (i
.tm
.opcode_modifier
.firstxmm0
)
4897 /* The first operand is implicit and must be xmm0. */
4898 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4899 if (i
.op
[0].regs
->reg_num
!= 0)
4900 return bad_implicit_operand (1);
4902 if (i
.tm
.opcode_modifier
.vex3sources
)
4904 /* Keep xmm0 for instructions with VEX prefix and 3
4910 /* We remove the first xmm0 and keep the number of
4911 operands unchanged, which in fact duplicates the
4913 for (j
= 1; j
< i
.operands
; j
++)
4915 i
.op
[j
- 1] = i
.op
[j
];
4916 i
.types
[j
- 1] = i
.types
[j
];
4917 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4921 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4923 assert ((MAX_OPERANDS
- 1) > dup
4924 && i
.tm
.opcode_modifier
.vex3sources
);
4926 /* Add the implicit xmm0 for instructions with VEX prefix
4928 for (j
= i
.operands
; j
> 0; j
--)
4930 i
.op
[j
] = i
.op
[j
- 1];
4931 i
.types
[j
] = i
.types
[j
- 1];
4932 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4935 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4936 i
.types
[0] = regxmm
;
4937 i
.tm
.operand_types
[0] = regxmm
;
4940 i
.reg_operands
+= 2;
4945 i
.op
[dup
] = i
.op
[dest
];
4946 i
.types
[dup
] = i
.types
[dest
];
4947 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4956 i
.op
[dup
] = i
.op
[dest
];
4957 i
.types
[dup
] = i
.types
[dest
];
4958 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4961 if (i
.tm
.opcode_modifier
.immext
)
4964 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4968 /* The first operand is implicit and must be xmm0/ymm0. */
4969 assert (i
.reg_operands
4970 && (operand_type_equal (&i
.types
[0], ®xmm
)
4971 || operand_type_equal (&i
.types
[0], ®ymm
)));
4972 if (i
.op
[0].regs
->reg_num
!= 0)
4973 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4975 for (j
= 1; j
< i
.operands
; j
++)
4977 i
.op
[j
- 1] = i
.op
[j
];
4978 i
.types
[j
- 1] = i
.types
[j
];
4980 /* We need to adjust fields in i.tm since they are used by
4981 build_modrm_byte. */
4982 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4989 else if (i
.tm
.opcode_modifier
.regkludge
)
4991 /* The imul $imm, %reg instruction is converted into
4992 imul $imm, %reg, %reg, and the clr %reg instruction
4993 is converted into xor %reg, %reg. */
4995 unsigned int first_reg_op
;
4997 if (operand_type_check (i
.types
[0], reg
))
5001 /* Pretend we saw the extra register operand. */
5002 assert (i
.reg_operands
== 1
5003 && i
.op
[first_reg_op
+ 1].regs
== 0);
5004 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5005 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5010 if (i
.tm
.opcode_modifier
.shortform
)
5012 if (i
.types
[0].bitfield
.sreg2
5013 || i
.types
[0].bitfield
.sreg3
)
5015 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5016 && i
.op
[0].regs
->reg_num
== 1)
5018 as_bad (_("you can't `pop %scs'"), register_prefix
);
5021 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5022 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5027 /* The register or float register operand is in operand
5031 if (i
.types
[0].bitfield
.floatreg
5032 || operand_type_check (i
.types
[0], reg
))
5036 /* Register goes in low 3 bits of opcode. */
5037 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5038 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5040 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5042 /* Warn about some common errors, but press on regardless.
5043 The first case can be generated by gcc (<= 2.8.1). */
5044 if (i
.operands
== 2)
5046 /* Reversed arguments on faddp, fsubp, etc. */
5047 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5048 register_prefix
, i
.op
[1].regs
->reg_name
,
5049 register_prefix
, i
.op
[0].regs
->reg_name
);
5053 /* Extraneous `l' suffix on fp insn. */
5054 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5055 register_prefix
, i
.op
[0].regs
->reg_name
);
5060 else if (i
.tm
.opcode_modifier
.modrm
)
5062 /* The opcode is completed (modulo i.tm.extension_opcode which
5063 must be put into the modrm byte). Now, we make the modrm and
5064 index base bytes based on all the info we've collected. */
5066 default_seg
= build_modrm_byte ();
5068 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5072 else if (i
.tm
.opcode_modifier
.isstring
)
5074 /* For the string instructions that allow a segment override
5075 on one of their operands, the default segment is ds. */
5079 if (i
.tm
.base_opcode
== 0x8d /* lea */
5082 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5084 /* If a segment was explicitly specified, and the specified segment
5085 is not the default, use an opcode prefix to select it. If we
5086 never figured out what the default segment is, then default_seg
5087 will be zero at this point, and the specified segment prefix will
5089 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5091 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5097 static const seg_entry
*
5098 build_modrm_byte (void)
5100 const seg_entry
*default_seg
= 0;
5101 unsigned int source
, dest
;
5104 /* The first operand of instructions with VEX prefix and 3 sources
5105 must be VEX_Imm4. */
5106 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5109 unsigned int nds
, reg
;
5111 if (i
.tm
.opcode_modifier
.veximmext
5112 && i
.tm
.opcode_modifier
.immext
)
5114 dest
= i
.operands
- 2;
5118 dest
= i
.operands
- 1;
5121 /* There are 2 kinds of instructions:
5122 1. 5 operands: one immediate operand and 4 register
5123 operands or 3 register operands plus 1 memory operand.
5124 It must have VexNDS and VexW0 or VexW1. The destination
5125 must be either XMM or YMM register.
5126 2. 4 operands: 4 register operands or 3 register operands
5127 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5128 if (!((i
.reg_operands
== 4
5129 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5130 && i
.tm
.opcode_modifier
.vexnds
5131 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5132 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
))
5134 && i
.imm_operands
== 1
5135 && i
.types
[0].bitfield
.vex_imm4
5136 && (i
.tm
.opcode_modifier
.vexw0
5137 || i
.tm
.opcode_modifier
.vexw1
))
5139 && (i
.imm_operands
== 0
5140 || (i
.imm_operands
== 1
5141 && i
.tm
.opcode_modifier
.immext
))
5142 && i
.tm
.opcode_modifier
.veximmext
))))
5145 if (i
.imm_operands
== 0)
5147 /* When there is no immediate operand, generate an 8bit
5148 immediate operand to encode the first operand. */
5149 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5150 i
.op
[i
.operands
].imms
= exp
;
5151 i
.types
[i
.operands
] = imm8
;
5153 /* If VexW1 is set, the first operand is the source and
5154 the second operand is encoded in the immediate operand. */
5155 if (i
.tm
.opcode_modifier
.vexw1
)
5166 /* FMA swaps REG and NDS. */
5167 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5175 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5176 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5178 exp
->X_op
= O_constant
;
5180 = ((i
.op
[reg
].regs
->reg_num
5181 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5187 if (i
.tm
.opcode_modifier
.vexw0
)
5189 /* If VexW0 is set, the third operand is the source and
5190 the second operand is encoded in the immediate
5197 /* VexW1 is set, the second operand is the source and
5198 the third operand is encoded in the immediate
5204 if (i
.tm
.opcode_modifier
.immext
)
5206 /* When ImmExt is set, the immdiate byte is the last
5208 imm
= i
.operands
- 1;
5216 /* Turn on Imm8 so that output_imm will generate it. */
5217 i
.types
[imm
].bitfield
.imm8
= 1;
5220 assert (operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
5221 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5223 i
.op
[imm
].imms
->X_add_number
5224 |= ((i
.op
[reg
].regs
->reg_num
5225 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5228 assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5229 || operand_type_equal (&i
.tm
.operand_types
[nds
], ®ymm
));
5230 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5235 /* SSE5 4 operand instructions are encoded in such a way that one of
5236 the inputs must match the destination register. Process_drex hides
5237 the 3rd argument in the drex field, so that by the time we get
5238 here, it looks to GAS as if this is a 2 operand instruction. */
5239 if ((i
.tm
.opcode_modifier
.drex
5240 || i
.tm
.opcode_modifier
.drexv
5241 || i
.tm
.opcode_modifier
.drexc
)
5242 && i
.reg_operands
== 2)
5244 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5245 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5247 i
.rm
.reg
= reg
->reg_num
;
5248 i
.rm
.regmem
= regmem
->reg_num
;
5250 if ((reg
->reg_flags
& RegRex
) != 0)
5252 if ((regmem
->reg_flags
& RegRex
) != 0)
5256 /* i.reg_operands MUST be the number of real register operands;
5257 implicit registers do not count. If there are 3 register
5258 operands, it must be a instruction with VexNDS. For a
5259 instruction with VexNDD, the destination register is encoded
5260 in VEX prefix. If there are 4 register operands, it must be
5261 a instruction with VEX prefix and 3 sources. */
5262 else if (i
.mem_operands
== 0
5263 && ((i
.reg_operands
== 2
5264 && !i
.tm
.opcode_modifier
.vexndd
)
5265 || (i
.reg_operands
== 3
5266 && i
.tm
.opcode_modifier
.vexnds
)
5267 || (i
.reg_operands
== 4 && vex_3_sources
)))
5275 /* When there are 3 operands, one of them may be immediate,
5276 which may be the first or the last operand. Otherwise,
5277 the first operand must be shift count register (cl) or it
5278 is an instruction with VexNDS. */
5279 assert (i
.imm_operands
== 1
5280 || (i
.imm_operands
== 0
5281 && (i
.tm
.opcode_modifier
.vexnds
5282 || i
.types
[0].bitfield
.shiftcount
)));
5283 if (operand_type_check (i
.types
[0], imm
)
5284 || i
.types
[0].bitfield
.shiftcount
)
5290 /* When there are 4 operands, the first two must be 8bit
5291 immediate operands. The source operand will be the 3rd
5294 For instructions with VexNDS, if the first operand
5295 an imm8, the source operand is the 2nd one. If the last
5296 operand is imm8, the source operand is the first one. */
5297 assert ((i
.imm_operands
== 2
5298 && i
.types
[0].bitfield
.imm8
5299 && i
.types
[1].bitfield
.imm8
)
5300 || (i
.tm
.opcode_modifier
.vexnds
5301 && i
.imm_operands
== 1
5302 && (i
.types
[0].bitfield
.imm8
5303 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5304 if (i
.tm
.opcode_modifier
.vexnds
)
5306 if (i
.types
[0].bitfield
.imm8
)
5324 if (i
.tm
.opcode_modifier
.vexnds
)
5326 /* For instructions with VexNDS, the register-only
5327 source operand must be XMM or YMM register. It is
5328 encoded in VEX prefix. */
5329 if ((dest
+ 1) >= i
.operands
5330 || (!operand_type_equal (&i
.tm
.operand_types
[dest
],
5332 && !operand_type_equal (&i
.tm
.operand_types
[dest
],
5335 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5341 /* One of the register operands will be encoded in the i.tm.reg
5342 field, the other in the combined i.tm.mode and i.tm.regmem
5343 fields. If no form of this instruction supports a memory
5344 destination operand, then we assume the source operand may
5345 sometimes be a memory operand and so we need to store the
5346 destination in the i.rm.reg field. */
5347 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5348 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5350 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5351 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5352 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5354 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5359 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5360 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5361 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5363 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5366 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5368 if (!i
.types
[0].bitfield
.control
5369 && !i
.types
[1].bitfield
.control
)
5371 i
.rex
&= ~(REX_R
| REX_B
);
5372 add_prefix (LOCK_PREFIX_OPCODE
);
5376 { /* If it's not 2 reg operands... */
5381 unsigned int fake_zero_displacement
= 0;
5384 /* This has been precalculated for SSE5 instructions
5385 that have a DREX field earlier in process_drex. */
5386 if (i
.tm
.opcode_modifier
.drex
5387 || i
.tm
.opcode_modifier
.drexv
5388 || i
.tm
.opcode_modifier
.drexc
)
5389 op
= i
.drex
.modrm_regmem
;
5392 for (op
= 0; op
< i
.operands
; op
++)
5393 if (operand_type_check (i
.types
[op
], anymem
))
5395 assert (op
< i
.operands
);
5400 if (i
.base_reg
== 0)
5403 if (!i
.disp_operands
)
5404 fake_zero_displacement
= 1;
5405 if (i
.index_reg
== 0)
5407 /* Operand is just <disp> */
5408 if (flag_code
== CODE_64BIT
)
5410 /* 64bit mode overwrites the 32bit absolute
5411 addressing by RIP relative addressing and
5412 absolute addressing is encoded by one of the
5413 redundant SIB forms. */
5414 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5415 i
.sib
.base
= NO_BASE_REGISTER
;
5416 i
.sib
.index
= NO_INDEX_REGISTER
;
5417 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5418 ? disp32s
: disp32
);
5420 else if ((flag_code
== CODE_16BIT
)
5421 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5423 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5424 i
.types
[op
] = disp16
;
5428 i
.rm
.regmem
= NO_BASE_REGISTER
;
5429 i
.types
[op
] = disp32
;
5432 else /* !i.base_reg && i.index_reg */
5434 if (i
.index_reg
->reg_num
== RegEiz
5435 || i
.index_reg
->reg_num
== RegRiz
)
5436 i
.sib
.index
= NO_INDEX_REGISTER
;
5438 i
.sib
.index
= i
.index_reg
->reg_num
;
5439 i
.sib
.base
= NO_BASE_REGISTER
;
5440 i
.sib
.scale
= i
.log2_scale_factor
;
5441 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5442 i
.types
[op
].bitfield
.disp8
= 0;
5443 i
.types
[op
].bitfield
.disp16
= 0;
5444 i
.types
[op
].bitfield
.disp64
= 0;
5445 if (flag_code
!= CODE_64BIT
)
5447 /* Must be 32 bit */
5448 i
.types
[op
].bitfield
.disp32
= 1;
5449 i
.types
[op
].bitfield
.disp32s
= 0;
5453 i
.types
[op
].bitfield
.disp32
= 0;
5454 i
.types
[op
].bitfield
.disp32s
= 1;
5456 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5460 /* RIP addressing for 64bit mode. */
5461 else if (i
.base_reg
->reg_num
== RegRip
||
5462 i
.base_reg
->reg_num
== RegEip
)
5464 i
.rm
.regmem
= NO_BASE_REGISTER
;
5465 i
.types
[op
].bitfield
.disp8
= 0;
5466 i
.types
[op
].bitfield
.disp16
= 0;
5467 i
.types
[op
].bitfield
.disp32
= 0;
5468 i
.types
[op
].bitfield
.disp32s
= 1;
5469 i
.types
[op
].bitfield
.disp64
= 0;
5470 i
.flags
[op
] |= Operand_PCrel
;
5471 if (! i
.disp_operands
)
5472 fake_zero_displacement
= 1;
5474 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5476 switch (i
.base_reg
->reg_num
)
5479 if (i
.index_reg
== 0)
5481 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5482 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5486 if (i
.index_reg
== 0)
5489 if (operand_type_check (i
.types
[op
], disp
) == 0)
5491 /* fake (%bp) into 0(%bp) */
5492 i
.types
[op
].bitfield
.disp8
= 1;
5493 fake_zero_displacement
= 1;
5496 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5497 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5499 default: /* (%si) -> 4 or (%di) -> 5 */
5500 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5502 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5504 else /* i.base_reg and 32/64 bit mode */
5506 if (flag_code
== CODE_64BIT
5507 && operand_type_check (i
.types
[op
], disp
))
5509 i386_operand_type temp
;
5510 operand_type_set (&temp
, 0);
5511 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5513 if (i
.prefix
[ADDR_PREFIX
] == 0)
5514 i
.types
[op
].bitfield
.disp32s
= 1;
5516 i
.types
[op
].bitfield
.disp32
= 1;
5519 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5520 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5522 i
.sib
.base
= i
.base_reg
->reg_num
;
5523 /* x86-64 ignores REX prefix bit here to avoid decoder
5525 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5528 if (i
.disp_operands
== 0)
5530 fake_zero_displacement
= 1;
5531 i
.types
[op
].bitfield
.disp8
= 1;
5534 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5538 i
.sib
.scale
= i
.log2_scale_factor
;
5539 if (i
.index_reg
== 0)
5541 /* <disp>(%esp) becomes two byte modrm with no index
5542 register. We've already stored the code for esp
5543 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5544 Any base register besides %esp will not use the
5545 extra modrm byte. */
5546 i
.sib
.index
= NO_INDEX_REGISTER
;
5550 if (i
.index_reg
->reg_num
== RegEiz
5551 || i
.index_reg
->reg_num
== RegRiz
)
5552 i
.sib
.index
= NO_INDEX_REGISTER
;
5554 i
.sib
.index
= i
.index_reg
->reg_num
;
5555 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5556 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5561 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5562 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5565 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5568 if (fake_zero_displacement
)
5570 /* Fakes a zero displacement assuming that i.types[op]
5571 holds the correct displacement size. */
5574 assert (i
.op
[op
].disps
== 0);
5575 exp
= &disp_expressions
[i
.disp_operands
++];
5576 i
.op
[op
].disps
= exp
;
5577 exp
->X_op
= O_constant
;
5578 exp
->X_add_number
= 0;
5579 exp
->X_add_symbol
= (symbolS
*) 0;
5580 exp
->X_op_symbol
= (symbolS
*) 0;
5588 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5589 (if any) based on i.tm.extension_opcode. Again, we must be
5590 careful to make sure that segment/control/debug/test/MMX
5591 registers are coded into the i.rm.reg field. */
5596 /* This has been precalculated for SSE5 instructions
5597 that have a DREX field earlier in process_drex. */
5598 if (i
.tm
.opcode_modifier
.drex
5599 || i
.tm
.opcode_modifier
.drexv
5600 || i
.tm
.opcode_modifier
.drexc
)
5602 op
= i
.drex
.modrm_reg
;
5603 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5604 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5609 unsigned int vex_reg
= ~0;
5611 for (op
= 0; op
< i
.operands
; op
++)
5612 if (i
.types
[op
].bitfield
.reg8
5613 || i
.types
[op
].bitfield
.reg16
5614 || i
.types
[op
].bitfield
.reg32
5615 || i
.types
[op
].bitfield
.reg64
5616 || i
.types
[op
].bitfield
.regmmx
5617 || i
.types
[op
].bitfield
.regxmm
5618 || i
.types
[op
].bitfield
.regymm
5619 || i
.types
[op
].bitfield
.sreg2
5620 || i
.types
[op
].bitfield
.sreg3
5621 || i
.types
[op
].bitfield
.control
5622 || i
.types
[op
].bitfield
.debug
5623 || i
.types
[op
].bitfield
.test
)
5628 else if (i
.tm
.opcode_modifier
.vexnds
)
5630 /* For instructions with VexNDS, the register-only
5631 source operand is encoded in VEX prefix. */
5632 assert (mem
!= (unsigned int) ~0);
5637 assert (op
< i
.operands
);
5642 assert (vex_reg
< i
.operands
);
5645 else if (i
.tm
.opcode_modifier
.vexndd
)
5647 /* For instructions with VexNDD, there should be
5648 no memory operand and the register destination
5649 is encoded in VEX prefix. */
5650 assert (i
.mem_operands
== 0
5651 && (op
+ 2) == i
.operands
);
5655 assert (op
< i
.operands
);
5657 if (vex_reg
!= (unsigned int) ~0)
5659 assert (i
.reg_operands
== 2);
5661 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5663 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5666 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5669 /* If there is an extension opcode to put here, the
5670 register number must be put into the regmem field. */
5671 if (i
.tm
.extension_opcode
!= None
)
5673 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5674 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5679 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5680 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5685 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5686 must set it to 3 to indicate this is a register operand
5687 in the regmem field. */
5688 if (!i
.mem_operands
)
5692 /* Fill in i.rm.reg field with extension opcode (if any). */
5693 if (i
.tm
.extension_opcode
!= None
5694 && !(i
.tm
.opcode_modifier
.drex
5695 || i
.tm
.opcode_modifier
.drexv
5696 || i
.tm
.opcode_modifier
.drexc
))
5697 i
.rm
.reg
= i
.tm
.extension_opcode
;
5703 output_branch (void)
5708 relax_substateT subtype
;
5713 if (flag_code
== CODE_16BIT
)
5717 if (i
.prefix
[DATA_PREFIX
] != 0)
5723 /* Pentium4 branch hints. */
5724 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5725 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5730 if (i
.prefix
[REX_PREFIX
] != 0)
5736 if (i
.prefixes
!= 0 && !intel_syntax
)
5737 as_warn (_("skipping prefixes on this instruction"));
5739 /* It's always a symbol; End frag & setup for relax.
5740 Make sure there is enough room in this frag for the largest
5741 instruction we may generate in md_convert_frag. This is 2
5742 bytes for the opcode and room for the prefix and largest
5744 frag_grow (prefix
+ 2 + 4);
5745 /* Prefix and 1 opcode byte go in fr_fix. */
5746 p
= frag_more (prefix
+ 1);
5747 if (i
.prefix
[DATA_PREFIX
] != 0)
5748 *p
++ = DATA_PREFIX_OPCODE
;
5749 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5750 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5751 *p
++ = i
.prefix
[SEG_PREFIX
];
5752 if (i
.prefix
[REX_PREFIX
] != 0)
5753 *p
++ = i
.prefix
[REX_PREFIX
];
5754 *p
= i
.tm
.base_opcode
;
5756 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5757 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5758 else if (cpu_arch_flags
.bitfield
.cpui386
)
5759 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5761 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5764 sym
= i
.op
[0].disps
->X_add_symbol
;
5765 off
= i
.op
[0].disps
->X_add_number
;
5767 if (i
.op
[0].disps
->X_op
!= O_constant
5768 && i
.op
[0].disps
->X_op
!= O_symbol
)
5770 /* Handle complex expressions. */
5771 sym
= make_expr_symbol (i
.op
[0].disps
);
5775 /* 1 possible extra opcode + 4 byte displacement go in var part.
5776 Pass reloc in fr_var. */
5777 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5787 if (i
.tm
.opcode_modifier
.jumpbyte
)
5789 /* This is a loop or jecxz type instruction. */
5791 if (i
.prefix
[ADDR_PREFIX
] != 0)
5793 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5796 /* Pentium4 branch hints. */
5797 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5798 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5800 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5809 if (flag_code
== CODE_16BIT
)
5812 if (i
.prefix
[DATA_PREFIX
] != 0)
5814 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5824 if (i
.prefix
[REX_PREFIX
] != 0)
5826 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5830 if (i
.prefixes
!= 0 && !intel_syntax
)
5831 as_warn (_("skipping prefixes on this instruction"));
5833 p
= frag_more (1 + size
);
5834 *p
++ = i
.tm
.base_opcode
;
5836 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5837 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5839 /* All jumps handled here are signed, but don't use a signed limit
5840 check for 32 and 16 bit jumps as we want to allow wrap around at
5841 4G and 64k respectively. */
5843 fixP
->fx_signed
= 1;
5847 output_interseg_jump (void)
5855 if (flag_code
== CODE_16BIT
)
5859 if (i
.prefix
[DATA_PREFIX
] != 0)
5865 if (i
.prefix
[REX_PREFIX
] != 0)
5875 if (i
.prefixes
!= 0 && !intel_syntax
)
5876 as_warn (_("skipping prefixes on this instruction"));
5878 /* 1 opcode; 2 segment; offset */
5879 p
= frag_more (prefix
+ 1 + 2 + size
);
5881 if (i
.prefix
[DATA_PREFIX
] != 0)
5882 *p
++ = DATA_PREFIX_OPCODE
;
5884 if (i
.prefix
[REX_PREFIX
] != 0)
5885 *p
++ = i
.prefix
[REX_PREFIX
];
5887 *p
++ = i
.tm
.base_opcode
;
5888 if (i
.op
[1].imms
->X_op
== O_constant
)
5890 offsetT n
= i
.op
[1].imms
->X_add_number
;
5893 && !fits_in_unsigned_word (n
)
5894 && !fits_in_signed_word (n
))
5896 as_bad (_("16-bit jump out of range"));
5899 md_number_to_chars (p
, n
, size
);
5902 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5903 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5904 if (i
.op
[0].imms
->X_op
!= O_constant
)
5905 as_bad (_("can't handle non absolute segment in `%s'"),
5907 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5913 fragS
*insn_start_frag
;
5914 offsetT insn_start_off
;
5916 /* Tie dwarf2 debug info to the address at the start of the insn.
5917 We can't do this after the insn has been output as the current
5918 frag may have been closed off. eg. by frag_var. */
5919 dwarf2_emit_insn (0);
5921 insn_start_frag
= frag_now
;
5922 insn_start_off
= frag_now_fix ();
5925 if (i
.tm
.opcode_modifier
.jump
)
5927 else if (i
.tm
.opcode_modifier
.jumpbyte
5928 || i
.tm
.opcode_modifier
.jumpdword
)
5930 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5931 output_interseg_jump ();
5934 /* Output normal instructions here. */
5938 unsigned int prefix
;
5940 /* Since the VEX prefix contains the implicit prefix, we don't
5941 need the explicit prefix. */
5942 if (!i
.tm
.opcode_modifier
.vex
)
5944 switch (i
.tm
.opcode_length
)
5947 if (i
.tm
.base_opcode
& 0xff000000)
5949 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5954 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5956 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5957 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5960 if (prefix
!= REPE_PREFIX_OPCODE
5961 || (i
.prefix
[LOCKREP_PREFIX
]
5962 != REPE_PREFIX_OPCODE
))
5963 add_prefix (prefix
);
5966 add_prefix (prefix
);
5975 /* The prefix bytes. */
5976 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5978 FRAG_APPEND_1_CHAR (*q
);
5981 if (i
.tm
.opcode_modifier
.vex
)
5983 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5988 /* REX byte is encoded in VEX prefix. */
5992 FRAG_APPEND_1_CHAR (*q
);
5995 /* There should be no other prefixes for instructions
6000 /* Now the VEX prefix. */
6001 p
= frag_more (i
.vex
.length
);
6002 for (j
= 0; j
< i
.vex
.length
; j
++)
6003 p
[j
] = i
.vex
.bytes
[j
];
6006 /* Now the opcode; be careful about word order here! */
6007 if (i
.tm
.opcode_length
== 1)
6009 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6013 switch (i
.tm
.opcode_length
)
6017 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6027 /* Put out high byte first: can't use md_number_to_chars! */
6028 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6029 *p
= i
.tm
.base_opcode
& 0xff;
6031 /* On SSE5, encode the OC1 bit in the DREX field if this
6032 encoding has multiple formats. */
6033 if (i
.tm
.opcode_modifier
.drex
6034 && i
.tm
.opcode_modifier
.drexv
6035 && DREX_OC1 (i
.tm
.extension_opcode
))
6036 *p
|= DREX_OC1_MASK
;
6039 /* Now the modrm byte and sib byte (if present). */
6040 if (i
.tm
.opcode_modifier
.modrm
)
6042 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6045 /* If i.rm.regmem == ESP (4)
6046 && i.rm.mode != (Register mode)
6048 ==> need second modrm byte. */
6049 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6051 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6052 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6054 | i
.sib
.scale
<< 6));
6057 /* Write the DREX byte if needed. */
6058 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6061 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6063 /* Encode the OC0 bit if this encoding has multiple
6065 if ((i
.tm
.opcode_modifier
.drex
6066 || i
.tm
.opcode_modifier
.drexv
)
6067 && DREX_OC0 (i
.tm
.extension_opcode
))
6068 *p
|= DREX_OC0_MASK
;
6071 if (i
.disp_operands
)
6072 output_disp (insn_start_frag
, insn_start_off
);
6075 output_imm (insn_start_frag
, insn_start_off
);
6081 pi ("" /*line*/, &i
);
6083 #endif /* DEBUG386 */
6086 /* Return the size of the displacement operand N. */
6089 disp_size (unsigned int n
)
6092 if (i
.types
[n
].bitfield
.disp64
)
6094 else if (i
.types
[n
].bitfield
.disp8
)
6096 else if (i
.types
[n
].bitfield
.disp16
)
6101 /* Return the size of the immediate operand N. */
6104 imm_size (unsigned int n
)
6107 if (i
.types
[n
].bitfield
.imm64
)
6109 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6111 else if (i
.types
[n
].bitfield
.imm16
)
6117 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6122 for (n
= 0; n
< i
.operands
; n
++)
6124 if (operand_type_check (i
.types
[n
], disp
))
6126 if (i
.op
[n
].disps
->X_op
== O_constant
)
6128 int size
= disp_size (n
);
6131 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6133 p
= frag_more (size
);
6134 md_number_to_chars (p
, val
, size
);
6138 enum bfd_reloc_code_real reloc_type
;
6139 int size
= disp_size (n
);
6140 int sign
= i
.types
[n
].bitfield
.disp32s
;
6141 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6143 /* We can't have 8 bit displacement here. */
6144 assert (!i
.types
[n
].bitfield
.disp8
);
6146 /* The PC relative address is computed relative
6147 to the instruction boundary, so in case immediate
6148 fields follows, we need to adjust the value. */
6149 if (pcrel
&& i
.imm_operands
)
6154 for (n1
= 0; n1
< i
.operands
; n1
++)
6155 if (operand_type_check (i
.types
[n1
], imm
))
6157 /* Only one immediate is allowed for PC
6158 relative address. */
6161 i
.op
[n
].disps
->X_add_number
-= sz
;
6163 /* We should find the immediate. */
6167 p
= frag_more (size
);
6168 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6170 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6171 && (((reloc_type
== BFD_RELOC_32
6172 || reloc_type
== BFD_RELOC_X86_64_32S
6173 || (reloc_type
== BFD_RELOC_64
6175 && (i
.op
[n
].disps
->X_op
== O_symbol
6176 || (i
.op
[n
].disps
->X_op
== O_add
6177 && ((symbol_get_value_expression
6178 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6180 || reloc_type
== BFD_RELOC_32_PCREL
))
6184 if (insn_start_frag
== frag_now
)
6185 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6190 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6191 for (fr
= insn_start_frag
->fr_next
;
6192 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6194 add
+= p
- frag_now
->fr_literal
;
6199 reloc_type
= BFD_RELOC_386_GOTPC
;
6200 i
.op
[n
].imms
->X_add_number
+= add
;
6202 else if (reloc_type
== BFD_RELOC_64
)
6203 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6205 /* Don't do the adjustment for x86-64, as there
6206 the pcrel addressing is relative to the _next_
6207 insn, and that is taken care of in other code. */
6208 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6210 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6211 i
.op
[n
].disps
, pcrel
, reloc_type
);
6218 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6223 for (n
= 0; n
< i
.operands
; n
++)
6225 if (operand_type_check (i
.types
[n
], imm
))
6227 if (i
.op
[n
].imms
->X_op
== O_constant
)
6229 int size
= imm_size (n
);
6232 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6234 p
= frag_more (size
);
6235 md_number_to_chars (p
, val
, size
);
6239 /* Not absolute_section.
6240 Need a 32-bit fixup (don't support 8bit
6241 non-absolute imms). Try to support other
6243 enum bfd_reloc_code_real reloc_type
;
6244 int size
= imm_size (n
);
6247 if (i
.types
[n
].bitfield
.imm32s
6248 && (i
.suffix
== QWORD_MNEM_SUFFIX
6249 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6254 p
= frag_more (size
);
6255 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6257 /* This is tough to explain. We end up with this one if we
6258 * have operands that look like
6259 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6260 * obtain the absolute address of the GOT, and it is strongly
6261 * preferable from a performance point of view to avoid using
6262 * a runtime relocation for this. The actual sequence of
6263 * instructions often look something like:
6268 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6270 * The call and pop essentially return the absolute address
6271 * of the label .L66 and store it in %ebx. The linker itself
6272 * will ultimately change the first operand of the addl so
6273 * that %ebx points to the GOT, but to keep things simple, the
6274 * .o file must have this operand set so that it generates not
6275 * the absolute address of .L66, but the absolute address of
6276 * itself. This allows the linker itself simply treat a GOTPC
6277 * relocation as asking for a pcrel offset to the GOT to be
6278 * added in, and the addend of the relocation is stored in the
6279 * operand field for the instruction itself.
6281 * Our job here is to fix the operand so that it would add
6282 * the correct offset so that %ebx would point to itself. The
6283 * thing that is tricky is that .-.L66 will point to the
6284 * beginning of the instruction, so we need to further modify
6285 * the operand so that it will point to itself. There are
6286 * other cases where you have something like:
6288 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6290 * and here no correction would be required. Internally in
6291 * the assembler we treat operands of this form as not being
6292 * pcrel since the '.' is explicitly mentioned, and I wonder
6293 * whether it would simplify matters to do it this way. Who
6294 * knows. In earlier versions of the PIC patches, the
6295 * pcrel_adjust field was used to store the correction, but
6296 * since the expression is not pcrel, I felt it would be
6297 * confusing to do it this way. */
6299 if ((reloc_type
== BFD_RELOC_32
6300 || reloc_type
== BFD_RELOC_X86_64_32S
6301 || reloc_type
== BFD_RELOC_64
)
6303 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6304 && (i
.op
[n
].imms
->X_op
== O_symbol
6305 || (i
.op
[n
].imms
->X_op
== O_add
6306 && ((symbol_get_value_expression
6307 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6312 if (insn_start_frag
== frag_now
)
6313 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6318 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6319 for (fr
= insn_start_frag
->fr_next
;
6320 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6322 add
+= p
- frag_now
->fr_literal
;
6326 reloc_type
= BFD_RELOC_386_GOTPC
;
6328 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6330 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6331 i
.op
[n
].imms
->X_add_number
+= add
;
6333 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6334 i
.op
[n
].imms
, 0, reloc_type
);
6340 /* x86_cons_fix_new is called via the expression parsing code when a
6341 reloc is needed. We use this hook to get the correct .got reloc. */
6342 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6343 static int cons_sign
= -1;
6346 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6349 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6351 got_reloc
= NO_RELOC
;
6354 if (exp
->X_op
== O_secrel
)
6356 exp
->X_op
= O_symbol
;
6357 r
= BFD_RELOC_32_SECREL
;
6361 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6364 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6365 # define lex_got(reloc, adjust, types) NULL
6367 /* Parse operands of the form
6368 <symbol>@GOTOFF+<nnn>
6369 and similar .plt or .got references.
6371 If we find one, set up the correct relocation in RELOC and copy the
6372 input string, minus the `@GOTOFF' into a malloc'd buffer for
6373 parsing by the calling routine. Return this buffer, and if ADJUST
6374 is non-null set it to the length of the string we removed from the
6375 input line. Otherwise return NULL. */
6377 lex_got (enum bfd_reloc_code_real
*reloc
,
6379 i386_operand_type
*types
)
6381 /* Some of the relocations depend on the size of what field is to
6382 be relocated. But in our callers i386_immediate and i386_displacement
6383 we don't yet know the operand size (this will be set by insn
6384 matching). Hence we record the word32 relocation here,
6385 and adjust the reloc according to the real size in reloc(). */
6386 static const struct {
6388 const enum bfd_reloc_code_real rel
[2];
6389 const i386_operand_type types64
;
6392 BFD_RELOC_X86_64_PLTOFF64
},
6393 OPERAND_TYPE_IMM64
},
6394 { "PLT", { BFD_RELOC_386_PLT32
,
6395 BFD_RELOC_X86_64_PLT32
},
6396 OPERAND_TYPE_IMM32_32S_DISP32
},
6398 BFD_RELOC_X86_64_GOTPLT64
},
6399 OPERAND_TYPE_IMM64_DISP64
},
6400 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6401 BFD_RELOC_X86_64_GOTOFF64
},
6402 OPERAND_TYPE_IMM64_DISP64
},
6404 BFD_RELOC_X86_64_GOTPCREL
},
6405 OPERAND_TYPE_IMM32_32S_DISP32
},
6406 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6407 BFD_RELOC_X86_64_TLSGD
},
6408 OPERAND_TYPE_IMM32_32S_DISP32
},
6409 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6411 OPERAND_TYPE_NONE
},
6413 BFD_RELOC_X86_64_TLSLD
},
6414 OPERAND_TYPE_IMM32_32S_DISP32
},
6415 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6416 BFD_RELOC_X86_64_GOTTPOFF
},
6417 OPERAND_TYPE_IMM32_32S_DISP32
},
6418 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6419 BFD_RELOC_X86_64_TPOFF32
},
6420 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6421 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6423 OPERAND_TYPE_NONE
},
6424 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6425 BFD_RELOC_X86_64_DTPOFF32
},
6427 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6428 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6430 OPERAND_TYPE_NONE
},
6431 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6433 OPERAND_TYPE_NONE
},
6434 { "GOT", { BFD_RELOC_386_GOT32
,
6435 BFD_RELOC_X86_64_GOT32
},
6436 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6437 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6438 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6439 OPERAND_TYPE_IMM32_32S_DISP32
},
6440 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6441 BFD_RELOC_X86_64_TLSDESC_CALL
},
6442 OPERAND_TYPE_IMM32_32S_DISP32
},
6450 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6451 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6454 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6458 len
= strlen (gotrel
[j
].str
);
6459 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6461 if (gotrel
[j
].rel
[object_64bit
] != 0)
6464 char *tmpbuf
, *past_reloc
;
6466 *reloc
= gotrel
[j
].rel
[object_64bit
];
6472 if (flag_code
!= CODE_64BIT
)
6474 types
->bitfield
.imm32
= 1;
6475 types
->bitfield
.disp32
= 1;
6478 *types
= gotrel
[j
].types64
;
6481 if (GOT_symbol
== NULL
)
6482 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6484 /* The length of the first part of our input line. */
6485 first
= cp
- input_line_pointer
;
6487 /* The second part goes from after the reloc token until
6488 (and including) an end_of_line char or comma. */
6489 past_reloc
= cp
+ 1 + len
;
6491 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6493 second
= cp
+ 1 - past_reloc
;
6495 /* Allocate and copy string. The trailing NUL shouldn't
6496 be necessary, but be safe. */
6497 tmpbuf
= xmalloc (first
+ second
+ 2);
6498 memcpy (tmpbuf
, input_line_pointer
, first
);
6499 if (second
!= 0 && *past_reloc
!= ' ')
6500 /* Replace the relocation token with ' ', so that
6501 errors like foo@GOTOFF1 will be detected. */
6502 tmpbuf
[first
++] = ' ';
6503 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6504 tmpbuf
[first
+ second
] = '\0';
6508 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6509 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6514 /* Might be a symbol version string. Don't as_bad here. */
6519 x86_cons (expressionS
*exp
, int size
)
6521 if (size
== 4 || (object_64bit
&& size
== 8))
6523 /* Handle @GOTOFF and the like in an expression. */
6525 char *gotfree_input_line
;
6528 save
= input_line_pointer
;
6529 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6530 if (gotfree_input_line
)
6531 input_line_pointer
= gotfree_input_line
;
6535 if (gotfree_input_line
)
6537 /* expression () has merrily parsed up to the end of line,
6538 or a comma - in the wrong buffer. Transfer how far
6539 input_line_pointer has moved to the right buffer. */
6540 input_line_pointer
= (save
6541 + (input_line_pointer
- gotfree_input_line
)
6543 free (gotfree_input_line
);
6544 if (exp
->X_op
== O_constant
6545 || exp
->X_op
== O_absent
6546 || exp
->X_op
== O_illegal
6547 || exp
->X_op
== O_register
6548 || exp
->X_op
== O_big
)
6550 char c
= *input_line_pointer
;
6551 *input_line_pointer
= 0;
6552 as_bad (_("missing or invalid expression `%s'"), save
);
6553 *input_line_pointer
= c
;
6562 static void signed_cons (int size
)
6564 if (flag_code
== CODE_64BIT
)
6572 pe_directive_secrel (dummy
)
6573 int dummy ATTRIBUTE_UNUSED
;
6580 if (exp
.X_op
== O_symbol
)
6581 exp
.X_op
= O_secrel
;
6583 emit_expr (&exp
, 4);
6585 while (*input_line_pointer
++ == ',');
6587 input_line_pointer
--;
6588 demand_empty_rest_of_line ();
6593 i386_immediate (char *imm_start
)
6595 char *save_input_line_pointer
;
6596 char *gotfree_input_line
;
6599 i386_operand_type types
;
6601 operand_type_set (&types
, ~0);
6603 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6605 as_bad (_("at most %d immediate operands are allowed"),
6606 MAX_IMMEDIATE_OPERANDS
);
6610 exp
= &im_expressions
[i
.imm_operands
++];
6611 i
.op
[this_operand
].imms
= exp
;
6613 if (is_space_char (*imm_start
))
6616 save_input_line_pointer
= input_line_pointer
;
6617 input_line_pointer
= imm_start
;
6619 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6620 if (gotfree_input_line
)
6621 input_line_pointer
= gotfree_input_line
;
6623 exp_seg
= expression (exp
);
6626 if (*input_line_pointer
)
6627 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6629 input_line_pointer
= save_input_line_pointer
;
6630 if (gotfree_input_line
)
6631 free (gotfree_input_line
);
6633 if (exp
->X_op
== O_absent
6634 || exp
->X_op
== O_illegal
6635 || exp
->X_op
== O_big
6636 || (gotfree_input_line
6637 && (exp
->X_op
== O_constant
6638 || exp
->X_op
== O_register
)))
6640 as_bad (_("missing or invalid immediate expression `%s'"),
6644 else if (exp
->X_op
== O_constant
)
6646 /* Size it properly later. */
6647 i
.types
[this_operand
].bitfield
.imm64
= 1;
6648 /* If BFD64, sign extend val. */
6649 if (!use_rela_relocations
6650 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6652 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6654 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6655 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6656 && exp_seg
!= absolute_section
6657 && exp_seg
!= text_section
6658 && exp_seg
!= data_section
6659 && exp_seg
!= bss_section
6660 && exp_seg
!= undefined_section
6661 && !bfd_is_com_section (exp_seg
))
6663 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6667 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6669 as_bad (_("illegal immediate register operand %s"), imm_start
);
6674 /* This is an address. The size of the address will be
6675 determined later, depending on destination register,
6676 suffix, or the default for the section. */
6677 i
.types
[this_operand
].bitfield
.imm8
= 1;
6678 i
.types
[this_operand
].bitfield
.imm16
= 1;
6679 i
.types
[this_operand
].bitfield
.imm32
= 1;
6680 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6681 i
.types
[this_operand
].bitfield
.imm64
= 1;
6682 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6690 i386_scale (char *scale
)
6693 char *save
= input_line_pointer
;
6695 input_line_pointer
= scale
;
6696 val
= get_absolute_expression ();
6701 i
.log2_scale_factor
= 0;
6704 i
.log2_scale_factor
= 1;
6707 i
.log2_scale_factor
= 2;
6710 i
.log2_scale_factor
= 3;
6714 char sep
= *input_line_pointer
;
6716 *input_line_pointer
= '\0';
6717 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6719 *input_line_pointer
= sep
;
6720 input_line_pointer
= save
;
6724 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6726 as_warn (_("scale factor of %d without an index register"),
6727 1 << i
.log2_scale_factor
);
6728 i
.log2_scale_factor
= 0;
6730 scale
= input_line_pointer
;
6731 input_line_pointer
= save
;
6736 i386_displacement (char *disp_start
, char *disp_end
)
6740 char *save_input_line_pointer
;
6741 char *gotfree_input_line
;
6743 i386_operand_type bigdisp
, types
= anydisp
;
6746 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6748 as_bad (_("at most %d displacement operands are allowed"),
6749 MAX_MEMORY_OPERANDS
);
6753 operand_type_set (&bigdisp
, 0);
6754 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6755 || (!current_templates
->start
->opcode_modifier
.jump
6756 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6758 bigdisp
.bitfield
.disp32
= 1;
6759 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6760 if (flag_code
== CODE_64BIT
)
6764 bigdisp
.bitfield
.disp32s
= 1;
6765 bigdisp
.bitfield
.disp64
= 1;
6768 else if ((flag_code
== CODE_16BIT
) ^ override
)
6770 bigdisp
.bitfield
.disp32
= 0;
6771 bigdisp
.bitfield
.disp16
= 1;
6776 /* For PC-relative branches, the width of the displacement
6777 is dependent upon data size, not address size. */
6778 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6779 if (flag_code
== CODE_64BIT
)
6781 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6782 bigdisp
.bitfield
.disp16
= 1;
6785 bigdisp
.bitfield
.disp32
= 1;
6786 bigdisp
.bitfield
.disp32s
= 1;
6792 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6794 : LONG_MNEM_SUFFIX
));
6795 bigdisp
.bitfield
.disp32
= 1;
6796 if ((flag_code
== CODE_16BIT
) ^ override
)
6798 bigdisp
.bitfield
.disp32
= 0;
6799 bigdisp
.bitfield
.disp16
= 1;
6803 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6806 exp
= &disp_expressions
[i
.disp_operands
];
6807 i
.op
[this_operand
].disps
= exp
;
6809 save_input_line_pointer
= input_line_pointer
;
6810 input_line_pointer
= disp_start
;
6811 END_STRING_AND_SAVE (disp_end
);
6813 #ifndef GCC_ASM_O_HACK
6814 #define GCC_ASM_O_HACK 0
6817 END_STRING_AND_SAVE (disp_end
+ 1);
6818 if (i
.types
[this_operand
].bitfield
.baseIndex
6819 && displacement_string_end
[-1] == '+')
6821 /* This hack is to avoid a warning when using the "o"
6822 constraint within gcc asm statements.
6825 #define _set_tssldt_desc(n,addr,limit,type) \
6826 __asm__ __volatile__ ( \
6828 "movw %w1,2+%0\n\t" \
6830 "movb %b1,4+%0\n\t" \
6831 "movb %4,5+%0\n\t" \
6832 "movb $0,6+%0\n\t" \
6833 "movb %h1,7+%0\n\t" \
6835 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6837 This works great except that the output assembler ends
6838 up looking a bit weird if it turns out that there is
6839 no offset. You end up producing code that looks like:
6852 So here we provide the missing zero. */
6854 *displacement_string_end
= '0';
6857 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6858 if (gotfree_input_line
)
6859 input_line_pointer
= gotfree_input_line
;
6861 exp_seg
= expression (exp
);
6864 if (*input_line_pointer
)
6865 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6867 RESTORE_END_STRING (disp_end
+ 1);
6869 input_line_pointer
= save_input_line_pointer
;
6870 if (gotfree_input_line
)
6871 free (gotfree_input_line
);
6874 /* We do this to make sure that the section symbol is in
6875 the symbol table. We will ultimately change the relocation
6876 to be relative to the beginning of the section. */
6877 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6878 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6879 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6881 if (exp
->X_op
!= O_symbol
)
6884 if (S_IS_LOCAL (exp
->X_add_symbol
)
6885 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6886 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6887 exp
->X_op
= O_subtract
;
6888 exp
->X_op_symbol
= GOT_symbol
;
6889 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6890 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6891 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6892 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6894 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6897 else if (exp
->X_op
== O_absent
6898 || exp
->X_op
== O_illegal
6899 || exp
->X_op
== O_big
6900 || (gotfree_input_line
6901 && (exp
->X_op
== O_constant
6902 || exp
->X_op
== O_register
)))
6905 as_bad (_("missing or invalid displacement expression `%s'"),
6910 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6911 else if (exp
->X_op
!= O_constant
6912 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6913 && exp_seg
!= absolute_section
6914 && exp_seg
!= text_section
6915 && exp_seg
!= data_section
6916 && exp_seg
!= bss_section
6917 && exp_seg
!= undefined_section
6918 && !bfd_is_com_section (exp_seg
))
6920 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6925 RESTORE_END_STRING (disp_end
);
6927 /* Check if this is a displacement only operand. */
6928 bigdisp
= i
.types
[this_operand
];
6929 bigdisp
.bitfield
.disp8
= 0;
6930 bigdisp
.bitfield
.disp16
= 0;
6931 bigdisp
.bitfield
.disp32
= 0;
6932 bigdisp
.bitfield
.disp32s
= 0;
6933 bigdisp
.bitfield
.disp64
= 0;
6934 if (operand_type_all_zero (&bigdisp
))
6935 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6941 /* Make sure the memory operand we've been dealt is valid.
6942 Return 1 on success, 0 on a failure. */
6945 i386_index_check (const char *operand_string
)
6948 const char *kind
= "base/index";
6949 #if INFER_ADDR_PREFIX
6955 if (current_templates
->start
->opcode_modifier
.isstring
6956 && !current_templates
->start
->opcode_modifier
.immext
6957 && (current_templates
->end
[-1].opcode_modifier
.isstring
6960 /* Memory operands of string insns are special in that they only allow
6961 a single register (rDI, rSI, or rBX) as their memory address. */
6962 unsigned int expected
;
6964 kind
= "string address";
6966 if (current_templates
->start
->opcode_modifier
.w
)
6968 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6970 if (!type
.bitfield
.baseindex
6971 || ((!i
.mem_operands
!= !intel_syntax
)
6972 && current_templates
->end
[-1].operand_types
[1]
6973 .bitfield
.baseindex
))
6974 type
= current_templates
->end
[-1].operand_types
[1];
6975 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6978 expected
= 3 /* rBX */;
6980 if (!i
.base_reg
|| i
.index_reg
6981 || operand_type_check (i
.types
[this_operand
], disp
))
6983 else if (!(flag_code
== CODE_64BIT
6984 ? i
.prefix
[ADDR_PREFIX
]
6985 ? i
.base_reg
->reg_type
.bitfield
.reg32
6986 : i
.base_reg
->reg_type
.bitfield
.reg64
6987 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6988 ? i
.base_reg
->reg_type
.bitfield
.reg32
6989 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6991 else if (i
.base_reg
->reg_num
!= expected
)
6998 for (j
= 0; j
< i386_regtab_size
; ++j
)
6999 if ((flag_code
== CODE_64BIT
7000 ? i
.prefix
[ADDR_PREFIX
]
7001 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7002 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7003 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7004 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7005 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7006 && i386_regtab
[j
].reg_num
== expected
)
7008 assert (j
< i386_regtab_size
);
7009 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7011 intel_syntax
? '[' : '(',
7013 i386_regtab
[j
].reg_name
,
7014 intel_syntax
? ']' : ')');
7018 else if (flag_code
== CODE_64BIT
)
7021 && ((i
.prefix
[ADDR_PREFIX
] == 0
7022 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7023 || (i
.prefix
[ADDR_PREFIX
]
7024 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7026 || i
.base_reg
->reg_num
!=
7027 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7029 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7030 || (i
.prefix
[ADDR_PREFIX
] == 0
7031 && i
.index_reg
->reg_num
!= RegRiz
7032 && !i
.index_reg
->reg_type
.bitfield
.reg64
7034 || (i
.prefix
[ADDR_PREFIX
]
7035 && i
.index_reg
->reg_num
!= RegEiz
7036 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7041 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7045 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7046 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7048 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7049 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7051 && i
.base_reg
->reg_num
< 6
7052 && i
.index_reg
->reg_num
>= 6
7053 && i
.log2_scale_factor
== 0))))
7060 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7062 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7063 && i
.index_reg
->reg_num
!= RegEiz
)
7064 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7070 #if INFER_ADDR_PREFIX
7071 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7073 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7075 /* Change the size of any displacement too. At most one of
7076 Disp16 or Disp32 is set.
7077 FIXME. There doesn't seem to be any real need for separate
7078 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7079 Removing them would probably clean up the code quite a lot. */
7080 if (flag_code
!= CODE_64BIT
7081 && (i
.types
[this_operand
].bitfield
.disp16
7082 || i
.types
[this_operand
].bitfield
.disp32
))
7083 i
.types
[this_operand
]
7084 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7089 as_bad (_("`%s' is not a valid %s expression"),
7094 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7096 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7097 ? flag_code
== CODE_32BIT
7106 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7110 i386_att_operand (char *operand_string
)
7114 char *op_string
= operand_string
;
7116 if (is_space_char (*op_string
))
7119 /* We check for an absolute prefix (differentiating,
7120 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7121 if (*op_string
== ABSOLUTE_PREFIX
)
7124 if (is_space_char (*op_string
))
7126 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7129 /* Check if operand is a register. */
7130 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7132 i386_operand_type temp
;
7134 /* Check for a segment override by searching for ':' after a
7135 segment register. */
7137 if (is_space_char (*op_string
))
7139 if (*op_string
== ':'
7140 && (r
->reg_type
.bitfield
.sreg2
7141 || r
->reg_type
.bitfield
.sreg3
))
7146 i
.seg
[i
.mem_operands
] = &es
;
7149 i
.seg
[i
.mem_operands
] = &cs
;
7152 i
.seg
[i
.mem_operands
] = &ss
;
7155 i
.seg
[i
.mem_operands
] = &ds
;
7158 i
.seg
[i
.mem_operands
] = &fs
;
7161 i
.seg
[i
.mem_operands
] = &gs
;
7165 /* Skip the ':' and whitespace. */
7167 if (is_space_char (*op_string
))
7170 if (!is_digit_char (*op_string
)
7171 && !is_identifier_char (*op_string
)
7172 && *op_string
!= '('
7173 && *op_string
!= ABSOLUTE_PREFIX
)
7175 as_bad (_("bad memory operand `%s'"), op_string
);
7178 /* Handle case of %es:*foo. */
7179 if (*op_string
== ABSOLUTE_PREFIX
)
7182 if (is_space_char (*op_string
))
7184 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7186 goto do_memory_reference
;
7190 as_bad (_("junk `%s' after register"), op_string
);
7194 temp
.bitfield
.baseindex
= 0;
7195 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7197 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7198 i
.op
[this_operand
].regs
= r
;
7201 else if (*op_string
== REGISTER_PREFIX
)
7203 as_bad (_("bad register name `%s'"), op_string
);
7206 else if (*op_string
== IMMEDIATE_PREFIX
)
7209 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7211 as_bad (_("immediate operand illegal with absolute jump"));
7214 if (!i386_immediate (op_string
))
7217 else if (is_digit_char (*op_string
)
7218 || is_identifier_char (*op_string
)
7219 || *op_string
== '(')
7221 /* This is a memory reference of some sort. */
7224 /* Start and end of displacement string expression (if found). */
7225 char *displacement_string_start
;
7226 char *displacement_string_end
;
7228 do_memory_reference
:
7229 if ((i
.mem_operands
== 1
7230 && !current_templates
->start
->opcode_modifier
.isstring
)
7231 || i
.mem_operands
== 2)
7233 as_bad (_("too many memory references for `%s'"),
7234 current_templates
->start
->name
);
7238 /* Check for base index form. We detect the base index form by
7239 looking for an ')' at the end of the operand, searching
7240 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7242 base_string
= op_string
+ strlen (op_string
);
7245 if (is_space_char (*base_string
))
7248 /* If we only have a displacement, set-up for it to be parsed later. */
7249 displacement_string_start
= op_string
;
7250 displacement_string_end
= base_string
+ 1;
7252 if (*base_string
== ')')
7255 unsigned int parens_balanced
= 1;
7256 /* We've already checked that the number of left & right ()'s are
7257 equal, so this loop will not be infinite. */
7261 if (*base_string
== ')')
7263 if (*base_string
== '(')
7266 while (parens_balanced
);
7268 temp_string
= base_string
;
7270 /* Skip past '(' and whitespace. */
7272 if (is_space_char (*base_string
))
7275 if (*base_string
== ','
7276 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7279 displacement_string_end
= temp_string
;
7281 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7285 base_string
= end_op
;
7286 if (is_space_char (*base_string
))
7290 /* There may be an index reg or scale factor here. */
7291 if (*base_string
== ',')
7294 if (is_space_char (*base_string
))
7297 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7300 base_string
= end_op
;
7301 if (is_space_char (*base_string
))
7303 if (*base_string
== ',')
7306 if (is_space_char (*base_string
))
7309 else if (*base_string
!= ')')
7311 as_bad (_("expecting `,' or `)' "
7312 "after index register in `%s'"),
7317 else if (*base_string
== REGISTER_PREFIX
)
7319 as_bad (_("bad register name `%s'"), base_string
);
7323 /* Check for scale factor. */
7324 if (*base_string
!= ')')
7326 char *end_scale
= i386_scale (base_string
);
7331 base_string
= end_scale
;
7332 if (is_space_char (*base_string
))
7334 if (*base_string
!= ')')
7336 as_bad (_("expecting `)' "
7337 "after scale factor in `%s'"),
7342 else if (!i
.index_reg
)
7344 as_bad (_("expecting index register or scale factor "
7345 "after `,'; got '%c'"),
7350 else if (*base_string
!= ')')
7352 as_bad (_("expecting `,' or `)' "
7353 "after base register in `%s'"),
7358 else if (*base_string
== REGISTER_PREFIX
)
7360 as_bad (_("bad register name `%s'"), base_string
);
7365 /* If there's an expression beginning the operand, parse it,
7366 assuming displacement_string_start and
7367 displacement_string_end are meaningful. */
7368 if (displacement_string_start
!= displacement_string_end
)
7370 if (!i386_displacement (displacement_string_start
,
7371 displacement_string_end
))
7375 /* Special case for (%dx) while doing input/output op. */
7377 && operand_type_equal (&i
.base_reg
->reg_type
,
7378 ®16_inoutportreg
)
7380 && i
.log2_scale_factor
== 0
7381 && i
.seg
[i
.mem_operands
] == 0
7382 && !operand_type_check (i
.types
[this_operand
], disp
))
7384 i
.types
[this_operand
] = inoutportreg
;
7388 if (i386_index_check (operand_string
) == 0)
7390 i
.types
[this_operand
].bitfield
.mem
= 1;
7395 /* It's not a memory operand; argh! */
7396 as_bad (_("invalid char %s beginning operand %d `%s'"),
7397 output_invalid (*op_string
),
7402 return 1; /* Normal return. */
7405 /* md_estimate_size_before_relax()
7407 Called just before relax() for rs_machine_dependent frags. The x86
7408 assembler uses these frags to handle variable size jump
7411 Any symbol that is now undefined will not become defined.
7412 Return the correct fr_subtype in the frag.
7413 Return the initial "guess for variable size of frag" to caller.
7414 The guess is actually the growth beyond the fixed part. Whatever
7415 we do to grow the fixed or variable part contributes to our
7419 md_estimate_size_before_relax (fragP
, segment
)
7423 /* We've already got fragP->fr_subtype right; all we have to do is
7424 check for un-relaxable symbols. On an ELF system, we can't relax
7425 an externally visible symbol, because it may be overridden by a
7427 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7428 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7430 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7431 || S_IS_WEAK (fragP
->fr_symbol
)))
7435 /* Symbol is undefined in this segment, or we need to keep a
7436 reloc so that weak symbols can be overridden. */
7437 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7438 enum bfd_reloc_code_real reloc_type
;
7439 unsigned char *opcode
;
7442 if (fragP
->fr_var
!= NO_RELOC
)
7443 reloc_type
= fragP
->fr_var
;
7445 reloc_type
= BFD_RELOC_16_PCREL
;
7447 reloc_type
= BFD_RELOC_32_PCREL
;
7449 old_fr_fix
= fragP
->fr_fix
;
7450 opcode
= (unsigned char *) fragP
->fr_opcode
;
7452 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7455 /* Make jmp (0xeb) a (d)word displacement jump. */
7457 fragP
->fr_fix
+= size
;
7458 fix_new (fragP
, old_fr_fix
, size
,
7460 fragP
->fr_offset
, 1,
7466 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7468 /* Negate the condition, and branch past an
7469 unconditional jump. */
7472 /* Insert an unconditional jump. */
7474 /* We added two extra opcode bytes, and have a two byte
7476 fragP
->fr_fix
+= 2 + 2;
7477 fix_new (fragP
, old_fr_fix
+ 2, 2,
7479 fragP
->fr_offset
, 1,
7486 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7491 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7493 fragP
->fr_offset
, 1,
7495 fixP
->fx_signed
= 1;
7499 /* This changes the byte-displacement jump 0x7N
7500 to the (d)word-displacement jump 0x0f,0x8N. */
7501 opcode
[1] = opcode
[0] + 0x10;
7502 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7503 /* We've added an opcode byte. */
7504 fragP
->fr_fix
+= 1 + size
;
7505 fix_new (fragP
, old_fr_fix
+ 1, size
,
7507 fragP
->fr_offset
, 1,
7512 BAD_CASE (fragP
->fr_subtype
);
7516 return fragP
->fr_fix
- old_fr_fix
;
7519 /* Guess size depending on current relax state. Initially the relax
7520 state will correspond to a short jump and we return 1, because
7521 the variable part of the frag (the branch offset) is one byte
7522 long. However, we can relax a section more than once and in that
7523 case we must either set fr_subtype back to the unrelaxed state,
7524 or return the value for the appropriate branch. */
7525 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7528 /* Called after relax() is finished.
7530 In: Address of frag.
7531 fr_type == rs_machine_dependent.
7532 fr_subtype is what the address relaxed to.
7534 Out: Any fixSs and constants are set up.
7535 Caller will turn frag into a ".space 0". */
7538 md_convert_frag (abfd
, sec
, fragP
)
7539 bfd
*abfd ATTRIBUTE_UNUSED
;
7540 segT sec ATTRIBUTE_UNUSED
;
7543 unsigned char *opcode
;
7544 unsigned char *where_to_put_displacement
= NULL
;
7545 offsetT target_address
;
7546 offsetT opcode_address
;
7547 unsigned int extension
= 0;
7548 offsetT displacement_from_opcode_start
;
7550 opcode
= (unsigned char *) fragP
->fr_opcode
;
7552 /* Address we want to reach in file space. */
7553 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7555 /* Address opcode resides at in file space. */
7556 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7558 /* Displacement from opcode start to fill into instruction. */
7559 displacement_from_opcode_start
= target_address
- opcode_address
;
7561 if ((fragP
->fr_subtype
& BIG
) == 0)
7563 /* Don't have to change opcode. */
7564 extension
= 1; /* 1 opcode + 1 displacement */
7565 where_to_put_displacement
= &opcode
[1];
7569 if (no_cond_jump_promotion
7570 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7571 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7572 _("long jump required"));
7574 switch (fragP
->fr_subtype
)
7576 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7577 extension
= 4; /* 1 opcode + 4 displacement */
7579 where_to_put_displacement
= &opcode
[1];
7582 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7583 extension
= 2; /* 1 opcode + 2 displacement */
7585 where_to_put_displacement
= &opcode
[1];
7588 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7589 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7590 extension
= 5; /* 2 opcode + 4 displacement */
7591 opcode
[1] = opcode
[0] + 0x10;
7592 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7593 where_to_put_displacement
= &opcode
[2];
7596 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7597 extension
= 3; /* 2 opcode + 2 displacement */
7598 opcode
[1] = opcode
[0] + 0x10;
7599 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7600 where_to_put_displacement
= &opcode
[2];
7603 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7608 where_to_put_displacement
= &opcode
[3];
7612 BAD_CASE (fragP
->fr_subtype
);
7617 /* If size if less then four we are sure that the operand fits,
7618 but if it's 4, then it could be that the displacement is larger
7620 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7622 && ((addressT
) (displacement_from_opcode_start
- extension
7623 + ((addressT
) 1 << 31))
7624 > (((addressT
) 2 << 31) - 1)))
7626 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7627 _("jump target out of range"));
7628 /* Make us emit 0. */
7629 displacement_from_opcode_start
= extension
;
7631 /* Now put displacement after opcode. */
7632 md_number_to_chars ((char *) where_to_put_displacement
,
7633 (valueT
) (displacement_from_opcode_start
- extension
),
7634 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7635 fragP
->fr_fix
+= extension
;
7638 /* Apply a fixup (fixS) to segment data, once it has been determined
7639 by our caller that we have all the info we need to fix it up.
7641 On the 386, immediates, displacements, and data pointers are all in
7642 the same (little-endian) format, so we don't need to care about which
7646 md_apply_fix (fixP
, valP
, seg
)
7647 /* The fix we're to put in. */
7649 /* Pointer to the value of the bits. */
7651 /* Segment fix is from. */
7652 segT seg ATTRIBUTE_UNUSED
;
7654 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7655 valueT value
= *valP
;
7657 #if !defined (TE_Mach)
7660 switch (fixP
->fx_r_type
)
7666 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7669 case BFD_RELOC_X86_64_32S
:
7670 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7673 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7676 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7681 if (fixP
->fx_addsy
!= NULL
7682 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7683 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7684 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7685 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7686 && !use_rela_relocations
)
7688 /* This is a hack. There should be a better way to handle this.
7689 This covers for the fact that bfd_install_relocation will
7690 subtract the current location (for partial_inplace, PC relative
7691 relocations); see more below. */
7695 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7698 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7700 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7703 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7706 || (symbol_section_p (fixP
->fx_addsy
)
7707 && sym_seg
!= absolute_section
))
7708 && !generic_force_reloc (fixP
))
7710 /* Yes, we add the values in twice. This is because
7711 bfd_install_relocation subtracts them out again. I think
7712 bfd_install_relocation is broken, but I don't dare change
7714 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7718 #if defined (OBJ_COFF) && defined (TE_PE)
7719 /* For some reason, the PE format does not store a
7720 section address offset for a PC relative symbol. */
7721 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7722 || S_IS_WEAK (fixP
->fx_addsy
))
7723 value
+= md_pcrel_from (fixP
);
7727 /* Fix a few things - the dynamic linker expects certain values here,
7728 and we must not disappoint it. */
7729 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7730 if (IS_ELF
&& fixP
->fx_addsy
)
7731 switch (fixP
->fx_r_type
)
7733 case BFD_RELOC_386_PLT32
:
7734 case BFD_RELOC_X86_64_PLT32
:
7735 /* Make the jump instruction point to the address of the operand. At
7736 runtime we merely add the offset to the actual PLT entry. */
7740 case BFD_RELOC_386_TLS_GD
:
7741 case BFD_RELOC_386_TLS_LDM
:
7742 case BFD_RELOC_386_TLS_IE_32
:
7743 case BFD_RELOC_386_TLS_IE
:
7744 case BFD_RELOC_386_TLS_GOTIE
:
7745 case BFD_RELOC_386_TLS_GOTDESC
:
7746 case BFD_RELOC_X86_64_TLSGD
:
7747 case BFD_RELOC_X86_64_TLSLD
:
7748 case BFD_RELOC_X86_64_GOTTPOFF
:
7749 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7750 value
= 0; /* Fully resolved at runtime. No addend. */
7752 case BFD_RELOC_386_TLS_LE
:
7753 case BFD_RELOC_386_TLS_LDO_32
:
7754 case BFD_RELOC_386_TLS_LE_32
:
7755 case BFD_RELOC_X86_64_DTPOFF32
:
7756 case BFD_RELOC_X86_64_DTPOFF64
:
7757 case BFD_RELOC_X86_64_TPOFF32
:
7758 case BFD_RELOC_X86_64_TPOFF64
:
7759 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7762 case BFD_RELOC_386_TLS_DESC_CALL
:
7763 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7764 value
= 0; /* Fully resolved at runtime. No addend. */
7765 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7769 case BFD_RELOC_386_GOT32
:
7770 case BFD_RELOC_X86_64_GOT32
:
7771 value
= 0; /* Fully resolved at runtime. No addend. */
7774 case BFD_RELOC_VTABLE_INHERIT
:
7775 case BFD_RELOC_VTABLE_ENTRY
:
7782 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7784 #endif /* !defined (TE_Mach) */
7786 /* Are we finished with this relocation now? */
7787 if (fixP
->fx_addsy
== NULL
)
7789 else if (use_rela_relocations
)
7791 fixP
->fx_no_overflow
= 1;
7792 /* Remember value for tc_gen_reloc. */
7793 fixP
->fx_addnumber
= value
;
7797 md_number_to_chars (p
, value
, fixP
->fx_size
);
7801 md_atof (int type
, char *litP
, int *sizeP
)
7803 /* This outputs the LITTLENUMs in REVERSE order;
7804 in accord with the bigendian 386. */
7805 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7808 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7811 output_invalid (int c
)
7814 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7817 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7818 "(0x%x)", (unsigned char) c
);
7819 return output_invalid_buf
;
7822 /* REG_STRING starts *before* REGISTER_PREFIX. */
7824 static const reg_entry
*
7825 parse_real_register (char *reg_string
, char **end_op
)
7827 char *s
= reg_string
;
7829 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7832 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7833 if (*s
== REGISTER_PREFIX
)
7836 if (is_space_char (*s
))
7840 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7842 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7843 return (const reg_entry
*) NULL
;
7847 /* For naked regs, make sure that we are not dealing with an identifier.
7848 This prevents confusing an identifier like `eax_var' with register
7850 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7851 return (const reg_entry
*) NULL
;
7855 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7857 /* Handle floating point regs, allowing spaces in the (i) part. */
7858 if (r
== i386_regtab
/* %st is first entry of table */)
7860 if (is_space_char (*s
))
7865 if (is_space_char (*s
))
7867 if (*s
>= '0' && *s
<= '7')
7871 if (is_space_char (*s
))
7876 r
= hash_find (reg_hash
, "st(0)");
7881 /* We have "%st(" then garbage. */
7882 return (const reg_entry
*) NULL
;
7886 if (r
== NULL
|| allow_pseudo_reg
)
7889 if (operand_type_all_zero (&r
->reg_type
))
7890 return (const reg_entry
*) NULL
;
7892 if ((r
->reg_type
.bitfield
.reg32
7893 || r
->reg_type
.bitfield
.sreg3
7894 || r
->reg_type
.bitfield
.control
7895 || r
->reg_type
.bitfield
.debug
7896 || r
->reg_type
.bitfield
.test
)
7897 && !cpu_arch_flags
.bitfield
.cpui386
)
7898 return (const reg_entry
*) NULL
;
7900 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7901 return (const reg_entry
*) NULL
;
7903 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7904 return (const reg_entry
*) NULL
;
7906 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7907 return (const reg_entry
*) NULL
;
7909 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7910 if (!allow_index_reg
7911 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7912 return (const reg_entry
*) NULL
;
7914 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7915 || r
->reg_type
.bitfield
.reg64
)
7916 && (!cpu_arch_flags
.bitfield
.cpulm
7917 || !operand_type_equal (&r
->reg_type
, &control
))
7918 && flag_code
!= CODE_64BIT
)
7919 return (const reg_entry
*) NULL
;
7921 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7922 return (const reg_entry
*) NULL
;
7927 /* REG_STRING starts *before* REGISTER_PREFIX. */
7929 static const reg_entry
*
7930 parse_register (char *reg_string
, char **end_op
)
7934 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7935 r
= parse_real_register (reg_string
, end_op
);
7940 char *save
= input_line_pointer
;
7944 input_line_pointer
= reg_string
;
7945 c
= get_symbol_end ();
7946 symbolP
= symbol_find (reg_string
);
7947 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7949 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7951 know (e
->X_op
== O_register
);
7952 know (e
->X_add_number
>= 0
7953 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7954 r
= i386_regtab
+ e
->X_add_number
;
7955 *end_op
= input_line_pointer
;
7957 *input_line_pointer
= c
;
7958 input_line_pointer
= save
;
7964 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7967 char *end
= input_line_pointer
;
7970 r
= parse_register (name
, &input_line_pointer
);
7971 if (r
&& end
<= input_line_pointer
)
7973 *nextcharP
= *input_line_pointer
;
7974 *input_line_pointer
= 0;
7975 e
->X_op
= O_register
;
7976 e
->X_add_number
= r
- i386_regtab
;
7979 input_line_pointer
= end
;
7985 md_operand (expressionS
*e
)
7987 if (*input_line_pointer
== REGISTER_PREFIX
)
7990 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7994 e
->X_op
= O_register
;
7995 e
->X_add_number
= r
- i386_regtab
;
7996 input_line_pointer
= end
;
8002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8003 const char *md_shortopts
= "kVQ:sqn";
8005 const char *md_shortopts
= "qn";
8008 #define OPTION_32 (OPTION_MD_BASE + 0)
8009 #define OPTION_64 (OPTION_MD_BASE + 1)
8010 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8011 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8012 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8013 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8014 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8015 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8016 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8017 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8018 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8019 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8021 struct option md_longopts
[] =
8023 {"32", no_argument
, NULL
, OPTION_32
},
8024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8025 {"64", no_argument
, NULL
, OPTION_64
},
8027 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8028 {"march", required_argument
, NULL
, OPTION_MARCH
},
8029 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8030 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8031 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8032 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8033 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8034 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8035 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8036 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8037 {NULL
, no_argument
, NULL
, 0}
8039 size_t md_longopts_size
= sizeof (md_longopts
);
8042 md_parse_option (int c
, char *arg
)
8050 optimize_align_code
= 0;
8057 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8058 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8059 should be emitted or not. FIXME: Not implemented. */
8063 /* -V: SVR4 argument to print version ID. */
8065 print_version_id ();
8068 /* -k: Ignore for FreeBSD compatibility. */
8073 /* -s: On i386 Solaris, this tells the native assembler to use
8074 .stab instead of .stab.excl. We always use .stab anyhow. */
8077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8080 const char **list
, **l
;
8082 list
= bfd_target_list ();
8083 for (l
= list
; *l
!= NULL
; l
++)
8084 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8085 || strcmp (*l
, "coff-x86-64") == 0
8086 || strcmp (*l
, "pe-x86-64") == 0
8087 || strcmp (*l
, "pei-x86-64") == 0)
8089 default_arch
= "x86_64";
8093 as_fatal (_("No compiled in support for x86_64"));
8100 default_arch
= "i386";
8104 #ifdef SVR4_COMMENT_CHARS
8109 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8111 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8115 i386_comment_chars
= n
;
8121 arch
= xstrdup (arg
);
8125 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8126 next
= strchr (arch
, '+');
8129 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8131 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8134 cpu_arch_name
= cpu_arch
[i
].name
;
8135 cpu_sub_arch_name
= NULL
;
8136 cpu_arch_flags
= cpu_arch
[i
].flags
;
8137 cpu_arch_isa
= cpu_arch
[i
].type
;
8138 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8139 if (!cpu_arch_tune_set
)
8141 cpu_arch_tune
= cpu_arch_isa
;
8142 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8146 else if (*cpu_arch
[i
].name
== '.'
8147 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8149 /* ISA entension. */
8150 i386_cpu_flags flags
;
8151 flags
= cpu_flags_or (cpu_arch_flags
,
8153 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8155 if (cpu_sub_arch_name
)
8157 char *name
= cpu_sub_arch_name
;
8158 cpu_sub_arch_name
= concat (name
,
8160 (const char *) NULL
);
8164 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8165 cpu_arch_flags
= flags
;
8171 if (i
>= ARRAY_SIZE (cpu_arch
))
8172 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8176 while (next
!= NULL
);
8181 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8182 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8184 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8186 cpu_arch_tune_set
= 1;
8187 cpu_arch_tune
= cpu_arch
[i
].type
;
8188 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8192 if (i
>= ARRAY_SIZE (cpu_arch
))
8193 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8196 case OPTION_MMNEMONIC
:
8197 if (strcasecmp (arg
, "att") == 0)
8199 else if (strcasecmp (arg
, "intel") == 0)
8202 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8205 case OPTION_MSYNTAX
:
8206 if (strcasecmp (arg
, "att") == 0)
8208 else if (strcasecmp (arg
, "intel") == 0)
8211 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8214 case OPTION_MINDEX_REG
:
8215 allow_index_reg
= 1;
8218 case OPTION_MNAKED_REG
:
8219 allow_naked_reg
= 1;
8222 case OPTION_MOLD_GCC
:
8226 case OPTION_MSSE2AVX
:
8230 case OPTION_MSSE_CHECK
:
8231 if (strcasecmp (arg
, "error") == 0)
8232 sse_check
= sse_check_error
;
8233 else if (strcasecmp (arg
, "warning") == 0)
8234 sse_check
= sse_check_warning
;
8235 else if (strcasecmp (arg
, "none") == 0)
8236 sse_check
= sse_check_none
;
8238 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8248 md_show_usage (stream
)
8251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8252 fprintf (stream
, _("\
8254 -V print assembler version number\n\
8257 fprintf (stream
, _("\
8258 -n Do not optimize code alignment\n\
8259 -q quieten some warnings\n"));
8260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8261 fprintf (stream
, _("\
8264 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8265 fprintf (stream
, _("\
8266 --32/--64 generate 32bit/64bit code\n"));
8268 #ifdef SVR4_COMMENT_CHARS
8269 fprintf (stream
, _("\
8270 --divide do not treat `/' as a comment character\n"));
8272 fprintf (stream
, _("\
8273 --divide ignored\n"));
8275 fprintf (stream
, _("\
8276 -march=CPU[,+EXTENSION...]\n\
8277 generate code for CPU and EXTENSION, CPU is one of:\n\
8278 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8279 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8280 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8281 generic32, generic64\n\
8282 EXTENSION is combination of:\n\
8283 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8284 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8285 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8286 fprintf (stream
, _("\
8287 -mtune=CPU optimize for CPU, CPU is one of:\n\
8288 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8289 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8290 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8291 generic32, generic64\n"));
8292 fprintf (stream
, _("\
8293 -msse2avx encode SSE instructions with VEX prefix\n"));
8294 fprintf (stream
, _("\
8295 -msse-check=[none|error|warning]\n\
8296 check SSE instructions\n"));
8297 fprintf (stream
, _("\
8298 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8299 fprintf (stream
, _("\
8300 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8301 fprintf (stream
, _("\
8302 -mindex-reg support pseudo index registers\n"));
8303 fprintf (stream
, _("\
8304 -mnaked-reg don't require `%%' prefix for registers\n"));
8305 fprintf (stream
, _("\
8306 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8309 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8310 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8312 /* Pick the target format to use. */
8315 i386_target_format (void)
8317 if (!strcmp (default_arch
, "x86_64"))
8319 set_code_flag (CODE_64BIT
);
8320 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8322 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8323 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8324 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8325 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8326 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8327 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8328 cpu_arch_isa_flags
.bitfield
.cpup4
= 1;
8329 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8330 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8331 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8333 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8335 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8336 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8337 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8338 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8339 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8340 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8341 cpu_arch_tune_flags
.bitfield
.cpup4
= 1;
8342 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8343 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8344 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8347 else if (!strcmp (default_arch
, "i386"))
8349 set_code_flag (CODE_32BIT
);
8350 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8352 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8353 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8354 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8356 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8358 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8359 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8360 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8364 as_fatal (_("Unknown architecture"));
8365 switch (OUTPUT_FLAVOR
)
8368 case bfd_target_coff_flavour
:
8369 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8372 #ifdef OBJ_MAYBE_AOUT
8373 case bfd_target_aout_flavour
:
8374 return AOUT_TARGET_FORMAT
;
8376 #ifdef OBJ_MAYBE_COFF
8377 case bfd_target_coff_flavour
:
8380 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8381 case bfd_target_elf_flavour
:
8383 if (flag_code
== CODE_64BIT
)
8386 use_rela_relocations
= 1;
8388 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8397 #endif /* OBJ_MAYBE_ more than one */
8399 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8401 i386_elf_emit_arch_note (void)
8403 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8406 asection
*seg
= now_seg
;
8407 subsegT subseg
= now_subseg
;
8408 Elf_Internal_Note i_note
;
8409 Elf_External_Note e_note
;
8410 asection
*note_secp
;
8413 /* Create the .note section. */
8414 note_secp
= subseg_new (".note", 0);
8415 bfd_set_section_flags (stdoutput
,
8417 SEC_HAS_CONTENTS
| SEC_READONLY
);
8419 /* Process the arch string. */
8420 len
= strlen (cpu_arch_name
);
8422 i_note
.namesz
= len
+ 1;
8424 i_note
.type
= NT_ARCH
;
8425 p
= frag_more (sizeof (e_note
.namesz
));
8426 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8427 p
= frag_more (sizeof (e_note
.descsz
));
8428 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8429 p
= frag_more (sizeof (e_note
.type
));
8430 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8431 p
= frag_more (len
+ 1);
8432 strcpy (p
, cpu_arch_name
);
8434 frag_align (2, 0, 0);
8436 subseg_set (seg
, subseg
);
8442 md_undefined_symbol (name
)
8445 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8446 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8447 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8448 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8452 if (symbol_find (name
))
8453 as_bad (_("GOT already in symbol table"));
8454 GOT_symbol
= symbol_new (name
, undefined_section
,
8455 (valueT
) 0, &zero_address_frag
);
8462 /* Round up a section size to the appropriate boundary. */
8465 md_section_align (segment
, size
)
8466 segT segment ATTRIBUTE_UNUSED
;
8469 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8470 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8472 /* For a.out, force the section size to be aligned. If we don't do
8473 this, BFD will align it for us, but it will not write out the
8474 final bytes of the section. This may be a bug in BFD, but it is
8475 easier to fix it here since that is how the other a.out targets
8479 align
= bfd_get_section_alignment (stdoutput
, segment
);
8480 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8487 /* On the i386, PC-relative offsets are relative to the start of the
8488 next instruction. That is, the address of the offset, plus its
8489 size, since the offset is always the last part of the insn. */
8492 md_pcrel_from (fixS
*fixP
)
8494 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8500 s_bss (int ignore ATTRIBUTE_UNUSED
)
8504 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8506 obj_elf_section_change_hook ();
8508 temp
= get_absolute_expression ();
8509 subseg_set (bss_section
, (subsegT
) temp
);
8510 demand_empty_rest_of_line ();
8516 i386_validate_fix (fixS
*fixp
)
8518 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8520 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8524 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8529 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8531 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8538 tc_gen_reloc (section
, fixp
)
8539 asection
*section ATTRIBUTE_UNUSED
;
8543 bfd_reloc_code_real_type code
;
8545 switch (fixp
->fx_r_type
)
8547 case BFD_RELOC_X86_64_PLT32
:
8548 case BFD_RELOC_X86_64_GOT32
:
8549 case BFD_RELOC_X86_64_GOTPCREL
:
8550 case BFD_RELOC_386_PLT32
:
8551 case BFD_RELOC_386_GOT32
:
8552 case BFD_RELOC_386_GOTOFF
:
8553 case BFD_RELOC_386_GOTPC
:
8554 case BFD_RELOC_386_TLS_GD
:
8555 case BFD_RELOC_386_TLS_LDM
:
8556 case BFD_RELOC_386_TLS_LDO_32
:
8557 case BFD_RELOC_386_TLS_IE_32
:
8558 case BFD_RELOC_386_TLS_IE
:
8559 case BFD_RELOC_386_TLS_GOTIE
:
8560 case BFD_RELOC_386_TLS_LE_32
:
8561 case BFD_RELOC_386_TLS_LE
:
8562 case BFD_RELOC_386_TLS_GOTDESC
:
8563 case BFD_RELOC_386_TLS_DESC_CALL
:
8564 case BFD_RELOC_X86_64_TLSGD
:
8565 case BFD_RELOC_X86_64_TLSLD
:
8566 case BFD_RELOC_X86_64_DTPOFF32
:
8567 case BFD_RELOC_X86_64_DTPOFF64
:
8568 case BFD_RELOC_X86_64_GOTTPOFF
:
8569 case BFD_RELOC_X86_64_TPOFF32
:
8570 case BFD_RELOC_X86_64_TPOFF64
:
8571 case BFD_RELOC_X86_64_GOTOFF64
:
8572 case BFD_RELOC_X86_64_GOTPC32
:
8573 case BFD_RELOC_X86_64_GOT64
:
8574 case BFD_RELOC_X86_64_GOTPCREL64
:
8575 case BFD_RELOC_X86_64_GOTPC64
:
8576 case BFD_RELOC_X86_64_GOTPLT64
:
8577 case BFD_RELOC_X86_64_PLTOFF64
:
8578 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8579 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8581 case BFD_RELOC_VTABLE_ENTRY
:
8582 case BFD_RELOC_VTABLE_INHERIT
:
8584 case BFD_RELOC_32_SECREL
:
8586 code
= fixp
->fx_r_type
;
8588 case BFD_RELOC_X86_64_32S
:
8589 if (!fixp
->fx_pcrel
)
8591 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8592 code
= fixp
->fx_r_type
;
8598 switch (fixp
->fx_size
)
8601 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8602 _("can not do %d byte pc-relative relocation"),
8604 code
= BFD_RELOC_32_PCREL
;
8606 case 1: code
= BFD_RELOC_8_PCREL
; break;
8607 case 2: code
= BFD_RELOC_16_PCREL
; break;
8608 case 4: code
= BFD_RELOC_32_PCREL
; break;
8610 case 8: code
= BFD_RELOC_64_PCREL
; break;
8616 switch (fixp
->fx_size
)
8619 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8620 _("can not do %d byte relocation"),
8622 code
= BFD_RELOC_32
;
8624 case 1: code
= BFD_RELOC_8
; break;
8625 case 2: code
= BFD_RELOC_16
; break;
8626 case 4: code
= BFD_RELOC_32
; break;
8628 case 8: code
= BFD_RELOC_64
; break;
8635 if ((code
== BFD_RELOC_32
8636 || code
== BFD_RELOC_32_PCREL
8637 || code
== BFD_RELOC_X86_64_32S
)
8639 && fixp
->fx_addsy
== GOT_symbol
)
8642 code
= BFD_RELOC_386_GOTPC
;
8644 code
= BFD_RELOC_X86_64_GOTPC32
;
8646 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8648 && fixp
->fx_addsy
== GOT_symbol
)
8650 code
= BFD_RELOC_X86_64_GOTPC64
;
8653 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8654 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8655 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8657 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8659 if (!use_rela_relocations
)
8661 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8662 vtable entry to be used in the relocation's section offset. */
8663 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8664 rel
->address
= fixp
->fx_offset
;
8668 /* Use the rela in 64bit mode. */
8671 if (!fixp
->fx_pcrel
)
8672 rel
->addend
= fixp
->fx_offset
;
8676 case BFD_RELOC_X86_64_PLT32
:
8677 case BFD_RELOC_X86_64_GOT32
:
8678 case BFD_RELOC_X86_64_GOTPCREL
:
8679 case BFD_RELOC_X86_64_TLSGD
:
8680 case BFD_RELOC_X86_64_TLSLD
:
8681 case BFD_RELOC_X86_64_GOTTPOFF
:
8682 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8683 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8684 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8687 rel
->addend
= (section
->vma
8689 + fixp
->fx_addnumber
8690 + md_pcrel_from (fixp
));
8695 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8696 if (rel
->howto
== NULL
)
8698 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8699 _("cannot represent relocation type %s"),
8700 bfd_get_reloc_code_name (code
));
8701 /* Set howto to a garbage value so that we can keep going. */
8702 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8703 assert (rel
->howto
!= NULL
);
8710 /* Parse operands using Intel syntax. This implements a recursive descent
8711 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8714 FIXME: We do not recognize the full operand grammar defined in the MASM
8715 documentation. In particular, all the structure/union and
8716 high-level macro operands are missing.
8718 Uppercase words are terminals, lower case words are non-terminals.
8719 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8720 bars '|' denote choices. Most grammar productions are implemented in
8721 functions called 'intel_<production>'.
8723 Initial production is 'expr'.
8729 binOp & | AND | \| | OR | ^ | XOR
8731 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8733 constant digits [[ radixOverride ]]
8735 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8773 => expr expr cmpOp e04
8776 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8777 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8779 hexdigit a | b | c | d | e | f
8780 | A | B | C | D | E | F
8786 mulOp * | / | % | MOD | << | SHL | >> | SHR
8790 register specialRegister
8794 segmentRegister CS | DS | ES | FS | GS | SS
8796 specialRegister CR0 | CR2 | CR3 | CR4
8797 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8798 | TR3 | TR4 | TR5 | TR6 | TR7
8800 We simplify the grammar in obvious places (e.g., register parsing is
8801 done by calling parse_register) and eliminate immediate left recursion
8802 to implement a recursive-descent parser.
8806 expr' cmpOp e04 expr'
8858 /* Parsing structure for the intel syntax parser. Used to implement the
8859 semantic actions for the operand grammar. */
8860 struct intel_parser_s
8862 char *op_string
; /* The string being parsed. */
8863 int got_a_float
; /* Whether the operand is a float. */
8864 int op_modifier
; /* Operand modifier. */
8865 int is_mem
; /* 1 if operand is memory reference. */
8866 int in_offset
; /* >=1 if parsing operand of offset. */
8867 int in_bracket
; /* >=1 if parsing operand in brackets. */
8868 const reg_entry
*reg
; /* Last register reference found. */
8869 char *disp
; /* Displacement string being built. */
8870 char *next_operand
; /* Resume point when splitting operands. */
8873 static struct intel_parser_s intel_parser
;
8875 /* Token structure for parsing intel syntax. */
8878 int code
; /* Token code. */
8879 const reg_entry
*reg
; /* Register entry for register tokens. */
8880 char *str
; /* String representation. */
8883 static struct intel_token cur_token
, prev_token
;
8885 /* Token codes for the intel parser. Since T_SHORT is already used
8886 by COFF, undefine it first to prevent a warning. */
8904 #define T_YMMWORD 16
8906 /* Prototypes for intel parser functions. */
8907 static int intel_match_token (int);
8908 static void intel_putback_token (void);
8909 static void intel_get_token (void);
8910 static int intel_expr (void);
8911 static int intel_e04 (void);
8912 static int intel_e05 (void);
8913 static int intel_e06 (void);
8914 static int intel_e09 (void);
8915 static int intel_e10 (void);
8916 static int intel_e11 (void);
8919 i386_intel_operand (char *operand_string
, int got_a_float
)
8923 const reg_entry
*final_base
= i
.base_reg
;
8924 const reg_entry
*final_index
= i
.index_reg
;
8926 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8927 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8931 /* Initialize token holders. */
8932 cur_token
.code
= prev_token
.code
= T_NIL
;
8933 cur_token
.reg
= prev_token
.reg
= NULL
;
8934 cur_token
.str
= prev_token
.str
= NULL
;
8936 /* Initialize parser structure. */
8937 intel_parser
.got_a_float
= got_a_float
;
8938 intel_parser
.op_modifier
= 0;
8939 intel_parser
.is_mem
= 0;
8940 intel_parser
.in_offset
= 0;
8941 intel_parser
.in_bracket
= 0;
8942 intel_parser
.reg
= NULL
;
8943 intel_parser
.disp
[0] = '\0';
8944 intel_parser
.next_operand
= NULL
;
8949 /* Read the first token and start the parser. */
8951 ret
= intel_expr ();
8956 if (cur_token
.code
!= T_NIL
)
8958 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8959 current_templates
->start
->name
, cur_token
.str
);
8962 /* If we found a memory reference, hand it over to i386_displacement
8963 to fill in the rest of the operand fields. */
8964 else if (intel_parser
.is_mem
)
8966 if ((i
.mem_operands
== 1
8967 && !current_templates
->start
->opcode_modifier
.isstring
)
8968 || i
.mem_operands
== 2)
8970 as_bad (_("too many memory references for '%s'"),
8971 current_templates
->start
->name
);
8976 char *s
= intel_parser
.disp
;
8978 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8979 /* See the comments in intel_bracket_expr. */
8980 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8982 /* Add the displacement expression. */
8984 ret
= i386_displacement (s
, s
+ strlen (s
));
8987 /* Swap base and index in 16-bit memory operands like
8988 [si+bx]. Since i386_index_check is also used in AT&T
8989 mode we have to do that here. */
8992 && i
.base_reg
->reg_type
.bitfield
.reg16
8993 && i
.index_reg
->reg_type
.bitfield
.reg16
8994 && i
.base_reg
->reg_num
>= 6
8995 && i
.index_reg
->reg_num
< 6)
8997 const reg_entry
*base
= i
.index_reg
;
8999 i
.index_reg
= i
.base_reg
;
9002 ret
= i386_index_check (operand_string
);
9006 i
.types
[this_operand
].bitfield
.mem
= 1;
9012 /* Constant and OFFSET expressions are handled by i386_immediate. */
9013 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
9014 || intel_parser
.reg
== NULL
)
9016 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
9018 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9019 as_warn (_("Segment override ignored"));
9020 i
.seg
[i
.mem_operands
] = NULL
;
9022 ret
= i386_immediate (intel_parser
.disp
);
9025 if (!final_base
&& !final_index
)
9027 final_base
= i
.base_reg
;
9028 final_index
= i
.index_reg
;
9031 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
9033 if (!ret
|| !intel_parser
.next_operand
)
9035 intel_parser
.op_string
= intel_parser
.next_operand
;
9036 this_operand
= i
.operands
++;
9037 i
.types
[this_operand
].bitfield
.unspecified
= 1;
9041 free (intel_parser
.disp
);
9043 if (final_base
|| final_index
)
9045 i
.base_reg
= final_base
;
9046 i
.index_reg
= final_index
;
9052 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9056 expr' cmpOp e04 expr'
9061 /* XXX Implement the comparison operators. */
9062 return intel_e04 ();
9079 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9080 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9082 if (cur_token
.code
== '+')
9084 else if (cur_token
.code
== '-')
9085 nregs
= NUM_ADDRESS_REGS
;
9089 strcat (intel_parser
.disp
, cur_token
.str
);
9090 intel_match_token (cur_token
.code
);
9101 int nregs
= ~NUM_ADDRESS_REGS
;
9108 if (cur_token
.code
== '&'
9109 || cur_token
.code
== '|'
9110 || cur_token
.code
== '^')
9114 str
[0] = cur_token
.code
;
9116 strcat (intel_parser
.disp
, str
);
9121 intel_match_token (cur_token
.code
);
9126 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9127 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9138 int nregs
= ~NUM_ADDRESS_REGS
;
9145 if (cur_token
.code
== '*'
9146 || cur_token
.code
== '/'
9147 || cur_token
.code
== '%')
9151 str
[0] = cur_token
.code
;
9153 strcat (intel_parser
.disp
, str
);
9155 else if (cur_token
.code
== T_SHL
)
9156 strcat (intel_parser
.disp
, "<<");
9157 else if (cur_token
.code
== T_SHR
)
9158 strcat (intel_parser
.disp
, ">>");
9162 intel_match_token (cur_token
.code
);
9167 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9168 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9186 int nregs
= ~NUM_ADDRESS_REGS
;
9191 /* Don't consume constants here. */
9192 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9194 /* Need to look one token ahead - if the next token
9195 is a constant, the current token is its sign. */
9198 intel_match_token (cur_token
.code
);
9199 next_code
= cur_token
.code
;
9200 intel_putback_token ();
9201 if (next_code
== T_CONST
)
9205 /* e09 OFFSET e09 */
9206 if (cur_token
.code
== T_OFFSET
)
9209 ++intel_parser
.in_offset
;
9213 else if (cur_token
.code
== T_SHORT
)
9214 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9217 else if (cur_token
.code
== '+')
9218 strcat (intel_parser
.disp
, "+");
9223 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9229 str
[0] = cur_token
.code
;
9231 strcat (intel_parser
.disp
, str
);
9238 intel_match_token (cur_token
.code
);
9246 /* e09' PTR e10 e09' */
9247 if (cur_token
.code
== T_PTR
)
9251 if (prev_token
.code
== T_BYTE
)
9253 suffix
= BYTE_MNEM_SUFFIX
;
9254 i
.types
[this_operand
].bitfield
.byte
= 1;
9257 else if (prev_token
.code
== T_WORD
)
9259 if ((current_templates
->start
->name
[0] == 'l'
9260 && current_templates
->start
->name
[2] == 's'
9261 && current_templates
->start
->name
[3] == 0)
9262 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9263 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9264 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9265 suffix
= SHORT_MNEM_SUFFIX
;
9267 suffix
= WORD_MNEM_SUFFIX
;
9268 i
.types
[this_operand
].bitfield
.word
= 1;
9271 else if (prev_token
.code
== T_DWORD
)
9273 if ((current_templates
->start
->name
[0] == 'l'
9274 && current_templates
->start
->name
[2] == 's'
9275 && current_templates
->start
->name
[3] == 0)
9276 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9277 suffix
= WORD_MNEM_SUFFIX
;
9278 else if (flag_code
== CODE_16BIT
9279 && (current_templates
->start
->opcode_modifier
.jump
9280 || current_templates
->start
->opcode_modifier
.jumpdword
))
9281 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9282 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9283 suffix
= SHORT_MNEM_SUFFIX
;
9285 suffix
= LONG_MNEM_SUFFIX
;
9286 i
.types
[this_operand
].bitfield
.dword
= 1;
9289 else if (prev_token
.code
== T_FWORD
)
9291 if (current_templates
->start
->name
[0] == 'l'
9292 && current_templates
->start
->name
[2] == 's'
9293 && current_templates
->start
->name
[3] == 0)
9294 suffix
= LONG_MNEM_SUFFIX
;
9295 else if (!intel_parser
.got_a_float
)
9297 if (flag_code
== CODE_16BIT
)
9298 add_prefix (DATA_PREFIX_OPCODE
);
9299 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9302 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9303 i
.types
[this_operand
].bitfield
.fword
= 1;
9306 else if (prev_token
.code
== T_QWORD
)
9308 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9309 || intel_parser
.got_a_float
== 1) /* "f..." */
9310 suffix
= LONG_MNEM_SUFFIX
;
9312 suffix
= QWORD_MNEM_SUFFIX
;
9313 i
.types
[this_operand
].bitfield
.qword
= 1;
9316 else if (prev_token
.code
== T_TBYTE
)
9318 if (intel_parser
.got_a_float
== 1)
9319 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9321 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9324 else if (prev_token
.code
== T_XMMWORD
)
9326 suffix
= XMMWORD_MNEM_SUFFIX
;
9327 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9330 else if (prev_token
.code
== T_YMMWORD
)
9332 suffix
= YMMWORD_MNEM_SUFFIX
;
9333 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9338 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9342 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9344 /* Operands for jump/call using 'ptr' notation denote absolute
9346 if (current_templates
->start
->opcode_modifier
.jump
9347 || current_templates
->start
->opcode_modifier
.jumpdword
)
9348 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9350 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9354 else if (i
.suffix
!= suffix
)
9356 as_bad (_("Conflicting operand modifiers"));
9362 /* e09' : e10 e09' */
9363 else if (cur_token
.code
== ':')
9365 if (prev_token
.code
!= T_REG
)
9367 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9368 segment/group identifier (which we don't have), using comma
9369 as the operand separator there is even less consistent, since
9370 there all branches only have a single operand. */
9371 if (this_operand
!= 0
9372 || intel_parser
.in_offset
9373 || intel_parser
.in_bracket
9374 || (!current_templates
->start
->opcode_modifier
.jump
9375 && !current_templates
->start
->opcode_modifier
.jumpdword
9376 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9377 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9378 return intel_match_token (T_NIL
);
9379 /* Remember the start of the 2nd operand and terminate 1st
9381 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9382 another expression), but it gets at least the simplest case
9383 (a plain number or symbol on the left side) right. */
9384 intel_parser
.next_operand
= intel_parser
.op_string
;
9385 *--intel_parser
.op_string
= '\0';
9386 return intel_match_token (':');
9394 intel_match_token (cur_token
.code
);
9400 --intel_parser
.in_offset
;
9403 if (NUM_ADDRESS_REGS
> nregs
)
9405 as_bad (_("Invalid operand to `OFFSET'"));
9408 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9411 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9412 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9417 intel_bracket_expr (void)
9419 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9420 const char *start
= intel_parser
.op_string
;
9423 if (i
.op
[this_operand
].regs
)
9424 return intel_match_token (T_NIL
);
9426 intel_match_token ('[');
9428 /* Mark as a memory operand only if it's not already known to be an
9429 offset expression. If it's an offset expression, we need to keep
9431 if (!intel_parser
.in_offset
)
9433 ++intel_parser
.in_bracket
;
9435 /* Operands for jump/call inside brackets denote absolute addresses. */
9436 if (current_templates
->start
->opcode_modifier
.jump
9437 || current_templates
->start
->opcode_modifier
.jumpdword
)
9438 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9440 /* Unfortunately gas always diverged from MASM in a respect that can't
9441 be easily fixed without risking to break code sequences likely to be
9442 encountered (the testsuite even check for this): MASM doesn't consider
9443 an expression inside brackets unconditionally as a memory reference.
9444 When that is e.g. a constant, an offset expression, or the sum of the
9445 two, this is still taken as a constant load. gas, however, always
9446 treated these as memory references. As a compromise, we'll try to make
9447 offset expressions inside brackets work the MASM way (since that's
9448 less likely to be found in real world code), but make constants alone
9449 continue to work the traditional gas way. In either case, issue a
9451 intel_parser
.op_modifier
&= ~was_offset
;
9454 strcat (intel_parser
.disp
, "[");
9456 /* Add a '+' to the displacement string if necessary. */
9457 if (*intel_parser
.disp
!= '\0'
9458 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9459 strcat (intel_parser
.disp
, "+");
9462 && (len
= intel_parser
.op_string
- start
- 1,
9463 intel_match_token (']')))
9465 /* Preserve brackets when the operand is an offset expression. */
9466 if (intel_parser
.in_offset
)
9467 strcat (intel_parser
.disp
, "]");
9470 --intel_parser
.in_bracket
;
9471 if (i
.base_reg
|| i
.index_reg
)
9472 intel_parser
.is_mem
= 1;
9473 if (!intel_parser
.is_mem
)
9475 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9476 /* Defer the warning until all of the operand was parsed. */
9477 intel_parser
.is_mem
= -1;
9478 else if (!quiet_warnings
)
9479 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9480 len
, start
, len
, start
);
9483 intel_parser
.op_modifier
|= was_offset
;
9500 while (cur_token
.code
== '[')
9502 if (!intel_bracket_expr ())
9528 switch (cur_token
.code
)
9532 intel_match_token ('(');
9533 strcat (intel_parser
.disp
, "(");
9535 if (intel_expr () && intel_match_token (')'))
9537 strcat (intel_parser
.disp
, ")");
9544 return intel_bracket_expr ();
9549 strcat (intel_parser
.disp
, cur_token
.str
);
9550 intel_match_token (cur_token
.code
);
9552 /* Mark as a memory operand only if it's not already known to be an
9553 offset expression. */
9554 if (!intel_parser
.in_offset
)
9555 intel_parser
.is_mem
= 1;
9562 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9564 intel_match_token (T_REG
);
9566 /* Check for segment change. */
9567 if (cur_token
.code
== ':')
9569 if (!reg
->reg_type
.bitfield
.sreg2
9570 && !reg
->reg_type
.bitfield
.sreg3
)
9572 as_bad (_("`%s' is not a valid segment register"),
9576 else if (i
.mem_operands
>= 2)
9577 as_warn (_("Segment override ignored"));
9578 else if (i
.seg
[i
.mem_operands
])
9579 as_warn (_("Extra segment override ignored"));
9582 if (!intel_parser
.in_offset
)
9583 intel_parser
.is_mem
= 1;
9584 switch (reg
->reg_num
)
9587 i
.seg
[i
.mem_operands
] = &es
;
9590 i
.seg
[i
.mem_operands
] = &cs
;
9593 i
.seg
[i
.mem_operands
] = &ss
;
9596 i
.seg
[i
.mem_operands
] = &ds
;
9599 i
.seg
[i
.mem_operands
] = &fs
;
9602 i
.seg
[i
.mem_operands
] = &gs
;
9608 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9610 as_bad (_("cannot use `FLAT' here"));
9614 /* Not a segment register. Check for register scaling. */
9615 else if (cur_token
.code
== '*')
9617 if (!intel_parser
.in_bracket
)
9619 as_bad (_("Register scaling only allowed in memory operands"));
9623 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9624 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9625 else if (i
.index_reg
)
9626 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9628 /* What follows must be a valid scale. */
9629 intel_match_token ('*');
9631 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9633 /* Set the scale after setting the register (otherwise,
9634 i386_scale will complain) */
9635 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9637 char *str
, sign
= cur_token
.code
;
9638 intel_match_token (cur_token
.code
);
9639 if (cur_token
.code
!= T_CONST
)
9641 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9645 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9646 strcpy (str
+ 1, cur_token
.str
);
9648 if (!i386_scale (str
))
9652 else if (!i386_scale (cur_token
.str
))
9654 intel_match_token (cur_token
.code
);
9657 /* No scaling. If this is a memory operand, the register is either a
9658 base register (first occurrence) or an index register (second
9660 else if (intel_parser
.in_bracket
)
9665 else if (!i
.index_reg
)
9669 as_bad (_("Too many register references in memory operand"));
9673 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9676 /* It's neither base nor index. */
9677 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9679 i386_operand_type temp
= reg
->reg_type
;
9680 temp
.bitfield
.baseindex
= 0;
9681 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9683 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9684 i
.op
[this_operand
].regs
= reg
;
9689 as_bad (_("Invalid use of register"));
9693 /* Since registers are not part of the displacement string (except
9694 when we're parsing offset operands), we may need to remove any
9695 preceding '+' from the displacement string. */
9696 if (*intel_parser
.disp
!= '\0'
9697 && !intel_parser
.in_offset
)
9699 char *s
= intel_parser
.disp
;
9700 s
+= strlen (s
) - 1;
9725 intel_match_token (cur_token
.code
);
9727 if (cur_token
.code
== T_PTR
)
9730 /* It must have been an identifier. */
9731 intel_putback_token ();
9732 cur_token
.code
= T_ID
;
9738 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9742 /* The identifier represents a memory reference only if it's not
9743 preceded by an offset modifier and if it's not an equate. */
9744 symbolP
= symbol_find(cur_token
.str
);
9745 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9746 intel_parser
.is_mem
= 1;
9754 char *save_str
, sign
= 0;
9756 /* Allow constants that start with `+' or `-'. */
9757 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9759 sign
= cur_token
.code
;
9760 intel_match_token (cur_token
.code
);
9761 if (cur_token
.code
!= T_CONST
)
9763 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9769 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9770 strcpy (save_str
+ !!sign
, cur_token
.str
);
9774 /* Get the next token to check for register scaling. */
9775 intel_match_token (cur_token
.code
);
9777 /* Check if this constant is a scaling factor for an
9779 if (cur_token
.code
== '*')
9781 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9783 const reg_entry
*reg
= cur_token
.reg
;
9785 if (!intel_parser
.in_bracket
)
9787 as_bad (_("Register scaling only allowed "
9788 "in memory operands"));
9792 /* Disallow things like [1*si].
9793 sp and esp are invalid as index. */
9794 if (reg
->reg_type
.bitfield
.reg16
)
9795 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9796 else if (i
.index_reg
)
9797 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9799 /* The constant is followed by `* reg', so it must be
9802 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9804 /* Set the scale after setting the register (otherwise,
9805 i386_scale will complain) */
9806 if (!i386_scale (save_str
))
9808 intel_match_token (T_REG
);
9810 /* Since registers are not part of the displacement
9811 string, we may need to remove any preceding '+' from
9812 the displacement string. */
9813 if (*intel_parser
.disp
!= '\0')
9815 char *s
= intel_parser
.disp
;
9816 s
+= strlen (s
) - 1;
9826 /* The constant was not used for register scaling. Since we have
9827 already consumed the token following `*' we now need to put it
9828 back in the stream. */
9829 intel_putback_token ();
9832 /* Add the constant to the displacement string. */
9833 strcat (intel_parser
.disp
, save_str
);
9840 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9844 /* Match the given token against cur_token. If they match, read the next
9845 token from the operand string. */
9847 intel_match_token (int code
)
9849 if (cur_token
.code
== code
)
9856 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9861 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9863 intel_get_token (void)
9866 const reg_entry
*reg
;
9867 struct intel_token new_token
;
9869 new_token
.code
= T_NIL
;
9870 new_token
.reg
= NULL
;
9871 new_token
.str
= NULL
;
9873 /* Free the memory allocated to the previous token and move
9874 cur_token to prev_token. */
9876 free (prev_token
.str
);
9878 prev_token
= cur_token
;
9880 /* Skip whitespace. */
9881 while (is_space_char (*intel_parser
.op_string
))
9882 intel_parser
.op_string
++;
9884 /* Return an empty token if we find nothing else on the line. */
9885 if (*intel_parser
.op_string
== '\0')
9887 cur_token
= new_token
;
9891 /* The new token cannot be larger than the remainder of the operand
9893 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9894 new_token
.str
[0] = '\0';
9896 if (strchr ("0123456789", *intel_parser
.op_string
))
9898 char *p
= new_token
.str
;
9899 char *q
= intel_parser
.op_string
;
9900 new_token
.code
= T_CONST
;
9902 /* Allow any kind of identifier char to encompass floating point and
9903 hexadecimal numbers. */
9904 while (is_identifier_char (*q
))
9908 /* Recognize special symbol names [0-9][bf]. */
9909 if (strlen (intel_parser
.op_string
) == 2
9910 && (intel_parser
.op_string
[1] == 'b'
9911 || intel_parser
.op_string
[1] == 'f'))
9912 new_token
.code
= T_ID
;
9915 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9917 size_t len
= end_op
- intel_parser
.op_string
;
9919 new_token
.code
= T_REG
;
9920 new_token
.reg
= reg
;
9922 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9923 new_token
.str
[len
] = '\0';
9926 else if (is_identifier_char (*intel_parser
.op_string
))
9928 char *p
= new_token
.str
;
9929 char *q
= intel_parser
.op_string
;
9931 /* A '.' or '$' followed by an identifier char is an identifier.
9932 Otherwise, it's operator '.' followed by an expression. */
9933 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9935 new_token
.code
= '.';
9936 new_token
.str
[0] = '.';
9937 new_token
.str
[1] = '\0';
9941 while (is_identifier_char (*q
) || *q
== '@')
9945 if (strcasecmp (new_token
.str
, "NOT") == 0)
9946 new_token
.code
= '~';
9948 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9949 new_token
.code
= '%';
9951 else if (strcasecmp (new_token
.str
, "AND") == 0)
9952 new_token
.code
= '&';
9954 else if (strcasecmp (new_token
.str
, "OR") == 0)
9955 new_token
.code
= '|';
9957 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9958 new_token
.code
= '^';
9960 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9961 new_token
.code
= T_SHL
;
9963 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9964 new_token
.code
= T_SHR
;
9966 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9967 new_token
.code
= T_BYTE
;
9969 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9970 new_token
.code
= T_WORD
;
9972 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9973 new_token
.code
= T_DWORD
;
9975 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9976 new_token
.code
= T_FWORD
;
9978 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9979 new_token
.code
= T_QWORD
;
9981 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9982 /* XXX remove (gcc still uses it) */
9983 || strcasecmp (new_token
.str
, "XWORD") == 0)
9984 new_token
.code
= T_TBYTE
;
9986 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9987 || strcasecmp (new_token
.str
, "OWORD") == 0)
9988 new_token
.code
= T_XMMWORD
;
9990 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9991 new_token
.code
= T_YMMWORD
;
9993 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9994 new_token
.code
= T_PTR
;
9996 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9997 new_token
.code
= T_SHORT
;
9999 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
10001 new_token
.code
= T_OFFSET
;
10003 /* ??? This is not mentioned in the MASM grammar but gcc
10004 makes use of it with -mintel-syntax. OFFSET may be
10005 followed by FLAT: */
10006 if (strncasecmp (q
, " FLAT:", 6) == 0)
10007 strcat (new_token
.str
, " FLAT:");
10011 new_token
.code
= T_ID
;
10015 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
10017 new_token
.code
= *intel_parser
.op_string
;
10018 new_token
.str
[0] = *intel_parser
.op_string
;
10019 new_token
.str
[1] = '\0';
10022 else if (strchr ("<>", *intel_parser
.op_string
)
10023 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
10025 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
10026 new_token
.str
[0] = *intel_parser
.op_string
;
10027 new_token
.str
[1] = *intel_parser
.op_string
;
10028 new_token
.str
[2] = '\0';
10032 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
10034 intel_parser
.op_string
+= strlen (new_token
.str
);
10035 cur_token
= new_token
;
10038 /* Put cur_token back into the token stream and make cur_token point to
10041 intel_putback_token (void)
10043 if (cur_token
.code
!= T_NIL
)
10045 intel_parser
.op_string
-= strlen (cur_token
.str
);
10046 free (cur_token
.str
);
10048 cur_token
= prev_token
;
10050 /* Forget prev_token. */
10051 prev_token
.code
= T_NIL
;
10052 prev_token
.reg
= NULL
;
10053 prev_token
.str
= NULL
;
10057 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10059 int saved_naked_reg
;
10060 char saved_register_dot
;
10062 saved_naked_reg
= allow_naked_reg
;
10063 allow_naked_reg
= 1;
10064 saved_register_dot
= register_chars
['.'];
10065 register_chars
['.'] = '.';
10066 allow_pseudo_reg
= 1;
10067 expression_and_evaluate (exp
);
10068 allow_pseudo_reg
= 0;
10069 register_chars
['.'] = saved_register_dot
;
10070 allow_naked_reg
= saved_naked_reg
;
10072 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10074 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10076 exp
->X_op
= O_constant
;
10077 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10078 .dw2_regnum
[flag_code
>> 1];
10081 exp
->X_op
= O_illegal
;
10086 tc_x86_frame_initial_instructions (void)
10088 static unsigned int sp_regno
[2];
10090 if (!sp_regno
[flag_code
>> 1])
10092 char *saved_input
= input_line_pointer
;
10093 char sp
[][4] = {"esp", "rsp"};
10096 input_line_pointer
= sp
[flag_code
>> 1];
10097 tc_x86_parse_to_dw2regnum (&exp
);
10098 assert (exp
.X_op
== O_constant
);
10099 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10100 input_line_pointer
= saved_input
;
10103 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10104 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10108 i386_elf_section_type (const char *str
, size_t len
)
10110 if (flag_code
== CODE_64BIT
10111 && len
== sizeof ("unwind") - 1
10112 && strncmp (str
, "unwind", 6) == 0)
10113 return SHT_X86_64_UNWIND
;
10120 i386_solaris_fix_up_eh_frame (segT sec
)
10122 if (flag_code
== CODE_64BIT
)
10123 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10129 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10133 expr
.X_op
= O_secrel
;
10134 expr
.X_add_symbol
= symbol
;
10135 expr
.X_add_number
= 0;
10136 emit_expr (&expr
, size
);
10140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10141 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10144 x86_64_section_letter (int letter
, char **ptr_msg
)
10146 if (flag_code
== CODE_64BIT
)
10149 return SHF_X86_64_LARGE
;
10151 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10154 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10159 x86_64_section_word (char *str
, size_t len
)
10161 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10162 return SHF_X86_64_LARGE
;
10168 handle_large_common (int small ATTRIBUTE_UNUSED
)
10170 if (flag_code
!= CODE_64BIT
)
10172 s_comm_internal (0, elf_common_parse
);
10173 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10177 static segT lbss_section
;
10178 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10179 asection
*saved_bss_section
= bss_section
;
10181 if (lbss_section
== NULL
)
10183 flagword applicable
;
10184 segT seg
= now_seg
;
10185 subsegT subseg
= now_subseg
;
10187 /* The .lbss section is for local .largecomm symbols. */
10188 lbss_section
= subseg_new (".lbss", 0);
10189 applicable
= bfd_applicable_section_flags (stdoutput
);
10190 bfd_set_section_flags (stdoutput
, lbss_section
,
10191 applicable
& SEC_ALLOC
);
10192 seg_info (lbss_section
)->bss
= 1;
10194 subseg_set (seg
, subseg
);
10197 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10198 bss_section
= lbss_section
;
10200 s_comm_internal (0, elf_common_parse
);
10202 elf_com_section_ptr
= saved_com_section_ptr
;
10203 bss_section
= saved_bss_section
;
10206 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */