1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx
;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm
;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm
;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm
;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation
*mask
;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation
*rounding
;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation
*broadcast
;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift
;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default
= 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default
= 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding
;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize
;
411 /* How to encode vector instructions. */
414 vex_encoding_default
= 0,
421 const char *rep_prefix
;
424 const char *hle_prefix
;
426 /* Have BND prefix. */
427 const char *bnd_prefix
;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix
;
433 enum i386_error error
;
436 typedef struct _i386_insn i386_insn
;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable
[] =
449 { rne
, STRING_COMMA_LEN ("rn-sae") },
450 { rd
, STRING_COMMA_LEN ("rd-sae") },
451 { ru
, STRING_COMMA_LEN ("ru-sae") },
452 { rz
, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly
, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars
[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars
= "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars
= "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars
[] = "#/";
497 const char line_separator_chars
[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS
[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS
[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars
[256];
510 static char register_chars
[256];
511 static char operand_chars
[256];
512 static char identifier_chars
[256];
513 static char digit_chars
[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack
[32];
531 static char *save_stack_p
;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates
*current_templates
;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
545 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
547 /* Current operand we are working on. */
548 static int this_operand
= -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code
;
559 static unsigned int object_64bit
;
560 static unsigned int disallow_64bit_reloc
;
561 static int use_rela_relocations
= 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj
= 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared
= 0;
588 /* 1 for intel syntax,
590 static int intel_syntax
= 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic
= !SYSV386_COMPAT
;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg
= 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg
= 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix
= 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg
= 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix
= 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence
= 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
627 static enum check_kind
633 sse_check
, operand_check
= check_warning
;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize
= 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space
= 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix
= "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size
= '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code
= 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings
= 0;
666 static const char *cpu_arch_name
= NULL
;
667 static char *cpu_sub_arch_name
= NULL
;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set
= 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags
;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags
;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion
= 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx
;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig
= rne
;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS
*GOT_symbol
;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column
;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment
;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table
[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch
[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
819 CPU_GENERIC32_FLAGS
, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
821 CPU_GENERIC64_FLAGS
, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
839 CPU_PENTIUMPRO_FLAGS
, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
849 CPU_NOCONA_FLAGS
, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
855 CPU_CORE2_FLAGS
, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
857 CPU_CORE2_FLAGS
, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
859 CPU_COREI7_FLAGS
, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
865 CPU_IAMCU_FLAGS
, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
871 CPU_ATHLON_FLAGS
, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
879 CPU_AMDFAM10_FLAGS
, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
881 CPU_BDVER1_FLAGS
, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
883 CPU_BDVER2_FLAGS
, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
885 CPU_BDVER3_FLAGS
, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
887 CPU_BDVER4_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
889 CPU_ZNVER1_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
891 CPU_ZNVER2_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
893 CPU_BTVER1_FLAGS
, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
895 CPU_BTVER2_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
917 CPU_SSSE3_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
919 CPU_SSE4_1_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
921 CPU_SSE4_2_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
923 CPU_SSE4_2_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
929 CPU_AVX512F_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
931 CPU_AVX512CD_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
933 CPU_AVX512ER_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
935 CPU_AVX512PF_FLAGS
, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512DQ_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512BW_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
941 CPU_AVX512VL_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
945 CPU_VMFUNC_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
949 CPU_XSAVE_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
951 CPU_XSAVEOPT_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
953 CPU_XSAVEC_FLAGS
, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
955 CPU_XSAVES_FLAGS
, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
959 CPU_PCLMUL_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
961 CPU_PCLMUL_FLAGS
, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
963 CPU_FSGSBASE_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
965 CPU_RDRND_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
979 CPU_MOVBE_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
985 CPU_LZCNT_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
991 CPU_INVPCID_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
993 CPU_CLFLUSH_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
997 CPU_SYSCALL_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
999 CPU_RDTSCP_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1001 CPU_3DNOW_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1003 CPU_3DNOWA_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1005 CPU_PADLOCK_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1007 CPU_SVME_FLAGS
, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1009 CPU_SVME_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1011 CPU_SSE4A_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1021 CPU_RDSEED_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1023 CPU_PRFCHW_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1025 CPU_SMAP_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1031 CPU_CLFLUSHOPT_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1033 CPU_PREFETCHWT1_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1037 CPU_CLWB_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1039 CPU_AVX512IFMA_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1041 CPU_AVX512VBMI_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1043 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1045 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512_VBMI2_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512_VNNI_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512_BITALG_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1055 CPU_CLZERO_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1057 CPU_MWAITX_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1059 CPU_OSPKE_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1061 CPU_RDPID_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1063 CPU_PTWRITE_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1067 CPU_SHSTK_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1069 CPU_GFNI_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1071 CPU_VAES_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1073 CPU_VPCLMULQDQ_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1075 CPU_WBNOINVD_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1077 CPU_PCONFIG_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1079 CPU_WAITPKG_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1081 CPU_CLDEMOTE_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1083 CPU_MOVDIRI_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1085 CPU_MOVDIR64B_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1087 CPU_AVX512_BF16_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1089 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1091 CPU_ENQCMD_FLAGS
, 0 },
1094 static const noarch_entry cpu_noarch
[] =
1096 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1097 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1098 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1099 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1100 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1101 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1102 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1103 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1104 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1105 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1106 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1107 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1108 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1109 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1110 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1111 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1112 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1113 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1114 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1115 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1116 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1117 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1118 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1119 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1120 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1121 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1122 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1123 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1124 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1125 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1126 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1127 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1128 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1129 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1130 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1131 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1132 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1133 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1137 /* Like s_lcomm_internal in gas/read.c but the alignment string
1138 is allowed to be optional. */
1141 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1148 && *input_line_pointer
== ',')
1150 align
= parse_align (needs_align
- 1);
1152 if (align
== (addressT
) -1)
1167 bss_alloc (symbolP
, size
, align
);
1172 pe_lcomm (int needs_align
)
1174 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1178 const pseudo_typeS md_pseudo_table
[] =
1180 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1181 {"align", s_align_bytes
, 0},
1183 {"align", s_align_ptwo
, 0},
1185 {"arch", set_cpu_arch
, 0},
1189 {"lcomm", pe_lcomm
, 1},
1191 {"ffloat", float_cons
, 'f'},
1192 {"dfloat", float_cons
, 'd'},
1193 {"tfloat", float_cons
, 'x'},
1195 {"slong", signed_cons
, 4},
1196 {"noopt", s_ignore
, 0},
1197 {"optim", s_ignore
, 0},
1198 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1199 {"code16", set_code_flag
, CODE_16BIT
},
1200 {"code32", set_code_flag
, CODE_32BIT
},
1202 {"code64", set_code_flag
, CODE_64BIT
},
1204 {"intel_syntax", set_intel_syntax
, 1},
1205 {"att_syntax", set_intel_syntax
, 0},
1206 {"intel_mnemonic", set_intel_mnemonic
, 1},
1207 {"att_mnemonic", set_intel_mnemonic
, 0},
1208 {"allow_index_reg", set_allow_index_reg
, 1},
1209 {"disallow_index_reg", set_allow_index_reg
, 0},
1210 {"sse_check", set_check
, 0},
1211 {"operand_check", set_check
, 1},
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 {"largecomm", handle_large_common
, 0},
1215 {"file", dwarf2_directive_file
, 0},
1216 {"loc", dwarf2_directive_loc
, 0},
1217 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1220 {"secrel32", pe_directive_secrel
, 0},
1225 /* For interface with expression (). */
1226 extern char *input_line_pointer
;
1228 /* Hash table for instruction mnemonic lookup. */
1229 static struct hash_control
*op_hash
;
1231 /* Hash table for register lookup. */
1232 static struct hash_control
*reg_hash
;
1234 /* Various efficient no-op patterns for aligning code labels.
1235 Note: Don't try to assemble the instructions in the comments.
1236 0L and 0w are not legal. */
1237 static const unsigned char f32_1
[] =
1239 static const unsigned char f32_2
[] =
1240 {0x66,0x90}; /* xchg %ax,%ax */
1241 static const unsigned char f32_3
[] =
1242 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1243 static const unsigned char f32_4
[] =
1244 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1245 static const unsigned char f32_6
[] =
1246 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1247 static const unsigned char f32_7
[] =
1248 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1249 static const unsigned char f16_3
[] =
1250 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1251 static const unsigned char f16_4
[] =
1252 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1253 static const unsigned char jump_disp8
[] =
1254 {0xeb}; /* jmp disp8 */
1255 static const unsigned char jump32_disp32
[] =
1256 {0xe9}; /* jmp disp32 */
1257 static const unsigned char jump16_disp32
[] =
1258 {0x66,0xe9}; /* jmp disp32 */
1259 /* 32-bit NOPs patterns. */
1260 static const unsigned char *const f32_patt
[] = {
1261 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1263 /* 16-bit NOPs patterns. */
1264 static const unsigned char *const f16_patt
[] = {
1265 f32_1
, f32_2
, f16_3
, f16_4
1267 /* nopl (%[re]ax) */
1268 static const unsigned char alt_3
[] =
1270 /* nopl 0(%[re]ax) */
1271 static const unsigned char alt_4
[] =
1272 {0x0f,0x1f,0x40,0x00};
1273 /* nopl 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_5
[] =
1275 {0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopw 0(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_6
[] =
1278 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1279 /* nopl 0L(%[re]ax) */
1280 static const unsigned char alt_7
[] =
1281 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1282 /* nopl 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_8
[] =
1284 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw 0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_9
[] =
1287 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_10
[] =
1290 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* data16 nopw %cs:0L(%eax,%eax,1) */
1292 static const unsigned char alt_11
[] =
1293 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1294 /* 32-bit and 64-bit NOPs patterns. */
1295 static const unsigned char *const alt_patt
[] = {
1296 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1297 alt_9
, alt_10
, alt_11
1300 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1301 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1304 i386_output_nops (char *where
, const unsigned char *const *patt
,
1305 int count
, int max_single_nop_size
)
1308 /* Place the longer NOP first. */
1311 const unsigned char *nops
;
1313 if (max_single_nop_size
< 1)
1315 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1316 max_single_nop_size
);
1320 nops
= patt
[max_single_nop_size
- 1];
1322 /* Use the smaller one if the requsted one isn't available. */
1325 max_single_nop_size
--;
1326 nops
= patt
[max_single_nop_size
- 1];
1329 last
= count
% max_single_nop_size
;
1332 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1333 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1337 nops
= patt
[last
- 1];
1340 /* Use the smaller one plus one-byte NOP if the needed one
1343 nops
= patt
[last
- 1];
1344 memcpy (where
+ offset
, nops
, last
);
1345 where
[offset
+ last
] = *patt
[0];
1348 memcpy (where
+ offset
, nops
, last
);
1353 fits_in_imm7 (offsetT num
)
1355 return (num
& 0x7f) == num
;
1359 fits_in_imm31 (offsetT num
)
1361 return (num
& 0x7fffffff) == num
;
1364 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1365 single NOP instruction LIMIT. */
1368 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1370 const unsigned char *const *patt
= NULL
;
1371 int max_single_nop_size
;
1372 /* Maximum number of NOPs before switching to jump over NOPs. */
1373 int max_number_of_nops
;
1375 switch (fragP
->fr_type
)
1384 /* We need to decide which NOP sequence to use for 32bit and
1385 64bit. When -mtune= is used:
1387 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1388 PROCESSOR_GENERIC32, f32_patt will be used.
1389 2. For the rest, alt_patt will be used.
1391 When -mtune= isn't used, alt_patt will be used if
1392 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1395 When -march= or .arch is used, we can't use anything beyond
1396 cpu_arch_isa_flags. */
1398 if (flag_code
== CODE_16BIT
)
1401 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1402 /* Limit number of NOPs to 2 in 16-bit mode. */
1403 max_number_of_nops
= 2;
1407 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1409 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1410 switch (cpu_arch_tune
)
1412 case PROCESSOR_UNKNOWN
:
1413 /* We use cpu_arch_isa_flags to check if we SHOULD
1414 optimize with nops. */
1415 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1420 case PROCESSOR_PENTIUM4
:
1421 case PROCESSOR_NOCONA
:
1422 case PROCESSOR_CORE
:
1423 case PROCESSOR_CORE2
:
1424 case PROCESSOR_COREI7
:
1425 case PROCESSOR_L1OM
:
1426 case PROCESSOR_K1OM
:
1427 case PROCESSOR_GENERIC64
:
1429 case PROCESSOR_ATHLON
:
1431 case PROCESSOR_AMDFAM10
:
1433 case PROCESSOR_ZNVER
:
1437 case PROCESSOR_I386
:
1438 case PROCESSOR_I486
:
1439 case PROCESSOR_PENTIUM
:
1440 case PROCESSOR_PENTIUMPRO
:
1441 case PROCESSOR_IAMCU
:
1442 case PROCESSOR_GENERIC32
:
1449 switch (fragP
->tc_frag_data
.tune
)
1451 case PROCESSOR_UNKNOWN
:
1452 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1453 PROCESSOR_UNKNOWN. */
1457 case PROCESSOR_I386
:
1458 case PROCESSOR_I486
:
1459 case PROCESSOR_PENTIUM
:
1460 case PROCESSOR_IAMCU
:
1462 case PROCESSOR_ATHLON
:
1464 case PROCESSOR_AMDFAM10
:
1466 case PROCESSOR_ZNVER
:
1468 case PROCESSOR_GENERIC32
:
1469 /* We use cpu_arch_isa_flags to check if we CAN optimize
1471 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1476 case PROCESSOR_PENTIUMPRO
:
1477 case PROCESSOR_PENTIUM4
:
1478 case PROCESSOR_NOCONA
:
1479 case PROCESSOR_CORE
:
1480 case PROCESSOR_CORE2
:
1481 case PROCESSOR_COREI7
:
1482 case PROCESSOR_L1OM
:
1483 case PROCESSOR_K1OM
:
1484 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1489 case PROCESSOR_GENERIC64
:
1495 if (patt
== f32_patt
)
1497 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1498 /* Limit number of NOPs to 2 for older processors. */
1499 max_number_of_nops
= 2;
1503 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1504 /* Limit number of NOPs to 7 for newer processors. */
1505 max_number_of_nops
= 7;
1510 limit
= max_single_nop_size
;
1512 if (fragP
->fr_type
== rs_fill_nop
)
1514 /* Output NOPs for .nop directive. */
1515 if (limit
> max_single_nop_size
)
1517 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1518 _("invalid single nop size: %d "
1519 "(expect within [0, %d])"),
1520 limit
, max_single_nop_size
);
1525 fragP
->fr_var
= count
;
1527 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1529 /* Generate jump over NOPs. */
1530 offsetT disp
= count
- 2;
1531 if (fits_in_imm7 (disp
))
1533 /* Use "jmp disp8" if possible. */
1535 where
[0] = jump_disp8
[0];
1541 unsigned int size_of_jump
;
1543 if (flag_code
== CODE_16BIT
)
1545 where
[0] = jump16_disp32
[0];
1546 where
[1] = jump16_disp32
[1];
1551 where
[0] = jump32_disp32
[0];
1555 count
-= size_of_jump
+ 4;
1556 if (!fits_in_imm31 (count
))
1558 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1559 _("jump over nop padding out of range"));
1563 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1564 where
+= size_of_jump
+ 4;
1568 /* Generate multiple NOPs. */
1569 i386_output_nops (where
, patt
, count
, limit
);
1573 operand_type_all_zero (const union i386_operand_type
*x
)
1575 switch (ARRAY_SIZE(x
->array
))
1586 return !x
->array
[0];
1593 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1595 switch (ARRAY_SIZE(x
->array
))
1613 operand_type_equal (const union i386_operand_type
*x
,
1614 const union i386_operand_type
*y
)
1616 switch (ARRAY_SIZE(x
->array
))
1619 if (x
->array
[2] != y
->array
[2])
1623 if (x
->array
[1] != y
->array
[1])
1627 return x
->array
[0] == y
->array
[0];
1635 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1637 switch (ARRAY_SIZE(x
->array
))
1652 return !x
->array
[0];
1659 cpu_flags_equal (const union i386_cpu_flags
*x
,
1660 const union i386_cpu_flags
*y
)
1662 switch (ARRAY_SIZE(x
->array
))
1665 if (x
->array
[3] != y
->array
[3])
1669 if (x
->array
[2] != y
->array
[2])
1673 if (x
->array
[1] != y
->array
[1])
1677 return x
->array
[0] == y
->array
[0];
1685 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1687 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1688 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1691 static INLINE i386_cpu_flags
1692 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1694 switch (ARRAY_SIZE (x
.array
))
1697 x
.array
[3] &= y
.array
[3];
1700 x
.array
[2] &= y
.array
[2];
1703 x
.array
[1] &= y
.array
[1];
1706 x
.array
[0] &= y
.array
[0];
1714 static INLINE i386_cpu_flags
1715 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1717 switch (ARRAY_SIZE (x
.array
))
1720 x
.array
[3] |= y
.array
[3];
1723 x
.array
[2] |= y
.array
[2];
1726 x
.array
[1] |= y
.array
[1];
1729 x
.array
[0] |= y
.array
[0];
1737 static INLINE i386_cpu_flags
1738 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1740 switch (ARRAY_SIZE (x
.array
))
1743 x
.array
[3] &= ~y
.array
[3];
1746 x
.array
[2] &= ~y
.array
[2];
1749 x
.array
[1] &= ~y
.array
[1];
1752 x
.array
[0] &= ~y
.array
[0];
1760 #define CPU_FLAGS_ARCH_MATCH 0x1
1761 #define CPU_FLAGS_64BIT_MATCH 0x2
1763 #define CPU_FLAGS_PERFECT_MATCH \
1764 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1766 /* Return CPU flags match bits. */
1769 cpu_flags_match (const insn_template
*t
)
1771 i386_cpu_flags x
= t
->cpu_flags
;
1772 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1774 x
.bitfield
.cpu64
= 0;
1775 x
.bitfield
.cpuno64
= 0;
1777 if (cpu_flags_all_zero (&x
))
1779 /* This instruction is available on all archs. */
1780 match
|= CPU_FLAGS_ARCH_MATCH
;
1784 /* This instruction is available only on some archs. */
1785 i386_cpu_flags cpu
= cpu_arch_flags
;
1787 /* AVX512VL is no standalone feature - match it and then strip it. */
1788 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1790 x
.bitfield
.cpuavx512vl
= 0;
1792 cpu
= cpu_flags_and (x
, cpu
);
1793 if (!cpu_flags_all_zero (&cpu
))
1795 if (x
.bitfield
.cpuavx
)
1797 /* We need to check a few extra flags with AVX. */
1798 if (cpu
.bitfield
.cpuavx
1799 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1800 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1801 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1802 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1803 match
|= CPU_FLAGS_ARCH_MATCH
;
1805 else if (x
.bitfield
.cpuavx512f
)
1807 /* We need to check a few extra flags with AVX512F. */
1808 if (cpu
.bitfield
.cpuavx512f
1809 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1810 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1811 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1812 match
|= CPU_FLAGS_ARCH_MATCH
;
1815 match
|= CPU_FLAGS_ARCH_MATCH
;
1821 static INLINE i386_operand_type
1822 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1824 switch (ARRAY_SIZE (x
.array
))
1827 x
.array
[2] &= y
.array
[2];
1830 x
.array
[1] &= y
.array
[1];
1833 x
.array
[0] &= y
.array
[0];
1841 static INLINE i386_operand_type
1842 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1844 switch (ARRAY_SIZE (x
.array
))
1847 x
.array
[2] &= ~y
.array
[2];
1850 x
.array
[1] &= ~y
.array
[1];
1853 x
.array
[0] &= ~y
.array
[0];
1861 static INLINE i386_operand_type
1862 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1864 switch (ARRAY_SIZE (x
.array
))
1867 x
.array
[2] |= y
.array
[2];
1870 x
.array
[1] |= y
.array
[1];
1873 x
.array
[0] |= y
.array
[0];
1881 static INLINE i386_operand_type
1882 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1884 switch (ARRAY_SIZE (x
.array
))
1887 x
.array
[2] ^= y
.array
[2];
1890 x
.array
[1] ^= y
.array
[1];
1893 x
.array
[0] ^= y
.array
[0];
1901 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1902 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1903 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1904 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1905 static const i386_operand_type anydisp
1906 = OPERAND_TYPE_ANYDISP
;
1907 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1908 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1909 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1910 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1911 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1912 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1913 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1914 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1915 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1916 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1917 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1928 operand_type_check (i386_operand_type t
, enum operand_type c
)
1933 return t
.bitfield
.reg
;
1936 return (t
.bitfield
.imm8
1940 || t
.bitfield
.imm32s
1941 || t
.bitfield
.imm64
);
1944 return (t
.bitfield
.disp8
1945 || t
.bitfield
.disp16
1946 || t
.bitfield
.disp32
1947 || t
.bitfield
.disp32s
1948 || t
.bitfield
.disp64
);
1951 return (t
.bitfield
.disp8
1952 || t
.bitfield
.disp16
1953 || t
.bitfield
.disp32
1954 || t
.bitfield
.disp32s
1955 || t
.bitfield
.disp64
1956 || t
.bitfield
.baseindex
);
1965 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1966 between operand GIVEN and opeand WANTED for instruction template T. */
1969 match_operand_size (const insn_template
*t
, unsigned int wanted
,
1972 return !((i
.types
[given
].bitfield
.byte
1973 && !t
->operand_types
[wanted
].bitfield
.byte
)
1974 || (i
.types
[given
].bitfield
.word
1975 && !t
->operand_types
[wanted
].bitfield
.word
)
1976 || (i
.types
[given
].bitfield
.dword
1977 && !t
->operand_types
[wanted
].bitfield
.dword
)
1978 || (i
.types
[given
].bitfield
.qword
1979 && !t
->operand_types
[wanted
].bitfield
.qword
)
1980 || (i
.types
[given
].bitfield
.tbyte
1981 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
1984 /* Return 1 if there is no conflict in SIMD register between operand
1985 GIVEN and opeand WANTED for instruction template T. */
1988 match_simd_size (const insn_template
*t
, unsigned int wanted
,
1991 return !((i
.types
[given
].bitfield
.xmmword
1992 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
1993 || (i
.types
[given
].bitfield
.ymmword
1994 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
1995 || (i
.types
[given
].bitfield
.zmmword
1996 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
1999 /* Return 1 if there is no conflict in any size between operand GIVEN
2000 and opeand WANTED for instruction template T. */
2003 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2006 return (match_operand_size (t
, wanted
, given
)
2007 && !((i
.types
[given
].bitfield
.unspecified
2009 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2010 || (i
.types
[given
].bitfield
.fword
2011 && !t
->operand_types
[wanted
].bitfield
.fword
)
2012 /* For scalar opcode templates to allow register and memory
2013 operands at the same time, some special casing is needed
2014 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2015 down-conversion vpmov*. */
2016 || ((t
->operand_types
[wanted
].bitfield
.regsimd
2017 && !t
->opcode_modifier
.broadcast
2018 && (t
->operand_types
[wanted
].bitfield
.byte
2019 || t
->operand_types
[wanted
].bitfield
.word
2020 || t
->operand_types
[wanted
].bitfield
.dword
2021 || t
->operand_types
[wanted
].bitfield
.qword
))
2022 ? (i
.types
[given
].bitfield
.xmmword
2023 || i
.types
[given
].bitfield
.ymmword
2024 || i
.types
[given
].bitfield
.zmmword
)
2025 : !match_simd_size(t
, wanted
, given
))));
2028 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2029 operands for instruction template T, and it has MATCH_REVERSE set if there
2030 is no size conflict on any operands for the template with operands reversed
2031 (and the template allows for reversing in the first place). */
2033 #define MATCH_STRAIGHT 1
2034 #define MATCH_REVERSE 2
2036 static INLINE
unsigned int
2037 operand_size_match (const insn_template
*t
)
2039 unsigned int j
, match
= MATCH_STRAIGHT
;
2041 /* Don't check jump instructions. */
2042 if (t
->opcode_modifier
.jump
2043 || t
->opcode_modifier
.jumpbyte
2044 || t
->opcode_modifier
.jumpdword
2045 || t
->opcode_modifier
.jumpintersegment
)
2048 /* Check memory and accumulator operand size. */
2049 for (j
= 0; j
< i
.operands
; j
++)
2051 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
2052 && t
->operand_types
[j
].bitfield
.anysize
)
2055 if (t
->operand_types
[j
].bitfield
.reg
2056 && !match_operand_size (t
, j
, j
))
2062 if (t
->operand_types
[j
].bitfield
.regsimd
2063 && !match_simd_size (t
, j
, j
))
2069 if (t
->operand_types
[j
].bitfield
.acc
2070 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2076 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2083 if (!t
->opcode_modifier
.d
)
2087 i
.error
= operand_size_mismatch
;
2091 /* Check reverse. */
2092 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2094 for (j
= 0; j
< i
.operands
; j
++)
2096 unsigned int given
= i
.operands
- j
- 1;
2098 if (t
->operand_types
[j
].bitfield
.reg
2099 && !match_operand_size (t
, j
, given
))
2102 if (t
->operand_types
[j
].bitfield
.regsimd
2103 && !match_simd_size (t
, j
, given
))
2106 if (t
->operand_types
[j
].bitfield
.acc
2107 && (!match_operand_size (t
, j
, given
)
2108 || !match_simd_size (t
, j
, given
)))
2111 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2115 return match
| MATCH_REVERSE
;
2119 operand_type_match (i386_operand_type overlap
,
2120 i386_operand_type given
)
2122 i386_operand_type temp
= overlap
;
2124 temp
.bitfield
.jumpabsolute
= 0;
2125 temp
.bitfield
.unspecified
= 0;
2126 temp
.bitfield
.byte
= 0;
2127 temp
.bitfield
.word
= 0;
2128 temp
.bitfield
.dword
= 0;
2129 temp
.bitfield
.fword
= 0;
2130 temp
.bitfield
.qword
= 0;
2131 temp
.bitfield
.tbyte
= 0;
2132 temp
.bitfield
.xmmword
= 0;
2133 temp
.bitfield
.ymmword
= 0;
2134 temp
.bitfield
.zmmword
= 0;
2135 if (operand_type_all_zero (&temp
))
2138 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2139 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2143 i
.error
= operand_type_mismatch
;
2147 /* If given types g0 and g1 are registers they must be of the same type
2148 unless the expected operand type register overlap is null.
2149 Memory operand size of certain SIMD instructions is also being checked
2153 operand_type_register_match (i386_operand_type g0
,
2154 i386_operand_type t0
,
2155 i386_operand_type g1
,
2156 i386_operand_type t1
)
2158 if (!g0
.bitfield
.reg
2159 && !g0
.bitfield
.regsimd
2160 && (!operand_type_check (g0
, anymem
)
2161 || g0
.bitfield
.unspecified
2162 || !t0
.bitfield
.regsimd
))
2165 if (!g1
.bitfield
.reg
2166 && !g1
.bitfield
.regsimd
2167 && (!operand_type_check (g1
, anymem
)
2168 || g1
.bitfield
.unspecified
2169 || !t1
.bitfield
.regsimd
))
2172 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2173 && g0
.bitfield
.word
== g1
.bitfield
.word
2174 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2175 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2176 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2177 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2178 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2181 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2182 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2183 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2184 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2185 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2186 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2187 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2190 i
.error
= register_type_mismatch
;
2195 static INLINE
unsigned int
2196 register_number (const reg_entry
*r
)
2198 unsigned int nr
= r
->reg_num
;
2200 if (r
->reg_flags
& RegRex
)
2203 if (r
->reg_flags
& RegVRex
)
2209 static INLINE
unsigned int
2210 mode_from_disp_size (i386_operand_type t
)
2212 if (t
.bitfield
.disp8
)
2214 else if (t
.bitfield
.disp16
2215 || t
.bitfield
.disp32
2216 || t
.bitfield
.disp32s
)
2223 fits_in_signed_byte (addressT num
)
2225 return num
+ 0x80 <= 0xff;
2229 fits_in_unsigned_byte (addressT num
)
2235 fits_in_unsigned_word (addressT num
)
2237 return num
<= 0xffff;
2241 fits_in_signed_word (addressT num
)
2243 return num
+ 0x8000 <= 0xffff;
2247 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2252 return num
+ 0x80000000 <= 0xffffffff;
2254 } /* fits_in_signed_long() */
2257 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2262 return num
<= 0xffffffff;
2264 } /* fits_in_unsigned_long() */
2267 fits_in_disp8 (offsetT num
)
2269 int shift
= i
.memshift
;
2275 mask
= (1 << shift
) - 1;
2277 /* Return 0 if NUM isn't properly aligned. */
2281 /* Check if NUM will fit in 8bit after shift. */
2282 return fits_in_signed_byte (num
>> shift
);
2286 fits_in_imm4 (offsetT num
)
2288 return (num
& 0xf) == num
;
2291 static i386_operand_type
2292 smallest_imm_type (offsetT num
)
2294 i386_operand_type t
;
2296 operand_type_set (&t
, 0);
2297 t
.bitfield
.imm64
= 1;
2299 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2301 /* This code is disabled on the 486 because all the Imm1 forms
2302 in the opcode table are slower on the i486. They're the
2303 versions with the implicitly specified single-position
2304 displacement, which has another syntax if you really want to
2306 t
.bitfield
.imm1
= 1;
2307 t
.bitfield
.imm8
= 1;
2308 t
.bitfield
.imm8s
= 1;
2309 t
.bitfield
.imm16
= 1;
2310 t
.bitfield
.imm32
= 1;
2311 t
.bitfield
.imm32s
= 1;
2313 else if (fits_in_signed_byte (num
))
2315 t
.bitfield
.imm8
= 1;
2316 t
.bitfield
.imm8s
= 1;
2317 t
.bitfield
.imm16
= 1;
2318 t
.bitfield
.imm32
= 1;
2319 t
.bitfield
.imm32s
= 1;
2321 else if (fits_in_unsigned_byte (num
))
2323 t
.bitfield
.imm8
= 1;
2324 t
.bitfield
.imm16
= 1;
2325 t
.bitfield
.imm32
= 1;
2326 t
.bitfield
.imm32s
= 1;
2328 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2330 t
.bitfield
.imm16
= 1;
2331 t
.bitfield
.imm32
= 1;
2332 t
.bitfield
.imm32s
= 1;
2334 else if (fits_in_signed_long (num
))
2336 t
.bitfield
.imm32
= 1;
2337 t
.bitfield
.imm32s
= 1;
2339 else if (fits_in_unsigned_long (num
))
2340 t
.bitfield
.imm32
= 1;
2346 offset_in_range (offsetT val
, int size
)
2352 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2353 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2354 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2356 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2362 /* If BFD64, sign extend val for 32bit address mode. */
2363 if (flag_code
!= CODE_64BIT
2364 || i
.prefix
[ADDR_PREFIX
])
2365 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2366 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2369 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2371 char buf1
[40], buf2
[40];
2373 sprint_value (buf1
, val
);
2374 sprint_value (buf2
, val
& mask
);
2375 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2390 a. PREFIX_EXIST if attempting to add a prefix where one from the
2391 same class already exists.
2392 b. PREFIX_LOCK if lock prefix is added.
2393 c. PREFIX_REP if rep/repne prefix is added.
2394 d. PREFIX_DS if ds prefix is added.
2395 e. PREFIX_OTHER if other prefix is added.
2398 static enum PREFIX_GROUP
2399 add_prefix (unsigned int prefix
)
2401 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2404 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2405 && flag_code
== CODE_64BIT
)
2407 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2408 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2409 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2410 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2421 case DS_PREFIX_OPCODE
:
2424 case CS_PREFIX_OPCODE
:
2425 case ES_PREFIX_OPCODE
:
2426 case FS_PREFIX_OPCODE
:
2427 case GS_PREFIX_OPCODE
:
2428 case SS_PREFIX_OPCODE
:
2432 case REPNE_PREFIX_OPCODE
:
2433 case REPE_PREFIX_OPCODE
:
2438 case LOCK_PREFIX_OPCODE
:
2447 case ADDR_PREFIX_OPCODE
:
2451 case DATA_PREFIX_OPCODE
:
2455 if (i
.prefix
[q
] != 0)
2463 i
.prefix
[q
] |= prefix
;
2466 as_bad (_("same type of prefix used twice"));
2472 update_code_flag (int value
, int check
)
2474 PRINTF_LIKE ((*as_error
));
2476 flag_code
= (enum flag_code
) value
;
2477 if (flag_code
== CODE_64BIT
)
2479 cpu_arch_flags
.bitfield
.cpu64
= 1;
2480 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2484 cpu_arch_flags
.bitfield
.cpu64
= 0;
2485 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2487 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2490 as_error
= as_fatal
;
2493 (*as_error
) (_("64bit mode not supported on `%s'."),
2494 cpu_arch_name
? cpu_arch_name
: default_arch
);
2496 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2499 as_error
= as_fatal
;
2502 (*as_error
) (_("32bit mode not supported on `%s'."),
2503 cpu_arch_name
? cpu_arch_name
: default_arch
);
2505 stackop_size
= '\0';
2509 set_code_flag (int value
)
2511 update_code_flag (value
, 0);
2515 set_16bit_gcc_code_flag (int new_code_flag
)
2517 flag_code
= (enum flag_code
) new_code_flag
;
2518 if (flag_code
!= CODE_16BIT
)
2520 cpu_arch_flags
.bitfield
.cpu64
= 0;
2521 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2522 stackop_size
= LONG_MNEM_SUFFIX
;
2526 set_intel_syntax (int syntax_flag
)
2528 /* Find out if register prefixing is specified. */
2529 int ask_naked_reg
= 0;
2532 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2535 int e
= get_symbol_name (&string
);
2537 if (strcmp (string
, "prefix") == 0)
2539 else if (strcmp (string
, "noprefix") == 0)
2542 as_bad (_("bad argument to syntax directive."));
2543 (void) restore_line_pointer (e
);
2545 demand_empty_rest_of_line ();
2547 intel_syntax
= syntax_flag
;
2549 if (ask_naked_reg
== 0)
2550 allow_naked_reg
= (intel_syntax
2551 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2553 allow_naked_reg
= (ask_naked_reg
< 0);
2555 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2557 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2558 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2559 register_prefix
= allow_naked_reg
? "" : "%";
2563 set_intel_mnemonic (int mnemonic_flag
)
2565 intel_mnemonic
= mnemonic_flag
;
2569 set_allow_index_reg (int flag
)
2571 allow_index_reg
= flag
;
2575 set_check (int what
)
2577 enum check_kind
*kind
;
2582 kind
= &operand_check
;
2593 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2596 int e
= get_symbol_name (&string
);
2598 if (strcmp (string
, "none") == 0)
2600 else if (strcmp (string
, "warning") == 0)
2601 *kind
= check_warning
;
2602 else if (strcmp (string
, "error") == 0)
2603 *kind
= check_error
;
2605 as_bad (_("bad argument to %s_check directive."), str
);
2606 (void) restore_line_pointer (e
);
2609 as_bad (_("missing argument for %s_check directive"), str
);
2611 demand_empty_rest_of_line ();
2615 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2616 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2619 static const char *arch
;
2621 /* Intel LIOM is only supported on ELF. */
2627 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2628 use default_arch. */
2629 arch
= cpu_arch_name
;
2631 arch
= default_arch
;
2634 /* If we are targeting Intel MCU, we must enable it. */
2635 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2636 || new_flag
.bitfield
.cpuiamcu
)
2639 /* If we are targeting Intel L1OM, we must enable it. */
2640 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2641 || new_flag
.bitfield
.cpul1om
)
2644 /* If we are targeting Intel K1OM, we must enable it. */
2645 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2646 || new_flag
.bitfield
.cpuk1om
)
2649 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2654 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2658 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2661 int e
= get_symbol_name (&string
);
2663 i386_cpu_flags flags
;
2665 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2667 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2669 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2673 cpu_arch_name
= cpu_arch
[j
].name
;
2674 cpu_sub_arch_name
= NULL
;
2675 cpu_arch_flags
= cpu_arch
[j
].flags
;
2676 if (flag_code
== CODE_64BIT
)
2678 cpu_arch_flags
.bitfield
.cpu64
= 1;
2679 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2683 cpu_arch_flags
.bitfield
.cpu64
= 0;
2684 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2686 cpu_arch_isa
= cpu_arch
[j
].type
;
2687 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2688 if (!cpu_arch_tune_set
)
2690 cpu_arch_tune
= cpu_arch_isa
;
2691 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2696 flags
= cpu_flags_or (cpu_arch_flags
,
2699 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2701 if (cpu_sub_arch_name
)
2703 char *name
= cpu_sub_arch_name
;
2704 cpu_sub_arch_name
= concat (name
,
2706 (const char *) NULL
);
2710 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2711 cpu_arch_flags
= flags
;
2712 cpu_arch_isa_flags
= flags
;
2716 = cpu_flags_or (cpu_arch_isa_flags
,
2718 (void) restore_line_pointer (e
);
2719 demand_empty_rest_of_line ();
2724 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2726 /* Disable an ISA extension. */
2727 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2728 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2730 flags
= cpu_flags_and_not (cpu_arch_flags
,
2731 cpu_noarch
[j
].flags
);
2732 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2734 if (cpu_sub_arch_name
)
2736 char *name
= cpu_sub_arch_name
;
2737 cpu_sub_arch_name
= concat (name
, string
,
2738 (const char *) NULL
);
2742 cpu_sub_arch_name
= xstrdup (string
);
2743 cpu_arch_flags
= flags
;
2744 cpu_arch_isa_flags
= flags
;
2746 (void) restore_line_pointer (e
);
2747 demand_empty_rest_of_line ();
2751 j
= ARRAY_SIZE (cpu_arch
);
2754 if (j
>= ARRAY_SIZE (cpu_arch
))
2755 as_bad (_("no such architecture: `%s'"), string
);
2757 *input_line_pointer
= e
;
2760 as_bad (_("missing cpu architecture"));
2762 no_cond_jump_promotion
= 0;
2763 if (*input_line_pointer
== ','
2764 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2769 ++input_line_pointer
;
2770 e
= get_symbol_name (&string
);
2772 if (strcmp (string
, "nojumps") == 0)
2773 no_cond_jump_promotion
= 1;
2774 else if (strcmp (string
, "jumps") == 0)
2777 as_bad (_("no such architecture modifier: `%s'"), string
);
2779 (void) restore_line_pointer (e
);
2782 demand_empty_rest_of_line ();
2785 enum bfd_architecture
2788 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2790 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2791 || flag_code
!= CODE_64BIT
)
2792 as_fatal (_("Intel L1OM is 64bit ELF only"));
2793 return bfd_arch_l1om
;
2795 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2797 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2798 || flag_code
!= CODE_64BIT
)
2799 as_fatal (_("Intel K1OM is 64bit ELF only"));
2800 return bfd_arch_k1om
;
2802 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2804 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2805 || flag_code
== CODE_64BIT
)
2806 as_fatal (_("Intel MCU is 32bit ELF only"));
2807 return bfd_arch_iamcu
;
2810 return bfd_arch_i386
;
2816 if (!strncmp (default_arch
, "x86_64", 6))
2818 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2820 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2821 || default_arch
[6] != '\0')
2822 as_fatal (_("Intel L1OM is 64bit ELF only"));
2823 return bfd_mach_l1om
;
2825 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2827 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2828 || default_arch
[6] != '\0')
2829 as_fatal (_("Intel K1OM is 64bit ELF only"));
2830 return bfd_mach_k1om
;
2832 else if (default_arch
[6] == '\0')
2833 return bfd_mach_x86_64
;
2835 return bfd_mach_x64_32
;
2837 else if (!strcmp (default_arch
, "i386")
2838 || !strcmp (default_arch
, "iamcu"))
2840 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2842 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2843 as_fatal (_("Intel MCU is 32bit ELF only"));
2844 return bfd_mach_i386_iamcu
;
2847 return bfd_mach_i386_i386
;
2850 as_fatal (_("unknown architecture"));
2856 const char *hash_err
;
2858 /* Support pseudo prefixes like {disp32}. */
2859 lex_type
['{'] = LEX_BEGIN_NAME
;
2861 /* Initialize op_hash hash table. */
2862 op_hash
= hash_new ();
2865 const insn_template
*optab
;
2866 templates
*core_optab
;
2868 /* Setup for loop. */
2870 core_optab
= XNEW (templates
);
2871 core_optab
->start
= optab
;
2876 if (optab
->name
== NULL
2877 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2879 /* different name --> ship out current template list;
2880 add to hash table; & begin anew. */
2881 core_optab
->end
= optab
;
2882 hash_err
= hash_insert (op_hash
,
2884 (void *) core_optab
);
2887 as_fatal (_("can't hash %s: %s"),
2891 if (optab
->name
== NULL
)
2893 core_optab
= XNEW (templates
);
2894 core_optab
->start
= optab
;
2899 /* Initialize reg_hash hash table. */
2900 reg_hash
= hash_new ();
2902 const reg_entry
*regtab
;
2903 unsigned int regtab_size
= i386_regtab_size
;
2905 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2907 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2909 as_fatal (_("can't hash %s: %s"),
2915 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2920 for (c
= 0; c
< 256; c
++)
2925 mnemonic_chars
[c
] = c
;
2926 register_chars
[c
] = c
;
2927 operand_chars
[c
] = c
;
2929 else if (ISLOWER (c
))
2931 mnemonic_chars
[c
] = c
;
2932 register_chars
[c
] = c
;
2933 operand_chars
[c
] = c
;
2935 else if (ISUPPER (c
))
2937 mnemonic_chars
[c
] = TOLOWER (c
);
2938 register_chars
[c
] = mnemonic_chars
[c
];
2939 operand_chars
[c
] = c
;
2941 else if (c
== '{' || c
== '}')
2943 mnemonic_chars
[c
] = c
;
2944 operand_chars
[c
] = c
;
2947 if (ISALPHA (c
) || ISDIGIT (c
))
2948 identifier_chars
[c
] = c
;
2951 identifier_chars
[c
] = c
;
2952 operand_chars
[c
] = c
;
2957 identifier_chars
['@'] = '@';
2960 identifier_chars
['?'] = '?';
2961 operand_chars
['?'] = '?';
2963 digit_chars
['-'] = '-';
2964 mnemonic_chars
['_'] = '_';
2965 mnemonic_chars
['-'] = '-';
2966 mnemonic_chars
['.'] = '.';
2967 identifier_chars
['_'] = '_';
2968 identifier_chars
['.'] = '.';
2970 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2971 operand_chars
[(unsigned char) *p
] = *p
;
2974 if (flag_code
== CODE_64BIT
)
2976 #if defined (OBJ_COFF) && defined (TE_PE)
2977 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2980 x86_dwarf2_return_column
= 16;
2982 x86_cie_data_alignment
= -8;
2986 x86_dwarf2_return_column
= 8;
2987 x86_cie_data_alignment
= -4;
2992 i386_print_statistics (FILE *file
)
2994 hash_print_statistics (file
, "i386 opcode", op_hash
);
2995 hash_print_statistics (file
, "i386 register", reg_hash
);
3000 /* Debugging routines for md_assemble. */
3001 static void pte (insn_template
*);
3002 static void pt (i386_operand_type
);
3003 static void pe (expressionS
*);
3004 static void ps (symbolS
*);
3007 pi (const char *line
, i386_insn
*x
)
3011 fprintf (stdout
, "%s: template ", line
);
3013 fprintf (stdout
, " address: base %s index %s scale %x\n",
3014 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3015 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3016 x
->log2_scale_factor
);
3017 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3018 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3019 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3020 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3021 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3022 (x
->rex
& REX_W
) != 0,
3023 (x
->rex
& REX_R
) != 0,
3024 (x
->rex
& REX_X
) != 0,
3025 (x
->rex
& REX_B
) != 0);
3026 for (j
= 0; j
< x
->operands
; j
++)
3028 fprintf (stdout
, " #%d: ", j
+ 1);
3030 fprintf (stdout
, "\n");
3031 if (x
->types
[j
].bitfield
.reg
3032 || x
->types
[j
].bitfield
.regmmx
3033 || x
->types
[j
].bitfield
.regsimd
3034 || x
->types
[j
].bitfield
.sreg
3035 || x
->types
[j
].bitfield
.control
3036 || x
->types
[j
].bitfield
.debug
3037 || x
->types
[j
].bitfield
.test
)
3038 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3039 if (operand_type_check (x
->types
[j
], imm
))
3041 if (operand_type_check (x
->types
[j
], disp
))
3042 pe (x
->op
[j
].disps
);
3047 pte (insn_template
*t
)
3050 fprintf (stdout
, " %d operands ", t
->operands
);
3051 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3052 if (t
->extension_opcode
!= None
)
3053 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3054 if (t
->opcode_modifier
.d
)
3055 fprintf (stdout
, "D");
3056 if (t
->opcode_modifier
.w
)
3057 fprintf (stdout
, "W");
3058 fprintf (stdout
, "\n");
3059 for (j
= 0; j
< t
->operands
; j
++)
3061 fprintf (stdout
, " #%d type ", j
+ 1);
3062 pt (t
->operand_types
[j
]);
3063 fprintf (stdout
, "\n");
3070 fprintf (stdout
, " operation %d\n", e
->X_op
);
3071 fprintf (stdout
, " add_number %ld (%lx)\n",
3072 (long) e
->X_add_number
, (long) e
->X_add_number
);
3073 if (e
->X_add_symbol
)
3075 fprintf (stdout
, " add_symbol ");
3076 ps (e
->X_add_symbol
);
3077 fprintf (stdout
, "\n");
3081 fprintf (stdout
, " op_symbol ");
3082 ps (e
->X_op_symbol
);
3083 fprintf (stdout
, "\n");
3090 fprintf (stdout
, "%s type %s%s",
3092 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3093 segment_name (S_GET_SEGMENT (s
)));
3096 static struct type_name
3098 i386_operand_type mask
;
3101 const type_names
[] =
3103 { OPERAND_TYPE_REG8
, "r8" },
3104 { OPERAND_TYPE_REG16
, "r16" },
3105 { OPERAND_TYPE_REG32
, "r32" },
3106 { OPERAND_TYPE_REG64
, "r64" },
3107 { OPERAND_TYPE_ACC8
, "acc8" },
3108 { OPERAND_TYPE_ACC16
, "acc16" },
3109 { OPERAND_TYPE_ACC32
, "acc32" },
3110 { OPERAND_TYPE_ACC64
, "acc64" },
3111 { OPERAND_TYPE_IMM8
, "i8" },
3112 { OPERAND_TYPE_IMM8
, "i8s" },
3113 { OPERAND_TYPE_IMM16
, "i16" },
3114 { OPERAND_TYPE_IMM32
, "i32" },
3115 { OPERAND_TYPE_IMM32S
, "i32s" },
3116 { OPERAND_TYPE_IMM64
, "i64" },
3117 { OPERAND_TYPE_IMM1
, "i1" },
3118 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3119 { OPERAND_TYPE_DISP8
, "d8" },
3120 { OPERAND_TYPE_DISP16
, "d16" },
3121 { OPERAND_TYPE_DISP32
, "d32" },
3122 { OPERAND_TYPE_DISP32S
, "d32s" },
3123 { OPERAND_TYPE_DISP64
, "d64" },
3124 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3125 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3126 { OPERAND_TYPE_CONTROL
, "control reg" },
3127 { OPERAND_TYPE_TEST
, "test reg" },
3128 { OPERAND_TYPE_DEBUG
, "debug reg" },
3129 { OPERAND_TYPE_FLOATREG
, "FReg" },
3130 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3131 { OPERAND_TYPE_SREG
, "SReg" },
3132 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3133 { OPERAND_TYPE_REGMMX
, "rMMX" },
3134 { OPERAND_TYPE_REGXMM
, "rXMM" },
3135 { OPERAND_TYPE_REGYMM
, "rYMM" },
3136 { OPERAND_TYPE_REGZMM
, "rZMM" },
3137 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3138 { OPERAND_TYPE_ESSEG
, "es" },
3142 pt (i386_operand_type t
)
3145 i386_operand_type a
;
3147 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3149 a
= operand_type_and (t
, type_names
[j
].mask
);
3150 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3151 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3156 #endif /* DEBUG386 */
3158 static bfd_reloc_code_real_type
3159 reloc (unsigned int size
,
3162 bfd_reloc_code_real_type other
)
3164 if (other
!= NO_RELOC
)
3166 reloc_howto_type
*rel
;
3171 case BFD_RELOC_X86_64_GOT32
:
3172 return BFD_RELOC_X86_64_GOT64
;
3174 case BFD_RELOC_X86_64_GOTPLT64
:
3175 return BFD_RELOC_X86_64_GOTPLT64
;
3177 case BFD_RELOC_X86_64_PLTOFF64
:
3178 return BFD_RELOC_X86_64_PLTOFF64
;
3180 case BFD_RELOC_X86_64_GOTPC32
:
3181 other
= BFD_RELOC_X86_64_GOTPC64
;
3183 case BFD_RELOC_X86_64_GOTPCREL
:
3184 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3186 case BFD_RELOC_X86_64_TPOFF32
:
3187 other
= BFD_RELOC_X86_64_TPOFF64
;
3189 case BFD_RELOC_X86_64_DTPOFF32
:
3190 other
= BFD_RELOC_X86_64_DTPOFF64
;
3196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3197 if (other
== BFD_RELOC_SIZE32
)
3200 other
= BFD_RELOC_SIZE64
;
3203 as_bad (_("there are no pc-relative size relocations"));
3209 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3210 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3213 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3215 as_bad (_("unknown relocation (%u)"), other
);
3216 else if (size
!= bfd_get_reloc_size (rel
))
3217 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3218 bfd_get_reloc_size (rel
),
3220 else if (pcrel
&& !rel
->pc_relative
)
3221 as_bad (_("non-pc-relative relocation for pc-relative field"));
3222 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3224 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3226 as_bad (_("relocated field and relocation type differ in signedness"));
3235 as_bad (_("there are no unsigned pc-relative relocations"));
3238 case 1: return BFD_RELOC_8_PCREL
;
3239 case 2: return BFD_RELOC_16_PCREL
;
3240 case 4: return BFD_RELOC_32_PCREL
;
3241 case 8: return BFD_RELOC_64_PCREL
;
3243 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3250 case 4: return BFD_RELOC_X86_64_32S
;
3255 case 1: return BFD_RELOC_8
;
3256 case 2: return BFD_RELOC_16
;
3257 case 4: return BFD_RELOC_32
;
3258 case 8: return BFD_RELOC_64
;
3260 as_bad (_("cannot do %s %u byte relocation"),
3261 sign
> 0 ? "signed" : "unsigned", size
);
3267 /* Here we decide which fixups can be adjusted to make them relative to
3268 the beginning of the section instead of the symbol. Basically we need
3269 to make sure that the dynamic relocations are done correctly, so in
3270 some cases we force the original symbol to be used. */
3273 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3275 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3279 /* Don't adjust pc-relative references to merge sections in 64-bit
3281 if (use_rela_relocations
3282 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3286 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3287 and changed later by validate_fix. */
3288 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3289 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3292 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3293 for size relocations. */
3294 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3295 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3296 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3297 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3298 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3299 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3300 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3301 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3302 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3303 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3304 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3305 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3306 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3307 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3308 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3309 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3310 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3311 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3312 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3313 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3314 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3315 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3316 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3317 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3318 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3319 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3320 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3321 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3322 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3323 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3324 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3325 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3326 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3333 intel_float_operand (const char *mnemonic
)
3335 /* Note that the value returned is meaningful only for opcodes with (memory)
3336 operands, hence the code here is free to improperly handle opcodes that
3337 have no operands (for better performance and smaller code). */
3339 if (mnemonic
[0] != 'f')
3340 return 0; /* non-math */
3342 switch (mnemonic
[1])
3344 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3345 the fs segment override prefix not currently handled because no
3346 call path can make opcodes without operands get here */
3348 return 2 /* integer op */;
3350 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3351 return 3; /* fldcw/fldenv */
3354 if (mnemonic
[2] != 'o' /* fnop */)
3355 return 3; /* non-waiting control op */
3358 if (mnemonic
[2] == 's')
3359 return 3; /* frstor/frstpm */
3362 if (mnemonic
[2] == 'a')
3363 return 3; /* fsave */
3364 if (mnemonic
[2] == 't')
3366 switch (mnemonic
[3])
3368 case 'c': /* fstcw */
3369 case 'd': /* fstdw */
3370 case 'e': /* fstenv */
3371 case 's': /* fsts[gw] */
3377 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3378 return 0; /* fxsave/fxrstor are not really math ops */
3385 /* Build the VEX prefix. */
3388 build_vex_prefix (const insn_template
*t
)
3390 unsigned int register_specifier
;
3391 unsigned int implied_prefix
;
3392 unsigned int vector_length
;
3395 /* Check register specifier. */
3396 if (i
.vex
.register_specifier
)
3398 register_specifier
=
3399 ~register_number (i
.vex
.register_specifier
) & 0xf;
3400 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3403 register_specifier
= 0xf;
3405 /* Use 2-byte VEX prefix by swapping destination and source operand
3406 if there are more than 1 register operand. */
3407 if (i
.reg_operands
> 1
3408 && i
.vec_encoding
!= vex_encoding_vex3
3409 && i
.dir_encoding
== dir_encoding_default
3410 && i
.operands
== i
.reg_operands
3411 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3412 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3413 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3416 unsigned int xchg
= i
.operands
- 1;
3417 union i386_op temp_op
;
3418 i386_operand_type temp_type
;
3420 temp_type
= i
.types
[xchg
];
3421 i
.types
[xchg
] = i
.types
[0];
3422 i
.types
[0] = temp_type
;
3423 temp_op
= i
.op
[xchg
];
3424 i
.op
[xchg
] = i
.op
[0];
3427 gas_assert (i
.rm
.mode
== 3);
3431 i
.rm
.regmem
= i
.rm
.reg
;
3434 if (i
.tm
.opcode_modifier
.d
)
3435 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3436 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3437 else /* Use the next insn. */
3441 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3442 are no memory operands and at least 3 register ones. */
3443 if (i
.reg_operands
>= 3
3444 && i
.vec_encoding
!= vex_encoding_vex3
3445 && i
.reg_operands
== i
.operands
- i
.imm_operands
3446 && i
.tm
.opcode_modifier
.vex
3447 && i
.tm
.opcode_modifier
.commutative
3448 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3450 && i
.vex
.register_specifier
3451 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3453 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3454 union i386_op temp_op
;
3455 i386_operand_type temp_type
;
3457 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3458 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3459 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3460 &i
.types
[i
.operands
- 3]));
3461 gas_assert (i
.rm
.mode
== 3);
3463 temp_type
= i
.types
[xchg
];
3464 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3465 i
.types
[xchg
+ 1] = temp_type
;
3466 temp_op
= i
.op
[xchg
];
3467 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3468 i
.op
[xchg
+ 1] = temp_op
;
3471 xchg
= i
.rm
.regmem
| 8;
3472 i
.rm
.regmem
= ~register_specifier
& 0xf;
3473 gas_assert (!(i
.rm
.regmem
& 8));
3474 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3475 register_specifier
= ~xchg
& 0xf;
3478 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3479 vector_length
= avxscalar
;
3480 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3486 /* Determine vector length from the last multi-length vector
3489 for (op
= t
->operands
; op
--;)
3490 if (t
->operand_types
[op
].bitfield
.xmmword
3491 && t
->operand_types
[op
].bitfield
.ymmword
3492 && i
.types
[op
].bitfield
.ymmword
)
3499 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3504 case DATA_PREFIX_OPCODE
:
3507 case REPE_PREFIX_OPCODE
:
3510 case REPNE_PREFIX_OPCODE
:
3517 /* Check the REX.W bit and VEXW. */
3518 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3519 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3520 else if (i
.tm
.opcode_modifier
.vexw
)
3521 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3523 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3525 /* Use 2-byte VEX prefix if possible. */
3527 && i
.vec_encoding
!= vex_encoding_vex3
3528 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3529 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3531 /* 2-byte VEX prefix. */
3535 i
.vex
.bytes
[0] = 0xc5;
3537 /* Check the REX.R bit. */
3538 r
= (i
.rex
& REX_R
) ? 0 : 1;
3539 i
.vex
.bytes
[1] = (r
<< 7
3540 | register_specifier
<< 3
3541 | vector_length
<< 2
3546 /* 3-byte VEX prefix. */
3551 switch (i
.tm
.opcode_modifier
.vexopcode
)
3555 i
.vex
.bytes
[0] = 0xc4;
3559 i
.vex
.bytes
[0] = 0xc4;
3563 i
.vex
.bytes
[0] = 0xc4;
3567 i
.vex
.bytes
[0] = 0x8f;
3571 i
.vex
.bytes
[0] = 0x8f;
3575 i
.vex
.bytes
[0] = 0x8f;
3581 /* The high 3 bits of the second VEX byte are 1's compliment
3582 of RXB bits from REX. */
3583 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3585 i
.vex
.bytes
[2] = (w
<< 7
3586 | register_specifier
<< 3
3587 | vector_length
<< 2
3592 static INLINE bfd_boolean
3593 is_evex_encoding (const insn_template
*t
)
3595 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3596 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3597 || t
->opcode_modifier
.sae
;
3600 static INLINE bfd_boolean
3601 is_any_vex_encoding (const insn_template
*t
)
3603 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3604 || is_evex_encoding (t
);
3607 /* Build the EVEX prefix. */
3610 build_evex_prefix (void)
3612 unsigned int register_specifier
;
3613 unsigned int implied_prefix
;
3615 rex_byte vrex_used
= 0;
3617 /* Check register specifier. */
3618 if (i
.vex
.register_specifier
)
3620 gas_assert ((i
.vrex
& REX_X
) == 0);
3622 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3623 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3624 register_specifier
+= 8;
3625 /* The upper 16 registers are encoded in the fourth byte of the
3627 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3628 i
.vex
.bytes
[3] = 0x8;
3629 register_specifier
= ~register_specifier
& 0xf;
3633 register_specifier
= 0xf;
3635 /* Encode upper 16 vector index register in the fourth byte of
3637 if (!(i
.vrex
& REX_X
))
3638 i
.vex
.bytes
[3] = 0x8;
3643 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3648 case DATA_PREFIX_OPCODE
:
3651 case REPE_PREFIX_OPCODE
:
3654 case REPNE_PREFIX_OPCODE
:
3661 /* 4 byte EVEX prefix. */
3663 i
.vex
.bytes
[0] = 0x62;
3666 switch (i
.tm
.opcode_modifier
.vexopcode
)
3682 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3684 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3686 /* The fifth bit of the second EVEX byte is 1's compliment of the
3687 REX_R bit in VREX. */
3688 if (!(i
.vrex
& REX_R
))
3689 i
.vex
.bytes
[1] |= 0x10;
3693 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3695 /* When all operands are registers, the REX_X bit in REX is not
3696 used. We reuse it to encode the upper 16 registers, which is
3697 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3698 as 1's compliment. */
3699 if ((i
.vrex
& REX_B
))
3702 i
.vex
.bytes
[1] &= ~0x40;
3706 /* EVEX instructions shouldn't need the REX prefix. */
3707 i
.vrex
&= ~vrex_used
;
3708 gas_assert (i
.vrex
== 0);
3710 /* Check the REX.W bit and VEXW. */
3711 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3712 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3713 else if (i
.tm
.opcode_modifier
.vexw
)
3714 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3716 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3718 /* Encode the U bit. */
3719 implied_prefix
|= 0x4;
3721 /* The third byte of the EVEX prefix. */
3722 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3724 /* The fourth byte of the EVEX prefix. */
3725 /* The zeroing-masking bit. */
3726 if (i
.mask
&& i
.mask
->zeroing
)
3727 i
.vex
.bytes
[3] |= 0x80;
3729 /* Don't always set the broadcast bit if there is no RC. */
3732 /* Encode the vector length. */
3733 unsigned int vec_length
;
3735 if (!i
.tm
.opcode_modifier
.evex
3736 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3740 /* Determine vector length from the last multi-length vector
3743 for (op
= i
.operands
; op
--;)
3744 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3745 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3746 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3748 if (i
.types
[op
].bitfield
.zmmword
)
3750 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3753 else if (i
.types
[op
].bitfield
.ymmword
)
3755 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3758 else if (i
.types
[op
].bitfield
.xmmword
)
3760 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3763 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3765 switch (i
.broadcast
->bytes
)
3768 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3771 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3774 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3783 if (op
>= MAX_OPERANDS
)
3787 switch (i
.tm
.opcode_modifier
.evex
)
3789 case EVEXLIG
: /* LL' is ignored */
3790 vec_length
= evexlig
<< 5;
3793 vec_length
= 0 << 5;
3796 vec_length
= 1 << 5;
3799 vec_length
= 2 << 5;
3805 i
.vex
.bytes
[3] |= vec_length
;
3806 /* Encode the broadcast bit. */
3808 i
.vex
.bytes
[3] |= 0x10;
3812 if (i
.rounding
->type
!= saeonly
)
3813 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3815 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3818 if (i
.mask
&& i
.mask
->mask
)
3819 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3823 process_immext (void)
3827 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3830 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3831 with an opcode suffix which is coded in the same place as an
3832 8-bit immediate field would be.
3833 Here we check those operands and remove them afterwards. */
3836 for (x
= 0; x
< i
.operands
; x
++)
3837 if (register_number (i
.op
[x
].regs
) != x
)
3838 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3839 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3845 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3847 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3848 suffix which is coded in the same place as an 8-bit immediate
3850 Here we check those operands and remove them afterwards. */
3853 if (i
.operands
!= 3)
3856 for (x
= 0; x
< 2; x
++)
3857 if (register_number (i
.op
[x
].regs
) != x
)
3858 goto bad_register_operand
;
3860 /* Check for third operand for mwaitx/monitorx insn. */
3861 if (register_number (i
.op
[x
].regs
)
3862 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3864 bad_register_operand
:
3865 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3866 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3873 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3874 which is coded in the same place as an 8-bit immediate field
3875 would be. Here we fake an 8-bit immediate operand from the
3876 opcode suffix stored in tm.extension_opcode.
3878 AVX instructions also use this encoding, for some of
3879 3 argument instructions. */
3881 gas_assert (i
.imm_operands
<= 1
3883 || (is_any_vex_encoding (&i
.tm
)
3884 && i
.operands
<= 4)));
3886 exp
= &im_expressions
[i
.imm_operands
++];
3887 i
.op
[i
.operands
].imms
= exp
;
3888 i
.types
[i
.operands
] = imm8
;
3890 exp
->X_op
= O_constant
;
3891 exp
->X_add_number
= i
.tm
.extension_opcode
;
3892 i
.tm
.extension_opcode
= None
;
3899 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3904 as_bad (_("invalid instruction `%s' after `%s'"),
3905 i
.tm
.name
, i
.hle_prefix
);
3908 if (i
.prefix
[LOCK_PREFIX
])
3910 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3914 case HLEPrefixRelease
:
3915 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3917 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3921 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3923 as_bad (_("memory destination needed for instruction `%s'"
3924 " after `xrelease'"), i
.tm
.name
);
3931 /* Try the shortest encoding by shortening operand size. */
3934 optimize_encoding (void)
3938 if (optimize_for_space
3939 && i
.reg_operands
== 1
3940 && i
.imm_operands
== 1
3941 && !i
.types
[1].bitfield
.byte
3942 && i
.op
[0].imms
->X_op
== O_constant
3943 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3944 && ((i
.tm
.base_opcode
== 0xa8
3945 && i
.tm
.extension_opcode
== None
)
3946 || (i
.tm
.base_opcode
== 0xf6
3947 && i
.tm
.extension_opcode
== 0x0)))
3950 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3952 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3953 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3955 i
.types
[1].bitfield
.byte
= 1;
3956 /* Ignore the suffix. */
3958 if (base_regnum
>= 4
3959 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3961 /* Handle SP, BP, SI and DI registers. */
3962 if (i
.types
[1].bitfield
.word
)
3964 else if (i
.types
[1].bitfield
.dword
)
3972 else if (flag_code
== CODE_64BIT
3973 && ((i
.types
[1].bitfield
.qword
3974 && i
.reg_operands
== 1
3975 && i
.imm_operands
== 1
3976 && i
.op
[0].imms
->X_op
== O_constant
3977 && ((i
.tm
.base_opcode
== 0xb0
3978 && i
.tm
.extension_opcode
== None
3979 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3980 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3981 && (((i
.tm
.base_opcode
== 0x24
3982 || i
.tm
.base_opcode
== 0xa8)
3983 && i
.tm
.extension_opcode
== None
)
3984 || (i
.tm
.base_opcode
== 0x80
3985 && i
.tm
.extension_opcode
== 0x4)
3986 || ((i
.tm
.base_opcode
== 0xf6
3987 || i
.tm
.base_opcode
== 0xc6)
3988 && i
.tm
.extension_opcode
== 0x0)))
3989 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3990 && i
.tm
.base_opcode
== 0x83
3991 && i
.tm
.extension_opcode
== 0x4)))
3992 || (i
.types
[0].bitfield
.qword
3993 && ((i
.reg_operands
== 2
3994 && i
.op
[0].regs
== i
.op
[1].regs
3995 && ((i
.tm
.base_opcode
== 0x30
3996 || i
.tm
.base_opcode
== 0x28)
3997 && i
.tm
.extension_opcode
== None
))
3998 || (i
.reg_operands
== 1
4000 && i
.tm
.base_opcode
== 0x30
4001 && i
.tm
.extension_opcode
== None
)))))
4004 andq $imm31, %r64 -> andl $imm31, %r32
4005 andq $imm7, %r64 -> andl $imm7, %r32
4006 testq $imm31, %r64 -> testl $imm31, %r32
4007 xorq %r64, %r64 -> xorl %r32, %r32
4008 subq %r64, %r64 -> subl %r32, %r32
4009 movq $imm31, %r64 -> movl $imm31, %r32
4010 movq $imm32, %r64 -> movl $imm32, %r32
4012 i
.tm
.opcode_modifier
.norex64
= 1;
4013 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
4016 movq $imm31, %r64 -> movl $imm31, %r32
4017 movq $imm32, %r64 -> movl $imm32, %r32
4019 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4020 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4021 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4022 i
.types
[0].bitfield
.imm32
= 1;
4023 i
.types
[0].bitfield
.imm32s
= 0;
4024 i
.types
[0].bitfield
.imm64
= 0;
4025 i
.types
[1].bitfield
.dword
= 1;
4026 i
.types
[1].bitfield
.qword
= 0;
4027 if (i
.tm
.base_opcode
== 0xc6)
4030 movq $imm31, %r64 -> movl $imm31, %r32
4032 i
.tm
.base_opcode
= 0xb0;
4033 i
.tm
.extension_opcode
= None
;
4034 i
.tm
.opcode_modifier
.shortform
= 1;
4035 i
.tm
.opcode_modifier
.modrm
= 0;
4039 else if (optimize
> 1
4040 && !optimize_for_space
4041 && i
.reg_operands
== 2
4042 && i
.op
[0].regs
== i
.op
[1].regs
4043 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4044 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4045 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4048 andb %rN, %rN -> testb %rN, %rN
4049 andw %rN, %rN -> testw %rN, %rN
4050 andq %rN, %rN -> testq %rN, %rN
4051 orb %rN, %rN -> testb %rN, %rN
4052 orw %rN, %rN -> testw %rN, %rN
4053 orq %rN, %rN -> testq %rN, %rN
4055 and outside of 64-bit mode
4057 andl %rN, %rN -> testl %rN, %rN
4058 orl %rN, %rN -> testl %rN, %rN
4060 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4062 else if (i
.reg_operands
== 3
4063 && i
.op
[0].regs
== i
.op
[1].regs
4064 && !i
.types
[2].bitfield
.xmmword
4065 && (i
.tm
.opcode_modifier
.vex
4066 || ((!i
.mask
|| i
.mask
->zeroing
)
4068 && is_evex_encoding (&i
.tm
)
4069 && (i
.vec_encoding
!= vex_encoding_evex
4070 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4071 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4072 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4073 && i
.types
[2].bitfield
.ymmword
))))
4074 && ((i
.tm
.base_opcode
== 0x55
4075 || i
.tm
.base_opcode
== 0x6655
4076 || i
.tm
.base_opcode
== 0x66df
4077 || i
.tm
.base_opcode
== 0x57
4078 || i
.tm
.base_opcode
== 0x6657
4079 || i
.tm
.base_opcode
== 0x66ef
4080 || i
.tm
.base_opcode
== 0x66f8
4081 || i
.tm
.base_opcode
== 0x66f9
4082 || i
.tm
.base_opcode
== 0x66fa
4083 || i
.tm
.base_opcode
== 0x66fb
4084 || i
.tm
.base_opcode
== 0x42
4085 || i
.tm
.base_opcode
== 0x6642
4086 || i
.tm
.base_opcode
== 0x47
4087 || i
.tm
.base_opcode
== 0x6647)
4088 && i
.tm
.extension_opcode
== None
))
4091 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4093 EVEX VOP %zmmM, %zmmM, %zmmN
4094 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4095 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4096 EVEX VOP %ymmM, %ymmM, %ymmN
4097 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4098 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4099 VEX VOP %ymmM, %ymmM, %ymmN
4100 -> VEX VOP %xmmM, %xmmM, %xmmN
4101 VOP, one of vpandn and vpxor:
4102 VEX VOP %ymmM, %ymmM, %ymmN
4103 -> VEX VOP %xmmM, %xmmM, %xmmN
4104 VOP, one of vpandnd and vpandnq:
4105 EVEX VOP %zmmM, %zmmM, %zmmN
4106 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4107 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4108 EVEX VOP %ymmM, %ymmM, %ymmN
4109 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4110 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4111 VOP, one of vpxord and vpxorq:
4112 EVEX VOP %zmmM, %zmmM, %zmmN
4113 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4114 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4115 EVEX VOP %ymmM, %ymmM, %ymmN
4116 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4117 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4118 VOP, one of kxord and kxorq:
4119 VEX VOP %kM, %kM, %kN
4120 -> VEX kxorw %kM, %kM, %kN
4121 VOP, one of kandnd and kandnq:
4122 VEX VOP %kM, %kM, %kN
4123 -> VEX kandnw %kM, %kM, %kN
4125 if (is_evex_encoding (&i
.tm
))
4127 if (i
.vec_encoding
!= vex_encoding_evex
)
4129 i
.tm
.opcode_modifier
.vex
= VEX128
;
4130 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4131 i
.tm
.opcode_modifier
.evex
= 0;
4133 else if (optimize
> 1)
4134 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4138 else if (i
.tm
.operand_types
[0].bitfield
.regmask
)
4140 i
.tm
.base_opcode
&= 0xff;
4141 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4144 i
.tm
.opcode_modifier
.vex
= VEX128
;
4146 if (i
.tm
.opcode_modifier
.vex
)
4147 for (j
= 0; j
< 3; j
++)
4149 i
.types
[j
].bitfield
.xmmword
= 1;
4150 i
.types
[j
].bitfield
.ymmword
= 0;
4153 else if (i
.vec_encoding
!= vex_encoding_evex
4154 && !i
.types
[0].bitfield
.zmmword
4155 && !i
.types
[1].bitfield
.zmmword
4158 && is_evex_encoding (&i
.tm
)
4159 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4160 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4161 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4162 || (i
.tm
.base_opcode
& ~4) == 0x66db
4163 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4164 && i
.tm
.extension_opcode
== None
)
4167 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4168 vmovdqu32 and vmovdqu64:
4169 EVEX VOP %xmmM, %xmmN
4170 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4171 EVEX VOP %ymmM, %ymmN
4172 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4174 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4176 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4178 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4180 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4181 VOP, one of vpand, vpandn, vpor, vpxor:
4182 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4183 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4184 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4185 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4186 EVEX VOP{d,q} mem, %xmmM, %xmmN
4187 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4188 EVEX VOP{d,q} mem, %ymmM, %ymmN
4189 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4191 for (j
= 0; j
< i
.operands
; j
++)
4192 if (operand_type_check (i
.types
[j
], disp
)
4193 && i
.op
[j
].disps
->X_op
== O_constant
)
4195 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4196 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4197 bytes, we choose EVEX Disp8 over VEX Disp32. */
4198 int evex_disp8
, vex_disp8
;
4199 unsigned int memshift
= i
.memshift
;
4200 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4202 evex_disp8
= fits_in_disp8 (n
);
4204 vex_disp8
= fits_in_disp8 (n
);
4205 if (evex_disp8
!= vex_disp8
)
4207 i
.memshift
= memshift
;
4211 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4214 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4215 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4216 i
.tm
.opcode_modifier
.vex
4217 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4218 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4219 /* VPAND, VPOR, and VPXOR are commutative. */
4220 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4221 i
.tm
.opcode_modifier
.commutative
= 1;
4222 i
.tm
.opcode_modifier
.evex
= 0;
4223 i
.tm
.opcode_modifier
.masking
= 0;
4224 i
.tm
.opcode_modifier
.broadcast
= 0;
4225 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4228 i
.types
[j
].bitfield
.disp8
4229 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4233 /* This is the guts of the machine-dependent assembler. LINE points to a
4234 machine dependent instruction. This function is supposed to emit
4235 the frags/bytes it assembles to. */
4238 md_assemble (char *line
)
4241 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4242 const insn_template
*t
;
4244 /* Initialize globals. */
4245 memset (&i
, '\0', sizeof (i
));
4246 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4247 i
.reloc
[j
] = NO_RELOC
;
4248 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4249 memset (im_expressions
, '\0', sizeof (im_expressions
));
4250 save_stack_p
= save_stack
;
4252 /* First parse an instruction mnemonic & call i386_operand for the operands.
4253 We assume that the scrubber has arranged it so that line[0] is the valid
4254 start of a (possibly prefixed) mnemonic. */
4256 line
= parse_insn (line
, mnemonic
);
4259 mnem_suffix
= i
.suffix
;
4261 line
= parse_operands (line
, mnemonic
);
4263 xfree (i
.memop1_string
);
4264 i
.memop1_string
= NULL
;
4268 /* Now we've parsed the mnemonic into a set of templates, and have the
4269 operands at hand. */
4271 /* All intel opcodes have reversed operands except for "bound" and
4272 "enter". We also don't reverse intersegment "jmp" and "call"
4273 instructions with 2 immediate operands so that the immediate segment
4274 precedes the offset, as it does when in AT&T mode. */
4277 && (strcmp (mnemonic
, "bound") != 0)
4278 && (strcmp (mnemonic
, "invlpga") != 0)
4279 && !(operand_type_check (i
.types
[0], imm
)
4280 && operand_type_check (i
.types
[1], imm
)))
4283 /* The order of the immediates should be reversed
4284 for 2 immediates extrq and insertq instructions */
4285 if (i
.imm_operands
== 2
4286 && (strcmp (mnemonic
, "extrq") == 0
4287 || strcmp (mnemonic
, "insertq") == 0))
4288 swap_2_operands (0, 1);
4293 /* Don't optimize displacement for movabs since it only takes 64bit
4296 && i
.disp_encoding
!= disp_encoding_32bit
4297 && (flag_code
!= CODE_64BIT
4298 || strcmp (mnemonic
, "movabs") != 0))
4301 /* Next, we find a template that matches the given insn,
4302 making sure the overlap of the given operands types is consistent
4303 with the template operand types. */
4305 if (!(t
= match_template (mnem_suffix
)))
4308 if (sse_check
!= check_none
4309 && !i
.tm
.opcode_modifier
.noavx
4310 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4311 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4312 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4313 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4314 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4315 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4316 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4317 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4318 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4319 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4321 (sse_check
== check_warning
4323 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4326 /* Zap movzx and movsx suffix. The suffix has been set from
4327 "word ptr" or "byte ptr" on the source operand in Intel syntax
4328 or extracted from mnemonic in AT&T syntax. But we'll use
4329 the destination register to choose the suffix for encoding. */
4330 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4332 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4333 there is no suffix, the default will be byte extension. */
4334 if (i
.reg_operands
!= 2
4337 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4342 if (i
.tm
.opcode_modifier
.fwait
)
4343 if (!add_prefix (FWAIT_OPCODE
))
4346 /* Check if REP prefix is OK. */
4347 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4349 as_bad (_("invalid instruction `%s' after `%s'"),
4350 i
.tm
.name
, i
.rep_prefix
);
4354 /* Check for lock without a lockable instruction. Destination operand
4355 must be memory unless it is xchg (0x86). */
4356 if (i
.prefix
[LOCK_PREFIX
]
4357 && (!i
.tm
.opcode_modifier
.islockable
4358 || i
.mem_operands
== 0
4359 || (i
.tm
.base_opcode
!= 0x86
4360 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4362 as_bad (_("expecting lockable instruction after `lock'"));
4366 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4367 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4369 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4373 /* Check if HLE prefix is OK. */
4374 if (i
.hle_prefix
&& !check_hle ())
4377 /* Check BND prefix. */
4378 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4379 as_bad (_("expecting valid branch instruction after `bnd'"));
4381 /* Check NOTRACK prefix. */
4382 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4383 as_bad (_("expecting indirect branch instruction after `notrack'"));
4385 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4387 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4388 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4389 else if (flag_code
!= CODE_16BIT
4390 ? i
.prefix
[ADDR_PREFIX
]
4391 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4392 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4395 /* Insert BND prefix. */
4396 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4398 if (!i
.prefix
[BND_PREFIX
])
4399 add_prefix (BND_PREFIX_OPCODE
);
4400 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4402 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4403 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4407 /* Check string instruction segment overrides. */
4408 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4410 if (!check_string ())
4412 i
.disp_operands
= 0;
4415 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4416 optimize_encoding ();
4418 if (!process_suffix ())
4421 /* Update operand types. */
4422 for (j
= 0; j
< i
.operands
; j
++)
4423 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4425 /* Make still unresolved immediate matches conform to size of immediate
4426 given in i.suffix. */
4427 if (!finalize_imm ())
4430 if (i
.types
[0].bitfield
.imm1
)
4431 i
.imm_operands
= 0; /* kludge for shift insns. */
4433 /* We only need to check those implicit registers for instructions
4434 with 3 operands or less. */
4435 if (i
.operands
<= 3)
4436 for (j
= 0; j
< i
.operands
; j
++)
4437 if (i
.types
[j
].bitfield
.inoutportreg
4438 || i
.types
[j
].bitfield
.shiftcount
4439 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4442 /* ImmExt should be processed after SSE2AVX. */
4443 if (!i
.tm
.opcode_modifier
.sse2avx
4444 && i
.tm
.opcode_modifier
.immext
)
4447 /* For insns with operands there are more diddles to do to the opcode. */
4450 if (!process_operands ())
4453 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4455 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4456 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4459 if (is_any_vex_encoding (&i
.tm
))
4461 if (!cpu_arch_flags
.bitfield
.cpui286
)
4463 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4468 if (i
.tm
.opcode_modifier
.vex
)
4469 build_vex_prefix (t
);
4471 build_evex_prefix ();
4474 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4475 instructions may define INT_OPCODE as well, so avoid this corner
4476 case for those instructions that use MODRM. */
4477 if (i
.tm
.base_opcode
== INT_OPCODE
4478 && !i
.tm
.opcode_modifier
.modrm
4479 && i
.op
[0].imms
->X_add_number
== 3)
4481 i
.tm
.base_opcode
= INT3_OPCODE
;
4485 if ((i
.tm
.opcode_modifier
.jump
4486 || i
.tm
.opcode_modifier
.jumpbyte
4487 || i
.tm
.opcode_modifier
.jumpdword
)
4488 && i
.op
[0].disps
->X_op
== O_constant
)
4490 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4491 the absolute address given by the constant. Since ix86 jumps and
4492 calls are pc relative, we need to generate a reloc. */
4493 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4494 i
.op
[0].disps
->X_op
= O_symbol
;
4497 if (i
.tm
.opcode_modifier
.rex64
)
4500 /* For 8 bit registers we need an empty rex prefix. Also if the
4501 instruction already has a prefix, we need to convert old
4502 registers to new ones. */
4504 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4505 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4506 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4507 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4508 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4509 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4514 i
.rex
|= REX_OPCODE
;
4515 for (x
= 0; x
< 2; x
++)
4517 /* Look for 8 bit operand that uses old registers. */
4518 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4519 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4521 /* In case it is "hi" register, give up. */
4522 if (i
.op
[x
].regs
->reg_num
> 3)
4523 as_bad (_("can't encode register '%s%s' in an "
4524 "instruction requiring REX prefix."),
4525 register_prefix
, i
.op
[x
].regs
->reg_name
);
4527 /* Otherwise it is equivalent to the extended register.
4528 Since the encoding doesn't change this is merely
4529 cosmetic cleanup for debug output. */
4531 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4536 if (i
.rex
== 0 && i
.rex_encoding
)
4538 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4539 that uses legacy register. If it is "hi" register, don't add
4540 the REX_OPCODE byte. */
4542 for (x
= 0; x
< 2; x
++)
4543 if (i
.types
[x
].bitfield
.reg
4544 && i
.types
[x
].bitfield
.byte
4545 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4546 && i
.op
[x
].regs
->reg_num
> 3)
4548 i
.rex_encoding
= FALSE
;
4557 add_prefix (REX_OPCODE
| i
.rex
);
4559 /* We are ready to output the insn. */
4564 parse_insn (char *line
, char *mnemonic
)
4567 char *token_start
= l
;
4570 const insn_template
*t
;
4576 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4581 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4583 as_bad (_("no such instruction: `%s'"), token_start
);
4588 if (!is_space_char (*l
)
4589 && *l
!= END_OF_INSN
4591 || (*l
!= PREFIX_SEPARATOR
4594 as_bad (_("invalid character %s in mnemonic"),
4595 output_invalid (*l
));
4598 if (token_start
== l
)
4600 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4601 as_bad (_("expecting prefix; got nothing"));
4603 as_bad (_("expecting mnemonic; got nothing"));
4607 /* Look up instruction (or prefix) via hash table. */
4608 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4610 if (*l
!= END_OF_INSN
4611 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4612 && current_templates
4613 && current_templates
->start
->opcode_modifier
.isprefix
)
4615 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4617 as_bad ((flag_code
!= CODE_64BIT
4618 ? _("`%s' is only supported in 64-bit mode")
4619 : _("`%s' is not supported in 64-bit mode")),
4620 current_templates
->start
->name
);
4623 /* If we are in 16-bit mode, do not allow addr16 or data16.
4624 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4625 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4626 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4627 && flag_code
!= CODE_64BIT
4628 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4629 ^ (flag_code
== CODE_16BIT
)))
4631 as_bad (_("redundant %s prefix"),
4632 current_templates
->start
->name
);
4635 if (current_templates
->start
->opcode_length
== 0)
4637 /* Handle pseudo prefixes. */
4638 switch (current_templates
->start
->base_opcode
)
4642 i
.disp_encoding
= disp_encoding_8bit
;
4646 i
.disp_encoding
= disp_encoding_32bit
;
4650 i
.dir_encoding
= dir_encoding_load
;
4654 i
.dir_encoding
= dir_encoding_store
;
4658 i
.vec_encoding
= vex_encoding_vex2
;
4662 i
.vec_encoding
= vex_encoding_vex3
;
4666 i
.vec_encoding
= vex_encoding_evex
;
4670 i
.rex_encoding
= TRUE
;
4674 i
.no_optimize
= TRUE
;
4682 /* Add prefix, checking for repeated prefixes. */
4683 switch (add_prefix (current_templates
->start
->base_opcode
))
4688 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4689 i
.notrack_prefix
= current_templates
->start
->name
;
4692 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4693 i
.hle_prefix
= current_templates
->start
->name
;
4694 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4695 i
.bnd_prefix
= current_templates
->start
->name
;
4697 i
.rep_prefix
= current_templates
->start
->name
;
4703 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4710 if (!current_templates
)
4712 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4713 Check if we should swap operand or force 32bit displacement in
4715 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4716 i
.dir_encoding
= dir_encoding_swap
;
4717 else if (mnem_p
- 3 == dot_p
4720 i
.disp_encoding
= disp_encoding_8bit
;
4721 else if (mnem_p
- 4 == dot_p
4725 i
.disp_encoding
= disp_encoding_32bit
;
4730 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4733 if (!current_templates
)
4736 if (mnem_p
> mnemonic
)
4738 /* See if we can get a match by trimming off a suffix. */
4741 case WORD_MNEM_SUFFIX
:
4742 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4743 i
.suffix
= SHORT_MNEM_SUFFIX
;
4746 case BYTE_MNEM_SUFFIX
:
4747 case QWORD_MNEM_SUFFIX
:
4748 i
.suffix
= mnem_p
[-1];
4750 current_templates
= (const templates
*) hash_find (op_hash
,
4753 case SHORT_MNEM_SUFFIX
:
4754 case LONG_MNEM_SUFFIX
:
4757 i
.suffix
= mnem_p
[-1];
4759 current_templates
= (const templates
*) hash_find (op_hash
,
4768 if (intel_float_operand (mnemonic
) == 1)
4769 i
.suffix
= SHORT_MNEM_SUFFIX
;
4771 i
.suffix
= LONG_MNEM_SUFFIX
;
4773 current_templates
= (const templates
*) hash_find (op_hash
,
4780 if (!current_templates
)
4782 as_bad (_("no such instruction: `%s'"), token_start
);
4787 if (current_templates
->start
->opcode_modifier
.jump
4788 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4790 /* Check for a branch hint. We allow ",pt" and ",pn" for
4791 predict taken and predict not taken respectively.
4792 I'm not sure that branch hints actually do anything on loop
4793 and jcxz insns (JumpByte) for current Pentium4 chips. They
4794 may work in the future and it doesn't hurt to accept them
4796 if (l
[0] == ',' && l
[1] == 'p')
4800 if (!add_prefix (DS_PREFIX_OPCODE
))
4804 else if (l
[2] == 'n')
4806 if (!add_prefix (CS_PREFIX_OPCODE
))
4812 /* Any other comma loses. */
4815 as_bad (_("invalid character %s in mnemonic"),
4816 output_invalid (*l
));
4820 /* Check if instruction is supported on specified architecture. */
4822 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4824 supported
|= cpu_flags_match (t
);
4825 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4827 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4828 as_warn (_("use .code16 to ensure correct addressing mode"));
4834 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4835 as_bad (flag_code
== CODE_64BIT
4836 ? _("`%s' is not supported in 64-bit mode")
4837 : _("`%s' is only supported in 64-bit mode"),
4838 current_templates
->start
->name
);
4840 as_bad (_("`%s' is not supported on `%s%s'"),
4841 current_templates
->start
->name
,
4842 cpu_arch_name
? cpu_arch_name
: default_arch
,
4843 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4849 parse_operands (char *l
, const char *mnemonic
)
4853 /* 1 if operand is pending after ','. */
4854 unsigned int expecting_operand
= 0;
4856 /* Non-zero if operand parens not balanced. */
4857 unsigned int paren_not_balanced
;
4859 while (*l
!= END_OF_INSN
)
4861 /* Skip optional white space before operand. */
4862 if (is_space_char (*l
))
4864 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4866 as_bad (_("invalid character %s before operand %d"),
4867 output_invalid (*l
),
4871 token_start
= l
; /* After white space. */
4872 paren_not_balanced
= 0;
4873 while (paren_not_balanced
|| *l
!= ',')
4875 if (*l
== END_OF_INSN
)
4877 if (paren_not_balanced
)
4880 as_bad (_("unbalanced parenthesis in operand %d."),
4883 as_bad (_("unbalanced brackets in operand %d."),
4888 break; /* we are done */
4890 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4892 as_bad (_("invalid character %s in operand %d"),
4893 output_invalid (*l
),
4900 ++paren_not_balanced
;
4902 --paren_not_balanced
;
4907 ++paren_not_balanced
;
4909 --paren_not_balanced
;
4913 if (l
!= token_start
)
4914 { /* Yes, we've read in another operand. */
4915 unsigned int operand_ok
;
4916 this_operand
= i
.operands
++;
4917 if (i
.operands
> MAX_OPERANDS
)
4919 as_bad (_("spurious operands; (%d operands/instruction max)"),
4923 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4924 /* Now parse operand adding info to 'i' as we go along. */
4925 END_STRING_AND_SAVE (l
);
4927 if (i
.mem_operands
> 1)
4929 as_bad (_("too many memory references for `%s'"),
4936 i386_intel_operand (token_start
,
4937 intel_float_operand (mnemonic
));
4939 operand_ok
= i386_att_operand (token_start
);
4941 RESTORE_END_STRING (l
);
4947 if (expecting_operand
)
4949 expecting_operand_after_comma
:
4950 as_bad (_("expecting operand after ','; got nothing"));
4955 as_bad (_("expecting operand before ','; got nothing"));
4960 /* Now *l must be either ',' or END_OF_INSN. */
4963 if (*++l
== END_OF_INSN
)
4965 /* Just skip it, if it's \n complain. */
4966 goto expecting_operand_after_comma
;
4968 expecting_operand
= 1;
4975 swap_2_operands (int xchg1
, int xchg2
)
4977 union i386_op temp_op
;
4978 i386_operand_type temp_type
;
4979 unsigned int temp_flags
;
4980 enum bfd_reloc_code_real temp_reloc
;
4982 temp_type
= i
.types
[xchg2
];
4983 i
.types
[xchg2
] = i
.types
[xchg1
];
4984 i
.types
[xchg1
] = temp_type
;
4986 temp_flags
= i
.flags
[xchg2
];
4987 i
.flags
[xchg2
] = i
.flags
[xchg1
];
4988 i
.flags
[xchg1
] = temp_flags
;
4990 temp_op
= i
.op
[xchg2
];
4991 i
.op
[xchg2
] = i
.op
[xchg1
];
4992 i
.op
[xchg1
] = temp_op
;
4994 temp_reloc
= i
.reloc
[xchg2
];
4995 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4996 i
.reloc
[xchg1
] = temp_reloc
;
5000 if (i
.mask
->operand
== xchg1
)
5001 i
.mask
->operand
= xchg2
;
5002 else if (i
.mask
->operand
== xchg2
)
5003 i
.mask
->operand
= xchg1
;
5007 if (i
.broadcast
->operand
== xchg1
)
5008 i
.broadcast
->operand
= xchg2
;
5009 else if (i
.broadcast
->operand
== xchg2
)
5010 i
.broadcast
->operand
= xchg1
;
5014 if (i
.rounding
->operand
== xchg1
)
5015 i
.rounding
->operand
= xchg2
;
5016 else if (i
.rounding
->operand
== xchg2
)
5017 i
.rounding
->operand
= xchg1
;
5022 swap_operands (void)
5028 swap_2_operands (1, i
.operands
- 2);
5032 swap_2_operands (0, i
.operands
- 1);
5038 if (i
.mem_operands
== 2)
5040 const seg_entry
*temp_seg
;
5041 temp_seg
= i
.seg
[0];
5042 i
.seg
[0] = i
.seg
[1];
5043 i
.seg
[1] = temp_seg
;
5047 /* Try to ensure constant immediates are represented in the smallest
5052 char guess_suffix
= 0;
5056 guess_suffix
= i
.suffix
;
5057 else if (i
.reg_operands
)
5059 /* Figure out a suffix from the last register operand specified.
5060 We can't do this properly yet, ie. excluding InOutPortReg,
5061 but the following works for instructions with immediates.
5062 In any case, we can't set i.suffix yet. */
5063 for (op
= i
.operands
; --op
>= 0;)
5064 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
5066 guess_suffix
= BYTE_MNEM_SUFFIX
;
5069 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
5071 guess_suffix
= WORD_MNEM_SUFFIX
;
5074 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
5076 guess_suffix
= LONG_MNEM_SUFFIX
;
5079 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
5081 guess_suffix
= QWORD_MNEM_SUFFIX
;
5085 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5086 guess_suffix
= WORD_MNEM_SUFFIX
;
5088 for (op
= i
.operands
; --op
>= 0;)
5089 if (operand_type_check (i
.types
[op
], imm
))
5091 switch (i
.op
[op
].imms
->X_op
)
5094 /* If a suffix is given, this operand may be shortened. */
5095 switch (guess_suffix
)
5097 case LONG_MNEM_SUFFIX
:
5098 i
.types
[op
].bitfield
.imm32
= 1;
5099 i
.types
[op
].bitfield
.imm64
= 1;
5101 case WORD_MNEM_SUFFIX
:
5102 i
.types
[op
].bitfield
.imm16
= 1;
5103 i
.types
[op
].bitfield
.imm32
= 1;
5104 i
.types
[op
].bitfield
.imm32s
= 1;
5105 i
.types
[op
].bitfield
.imm64
= 1;
5107 case BYTE_MNEM_SUFFIX
:
5108 i
.types
[op
].bitfield
.imm8
= 1;
5109 i
.types
[op
].bitfield
.imm8s
= 1;
5110 i
.types
[op
].bitfield
.imm16
= 1;
5111 i
.types
[op
].bitfield
.imm32
= 1;
5112 i
.types
[op
].bitfield
.imm32s
= 1;
5113 i
.types
[op
].bitfield
.imm64
= 1;
5117 /* If this operand is at most 16 bits, convert it
5118 to a signed 16 bit number before trying to see
5119 whether it will fit in an even smaller size.
5120 This allows a 16-bit operand such as $0xffe0 to
5121 be recognised as within Imm8S range. */
5122 if ((i
.types
[op
].bitfield
.imm16
)
5123 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5125 i
.op
[op
].imms
->X_add_number
=
5126 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5129 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5130 if ((i
.types
[op
].bitfield
.imm32
)
5131 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5134 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5135 ^ ((offsetT
) 1 << 31))
5136 - ((offsetT
) 1 << 31));
5140 = operand_type_or (i
.types
[op
],
5141 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5143 /* We must avoid matching of Imm32 templates when 64bit
5144 only immediate is available. */
5145 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5146 i
.types
[op
].bitfield
.imm32
= 0;
5153 /* Symbols and expressions. */
5155 /* Convert symbolic operand to proper sizes for matching, but don't
5156 prevent matching a set of insns that only supports sizes other
5157 than those matching the insn suffix. */
5159 i386_operand_type mask
, allowed
;
5160 const insn_template
*t
;
5162 operand_type_set (&mask
, 0);
5163 operand_type_set (&allowed
, 0);
5165 for (t
= current_templates
->start
;
5166 t
< current_templates
->end
;
5168 allowed
= operand_type_or (allowed
,
5169 t
->operand_types
[op
]);
5170 switch (guess_suffix
)
5172 case QWORD_MNEM_SUFFIX
:
5173 mask
.bitfield
.imm64
= 1;
5174 mask
.bitfield
.imm32s
= 1;
5176 case LONG_MNEM_SUFFIX
:
5177 mask
.bitfield
.imm32
= 1;
5179 case WORD_MNEM_SUFFIX
:
5180 mask
.bitfield
.imm16
= 1;
5182 case BYTE_MNEM_SUFFIX
:
5183 mask
.bitfield
.imm8
= 1;
5188 allowed
= operand_type_and (mask
, allowed
);
5189 if (!operand_type_all_zero (&allowed
))
5190 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5197 /* Try to use the smallest displacement type too. */
5199 optimize_disp (void)
5203 for (op
= i
.operands
; --op
>= 0;)
5204 if (operand_type_check (i
.types
[op
], disp
))
5206 if (i
.op
[op
].disps
->X_op
== O_constant
)
5208 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5210 if (i
.types
[op
].bitfield
.disp16
5211 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5213 /* If this operand is at most 16 bits, convert
5214 to a signed 16 bit number and don't use 64bit
5216 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5217 i
.types
[op
].bitfield
.disp64
= 0;
5220 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5221 if (i
.types
[op
].bitfield
.disp32
5222 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5224 /* If this operand is at most 32 bits, convert
5225 to a signed 32 bit number and don't use 64bit
5227 op_disp
&= (((offsetT
) 2 << 31) - 1);
5228 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5229 i
.types
[op
].bitfield
.disp64
= 0;
5232 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5234 i
.types
[op
].bitfield
.disp8
= 0;
5235 i
.types
[op
].bitfield
.disp16
= 0;
5236 i
.types
[op
].bitfield
.disp32
= 0;
5237 i
.types
[op
].bitfield
.disp32s
= 0;
5238 i
.types
[op
].bitfield
.disp64
= 0;
5242 else if (flag_code
== CODE_64BIT
)
5244 if (fits_in_signed_long (op_disp
))
5246 i
.types
[op
].bitfield
.disp64
= 0;
5247 i
.types
[op
].bitfield
.disp32s
= 1;
5249 if (i
.prefix
[ADDR_PREFIX
]
5250 && fits_in_unsigned_long (op_disp
))
5251 i
.types
[op
].bitfield
.disp32
= 1;
5253 if ((i
.types
[op
].bitfield
.disp32
5254 || i
.types
[op
].bitfield
.disp32s
5255 || i
.types
[op
].bitfield
.disp16
)
5256 && fits_in_disp8 (op_disp
))
5257 i
.types
[op
].bitfield
.disp8
= 1;
5259 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5260 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5262 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5263 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5264 i
.types
[op
].bitfield
.disp8
= 0;
5265 i
.types
[op
].bitfield
.disp16
= 0;
5266 i
.types
[op
].bitfield
.disp32
= 0;
5267 i
.types
[op
].bitfield
.disp32s
= 0;
5268 i
.types
[op
].bitfield
.disp64
= 0;
5271 /* We only support 64bit displacement on constants. */
5272 i
.types
[op
].bitfield
.disp64
= 0;
5276 /* Return 1 if there is a match in broadcast bytes between operand
5277 GIVEN and instruction template T. */
5280 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5282 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5283 && i
.types
[given
].bitfield
.byte
)
5284 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5285 && i
.types
[given
].bitfield
.word
)
5286 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5287 && i
.types
[given
].bitfield
.dword
)
5288 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5289 && i
.types
[given
].bitfield
.qword
));
5292 /* Check if operands are valid for the instruction. */
5295 check_VecOperands (const insn_template
*t
)
5299 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5301 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5302 any one operand are implicity requiring AVX512VL support if the actual
5303 operand size is YMMword or XMMword. Since this function runs after
5304 template matching, there's no need to check for YMMword/XMMword in
5306 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5307 if (!cpu_flags_all_zero (&cpu
)
5308 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5309 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5311 for (op
= 0; op
< t
->operands
; ++op
)
5313 if (t
->operand_types
[op
].bitfield
.zmmword
5314 && (i
.types
[op
].bitfield
.ymmword
5315 || i
.types
[op
].bitfield
.xmmword
))
5317 i
.error
= unsupported
;
5323 /* Without VSIB byte, we can't have a vector register for index. */
5324 if (!t
->opcode_modifier
.vecsib
5326 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5327 || i
.index_reg
->reg_type
.bitfield
.ymmword
5328 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5330 i
.error
= unsupported_vector_index_register
;
5334 /* Check if default mask is allowed. */
5335 if (t
->opcode_modifier
.nodefmask
5336 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5338 i
.error
= no_default_mask
;
5342 /* For VSIB byte, we need a vector register for index, and all vector
5343 registers must be distinct. */
5344 if (t
->opcode_modifier
.vecsib
)
5347 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5348 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5349 || (t
->opcode_modifier
.vecsib
== VecSIB256
5350 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5351 || (t
->opcode_modifier
.vecsib
== VecSIB512
5352 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5354 i
.error
= invalid_vsib_address
;
5358 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5359 if (i
.reg_operands
== 2 && !i
.mask
)
5361 gas_assert (i
.types
[0].bitfield
.regsimd
);
5362 gas_assert (i
.types
[0].bitfield
.xmmword
5363 || i
.types
[0].bitfield
.ymmword
);
5364 gas_assert (i
.types
[2].bitfield
.regsimd
);
5365 gas_assert (i
.types
[2].bitfield
.xmmword
5366 || i
.types
[2].bitfield
.ymmword
);
5367 if (operand_check
== check_none
)
5369 if (register_number (i
.op
[0].regs
)
5370 != register_number (i
.index_reg
)
5371 && register_number (i
.op
[2].regs
)
5372 != register_number (i
.index_reg
)
5373 && register_number (i
.op
[0].regs
)
5374 != register_number (i
.op
[2].regs
))
5376 if (operand_check
== check_error
)
5378 i
.error
= invalid_vector_register_set
;
5381 as_warn (_("mask, index, and destination registers should be distinct"));
5383 else if (i
.reg_operands
== 1 && i
.mask
)
5385 if (i
.types
[1].bitfield
.regsimd
5386 && (i
.types
[1].bitfield
.xmmword
5387 || i
.types
[1].bitfield
.ymmword
5388 || i
.types
[1].bitfield
.zmmword
)
5389 && (register_number (i
.op
[1].regs
)
5390 == register_number (i
.index_reg
)))
5392 if (operand_check
== check_error
)
5394 i
.error
= invalid_vector_register_set
;
5397 if (operand_check
!= check_none
)
5398 as_warn (_("index and destination registers should be distinct"));
5403 /* Check if broadcast is supported by the instruction and is applied
5404 to the memory operand. */
5407 i386_operand_type type
, overlap
;
5409 /* Check if specified broadcast is supported in this instruction,
5410 and its broadcast bytes match the memory operand. */
5411 op
= i
.broadcast
->operand
;
5412 if (!t
->opcode_modifier
.broadcast
5413 || !(i
.flags
[op
] & Operand_Mem
)
5414 || (!i
.types
[op
].bitfield
.unspecified
5415 && !match_broadcast_size (t
, op
)))
5418 i
.error
= unsupported_broadcast
;
5422 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5423 * i
.broadcast
->type
);
5424 operand_type_set (&type
, 0);
5425 switch (i
.broadcast
->bytes
)
5428 type
.bitfield
.word
= 1;
5431 type
.bitfield
.dword
= 1;
5434 type
.bitfield
.qword
= 1;
5437 type
.bitfield
.xmmword
= 1;
5440 type
.bitfield
.ymmword
= 1;
5443 type
.bitfield
.zmmword
= 1;
5449 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5450 if (operand_type_all_zero (&overlap
))
5453 if (t
->opcode_modifier
.checkregsize
)
5457 type
.bitfield
.baseindex
= 1;
5458 for (j
= 0; j
< i
.operands
; ++j
)
5461 && !operand_type_register_match(i
.types
[j
],
5462 t
->operand_types
[j
],
5464 t
->operand_types
[op
]))
5469 /* If broadcast is supported in this instruction, we need to check if
5470 operand of one-element size isn't specified without broadcast. */
5471 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5473 /* Find memory operand. */
5474 for (op
= 0; op
< i
.operands
; op
++)
5475 if (i
.flags
[op
] & Operand_Mem
)
5477 gas_assert (op
< i
.operands
);
5478 /* Check size of the memory operand. */
5479 if (match_broadcast_size (t
, op
))
5481 i
.error
= broadcast_needed
;
5486 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5488 /* Check if requested masking is supported. */
5491 switch (t
->opcode_modifier
.masking
)
5495 case MERGING_MASKING
:
5496 if (i
.mask
->zeroing
)
5499 i
.error
= unsupported_masking
;
5503 case DYNAMIC_MASKING
:
5504 /* Memory destinations allow only merging masking. */
5505 if (i
.mask
->zeroing
&& i
.mem_operands
)
5507 /* Find memory operand. */
5508 for (op
= 0; op
< i
.operands
; op
++)
5509 if (i
.flags
[op
] & Operand_Mem
)
5511 gas_assert (op
< i
.operands
);
5512 if (op
== i
.operands
- 1)
5514 i
.error
= unsupported_masking
;
5524 /* Check if masking is applied to dest operand. */
5525 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5527 i
.error
= mask_not_on_destination
;
5534 if (!t
->opcode_modifier
.sae
5535 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5537 i
.error
= unsupported_rc_sae
;
5540 /* If the instruction has several immediate operands and one of
5541 them is rounding, the rounding operand should be the last
5542 immediate operand. */
5543 if (i
.imm_operands
> 1
5544 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5546 i
.error
= rc_sae_operand_not_last_imm
;
5551 /* Check vector Disp8 operand. */
5552 if (t
->opcode_modifier
.disp8memshift
5553 && i
.disp_encoding
!= disp_encoding_32bit
)
5556 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5557 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5558 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5561 const i386_operand_type
*type
= NULL
;
5564 for (op
= 0; op
< i
.operands
; op
++)
5565 if (i
.flags
[op
] & Operand_Mem
)
5567 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5568 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5569 else if (t
->operand_types
[op
].bitfield
.xmmword
5570 + t
->operand_types
[op
].bitfield
.ymmword
5571 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5572 type
= &t
->operand_types
[op
];
5573 else if (!i
.types
[op
].bitfield
.unspecified
)
5574 type
= &i
.types
[op
];
5576 else if (i
.types
[op
].bitfield
.regsimd
5577 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5579 if (i
.types
[op
].bitfield
.zmmword
)
5581 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5583 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5589 if (type
->bitfield
.zmmword
)
5591 else if (type
->bitfield
.ymmword
)
5593 else if (type
->bitfield
.xmmword
)
5597 /* For the check in fits_in_disp8(). */
5598 if (i
.memshift
== 0)
5602 for (op
= 0; op
< i
.operands
; op
++)
5603 if (operand_type_check (i
.types
[op
], disp
)
5604 && i
.op
[op
].disps
->X_op
== O_constant
)
5606 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5608 i
.types
[op
].bitfield
.disp8
= 1;
5611 i
.types
[op
].bitfield
.disp8
= 0;
5620 /* Check if operands are valid for the instruction. Update VEX
5624 VEX_check_operands (const insn_template
*t
)
5626 if (i
.vec_encoding
== vex_encoding_evex
)
5628 /* This instruction must be encoded with EVEX prefix. */
5629 if (!is_evex_encoding (t
))
5631 i
.error
= unsupported
;
5637 if (!t
->opcode_modifier
.vex
)
5639 /* This instruction template doesn't have VEX prefix. */
5640 if (i
.vec_encoding
!= vex_encoding_default
)
5642 i
.error
= unsupported
;
5648 /* Check the special Imm4 cases; must be the first operand. */
5649 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5651 if (i
.op
[0].imms
->X_op
!= O_constant
5652 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5658 /* Turn off Imm<N> so that update_imm won't complain. */
5659 operand_type_set (&i
.types
[0], 0);
5665 static const insn_template
*
5666 match_template (char mnem_suffix
)
5668 /* Points to template once we've found it. */
5669 const insn_template
*t
;
5670 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5671 i386_operand_type overlap4
;
5672 unsigned int found_reverse_match
;
5673 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5674 i386_operand_type operand_types
[MAX_OPERANDS
];
5675 int addr_prefix_disp
;
5677 unsigned int found_cpu_match
, size_match
;
5678 unsigned int check_register
;
5679 enum i386_error specific_error
= 0;
5681 #if MAX_OPERANDS != 5
5682 # error "MAX_OPERANDS must be 5."
5685 found_reverse_match
= 0;
5686 addr_prefix_disp
= -1;
5688 memset (&suffix_check
, 0, sizeof (suffix_check
));
5689 if (intel_syntax
&& i
.broadcast
)
5691 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5692 suffix_check
.no_bsuf
= 1;
5693 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5694 suffix_check
.no_wsuf
= 1;
5695 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5696 suffix_check
.no_ssuf
= 1;
5697 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5698 suffix_check
.no_lsuf
= 1;
5699 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5700 suffix_check
.no_qsuf
= 1;
5701 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5702 suffix_check
.no_ldsuf
= 1;
5704 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5707 switch (mnem_suffix
)
5709 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5710 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5711 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5712 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5713 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5717 /* Must have right number of operands. */
5718 i
.error
= number_of_operands_mismatch
;
5720 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5722 addr_prefix_disp
= -1;
5723 found_reverse_match
= 0;
5725 if (i
.operands
!= t
->operands
)
5728 /* Check processor support. */
5729 i
.error
= unsupported
;
5730 found_cpu_match
= (cpu_flags_match (t
)
5731 == CPU_FLAGS_PERFECT_MATCH
);
5732 if (!found_cpu_match
)
5735 /* Check AT&T mnemonic. */
5736 i
.error
= unsupported_with_intel_mnemonic
;
5737 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5740 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5741 i
.error
= unsupported_syntax
;
5742 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5743 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5744 || (intel64
&& t
->opcode_modifier
.amd64
)
5745 || (!intel64
&& t
->opcode_modifier
.intel64
))
5748 /* Check the suffix, except for some instructions in intel mode. */
5749 i
.error
= invalid_instruction_suffix
;
5750 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5751 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5752 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5753 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5754 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5755 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5756 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5758 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5759 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5760 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5761 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5762 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5763 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5764 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5767 size_match
= operand_size_match (t
);
5771 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5772 operand_types
[j
] = t
->operand_types
[j
];
5774 /* In general, don't allow 64-bit operands in 32-bit mode. */
5775 if (i
.suffix
== QWORD_MNEM_SUFFIX
5776 && flag_code
!= CODE_64BIT
5778 ? (!t
->opcode_modifier
.ignoresize
5779 && !t
->opcode_modifier
.broadcast
5780 && !intel_float_operand (t
->name
))
5781 : intel_float_operand (t
->name
) != 2)
5782 && ((!operand_types
[0].bitfield
.regmmx
5783 && !operand_types
[0].bitfield
.regsimd
)
5784 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5785 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5786 && (t
->base_opcode
!= 0x0fc7
5787 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5790 /* In general, don't allow 32-bit operands on pre-386. */
5791 else if (i
.suffix
== LONG_MNEM_SUFFIX
5792 && !cpu_arch_flags
.bitfield
.cpui386
5794 ? (!t
->opcode_modifier
.ignoresize
5795 && !intel_float_operand (t
->name
))
5796 : intel_float_operand (t
->name
) != 2)
5797 && ((!operand_types
[0].bitfield
.regmmx
5798 && !operand_types
[0].bitfield
.regsimd
)
5799 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5800 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5803 /* Do not verify operands when there are none. */
5807 /* We've found a match; break out of loop. */
5811 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5812 into Disp32/Disp16/Disp32 operand. */
5813 if (i
.prefix
[ADDR_PREFIX
] != 0)
5815 /* There should be only one Disp operand. */
5819 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5821 if (operand_types
[j
].bitfield
.disp16
)
5823 addr_prefix_disp
= j
;
5824 operand_types
[j
].bitfield
.disp32
= 1;
5825 operand_types
[j
].bitfield
.disp16
= 0;
5831 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5833 if (operand_types
[j
].bitfield
.disp32
)
5835 addr_prefix_disp
= j
;
5836 operand_types
[j
].bitfield
.disp32
= 0;
5837 operand_types
[j
].bitfield
.disp16
= 1;
5843 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5845 if (operand_types
[j
].bitfield
.disp64
)
5847 addr_prefix_disp
= j
;
5848 operand_types
[j
].bitfield
.disp64
= 0;
5849 operand_types
[j
].bitfield
.disp32
= 1;
5857 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5858 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5861 /* We check register size if needed. */
5862 if (t
->opcode_modifier
.checkregsize
)
5864 check_register
= (1 << t
->operands
) - 1;
5866 check_register
&= ~(1 << i
.broadcast
->operand
);
5871 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5872 switch (t
->operands
)
5875 if (!operand_type_match (overlap0
, i
.types
[0]))
5879 /* xchg %eax, %eax is a special case. It is an alias for nop
5880 only in 32bit mode and we can use opcode 0x90. In 64bit
5881 mode, we can't use 0x90 for xchg %eax, %eax since it should
5882 zero-extend %eax to %rax. */
5883 if (flag_code
== CODE_64BIT
5884 && t
->base_opcode
== 0x90
5885 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.dword
5886 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.dword
)
5888 /* xrelease mov %eax, <disp> is another special case. It must not
5889 match the accumulator-only encoding of mov. */
5890 if (flag_code
!= CODE_64BIT
5892 && t
->base_opcode
== 0xa0
5893 && i
.types
[0].bitfield
.acc
5894 && (i
.flags
[1] & Operand_Mem
))
5899 if (!(size_match
& MATCH_STRAIGHT
))
5901 /* Reverse direction of operands if swapping is possible in the first
5902 place (operands need to be symmetric) and
5903 - the load form is requested, and the template is a store form,
5904 - the store form is requested, and the template is a load form,
5905 - the non-default (swapped) form is requested. */
5906 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5907 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5908 && !operand_type_all_zero (&overlap1
))
5909 switch (i
.dir_encoding
)
5911 case dir_encoding_load
:
5912 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5913 || t
->opcode_modifier
.regmem
)
5917 case dir_encoding_store
:
5918 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5919 && !t
->opcode_modifier
.regmem
)
5923 case dir_encoding_swap
:
5926 case dir_encoding_default
:
5929 /* If we want store form, we skip the current load. */
5930 if ((i
.dir_encoding
== dir_encoding_store
5931 || i
.dir_encoding
== dir_encoding_swap
)
5932 && i
.mem_operands
== 0
5933 && t
->opcode_modifier
.load
)
5938 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5939 if (!operand_type_match (overlap0
, i
.types
[0])
5940 || !operand_type_match (overlap1
, i
.types
[1])
5941 || ((check_register
& 3) == 3
5942 && !operand_type_register_match (i
.types
[0],
5947 /* Check if other direction is valid ... */
5948 if (!t
->opcode_modifier
.d
)
5952 if (!(size_match
& MATCH_REVERSE
))
5954 /* Try reversing direction of operands. */
5955 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
5956 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
5957 if (!operand_type_match (overlap0
, i
.types
[0])
5958 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
5960 && !operand_type_register_match (i
.types
[0],
5961 operand_types
[i
.operands
- 1],
5962 i
.types
[i
.operands
- 1],
5965 /* Does not match either direction. */
5968 /* found_reverse_match holds which of D or FloatR
5970 if (!t
->opcode_modifier
.d
)
5971 found_reverse_match
= 0;
5972 else if (operand_types
[0].bitfield
.tbyte
)
5973 found_reverse_match
= Opcode_FloatD
;
5974 else if (operand_types
[0].bitfield
.xmmword
5975 || operand_types
[i
.operands
- 1].bitfield
.xmmword
5976 || operand_types
[0].bitfield
.regmmx
5977 || operand_types
[i
.operands
- 1].bitfield
.regmmx
5978 || is_any_vex_encoding(t
))
5979 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
5980 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
5982 found_reverse_match
= Opcode_D
;
5983 if (t
->opcode_modifier
.floatr
)
5984 found_reverse_match
|= Opcode_FloatR
;
5988 /* Found a forward 2 operand match here. */
5989 switch (t
->operands
)
5992 overlap4
= operand_type_and (i
.types
[4],
5996 overlap3
= operand_type_and (i
.types
[3],
6000 overlap2
= operand_type_and (i
.types
[2],
6005 switch (t
->operands
)
6008 if (!operand_type_match (overlap4
, i
.types
[4])
6009 || !operand_type_register_match (i
.types
[3],
6016 if (!operand_type_match (overlap3
, i
.types
[3])
6017 || ((check_register
& 0xa) == 0xa
6018 && !operand_type_register_match (i
.types
[1],
6022 || ((check_register
& 0xc) == 0xc
6023 && !operand_type_register_match (i
.types
[2],
6030 /* Here we make use of the fact that there are no
6031 reverse match 3 operand instructions. */
6032 if (!operand_type_match (overlap2
, i
.types
[2])
6033 || ((check_register
& 5) == 5
6034 && !operand_type_register_match (i
.types
[0],
6038 || ((check_register
& 6) == 6
6039 && !operand_type_register_match (i
.types
[1],
6047 /* Found either forward/reverse 2, 3 or 4 operand match here:
6048 slip through to break. */
6050 if (!found_cpu_match
)
6053 /* Check if vector and VEX operands are valid. */
6054 if (check_VecOperands (t
) || VEX_check_operands (t
))
6056 specific_error
= i
.error
;
6060 /* We've found a match; break out of loop. */
6064 if (t
== current_templates
->end
)
6066 /* We found no match. */
6067 const char *err_msg
;
6068 switch (specific_error
? specific_error
: i
.error
)
6072 case operand_size_mismatch
:
6073 err_msg
= _("operand size mismatch");
6075 case operand_type_mismatch
:
6076 err_msg
= _("operand type mismatch");
6078 case register_type_mismatch
:
6079 err_msg
= _("register type mismatch");
6081 case number_of_operands_mismatch
:
6082 err_msg
= _("number of operands mismatch");
6084 case invalid_instruction_suffix
:
6085 err_msg
= _("invalid instruction suffix");
6088 err_msg
= _("constant doesn't fit in 4 bits");
6090 case unsupported_with_intel_mnemonic
:
6091 err_msg
= _("unsupported with Intel mnemonic");
6093 case unsupported_syntax
:
6094 err_msg
= _("unsupported syntax");
6097 as_bad (_("unsupported instruction `%s'"),
6098 current_templates
->start
->name
);
6100 case invalid_vsib_address
:
6101 err_msg
= _("invalid VSIB address");
6103 case invalid_vector_register_set
:
6104 err_msg
= _("mask, index, and destination registers must be distinct");
6106 case unsupported_vector_index_register
:
6107 err_msg
= _("unsupported vector index register");
6109 case unsupported_broadcast
:
6110 err_msg
= _("unsupported broadcast");
6112 case broadcast_needed
:
6113 err_msg
= _("broadcast is needed for operand of such type");
6115 case unsupported_masking
:
6116 err_msg
= _("unsupported masking");
6118 case mask_not_on_destination
:
6119 err_msg
= _("mask not on destination operand");
6121 case no_default_mask
:
6122 err_msg
= _("default mask isn't allowed");
6124 case unsupported_rc_sae
:
6125 err_msg
= _("unsupported static rounding/sae");
6127 case rc_sae_operand_not_last_imm
:
6129 err_msg
= _("RC/SAE operand must precede immediate operands");
6131 err_msg
= _("RC/SAE operand must follow immediate operands");
6133 case invalid_register_operand
:
6134 err_msg
= _("invalid register operand");
6137 as_bad (_("%s for `%s'"), err_msg
,
6138 current_templates
->start
->name
);
6142 if (!quiet_warnings
)
6145 && (i
.types
[0].bitfield
.jumpabsolute
6146 != operand_types
[0].bitfield
.jumpabsolute
))
6148 as_warn (_("indirect %s without `*'"), t
->name
);
6151 if (t
->opcode_modifier
.isprefix
6152 && t
->opcode_modifier
.ignoresize
)
6154 /* Warn them that a data or address size prefix doesn't
6155 affect assembly of the next line of code. */
6156 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6160 /* Copy the template we found. */
6163 if (addr_prefix_disp
!= -1)
6164 i
.tm
.operand_types
[addr_prefix_disp
]
6165 = operand_types
[addr_prefix_disp
];
6167 if (found_reverse_match
)
6169 /* If we found a reverse match we must alter the opcode direction
6170 bit and clear/flip the regmem modifier one. found_reverse_match
6171 holds bits to change (different for int & float insns). */
6173 i
.tm
.base_opcode
^= found_reverse_match
;
6175 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6176 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6178 /* Certain SIMD insns have their load forms specified in the opcode
6179 table, and hence we need to _set_ RegMem instead of clearing it.
6180 We need to avoid setting the bit though on insns like KMOVW. */
6181 i
.tm
.opcode_modifier
.regmem
6182 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6183 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6184 && !i
.tm
.opcode_modifier
.regmem
;
6193 unsigned int mem_op
= i
.flags
[0] & Operand_Mem
? 0 : 1;
6195 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
6197 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
6199 as_bad (_("`%s' operand %d must use `%ses' segment"),
6205 /* There's only ever one segment override allowed per instruction.
6206 This instruction possibly has a legal segment override on the
6207 second operand, so copy the segment to where non-string
6208 instructions store it, allowing common code. */
6209 i
.seg
[0] = i
.seg
[1];
6211 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
6213 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
6215 as_bad (_("`%s' operand %d must use `%ses' segment"),
6226 process_suffix (void)
6228 /* If matched instruction specifies an explicit instruction mnemonic
6230 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6231 i
.suffix
= WORD_MNEM_SUFFIX
;
6232 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6233 i
.suffix
= LONG_MNEM_SUFFIX
;
6234 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6235 i
.suffix
= QWORD_MNEM_SUFFIX
;
6236 else if (i
.reg_operands
)
6238 /* If there's no instruction mnemonic suffix we try to invent one
6239 based on register operands. */
6242 /* We take i.suffix from the last register operand specified,
6243 Destination register type is more significant than source
6244 register type. crc32 in SSE4.2 prefers source register
6246 if (i
.tm
.base_opcode
== 0xf20f38f0 && i
.types
[0].bitfield
.reg
)
6248 if (i
.types
[0].bitfield
.byte
)
6249 i
.suffix
= BYTE_MNEM_SUFFIX
;
6250 else if (i
.types
[0].bitfield
.word
)
6251 i
.suffix
= WORD_MNEM_SUFFIX
;
6252 else if (i
.types
[0].bitfield
.dword
)
6253 i
.suffix
= LONG_MNEM_SUFFIX
;
6254 else if (i
.types
[0].bitfield
.qword
)
6255 i
.suffix
= QWORD_MNEM_SUFFIX
;
6262 if (i
.tm
.base_opcode
== 0xf20f38f0)
6264 /* We have to know the operand size for crc32. */
6265 as_bad (_("ambiguous memory operand size for `%s`"),
6270 for (op
= i
.operands
; --op
>= 0;)
6271 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
6272 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
6274 if (!i
.types
[op
].bitfield
.reg
)
6276 if (i
.types
[op
].bitfield
.byte
)
6277 i
.suffix
= BYTE_MNEM_SUFFIX
;
6278 else if (i
.types
[op
].bitfield
.word
)
6279 i
.suffix
= WORD_MNEM_SUFFIX
;
6280 else if (i
.types
[op
].bitfield
.dword
)
6281 i
.suffix
= LONG_MNEM_SUFFIX
;
6282 else if (i
.types
[op
].bitfield
.qword
)
6283 i
.suffix
= QWORD_MNEM_SUFFIX
;
6290 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6293 && i
.tm
.opcode_modifier
.ignoresize
6294 && i
.tm
.opcode_modifier
.no_bsuf
)
6296 else if (!check_byte_reg ())
6299 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6302 && i
.tm
.opcode_modifier
.ignoresize
6303 && i
.tm
.opcode_modifier
.no_lsuf
6304 && !i
.tm
.opcode_modifier
.todword
6305 && !i
.tm
.opcode_modifier
.toqword
)
6307 else if (!check_long_reg ())
6310 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6313 && i
.tm
.opcode_modifier
.ignoresize
6314 && i
.tm
.opcode_modifier
.no_qsuf
6315 && !i
.tm
.opcode_modifier
.todword
6316 && !i
.tm
.opcode_modifier
.toqword
)
6318 else if (!check_qword_reg ())
6321 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6324 && i
.tm
.opcode_modifier
.ignoresize
6325 && i
.tm
.opcode_modifier
.no_wsuf
)
6327 else if (!check_word_reg ())
6330 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6331 /* Do nothing if the instruction is going to ignore the prefix. */
6336 else if (i
.tm
.opcode_modifier
.defaultsize
6338 /* exclude fldenv/frstor/fsave/fstenv */
6339 && i
.tm
.opcode_modifier
.no_ssuf
)
6341 if (stackop_size
== LONG_MNEM_SUFFIX
6342 && i
.tm
.base_opcode
== 0xcf)
6344 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6345 .code16gcc directive to support 16-bit mode with
6346 32-bit address. For IRET without a suffix, generate
6347 16-bit IRET (opcode 0xcf) to return from an interrupt
6349 i
.suffix
= WORD_MNEM_SUFFIX
;
6350 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6353 i
.suffix
= stackop_size
;
6355 else if (intel_syntax
6357 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
6358 || i
.tm
.opcode_modifier
.jumpbyte
6359 || i
.tm
.opcode_modifier
.jumpintersegment
6360 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6361 && i
.tm
.extension_opcode
<= 3)))
6366 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6368 i
.suffix
= QWORD_MNEM_SUFFIX
;
6373 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6374 i
.suffix
= LONG_MNEM_SUFFIX
;
6377 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6378 i
.suffix
= WORD_MNEM_SUFFIX
;
6387 if (i
.tm
.opcode_modifier
.w
)
6389 as_bad (_("no instruction mnemonic suffix given and "
6390 "no register operands; can't size instruction"));
6396 unsigned int suffixes
;
6398 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6399 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6401 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6403 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6405 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6407 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6410 /* There are more than suffix matches. */
6411 if (i
.tm
.opcode_modifier
.w
6412 || ((suffixes
& (suffixes
- 1))
6413 && !i
.tm
.opcode_modifier
.defaultsize
6414 && !i
.tm
.opcode_modifier
.ignoresize
))
6416 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6422 /* Change the opcode based on the operand size given by i.suffix. */
6425 /* Size floating point instruction. */
6426 case LONG_MNEM_SUFFIX
:
6427 if (i
.tm
.opcode_modifier
.floatmf
)
6429 i
.tm
.base_opcode
^= 4;
6433 case WORD_MNEM_SUFFIX
:
6434 case QWORD_MNEM_SUFFIX
:
6435 /* It's not a byte, select word/dword operation. */
6436 if (i
.tm
.opcode_modifier
.w
)
6438 if (i
.tm
.opcode_modifier
.shortform
)
6439 i
.tm
.base_opcode
|= 8;
6441 i
.tm
.base_opcode
|= 1;
6444 case SHORT_MNEM_SUFFIX
:
6445 /* Now select between word & dword operations via the operand
6446 size prefix, except for instructions that will ignore this
6448 if (i
.reg_operands
> 0
6449 && i
.types
[0].bitfield
.reg
6450 && i
.tm
.opcode_modifier
.addrprefixopreg
6451 && (i
.tm
.opcode_modifier
.immext
6452 || i
.operands
== 1))
6454 /* The address size override prefix changes the size of the
6456 if ((flag_code
== CODE_32BIT
6457 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6458 || (flag_code
!= CODE_32BIT
6459 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6460 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6463 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6464 && !i
.tm
.opcode_modifier
.ignoresize
6465 && !i
.tm
.opcode_modifier
.floatmf
6466 && !is_any_vex_encoding (&i
.tm
)
6467 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6468 || (flag_code
== CODE_64BIT
6469 && i
.tm
.opcode_modifier
.jumpbyte
)))
6471 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6473 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
6474 prefix
= ADDR_PREFIX_OPCODE
;
6476 if (!add_prefix (prefix
))
6480 /* Set mode64 for an operand. */
6481 if (i
.suffix
== QWORD_MNEM_SUFFIX
6482 && flag_code
== CODE_64BIT
6483 && !i
.tm
.opcode_modifier
.norex64
6484 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6486 && ! (i
.operands
== 2
6487 && i
.tm
.base_opcode
== 0x90
6488 && i
.tm
.extension_opcode
== None
6489 && i
.types
[0].bitfield
.acc
&& i
.types
[0].bitfield
.qword
6490 && i
.types
[1].bitfield
.acc
&& i
.types
[1].bitfield
.qword
))
6496 if (i
.reg_operands
!= 0
6498 && i
.tm
.opcode_modifier
.addrprefixopreg
6499 && !i
.tm
.opcode_modifier
.immext
)
6501 /* Check invalid register operand when the address size override
6502 prefix changes the size of register operands. */
6504 enum { need_word
, need_dword
, need_qword
} need
;
6506 if (flag_code
== CODE_32BIT
)
6507 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6510 if (i
.prefix
[ADDR_PREFIX
])
6513 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6516 for (op
= 0; op
< i
.operands
; op
++)
6517 if (i
.types
[op
].bitfield
.reg
6518 && ((need
== need_word
6519 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6520 || (need
== need_dword
6521 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6522 || (need
== need_qword
6523 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6525 as_bad (_("invalid register operand size for `%s'"),
6535 check_byte_reg (void)
6539 for (op
= i
.operands
; --op
>= 0;)
6541 /* Skip non-register operands. */
6542 if (!i
.types
[op
].bitfield
.reg
)
6545 /* If this is an eight bit register, it's OK. If it's the 16 or
6546 32 bit version of an eight bit register, we will just use the
6547 low portion, and that's OK too. */
6548 if (i
.types
[op
].bitfield
.byte
)
6551 /* I/O port address operands are OK too. */
6552 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
6555 /* crc32 doesn't generate this warning. */
6556 if (i
.tm
.base_opcode
== 0xf20f38f0)
6559 if ((i
.types
[op
].bitfield
.word
6560 || i
.types
[op
].bitfield
.dword
6561 || i
.types
[op
].bitfield
.qword
)
6562 && i
.op
[op
].regs
->reg_num
< 4
6563 /* Prohibit these changes in 64bit mode, since the lowering
6564 would be more complicated. */
6565 && flag_code
!= CODE_64BIT
)
6567 #if REGISTER_WARNINGS
6568 if (!quiet_warnings
)
6569 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6571 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6572 ? REGNAM_AL
- REGNAM_AX
6573 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6575 i
.op
[op
].regs
->reg_name
,
6580 /* Any other register is bad. */
6581 if (i
.types
[op
].bitfield
.reg
6582 || i
.types
[op
].bitfield
.regmmx
6583 || i
.types
[op
].bitfield
.regsimd
6584 || i
.types
[op
].bitfield
.sreg
6585 || i
.types
[op
].bitfield
.control
6586 || i
.types
[op
].bitfield
.debug
6587 || i
.types
[op
].bitfield
.test
)
6589 as_bad (_("`%s%s' not allowed with `%s%c'"),
6591 i
.op
[op
].regs
->reg_name
,
6601 check_long_reg (void)
6605 for (op
= i
.operands
; --op
>= 0;)
6606 /* Skip non-register operands. */
6607 if (!i
.types
[op
].bitfield
.reg
)
6609 /* Reject eight bit registers, except where the template requires
6610 them. (eg. movzb) */
6611 else if (i
.types
[op
].bitfield
.byte
6612 && (i
.tm
.operand_types
[op
].bitfield
.reg
6613 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6614 && (i
.tm
.operand_types
[op
].bitfield
.word
6615 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6617 as_bad (_("`%s%s' not allowed with `%s%c'"),
6619 i
.op
[op
].regs
->reg_name
,
6624 /* Warn if the e prefix on a general reg is missing. */
6625 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6626 && i
.types
[op
].bitfield
.word
6627 && (i
.tm
.operand_types
[op
].bitfield
.reg
6628 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6629 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6631 /* Prohibit these changes in the 64bit mode, since the
6632 lowering is more complicated. */
6633 if (flag_code
== CODE_64BIT
)
6635 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6636 register_prefix
, i
.op
[op
].regs
->reg_name
,
6640 #if REGISTER_WARNINGS
6641 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6643 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6644 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6647 /* Warn if the r prefix on a general reg is present. */
6648 else if (i
.types
[op
].bitfield
.qword
6649 && (i
.tm
.operand_types
[op
].bitfield
.reg
6650 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6651 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6654 && i
.tm
.opcode_modifier
.toqword
6655 && !i
.types
[0].bitfield
.regsimd
)
6657 /* Convert to QWORD. We want REX byte. */
6658 i
.suffix
= QWORD_MNEM_SUFFIX
;
6662 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6663 register_prefix
, i
.op
[op
].regs
->reg_name
,
6672 check_qword_reg (void)
6676 for (op
= i
.operands
; --op
>= 0; )
6677 /* Skip non-register operands. */
6678 if (!i
.types
[op
].bitfield
.reg
)
6680 /* Reject eight bit registers, except where the template requires
6681 them. (eg. movzb) */
6682 else if (i
.types
[op
].bitfield
.byte
6683 && (i
.tm
.operand_types
[op
].bitfield
.reg
6684 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6685 && (i
.tm
.operand_types
[op
].bitfield
.word
6686 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6688 as_bad (_("`%s%s' not allowed with `%s%c'"),
6690 i
.op
[op
].regs
->reg_name
,
6695 /* Warn if the r prefix on a general reg is missing. */
6696 else if ((i
.types
[op
].bitfield
.word
6697 || i
.types
[op
].bitfield
.dword
)
6698 && (i
.tm
.operand_types
[op
].bitfield
.reg
6699 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6700 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6702 /* Prohibit these changes in the 64bit mode, since the
6703 lowering is more complicated. */
6705 && i
.tm
.opcode_modifier
.todword
6706 && !i
.types
[0].bitfield
.regsimd
)
6708 /* Convert to DWORD. We don't want REX byte. */
6709 i
.suffix
= LONG_MNEM_SUFFIX
;
6713 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6714 register_prefix
, i
.op
[op
].regs
->reg_name
,
6723 check_word_reg (void)
6726 for (op
= i
.operands
; --op
>= 0;)
6727 /* Skip non-register operands. */
6728 if (!i
.types
[op
].bitfield
.reg
)
6730 /* Reject eight bit registers, except where the template requires
6731 them. (eg. movzb) */
6732 else if (i
.types
[op
].bitfield
.byte
6733 && (i
.tm
.operand_types
[op
].bitfield
.reg
6734 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6735 && (i
.tm
.operand_types
[op
].bitfield
.word
6736 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6738 as_bad (_("`%s%s' not allowed with `%s%c'"),
6740 i
.op
[op
].regs
->reg_name
,
6745 /* Warn if the e or r prefix on a general reg is present. */
6746 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6747 && (i
.types
[op
].bitfield
.dword
6748 || i
.types
[op
].bitfield
.qword
)
6749 && (i
.tm
.operand_types
[op
].bitfield
.reg
6750 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6751 && i
.tm
.operand_types
[op
].bitfield
.word
)
6753 /* Prohibit these changes in the 64bit mode, since the
6754 lowering is more complicated. */
6755 if (flag_code
== CODE_64BIT
)
6757 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6758 register_prefix
, i
.op
[op
].regs
->reg_name
,
6762 #if REGISTER_WARNINGS
6763 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6765 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6766 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6773 update_imm (unsigned int j
)
6775 i386_operand_type overlap
= i
.types
[j
];
6776 if ((overlap
.bitfield
.imm8
6777 || overlap
.bitfield
.imm8s
6778 || overlap
.bitfield
.imm16
6779 || overlap
.bitfield
.imm32
6780 || overlap
.bitfield
.imm32s
6781 || overlap
.bitfield
.imm64
)
6782 && !operand_type_equal (&overlap
, &imm8
)
6783 && !operand_type_equal (&overlap
, &imm8s
)
6784 && !operand_type_equal (&overlap
, &imm16
)
6785 && !operand_type_equal (&overlap
, &imm32
)
6786 && !operand_type_equal (&overlap
, &imm32s
)
6787 && !operand_type_equal (&overlap
, &imm64
))
6791 i386_operand_type temp
;
6793 operand_type_set (&temp
, 0);
6794 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6796 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6797 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6799 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6800 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6801 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6803 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6804 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6807 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6810 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6811 || operand_type_equal (&overlap
, &imm16_32
)
6812 || operand_type_equal (&overlap
, &imm16_32s
))
6814 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6819 if (!operand_type_equal (&overlap
, &imm8
)
6820 && !operand_type_equal (&overlap
, &imm8s
)
6821 && !operand_type_equal (&overlap
, &imm16
)
6822 && !operand_type_equal (&overlap
, &imm32
)
6823 && !operand_type_equal (&overlap
, &imm32s
)
6824 && !operand_type_equal (&overlap
, &imm64
))
6826 as_bad (_("no instruction mnemonic suffix given; "
6827 "can't determine immediate size"));
6831 i
.types
[j
] = overlap
;
6841 /* Update the first 2 immediate operands. */
6842 n
= i
.operands
> 2 ? 2 : i
.operands
;
6845 for (j
= 0; j
< n
; j
++)
6846 if (update_imm (j
) == 0)
6849 /* The 3rd operand can't be immediate operand. */
6850 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6857 process_operands (void)
6859 /* Default segment register this instruction will use for memory
6860 accesses. 0 means unknown. This is only for optimizing out
6861 unnecessary segment overrides. */
6862 const seg_entry
*default_seg
= 0;
6864 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6866 unsigned int dupl
= i
.operands
;
6867 unsigned int dest
= dupl
- 1;
6870 /* The destination must be an xmm register. */
6871 gas_assert (i
.reg_operands
6872 && MAX_OPERANDS
> dupl
6873 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6875 if (i
.tm
.operand_types
[0].bitfield
.acc
6876 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6878 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6880 /* Keep xmm0 for instructions with VEX prefix and 3
6882 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6883 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6888 /* We remove the first xmm0 and keep the number of
6889 operands unchanged, which in fact duplicates the
6891 for (j
= 1; j
< i
.operands
; j
++)
6893 i
.op
[j
- 1] = i
.op
[j
];
6894 i
.types
[j
- 1] = i
.types
[j
];
6895 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6896 i
.flags
[j
- 1] = i
.flags
[j
];
6900 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6902 gas_assert ((MAX_OPERANDS
- 1) > dupl
6903 && (i
.tm
.opcode_modifier
.vexsources
6906 /* Add the implicit xmm0 for instructions with VEX prefix
6908 for (j
= i
.operands
; j
> 0; j
--)
6910 i
.op
[j
] = i
.op
[j
- 1];
6911 i
.types
[j
] = i
.types
[j
- 1];
6912 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6913 i
.flags
[j
] = i
.flags
[j
- 1];
6916 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6917 i
.types
[0] = regxmm
;
6918 i
.tm
.operand_types
[0] = regxmm
;
6921 i
.reg_operands
+= 2;
6926 i
.op
[dupl
] = i
.op
[dest
];
6927 i
.types
[dupl
] = i
.types
[dest
];
6928 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6929 i
.flags
[dupl
] = i
.flags
[dest
];
6938 i
.op
[dupl
] = i
.op
[dest
];
6939 i
.types
[dupl
] = i
.types
[dest
];
6940 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6941 i
.flags
[dupl
] = i
.flags
[dest
];
6944 if (i
.tm
.opcode_modifier
.immext
)
6947 else if (i
.tm
.operand_types
[0].bitfield
.acc
6948 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6952 for (j
= 1; j
< i
.operands
; j
++)
6954 i
.op
[j
- 1] = i
.op
[j
];
6955 i
.types
[j
- 1] = i
.types
[j
];
6957 /* We need to adjust fields in i.tm since they are used by
6958 build_modrm_byte. */
6959 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6961 i
.flags
[j
- 1] = i
.flags
[j
];
6968 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6970 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6972 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6973 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6974 regnum
= register_number (i
.op
[1].regs
);
6975 first_reg_in_group
= regnum
& ~3;
6976 last_reg_in_group
= first_reg_in_group
+ 3;
6977 if (regnum
!= first_reg_in_group
)
6978 as_warn (_("source register `%s%s' implicitly denotes"
6979 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6980 register_prefix
, i
.op
[1].regs
->reg_name
,
6981 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6982 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6985 else if (i
.tm
.opcode_modifier
.regkludge
)
6987 /* The imul $imm, %reg instruction is converted into
6988 imul $imm, %reg, %reg, and the clr %reg instruction
6989 is converted into xor %reg, %reg. */
6991 unsigned int first_reg_op
;
6993 if (operand_type_check (i
.types
[0], reg
))
6997 /* Pretend we saw the extra register operand. */
6998 gas_assert (i
.reg_operands
== 1
6999 && i
.op
[first_reg_op
+ 1].regs
== 0);
7000 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7001 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7006 if (i
.tm
.opcode_modifier
.shortform
)
7008 if (i
.types
[0].bitfield
.sreg
)
7010 if (flag_code
!= CODE_64BIT
7011 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7012 && i
.op
[0].regs
->reg_num
== 1
7013 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7014 && i
.op
[0].regs
->reg_num
< 4)
7016 as_bad (_("you can't `%s %s%s'"),
7017 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7020 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7022 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7023 i
.tm
.opcode_length
= 2;
7025 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7029 /* The register or float register operand is in operand
7033 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
7034 || operand_type_check (i
.types
[0], reg
))
7038 /* Register goes in low 3 bits of opcode. */
7039 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7040 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7042 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7044 /* Warn about some common errors, but press on regardless.
7045 The first case can be generated by gcc (<= 2.8.1). */
7046 if (i
.operands
== 2)
7048 /* Reversed arguments on faddp, fsubp, etc. */
7049 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7050 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7051 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7055 /* Extraneous `l' suffix on fp insn. */
7056 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7057 register_prefix
, i
.op
[0].regs
->reg_name
);
7062 else if (i
.tm
.opcode_modifier
.modrm
)
7064 /* The opcode is completed (modulo i.tm.extension_opcode which
7065 must be put into the modrm byte). Now, we make the modrm and
7066 index base bytes based on all the info we've collected. */
7068 default_seg
= build_modrm_byte ();
7070 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7074 else if (i
.tm
.opcode_modifier
.isstring
)
7076 /* For the string instructions that allow a segment override
7077 on one of their operands, the default segment is ds. */
7081 if (i
.tm
.base_opcode
== 0x8d /* lea */
7084 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7086 /* If a segment was explicitly specified, and the specified segment
7087 is not the default, use an opcode prefix to select it. If we
7088 never figured out what the default segment is, then default_seg
7089 will be zero at this point, and the specified segment prefix will
7091 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7093 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7099 static const seg_entry
*
7100 build_modrm_byte (void)
7102 const seg_entry
*default_seg
= 0;
7103 unsigned int source
, dest
;
7106 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7109 unsigned int nds
, reg_slot
;
7112 dest
= i
.operands
- 1;
7115 /* There are 2 kinds of instructions:
7116 1. 5 operands: 4 register operands or 3 register operands
7117 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7118 VexW0 or VexW1. The destination must be either XMM, YMM or
7120 2. 4 operands: 4 register operands or 3 register operands
7121 plus 1 memory operand, with VexXDS. */
7122 gas_assert ((i
.reg_operands
== 4
7123 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7124 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7125 && i
.tm
.opcode_modifier
.vexw
7126 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
);
7128 /* If VexW1 is set, the first non-immediate operand is the source and
7129 the second non-immediate one is encoded in the immediate operand. */
7130 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7132 source
= i
.imm_operands
;
7133 reg_slot
= i
.imm_operands
+ 1;
7137 source
= i
.imm_operands
+ 1;
7138 reg_slot
= i
.imm_operands
;
7141 if (i
.imm_operands
== 0)
7143 /* When there is no immediate operand, generate an 8bit
7144 immediate operand to encode the first operand. */
7145 exp
= &im_expressions
[i
.imm_operands
++];
7146 i
.op
[i
.operands
].imms
= exp
;
7147 i
.types
[i
.operands
] = imm8
;
7150 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7151 exp
->X_op
= O_constant
;
7152 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7153 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7157 gas_assert (i
.imm_operands
== 1);
7158 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7159 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7161 /* Turn on Imm8 again so that output_imm will generate it. */
7162 i
.types
[0].bitfield
.imm8
= 1;
7164 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
7165 i
.op
[0].imms
->X_add_number
7166 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7167 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7170 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
7171 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7176 /* i.reg_operands MUST be the number of real register operands;
7177 implicit registers do not count. If there are 3 register
7178 operands, it must be a instruction with VexNDS. For a
7179 instruction with VexNDD, the destination register is encoded
7180 in VEX prefix. If there are 4 register operands, it must be
7181 a instruction with VEX prefix and 3 sources. */
7182 if (i
.mem_operands
== 0
7183 && ((i
.reg_operands
== 2
7184 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7185 || (i
.reg_operands
== 3
7186 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7187 || (i
.reg_operands
== 4 && vex_3_sources
)))
7195 /* When there are 3 operands, one of them may be immediate,
7196 which may be the first or the last operand. Otherwise,
7197 the first operand must be shift count register (cl) or it
7198 is an instruction with VexNDS. */
7199 gas_assert (i
.imm_operands
== 1
7200 || (i
.imm_operands
== 0
7201 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7202 || i
.types
[0].bitfield
.shiftcount
)));
7203 if (operand_type_check (i
.types
[0], imm
)
7204 || i
.types
[0].bitfield
.shiftcount
)
7210 /* When there are 4 operands, the first two must be 8bit
7211 immediate operands. The source operand will be the 3rd
7214 For instructions with VexNDS, if the first operand
7215 an imm8, the source operand is the 2nd one. If the last
7216 operand is imm8, the source operand is the first one. */
7217 gas_assert ((i
.imm_operands
== 2
7218 && i
.types
[0].bitfield
.imm8
7219 && i
.types
[1].bitfield
.imm8
)
7220 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7221 && i
.imm_operands
== 1
7222 && (i
.types
[0].bitfield
.imm8
7223 || i
.types
[i
.operands
- 1].bitfield
.imm8
7225 if (i
.imm_operands
== 2)
7229 if (i
.types
[0].bitfield
.imm8
)
7236 if (is_evex_encoding (&i
.tm
))
7238 /* For EVEX instructions, when there are 5 operands, the
7239 first one must be immediate operand. If the second one
7240 is immediate operand, the source operand is the 3th
7241 one. If the last one is immediate operand, the source
7242 operand is the 2nd one. */
7243 gas_assert (i
.imm_operands
== 2
7244 && i
.tm
.opcode_modifier
.sae
7245 && operand_type_check (i
.types
[0], imm
));
7246 if (operand_type_check (i
.types
[1], imm
))
7248 else if (operand_type_check (i
.types
[4], imm
))
7262 /* RC/SAE operand could be between DEST and SRC. That happens
7263 when one operand is GPR and the other one is XMM/YMM/ZMM
7265 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7268 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7270 /* For instructions with VexNDS, the register-only source
7271 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7272 register. It is encoded in VEX prefix. */
7274 i386_operand_type op
;
7277 /* Check register-only source operand when two source
7278 operands are swapped. */
7279 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7280 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7288 op
= i
.tm
.operand_types
[vvvv
];
7289 if ((dest
+ 1) >= i
.operands
7290 || ((!op
.bitfield
.reg
7291 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7292 && !op
.bitfield
.regsimd
7293 && !operand_type_equal (&op
, ®mask
)))
7295 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7301 /* One of the register operands will be encoded in the i.rm.reg
7302 field, the other in the combined i.rm.mode and i.rm.regmem
7303 fields. If no form of this instruction supports a memory
7304 destination operand, then we assume the source operand may
7305 sometimes be a memory operand and so we need to store the
7306 destination in the i.rm.reg field. */
7307 if (!i
.tm
.opcode_modifier
.regmem
7308 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7310 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7311 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7312 if (i
.op
[dest
].regs
->reg_type
.bitfield
.regmmx
7313 || i
.op
[source
].regs
->reg_type
.bitfield
.regmmx
)
7314 i
.has_regmmx
= TRUE
;
7315 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.regsimd
7316 || i
.op
[source
].regs
->reg_type
.bitfield
.regsimd
)
7318 if (i
.types
[dest
].bitfield
.zmmword
7319 || i
.types
[source
].bitfield
.zmmword
)
7320 i
.has_regzmm
= TRUE
;
7321 else if (i
.types
[dest
].bitfield
.ymmword
7322 || i
.types
[source
].bitfield
.ymmword
)
7323 i
.has_regymm
= TRUE
;
7325 i
.has_regxmm
= TRUE
;
7327 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7329 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7331 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7333 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7338 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7339 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7340 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7342 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7344 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7346 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7349 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7351 if (!i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.control
)
7354 add_prefix (LOCK_PREFIX_OPCODE
);
7358 { /* If it's not 2 reg operands... */
7363 unsigned int fake_zero_displacement
= 0;
7366 for (op
= 0; op
< i
.operands
; op
++)
7367 if (i
.flags
[op
] & Operand_Mem
)
7369 gas_assert (op
< i
.operands
);
7371 if (i
.tm
.opcode_modifier
.vecsib
)
7373 if (i
.index_reg
->reg_num
== RegIZ
)
7376 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7379 i
.sib
.base
= NO_BASE_REGISTER
;
7380 i
.sib
.scale
= i
.log2_scale_factor
;
7381 i
.types
[op
].bitfield
.disp8
= 0;
7382 i
.types
[op
].bitfield
.disp16
= 0;
7383 i
.types
[op
].bitfield
.disp64
= 0;
7384 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7386 /* Must be 32 bit */
7387 i
.types
[op
].bitfield
.disp32
= 1;
7388 i
.types
[op
].bitfield
.disp32s
= 0;
7392 i
.types
[op
].bitfield
.disp32
= 0;
7393 i
.types
[op
].bitfield
.disp32s
= 1;
7396 i
.sib
.index
= i
.index_reg
->reg_num
;
7397 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7399 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7405 if (i
.base_reg
== 0)
7408 if (!i
.disp_operands
)
7409 fake_zero_displacement
= 1;
7410 if (i
.index_reg
== 0)
7412 i386_operand_type newdisp
;
7414 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7415 /* Operand is just <disp> */
7416 if (flag_code
== CODE_64BIT
)
7418 /* 64bit mode overwrites the 32bit absolute
7419 addressing by RIP relative addressing and
7420 absolute addressing is encoded by one of the
7421 redundant SIB forms. */
7422 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7423 i
.sib
.base
= NO_BASE_REGISTER
;
7424 i
.sib
.index
= NO_INDEX_REGISTER
;
7425 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7427 else if ((flag_code
== CODE_16BIT
)
7428 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7430 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7435 i
.rm
.regmem
= NO_BASE_REGISTER
;
7438 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7439 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7441 else if (!i
.tm
.opcode_modifier
.vecsib
)
7443 /* !i.base_reg && i.index_reg */
7444 if (i
.index_reg
->reg_num
== RegIZ
)
7445 i
.sib
.index
= NO_INDEX_REGISTER
;
7447 i
.sib
.index
= i
.index_reg
->reg_num
;
7448 i
.sib
.base
= NO_BASE_REGISTER
;
7449 i
.sib
.scale
= i
.log2_scale_factor
;
7450 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7451 i
.types
[op
].bitfield
.disp8
= 0;
7452 i
.types
[op
].bitfield
.disp16
= 0;
7453 i
.types
[op
].bitfield
.disp64
= 0;
7454 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7456 /* Must be 32 bit */
7457 i
.types
[op
].bitfield
.disp32
= 1;
7458 i
.types
[op
].bitfield
.disp32s
= 0;
7462 i
.types
[op
].bitfield
.disp32
= 0;
7463 i
.types
[op
].bitfield
.disp32s
= 1;
7465 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7469 /* RIP addressing for 64bit mode. */
7470 else if (i
.base_reg
->reg_num
== RegIP
)
7472 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7473 i
.rm
.regmem
= NO_BASE_REGISTER
;
7474 i
.types
[op
].bitfield
.disp8
= 0;
7475 i
.types
[op
].bitfield
.disp16
= 0;
7476 i
.types
[op
].bitfield
.disp32
= 0;
7477 i
.types
[op
].bitfield
.disp32s
= 1;
7478 i
.types
[op
].bitfield
.disp64
= 0;
7479 i
.flags
[op
] |= Operand_PCrel
;
7480 if (! i
.disp_operands
)
7481 fake_zero_displacement
= 1;
7483 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7485 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7486 switch (i
.base_reg
->reg_num
)
7489 if (i
.index_reg
== 0)
7491 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7492 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7496 if (i
.index_reg
== 0)
7499 if (operand_type_check (i
.types
[op
], disp
) == 0)
7501 /* fake (%bp) into 0(%bp) */
7502 i
.types
[op
].bitfield
.disp8
= 1;
7503 fake_zero_displacement
= 1;
7506 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7507 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7509 default: /* (%si) -> 4 or (%di) -> 5 */
7510 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7512 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7514 else /* i.base_reg and 32/64 bit mode */
7516 if (flag_code
== CODE_64BIT
7517 && operand_type_check (i
.types
[op
], disp
))
7519 i
.types
[op
].bitfield
.disp16
= 0;
7520 i
.types
[op
].bitfield
.disp64
= 0;
7521 if (i
.prefix
[ADDR_PREFIX
] == 0)
7523 i
.types
[op
].bitfield
.disp32
= 0;
7524 i
.types
[op
].bitfield
.disp32s
= 1;
7528 i
.types
[op
].bitfield
.disp32
= 1;
7529 i
.types
[op
].bitfield
.disp32s
= 0;
7533 if (!i
.tm
.opcode_modifier
.vecsib
)
7534 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7535 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7537 i
.sib
.base
= i
.base_reg
->reg_num
;
7538 /* x86-64 ignores REX prefix bit here to avoid decoder
7540 if (!(i
.base_reg
->reg_flags
& RegRex
)
7541 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7542 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7544 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7546 fake_zero_displacement
= 1;
7547 i
.types
[op
].bitfield
.disp8
= 1;
7549 i
.sib
.scale
= i
.log2_scale_factor
;
7550 if (i
.index_reg
== 0)
7552 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7553 /* <disp>(%esp) becomes two byte modrm with no index
7554 register. We've already stored the code for esp
7555 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7556 Any base register besides %esp will not use the
7557 extra modrm byte. */
7558 i
.sib
.index
= NO_INDEX_REGISTER
;
7560 else if (!i
.tm
.opcode_modifier
.vecsib
)
7562 if (i
.index_reg
->reg_num
== RegIZ
)
7563 i
.sib
.index
= NO_INDEX_REGISTER
;
7565 i
.sib
.index
= i
.index_reg
->reg_num
;
7566 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7567 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7572 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7573 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7577 if (!fake_zero_displacement
7581 fake_zero_displacement
= 1;
7582 if (i
.disp_encoding
== disp_encoding_8bit
)
7583 i
.types
[op
].bitfield
.disp8
= 1;
7585 i
.types
[op
].bitfield
.disp32
= 1;
7587 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7591 if (fake_zero_displacement
)
7593 /* Fakes a zero displacement assuming that i.types[op]
7594 holds the correct displacement size. */
7597 gas_assert (i
.op
[op
].disps
== 0);
7598 exp
= &disp_expressions
[i
.disp_operands
++];
7599 i
.op
[op
].disps
= exp
;
7600 exp
->X_op
= O_constant
;
7601 exp
->X_add_number
= 0;
7602 exp
->X_add_symbol
= (symbolS
*) 0;
7603 exp
->X_op_symbol
= (symbolS
*) 0;
7611 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7613 if (operand_type_check (i
.types
[0], imm
))
7614 i
.vex
.register_specifier
= NULL
;
7617 /* VEX.vvvv encodes one of the sources when the first
7618 operand is not an immediate. */
7619 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7620 i
.vex
.register_specifier
= i
.op
[0].regs
;
7622 i
.vex
.register_specifier
= i
.op
[1].regs
;
7625 /* Destination is a XMM register encoded in the ModRM.reg
7627 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7628 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7631 /* ModRM.rm and VEX.B encodes the other source. */
7632 if (!i
.mem_operands
)
7636 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7637 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7639 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7641 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7645 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7647 i
.vex
.register_specifier
= i
.op
[2].regs
;
7648 if (!i
.mem_operands
)
7651 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7652 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7656 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7657 (if any) based on i.tm.extension_opcode. Again, we must be
7658 careful to make sure that segment/control/debug/test/MMX
7659 registers are coded into the i.rm.reg field. */
7660 else if (i
.reg_operands
)
7663 unsigned int vex_reg
= ~0;
7665 for (op
= 0; op
< i
.operands
; op
++)
7667 if (i
.types
[op
].bitfield
.reg
7668 || i
.types
[op
].bitfield
.regbnd
7669 || i
.types
[op
].bitfield
.regmask
7670 || i
.types
[op
].bitfield
.sreg
7671 || i
.types
[op
].bitfield
.control
7672 || i
.types
[op
].bitfield
.debug
7673 || i
.types
[op
].bitfield
.test
)
7675 if (i
.types
[op
].bitfield
.regsimd
)
7677 if (i
.types
[op
].bitfield
.zmmword
)
7678 i
.has_regzmm
= TRUE
;
7679 else if (i
.types
[op
].bitfield
.ymmword
)
7680 i
.has_regymm
= TRUE
;
7682 i
.has_regxmm
= TRUE
;
7685 if (i
.types
[op
].bitfield
.regmmx
)
7687 i
.has_regmmx
= TRUE
;
7694 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7696 /* For instructions with VexNDS, the register-only
7697 source operand is encoded in VEX prefix. */
7698 gas_assert (mem
!= (unsigned int) ~0);
7703 gas_assert (op
< i
.operands
);
7707 /* Check register-only source operand when two source
7708 operands are swapped. */
7709 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7710 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7714 gas_assert (mem
== (vex_reg
+ 1)
7715 && op
< i
.operands
);
7720 gas_assert (vex_reg
< i
.operands
);
7724 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7726 /* For instructions with VexNDD, the register destination
7727 is encoded in VEX prefix. */
7728 if (i
.mem_operands
== 0)
7730 /* There is no memory operand. */
7731 gas_assert ((op
+ 2) == i
.operands
);
7736 /* There are only 2 non-immediate operands. */
7737 gas_assert (op
< i
.imm_operands
+ 2
7738 && i
.operands
== i
.imm_operands
+ 2);
7739 vex_reg
= i
.imm_operands
+ 1;
7743 gas_assert (op
< i
.operands
);
7745 if (vex_reg
!= (unsigned int) ~0)
7747 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7749 if ((!type
->bitfield
.reg
7750 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7751 && !type
->bitfield
.regsimd
7752 && !operand_type_equal (type
, ®mask
))
7755 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7758 /* Don't set OP operand twice. */
7761 /* If there is an extension opcode to put here, the
7762 register number must be put into the regmem field. */
7763 if (i
.tm
.extension_opcode
!= None
)
7765 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7766 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7768 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7773 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7774 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7776 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7781 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7782 must set it to 3 to indicate this is a register operand
7783 in the regmem field. */
7784 if (!i
.mem_operands
)
7788 /* Fill in i.rm.reg field with extension opcode (if any). */
7789 if (i
.tm
.extension_opcode
!= None
)
7790 i
.rm
.reg
= i
.tm
.extension_opcode
;
7796 output_branch (void)
7802 relax_substateT subtype
;
7806 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7807 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7810 if (i
.prefix
[DATA_PREFIX
] != 0)
7816 /* Pentium4 branch hints. */
7817 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7818 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7823 if (i
.prefix
[REX_PREFIX
] != 0)
7829 /* BND prefixed jump. */
7830 if (i
.prefix
[BND_PREFIX
] != 0)
7832 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7836 if (i
.prefixes
!= 0 && !intel_syntax
)
7837 as_warn (_("skipping prefixes on this instruction"));
7839 /* It's always a symbol; End frag & setup for relax.
7840 Make sure there is enough room in this frag for the largest
7841 instruction we may generate in md_convert_frag. This is 2
7842 bytes for the opcode and room for the prefix and largest
7844 frag_grow (prefix
+ 2 + 4);
7845 /* Prefix and 1 opcode byte go in fr_fix. */
7846 p
= frag_more (prefix
+ 1);
7847 if (i
.prefix
[DATA_PREFIX
] != 0)
7848 *p
++ = DATA_PREFIX_OPCODE
;
7849 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7850 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7851 *p
++ = i
.prefix
[SEG_PREFIX
];
7852 if (i
.prefix
[REX_PREFIX
] != 0)
7853 *p
++ = i
.prefix
[REX_PREFIX
];
7854 *p
= i
.tm
.base_opcode
;
7856 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7857 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7858 else if (cpu_arch_flags
.bitfield
.cpui386
)
7859 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7861 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7864 sym
= i
.op
[0].disps
->X_add_symbol
;
7865 off
= i
.op
[0].disps
->X_add_number
;
7867 if (i
.op
[0].disps
->X_op
!= O_constant
7868 && i
.op
[0].disps
->X_op
!= O_symbol
)
7870 /* Handle complex expressions. */
7871 sym
= make_expr_symbol (i
.op
[0].disps
);
7875 /* 1 possible extra opcode + 4 byte displacement go in var part.
7876 Pass reloc in fr_var. */
7877 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7880 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7881 /* Return TRUE iff PLT32 relocation should be used for branching to
7885 need_plt32_p (symbolS
*s
)
7887 /* PLT32 relocation is ELF only. */
7892 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7893 krtld support it. */
7897 /* Since there is no need to prepare for PLT branch on x86-64, we
7898 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7899 be used as a marker for 32-bit PC-relative branches. */
7903 /* Weak or undefined symbol need PLT32 relocation. */
7904 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7907 /* Non-global symbol doesn't need PLT32 relocation. */
7908 if (! S_IS_EXTERNAL (s
))
7911 /* Other global symbols need PLT32 relocation. NB: Symbol with
7912 non-default visibilities are treated as normal global symbol
7913 so that PLT32 relocation can be used as a marker for 32-bit
7914 PC-relative branches. It is useful for linker relaxation. */
7925 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7927 if (i
.tm
.opcode_modifier
.jumpbyte
)
7929 /* This is a loop or jecxz type instruction. */
7931 if (i
.prefix
[ADDR_PREFIX
] != 0)
7933 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7936 /* Pentium4 branch hints. */
7937 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7938 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7940 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7949 if (flag_code
== CODE_16BIT
)
7952 if (i
.prefix
[DATA_PREFIX
] != 0)
7954 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7964 if (i
.prefix
[REX_PREFIX
] != 0)
7966 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7970 /* BND prefixed jump. */
7971 if (i
.prefix
[BND_PREFIX
] != 0)
7973 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7977 if (i
.prefixes
!= 0 && !intel_syntax
)
7978 as_warn (_("skipping prefixes on this instruction"));
7980 p
= frag_more (i
.tm
.opcode_length
+ size
);
7981 switch (i
.tm
.opcode_length
)
7984 *p
++ = i
.tm
.base_opcode
>> 8;
7987 *p
++ = i
.tm
.base_opcode
;
7993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7995 && jump_reloc
== NO_RELOC
7996 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7997 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8000 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8002 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8003 i
.op
[0].disps
, 1, jump_reloc
);
8005 /* All jumps handled here are signed, but don't use a signed limit
8006 check for 32 and 16 bit jumps as we want to allow wrap around at
8007 4G and 64k respectively. */
8009 fixP
->fx_signed
= 1;
8013 output_interseg_jump (void)
8021 if (flag_code
== CODE_16BIT
)
8025 if (i
.prefix
[DATA_PREFIX
] != 0)
8031 if (i
.prefix
[REX_PREFIX
] != 0)
8041 if (i
.prefixes
!= 0 && !intel_syntax
)
8042 as_warn (_("skipping prefixes on this instruction"));
8044 /* 1 opcode; 2 segment; offset */
8045 p
= frag_more (prefix
+ 1 + 2 + size
);
8047 if (i
.prefix
[DATA_PREFIX
] != 0)
8048 *p
++ = DATA_PREFIX_OPCODE
;
8050 if (i
.prefix
[REX_PREFIX
] != 0)
8051 *p
++ = i
.prefix
[REX_PREFIX
];
8053 *p
++ = i
.tm
.base_opcode
;
8054 if (i
.op
[1].imms
->X_op
== O_constant
)
8056 offsetT n
= i
.op
[1].imms
->X_add_number
;
8059 && !fits_in_unsigned_word (n
)
8060 && !fits_in_signed_word (n
))
8062 as_bad (_("16-bit jump out of range"));
8065 md_number_to_chars (p
, n
, size
);
8068 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8069 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8070 if (i
.op
[0].imms
->X_op
!= O_constant
)
8071 as_bad (_("can't handle non absolute segment in `%s'"),
8073 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8081 asection
*seg
= now_seg
;
8082 subsegT subseg
= now_subseg
;
8084 unsigned int alignment
, align_size_1
;
8085 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8086 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8087 unsigned int padding
;
8089 if (!IS_ELF
|| !x86_used_note
)
8092 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8094 /* The .note.gnu.property section layout:
8096 Field Length Contents
8099 n_descsz 4 The note descriptor size
8100 n_type 4 NT_GNU_PROPERTY_TYPE_0
8102 n_desc n_descsz The program property array
8106 /* Create the .note.gnu.property section. */
8107 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8108 bfd_set_section_flags (sec
,
8115 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8126 bfd_set_section_alignment (sec
, alignment
);
8127 elf_section_type (sec
) = SHT_NOTE
;
8129 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8131 isa_1_descsz_raw
= 4 + 4 + 4;
8132 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8133 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8135 feature_2_descsz_raw
= isa_1_descsz
;
8136 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8138 feature_2_descsz_raw
+= 4 + 4 + 4;
8139 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8140 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8143 descsz
= feature_2_descsz
;
8144 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8145 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8147 /* Write n_namsz. */
8148 md_number_to_chars (p
, (valueT
) 4, 4);
8150 /* Write n_descsz. */
8151 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8154 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8157 memcpy (p
+ 4 * 3, "GNU", 4);
8159 /* Write 4-byte type. */
8160 md_number_to_chars (p
+ 4 * 4,
8161 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8163 /* Write 4-byte data size. */
8164 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8166 /* Write 4-byte data. */
8167 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8169 /* Zero out paddings. */
8170 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8172 memset (p
+ 4 * 7, 0, padding
);
8174 /* Write 4-byte type. */
8175 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8176 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8178 /* Write 4-byte data size. */
8179 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8181 /* Write 4-byte data. */
8182 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8183 (valueT
) x86_feature_2_used
, 4);
8185 /* Zero out paddings. */
8186 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8188 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8190 /* We probably can't restore the current segment, for there likely
8193 subseg_set (seg
, subseg
);
8198 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8199 const char *frag_now_ptr
)
8201 unsigned int len
= 0;
8203 if (start_frag
!= frag_now
)
8205 const fragS
*fr
= start_frag
;
8210 } while (fr
&& fr
!= frag_now
);
8213 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8219 fragS
*insn_start_frag
;
8220 offsetT insn_start_off
;
8222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8223 if (IS_ELF
&& x86_used_note
)
8225 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8226 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8227 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8228 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8229 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8230 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8231 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8232 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8233 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8234 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8235 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8236 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8237 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8238 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8239 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8240 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8241 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8242 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8243 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8244 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8245 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8246 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8247 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8248 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8249 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8250 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8251 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8252 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8253 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8254 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8255 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8256 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8257 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8258 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8259 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8260 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8261 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8262 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8263 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8264 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8265 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8266 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8267 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8268 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8269 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8270 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8271 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8272 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8273 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8274 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8276 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8277 || i
.tm
.cpu_flags
.bitfield
.cpu287
8278 || i
.tm
.cpu_flags
.bitfield
.cpu387
8279 || i
.tm
.cpu_flags
.bitfield
.cpu687
8280 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8281 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8282 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8283 Xfence instructions. */
8284 if (i
.tm
.base_opcode
!= 0xf18
8285 && i
.tm
.base_opcode
!= 0xf0d
8286 && i
.tm
.base_opcode
!= 0xfaef8
8288 || i
.tm
.cpu_flags
.bitfield
.cpummx
8289 || i
.tm
.cpu_flags
.bitfield
.cpua3dnow
8290 || i
.tm
.cpu_flags
.bitfield
.cpua3dnowa
))
8291 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8293 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8295 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8297 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8298 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8299 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8300 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8301 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8302 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8303 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8304 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8305 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8309 /* Tie dwarf2 debug info to the address at the start of the insn.
8310 We can't do this after the insn has been output as the current
8311 frag may have been closed off. eg. by frag_var. */
8312 dwarf2_emit_insn (0);
8314 insn_start_frag
= frag_now
;
8315 insn_start_off
= frag_now_fix ();
8318 if (i
.tm
.opcode_modifier
.jump
)
8320 else if (i
.tm
.opcode_modifier
.jumpbyte
8321 || i
.tm
.opcode_modifier
.jumpdword
)
8323 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
8324 output_interseg_jump ();
8327 /* Output normal instructions here. */
8331 unsigned int prefix
;
8334 && (i
.tm
.base_opcode
== 0xfaee8
8335 || i
.tm
.base_opcode
== 0xfaef0
8336 || i
.tm
.base_opcode
== 0xfaef8))
8338 /* Encode lfence, mfence, and sfence as
8339 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8340 offsetT val
= 0x240483f0ULL
;
8342 md_number_to_chars (p
, val
, 5);
8346 /* Some processors fail on LOCK prefix. This options makes
8347 assembler ignore LOCK prefix and serves as a workaround. */
8348 if (omit_lock_prefix
)
8350 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8352 i
.prefix
[LOCK_PREFIX
] = 0;
8355 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8356 don't need the explicit prefix. */
8357 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8359 switch (i
.tm
.opcode_length
)
8362 if (i
.tm
.base_opcode
& 0xff000000)
8364 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8365 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8366 || prefix
!= REPE_PREFIX_OPCODE
8367 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8368 add_prefix (prefix
);
8372 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8374 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8375 add_prefix (prefix
);
8381 /* Check for pseudo prefixes. */
8382 as_bad_where (insn_start_frag
->fr_file
,
8383 insn_start_frag
->fr_line
,
8384 _("pseudo prefix without instruction"));
8390 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8391 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8392 R_X86_64_GOTTPOFF relocation so that linker can safely
8393 perform IE->LE optimization. */
8394 if (x86_elf_abi
== X86_64_X32_ABI
8396 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8397 && i
.prefix
[REX_PREFIX
] == 0)
8398 add_prefix (REX_OPCODE
);
8401 /* The prefix bytes. */
8402 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8404 FRAG_APPEND_1_CHAR (*q
);
8408 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8413 /* REX byte is encoded in VEX prefix. */
8417 FRAG_APPEND_1_CHAR (*q
);
8420 /* There should be no other prefixes for instructions
8425 /* For EVEX instructions i.vrex should become 0 after
8426 build_evex_prefix. For VEX instructions upper 16 registers
8427 aren't available, so VREX should be 0. */
8430 /* Now the VEX prefix. */
8431 p
= frag_more (i
.vex
.length
);
8432 for (j
= 0; j
< i
.vex
.length
; j
++)
8433 p
[j
] = i
.vex
.bytes
[j
];
8436 /* Now the opcode; be careful about word order here! */
8437 if (i
.tm
.opcode_length
== 1)
8439 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8443 switch (i
.tm
.opcode_length
)
8447 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8448 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8452 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8462 /* Put out high byte first: can't use md_number_to_chars! */
8463 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8464 *p
= i
.tm
.base_opcode
& 0xff;
8467 /* Now the modrm byte and sib byte (if present). */
8468 if (i
.tm
.opcode_modifier
.modrm
)
8470 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8473 /* If i.rm.regmem == ESP (4)
8474 && i.rm.mode != (Register mode)
8476 ==> need second modrm byte. */
8477 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8479 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8480 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8482 | i
.sib
.scale
<< 6));
8485 if (i
.disp_operands
)
8486 output_disp (insn_start_frag
, insn_start_off
);
8489 output_imm (insn_start_frag
, insn_start_off
);
8492 * frag_now_fix () returning plain abs_section_offset when we're in the
8493 * absolute section, and abs_section_offset not getting updated as data
8494 * gets added to the frag breaks the logic below.
8496 if (now_seg
!= absolute_section
)
8498 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8500 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8508 pi ("" /*line*/, &i
);
8510 #endif /* DEBUG386 */
8513 /* Return the size of the displacement operand N. */
8516 disp_size (unsigned int n
)
8520 if (i
.types
[n
].bitfield
.disp64
)
8522 else if (i
.types
[n
].bitfield
.disp8
)
8524 else if (i
.types
[n
].bitfield
.disp16
)
8529 /* Return the size of the immediate operand N. */
8532 imm_size (unsigned int n
)
8535 if (i
.types
[n
].bitfield
.imm64
)
8537 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8539 else if (i
.types
[n
].bitfield
.imm16
)
8545 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8550 for (n
= 0; n
< i
.operands
; n
++)
8552 if (operand_type_check (i
.types
[n
], disp
))
8554 if (i
.op
[n
].disps
->X_op
== O_constant
)
8556 int size
= disp_size (n
);
8557 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8559 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8561 p
= frag_more (size
);
8562 md_number_to_chars (p
, val
, size
);
8566 enum bfd_reloc_code_real reloc_type
;
8567 int size
= disp_size (n
);
8568 int sign
= i
.types
[n
].bitfield
.disp32s
;
8569 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8572 /* We can't have 8 bit displacement here. */
8573 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8575 /* The PC relative address is computed relative
8576 to the instruction boundary, so in case immediate
8577 fields follows, we need to adjust the value. */
8578 if (pcrel
&& i
.imm_operands
)
8583 for (n1
= 0; n1
< i
.operands
; n1
++)
8584 if (operand_type_check (i
.types
[n1
], imm
))
8586 /* Only one immediate is allowed for PC
8587 relative address. */
8588 gas_assert (sz
== 0);
8590 i
.op
[n
].disps
->X_add_number
-= sz
;
8592 /* We should find the immediate. */
8593 gas_assert (sz
!= 0);
8596 p
= frag_more (size
);
8597 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
8599 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
8600 && (((reloc_type
== BFD_RELOC_32
8601 || reloc_type
== BFD_RELOC_X86_64_32S
8602 || (reloc_type
== BFD_RELOC_64
8604 && (i
.op
[n
].disps
->X_op
== O_symbol
8605 || (i
.op
[n
].disps
->X_op
== O_add
8606 && ((symbol_get_value_expression
8607 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
8609 || reloc_type
== BFD_RELOC_32_PCREL
))
8613 reloc_type
= BFD_RELOC_386_GOTPC
;
8614 i
.op
[n
].imms
->X_add_number
+=
8615 encoding_length (insn_start_frag
, insn_start_off
, p
);
8617 else if (reloc_type
== BFD_RELOC_64
)
8618 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8620 /* Don't do the adjustment for x86-64, as there
8621 the pcrel addressing is relative to the _next_
8622 insn, and that is taken care of in other code. */
8623 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8625 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
8626 size
, i
.op
[n
].disps
, pcrel
,
8628 /* Check for "call/jmp *mem", "mov mem, %reg",
8629 "test %reg, mem" and "binop mem, %reg" where binop
8630 is one of adc, add, and, cmp, or, sbb, sub, xor
8631 instructions without data prefix. Always generate
8632 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8633 if (i
.prefix
[DATA_PREFIX
] == 0
8634 && (generate_relax_relocations
8637 && i
.rm
.regmem
== 5))
8639 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
8640 && ((i
.operands
== 1
8641 && i
.tm
.base_opcode
== 0xff
8642 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
8644 && (i
.tm
.base_opcode
== 0x8b
8645 || i
.tm
.base_opcode
== 0x85
8646 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
8650 fixP
->fx_tcbit
= i
.rex
!= 0;
8652 && (i
.base_reg
->reg_num
== RegIP
))
8653 fixP
->fx_tcbit2
= 1;
8656 fixP
->fx_tcbit2
= 1;
8664 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
8669 for (n
= 0; n
< i
.operands
; n
++)
8671 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8672 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
8675 if (operand_type_check (i
.types
[n
], imm
))
8677 if (i
.op
[n
].imms
->X_op
== O_constant
)
8679 int size
= imm_size (n
);
8682 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
8684 p
= frag_more (size
);
8685 md_number_to_chars (p
, val
, size
);
8689 /* Not absolute_section.
8690 Need a 32-bit fixup (don't support 8bit
8691 non-absolute imms). Try to support other
8693 enum bfd_reloc_code_real reloc_type
;
8694 int size
= imm_size (n
);
8697 if (i
.types
[n
].bitfield
.imm32s
8698 && (i
.suffix
== QWORD_MNEM_SUFFIX
8699 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
8704 p
= frag_more (size
);
8705 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
8707 /* This is tough to explain. We end up with this one if we
8708 * have operands that look like
8709 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8710 * obtain the absolute address of the GOT, and it is strongly
8711 * preferable from a performance point of view to avoid using
8712 * a runtime relocation for this. The actual sequence of
8713 * instructions often look something like:
8718 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8720 * The call and pop essentially return the absolute address
8721 * of the label .L66 and store it in %ebx. The linker itself
8722 * will ultimately change the first operand of the addl so
8723 * that %ebx points to the GOT, but to keep things simple, the
8724 * .o file must have this operand set so that it generates not
8725 * the absolute address of .L66, but the absolute address of
8726 * itself. This allows the linker itself simply treat a GOTPC
8727 * relocation as asking for a pcrel offset to the GOT to be
8728 * added in, and the addend of the relocation is stored in the
8729 * operand field for the instruction itself.
8731 * Our job here is to fix the operand so that it would add
8732 * the correct offset so that %ebx would point to itself. The
8733 * thing that is tricky is that .-.L66 will point to the
8734 * beginning of the instruction, so we need to further modify
8735 * the operand so that it will point to itself. There are
8736 * other cases where you have something like:
8738 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8740 * and here no correction would be required. Internally in
8741 * the assembler we treat operands of this form as not being
8742 * pcrel since the '.' is explicitly mentioned, and I wonder
8743 * whether it would simplify matters to do it this way. Who
8744 * knows. In earlier versions of the PIC patches, the
8745 * pcrel_adjust field was used to store the correction, but
8746 * since the expression is not pcrel, I felt it would be
8747 * confusing to do it this way. */
8749 if ((reloc_type
== BFD_RELOC_32
8750 || reloc_type
== BFD_RELOC_X86_64_32S
8751 || reloc_type
== BFD_RELOC_64
)
8753 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
8754 && (i
.op
[n
].imms
->X_op
== O_symbol
8755 || (i
.op
[n
].imms
->X_op
== O_add
8756 && ((symbol_get_value_expression
8757 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
8761 reloc_type
= BFD_RELOC_386_GOTPC
;
8763 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
8765 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
8766 i
.op
[n
].imms
->X_add_number
+=
8767 encoding_length (insn_start_frag
, insn_start_off
, p
);
8769 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8770 i
.op
[n
].imms
, 0, reloc_type
);
8776 /* x86_cons_fix_new is called via the expression parsing code when a
8777 reloc is needed. We use this hook to get the correct .got reloc. */
8778 static int cons_sign
= -1;
8781 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
8782 expressionS
*exp
, bfd_reloc_code_real_type r
)
8784 r
= reloc (len
, 0, cons_sign
, r
);
8787 if (exp
->X_op
== O_secrel
)
8789 exp
->X_op
= O_symbol
;
8790 r
= BFD_RELOC_32_SECREL
;
8794 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8797 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8798 purpose of the `.dc.a' internal pseudo-op. */
8801 x86_address_bytes (void)
8803 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8805 return stdoutput
->arch_info
->bits_per_address
/ 8;
8808 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8810 # define lex_got(reloc, adjust, types) NULL
8812 /* Parse operands of the form
8813 <symbol>@GOTOFF+<nnn>
8814 and similar .plt or .got references.
8816 If we find one, set up the correct relocation in RELOC and copy the
8817 input string, minus the `@GOTOFF' into a malloc'd buffer for
8818 parsing by the calling routine. Return this buffer, and if ADJUST
8819 is non-null set it to the length of the string we removed from the
8820 input line. Otherwise return NULL. */
8822 lex_got (enum bfd_reloc_code_real
*rel
,
8824 i386_operand_type
*types
)
8826 /* Some of the relocations depend on the size of what field is to
8827 be relocated. But in our callers i386_immediate and i386_displacement
8828 we don't yet know the operand size (this will be set by insn
8829 matching). Hence we record the word32 relocation here,
8830 and adjust the reloc according to the real size in reloc(). */
8831 static const struct {
8834 const enum bfd_reloc_code_real rel
[2];
8835 const i386_operand_type types64
;
8837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8838 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8840 OPERAND_TYPE_IMM32_64
},
8842 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8843 BFD_RELOC_X86_64_PLTOFF64
},
8844 OPERAND_TYPE_IMM64
},
8845 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8846 BFD_RELOC_X86_64_PLT32
},
8847 OPERAND_TYPE_IMM32_32S_DISP32
},
8848 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8849 BFD_RELOC_X86_64_GOTPLT64
},
8850 OPERAND_TYPE_IMM64_DISP64
},
8851 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8852 BFD_RELOC_X86_64_GOTOFF64
},
8853 OPERAND_TYPE_IMM64_DISP64
},
8854 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8855 BFD_RELOC_X86_64_GOTPCREL
},
8856 OPERAND_TYPE_IMM32_32S_DISP32
},
8857 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8858 BFD_RELOC_X86_64_TLSGD
},
8859 OPERAND_TYPE_IMM32_32S_DISP32
},
8860 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8861 _dummy_first_bfd_reloc_code_real
},
8862 OPERAND_TYPE_NONE
},
8863 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8864 BFD_RELOC_X86_64_TLSLD
},
8865 OPERAND_TYPE_IMM32_32S_DISP32
},
8866 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8867 BFD_RELOC_X86_64_GOTTPOFF
},
8868 OPERAND_TYPE_IMM32_32S_DISP32
},
8869 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8870 BFD_RELOC_X86_64_TPOFF32
},
8871 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8872 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8873 _dummy_first_bfd_reloc_code_real
},
8874 OPERAND_TYPE_NONE
},
8875 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8876 BFD_RELOC_X86_64_DTPOFF32
},
8877 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8878 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8879 _dummy_first_bfd_reloc_code_real
},
8880 OPERAND_TYPE_NONE
},
8881 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8882 _dummy_first_bfd_reloc_code_real
},
8883 OPERAND_TYPE_NONE
},
8884 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8885 BFD_RELOC_X86_64_GOT32
},
8886 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8887 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8888 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8889 OPERAND_TYPE_IMM32_32S_DISP32
},
8890 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8891 BFD_RELOC_X86_64_TLSDESC_CALL
},
8892 OPERAND_TYPE_IMM32_32S_DISP32
},
8897 #if defined (OBJ_MAYBE_ELF)
8902 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8903 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8906 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8908 int len
= gotrel
[j
].len
;
8909 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8911 if (gotrel
[j
].rel
[object_64bit
] != 0)
8914 char *tmpbuf
, *past_reloc
;
8916 *rel
= gotrel
[j
].rel
[object_64bit
];
8920 if (flag_code
!= CODE_64BIT
)
8922 types
->bitfield
.imm32
= 1;
8923 types
->bitfield
.disp32
= 1;
8926 *types
= gotrel
[j
].types64
;
8929 if (j
!= 0 && GOT_symbol
== NULL
)
8930 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8932 /* The length of the first part of our input line. */
8933 first
= cp
- input_line_pointer
;
8935 /* The second part goes from after the reloc token until
8936 (and including) an end_of_line char or comma. */
8937 past_reloc
= cp
+ 1 + len
;
8939 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8941 second
= cp
+ 1 - past_reloc
;
8943 /* Allocate and copy string. The trailing NUL shouldn't
8944 be necessary, but be safe. */
8945 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8946 memcpy (tmpbuf
, input_line_pointer
, first
);
8947 if (second
!= 0 && *past_reloc
!= ' ')
8948 /* Replace the relocation token with ' ', so that
8949 errors like foo@GOTOFF1 will be detected. */
8950 tmpbuf
[first
++] = ' ';
8952 /* Increment length by 1 if the relocation token is
8957 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8958 tmpbuf
[first
+ second
] = '\0';
8962 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8963 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8968 /* Might be a symbol version string. Don't as_bad here. */
8977 /* Parse operands of the form
8978 <symbol>@SECREL32+<nnn>
8980 If we find one, set up the correct relocation in RELOC and copy the
8981 input string, minus the `@SECREL32' into a malloc'd buffer for
8982 parsing by the calling routine. Return this buffer, and if ADJUST
8983 is non-null set it to the length of the string we removed from the
8984 input line. Otherwise return NULL.
8986 This function is copied from the ELF version above adjusted for PE targets. */
8989 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8990 int *adjust ATTRIBUTE_UNUSED
,
8991 i386_operand_type
*types
)
8997 const enum bfd_reloc_code_real rel
[2];
8998 const i386_operand_type types64
;
9002 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9003 BFD_RELOC_32_SECREL
},
9004 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9010 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9011 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9014 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9016 int len
= gotrel
[j
].len
;
9018 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9020 if (gotrel
[j
].rel
[object_64bit
] != 0)
9023 char *tmpbuf
, *past_reloc
;
9025 *rel
= gotrel
[j
].rel
[object_64bit
];
9031 if (flag_code
!= CODE_64BIT
)
9033 types
->bitfield
.imm32
= 1;
9034 types
->bitfield
.disp32
= 1;
9037 *types
= gotrel
[j
].types64
;
9040 /* The length of the first part of our input line. */
9041 first
= cp
- input_line_pointer
;
9043 /* The second part goes from after the reloc token until
9044 (and including) an end_of_line char or comma. */
9045 past_reloc
= cp
+ 1 + len
;
9047 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9049 second
= cp
+ 1 - past_reloc
;
9051 /* Allocate and copy string. The trailing NUL shouldn't
9052 be necessary, but be safe. */
9053 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9054 memcpy (tmpbuf
, input_line_pointer
, first
);
9055 if (second
!= 0 && *past_reloc
!= ' ')
9056 /* Replace the relocation token with ' ', so that
9057 errors like foo@SECLREL321 will be detected. */
9058 tmpbuf
[first
++] = ' ';
9059 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9060 tmpbuf
[first
+ second
] = '\0';
9064 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9065 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9070 /* Might be a symbol version string. Don't as_bad here. */
9076 bfd_reloc_code_real_type
9077 x86_cons (expressionS
*exp
, int size
)
9079 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9081 intel_syntax
= -intel_syntax
;
9084 if (size
== 4 || (object_64bit
&& size
== 8))
9086 /* Handle @GOTOFF and the like in an expression. */
9088 char *gotfree_input_line
;
9091 save
= input_line_pointer
;
9092 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9093 if (gotfree_input_line
)
9094 input_line_pointer
= gotfree_input_line
;
9098 if (gotfree_input_line
)
9100 /* expression () has merrily parsed up to the end of line,
9101 or a comma - in the wrong buffer. Transfer how far
9102 input_line_pointer has moved to the right buffer. */
9103 input_line_pointer
= (save
9104 + (input_line_pointer
- gotfree_input_line
)
9106 free (gotfree_input_line
);
9107 if (exp
->X_op
== O_constant
9108 || exp
->X_op
== O_absent
9109 || exp
->X_op
== O_illegal
9110 || exp
->X_op
== O_register
9111 || exp
->X_op
== O_big
)
9113 char c
= *input_line_pointer
;
9114 *input_line_pointer
= 0;
9115 as_bad (_("missing or invalid expression `%s'"), save
);
9116 *input_line_pointer
= c
;
9118 else if ((got_reloc
== BFD_RELOC_386_PLT32
9119 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9120 && exp
->X_op
!= O_symbol
)
9122 char c
= *input_line_pointer
;
9123 *input_line_pointer
= 0;
9124 as_bad (_("invalid PLT expression `%s'"), save
);
9125 *input_line_pointer
= c
;
9132 intel_syntax
= -intel_syntax
;
9135 i386_intel_simplify (exp
);
9141 signed_cons (int size
)
9143 if (flag_code
== CODE_64BIT
)
9151 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9158 if (exp
.X_op
== O_symbol
)
9159 exp
.X_op
= O_secrel
;
9161 emit_expr (&exp
, 4);
9163 while (*input_line_pointer
++ == ',');
9165 input_line_pointer
--;
9166 demand_empty_rest_of_line ();
9170 /* Handle Vector operations. */
9173 check_VecOperations (char *op_string
, char *op_end
)
9175 const reg_entry
*mask
;
9180 && (op_end
== NULL
|| op_string
< op_end
))
9183 if (*op_string
== '{')
9187 /* Check broadcasts. */
9188 if (strncmp (op_string
, "1to", 3) == 0)
9193 goto duplicated_vec_op
;
9196 if (*op_string
== '8')
9198 else if (*op_string
== '4')
9200 else if (*op_string
== '2')
9202 else if (*op_string
== '1'
9203 && *(op_string
+1) == '6')
9210 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9215 broadcast_op
.type
= bcst_type
;
9216 broadcast_op
.operand
= this_operand
;
9217 broadcast_op
.bytes
= 0;
9218 i
.broadcast
= &broadcast_op
;
9220 /* Check masking operation. */
9221 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9223 /* k0 can't be used for write mask. */
9224 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
9226 as_bad (_("`%s%s' can't be used for write mask"),
9227 register_prefix
, mask
->reg_name
);
9233 mask_op
.mask
= mask
;
9234 mask_op
.zeroing
= 0;
9235 mask_op
.operand
= this_operand
;
9241 goto duplicated_vec_op
;
9243 i
.mask
->mask
= mask
;
9245 /* Only "{z}" is allowed here. No need to check
9246 zeroing mask explicitly. */
9247 if (i
.mask
->operand
!= this_operand
)
9249 as_bad (_("invalid write mask `%s'"), saved
);
9256 /* Check zeroing-flag for masking operation. */
9257 else if (*op_string
== 'z')
9261 mask_op
.mask
= NULL
;
9262 mask_op
.zeroing
= 1;
9263 mask_op
.operand
= this_operand
;
9268 if (i
.mask
->zeroing
)
9271 as_bad (_("duplicated `%s'"), saved
);
9275 i
.mask
->zeroing
= 1;
9277 /* Only "{%k}" is allowed here. No need to check mask
9278 register explicitly. */
9279 if (i
.mask
->operand
!= this_operand
)
9281 as_bad (_("invalid zeroing-masking `%s'"),
9290 goto unknown_vec_op
;
9292 if (*op_string
!= '}')
9294 as_bad (_("missing `}' in `%s'"), saved
);
9299 /* Strip whitespace since the addition of pseudo prefixes
9300 changed how the scrubber treats '{'. */
9301 if (is_space_char (*op_string
))
9307 /* We don't know this one. */
9308 as_bad (_("unknown vector operation: `%s'"), saved
);
9312 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9314 as_bad (_("zeroing-masking only allowed with write mask"));
9322 i386_immediate (char *imm_start
)
9324 char *save_input_line_pointer
;
9325 char *gotfree_input_line
;
9328 i386_operand_type types
;
9330 operand_type_set (&types
, ~0);
9332 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9334 as_bad (_("at most %d immediate operands are allowed"),
9335 MAX_IMMEDIATE_OPERANDS
);
9339 exp
= &im_expressions
[i
.imm_operands
++];
9340 i
.op
[this_operand
].imms
= exp
;
9342 if (is_space_char (*imm_start
))
9345 save_input_line_pointer
= input_line_pointer
;
9346 input_line_pointer
= imm_start
;
9348 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9349 if (gotfree_input_line
)
9350 input_line_pointer
= gotfree_input_line
;
9352 exp_seg
= expression (exp
);
9356 /* Handle vector operations. */
9357 if (*input_line_pointer
== '{')
9359 input_line_pointer
= check_VecOperations (input_line_pointer
,
9361 if (input_line_pointer
== NULL
)
9365 if (*input_line_pointer
)
9366 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9368 input_line_pointer
= save_input_line_pointer
;
9369 if (gotfree_input_line
)
9371 free (gotfree_input_line
);
9373 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9374 exp
->X_op
= O_illegal
;
9377 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9381 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9382 i386_operand_type types
, const char *imm_start
)
9384 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9387 as_bad (_("missing or invalid immediate expression `%s'"),
9391 else if (exp
->X_op
== O_constant
)
9393 /* Size it properly later. */
9394 i
.types
[this_operand
].bitfield
.imm64
= 1;
9395 /* If not 64bit, sign extend val. */
9396 if (flag_code
!= CODE_64BIT
9397 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9399 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9401 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9402 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9403 && exp_seg
!= absolute_section
9404 && exp_seg
!= text_section
9405 && exp_seg
!= data_section
9406 && exp_seg
!= bss_section
9407 && exp_seg
!= undefined_section
9408 && !bfd_is_com_section (exp_seg
))
9410 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9414 else if (!intel_syntax
&& exp_seg
== reg_section
)
9417 as_bad (_("illegal immediate register operand %s"), imm_start
);
9422 /* This is an address. The size of the address will be
9423 determined later, depending on destination register,
9424 suffix, or the default for the section. */
9425 i
.types
[this_operand
].bitfield
.imm8
= 1;
9426 i
.types
[this_operand
].bitfield
.imm16
= 1;
9427 i
.types
[this_operand
].bitfield
.imm32
= 1;
9428 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9429 i
.types
[this_operand
].bitfield
.imm64
= 1;
9430 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9438 i386_scale (char *scale
)
9441 char *save
= input_line_pointer
;
9443 input_line_pointer
= scale
;
9444 val
= get_absolute_expression ();
9449 i
.log2_scale_factor
= 0;
9452 i
.log2_scale_factor
= 1;
9455 i
.log2_scale_factor
= 2;
9458 i
.log2_scale_factor
= 3;
9462 char sep
= *input_line_pointer
;
9464 *input_line_pointer
= '\0';
9465 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9467 *input_line_pointer
= sep
;
9468 input_line_pointer
= save
;
9472 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9474 as_warn (_("scale factor of %d without an index register"),
9475 1 << i
.log2_scale_factor
);
9476 i
.log2_scale_factor
= 0;
9478 scale
= input_line_pointer
;
9479 input_line_pointer
= save
;
9484 i386_displacement (char *disp_start
, char *disp_end
)
9488 char *save_input_line_pointer
;
9489 char *gotfree_input_line
;
9491 i386_operand_type bigdisp
, types
= anydisp
;
9494 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9496 as_bad (_("at most %d displacement operands are allowed"),
9497 MAX_MEMORY_OPERANDS
);
9501 operand_type_set (&bigdisp
, 0);
9502 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
9503 || (!current_templates
->start
->opcode_modifier
.jump
9504 && !current_templates
->start
->opcode_modifier
.jumpdword
))
9506 bigdisp
.bitfield
.disp32
= 1;
9507 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9508 if (flag_code
== CODE_64BIT
)
9512 bigdisp
.bitfield
.disp32s
= 1;
9513 bigdisp
.bitfield
.disp64
= 1;
9516 else if ((flag_code
== CODE_16BIT
) ^ override
)
9518 bigdisp
.bitfield
.disp32
= 0;
9519 bigdisp
.bitfield
.disp16
= 1;
9524 /* For PC-relative branches, the width of the displacement
9525 is dependent upon data size, not address size. */
9526 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9527 if (flag_code
== CODE_64BIT
)
9529 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9530 bigdisp
.bitfield
.disp16
= 1;
9533 bigdisp
.bitfield
.disp32
= 1;
9534 bigdisp
.bitfield
.disp32s
= 1;
9540 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9542 : LONG_MNEM_SUFFIX
));
9543 bigdisp
.bitfield
.disp32
= 1;
9544 if ((flag_code
== CODE_16BIT
) ^ override
)
9546 bigdisp
.bitfield
.disp32
= 0;
9547 bigdisp
.bitfield
.disp16
= 1;
9551 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9554 exp
= &disp_expressions
[i
.disp_operands
];
9555 i
.op
[this_operand
].disps
= exp
;
9557 save_input_line_pointer
= input_line_pointer
;
9558 input_line_pointer
= disp_start
;
9559 END_STRING_AND_SAVE (disp_end
);
9561 #ifndef GCC_ASM_O_HACK
9562 #define GCC_ASM_O_HACK 0
9565 END_STRING_AND_SAVE (disp_end
+ 1);
9566 if (i
.types
[this_operand
].bitfield
.baseIndex
9567 && displacement_string_end
[-1] == '+')
9569 /* This hack is to avoid a warning when using the "o"
9570 constraint within gcc asm statements.
9573 #define _set_tssldt_desc(n,addr,limit,type) \
9574 __asm__ __volatile__ ( \
9576 "movw %w1,2+%0\n\t" \
9578 "movb %b1,4+%0\n\t" \
9579 "movb %4,5+%0\n\t" \
9580 "movb $0,6+%0\n\t" \
9581 "movb %h1,7+%0\n\t" \
9583 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9585 This works great except that the output assembler ends
9586 up looking a bit weird if it turns out that there is
9587 no offset. You end up producing code that looks like:
9600 So here we provide the missing zero. */
9602 *displacement_string_end
= '0';
9605 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9606 if (gotfree_input_line
)
9607 input_line_pointer
= gotfree_input_line
;
9609 exp_seg
= expression (exp
);
9612 if (*input_line_pointer
)
9613 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9615 RESTORE_END_STRING (disp_end
+ 1);
9617 input_line_pointer
= save_input_line_pointer
;
9618 if (gotfree_input_line
)
9620 free (gotfree_input_line
);
9622 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9623 exp
->X_op
= O_illegal
;
9626 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
9628 RESTORE_END_STRING (disp_end
);
9634 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9635 i386_operand_type types
, const char *disp_start
)
9637 i386_operand_type bigdisp
;
9640 /* We do this to make sure that the section symbol is in
9641 the symbol table. We will ultimately change the relocation
9642 to be relative to the beginning of the section. */
9643 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
9644 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
9645 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9647 if (exp
->X_op
!= O_symbol
)
9650 if (S_IS_LOCAL (exp
->X_add_symbol
)
9651 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
9652 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
9653 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
9654 exp
->X_op
= O_subtract
;
9655 exp
->X_op_symbol
= GOT_symbol
;
9656 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
9657 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
9658 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
9659 i
.reloc
[this_operand
] = BFD_RELOC_64
;
9661 i
.reloc
[this_operand
] = BFD_RELOC_32
;
9664 else if (exp
->X_op
== O_absent
9665 || exp
->X_op
== O_illegal
9666 || exp
->X_op
== O_big
)
9669 as_bad (_("missing or invalid displacement expression `%s'"),
9674 else if (flag_code
== CODE_64BIT
9675 && !i
.prefix
[ADDR_PREFIX
]
9676 && exp
->X_op
== O_constant
)
9678 /* Since displacement is signed extended to 64bit, don't allow
9679 disp32 and turn off disp32s if they are out of range. */
9680 i
.types
[this_operand
].bitfield
.disp32
= 0;
9681 if (!fits_in_signed_long (exp
->X_add_number
))
9683 i
.types
[this_operand
].bitfield
.disp32s
= 0;
9684 if (i
.types
[this_operand
].bitfield
.baseindex
)
9686 as_bad (_("0x%lx out range of signed 32bit displacement"),
9687 (long) exp
->X_add_number
);
9693 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9694 else if (exp
->X_op
!= O_constant
9695 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
9696 && exp_seg
!= absolute_section
9697 && exp_seg
!= text_section
9698 && exp_seg
!= data_section
9699 && exp_seg
!= bss_section
9700 && exp_seg
!= undefined_section
9701 && !bfd_is_com_section (exp_seg
))
9703 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9708 /* Check if this is a displacement only operand. */
9709 bigdisp
= i
.types
[this_operand
];
9710 bigdisp
.bitfield
.disp8
= 0;
9711 bigdisp
.bitfield
.disp16
= 0;
9712 bigdisp
.bitfield
.disp32
= 0;
9713 bigdisp
.bitfield
.disp32s
= 0;
9714 bigdisp
.bitfield
.disp64
= 0;
9715 if (operand_type_all_zero (&bigdisp
))
9716 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9722 /* Return the active addressing mode, taking address override and
9723 registers forming the address into consideration. Update the
9724 address override prefix if necessary. */
9726 static enum flag_code
9727 i386_addressing_mode (void)
9729 enum flag_code addr_mode
;
9731 if (i
.prefix
[ADDR_PREFIX
])
9732 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
9735 addr_mode
= flag_code
;
9737 #if INFER_ADDR_PREFIX
9738 if (i
.mem_operands
== 0)
9740 /* Infer address prefix from the first memory operand. */
9741 const reg_entry
*addr_reg
= i
.base_reg
;
9743 if (addr_reg
== NULL
)
9744 addr_reg
= i
.index_reg
;
9748 if (addr_reg
->reg_type
.bitfield
.dword
)
9749 addr_mode
= CODE_32BIT
;
9750 else if (flag_code
!= CODE_64BIT
9751 && addr_reg
->reg_type
.bitfield
.word
)
9752 addr_mode
= CODE_16BIT
;
9754 if (addr_mode
!= flag_code
)
9756 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
9758 /* Change the size of any displacement too. At most one
9759 of Disp16 or Disp32 is set.
9760 FIXME. There doesn't seem to be any real need for
9761 separate Disp16 and Disp32 flags. The same goes for
9762 Imm16 and Imm32. Removing them would probably clean
9763 up the code quite a lot. */
9764 if (flag_code
!= CODE_64BIT
9765 && (i
.types
[this_operand
].bitfield
.disp16
9766 || i
.types
[this_operand
].bitfield
.disp32
))
9767 i
.types
[this_operand
]
9768 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
9778 /* Make sure the memory operand we've been dealt is valid.
9779 Return 1 on success, 0 on a failure. */
9782 i386_index_check (const char *operand_string
)
9784 const char *kind
= "base/index";
9785 enum flag_code addr_mode
= i386_addressing_mode ();
9787 if (current_templates
->start
->opcode_modifier
.isstring
9788 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
9789 && (current_templates
->end
[-1].opcode_modifier
.isstring
9792 /* Memory operands of string insns are special in that they only allow
9793 a single register (rDI, rSI, or rBX) as their memory address. */
9794 const reg_entry
*expected_reg
;
9795 static const char *di_si
[][2] =
9801 static const char *bx
[] = { "ebx", "bx", "rbx" };
9803 kind
= "string address";
9805 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9807 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9809 if (!type
.bitfield
.baseindex
9810 || ((!i
.mem_operands
!= !intel_syntax
)
9811 && current_templates
->end
[-1].operand_types
[1]
9812 .bitfield
.baseindex
))
9813 type
= current_templates
->end
[-1].operand_types
[1];
9814 expected_reg
= hash_find (reg_hash
,
9815 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9819 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9821 if (i
.base_reg
!= expected_reg
9823 || operand_type_check (i
.types
[this_operand
], disp
))
9825 /* The second memory operand must have the same size as
9829 && !((addr_mode
== CODE_64BIT
9830 && i
.base_reg
->reg_type
.bitfield
.qword
)
9831 || (addr_mode
== CODE_32BIT
9832 ? i
.base_reg
->reg_type
.bitfield
.dword
9833 : i
.base_reg
->reg_type
.bitfield
.word
)))
9836 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9838 intel_syntax
? '[' : '(',
9840 expected_reg
->reg_name
,
9841 intel_syntax
? ']' : ')');
9848 as_bad (_("`%s' is not a valid %s expression"),
9849 operand_string
, kind
);
9854 if (addr_mode
!= CODE_16BIT
)
9856 /* 32-bit/64-bit checks. */
9858 && ((addr_mode
== CODE_64BIT
9859 ? !i
.base_reg
->reg_type
.bitfield
.qword
9860 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9861 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
9862 || i
.base_reg
->reg_num
== RegIZ
))
9864 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9865 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9866 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9867 && ((addr_mode
== CODE_64BIT
9868 ? !i
.index_reg
->reg_type
.bitfield
.qword
9869 : !i
.index_reg
->reg_type
.bitfield
.dword
)
9870 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9873 /* bndmk, bndldx, and bndstx have special restrictions. */
9874 if (current_templates
->start
->base_opcode
== 0xf30f1b
9875 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9877 /* They cannot use RIP-relative addressing. */
9878 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9880 as_bad (_("`%s' cannot be used here"), operand_string
);
9884 /* bndldx and bndstx ignore their scale factor. */
9885 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9886 && i
.log2_scale_factor
)
9887 as_warn (_("register scaling is being ignored here"));
9892 /* 16-bit checks. */
9894 && (!i
.base_reg
->reg_type
.bitfield
.word
9895 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9897 && (!i
.index_reg
->reg_type
.bitfield
.word
9898 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9900 && i
.base_reg
->reg_num
< 6
9901 && i
.index_reg
->reg_num
>= 6
9902 && i
.log2_scale_factor
== 0))))
9909 /* Handle vector immediates. */
9912 RC_SAE_immediate (const char *imm_start
)
9914 unsigned int match_found
, j
;
9915 const char *pstr
= imm_start
;
9923 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9925 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9929 rc_op
.type
= RC_NamesTable
[j
].type
;
9930 rc_op
.operand
= this_operand
;
9931 i
.rounding
= &rc_op
;
9935 as_bad (_("duplicated `%s'"), imm_start
);
9938 pstr
+= RC_NamesTable
[j
].len
;
9948 as_bad (_("Missing '}': '%s'"), imm_start
);
9951 /* RC/SAE immediate string should contain nothing more. */;
9954 as_bad (_("Junk after '}': '%s'"), imm_start
);
9958 exp
= &im_expressions
[i
.imm_operands
++];
9959 i
.op
[this_operand
].imms
= exp
;
9961 exp
->X_op
= O_constant
;
9962 exp
->X_add_number
= 0;
9963 exp
->X_add_symbol
= (symbolS
*) 0;
9964 exp
->X_op_symbol
= (symbolS
*) 0;
9966 i
.types
[this_operand
].bitfield
.imm8
= 1;
9970 /* Only string instructions can have a second memory operand, so
9971 reduce current_templates to just those if it contains any. */
9973 maybe_adjust_templates (void)
9975 const insn_template
*t
;
9977 gas_assert (i
.mem_operands
== 1);
9979 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9980 if (t
->opcode_modifier
.isstring
)
9983 if (t
< current_templates
->end
)
9985 static templates aux_templates
;
9986 bfd_boolean recheck
;
9988 aux_templates
.start
= t
;
9989 for (; t
< current_templates
->end
; ++t
)
9990 if (!t
->opcode_modifier
.isstring
)
9992 aux_templates
.end
= t
;
9994 /* Determine whether to re-check the first memory operand. */
9995 recheck
= (aux_templates
.start
!= current_templates
->start
9996 || t
!= current_templates
->end
);
9998 current_templates
= &aux_templates
;
10002 i
.mem_operands
= 0;
10003 if (i
.memop1_string
!= NULL
10004 && i386_index_check (i
.memop1_string
) == 0)
10006 i
.mem_operands
= 1;
10013 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10017 i386_att_operand (char *operand_string
)
10019 const reg_entry
*r
;
10021 char *op_string
= operand_string
;
10023 if (is_space_char (*op_string
))
10026 /* We check for an absolute prefix (differentiating,
10027 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10028 if (*op_string
== ABSOLUTE_PREFIX
)
10031 if (is_space_char (*op_string
))
10033 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10036 /* Check if operand is a register. */
10037 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10039 i386_operand_type temp
;
10041 /* Check for a segment override by searching for ':' after a
10042 segment register. */
10043 op_string
= end_op
;
10044 if (is_space_char (*op_string
))
10046 if (*op_string
== ':' && r
->reg_type
.bitfield
.sreg
)
10048 switch (r
->reg_num
)
10051 i
.seg
[i
.mem_operands
] = &es
;
10054 i
.seg
[i
.mem_operands
] = &cs
;
10057 i
.seg
[i
.mem_operands
] = &ss
;
10060 i
.seg
[i
.mem_operands
] = &ds
;
10063 i
.seg
[i
.mem_operands
] = &fs
;
10066 i
.seg
[i
.mem_operands
] = &gs
;
10070 /* Skip the ':' and whitespace. */
10072 if (is_space_char (*op_string
))
10075 if (!is_digit_char (*op_string
)
10076 && !is_identifier_char (*op_string
)
10077 && *op_string
!= '('
10078 && *op_string
!= ABSOLUTE_PREFIX
)
10080 as_bad (_("bad memory operand `%s'"), op_string
);
10083 /* Handle case of %es:*foo. */
10084 if (*op_string
== ABSOLUTE_PREFIX
)
10087 if (is_space_char (*op_string
))
10089 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
10091 goto do_memory_reference
;
10094 /* Handle vector operations. */
10095 if (*op_string
== '{')
10097 op_string
= check_VecOperations (op_string
, NULL
);
10098 if (op_string
== NULL
)
10104 as_bad (_("junk `%s' after register"), op_string
);
10107 temp
= r
->reg_type
;
10108 temp
.bitfield
.baseindex
= 0;
10109 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10111 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10112 i
.op
[this_operand
].regs
= r
;
10115 else if (*op_string
== REGISTER_PREFIX
)
10117 as_bad (_("bad register name `%s'"), op_string
);
10120 else if (*op_string
== IMMEDIATE_PREFIX
)
10123 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
10125 as_bad (_("immediate operand illegal with absolute jump"));
10128 if (!i386_immediate (op_string
))
10131 else if (RC_SAE_immediate (operand_string
))
10133 /* If it is a RC or SAE immediate, do nothing. */
10136 else if (is_digit_char (*op_string
)
10137 || is_identifier_char (*op_string
)
10138 || *op_string
== '"'
10139 || *op_string
== '(')
10141 /* This is a memory reference of some sort. */
10144 /* Start and end of displacement string expression (if found). */
10145 char *displacement_string_start
;
10146 char *displacement_string_end
;
10149 do_memory_reference
:
10150 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10152 if ((i
.mem_operands
== 1
10153 && !current_templates
->start
->opcode_modifier
.isstring
)
10154 || i
.mem_operands
== 2)
10156 as_bad (_("too many memory references for `%s'"),
10157 current_templates
->start
->name
);
10161 /* Check for base index form. We detect the base index form by
10162 looking for an ')' at the end of the operand, searching
10163 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10165 base_string
= op_string
+ strlen (op_string
);
10167 /* Handle vector operations. */
10168 vop_start
= strchr (op_string
, '{');
10169 if (vop_start
&& vop_start
< base_string
)
10171 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10173 base_string
= vop_start
;
10177 if (is_space_char (*base_string
))
10180 /* If we only have a displacement, set-up for it to be parsed later. */
10181 displacement_string_start
= op_string
;
10182 displacement_string_end
= base_string
+ 1;
10184 if (*base_string
== ')')
10187 unsigned int parens_balanced
= 1;
10188 /* We've already checked that the number of left & right ()'s are
10189 equal, so this loop will not be infinite. */
10193 if (*base_string
== ')')
10195 if (*base_string
== '(')
10198 while (parens_balanced
);
10200 temp_string
= base_string
;
10202 /* Skip past '(' and whitespace. */
10204 if (is_space_char (*base_string
))
10207 if (*base_string
== ','
10208 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10211 displacement_string_end
= temp_string
;
10213 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10217 base_string
= end_op
;
10218 if (is_space_char (*base_string
))
10222 /* There may be an index reg or scale factor here. */
10223 if (*base_string
== ',')
10226 if (is_space_char (*base_string
))
10229 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10232 base_string
= end_op
;
10233 if (is_space_char (*base_string
))
10235 if (*base_string
== ',')
10238 if (is_space_char (*base_string
))
10241 else if (*base_string
!= ')')
10243 as_bad (_("expecting `,' or `)' "
10244 "after index register in `%s'"),
10249 else if (*base_string
== REGISTER_PREFIX
)
10251 end_op
= strchr (base_string
, ',');
10254 as_bad (_("bad register name `%s'"), base_string
);
10258 /* Check for scale factor. */
10259 if (*base_string
!= ')')
10261 char *end_scale
= i386_scale (base_string
);
10266 base_string
= end_scale
;
10267 if (is_space_char (*base_string
))
10269 if (*base_string
!= ')')
10271 as_bad (_("expecting `)' "
10272 "after scale factor in `%s'"),
10277 else if (!i
.index_reg
)
10279 as_bad (_("expecting index register or scale factor "
10280 "after `,'; got '%c'"),
10285 else if (*base_string
!= ')')
10287 as_bad (_("expecting `,' or `)' "
10288 "after base register in `%s'"),
10293 else if (*base_string
== REGISTER_PREFIX
)
10295 end_op
= strchr (base_string
, ',');
10298 as_bad (_("bad register name `%s'"), base_string
);
10303 /* If there's an expression beginning the operand, parse it,
10304 assuming displacement_string_start and
10305 displacement_string_end are meaningful. */
10306 if (displacement_string_start
!= displacement_string_end
)
10308 if (!i386_displacement (displacement_string_start
,
10309 displacement_string_end
))
10313 /* Special case for (%dx) while doing input/output op. */
10315 && i
.base_reg
->reg_type
.bitfield
.inoutportreg
10316 && i
.index_reg
== 0
10317 && i
.log2_scale_factor
== 0
10318 && i
.seg
[i
.mem_operands
] == 0
10319 && !operand_type_check (i
.types
[this_operand
], disp
))
10321 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10325 if (i386_index_check (operand_string
) == 0)
10327 i
.flags
[this_operand
] |= Operand_Mem
;
10328 if (i
.mem_operands
== 0)
10329 i
.memop1_string
= xstrdup (operand_string
);
10334 /* It's not a memory operand; argh! */
10335 as_bad (_("invalid char %s beginning operand %d `%s'"),
10336 output_invalid (*op_string
),
10341 return 1; /* Normal return. */
10344 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10345 that an rs_machine_dependent frag may reach. */
10348 i386_frag_max_var (fragS
*frag
)
10350 /* The only relaxable frags are for jumps.
10351 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10352 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10353 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10358 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10360 /* STT_GNU_IFUNC symbol must go through PLT. */
10361 if ((symbol_get_bfdsym (fr_symbol
)->flags
10362 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10365 if (!S_IS_EXTERNAL (fr_symbol
))
10366 /* Symbol may be weak or local. */
10367 return !S_IS_WEAK (fr_symbol
);
10369 /* Global symbols with non-default visibility can't be preempted. */
10370 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10373 if (fr_var
!= NO_RELOC
)
10374 switch ((enum bfd_reloc_code_real
) fr_var
)
10376 case BFD_RELOC_386_PLT32
:
10377 case BFD_RELOC_X86_64_PLT32
:
10378 /* Symbol with PLT relocation may be preempted. */
10384 /* Global symbols with default visibility in a shared library may be
10385 preempted by another definition. */
10390 /* md_estimate_size_before_relax()
10392 Called just before relax() for rs_machine_dependent frags. The x86
10393 assembler uses these frags to handle variable size jump
10396 Any symbol that is now undefined will not become defined.
10397 Return the correct fr_subtype in the frag.
10398 Return the initial "guess for variable size of frag" to caller.
10399 The guess is actually the growth beyond the fixed part. Whatever
10400 we do to grow the fixed or variable part contributes to our
10404 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
10406 /* We've already got fragP->fr_subtype right; all we have to do is
10407 check for un-relaxable symbols. On an ELF system, we can't relax
10408 an externally visible symbol, because it may be overridden by a
10410 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
10411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10413 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
10416 #if defined (OBJ_COFF) && defined (TE_PE)
10417 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
10418 && S_IS_WEAK (fragP
->fr_symbol
))
10422 /* Symbol is undefined in this segment, or we need to keep a
10423 reloc so that weak symbols can be overridden. */
10424 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
10425 enum bfd_reloc_code_real reloc_type
;
10426 unsigned char *opcode
;
10429 if (fragP
->fr_var
!= NO_RELOC
)
10430 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
10431 else if (size
== 2)
10432 reloc_type
= BFD_RELOC_16_PCREL
;
10433 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10434 else if (need_plt32_p (fragP
->fr_symbol
))
10435 reloc_type
= BFD_RELOC_X86_64_PLT32
;
10438 reloc_type
= BFD_RELOC_32_PCREL
;
10440 old_fr_fix
= fragP
->fr_fix
;
10441 opcode
= (unsigned char *) fragP
->fr_opcode
;
10443 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
10446 /* Make jmp (0xeb) a (d)word displacement jump. */
10448 fragP
->fr_fix
+= size
;
10449 fix_new (fragP
, old_fr_fix
, size
,
10451 fragP
->fr_offset
, 1,
10457 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
10459 /* Negate the condition, and branch past an
10460 unconditional jump. */
10463 /* Insert an unconditional jump. */
10465 /* We added two extra opcode bytes, and have a two byte
10467 fragP
->fr_fix
+= 2 + 2;
10468 fix_new (fragP
, old_fr_fix
+ 2, 2,
10470 fragP
->fr_offset
, 1,
10474 /* Fall through. */
10477 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
10481 fragP
->fr_fix
+= 1;
10482 fixP
= fix_new (fragP
, old_fr_fix
, 1,
10484 fragP
->fr_offset
, 1,
10485 BFD_RELOC_8_PCREL
);
10486 fixP
->fx_signed
= 1;
10490 /* This changes the byte-displacement jump 0x7N
10491 to the (d)word-displacement jump 0x0f,0x8N. */
10492 opcode
[1] = opcode
[0] + 0x10;
10493 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10494 /* We've added an opcode byte. */
10495 fragP
->fr_fix
+= 1 + size
;
10496 fix_new (fragP
, old_fr_fix
+ 1, size
,
10498 fragP
->fr_offset
, 1,
10503 BAD_CASE (fragP
->fr_subtype
);
10507 return fragP
->fr_fix
- old_fr_fix
;
10510 /* Guess size depending on current relax state. Initially the relax
10511 state will correspond to a short jump and we return 1, because
10512 the variable part of the frag (the branch offset) is one byte
10513 long. However, we can relax a section more than once and in that
10514 case we must either set fr_subtype back to the unrelaxed state,
10515 or return the value for the appropriate branch. */
10516 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
10519 /* Called after relax() is finished.
10521 In: Address of frag.
10522 fr_type == rs_machine_dependent.
10523 fr_subtype is what the address relaxed to.
10525 Out: Any fixSs and constants are set up.
10526 Caller will turn frag into a ".space 0". */
10529 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
10532 unsigned char *opcode
;
10533 unsigned char *where_to_put_displacement
= NULL
;
10534 offsetT target_address
;
10535 offsetT opcode_address
;
10536 unsigned int extension
= 0;
10537 offsetT displacement_from_opcode_start
;
10539 opcode
= (unsigned char *) fragP
->fr_opcode
;
10541 /* Address we want to reach in file space. */
10542 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
10544 /* Address opcode resides at in file space. */
10545 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
10547 /* Displacement from opcode start to fill into instruction. */
10548 displacement_from_opcode_start
= target_address
- opcode_address
;
10550 if ((fragP
->fr_subtype
& BIG
) == 0)
10552 /* Don't have to change opcode. */
10553 extension
= 1; /* 1 opcode + 1 displacement */
10554 where_to_put_displacement
= &opcode
[1];
10558 if (no_cond_jump_promotion
10559 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
10560 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
10561 _("long jump required"));
10563 switch (fragP
->fr_subtype
)
10565 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
10566 extension
= 4; /* 1 opcode + 4 displacement */
10568 where_to_put_displacement
= &opcode
[1];
10571 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
10572 extension
= 2; /* 1 opcode + 2 displacement */
10574 where_to_put_displacement
= &opcode
[1];
10577 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
10578 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
10579 extension
= 5; /* 2 opcode + 4 displacement */
10580 opcode
[1] = opcode
[0] + 0x10;
10581 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10582 where_to_put_displacement
= &opcode
[2];
10585 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
10586 extension
= 3; /* 2 opcode + 2 displacement */
10587 opcode
[1] = opcode
[0] + 0x10;
10588 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
10589 where_to_put_displacement
= &opcode
[2];
10592 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
10597 where_to_put_displacement
= &opcode
[3];
10601 BAD_CASE (fragP
->fr_subtype
);
10606 /* If size if less then four we are sure that the operand fits,
10607 but if it's 4, then it could be that the displacement is larger
10609 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
10611 && ((addressT
) (displacement_from_opcode_start
- extension
10612 + ((addressT
) 1 << 31))
10613 > (((addressT
) 2 << 31) - 1)))
10615 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10616 _("jump target out of range"));
10617 /* Make us emit 0. */
10618 displacement_from_opcode_start
= extension
;
10620 /* Now put displacement after opcode. */
10621 md_number_to_chars ((char *) where_to_put_displacement
,
10622 (valueT
) (displacement_from_opcode_start
- extension
),
10623 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
10624 fragP
->fr_fix
+= extension
;
10627 /* Apply a fixup (fixP) to segment data, once it has been determined
10628 by our caller that we have all the info we need to fix it up.
10630 Parameter valP is the pointer to the value of the bits.
10632 On the 386, immediates, displacements, and data pointers are all in
10633 the same (little-endian) format, so we don't need to care about which
10634 we are handling. */
10637 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10639 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
10640 valueT value
= *valP
;
10642 #if !defined (TE_Mach)
10643 if (fixP
->fx_pcrel
)
10645 switch (fixP
->fx_r_type
)
10651 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
10654 case BFD_RELOC_X86_64_32S
:
10655 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
10658 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
10661 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
10666 if (fixP
->fx_addsy
!= NULL
10667 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
10668 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
10669 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
10670 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
10671 && !use_rela_relocations
)
10673 /* This is a hack. There should be a better way to handle this.
10674 This covers for the fact that bfd_install_relocation will
10675 subtract the current location (for partial_inplace, PC relative
10676 relocations); see more below. */
10680 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
10683 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10685 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10688 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
10690 if ((sym_seg
== seg
10691 || (symbol_section_p (fixP
->fx_addsy
)
10692 && sym_seg
!= absolute_section
))
10693 && !generic_force_reloc (fixP
))
10695 /* Yes, we add the values in twice. This is because
10696 bfd_install_relocation subtracts them out again. I think
10697 bfd_install_relocation is broken, but I don't dare change
10699 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10703 #if defined (OBJ_COFF) && defined (TE_PE)
10704 /* For some reason, the PE format does not store a
10705 section address offset for a PC relative symbol. */
10706 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
10707 || S_IS_WEAK (fixP
->fx_addsy
))
10708 value
+= md_pcrel_from (fixP
);
10711 #if defined (OBJ_COFF) && defined (TE_PE)
10712 if (fixP
->fx_addsy
!= NULL
10713 && S_IS_WEAK (fixP
->fx_addsy
)
10714 /* PR 16858: Do not modify weak function references. */
10715 && ! fixP
->fx_pcrel
)
10717 #if !defined (TE_PEP)
10718 /* For x86 PE weak function symbols are neither PC-relative
10719 nor do they set S_IS_FUNCTION. So the only reliable way
10720 to detect them is to check the flags of their containing
10722 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
10723 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
10727 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10731 /* Fix a few things - the dynamic linker expects certain values here,
10732 and we must not disappoint it. */
10733 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10734 if (IS_ELF
&& fixP
->fx_addsy
)
10735 switch (fixP
->fx_r_type
)
10737 case BFD_RELOC_386_PLT32
:
10738 case BFD_RELOC_X86_64_PLT32
:
10739 /* Make the jump instruction point to the address of the operand.
10740 At runtime we merely add the offset to the actual PLT entry.
10741 NB: Subtract the offset size only for jump instructions. */
10742 if (fixP
->fx_pcrel
)
10746 case BFD_RELOC_386_TLS_GD
:
10747 case BFD_RELOC_386_TLS_LDM
:
10748 case BFD_RELOC_386_TLS_IE_32
:
10749 case BFD_RELOC_386_TLS_IE
:
10750 case BFD_RELOC_386_TLS_GOTIE
:
10751 case BFD_RELOC_386_TLS_GOTDESC
:
10752 case BFD_RELOC_X86_64_TLSGD
:
10753 case BFD_RELOC_X86_64_TLSLD
:
10754 case BFD_RELOC_X86_64_GOTTPOFF
:
10755 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10756 value
= 0; /* Fully resolved at runtime. No addend. */
10758 case BFD_RELOC_386_TLS_LE
:
10759 case BFD_RELOC_386_TLS_LDO_32
:
10760 case BFD_RELOC_386_TLS_LE_32
:
10761 case BFD_RELOC_X86_64_DTPOFF32
:
10762 case BFD_RELOC_X86_64_DTPOFF64
:
10763 case BFD_RELOC_X86_64_TPOFF32
:
10764 case BFD_RELOC_X86_64_TPOFF64
:
10765 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10768 case BFD_RELOC_386_TLS_DESC_CALL
:
10769 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10770 value
= 0; /* Fully resolved at runtime. No addend. */
10771 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
10775 case BFD_RELOC_VTABLE_INHERIT
:
10776 case BFD_RELOC_VTABLE_ENTRY
:
10783 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10785 #endif /* !defined (TE_Mach) */
10787 /* Are we finished with this relocation now? */
10788 if (fixP
->fx_addsy
== NULL
)
10790 #if defined (OBJ_COFF) && defined (TE_PE)
10791 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
10794 /* Remember value for tc_gen_reloc. */
10795 fixP
->fx_addnumber
= value
;
10796 /* Clear out the frag for now. */
10800 else if (use_rela_relocations
)
10802 fixP
->fx_no_overflow
= 1;
10803 /* Remember value for tc_gen_reloc. */
10804 fixP
->fx_addnumber
= value
;
10808 md_number_to_chars (p
, value
, fixP
->fx_size
);
10812 md_atof (int type
, char *litP
, int *sizeP
)
10814 /* This outputs the LITTLENUMs in REVERSE order;
10815 in accord with the bigendian 386. */
10816 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10819 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10822 output_invalid (int c
)
10825 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10828 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10829 "(0x%x)", (unsigned char) c
);
10830 return output_invalid_buf
;
10833 /* REG_STRING starts *before* REGISTER_PREFIX. */
10835 static const reg_entry
*
10836 parse_real_register (char *reg_string
, char **end_op
)
10838 char *s
= reg_string
;
10840 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10841 const reg_entry
*r
;
10843 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10844 if (*s
== REGISTER_PREFIX
)
10847 if (is_space_char (*s
))
10850 p
= reg_name_given
;
10851 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10853 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10854 return (const reg_entry
*) NULL
;
10858 /* For naked regs, make sure that we are not dealing with an identifier.
10859 This prevents confusing an identifier like `eax_var' with register
10861 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10862 return (const reg_entry
*) NULL
;
10866 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10868 /* Handle floating point regs, allowing spaces in the (i) part. */
10869 if (r
== i386_regtab
/* %st is first entry of table */)
10871 if (!cpu_arch_flags
.bitfield
.cpu8087
10872 && !cpu_arch_flags
.bitfield
.cpu287
10873 && !cpu_arch_flags
.bitfield
.cpu387
)
10874 return (const reg_entry
*) NULL
;
10876 if (is_space_char (*s
))
10881 if (is_space_char (*s
))
10883 if (*s
>= '0' && *s
<= '7')
10885 int fpr
= *s
- '0';
10887 if (is_space_char (*s
))
10892 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10897 /* We have "%st(" then garbage. */
10898 return (const reg_entry
*) NULL
;
10902 if (r
== NULL
|| allow_pseudo_reg
)
10905 if (operand_type_all_zero (&r
->reg_type
))
10906 return (const reg_entry
*) NULL
;
10908 if ((r
->reg_type
.bitfield
.dword
10909 || (r
->reg_type
.bitfield
.sreg
&& r
->reg_num
> 3)
10910 || r
->reg_type
.bitfield
.control
10911 || r
->reg_type
.bitfield
.debug
10912 || r
->reg_type
.bitfield
.test
)
10913 && !cpu_arch_flags
.bitfield
.cpui386
)
10914 return (const reg_entry
*) NULL
;
10916 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
10917 return (const reg_entry
*) NULL
;
10919 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
10921 if (r
->reg_type
.bitfield
.zmmword
|| r
->reg_type
.bitfield
.regmask
)
10922 return (const reg_entry
*) NULL
;
10924 if (!cpu_arch_flags
.bitfield
.cpuavx
)
10926 if (r
->reg_type
.bitfield
.ymmword
)
10927 return (const reg_entry
*) NULL
;
10929 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
10930 return (const reg_entry
*) NULL
;
10934 if (r
->reg_type
.bitfield
.regbnd
&& !cpu_arch_flags
.bitfield
.cpumpx
)
10935 return (const reg_entry
*) NULL
;
10937 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10938 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
10939 return (const reg_entry
*) NULL
;
10941 /* Upper 16 vector registers are only available with VREX in 64bit
10942 mode, and require EVEX encoding. */
10943 if (r
->reg_flags
& RegVRex
)
10945 if (!cpu_arch_flags
.bitfield
.cpuavx512f
10946 || flag_code
!= CODE_64BIT
)
10947 return (const reg_entry
*) NULL
;
10949 i
.vec_encoding
= vex_encoding_evex
;
10952 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
10953 && (!cpu_arch_flags
.bitfield
.cpulm
|| !r
->reg_type
.bitfield
.control
)
10954 && flag_code
!= CODE_64BIT
)
10955 return (const reg_entry
*) NULL
;
10957 if (r
->reg_type
.bitfield
.sreg
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10958 return (const reg_entry
*) NULL
;
10963 /* REG_STRING starts *before* REGISTER_PREFIX. */
10965 static const reg_entry
*
10966 parse_register (char *reg_string
, char **end_op
)
10968 const reg_entry
*r
;
10970 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10971 r
= parse_real_register (reg_string
, end_op
);
10976 char *save
= input_line_pointer
;
10980 input_line_pointer
= reg_string
;
10981 c
= get_symbol_name (®_string
);
10982 symbolP
= symbol_find (reg_string
);
10983 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10985 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10987 know (e
->X_op
== O_register
);
10988 know (e
->X_add_number
>= 0
10989 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10990 r
= i386_regtab
+ e
->X_add_number
;
10991 if ((r
->reg_flags
& RegVRex
))
10992 i
.vec_encoding
= vex_encoding_evex
;
10993 *end_op
= input_line_pointer
;
10995 *input_line_pointer
= c
;
10996 input_line_pointer
= save
;
11002 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11004 const reg_entry
*r
;
11005 char *end
= input_line_pointer
;
11008 r
= parse_register (name
, &input_line_pointer
);
11009 if (r
&& end
<= input_line_pointer
)
11011 *nextcharP
= *input_line_pointer
;
11012 *input_line_pointer
= 0;
11013 e
->X_op
= O_register
;
11014 e
->X_add_number
= r
- i386_regtab
;
11017 input_line_pointer
= end
;
11019 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11023 md_operand (expressionS
*e
)
11026 const reg_entry
*r
;
11028 switch (*input_line_pointer
)
11030 case REGISTER_PREFIX
:
11031 r
= parse_real_register (input_line_pointer
, &end
);
11034 e
->X_op
= O_register
;
11035 e
->X_add_number
= r
- i386_regtab
;
11036 input_line_pointer
= end
;
11041 gas_assert (intel_syntax
);
11042 end
= input_line_pointer
++;
11044 if (*input_line_pointer
== ']')
11046 ++input_line_pointer
;
11047 e
->X_op_symbol
= make_expr_symbol (e
);
11048 e
->X_add_symbol
= NULL
;
11049 e
->X_add_number
= 0;
11054 e
->X_op
= O_absent
;
11055 input_line_pointer
= end
;
11062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11063 const char *md_shortopts
= "kVQ:sqnO::";
11065 const char *md_shortopts
= "qnO::";
11068 #define OPTION_32 (OPTION_MD_BASE + 0)
11069 #define OPTION_64 (OPTION_MD_BASE + 1)
11070 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11071 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11072 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11073 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11074 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11075 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11076 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11077 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11078 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11079 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11080 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11081 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11082 #define OPTION_X32 (OPTION_MD_BASE + 14)
11083 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11084 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11085 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11086 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11087 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11088 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11089 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11090 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11091 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11092 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11093 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11094 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11096 struct option md_longopts
[] =
11098 {"32", no_argument
, NULL
, OPTION_32
},
11099 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11100 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11101 {"64", no_argument
, NULL
, OPTION_64
},
11103 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11104 {"x32", no_argument
, NULL
, OPTION_X32
},
11105 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11106 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
11108 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
11109 {"march", required_argument
, NULL
, OPTION_MARCH
},
11110 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11111 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
11112 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
11113 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
11114 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
11115 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
11116 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
11117 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
11118 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
11119 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
11120 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
11121 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
11122 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
11123 # if defined (TE_PE) || defined (TE_PEP)
11124 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
11126 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
11127 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
11128 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
11129 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
11130 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
11131 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
11132 {NULL
, no_argument
, NULL
, 0}
11134 size_t md_longopts_size
= sizeof (md_longopts
);
11137 md_parse_option (int c
, const char *arg
)
11140 char *arch
, *next
, *saved
;
11145 optimize_align_code
= 0;
11149 quiet_warnings
= 1;
11152 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11153 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11154 should be emitted or not. FIXME: Not implemented. */
11156 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
11160 /* -V: SVR4 argument to print version ID. */
11162 print_version_id ();
11165 /* -k: Ignore for FreeBSD compatibility. */
11170 /* -s: On i386 Solaris, this tells the native assembler to use
11171 .stab instead of .stab.excl. We always use .stab anyhow. */
11174 case OPTION_MSHARED
:
11178 case OPTION_X86_USED_NOTE
:
11179 if (strcasecmp (arg
, "yes") == 0)
11181 else if (strcasecmp (arg
, "no") == 0)
11184 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
11189 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11190 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11193 const char **list
, **l
;
11195 list
= bfd_target_list ();
11196 for (l
= list
; *l
!= NULL
; l
++)
11197 if (CONST_STRNEQ (*l
, "elf64-x86-64")
11198 || strcmp (*l
, "coff-x86-64") == 0
11199 || strcmp (*l
, "pe-x86-64") == 0
11200 || strcmp (*l
, "pei-x86-64") == 0
11201 || strcmp (*l
, "mach-o-x86-64") == 0)
11203 default_arch
= "x86_64";
11207 as_fatal (_("no compiled in support for x86_64"));
11213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11217 const char **list
, **l
;
11219 list
= bfd_target_list ();
11220 for (l
= list
; *l
!= NULL
; l
++)
11221 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
11223 default_arch
= "x86_64:32";
11227 as_fatal (_("no compiled in support for 32bit x86_64"));
11231 as_fatal (_("32bit x86_64 is only supported for ELF"));
11236 default_arch
= "i386";
11239 case OPTION_DIVIDE
:
11240 #ifdef SVR4_COMMENT_CHARS
11245 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
11247 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
11251 i386_comment_chars
= n
;
11257 saved
= xstrdup (arg
);
11259 /* Allow -march=+nosse. */
11265 as_fatal (_("invalid -march= option: `%s'"), arg
);
11266 next
= strchr (arch
, '+');
11269 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11271 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
11274 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11277 cpu_arch_name
= cpu_arch
[j
].name
;
11278 cpu_sub_arch_name
= NULL
;
11279 cpu_arch_flags
= cpu_arch
[j
].flags
;
11280 cpu_arch_isa
= cpu_arch
[j
].type
;
11281 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
11282 if (!cpu_arch_tune_set
)
11284 cpu_arch_tune
= cpu_arch_isa
;
11285 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11289 else if (*cpu_arch
[j
].name
== '.'
11290 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
11292 /* ISA extension. */
11293 i386_cpu_flags flags
;
11295 flags
= cpu_flags_or (cpu_arch_flags
,
11296 cpu_arch
[j
].flags
);
11298 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11300 if (cpu_sub_arch_name
)
11302 char *name
= cpu_sub_arch_name
;
11303 cpu_sub_arch_name
= concat (name
,
11305 (const char *) NULL
);
11309 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
11310 cpu_arch_flags
= flags
;
11311 cpu_arch_isa_flags
= flags
;
11315 = cpu_flags_or (cpu_arch_isa_flags
,
11316 cpu_arch
[j
].flags
);
11321 if (j
>= ARRAY_SIZE (cpu_arch
))
11323 /* Disable an ISA extension. */
11324 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11325 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
11327 i386_cpu_flags flags
;
11329 flags
= cpu_flags_and_not (cpu_arch_flags
,
11330 cpu_noarch
[j
].flags
);
11331 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
11333 if (cpu_sub_arch_name
)
11335 char *name
= cpu_sub_arch_name
;
11336 cpu_sub_arch_name
= concat (arch
,
11337 (const char *) NULL
);
11341 cpu_sub_arch_name
= xstrdup (arch
);
11342 cpu_arch_flags
= flags
;
11343 cpu_arch_isa_flags
= flags
;
11348 if (j
>= ARRAY_SIZE (cpu_noarch
))
11349 j
= ARRAY_SIZE (cpu_arch
);
11352 if (j
>= ARRAY_SIZE (cpu_arch
))
11353 as_fatal (_("invalid -march= option: `%s'"), arg
);
11357 while (next
!= NULL
);
11363 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11364 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11366 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
11368 cpu_arch_tune_set
= 1;
11369 cpu_arch_tune
= cpu_arch
[j
].type
;
11370 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
11374 if (j
>= ARRAY_SIZE (cpu_arch
))
11375 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
11378 case OPTION_MMNEMONIC
:
11379 if (strcasecmp (arg
, "att") == 0)
11380 intel_mnemonic
= 0;
11381 else if (strcasecmp (arg
, "intel") == 0)
11382 intel_mnemonic
= 1;
11384 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
11387 case OPTION_MSYNTAX
:
11388 if (strcasecmp (arg
, "att") == 0)
11390 else if (strcasecmp (arg
, "intel") == 0)
11393 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
11396 case OPTION_MINDEX_REG
:
11397 allow_index_reg
= 1;
11400 case OPTION_MNAKED_REG
:
11401 allow_naked_reg
= 1;
11404 case OPTION_MSSE2AVX
:
11408 case OPTION_MSSE_CHECK
:
11409 if (strcasecmp (arg
, "error") == 0)
11410 sse_check
= check_error
;
11411 else if (strcasecmp (arg
, "warning") == 0)
11412 sse_check
= check_warning
;
11413 else if (strcasecmp (arg
, "none") == 0)
11414 sse_check
= check_none
;
11416 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
11419 case OPTION_MOPERAND_CHECK
:
11420 if (strcasecmp (arg
, "error") == 0)
11421 operand_check
= check_error
;
11422 else if (strcasecmp (arg
, "warning") == 0)
11423 operand_check
= check_warning
;
11424 else if (strcasecmp (arg
, "none") == 0)
11425 operand_check
= check_none
;
11427 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
11430 case OPTION_MAVXSCALAR
:
11431 if (strcasecmp (arg
, "128") == 0)
11432 avxscalar
= vex128
;
11433 else if (strcasecmp (arg
, "256") == 0)
11434 avxscalar
= vex256
;
11436 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
11439 case OPTION_MVEXWIG
:
11440 if (strcmp (arg
, "0") == 0)
11442 else if (strcmp (arg
, "1") == 0)
11445 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
11448 case OPTION_MADD_BND_PREFIX
:
11449 add_bnd_prefix
= 1;
11452 case OPTION_MEVEXLIG
:
11453 if (strcmp (arg
, "128") == 0)
11454 evexlig
= evexl128
;
11455 else if (strcmp (arg
, "256") == 0)
11456 evexlig
= evexl256
;
11457 else if (strcmp (arg
, "512") == 0)
11458 evexlig
= evexl512
;
11460 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
11463 case OPTION_MEVEXRCIG
:
11464 if (strcmp (arg
, "rne") == 0)
11466 else if (strcmp (arg
, "rd") == 0)
11468 else if (strcmp (arg
, "ru") == 0)
11470 else if (strcmp (arg
, "rz") == 0)
11473 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
11476 case OPTION_MEVEXWIG
:
11477 if (strcmp (arg
, "0") == 0)
11479 else if (strcmp (arg
, "1") == 0)
11482 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
11485 # if defined (TE_PE) || defined (TE_PEP)
11486 case OPTION_MBIG_OBJ
:
11491 case OPTION_MOMIT_LOCK_PREFIX
:
11492 if (strcasecmp (arg
, "yes") == 0)
11493 omit_lock_prefix
= 1;
11494 else if (strcasecmp (arg
, "no") == 0)
11495 omit_lock_prefix
= 0;
11497 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
11500 case OPTION_MFENCE_AS_LOCK_ADD
:
11501 if (strcasecmp (arg
, "yes") == 0)
11503 else if (strcasecmp (arg
, "no") == 0)
11506 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
11509 case OPTION_MRELAX_RELOCATIONS
:
11510 if (strcasecmp (arg
, "yes") == 0)
11511 generate_relax_relocations
= 1;
11512 else if (strcasecmp (arg
, "no") == 0)
11513 generate_relax_relocations
= 0;
11515 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
11518 case OPTION_MAMD64
:
11522 case OPTION_MINTEL64
:
11530 /* Turn off -Os. */
11531 optimize_for_space
= 0;
11533 else if (*arg
== 's')
11535 optimize_for_space
= 1;
11536 /* Turn on all encoding optimizations. */
11537 optimize
= INT_MAX
;
11541 optimize
= atoi (arg
);
11542 /* Turn off -Os. */
11543 optimize_for_space
= 0;
11553 #define MESSAGE_TEMPLATE \
11557 output_message (FILE *stream
, char *p
, char *message
, char *start
,
11558 int *left_p
, const char *name
, int len
)
11560 int size
= sizeof (MESSAGE_TEMPLATE
);
11561 int left
= *left_p
;
11563 /* Reserve 2 spaces for ", " or ",\0" */
11566 /* Check if there is any room. */
11574 p
= mempcpy (p
, name
, len
);
11578 /* Output the current message now and start a new one. */
11581 fprintf (stream
, "%s\n", message
);
11583 left
= size
- (start
- message
) - len
- 2;
11585 gas_assert (left
>= 0);
11587 p
= mempcpy (p
, name
, len
);
11595 show_arch (FILE *stream
, int ext
, int check
)
11597 static char message
[] = MESSAGE_TEMPLATE
;
11598 char *start
= message
+ 27;
11600 int size
= sizeof (MESSAGE_TEMPLATE
);
11607 left
= size
- (start
- message
);
11608 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
11610 /* Should it be skipped? */
11611 if (cpu_arch
[j
].skip
)
11614 name
= cpu_arch
[j
].name
;
11615 len
= cpu_arch
[j
].len
;
11618 /* It is an extension. Skip if we aren't asked to show it. */
11629 /* It is an processor. Skip if we show only extension. */
11632 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
11634 /* It is an impossible processor - skip. */
11638 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
11641 /* Display disabled extensions. */
11643 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
11645 name
= cpu_noarch
[j
].name
;
11646 len
= cpu_noarch
[j
].len
;
11647 p
= output_message (stream
, p
, message
, start
, &left
, name
,
11652 fprintf (stream
, "%s\n", message
);
11656 md_show_usage (FILE *stream
)
11658 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11659 fprintf (stream
, _("\
11660 -Qy, -Qn ignored\n\
11661 -V print assembler version number\n\
11664 fprintf (stream
, _("\
11665 -n Do not optimize code alignment\n\
11666 -q quieten some warnings\n"));
11667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11668 fprintf (stream
, _("\
11671 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11672 || defined (TE_PE) || defined (TE_PEP))
11673 fprintf (stream
, _("\
11674 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11676 #ifdef SVR4_COMMENT_CHARS
11677 fprintf (stream
, _("\
11678 --divide do not treat `/' as a comment character\n"));
11680 fprintf (stream
, _("\
11681 --divide ignored\n"));
11683 fprintf (stream
, _("\
11684 -march=CPU[,+EXTENSION...]\n\
11685 generate code for CPU and EXTENSION, CPU is one of:\n"));
11686 show_arch (stream
, 0, 1);
11687 fprintf (stream
, _("\
11688 EXTENSION is combination of:\n"));
11689 show_arch (stream
, 1, 0);
11690 fprintf (stream
, _("\
11691 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11692 show_arch (stream
, 0, 0);
11693 fprintf (stream
, _("\
11694 -msse2avx encode SSE instructions with VEX prefix\n"));
11695 fprintf (stream
, _("\
11696 -msse-check=[none|error|warning] (default: warning)\n\
11697 check SSE instructions\n"));
11698 fprintf (stream
, _("\
11699 -moperand-check=[none|error|warning] (default: warning)\n\
11700 check operand combinations for validity\n"));
11701 fprintf (stream
, _("\
11702 -mavxscalar=[128|256] (default: 128)\n\
11703 encode scalar AVX instructions with specific vector\n\
11705 fprintf (stream
, _("\
11706 -mvexwig=[0|1] (default: 0)\n\
11707 encode VEX instructions with specific VEX.W value\n\
11708 for VEX.W bit ignored instructions\n"));
11709 fprintf (stream
, _("\
11710 -mevexlig=[128|256|512] (default: 128)\n\
11711 encode scalar EVEX instructions with specific vector\n\
11713 fprintf (stream
, _("\
11714 -mevexwig=[0|1] (default: 0)\n\
11715 encode EVEX instructions with specific EVEX.W value\n\
11716 for EVEX.W bit ignored instructions\n"));
11717 fprintf (stream
, _("\
11718 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11719 encode EVEX instructions with specific EVEX.RC value\n\
11720 for SAE-only ignored instructions\n"));
11721 fprintf (stream
, _("\
11722 -mmnemonic=[att|intel] "));
11723 if (SYSV386_COMPAT
)
11724 fprintf (stream
, _("(default: att)\n"));
11726 fprintf (stream
, _("(default: intel)\n"));
11727 fprintf (stream
, _("\
11728 use AT&T/Intel mnemonic\n"));
11729 fprintf (stream
, _("\
11730 -msyntax=[att|intel] (default: att)\n\
11731 use AT&T/Intel syntax\n"));
11732 fprintf (stream
, _("\
11733 -mindex-reg support pseudo index registers\n"));
11734 fprintf (stream
, _("\
11735 -mnaked-reg don't require `%%' prefix for registers\n"));
11736 fprintf (stream
, _("\
11737 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11738 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11739 fprintf (stream
, _("\
11740 -mshared disable branch optimization for shared code\n"));
11741 fprintf (stream
, _("\
11742 -mx86-used-note=[no|yes] "));
11743 if (DEFAULT_X86_USED_NOTE
)
11744 fprintf (stream
, _("(default: yes)\n"));
11746 fprintf (stream
, _("(default: no)\n"));
11747 fprintf (stream
, _("\
11748 generate x86 used ISA and feature properties\n"));
11750 #if defined (TE_PE) || defined (TE_PEP)
11751 fprintf (stream
, _("\
11752 -mbig-obj generate big object files\n"));
11754 fprintf (stream
, _("\
11755 -momit-lock-prefix=[no|yes] (default: no)\n\
11756 strip all lock prefixes\n"));
11757 fprintf (stream
, _("\
11758 -mfence-as-lock-add=[no|yes] (default: no)\n\
11759 encode lfence, mfence and sfence as\n\
11760 lock addl $0x0, (%%{re}sp)\n"));
11761 fprintf (stream
, _("\
11762 -mrelax-relocations=[no|yes] "));
11763 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
11764 fprintf (stream
, _("(default: yes)\n"));
11766 fprintf (stream
, _("(default: no)\n"));
11767 fprintf (stream
, _("\
11768 generate relax relocations\n"));
11769 fprintf (stream
, _("\
11770 -mamd64 accept only AMD64 ISA [default]\n"));
11771 fprintf (stream
, _("\
11772 -mintel64 accept only Intel64 ISA\n"));
11775 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11776 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11777 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11779 /* Pick the target format to use. */
11782 i386_target_format (void)
11784 if (!strncmp (default_arch
, "x86_64", 6))
11786 update_code_flag (CODE_64BIT
, 1);
11787 if (default_arch
[6] == '\0')
11788 x86_elf_abi
= X86_64_ABI
;
11790 x86_elf_abi
= X86_64_X32_ABI
;
11792 else if (!strcmp (default_arch
, "i386"))
11793 update_code_flag (CODE_32BIT
, 1);
11794 else if (!strcmp (default_arch
, "iamcu"))
11796 update_code_flag (CODE_32BIT
, 1);
11797 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
11799 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
11800 cpu_arch_name
= "iamcu";
11801 cpu_sub_arch_name
= NULL
;
11802 cpu_arch_flags
= iamcu_flags
;
11803 cpu_arch_isa
= PROCESSOR_IAMCU
;
11804 cpu_arch_isa_flags
= iamcu_flags
;
11805 if (!cpu_arch_tune_set
)
11807 cpu_arch_tune
= cpu_arch_isa
;
11808 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
11811 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
11812 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11816 as_fatal (_("unknown architecture"));
11818 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
11819 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11820 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
11821 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
11823 switch (OUTPUT_FLAVOR
)
11825 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11826 case bfd_target_aout_flavour
:
11827 return AOUT_TARGET_FORMAT
;
11829 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11830 # if defined (TE_PE) || defined (TE_PEP)
11831 case bfd_target_coff_flavour
:
11832 if (flag_code
== CODE_64BIT
)
11833 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
11836 # elif defined (TE_GO32)
11837 case bfd_target_coff_flavour
:
11838 return "coff-go32";
11840 case bfd_target_coff_flavour
:
11841 return "coff-i386";
11844 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11845 case bfd_target_elf_flavour
:
11847 const char *format
;
11849 switch (x86_elf_abi
)
11852 format
= ELF_TARGET_FORMAT
;
11855 use_rela_relocations
= 1;
11857 format
= ELF_TARGET_FORMAT64
;
11859 case X86_64_X32_ABI
:
11860 use_rela_relocations
= 1;
11862 disallow_64bit_reloc
= 1;
11863 format
= ELF_TARGET_FORMAT32
;
11866 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11868 if (x86_elf_abi
!= X86_64_ABI
)
11869 as_fatal (_("Intel L1OM is 64bit only"));
11870 return ELF_TARGET_L1OM_FORMAT
;
11872 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11874 if (x86_elf_abi
!= X86_64_ABI
)
11875 as_fatal (_("Intel K1OM is 64bit only"));
11876 return ELF_TARGET_K1OM_FORMAT
;
11878 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11880 if (x86_elf_abi
!= I386_ABI
)
11881 as_fatal (_("Intel MCU is 32bit only"));
11882 return ELF_TARGET_IAMCU_FORMAT
;
11888 #if defined (OBJ_MACH_O)
11889 case bfd_target_mach_o_flavour
:
11890 if (flag_code
== CODE_64BIT
)
11892 use_rela_relocations
= 1;
11894 return "mach-o-x86-64";
11897 return "mach-o-i386";
11905 #endif /* OBJ_MAYBE_ more than one */
11908 md_undefined_symbol (char *name
)
11910 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11911 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11912 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11913 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11917 if (symbol_find (name
))
11918 as_bad (_("GOT already in symbol table"));
11919 GOT_symbol
= symbol_new (name
, undefined_section
,
11920 (valueT
) 0, &zero_address_frag
);
11927 /* Round up a section size to the appropriate boundary. */
11930 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11932 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11933 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11935 /* For a.out, force the section size to be aligned. If we don't do
11936 this, BFD will align it for us, but it will not write out the
11937 final bytes of the section. This may be a bug in BFD, but it is
11938 easier to fix it here since that is how the other a.out targets
11942 align
= bfd_section_alignment (segment
);
11943 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11950 /* On the i386, PC-relative offsets are relative to the start of the
11951 next instruction. That is, the address of the offset, plus its
11952 size, since the offset is always the last part of the insn. */
11955 md_pcrel_from (fixS
*fixP
)
11957 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11963 s_bss (int ignore ATTRIBUTE_UNUSED
)
11967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11969 obj_elf_section_change_hook ();
11971 temp
= get_absolute_expression ();
11972 subseg_set (bss_section
, (subsegT
) temp
);
11973 demand_empty_rest_of_line ();
11979 i386_validate_fix (fixS
*fixp
)
11981 if (fixp
->fx_subsy
)
11983 if (fixp
->fx_subsy
== GOT_symbol
)
11985 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11990 if (fixp
->fx_tcbit2
)
11991 fixp
->fx_r_type
= (fixp
->fx_tcbit
11992 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11993 : BFD_RELOC_X86_64_GOTPCRELX
);
11996 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
12001 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
12003 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
12005 fixp
->fx_subsy
= 0;
12008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12009 else if (!object_64bit
)
12011 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
12012 && fixp
->fx_tcbit2
)
12013 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
12019 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12022 bfd_reloc_code_real_type code
;
12024 switch (fixp
->fx_r_type
)
12026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12027 case BFD_RELOC_SIZE32
:
12028 case BFD_RELOC_SIZE64
:
12029 if (S_IS_DEFINED (fixp
->fx_addsy
)
12030 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
12032 /* Resolve size relocation against local symbol to size of
12033 the symbol plus addend. */
12034 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
12035 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
12036 && !fits_in_unsigned_long (value
))
12037 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12038 _("symbol size computation overflow"));
12039 fixp
->fx_addsy
= NULL
;
12040 fixp
->fx_subsy
= NULL
;
12041 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
12045 /* Fall through. */
12047 case BFD_RELOC_X86_64_PLT32
:
12048 case BFD_RELOC_X86_64_GOT32
:
12049 case BFD_RELOC_X86_64_GOTPCREL
:
12050 case BFD_RELOC_X86_64_GOTPCRELX
:
12051 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12052 case BFD_RELOC_386_PLT32
:
12053 case BFD_RELOC_386_GOT32
:
12054 case BFD_RELOC_386_GOT32X
:
12055 case BFD_RELOC_386_GOTOFF
:
12056 case BFD_RELOC_386_GOTPC
:
12057 case BFD_RELOC_386_TLS_GD
:
12058 case BFD_RELOC_386_TLS_LDM
:
12059 case BFD_RELOC_386_TLS_LDO_32
:
12060 case BFD_RELOC_386_TLS_IE_32
:
12061 case BFD_RELOC_386_TLS_IE
:
12062 case BFD_RELOC_386_TLS_GOTIE
:
12063 case BFD_RELOC_386_TLS_LE_32
:
12064 case BFD_RELOC_386_TLS_LE
:
12065 case BFD_RELOC_386_TLS_GOTDESC
:
12066 case BFD_RELOC_386_TLS_DESC_CALL
:
12067 case BFD_RELOC_X86_64_TLSGD
:
12068 case BFD_RELOC_X86_64_TLSLD
:
12069 case BFD_RELOC_X86_64_DTPOFF32
:
12070 case BFD_RELOC_X86_64_DTPOFF64
:
12071 case BFD_RELOC_X86_64_GOTTPOFF
:
12072 case BFD_RELOC_X86_64_TPOFF32
:
12073 case BFD_RELOC_X86_64_TPOFF64
:
12074 case BFD_RELOC_X86_64_GOTOFF64
:
12075 case BFD_RELOC_X86_64_GOTPC32
:
12076 case BFD_RELOC_X86_64_GOT64
:
12077 case BFD_RELOC_X86_64_GOTPCREL64
:
12078 case BFD_RELOC_X86_64_GOTPC64
:
12079 case BFD_RELOC_X86_64_GOTPLT64
:
12080 case BFD_RELOC_X86_64_PLTOFF64
:
12081 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12082 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12083 case BFD_RELOC_RVA
:
12084 case BFD_RELOC_VTABLE_ENTRY
:
12085 case BFD_RELOC_VTABLE_INHERIT
:
12087 case BFD_RELOC_32_SECREL
:
12089 code
= fixp
->fx_r_type
;
12091 case BFD_RELOC_X86_64_32S
:
12092 if (!fixp
->fx_pcrel
)
12094 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12095 code
= fixp
->fx_r_type
;
12098 /* Fall through. */
12100 if (fixp
->fx_pcrel
)
12102 switch (fixp
->fx_size
)
12105 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12106 _("can not do %d byte pc-relative relocation"),
12108 code
= BFD_RELOC_32_PCREL
;
12110 case 1: code
= BFD_RELOC_8_PCREL
; break;
12111 case 2: code
= BFD_RELOC_16_PCREL
; break;
12112 case 4: code
= BFD_RELOC_32_PCREL
; break;
12114 case 8: code
= BFD_RELOC_64_PCREL
; break;
12120 switch (fixp
->fx_size
)
12123 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12124 _("can not do %d byte relocation"),
12126 code
= BFD_RELOC_32
;
12128 case 1: code
= BFD_RELOC_8
; break;
12129 case 2: code
= BFD_RELOC_16
; break;
12130 case 4: code
= BFD_RELOC_32
; break;
12132 case 8: code
= BFD_RELOC_64
; break;
12139 if ((code
== BFD_RELOC_32
12140 || code
== BFD_RELOC_32_PCREL
12141 || code
== BFD_RELOC_X86_64_32S
)
12143 && fixp
->fx_addsy
== GOT_symbol
)
12146 code
= BFD_RELOC_386_GOTPC
;
12148 code
= BFD_RELOC_X86_64_GOTPC32
;
12150 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
12152 && fixp
->fx_addsy
== GOT_symbol
)
12154 code
= BFD_RELOC_X86_64_GOTPC64
;
12157 rel
= XNEW (arelent
);
12158 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
12159 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12161 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12163 if (!use_rela_relocations
)
12165 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12166 vtable entry to be used in the relocation's section offset. */
12167 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12168 rel
->address
= fixp
->fx_offset
;
12169 #if defined (OBJ_COFF) && defined (TE_PE)
12170 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
12171 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
12176 /* Use the rela in 64bit mode. */
12179 if (disallow_64bit_reloc
)
12182 case BFD_RELOC_X86_64_DTPOFF64
:
12183 case BFD_RELOC_X86_64_TPOFF64
:
12184 case BFD_RELOC_64_PCREL
:
12185 case BFD_RELOC_X86_64_GOTOFF64
:
12186 case BFD_RELOC_X86_64_GOT64
:
12187 case BFD_RELOC_X86_64_GOTPCREL64
:
12188 case BFD_RELOC_X86_64_GOTPC64
:
12189 case BFD_RELOC_X86_64_GOTPLT64
:
12190 case BFD_RELOC_X86_64_PLTOFF64
:
12191 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12192 _("cannot represent relocation type %s in x32 mode"),
12193 bfd_get_reloc_code_name (code
));
12199 if (!fixp
->fx_pcrel
)
12200 rel
->addend
= fixp
->fx_offset
;
12204 case BFD_RELOC_X86_64_PLT32
:
12205 case BFD_RELOC_X86_64_GOT32
:
12206 case BFD_RELOC_X86_64_GOTPCREL
:
12207 case BFD_RELOC_X86_64_GOTPCRELX
:
12208 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
12209 case BFD_RELOC_X86_64_TLSGD
:
12210 case BFD_RELOC_X86_64_TLSLD
:
12211 case BFD_RELOC_X86_64_GOTTPOFF
:
12212 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12213 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12214 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
12217 rel
->addend
= (section
->vma
12219 + fixp
->fx_addnumber
12220 + md_pcrel_from (fixp
));
12225 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12226 if (rel
->howto
== NULL
)
12228 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12229 _("cannot represent relocation type %s"),
12230 bfd_get_reloc_code_name (code
));
12231 /* Set howto to a garbage value so that we can keep going. */
12232 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
12233 gas_assert (rel
->howto
!= NULL
);
12239 #include "tc-i386-intel.c"
12242 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
12244 int saved_naked_reg
;
12245 char saved_register_dot
;
12247 saved_naked_reg
= allow_naked_reg
;
12248 allow_naked_reg
= 1;
12249 saved_register_dot
= register_chars
['.'];
12250 register_chars
['.'] = '.';
12251 allow_pseudo_reg
= 1;
12252 expression_and_evaluate (exp
);
12253 allow_pseudo_reg
= 0;
12254 register_chars
['.'] = saved_register_dot
;
12255 allow_naked_reg
= saved_naked_reg
;
12257 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
12259 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
12261 exp
->X_op
= O_constant
;
12262 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
12263 .dw2_regnum
[flag_code
>> 1];
12266 exp
->X_op
= O_illegal
;
12271 tc_x86_frame_initial_instructions (void)
12273 static unsigned int sp_regno
[2];
12275 if (!sp_regno
[flag_code
>> 1])
12277 char *saved_input
= input_line_pointer
;
12278 char sp
[][4] = {"esp", "rsp"};
12281 input_line_pointer
= sp
[flag_code
>> 1];
12282 tc_x86_parse_to_dw2regnum (&exp
);
12283 gas_assert (exp
.X_op
== O_constant
);
12284 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
12285 input_line_pointer
= saved_input
;
12288 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
12289 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
12293 x86_dwarf2_addr_size (void)
12295 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12296 if (x86_elf_abi
== X86_64_X32_ABI
)
12299 return bfd_arch_bits_per_address (stdoutput
) / 8;
12303 i386_elf_section_type (const char *str
, size_t len
)
12305 if (flag_code
== CODE_64BIT
12306 && len
== sizeof ("unwind") - 1
12307 && strncmp (str
, "unwind", 6) == 0)
12308 return SHT_X86_64_UNWIND
;
12315 i386_solaris_fix_up_eh_frame (segT sec
)
12317 if (flag_code
== CODE_64BIT
)
12318 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
12324 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
12328 exp
.X_op
= O_secrel
;
12329 exp
.X_add_symbol
= symbol
;
12330 exp
.X_add_number
= 0;
12331 emit_expr (&exp
, size
);
12335 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12336 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12339 x86_64_section_letter (int letter
, const char **ptr_msg
)
12341 if (flag_code
== CODE_64BIT
)
12344 return SHF_X86_64_LARGE
;
12346 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12349 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
12354 x86_64_section_word (char *str
, size_t len
)
12356 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
12357 return SHF_X86_64_LARGE
;
12363 handle_large_common (int small ATTRIBUTE_UNUSED
)
12365 if (flag_code
!= CODE_64BIT
)
12367 s_comm_internal (0, elf_common_parse
);
12368 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12372 static segT lbss_section
;
12373 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
12374 asection
*saved_bss_section
= bss_section
;
12376 if (lbss_section
== NULL
)
12378 flagword applicable
;
12379 segT seg
= now_seg
;
12380 subsegT subseg
= now_subseg
;
12382 /* The .lbss section is for local .largecomm symbols. */
12383 lbss_section
= subseg_new (".lbss", 0);
12384 applicable
= bfd_applicable_section_flags (stdoutput
);
12385 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
12386 seg_info (lbss_section
)->bss
= 1;
12388 subseg_set (seg
, subseg
);
12391 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
12392 bss_section
= lbss_section
;
12394 s_comm_internal (0, elf_common_parse
);
12396 elf_com_section_ptr
= saved_com_section_ptr
;
12397 bss_section
= saved_bss_section
;
12400 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */