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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 };
285
286 struct _i386_insn
287 {
288 /* TM holds the template for the insn were currently assembling. */
289 insn_template tm;
290
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
293 char suffix;
294
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
300 operands. */
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
306
307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
310
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
314
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
317
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
327
328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
338 modrm_byte rm;
339 rex_byte rex;
340 rex_byte vrex;
341 sib_byte sib;
342 vex_prefix vex;
343
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
363
364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
371
372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
374
375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
377
378 /* How to encode vector instructions. */
379 enum
380 {
381 vex_encoding_default = 0,
382 vex_encoding_vex2,
383 vex_encoding_vex3,
384 vex_encoding_evex
385 } vec_encoding;
386
387 /* REP prefix. */
388 const char *rep_prefix;
389
390 /* HLE prefix. */
391 const char *hle_prefix;
392
393 /* Have BND prefix. */
394 const char *bnd_prefix;
395
396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
398
399 /* Error message. */
400 enum i386_error error;
401 };
402
403 typedef struct _i386_insn i386_insn;
404
405 /* Link RC type with corresponding string, that'll be looked for in
406 asm. */
407 struct RC_name
408 {
409 enum rc_type type;
410 const char *name;
411 unsigned int len;
412 };
413
414 static const struct RC_name RC_NamesTable[] =
415 {
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
421 };
422
423 /* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
425 const char extra_symbol_chars[] = "*%-([{}"
426 #ifdef LEX_AT
427 "@"
428 #endif
429 #ifdef LEX_QM
430 "?"
431 #endif
432 ;
433
434 #if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
436 && !defined (TE_GNU) \
437 && !defined (TE_LINUX) \
438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
440 && !defined (TE_FreeBSD) \
441 && !defined (TE_DragonFly) \
442 && !defined (TE_NetBSD)))
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446 const char *i386_comment_chars = "#/";
447 #define SVR4_COMMENT_CHARS 1
448 #define PREFIX_SEPARATOR '\\'
449
450 #else
451 const char *i386_comment_chars = "#";
452 #define PREFIX_SEPARATOR '/'
453 #endif
454
455 /* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
459 first line of the input file. This is because the compiler outputs
460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
462 '/' isn't otherwise defined. */
463 const char line_comment_chars[] = "#/";
464
465 const char line_separator_chars[] = ";";
466
467 /* Chars that can be used to separate mant from exp in floating point
468 nums. */
469 const char EXP_CHARS[] = "eE";
470
471 /* Chars that mean this number is a floating point constant
472 As in 0f12.456
473 or 0d1.2345e12. */
474 const char FLT_CHARS[] = "fFdDxX";
475
476 /* Tables for lexical analysis. */
477 static char mnemonic_chars[256];
478 static char register_chars[256];
479 static char operand_chars[256];
480 static char identifier_chars[256];
481 static char digit_chars[256];
482
483 /* Lexical macros. */
484 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485 #define is_operand_char(x) (operand_chars[(unsigned char) x])
486 #define is_register_char(x) (register_chars[(unsigned char) x])
487 #define is_space_char(x) ((x) == ' ')
488 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489 #define is_digit_char(x) (digit_chars[(unsigned char) x])
490
491 /* All non-digit non-letter characters that may occur in an operand. */
492 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
493
494 /* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
497 assembler instruction). */
498 static char save_stack[32];
499 static char *save_stack_p;
500 #define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502 #define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
504
505 /* The instruction we're assembling. */
506 static i386_insn i;
507
508 /* Possible templates for current insn. */
509 static const templates *current_templates;
510
511 /* Per instruction expressionS buffers: max displacements & immediates. */
512 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
514
515 /* Current operand we are working on. */
516 static int this_operand = -1;
517
518 /* We support four different modes. FLAG_CODE variable is used to distinguish
519 these. */
520
521 enum flag_code {
522 CODE_32BIT,
523 CODE_16BIT,
524 CODE_64BIT };
525
526 static enum flag_code flag_code;
527 static unsigned int object_64bit;
528 static unsigned int disallow_64bit_reloc;
529 static int use_rela_relocations = 0;
530
531 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
534
535 /* The ELF ABI to use. */
536 enum x86_elf_abi
537 {
538 I386_ABI,
539 X86_64_ABI,
540 X86_64_X32_ABI
541 };
542
543 static enum x86_elf_abi x86_elf_abi = I386_ABI;
544 #endif
545
546 #if defined (TE_PE) || defined (TE_PEP)
547 /* Use big object file format. */
548 static int use_big_obj = 0;
549 #endif
550
551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552 /* 1 if generating code for a shared library. */
553 static int shared = 0;
554 #endif
555
556 /* 1 for intel syntax,
557 0 if att syntax. */
558 static int intel_syntax = 0;
559
560 /* 1 for Intel64 ISA,
561 0 if AMD64 ISA. */
562 static int intel64;
563
564 /* 1 for intel mnemonic,
565 0 if att mnemonic. */
566 static int intel_mnemonic = !SYSV386_COMPAT;
567
568 /* 1 if support old (<= 2.8.1) versions of gcc. */
569 static int old_gcc = OLDGCC_COMPAT;
570
571 /* 1 if pseudo registers are permitted. */
572 static int allow_pseudo_reg = 0;
573
574 /* 1 if register prefix % not required. */
575 static int allow_naked_reg = 0;
576
577 /* 1 if the assembler should add BND prefix for all control-transferring
578 instructions supporting it, even if this prefix wasn't specified
579 explicitly. */
580 static int add_bnd_prefix = 0;
581
582 /* 1 if pseudo index register, eiz/riz, is allowed . */
583 static int allow_index_reg = 0;
584
585 /* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587 static int omit_lock_prefix = 0;
588
589 /* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591 static int avoid_fence = 0;
592
593 /* 1 if the assembler should generate relax relocations. */
594
595 static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
597
598 static enum check_kind
599 {
600 check_none = 0,
601 check_warning,
602 check_error
603 }
604 sse_check, operand_check = check_warning;
605
606 /* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 */
611 static int optimize = 0;
612
613 /* Optimization:
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
616 register.
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
618 "testb $imm7,%r8".
619 */
620 static int optimize_for_space = 0;
621
622 /* Register prefix used for error message. */
623 static const char *register_prefix = "%";
624
625 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628 static char stackop_size = '\0';
629
630 /* Non-zero to optimize code alignment. */
631 int optimize_align_code = 1;
632
633 /* Non-zero to quieten some warnings. */
634 static int quiet_warnings = 0;
635
636 /* CPU name. */
637 static const char *cpu_arch_name = NULL;
638 static char *cpu_sub_arch_name = NULL;
639
640 /* CPU feature flags. */
641 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
642
643 /* If we have selected a cpu we are generating instructions for. */
644 static int cpu_arch_tune_set = 0;
645
646 /* Cpu we are generating instructions for. */
647 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
648
649 /* CPU feature flags of cpu we are generating instructions for. */
650 static i386_cpu_flags cpu_arch_tune_flags;
651
652 /* CPU instruction set architecture used. */
653 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
654
655 /* CPU feature flags of instruction set architecture used. */
656 i386_cpu_flags cpu_arch_isa_flags;
657
658 /* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660 static unsigned int no_cond_jump_promotion = 0;
661
662 /* Encode SSE instructions with VEX prefix. */
663 static unsigned int sse2avx;
664
665 /* Encode scalar AVX instructions with specific vector length. */
666 static enum
667 {
668 vex128 = 0,
669 vex256
670 } avxscalar;
671
672 /* Encode scalar EVEX LIG instructions with specific vector length. */
673 static enum
674 {
675 evexl128 = 0,
676 evexl256,
677 evexl512
678 } evexlig;
679
680 /* Encode EVEX WIG instructions with specific evex.w. */
681 static enum
682 {
683 evexw0 = 0,
684 evexw1
685 } evexwig;
686
687 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
688 static enum rc_type evexrcig = rne;
689
690 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
691 static symbolS *GOT_symbol;
692
693 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
694 unsigned int x86_dwarf2_return_column;
695
696 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697 int x86_cie_data_alignment;
698
699 /* Interface to relax_segment.
700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
703
704 /* Types. */
705 #define UNCOND_JUMP 0
706 #define COND_JUMP 1
707 #define COND_JUMP86 2
708
709 /* Sizes. */
710 #define CODE16 1
711 #define SMALL 0
712 #define SMALL16 (SMALL | CODE16)
713 #define BIG 2
714 #define BIG16 (BIG | CODE16)
715
716 #ifndef INLINE
717 #ifdef __GNUC__
718 #define INLINE __inline__
719 #else
720 #define INLINE
721 #endif
722 #endif
723
724 #define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726 #define TYPE_FROM_RELAX_STATE(s) \
727 ((s) >> 2)
728 #define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
730
731 /* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
738
739 const relax_typeS md_relax_table[] =
740 {
741 /* The fields are:
742 1) most positive reach of this state,
743 2) most negative reach of this state,
744 3) how many bytes this mode will have in the variable part of the frag
745 4) which index into the table to try if we can't fit into this one. */
746
747 /* UNCOND_JUMP states. */
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
752 {0, 0, 4, 0},
753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
755 {0, 0, 2, 0},
756
757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
762 {0, 0, 5, 0},
763 /* word conditionals add 3 bytes to frag:
764 1 extra opcode byte, 2 displacement bytes. */
765 {0, 0, 3, 0},
766
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
772 {0, 0, 5, 0},
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
775 {0, 0, 4, 0}
776 };
777
778 static const arch_entry cpu_arch[] =
779 {
780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
783 CPU_GENERIC32_FLAGS, 0 },
784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
785 CPU_GENERIC64_FLAGS, 0 },
786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
787 CPU_NONE_FLAGS, 0 },
788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
789 CPU_I186_FLAGS, 0 },
790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
791 CPU_I286_FLAGS, 0 },
792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
793 CPU_I386_FLAGS, 0 },
794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
795 CPU_I486_FLAGS, 0 },
796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
797 CPU_I586_FLAGS, 0 },
798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
799 CPU_I686_FLAGS, 0 },
800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
801 CPU_I586_FLAGS, 0 },
802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
803 CPU_PENTIUMPRO_FLAGS, 0 },
804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
805 CPU_P2_FLAGS, 0 },
806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
807 CPU_P3_FLAGS, 0 },
808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
809 CPU_P4_FLAGS, 0 },
810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
811 CPU_CORE_FLAGS, 0 },
812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
813 CPU_NOCONA_FLAGS, 0 },
814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
815 CPU_CORE_FLAGS, 1 },
816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
817 CPU_CORE_FLAGS, 0 },
818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
819 CPU_CORE2_FLAGS, 1 },
820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
821 CPU_CORE2_FLAGS, 0 },
822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
823 CPU_COREI7_FLAGS, 0 },
824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
825 CPU_L1OM_FLAGS, 0 },
826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
827 CPU_K1OM_FLAGS, 0 },
828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
829 CPU_IAMCU_FLAGS, 0 },
830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
831 CPU_K6_FLAGS, 0 },
832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
833 CPU_K6_2_FLAGS, 0 },
834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
835 CPU_ATHLON_FLAGS, 0 },
836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
837 CPU_K8_FLAGS, 1 },
838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
839 CPU_K8_FLAGS, 0 },
840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
841 CPU_K8_FLAGS, 0 },
842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
843 CPU_AMDFAM10_FLAGS, 0 },
844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
845 CPU_BDVER1_FLAGS, 0 },
846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
847 CPU_BDVER2_FLAGS, 0 },
848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
849 CPU_BDVER3_FLAGS, 0 },
850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
851 CPU_BDVER4_FLAGS, 0 },
852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
853 CPU_ZNVER1_FLAGS, 0 },
854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
855 CPU_BTVER1_FLAGS, 0 },
856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
857 CPU_BTVER2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
859 CPU_8087_FLAGS, 0 },
860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
861 CPU_287_FLAGS, 0 },
862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
863 CPU_387_FLAGS, 0 },
864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
865 CPU_687_FLAGS, 0 },
866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
867 CPU_MMX_FLAGS, 0 },
868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
869 CPU_SSE_FLAGS, 0 },
870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
871 CPU_SSE2_FLAGS, 0 },
872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
873 CPU_SSE3_FLAGS, 0 },
874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
875 CPU_SSSE3_FLAGS, 0 },
876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
877 CPU_SSE4_1_FLAGS, 0 },
878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
879 CPU_SSE4_2_FLAGS, 0 },
880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
881 CPU_SSE4_2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
883 CPU_AVX_FLAGS, 0 },
884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
885 CPU_AVX2_FLAGS, 0 },
886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
887 CPU_AVX512F_FLAGS, 0 },
888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
889 CPU_AVX512CD_FLAGS, 0 },
890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
891 CPU_AVX512ER_FLAGS, 0 },
892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
893 CPU_AVX512PF_FLAGS, 0 },
894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
895 CPU_AVX512DQ_FLAGS, 0 },
896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
897 CPU_AVX512BW_FLAGS, 0 },
898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
899 CPU_AVX512VL_FLAGS, 0 },
900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
901 CPU_VMX_FLAGS, 0 },
902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
903 CPU_VMFUNC_FLAGS, 0 },
904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
905 CPU_SMX_FLAGS, 0 },
906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
907 CPU_XSAVE_FLAGS, 0 },
908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
909 CPU_XSAVEOPT_FLAGS, 0 },
910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
911 CPU_XSAVEC_FLAGS, 0 },
912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
913 CPU_XSAVES_FLAGS, 0 },
914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
915 CPU_AES_FLAGS, 0 },
916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
917 CPU_PCLMUL_FLAGS, 0 },
918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
919 CPU_PCLMUL_FLAGS, 1 },
920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
921 CPU_FSGSBASE_FLAGS, 0 },
922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
923 CPU_RDRND_FLAGS, 0 },
924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
925 CPU_F16C_FLAGS, 0 },
926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
927 CPU_BMI2_FLAGS, 0 },
928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
929 CPU_FMA_FLAGS, 0 },
930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
931 CPU_FMA4_FLAGS, 0 },
932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
933 CPU_XOP_FLAGS, 0 },
934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
935 CPU_LWP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
937 CPU_MOVBE_FLAGS, 0 },
938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
939 CPU_CX16_FLAGS, 0 },
940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
941 CPU_EPT_FLAGS, 0 },
942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
943 CPU_LZCNT_FLAGS, 0 },
944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
945 CPU_HLE_FLAGS, 0 },
946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
947 CPU_RTM_FLAGS, 0 },
948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
949 CPU_INVPCID_FLAGS, 0 },
950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
951 CPU_CLFLUSH_FLAGS, 0 },
952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
953 CPU_NOP_FLAGS, 0 },
954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
955 CPU_SYSCALL_FLAGS, 0 },
956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
957 CPU_RDTSCP_FLAGS, 0 },
958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
959 CPU_3DNOW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
961 CPU_3DNOWA_FLAGS, 0 },
962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
963 CPU_PADLOCK_FLAGS, 0 },
964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
965 CPU_SVME_FLAGS, 1 },
966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
967 CPU_SVME_FLAGS, 0 },
968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
969 CPU_SSE4A_FLAGS, 0 },
970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
971 CPU_ABM_FLAGS, 0 },
972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
973 CPU_BMI_FLAGS, 0 },
974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
975 CPU_TBM_FLAGS, 0 },
976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
977 CPU_ADX_FLAGS, 0 },
978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
979 CPU_RDSEED_FLAGS, 0 },
980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
981 CPU_PRFCHW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
983 CPU_SMAP_FLAGS, 0 },
984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
985 CPU_MPX_FLAGS, 0 },
986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
987 CPU_SHA_FLAGS, 0 },
988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
989 CPU_CLFLUSHOPT_FLAGS, 0 },
990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
991 CPU_PREFETCHWT1_FLAGS, 0 },
992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
993 CPU_SE1_FLAGS, 0 },
994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
995 CPU_CLWB_FLAGS, 0 },
996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
997 CPU_AVX512IFMA_FLAGS, 0 },
998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
999 CPU_AVX512VBMI_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1013 CPU_CLZERO_FLAGS, 0 },
1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1015 CPU_MWAITX_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1017 CPU_OSPKE_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1019 CPU_RDPID_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1023 CPU_IBT_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
1036 };
1037
1038 static const noarch_entry cpu_noarch[] =
1039 {
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1071 };
1072
1073 #ifdef I386COFF
1074 /* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1076
1077 static symbolS *
1078 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1079 {
1080 addressT align = 0;
1081
1082 SKIP_WHITESPACE ();
1083
1084 if (needs_align
1085 && *input_line_pointer == ',')
1086 {
1087 align = parse_align (needs_align - 1);
1088
1089 if (align == (addressT) -1)
1090 return NULL;
1091 }
1092 else
1093 {
1094 if (size >= 8)
1095 align = 3;
1096 else if (size >= 4)
1097 align = 2;
1098 else if (size >= 2)
1099 align = 1;
1100 else
1101 align = 0;
1102 }
1103
1104 bss_alloc (symbolP, size, align);
1105 return symbolP;
1106 }
1107
1108 static void
1109 pe_lcomm (int needs_align)
1110 {
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1112 }
1113 #endif
1114
1115 const pseudo_typeS md_pseudo_table[] =
1116 {
1117 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1119 #else
1120 {"align", s_align_ptwo, 0},
1121 #endif
1122 {"arch", set_cpu_arch, 0},
1123 #ifndef I386COFF
1124 {"bss", s_bss, 0},
1125 #else
1126 {"lcomm", pe_lcomm, 1},
1127 #endif
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1131 {"value", cons, 2},
1132 {"slong", signed_cons, 4},
1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
1138 #ifdef BFD64
1139 {"code64", set_code_flag, CODE_64BIT},
1140 #endif
1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
1149 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
1151 #else
1152 {"file", dwarf2_directive_file, 0},
1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1155 #endif
1156 #ifdef TE_PE
1157 {"secrel32", pe_directive_secrel, 0},
1158 #endif
1159 {0, 0, 0}
1160 };
1161
1162 /* For interface with expression (). */
1163 extern char *input_line_pointer;
1164
1165 /* Hash table for instruction mnemonic lookup. */
1166 static struct hash_control *op_hash;
1167
1168 /* Hash table for register lookup. */
1169 static struct hash_control *reg_hash;
1170 \f
1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
1174 static const unsigned char f32_1[] =
1175 {0x90}; /* nop */
1176 static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178 static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180 static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1182 static const unsigned char f32_6[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184 static const unsigned char f32_7[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1186 static const unsigned char f16_3[] =
1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1188 static const unsigned char f16_4[] =
1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190 static const unsigned char jump_disp8[] =
1191 {0xeb}; /* jmp disp8 */
1192 static const unsigned char jump32_disp32[] =
1193 {0xe9}; /* jmp disp32 */
1194 static const unsigned char jump16_disp32[] =
1195 {0x66,0xe9}; /* jmp disp32 */
1196 /* 32-bit NOPs patterns. */
1197 static const unsigned char *const f32_patt[] = {
1198 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1199 };
1200 /* 16-bit NOPs patterns. */
1201 static const unsigned char *const f16_patt[] = {
1202 f32_1, f32_2, f16_3, f16_4
1203 };
1204 /* nopl (%[re]ax) */
1205 static const unsigned char alt_3[] =
1206 {0x0f,0x1f,0x00};
1207 /* nopl 0(%[re]ax) */
1208 static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210 /* nopl 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopw 0(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopl 0L(%[re]ax) */
1217 static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219 /* nopl 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw 0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* data16 nopw %cs:0L(%eax,%eax,1) */
1229 static const unsigned char alt_11[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* 32-bit and 64-bit NOPs patterns. */
1232 static const unsigned char *const alt_patt[] = {
1233 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1234 alt_9, alt_10, alt_11
1235 };
1236
1237 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1239
1240 static void
1241 i386_output_nops (char *where, const unsigned char *const *patt,
1242 int count, int max_single_nop_size)
1243
1244 {
1245 /* Place the longer NOP first. */
1246 int last;
1247 int offset;
1248 const unsigned char *nops = patt[max_single_nop_size - 1];
1249
1250 /* Use the smaller one if the requsted one isn't available. */
1251 if (nops == NULL)
1252 {
1253 max_single_nop_size--;
1254 nops = patt[max_single_nop_size - 1];
1255 }
1256
1257 last = count % max_single_nop_size;
1258
1259 count -= last;
1260 for (offset = 0; offset < count; offset += max_single_nop_size)
1261 memcpy (where + offset, nops, max_single_nop_size);
1262
1263 if (last)
1264 {
1265 nops = patt[last - 1];
1266 if (nops == NULL)
1267 {
1268 /* Use the smaller one plus one-byte NOP if the needed one
1269 isn't available. */
1270 last--;
1271 nops = patt[last - 1];
1272 memcpy (where + offset, nops, last);
1273 where[offset + last] = *patt[0];
1274 }
1275 else
1276 memcpy (where + offset, nops, last);
1277 }
1278 }
1279
1280 static INLINE int
1281 fits_in_imm7 (offsetT num)
1282 {
1283 return (num & 0x7f) == num;
1284 }
1285
1286 static INLINE int
1287 fits_in_imm31 (offsetT num)
1288 {
1289 return (num & 0x7fffffff) == num;
1290 }
1291
1292 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1294
1295 void
1296 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1297 {
1298 const unsigned char *const *patt = NULL;
1299 int max_single_nop_size;
1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops;
1302
1303 switch (fragP->fr_type)
1304 {
1305 case rs_fill_nop:
1306 case rs_align_code:
1307 break;
1308 default:
1309 return;
1310 }
1311
1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
1314
1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
1317 2. For the rest, alt_patt will be used.
1318
1319 When -mtune= isn't used, alt_patt will be used if
1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1321 be used.
1322
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1325
1326 if (flag_code == CODE_16BIT)
1327 {
1328 patt = f16_patt;
1329 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops = 2;
1332 }
1333 else
1334 {
1335 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1336 {
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune)
1339 {
1340 case PROCESSOR_UNKNOWN:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
1342 optimize with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1344 patt = alt_patt;
1345 else
1346 patt = f32_patt;
1347 break;
1348 case PROCESSOR_PENTIUM4:
1349 case PROCESSOR_NOCONA:
1350 case PROCESSOR_CORE:
1351 case PROCESSOR_CORE2:
1352 case PROCESSOR_COREI7:
1353 case PROCESSOR_L1OM:
1354 case PROCESSOR_K1OM:
1355 case PROCESSOR_GENERIC64:
1356 case PROCESSOR_K6:
1357 case PROCESSOR_ATHLON:
1358 case PROCESSOR_K8:
1359 case PROCESSOR_AMDFAM10:
1360 case PROCESSOR_BD:
1361 case PROCESSOR_ZNVER:
1362 case PROCESSOR_BT:
1363 patt = alt_patt;
1364 break;
1365 case PROCESSOR_I386:
1366 case PROCESSOR_I486:
1367 case PROCESSOR_PENTIUM:
1368 case PROCESSOR_PENTIUMPRO:
1369 case PROCESSOR_IAMCU:
1370 case PROCESSOR_GENERIC32:
1371 patt = f32_patt;
1372 break;
1373 }
1374 }
1375 else
1376 {
1377 switch (fragP->tc_frag_data.tune)
1378 {
1379 case PROCESSOR_UNKNOWN:
1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1381 PROCESSOR_UNKNOWN. */
1382 abort ();
1383 break;
1384
1385 case PROCESSOR_I386:
1386 case PROCESSOR_I486:
1387 case PROCESSOR_PENTIUM:
1388 case PROCESSOR_IAMCU:
1389 case PROCESSOR_K6:
1390 case PROCESSOR_ATHLON:
1391 case PROCESSOR_K8:
1392 case PROCESSOR_AMDFAM10:
1393 case PROCESSOR_BD:
1394 case PROCESSOR_ZNVER:
1395 case PROCESSOR_BT:
1396 case PROCESSOR_GENERIC32:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
1398 with nops. */
1399 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1400 patt = alt_patt;
1401 else
1402 patt = f32_patt;
1403 break;
1404 case PROCESSOR_PENTIUMPRO:
1405 case PROCESSOR_PENTIUM4:
1406 case PROCESSOR_NOCONA:
1407 case PROCESSOR_CORE:
1408 case PROCESSOR_CORE2:
1409 case PROCESSOR_COREI7:
1410 case PROCESSOR_L1OM:
1411 case PROCESSOR_K1OM:
1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1413 patt = alt_patt;
1414 else
1415 patt = f32_patt;
1416 break;
1417 case PROCESSOR_GENERIC64:
1418 patt = alt_patt;
1419 break;
1420 }
1421 }
1422
1423 if (patt == f32_patt)
1424 {
1425 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops = 2;
1428 }
1429 else
1430 {
1431 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops = 7;
1434 }
1435 }
1436
1437 if (limit == 0)
1438 limit = max_single_nop_size;
1439
1440 if (fragP->fr_type == rs_fill_nop)
1441 {
1442 /* Output NOPs for .nop directive. */
1443 if (limit > max_single_nop_size)
1444 {
1445 as_bad_where (fragP->fr_file, fragP->fr_line,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit, max_single_nop_size);
1449 return;
1450 }
1451 }
1452 else
1453 fragP->fr_var = count;
1454
1455 if ((count / max_single_nop_size) > max_number_of_nops)
1456 {
1457 /* Generate jump over NOPs. */
1458 offsetT disp = count - 2;
1459 if (fits_in_imm7 (disp))
1460 {
1461 /* Use "jmp disp8" if possible. */
1462 count = disp;
1463 where[0] = jump_disp8[0];
1464 where[1] = count;
1465 where += 2;
1466 }
1467 else
1468 {
1469 unsigned int size_of_jump;
1470
1471 if (flag_code == CODE_16BIT)
1472 {
1473 where[0] = jump16_disp32[0];
1474 where[1] = jump16_disp32[1];
1475 size_of_jump = 2;
1476 }
1477 else
1478 {
1479 where[0] = jump32_disp32[0];
1480 size_of_jump = 1;
1481 }
1482
1483 count -= size_of_jump + 4;
1484 if (!fits_in_imm31 (count))
1485 {
1486 as_bad_where (fragP->fr_file, fragP->fr_line,
1487 _("jump over nop padding out of range"));
1488 return;
1489 }
1490
1491 md_number_to_chars (where + size_of_jump, count, 4);
1492 where += size_of_jump + 4;
1493 }
1494 }
1495
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where, patt, count, limit);
1498 }
1499
1500 static INLINE int
1501 operand_type_all_zero (const union i386_operand_type *x)
1502 {
1503 switch (ARRAY_SIZE(x->array))
1504 {
1505 case 3:
1506 if (x->array[2])
1507 return 0;
1508 /* Fall through. */
1509 case 2:
1510 if (x->array[1])
1511 return 0;
1512 /* Fall through. */
1513 case 1:
1514 return !x->array[0];
1515 default:
1516 abort ();
1517 }
1518 }
1519
1520 static INLINE void
1521 operand_type_set (union i386_operand_type *x, unsigned int v)
1522 {
1523 switch (ARRAY_SIZE(x->array))
1524 {
1525 case 3:
1526 x->array[2] = v;
1527 /* Fall through. */
1528 case 2:
1529 x->array[1] = v;
1530 /* Fall through. */
1531 case 1:
1532 x->array[0] = v;
1533 /* Fall through. */
1534 break;
1535 default:
1536 abort ();
1537 }
1538 }
1539
1540 static INLINE int
1541 operand_type_equal (const union i386_operand_type *x,
1542 const union i386_operand_type *y)
1543 {
1544 switch (ARRAY_SIZE(x->array))
1545 {
1546 case 3:
1547 if (x->array[2] != y->array[2])
1548 return 0;
1549 /* Fall through. */
1550 case 2:
1551 if (x->array[1] != y->array[1])
1552 return 0;
1553 /* Fall through. */
1554 case 1:
1555 return x->array[0] == y->array[0];
1556 break;
1557 default:
1558 abort ();
1559 }
1560 }
1561
1562 static INLINE int
1563 cpu_flags_all_zero (const union i386_cpu_flags *x)
1564 {
1565 switch (ARRAY_SIZE(x->array))
1566 {
1567 case 4:
1568 if (x->array[3])
1569 return 0;
1570 /* Fall through. */
1571 case 3:
1572 if (x->array[2])
1573 return 0;
1574 /* Fall through. */
1575 case 2:
1576 if (x->array[1])
1577 return 0;
1578 /* Fall through. */
1579 case 1:
1580 return !x->array[0];
1581 default:
1582 abort ();
1583 }
1584 }
1585
1586 static INLINE int
1587 cpu_flags_equal (const union i386_cpu_flags *x,
1588 const union i386_cpu_flags *y)
1589 {
1590 switch (ARRAY_SIZE(x->array))
1591 {
1592 case 4:
1593 if (x->array[3] != y->array[3])
1594 return 0;
1595 /* Fall through. */
1596 case 3:
1597 if (x->array[2] != y->array[2])
1598 return 0;
1599 /* Fall through. */
1600 case 2:
1601 if (x->array[1] != y->array[1])
1602 return 0;
1603 /* Fall through. */
1604 case 1:
1605 return x->array[0] == y->array[0];
1606 break;
1607 default:
1608 abort ();
1609 }
1610 }
1611
1612 static INLINE int
1613 cpu_flags_check_cpu64 (i386_cpu_flags f)
1614 {
1615 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1616 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1617 }
1618
1619 static INLINE i386_cpu_flags
1620 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1621 {
1622 switch (ARRAY_SIZE (x.array))
1623 {
1624 case 4:
1625 x.array [3] &= y.array [3];
1626 /* Fall through. */
1627 case 3:
1628 x.array [2] &= y.array [2];
1629 /* Fall through. */
1630 case 2:
1631 x.array [1] &= y.array [1];
1632 /* Fall through. */
1633 case 1:
1634 x.array [0] &= y.array [0];
1635 break;
1636 default:
1637 abort ();
1638 }
1639 return x;
1640 }
1641
1642 static INLINE i386_cpu_flags
1643 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1644 {
1645 switch (ARRAY_SIZE (x.array))
1646 {
1647 case 4:
1648 x.array [3] |= y.array [3];
1649 /* Fall through. */
1650 case 3:
1651 x.array [2] |= y.array [2];
1652 /* Fall through. */
1653 case 2:
1654 x.array [1] |= y.array [1];
1655 /* Fall through. */
1656 case 1:
1657 x.array [0] |= y.array [0];
1658 break;
1659 default:
1660 abort ();
1661 }
1662 return x;
1663 }
1664
1665 static INLINE i386_cpu_flags
1666 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1667 {
1668 switch (ARRAY_SIZE (x.array))
1669 {
1670 case 4:
1671 x.array [3] &= ~y.array [3];
1672 /* Fall through. */
1673 case 3:
1674 x.array [2] &= ~y.array [2];
1675 /* Fall through. */
1676 case 2:
1677 x.array [1] &= ~y.array [1];
1678 /* Fall through. */
1679 case 1:
1680 x.array [0] &= ~y.array [0];
1681 break;
1682 default:
1683 abort ();
1684 }
1685 return x;
1686 }
1687
1688 #define CPU_FLAGS_ARCH_MATCH 0x1
1689 #define CPU_FLAGS_64BIT_MATCH 0x2
1690
1691 #define CPU_FLAGS_PERFECT_MATCH \
1692 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1693
1694 /* Return CPU flags match bits. */
1695
1696 static int
1697 cpu_flags_match (const insn_template *t)
1698 {
1699 i386_cpu_flags x = t->cpu_flags;
1700 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1701
1702 x.bitfield.cpu64 = 0;
1703 x.bitfield.cpuno64 = 0;
1704
1705 if (cpu_flags_all_zero (&x))
1706 {
1707 /* This instruction is available on all archs. */
1708 match |= CPU_FLAGS_ARCH_MATCH;
1709 }
1710 else
1711 {
1712 /* This instruction is available only on some archs. */
1713 i386_cpu_flags cpu = cpu_arch_flags;
1714
1715 /* AVX512VL is no standalone feature - match it and then strip it. */
1716 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1717 return match;
1718 x.bitfield.cpuavx512vl = 0;
1719
1720 cpu = cpu_flags_and (x, cpu);
1721 if (!cpu_flags_all_zero (&cpu))
1722 {
1723 if (x.bitfield.cpuavx)
1724 {
1725 /* We need to check a few extra flags with AVX. */
1726 if (cpu.bitfield.cpuavx
1727 && (!t->opcode_modifier.sse2avx || sse2avx)
1728 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1729 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1730 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1731 match |= CPU_FLAGS_ARCH_MATCH;
1732 }
1733 else if (x.bitfield.cpuavx512f)
1734 {
1735 /* We need to check a few extra flags with AVX512F. */
1736 if (cpu.bitfield.cpuavx512f
1737 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1738 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1739 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1740 match |= CPU_FLAGS_ARCH_MATCH;
1741 }
1742 else
1743 match |= CPU_FLAGS_ARCH_MATCH;
1744 }
1745 }
1746 return match;
1747 }
1748
1749 static INLINE i386_operand_type
1750 operand_type_and (i386_operand_type x, i386_operand_type y)
1751 {
1752 switch (ARRAY_SIZE (x.array))
1753 {
1754 case 3:
1755 x.array [2] &= y.array [2];
1756 /* Fall through. */
1757 case 2:
1758 x.array [1] &= y.array [1];
1759 /* Fall through. */
1760 case 1:
1761 x.array [0] &= y.array [0];
1762 break;
1763 default:
1764 abort ();
1765 }
1766 return x;
1767 }
1768
1769 static INLINE i386_operand_type
1770 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1771 {
1772 switch (ARRAY_SIZE (x.array))
1773 {
1774 case 3:
1775 x.array [2] &= ~y.array [2];
1776 /* Fall through. */
1777 case 2:
1778 x.array [1] &= ~y.array [1];
1779 /* Fall through. */
1780 case 1:
1781 x.array [0] &= ~y.array [0];
1782 break;
1783 default:
1784 abort ();
1785 }
1786 return x;
1787 }
1788
1789 static INLINE i386_operand_type
1790 operand_type_or (i386_operand_type x, i386_operand_type y)
1791 {
1792 switch (ARRAY_SIZE (x.array))
1793 {
1794 case 3:
1795 x.array [2] |= y.array [2];
1796 /* Fall through. */
1797 case 2:
1798 x.array [1] |= y.array [1];
1799 /* Fall through. */
1800 case 1:
1801 x.array [0] |= y.array [0];
1802 break;
1803 default:
1804 abort ();
1805 }
1806 return x;
1807 }
1808
1809 static INLINE i386_operand_type
1810 operand_type_xor (i386_operand_type x, i386_operand_type y)
1811 {
1812 switch (ARRAY_SIZE (x.array))
1813 {
1814 case 3:
1815 x.array [2] ^= y.array [2];
1816 /* Fall through. */
1817 case 2:
1818 x.array [1] ^= y.array [1];
1819 /* Fall through. */
1820 case 1:
1821 x.array [0] ^= y.array [0];
1822 break;
1823 default:
1824 abort ();
1825 }
1826 return x;
1827 }
1828
1829 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1830 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1831 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1832 static const i386_operand_type inoutportreg
1833 = OPERAND_TYPE_INOUTPORTREG;
1834 static const i386_operand_type reg16_inoutportreg
1835 = OPERAND_TYPE_REG16_INOUTPORTREG;
1836 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1837 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1838 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1839 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1840 static const i386_operand_type anydisp
1841 = OPERAND_TYPE_ANYDISP;
1842 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1843 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1844 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1845 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1846 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1847 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1848 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1849 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1850 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1851 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1852 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1853 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1854
1855 enum operand_type
1856 {
1857 reg,
1858 imm,
1859 disp,
1860 anymem
1861 };
1862
1863 static INLINE int
1864 operand_type_check (i386_operand_type t, enum operand_type c)
1865 {
1866 switch (c)
1867 {
1868 case reg:
1869 return t.bitfield.reg;
1870
1871 case imm:
1872 return (t.bitfield.imm8
1873 || t.bitfield.imm8s
1874 || t.bitfield.imm16
1875 || t.bitfield.imm32
1876 || t.bitfield.imm32s
1877 || t.bitfield.imm64);
1878
1879 case disp:
1880 return (t.bitfield.disp8
1881 || t.bitfield.disp16
1882 || t.bitfield.disp32
1883 || t.bitfield.disp32s
1884 || t.bitfield.disp64);
1885
1886 case anymem:
1887 return (t.bitfield.disp8
1888 || t.bitfield.disp16
1889 || t.bitfield.disp32
1890 || t.bitfield.disp32s
1891 || t.bitfield.disp64
1892 || t.bitfield.baseindex);
1893
1894 default:
1895 abort ();
1896 }
1897
1898 return 0;
1899 }
1900
1901 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1902 operand J for instruction template T. */
1903
1904 static INLINE int
1905 match_reg_size (const insn_template *t, unsigned int j)
1906 {
1907 return !((i.types[j].bitfield.byte
1908 && !t->operand_types[j].bitfield.byte)
1909 || (i.types[j].bitfield.word
1910 && !t->operand_types[j].bitfield.word)
1911 || (i.types[j].bitfield.dword
1912 && !t->operand_types[j].bitfield.dword)
1913 || (i.types[j].bitfield.qword
1914 && !t->operand_types[j].bitfield.qword)
1915 || (i.types[j].bitfield.tbyte
1916 && !t->operand_types[j].bitfield.tbyte));
1917 }
1918
1919 /* Return 1 if there is no conflict in SIMD register on
1920 operand J for instruction template T. */
1921
1922 static INLINE int
1923 match_simd_size (const insn_template *t, unsigned int j)
1924 {
1925 return !((i.types[j].bitfield.xmmword
1926 && !t->operand_types[j].bitfield.xmmword)
1927 || (i.types[j].bitfield.ymmword
1928 && !t->operand_types[j].bitfield.ymmword)
1929 || (i.types[j].bitfield.zmmword
1930 && !t->operand_types[j].bitfield.zmmword));
1931 }
1932
1933 /* Return 1 if there is no conflict in any size on operand J for
1934 instruction template T. */
1935
1936 static INLINE int
1937 match_mem_size (const insn_template *t, unsigned int j)
1938 {
1939 return (match_reg_size (t, j)
1940 && !((i.types[j].bitfield.unspecified
1941 && !i.broadcast
1942 && !t->operand_types[j].bitfield.unspecified)
1943 || (i.types[j].bitfield.fword
1944 && !t->operand_types[j].bitfield.fword)
1945 /* For scalar opcode templates to allow register and memory
1946 operands at the same time, some special casing is needed
1947 here. */
1948 || ((t->operand_types[j].bitfield.regsimd
1949 && !t->opcode_modifier.broadcast
1950 && (t->operand_types[j].bitfield.dword
1951 || t->operand_types[j].bitfield.qword))
1952 ? (i.types[j].bitfield.xmmword
1953 || i.types[j].bitfield.ymmword
1954 || i.types[j].bitfield.zmmword)
1955 : !match_simd_size(t, j))));
1956 }
1957
1958 /* Return 1 if there is no size conflict on any operands for
1959 instruction template T. */
1960
1961 static INLINE int
1962 operand_size_match (const insn_template *t)
1963 {
1964 unsigned int j;
1965 int match = 1;
1966
1967 /* Don't check jump instructions. */
1968 if (t->opcode_modifier.jump
1969 || t->opcode_modifier.jumpbyte
1970 || t->opcode_modifier.jumpdword
1971 || t->opcode_modifier.jumpintersegment)
1972 return match;
1973
1974 /* Check memory and accumulator operand size. */
1975 for (j = 0; j < i.operands; j++)
1976 {
1977 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1978 && t->operand_types[j].bitfield.anysize)
1979 continue;
1980
1981 if (t->operand_types[j].bitfield.reg
1982 && !match_reg_size (t, j))
1983 {
1984 match = 0;
1985 break;
1986 }
1987
1988 if (t->operand_types[j].bitfield.regsimd
1989 && !match_simd_size (t, j))
1990 {
1991 match = 0;
1992 break;
1993 }
1994
1995 if (t->operand_types[j].bitfield.acc
1996 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1997 {
1998 match = 0;
1999 break;
2000 }
2001
2002 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2003 {
2004 match = 0;
2005 break;
2006 }
2007 }
2008
2009 if (match)
2010 return match;
2011 else if (!t->opcode_modifier.d)
2012 {
2013 mismatch:
2014 i.error = operand_size_mismatch;
2015 return 0;
2016 }
2017
2018 /* Check reverse. */
2019 gas_assert (i.operands == 2);
2020
2021 match = 1;
2022 for (j = 0; j < 2; j++)
2023 {
2024 if ((t->operand_types[j].bitfield.reg
2025 || t->operand_types[j].bitfield.acc)
2026 && !match_reg_size (t, j ? 0 : 1))
2027 goto mismatch;
2028
2029 if (i.types[j].bitfield.mem
2030 && !match_mem_size (t, j ? 0 : 1))
2031 goto mismatch;
2032 }
2033
2034 return match;
2035 }
2036
2037 static INLINE int
2038 operand_type_match (i386_operand_type overlap,
2039 i386_operand_type given)
2040 {
2041 i386_operand_type temp = overlap;
2042
2043 temp.bitfield.jumpabsolute = 0;
2044 temp.bitfield.unspecified = 0;
2045 temp.bitfield.byte = 0;
2046 temp.bitfield.word = 0;
2047 temp.bitfield.dword = 0;
2048 temp.bitfield.fword = 0;
2049 temp.bitfield.qword = 0;
2050 temp.bitfield.tbyte = 0;
2051 temp.bitfield.xmmword = 0;
2052 temp.bitfield.ymmword = 0;
2053 temp.bitfield.zmmword = 0;
2054 if (operand_type_all_zero (&temp))
2055 goto mismatch;
2056
2057 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2058 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2059 return 1;
2060
2061 mismatch:
2062 i.error = operand_type_mismatch;
2063 return 0;
2064 }
2065
2066 /* If given types g0 and g1 are registers they must be of the same type
2067 unless the expected operand type register overlap is null.
2068 Memory operand size of certain SIMD instructions is also being checked
2069 here. */
2070
2071 static INLINE int
2072 operand_type_register_match (i386_operand_type g0,
2073 i386_operand_type t0,
2074 i386_operand_type g1,
2075 i386_operand_type t1)
2076 {
2077 if (!g0.bitfield.reg
2078 && !g0.bitfield.regsimd
2079 && (!operand_type_check (g0, anymem)
2080 || g0.bitfield.unspecified
2081 || !t0.bitfield.regsimd))
2082 return 1;
2083
2084 if (!g1.bitfield.reg
2085 && !g1.bitfield.regsimd
2086 && (!operand_type_check (g1, anymem)
2087 || g1.bitfield.unspecified
2088 || !t1.bitfield.regsimd))
2089 return 1;
2090
2091 if (g0.bitfield.byte == g1.bitfield.byte
2092 && g0.bitfield.word == g1.bitfield.word
2093 && g0.bitfield.dword == g1.bitfield.dword
2094 && g0.bitfield.qword == g1.bitfield.qword
2095 && g0.bitfield.xmmword == g1.bitfield.xmmword
2096 && g0.bitfield.ymmword == g1.bitfield.ymmword
2097 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2098 return 1;
2099
2100 if (!(t0.bitfield.byte & t1.bitfield.byte)
2101 && !(t0.bitfield.word & t1.bitfield.word)
2102 && !(t0.bitfield.dword & t1.bitfield.dword)
2103 && !(t0.bitfield.qword & t1.bitfield.qword)
2104 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2105 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2106 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2107 return 1;
2108
2109 i.error = register_type_mismatch;
2110
2111 return 0;
2112 }
2113
2114 static INLINE unsigned int
2115 register_number (const reg_entry *r)
2116 {
2117 unsigned int nr = r->reg_num;
2118
2119 if (r->reg_flags & RegRex)
2120 nr += 8;
2121
2122 if (r->reg_flags & RegVRex)
2123 nr += 16;
2124
2125 return nr;
2126 }
2127
2128 static INLINE unsigned int
2129 mode_from_disp_size (i386_operand_type t)
2130 {
2131 if (t.bitfield.disp8)
2132 return 1;
2133 else if (t.bitfield.disp16
2134 || t.bitfield.disp32
2135 || t.bitfield.disp32s)
2136 return 2;
2137 else
2138 return 0;
2139 }
2140
2141 static INLINE int
2142 fits_in_signed_byte (addressT num)
2143 {
2144 return num + 0x80 <= 0xff;
2145 }
2146
2147 static INLINE int
2148 fits_in_unsigned_byte (addressT num)
2149 {
2150 return num <= 0xff;
2151 }
2152
2153 static INLINE int
2154 fits_in_unsigned_word (addressT num)
2155 {
2156 return num <= 0xffff;
2157 }
2158
2159 static INLINE int
2160 fits_in_signed_word (addressT num)
2161 {
2162 return num + 0x8000 <= 0xffff;
2163 }
2164
2165 static INLINE int
2166 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2167 {
2168 #ifndef BFD64
2169 return 1;
2170 #else
2171 return num + 0x80000000 <= 0xffffffff;
2172 #endif
2173 } /* fits_in_signed_long() */
2174
2175 static INLINE int
2176 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2177 {
2178 #ifndef BFD64
2179 return 1;
2180 #else
2181 return num <= 0xffffffff;
2182 #endif
2183 } /* fits_in_unsigned_long() */
2184
2185 static INLINE int
2186 fits_in_disp8 (offsetT num)
2187 {
2188 int shift = i.memshift;
2189 unsigned int mask;
2190
2191 if (shift == -1)
2192 abort ();
2193
2194 mask = (1 << shift) - 1;
2195
2196 /* Return 0 if NUM isn't properly aligned. */
2197 if ((num & mask))
2198 return 0;
2199
2200 /* Check if NUM will fit in 8bit after shift. */
2201 return fits_in_signed_byte (num >> shift);
2202 }
2203
2204 static INLINE int
2205 fits_in_imm4 (offsetT num)
2206 {
2207 return (num & 0xf) == num;
2208 }
2209
2210 static i386_operand_type
2211 smallest_imm_type (offsetT num)
2212 {
2213 i386_operand_type t;
2214
2215 operand_type_set (&t, 0);
2216 t.bitfield.imm64 = 1;
2217
2218 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2219 {
2220 /* This code is disabled on the 486 because all the Imm1 forms
2221 in the opcode table are slower on the i486. They're the
2222 versions with the implicitly specified single-position
2223 displacement, which has another syntax if you really want to
2224 use that form. */
2225 t.bitfield.imm1 = 1;
2226 t.bitfield.imm8 = 1;
2227 t.bitfield.imm8s = 1;
2228 t.bitfield.imm16 = 1;
2229 t.bitfield.imm32 = 1;
2230 t.bitfield.imm32s = 1;
2231 }
2232 else if (fits_in_signed_byte (num))
2233 {
2234 t.bitfield.imm8 = 1;
2235 t.bitfield.imm8s = 1;
2236 t.bitfield.imm16 = 1;
2237 t.bitfield.imm32 = 1;
2238 t.bitfield.imm32s = 1;
2239 }
2240 else if (fits_in_unsigned_byte (num))
2241 {
2242 t.bitfield.imm8 = 1;
2243 t.bitfield.imm16 = 1;
2244 t.bitfield.imm32 = 1;
2245 t.bitfield.imm32s = 1;
2246 }
2247 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2248 {
2249 t.bitfield.imm16 = 1;
2250 t.bitfield.imm32 = 1;
2251 t.bitfield.imm32s = 1;
2252 }
2253 else if (fits_in_signed_long (num))
2254 {
2255 t.bitfield.imm32 = 1;
2256 t.bitfield.imm32s = 1;
2257 }
2258 else if (fits_in_unsigned_long (num))
2259 t.bitfield.imm32 = 1;
2260
2261 return t;
2262 }
2263
2264 static offsetT
2265 offset_in_range (offsetT val, int size)
2266 {
2267 addressT mask;
2268
2269 switch (size)
2270 {
2271 case 1: mask = ((addressT) 1 << 8) - 1; break;
2272 case 2: mask = ((addressT) 1 << 16) - 1; break;
2273 case 4: mask = ((addressT) 2 << 31) - 1; break;
2274 #ifdef BFD64
2275 case 8: mask = ((addressT) 2 << 63) - 1; break;
2276 #endif
2277 default: abort ();
2278 }
2279
2280 #ifdef BFD64
2281 /* If BFD64, sign extend val for 32bit address mode. */
2282 if (flag_code != CODE_64BIT
2283 || i.prefix[ADDR_PREFIX])
2284 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2285 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2286 #endif
2287
2288 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2289 {
2290 char buf1[40], buf2[40];
2291
2292 sprint_value (buf1, val);
2293 sprint_value (buf2, val & mask);
2294 as_warn (_("%s shortened to %s"), buf1, buf2);
2295 }
2296 return val & mask;
2297 }
2298
2299 enum PREFIX_GROUP
2300 {
2301 PREFIX_EXIST = 0,
2302 PREFIX_LOCK,
2303 PREFIX_REP,
2304 PREFIX_DS,
2305 PREFIX_OTHER
2306 };
2307
2308 /* Returns
2309 a. PREFIX_EXIST if attempting to add a prefix where one from the
2310 same class already exists.
2311 b. PREFIX_LOCK if lock prefix is added.
2312 c. PREFIX_REP if rep/repne prefix is added.
2313 d. PREFIX_DS if ds prefix is added.
2314 e. PREFIX_OTHER if other prefix is added.
2315 */
2316
2317 static enum PREFIX_GROUP
2318 add_prefix (unsigned int prefix)
2319 {
2320 enum PREFIX_GROUP ret = PREFIX_OTHER;
2321 unsigned int q;
2322
2323 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2324 && flag_code == CODE_64BIT)
2325 {
2326 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2327 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2328 && (prefix & (REX_R | REX_X | REX_B))))
2329 ret = PREFIX_EXIST;
2330 q = REX_PREFIX;
2331 }
2332 else
2333 {
2334 switch (prefix)
2335 {
2336 default:
2337 abort ();
2338
2339 case DS_PREFIX_OPCODE:
2340 ret = PREFIX_DS;
2341 /* Fall through. */
2342 case CS_PREFIX_OPCODE:
2343 case ES_PREFIX_OPCODE:
2344 case FS_PREFIX_OPCODE:
2345 case GS_PREFIX_OPCODE:
2346 case SS_PREFIX_OPCODE:
2347 q = SEG_PREFIX;
2348 break;
2349
2350 case REPNE_PREFIX_OPCODE:
2351 case REPE_PREFIX_OPCODE:
2352 q = REP_PREFIX;
2353 ret = PREFIX_REP;
2354 break;
2355
2356 case LOCK_PREFIX_OPCODE:
2357 q = LOCK_PREFIX;
2358 ret = PREFIX_LOCK;
2359 break;
2360
2361 case FWAIT_OPCODE:
2362 q = WAIT_PREFIX;
2363 break;
2364
2365 case ADDR_PREFIX_OPCODE:
2366 q = ADDR_PREFIX;
2367 break;
2368
2369 case DATA_PREFIX_OPCODE:
2370 q = DATA_PREFIX;
2371 break;
2372 }
2373 if (i.prefix[q] != 0)
2374 ret = PREFIX_EXIST;
2375 }
2376
2377 if (ret)
2378 {
2379 if (!i.prefix[q])
2380 ++i.prefixes;
2381 i.prefix[q] |= prefix;
2382 }
2383 else
2384 as_bad (_("same type of prefix used twice"));
2385
2386 return ret;
2387 }
2388
2389 static void
2390 update_code_flag (int value, int check)
2391 {
2392 PRINTF_LIKE ((*as_error));
2393
2394 flag_code = (enum flag_code) value;
2395 if (flag_code == CODE_64BIT)
2396 {
2397 cpu_arch_flags.bitfield.cpu64 = 1;
2398 cpu_arch_flags.bitfield.cpuno64 = 0;
2399 }
2400 else
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 0;
2403 cpu_arch_flags.bitfield.cpuno64 = 1;
2404 }
2405 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2406 {
2407 if (check)
2408 as_error = as_fatal;
2409 else
2410 as_error = as_bad;
2411 (*as_error) (_("64bit mode not supported on `%s'."),
2412 cpu_arch_name ? cpu_arch_name : default_arch);
2413 }
2414 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2415 {
2416 if (check)
2417 as_error = as_fatal;
2418 else
2419 as_error = as_bad;
2420 (*as_error) (_("32bit mode not supported on `%s'."),
2421 cpu_arch_name ? cpu_arch_name : default_arch);
2422 }
2423 stackop_size = '\0';
2424 }
2425
2426 static void
2427 set_code_flag (int value)
2428 {
2429 update_code_flag (value, 0);
2430 }
2431
2432 static void
2433 set_16bit_gcc_code_flag (int new_code_flag)
2434 {
2435 flag_code = (enum flag_code) new_code_flag;
2436 if (flag_code != CODE_16BIT)
2437 abort ();
2438 cpu_arch_flags.bitfield.cpu64 = 0;
2439 cpu_arch_flags.bitfield.cpuno64 = 1;
2440 stackop_size = LONG_MNEM_SUFFIX;
2441 }
2442
2443 static void
2444 set_intel_syntax (int syntax_flag)
2445 {
2446 /* Find out if register prefixing is specified. */
2447 int ask_naked_reg = 0;
2448
2449 SKIP_WHITESPACE ();
2450 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2451 {
2452 char *string;
2453 int e = get_symbol_name (&string);
2454
2455 if (strcmp (string, "prefix") == 0)
2456 ask_naked_reg = 1;
2457 else if (strcmp (string, "noprefix") == 0)
2458 ask_naked_reg = -1;
2459 else
2460 as_bad (_("bad argument to syntax directive."));
2461 (void) restore_line_pointer (e);
2462 }
2463 demand_empty_rest_of_line ();
2464
2465 intel_syntax = syntax_flag;
2466
2467 if (ask_naked_reg == 0)
2468 allow_naked_reg = (intel_syntax
2469 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2470 else
2471 allow_naked_reg = (ask_naked_reg < 0);
2472
2473 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2474
2475 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2476 identifier_chars['$'] = intel_syntax ? '$' : 0;
2477 register_prefix = allow_naked_reg ? "" : "%";
2478 }
2479
2480 static void
2481 set_intel_mnemonic (int mnemonic_flag)
2482 {
2483 intel_mnemonic = mnemonic_flag;
2484 }
2485
2486 static void
2487 set_allow_index_reg (int flag)
2488 {
2489 allow_index_reg = flag;
2490 }
2491
2492 static void
2493 set_check (int what)
2494 {
2495 enum check_kind *kind;
2496 const char *str;
2497
2498 if (what)
2499 {
2500 kind = &operand_check;
2501 str = "operand";
2502 }
2503 else
2504 {
2505 kind = &sse_check;
2506 str = "sse";
2507 }
2508
2509 SKIP_WHITESPACE ();
2510
2511 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2512 {
2513 char *string;
2514 int e = get_symbol_name (&string);
2515
2516 if (strcmp (string, "none") == 0)
2517 *kind = check_none;
2518 else if (strcmp (string, "warning") == 0)
2519 *kind = check_warning;
2520 else if (strcmp (string, "error") == 0)
2521 *kind = check_error;
2522 else
2523 as_bad (_("bad argument to %s_check directive."), str);
2524 (void) restore_line_pointer (e);
2525 }
2526 else
2527 as_bad (_("missing argument for %s_check directive"), str);
2528
2529 demand_empty_rest_of_line ();
2530 }
2531
2532 static void
2533 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2534 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2535 {
2536 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2537 static const char *arch;
2538
2539 /* Intel LIOM is only supported on ELF. */
2540 if (!IS_ELF)
2541 return;
2542
2543 if (!arch)
2544 {
2545 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2546 use default_arch. */
2547 arch = cpu_arch_name;
2548 if (!arch)
2549 arch = default_arch;
2550 }
2551
2552 /* If we are targeting Intel MCU, we must enable it. */
2553 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2554 || new_flag.bitfield.cpuiamcu)
2555 return;
2556
2557 /* If we are targeting Intel L1OM, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2559 || new_flag.bitfield.cpul1om)
2560 return;
2561
2562 /* If we are targeting Intel K1OM, we must enable it. */
2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2564 || new_flag.bitfield.cpuk1om)
2565 return;
2566
2567 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2568 #endif
2569 }
2570
2571 static void
2572 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2573 {
2574 SKIP_WHITESPACE ();
2575
2576 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2577 {
2578 char *string;
2579 int e = get_symbol_name (&string);
2580 unsigned int j;
2581 i386_cpu_flags flags;
2582
2583 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2584 {
2585 if (strcmp (string, cpu_arch[j].name) == 0)
2586 {
2587 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2588
2589 if (*string != '.')
2590 {
2591 cpu_arch_name = cpu_arch[j].name;
2592 cpu_sub_arch_name = NULL;
2593 cpu_arch_flags = cpu_arch[j].flags;
2594 if (flag_code == CODE_64BIT)
2595 {
2596 cpu_arch_flags.bitfield.cpu64 = 1;
2597 cpu_arch_flags.bitfield.cpuno64 = 0;
2598 }
2599 else
2600 {
2601 cpu_arch_flags.bitfield.cpu64 = 0;
2602 cpu_arch_flags.bitfield.cpuno64 = 1;
2603 }
2604 cpu_arch_isa = cpu_arch[j].type;
2605 cpu_arch_isa_flags = cpu_arch[j].flags;
2606 if (!cpu_arch_tune_set)
2607 {
2608 cpu_arch_tune = cpu_arch_isa;
2609 cpu_arch_tune_flags = cpu_arch_isa_flags;
2610 }
2611 break;
2612 }
2613
2614 flags = cpu_flags_or (cpu_arch_flags,
2615 cpu_arch[j].flags);
2616
2617 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2618 {
2619 if (cpu_sub_arch_name)
2620 {
2621 char *name = cpu_sub_arch_name;
2622 cpu_sub_arch_name = concat (name,
2623 cpu_arch[j].name,
2624 (const char *) NULL);
2625 free (name);
2626 }
2627 else
2628 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2629 cpu_arch_flags = flags;
2630 cpu_arch_isa_flags = flags;
2631 }
2632 (void) restore_line_pointer (e);
2633 demand_empty_rest_of_line ();
2634 return;
2635 }
2636 }
2637
2638 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2639 {
2640 /* Disable an ISA extension. */
2641 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2642 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2643 {
2644 flags = cpu_flags_and_not (cpu_arch_flags,
2645 cpu_noarch[j].flags);
2646 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2647 {
2648 if (cpu_sub_arch_name)
2649 {
2650 char *name = cpu_sub_arch_name;
2651 cpu_sub_arch_name = concat (name, string,
2652 (const char *) NULL);
2653 free (name);
2654 }
2655 else
2656 cpu_sub_arch_name = xstrdup (string);
2657 cpu_arch_flags = flags;
2658 cpu_arch_isa_flags = flags;
2659 }
2660 (void) restore_line_pointer (e);
2661 demand_empty_rest_of_line ();
2662 return;
2663 }
2664
2665 j = ARRAY_SIZE (cpu_arch);
2666 }
2667
2668 if (j >= ARRAY_SIZE (cpu_arch))
2669 as_bad (_("no such architecture: `%s'"), string);
2670
2671 *input_line_pointer = e;
2672 }
2673 else
2674 as_bad (_("missing cpu architecture"));
2675
2676 no_cond_jump_promotion = 0;
2677 if (*input_line_pointer == ','
2678 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2679 {
2680 char *string;
2681 char e;
2682
2683 ++input_line_pointer;
2684 e = get_symbol_name (&string);
2685
2686 if (strcmp (string, "nojumps") == 0)
2687 no_cond_jump_promotion = 1;
2688 else if (strcmp (string, "jumps") == 0)
2689 ;
2690 else
2691 as_bad (_("no such architecture modifier: `%s'"), string);
2692
2693 (void) restore_line_pointer (e);
2694 }
2695
2696 demand_empty_rest_of_line ();
2697 }
2698
2699 enum bfd_architecture
2700 i386_arch (void)
2701 {
2702 if (cpu_arch_isa == PROCESSOR_L1OM)
2703 {
2704 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2705 || flag_code != CODE_64BIT)
2706 as_fatal (_("Intel L1OM is 64bit ELF only"));
2707 return bfd_arch_l1om;
2708 }
2709 else if (cpu_arch_isa == PROCESSOR_K1OM)
2710 {
2711 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2712 || flag_code != CODE_64BIT)
2713 as_fatal (_("Intel K1OM is 64bit ELF only"));
2714 return bfd_arch_k1om;
2715 }
2716 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2717 {
2718 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2719 || flag_code == CODE_64BIT)
2720 as_fatal (_("Intel MCU is 32bit ELF only"));
2721 return bfd_arch_iamcu;
2722 }
2723 else
2724 return bfd_arch_i386;
2725 }
2726
2727 unsigned long
2728 i386_mach (void)
2729 {
2730 if (!strncmp (default_arch, "x86_64", 6))
2731 {
2732 if (cpu_arch_isa == PROCESSOR_L1OM)
2733 {
2734 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2735 || default_arch[6] != '\0')
2736 as_fatal (_("Intel L1OM is 64bit ELF only"));
2737 return bfd_mach_l1om;
2738 }
2739 else if (cpu_arch_isa == PROCESSOR_K1OM)
2740 {
2741 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2742 || default_arch[6] != '\0')
2743 as_fatal (_("Intel K1OM is 64bit ELF only"));
2744 return bfd_mach_k1om;
2745 }
2746 else if (default_arch[6] == '\0')
2747 return bfd_mach_x86_64;
2748 else
2749 return bfd_mach_x64_32;
2750 }
2751 else if (!strcmp (default_arch, "i386")
2752 || !strcmp (default_arch, "iamcu"))
2753 {
2754 if (cpu_arch_isa == PROCESSOR_IAMCU)
2755 {
2756 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2757 as_fatal (_("Intel MCU is 32bit ELF only"));
2758 return bfd_mach_i386_iamcu;
2759 }
2760 else
2761 return bfd_mach_i386_i386;
2762 }
2763 else
2764 as_fatal (_("unknown architecture"));
2765 }
2766 \f
2767 void
2768 md_begin (void)
2769 {
2770 const char *hash_err;
2771
2772 /* Support pseudo prefixes like {disp32}. */
2773 lex_type ['{'] = LEX_BEGIN_NAME;
2774
2775 /* Initialize op_hash hash table. */
2776 op_hash = hash_new ();
2777
2778 {
2779 const insn_template *optab;
2780 templates *core_optab;
2781
2782 /* Setup for loop. */
2783 optab = i386_optab;
2784 core_optab = XNEW (templates);
2785 core_optab->start = optab;
2786
2787 while (1)
2788 {
2789 ++optab;
2790 if (optab->name == NULL
2791 || strcmp (optab->name, (optab - 1)->name) != 0)
2792 {
2793 /* different name --> ship out current template list;
2794 add to hash table; & begin anew. */
2795 core_optab->end = optab;
2796 hash_err = hash_insert (op_hash,
2797 (optab - 1)->name,
2798 (void *) core_optab);
2799 if (hash_err)
2800 {
2801 as_fatal (_("can't hash %s: %s"),
2802 (optab - 1)->name,
2803 hash_err);
2804 }
2805 if (optab->name == NULL)
2806 break;
2807 core_optab = XNEW (templates);
2808 core_optab->start = optab;
2809 }
2810 }
2811 }
2812
2813 /* Initialize reg_hash hash table. */
2814 reg_hash = hash_new ();
2815 {
2816 const reg_entry *regtab;
2817 unsigned int regtab_size = i386_regtab_size;
2818
2819 for (regtab = i386_regtab; regtab_size--; regtab++)
2820 {
2821 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2822 if (hash_err)
2823 as_fatal (_("can't hash %s: %s"),
2824 regtab->reg_name,
2825 hash_err);
2826 }
2827 }
2828
2829 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2830 {
2831 int c;
2832 char *p;
2833
2834 for (c = 0; c < 256; c++)
2835 {
2836 if (ISDIGIT (c))
2837 {
2838 digit_chars[c] = c;
2839 mnemonic_chars[c] = c;
2840 register_chars[c] = c;
2841 operand_chars[c] = c;
2842 }
2843 else if (ISLOWER (c))
2844 {
2845 mnemonic_chars[c] = c;
2846 register_chars[c] = c;
2847 operand_chars[c] = c;
2848 }
2849 else if (ISUPPER (c))
2850 {
2851 mnemonic_chars[c] = TOLOWER (c);
2852 register_chars[c] = mnemonic_chars[c];
2853 operand_chars[c] = c;
2854 }
2855 else if (c == '{' || c == '}')
2856 {
2857 mnemonic_chars[c] = c;
2858 operand_chars[c] = c;
2859 }
2860
2861 if (ISALPHA (c) || ISDIGIT (c))
2862 identifier_chars[c] = c;
2863 else if (c >= 128)
2864 {
2865 identifier_chars[c] = c;
2866 operand_chars[c] = c;
2867 }
2868 }
2869
2870 #ifdef LEX_AT
2871 identifier_chars['@'] = '@';
2872 #endif
2873 #ifdef LEX_QM
2874 identifier_chars['?'] = '?';
2875 operand_chars['?'] = '?';
2876 #endif
2877 digit_chars['-'] = '-';
2878 mnemonic_chars['_'] = '_';
2879 mnemonic_chars['-'] = '-';
2880 mnemonic_chars['.'] = '.';
2881 identifier_chars['_'] = '_';
2882 identifier_chars['.'] = '.';
2883
2884 for (p = operand_special_chars; *p != '\0'; p++)
2885 operand_chars[(unsigned char) *p] = *p;
2886 }
2887
2888 if (flag_code == CODE_64BIT)
2889 {
2890 #if defined (OBJ_COFF) && defined (TE_PE)
2891 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2892 ? 32 : 16);
2893 #else
2894 x86_dwarf2_return_column = 16;
2895 #endif
2896 x86_cie_data_alignment = -8;
2897 }
2898 else
2899 {
2900 x86_dwarf2_return_column = 8;
2901 x86_cie_data_alignment = -4;
2902 }
2903 }
2904
2905 void
2906 i386_print_statistics (FILE *file)
2907 {
2908 hash_print_statistics (file, "i386 opcode", op_hash);
2909 hash_print_statistics (file, "i386 register", reg_hash);
2910 }
2911 \f
2912 #ifdef DEBUG386
2913
2914 /* Debugging routines for md_assemble. */
2915 static void pte (insn_template *);
2916 static void pt (i386_operand_type);
2917 static void pe (expressionS *);
2918 static void ps (symbolS *);
2919
2920 static void
2921 pi (char *line, i386_insn *x)
2922 {
2923 unsigned int j;
2924
2925 fprintf (stdout, "%s: template ", line);
2926 pte (&x->tm);
2927 fprintf (stdout, " address: base %s index %s scale %x\n",
2928 x->base_reg ? x->base_reg->reg_name : "none",
2929 x->index_reg ? x->index_reg->reg_name : "none",
2930 x->log2_scale_factor);
2931 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2932 x->rm.mode, x->rm.reg, x->rm.regmem);
2933 fprintf (stdout, " sib: base %x index %x scale %x\n",
2934 x->sib.base, x->sib.index, x->sib.scale);
2935 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2936 (x->rex & REX_W) != 0,
2937 (x->rex & REX_R) != 0,
2938 (x->rex & REX_X) != 0,
2939 (x->rex & REX_B) != 0);
2940 for (j = 0; j < x->operands; j++)
2941 {
2942 fprintf (stdout, " #%d: ", j + 1);
2943 pt (x->types[j]);
2944 fprintf (stdout, "\n");
2945 if (x->types[j].bitfield.reg
2946 || x->types[j].bitfield.regmmx
2947 || x->types[j].bitfield.regsimd
2948 || x->types[j].bitfield.sreg2
2949 || x->types[j].bitfield.sreg3
2950 || x->types[j].bitfield.control
2951 || x->types[j].bitfield.debug
2952 || x->types[j].bitfield.test)
2953 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2954 if (operand_type_check (x->types[j], imm))
2955 pe (x->op[j].imms);
2956 if (operand_type_check (x->types[j], disp))
2957 pe (x->op[j].disps);
2958 }
2959 }
2960
2961 static void
2962 pte (insn_template *t)
2963 {
2964 unsigned int j;
2965 fprintf (stdout, " %d operands ", t->operands);
2966 fprintf (stdout, "opcode %x ", t->base_opcode);
2967 if (t->extension_opcode != None)
2968 fprintf (stdout, "ext %x ", t->extension_opcode);
2969 if (t->opcode_modifier.d)
2970 fprintf (stdout, "D");
2971 if (t->opcode_modifier.w)
2972 fprintf (stdout, "W");
2973 fprintf (stdout, "\n");
2974 for (j = 0; j < t->operands; j++)
2975 {
2976 fprintf (stdout, " #%d type ", j + 1);
2977 pt (t->operand_types[j]);
2978 fprintf (stdout, "\n");
2979 }
2980 }
2981
2982 static void
2983 pe (expressionS *e)
2984 {
2985 fprintf (stdout, " operation %d\n", e->X_op);
2986 fprintf (stdout, " add_number %ld (%lx)\n",
2987 (long) e->X_add_number, (long) e->X_add_number);
2988 if (e->X_add_symbol)
2989 {
2990 fprintf (stdout, " add_symbol ");
2991 ps (e->X_add_symbol);
2992 fprintf (stdout, "\n");
2993 }
2994 if (e->X_op_symbol)
2995 {
2996 fprintf (stdout, " op_symbol ");
2997 ps (e->X_op_symbol);
2998 fprintf (stdout, "\n");
2999 }
3000 }
3001
3002 static void
3003 ps (symbolS *s)
3004 {
3005 fprintf (stdout, "%s type %s%s",
3006 S_GET_NAME (s),
3007 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3008 segment_name (S_GET_SEGMENT (s)));
3009 }
3010
3011 static struct type_name
3012 {
3013 i386_operand_type mask;
3014 const char *name;
3015 }
3016 const type_names[] =
3017 {
3018 { OPERAND_TYPE_REG8, "r8" },
3019 { OPERAND_TYPE_REG16, "r16" },
3020 { OPERAND_TYPE_REG32, "r32" },
3021 { OPERAND_TYPE_REG64, "r64" },
3022 { OPERAND_TYPE_IMM8, "i8" },
3023 { OPERAND_TYPE_IMM8, "i8s" },
3024 { OPERAND_TYPE_IMM16, "i16" },
3025 { OPERAND_TYPE_IMM32, "i32" },
3026 { OPERAND_TYPE_IMM32S, "i32s" },
3027 { OPERAND_TYPE_IMM64, "i64" },
3028 { OPERAND_TYPE_IMM1, "i1" },
3029 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3030 { OPERAND_TYPE_DISP8, "d8" },
3031 { OPERAND_TYPE_DISP16, "d16" },
3032 { OPERAND_TYPE_DISP32, "d32" },
3033 { OPERAND_TYPE_DISP32S, "d32s" },
3034 { OPERAND_TYPE_DISP64, "d64" },
3035 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3036 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3037 { OPERAND_TYPE_CONTROL, "control reg" },
3038 { OPERAND_TYPE_TEST, "test reg" },
3039 { OPERAND_TYPE_DEBUG, "debug reg" },
3040 { OPERAND_TYPE_FLOATREG, "FReg" },
3041 { OPERAND_TYPE_FLOATACC, "FAcc" },
3042 { OPERAND_TYPE_SREG2, "SReg2" },
3043 { OPERAND_TYPE_SREG3, "SReg3" },
3044 { OPERAND_TYPE_ACC, "Acc" },
3045 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3046 { OPERAND_TYPE_REGMMX, "rMMX" },
3047 { OPERAND_TYPE_REGXMM, "rXMM" },
3048 { OPERAND_TYPE_REGYMM, "rYMM" },
3049 { OPERAND_TYPE_REGZMM, "rZMM" },
3050 { OPERAND_TYPE_REGMASK, "Mask reg" },
3051 { OPERAND_TYPE_ESSEG, "es" },
3052 };
3053
3054 static void
3055 pt (i386_operand_type t)
3056 {
3057 unsigned int j;
3058 i386_operand_type a;
3059
3060 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3061 {
3062 a = operand_type_and (t, type_names[j].mask);
3063 if (!operand_type_all_zero (&a))
3064 fprintf (stdout, "%s, ", type_names[j].name);
3065 }
3066 fflush (stdout);
3067 }
3068
3069 #endif /* DEBUG386 */
3070 \f
3071 static bfd_reloc_code_real_type
3072 reloc (unsigned int size,
3073 int pcrel,
3074 int sign,
3075 bfd_reloc_code_real_type other)
3076 {
3077 if (other != NO_RELOC)
3078 {
3079 reloc_howto_type *rel;
3080
3081 if (size == 8)
3082 switch (other)
3083 {
3084 case BFD_RELOC_X86_64_GOT32:
3085 return BFD_RELOC_X86_64_GOT64;
3086 break;
3087 case BFD_RELOC_X86_64_GOTPLT64:
3088 return BFD_RELOC_X86_64_GOTPLT64;
3089 break;
3090 case BFD_RELOC_X86_64_PLTOFF64:
3091 return BFD_RELOC_X86_64_PLTOFF64;
3092 break;
3093 case BFD_RELOC_X86_64_GOTPC32:
3094 other = BFD_RELOC_X86_64_GOTPC64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPCREL:
3097 other = BFD_RELOC_X86_64_GOTPCREL64;
3098 break;
3099 case BFD_RELOC_X86_64_TPOFF32:
3100 other = BFD_RELOC_X86_64_TPOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_DTPOFF32:
3103 other = BFD_RELOC_X86_64_DTPOFF64;
3104 break;
3105 default:
3106 break;
3107 }
3108
3109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3110 if (other == BFD_RELOC_SIZE32)
3111 {
3112 if (size == 8)
3113 other = BFD_RELOC_SIZE64;
3114 if (pcrel)
3115 {
3116 as_bad (_("there are no pc-relative size relocations"));
3117 return NO_RELOC;
3118 }
3119 }
3120 #endif
3121
3122 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3123 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3124 sign = -1;
3125
3126 rel = bfd_reloc_type_lookup (stdoutput, other);
3127 if (!rel)
3128 as_bad (_("unknown relocation (%u)"), other);
3129 else if (size != bfd_get_reloc_size (rel))
3130 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3131 bfd_get_reloc_size (rel),
3132 size);
3133 else if (pcrel && !rel->pc_relative)
3134 as_bad (_("non-pc-relative relocation for pc-relative field"));
3135 else if ((rel->complain_on_overflow == complain_overflow_signed
3136 && !sign)
3137 || (rel->complain_on_overflow == complain_overflow_unsigned
3138 && sign > 0))
3139 as_bad (_("relocated field and relocation type differ in signedness"));
3140 else
3141 return other;
3142 return NO_RELOC;
3143 }
3144
3145 if (pcrel)
3146 {
3147 if (!sign)
3148 as_bad (_("there are no unsigned pc-relative relocations"));
3149 switch (size)
3150 {
3151 case 1: return BFD_RELOC_8_PCREL;
3152 case 2: return BFD_RELOC_16_PCREL;
3153 case 4: return BFD_RELOC_32_PCREL;
3154 case 8: return BFD_RELOC_64_PCREL;
3155 }
3156 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3157 }
3158 else
3159 {
3160 if (sign > 0)
3161 switch (size)
3162 {
3163 case 4: return BFD_RELOC_X86_64_32S;
3164 }
3165 else
3166 switch (size)
3167 {
3168 case 1: return BFD_RELOC_8;
3169 case 2: return BFD_RELOC_16;
3170 case 4: return BFD_RELOC_32;
3171 case 8: return BFD_RELOC_64;
3172 }
3173 as_bad (_("cannot do %s %u byte relocation"),
3174 sign > 0 ? "signed" : "unsigned", size);
3175 }
3176
3177 return NO_RELOC;
3178 }
3179
3180 /* Here we decide which fixups can be adjusted to make them relative to
3181 the beginning of the section instead of the symbol. Basically we need
3182 to make sure that the dynamic relocations are done correctly, so in
3183 some cases we force the original symbol to be used. */
3184
3185 int
3186 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3187 {
3188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3189 if (!IS_ELF)
3190 return 1;
3191
3192 /* Don't adjust pc-relative references to merge sections in 64-bit
3193 mode. */
3194 if (use_rela_relocations
3195 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3196 && fixP->fx_pcrel)
3197 return 0;
3198
3199 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3200 and changed later by validate_fix. */
3201 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3202 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3203 return 0;
3204
3205 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3206 for size relocations. */
3207 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3208 || fixP->fx_r_type == BFD_RELOC_SIZE64
3209 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3210 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3211 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3212 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3213 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3214 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3215 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3223 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3224 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3225 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3226 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3228 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3229 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3231 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3234 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3240 return 0;
3241 #endif
3242 return 1;
3243 }
3244
3245 static int
3246 intel_float_operand (const char *mnemonic)
3247 {
3248 /* Note that the value returned is meaningful only for opcodes with (memory)
3249 operands, hence the code here is free to improperly handle opcodes that
3250 have no operands (for better performance and smaller code). */
3251
3252 if (mnemonic[0] != 'f')
3253 return 0; /* non-math */
3254
3255 switch (mnemonic[1])
3256 {
3257 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3258 the fs segment override prefix not currently handled because no
3259 call path can make opcodes without operands get here */
3260 case 'i':
3261 return 2 /* integer op */;
3262 case 'l':
3263 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3264 return 3; /* fldcw/fldenv */
3265 break;
3266 case 'n':
3267 if (mnemonic[2] != 'o' /* fnop */)
3268 return 3; /* non-waiting control op */
3269 break;
3270 case 'r':
3271 if (mnemonic[2] == 's')
3272 return 3; /* frstor/frstpm */
3273 break;
3274 case 's':
3275 if (mnemonic[2] == 'a')
3276 return 3; /* fsave */
3277 if (mnemonic[2] == 't')
3278 {
3279 switch (mnemonic[3])
3280 {
3281 case 'c': /* fstcw */
3282 case 'd': /* fstdw */
3283 case 'e': /* fstenv */
3284 case 's': /* fsts[gw] */
3285 return 3;
3286 }
3287 }
3288 break;
3289 case 'x':
3290 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3291 return 0; /* fxsave/fxrstor are not really math ops */
3292 break;
3293 }
3294
3295 return 1;
3296 }
3297
3298 /* Build the VEX prefix. */
3299
3300 static void
3301 build_vex_prefix (const insn_template *t)
3302 {
3303 unsigned int register_specifier;
3304 unsigned int implied_prefix;
3305 unsigned int vector_length;
3306
3307 /* Check register specifier. */
3308 if (i.vex.register_specifier)
3309 {
3310 register_specifier =
3311 ~register_number (i.vex.register_specifier) & 0xf;
3312 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3313 }
3314 else
3315 register_specifier = 0xf;
3316
3317 /* Use 2-byte VEX prefix by swapping destination and source
3318 operand. */
3319 if (i.vec_encoding != vex_encoding_vex3
3320 && i.dir_encoding == dir_encoding_default
3321 && i.operands == i.reg_operands
3322 && i.tm.opcode_modifier.vexopcode == VEX0F
3323 && i.tm.opcode_modifier.load
3324 && i.rex == REX_B)
3325 {
3326 unsigned int xchg = i.operands - 1;
3327 union i386_op temp_op;
3328 i386_operand_type temp_type;
3329
3330 temp_type = i.types[xchg];
3331 i.types[xchg] = i.types[0];
3332 i.types[0] = temp_type;
3333 temp_op = i.op[xchg];
3334 i.op[xchg] = i.op[0];
3335 i.op[0] = temp_op;
3336
3337 gas_assert (i.rm.mode == 3);
3338
3339 i.rex = REX_R;
3340 xchg = i.rm.regmem;
3341 i.rm.regmem = i.rm.reg;
3342 i.rm.reg = xchg;
3343
3344 /* Use the next insn. */
3345 i.tm = t[1];
3346 }
3347
3348 if (i.tm.opcode_modifier.vex == VEXScalar)
3349 vector_length = avxscalar;
3350 else if (i.tm.opcode_modifier.vex == VEX256)
3351 vector_length = 1;
3352 else
3353 {
3354 unsigned int op;
3355
3356 vector_length = 0;
3357 for (op = 0; op < t->operands; ++op)
3358 if (t->operand_types[op].bitfield.xmmword
3359 && t->operand_types[op].bitfield.ymmword
3360 && i.types[op].bitfield.ymmword)
3361 {
3362 vector_length = 1;
3363 break;
3364 }
3365 }
3366
3367 switch ((i.tm.base_opcode >> 8) & 0xff)
3368 {
3369 case 0:
3370 implied_prefix = 0;
3371 break;
3372 case DATA_PREFIX_OPCODE:
3373 implied_prefix = 1;
3374 break;
3375 case REPE_PREFIX_OPCODE:
3376 implied_prefix = 2;
3377 break;
3378 case REPNE_PREFIX_OPCODE:
3379 implied_prefix = 3;
3380 break;
3381 default:
3382 abort ();
3383 }
3384
3385 /* Use 2-byte VEX prefix if possible. */
3386 if (i.vec_encoding != vex_encoding_vex3
3387 && i.tm.opcode_modifier.vexopcode == VEX0F
3388 && i.tm.opcode_modifier.vexw != VEXW1
3389 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3390 {
3391 /* 2-byte VEX prefix. */
3392 unsigned int r;
3393
3394 i.vex.length = 2;
3395 i.vex.bytes[0] = 0xc5;
3396
3397 /* Check the REX.R bit. */
3398 r = (i.rex & REX_R) ? 0 : 1;
3399 i.vex.bytes[1] = (r << 7
3400 | register_specifier << 3
3401 | vector_length << 2
3402 | implied_prefix);
3403 }
3404 else
3405 {
3406 /* 3-byte VEX prefix. */
3407 unsigned int m, w;
3408
3409 i.vex.length = 3;
3410
3411 switch (i.tm.opcode_modifier.vexopcode)
3412 {
3413 case VEX0F:
3414 m = 0x1;
3415 i.vex.bytes[0] = 0xc4;
3416 break;
3417 case VEX0F38:
3418 m = 0x2;
3419 i.vex.bytes[0] = 0xc4;
3420 break;
3421 case VEX0F3A:
3422 m = 0x3;
3423 i.vex.bytes[0] = 0xc4;
3424 break;
3425 case XOP08:
3426 m = 0x8;
3427 i.vex.bytes[0] = 0x8f;
3428 break;
3429 case XOP09:
3430 m = 0x9;
3431 i.vex.bytes[0] = 0x8f;
3432 break;
3433 case XOP0A:
3434 m = 0xa;
3435 i.vex.bytes[0] = 0x8f;
3436 break;
3437 default:
3438 abort ();
3439 }
3440
3441 /* The high 3 bits of the second VEX byte are 1's compliment
3442 of RXB bits from REX. */
3443 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3444
3445 /* Check the REX.W bit. */
3446 w = (i.rex & REX_W) ? 1 : 0;
3447 if (i.tm.opcode_modifier.vexw == VEXW1)
3448 w = 1;
3449
3450 i.vex.bytes[2] = (w << 7
3451 | register_specifier << 3
3452 | vector_length << 2
3453 | implied_prefix);
3454 }
3455 }
3456
3457 /* Build the EVEX prefix. */
3458
3459 static void
3460 build_evex_prefix (void)
3461 {
3462 unsigned int register_specifier;
3463 unsigned int implied_prefix;
3464 unsigned int m, w;
3465 rex_byte vrex_used = 0;
3466
3467 /* Check register specifier. */
3468 if (i.vex.register_specifier)
3469 {
3470 gas_assert ((i.vrex & REX_X) == 0);
3471
3472 register_specifier = i.vex.register_specifier->reg_num;
3473 if ((i.vex.register_specifier->reg_flags & RegRex))
3474 register_specifier += 8;
3475 /* The upper 16 registers are encoded in the fourth byte of the
3476 EVEX prefix. */
3477 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3478 i.vex.bytes[3] = 0x8;
3479 register_specifier = ~register_specifier & 0xf;
3480 }
3481 else
3482 {
3483 register_specifier = 0xf;
3484
3485 /* Encode upper 16 vector index register in the fourth byte of
3486 the EVEX prefix. */
3487 if (!(i.vrex & REX_X))
3488 i.vex.bytes[3] = 0x8;
3489 else
3490 vrex_used |= REX_X;
3491 }
3492
3493 switch ((i.tm.base_opcode >> 8) & 0xff)
3494 {
3495 case 0:
3496 implied_prefix = 0;
3497 break;
3498 case DATA_PREFIX_OPCODE:
3499 implied_prefix = 1;
3500 break;
3501 case REPE_PREFIX_OPCODE:
3502 implied_prefix = 2;
3503 break;
3504 case REPNE_PREFIX_OPCODE:
3505 implied_prefix = 3;
3506 break;
3507 default:
3508 abort ();
3509 }
3510
3511 /* 4 byte EVEX prefix. */
3512 i.vex.length = 4;
3513 i.vex.bytes[0] = 0x62;
3514
3515 /* mmmm bits. */
3516 switch (i.tm.opcode_modifier.vexopcode)
3517 {
3518 case VEX0F:
3519 m = 1;
3520 break;
3521 case VEX0F38:
3522 m = 2;
3523 break;
3524 case VEX0F3A:
3525 m = 3;
3526 break;
3527 default:
3528 abort ();
3529 break;
3530 }
3531
3532 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3533 bits from REX. */
3534 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3535
3536 /* The fifth bit of the second EVEX byte is 1's compliment of the
3537 REX_R bit in VREX. */
3538 if (!(i.vrex & REX_R))
3539 i.vex.bytes[1] |= 0x10;
3540 else
3541 vrex_used |= REX_R;
3542
3543 if ((i.reg_operands + i.imm_operands) == i.operands)
3544 {
3545 /* When all operands are registers, the REX_X bit in REX is not
3546 used. We reuse it to encode the upper 16 registers, which is
3547 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3548 as 1's compliment. */
3549 if ((i.vrex & REX_B))
3550 {
3551 vrex_used |= REX_B;
3552 i.vex.bytes[1] &= ~0x40;
3553 }
3554 }
3555
3556 /* EVEX instructions shouldn't need the REX prefix. */
3557 i.vrex &= ~vrex_used;
3558 gas_assert (i.vrex == 0);
3559
3560 /* Check the REX.W bit. */
3561 w = (i.rex & REX_W) ? 1 : 0;
3562 if (i.tm.opcode_modifier.vexw)
3563 {
3564 if (i.tm.opcode_modifier.vexw == VEXW1)
3565 w = 1;
3566 }
3567 /* If w is not set it means we are dealing with WIG instruction. */
3568 else if (!w)
3569 {
3570 if (evexwig == evexw1)
3571 w = 1;
3572 }
3573
3574 /* Encode the U bit. */
3575 implied_prefix |= 0x4;
3576
3577 /* The third byte of the EVEX prefix. */
3578 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3579
3580 /* The fourth byte of the EVEX prefix. */
3581 /* The zeroing-masking bit. */
3582 if (i.mask && i.mask->zeroing)
3583 i.vex.bytes[3] |= 0x80;
3584
3585 /* Don't always set the broadcast bit if there is no RC. */
3586 if (!i.rounding)
3587 {
3588 /* Encode the vector length. */
3589 unsigned int vec_length;
3590
3591 switch (i.tm.opcode_modifier.evex)
3592 {
3593 case EVEXLIG: /* LL' is ignored */
3594 vec_length = evexlig << 5;
3595 break;
3596 case EVEX128:
3597 vec_length = 0 << 5;
3598 break;
3599 case EVEX256:
3600 vec_length = 1 << 5;
3601 break;
3602 case EVEX512:
3603 vec_length = 2 << 5;
3604 break;
3605 default:
3606 abort ();
3607 break;
3608 }
3609 i.vex.bytes[3] |= vec_length;
3610 /* Encode the broadcast bit. */
3611 if (i.broadcast)
3612 i.vex.bytes[3] |= 0x10;
3613 }
3614 else
3615 {
3616 if (i.rounding->type != saeonly)
3617 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3618 else
3619 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3620 }
3621
3622 if (i.mask && i.mask->mask)
3623 i.vex.bytes[3] |= i.mask->mask->reg_num;
3624 }
3625
3626 static void
3627 process_immext (void)
3628 {
3629 expressionS *exp;
3630
3631 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3632 && i.operands > 0)
3633 {
3634 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3635 with an opcode suffix which is coded in the same place as an
3636 8-bit immediate field would be.
3637 Here we check those operands and remove them afterwards. */
3638 unsigned int x;
3639
3640 for (x = 0; x < i.operands; x++)
3641 if (register_number (i.op[x].regs) != x)
3642 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3643 register_prefix, i.op[x].regs->reg_name, x + 1,
3644 i.tm.name);
3645
3646 i.operands = 0;
3647 }
3648
3649 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3650 {
3651 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3652 suffix which is coded in the same place as an 8-bit immediate
3653 field would be.
3654 Here we check those operands and remove them afterwards. */
3655 unsigned int x;
3656
3657 if (i.operands != 3)
3658 abort();
3659
3660 for (x = 0; x < 2; x++)
3661 if (register_number (i.op[x].regs) != x)
3662 goto bad_register_operand;
3663
3664 /* Check for third operand for mwaitx/monitorx insn. */
3665 if (register_number (i.op[x].regs)
3666 != (x + (i.tm.extension_opcode == 0xfb)))
3667 {
3668 bad_register_operand:
3669 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3670 register_prefix, i.op[x].regs->reg_name, x+1,
3671 i.tm.name);
3672 }
3673
3674 i.operands = 0;
3675 }
3676
3677 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3678 which is coded in the same place as an 8-bit immediate field
3679 would be. Here we fake an 8-bit immediate operand from the
3680 opcode suffix stored in tm.extension_opcode.
3681
3682 AVX instructions also use this encoding, for some of
3683 3 argument instructions. */
3684
3685 gas_assert (i.imm_operands <= 1
3686 && (i.operands <= 2
3687 || ((i.tm.opcode_modifier.vex
3688 || i.tm.opcode_modifier.evex)
3689 && i.operands <= 4)));
3690
3691 exp = &im_expressions[i.imm_operands++];
3692 i.op[i.operands].imms = exp;
3693 i.types[i.operands] = imm8;
3694 i.operands++;
3695 exp->X_op = O_constant;
3696 exp->X_add_number = i.tm.extension_opcode;
3697 i.tm.extension_opcode = None;
3698 }
3699
3700
3701 static int
3702 check_hle (void)
3703 {
3704 switch (i.tm.opcode_modifier.hleprefixok)
3705 {
3706 default:
3707 abort ();
3708 case HLEPrefixNone:
3709 as_bad (_("invalid instruction `%s' after `%s'"),
3710 i.tm.name, i.hle_prefix);
3711 return 0;
3712 case HLEPrefixLock:
3713 if (i.prefix[LOCK_PREFIX])
3714 return 1;
3715 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3716 return 0;
3717 case HLEPrefixAny:
3718 return 1;
3719 case HLEPrefixRelease:
3720 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3721 {
3722 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3723 i.tm.name);
3724 return 0;
3725 }
3726 if (i.mem_operands == 0
3727 || !operand_type_check (i.types[i.operands - 1], anymem))
3728 {
3729 as_bad (_("memory destination needed for instruction `%s'"
3730 " after `xrelease'"), i.tm.name);
3731 return 0;
3732 }
3733 return 1;
3734 }
3735 }
3736
3737 /* Try the shortest encoding by shortening operand size. */
3738
3739 static void
3740 optimize_encoding (void)
3741 {
3742 int j;
3743
3744 if (optimize_for_space
3745 && i.reg_operands == 1
3746 && i.imm_operands == 1
3747 && !i.types[1].bitfield.byte
3748 && i.op[0].imms->X_op == O_constant
3749 && fits_in_imm7 (i.op[0].imms->X_add_number)
3750 && ((i.tm.base_opcode == 0xa8
3751 && i.tm.extension_opcode == None)
3752 || (i.tm.base_opcode == 0xf6
3753 && i.tm.extension_opcode == 0x0)))
3754 {
3755 /* Optimize: -Os:
3756 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3757 */
3758 unsigned int base_regnum = i.op[1].regs->reg_num;
3759 if (flag_code == CODE_64BIT || base_regnum < 4)
3760 {
3761 i.types[1].bitfield.byte = 1;
3762 /* Ignore the suffix. */
3763 i.suffix = 0;
3764 if (base_regnum >= 4
3765 && !(i.op[1].regs->reg_flags & RegRex))
3766 {
3767 /* Handle SP, BP, SI and DI registers. */
3768 if (i.types[1].bitfield.word)
3769 j = 16;
3770 else if (i.types[1].bitfield.dword)
3771 j = 32;
3772 else
3773 j = 48;
3774 i.op[1].regs -= j;
3775 }
3776 }
3777 }
3778 else if (flag_code == CODE_64BIT
3779 && ((i.reg_operands == 1
3780 && i.imm_operands == 1
3781 && i.op[0].imms->X_op == O_constant
3782 && ((i.tm.base_opcode == 0xb0
3783 && i.tm.extension_opcode == None
3784 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3785 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3786 && (((i.tm.base_opcode == 0x24
3787 || i.tm.base_opcode == 0xa8)
3788 && i.tm.extension_opcode == None)
3789 || (i.tm.base_opcode == 0x80
3790 && i.tm.extension_opcode == 0x4)
3791 || ((i.tm.base_opcode == 0xf6
3792 || i.tm.base_opcode == 0xc6)
3793 && i.tm.extension_opcode == 0x0)))))
3794 || (i.reg_operands == 2
3795 && i.op[0].regs == i.op[1].regs
3796 && ((i.tm.base_opcode == 0x30
3797 || i.tm.base_opcode == 0x28)
3798 && i.tm.extension_opcode == None)))
3799 && i.types[1].bitfield.qword)
3800 {
3801 /* Optimize: -O:
3802 andq $imm31, %r64 -> andl $imm31, %r32
3803 testq $imm31, %r64 -> testl $imm31, %r32
3804 xorq %r64, %r64 -> xorl %r32, %r32
3805 subq %r64, %r64 -> subl %r32, %r32
3806 movq $imm31, %r64 -> movl $imm31, %r32
3807 movq $imm32, %r64 -> movl $imm32, %r32
3808 */
3809 i.tm.opcode_modifier.norex64 = 1;
3810 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3811 {
3812 /* Handle
3813 movq $imm31, %r64 -> movl $imm31, %r32
3814 movq $imm32, %r64 -> movl $imm32, %r32
3815 */
3816 i.tm.operand_types[0].bitfield.imm32 = 1;
3817 i.tm.operand_types[0].bitfield.imm32s = 0;
3818 i.tm.operand_types[0].bitfield.imm64 = 0;
3819 i.types[0].bitfield.imm32 = 1;
3820 i.types[0].bitfield.imm32s = 0;
3821 i.types[0].bitfield.imm64 = 0;
3822 i.types[1].bitfield.dword = 1;
3823 i.types[1].bitfield.qword = 0;
3824 if (i.tm.base_opcode == 0xc6)
3825 {
3826 /* Handle
3827 movq $imm31, %r64 -> movl $imm31, %r32
3828 */
3829 i.tm.base_opcode = 0xb0;
3830 i.tm.extension_opcode = None;
3831 i.tm.opcode_modifier.shortform = 1;
3832 i.tm.opcode_modifier.modrm = 0;
3833 }
3834 }
3835 }
3836 else if (optimize > 1
3837 && i.reg_operands == 3
3838 && i.op[0].regs == i.op[1].regs
3839 && !i.types[2].bitfield.xmmword
3840 && (i.tm.opcode_modifier.vex
3841 || (!i.mask
3842 && !i.rounding
3843 && i.tm.opcode_modifier.evex
3844 && cpu_arch_flags.bitfield.cpuavx512vl))
3845 && ((i.tm.base_opcode == 0x55
3846 || i.tm.base_opcode == 0x6655
3847 || i.tm.base_opcode == 0x66df
3848 || i.tm.base_opcode == 0x57
3849 || i.tm.base_opcode == 0x6657
3850 || i.tm.base_opcode == 0x66ef
3851 || i.tm.base_opcode == 0x66f8
3852 || i.tm.base_opcode == 0x66f9
3853 || i.tm.base_opcode == 0x66fa
3854 || i.tm.base_opcode == 0x66fb)
3855 && i.tm.extension_opcode == None))
3856 {
3857 /* Optimize: -O2:
3858 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3859 vpsubq and vpsubw:
3860 EVEX VOP %zmmM, %zmmM, %zmmN
3861 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3862 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3863 EVEX VOP %ymmM, %ymmM, %ymmN
3864 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3865 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3866 VEX VOP %ymmM, %ymmM, %ymmN
3867 -> VEX VOP %xmmM, %xmmM, %xmmN
3868 VOP, one of vpandn and vpxor:
3869 VEX VOP %ymmM, %ymmM, %ymmN
3870 -> VEX VOP %xmmM, %xmmM, %xmmN
3871 VOP, one of vpandnd and vpandnq:
3872 EVEX VOP %zmmM, %zmmM, %zmmN
3873 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3874 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3875 EVEX VOP %ymmM, %ymmM, %ymmN
3876 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3877 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3878 VOP, one of vpxord and vpxorq:
3879 EVEX VOP %zmmM, %zmmM, %zmmN
3880 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 EVEX VOP %ymmM, %ymmM, %ymmN
3883 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3884 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3885 */
3886 if (i.tm.opcode_modifier.evex)
3887 {
3888 /* If only lower 16 vector registers are used, we can use
3889 VEX encoding. */
3890 for (j = 0; j < 3; j++)
3891 if (register_number (i.op[j].regs) > 15)
3892 break;
3893
3894 if (j < 3)
3895 i.tm.opcode_modifier.evex = EVEX128;
3896 else
3897 {
3898 i.tm.opcode_modifier.vex = VEX128;
3899 i.tm.opcode_modifier.vexw = VEXW0;
3900 i.tm.opcode_modifier.evex = 0;
3901 }
3902 }
3903 else
3904 i.tm.opcode_modifier.vex = VEX128;
3905
3906 if (i.tm.opcode_modifier.vex)
3907 for (j = 0; j < 3; j++)
3908 {
3909 i.types[j].bitfield.xmmword = 1;
3910 i.types[j].bitfield.ymmword = 0;
3911 }
3912 }
3913 }
3914
3915 /* This is the guts of the machine-dependent assembler. LINE points to a
3916 machine dependent instruction. This function is supposed to emit
3917 the frags/bytes it assembles to. */
3918
3919 void
3920 md_assemble (char *line)
3921 {
3922 unsigned int j;
3923 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3924 const insn_template *t;
3925
3926 /* Initialize globals. */
3927 memset (&i, '\0', sizeof (i));
3928 for (j = 0; j < MAX_OPERANDS; j++)
3929 i.reloc[j] = NO_RELOC;
3930 memset (disp_expressions, '\0', sizeof (disp_expressions));
3931 memset (im_expressions, '\0', sizeof (im_expressions));
3932 save_stack_p = save_stack;
3933
3934 /* First parse an instruction mnemonic & call i386_operand for the operands.
3935 We assume that the scrubber has arranged it so that line[0] is the valid
3936 start of a (possibly prefixed) mnemonic. */
3937
3938 line = parse_insn (line, mnemonic);
3939 if (line == NULL)
3940 return;
3941 mnem_suffix = i.suffix;
3942
3943 line = parse_operands (line, mnemonic);
3944 this_operand = -1;
3945 xfree (i.memop1_string);
3946 i.memop1_string = NULL;
3947 if (line == NULL)
3948 return;
3949
3950 /* Now we've parsed the mnemonic into a set of templates, and have the
3951 operands at hand. */
3952
3953 /* All intel opcodes have reversed operands except for "bound" and
3954 "enter". We also don't reverse intersegment "jmp" and "call"
3955 instructions with 2 immediate operands so that the immediate segment
3956 precedes the offset, as it does when in AT&T mode. */
3957 if (intel_syntax
3958 && i.operands > 1
3959 && (strcmp (mnemonic, "bound") != 0)
3960 && (strcmp (mnemonic, "invlpga") != 0)
3961 && !(operand_type_check (i.types[0], imm)
3962 && operand_type_check (i.types[1], imm)))
3963 swap_operands ();
3964
3965 /* The order of the immediates should be reversed
3966 for 2 immediates extrq and insertq instructions */
3967 if (i.imm_operands == 2
3968 && (strcmp (mnemonic, "extrq") == 0
3969 || strcmp (mnemonic, "insertq") == 0))
3970 swap_2_operands (0, 1);
3971
3972 if (i.imm_operands)
3973 optimize_imm ();
3974
3975 /* Don't optimize displacement for movabs since it only takes 64bit
3976 displacement. */
3977 if (i.disp_operands
3978 && i.disp_encoding != disp_encoding_32bit
3979 && (flag_code != CODE_64BIT
3980 || strcmp (mnemonic, "movabs") != 0))
3981 optimize_disp ();
3982
3983 /* Next, we find a template that matches the given insn,
3984 making sure the overlap of the given operands types is consistent
3985 with the template operand types. */
3986
3987 if (!(t = match_template (mnem_suffix)))
3988 return;
3989
3990 if (sse_check != check_none
3991 && !i.tm.opcode_modifier.noavx
3992 && !i.tm.cpu_flags.bitfield.cpuavx
3993 && (i.tm.cpu_flags.bitfield.cpusse
3994 || i.tm.cpu_flags.bitfield.cpusse2
3995 || i.tm.cpu_flags.bitfield.cpusse3
3996 || i.tm.cpu_flags.bitfield.cpussse3
3997 || i.tm.cpu_flags.bitfield.cpusse4_1
3998 || i.tm.cpu_flags.bitfield.cpusse4_2
3999 || i.tm.cpu_flags.bitfield.cpupclmul
4000 || i.tm.cpu_flags.bitfield.cpuaes
4001 || i.tm.cpu_flags.bitfield.cpugfni))
4002 {
4003 (sse_check == check_warning
4004 ? as_warn
4005 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4006 }
4007
4008 /* Zap movzx and movsx suffix. The suffix has been set from
4009 "word ptr" or "byte ptr" on the source operand in Intel syntax
4010 or extracted from mnemonic in AT&T syntax. But we'll use
4011 the destination register to choose the suffix for encoding. */
4012 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4013 {
4014 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4015 there is no suffix, the default will be byte extension. */
4016 if (i.reg_operands != 2
4017 && !i.suffix
4018 && intel_syntax)
4019 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4020
4021 i.suffix = 0;
4022 }
4023
4024 if (i.tm.opcode_modifier.fwait)
4025 if (!add_prefix (FWAIT_OPCODE))
4026 return;
4027
4028 /* Check if REP prefix is OK. */
4029 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4030 {
4031 as_bad (_("invalid instruction `%s' after `%s'"),
4032 i.tm.name, i.rep_prefix);
4033 return;
4034 }
4035
4036 /* Check for lock without a lockable instruction. Destination operand
4037 must be memory unless it is xchg (0x86). */
4038 if (i.prefix[LOCK_PREFIX]
4039 && (!i.tm.opcode_modifier.islockable
4040 || i.mem_operands == 0
4041 || (i.tm.base_opcode != 0x86
4042 && !operand_type_check (i.types[i.operands - 1], anymem))))
4043 {
4044 as_bad (_("expecting lockable instruction after `lock'"));
4045 return;
4046 }
4047
4048 /* Check if HLE prefix is OK. */
4049 if (i.hle_prefix && !check_hle ())
4050 return;
4051
4052 /* Check BND prefix. */
4053 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4054 as_bad (_("expecting valid branch instruction after `bnd'"));
4055
4056 /* Check NOTRACK prefix. */
4057 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4058 as_bad (_("expecting indirect branch instruction after `notrack'"));
4059
4060 if (i.tm.cpu_flags.bitfield.cpumpx)
4061 {
4062 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4063 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4064 else if (flag_code != CODE_16BIT
4065 ? i.prefix[ADDR_PREFIX]
4066 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4067 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4068 }
4069
4070 /* Insert BND prefix. */
4071 if (add_bnd_prefix
4072 && i.tm.opcode_modifier.bndprefixok
4073 && !i.prefix[BND_PREFIX])
4074 add_prefix (BND_PREFIX_OPCODE);
4075
4076 /* Check string instruction segment overrides. */
4077 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4078 {
4079 if (!check_string ())
4080 return;
4081 i.disp_operands = 0;
4082 }
4083
4084 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4085 optimize_encoding ();
4086
4087 if (!process_suffix ())
4088 return;
4089
4090 /* Update operand types. */
4091 for (j = 0; j < i.operands; j++)
4092 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4093
4094 /* Make still unresolved immediate matches conform to size of immediate
4095 given in i.suffix. */
4096 if (!finalize_imm ())
4097 return;
4098
4099 if (i.types[0].bitfield.imm1)
4100 i.imm_operands = 0; /* kludge for shift insns. */
4101
4102 /* We only need to check those implicit registers for instructions
4103 with 3 operands or less. */
4104 if (i.operands <= 3)
4105 for (j = 0; j < i.operands; j++)
4106 if (i.types[j].bitfield.inoutportreg
4107 || i.types[j].bitfield.shiftcount
4108 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4109 i.reg_operands--;
4110
4111 /* ImmExt should be processed after SSE2AVX. */
4112 if (!i.tm.opcode_modifier.sse2avx
4113 && i.tm.opcode_modifier.immext)
4114 process_immext ();
4115
4116 /* For insns with operands there are more diddles to do to the opcode. */
4117 if (i.operands)
4118 {
4119 if (!process_operands ())
4120 return;
4121 }
4122 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4123 {
4124 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4125 as_warn (_("translating to `%sp'"), i.tm.name);
4126 }
4127
4128 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4129 {
4130 if (flag_code == CODE_16BIT)
4131 {
4132 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4133 i.tm.name);
4134 return;
4135 }
4136
4137 if (i.tm.opcode_modifier.vex)
4138 build_vex_prefix (t);
4139 else
4140 build_evex_prefix ();
4141 }
4142
4143 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4144 instructions may define INT_OPCODE as well, so avoid this corner
4145 case for those instructions that use MODRM. */
4146 if (i.tm.base_opcode == INT_OPCODE
4147 && !i.tm.opcode_modifier.modrm
4148 && i.op[0].imms->X_add_number == 3)
4149 {
4150 i.tm.base_opcode = INT3_OPCODE;
4151 i.imm_operands = 0;
4152 }
4153
4154 if ((i.tm.opcode_modifier.jump
4155 || i.tm.opcode_modifier.jumpbyte
4156 || i.tm.opcode_modifier.jumpdword)
4157 && i.op[0].disps->X_op == O_constant)
4158 {
4159 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4160 the absolute address given by the constant. Since ix86 jumps and
4161 calls are pc relative, we need to generate a reloc. */
4162 i.op[0].disps->X_add_symbol = &abs_symbol;
4163 i.op[0].disps->X_op = O_symbol;
4164 }
4165
4166 if (i.tm.opcode_modifier.rex64)
4167 i.rex |= REX_W;
4168
4169 /* For 8 bit registers we need an empty rex prefix. Also if the
4170 instruction already has a prefix, we need to convert old
4171 registers to new ones. */
4172
4173 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4174 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4175 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4176 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4177 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4178 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4179 && i.rex != 0))
4180 {
4181 int x;
4182
4183 i.rex |= REX_OPCODE;
4184 for (x = 0; x < 2; x++)
4185 {
4186 /* Look for 8 bit operand that uses old registers. */
4187 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4188 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4189 {
4190 /* In case it is "hi" register, give up. */
4191 if (i.op[x].regs->reg_num > 3)
4192 as_bad (_("can't encode register '%s%s' in an "
4193 "instruction requiring REX prefix."),
4194 register_prefix, i.op[x].regs->reg_name);
4195
4196 /* Otherwise it is equivalent to the extended register.
4197 Since the encoding doesn't change this is merely
4198 cosmetic cleanup for debug output. */
4199
4200 i.op[x].regs = i.op[x].regs + 8;
4201 }
4202 }
4203 }
4204
4205 if (i.rex == 0 && i.rex_encoding)
4206 {
4207 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4208 that uses legacy register. If it is "hi" register, don't add
4209 the REX_OPCODE byte. */
4210 int x;
4211 for (x = 0; x < 2; x++)
4212 if (i.types[x].bitfield.reg
4213 && i.types[x].bitfield.byte
4214 && (i.op[x].regs->reg_flags & RegRex64) == 0
4215 && i.op[x].regs->reg_num > 3)
4216 {
4217 i.rex_encoding = FALSE;
4218 break;
4219 }
4220
4221 if (i.rex_encoding)
4222 i.rex = REX_OPCODE;
4223 }
4224
4225 if (i.rex != 0)
4226 add_prefix (REX_OPCODE | i.rex);
4227
4228 /* We are ready to output the insn. */
4229 output_insn ();
4230 }
4231
4232 static char *
4233 parse_insn (char *line, char *mnemonic)
4234 {
4235 char *l = line;
4236 char *token_start = l;
4237 char *mnem_p;
4238 int supported;
4239 const insn_template *t;
4240 char *dot_p = NULL;
4241
4242 while (1)
4243 {
4244 mnem_p = mnemonic;
4245 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4246 {
4247 if (*mnem_p == '.')
4248 dot_p = mnem_p;
4249 mnem_p++;
4250 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4251 {
4252 as_bad (_("no such instruction: `%s'"), token_start);
4253 return NULL;
4254 }
4255 l++;
4256 }
4257 if (!is_space_char (*l)
4258 && *l != END_OF_INSN
4259 && (intel_syntax
4260 || (*l != PREFIX_SEPARATOR
4261 && *l != ',')))
4262 {
4263 as_bad (_("invalid character %s in mnemonic"),
4264 output_invalid (*l));
4265 return NULL;
4266 }
4267 if (token_start == l)
4268 {
4269 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4270 as_bad (_("expecting prefix; got nothing"));
4271 else
4272 as_bad (_("expecting mnemonic; got nothing"));
4273 return NULL;
4274 }
4275
4276 /* Look up instruction (or prefix) via hash table. */
4277 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4278
4279 if (*l != END_OF_INSN
4280 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4281 && current_templates
4282 && current_templates->start->opcode_modifier.isprefix)
4283 {
4284 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4285 {
4286 as_bad ((flag_code != CODE_64BIT
4287 ? _("`%s' is only supported in 64-bit mode")
4288 : _("`%s' is not supported in 64-bit mode")),
4289 current_templates->start->name);
4290 return NULL;
4291 }
4292 /* If we are in 16-bit mode, do not allow addr16 or data16.
4293 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4294 if ((current_templates->start->opcode_modifier.size16
4295 || current_templates->start->opcode_modifier.size32)
4296 && flag_code != CODE_64BIT
4297 && (current_templates->start->opcode_modifier.size32
4298 ^ (flag_code == CODE_16BIT)))
4299 {
4300 as_bad (_("redundant %s prefix"),
4301 current_templates->start->name);
4302 return NULL;
4303 }
4304 if (current_templates->start->opcode_length == 0)
4305 {
4306 /* Handle pseudo prefixes. */
4307 switch (current_templates->start->base_opcode)
4308 {
4309 case 0x0:
4310 /* {disp8} */
4311 i.disp_encoding = disp_encoding_8bit;
4312 break;
4313 case 0x1:
4314 /* {disp32} */
4315 i.disp_encoding = disp_encoding_32bit;
4316 break;
4317 case 0x2:
4318 /* {load} */
4319 i.dir_encoding = dir_encoding_load;
4320 break;
4321 case 0x3:
4322 /* {store} */
4323 i.dir_encoding = dir_encoding_store;
4324 break;
4325 case 0x4:
4326 /* {vex2} */
4327 i.vec_encoding = vex_encoding_vex2;
4328 break;
4329 case 0x5:
4330 /* {vex3} */
4331 i.vec_encoding = vex_encoding_vex3;
4332 break;
4333 case 0x6:
4334 /* {evex} */
4335 i.vec_encoding = vex_encoding_evex;
4336 break;
4337 case 0x7:
4338 /* {rex} */
4339 i.rex_encoding = TRUE;
4340 break;
4341 case 0x8:
4342 /* {nooptimize} */
4343 i.no_optimize = TRUE;
4344 break;
4345 default:
4346 abort ();
4347 }
4348 }
4349 else
4350 {
4351 /* Add prefix, checking for repeated prefixes. */
4352 switch (add_prefix (current_templates->start->base_opcode))
4353 {
4354 case PREFIX_EXIST:
4355 return NULL;
4356 case PREFIX_DS:
4357 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4358 i.notrack_prefix = current_templates->start->name;
4359 break;
4360 case PREFIX_REP:
4361 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4362 i.hle_prefix = current_templates->start->name;
4363 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4364 i.bnd_prefix = current_templates->start->name;
4365 else
4366 i.rep_prefix = current_templates->start->name;
4367 break;
4368 default:
4369 break;
4370 }
4371 }
4372 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4373 token_start = ++l;
4374 }
4375 else
4376 break;
4377 }
4378
4379 if (!current_templates)
4380 {
4381 /* Check if we should swap operand or force 32bit displacement in
4382 encoding. */
4383 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4384 i.dir_encoding = dir_encoding_store;
4385 else if (mnem_p - 3 == dot_p
4386 && dot_p[1] == 'd'
4387 && dot_p[2] == '8')
4388 i.disp_encoding = disp_encoding_8bit;
4389 else if (mnem_p - 4 == dot_p
4390 && dot_p[1] == 'd'
4391 && dot_p[2] == '3'
4392 && dot_p[3] == '2')
4393 i.disp_encoding = disp_encoding_32bit;
4394 else
4395 goto check_suffix;
4396 mnem_p = dot_p;
4397 *dot_p = '\0';
4398 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4399 }
4400
4401 if (!current_templates)
4402 {
4403 check_suffix:
4404 /* See if we can get a match by trimming off a suffix. */
4405 switch (mnem_p[-1])
4406 {
4407 case WORD_MNEM_SUFFIX:
4408 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4409 i.suffix = SHORT_MNEM_SUFFIX;
4410 else
4411 /* Fall through. */
4412 case BYTE_MNEM_SUFFIX:
4413 case QWORD_MNEM_SUFFIX:
4414 i.suffix = mnem_p[-1];
4415 mnem_p[-1] = '\0';
4416 current_templates = (const templates *) hash_find (op_hash,
4417 mnemonic);
4418 break;
4419 case SHORT_MNEM_SUFFIX:
4420 case LONG_MNEM_SUFFIX:
4421 if (!intel_syntax)
4422 {
4423 i.suffix = mnem_p[-1];
4424 mnem_p[-1] = '\0';
4425 current_templates = (const templates *) hash_find (op_hash,
4426 mnemonic);
4427 }
4428 break;
4429
4430 /* Intel Syntax. */
4431 case 'd':
4432 if (intel_syntax)
4433 {
4434 if (intel_float_operand (mnemonic) == 1)
4435 i.suffix = SHORT_MNEM_SUFFIX;
4436 else
4437 i.suffix = LONG_MNEM_SUFFIX;
4438 mnem_p[-1] = '\0';
4439 current_templates = (const templates *) hash_find (op_hash,
4440 mnemonic);
4441 }
4442 break;
4443 }
4444 if (!current_templates)
4445 {
4446 as_bad (_("no such instruction: `%s'"), token_start);
4447 return NULL;
4448 }
4449 }
4450
4451 if (current_templates->start->opcode_modifier.jump
4452 || current_templates->start->opcode_modifier.jumpbyte)
4453 {
4454 /* Check for a branch hint. We allow ",pt" and ",pn" for
4455 predict taken and predict not taken respectively.
4456 I'm not sure that branch hints actually do anything on loop
4457 and jcxz insns (JumpByte) for current Pentium4 chips. They
4458 may work in the future and it doesn't hurt to accept them
4459 now. */
4460 if (l[0] == ',' && l[1] == 'p')
4461 {
4462 if (l[2] == 't')
4463 {
4464 if (!add_prefix (DS_PREFIX_OPCODE))
4465 return NULL;
4466 l += 3;
4467 }
4468 else if (l[2] == 'n')
4469 {
4470 if (!add_prefix (CS_PREFIX_OPCODE))
4471 return NULL;
4472 l += 3;
4473 }
4474 }
4475 }
4476 /* Any other comma loses. */
4477 if (*l == ',')
4478 {
4479 as_bad (_("invalid character %s in mnemonic"),
4480 output_invalid (*l));
4481 return NULL;
4482 }
4483
4484 /* Check if instruction is supported on specified architecture. */
4485 supported = 0;
4486 for (t = current_templates->start; t < current_templates->end; ++t)
4487 {
4488 supported |= cpu_flags_match (t);
4489 if (supported == CPU_FLAGS_PERFECT_MATCH)
4490 {
4491 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4492 as_warn (_("use .code16 to ensure correct addressing mode"));
4493
4494 return l;
4495 }
4496 }
4497
4498 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4499 as_bad (flag_code == CODE_64BIT
4500 ? _("`%s' is not supported in 64-bit mode")
4501 : _("`%s' is only supported in 64-bit mode"),
4502 current_templates->start->name);
4503 else
4504 as_bad (_("`%s' is not supported on `%s%s'"),
4505 current_templates->start->name,
4506 cpu_arch_name ? cpu_arch_name : default_arch,
4507 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4508
4509 return NULL;
4510 }
4511
4512 static char *
4513 parse_operands (char *l, const char *mnemonic)
4514 {
4515 char *token_start;
4516
4517 /* 1 if operand is pending after ','. */
4518 unsigned int expecting_operand = 0;
4519
4520 /* Non-zero if operand parens not balanced. */
4521 unsigned int paren_not_balanced;
4522
4523 while (*l != END_OF_INSN)
4524 {
4525 /* Skip optional white space before operand. */
4526 if (is_space_char (*l))
4527 ++l;
4528 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4529 {
4530 as_bad (_("invalid character %s before operand %d"),
4531 output_invalid (*l),
4532 i.operands + 1);
4533 return NULL;
4534 }
4535 token_start = l; /* After white space. */
4536 paren_not_balanced = 0;
4537 while (paren_not_balanced || *l != ',')
4538 {
4539 if (*l == END_OF_INSN)
4540 {
4541 if (paren_not_balanced)
4542 {
4543 if (!intel_syntax)
4544 as_bad (_("unbalanced parenthesis in operand %d."),
4545 i.operands + 1);
4546 else
4547 as_bad (_("unbalanced brackets in operand %d."),
4548 i.operands + 1);
4549 return NULL;
4550 }
4551 else
4552 break; /* we are done */
4553 }
4554 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4555 {
4556 as_bad (_("invalid character %s in operand %d"),
4557 output_invalid (*l),
4558 i.operands + 1);
4559 return NULL;
4560 }
4561 if (!intel_syntax)
4562 {
4563 if (*l == '(')
4564 ++paren_not_balanced;
4565 if (*l == ')')
4566 --paren_not_balanced;
4567 }
4568 else
4569 {
4570 if (*l == '[')
4571 ++paren_not_balanced;
4572 if (*l == ']')
4573 --paren_not_balanced;
4574 }
4575 l++;
4576 }
4577 if (l != token_start)
4578 { /* Yes, we've read in another operand. */
4579 unsigned int operand_ok;
4580 this_operand = i.operands++;
4581 if (i.operands > MAX_OPERANDS)
4582 {
4583 as_bad (_("spurious operands; (%d operands/instruction max)"),
4584 MAX_OPERANDS);
4585 return NULL;
4586 }
4587 i.types[this_operand].bitfield.unspecified = 1;
4588 /* Now parse operand adding info to 'i' as we go along. */
4589 END_STRING_AND_SAVE (l);
4590
4591 if (intel_syntax)
4592 operand_ok =
4593 i386_intel_operand (token_start,
4594 intel_float_operand (mnemonic));
4595 else
4596 operand_ok = i386_att_operand (token_start);
4597
4598 RESTORE_END_STRING (l);
4599 if (!operand_ok)
4600 return NULL;
4601 }
4602 else
4603 {
4604 if (expecting_operand)
4605 {
4606 expecting_operand_after_comma:
4607 as_bad (_("expecting operand after ','; got nothing"));
4608 return NULL;
4609 }
4610 if (*l == ',')
4611 {
4612 as_bad (_("expecting operand before ','; got nothing"));
4613 return NULL;
4614 }
4615 }
4616
4617 /* Now *l must be either ',' or END_OF_INSN. */
4618 if (*l == ',')
4619 {
4620 if (*++l == END_OF_INSN)
4621 {
4622 /* Just skip it, if it's \n complain. */
4623 goto expecting_operand_after_comma;
4624 }
4625 expecting_operand = 1;
4626 }
4627 }
4628 return l;
4629 }
4630
4631 static void
4632 swap_2_operands (int xchg1, int xchg2)
4633 {
4634 union i386_op temp_op;
4635 i386_operand_type temp_type;
4636 enum bfd_reloc_code_real temp_reloc;
4637
4638 temp_type = i.types[xchg2];
4639 i.types[xchg2] = i.types[xchg1];
4640 i.types[xchg1] = temp_type;
4641 temp_op = i.op[xchg2];
4642 i.op[xchg2] = i.op[xchg1];
4643 i.op[xchg1] = temp_op;
4644 temp_reloc = i.reloc[xchg2];
4645 i.reloc[xchg2] = i.reloc[xchg1];
4646 i.reloc[xchg1] = temp_reloc;
4647
4648 if (i.mask)
4649 {
4650 if (i.mask->operand == xchg1)
4651 i.mask->operand = xchg2;
4652 else if (i.mask->operand == xchg2)
4653 i.mask->operand = xchg1;
4654 }
4655 if (i.broadcast)
4656 {
4657 if (i.broadcast->operand == xchg1)
4658 i.broadcast->operand = xchg2;
4659 else if (i.broadcast->operand == xchg2)
4660 i.broadcast->operand = xchg1;
4661 }
4662 if (i.rounding)
4663 {
4664 if (i.rounding->operand == xchg1)
4665 i.rounding->operand = xchg2;
4666 else if (i.rounding->operand == xchg2)
4667 i.rounding->operand = xchg1;
4668 }
4669 }
4670
4671 static void
4672 swap_operands (void)
4673 {
4674 switch (i.operands)
4675 {
4676 case 5:
4677 case 4:
4678 swap_2_operands (1, i.operands - 2);
4679 /* Fall through. */
4680 case 3:
4681 case 2:
4682 swap_2_operands (0, i.operands - 1);
4683 break;
4684 default:
4685 abort ();
4686 }
4687
4688 if (i.mem_operands == 2)
4689 {
4690 const seg_entry *temp_seg;
4691 temp_seg = i.seg[0];
4692 i.seg[0] = i.seg[1];
4693 i.seg[1] = temp_seg;
4694 }
4695 }
4696
4697 /* Try to ensure constant immediates are represented in the smallest
4698 opcode possible. */
4699 static void
4700 optimize_imm (void)
4701 {
4702 char guess_suffix = 0;
4703 int op;
4704
4705 if (i.suffix)
4706 guess_suffix = i.suffix;
4707 else if (i.reg_operands)
4708 {
4709 /* Figure out a suffix from the last register operand specified.
4710 We can't do this properly yet, ie. excluding InOutPortReg,
4711 but the following works for instructions with immediates.
4712 In any case, we can't set i.suffix yet. */
4713 for (op = i.operands; --op >= 0;)
4714 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4715 {
4716 guess_suffix = BYTE_MNEM_SUFFIX;
4717 break;
4718 }
4719 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4720 {
4721 guess_suffix = WORD_MNEM_SUFFIX;
4722 break;
4723 }
4724 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4725 {
4726 guess_suffix = LONG_MNEM_SUFFIX;
4727 break;
4728 }
4729 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4730 {
4731 guess_suffix = QWORD_MNEM_SUFFIX;
4732 break;
4733 }
4734 }
4735 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4736 guess_suffix = WORD_MNEM_SUFFIX;
4737
4738 for (op = i.operands; --op >= 0;)
4739 if (operand_type_check (i.types[op], imm))
4740 {
4741 switch (i.op[op].imms->X_op)
4742 {
4743 case O_constant:
4744 /* If a suffix is given, this operand may be shortened. */
4745 switch (guess_suffix)
4746 {
4747 case LONG_MNEM_SUFFIX:
4748 i.types[op].bitfield.imm32 = 1;
4749 i.types[op].bitfield.imm64 = 1;
4750 break;
4751 case WORD_MNEM_SUFFIX:
4752 i.types[op].bitfield.imm16 = 1;
4753 i.types[op].bitfield.imm32 = 1;
4754 i.types[op].bitfield.imm32s = 1;
4755 i.types[op].bitfield.imm64 = 1;
4756 break;
4757 case BYTE_MNEM_SUFFIX:
4758 i.types[op].bitfield.imm8 = 1;
4759 i.types[op].bitfield.imm8s = 1;
4760 i.types[op].bitfield.imm16 = 1;
4761 i.types[op].bitfield.imm32 = 1;
4762 i.types[op].bitfield.imm32s = 1;
4763 i.types[op].bitfield.imm64 = 1;
4764 break;
4765 }
4766
4767 /* If this operand is at most 16 bits, convert it
4768 to a signed 16 bit number before trying to see
4769 whether it will fit in an even smaller size.
4770 This allows a 16-bit operand such as $0xffe0 to
4771 be recognised as within Imm8S range. */
4772 if ((i.types[op].bitfield.imm16)
4773 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4774 {
4775 i.op[op].imms->X_add_number =
4776 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4777 }
4778 #ifdef BFD64
4779 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4780 if ((i.types[op].bitfield.imm32)
4781 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4782 == 0))
4783 {
4784 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4785 ^ ((offsetT) 1 << 31))
4786 - ((offsetT) 1 << 31));
4787 }
4788 #endif
4789 i.types[op]
4790 = operand_type_or (i.types[op],
4791 smallest_imm_type (i.op[op].imms->X_add_number));
4792
4793 /* We must avoid matching of Imm32 templates when 64bit
4794 only immediate is available. */
4795 if (guess_suffix == QWORD_MNEM_SUFFIX)
4796 i.types[op].bitfield.imm32 = 0;
4797 break;
4798
4799 case O_absent:
4800 case O_register:
4801 abort ();
4802
4803 /* Symbols and expressions. */
4804 default:
4805 /* Convert symbolic operand to proper sizes for matching, but don't
4806 prevent matching a set of insns that only supports sizes other
4807 than those matching the insn suffix. */
4808 {
4809 i386_operand_type mask, allowed;
4810 const insn_template *t;
4811
4812 operand_type_set (&mask, 0);
4813 operand_type_set (&allowed, 0);
4814
4815 for (t = current_templates->start;
4816 t < current_templates->end;
4817 ++t)
4818 allowed = operand_type_or (allowed,
4819 t->operand_types[op]);
4820 switch (guess_suffix)
4821 {
4822 case QWORD_MNEM_SUFFIX:
4823 mask.bitfield.imm64 = 1;
4824 mask.bitfield.imm32s = 1;
4825 break;
4826 case LONG_MNEM_SUFFIX:
4827 mask.bitfield.imm32 = 1;
4828 break;
4829 case WORD_MNEM_SUFFIX:
4830 mask.bitfield.imm16 = 1;
4831 break;
4832 case BYTE_MNEM_SUFFIX:
4833 mask.bitfield.imm8 = 1;
4834 break;
4835 default:
4836 break;
4837 }
4838 allowed = operand_type_and (mask, allowed);
4839 if (!operand_type_all_zero (&allowed))
4840 i.types[op] = operand_type_and (i.types[op], mask);
4841 }
4842 break;
4843 }
4844 }
4845 }
4846
4847 /* Try to use the smallest displacement type too. */
4848 static void
4849 optimize_disp (void)
4850 {
4851 int op;
4852
4853 for (op = i.operands; --op >= 0;)
4854 if (operand_type_check (i.types[op], disp))
4855 {
4856 if (i.op[op].disps->X_op == O_constant)
4857 {
4858 offsetT op_disp = i.op[op].disps->X_add_number;
4859
4860 if (i.types[op].bitfield.disp16
4861 && (op_disp & ~(offsetT) 0xffff) == 0)
4862 {
4863 /* If this operand is at most 16 bits, convert
4864 to a signed 16 bit number and don't use 64bit
4865 displacement. */
4866 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4867 i.types[op].bitfield.disp64 = 0;
4868 }
4869 #ifdef BFD64
4870 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4871 if (i.types[op].bitfield.disp32
4872 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4873 {
4874 /* If this operand is at most 32 bits, convert
4875 to a signed 32 bit number and don't use 64bit
4876 displacement. */
4877 op_disp &= (((offsetT) 2 << 31) - 1);
4878 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4879 i.types[op].bitfield.disp64 = 0;
4880 }
4881 #endif
4882 if (!op_disp && i.types[op].bitfield.baseindex)
4883 {
4884 i.types[op].bitfield.disp8 = 0;
4885 i.types[op].bitfield.disp16 = 0;
4886 i.types[op].bitfield.disp32 = 0;
4887 i.types[op].bitfield.disp32s = 0;
4888 i.types[op].bitfield.disp64 = 0;
4889 i.op[op].disps = 0;
4890 i.disp_operands--;
4891 }
4892 else if (flag_code == CODE_64BIT)
4893 {
4894 if (fits_in_signed_long (op_disp))
4895 {
4896 i.types[op].bitfield.disp64 = 0;
4897 i.types[op].bitfield.disp32s = 1;
4898 }
4899 if (i.prefix[ADDR_PREFIX]
4900 && fits_in_unsigned_long (op_disp))
4901 i.types[op].bitfield.disp32 = 1;
4902 }
4903 if ((i.types[op].bitfield.disp32
4904 || i.types[op].bitfield.disp32s
4905 || i.types[op].bitfield.disp16)
4906 && fits_in_disp8 (op_disp))
4907 i.types[op].bitfield.disp8 = 1;
4908 }
4909 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4910 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4911 {
4912 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4913 i.op[op].disps, 0, i.reloc[op]);
4914 i.types[op].bitfield.disp8 = 0;
4915 i.types[op].bitfield.disp16 = 0;
4916 i.types[op].bitfield.disp32 = 0;
4917 i.types[op].bitfield.disp32s = 0;
4918 i.types[op].bitfield.disp64 = 0;
4919 }
4920 else
4921 /* We only support 64bit displacement on constants. */
4922 i.types[op].bitfield.disp64 = 0;
4923 }
4924 }
4925
4926 /* Check if operands are valid for the instruction. */
4927
4928 static int
4929 check_VecOperands (const insn_template *t)
4930 {
4931 unsigned int op;
4932
4933 /* Without VSIB byte, we can't have a vector register for index. */
4934 if (!t->opcode_modifier.vecsib
4935 && i.index_reg
4936 && (i.index_reg->reg_type.bitfield.xmmword
4937 || i.index_reg->reg_type.bitfield.ymmword
4938 || i.index_reg->reg_type.bitfield.zmmword))
4939 {
4940 i.error = unsupported_vector_index_register;
4941 return 1;
4942 }
4943
4944 /* Check if default mask is allowed. */
4945 if (t->opcode_modifier.nodefmask
4946 && (!i.mask || i.mask->mask->reg_num == 0))
4947 {
4948 i.error = no_default_mask;
4949 return 1;
4950 }
4951
4952 /* For VSIB byte, we need a vector register for index, and all vector
4953 registers must be distinct. */
4954 if (t->opcode_modifier.vecsib)
4955 {
4956 if (!i.index_reg
4957 || !((t->opcode_modifier.vecsib == VecSIB128
4958 && i.index_reg->reg_type.bitfield.xmmword)
4959 || (t->opcode_modifier.vecsib == VecSIB256
4960 && i.index_reg->reg_type.bitfield.ymmword)
4961 || (t->opcode_modifier.vecsib == VecSIB512
4962 && i.index_reg->reg_type.bitfield.zmmword)))
4963 {
4964 i.error = invalid_vsib_address;
4965 return 1;
4966 }
4967
4968 gas_assert (i.reg_operands == 2 || i.mask);
4969 if (i.reg_operands == 2 && !i.mask)
4970 {
4971 gas_assert (i.types[0].bitfield.regsimd);
4972 gas_assert (i.types[0].bitfield.xmmword
4973 || i.types[0].bitfield.ymmword);
4974 gas_assert (i.types[2].bitfield.regsimd);
4975 gas_assert (i.types[2].bitfield.xmmword
4976 || i.types[2].bitfield.ymmword);
4977 if (operand_check == check_none)
4978 return 0;
4979 if (register_number (i.op[0].regs)
4980 != register_number (i.index_reg)
4981 && register_number (i.op[2].regs)
4982 != register_number (i.index_reg)
4983 && register_number (i.op[0].regs)
4984 != register_number (i.op[2].regs))
4985 return 0;
4986 if (operand_check == check_error)
4987 {
4988 i.error = invalid_vector_register_set;
4989 return 1;
4990 }
4991 as_warn (_("mask, index, and destination registers should be distinct"));
4992 }
4993 else if (i.reg_operands == 1 && i.mask)
4994 {
4995 if (i.types[1].bitfield.regsimd
4996 && (i.types[1].bitfield.xmmword
4997 || i.types[1].bitfield.ymmword
4998 || i.types[1].bitfield.zmmword)
4999 && (register_number (i.op[1].regs)
5000 == register_number (i.index_reg)))
5001 {
5002 if (operand_check == check_error)
5003 {
5004 i.error = invalid_vector_register_set;
5005 return 1;
5006 }
5007 if (operand_check != check_none)
5008 as_warn (_("index and destination registers should be distinct"));
5009 }
5010 }
5011 }
5012
5013 /* Check if broadcast is supported by the instruction and is applied
5014 to the memory operand. */
5015 if (i.broadcast)
5016 {
5017 int broadcasted_opnd_size;
5018
5019 /* Check if specified broadcast is supported in this instruction,
5020 and it's applied to memory operand of DWORD or QWORD type,
5021 depending on VecESize. */
5022 if (i.broadcast->type != t->opcode_modifier.broadcast
5023 || !i.types[i.broadcast->operand].bitfield.mem
5024 || (t->opcode_modifier.vecesize == 0
5025 && !i.types[i.broadcast->operand].bitfield.dword
5026 && !i.types[i.broadcast->operand].bitfield.unspecified)
5027 || (t->opcode_modifier.vecesize == 1
5028 && !i.types[i.broadcast->operand].bitfield.qword
5029 && !i.types[i.broadcast->operand].bitfield.unspecified))
5030 goto bad_broadcast;
5031
5032 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5033 if (i.broadcast->type == BROADCAST_1TO16)
5034 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5035 else if (i.broadcast->type == BROADCAST_1TO8)
5036 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
5037 else if (i.broadcast->type == BROADCAST_1TO4)
5038 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5039 else if (i.broadcast->type == BROADCAST_1TO2)
5040 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
5041 else
5042 goto bad_broadcast;
5043
5044 if ((broadcasted_opnd_size == 256
5045 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5046 || (broadcasted_opnd_size == 512
5047 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5048 {
5049 bad_broadcast:
5050 i.error = unsupported_broadcast;
5051 return 1;
5052 }
5053 }
5054 /* If broadcast is supported in this instruction, we need to check if
5055 operand of one-element size isn't specified without broadcast. */
5056 else if (t->opcode_modifier.broadcast && i.mem_operands)
5057 {
5058 /* Find memory operand. */
5059 for (op = 0; op < i.operands; op++)
5060 if (operand_type_check (i.types[op], anymem))
5061 break;
5062 gas_assert (op < i.operands);
5063 /* Check size of the memory operand. */
5064 if ((t->opcode_modifier.vecesize == 0
5065 && i.types[op].bitfield.dword)
5066 || (t->opcode_modifier.vecesize == 1
5067 && i.types[op].bitfield.qword))
5068 {
5069 i.error = broadcast_needed;
5070 return 1;
5071 }
5072 }
5073
5074 /* Check if requested masking is supported. */
5075 if (i.mask
5076 && (!t->opcode_modifier.masking
5077 || (i.mask->zeroing
5078 && t->opcode_modifier.masking == MERGING_MASKING)))
5079 {
5080 i.error = unsupported_masking;
5081 return 1;
5082 }
5083
5084 /* Check if masking is applied to dest operand. */
5085 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5086 {
5087 i.error = mask_not_on_destination;
5088 return 1;
5089 }
5090
5091 /* Check RC/SAE. */
5092 if (i.rounding)
5093 {
5094 if ((i.rounding->type != saeonly
5095 && !t->opcode_modifier.staticrounding)
5096 || (i.rounding->type == saeonly
5097 && (t->opcode_modifier.staticrounding
5098 || !t->opcode_modifier.sae)))
5099 {
5100 i.error = unsupported_rc_sae;
5101 return 1;
5102 }
5103 /* If the instruction has several immediate operands and one of
5104 them is rounding, the rounding operand should be the last
5105 immediate operand. */
5106 if (i.imm_operands > 1
5107 && i.rounding->operand != (int) (i.imm_operands - 1))
5108 {
5109 i.error = rc_sae_operand_not_last_imm;
5110 return 1;
5111 }
5112 }
5113
5114 /* Check vector Disp8 operand. */
5115 if (t->opcode_modifier.disp8memshift
5116 && i.disp_encoding != disp_encoding_32bit)
5117 {
5118 if (i.broadcast)
5119 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5120 else
5121 i.memshift = t->opcode_modifier.disp8memshift;
5122
5123 for (op = 0; op < i.operands; op++)
5124 if (operand_type_check (i.types[op], disp)
5125 && i.op[op].disps->X_op == O_constant)
5126 {
5127 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5128 {
5129 i.types[op].bitfield.disp8 = 1;
5130 return 0;
5131 }
5132 i.types[op].bitfield.disp8 = 0;
5133 }
5134 }
5135
5136 i.memshift = 0;
5137
5138 return 0;
5139 }
5140
5141 /* Check if operands are valid for the instruction. Update VEX
5142 operand types. */
5143
5144 static int
5145 VEX_check_operands (const insn_template *t)
5146 {
5147 if (i.vec_encoding == vex_encoding_evex)
5148 {
5149 /* This instruction must be encoded with EVEX prefix. */
5150 if (!t->opcode_modifier.evex)
5151 {
5152 i.error = unsupported;
5153 return 1;
5154 }
5155 return 0;
5156 }
5157
5158 if (!t->opcode_modifier.vex)
5159 {
5160 /* This instruction template doesn't have VEX prefix. */
5161 if (i.vec_encoding != vex_encoding_default)
5162 {
5163 i.error = unsupported;
5164 return 1;
5165 }
5166 return 0;
5167 }
5168
5169 /* Only check VEX_Imm4, which must be the first operand. */
5170 if (t->operand_types[0].bitfield.vec_imm4)
5171 {
5172 if (i.op[0].imms->X_op != O_constant
5173 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5174 {
5175 i.error = bad_imm4;
5176 return 1;
5177 }
5178
5179 /* Turn off Imm8 so that update_imm won't complain. */
5180 i.types[0] = vec_imm4;
5181 }
5182
5183 return 0;
5184 }
5185
5186 static const insn_template *
5187 match_template (char mnem_suffix)
5188 {
5189 /* Points to template once we've found it. */
5190 const insn_template *t;
5191 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5192 i386_operand_type overlap4;
5193 unsigned int found_reverse_match;
5194 i386_opcode_modifier suffix_check, mnemsuf_check;
5195 i386_operand_type operand_types [MAX_OPERANDS];
5196 int addr_prefix_disp;
5197 unsigned int j;
5198 unsigned int found_cpu_match;
5199 unsigned int check_register;
5200 enum i386_error specific_error = 0;
5201
5202 #if MAX_OPERANDS != 5
5203 # error "MAX_OPERANDS must be 5."
5204 #endif
5205
5206 found_reverse_match = 0;
5207 addr_prefix_disp = -1;
5208
5209 memset (&suffix_check, 0, sizeof (suffix_check));
5210 if (i.suffix == BYTE_MNEM_SUFFIX)
5211 suffix_check.no_bsuf = 1;
5212 else if (i.suffix == WORD_MNEM_SUFFIX)
5213 suffix_check.no_wsuf = 1;
5214 else if (i.suffix == SHORT_MNEM_SUFFIX)
5215 suffix_check.no_ssuf = 1;
5216 else if (i.suffix == LONG_MNEM_SUFFIX)
5217 suffix_check.no_lsuf = 1;
5218 else if (i.suffix == QWORD_MNEM_SUFFIX)
5219 suffix_check.no_qsuf = 1;
5220 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5221 suffix_check.no_ldsuf = 1;
5222
5223 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5224 if (intel_syntax)
5225 {
5226 switch (mnem_suffix)
5227 {
5228 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5229 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5230 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5231 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5232 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5233 }
5234 }
5235
5236 /* Must have right number of operands. */
5237 i.error = number_of_operands_mismatch;
5238
5239 for (t = current_templates->start; t < current_templates->end; t++)
5240 {
5241 addr_prefix_disp = -1;
5242
5243 if (i.operands != t->operands)
5244 continue;
5245
5246 /* Check processor support. */
5247 i.error = unsupported;
5248 found_cpu_match = (cpu_flags_match (t)
5249 == CPU_FLAGS_PERFECT_MATCH);
5250 if (!found_cpu_match)
5251 continue;
5252
5253 /* Check old gcc support. */
5254 i.error = old_gcc_only;
5255 if (!old_gcc && t->opcode_modifier.oldgcc)
5256 continue;
5257
5258 /* Check AT&T mnemonic. */
5259 i.error = unsupported_with_intel_mnemonic;
5260 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5261 continue;
5262
5263 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5264 i.error = unsupported_syntax;
5265 if ((intel_syntax && t->opcode_modifier.attsyntax)
5266 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5267 || (intel64 && t->opcode_modifier.amd64)
5268 || (!intel64 && t->opcode_modifier.intel64))
5269 continue;
5270
5271 /* Check the suffix, except for some instructions in intel mode. */
5272 i.error = invalid_instruction_suffix;
5273 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5274 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5275 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5276 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5277 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5278 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5279 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5280 continue;
5281 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5282 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5283 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5284 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5285 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5286 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5287 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5288 continue;
5289
5290 if (!operand_size_match (t))
5291 continue;
5292
5293 for (j = 0; j < MAX_OPERANDS; j++)
5294 operand_types[j] = t->operand_types[j];
5295
5296 /* In general, don't allow 64-bit operands in 32-bit mode. */
5297 if (i.suffix == QWORD_MNEM_SUFFIX
5298 && flag_code != CODE_64BIT
5299 && (intel_syntax
5300 ? (!t->opcode_modifier.ignoresize
5301 && !intel_float_operand (t->name))
5302 : intel_float_operand (t->name) != 2)
5303 && ((!operand_types[0].bitfield.regmmx
5304 && !operand_types[0].bitfield.regsimd)
5305 || (!operand_types[t->operands > 1].bitfield.regmmx
5306 && !operand_types[t->operands > 1].bitfield.regsimd))
5307 && (t->base_opcode != 0x0fc7
5308 || t->extension_opcode != 1 /* cmpxchg8b */))
5309 continue;
5310
5311 /* In general, don't allow 32-bit operands on pre-386. */
5312 else if (i.suffix == LONG_MNEM_SUFFIX
5313 && !cpu_arch_flags.bitfield.cpui386
5314 && (intel_syntax
5315 ? (!t->opcode_modifier.ignoresize
5316 && !intel_float_operand (t->name))
5317 : intel_float_operand (t->name) != 2)
5318 && ((!operand_types[0].bitfield.regmmx
5319 && !operand_types[0].bitfield.regsimd)
5320 || (!operand_types[t->operands > 1].bitfield.regmmx
5321 && !operand_types[t->operands > 1].bitfield.regsimd)))
5322 continue;
5323
5324 /* Do not verify operands when there are none. */
5325 else
5326 {
5327 if (!t->operands)
5328 /* We've found a match; break out of loop. */
5329 break;
5330 }
5331
5332 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5333 into Disp32/Disp16/Disp32 operand. */
5334 if (i.prefix[ADDR_PREFIX] != 0)
5335 {
5336 /* There should be only one Disp operand. */
5337 switch (flag_code)
5338 {
5339 case CODE_16BIT:
5340 for (j = 0; j < MAX_OPERANDS; j++)
5341 {
5342 if (operand_types[j].bitfield.disp16)
5343 {
5344 addr_prefix_disp = j;
5345 operand_types[j].bitfield.disp32 = 1;
5346 operand_types[j].bitfield.disp16 = 0;
5347 break;
5348 }
5349 }
5350 break;
5351 case CODE_32BIT:
5352 for (j = 0; j < MAX_OPERANDS; j++)
5353 {
5354 if (operand_types[j].bitfield.disp32)
5355 {
5356 addr_prefix_disp = j;
5357 operand_types[j].bitfield.disp32 = 0;
5358 operand_types[j].bitfield.disp16 = 1;
5359 break;
5360 }
5361 }
5362 break;
5363 case CODE_64BIT:
5364 for (j = 0; j < MAX_OPERANDS; j++)
5365 {
5366 if (operand_types[j].bitfield.disp64)
5367 {
5368 addr_prefix_disp = j;
5369 operand_types[j].bitfield.disp64 = 0;
5370 operand_types[j].bitfield.disp32 = 1;
5371 break;
5372 }
5373 }
5374 break;
5375 }
5376 }
5377
5378 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5379 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5380 continue;
5381
5382 /* We check register size if needed. */
5383 check_register = t->opcode_modifier.checkregsize;
5384 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5385 switch (t->operands)
5386 {
5387 case 1:
5388 if (!operand_type_match (overlap0, i.types[0]))
5389 continue;
5390 break;
5391 case 2:
5392 /* xchg %eax, %eax is a special case. It is an alias for nop
5393 only in 32bit mode and we can use opcode 0x90. In 64bit
5394 mode, we can't use 0x90 for xchg %eax, %eax since it should
5395 zero-extend %eax to %rax. */
5396 if (flag_code == CODE_64BIT
5397 && t->base_opcode == 0x90
5398 && operand_type_equal (&i.types [0], &acc32)
5399 && operand_type_equal (&i.types [1], &acc32))
5400 continue;
5401 /* If we want store form, we reverse direction of operands. */
5402 if (i.dir_encoding == dir_encoding_store
5403 && t->opcode_modifier.d)
5404 goto check_reverse;
5405 /* Fall through. */
5406
5407 case 3:
5408 /* If we want store form, we skip the current load. */
5409 if (i.dir_encoding == dir_encoding_store
5410 && i.mem_operands == 0
5411 && t->opcode_modifier.load)
5412 continue;
5413 /* Fall through. */
5414 case 4:
5415 case 5:
5416 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5417 if (!operand_type_match (overlap0, i.types[0])
5418 || !operand_type_match (overlap1, i.types[1])
5419 || (check_register
5420 && !operand_type_register_match (i.types[0],
5421 operand_types[0],
5422 i.types[1],
5423 operand_types[1])))
5424 {
5425 /* Check if other direction is valid ... */
5426 if (!t->opcode_modifier.d)
5427 continue;
5428
5429 check_reverse:
5430 /* Try reversing direction of operands. */
5431 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5432 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5433 if (!operand_type_match (overlap0, i.types[0])
5434 || !operand_type_match (overlap1, i.types[1])
5435 || (check_register
5436 && !operand_type_register_match (i.types[0],
5437 operand_types[1],
5438 i.types[1],
5439 operand_types[0])))
5440 {
5441 /* Does not match either direction. */
5442 continue;
5443 }
5444 /* found_reverse_match holds which of D or FloatR
5445 we've found. */
5446 if (!t->opcode_modifier.d)
5447 found_reverse_match = 0;
5448 else if (operand_types[0].bitfield.tbyte)
5449 found_reverse_match = Opcode_FloatD;
5450 else
5451 found_reverse_match = Opcode_D;
5452 if (t->opcode_modifier.floatr)
5453 found_reverse_match |= Opcode_FloatR;
5454 }
5455 else
5456 {
5457 /* Found a forward 2 operand match here. */
5458 switch (t->operands)
5459 {
5460 case 5:
5461 overlap4 = operand_type_and (i.types[4],
5462 operand_types[4]);
5463 /* Fall through. */
5464 case 4:
5465 overlap3 = operand_type_and (i.types[3],
5466 operand_types[3]);
5467 /* Fall through. */
5468 case 3:
5469 overlap2 = operand_type_and (i.types[2],
5470 operand_types[2]);
5471 break;
5472 }
5473
5474 switch (t->operands)
5475 {
5476 case 5:
5477 if (!operand_type_match (overlap4, i.types[4])
5478 || !operand_type_register_match (i.types[3],
5479 operand_types[3],
5480 i.types[4],
5481 operand_types[4]))
5482 continue;
5483 /* Fall through. */
5484 case 4:
5485 if (!operand_type_match (overlap3, i.types[3])
5486 || (check_register
5487 && !operand_type_register_match (i.types[2],
5488 operand_types[2],
5489 i.types[3],
5490 operand_types[3])))
5491 continue;
5492 /* Fall through. */
5493 case 3:
5494 /* Here we make use of the fact that there are no
5495 reverse match 3 operand instructions, and all 3
5496 operand instructions only need to be checked for
5497 register consistency between operands 2 and 3. */
5498 if (!operand_type_match (overlap2, i.types[2])
5499 || (check_register
5500 && !operand_type_register_match (i.types[1],
5501 operand_types[1],
5502 i.types[2],
5503 operand_types[2])))
5504 continue;
5505 break;
5506 }
5507 }
5508 /* Found either forward/reverse 2, 3 or 4 operand match here:
5509 slip through to break. */
5510 }
5511 if (!found_cpu_match)
5512 {
5513 found_reverse_match = 0;
5514 continue;
5515 }
5516
5517 /* Check if vector and VEX operands are valid. */
5518 if (check_VecOperands (t) || VEX_check_operands (t))
5519 {
5520 specific_error = i.error;
5521 continue;
5522 }
5523
5524 /* We've found a match; break out of loop. */
5525 break;
5526 }
5527
5528 if (t == current_templates->end)
5529 {
5530 /* We found no match. */
5531 const char *err_msg;
5532 switch (specific_error ? specific_error : i.error)
5533 {
5534 default:
5535 abort ();
5536 case operand_size_mismatch:
5537 err_msg = _("operand size mismatch");
5538 break;
5539 case operand_type_mismatch:
5540 err_msg = _("operand type mismatch");
5541 break;
5542 case register_type_mismatch:
5543 err_msg = _("register type mismatch");
5544 break;
5545 case number_of_operands_mismatch:
5546 err_msg = _("number of operands mismatch");
5547 break;
5548 case invalid_instruction_suffix:
5549 err_msg = _("invalid instruction suffix");
5550 break;
5551 case bad_imm4:
5552 err_msg = _("constant doesn't fit in 4 bits");
5553 break;
5554 case old_gcc_only:
5555 err_msg = _("only supported with old gcc");
5556 break;
5557 case unsupported_with_intel_mnemonic:
5558 err_msg = _("unsupported with Intel mnemonic");
5559 break;
5560 case unsupported_syntax:
5561 err_msg = _("unsupported syntax");
5562 break;
5563 case unsupported:
5564 as_bad (_("unsupported instruction `%s'"),
5565 current_templates->start->name);
5566 return NULL;
5567 case invalid_vsib_address:
5568 err_msg = _("invalid VSIB address");
5569 break;
5570 case invalid_vector_register_set:
5571 err_msg = _("mask, index, and destination registers must be distinct");
5572 break;
5573 case unsupported_vector_index_register:
5574 err_msg = _("unsupported vector index register");
5575 break;
5576 case unsupported_broadcast:
5577 err_msg = _("unsupported broadcast");
5578 break;
5579 case broadcast_not_on_src_operand:
5580 err_msg = _("broadcast not on source memory operand");
5581 break;
5582 case broadcast_needed:
5583 err_msg = _("broadcast is needed for operand of such type");
5584 break;
5585 case unsupported_masking:
5586 err_msg = _("unsupported masking");
5587 break;
5588 case mask_not_on_destination:
5589 err_msg = _("mask not on destination operand");
5590 break;
5591 case no_default_mask:
5592 err_msg = _("default mask isn't allowed");
5593 break;
5594 case unsupported_rc_sae:
5595 err_msg = _("unsupported static rounding/sae");
5596 break;
5597 case rc_sae_operand_not_last_imm:
5598 if (intel_syntax)
5599 err_msg = _("RC/SAE operand must precede immediate operands");
5600 else
5601 err_msg = _("RC/SAE operand must follow immediate operands");
5602 break;
5603 case invalid_register_operand:
5604 err_msg = _("invalid register operand");
5605 break;
5606 }
5607 as_bad (_("%s for `%s'"), err_msg,
5608 current_templates->start->name);
5609 return NULL;
5610 }
5611
5612 if (!quiet_warnings)
5613 {
5614 if (!intel_syntax
5615 && (i.types[0].bitfield.jumpabsolute
5616 != operand_types[0].bitfield.jumpabsolute))
5617 {
5618 as_warn (_("indirect %s without `*'"), t->name);
5619 }
5620
5621 if (t->opcode_modifier.isprefix
5622 && t->opcode_modifier.ignoresize)
5623 {
5624 /* Warn them that a data or address size prefix doesn't
5625 affect assembly of the next line of code. */
5626 as_warn (_("stand-alone `%s' prefix"), t->name);
5627 }
5628 }
5629
5630 /* Copy the template we found. */
5631 i.tm = *t;
5632
5633 if (addr_prefix_disp != -1)
5634 i.tm.operand_types[addr_prefix_disp]
5635 = operand_types[addr_prefix_disp];
5636
5637 if (found_reverse_match)
5638 {
5639 /* If we found a reverse match we must alter the opcode
5640 direction bit. found_reverse_match holds bits to change
5641 (different for int & float insns). */
5642
5643 i.tm.base_opcode ^= found_reverse_match;
5644
5645 i.tm.operand_types[0] = operand_types[1];
5646 i.tm.operand_types[1] = operand_types[0];
5647 }
5648
5649 return t;
5650 }
5651
5652 static int
5653 check_string (void)
5654 {
5655 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5656 if (i.tm.operand_types[mem_op].bitfield.esseg)
5657 {
5658 if (i.seg[0] != NULL && i.seg[0] != &es)
5659 {
5660 as_bad (_("`%s' operand %d must use `%ses' segment"),
5661 i.tm.name,
5662 mem_op + 1,
5663 register_prefix);
5664 return 0;
5665 }
5666 /* There's only ever one segment override allowed per instruction.
5667 This instruction possibly has a legal segment override on the
5668 second operand, so copy the segment to where non-string
5669 instructions store it, allowing common code. */
5670 i.seg[0] = i.seg[1];
5671 }
5672 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5673 {
5674 if (i.seg[1] != NULL && i.seg[1] != &es)
5675 {
5676 as_bad (_("`%s' operand %d must use `%ses' segment"),
5677 i.tm.name,
5678 mem_op + 2,
5679 register_prefix);
5680 return 0;
5681 }
5682 }
5683 return 1;
5684 }
5685
5686 static int
5687 process_suffix (void)
5688 {
5689 /* If matched instruction specifies an explicit instruction mnemonic
5690 suffix, use it. */
5691 if (i.tm.opcode_modifier.size16)
5692 i.suffix = WORD_MNEM_SUFFIX;
5693 else if (i.tm.opcode_modifier.size32)
5694 i.suffix = LONG_MNEM_SUFFIX;
5695 else if (i.tm.opcode_modifier.size64)
5696 i.suffix = QWORD_MNEM_SUFFIX;
5697 else if (i.reg_operands)
5698 {
5699 /* If there's no instruction mnemonic suffix we try to invent one
5700 based on register operands. */
5701 if (!i.suffix)
5702 {
5703 /* We take i.suffix from the last register operand specified,
5704 Destination register type is more significant than source
5705 register type. crc32 in SSE4.2 prefers source register
5706 type. */
5707 if (i.tm.base_opcode == 0xf20f38f1)
5708 {
5709 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5710 i.suffix = WORD_MNEM_SUFFIX;
5711 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5712 i.suffix = LONG_MNEM_SUFFIX;
5713 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5714 i.suffix = QWORD_MNEM_SUFFIX;
5715 }
5716 else if (i.tm.base_opcode == 0xf20f38f0)
5717 {
5718 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5719 i.suffix = BYTE_MNEM_SUFFIX;
5720 }
5721
5722 if (!i.suffix)
5723 {
5724 int op;
5725
5726 if (i.tm.base_opcode == 0xf20f38f1
5727 || i.tm.base_opcode == 0xf20f38f0)
5728 {
5729 /* We have to know the operand size for crc32. */
5730 as_bad (_("ambiguous memory operand size for `%s`"),
5731 i.tm.name);
5732 return 0;
5733 }
5734
5735 for (op = i.operands; --op >= 0;)
5736 if (!i.tm.operand_types[op].bitfield.inoutportreg
5737 && !i.tm.operand_types[op].bitfield.shiftcount)
5738 {
5739 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5740 {
5741 i.suffix = BYTE_MNEM_SUFFIX;
5742 break;
5743 }
5744 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5745 {
5746 i.suffix = WORD_MNEM_SUFFIX;
5747 break;
5748 }
5749 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5750 {
5751 i.suffix = LONG_MNEM_SUFFIX;
5752 break;
5753 }
5754 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5755 {
5756 i.suffix = QWORD_MNEM_SUFFIX;
5757 break;
5758 }
5759 }
5760 }
5761 }
5762 else if (i.suffix == BYTE_MNEM_SUFFIX)
5763 {
5764 if (intel_syntax
5765 && i.tm.opcode_modifier.ignoresize
5766 && i.tm.opcode_modifier.no_bsuf)
5767 i.suffix = 0;
5768 else if (!check_byte_reg ())
5769 return 0;
5770 }
5771 else if (i.suffix == LONG_MNEM_SUFFIX)
5772 {
5773 if (intel_syntax
5774 && i.tm.opcode_modifier.ignoresize
5775 && i.tm.opcode_modifier.no_lsuf)
5776 i.suffix = 0;
5777 else if (!check_long_reg ())
5778 return 0;
5779 }
5780 else if (i.suffix == QWORD_MNEM_SUFFIX)
5781 {
5782 if (intel_syntax
5783 && i.tm.opcode_modifier.ignoresize
5784 && i.tm.opcode_modifier.no_qsuf)
5785 i.suffix = 0;
5786 else if (!check_qword_reg ())
5787 return 0;
5788 }
5789 else if (i.suffix == WORD_MNEM_SUFFIX)
5790 {
5791 if (intel_syntax
5792 && i.tm.opcode_modifier.ignoresize
5793 && i.tm.opcode_modifier.no_wsuf)
5794 i.suffix = 0;
5795 else if (!check_word_reg ())
5796 return 0;
5797 }
5798 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5799 || i.suffix == YMMWORD_MNEM_SUFFIX
5800 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5801 {
5802 /* Skip if the instruction has x/y/z suffix. match_template
5803 should check if it is a valid suffix. */
5804 }
5805 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5806 /* Do nothing if the instruction is going to ignore the prefix. */
5807 ;
5808 else
5809 abort ();
5810 }
5811 else if (i.tm.opcode_modifier.defaultsize
5812 && !i.suffix
5813 /* exclude fldenv/frstor/fsave/fstenv */
5814 && i.tm.opcode_modifier.no_ssuf)
5815 {
5816 i.suffix = stackop_size;
5817 }
5818 else if (intel_syntax
5819 && !i.suffix
5820 && (i.tm.operand_types[0].bitfield.jumpabsolute
5821 || i.tm.opcode_modifier.jumpbyte
5822 || i.tm.opcode_modifier.jumpintersegment
5823 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5824 && i.tm.extension_opcode <= 3)))
5825 {
5826 switch (flag_code)
5827 {
5828 case CODE_64BIT:
5829 if (!i.tm.opcode_modifier.no_qsuf)
5830 {
5831 i.suffix = QWORD_MNEM_SUFFIX;
5832 break;
5833 }
5834 /* Fall through. */
5835 case CODE_32BIT:
5836 if (!i.tm.opcode_modifier.no_lsuf)
5837 i.suffix = LONG_MNEM_SUFFIX;
5838 break;
5839 case CODE_16BIT:
5840 if (!i.tm.opcode_modifier.no_wsuf)
5841 i.suffix = WORD_MNEM_SUFFIX;
5842 break;
5843 }
5844 }
5845
5846 if (!i.suffix)
5847 {
5848 if (!intel_syntax)
5849 {
5850 if (i.tm.opcode_modifier.w)
5851 {
5852 as_bad (_("no instruction mnemonic suffix given and "
5853 "no register operands; can't size instruction"));
5854 return 0;
5855 }
5856 }
5857 else
5858 {
5859 unsigned int suffixes;
5860
5861 suffixes = !i.tm.opcode_modifier.no_bsuf;
5862 if (!i.tm.opcode_modifier.no_wsuf)
5863 suffixes |= 1 << 1;
5864 if (!i.tm.opcode_modifier.no_lsuf)
5865 suffixes |= 1 << 2;
5866 if (!i.tm.opcode_modifier.no_ldsuf)
5867 suffixes |= 1 << 3;
5868 if (!i.tm.opcode_modifier.no_ssuf)
5869 suffixes |= 1 << 4;
5870 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5871 suffixes |= 1 << 5;
5872
5873 /* There are more than suffix matches. */
5874 if (i.tm.opcode_modifier.w
5875 || ((suffixes & (suffixes - 1))
5876 && !i.tm.opcode_modifier.defaultsize
5877 && !i.tm.opcode_modifier.ignoresize))
5878 {
5879 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5880 return 0;
5881 }
5882 }
5883 }
5884
5885 /* Change the opcode based on the operand size given by i.suffix;
5886 We don't need to change things for byte insns. */
5887
5888 if (i.suffix
5889 && i.suffix != BYTE_MNEM_SUFFIX
5890 && i.suffix != XMMWORD_MNEM_SUFFIX
5891 && i.suffix != YMMWORD_MNEM_SUFFIX
5892 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5893 {
5894 /* It's not a byte, select word/dword operation. */
5895 if (i.tm.opcode_modifier.w)
5896 {
5897 if (i.tm.opcode_modifier.shortform)
5898 i.tm.base_opcode |= 8;
5899 else
5900 i.tm.base_opcode |= 1;
5901 }
5902
5903 /* Now select between word & dword operations via the operand
5904 size prefix, except for instructions that will ignore this
5905 prefix anyway. */
5906 if (i.tm.opcode_modifier.addrprefixop0)
5907 {
5908 /* The address size override prefix changes the size of the
5909 first operand. */
5910 if ((flag_code == CODE_32BIT
5911 && i.op->regs[0].reg_type.bitfield.word)
5912 || (flag_code != CODE_32BIT
5913 && i.op->regs[0].reg_type.bitfield.dword))
5914 if (!add_prefix (ADDR_PREFIX_OPCODE))
5915 return 0;
5916 }
5917 else if (i.suffix != QWORD_MNEM_SUFFIX
5918 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5919 && !i.tm.opcode_modifier.ignoresize
5920 && !i.tm.opcode_modifier.floatmf
5921 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5922 || (flag_code == CODE_64BIT
5923 && i.tm.opcode_modifier.jumpbyte)))
5924 {
5925 unsigned int prefix = DATA_PREFIX_OPCODE;
5926
5927 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5928 prefix = ADDR_PREFIX_OPCODE;
5929
5930 if (!add_prefix (prefix))
5931 return 0;
5932 }
5933
5934 /* Set mode64 for an operand. */
5935 if (i.suffix == QWORD_MNEM_SUFFIX
5936 && flag_code == CODE_64BIT
5937 && !i.tm.opcode_modifier.norex64)
5938 {
5939 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5940 need rex64. cmpxchg8b is also a special case. */
5941 if (! (i.operands == 2
5942 && i.tm.base_opcode == 0x90
5943 && i.tm.extension_opcode == None
5944 && operand_type_equal (&i.types [0], &acc64)
5945 && operand_type_equal (&i.types [1], &acc64))
5946 && ! (i.operands == 1
5947 && i.tm.base_opcode == 0xfc7
5948 && i.tm.extension_opcode == 1
5949 && !operand_type_check (i.types [0], reg)
5950 && operand_type_check (i.types [0], anymem)))
5951 i.rex |= REX_W;
5952 }
5953
5954 /* Size floating point instruction. */
5955 if (i.suffix == LONG_MNEM_SUFFIX)
5956 if (i.tm.opcode_modifier.floatmf)
5957 i.tm.base_opcode ^= 4;
5958 }
5959
5960 return 1;
5961 }
5962
5963 static int
5964 check_byte_reg (void)
5965 {
5966 int op;
5967
5968 for (op = i.operands; --op >= 0;)
5969 {
5970 /* Skip non-register operands. */
5971 if (!i.types[op].bitfield.reg)
5972 continue;
5973
5974 /* If this is an eight bit register, it's OK. If it's the 16 or
5975 32 bit version of an eight bit register, we will just use the
5976 low portion, and that's OK too. */
5977 if (i.types[op].bitfield.byte)
5978 continue;
5979
5980 /* I/O port address operands are OK too. */
5981 if (i.tm.operand_types[op].bitfield.inoutportreg)
5982 continue;
5983
5984 /* crc32 doesn't generate this warning. */
5985 if (i.tm.base_opcode == 0xf20f38f0)
5986 continue;
5987
5988 if ((i.types[op].bitfield.word
5989 || i.types[op].bitfield.dword
5990 || i.types[op].bitfield.qword)
5991 && i.op[op].regs->reg_num < 4
5992 /* Prohibit these changes in 64bit mode, since the lowering
5993 would be more complicated. */
5994 && flag_code != CODE_64BIT)
5995 {
5996 #if REGISTER_WARNINGS
5997 if (!quiet_warnings)
5998 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5999 register_prefix,
6000 (i.op[op].regs + (i.types[op].bitfield.word
6001 ? REGNAM_AL - REGNAM_AX
6002 : REGNAM_AL - REGNAM_EAX))->reg_name,
6003 register_prefix,
6004 i.op[op].regs->reg_name,
6005 i.suffix);
6006 #endif
6007 continue;
6008 }
6009 /* Any other register is bad. */
6010 if (i.types[op].bitfield.reg
6011 || i.types[op].bitfield.regmmx
6012 || i.types[op].bitfield.regsimd
6013 || i.types[op].bitfield.sreg2
6014 || i.types[op].bitfield.sreg3
6015 || i.types[op].bitfield.control
6016 || i.types[op].bitfield.debug
6017 || i.types[op].bitfield.test)
6018 {
6019 as_bad (_("`%s%s' not allowed with `%s%c'"),
6020 register_prefix,
6021 i.op[op].regs->reg_name,
6022 i.tm.name,
6023 i.suffix);
6024 return 0;
6025 }
6026 }
6027 return 1;
6028 }
6029
6030 static int
6031 check_long_reg (void)
6032 {
6033 int op;
6034
6035 for (op = i.operands; --op >= 0;)
6036 /* Skip non-register operands. */
6037 if (!i.types[op].bitfield.reg)
6038 continue;
6039 /* Reject eight bit registers, except where the template requires
6040 them. (eg. movzb) */
6041 else if (i.types[op].bitfield.byte
6042 && (i.tm.operand_types[op].bitfield.reg
6043 || i.tm.operand_types[op].bitfield.acc)
6044 && (i.tm.operand_types[op].bitfield.word
6045 || i.tm.operand_types[op].bitfield.dword))
6046 {
6047 as_bad (_("`%s%s' not allowed with `%s%c'"),
6048 register_prefix,
6049 i.op[op].regs->reg_name,
6050 i.tm.name,
6051 i.suffix);
6052 return 0;
6053 }
6054 /* Warn if the e prefix on a general reg is missing. */
6055 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6056 && i.types[op].bitfield.word
6057 && (i.tm.operand_types[op].bitfield.reg
6058 || i.tm.operand_types[op].bitfield.acc)
6059 && i.tm.operand_types[op].bitfield.dword)
6060 {
6061 /* Prohibit these changes in the 64bit mode, since the
6062 lowering is more complicated. */
6063 if (flag_code == CODE_64BIT)
6064 {
6065 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6066 register_prefix, i.op[op].regs->reg_name,
6067 i.suffix);
6068 return 0;
6069 }
6070 #if REGISTER_WARNINGS
6071 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6072 register_prefix,
6073 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6074 register_prefix, i.op[op].regs->reg_name, i.suffix);
6075 #endif
6076 }
6077 /* Warn if the r prefix on a general reg is present. */
6078 else if (i.types[op].bitfield.qword
6079 && (i.tm.operand_types[op].bitfield.reg
6080 || i.tm.operand_types[op].bitfield.acc)
6081 && i.tm.operand_types[op].bitfield.dword)
6082 {
6083 if (intel_syntax
6084 && i.tm.opcode_modifier.toqword
6085 && !i.types[0].bitfield.regsimd)
6086 {
6087 /* Convert to QWORD. We want REX byte. */
6088 i.suffix = QWORD_MNEM_SUFFIX;
6089 }
6090 else
6091 {
6092 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6093 register_prefix, i.op[op].regs->reg_name,
6094 i.suffix);
6095 return 0;
6096 }
6097 }
6098 return 1;
6099 }
6100
6101 static int
6102 check_qword_reg (void)
6103 {
6104 int op;
6105
6106 for (op = i.operands; --op >= 0; )
6107 /* Skip non-register operands. */
6108 if (!i.types[op].bitfield.reg)
6109 continue;
6110 /* Reject eight bit registers, except where the template requires
6111 them. (eg. movzb) */
6112 else if (i.types[op].bitfield.byte
6113 && (i.tm.operand_types[op].bitfield.reg
6114 || i.tm.operand_types[op].bitfield.acc)
6115 && (i.tm.operand_types[op].bitfield.word
6116 || i.tm.operand_types[op].bitfield.dword))
6117 {
6118 as_bad (_("`%s%s' not allowed with `%s%c'"),
6119 register_prefix,
6120 i.op[op].regs->reg_name,
6121 i.tm.name,
6122 i.suffix);
6123 return 0;
6124 }
6125 /* Warn if the r prefix on a general reg is missing. */
6126 else if ((i.types[op].bitfield.word
6127 || i.types[op].bitfield.dword)
6128 && (i.tm.operand_types[op].bitfield.reg
6129 || i.tm.operand_types[op].bitfield.acc)
6130 && i.tm.operand_types[op].bitfield.qword)
6131 {
6132 /* Prohibit these changes in the 64bit mode, since the
6133 lowering is more complicated. */
6134 if (intel_syntax
6135 && i.tm.opcode_modifier.todword
6136 && !i.types[0].bitfield.regsimd)
6137 {
6138 /* Convert to DWORD. We don't want REX byte. */
6139 i.suffix = LONG_MNEM_SUFFIX;
6140 }
6141 else
6142 {
6143 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6144 register_prefix, i.op[op].regs->reg_name,
6145 i.suffix);
6146 return 0;
6147 }
6148 }
6149 return 1;
6150 }
6151
6152 static int
6153 check_word_reg (void)
6154 {
6155 int op;
6156 for (op = i.operands; --op >= 0;)
6157 /* Skip non-register operands. */
6158 if (!i.types[op].bitfield.reg)
6159 continue;
6160 /* Reject eight bit registers, except where the template requires
6161 them. (eg. movzb) */
6162 else if (i.types[op].bitfield.byte
6163 && (i.tm.operand_types[op].bitfield.reg
6164 || i.tm.operand_types[op].bitfield.acc)
6165 && (i.tm.operand_types[op].bitfield.word
6166 || i.tm.operand_types[op].bitfield.dword))
6167 {
6168 as_bad (_("`%s%s' not allowed with `%s%c'"),
6169 register_prefix,
6170 i.op[op].regs->reg_name,
6171 i.tm.name,
6172 i.suffix);
6173 return 0;
6174 }
6175 /* Warn if the e or r prefix on a general reg is present. */
6176 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6177 && (i.types[op].bitfield.dword
6178 || i.types[op].bitfield.qword)
6179 && (i.tm.operand_types[op].bitfield.reg
6180 || i.tm.operand_types[op].bitfield.acc)
6181 && i.tm.operand_types[op].bitfield.word)
6182 {
6183 /* Prohibit these changes in the 64bit mode, since the
6184 lowering is more complicated. */
6185 if (flag_code == CODE_64BIT)
6186 {
6187 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6188 register_prefix, i.op[op].regs->reg_name,
6189 i.suffix);
6190 return 0;
6191 }
6192 #if REGISTER_WARNINGS
6193 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6194 register_prefix,
6195 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6196 register_prefix, i.op[op].regs->reg_name, i.suffix);
6197 #endif
6198 }
6199 return 1;
6200 }
6201
6202 static int
6203 update_imm (unsigned int j)
6204 {
6205 i386_operand_type overlap = i.types[j];
6206 if ((overlap.bitfield.imm8
6207 || overlap.bitfield.imm8s
6208 || overlap.bitfield.imm16
6209 || overlap.bitfield.imm32
6210 || overlap.bitfield.imm32s
6211 || overlap.bitfield.imm64)
6212 && !operand_type_equal (&overlap, &imm8)
6213 && !operand_type_equal (&overlap, &imm8s)
6214 && !operand_type_equal (&overlap, &imm16)
6215 && !operand_type_equal (&overlap, &imm32)
6216 && !operand_type_equal (&overlap, &imm32s)
6217 && !operand_type_equal (&overlap, &imm64))
6218 {
6219 if (i.suffix)
6220 {
6221 i386_operand_type temp;
6222
6223 operand_type_set (&temp, 0);
6224 if (i.suffix == BYTE_MNEM_SUFFIX)
6225 {
6226 temp.bitfield.imm8 = overlap.bitfield.imm8;
6227 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6228 }
6229 else if (i.suffix == WORD_MNEM_SUFFIX)
6230 temp.bitfield.imm16 = overlap.bitfield.imm16;
6231 else if (i.suffix == QWORD_MNEM_SUFFIX)
6232 {
6233 temp.bitfield.imm64 = overlap.bitfield.imm64;
6234 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6235 }
6236 else
6237 temp.bitfield.imm32 = overlap.bitfield.imm32;
6238 overlap = temp;
6239 }
6240 else if (operand_type_equal (&overlap, &imm16_32_32s)
6241 || operand_type_equal (&overlap, &imm16_32)
6242 || operand_type_equal (&overlap, &imm16_32s))
6243 {
6244 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6245 overlap = imm16;
6246 else
6247 overlap = imm32s;
6248 }
6249 if (!operand_type_equal (&overlap, &imm8)
6250 && !operand_type_equal (&overlap, &imm8s)
6251 && !operand_type_equal (&overlap, &imm16)
6252 && !operand_type_equal (&overlap, &imm32)
6253 && !operand_type_equal (&overlap, &imm32s)
6254 && !operand_type_equal (&overlap, &imm64))
6255 {
6256 as_bad (_("no instruction mnemonic suffix given; "
6257 "can't determine immediate size"));
6258 return 0;
6259 }
6260 }
6261 i.types[j] = overlap;
6262
6263 return 1;
6264 }
6265
6266 static int
6267 finalize_imm (void)
6268 {
6269 unsigned int j, n;
6270
6271 /* Update the first 2 immediate operands. */
6272 n = i.operands > 2 ? 2 : i.operands;
6273 if (n)
6274 {
6275 for (j = 0; j < n; j++)
6276 if (update_imm (j) == 0)
6277 return 0;
6278
6279 /* The 3rd operand can't be immediate operand. */
6280 gas_assert (operand_type_check (i.types[2], imm) == 0);
6281 }
6282
6283 return 1;
6284 }
6285
6286 static int
6287 process_operands (void)
6288 {
6289 /* Default segment register this instruction will use for memory
6290 accesses. 0 means unknown. This is only for optimizing out
6291 unnecessary segment overrides. */
6292 const seg_entry *default_seg = 0;
6293
6294 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6295 {
6296 unsigned int dupl = i.operands;
6297 unsigned int dest = dupl - 1;
6298 unsigned int j;
6299
6300 /* The destination must be an xmm register. */
6301 gas_assert (i.reg_operands
6302 && MAX_OPERANDS > dupl
6303 && operand_type_equal (&i.types[dest], &regxmm));
6304
6305 if (i.tm.operand_types[0].bitfield.acc
6306 && i.tm.operand_types[0].bitfield.xmmword)
6307 {
6308 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6309 {
6310 /* Keep xmm0 for instructions with VEX prefix and 3
6311 sources. */
6312 i.tm.operand_types[0].bitfield.acc = 0;
6313 i.tm.operand_types[0].bitfield.regsimd = 1;
6314 goto duplicate;
6315 }
6316 else
6317 {
6318 /* We remove the first xmm0 and keep the number of
6319 operands unchanged, which in fact duplicates the
6320 destination. */
6321 for (j = 1; j < i.operands; j++)
6322 {
6323 i.op[j - 1] = i.op[j];
6324 i.types[j - 1] = i.types[j];
6325 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6326 }
6327 }
6328 }
6329 else if (i.tm.opcode_modifier.implicit1stxmm0)
6330 {
6331 gas_assert ((MAX_OPERANDS - 1) > dupl
6332 && (i.tm.opcode_modifier.vexsources
6333 == VEX3SOURCES));
6334
6335 /* Add the implicit xmm0 for instructions with VEX prefix
6336 and 3 sources. */
6337 for (j = i.operands; j > 0; j--)
6338 {
6339 i.op[j] = i.op[j - 1];
6340 i.types[j] = i.types[j - 1];
6341 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6342 }
6343 i.op[0].regs
6344 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6345 i.types[0] = regxmm;
6346 i.tm.operand_types[0] = regxmm;
6347
6348 i.operands += 2;
6349 i.reg_operands += 2;
6350 i.tm.operands += 2;
6351
6352 dupl++;
6353 dest++;
6354 i.op[dupl] = i.op[dest];
6355 i.types[dupl] = i.types[dest];
6356 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6357 }
6358 else
6359 {
6360 duplicate:
6361 i.operands++;
6362 i.reg_operands++;
6363 i.tm.operands++;
6364
6365 i.op[dupl] = i.op[dest];
6366 i.types[dupl] = i.types[dest];
6367 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6368 }
6369
6370 if (i.tm.opcode_modifier.immext)
6371 process_immext ();
6372 }
6373 else if (i.tm.operand_types[0].bitfield.acc
6374 && i.tm.operand_types[0].bitfield.xmmword)
6375 {
6376 unsigned int j;
6377
6378 for (j = 1; j < i.operands; j++)
6379 {
6380 i.op[j - 1] = i.op[j];
6381 i.types[j - 1] = i.types[j];
6382
6383 /* We need to adjust fields in i.tm since they are used by
6384 build_modrm_byte. */
6385 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6386 }
6387
6388 i.operands--;
6389 i.reg_operands--;
6390 i.tm.operands--;
6391 }
6392 else if (i.tm.opcode_modifier.implicitquadgroup)
6393 {
6394 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6395
6396 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6397 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6398 regnum = register_number (i.op[1].regs);
6399 first_reg_in_group = regnum & ~3;
6400 last_reg_in_group = first_reg_in_group + 3;
6401 if (regnum != first_reg_in_group)
6402 as_warn (_("source register `%s%s' implicitly denotes"
6403 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6404 register_prefix, i.op[1].regs->reg_name,
6405 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6406 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6407 i.tm.name);
6408 }
6409 else if (i.tm.opcode_modifier.regkludge)
6410 {
6411 /* The imul $imm, %reg instruction is converted into
6412 imul $imm, %reg, %reg, and the clr %reg instruction
6413 is converted into xor %reg, %reg. */
6414
6415 unsigned int first_reg_op;
6416
6417 if (operand_type_check (i.types[0], reg))
6418 first_reg_op = 0;
6419 else
6420 first_reg_op = 1;
6421 /* Pretend we saw the extra register operand. */
6422 gas_assert (i.reg_operands == 1
6423 && i.op[first_reg_op + 1].regs == 0);
6424 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6425 i.types[first_reg_op + 1] = i.types[first_reg_op];
6426 i.operands++;
6427 i.reg_operands++;
6428 }
6429
6430 if (i.tm.opcode_modifier.shortform)
6431 {
6432 if (i.types[0].bitfield.sreg2
6433 || i.types[0].bitfield.sreg3)
6434 {
6435 if (i.tm.base_opcode == POP_SEG_SHORT
6436 && i.op[0].regs->reg_num == 1)
6437 {
6438 as_bad (_("you can't `pop %scs'"), register_prefix);
6439 return 0;
6440 }
6441 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6442 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6443 i.rex |= REX_B;
6444 }
6445 else
6446 {
6447 /* The register or float register operand is in operand
6448 0 or 1. */
6449 unsigned int op;
6450
6451 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6452 || operand_type_check (i.types[0], reg))
6453 op = 0;
6454 else
6455 op = 1;
6456 /* Register goes in low 3 bits of opcode. */
6457 i.tm.base_opcode |= i.op[op].regs->reg_num;
6458 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6459 i.rex |= REX_B;
6460 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6461 {
6462 /* Warn about some common errors, but press on regardless.
6463 The first case can be generated by gcc (<= 2.8.1). */
6464 if (i.operands == 2)
6465 {
6466 /* Reversed arguments on faddp, fsubp, etc. */
6467 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6468 register_prefix, i.op[!intel_syntax].regs->reg_name,
6469 register_prefix, i.op[intel_syntax].regs->reg_name);
6470 }
6471 else
6472 {
6473 /* Extraneous `l' suffix on fp insn. */
6474 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6475 register_prefix, i.op[0].regs->reg_name);
6476 }
6477 }
6478 }
6479 }
6480 else if (i.tm.opcode_modifier.modrm)
6481 {
6482 /* The opcode is completed (modulo i.tm.extension_opcode which
6483 must be put into the modrm byte). Now, we make the modrm and
6484 index base bytes based on all the info we've collected. */
6485
6486 default_seg = build_modrm_byte ();
6487 }
6488 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6489 {
6490 default_seg = &ds;
6491 }
6492 else if (i.tm.opcode_modifier.isstring)
6493 {
6494 /* For the string instructions that allow a segment override
6495 on one of their operands, the default segment is ds. */
6496 default_seg = &ds;
6497 }
6498
6499 if (i.tm.base_opcode == 0x8d /* lea */
6500 && i.seg[0]
6501 && !quiet_warnings)
6502 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6503
6504 /* If a segment was explicitly specified, and the specified segment
6505 is not the default, use an opcode prefix to select it. If we
6506 never figured out what the default segment is, then default_seg
6507 will be zero at this point, and the specified segment prefix will
6508 always be used. */
6509 if ((i.seg[0]) && (i.seg[0] != default_seg))
6510 {
6511 if (!add_prefix (i.seg[0]->seg_prefix))
6512 return 0;
6513 }
6514 return 1;
6515 }
6516
6517 static const seg_entry *
6518 build_modrm_byte (void)
6519 {
6520 const seg_entry *default_seg = 0;
6521 unsigned int source, dest;
6522 int vex_3_sources;
6523
6524 /* The first operand of instructions with VEX prefix and 3 sources
6525 must be VEX_Imm4. */
6526 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6527 if (vex_3_sources)
6528 {
6529 unsigned int nds, reg_slot;
6530 expressionS *exp;
6531
6532 if (i.tm.opcode_modifier.veximmext
6533 && i.tm.opcode_modifier.immext)
6534 {
6535 dest = i.operands - 2;
6536 gas_assert (dest == 3);
6537 }
6538 else
6539 dest = i.operands - 1;
6540 nds = dest - 1;
6541
6542 /* There are 2 kinds of instructions:
6543 1. 5 operands: 4 register operands or 3 register operands
6544 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6545 VexW0 or VexW1. The destination must be either XMM, YMM or
6546 ZMM register.
6547 2. 4 operands: 4 register operands or 3 register operands
6548 plus 1 memory operand, VexXDS, and VexImmExt */
6549 gas_assert ((i.reg_operands == 4
6550 || (i.reg_operands == 3 && i.mem_operands == 1))
6551 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6552 && (i.tm.opcode_modifier.veximmext
6553 || (i.imm_operands == 1
6554 && i.types[0].bitfield.vec_imm4
6555 && (i.tm.opcode_modifier.vexw == VEXW0
6556 || i.tm.opcode_modifier.vexw == VEXW1)
6557 && i.tm.operand_types[dest].bitfield.regsimd)));
6558
6559 if (i.imm_operands == 0)
6560 {
6561 /* When there is no immediate operand, generate an 8bit
6562 immediate operand to encode the first operand. */
6563 exp = &im_expressions[i.imm_operands++];
6564 i.op[i.operands].imms = exp;
6565 i.types[i.operands] = imm8;
6566 i.operands++;
6567 /* If VexW1 is set, the first operand is the source and
6568 the second operand is encoded in the immediate operand. */
6569 if (i.tm.opcode_modifier.vexw == VEXW1)
6570 {
6571 source = 0;
6572 reg_slot = 1;
6573 }
6574 else
6575 {
6576 source = 1;
6577 reg_slot = 0;
6578 }
6579
6580 /* FMA swaps REG and NDS. */
6581 if (i.tm.cpu_flags.bitfield.cpufma)
6582 {
6583 unsigned int tmp;
6584 tmp = reg_slot;
6585 reg_slot = nds;
6586 nds = tmp;
6587 }
6588
6589 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6590 exp->X_op = O_constant;
6591 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6592 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6593 }
6594 else
6595 {
6596 unsigned int imm_slot;
6597
6598 if (i.tm.opcode_modifier.vexw == VEXW0)
6599 {
6600 /* If VexW0 is set, the third operand is the source and
6601 the second operand is encoded in the immediate
6602 operand. */
6603 source = 2;
6604 reg_slot = 1;
6605 }
6606 else
6607 {
6608 /* VexW1 is set, the second operand is the source and
6609 the third operand is encoded in the immediate
6610 operand. */
6611 source = 1;
6612 reg_slot = 2;
6613 }
6614
6615 if (i.tm.opcode_modifier.immext)
6616 {
6617 /* When ImmExt is set, the immediate byte is the last
6618 operand. */
6619 imm_slot = i.operands - 1;
6620 source--;
6621 reg_slot--;
6622 }
6623 else
6624 {
6625 imm_slot = 0;
6626
6627 /* Turn on Imm8 so that output_imm will generate it. */
6628 i.types[imm_slot].bitfield.imm8 = 1;
6629 }
6630
6631 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6632 i.op[imm_slot].imms->X_add_number
6633 |= register_number (i.op[reg_slot].regs) << 4;
6634 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6635 }
6636
6637 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6638 i.vex.register_specifier = i.op[nds].regs;
6639 }
6640 else
6641 source = dest = 0;
6642
6643 /* i.reg_operands MUST be the number of real register operands;
6644 implicit registers do not count. If there are 3 register
6645 operands, it must be a instruction with VexNDS. For a
6646 instruction with VexNDD, the destination register is encoded
6647 in VEX prefix. If there are 4 register operands, it must be
6648 a instruction with VEX prefix and 3 sources. */
6649 if (i.mem_operands == 0
6650 && ((i.reg_operands == 2
6651 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6652 || (i.reg_operands == 3
6653 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6654 || (i.reg_operands == 4 && vex_3_sources)))
6655 {
6656 switch (i.operands)
6657 {
6658 case 2:
6659 source = 0;
6660 break;
6661 case 3:
6662 /* When there are 3 operands, one of them may be immediate,
6663 which may be the first or the last operand. Otherwise,
6664 the first operand must be shift count register (cl) or it
6665 is an instruction with VexNDS. */
6666 gas_assert (i.imm_operands == 1
6667 || (i.imm_operands == 0
6668 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6669 || i.types[0].bitfield.shiftcount)));
6670 if (operand_type_check (i.types[0], imm)
6671 || i.types[0].bitfield.shiftcount)
6672 source = 1;
6673 else
6674 source = 0;
6675 break;
6676 case 4:
6677 /* When there are 4 operands, the first two must be 8bit
6678 immediate operands. The source operand will be the 3rd
6679 one.
6680
6681 For instructions with VexNDS, if the first operand
6682 an imm8, the source operand is the 2nd one. If the last
6683 operand is imm8, the source operand is the first one. */
6684 gas_assert ((i.imm_operands == 2
6685 && i.types[0].bitfield.imm8
6686 && i.types[1].bitfield.imm8)
6687 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6688 && i.imm_operands == 1
6689 && (i.types[0].bitfield.imm8
6690 || i.types[i.operands - 1].bitfield.imm8
6691 || i.rounding)));
6692 if (i.imm_operands == 2)
6693 source = 2;
6694 else
6695 {
6696 if (i.types[0].bitfield.imm8)
6697 source = 1;
6698 else
6699 source = 0;
6700 }
6701 break;
6702 case 5:
6703 if (i.tm.opcode_modifier.evex)
6704 {
6705 /* For EVEX instructions, when there are 5 operands, the
6706 first one must be immediate operand. If the second one
6707 is immediate operand, the source operand is the 3th
6708 one. If the last one is immediate operand, the source
6709 operand is the 2nd one. */
6710 gas_assert (i.imm_operands == 2
6711 && i.tm.opcode_modifier.sae
6712 && operand_type_check (i.types[0], imm));
6713 if (operand_type_check (i.types[1], imm))
6714 source = 2;
6715 else if (operand_type_check (i.types[4], imm))
6716 source = 1;
6717 else
6718 abort ();
6719 }
6720 break;
6721 default:
6722 abort ();
6723 }
6724
6725 if (!vex_3_sources)
6726 {
6727 dest = source + 1;
6728
6729 /* RC/SAE operand could be between DEST and SRC. That happens
6730 when one operand is GPR and the other one is XMM/YMM/ZMM
6731 register. */
6732 if (i.rounding && i.rounding->operand == (int) dest)
6733 dest++;
6734
6735 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6736 {
6737 /* For instructions with VexNDS, the register-only source
6738 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6739 register. It is encoded in VEX prefix. We need to
6740 clear RegMem bit before calling operand_type_equal. */
6741
6742 i386_operand_type op;
6743 unsigned int vvvv;
6744
6745 /* Check register-only source operand when two source
6746 operands are swapped. */
6747 if (!i.tm.operand_types[source].bitfield.baseindex
6748 && i.tm.operand_types[dest].bitfield.baseindex)
6749 {
6750 vvvv = source;
6751 source = dest;
6752 }
6753 else
6754 vvvv = dest;
6755
6756 op = i.tm.operand_types[vvvv];
6757 op.bitfield.regmem = 0;
6758 if ((dest + 1) >= i.operands
6759 || ((!op.bitfield.reg
6760 || (!op.bitfield.dword && !op.bitfield.qword))
6761 && !op.bitfield.regsimd
6762 && !operand_type_equal (&op, &regmask)))
6763 abort ();
6764 i.vex.register_specifier = i.op[vvvv].regs;
6765 dest++;
6766 }
6767 }
6768
6769 i.rm.mode = 3;
6770 /* One of the register operands will be encoded in the i.tm.reg
6771 field, the other in the combined i.tm.mode and i.tm.regmem
6772 fields. If no form of this instruction supports a memory
6773 destination operand, then we assume the source operand may
6774 sometimes be a memory operand and so we need to store the
6775 destination in the i.rm.reg field. */
6776 if (!i.tm.operand_types[dest].bitfield.regmem
6777 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6778 {
6779 i.rm.reg = i.op[dest].regs->reg_num;
6780 i.rm.regmem = i.op[source].regs->reg_num;
6781 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6782 i.rex |= REX_R;
6783 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6784 i.vrex |= REX_R;
6785 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6786 i.rex |= REX_B;
6787 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6788 i.vrex |= REX_B;
6789 }
6790 else
6791 {
6792 i.rm.reg = i.op[source].regs->reg_num;
6793 i.rm.regmem = i.op[dest].regs->reg_num;
6794 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6795 i.rex |= REX_B;
6796 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6797 i.vrex |= REX_B;
6798 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6799 i.rex |= REX_R;
6800 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6801 i.vrex |= REX_R;
6802 }
6803 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6804 {
6805 if (!i.types[0].bitfield.control
6806 && !i.types[1].bitfield.control)
6807 abort ();
6808 i.rex &= ~(REX_R | REX_B);
6809 add_prefix (LOCK_PREFIX_OPCODE);
6810 }
6811 }
6812 else
6813 { /* If it's not 2 reg operands... */
6814 unsigned int mem;
6815
6816 if (i.mem_operands)
6817 {
6818 unsigned int fake_zero_displacement = 0;
6819 unsigned int op;
6820
6821 for (op = 0; op < i.operands; op++)
6822 if (operand_type_check (i.types[op], anymem))
6823 break;
6824 gas_assert (op < i.operands);
6825
6826 if (i.tm.opcode_modifier.vecsib)
6827 {
6828 if (i.index_reg->reg_num == RegEiz
6829 || i.index_reg->reg_num == RegRiz)
6830 abort ();
6831
6832 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6833 if (!i.base_reg)
6834 {
6835 i.sib.base = NO_BASE_REGISTER;
6836 i.sib.scale = i.log2_scale_factor;
6837 i.types[op].bitfield.disp8 = 0;
6838 i.types[op].bitfield.disp16 = 0;
6839 i.types[op].bitfield.disp64 = 0;
6840 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6841 {
6842 /* Must be 32 bit */
6843 i.types[op].bitfield.disp32 = 1;
6844 i.types[op].bitfield.disp32s = 0;
6845 }
6846 else
6847 {
6848 i.types[op].bitfield.disp32 = 0;
6849 i.types[op].bitfield.disp32s = 1;
6850 }
6851 }
6852 i.sib.index = i.index_reg->reg_num;
6853 if ((i.index_reg->reg_flags & RegRex) != 0)
6854 i.rex |= REX_X;
6855 if ((i.index_reg->reg_flags & RegVRex) != 0)
6856 i.vrex |= REX_X;
6857 }
6858
6859 default_seg = &ds;
6860
6861 if (i.base_reg == 0)
6862 {
6863 i.rm.mode = 0;
6864 if (!i.disp_operands)
6865 fake_zero_displacement = 1;
6866 if (i.index_reg == 0)
6867 {
6868 i386_operand_type newdisp;
6869
6870 gas_assert (!i.tm.opcode_modifier.vecsib);
6871 /* Operand is just <disp> */
6872 if (flag_code == CODE_64BIT)
6873 {
6874 /* 64bit mode overwrites the 32bit absolute
6875 addressing by RIP relative addressing and
6876 absolute addressing is encoded by one of the
6877 redundant SIB forms. */
6878 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6879 i.sib.base = NO_BASE_REGISTER;
6880 i.sib.index = NO_INDEX_REGISTER;
6881 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
6882 }
6883 else if ((flag_code == CODE_16BIT)
6884 ^ (i.prefix[ADDR_PREFIX] != 0))
6885 {
6886 i.rm.regmem = NO_BASE_REGISTER_16;
6887 newdisp = disp16;
6888 }
6889 else
6890 {
6891 i.rm.regmem = NO_BASE_REGISTER;
6892 newdisp = disp32;
6893 }
6894 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6895 i.types[op] = operand_type_or (i.types[op], newdisp);
6896 }
6897 else if (!i.tm.opcode_modifier.vecsib)
6898 {
6899 /* !i.base_reg && i.index_reg */
6900 if (i.index_reg->reg_num == RegEiz
6901 || i.index_reg->reg_num == RegRiz)
6902 i.sib.index = NO_INDEX_REGISTER;
6903 else
6904 i.sib.index = i.index_reg->reg_num;
6905 i.sib.base = NO_BASE_REGISTER;
6906 i.sib.scale = i.log2_scale_factor;
6907 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6908 i.types[op].bitfield.disp8 = 0;
6909 i.types[op].bitfield.disp16 = 0;
6910 i.types[op].bitfield.disp64 = 0;
6911 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6912 {
6913 /* Must be 32 bit */
6914 i.types[op].bitfield.disp32 = 1;
6915 i.types[op].bitfield.disp32s = 0;
6916 }
6917 else
6918 {
6919 i.types[op].bitfield.disp32 = 0;
6920 i.types[op].bitfield.disp32s = 1;
6921 }
6922 if ((i.index_reg->reg_flags & RegRex) != 0)
6923 i.rex |= REX_X;
6924 }
6925 }
6926 /* RIP addressing for 64bit mode. */
6927 else if (i.base_reg->reg_num == RegRip ||
6928 i.base_reg->reg_num == RegEip)
6929 {
6930 gas_assert (!i.tm.opcode_modifier.vecsib);
6931 i.rm.regmem = NO_BASE_REGISTER;
6932 i.types[op].bitfield.disp8 = 0;
6933 i.types[op].bitfield.disp16 = 0;
6934 i.types[op].bitfield.disp32 = 0;
6935 i.types[op].bitfield.disp32s = 1;
6936 i.types[op].bitfield.disp64 = 0;
6937 i.flags[op] |= Operand_PCrel;
6938 if (! i.disp_operands)
6939 fake_zero_displacement = 1;
6940 }
6941 else if (i.base_reg->reg_type.bitfield.word)
6942 {
6943 gas_assert (!i.tm.opcode_modifier.vecsib);
6944 switch (i.base_reg->reg_num)
6945 {
6946 case 3: /* (%bx) */
6947 if (i.index_reg == 0)
6948 i.rm.regmem = 7;
6949 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6950 i.rm.regmem = i.index_reg->reg_num - 6;
6951 break;
6952 case 5: /* (%bp) */
6953 default_seg = &ss;
6954 if (i.index_reg == 0)
6955 {
6956 i.rm.regmem = 6;
6957 if (operand_type_check (i.types[op], disp) == 0)
6958 {
6959 /* fake (%bp) into 0(%bp) */
6960 i.types[op].bitfield.disp8 = 1;
6961 fake_zero_displacement = 1;
6962 }
6963 }
6964 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6965 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6966 break;
6967 default: /* (%si) -> 4 or (%di) -> 5 */
6968 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6969 }
6970 i.rm.mode = mode_from_disp_size (i.types[op]);
6971 }
6972 else /* i.base_reg and 32/64 bit mode */
6973 {
6974 if (flag_code == CODE_64BIT
6975 && operand_type_check (i.types[op], disp))
6976 {
6977 i.types[op].bitfield.disp16 = 0;
6978 i.types[op].bitfield.disp64 = 0;
6979 if (i.prefix[ADDR_PREFIX] == 0)
6980 {
6981 i.types[op].bitfield.disp32 = 0;
6982 i.types[op].bitfield.disp32s = 1;
6983 }
6984 else
6985 {
6986 i.types[op].bitfield.disp32 = 1;
6987 i.types[op].bitfield.disp32s = 0;
6988 }
6989 }
6990
6991 if (!i.tm.opcode_modifier.vecsib)
6992 i.rm.regmem = i.base_reg->reg_num;
6993 if ((i.base_reg->reg_flags & RegRex) != 0)
6994 i.rex |= REX_B;
6995 i.sib.base = i.base_reg->reg_num;
6996 /* x86-64 ignores REX prefix bit here to avoid decoder
6997 complications. */
6998 if (!(i.base_reg->reg_flags & RegRex)
6999 && (i.base_reg->reg_num == EBP_REG_NUM
7000 || i.base_reg->reg_num == ESP_REG_NUM))
7001 default_seg = &ss;
7002 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7003 {
7004 fake_zero_displacement = 1;
7005 i.types[op].bitfield.disp8 = 1;
7006 }
7007 i.sib.scale = i.log2_scale_factor;
7008 if (i.index_reg == 0)
7009 {
7010 gas_assert (!i.tm.opcode_modifier.vecsib);
7011 /* <disp>(%esp) becomes two byte modrm with no index
7012 register. We've already stored the code for esp
7013 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7014 Any base register besides %esp will not use the
7015 extra modrm byte. */
7016 i.sib.index = NO_INDEX_REGISTER;
7017 }
7018 else if (!i.tm.opcode_modifier.vecsib)
7019 {
7020 if (i.index_reg->reg_num == RegEiz
7021 || i.index_reg->reg_num == RegRiz)
7022 i.sib.index = NO_INDEX_REGISTER;
7023 else
7024 i.sib.index = i.index_reg->reg_num;
7025 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7026 if ((i.index_reg->reg_flags & RegRex) != 0)
7027 i.rex |= REX_X;
7028 }
7029
7030 if (i.disp_operands
7031 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7032 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7033 i.rm.mode = 0;
7034 else
7035 {
7036 if (!fake_zero_displacement
7037 && !i.disp_operands
7038 && i.disp_encoding)
7039 {
7040 fake_zero_displacement = 1;
7041 if (i.disp_encoding == disp_encoding_8bit)
7042 i.types[op].bitfield.disp8 = 1;
7043 else
7044 i.types[op].bitfield.disp32 = 1;
7045 }
7046 i.rm.mode = mode_from_disp_size (i.types[op]);
7047 }
7048 }
7049
7050 if (fake_zero_displacement)
7051 {
7052 /* Fakes a zero displacement assuming that i.types[op]
7053 holds the correct displacement size. */
7054 expressionS *exp;
7055
7056 gas_assert (i.op[op].disps == 0);
7057 exp = &disp_expressions[i.disp_operands++];
7058 i.op[op].disps = exp;
7059 exp->X_op = O_constant;
7060 exp->X_add_number = 0;
7061 exp->X_add_symbol = (symbolS *) 0;
7062 exp->X_op_symbol = (symbolS *) 0;
7063 }
7064
7065 mem = op;
7066 }
7067 else
7068 mem = ~0;
7069
7070 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7071 {
7072 if (operand_type_check (i.types[0], imm))
7073 i.vex.register_specifier = NULL;
7074 else
7075 {
7076 /* VEX.vvvv encodes one of the sources when the first
7077 operand is not an immediate. */
7078 if (i.tm.opcode_modifier.vexw == VEXW0)
7079 i.vex.register_specifier = i.op[0].regs;
7080 else
7081 i.vex.register_specifier = i.op[1].regs;
7082 }
7083
7084 /* Destination is a XMM register encoded in the ModRM.reg
7085 and VEX.R bit. */
7086 i.rm.reg = i.op[2].regs->reg_num;
7087 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7088 i.rex |= REX_R;
7089
7090 /* ModRM.rm and VEX.B encodes the other source. */
7091 if (!i.mem_operands)
7092 {
7093 i.rm.mode = 3;
7094
7095 if (i.tm.opcode_modifier.vexw == VEXW0)
7096 i.rm.regmem = i.op[1].regs->reg_num;
7097 else
7098 i.rm.regmem = i.op[0].regs->reg_num;
7099
7100 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7101 i.rex |= REX_B;
7102 }
7103 }
7104 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7105 {
7106 i.vex.register_specifier = i.op[2].regs;
7107 if (!i.mem_operands)
7108 {
7109 i.rm.mode = 3;
7110 i.rm.regmem = i.op[1].regs->reg_num;
7111 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7112 i.rex |= REX_B;
7113 }
7114 }
7115 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7116 (if any) based on i.tm.extension_opcode. Again, we must be
7117 careful to make sure that segment/control/debug/test/MMX
7118 registers are coded into the i.rm.reg field. */
7119 else if (i.reg_operands)
7120 {
7121 unsigned int op;
7122 unsigned int vex_reg = ~0;
7123
7124 for (op = 0; op < i.operands; op++)
7125 if (i.types[op].bitfield.reg
7126 || i.types[op].bitfield.regmmx
7127 || i.types[op].bitfield.regsimd
7128 || i.types[op].bitfield.regbnd
7129 || i.types[op].bitfield.regmask
7130 || i.types[op].bitfield.sreg2
7131 || i.types[op].bitfield.sreg3
7132 || i.types[op].bitfield.control
7133 || i.types[op].bitfield.debug
7134 || i.types[op].bitfield.test)
7135 break;
7136
7137 if (vex_3_sources)
7138 op = dest;
7139 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7140 {
7141 /* For instructions with VexNDS, the register-only
7142 source operand is encoded in VEX prefix. */
7143 gas_assert (mem != (unsigned int) ~0);
7144
7145 if (op > mem)
7146 {
7147 vex_reg = op++;
7148 gas_assert (op < i.operands);
7149 }
7150 else
7151 {
7152 /* Check register-only source operand when two source
7153 operands are swapped. */
7154 if (!i.tm.operand_types[op].bitfield.baseindex
7155 && i.tm.operand_types[op + 1].bitfield.baseindex)
7156 {
7157 vex_reg = op;
7158 op += 2;
7159 gas_assert (mem == (vex_reg + 1)
7160 && op < i.operands);
7161 }
7162 else
7163 {
7164 vex_reg = op + 1;
7165 gas_assert (vex_reg < i.operands);
7166 }
7167 }
7168 }
7169 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7170 {
7171 /* For instructions with VexNDD, the register destination
7172 is encoded in VEX prefix. */
7173 if (i.mem_operands == 0)
7174 {
7175 /* There is no memory operand. */
7176 gas_assert ((op + 2) == i.operands);
7177 vex_reg = op + 1;
7178 }
7179 else
7180 {
7181 /* There are only 2 operands. */
7182 gas_assert (op < 2 && i.operands == 2);
7183 vex_reg = 1;
7184 }
7185 }
7186 else
7187 gas_assert (op < i.operands);
7188
7189 if (vex_reg != (unsigned int) ~0)
7190 {
7191 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7192
7193 if ((!type->bitfield.reg
7194 || (!type->bitfield.dword && !type->bitfield.qword))
7195 && !type->bitfield.regsimd
7196 && !operand_type_equal (type, &regmask))
7197 abort ();
7198
7199 i.vex.register_specifier = i.op[vex_reg].regs;
7200 }
7201
7202 /* Don't set OP operand twice. */
7203 if (vex_reg != op)
7204 {
7205 /* If there is an extension opcode to put here, the
7206 register number must be put into the regmem field. */
7207 if (i.tm.extension_opcode != None)
7208 {
7209 i.rm.regmem = i.op[op].regs->reg_num;
7210 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7211 i.rex |= REX_B;
7212 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7213 i.vrex |= REX_B;
7214 }
7215 else
7216 {
7217 i.rm.reg = i.op[op].regs->reg_num;
7218 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7219 i.rex |= REX_R;
7220 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7221 i.vrex |= REX_R;
7222 }
7223 }
7224
7225 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7226 must set it to 3 to indicate this is a register operand
7227 in the regmem field. */
7228 if (!i.mem_operands)
7229 i.rm.mode = 3;
7230 }
7231
7232 /* Fill in i.rm.reg field with extension opcode (if any). */
7233 if (i.tm.extension_opcode != None)
7234 i.rm.reg = i.tm.extension_opcode;
7235 }
7236 return default_seg;
7237 }
7238
7239 static void
7240 output_branch (void)
7241 {
7242 char *p;
7243 int size;
7244 int code16;
7245 int prefix;
7246 relax_substateT subtype;
7247 symbolS *sym;
7248 offsetT off;
7249
7250 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7251 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7252
7253 prefix = 0;
7254 if (i.prefix[DATA_PREFIX] != 0)
7255 {
7256 prefix = 1;
7257 i.prefixes -= 1;
7258 code16 ^= CODE16;
7259 }
7260 /* Pentium4 branch hints. */
7261 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7262 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7263 {
7264 prefix++;
7265 i.prefixes--;
7266 }
7267 if (i.prefix[REX_PREFIX] != 0)
7268 {
7269 prefix++;
7270 i.prefixes--;
7271 }
7272
7273 /* BND prefixed jump. */
7274 if (i.prefix[BND_PREFIX] != 0)
7275 {
7276 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7277 i.prefixes -= 1;
7278 }
7279
7280 if (i.prefixes != 0 && !intel_syntax)
7281 as_warn (_("skipping prefixes on this instruction"));
7282
7283 /* It's always a symbol; End frag & setup for relax.
7284 Make sure there is enough room in this frag for the largest
7285 instruction we may generate in md_convert_frag. This is 2
7286 bytes for the opcode and room for the prefix and largest
7287 displacement. */
7288 frag_grow (prefix + 2 + 4);
7289 /* Prefix and 1 opcode byte go in fr_fix. */
7290 p = frag_more (prefix + 1);
7291 if (i.prefix[DATA_PREFIX] != 0)
7292 *p++ = DATA_PREFIX_OPCODE;
7293 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7294 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7295 *p++ = i.prefix[SEG_PREFIX];
7296 if (i.prefix[REX_PREFIX] != 0)
7297 *p++ = i.prefix[REX_PREFIX];
7298 *p = i.tm.base_opcode;
7299
7300 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7301 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7302 else if (cpu_arch_flags.bitfield.cpui386)
7303 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7304 else
7305 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7306 subtype |= code16;
7307
7308 sym = i.op[0].disps->X_add_symbol;
7309 off = i.op[0].disps->X_add_number;
7310
7311 if (i.op[0].disps->X_op != O_constant
7312 && i.op[0].disps->X_op != O_symbol)
7313 {
7314 /* Handle complex expressions. */
7315 sym = make_expr_symbol (i.op[0].disps);
7316 off = 0;
7317 }
7318
7319 /* 1 possible extra opcode + 4 byte displacement go in var part.
7320 Pass reloc in fr_var. */
7321 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7322 }
7323
7324 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7325 /* Return TRUE iff PLT32 relocation should be used for branching to
7326 symbol S. */
7327
7328 static bfd_boolean
7329 need_plt32_p (symbolS *s)
7330 {
7331 /* PLT32 relocation is ELF only. */
7332 if (!IS_ELF)
7333 return FALSE;
7334
7335 /* Since there is no need to prepare for PLT branch on x86-64, we
7336 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7337 be used as a marker for 32-bit PC-relative branches. */
7338 if (!object_64bit)
7339 return FALSE;
7340
7341 /* Weak or undefined symbol need PLT32 relocation. */
7342 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7343 return TRUE;
7344
7345 /* Non-global symbol doesn't need PLT32 relocation. */
7346 if (! S_IS_EXTERNAL (s))
7347 return FALSE;
7348
7349 /* Other global symbols need PLT32 relocation. NB: Symbol with
7350 non-default visibilities are treated as normal global symbol
7351 so that PLT32 relocation can be used as a marker for 32-bit
7352 PC-relative branches. It is useful for linker relaxation. */
7353 return TRUE;
7354 }
7355 #endif
7356
7357 static void
7358 output_jump (void)
7359 {
7360 char *p;
7361 int size;
7362 fixS *fixP;
7363 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7364
7365 if (i.tm.opcode_modifier.jumpbyte)
7366 {
7367 /* This is a loop or jecxz type instruction. */
7368 size = 1;
7369 if (i.prefix[ADDR_PREFIX] != 0)
7370 {
7371 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7372 i.prefixes -= 1;
7373 }
7374 /* Pentium4 branch hints. */
7375 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7376 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7377 {
7378 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7379 i.prefixes--;
7380 }
7381 }
7382 else
7383 {
7384 int code16;
7385
7386 code16 = 0;
7387 if (flag_code == CODE_16BIT)
7388 code16 = CODE16;
7389
7390 if (i.prefix[DATA_PREFIX] != 0)
7391 {
7392 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7393 i.prefixes -= 1;
7394 code16 ^= CODE16;
7395 }
7396
7397 size = 4;
7398 if (code16)
7399 size = 2;
7400 }
7401
7402 if (i.prefix[REX_PREFIX] != 0)
7403 {
7404 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7405 i.prefixes -= 1;
7406 }
7407
7408 /* BND prefixed jump. */
7409 if (i.prefix[BND_PREFIX] != 0)
7410 {
7411 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7412 i.prefixes -= 1;
7413 }
7414
7415 if (i.prefixes != 0 && !intel_syntax)
7416 as_warn (_("skipping prefixes on this instruction"));
7417
7418 p = frag_more (i.tm.opcode_length + size);
7419 switch (i.tm.opcode_length)
7420 {
7421 case 2:
7422 *p++ = i.tm.base_opcode >> 8;
7423 /* Fall through. */
7424 case 1:
7425 *p++ = i.tm.base_opcode;
7426 break;
7427 default:
7428 abort ();
7429 }
7430
7431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7432 if (size == 4
7433 && jump_reloc == NO_RELOC
7434 && need_plt32_p (i.op[0].disps->X_add_symbol))
7435 jump_reloc = BFD_RELOC_X86_64_PLT32;
7436 #endif
7437
7438 jump_reloc = reloc (size, 1, 1, jump_reloc);
7439
7440 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7441 i.op[0].disps, 1, jump_reloc);
7442
7443 /* All jumps handled here are signed, but don't use a signed limit
7444 check for 32 and 16 bit jumps as we want to allow wrap around at
7445 4G and 64k respectively. */
7446 if (size == 1)
7447 fixP->fx_signed = 1;
7448 }
7449
7450 static void
7451 output_interseg_jump (void)
7452 {
7453 char *p;
7454 int size;
7455 int prefix;
7456 int code16;
7457
7458 code16 = 0;
7459 if (flag_code == CODE_16BIT)
7460 code16 = CODE16;
7461
7462 prefix = 0;
7463 if (i.prefix[DATA_PREFIX] != 0)
7464 {
7465 prefix = 1;
7466 i.prefixes -= 1;
7467 code16 ^= CODE16;
7468 }
7469 if (i.prefix[REX_PREFIX] != 0)
7470 {
7471 prefix++;
7472 i.prefixes -= 1;
7473 }
7474
7475 size = 4;
7476 if (code16)
7477 size = 2;
7478
7479 if (i.prefixes != 0 && !intel_syntax)
7480 as_warn (_("skipping prefixes on this instruction"));
7481
7482 /* 1 opcode; 2 segment; offset */
7483 p = frag_more (prefix + 1 + 2 + size);
7484
7485 if (i.prefix[DATA_PREFIX] != 0)
7486 *p++ = DATA_PREFIX_OPCODE;
7487
7488 if (i.prefix[REX_PREFIX] != 0)
7489 *p++ = i.prefix[REX_PREFIX];
7490
7491 *p++ = i.tm.base_opcode;
7492 if (i.op[1].imms->X_op == O_constant)
7493 {
7494 offsetT n = i.op[1].imms->X_add_number;
7495
7496 if (size == 2
7497 && !fits_in_unsigned_word (n)
7498 && !fits_in_signed_word (n))
7499 {
7500 as_bad (_("16-bit jump out of range"));
7501 return;
7502 }
7503 md_number_to_chars (p, n, size);
7504 }
7505 else
7506 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7507 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7508 if (i.op[0].imms->X_op != O_constant)
7509 as_bad (_("can't handle non absolute segment in `%s'"),
7510 i.tm.name);
7511 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7512 }
7513
7514 static void
7515 output_insn (void)
7516 {
7517 fragS *insn_start_frag;
7518 offsetT insn_start_off;
7519
7520 /* Tie dwarf2 debug info to the address at the start of the insn.
7521 We can't do this after the insn has been output as the current
7522 frag may have been closed off. eg. by frag_var. */
7523 dwarf2_emit_insn (0);
7524
7525 insn_start_frag = frag_now;
7526 insn_start_off = frag_now_fix ();
7527
7528 /* Output jumps. */
7529 if (i.tm.opcode_modifier.jump)
7530 output_branch ();
7531 else if (i.tm.opcode_modifier.jumpbyte
7532 || i.tm.opcode_modifier.jumpdword)
7533 output_jump ();
7534 else if (i.tm.opcode_modifier.jumpintersegment)
7535 output_interseg_jump ();
7536 else
7537 {
7538 /* Output normal instructions here. */
7539 char *p;
7540 unsigned char *q;
7541 unsigned int j;
7542 unsigned int prefix;
7543
7544 if (avoid_fence
7545 && i.tm.base_opcode == 0xfae
7546 && i.operands == 1
7547 && i.imm_operands == 1
7548 && (i.op[0].imms->X_add_number == 0xe8
7549 || i.op[0].imms->X_add_number == 0xf0
7550 || i.op[0].imms->X_add_number == 0xf8))
7551 {
7552 /* Encode lfence, mfence, and sfence as
7553 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7554 offsetT val = 0x240483f0ULL;
7555 p = frag_more (5);
7556 md_number_to_chars (p, val, 5);
7557 return;
7558 }
7559
7560 /* Some processors fail on LOCK prefix. This options makes
7561 assembler ignore LOCK prefix and serves as a workaround. */
7562 if (omit_lock_prefix)
7563 {
7564 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7565 return;
7566 i.prefix[LOCK_PREFIX] = 0;
7567 }
7568
7569 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7570 don't need the explicit prefix. */
7571 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7572 {
7573 switch (i.tm.opcode_length)
7574 {
7575 case 3:
7576 if (i.tm.base_opcode & 0xff000000)
7577 {
7578 prefix = (i.tm.base_opcode >> 24) & 0xff;
7579 goto check_prefix;
7580 }
7581 break;
7582 case 2:
7583 if ((i.tm.base_opcode & 0xff0000) != 0)
7584 {
7585 prefix = (i.tm.base_opcode >> 16) & 0xff;
7586 if (i.tm.cpu_flags.bitfield.cpupadlock)
7587 {
7588 check_prefix:
7589 if (prefix != REPE_PREFIX_OPCODE
7590 || (i.prefix[REP_PREFIX]
7591 != REPE_PREFIX_OPCODE))
7592 add_prefix (prefix);
7593 }
7594 else
7595 add_prefix (prefix);
7596 }
7597 break;
7598 case 1:
7599 break;
7600 case 0:
7601 /* Check for pseudo prefixes. */
7602 as_bad_where (insn_start_frag->fr_file,
7603 insn_start_frag->fr_line,
7604 _("pseudo prefix without instruction"));
7605 return;
7606 default:
7607 abort ();
7608 }
7609
7610 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7611 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7612 R_X86_64_GOTTPOFF relocation so that linker can safely
7613 perform IE->LE optimization. */
7614 if (x86_elf_abi == X86_64_X32_ABI
7615 && i.operands == 2
7616 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7617 && i.prefix[REX_PREFIX] == 0)
7618 add_prefix (REX_OPCODE);
7619 #endif
7620
7621 /* The prefix bytes. */
7622 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7623 if (*q)
7624 FRAG_APPEND_1_CHAR (*q);
7625 }
7626 else
7627 {
7628 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7629 if (*q)
7630 switch (j)
7631 {
7632 case REX_PREFIX:
7633 /* REX byte is encoded in VEX prefix. */
7634 break;
7635 case SEG_PREFIX:
7636 case ADDR_PREFIX:
7637 FRAG_APPEND_1_CHAR (*q);
7638 break;
7639 default:
7640 /* There should be no other prefixes for instructions
7641 with VEX prefix. */
7642 abort ();
7643 }
7644
7645 /* For EVEX instructions i.vrex should become 0 after
7646 build_evex_prefix. For VEX instructions upper 16 registers
7647 aren't available, so VREX should be 0. */
7648 if (i.vrex)
7649 abort ();
7650 /* Now the VEX prefix. */
7651 p = frag_more (i.vex.length);
7652 for (j = 0; j < i.vex.length; j++)
7653 p[j] = i.vex.bytes[j];
7654 }
7655
7656 /* Now the opcode; be careful about word order here! */
7657 if (i.tm.opcode_length == 1)
7658 {
7659 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7660 }
7661 else
7662 {
7663 switch (i.tm.opcode_length)
7664 {
7665 case 4:
7666 p = frag_more (4);
7667 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7668 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7669 break;
7670 case 3:
7671 p = frag_more (3);
7672 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7673 break;
7674 case 2:
7675 p = frag_more (2);
7676 break;
7677 default:
7678 abort ();
7679 break;
7680 }
7681
7682 /* Put out high byte first: can't use md_number_to_chars! */
7683 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7684 *p = i.tm.base_opcode & 0xff;
7685 }
7686
7687 /* Now the modrm byte and sib byte (if present). */
7688 if (i.tm.opcode_modifier.modrm)
7689 {
7690 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7691 | i.rm.reg << 3
7692 | i.rm.mode << 6));
7693 /* If i.rm.regmem == ESP (4)
7694 && i.rm.mode != (Register mode)
7695 && not 16 bit
7696 ==> need second modrm byte. */
7697 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7698 && i.rm.mode != 3
7699 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7700 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7701 | i.sib.index << 3
7702 | i.sib.scale << 6));
7703 }
7704
7705 if (i.disp_operands)
7706 output_disp (insn_start_frag, insn_start_off);
7707
7708 if (i.imm_operands)
7709 output_imm (insn_start_frag, insn_start_off);
7710 }
7711
7712 #ifdef DEBUG386
7713 if (flag_debug)
7714 {
7715 pi ("" /*line*/, &i);
7716 }
7717 #endif /* DEBUG386 */
7718 }
7719
7720 /* Return the size of the displacement operand N. */
7721
7722 static int
7723 disp_size (unsigned int n)
7724 {
7725 int size = 4;
7726
7727 if (i.types[n].bitfield.disp64)
7728 size = 8;
7729 else if (i.types[n].bitfield.disp8)
7730 size = 1;
7731 else if (i.types[n].bitfield.disp16)
7732 size = 2;
7733 return size;
7734 }
7735
7736 /* Return the size of the immediate operand N. */
7737
7738 static int
7739 imm_size (unsigned int n)
7740 {
7741 int size = 4;
7742 if (i.types[n].bitfield.imm64)
7743 size = 8;
7744 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7745 size = 1;
7746 else if (i.types[n].bitfield.imm16)
7747 size = 2;
7748 return size;
7749 }
7750
7751 static void
7752 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7753 {
7754 char *p;
7755 unsigned int n;
7756
7757 for (n = 0; n < i.operands; n++)
7758 {
7759 if (operand_type_check (i.types[n], disp))
7760 {
7761 if (i.op[n].disps->X_op == O_constant)
7762 {
7763 int size = disp_size (n);
7764 offsetT val = i.op[n].disps->X_add_number;
7765
7766 val = offset_in_range (val >> i.memshift, size);
7767 p = frag_more (size);
7768 md_number_to_chars (p, val, size);
7769 }
7770 else
7771 {
7772 enum bfd_reloc_code_real reloc_type;
7773 int size = disp_size (n);
7774 int sign = i.types[n].bitfield.disp32s;
7775 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7776 fixS *fixP;
7777
7778 /* We can't have 8 bit displacement here. */
7779 gas_assert (!i.types[n].bitfield.disp8);
7780
7781 /* The PC relative address is computed relative
7782 to the instruction boundary, so in case immediate
7783 fields follows, we need to adjust the value. */
7784 if (pcrel && i.imm_operands)
7785 {
7786 unsigned int n1;
7787 int sz = 0;
7788
7789 for (n1 = 0; n1 < i.operands; n1++)
7790 if (operand_type_check (i.types[n1], imm))
7791 {
7792 /* Only one immediate is allowed for PC
7793 relative address. */
7794 gas_assert (sz == 0);
7795 sz = imm_size (n1);
7796 i.op[n].disps->X_add_number -= sz;
7797 }
7798 /* We should find the immediate. */
7799 gas_assert (sz != 0);
7800 }
7801
7802 p = frag_more (size);
7803 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7804 if (GOT_symbol
7805 && GOT_symbol == i.op[n].disps->X_add_symbol
7806 && (((reloc_type == BFD_RELOC_32
7807 || reloc_type == BFD_RELOC_X86_64_32S
7808 || (reloc_type == BFD_RELOC_64
7809 && object_64bit))
7810 && (i.op[n].disps->X_op == O_symbol
7811 || (i.op[n].disps->X_op == O_add
7812 && ((symbol_get_value_expression
7813 (i.op[n].disps->X_op_symbol)->X_op)
7814 == O_subtract))))
7815 || reloc_type == BFD_RELOC_32_PCREL))
7816 {
7817 offsetT add;
7818
7819 if (insn_start_frag == frag_now)
7820 add = (p - frag_now->fr_literal) - insn_start_off;
7821 else
7822 {
7823 fragS *fr;
7824
7825 add = insn_start_frag->fr_fix - insn_start_off;
7826 for (fr = insn_start_frag->fr_next;
7827 fr && fr != frag_now; fr = fr->fr_next)
7828 add += fr->fr_fix;
7829 add += p - frag_now->fr_literal;
7830 }
7831
7832 if (!object_64bit)
7833 {
7834 reloc_type = BFD_RELOC_386_GOTPC;
7835 i.op[n].imms->X_add_number += add;
7836 }
7837 else if (reloc_type == BFD_RELOC_64)
7838 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7839 else
7840 /* Don't do the adjustment for x86-64, as there
7841 the pcrel addressing is relative to the _next_
7842 insn, and that is taken care of in other code. */
7843 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7844 }
7845 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7846 size, i.op[n].disps, pcrel,
7847 reloc_type);
7848 /* Check for "call/jmp *mem", "mov mem, %reg",
7849 "test %reg, mem" and "binop mem, %reg" where binop
7850 is one of adc, add, and, cmp, or, sbb, sub, xor
7851 instructions. Always generate R_386_GOT32X for
7852 "sym*GOT" operand in 32-bit mode. */
7853 if ((generate_relax_relocations
7854 || (!object_64bit
7855 && i.rm.mode == 0
7856 && i.rm.regmem == 5))
7857 && (i.rm.mode == 2
7858 || (i.rm.mode == 0 && i.rm.regmem == 5))
7859 && ((i.operands == 1
7860 && i.tm.base_opcode == 0xff
7861 && (i.rm.reg == 2 || i.rm.reg == 4))
7862 || (i.operands == 2
7863 && (i.tm.base_opcode == 0x8b
7864 || i.tm.base_opcode == 0x85
7865 || (i.tm.base_opcode & 0xc7) == 0x03))))
7866 {
7867 if (object_64bit)
7868 {
7869 fixP->fx_tcbit = i.rex != 0;
7870 if (i.base_reg
7871 && (i.base_reg->reg_num == RegRip
7872 || i.base_reg->reg_num == RegEip))
7873 fixP->fx_tcbit2 = 1;
7874 }
7875 else
7876 fixP->fx_tcbit2 = 1;
7877 }
7878 }
7879 }
7880 }
7881 }
7882
7883 static void
7884 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7885 {
7886 char *p;
7887 unsigned int n;
7888
7889 for (n = 0; n < i.operands; n++)
7890 {
7891 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7892 if (i.rounding && (int) n == i.rounding->operand)
7893 continue;
7894
7895 if (operand_type_check (i.types[n], imm))
7896 {
7897 if (i.op[n].imms->X_op == O_constant)
7898 {
7899 int size = imm_size (n);
7900 offsetT val;
7901
7902 val = offset_in_range (i.op[n].imms->X_add_number,
7903 size);
7904 p = frag_more (size);
7905 md_number_to_chars (p, val, size);
7906 }
7907 else
7908 {
7909 /* Not absolute_section.
7910 Need a 32-bit fixup (don't support 8bit
7911 non-absolute imms). Try to support other
7912 sizes ... */
7913 enum bfd_reloc_code_real reloc_type;
7914 int size = imm_size (n);
7915 int sign;
7916
7917 if (i.types[n].bitfield.imm32s
7918 && (i.suffix == QWORD_MNEM_SUFFIX
7919 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7920 sign = 1;
7921 else
7922 sign = 0;
7923
7924 p = frag_more (size);
7925 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7926
7927 /* This is tough to explain. We end up with this one if we
7928 * have operands that look like
7929 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7930 * obtain the absolute address of the GOT, and it is strongly
7931 * preferable from a performance point of view to avoid using
7932 * a runtime relocation for this. The actual sequence of
7933 * instructions often look something like:
7934 *
7935 * call .L66
7936 * .L66:
7937 * popl %ebx
7938 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7939 *
7940 * The call and pop essentially return the absolute address
7941 * of the label .L66 and store it in %ebx. The linker itself
7942 * will ultimately change the first operand of the addl so
7943 * that %ebx points to the GOT, but to keep things simple, the
7944 * .o file must have this operand set so that it generates not
7945 * the absolute address of .L66, but the absolute address of
7946 * itself. This allows the linker itself simply treat a GOTPC
7947 * relocation as asking for a pcrel offset to the GOT to be
7948 * added in, and the addend of the relocation is stored in the
7949 * operand field for the instruction itself.
7950 *
7951 * Our job here is to fix the operand so that it would add
7952 * the correct offset so that %ebx would point to itself. The
7953 * thing that is tricky is that .-.L66 will point to the
7954 * beginning of the instruction, so we need to further modify
7955 * the operand so that it will point to itself. There are
7956 * other cases where you have something like:
7957 *
7958 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7959 *
7960 * and here no correction would be required. Internally in
7961 * the assembler we treat operands of this form as not being
7962 * pcrel since the '.' is explicitly mentioned, and I wonder
7963 * whether it would simplify matters to do it this way. Who
7964 * knows. In earlier versions of the PIC patches, the
7965 * pcrel_adjust field was used to store the correction, but
7966 * since the expression is not pcrel, I felt it would be
7967 * confusing to do it this way. */
7968
7969 if ((reloc_type == BFD_RELOC_32
7970 || reloc_type == BFD_RELOC_X86_64_32S
7971 || reloc_type == BFD_RELOC_64)
7972 && GOT_symbol
7973 && GOT_symbol == i.op[n].imms->X_add_symbol
7974 && (i.op[n].imms->X_op == O_symbol
7975 || (i.op[n].imms->X_op == O_add
7976 && ((symbol_get_value_expression
7977 (i.op[n].imms->X_op_symbol)->X_op)
7978 == O_subtract))))
7979 {
7980 offsetT add;
7981
7982 if (insn_start_frag == frag_now)
7983 add = (p - frag_now->fr_literal) - insn_start_off;
7984 else
7985 {
7986 fragS *fr;
7987
7988 add = insn_start_frag->fr_fix - insn_start_off;
7989 for (fr = insn_start_frag->fr_next;
7990 fr && fr != frag_now; fr = fr->fr_next)
7991 add += fr->fr_fix;
7992 add += p - frag_now->fr_literal;
7993 }
7994
7995 if (!object_64bit)
7996 reloc_type = BFD_RELOC_386_GOTPC;
7997 else if (size == 4)
7998 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7999 else if (size == 8)
8000 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8001 i.op[n].imms->X_add_number += add;
8002 }
8003 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8004 i.op[n].imms, 0, reloc_type);
8005 }
8006 }
8007 }
8008 }
8009 \f
8010 /* x86_cons_fix_new is called via the expression parsing code when a
8011 reloc is needed. We use this hook to get the correct .got reloc. */
8012 static int cons_sign = -1;
8013
8014 void
8015 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8016 expressionS *exp, bfd_reloc_code_real_type r)
8017 {
8018 r = reloc (len, 0, cons_sign, r);
8019
8020 #ifdef TE_PE
8021 if (exp->X_op == O_secrel)
8022 {
8023 exp->X_op = O_symbol;
8024 r = BFD_RELOC_32_SECREL;
8025 }
8026 #endif
8027
8028 fix_new_exp (frag, off, len, exp, 0, r);
8029 }
8030
8031 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8032 purpose of the `.dc.a' internal pseudo-op. */
8033
8034 int
8035 x86_address_bytes (void)
8036 {
8037 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8038 return 4;
8039 return stdoutput->arch_info->bits_per_address / 8;
8040 }
8041
8042 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8043 || defined (LEX_AT)
8044 # define lex_got(reloc, adjust, types) NULL
8045 #else
8046 /* Parse operands of the form
8047 <symbol>@GOTOFF+<nnn>
8048 and similar .plt or .got references.
8049
8050 If we find one, set up the correct relocation in RELOC and copy the
8051 input string, minus the `@GOTOFF' into a malloc'd buffer for
8052 parsing by the calling routine. Return this buffer, and if ADJUST
8053 is non-null set it to the length of the string we removed from the
8054 input line. Otherwise return NULL. */
8055 static char *
8056 lex_got (enum bfd_reloc_code_real *rel,
8057 int *adjust,
8058 i386_operand_type *types)
8059 {
8060 /* Some of the relocations depend on the size of what field is to
8061 be relocated. But in our callers i386_immediate and i386_displacement
8062 we don't yet know the operand size (this will be set by insn
8063 matching). Hence we record the word32 relocation here,
8064 and adjust the reloc according to the real size in reloc(). */
8065 static const struct {
8066 const char *str;
8067 int len;
8068 const enum bfd_reloc_code_real rel[2];
8069 const i386_operand_type types64;
8070 } gotrel[] = {
8071 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8072 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8073 BFD_RELOC_SIZE32 },
8074 OPERAND_TYPE_IMM32_64 },
8075 #endif
8076 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8077 BFD_RELOC_X86_64_PLTOFF64 },
8078 OPERAND_TYPE_IMM64 },
8079 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8080 BFD_RELOC_X86_64_PLT32 },
8081 OPERAND_TYPE_IMM32_32S_DISP32 },
8082 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8083 BFD_RELOC_X86_64_GOTPLT64 },
8084 OPERAND_TYPE_IMM64_DISP64 },
8085 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8086 BFD_RELOC_X86_64_GOTOFF64 },
8087 OPERAND_TYPE_IMM64_DISP64 },
8088 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8089 BFD_RELOC_X86_64_GOTPCREL },
8090 OPERAND_TYPE_IMM32_32S_DISP32 },
8091 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8092 BFD_RELOC_X86_64_TLSGD },
8093 OPERAND_TYPE_IMM32_32S_DISP32 },
8094 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8095 _dummy_first_bfd_reloc_code_real },
8096 OPERAND_TYPE_NONE },
8097 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8098 BFD_RELOC_X86_64_TLSLD },
8099 OPERAND_TYPE_IMM32_32S_DISP32 },
8100 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8101 BFD_RELOC_X86_64_GOTTPOFF },
8102 OPERAND_TYPE_IMM32_32S_DISP32 },
8103 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8104 BFD_RELOC_X86_64_TPOFF32 },
8105 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8106 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8107 _dummy_first_bfd_reloc_code_real },
8108 OPERAND_TYPE_NONE },
8109 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8110 BFD_RELOC_X86_64_DTPOFF32 },
8111 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8112 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8113 _dummy_first_bfd_reloc_code_real },
8114 OPERAND_TYPE_NONE },
8115 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8116 _dummy_first_bfd_reloc_code_real },
8117 OPERAND_TYPE_NONE },
8118 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8119 BFD_RELOC_X86_64_GOT32 },
8120 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8121 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8122 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8123 OPERAND_TYPE_IMM32_32S_DISP32 },
8124 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8125 BFD_RELOC_X86_64_TLSDESC_CALL },
8126 OPERAND_TYPE_IMM32_32S_DISP32 },
8127 };
8128 char *cp;
8129 unsigned int j;
8130
8131 #if defined (OBJ_MAYBE_ELF)
8132 if (!IS_ELF)
8133 return NULL;
8134 #endif
8135
8136 for (cp = input_line_pointer; *cp != '@'; cp++)
8137 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8138 return NULL;
8139
8140 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8141 {
8142 int len = gotrel[j].len;
8143 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8144 {
8145 if (gotrel[j].rel[object_64bit] != 0)
8146 {
8147 int first, second;
8148 char *tmpbuf, *past_reloc;
8149
8150 *rel = gotrel[j].rel[object_64bit];
8151
8152 if (types)
8153 {
8154 if (flag_code != CODE_64BIT)
8155 {
8156 types->bitfield.imm32 = 1;
8157 types->bitfield.disp32 = 1;
8158 }
8159 else
8160 *types = gotrel[j].types64;
8161 }
8162
8163 if (j != 0 && GOT_symbol == NULL)
8164 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8165
8166 /* The length of the first part of our input line. */
8167 first = cp - input_line_pointer;
8168
8169 /* The second part goes from after the reloc token until
8170 (and including) an end_of_line char or comma. */
8171 past_reloc = cp + 1 + len;
8172 cp = past_reloc;
8173 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8174 ++cp;
8175 second = cp + 1 - past_reloc;
8176
8177 /* Allocate and copy string. The trailing NUL shouldn't
8178 be necessary, but be safe. */
8179 tmpbuf = XNEWVEC (char, first + second + 2);
8180 memcpy (tmpbuf, input_line_pointer, first);
8181 if (second != 0 && *past_reloc != ' ')
8182 /* Replace the relocation token with ' ', so that
8183 errors like foo@GOTOFF1 will be detected. */
8184 tmpbuf[first++] = ' ';
8185 else
8186 /* Increment length by 1 if the relocation token is
8187 removed. */
8188 len++;
8189 if (adjust)
8190 *adjust = len;
8191 memcpy (tmpbuf + first, past_reloc, second);
8192 tmpbuf[first + second] = '\0';
8193 return tmpbuf;
8194 }
8195
8196 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8197 gotrel[j].str, 1 << (5 + object_64bit));
8198 return NULL;
8199 }
8200 }
8201
8202 /* Might be a symbol version string. Don't as_bad here. */
8203 return NULL;
8204 }
8205 #endif
8206
8207 #ifdef TE_PE
8208 #ifdef lex_got
8209 #undef lex_got
8210 #endif
8211 /* Parse operands of the form
8212 <symbol>@SECREL32+<nnn>
8213
8214 If we find one, set up the correct relocation in RELOC and copy the
8215 input string, minus the `@SECREL32' into a malloc'd buffer for
8216 parsing by the calling routine. Return this buffer, and if ADJUST
8217 is non-null set it to the length of the string we removed from the
8218 input line. Otherwise return NULL.
8219
8220 This function is copied from the ELF version above adjusted for PE targets. */
8221
8222 static char *
8223 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8224 int *adjust ATTRIBUTE_UNUSED,
8225 i386_operand_type *types)
8226 {
8227 static const struct
8228 {
8229 const char *str;
8230 int len;
8231 const enum bfd_reloc_code_real rel[2];
8232 const i386_operand_type types64;
8233 }
8234 gotrel[] =
8235 {
8236 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8237 BFD_RELOC_32_SECREL },
8238 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8239 };
8240
8241 char *cp;
8242 unsigned j;
8243
8244 for (cp = input_line_pointer; *cp != '@'; cp++)
8245 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8246 return NULL;
8247
8248 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8249 {
8250 int len = gotrel[j].len;
8251
8252 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8253 {
8254 if (gotrel[j].rel[object_64bit] != 0)
8255 {
8256 int first, second;
8257 char *tmpbuf, *past_reloc;
8258
8259 *rel = gotrel[j].rel[object_64bit];
8260 if (adjust)
8261 *adjust = len;
8262
8263 if (types)
8264 {
8265 if (flag_code != CODE_64BIT)
8266 {
8267 types->bitfield.imm32 = 1;
8268 types->bitfield.disp32 = 1;
8269 }
8270 else
8271 *types = gotrel[j].types64;
8272 }
8273
8274 /* The length of the first part of our input line. */
8275 first = cp - input_line_pointer;
8276
8277 /* The second part goes from after the reloc token until
8278 (and including) an end_of_line char or comma. */
8279 past_reloc = cp + 1 + len;
8280 cp = past_reloc;
8281 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8282 ++cp;
8283 second = cp + 1 - past_reloc;
8284
8285 /* Allocate and copy string. The trailing NUL shouldn't
8286 be necessary, but be safe. */
8287 tmpbuf = XNEWVEC (char, first + second + 2);
8288 memcpy (tmpbuf, input_line_pointer, first);
8289 if (second != 0 && *past_reloc != ' ')
8290 /* Replace the relocation token with ' ', so that
8291 errors like foo@SECLREL321 will be detected. */
8292 tmpbuf[first++] = ' ';
8293 memcpy (tmpbuf + first, past_reloc, second);
8294 tmpbuf[first + second] = '\0';
8295 return tmpbuf;
8296 }
8297
8298 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8299 gotrel[j].str, 1 << (5 + object_64bit));
8300 return NULL;
8301 }
8302 }
8303
8304 /* Might be a symbol version string. Don't as_bad here. */
8305 return NULL;
8306 }
8307
8308 #endif /* TE_PE */
8309
8310 bfd_reloc_code_real_type
8311 x86_cons (expressionS *exp, int size)
8312 {
8313 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8314
8315 intel_syntax = -intel_syntax;
8316
8317 exp->X_md = 0;
8318 if (size == 4 || (object_64bit && size == 8))
8319 {
8320 /* Handle @GOTOFF and the like in an expression. */
8321 char *save;
8322 char *gotfree_input_line;
8323 int adjust = 0;
8324
8325 save = input_line_pointer;
8326 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8327 if (gotfree_input_line)
8328 input_line_pointer = gotfree_input_line;
8329
8330 expression (exp);
8331
8332 if (gotfree_input_line)
8333 {
8334 /* expression () has merrily parsed up to the end of line,
8335 or a comma - in the wrong buffer. Transfer how far
8336 input_line_pointer has moved to the right buffer. */
8337 input_line_pointer = (save
8338 + (input_line_pointer - gotfree_input_line)
8339 + adjust);
8340 free (gotfree_input_line);
8341 if (exp->X_op == O_constant
8342 || exp->X_op == O_absent
8343 || exp->X_op == O_illegal
8344 || exp->X_op == O_register
8345 || exp->X_op == O_big)
8346 {
8347 char c = *input_line_pointer;
8348 *input_line_pointer = 0;
8349 as_bad (_("missing or invalid expression `%s'"), save);
8350 *input_line_pointer = c;
8351 }
8352 }
8353 }
8354 else
8355 expression (exp);
8356
8357 intel_syntax = -intel_syntax;
8358
8359 if (intel_syntax)
8360 i386_intel_simplify (exp);
8361
8362 return got_reloc;
8363 }
8364
8365 static void
8366 signed_cons (int size)
8367 {
8368 if (flag_code == CODE_64BIT)
8369 cons_sign = 1;
8370 cons (size);
8371 cons_sign = -1;
8372 }
8373
8374 #ifdef TE_PE
8375 static void
8376 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8377 {
8378 expressionS exp;
8379
8380 do
8381 {
8382 expression (&exp);
8383 if (exp.X_op == O_symbol)
8384 exp.X_op = O_secrel;
8385
8386 emit_expr (&exp, 4);
8387 }
8388 while (*input_line_pointer++ == ',');
8389
8390 input_line_pointer--;
8391 demand_empty_rest_of_line ();
8392 }
8393 #endif
8394
8395 /* Handle Vector operations. */
8396
8397 static char *
8398 check_VecOperations (char *op_string, char *op_end)
8399 {
8400 const reg_entry *mask;
8401 const char *saved;
8402 char *end_op;
8403
8404 while (*op_string
8405 && (op_end == NULL || op_string < op_end))
8406 {
8407 saved = op_string;
8408 if (*op_string == '{')
8409 {
8410 op_string++;
8411
8412 /* Check broadcasts. */
8413 if (strncmp (op_string, "1to", 3) == 0)
8414 {
8415 int bcst_type;
8416
8417 if (i.broadcast)
8418 goto duplicated_vec_op;
8419
8420 op_string += 3;
8421 if (*op_string == '8')
8422 bcst_type = BROADCAST_1TO8;
8423 else if (*op_string == '4')
8424 bcst_type = BROADCAST_1TO4;
8425 else if (*op_string == '2')
8426 bcst_type = BROADCAST_1TO2;
8427 else if (*op_string == '1'
8428 && *(op_string+1) == '6')
8429 {
8430 bcst_type = BROADCAST_1TO16;
8431 op_string++;
8432 }
8433 else
8434 {
8435 as_bad (_("Unsupported broadcast: `%s'"), saved);
8436 return NULL;
8437 }
8438 op_string++;
8439
8440 broadcast_op.type = bcst_type;
8441 broadcast_op.operand = this_operand;
8442 i.broadcast = &broadcast_op;
8443 }
8444 /* Check masking operation. */
8445 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8446 {
8447 /* k0 can't be used for write mask. */
8448 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8449 {
8450 as_bad (_("`%s%s' can't be used for write mask"),
8451 register_prefix, mask->reg_name);
8452 return NULL;
8453 }
8454
8455 if (!i.mask)
8456 {
8457 mask_op.mask = mask;
8458 mask_op.zeroing = 0;
8459 mask_op.operand = this_operand;
8460 i.mask = &mask_op;
8461 }
8462 else
8463 {
8464 if (i.mask->mask)
8465 goto duplicated_vec_op;
8466
8467 i.mask->mask = mask;
8468
8469 /* Only "{z}" is allowed here. No need to check
8470 zeroing mask explicitly. */
8471 if (i.mask->operand != this_operand)
8472 {
8473 as_bad (_("invalid write mask `%s'"), saved);
8474 return NULL;
8475 }
8476 }
8477
8478 op_string = end_op;
8479 }
8480 /* Check zeroing-flag for masking operation. */
8481 else if (*op_string == 'z')
8482 {
8483 if (!i.mask)
8484 {
8485 mask_op.mask = NULL;
8486 mask_op.zeroing = 1;
8487 mask_op.operand = this_operand;
8488 i.mask = &mask_op;
8489 }
8490 else
8491 {
8492 if (i.mask->zeroing)
8493 {
8494 duplicated_vec_op:
8495 as_bad (_("duplicated `%s'"), saved);
8496 return NULL;
8497 }
8498
8499 i.mask->zeroing = 1;
8500
8501 /* Only "{%k}" is allowed here. No need to check mask
8502 register explicitly. */
8503 if (i.mask->operand != this_operand)
8504 {
8505 as_bad (_("invalid zeroing-masking `%s'"),
8506 saved);
8507 return NULL;
8508 }
8509 }
8510
8511 op_string++;
8512 }
8513 else
8514 goto unknown_vec_op;
8515
8516 if (*op_string != '}')
8517 {
8518 as_bad (_("missing `}' in `%s'"), saved);
8519 return NULL;
8520 }
8521 op_string++;
8522 continue;
8523 }
8524 unknown_vec_op:
8525 /* We don't know this one. */
8526 as_bad (_("unknown vector operation: `%s'"), saved);
8527 return NULL;
8528 }
8529
8530 if (i.mask && i.mask->zeroing && !i.mask->mask)
8531 {
8532 as_bad (_("zeroing-masking only allowed with write mask"));
8533 return NULL;
8534 }
8535
8536 return op_string;
8537 }
8538
8539 static int
8540 i386_immediate (char *imm_start)
8541 {
8542 char *save_input_line_pointer;
8543 char *gotfree_input_line;
8544 segT exp_seg = 0;
8545 expressionS *exp;
8546 i386_operand_type types;
8547
8548 operand_type_set (&types, ~0);
8549
8550 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8551 {
8552 as_bad (_("at most %d immediate operands are allowed"),
8553 MAX_IMMEDIATE_OPERANDS);
8554 return 0;
8555 }
8556
8557 exp = &im_expressions[i.imm_operands++];
8558 i.op[this_operand].imms = exp;
8559
8560 if (is_space_char (*imm_start))
8561 ++imm_start;
8562
8563 save_input_line_pointer = input_line_pointer;
8564 input_line_pointer = imm_start;
8565
8566 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8567 if (gotfree_input_line)
8568 input_line_pointer = gotfree_input_line;
8569
8570 exp_seg = expression (exp);
8571
8572 SKIP_WHITESPACE ();
8573
8574 /* Handle vector operations. */
8575 if (*input_line_pointer == '{')
8576 {
8577 input_line_pointer = check_VecOperations (input_line_pointer,
8578 NULL);
8579 if (input_line_pointer == NULL)
8580 return 0;
8581 }
8582
8583 if (*input_line_pointer)
8584 as_bad (_("junk `%s' after expression"), input_line_pointer);
8585
8586 input_line_pointer = save_input_line_pointer;
8587 if (gotfree_input_line)
8588 {
8589 free (gotfree_input_line);
8590
8591 if (exp->X_op == O_constant || exp->X_op == O_register)
8592 exp->X_op = O_illegal;
8593 }
8594
8595 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8596 }
8597
8598 static int
8599 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8600 i386_operand_type types, const char *imm_start)
8601 {
8602 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8603 {
8604 if (imm_start)
8605 as_bad (_("missing or invalid immediate expression `%s'"),
8606 imm_start);
8607 return 0;
8608 }
8609 else if (exp->X_op == O_constant)
8610 {
8611 /* Size it properly later. */
8612 i.types[this_operand].bitfield.imm64 = 1;
8613 /* If not 64bit, sign extend val. */
8614 if (flag_code != CODE_64BIT
8615 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8616 exp->X_add_number
8617 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8618 }
8619 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8620 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8621 && exp_seg != absolute_section
8622 && exp_seg != text_section
8623 && exp_seg != data_section
8624 && exp_seg != bss_section
8625 && exp_seg != undefined_section
8626 && !bfd_is_com_section (exp_seg))
8627 {
8628 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8629 return 0;
8630 }
8631 #endif
8632 else if (!intel_syntax && exp_seg == reg_section)
8633 {
8634 if (imm_start)
8635 as_bad (_("illegal immediate register operand %s"), imm_start);
8636 return 0;
8637 }
8638 else
8639 {
8640 /* This is an address. The size of the address will be
8641 determined later, depending on destination register,
8642 suffix, or the default for the section. */
8643 i.types[this_operand].bitfield.imm8 = 1;
8644 i.types[this_operand].bitfield.imm16 = 1;
8645 i.types[this_operand].bitfield.imm32 = 1;
8646 i.types[this_operand].bitfield.imm32s = 1;
8647 i.types[this_operand].bitfield.imm64 = 1;
8648 i.types[this_operand] = operand_type_and (i.types[this_operand],
8649 types);
8650 }
8651
8652 return 1;
8653 }
8654
8655 static char *
8656 i386_scale (char *scale)
8657 {
8658 offsetT val;
8659 char *save = input_line_pointer;
8660
8661 input_line_pointer = scale;
8662 val = get_absolute_expression ();
8663
8664 switch (val)
8665 {
8666 case 1:
8667 i.log2_scale_factor = 0;
8668 break;
8669 case 2:
8670 i.log2_scale_factor = 1;
8671 break;
8672 case 4:
8673 i.log2_scale_factor = 2;
8674 break;
8675 case 8:
8676 i.log2_scale_factor = 3;
8677 break;
8678 default:
8679 {
8680 char sep = *input_line_pointer;
8681
8682 *input_line_pointer = '\0';
8683 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8684 scale);
8685 *input_line_pointer = sep;
8686 input_line_pointer = save;
8687 return NULL;
8688 }
8689 }
8690 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8691 {
8692 as_warn (_("scale factor of %d without an index register"),
8693 1 << i.log2_scale_factor);
8694 i.log2_scale_factor = 0;
8695 }
8696 scale = input_line_pointer;
8697 input_line_pointer = save;
8698 return scale;
8699 }
8700
8701 static int
8702 i386_displacement (char *disp_start, char *disp_end)
8703 {
8704 expressionS *exp;
8705 segT exp_seg = 0;
8706 char *save_input_line_pointer;
8707 char *gotfree_input_line;
8708 int override;
8709 i386_operand_type bigdisp, types = anydisp;
8710 int ret;
8711
8712 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8713 {
8714 as_bad (_("at most %d displacement operands are allowed"),
8715 MAX_MEMORY_OPERANDS);
8716 return 0;
8717 }
8718
8719 operand_type_set (&bigdisp, 0);
8720 if ((i.types[this_operand].bitfield.jumpabsolute)
8721 || (!current_templates->start->opcode_modifier.jump
8722 && !current_templates->start->opcode_modifier.jumpdword))
8723 {
8724 bigdisp.bitfield.disp32 = 1;
8725 override = (i.prefix[ADDR_PREFIX] != 0);
8726 if (flag_code == CODE_64BIT)
8727 {
8728 if (!override)
8729 {
8730 bigdisp.bitfield.disp32s = 1;
8731 bigdisp.bitfield.disp64 = 1;
8732 }
8733 }
8734 else if ((flag_code == CODE_16BIT) ^ override)
8735 {
8736 bigdisp.bitfield.disp32 = 0;
8737 bigdisp.bitfield.disp16 = 1;
8738 }
8739 }
8740 else
8741 {
8742 /* For PC-relative branches, the width of the displacement
8743 is dependent upon data size, not address size. */
8744 override = (i.prefix[DATA_PREFIX] != 0);
8745 if (flag_code == CODE_64BIT)
8746 {
8747 if (override || i.suffix == WORD_MNEM_SUFFIX)
8748 bigdisp.bitfield.disp16 = 1;
8749 else
8750 {
8751 bigdisp.bitfield.disp32 = 1;
8752 bigdisp.bitfield.disp32s = 1;
8753 }
8754 }
8755 else
8756 {
8757 if (!override)
8758 override = (i.suffix == (flag_code != CODE_16BIT
8759 ? WORD_MNEM_SUFFIX
8760 : LONG_MNEM_SUFFIX));
8761 bigdisp.bitfield.disp32 = 1;
8762 if ((flag_code == CODE_16BIT) ^ override)
8763 {
8764 bigdisp.bitfield.disp32 = 0;
8765 bigdisp.bitfield.disp16 = 1;
8766 }
8767 }
8768 }
8769 i.types[this_operand] = operand_type_or (i.types[this_operand],
8770 bigdisp);
8771
8772 exp = &disp_expressions[i.disp_operands];
8773 i.op[this_operand].disps = exp;
8774 i.disp_operands++;
8775 save_input_line_pointer = input_line_pointer;
8776 input_line_pointer = disp_start;
8777 END_STRING_AND_SAVE (disp_end);
8778
8779 #ifndef GCC_ASM_O_HACK
8780 #define GCC_ASM_O_HACK 0
8781 #endif
8782 #if GCC_ASM_O_HACK
8783 END_STRING_AND_SAVE (disp_end + 1);
8784 if (i.types[this_operand].bitfield.baseIndex
8785 && displacement_string_end[-1] == '+')
8786 {
8787 /* This hack is to avoid a warning when using the "o"
8788 constraint within gcc asm statements.
8789 For instance:
8790
8791 #define _set_tssldt_desc(n,addr,limit,type) \
8792 __asm__ __volatile__ ( \
8793 "movw %w2,%0\n\t" \
8794 "movw %w1,2+%0\n\t" \
8795 "rorl $16,%1\n\t" \
8796 "movb %b1,4+%0\n\t" \
8797 "movb %4,5+%0\n\t" \
8798 "movb $0,6+%0\n\t" \
8799 "movb %h1,7+%0\n\t" \
8800 "rorl $16,%1" \
8801 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8802
8803 This works great except that the output assembler ends
8804 up looking a bit weird if it turns out that there is
8805 no offset. You end up producing code that looks like:
8806
8807 #APP
8808 movw $235,(%eax)
8809 movw %dx,2+(%eax)
8810 rorl $16,%edx
8811 movb %dl,4+(%eax)
8812 movb $137,5+(%eax)
8813 movb $0,6+(%eax)
8814 movb %dh,7+(%eax)
8815 rorl $16,%edx
8816 #NO_APP
8817
8818 So here we provide the missing zero. */
8819
8820 *displacement_string_end = '0';
8821 }
8822 #endif
8823 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8824 if (gotfree_input_line)
8825 input_line_pointer = gotfree_input_line;
8826
8827 exp_seg = expression (exp);
8828
8829 SKIP_WHITESPACE ();
8830 if (*input_line_pointer)
8831 as_bad (_("junk `%s' after expression"), input_line_pointer);
8832 #if GCC_ASM_O_HACK
8833 RESTORE_END_STRING (disp_end + 1);
8834 #endif
8835 input_line_pointer = save_input_line_pointer;
8836 if (gotfree_input_line)
8837 {
8838 free (gotfree_input_line);
8839
8840 if (exp->X_op == O_constant || exp->X_op == O_register)
8841 exp->X_op = O_illegal;
8842 }
8843
8844 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8845
8846 RESTORE_END_STRING (disp_end);
8847
8848 return ret;
8849 }
8850
8851 static int
8852 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8853 i386_operand_type types, const char *disp_start)
8854 {
8855 i386_operand_type bigdisp;
8856 int ret = 1;
8857
8858 /* We do this to make sure that the section symbol is in
8859 the symbol table. We will ultimately change the relocation
8860 to be relative to the beginning of the section. */
8861 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8862 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8863 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8864 {
8865 if (exp->X_op != O_symbol)
8866 goto inv_disp;
8867
8868 if (S_IS_LOCAL (exp->X_add_symbol)
8869 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8870 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8871 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8872 exp->X_op = O_subtract;
8873 exp->X_op_symbol = GOT_symbol;
8874 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8875 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8876 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8877 i.reloc[this_operand] = BFD_RELOC_64;
8878 else
8879 i.reloc[this_operand] = BFD_RELOC_32;
8880 }
8881
8882 else if (exp->X_op == O_absent
8883 || exp->X_op == O_illegal
8884 || exp->X_op == O_big)
8885 {
8886 inv_disp:
8887 as_bad (_("missing or invalid displacement expression `%s'"),
8888 disp_start);
8889 ret = 0;
8890 }
8891
8892 else if (flag_code == CODE_64BIT
8893 && !i.prefix[ADDR_PREFIX]
8894 && exp->X_op == O_constant)
8895 {
8896 /* Since displacement is signed extended to 64bit, don't allow
8897 disp32 and turn off disp32s if they are out of range. */
8898 i.types[this_operand].bitfield.disp32 = 0;
8899 if (!fits_in_signed_long (exp->X_add_number))
8900 {
8901 i.types[this_operand].bitfield.disp32s = 0;
8902 if (i.types[this_operand].bitfield.baseindex)
8903 {
8904 as_bad (_("0x%lx out range of signed 32bit displacement"),
8905 (long) exp->X_add_number);
8906 ret = 0;
8907 }
8908 }
8909 }
8910
8911 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8912 else if (exp->X_op != O_constant
8913 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8914 && exp_seg != absolute_section
8915 && exp_seg != text_section
8916 && exp_seg != data_section
8917 && exp_seg != bss_section
8918 && exp_seg != undefined_section
8919 && !bfd_is_com_section (exp_seg))
8920 {
8921 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8922 ret = 0;
8923 }
8924 #endif
8925
8926 /* Check if this is a displacement only operand. */
8927 bigdisp = i.types[this_operand];
8928 bigdisp.bitfield.disp8 = 0;
8929 bigdisp.bitfield.disp16 = 0;
8930 bigdisp.bitfield.disp32 = 0;
8931 bigdisp.bitfield.disp32s = 0;
8932 bigdisp.bitfield.disp64 = 0;
8933 if (operand_type_all_zero (&bigdisp))
8934 i.types[this_operand] = operand_type_and (i.types[this_operand],
8935 types);
8936
8937 return ret;
8938 }
8939
8940 /* Return the active addressing mode, taking address override and
8941 registers forming the address into consideration. Update the
8942 address override prefix if necessary. */
8943
8944 static enum flag_code
8945 i386_addressing_mode (void)
8946 {
8947 enum flag_code addr_mode;
8948
8949 if (i.prefix[ADDR_PREFIX])
8950 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8951 else
8952 {
8953 addr_mode = flag_code;
8954
8955 #if INFER_ADDR_PREFIX
8956 if (i.mem_operands == 0)
8957 {
8958 /* Infer address prefix from the first memory operand. */
8959 const reg_entry *addr_reg = i.base_reg;
8960
8961 if (addr_reg == NULL)
8962 addr_reg = i.index_reg;
8963
8964 if (addr_reg)
8965 {
8966 if (addr_reg->reg_num == RegEip
8967 || addr_reg->reg_num == RegEiz
8968 || addr_reg->reg_type.bitfield.dword)
8969 addr_mode = CODE_32BIT;
8970 else if (flag_code != CODE_64BIT
8971 && addr_reg->reg_type.bitfield.word)
8972 addr_mode = CODE_16BIT;
8973
8974 if (addr_mode != flag_code)
8975 {
8976 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8977 i.prefixes += 1;
8978 /* Change the size of any displacement too. At most one
8979 of Disp16 or Disp32 is set.
8980 FIXME. There doesn't seem to be any real need for
8981 separate Disp16 and Disp32 flags. The same goes for
8982 Imm16 and Imm32. Removing them would probably clean
8983 up the code quite a lot. */
8984 if (flag_code != CODE_64BIT
8985 && (i.types[this_operand].bitfield.disp16
8986 || i.types[this_operand].bitfield.disp32))
8987 i.types[this_operand]
8988 = operand_type_xor (i.types[this_operand], disp16_32);
8989 }
8990 }
8991 }
8992 #endif
8993 }
8994
8995 return addr_mode;
8996 }
8997
8998 /* Make sure the memory operand we've been dealt is valid.
8999 Return 1 on success, 0 on a failure. */
9000
9001 static int
9002 i386_index_check (const char *operand_string)
9003 {
9004 const char *kind = "base/index";
9005 enum flag_code addr_mode = i386_addressing_mode ();
9006
9007 if (current_templates->start->opcode_modifier.isstring
9008 && !current_templates->start->opcode_modifier.immext
9009 && (current_templates->end[-1].opcode_modifier.isstring
9010 || i.mem_operands))
9011 {
9012 /* Memory operands of string insns are special in that they only allow
9013 a single register (rDI, rSI, or rBX) as their memory address. */
9014 const reg_entry *expected_reg;
9015 static const char *di_si[][2] =
9016 {
9017 { "esi", "edi" },
9018 { "si", "di" },
9019 { "rsi", "rdi" }
9020 };
9021 static const char *bx[] = { "ebx", "bx", "rbx" };
9022
9023 kind = "string address";
9024
9025 if (current_templates->start->opcode_modifier.repprefixok)
9026 {
9027 i386_operand_type type = current_templates->end[-1].operand_types[0];
9028
9029 if (!type.bitfield.baseindex
9030 || ((!i.mem_operands != !intel_syntax)
9031 && current_templates->end[-1].operand_types[1]
9032 .bitfield.baseindex))
9033 type = current_templates->end[-1].operand_types[1];
9034 expected_reg = hash_find (reg_hash,
9035 di_si[addr_mode][type.bitfield.esseg]);
9036
9037 }
9038 else
9039 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9040
9041 if (i.base_reg != expected_reg
9042 || i.index_reg
9043 || operand_type_check (i.types[this_operand], disp))
9044 {
9045 /* The second memory operand must have the same size as
9046 the first one. */
9047 if (i.mem_operands
9048 && i.base_reg
9049 && !((addr_mode == CODE_64BIT
9050 && i.base_reg->reg_type.bitfield.qword)
9051 || (addr_mode == CODE_32BIT
9052 ? i.base_reg->reg_type.bitfield.dword
9053 : i.base_reg->reg_type.bitfield.word)))
9054 goto bad_address;
9055
9056 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9057 operand_string,
9058 intel_syntax ? '[' : '(',
9059 register_prefix,
9060 expected_reg->reg_name,
9061 intel_syntax ? ']' : ')');
9062 return 1;
9063 }
9064 else
9065 return 1;
9066
9067 bad_address:
9068 as_bad (_("`%s' is not a valid %s expression"),
9069 operand_string, kind);
9070 return 0;
9071 }
9072 else
9073 {
9074 if (addr_mode != CODE_16BIT)
9075 {
9076 /* 32-bit/64-bit checks. */
9077 if ((i.base_reg
9078 && (addr_mode == CODE_64BIT
9079 ? !i.base_reg->reg_type.bitfield.qword
9080 : !i.base_reg->reg_type.bitfield.dword)
9081 && (i.index_reg
9082 || (i.base_reg->reg_num
9083 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9084 || (i.index_reg
9085 && !i.index_reg->reg_type.bitfield.xmmword
9086 && !i.index_reg->reg_type.bitfield.ymmword
9087 && !i.index_reg->reg_type.bitfield.zmmword
9088 && ((addr_mode == CODE_64BIT
9089 ? !(i.index_reg->reg_type.bitfield.qword
9090 || i.index_reg->reg_num == RegRiz)
9091 : !(i.index_reg->reg_type.bitfield.dword
9092 || i.index_reg->reg_num == RegEiz))
9093 || !i.index_reg->reg_type.bitfield.baseindex)))
9094 goto bad_address;
9095
9096 /* bndmk, bndldx, and bndstx have special restrictions. */
9097 if (current_templates->start->base_opcode == 0xf30f1b
9098 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9099 {
9100 /* They cannot use RIP-relative addressing. */
9101 if (i.base_reg && i.base_reg->reg_num == RegRip)
9102 {
9103 as_bad (_("`%s' cannot be used here"), operand_string);
9104 return 0;
9105 }
9106
9107 /* bndldx and bndstx ignore their scale factor. */
9108 if (current_templates->start->base_opcode != 0xf30f1b
9109 && i.log2_scale_factor)
9110 as_warn (_("register scaling is being ignored here"));
9111 }
9112 }
9113 else
9114 {
9115 /* 16-bit checks. */
9116 if ((i.base_reg
9117 && (!i.base_reg->reg_type.bitfield.word
9118 || !i.base_reg->reg_type.bitfield.baseindex))
9119 || (i.index_reg
9120 && (!i.index_reg->reg_type.bitfield.word
9121 || !i.index_reg->reg_type.bitfield.baseindex
9122 || !(i.base_reg
9123 && i.base_reg->reg_num < 6
9124 && i.index_reg->reg_num >= 6
9125 && i.log2_scale_factor == 0))))
9126 goto bad_address;
9127 }
9128 }
9129 return 1;
9130 }
9131
9132 /* Handle vector immediates. */
9133
9134 static int
9135 RC_SAE_immediate (const char *imm_start)
9136 {
9137 unsigned int match_found, j;
9138 const char *pstr = imm_start;
9139 expressionS *exp;
9140
9141 if (*pstr != '{')
9142 return 0;
9143
9144 pstr++;
9145 match_found = 0;
9146 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9147 {
9148 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9149 {
9150 if (!i.rounding)
9151 {
9152 rc_op.type = RC_NamesTable[j].type;
9153 rc_op.operand = this_operand;
9154 i.rounding = &rc_op;
9155 }
9156 else
9157 {
9158 as_bad (_("duplicated `%s'"), imm_start);
9159 return 0;
9160 }
9161 pstr += RC_NamesTable[j].len;
9162 match_found = 1;
9163 break;
9164 }
9165 }
9166 if (!match_found)
9167 return 0;
9168
9169 if (*pstr++ != '}')
9170 {
9171 as_bad (_("Missing '}': '%s'"), imm_start);
9172 return 0;
9173 }
9174 /* RC/SAE immediate string should contain nothing more. */;
9175 if (*pstr != 0)
9176 {
9177 as_bad (_("Junk after '}': '%s'"), imm_start);
9178 return 0;
9179 }
9180
9181 exp = &im_expressions[i.imm_operands++];
9182 i.op[this_operand].imms = exp;
9183
9184 exp->X_op = O_constant;
9185 exp->X_add_number = 0;
9186 exp->X_add_symbol = (symbolS *) 0;
9187 exp->X_op_symbol = (symbolS *) 0;
9188
9189 i.types[this_operand].bitfield.imm8 = 1;
9190 return 1;
9191 }
9192
9193 /* Only string instructions can have a second memory operand, so
9194 reduce current_templates to just those if it contains any. */
9195 static int
9196 maybe_adjust_templates (void)
9197 {
9198 const insn_template *t;
9199
9200 gas_assert (i.mem_operands == 1);
9201
9202 for (t = current_templates->start; t < current_templates->end; ++t)
9203 if (t->opcode_modifier.isstring)
9204 break;
9205
9206 if (t < current_templates->end)
9207 {
9208 static templates aux_templates;
9209 bfd_boolean recheck;
9210
9211 aux_templates.start = t;
9212 for (; t < current_templates->end; ++t)
9213 if (!t->opcode_modifier.isstring)
9214 break;
9215 aux_templates.end = t;
9216
9217 /* Determine whether to re-check the first memory operand. */
9218 recheck = (aux_templates.start != current_templates->start
9219 || t != current_templates->end);
9220
9221 current_templates = &aux_templates;
9222
9223 if (recheck)
9224 {
9225 i.mem_operands = 0;
9226 if (i.memop1_string != NULL
9227 && i386_index_check (i.memop1_string) == 0)
9228 return 0;
9229 i.mem_operands = 1;
9230 }
9231 }
9232
9233 return 1;
9234 }
9235
9236 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9237 on error. */
9238
9239 static int
9240 i386_att_operand (char *operand_string)
9241 {
9242 const reg_entry *r;
9243 char *end_op;
9244 char *op_string = operand_string;
9245
9246 if (is_space_char (*op_string))
9247 ++op_string;
9248
9249 /* We check for an absolute prefix (differentiating,
9250 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9251 if (*op_string == ABSOLUTE_PREFIX)
9252 {
9253 ++op_string;
9254 if (is_space_char (*op_string))
9255 ++op_string;
9256 i.types[this_operand].bitfield.jumpabsolute = 1;
9257 }
9258
9259 /* Check if operand is a register. */
9260 if ((r = parse_register (op_string, &end_op)) != NULL)
9261 {
9262 i386_operand_type temp;
9263
9264 /* Check for a segment override by searching for ':' after a
9265 segment register. */
9266 op_string = end_op;
9267 if (is_space_char (*op_string))
9268 ++op_string;
9269 if (*op_string == ':'
9270 && (r->reg_type.bitfield.sreg2
9271 || r->reg_type.bitfield.sreg3))
9272 {
9273 switch (r->reg_num)
9274 {
9275 case 0:
9276 i.seg[i.mem_operands] = &es;
9277 break;
9278 case 1:
9279 i.seg[i.mem_operands] = &cs;
9280 break;
9281 case 2:
9282 i.seg[i.mem_operands] = &ss;
9283 break;
9284 case 3:
9285 i.seg[i.mem_operands] = &ds;
9286 break;
9287 case 4:
9288 i.seg[i.mem_operands] = &fs;
9289 break;
9290 case 5:
9291 i.seg[i.mem_operands] = &gs;
9292 break;
9293 }
9294
9295 /* Skip the ':' and whitespace. */
9296 ++op_string;
9297 if (is_space_char (*op_string))
9298 ++op_string;
9299
9300 if (!is_digit_char (*op_string)
9301 && !is_identifier_char (*op_string)
9302 && *op_string != '('
9303 && *op_string != ABSOLUTE_PREFIX)
9304 {
9305 as_bad (_("bad memory operand `%s'"), op_string);
9306 return 0;
9307 }
9308 /* Handle case of %es:*foo. */
9309 if (*op_string == ABSOLUTE_PREFIX)
9310 {
9311 ++op_string;
9312 if (is_space_char (*op_string))
9313 ++op_string;
9314 i.types[this_operand].bitfield.jumpabsolute = 1;
9315 }
9316 goto do_memory_reference;
9317 }
9318
9319 /* Handle vector operations. */
9320 if (*op_string == '{')
9321 {
9322 op_string = check_VecOperations (op_string, NULL);
9323 if (op_string == NULL)
9324 return 0;
9325 }
9326
9327 if (*op_string)
9328 {
9329 as_bad (_("junk `%s' after register"), op_string);
9330 return 0;
9331 }
9332 temp = r->reg_type;
9333 temp.bitfield.baseindex = 0;
9334 i.types[this_operand] = operand_type_or (i.types[this_operand],
9335 temp);
9336 i.types[this_operand].bitfield.unspecified = 0;
9337 i.op[this_operand].regs = r;
9338 i.reg_operands++;
9339 }
9340 else if (*op_string == REGISTER_PREFIX)
9341 {
9342 as_bad (_("bad register name `%s'"), op_string);
9343 return 0;
9344 }
9345 else if (*op_string == IMMEDIATE_PREFIX)
9346 {
9347 ++op_string;
9348 if (i.types[this_operand].bitfield.jumpabsolute)
9349 {
9350 as_bad (_("immediate operand illegal with absolute jump"));
9351 return 0;
9352 }
9353 if (!i386_immediate (op_string))
9354 return 0;
9355 }
9356 else if (RC_SAE_immediate (operand_string))
9357 {
9358 /* If it is a RC or SAE immediate, do nothing. */
9359 ;
9360 }
9361 else if (is_digit_char (*op_string)
9362 || is_identifier_char (*op_string)
9363 || *op_string == '"'
9364 || *op_string == '(')
9365 {
9366 /* This is a memory reference of some sort. */
9367 char *base_string;
9368
9369 /* Start and end of displacement string expression (if found). */
9370 char *displacement_string_start;
9371 char *displacement_string_end;
9372 char *vop_start;
9373
9374 do_memory_reference:
9375 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9376 return 0;
9377 if ((i.mem_operands == 1
9378 && !current_templates->start->opcode_modifier.isstring)
9379 || i.mem_operands == 2)
9380 {
9381 as_bad (_("too many memory references for `%s'"),
9382 current_templates->start->name);
9383 return 0;
9384 }
9385
9386 /* Check for base index form. We detect the base index form by
9387 looking for an ')' at the end of the operand, searching
9388 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9389 after the '('. */
9390 base_string = op_string + strlen (op_string);
9391
9392 /* Handle vector operations. */
9393 vop_start = strchr (op_string, '{');
9394 if (vop_start && vop_start < base_string)
9395 {
9396 if (check_VecOperations (vop_start, base_string) == NULL)
9397 return 0;
9398 base_string = vop_start;
9399 }
9400
9401 --base_string;
9402 if (is_space_char (*base_string))
9403 --base_string;
9404
9405 /* If we only have a displacement, set-up for it to be parsed later. */
9406 displacement_string_start = op_string;
9407 displacement_string_end = base_string + 1;
9408
9409 if (*base_string == ')')
9410 {
9411 char *temp_string;
9412 unsigned int parens_balanced = 1;
9413 /* We've already checked that the number of left & right ()'s are
9414 equal, so this loop will not be infinite. */
9415 do
9416 {
9417 base_string--;
9418 if (*base_string == ')')
9419 parens_balanced++;
9420 if (*base_string == '(')
9421 parens_balanced--;
9422 }
9423 while (parens_balanced);
9424
9425 temp_string = base_string;
9426
9427 /* Skip past '(' and whitespace. */
9428 ++base_string;
9429 if (is_space_char (*base_string))
9430 ++base_string;
9431
9432 if (*base_string == ','
9433 || ((i.base_reg = parse_register (base_string, &end_op))
9434 != NULL))
9435 {
9436 displacement_string_end = temp_string;
9437
9438 i.types[this_operand].bitfield.baseindex = 1;
9439
9440 if (i.base_reg)
9441 {
9442 base_string = end_op;
9443 if (is_space_char (*base_string))
9444 ++base_string;
9445 }
9446
9447 /* There may be an index reg or scale factor here. */
9448 if (*base_string == ',')
9449 {
9450 ++base_string;
9451 if (is_space_char (*base_string))
9452 ++base_string;
9453
9454 if ((i.index_reg = parse_register (base_string, &end_op))
9455 != NULL)
9456 {
9457 base_string = end_op;
9458 if (is_space_char (*base_string))
9459 ++base_string;
9460 if (*base_string == ',')
9461 {
9462 ++base_string;
9463 if (is_space_char (*base_string))
9464 ++base_string;
9465 }
9466 else if (*base_string != ')')
9467 {
9468 as_bad (_("expecting `,' or `)' "
9469 "after index register in `%s'"),
9470 operand_string);
9471 return 0;
9472 }
9473 }
9474 else if (*base_string == REGISTER_PREFIX)
9475 {
9476 end_op = strchr (base_string, ',');
9477 if (end_op)
9478 *end_op = '\0';
9479 as_bad (_("bad register name `%s'"), base_string);
9480 return 0;
9481 }
9482
9483 /* Check for scale factor. */
9484 if (*base_string != ')')
9485 {
9486 char *end_scale = i386_scale (base_string);
9487
9488 if (!end_scale)
9489 return 0;
9490
9491 base_string = end_scale;
9492 if (is_space_char (*base_string))
9493 ++base_string;
9494 if (*base_string != ')')
9495 {
9496 as_bad (_("expecting `)' "
9497 "after scale factor in `%s'"),
9498 operand_string);
9499 return 0;
9500 }
9501 }
9502 else if (!i.index_reg)
9503 {
9504 as_bad (_("expecting index register or scale factor "
9505 "after `,'; got '%c'"),
9506 *base_string);
9507 return 0;
9508 }
9509 }
9510 else if (*base_string != ')')
9511 {
9512 as_bad (_("expecting `,' or `)' "
9513 "after base register in `%s'"),
9514 operand_string);
9515 return 0;
9516 }
9517 }
9518 else if (*base_string == REGISTER_PREFIX)
9519 {
9520 end_op = strchr (base_string, ',');
9521 if (end_op)
9522 *end_op = '\0';
9523 as_bad (_("bad register name `%s'"), base_string);
9524 return 0;
9525 }
9526 }
9527
9528 /* If there's an expression beginning the operand, parse it,
9529 assuming displacement_string_start and
9530 displacement_string_end are meaningful. */
9531 if (displacement_string_start != displacement_string_end)
9532 {
9533 if (!i386_displacement (displacement_string_start,
9534 displacement_string_end))
9535 return 0;
9536 }
9537
9538 /* Special case for (%dx) while doing input/output op. */
9539 if (i.base_reg
9540 && operand_type_equal (&i.base_reg->reg_type,
9541 &reg16_inoutportreg)
9542 && i.index_reg == 0
9543 && i.log2_scale_factor == 0
9544 && i.seg[i.mem_operands] == 0
9545 && !operand_type_check (i.types[this_operand], disp))
9546 {
9547 i.types[this_operand] = inoutportreg;
9548 return 1;
9549 }
9550
9551 if (i386_index_check (operand_string) == 0)
9552 return 0;
9553 i.types[this_operand].bitfield.mem = 1;
9554 if (i.mem_operands == 0)
9555 i.memop1_string = xstrdup (operand_string);
9556 i.mem_operands++;
9557 }
9558 else
9559 {
9560 /* It's not a memory operand; argh! */
9561 as_bad (_("invalid char %s beginning operand %d `%s'"),
9562 output_invalid (*op_string),
9563 this_operand + 1,
9564 op_string);
9565 return 0;
9566 }
9567 return 1; /* Normal return. */
9568 }
9569 \f
9570 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9571 that an rs_machine_dependent frag may reach. */
9572
9573 unsigned int
9574 i386_frag_max_var (fragS *frag)
9575 {
9576 /* The only relaxable frags are for jumps.
9577 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9578 gas_assert (frag->fr_type == rs_machine_dependent);
9579 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9580 }
9581
9582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9583 static int
9584 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9585 {
9586 /* STT_GNU_IFUNC symbol must go through PLT. */
9587 if ((symbol_get_bfdsym (fr_symbol)->flags
9588 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9589 return 0;
9590
9591 if (!S_IS_EXTERNAL (fr_symbol))
9592 /* Symbol may be weak or local. */
9593 return !S_IS_WEAK (fr_symbol);
9594
9595 /* Global symbols with non-default visibility can't be preempted. */
9596 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9597 return 1;
9598
9599 if (fr_var != NO_RELOC)
9600 switch ((enum bfd_reloc_code_real) fr_var)
9601 {
9602 case BFD_RELOC_386_PLT32:
9603 case BFD_RELOC_X86_64_PLT32:
9604 /* Symbol with PLT relocation may be preempted. */
9605 return 0;
9606 default:
9607 abort ();
9608 }
9609
9610 /* Global symbols with default visibility in a shared library may be
9611 preempted by another definition. */
9612 return !shared;
9613 }
9614 #endif
9615
9616 /* md_estimate_size_before_relax()
9617
9618 Called just before relax() for rs_machine_dependent frags. The x86
9619 assembler uses these frags to handle variable size jump
9620 instructions.
9621
9622 Any symbol that is now undefined will not become defined.
9623 Return the correct fr_subtype in the frag.
9624 Return the initial "guess for variable size of frag" to caller.
9625 The guess is actually the growth beyond the fixed part. Whatever
9626 we do to grow the fixed or variable part contributes to our
9627 returned value. */
9628
9629 int
9630 md_estimate_size_before_relax (fragS *fragP, segT segment)
9631 {
9632 /* We've already got fragP->fr_subtype right; all we have to do is
9633 check for un-relaxable symbols. On an ELF system, we can't relax
9634 an externally visible symbol, because it may be overridden by a
9635 shared library. */
9636 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9637 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9638 || (IS_ELF
9639 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9640 fragP->fr_var))
9641 #endif
9642 #if defined (OBJ_COFF) && defined (TE_PE)
9643 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9644 && S_IS_WEAK (fragP->fr_symbol))
9645 #endif
9646 )
9647 {
9648 /* Symbol is undefined in this segment, or we need to keep a
9649 reloc so that weak symbols can be overridden. */
9650 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9651 enum bfd_reloc_code_real reloc_type;
9652 unsigned char *opcode;
9653 int old_fr_fix;
9654
9655 if (fragP->fr_var != NO_RELOC)
9656 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9657 else if (size == 2)
9658 reloc_type = BFD_RELOC_16_PCREL;
9659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9660 else if (need_plt32_p (fragP->fr_symbol))
9661 reloc_type = BFD_RELOC_X86_64_PLT32;
9662 #endif
9663 else
9664 reloc_type = BFD_RELOC_32_PCREL;
9665
9666 old_fr_fix = fragP->fr_fix;
9667 opcode = (unsigned char *) fragP->fr_opcode;
9668
9669 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9670 {
9671 case UNCOND_JUMP:
9672 /* Make jmp (0xeb) a (d)word displacement jump. */
9673 opcode[0] = 0xe9;
9674 fragP->fr_fix += size;
9675 fix_new (fragP, old_fr_fix, size,
9676 fragP->fr_symbol,
9677 fragP->fr_offset, 1,
9678 reloc_type);
9679 break;
9680
9681 case COND_JUMP86:
9682 if (size == 2
9683 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9684 {
9685 /* Negate the condition, and branch past an
9686 unconditional jump. */
9687 opcode[0] ^= 1;
9688 opcode[1] = 3;
9689 /* Insert an unconditional jump. */
9690 opcode[2] = 0xe9;
9691 /* We added two extra opcode bytes, and have a two byte
9692 offset. */
9693 fragP->fr_fix += 2 + 2;
9694 fix_new (fragP, old_fr_fix + 2, 2,
9695 fragP->fr_symbol,
9696 fragP->fr_offset, 1,
9697 reloc_type);
9698 break;
9699 }
9700 /* Fall through. */
9701
9702 case COND_JUMP:
9703 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9704 {
9705 fixS *fixP;
9706
9707 fragP->fr_fix += 1;
9708 fixP = fix_new (fragP, old_fr_fix, 1,
9709 fragP->fr_symbol,
9710 fragP->fr_offset, 1,
9711 BFD_RELOC_8_PCREL);
9712 fixP->fx_signed = 1;
9713 break;
9714 }
9715
9716 /* This changes the byte-displacement jump 0x7N
9717 to the (d)word-displacement jump 0x0f,0x8N. */
9718 opcode[1] = opcode[0] + 0x10;
9719 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9720 /* We've added an opcode byte. */
9721 fragP->fr_fix += 1 + size;
9722 fix_new (fragP, old_fr_fix + 1, size,
9723 fragP->fr_symbol,
9724 fragP->fr_offset, 1,
9725 reloc_type);
9726 break;
9727
9728 default:
9729 BAD_CASE (fragP->fr_subtype);
9730 break;
9731 }
9732 frag_wane (fragP);
9733 return fragP->fr_fix - old_fr_fix;
9734 }
9735
9736 /* Guess size depending on current relax state. Initially the relax
9737 state will correspond to a short jump and we return 1, because
9738 the variable part of the frag (the branch offset) is one byte
9739 long. However, we can relax a section more than once and in that
9740 case we must either set fr_subtype back to the unrelaxed state,
9741 or return the value for the appropriate branch. */
9742 return md_relax_table[fragP->fr_subtype].rlx_length;
9743 }
9744
9745 /* Called after relax() is finished.
9746
9747 In: Address of frag.
9748 fr_type == rs_machine_dependent.
9749 fr_subtype is what the address relaxed to.
9750
9751 Out: Any fixSs and constants are set up.
9752 Caller will turn frag into a ".space 0". */
9753
9754 void
9755 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9756 fragS *fragP)
9757 {
9758 unsigned char *opcode;
9759 unsigned char *where_to_put_displacement = NULL;
9760 offsetT target_address;
9761 offsetT opcode_address;
9762 unsigned int extension = 0;
9763 offsetT displacement_from_opcode_start;
9764
9765 opcode = (unsigned char *) fragP->fr_opcode;
9766
9767 /* Address we want to reach in file space. */
9768 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9769
9770 /* Address opcode resides at in file space. */
9771 opcode_address = fragP->fr_address + fragP->fr_fix;
9772
9773 /* Displacement from opcode start to fill into instruction. */
9774 displacement_from_opcode_start = target_address - opcode_address;
9775
9776 if ((fragP->fr_subtype & BIG) == 0)
9777 {
9778 /* Don't have to change opcode. */
9779 extension = 1; /* 1 opcode + 1 displacement */
9780 where_to_put_displacement = &opcode[1];
9781 }
9782 else
9783 {
9784 if (no_cond_jump_promotion
9785 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9786 as_warn_where (fragP->fr_file, fragP->fr_line,
9787 _("long jump required"));
9788
9789 switch (fragP->fr_subtype)
9790 {
9791 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9792 extension = 4; /* 1 opcode + 4 displacement */
9793 opcode[0] = 0xe9;
9794 where_to_put_displacement = &opcode[1];
9795 break;
9796
9797 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9798 extension = 2; /* 1 opcode + 2 displacement */
9799 opcode[0] = 0xe9;
9800 where_to_put_displacement = &opcode[1];
9801 break;
9802
9803 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9804 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9805 extension = 5; /* 2 opcode + 4 displacement */
9806 opcode[1] = opcode[0] + 0x10;
9807 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9808 where_to_put_displacement = &opcode[2];
9809 break;
9810
9811 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9812 extension = 3; /* 2 opcode + 2 displacement */
9813 opcode[1] = opcode[0] + 0x10;
9814 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9815 where_to_put_displacement = &opcode[2];
9816 break;
9817
9818 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9819 extension = 4;
9820 opcode[0] ^= 1;
9821 opcode[1] = 3;
9822 opcode[2] = 0xe9;
9823 where_to_put_displacement = &opcode[3];
9824 break;
9825
9826 default:
9827 BAD_CASE (fragP->fr_subtype);
9828 break;
9829 }
9830 }
9831
9832 /* If size if less then four we are sure that the operand fits,
9833 but if it's 4, then it could be that the displacement is larger
9834 then -/+ 2GB. */
9835 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9836 && object_64bit
9837 && ((addressT) (displacement_from_opcode_start - extension
9838 + ((addressT) 1 << 31))
9839 > (((addressT) 2 << 31) - 1)))
9840 {
9841 as_bad_where (fragP->fr_file, fragP->fr_line,
9842 _("jump target out of range"));
9843 /* Make us emit 0. */
9844 displacement_from_opcode_start = extension;
9845 }
9846 /* Now put displacement after opcode. */
9847 md_number_to_chars ((char *) where_to_put_displacement,
9848 (valueT) (displacement_from_opcode_start - extension),
9849 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9850 fragP->fr_fix += extension;
9851 }
9852 \f
9853 /* Apply a fixup (fixP) to segment data, once it has been determined
9854 by our caller that we have all the info we need to fix it up.
9855
9856 Parameter valP is the pointer to the value of the bits.
9857
9858 On the 386, immediates, displacements, and data pointers are all in
9859 the same (little-endian) format, so we don't need to care about which
9860 we are handling. */
9861
9862 void
9863 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9864 {
9865 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9866 valueT value = *valP;
9867
9868 #if !defined (TE_Mach)
9869 if (fixP->fx_pcrel)
9870 {
9871 switch (fixP->fx_r_type)
9872 {
9873 default:
9874 break;
9875
9876 case BFD_RELOC_64:
9877 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9878 break;
9879 case BFD_RELOC_32:
9880 case BFD_RELOC_X86_64_32S:
9881 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9882 break;
9883 case BFD_RELOC_16:
9884 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9885 break;
9886 case BFD_RELOC_8:
9887 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9888 break;
9889 }
9890 }
9891
9892 if (fixP->fx_addsy != NULL
9893 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9894 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9895 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9896 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9897 && !use_rela_relocations)
9898 {
9899 /* This is a hack. There should be a better way to handle this.
9900 This covers for the fact that bfd_install_relocation will
9901 subtract the current location (for partial_inplace, PC relative
9902 relocations); see more below. */
9903 #ifndef OBJ_AOUT
9904 if (IS_ELF
9905 #ifdef TE_PE
9906 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9907 #endif
9908 )
9909 value += fixP->fx_where + fixP->fx_frag->fr_address;
9910 #endif
9911 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9912 if (IS_ELF)
9913 {
9914 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9915
9916 if ((sym_seg == seg
9917 || (symbol_section_p (fixP->fx_addsy)
9918 && sym_seg != absolute_section))
9919 && !generic_force_reloc (fixP))
9920 {
9921 /* Yes, we add the values in twice. This is because
9922 bfd_install_relocation subtracts them out again. I think
9923 bfd_install_relocation is broken, but I don't dare change
9924 it. FIXME. */
9925 value += fixP->fx_where + fixP->fx_frag->fr_address;
9926 }
9927 }
9928 #endif
9929 #if defined (OBJ_COFF) && defined (TE_PE)
9930 /* For some reason, the PE format does not store a
9931 section address offset for a PC relative symbol. */
9932 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9933 || S_IS_WEAK (fixP->fx_addsy))
9934 value += md_pcrel_from (fixP);
9935 #endif
9936 }
9937 #if defined (OBJ_COFF) && defined (TE_PE)
9938 if (fixP->fx_addsy != NULL
9939 && S_IS_WEAK (fixP->fx_addsy)
9940 /* PR 16858: Do not modify weak function references. */
9941 && ! fixP->fx_pcrel)
9942 {
9943 #if !defined (TE_PEP)
9944 /* For x86 PE weak function symbols are neither PC-relative
9945 nor do they set S_IS_FUNCTION. So the only reliable way
9946 to detect them is to check the flags of their containing
9947 section. */
9948 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9949 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9950 ;
9951 else
9952 #endif
9953 value -= S_GET_VALUE (fixP->fx_addsy);
9954 }
9955 #endif
9956
9957 /* Fix a few things - the dynamic linker expects certain values here,
9958 and we must not disappoint it. */
9959 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9960 if (IS_ELF && fixP->fx_addsy)
9961 switch (fixP->fx_r_type)
9962 {
9963 case BFD_RELOC_386_PLT32:
9964 case BFD_RELOC_X86_64_PLT32:
9965 /* Make the jump instruction point to the address of the operand. At
9966 runtime we merely add the offset to the actual PLT entry. */
9967 value = -4;
9968 break;
9969
9970 case BFD_RELOC_386_TLS_GD:
9971 case BFD_RELOC_386_TLS_LDM:
9972 case BFD_RELOC_386_TLS_IE_32:
9973 case BFD_RELOC_386_TLS_IE:
9974 case BFD_RELOC_386_TLS_GOTIE:
9975 case BFD_RELOC_386_TLS_GOTDESC:
9976 case BFD_RELOC_X86_64_TLSGD:
9977 case BFD_RELOC_X86_64_TLSLD:
9978 case BFD_RELOC_X86_64_GOTTPOFF:
9979 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9980 value = 0; /* Fully resolved at runtime. No addend. */
9981 /* Fallthrough */
9982 case BFD_RELOC_386_TLS_LE:
9983 case BFD_RELOC_386_TLS_LDO_32:
9984 case BFD_RELOC_386_TLS_LE_32:
9985 case BFD_RELOC_X86_64_DTPOFF32:
9986 case BFD_RELOC_X86_64_DTPOFF64:
9987 case BFD_RELOC_X86_64_TPOFF32:
9988 case BFD_RELOC_X86_64_TPOFF64:
9989 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9990 break;
9991
9992 case BFD_RELOC_386_TLS_DESC_CALL:
9993 case BFD_RELOC_X86_64_TLSDESC_CALL:
9994 value = 0; /* Fully resolved at runtime. No addend. */
9995 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9996 fixP->fx_done = 0;
9997 return;
9998
9999 case BFD_RELOC_VTABLE_INHERIT:
10000 case BFD_RELOC_VTABLE_ENTRY:
10001 fixP->fx_done = 0;
10002 return;
10003
10004 default:
10005 break;
10006 }
10007 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10008 *valP = value;
10009 #endif /* !defined (TE_Mach) */
10010
10011 /* Are we finished with this relocation now? */
10012 if (fixP->fx_addsy == NULL)
10013 fixP->fx_done = 1;
10014 #if defined (OBJ_COFF) && defined (TE_PE)
10015 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10016 {
10017 fixP->fx_done = 0;
10018 /* Remember value for tc_gen_reloc. */
10019 fixP->fx_addnumber = value;
10020 /* Clear out the frag for now. */
10021 value = 0;
10022 }
10023 #endif
10024 else if (use_rela_relocations)
10025 {
10026 fixP->fx_no_overflow = 1;
10027 /* Remember value for tc_gen_reloc. */
10028 fixP->fx_addnumber = value;
10029 value = 0;
10030 }
10031
10032 md_number_to_chars (p, value, fixP->fx_size);
10033 }
10034 \f
10035 const char *
10036 md_atof (int type, char *litP, int *sizeP)
10037 {
10038 /* This outputs the LITTLENUMs in REVERSE order;
10039 in accord with the bigendian 386. */
10040 return ieee_md_atof (type, litP, sizeP, FALSE);
10041 }
10042 \f
10043 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10044
10045 static char *
10046 output_invalid (int c)
10047 {
10048 if (ISPRINT (c))
10049 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10050 "'%c'", c);
10051 else
10052 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10053 "(0x%x)", (unsigned char) c);
10054 return output_invalid_buf;
10055 }
10056
10057 /* REG_STRING starts *before* REGISTER_PREFIX. */
10058
10059 static const reg_entry *
10060 parse_real_register (char *reg_string, char **end_op)
10061 {
10062 char *s = reg_string;
10063 char *p;
10064 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10065 const reg_entry *r;
10066
10067 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10068 if (*s == REGISTER_PREFIX)
10069 ++s;
10070
10071 if (is_space_char (*s))
10072 ++s;
10073
10074 p = reg_name_given;
10075 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10076 {
10077 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10078 return (const reg_entry *) NULL;
10079 s++;
10080 }
10081
10082 /* For naked regs, make sure that we are not dealing with an identifier.
10083 This prevents confusing an identifier like `eax_var' with register
10084 `eax'. */
10085 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10086 return (const reg_entry *) NULL;
10087
10088 *end_op = s;
10089
10090 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10091
10092 /* Handle floating point regs, allowing spaces in the (i) part. */
10093 if (r == i386_regtab /* %st is first entry of table */)
10094 {
10095 if (is_space_char (*s))
10096 ++s;
10097 if (*s == '(')
10098 {
10099 ++s;
10100 if (is_space_char (*s))
10101 ++s;
10102 if (*s >= '0' && *s <= '7')
10103 {
10104 int fpr = *s - '0';
10105 ++s;
10106 if (is_space_char (*s))
10107 ++s;
10108 if (*s == ')')
10109 {
10110 *end_op = s + 1;
10111 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10112 know (r);
10113 return r + fpr;
10114 }
10115 }
10116 /* We have "%st(" then garbage. */
10117 return (const reg_entry *) NULL;
10118 }
10119 }
10120
10121 if (r == NULL || allow_pseudo_reg)
10122 return r;
10123
10124 if (operand_type_all_zero (&r->reg_type))
10125 return (const reg_entry *) NULL;
10126
10127 if ((r->reg_type.bitfield.dword
10128 || r->reg_type.bitfield.sreg3
10129 || r->reg_type.bitfield.control
10130 || r->reg_type.bitfield.debug
10131 || r->reg_type.bitfield.test)
10132 && !cpu_arch_flags.bitfield.cpui386)
10133 return (const reg_entry *) NULL;
10134
10135 if (r->reg_type.bitfield.tbyte
10136 && !cpu_arch_flags.bitfield.cpu8087
10137 && !cpu_arch_flags.bitfield.cpu287
10138 && !cpu_arch_flags.bitfield.cpu387)
10139 return (const reg_entry *) NULL;
10140
10141 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
10142 return (const reg_entry *) NULL;
10143
10144 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
10145 return (const reg_entry *) NULL;
10146
10147 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
10148 return (const reg_entry *) NULL;
10149
10150 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
10151 return (const reg_entry *) NULL;
10152
10153 if (r->reg_type.bitfield.regmask
10154 && !cpu_arch_flags.bitfield.cpuregmask)
10155 return (const reg_entry *) NULL;
10156
10157 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10158 if (!allow_index_reg
10159 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10160 return (const reg_entry *) NULL;
10161
10162 /* Upper 16 vector register is only available with VREX in 64bit
10163 mode. */
10164 if ((r->reg_flags & RegVRex))
10165 {
10166 if (i.vec_encoding == vex_encoding_default)
10167 i.vec_encoding = vex_encoding_evex;
10168
10169 if (!cpu_arch_flags.bitfield.cpuvrex
10170 || i.vec_encoding != vex_encoding_evex
10171 || flag_code != CODE_64BIT)
10172 return (const reg_entry *) NULL;
10173 }
10174
10175 if (((r->reg_flags & (RegRex64 | RegRex))
10176 || r->reg_type.bitfield.qword)
10177 && (!cpu_arch_flags.bitfield.cpulm
10178 || !operand_type_equal (&r->reg_type, &control))
10179 && flag_code != CODE_64BIT)
10180 return (const reg_entry *) NULL;
10181
10182 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10183 return (const reg_entry *) NULL;
10184
10185 return r;
10186 }
10187
10188 /* REG_STRING starts *before* REGISTER_PREFIX. */
10189
10190 static const reg_entry *
10191 parse_register (char *reg_string, char **end_op)
10192 {
10193 const reg_entry *r;
10194
10195 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10196 r = parse_real_register (reg_string, end_op);
10197 else
10198 r = NULL;
10199 if (!r)
10200 {
10201 char *save = input_line_pointer;
10202 char c;
10203 symbolS *symbolP;
10204
10205 input_line_pointer = reg_string;
10206 c = get_symbol_name (&reg_string);
10207 symbolP = symbol_find (reg_string);
10208 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10209 {
10210 const expressionS *e = symbol_get_value_expression (symbolP);
10211
10212 know (e->X_op == O_register);
10213 know (e->X_add_number >= 0
10214 && (valueT) e->X_add_number < i386_regtab_size);
10215 r = i386_regtab + e->X_add_number;
10216 if ((r->reg_flags & RegVRex))
10217 i.vec_encoding = vex_encoding_evex;
10218 *end_op = input_line_pointer;
10219 }
10220 *input_line_pointer = c;
10221 input_line_pointer = save;
10222 }
10223 return r;
10224 }
10225
10226 int
10227 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10228 {
10229 const reg_entry *r;
10230 char *end = input_line_pointer;
10231
10232 *end = *nextcharP;
10233 r = parse_register (name, &input_line_pointer);
10234 if (r && end <= input_line_pointer)
10235 {
10236 *nextcharP = *input_line_pointer;
10237 *input_line_pointer = 0;
10238 e->X_op = O_register;
10239 e->X_add_number = r - i386_regtab;
10240 return 1;
10241 }
10242 input_line_pointer = end;
10243 *end = 0;
10244 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10245 }
10246
10247 void
10248 md_operand (expressionS *e)
10249 {
10250 char *end;
10251 const reg_entry *r;
10252
10253 switch (*input_line_pointer)
10254 {
10255 case REGISTER_PREFIX:
10256 r = parse_real_register (input_line_pointer, &end);
10257 if (r)
10258 {
10259 e->X_op = O_register;
10260 e->X_add_number = r - i386_regtab;
10261 input_line_pointer = end;
10262 }
10263 break;
10264
10265 case '[':
10266 gas_assert (intel_syntax);
10267 end = input_line_pointer++;
10268 expression (e);
10269 if (*input_line_pointer == ']')
10270 {
10271 ++input_line_pointer;
10272 e->X_op_symbol = make_expr_symbol (e);
10273 e->X_add_symbol = NULL;
10274 e->X_add_number = 0;
10275 e->X_op = O_index;
10276 }
10277 else
10278 {
10279 e->X_op = O_absent;
10280 input_line_pointer = end;
10281 }
10282 break;
10283 }
10284 }
10285
10286 \f
10287 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10288 const char *md_shortopts = "kVQ:sqnO::";
10289 #else
10290 const char *md_shortopts = "qnO::";
10291 #endif
10292
10293 #define OPTION_32 (OPTION_MD_BASE + 0)
10294 #define OPTION_64 (OPTION_MD_BASE + 1)
10295 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10296 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10297 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10298 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10299 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10300 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10301 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10302 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10303 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10304 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10305 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10306 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10307 #define OPTION_X32 (OPTION_MD_BASE + 14)
10308 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10309 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10310 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10311 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10312 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10313 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10314 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10315 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10316 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10317 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10318 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10319
10320 struct option md_longopts[] =
10321 {
10322 {"32", no_argument, NULL, OPTION_32},
10323 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10324 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10325 {"64", no_argument, NULL, OPTION_64},
10326 #endif
10327 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10328 {"x32", no_argument, NULL, OPTION_X32},
10329 {"mshared", no_argument, NULL, OPTION_MSHARED},
10330 #endif
10331 {"divide", no_argument, NULL, OPTION_DIVIDE},
10332 {"march", required_argument, NULL, OPTION_MARCH},
10333 {"mtune", required_argument, NULL, OPTION_MTUNE},
10334 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10335 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10336 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10337 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10338 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10339 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10340 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10341 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10342 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10343 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10344 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10345 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10346 # if defined (TE_PE) || defined (TE_PEP)
10347 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10348 #endif
10349 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10350 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10351 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10352 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10353 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10354 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10355 {NULL, no_argument, NULL, 0}
10356 };
10357 size_t md_longopts_size = sizeof (md_longopts);
10358
10359 int
10360 md_parse_option (int c, const char *arg)
10361 {
10362 unsigned int j;
10363 char *arch, *next, *saved;
10364
10365 switch (c)
10366 {
10367 case 'n':
10368 optimize_align_code = 0;
10369 break;
10370
10371 case 'q':
10372 quiet_warnings = 1;
10373 break;
10374
10375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10376 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10377 should be emitted or not. FIXME: Not implemented. */
10378 case 'Q':
10379 break;
10380
10381 /* -V: SVR4 argument to print version ID. */
10382 case 'V':
10383 print_version_id ();
10384 break;
10385
10386 /* -k: Ignore for FreeBSD compatibility. */
10387 case 'k':
10388 break;
10389
10390 case 's':
10391 /* -s: On i386 Solaris, this tells the native assembler to use
10392 .stab instead of .stab.excl. We always use .stab anyhow. */
10393 break;
10394
10395 case OPTION_MSHARED:
10396 shared = 1;
10397 break;
10398 #endif
10399 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10400 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10401 case OPTION_64:
10402 {
10403 const char **list, **l;
10404
10405 list = bfd_target_list ();
10406 for (l = list; *l != NULL; l++)
10407 if (CONST_STRNEQ (*l, "elf64-x86-64")
10408 || strcmp (*l, "coff-x86-64") == 0
10409 || strcmp (*l, "pe-x86-64") == 0
10410 || strcmp (*l, "pei-x86-64") == 0
10411 || strcmp (*l, "mach-o-x86-64") == 0)
10412 {
10413 default_arch = "x86_64";
10414 break;
10415 }
10416 if (*l == NULL)
10417 as_fatal (_("no compiled in support for x86_64"));
10418 free (list);
10419 }
10420 break;
10421 #endif
10422
10423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10424 case OPTION_X32:
10425 if (IS_ELF)
10426 {
10427 const char **list, **l;
10428
10429 list = bfd_target_list ();
10430 for (l = list; *l != NULL; l++)
10431 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10432 {
10433 default_arch = "x86_64:32";
10434 break;
10435 }
10436 if (*l == NULL)
10437 as_fatal (_("no compiled in support for 32bit x86_64"));
10438 free (list);
10439 }
10440 else
10441 as_fatal (_("32bit x86_64 is only supported for ELF"));
10442 break;
10443 #endif
10444
10445 case OPTION_32:
10446 default_arch = "i386";
10447 break;
10448
10449 case OPTION_DIVIDE:
10450 #ifdef SVR4_COMMENT_CHARS
10451 {
10452 char *n, *t;
10453 const char *s;
10454
10455 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10456 t = n;
10457 for (s = i386_comment_chars; *s != '\0'; s++)
10458 if (*s != '/')
10459 *t++ = *s;
10460 *t = '\0';
10461 i386_comment_chars = n;
10462 }
10463 #endif
10464 break;
10465
10466 case OPTION_MARCH:
10467 saved = xstrdup (arg);
10468 arch = saved;
10469 /* Allow -march=+nosse. */
10470 if (*arch == '+')
10471 arch++;
10472 do
10473 {
10474 if (*arch == '.')
10475 as_fatal (_("invalid -march= option: `%s'"), arg);
10476 next = strchr (arch, '+');
10477 if (next)
10478 *next++ = '\0';
10479 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10480 {
10481 if (strcmp (arch, cpu_arch [j].name) == 0)
10482 {
10483 /* Processor. */
10484 if (! cpu_arch[j].flags.bitfield.cpui386)
10485 continue;
10486
10487 cpu_arch_name = cpu_arch[j].name;
10488 cpu_sub_arch_name = NULL;
10489 cpu_arch_flags = cpu_arch[j].flags;
10490 cpu_arch_isa = cpu_arch[j].type;
10491 cpu_arch_isa_flags = cpu_arch[j].flags;
10492 if (!cpu_arch_tune_set)
10493 {
10494 cpu_arch_tune = cpu_arch_isa;
10495 cpu_arch_tune_flags = cpu_arch_isa_flags;
10496 }
10497 break;
10498 }
10499 else if (*cpu_arch [j].name == '.'
10500 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10501 {
10502 /* ISA extension. */
10503 i386_cpu_flags flags;
10504
10505 flags = cpu_flags_or (cpu_arch_flags,
10506 cpu_arch[j].flags);
10507
10508 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10509 {
10510 if (cpu_sub_arch_name)
10511 {
10512 char *name = cpu_sub_arch_name;
10513 cpu_sub_arch_name = concat (name,
10514 cpu_arch[j].name,
10515 (const char *) NULL);
10516 free (name);
10517 }
10518 else
10519 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10520 cpu_arch_flags = flags;
10521 cpu_arch_isa_flags = flags;
10522 }
10523 break;
10524 }
10525 }
10526
10527 if (j >= ARRAY_SIZE (cpu_arch))
10528 {
10529 /* Disable an ISA extension. */
10530 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10531 if (strcmp (arch, cpu_noarch [j].name) == 0)
10532 {
10533 i386_cpu_flags flags;
10534
10535 flags = cpu_flags_and_not (cpu_arch_flags,
10536 cpu_noarch[j].flags);
10537 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10538 {
10539 if (cpu_sub_arch_name)
10540 {
10541 char *name = cpu_sub_arch_name;
10542 cpu_sub_arch_name = concat (arch,
10543 (const char *) NULL);
10544 free (name);
10545 }
10546 else
10547 cpu_sub_arch_name = xstrdup (arch);
10548 cpu_arch_flags = flags;
10549 cpu_arch_isa_flags = flags;
10550 }
10551 break;
10552 }
10553
10554 if (j >= ARRAY_SIZE (cpu_noarch))
10555 j = ARRAY_SIZE (cpu_arch);
10556 }
10557
10558 if (j >= ARRAY_SIZE (cpu_arch))
10559 as_fatal (_("invalid -march= option: `%s'"), arg);
10560
10561 arch = next;
10562 }
10563 while (next != NULL);
10564 free (saved);
10565 break;
10566
10567 case OPTION_MTUNE:
10568 if (*arg == '.')
10569 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10570 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10571 {
10572 if (strcmp (arg, cpu_arch [j].name) == 0)
10573 {
10574 cpu_arch_tune_set = 1;
10575 cpu_arch_tune = cpu_arch [j].type;
10576 cpu_arch_tune_flags = cpu_arch[j].flags;
10577 break;
10578 }
10579 }
10580 if (j >= ARRAY_SIZE (cpu_arch))
10581 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10582 break;
10583
10584 case OPTION_MMNEMONIC:
10585 if (strcasecmp (arg, "att") == 0)
10586 intel_mnemonic = 0;
10587 else if (strcasecmp (arg, "intel") == 0)
10588 intel_mnemonic = 1;
10589 else
10590 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10591 break;
10592
10593 case OPTION_MSYNTAX:
10594 if (strcasecmp (arg, "att") == 0)
10595 intel_syntax = 0;
10596 else if (strcasecmp (arg, "intel") == 0)
10597 intel_syntax = 1;
10598 else
10599 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10600 break;
10601
10602 case OPTION_MINDEX_REG:
10603 allow_index_reg = 1;
10604 break;
10605
10606 case OPTION_MNAKED_REG:
10607 allow_naked_reg = 1;
10608 break;
10609
10610 case OPTION_MOLD_GCC:
10611 old_gcc = 1;
10612 break;
10613
10614 case OPTION_MSSE2AVX:
10615 sse2avx = 1;
10616 break;
10617
10618 case OPTION_MSSE_CHECK:
10619 if (strcasecmp (arg, "error") == 0)
10620 sse_check = check_error;
10621 else if (strcasecmp (arg, "warning") == 0)
10622 sse_check = check_warning;
10623 else if (strcasecmp (arg, "none") == 0)
10624 sse_check = check_none;
10625 else
10626 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10627 break;
10628
10629 case OPTION_MOPERAND_CHECK:
10630 if (strcasecmp (arg, "error") == 0)
10631 operand_check = check_error;
10632 else if (strcasecmp (arg, "warning") == 0)
10633 operand_check = check_warning;
10634 else if (strcasecmp (arg, "none") == 0)
10635 operand_check = check_none;
10636 else
10637 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10638 break;
10639
10640 case OPTION_MAVXSCALAR:
10641 if (strcasecmp (arg, "128") == 0)
10642 avxscalar = vex128;
10643 else if (strcasecmp (arg, "256") == 0)
10644 avxscalar = vex256;
10645 else
10646 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10647 break;
10648
10649 case OPTION_MADD_BND_PREFIX:
10650 add_bnd_prefix = 1;
10651 break;
10652
10653 case OPTION_MEVEXLIG:
10654 if (strcmp (arg, "128") == 0)
10655 evexlig = evexl128;
10656 else if (strcmp (arg, "256") == 0)
10657 evexlig = evexl256;
10658 else if (strcmp (arg, "512") == 0)
10659 evexlig = evexl512;
10660 else
10661 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10662 break;
10663
10664 case OPTION_MEVEXRCIG:
10665 if (strcmp (arg, "rne") == 0)
10666 evexrcig = rne;
10667 else if (strcmp (arg, "rd") == 0)
10668 evexrcig = rd;
10669 else if (strcmp (arg, "ru") == 0)
10670 evexrcig = ru;
10671 else if (strcmp (arg, "rz") == 0)
10672 evexrcig = rz;
10673 else
10674 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10675 break;
10676
10677 case OPTION_MEVEXWIG:
10678 if (strcmp (arg, "0") == 0)
10679 evexwig = evexw0;
10680 else if (strcmp (arg, "1") == 0)
10681 evexwig = evexw1;
10682 else
10683 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10684 break;
10685
10686 # if defined (TE_PE) || defined (TE_PEP)
10687 case OPTION_MBIG_OBJ:
10688 use_big_obj = 1;
10689 break;
10690 #endif
10691
10692 case OPTION_MOMIT_LOCK_PREFIX:
10693 if (strcasecmp (arg, "yes") == 0)
10694 omit_lock_prefix = 1;
10695 else if (strcasecmp (arg, "no") == 0)
10696 omit_lock_prefix = 0;
10697 else
10698 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10699 break;
10700
10701 case OPTION_MFENCE_AS_LOCK_ADD:
10702 if (strcasecmp (arg, "yes") == 0)
10703 avoid_fence = 1;
10704 else if (strcasecmp (arg, "no") == 0)
10705 avoid_fence = 0;
10706 else
10707 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10708 break;
10709
10710 case OPTION_MRELAX_RELOCATIONS:
10711 if (strcasecmp (arg, "yes") == 0)
10712 generate_relax_relocations = 1;
10713 else if (strcasecmp (arg, "no") == 0)
10714 generate_relax_relocations = 0;
10715 else
10716 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10717 break;
10718
10719 case OPTION_MAMD64:
10720 intel64 = 0;
10721 break;
10722
10723 case OPTION_MINTEL64:
10724 intel64 = 1;
10725 break;
10726
10727 case 'O':
10728 if (arg == NULL)
10729 {
10730 optimize = 1;
10731 /* Turn off -Os. */
10732 optimize_for_space = 0;
10733 }
10734 else if (*arg == 's')
10735 {
10736 optimize_for_space = 1;
10737 /* Turn on all encoding optimizations. */
10738 optimize = -1;
10739 }
10740 else
10741 {
10742 optimize = atoi (arg);
10743 /* Turn off -Os. */
10744 optimize_for_space = 0;
10745 }
10746 break;
10747
10748 default:
10749 return 0;
10750 }
10751 return 1;
10752 }
10753
10754 #define MESSAGE_TEMPLATE \
10755 " "
10756
10757 static char *
10758 output_message (FILE *stream, char *p, char *message, char *start,
10759 int *left_p, const char *name, int len)
10760 {
10761 int size = sizeof (MESSAGE_TEMPLATE);
10762 int left = *left_p;
10763
10764 /* Reserve 2 spaces for ", " or ",\0" */
10765 left -= len + 2;
10766
10767 /* Check if there is any room. */
10768 if (left >= 0)
10769 {
10770 if (p != start)
10771 {
10772 *p++ = ',';
10773 *p++ = ' ';
10774 }
10775 p = mempcpy (p, name, len);
10776 }
10777 else
10778 {
10779 /* Output the current message now and start a new one. */
10780 *p++ = ',';
10781 *p = '\0';
10782 fprintf (stream, "%s\n", message);
10783 p = start;
10784 left = size - (start - message) - len - 2;
10785
10786 gas_assert (left >= 0);
10787
10788 p = mempcpy (p, name, len);
10789 }
10790
10791 *left_p = left;
10792 return p;
10793 }
10794
10795 static void
10796 show_arch (FILE *stream, int ext, int check)
10797 {
10798 static char message[] = MESSAGE_TEMPLATE;
10799 char *start = message + 27;
10800 char *p;
10801 int size = sizeof (MESSAGE_TEMPLATE);
10802 int left;
10803 const char *name;
10804 int len;
10805 unsigned int j;
10806
10807 p = start;
10808 left = size - (start - message);
10809 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10810 {
10811 /* Should it be skipped? */
10812 if (cpu_arch [j].skip)
10813 continue;
10814
10815 name = cpu_arch [j].name;
10816 len = cpu_arch [j].len;
10817 if (*name == '.')
10818 {
10819 /* It is an extension. Skip if we aren't asked to show it. */
10820 if (ext)
10821 {
10822 name++;
10823 len--;
10824 }
10825 else
10826 continue;
10827 }
10828 else if (ext)
10829 {
10830 /* It is an processor. Skip if we show only extension. */
10831 continue;
10832 }
10833 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10834 {
10835 /* It is an impossible processor - skip. */
10836 continue;
10837 }
10838
10839 p = output_message (stream, p, message, start, &left, name, len);
10840 }
10841
10842 /* Display disabled extensions. */
10843 if (ext)
10844 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10845 {
10846 name = cpu_noarch [j].name;
10847 len = cpu_noarch [j].len;
10848 p = output_message (stream, p, message, start, &left, name,
10849 len);
10850 }
10851
10852 *p = '\0';
10853 fprintf (stream, "%s\n", message);
10854 }
10855
10856 void
10857 md_show_usage (FILE *stream)
10858 {
10859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10860 fprintf (stream, _("\
10861 -Q ignored\n\
10862 -V print assembler version number\n\
10863 -k ignored\n"));
10864 #endif
10865 fprintf (stream, _("\
10866 -n Do not optimize code alignment\n\
10867 -q quieten some warnings\n"));
10868 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10869 fprintf (stream, _("\
10870 -s ignored\n"));
10871 #endif
10872 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10873 || defined (TE_PE) || defined (TE_PEP))
10874 fprintf (stream, _("\
10875 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10876 #endif
10877 #ifdef SVR4_COMMENT_CHARS
10878 fprintf (stream, _("\
10879 --divide do not treat `/' as a comment character\n"));
10880 #else
10881 fprintf (stream, _("\
10882 --divide ignored\n"));
10883 #endif
10884 fprintf (stream, _("\
10885 -march=CPU[,+EXTENSION...]\n\
10886 generate code for CPU and EXTENSION, CPU is one of:\n"));
10887 show_arch (stream, 0, 1);
10888 fprintf (stream, _("\
10889 EXTENSION is combination of:\n"));
10890 show_arch (stream, 1, 0);
10891 fprintf (stream, _("\
10892 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10893 show_arch (stream, 0, 0);
10894 fprintf (stream, _("\
10895 -msse2avx encode SSE instructions with VEX prefix\n"));
10896 fprintf (stream, _("\
10897 -msse-check=[none|error|warning]\n\
10898 check SSE instructions\n"));
10899 fprintf (stream, _("\
10900 -moperand-check=[none|error|warning]\n\
10901 check operand combinations for validity\n"));
10902 fprintf (stream, _("\
10903 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10904 length\n"));
10905 fprintf (stream, _("\
10906 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10907 length\n"));
10908 fprintf (stream, _("\
10909 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10910 for EVEX.W bit ignored instructions\n"));
10911 fprintf (stream, _("\
10912 -mevexrcig=[rne|rd|ru|rz]\n\
10913 encode EVEX instructions with specific EVEX.RC value\n\
10914 for SAE-only ignored instructions\n"));
10915 fprintf (stream, _("\
10916 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10917 fprintf (stream, _("\
10918 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10919 fprintf (stream, _("\
10920 -mindex-reg support pseudo index registers\n"));
10921 fprintf (stream, _("\
10922 -mnaked-reg don't require `%%' prefix for registers\n"));
10923 fprintf (stream, _("\
10924 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10925 fprintf (stream, _("\
10926 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10927 fprintf (stream, _("\
10928 -mshared disable branch optimization for shared code\n"));
10929 # if defined (TE_PE) || defined (TE_PEP)
10930 fprintf (stream, _("\
10931 -mbig-obj generate big object files\n"));
10932 #endif
10933 fprintf (stream, _("\
10934 -momit-lock-prefix=[no|yes]\n\
10935 strip all lock prefixes\n"));
10936 fprintf (stream, _("\
10937 -mfence-as-lock-add=[no|yes]\n\
10938 encode lfence, mfence and sfence as\n\
10939 lock addl $0x0, (%%{re}sp)\n"));
10940 fprintf (stream, _("\
10941 -mrelax-relocations=[no|yes]\n\
10942 generate relax relocations\n"));
10943 fprintf (stream, _("\
10944 -mamd64 accept only AMD64 ISA\n"));
10945 fprintf (stream, _("\
10946 -mintel64 accept only Intel64 ISA\n"));
10947 }
10948
10949 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10950 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10951 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10952
10953 /* Pick the target format to use. */
10954
10955 const char *
10956 i386_target_format (void)
10957 {
10958 if (!strncmp (default_arch, "x86_64", 6))
10959 {
10960 update_code_flag (CODE_64BIT, 1);
10961 if (default_arch[6] == '\0')
10962 x86_elf_abi = X86_64_ABI;
10963 else
10964 x86_elf_abi = X86_64_X32_ABI;
10965 }
10966 else if (!strcmp (default_arch, "i386"))
10967 update_code_flag (CODE_32BIT, 1);
10968 else if (!strcmp (default_arch, "iamcu"))
10969 {
10970 update_code_flag (CODE_32BIT, 1);
10971 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10972 {
10973 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10974 cpu_arch_name = "iamcu";
10975 cpu_sub_arch_name = NULL;
10976 cpu_arch_flags = iamcu_flags;
10977 cpu_arch_isa = PROCESSOR_IAMCU;
10978 cpu_arch_isa_flags = iamcu_flags;
10979 if (!cpu_arch_tune_set)
10980 {
10981 cpu_arch_tune = cpu_arch_isa;
10982 cpu_arch_tune_flags = cpu_arch_isa_flags;
10983 }
10984 }
10985 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10986 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10987 cpu_arch_name);
10988 }
10989 else
10990 as_fatal (_("unknown architecture"));
10991
10992 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10993 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10994 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10995 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10996
10997 switch (OUTPUT_FLAVOR)
10998 {
10999 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11000 case bfd_target_aout_flavour:
11001 return AOUT_TARGET_FORMAT;
11002 #endif
11003 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11004 # if defined (TE_PE) || defined (TE_PEP)
11005 case bfd_target_coff_flavour:
11006 if (flag_code == CODE_64BIT)
11007 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11008 else
11009 return "pe-i386";
11010 # elif defined (TE_GO32)
11011 case bfd_target_coff_flavour:
11012 return "coff-go32";
11013 # else
11014 case bfd_target_coff_flavour:
11015 return "coff-i386";
11016 # endif
11017 #endif
11018 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11019 case bfd_target_elf_flavour:
11020 {
11021 const char *format;
11022
11023 switch (x86_elf_abi)
11024 {
11025 default:
11026 format = ELF_TARGET_FORMAT;
11027 break;
11028 case X86_64_ABI:
11029 use_rela_relocations = 1;
11030 object_64bit = 1;
11031 format = ELF_TARGET_FORMAT64;
11032 break;
11033 case X86_64_X32_ABI:
11034 use_rela_relocations = 1;
11035 object_64bit = 1;
11036 disallow_64bit_reloc = 1;
11037 format = ELF_TARGET_FORMAT32;
11038 break;
11039 }
11040 if (cpu_arch_isa == PROCESSOR_L1OM)
11041 {
11042 if (x86_elf_abi != X86_64_ABI)
11043 as_fatal (_("Intel L1OM is 64bit only"));
11044 return ELF_TARGET_L1OM_FORMAT;
11045 }
11046 else if (cpu_arch_isa == PROCESSOR_K1OM)
11047 {
11048 if (x86_elf_abi != X86_64_ABI)
11049 as_fatal (_("Intel K1OM is 64bit only"));
11050 return ELF_TARGET_K1OM_FORMAT;
11051 }
11052 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11053 {
11054 if (x86_elf_abi != I386_ABI)
11055 as_fatal (_("Intel MCU is 32bit only"));
11056 return ELF_TARGET_IAMCU_FORMAT;
11057 }
11058 else
11059 return format;
11060 }
11061 #endif
11062 #if defined (OBJ_MACH_O)
11063 case bfd_target_mach_o_flavour:
11064 if (flag_code == CODE_64BIT)
11065 {
11066 use_rela_relocations = 1;
11067 object_64bit = 1;
11068 return "mach-o-x86-64";
11069 }
11070 else
11071 return "mach-o-i386";
11072 #endif
11073 default:
11074 abort ();
11075 return NULL;
11076 }
11077 }
11078
11079 #endif /* OBJ_MAYBE_ more than one */
11080 \f
11081 symbolS *
11082 md_undefined_symbol (char *name)
11083 {
11084 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11085 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11086 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11087 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11088 {
11089 if (!GOT_symbol)
11090 {
11091 if (symbol_find (name))
11092 as_bad (_("GOT already in symbol table"));
11093 GOT_symbol = symbol_new (name, undefined_section,
11094 (valueT) 0, &zero_address_frag);
11095 };
11096 return GOT_symbol;
11097 }
11098 return 0;
11099 }
11100
11101 /* Round up a section size to the appropriate boundary. */
11102
11103 valueT
11104 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11105 {
11106 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11107 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11108 {
11109 /* For a.out, force the section size to be aligned. If we don't do
11110 this, BFD will align it for us, but it will not write out the
11111 final bytes of the section. This may be a bug in BFD, but it is
11112 easier to fix it here since that is how the other a.out targets
11113 work. */
11114 int align;
11115
11116 align = bfd_get_section_alignment (stdoutput, segment);
11117 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11118 }
11119 #endif
11120
11121 return size;
11122 }
11123
11124 /* On the i386, PC-relative offsets are relative to the start of the
11125 next instruction. That is, the address of the offset, plus its
11126 size, since the offset is always the last part of the insn. */
11127
11128 long
11129 md_pcrel_from (fixS *fixP)
11130 {
11131 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11132 }
11133
11134 #ifndef I386COFF
11135
11136 static void
11137 s_bss (int ignore ATTRIBUTE_UNUSED)
11138 {
11139 int temp;
11140
11141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11142 if (IS_ELF)
11143 obj_elf_section_change_hook ();
11144 #endif
11145 temp = get_absolute_expression ();
11146 subseg_set (bss_section, (subsegT) temp);
11147 demand_empty_rest_of_line ();
11148 }
11149
11150 #endif
11151
11152 void
11153 i386_validate_fix (fixS *fixp)
11154 {
11155 if (fixp->fx_subsy)
11156 {
11157 if (fixp->fx_subsy == GOT_symbol)
11158 {
11159 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11160 {
11161 if (!object_64bit)
11162 abort ();
11163 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11164 if (fixp->fx_tcbit2)
11165 fixp->fx_r_type = (fixp->fx_tcbit
11166 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11167 : BFD_RELOC_X86_64_GOTPCRELX);
11168 else
11169 #endif
11170 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11171 }
11172 else
11173 {
11174 if (!object_64bit)
11175 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11176 else
11177 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11178 }
11179 fixp->fx_subsy = 0;
11180 }
11181 }
11182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11183 else if (!object_64bit)
11184 {
11185 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11186 && fixp->fx_tcbit2)
11187 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11188 }
11189 #endif
11190 }
11191
11192 arelent *
11193 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11194 {
11195 arelent *rel;
11196 bfd_reloc_code_real_type code;
11197
11198 switch (fixp->fx_r_type)
11199 {
11200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11201 case BFD_RELOC_SIZE32:
11202 case BFD_RELOC_SIZE64:
11203 if (S_IS_DEFINED (fixp->fx_addsy)
11204 && !S_IS_EXTERNAL (fixp->fx_addsy))
11205 {
11206 /* Resolve size relocation against local symbol to size of
11207 the symbol plus addend. */
11208 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11209 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11210 && !fits_in_unsigned_long (value))
11211 as_bad_where (fixp->fx_file, fixp->fx_line,
11212 _("symbol size computation overflow"));
11213 fixp->fx_addsy = NULL;
11214 fixp->fx_subsy = NULL;
11215 md_apply_fix (fixp, (valueT *) &value, NULL);
11216 return NULL;
11217 }
11218 #endif
11219 /* Fall through. */
11220
11221 case BFD_RELOC_X86_64_PLT32:
11222 case BFD_RELOC_X86_64_GOT32:
11223 case BFD_RELOC_X86_64_GOTPCREL:
11224 case BFD_RELOC_X86_64_GOTPCRELX:
11225 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11226 case BFD_RELOC_386_PLT32:
11227 case BFD_RELOC_386_GOT32:
11228 case BFD_RELOC_386_GOT32X:
11229 case BFD_RELOC_386_GOTOFF:
11230 case BFD_RELOC_386_GOTPC:
11231 case BFD_RELOC_386_TLS_GD:
11232 case BFD_RELOC_386_TLS_LDM:
11233 case BFD_RELOC_386_TLS_LDO_32:
11234 case BFD_RELOC_386_TLS_IE_32:
11235 case BFD_RELOC_386_TLS_IE:
11236 case BFD_RELOC_386_TLS_GOTIE:
11237 case BFD_RELOC_386_TLS_LE_32:
11238 case BFD_RELOC_386_TLS_LE:
11239 case BFD_RELOC_386_TLS_GOTDESC:
11240 case BFD_RELOC_386_TLS_DESC_CALL:
11241 case BFD_RELOC_X86_64_TLSGD:
11242 case BFD_RELOC_X86_64_TLSLD:
11243 case BFD_RELOC_X86_64_DTPOFF32:
11244 case BFD_RELOC_X86_64_DTPOFF64:
11245 case BFD_RELOC_X86_64_GOTTPOFF:
11246 case BFD_RELOC_X86_64_TPOFF32:
11247 case BFD_RELOC_X86_64_TPOFF64:
11248 case BFD_RELOC_X86_64_GOTOFF64:
11249 case BFD_RELOC_X86_64_GOTPC32:
11250 case BFD_RELOC_X86_64_GOT64:
11251 case BFD_RELOC_X86_64_GOTPCREL64:
11252 case BFD_RELOC_X86_64_GOTPC64:
11253 case BFD_RELOC_X86_64_GOTPLT64:
11254 case BFD_RELOC_X86_64_PLTOFF64:
11255 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11256 case BFD_RELOC_X86_64_TLSDESC_CALL:
11257 case BFD_RELOC_RVA:
11258 case BFD_RELOC_VTABLE_ENTRY:
11259 case BFD_RELOC_VTABLE_INHERIT:
11260 #ifdef TE_PE
11261 case BFD_RELOC_32_SECREL:
11262 #endif
11263 code = fixp->fx_r_type;
11264 break;
11265 case BFD_RELOC_X86_64_32S:
11266 if (!fixp->fx_pcrel)
11267 {
11268 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11269 code = fixp->fx_r_type;
11270 break;
11271 }
11272 /* Fall through. */
11273 default:
11274 if (fixp->fx_pcrel)
11275 {
11276 switch (fixp->fx_size)
11277 {
11278 default:
11279 as_bad_where (fixp->fx_file, fixp->fx_line,
11280 _("can not do %d byte pc-relative relocation"),
11281 fixp->fx_size);
11282 code = BFD_RELOC_32_PCREL;
11283 break;
11284 case 1: code = BFD_RELOC_8_PCREL; break;
11285 case 2: code = BFD_RELOC_16_PCREL; break;
11286 case 4: code = BFD_RELOC_32_PCREL; break;
11287 #ifdef BFD64
11288 case 8: code = BFD_RELOC_64_PCREL; break;
11289 #endif
11290 }
11291 }
11292 else
11293 {
11294 switch (fixp->fx_size)
11295 {
11296 default:
11297 as_bad_where (fixp->fx_file, fixp->fx_line,
11298 _("can not do %d byte relocation"),
11299 fixp->fx_size);
11300 code = BFD_RELOC_32;
11301 break;
11302 case 1: code = BFD_RELOC_8; break;
11303 case 2: code = BFD_RELOC_16; break;
11304 case 4: code = BFD_RELOC_32; break;
11305 #ifdef BFD64
11306 case 8: code = BFD_RELOC_64; break;
11307 #endif
11308 }
11309 }
11310 break;
11311 }
11312
11313 if ((code == BFD_RELOC_32
11314 || code == BFD_RELOC_32_PCREL
11315 || code == BFD_RELOC_X86_64_32S)
11316 && GOT_symbol
11317 && fixp->fx_addsy == GOT_symbol)
11318 {
11319 if (!object_64bit)
11320 code = BFD_RELOC_386_GOTPC;
11321 else
11322 code = BFD_RELOC_X86_64_GOTPC32;
11323 }
11324 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11325 && GOT_symbol
11326 && fixp->fx_addsy == GOT_symbol)
11327 {
11328 code = BFD_RELOC_X86_64_GOTPC64;
11329 }
11330
11331 rel = XNEW (arelent);
11332 rel->sym_ptr_ptr = XNEW (asymbol *);
11333 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11334
11335 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11336
11337 if (!use_rela_relocations)
11338 {
11339 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11340 vtable entry to be used in the relocation's section offset. */
11341 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11342 rel->address = fixp->fx_offset;
11343 #if defined (OBJ_COFF) && defined (TE_PE)
11344 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11345 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11346 else
11347 #endif
11348 rel->addend = 0;
11349 }
11350 /* Use the rela in 64bit mode. */
11351 else
11352 {
11353 if (disallow_64bit_reloc)
11354 switch (code)
11355 {
11356 case BFD_RELOC_X86_64_DTPOFF64:
11357 case BFD_RELOC_X86_64_TPOFF64:
11358 case BFD_RELOC_64_PCREL:
11359 case BFD_RELOC_X86_64_GOTOFF64:
11360 case BFD_RELOC_X86_64_GOT64:
11361 case BFD_RELOC_X86_64_GOTPCREL64:
11362 case BFD_RELOC_X86_64_GOTPC64:
11363 case BFD_RELOC_X86_64_GOTPLT64:
11364 case BFD_RELOC_X86_64_PLTOFF64:
11365 as_bad_where (fixp->fx_file, fixp->fx_line,
11366 _("cannot represent relocation type %s in x32 mode"),
11367 bfd_get_reloc_code_name (code));
11368 break;
11369 default:
11370 break;
11371 }
11372
11373 if (!fixp->fx_pcrel)
11374 rel->addend = fixp->fx_offset;
11375 else
11376 switch (code)
11377 {
11378 case BFD_RELOC_X86_64_PLT32:
11379 case BFD_RELOC_X86_64_GOT32:
11380 case BFD_RELOC_X86_64_GOTPCREL:
11381 case BFD_RELOC_X86_64_GOTPCRELX:
11382 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11383 case BFD_RELOC_X86_64_TLSGD:
11384 case BFD_RELOC_X86_64_TLSLD:
11385 case BFD_RELOC_X86_64_GOTTPOFF:
11386 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11387 case BFD_RELOC_X86_64_TLSDESC_CALL:
11388 rel->addend = fixp->fx_offset - fixp->fx_size;
11389 break;
11390 default:
11391 rel->addend = (section->vma
11392 - fixp->fx_size
11393 + fixp->fx_addnumber
11394 + md_pcrel_from (fixp));
11395 break;
11396 }
11397 }
11398
11399 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11400 if (rel->howto == NULL)
11401 {
11402 as_bad_where (fixp->fx_file, fixp->fx_line,
11403 _("cannot represent relocation type %s"),
11404 bfd_get_reloc_code_name (code));
11405 /* Set howto to a garbage value so that we can keep going. */
11406 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11407 gas_assert (rel->howto != NULL);
11408 }
11409
11410 return rel;
11411 }
11412
11413 #include "tc-i386-intel.c"
11414
11415 void
11416 tc_x86_parse_to_dw2regnum (expressionS *exp)
11417 {
11418 int saved_naked_reg;
11419 char saved_register_dot;
11420
11421 saved_naked_reg = allow_naked_reg;
11422 allow_naked_reg = 1;
11423 saved_register_dot = register_chars['.'];
11424 register_chars['.'] = '.';
11425 allow_pseudo_reg = 1;
11426 expression_and_evaluate (exp);
11427 allow_pseudo_reg = 0;
11428 register_chars['.'] = saved_register_dot;
11429 allow_naked_reg = saved_naked_reg;
11430
11431 if (exp->X_op == O_register && exp->X_add_number >= 0)
11432 {
11433 if ((addressT) exp->X_add_number < i386_regtab_size)
11434 {
11435 exp->X_op = O_constant;
11436 exp->X_add_number = i386_regtab[exp->X_add_number]
11437 .dw2_regnum[flag_code >> 1];
11438 }
11439 else
11440 exp->X_op = O_illegal;
11441 }
11442 }
11443
11444 void
11445 tc_x86_frame_initial_instructions (void)
11446 {
11447 static unsigned int sp_regno[2];
11448
11449 if (!sp_regno[flag_code >> 1])
11450 {
11451 char *saved_input = input_line_pointer;
11452 char sp[][4] = {"esp", "rsp"};
11453 expressionS exp;
11454
11455 input_line_pointer = sp[flag_code >> 1];
11456 tc_x86_parse_to_dw2regnum (&exp);
11457 gas_assert (exp.X_op == O_constant);
11458 sp_regno[flag_code >> 1] = exp.X_add_number;
11459 input_line_pointer = saved_input;
11460 }
11461
11462 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11463 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11464 }
11465
11466 int
11467 x86_dwarf2_addr_size (void)
11468 {
11469 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11470 if (x86_elf_abi == X86_64_X32_ABI)
11471 return 4;
11472 #endif
11473 return bfd_arch_bits_per_address (stdoutput) / 8;
11474 }
11475
11476 int
11477 i386_elf_section_type (const char *str, size_t len)
11478 {
11479 if (flag_code == CODE_64BIT
11480 && len == sizeof ("unwind") - 1
11481 && strncmp (str, "unwind", 6) == 0)
11482 return SHT_X86_64_UNWIND;
11483
11484 return -1;
11485 }
11486
11487 #ifdef TE_SOLARIS
11488 void
11489 i386_solaris_fix_up_eh_frame (segT sec)
11490 {
11491 if (flag_code == CODE_64BIT)
11492 elf_section_type (sec) = SHT_X86_64_UNWIND;
11493 }
11494 #endif
11495
11496 #ifdef TE_PE
11497 void
11498 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11499 {
11500 expressionS exp;
11501
11502 exp.X_op = O_secrel;
11503 exp.X_add_symbol = symbol;
11504 exp.X_add_number = 0;
11505 emit_expr (&exp, size);
11506 }
11507 #endif
11508
11509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11510 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11511
11512 bfd_vma
11513 x86_64_section_letter (int letter, const char **ptr_msg)
11514 {
11515 if (flag_code == CODE_64BIT)
11516 {
11517 if (letter == 'l')
11518 return SHF_X86_64_LARGE;
11519
11520 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11521 }
11522 else
11523 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11524 return -1;
11525 }
11526
11527 bfd_vma
11528 x86_64_section_word (char *str, size_t len)
11529 {
11530 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11531 return SHF_X86_64_LARGE;
11532
11533 return -1;
11534 }
11535
11536 static void
11537 handle_large_common (int small ATTRIBUTE_UNUSED)
11538 {
11539 if (flag_code != CODE_64BIT)
11540 {
11541 s_comm_internal (0, elf_common_parse);
11542 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11543 }
11544 else
11545 {
11546 static segT lbss_section;
11547 asection *saved_com_section_ptr = elf_com_section_ptr;
11548 asection *saved_bss_section = bss_section;
11549
11550 if (lbss_section == NULL)
11551 {
11552 flagword applicable;
11553 segT seg = now_seg;
11554 subsegT subseg = now_subseg;
11555
11556 /* The .lbss section is for local .largecomm symbols. */
11557 lbss_section = subseg_new (".lbss", 0);
11558 applicable = bfd_applicable_section_flags (stdoutput);
11559 bfd_set_section_flags (stdoutput, lbss_section,
11560 applicable & SEC_ALLOC);
11561 seg_info (lbss_section)->bss = 1;
11562
11563 subseg_set (seg, subseg);
11564 }
11565
11566 elf_com_section_ptr = &_bfd_elf_large_com_section;
11567 bss_section = lbss_section;
11568
11569 s_comm_internal (0, elf_common_parse);
11570
11571 elf_com_section_ptr = saved_com_section_ptr;
11572 bss_section = saved_bss_section;
11573 }
11574 }
11575 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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