1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* parse_register() returns this when a register alias cannot be used. */
214 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
215 { Dw2Inval
, Dw2Inval
} };
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form
;
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute
;
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx
;
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm
;
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm
;
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm
;
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc
;
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
386 /* Masking attributes. */
387 struct Mask_Operation
*mask
;
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation
*rounding
;
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation
*broadcast
;
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift
;
398 /* Prefer load or store in encoding. */
401 dir_encoding_default
= 0,
407 /* Prefer 8bit or 32bit displacement in encoding. */
410 disp_encoding_default
= 0,
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding
;
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize
;
421 /* How to encode vector instructions. */
424 vex_encoding_default
= 0,
431 const char *rep_prefix
;
434 const char *hle_prefix
;
436 /* Have BND prefix. */
437 const char *bnd_prefix
;
439 /* Have NOTRACK prefix. */
440 const char *notrack_prefix
;
443 enum i386_error error
;
446 typedef struct _i386_insn i386_insn
;
448 /* Link RC type with corresponding string, that'll be looked for in
457 static const struct RC_name RC_NamesTable
[] =
459 { rne
, STRING_COMMA_LEN ("rn-sae") },
460 { rd
, STRING_COMMA_LEN ("rd-sae") },
461 { ru
, STRING_COMMA_LEN ("ru-sae") },
462 { rz
, STRING_COMMA_LEN ("rz-sae") },
463 { saeonly
, STRING_COMMA_LEN ("sae") },
466 /* List of chars besides those in app.c:symbol_chars that can start an
467 operand. Used to prevent the scrubber eating vital white-space. */
468 const char extra_symbol_chars
[] = "*%-([{}"
477 #if (defined (TE_I386AIX) \
478 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
479 && !defined (TE_GNU) \
480 && !defined (TE_LINUX) \
481 && !defined (TE_NACL) \
482 && !defined (TE_FreeBSD) \
483 && !defined (TE_DragonFly) \
484 && !defined (TE_NetBSD)))
485 /* This array holds the chars that always start a comment. If the
486 pre-processor is disabled, these aren't very useful. The option
487 --divide will remove '/' from this list. */
488 const char *i386_comment_chars
= "#/";
489 #define SVR4_COMMENT_CHARS 1
490 #define PREFIX_SEPARATOR '\\'
493 const char *i386_comment_chars
= "#";
494 #define PREFIX_SEPARATOR '/'
497 /* This array holds the chars that only start a comment at the beginning of
498 a line. If the line seems to have the form '# 123 filename'
499 .line and .file directives will appear in the pre-processed output.
500 Note that input_file.c hand checks for '#' at the beginning of the
501 first line of the input file. This is because the compiler outputs
502 #NO_APP at the beginning of its output.
503 Also note that comments started like this one will always work if
504 '/' isn't otherwise defined. */
505 const char line_comment_chars
[] = "#/";
507 const char line_separator_chars
[] = ";";
509 /* Chars that can be used to separate mant from exp in floating point
511 const char EXP_CHARS
[] = "eE";
513 /* Chars that mean this number is a floating point constant
516 const char FLT_CHARS
[] = "fFdDxX";
518 /* Tables for lexical analysis. */
519 static char mnemonic_chars
[256];
520 static char register_chars
[256];
521 static char operand_chars
[256];
522 static char identifier_chars
[256];
523 static char digit_chars
[256];
525 /* Lexical macros. */
526 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
527 #define is_operand_char(x) (operand_chars[(unsigned char) x])
528 #define is_register_char(x) (register_chars[(unsigned char) x])
529 #define is_space_char(x) ((x) == ' ')
530 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
531 #define is_digit_char(x) (digit_chars[(unsigned char) x])
533 /* All non-digit non-letter characters that may occur in an operand. */
534 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
536 /* md_assemble() always leaves the strings it's passed unaltered. To
537 effect this we maintain a stack of saved characters that we've smashed
538 with '\0's (indicating end of strings for various sub-fields of the
539 assembler instruction). */
540 static char save_stack
[32];
541 static char *save_stack_p
;
542 #define END_STRING_AND_SAVE(s) \
543 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
544 #define RESTORE_END_STRING(s) \
545 do { *(s) = *--save_stack_p; } while (0)
547 /* The instruction we're assembling. */
550 /* Possible templates for current insn. */
551 static const templates
*current_templates
;
553 /* Per instruction expressionS buffers: max displacements & immediates. */
554 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
555 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
557 /* Current operand we are working on. */
558 static int this_operand
= -1;
560 /* We support four different modes. FLAG_CODE variable is used to distinguish
568 static enum flag_code flag_code
;
569 static unsigned int object_64bit
;
570 static unsigned int disallow_64bit_reloc
;
571 static int use_rela_relocations
= 0;
572 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
573 static const char *tls_get_addr
;
575 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
576 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
577 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
579 /* The ELF ABI to use. */
587 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
590 #if defined (TE_PE) || defined (TE_PEP)
591 /* Use big object file format. */
592 static int use_big_obj
= 0;
595 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
596 /* 1 if generating code for a shared library. */
597 static int shared
= 0;
600 /* 1 for intel syntax,
602 static int intel_syntax
= 0;
604 static enum x86_64_isa
606 amd64
= 1, /* AMD64 ISA. */
607 intel64
/* Intel64 ISA. */
610 /* 1 for intel mnemonic,
611 0 if att mnemonic. */
612 static int intel_mnemonic
= !SYSV386_COMPAT
;
614 /* 1 if pseudo registers are permitted. */
615 static int allow_pseudo_reg
= 0;
617 /* 1 if register prefix % not required. */
618 static int allow_naked_reg
= 0;
620 /* 1 if the assembler should add BND prefix for all control-transferring
621 instructions supporting it, even if this prefix wasn't specified
623 static int add_bnd_prefix
= 0;
625 /* 1 if pseudo index register, eiz/riz, is allowed . */
626 static int allow_index_reg
= 0;
628 /* 1 if the assembler should ignore LOCK prefix, even if it was
629 specified explicitly. */
630 static int omit_lock_prefix
= 0;
632 /* 1 if the assembler should encode lfence, mfence, and sfence as
633 "lock addl $0, (%{re}sp)". */
634 static int avoid_fence
= 0;
636 /* 1 if lfence should be inserted after every load. */
637 static int lfence_after_load
= 0;
639 /* Non-zero if lfence should be inserted before indirect branch. */
640 static enum lfence_before_indirect_branch_kind
642 lfence_branch_none
= 0,
643 lfence_branch_register
,
644 lfence_branch_memory
,
647 lfence_before_indirect_branch
;
649 /* Non-zero if lfence should be inserted before ret. */
650 static enum lfence_before_ret_kind
652 lfence_before_ret_none
= 0,
653 lfence_before_ret_not
,
654 lfence_before_ret_or
,
655 lfence_before_ret_shl
659 /* Types of previous instruction is .byte or prefix. */
674 /* 1 if the assembler should generate relax relocations. */
676 static int generate_relax_relocations
677 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
679 static enum check_kind
685 sse_check
, operand_check
= check_warning
;
687 /* Non-zero if branches should be aligned within power of 2 boundary. */
688 static int align_branch_power
= 0;
690 /* Types of branches to align. */
691 enum align_branch_kind
693 align_branch_none
= 0,
694 align_branch_jcc
= 1,
695 align_branch_fused
= 2,
696 align_branch_jmp
= 3,
697 align_branch_call
= 4,
698 align_branch_indirect
= 5,
702 /* Type bits of branches to align. */
703 enum align_branch_bit
705 align_branch_jcc_bit
= 1 << align_branch_jcc
,
706 align_branch_fused_bit
= 1 << align_branch_fused
,
707 align_branch_jmp_bit
= 1 << align_branch_jmp
,
708 align_branch_call_bit
= 1 << align_branch_call
,
709 align_branch_indirect_bit
= 1 << align_branch_indirect
,
710 align_branch_ret_bit
= 1 << align_branch_ret
713 static unsigned int align_branch
= (align_branch_jcc_bit
714 | align_branch_fused_bit
715 | align_branch_jmp_bit
);
717 /* Types of condition jump used by macro-fusion. */
720 mf_jcc_jo
= 0, /* base opcode 0x70 */
721 mf_jcc_jc
, /* base opcode 0x72 */
722 mf_jcc_je
, /* base opcode 0x74 */
723 mf_jcc_jna
, /* base opcode 0x76 */
724 mf_jcc_js
, /* base opcode 0x78 */
725 mf_jcc_jp
, /* base opcode 0x7a */
726 mf_jcc_jl
, /* base opcode 0x7c */
727 mf_jcc_jle
, /* base opcode 0x7e */
730 /* Types of compare flag-modifying insntructions used by macro-fusion. */
733 mf_cmp_test_and
, /* test/cmp */
734 mf_cmp_alu_cmp
, /* add/sub/cmp */
735 mf_cmp_incdec
/* inc/dec */
738 /* The maximum padding size for fused jcc. CMP like instruction can
739 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
741 #define MAX_FUSED_JCC_PADDING_SIZE 20
743 /* The maximum number of prefixes added for an instruction. */
744 static unsigned int align_branch_prefix_size
= 5;
747 1. Clear the REX_W bit with register operand if possible.
748 2. Above plus use 128bit vector instruction to clear the full vector
751 static int optimize
= 0;
754 1. Clear the REX_W bit with register operand if possible.
755 2. Above plus use 128bit vector instruction to clear the full vector
757 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
760 static int optimize_for_space
= 0;
762 /* Register prefix used for error message. */
763 static const char *register_prefix
= "%";
765 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
766 leave, push, and pop instructions so that gcc has the same stack
767 frame as in 32 bit mode. */
768 static char stackop_size
= '\0';
770 /* Non-zero to optimize code alignment. */
771 int optimize_align_code
= 1;
773 /* Non-zero to quieten some warnings. */
774 static int quiet_warnings
= 0;
777 static const char *cpu_arch_name
= NULL
;
778 static char *cpu_sub_arch_name
= NULL
;
780 /* CPU feature flags. */
781 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
783 /* If we have selected a cpu we are generating instructions for. */
784 static int cpu_arch_tune_set
= 0;
786 /* Cpu we are generating instructions for. */
787 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
789 /* CPU feature flags of cpu we are generating instructions for. */
790 static i386_cpu_flags cpu_arch_tune_flags
;
792 /* CPU instruction set architecture used. */
793 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
795 /* CPU feature flags of instruction set architecture used. */
796 i386_cpu_flags cpu_arch_isa_flags
;
798 /* If set, conditional jumps are not automatically promoted to handle
799 larger than a byte offset. */
800 static unsigned int no_cond_jump_promotion
= 0;
802 /* Encode SSE instructions with VEX prefix. */
803 static unsigned int sse2avx
;
805 /* Encode scalar AVX instructions with specific vector length. */
812 /* Encode VEX WIG instructions with specific vex.w. */
819 /* Encode scalar EVEX LIG instructions with specific vector length. */
827 /* Encode EVEX WIG instructions with specific evex.w. */
834 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
835 static enum rc_type evexrcig
= rne
;
837 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
838 static symbolS
*GOT_symbol
;
840 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
841 unsigned int x86_dwarf2_return_column
;
843 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
844 int x86_cie_data_alignment
;
846 /* Interface to relax_segment.
847 There are 3 major relax states for 386 jump insns because the
848 different types of jumps add different sizes to frags when we're
849 figuring out what sort of jump to choose to reach a given label.
851 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
852 branches which are handled by md_estimate_size_before_relax() and
853 i386_generic_table_relax_frag(). */
856 #define UNCOND_JUMP 0
858 #define COND_JUMP86 2
859 #define BRANCH_PADDING 3
860 #define BRANCH_PREFIX 4
861 #define FUSED_JCC_PADDING 5
866 #define SMALL16 (SMALL | CODE16)
868 #define BIG16 (BIG | CODE16)
872 #define INLINE __inline__
878 #define ENCODE_RELAX_STATE(type, size) \
879 ((relax_substateT) (((type) << 2) | (size)))
880 #define TYPE_FROM_RELAX_STATE(s) \
882 #define DISP_SIZE_FROM_RELAX_STATE(s) \
883 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
885 /* This table is used by relax_frag to promote short jumps to long
886 ones where necessary. SMALL (short) jumps may be promoted to BIG
887 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
888 don't allow a short jump in a 32 bit code segment to be promoted to
889 a 16 bit offset jump because it's slower (requires data size
890 prefix), and doesn't work, unless the destination is in the bottom
891 64k of the code segment (The top 16 bits of eip are zeroed). */
893 const relax_typeS md_relax_table
[] =
896 1) most positive reach of this state,
897 2) most negative reach of this state,
898 3) how many bytes this mode will have in the variable part of the frag
899 4) which index into the table to try if we can't fit into this one. */
901 /* UNCOND_JUMP states. */
902 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
904 /* dword jmp adds 4 bytes to frag:
905 0 extra opcode bytes, 4 displacement bytes. */
907 /* word jmp adds 2 byte2 to frag:
908 0 extra opcode bytes, 2 displacement bytes. */
911 /* COND_JUMP states. */
912 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
914 /* dword conditionals adds 5 bytes to frag:
915 1 extra opcode byte, 4 displacement bytes. */
917 /* word conditionals add 3 bytes to frag:
918 1 extra opcode byte, 2 displacement bytes. */
921 /* COND_JUMP86 states. */
922 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
924 /* dword conditionals adds 5 bytes to frag:
925 1 extra opcode byte, 4 displacement bytes. */
927 /* word conditionals add 4 bytes to frag:
928 1 displacement byte and a 3 byte long branch insn. */
932 static const arch_entry cpu_arch
[] =
934 /* Do not replace the first two entries - i386_target_format()
935 relies on them being there in this order. */
936 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
937 CPU_GENERIC32_FLAGS
, 0 },
938 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
939 CPU_GENERIC64_FLAGS
, 0 },
940 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
942 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
948 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
950 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
952 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
954 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
956 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
957 CPU_PENTIUMPRO_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
960 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
962 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
964 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
966 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
967 CPU_NOCONA_FLAGS
, 0 },
968 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
970 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
972 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
973 CPU_CORE2_FLAGS
, 1 },
974 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
975 CPU_CORE2_FLAGS
, 0 },
976 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
977 CPU_COREI7_FLAGS
, 0 },
978 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
980 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
982 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
983 CPU_IAMCU_FLAGS
, 0 },
984 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
986 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
988 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
989 CPU_ATHLON_FLAGS
, 0 },
990 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
992 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
994 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
996 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
997 CPU_AMDFAM10_FLAGS
, 0 },
998 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
999 CPU_BDVER1_FLAGS
, 0 },
1000 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
1001 CPU_BDVER2_FLAGS
, 0 },
1002 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
1003 CPU_BDVER3_FLAGS
, 0 },
1004 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
1005 CPU_BDVER4_FLAGS
, 0 },
1006 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
1007 CPU_ZNVER1_FLAGS
, 0 },
1008 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
1009 CPU_ZNVER2_FLAGS
, 0 },
1010 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
1011 CPU_BTVER1_FLAGS
, 0 },
1012 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
1013 CPU_BTVER2_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
1015 CPU_8087_FLAGS
, 0 },
1016 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
1018 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
1022 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
1023 CPU_CMOV_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
1025 CPU_FXSR_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
1028 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
1031 CPU_SSE2_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
1033 CPU_SSE3_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1035 CPU_SSE4A_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
1037 CPU_SSSE3_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
1039 CPU_SSE4_1_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
1041 CPU_SSE4_2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
1043 CPU_SSE4_2_FLAGS
, 0 },
1044 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1047 CPU_AVX2_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1049 CPU_AVX512F_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1051 CPU_AVX512CD_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1053 CPU_AVX512ER_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1055 CPU_AVX512PF_FLAGS
, 0 },
1056 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1057 CPU_AVX512DQ_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1059 CPU_AVX512BW_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1061 CPU_AVX512VL_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1065 CPU_VMFUNC_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1068 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1069 CPU_XSAVE_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1071 CPU_XSAVEOPT_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1073 CPU_XSAVEC_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1075 CPU_XSAVES_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1078 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1079 CPU_PCLMUL_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1081 CPU_PCLMUL_FLAGS
, 1 },
1082 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1083 CPU_FSGSBASE_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1085 CPU_RDRND_FLAGS
, 0 },
1086 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1087 CPU_F16C_FLAGS
, 0 },
1088 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1089 CPU_BMI2_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1093 CPU_FMA4_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1099 CPU_MOVBE_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1101 CPU_CX16_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1105 CPU_LZCNT_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN
,
1107 CPU_POPCNT_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1110 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1112 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1113 CPU_INVPCID_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1115 CPU_CLFLUSH_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1118 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1119 CPU_SYSCALL_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1121 CPU_RDTSCP_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1123 CPU_3DNOW_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1125 CPU_3DNOWA_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1127 CPU_PADLOCK_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1129 CPU_SVME_FLAGS
, 1 },
1130 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1131 CPU_SVME_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1133 CPU_SSE4A_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1136 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1140 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1142 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1143 CPU_RDSEED_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1145 CPU_PRFCHW_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1147 CPU_SMAP_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1150 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1152 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1153 CPU_CLFLUSHOPT_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1155 CPU_PREFETCHWT1_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1158 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1159 CPU_CLWB_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512IFMA_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1163 CPU_AVX512VBMI_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1165 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1167 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1168 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1169 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1170 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1171 CPU_AVX512_VBMI2_FLAGS
, 0 },
1172 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1173 CPU_AVX512_VNNI_FLAGS
, 0 },
1174 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1175 CPU_AVX512_BITALG_FLAGS
, 0 },
1176 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1177 CPU_CLZERO_FLAGS
, 0 },
1178 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1179 CPU_MWAITX_FLAGS
, 0 },
1180 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1181 CPU_OSPKE_FLAGS
, 0 },
1182 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1183 CPU_RDPID_FLAGS
, 0 },
1184 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1185 CPU_PTWRITE_FLAGS
, 0 },
1186 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1188 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1189 CPU_SHSTK_FLAGS
, 0 },
1190 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1191 CPU_GFNI_FLAGS
, 0 },
1192 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1193 CPU_VAES_FLAGS
, 0 },
1194 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1195 CPU_VPCLMULQDQ_FLAGS
, 0 },
1196 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1197 CPU_WBNOINVD_FLAGS
, 0 },
1198 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1199 CPU_PCONFIG_FLAGS
, 0 },
1200 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1201 CPU_WAITPKG_FLAGS
, 0 },
1202 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1203 CPU_CLDEMOTE_FLAGS
, 0 },
1204 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1205 CPU_MOVDIRI_FLAGS
, 0 },
1206 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1207 CPU_MOVDIR64B_FLAGS
, 0 },
1208 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1209 CPU_AVX512_BF16_FLAGS
, 0 },
1210 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1211 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1212 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1213 CPU_ENQCMD_FLAGS
, 0 },
1214 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN
,
1215 CPU_SERIALIZE_FLAGS
, 0 },
1216 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1217 CPU_RDPRU_FLAGS
, 0 },
1218 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1219 CPU_MCOMMIT_FLAGS
, 0 },
1220 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN
,
1221 CPU_SEV_ES_FLAGS
, 0 },
1222 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN
,
1223 CPU_TSXLDTRK_FLAGS
, 0 },
1226 static const noarch_entry cpu_noarch
[] =
1228 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1229 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1230 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1231 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1232 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1233 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1234 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1235 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1236 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1237 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1238 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1239 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1240 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1241 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1242 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1243 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1244 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1245 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1246 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1247 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1248 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1249 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1250 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1251 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1252 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1253 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1254 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1255 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1256 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1257 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1258 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1259 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1260 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1261 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1262 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1263 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1264 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1265 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1266 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1267 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS
},
1268 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS
},
1272 /* Like s_lcomm_internal in gas/read.c but the alignment string
1273 is allowed to be optional. */
1276 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1283 && *input_line_pointer
== ',')
1285 align
= parse_align (needs_align
- 1);
1287 if (align
== (addressT
) -1)
1302 bss_alloc (symbolP
, size
, align
);
1307 pe_lcomm (int needs_align
)
1309 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1313 const pseudo_typeS md_pseudo_table
[] =
1315 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1316 {"align", s_align_bytes
, 0},
1318 {"align", s_align_ptwo
, 0},
1320 {"arch", set_cpu_arch
, 0},
1324 {"lcomm", pe_lcomm
, 1},
1326 {"ffloat", float_cons
, 'f'},
1327 {"dfloat", float_cons
, 'd'},
1328 {"tfloat", float_cons
, 'x'},
1330 {"slong", signed_cons
, 4},
1331 {"noopt", s_ignore
, 0},
1332 {"optim", s_ignore
, 0},
1333 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1334 {"code16", set_code_flag
, CODE_16BIT
},
1335 {"code32", set_code_flag
, CODE_32BIT
},
1337 {"code64", set_code_flag
, CODE_64BIT
},
1339 {"intel_syntax", set_intel_syntax
, 1},
1340 {"att_syntax", set_intel_syntax
, 0},
1341 {"intel_mnemonic", set_intel_mnemonic
, 1},
1342 {"att_mnemonic", set_intel_mnemonic
, 0},
1343 {"allow_index_reg", set_allow_index_reg
, 1},
1344 {"disallow_index_reg", set_allow_index_reg
, 0},
1345 {"sse_check", set_check
, 0},
1346 {"operand_check", set_check
, 1},
1347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1348 {"largecomm", handle_large_common
, 0},
1350 {"file", dwarf2_directive_file
, 0},
1351 {"loc", dwarf2_directive_loc
, 0},
1352 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1355 {"secrel32", pe_directive_secrel
, 0},
1360 /* For interface with expression (). */
1361 extern char *input_line_pointer
;
1363 /* Hash table for instruction mnemonic lookup. */
1364 static struct hash_control
*op_hash
;
1366 /* Hash table for register lookup. */
1367 static struct hash_control
*reg_hash
;
1369 /* Various efficient no-op patterns for aligning code labels.
1370 Note: Don't try to assemble the instructions in the comments.
1371 0L and 0w are not legal. */
1372 static const unsigned char f32_1
[] =
1374 static const unsigned char f32_2
[] =
1375 {0x66,0x90}; /* xchg %ax,%ax */
1376 static const unsigned char f32_3
[] =
1377 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1378 static const unsigned char f32_4
[] =
1379 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1380 static const unsigned char f32_6
[] =
1381 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1382 static const unsigned char f32_7
[] =
1383 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1384 static const unsigned char f16_3
[] =
1385 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1386 static const unsigned char f16_4
[] =
1387 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1388 static const unsigned char jump_disp8
[] =
1389 {0xeb}; /* jmp disp8 */
1390 static const unsigned char jump32_disp32
[] =
1391 {0xe9}; /* jmp disp32 */
1392 static const unsigned char jump16_disp32
[] =
1393 {0x66,0xe9}; /* jmp disp32 */
1394 /* 32-bit NOPs patterns. */
1395 static const unsigned char *const f32_patt
[] = {
1396 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1398 /* 16-bit NOPs patterns. */
1399 static const unsigned char *const f16_patt
[] = {
1400 f32_1
, f32_2
, f16_3
, f16_4
1402 /* nopl (%[re]ax) */
1403 static const unsigned char alt_3
[] =
1405 /* nopl 0(%[re]ax) */
1406 static const unsigned char alt_4
[] =
1407 {0x0f,0x1f,0x40,0x00};
1408 /* nopl 0(%[re]ax,%[re]ax,1) */
1409 static const unsigned char alt_5
[] =
1410 {0x0f,0x1f,0x44,0x00,0x00};
1411 /* nopw 0(%[re]ax,%[re]ax,1) */
1412 static const unsigned char alt_6
[] =
1413 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1414 /* nopl 0L(%[re]ax) */
1415 static const unsigned char alt_7
[] =
1416 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1417 /* nopl 0L(%[re]ax,%[re]ax,1) */
1418 static const unsigned char alt_8
[] =
1419 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1420 /* nopw 0L(%[re]ax,%[re]ax,1) */
1421 static const unsigned char alt_9
[] =
1422 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1423 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1424 static const unsigned char alt_10
[] =
1425 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1426 /* data16 nopw %cs:0L(%eax,%eax,1) */
1427 static const unsigned char alt_11
[] =
1428 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1429 /* 32-bit and 64-bit NOPs patterns. */
1430 static const unsigned char *const alt_patt
[] = {
1431 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1432 alt_9
, alt_10
, alt_11
1435 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1436 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1439 i386_output_nops (char *where
, const unsigned char *const *patt
,
1440 int count
, int max_single_nop_size
)
1443 /* Place the longer NOP first. */
1446 const unsigned char *nops
;
1448 if (max_single_nop_size
< 1)
1450 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1451 max_single_nop_size
);
1455 nops
= patt
[max_single_nop_size
- 1];
1457 /* Use the smaller one if the requsted one isn't available. */
1460 max_single_nop_size
--;
1461 nops
= patt
[max_single_nop_size
- 1];
1464 last
= count
% max_single_nop_size
;
1467 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1468 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1472 nops
= patt
[last
- 1];
1475 /* Use the smaller one plus one-byte NOP if the needed one
1478 nops
= patt
[last
- 1];
1479 memcpy (where
+ offset
, nops
, last
);
1480 where
[offset
+ last
] = *patt
[0];
1483 memcpy (where
+ offset
, nops
, last
);
1488 fits_in_imm7 (offsetT num
)
1490 return (num
& 0x7f) == num
;
1494 fits_in_imm31 (offsetT num
)
1496 return (num
& 0x7fffffff) == num
;
1499 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1500 single NOP instruction LIMIT. */
1503 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1505 const unsigned char *const *patt
= NULL
;
1506 int max_single_nop_size
;
1507 /* Maximum number of NOPs before switching to jump over NOPs. */
1508 int max_number_of_nops
;
1510 switch (fragP
->fr_type
)
1515 case rs_machine_dependent
:
1516 /* Allow NOP padding for jumps and calls. */
1517 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1518 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1525 /* We need to decide which NOP sequence to use for 32bit and
1526 64bit. When -mtune= is used:
1528 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1529 PROCESSOR_GENERIC32, f32_patt will be used.
1530 2. For the rest, alt_patt will be used.
1532 When -mtune= isn't used, alt_patt will be used if
1533 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1536 When -march= or .arch is used, we can't use anything beyond
1537 cpu_arch_isa_flags. */
1539 if (flag_code
== CODE_16BIT
)
1542 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1543 /* Limit number of NOPs to 2 in 16-bit mode. */
1544 max_number_of_nops
= 2;
1548 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1550 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1551 switch (cpu_arch_tune
)
1553 case PROCESSOR_UNKNOWN
:
1554 /* We use cpu_arch_isa_flags to check if we SHOULD
1555 optimize with nops. */
1556 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1561 case PROCESSOR_PENTIUM4
:
1562 case PROCESSOR_NOCONA
:
1563 case PROCESSOR_CORE
:
1564 case PROCESSOR_CORE2
:
1565 case PROCESSOR_COREI7
:
1566 case PROCESSOR_L1OM
:
1567 case PROCESSOR_K1OM
:
1568 case PROCESSOR_GENERIC64
:
1570 case PROCESSOR_ATHLON
:
1572 case PROCESSOR_AMDFAM10
:
1574 case PROCESSOR_ZNVER
:
1578 case PROCESSOR_I386
:
1579 case PROCESSOR_I486
:
1580 case PROCESSOR_PENTIUM
:
1581 case PROCESSOR_PENTIUMPRO
:
1582 case PROCESSOR_IAMCU
:
1583 case PROCESSOR_GENERIC32
:
1590 switch (fragP
->tc_frag_data
.tune
)
1592 case PROCESSOR_UNKNOWN
:
1593 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1594 PROCESSOR_UNKNOWN. */
1598 case PROCESSOR_I386
:
1599 case PROCESSOR_I486
:
1600 case PROCESSOR_PENTIUM
:
1601 case PROCESSOR_IAMCU
:
1603 case PROCESSOR_ATHLON
:
1605 case PROCESSOR_AMDFAM10
:
1607 case PROCESSOR_ZNVER
:
1609 case PROCESSOR_GENERIC32
:
1610 /* We use cpu_arch_isa_flags to check if we CAN optimize
1612 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1617 case PROCESSOR_PENTIUMPRO
:
1618 case PROCESSOR_PENTIUM4
:
1619 case PROCESSOR_NOCONA
:
1620 case PROCESSOR_CORE
:
1621 case PROCESSOR_CORE2
:
1622 case PROCESSOR_COREI7
:
1623 case PROCESSOR_L1OM
:
1624 case PROCESSOR_K1OM
:
1625 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1630 case PROCESSOR_GENERIC64
:
1636 if (patt
== f32_patt
)
1638 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1639 /* Limit number of NOPs to 2 for older processors. */
1640 max_number_of_nops
= 2;
1644 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1645 /* Limit number of NOPs to 7 for newer processors. */
1646 max_number_of_nops
= 7;
1651 limit
= max_single_nop_size
;
1653 if (fragP
->fr_type
== rs_fill_nop
)
1655 /* Output NOPs for .nop directive. */
1656 if (limit
> max_single_nop_size
)
1658 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1659 _("invalid single nop size: %d "
1660 "(expect within [0, %d])"),
1661 limit
, max_single_nop_size
);
1665 else if (fragP
->fr_type
!= rs_machine_dependent
)
1666 fragP
->fr_var
= count
;
1668 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1670 /* Generate jump over NOPs. */
1671 offsetT disp
= count
- 2;
1672 if (fits_in_imm7 (disp
))
1674 /* Use "jmp disp8" if possible. */
1676 where
[0] = jump_disp8
[0];
1682 unsigned int size_of_jump
;
1684 if (flag_code
== CODE_16BIT
)
1686 where
[0] = jump16_disp32
[0];
1687 where
[1] = jump16_disp32
[1];
1692 where
[0] = jump32_disp32
[0];
1696 count
-= size_of_jump
+ 4;
1697 if (!fits_in_imm31 (count
))
1699 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1700 _("jump over nop padding out of range"));
1704 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1705 where
+= size_of_jump
+ 4;
1709 /* Generate multiple NOPs. */
1710 i386_output_nops (where
, patt
, count
, limit
);
1714 operand_type_all_zero (const union i386_operand_type
*x
)
1716 switch (ARRAY_SIZE(x
->array
))
1727 return !x
->array
[0];
1734 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1736 switch (ARRAY_SIZE(x
->array
))
1752 x
->bitfield
.class = ClassNone
;
1753 x
->bitfield
.instance
= InstanceNone
;
1757 operand_type_equal (const union i386_operand_type
*x
,
1758 const union i386_operand_type
*y
)
1760 switch (ARRAY_SIZE(x
->array
))
1763 if (x
->array
[2] != y
->array
[2])
1767 if (x
->array
[1] != y
->array
[1])
1771 return x
->array
[0] == y
->array
[0];
1779 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1781 switch (ARRAY_SIZE(x
->array
))
1796 return !x
->array
[0];
1803 cpu_flags_equal (const union i386_cpu_flags
*x
,
1804 const union i386_cpu_flags
*y
)
1806 switch (ARRAY_SIZE(x
->array
))
1809 if (x
->array
[3] != y
->array
[3])
1813 if (x
->array
[2] != y
->array
[2])
1817 if (x
->array
[1] != y
->array
[1])
1821 return x
->array
[0] == y
->array
[0];
1829 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1831 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1832 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1835 static INLINE i386_cpu_flags
1836 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1838 switch (ARRAY_SIZE (x
.array
))
1841 x
.array
[3] &= y
.array
[3];
1844 x
.array
[2] &= y
.array
[2];
1847 x
.array
[1] &= y
.array
[1];
1850 x
.array
[0] &= y
.array
[0];
1858 static INLINE i386_cpu_flags
1859 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1861 switch (ARRAY_SIZE (x
.array
))
1864 x
.array
[3] |= y
.array
[3];
1867 x
.array
[2] |= y
.array
[2];
1870 x
.array
[1] |= y
.array
[1];
1873 x
.array
[0] |= y
.array
[0];
1881 static INLINE i386_cpu_flags
1882 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1884 switch (ARRAY_SIZE (x
.array
))
1887 x
.array
[3] &= ~y
.array
[3];
1890 x
.array
[2] &= ~y
.array
[2];
1893 x
.array
[1] &= ~y
.array
[1];
1896 x
.array
[0] &= ~y
.array
[0];
1904 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1906 #define CPU_FLAGS_ARCH_MATCH 0x1
1907 #define CPU_FLAGS_64BIT_MATCH 0x2
1909 #define CPU_FLAGS_PERFECT_MATCH \
1910 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1912 /* Return CPU flags match bits. */
1915 cpu_flags_match (const insn_template
*t
)
1917 i386_cpu_flags x
= t
->cpu_flags
;
1918 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1920 x
.bitfield
.cpu64
= 0;
1921 x
.bitfield
.cpuno64
= 0;
1923 if (cpu_flags_all_zero (&x
))
1925 /* This instruction is available on all archs. */
1926 match
|= CPU_FLAGS_ARCH_MATCH
;
1930 /* This instruction is available only on some archs. */
1931 i386_cpu_flags cpu
= cpu_arch_flags
;
1933 /* AVX512VL is no standalone feature - match it and then strip it. */
1934 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1936 x
.bitfield
.cpuavx512vl
= 0;
1938 cpu
= cpu_flags_and (x
, cpu
);
1939 if (!cpu_flags_all_zero (&cpu
))
1941 if (x
.bitfield
.cpuavx
)
1943 /* We need to check a few extra flags with AVX. */
1944 if (cpu
.bitfield
.cpuavx
1945 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1946 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1947 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1948 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1949 match
|= CPU_FLAGS_ARCH_MATCH
;
1951 else if (x
.bitfield
.cpuavx512f
)
1953 /* We need to check a few extra flags with AVX512F. */
1954 if (cpu
.bitfield
.cpuavx512f
1955 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1956 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1957 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1958 match
|= CPU_FLAGS_ARCH_MATCH
;
1961 match
|= CPU_FLAGS_ARCH_MATCH
;
1967 static INLINE i386_operand_type
1968 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1970 if (x
.bitfield
.class != y
.bitfield
.class)
1971 x
.bitfield
.class = ClassNone
;
1972 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1973 x
.bitfield
.instance
= InstanceNone
;
1975 switch (ARRAY_SIZE (x
.array
))
1978 x
.array
[2] &= y
.array
[2];
1981 x
.array
[1] &= y
.array
[1];
1984 x
.array
[0] &= y
.array
[0];
1992 static INLINE i386_operand_type
1993 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1995 gas_assert (y
.bitfield
.class == ClassNone
);
1996 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1998 switch (ARRAY_SIZE (x
.array
))
2001 x
.array
[2] &= ~y
.array
[2];
2004 x
.array
[1] &= ~y
.array
[1];
2007 x
.array
[0] &= ~y
.array
[0];
2015 static INLINE i386_operand_type
2016 operand_type_or (i386_operand_type x
, i386_operand_type y
)
2018 gas_assert (x
.bitfield
.class == ClassNone
||
2019 y
.bitfield
.class == ClassNone
||
2020 x
.bitfield
.class == y
.bitfield
.class);
2021 gas_assert (x
.bitfield
.instance
== InstanceNone
||
2022 y
.bitfield
.instance
== InstanceNone
||
2023 x
.bitfield
.instance
== y
.bitfield
.instance
);
2025 switch (ARRAY_SIZE (x
.array
))
2028 x
.array
[2] |= y
.array
[2];
2031 x
.array
[1] |= y
.array
[1];
2034 x
.array
[0] |= y
.array
[0];
2042 static INLINE i386_operand_type
2043 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2045 gas_assert (y
.bitfield
.class == ClassNone
);
2046 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2048 switch (ARRAY_SIZE (x
.array
))
2051 x
.array
[2] ^= y
.array
[2];
2054 x
.array
[1] ^= y
.array
[1];
2057 x
.array
[0] ^= y
.array
[0];
2065 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2066 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2067 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2068 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2069 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2070 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2071 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2072 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2073 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2074 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2075 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2076 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2077 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2078 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2079 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2080 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2081 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2092 operand_type_check (i386_operand_type t
, enum operand_type c
)
2097 return t
.bitfield
.class == Reg
;
2100 return (t
.bitfield
.imm8
2104 || t
.bitfield
.imm32s
2105 || t
.bitfield
.imm64
);
2108 return (t
.bitfield
.disp8
2109 || t
.bitfield
.disp16
2110 || t
.bitfield
.disp32
2111 || t
.bitfield
.disp32s
2112 || t
.bitfield
.disp64
);
2115 return (t
.bitfield
.disp8
2116 || t
.bitfield
.disp16
2117 || t
.bitfield
.disp32
2118 || t
.bitfield
.disp32s
2119 || t
.bitfield
.disp64
2120 || t
.bitfield
.baseindex
);
2129 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2130 between operand GIVEN and opeand WANTED for instruction template T. */
2133 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2136 return !((i
.types
[given
].bitfield
.byte
2137 && !t
->operand_types
[wanted
].bitfield
.byte
)
2138 || (i
.types
[given
].bitfield
.word
2139 && !t
->operand_types
[wanted
].bitfield
.word
)
2140 || (i
.types
[given
].bitfield
.dword
2141 && !t
->operand_types
[wanted
].bitfield
.dword
)
2142 || (i
.types
[given
].bitfield
.qword
2143 && !t
->operand_types
[wanted
].bitfield
.qword
)
2144 || (i
.types
[given
].bitfield
.tbyte
2145 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2148 /* Return 1 if there is no conflict in SIMD register between operand
2149 GIVEN and opeand WANTED for instruction template T. */
2152 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2155 return !((i
.types
[given
].bitfield
.xmmword
2156 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2157 || (i
.types
[given
].bitfield
.ymmword
2158 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2159 || (i
.types
[given
].bitfield
.zmmword
2160 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2163 /* Return 1 if there is no conflict in any size between operand GIVEN
2164 and opeand WANTED for instruction template T. */
2167 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2170 return (match_operand_size (t
, wanted
, given
)
2171 && !((i
.types
[given
].bitfield
.unspecified
2173 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2174 || (i
.types
[given
].bitfield
.fword
2175 && !t
->operand_types
[wanted
].bitfield
.fword
)
2176 /* For scalar opcode templates to allow register and memory
2177 operands at the same time, some special casing is needed
2178 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2179 down-conversion vpmov*. */
2180 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2181 && t
->operand_types
[wanted
].bitfield
.byte
2182 + t
->operand_types
[wanted
].bitfield
.word
2183 + t
->operand_types
[wanted
].bitfield
.dword
2184 + t
->operand_types
[wanted
].bitfield
.qword
2185 > !!t
->opcode_modifier
.broadcast
)
2186 ? (i
.types
[given
].bitfield
.xmmword
2187 || i
.types
[given
].bitfield
.ymmword
2188 || i
.types
[given
].bitfield
.zmmword
)
2189 : !match_simd_size(t
, wanted
, given
))));
2192 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2193 operands for instruction template T, and it has MATCH_REVERSE set if there
2194 is no size conflict on any operands for the template with operands reversed
2195 (and the template allows for reversing in the first place). */
2197 #define MATCH_STRAIGHT 1
2198 #define MATCH_REVERSE 2
2200 static INLINE
unsigned int
2201 operand_size_match (const insn_template
*t
)
2203 unsigned int j
, match
= MATCH_STRAIGHT
;
2205 /* Don't check non-absolute jump instructions. */
2206 if (t
->opcode_modifier
.jump
2207 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2210 /* Check memory and accumulator operand size. */
2211 for (j
= 0; j
< i
.operands
; j
++)
2213 if (i
.types
[j
].bitfield
.class != Reg
2214 && i
.types
[j
].bitfield
.class != RegSIMD
2215 && t
->opcode_modifier
.anysize
)
2218 if (t
->operand_types
[j
].bitfield
.class == Reg
2219 && !match_operand_size (t
, j
, j
))
2225 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2226 && !match_simd_size (t
, j
, j
))
2232 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2233 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2239 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2246 if (!t
->opcode_modifier
.d
)
2250 i
.error
= operand_size_mismatch
;
2254 /* Check reverse. */
2255 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2257 for (j
= 0; j
< i
.operands
; j
++)
2259 unsigned int given
= i
.operands
- j
- 1;
2261 if (t
->operand_types
[j
].bitfield
.class == Reg
2262 && !match_operand_size (t
, j
, given
))
2265 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2266 && !match_simd_size (t
, j
, given
))
2269 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2270 && (!match_operand_size (t
, j
, given
)
2271 || !match_simd_size (t
, j
, given
)))
2274 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2278 return match
| MATCH_REVERSE
;
2282 operand_type_match (i386_operand_type overlap
,
2283 i386_operand_type given
)
2285 i386_operand_type temp
= overlap
;
2287 temp
.bitfield
.unspecified
= 0;
2288 temp
.bitfield
.byte
= 0;
2289 temp
.bitfield
.word
= 0;
2290 temp
.bitfield
.dword
= 0;
2291 temp
.bitfield
.fword
= 0;
2292 temp
.bitfield
.qword
= 0;
2293 temp
.bitfield
.tbyte
= 0;
2294 temp
.bitfield
.xmmword
= 0;
2295 temp
.bitfield
.ymmword
= 0;
2296 temp
.bitfield
.zmmword
= 0;
2297 if (operand_type_all_zero (&temp
))
2300 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2304 i
.error
= operand_type_mismatch
;
2308 /* If given types g0 and g1 are registers they must be of the same type
2309 unless the expected operand type register overlap is null.
2310 Some Intel syntax memory operand size checking also happens here. */
2313 operand_type_register_match (i386_operand_type g0
,
2314 i386_operand_type t0
,
2315 i386_operand_type g1
,
2316 i386_operand_type t1
)
2318 if (g0
.bitfield
.class != Reg
2319 && g0
.bitfield
.class != RegSIMD
2320 && (!operand_type_check (g0
, anymem
)
2321 || g0
.bitfield
.unspecified
2322 || (t0
.bitfield
.class != Reg
2323 && t0
.bitfield
.class != RegSIMD
)))
2326 if (g1
.bitfield
.class != Reg
2327 && g1
.bitfield
.class != RegSIMD
2328 && (!operand_type_check (g1
, anymem
)
2329 || g1
.bitfield
.unspecified
2330 || (t1
.bitfield
.class != Reg
2331 && t1
.bitfield
.class != RegSIMD
)))
2334 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2335 && g0
.bitfield
.word
== g1
.bitfield
.word
2336 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2337 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2338 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2339 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2340 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2343 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2344 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2345 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2346 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2347 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2348 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2349 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2352 i
.error
= register_type_mismatch
;
2357 static INLINE
unsigned int
2358 register_number (const reg_entry
*r
)
2360 unsigned int nr
= r
->reg_num
;
2362 if (r
->reg_flags
& RegRex
)
2365 if (r
->reg_flags
& RegVRex
)
2371 static INLINE
unsigned int
2372 mode_from_disp_size (i386_operand_type t
)
2374 if (t
.bitfield
.disp8
)
2376 else if (t
.bitfield
.disp16
2377 || t
.bitfield
.disp32
2378 || t
.bitfield
.disp32s
)
2385 fits_in_signed_byte (addressT num
)
2387 return num
+ 0x80 <= 0xff;
2391 fits_in_unsigned_byte (addressT num
)
2397 fits_in_unsigned_word (addressT num
)
2399 return num
<= 0xffff;
2403 fits_in_signed_word (addressT num
)
2405 return num
+ 0x8000 <= 0xffff;
2409 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2414 return num
+ 0x80000000 <= 0xffffffff;
2416 } /* fits_in_signed_long() */
2419 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2424 return num
<= 0xffffffff;
2426 } /* fits_in_unsigned_long() */
2429 fits_in_disp8 (offsetT num
)
2431 int shift
= i
.memshift
;
2437 mask
= (1 << shift
) - 1;
2439 /* Return 0 if NUM isn't properly aligned. */
2443 /* Check if NUM will fit in 8bit after shift. */
2444 return fits_in_signed_byte (num
>> shift
);
2448 fits_in_imm4 (offsetT num
)
2450 return (num
& 0xf) == num
;
2453 static i386_operand_type
2454 smallest_imm_type (offsetT num
)
2456 i386_operand_type t
;
2458 operand_type_set (&t
, 0);
2459 t
.bitfield
.imm64
= 1;
2461 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2463 /* This code is disabled on the 486 because all the Imm1 forms
2464 in the opcode table are slower on the i486. They're the
2465 versions with the implicitly specified single-position
2466 displacement, which has another syntax if you really want to
2468 t
.bitfield
.imm1
= 1;
2469 t
.bitfield
.imm8
= 1;
2470 t
.bitfield
.imm8s
= 1;
2471 t
.bitfield
.imm16
= 1;
2472 t
.bitfield
.imm32
= 1;
2473 t
.bitfield
.imm32s
= 1;
2475 else if (fits_in_signed_byte (num
))
2477 t
.bitfield
.imm8
= 1;
2478 t
.bitfield
.imm8s
= 1;
2479 t
.bitfield
.imm16
= 1;
2480 t
.bitfield
.imm32
= 1;
2481 t
.bitfield
.imm32s
= 1;
2483 else if (fits_in_unsigned_byte (num
))
2485 t
.bitfield
.imm8
= 1;
2486 t
.bitfield
.imm16
= 1;
2487 t
.bitfield
.imm32
= 1;
2488 t
.bitfield
.imm32s
= 1;
2490 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2492 t
.bitfield
.imm16
= 1;
2493 t
.bitfield
.imm32
= 1;
2494 t
.bitfield
.imm32s
= 1;
2496 else if (fits_in_signed_long (num
))
2498 t
.bitfield
.imm32
= 1;
2499 t
.bitfield
.imm32s
= 1;
2501 else if (fits_in_unsigned_long (num
))
2502 t
.bitfield
.imm32
= 1;
2508 offset_in_range (offsetT val
, int size
)
2514 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2515 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2516 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2518 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2524 /* If BFD64, sign extend val for 32bit address mode. */
2525 if (flag_code
!= CODE_64BIT
2526 || i
.prefix
[ADDR_PREFIX
])
2527 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2528 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2531 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2533 char buf1
[40], buf2
[40];
2535 sprint_value (buf1
, val
);
2536 sprint_value (buf2
, val
& mask
);
2537 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2552 a. PREFIX_EXIST if attempting to add a prefix where one from the
2553 same class already exists.
2554 b. PREFIX_LOCK if lock prefix is added.
2555 c. PREFIX_REP if rep/repne prefix is added.
2556 d. PREFIX_DS if ds prefix is added.
2557 e. PREFIX_OTHER if other prefix is added.
2560 static enum PREFIX_GROUP
2561 add_prefix (unsigned int prefix
)
2563 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2566 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2567 && flag_code
== CODE_64BIT
)
2569 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2570 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2571 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2572 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2583 case DS_PREFIX_OPCODE
:
2586 case CS_PREFIX_OPCODE
:
2587 case ES_PREFIX_OPCODE
:
2588 case FS_PREFIX_OPCODE
:
2589 case GS_PREFIX_OPCODE
:
2590 case SS_PREFIX_OPCODE
:
2594 case REPNE_PREFIX_OPCODE
:
2595 case REPE_PREFIX_OPCODE
:
2600 case LOCK_PREFIX_OPCODE
:
2609 case ADDR_PREFIX_OPCODE
:
2613 case DATA_PREFIX_OPCODE
:
2617 if (i
.prefix
[q
] != 0)
2625 i
.prefix
[q
] |= prefix
;
2628 as_bad (_("same type of prefix used twice"));
2634 update_code_flag (int value
, int check
)
2636 PRINTF_LIKE ((*as_error
));
2638 flag_code
= (enum flag_code
) value
;
2639 if (flag_code
== CODE_64BIT
)
2641 cpu_arch_flags
.bitfield
.cpu64
= 1;
2642 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2646 cpu_arch_flags
.bitfield
.cpu64
= 0;
2647 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2649 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2652 as_error
= as_fatal
;
2655 (*as_error
) (_("64bit mode not supported on `%s'."),
2656 cpu_arch_name
? cpu_arch_name
: default_arch
);
2658 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2661 as_error
= as_fatal
;
2664 (*as_error
) (_("32bit mode not supported on `%s'."),
2665 cpu_arch_name
? cpu_arch_name
: default_arch
);
2667 stackop_size
= '\0';
2671 set_code_flag (int value
)
2673 update_code_flag (value
, 0);
2677 set_16bit_gcc_code_flag (int new_code_flag
)
2679 flag_code
= (enum flag_code
) new_code_flag
;
2680 if (flag_code
!= CODE_16BIT
)
2682 cpu_arch_flags
.bitfield
.cpu64
= 0;
2683 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2684 stackop_size
= LONG_MNEM_SUFFIX
;
2688 set_intel_syntax (int syntax_flag
)
2690 /* Find out if register prefixing is specified. */
2691 int ask_naked_reg
= 0;
2694 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2697 int e
= get_symbol_name (&string
);
2699 if (strcmp (string
, "prefix") == 0)
2701 else if (strcmp (string
, "noprefix") == 0)
2704 as_bad (_("bad argument to syntax directive."));
2705 (void) restore_line_pointer (e
);
2707 demand_empty_rest_of_line ();
2709 intel_syntax
= syntax_flag
;
2711 if (ask_naked_reg
== 0)
2712 allow_naked_reg
= (intel_syntax
2713 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2715 allow_naked_reg
= (ask_naked_reg
< 0);
2717 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2719 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2720 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2721 register_prefix
= allow_naked_reg
? "" : "%";
2725 set_intel_mnemonic (int mnemonic_flag
)
2727 intel_mnemonic
= mnemonic_flag
;
2731 set_allow_index_reg (int flag
)
2733 allow_index_reg
= flag
;
2737 set_check (int what
)
2739 enum check_kind
*kind
;
2744 kind
= &operand_check
;
2755 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2758 int e
= get_symbol_name (&string
);
2760 if (strcmp (string
, "none") == 0)
2762 else if (strcmp (string
, "warning") == 0)
2763 *kind
= check_warning
;
2764 else if (strcmp (string
, "error") == 0)
2765 *kind
= check_error
;
2767 as_bad (_("bad argument to %s_check directive."), str
);
2768 (void) restore_line_pointer (e
);
2771 as_bad (_("missing argument for %s_check directive"), str
);
2773 demand_empty_rest_of_line ();
2777 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2778 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2780 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2781 static const char *arch
;
2783 /* Intel LIOM is only supported on ELF. */
2789 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2790 use default_arch. */
2791 arch
= cpu_arch_name
;
2793 arch
= default_arch
;
2796 /* If we are targeting Intel MCU, we must enable it. */
2797 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2798 || new_flag
.bitfield
.cpuiamcu
)
2801 /* If we are targeting Intel L1OM, we must enable it. */
2802 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2803 || new_flag
.bitfield
.cpul1om
)
2806 /* If we are targeting Intel K1OM, we must enable it. */
2807 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2808 || new_flag
.bitfield
.cpuk1om
)
2811 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2816 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2820 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2823 int e
= get_symbol_name (&string
);
2825 i386_cpu_flags flags
;
2827 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2829 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2831 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2835 cpu_arch_name
= cpu_arch
[j
].name
;
2836 cpu_sub_arch_name
= NULL
;
2837 cpu_arch_flags
= cpu_arch
[j
].flags
;
2838 if (flag_code
== CODE_64BIT
)
2840 cpu_arch_flags
.bitfield
.cpu64
= 1;
2841 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2845 cpu_arch_flags
.bitfield
.cpu64
= 0;
2846 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2848 cpu_arch_isa
= cpu_arch
[j
].type
;
2849 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2850 if (!cpu_arch_tune_set
)
2852 cpu_arch_tune
= cpu_arch_isa
;
2853 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2858 flags
= cpu_flags_or (cpu_arch_flags
,
2861 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2863 if (cpu_sub_arch_name
)
2865 char *name
= cpu_sub_arch_name
;
2866 cpu_sub_arch_name
= concat (name
,
2868 (const char *) NULL
);
2872 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2873 cpu_arch_flags
= flags
;
2874 cpu_arch_isa_flags
= flags
;
2878 = cpu_flags_or (cpu_arch_isa_flags
,
2880 (void) restore_line_pointer (e
);
2881 demand_empty_rest_of_line ();
2886 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2888 /* Disable an ISA extension. */
2889 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2890 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2892 flags
= cpu_flags_and_not (cpu_arch_flags
,
2893 cpu_noarch
[j
].flags
);
2894 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2896 if (cpu_sub_arch_name
)
2898 char *name
= cpu_sub_arch_name
;
2899 cpu_sub_arch_name
= concat (name
, string
,
2900 (const char *) NULL
);
2904 cpu_sub_arch_name
= xstrdup (string
);
2905 cpu_arch_flags
= flags
;
2906 cpu_arch_isa_flags
= flags
;
2908 (void) restore_line_pointer (e
);
2909 demand_empty_rest_of_line ();
2913 j
= ARRAY_SIZE (cpu_arch
);
2916 if (j
>= ARRAY_SIZE (cpu_arch
))
2917 as_bad (_("no such architecture: `%s'"), string
);
2919 *input_line_pointer
= e
;
2922 as_bad (_("missing cpu architecture"));
2924 no_cond_jump_promotion
= 0;
2925 if (*input_line_pointer
== ','
2926 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2931 ++input_line_pointer
;
2932 e
= get_symbol_name (&string
);
2934 if (strcmp (string
, "nojumps") == 0)
2935 no_cond_jump_promotion
= 1;
2936 else if (strcmp (string
, "jumps") == 0)
2939 as_bad (_("no such architecture modifier: `%s'"), string
);
2941 (void) restore_line_pointer (e
);
2944 demand_empty_rest_of_line ();
2947 enum bfd_architecture
2950 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2952 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2953 || flag_code
!= CODE_64BIT
)
2954 as_fatal (_("Intel L1OM is 64bit ELF only"));
2955 return bfd_arch_l1om
;
2957 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2959 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2960 || flag_code
!= CODE_64BIT
)
2961 as_fatal (_("Intel K1OM is 64bit ELF only"));
2962 return bfd_arch_k1om
;
2964 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2966 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2967 || flag_code
== CODE_64BIT
)
2968 as_fatal (_("Intel MCU is 32bit ELF only"));
2969 return bfd_arch_iamcu
;
2972 return bfd_arch_i386
;
2978 if (!strncmp (default_arch
, "x86_64", 6))
2980 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2982 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2983 || default_arch
[6] != '\0')
2984 as_fatal (_("Intel L1OM is 64bit ELF only"));
2985 return bfd_mach_l1om
;
2987 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2989 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2990 || default_arch
[6] != '\0')
2991 as_fatal (_("Intel K1OM is 64bit ELF only"));
2992 return bfd_mach_k1om
;
2994 else if (default_arch
[6] == '\0')
2995 return bfd_mach_x86_64
;
2997 return bfd_mach_x64_32
;
2999 else if (!strcmp (default_arch
, "i386")
3000 || !strcmp (default_arch
, "iamcu"))
3002 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3004 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3005 as_fatal (_("Intel MCU is 32bit ELF only"));
3006 return bfd_mach_i386_iamcu
;
3009 return bfd_mach_i386_i386
;
3012 as_fatal (_("unknown architecture"));
3018 const char *hash_err
;
3020 /* Support pseudo prefixes like {disp32}. */
3021 lex_type
['{'] = LEX_BEGIN_NAME
;
3023 /* Initialize op_hash hash table. */
3024 op_hash
= hash_new ();
3027 const insn_template
*optab
;
3028 templates
*core_optab
;
3030 /* Setup for loop. */
3032 core_optab
= XNEW (templates
);
3033 core_optab
->start
= optab
;
3038 if (optab
->name
== NULL
3039 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
3041 /* different name --> ship out current template list;
3042 add to hash table; & begin anew. */
3043 core_optab
->end
= optab
;
3044 hash_err
= hash_insert (op_hash
,
3046 (void *) core_optab
);
3049 as_fatal (_("can't hash %s: %s"),
3053 if (optab
->name
== NULL
)
3055 core_optab
= XNEW (templates
);
3056 core_optab
->start
= optab
;
3061 /* Initialize reg_hash hash table. */
3062 reg_hash
= hash_new ();
3064 const reg_entry
*regtab
;
3065 unsigned int regtab_size
= i386_regtab_size
;
3067 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3069 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3071 as_fatal (_("can't hash %s: %s"),
3077 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3082 for (c
= 0; c
< 256; c
++)
3087 mnemonic_chars
[c
] = c
;
3088 register_chars
[c
] = c
;
3089 operand_chars
[c
] = c
;
3091 else if (ISLOWER (c
))
3093 mnemonic_chars
[c
] = c
;
3094 register_chars
[c
] = c
;
3095 operand_chars
[c
] = c
;
3097 else if (ISUPPER (c
))
3099 mnemonic_chars
[c
] = TOLOWER (c
);
3100 register_chars
[c
] = mnemonic_chars
[c
];
3101 operand_chars
[c
] = c
;
3103 else if (c
== '{' || c
== '}')
3105 mnemonic_chars
[c
] = c
;
3106 operand_chars
[c
] = c
;
3109 if (ISALPHA (c
) || ISDIGIT (c
))
3110 identifier_chars
[c
] = c
;
3113 identifier_chars
[c
] = c
;
3114 operand_chars
[c
] = c
;
3119 identifier_chars
['@'] = '@';
3122 identifier_chars
['?'] = '?';
3123 operand_chars
['?'] = '?';
3125 digit_chars
['-'] = '-';
3126 mnemonic_chars
['_'] = '_';
3127 mnemonic_chars
['-'] = '-';
3128 mnemonic_chars
['.'] = '.';
3129 identifier_chars
['_'] = '_';
3130 identifier_chars
['.'] = '.';
3132 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3133 operand_chars
[(unsigned char) *p
] = *p
;
3136 if (flag_code
== CODE_64BIT
)
3138 #if defined (OBJ_COFF) && defined (TE_PE)
3139 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3142 x86_dwarf2_return_column
= 16;
3144 x86_cie_data_alignment
= -8;
3148 x86_dwarf2_return_column
= 8;
3149 x86_cie_data_alignment
= -4;
3152 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3153 can be turned into BRANCH_PREFIX frag. */
3154 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3159 i386_print_statistics (FILE *file
)
3161 hash_print_statistics (file
, "i386 opcode", op_hash
);
3162 hash_print_statistics (file
, "i386 register", reg_hash
);
3167 /* Debugging routines for md_assemble. */
3168 static void pte (insn_template
*);
3169 static void pt (i386_operand_type
);
3170 static void pe (expressionS
*);
3171 static void ps (symbolS
*);
3174 pi (const char *line
, i386_insn
*x
)
3178 fprintf (stdout
, "%s: template ", line
);
3180 fprintf (stdout
, " address: base %s index %s scale %x\n",
3181 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3182 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3183 x
->log2_scale_factor
);
3184 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3185 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3186 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3187 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3188 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3189 (x
->rex
& REX_W
) != 0,
3190 (x
->rex
& REX_R
) != 0,
3191 (x
->rex
& REX_X
) != 0,
3192 (x
->rex
& REX_B
) != 0);
3193 for (j
= 0; j
< x
->operands
; j
++)
3195 fprintf (stdout
, " #%d: ", j
+ 1);
3197 fprintf (stdout
, "\n");
3198 if (x
->types
[j
].bitfield
.class == Reg
3199 || x
->types
[j
].bitfield
.class == RegMMX
3200 || x
->types
[j
].bitfield
.class == RegSIMD
3201 || x
->types
[j
].bitfield
.class == SReg
3202 || x
->types
[j
].bitfield
.class == RegCR
3203 || x
->types
[j
].bitfield
.class == RegDR
3204 || x
->types
[j
].bitfield
.class == RegTR
)
3205 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3206 if (operand_type_check (x
->types
[j
], imm
))
3208 if (operand_type_check (x
->types
[j
], disp
))
3209 pe (x
->op
[j
].disps
);
3214 pte (insn_template
*t
)
3217 fprintf (stdout
, " %d operands ", t
->operands
);
3218 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3219 if (t
->extension_opcode
!= None
)
3220 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3221 if (t
->opcode_modifier
.d
)
3222 fprintf (stdout
, "D");
3223 if (t
->opcode_modifier
.w
)
3224 fprintf (stdout
, "W");
3225 fprintf (stdout
, "\n");
3226 for (j
= 0; j
< t
->operands
; j
++)
3228 fprintf (stdout
, " #%d type ", j
+ 1);
3229 pt (t
->operand_types
[j
]);
3230 fprintf (stdout
, "\n");
3237 fprintf (stdout
, " operation %d\n", e
->X_op
);
3238 fprintf (stdout
, " add_number %ld (%lx)\n",
3239 (long) e
->X_add_number
, (long) e
->X_add_number
);
3240 if (e
->X_add_symbol
)
3242 fprintf (stdout
, " add_symbol ");
3243 ps (e
->X_add_symbol
);
3244 fprintf (stdout
, "\n");
3248 fprintf (stdout
, " op_symbol ");
3249 ps (e
->X_op_symbol
);
3250 fprintf (stdout
, "\n");
3257 fprintf (stdout
, "%s type %s%s",
3259 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3260 segment_name (S_GET_SEGMENT (s
)));
3263 static struct type_name
3265 i386_operand_type mask
;
3268 const type_names
[] =
3270 { OPERAND_TYPE_REG8
, "r8" },
3271 { OPERAND_TYPE_REG16
, "r16" },
3272 { OPERAND_TYPE_REG32
, "r32" },
3273 { OPERAND_TYPE_REG64
, "r64" },
3274 { OPERAND_TYPE_ACC8
, "acc8" },
3275 { OPERAND_TYPE_ACC16
, "acc16" },
3276 { OPERAND_TYPE_ACC32
, "acc32" },
3277 { OPERAND_TYPE_ACC64
, "acc64" },
3278 { OPERAND_TYPE_IMM8
, "i8" },
3279 { OPERAND_TYPE_IMM8
, "i8s" },
3280 { OPERAND_TYPE_IMM16
, "i16" },
3281 { OPERAND_TYPE_IMM32
, "i32" },
3282 { OPERAND_TYPE_IMM32S
, "i32s" },
3283 { OPERAND_TYPE_IMM64
, "i64" },
3284 { OPERAND_TYPE_IMM1
, "i1" },
3285 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3286 { OPERAND_TYPE_DISP8
, "d8" },
3287 { OPERAND_TYPE_DISP16
, "d16" },
3288 { OPERAND_TYPE_DISP32
, "d32" },
3289 { OPERAND_TYPE_DISP32S
, "d32s" },
3290 { OPERAND_TYPE_DISP64
, "d64" },
3291 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3292 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3293 { OPERAND_TYPE_CONTROL
, "control reg" },
3294 { OPERAND_TYPE_TEST
, "test reg" },
3295 { OPERAND_TYPE_DEBUG
, "debug reg" },
3296 { OPERAND_TYPE_FLOATREG
, "FReg" },
3297 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3298 { OPERAND_TYPE_SREG
, "SReg" },
3299 { OPERAND_TYPE_REGMMX
, "rMMX" },
3300 { OPERAND_TYPE_REGXMM
, "rXMM" },
3301 { OPERAND_TYPE_REGYMM
, "rYMM" },
3302 { OPERAND_TYPE_REGZMM
, "rZMM" },
3303 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3307 pt (i386_operand_type t
)
3310 i386_operand_type a
;
3312 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3314 a
= operand_type_and (t
, type_names
[j
].mask
);
3315 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3316 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3321 #endif /* DEBUG386 */
3323 static bfd_reloc_code_real_type
3324 reloc (unsigned int size
,
3327 bfd_reloc_code_real_type other
)
3329 if (other
!= NO_RELOC
)
3331 reloc_howto_type
*rel
;
3336 case BFD_RELOC_X86_64_GOT32
:
3337 return BFD_RELOC_X86_64_GOT64
;
3339 case BFD_RELOC_X86_64_GOTPLT64
:
3340 return BFD_RELOC_X86_64_GOTPLT64
;
3342 case BFD_RELOC_X86_64_PLTOFF64
:
3343 return BFD_RELOC_X86_64_PLTOFF64
;
3345 case BFD_RELOC_X86_64_GOTPC32
:
3346 other
= BFD_RELOC_X86_64_GOTPC64
;
3348 case BFD_RELOC_X86_64_GOTPCREL
:
3349 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3351 case BFD_RELOC_X86_64_TPOFF32
:
3352 other
= BFD_RELOC_X86_64_TPOFF64
;
3354 case BFD_RELOC_X86_64_DTPOFF32
:
3355 other
= BFD_RELOC_X86_64_DTPOFF64
;
3361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3362 if (other
== BFD_RELOC_SIZE32
)
3365 other
= BFD_RELOC_SIZE64
;
3368 as_bad (_("there are no pc-relative size relocations"));
3374 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3375 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3378 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3380 as_bad (_("unknown relocation (%u)"), other
);
3381 else if (size
!= bfd_get_reloc_size (rel
))
3382 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3383 bfd_get_reloc_size (rel
),
3385 else if (pcrel
&& !rel
->pc_relative
)
3386 as_bad (_("non-pc-relative relocation for pc-relative field"));
3387 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3389 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3391 as_bad (_("relocated field and relocation type differ in signedness"));
3400 as_bad (_("there are no unsigned pc-relative relocations"));
3403 case 1: return BFD_RELOC_8_PCREL
;
3404 case 2: return BFD_RELOC_16_PCREL
;
3405 case 4: return BFD_RELOC_32_PCREL
;
3406 case 8: return BFD_RELOC_64_PCREL
;
3408 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3415 case 4: return BFD_RELOC_X86_64_32S
;
3420 case 1: return BFD_RELOC_8
;
3421 case 2: return BFD_RELOC_16
;
3422 case 4: return BFD_RELOC_32
;
3423 case 8: return BFD_RELOC_64
;
3425 as_bad (_("cannot do %s %u byte relocation"),
3426 sign
> 0 ? "signed" : "unsigned", size
);
3432 /* Here we decide which fixups can be adjusted to make them relative to
3433 the beginning of the section instead of the symbol. Basically we need
3434 to make sure that the dynamic relocations are done correctly, so in
3435 some cases we force the original symbol to be used. */
3438 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3440 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3444 /* Don't adjust pc-relative references to merge sections in 64-bit
3446 if (use_rela_relocations
3447 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3451 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3452 and changed later by validate_fix. */
3453 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3454 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3457 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3458 for size relocations. */
3459 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3460 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3461 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3462 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3463 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3464 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3465 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3466 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3467 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3468 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3474 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3475 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3476 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3477 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3478 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3488 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3489 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3496 intel_float_operand (const char *mnemonic
)
3498 /* Note that the value returned is meaningful only for opcodes with (memory)
3499 operands, hence the code here is free to improperly handle opcodes that
3500 have no operands (for better performance and smaller code). */
3502 if (mnemonic
[0] != 'f')
3503 return 0; /* non-math */
3505 switch (mnemonic
[1])
3507 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3508 the fs segment override prefix not currently handled because no
3509 call path can make opcodes without operands get here */
3511 return 2 /* integer op */;
3513 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3514 return 3; /* fldcw/fldenv */
3517 if (mnemonic
[2] != 'o' /* fnop */)
3518 return 3; /* non-waiting control op */
3521 if (mnemonic
[2] == 's')
3522 return 3; /* frstor/frstpm */
3525 if (mnemonic
[2] == 'a')
3526 return 3; /* fsave */
3527 if (mnemonic
[2] == 't')
3529 switch (mnemonic
[3])
3531 case 'c': /* fstcw */
3532 case 'd': /* fstdw */
3533 case 'e': /* fstenv */
3534 case 's': /* fsts[gw] */
3540 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3541 return 0; /* fxsave/fxrstor are not really math ops */
3548 /* Build the VEX prefix. */
3551 build_vex_prefix (const insn_template
*t
)
3553 unsigned int register_specifier
;
3554 unsigned int implied_prefix
;
3555 unsigned int vector_length
;
3558 /* Check register specifier. */
3559 if (i
.vex
.register_specifier
)
3561 register_specifier
=
3562 ~register_number (i
.vex
.register_specifier
) & 0xf;
3563 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3566 register_specifier
= 0xf;
3568 /* Use 2-byte VEX prefix by swapping destination and source operand
3569 if there are more than 1 register operand. */
3570 if (i
.reg_operands
> 1
3571 && i
.vec_encoding
!= vex_encoding_vex3
3572 && i
.dir_encoding
== dir_encoding_default
3573 && i
.operands
== i
.reg_operands
3574 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3575 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3576 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3579 unsigned int xchg
= i
.operands
- 1;
3580 union i386_op temp_op
;
3581 i386_operand_type temp_type
;
3583 temp_type
= i
.types
[xchg
];
3584 i
.types
[xchg
] = i
.types
[0];
3585 i
.types
[0] = temp_type
;
3586 temp_op
= i
.op
[xchg
];
3587 i
.op
[xchg
] = i
.op
[0];
3590 gas_assert (i
.rm
.mode
== 3);
3594 i
.rm
.regmem
= i
.rm
.reg
;
3597 if (i
.tm
.opcode_modifier
.d
)
3598 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3599 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3600 else /* Use the next insn. */
3604 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3605 are no memory operands and at least 3 register ones. */
3606 if (i
.reg_operands
>= 3
3607 && i
.vec_encoding
!= vex_encoding_vex3
3608 && i
.reg_operands
== i
.operands
- i
.imm_operands
3609 && i
.tm
.opcode_modifier
.vex
3610 && i
.tm
.opcode_modifier
.commutative
3611 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3613 && i
.vex
.register_specifier
3614 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3616 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3617 union i386_op temp_op
;
3618 i386_operand_type temp_type
;
3620 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3621 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3622 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3623 &i
.types
[i
.operands
- 3]));
3624 gas_assert (i
.rm
.mode
== 3);
3626 temp_type
= i
.types
[xchg
];
3627 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3628 i
.types
[xchg
+ 1] = temp_type
;
3629 temp_op
= i
.op
[xchg
];
3630 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3631 i
.op
[xchg
+ 1] = temp_op
;
3634 xchg
= i
.rm
.regmem
| 8;
3635 i
.rm
.regmem
= ~register_specifier
& 0xf;
3636 gas_assert (!(i
.rm
.regmem
& 8));
3637 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3638 register_specifier
= ~xchg
& 0xf;
3641 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3642 vector_length
= avxscalar
;
3643 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3649 /* Determine vector length from the last multi-length vector
3652 for (op
= t
->operands
; op
--;)
3653 if (t
->operand_types
[op
].bitfield
.xmmword
3654 && t
->operand_types
[op
].bitfield
.ymmword
3655 && i
.types
[op
].bitfield
.ymmword
)
3662 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3667 case DATA_PREFIX_OPCODE
:
3670 case REPE_PREFIX_OPCODE
:
3673 case REPNE_PREFIX_OPCODE
:
3680 /* Check the REX.W bit and VEXW. */
3681 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3682 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3683 else if (i
.tm
.opcode_modifier
.vexw
)
3684 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3686 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3688 /* Use 2-byte VEX prefix if possible. */
3690 && i
.vec_encoding
!= vex_encoding_vex3
3691 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3692 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3694 /* 2-byte VEX prefix. */
3698 i
.vex
.bytes
[0] = 0xc5;
3700 /* Check the REX.R bit. */
3701 r
= (i
.rex
& REX_R
) ? 0 : 1;
3702 i
.vex
.bytes
[1] = (r
<< 7
3703 | register_specifier
<< 3
3704 | vector_length
<< 2
3709 /* 3-byte VEX prefix. */
3714 switch (i
.tm
.opcode_modifier
.vexopcode
)
3718 i
.vex
.bytes
[0] = 0xc4;
3722 i
.vex
.bytes
[0] = 0xc4;
3726 i
.vex
.bytes
[0] = 0xc4;
3730 i
.vex
.bytes
[0] = 0x8f;
3734 i
.vex
.bytes
[0] = 0x8f;
3738 i
.vex
.bytes
[0] = 0x8f;
3744 /* The high 3 bits of the second VEX byte are 1's compliment
3745 of RXB bits from REX. */
3746 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3748 i
.vex
.bytes
[2] = (w
<< 7
3749 | register_specifier
<< 3
3750 | vector_length
<< 2
3755 static INLINE bfd_boolean
3756 is_evex_encoding (const insn_template
*t
)
3758 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3759 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3760 || t
->opcode_modifier
.sae
;
3763 static INLINE bfd_boolean
3764 is_any_vex_encoding (const insn_template
*t
)
3766 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3767 || is_evex_encoding (t
);
3770 /* Build the EVEX prefix. */
3773 build_evex_prefix (void)
3775 unsigned int register_specifier
;
3776 unsigned int implied_prefix
;
3778 rex_byte vrex_used
= 0;
3780 /* Check register specifier. */
3781 if (i
.vex
.register_specifier
)
3783 gas_assert ((i
.vrex
& REX_X
) == 0);
3785 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3786 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3787 register_specifier
+= 8;
3788 /* The upper 16 registers are encoded in the fourth byte of the
3790 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3791 i
.vex
.bytes
[3] = 0x8;
3792 register_specifier
= ~register_specifier
& 0xf;
3796 register_specifier
= 0xf;
3798 /* Encode upper 16 vector index register in the fourth byte of
3800 if (!(i
.vrex
& REX_X
))
3801 i
.vex
.bytes
[3] = 0x8;
3806 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3811 case DATA_PREFIX_OPCODE
:
3814 case REPE_PREFIX_OPCODE
:
3817 case REPNE_PREFIX_OPCODE
:
3824 /* 4 byte EVEX prefix. */
3826 i
.vex
.bytes
[0] = 0x62;
3829 switch (i
.tm
.opcode_modifier
.vexopcode
)
3845 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3847 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3849 /* The fifth bit of the second EVEX byte is 1's compliment of the
3850 REX_R bit in VREX. */
3851 if (!(i
.vrex
& REX_R
))
3852 i
.vex
.bytes
[1] |= 0x10;
3856 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3858 /* When all operands are registers, the REX_X bit in REX is not
3859 used. We reuse it to encode the upper 16 registers, which is
3860 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3861 as 1's compliment. */
3862 if ((i
.vrex
& REX_B
))
3865 i
.vex
.bytes
[1] &= ~0x40;
3869 /* EVEX instructions shouldn't need the REX prefix. */
3870 i
.vrex
&= ~vrex_used
;
3871 gas_assert (i
.vrex
== 0);
3873 /* Check the REX.W bit and VEXW. */
3874 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3875 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3876 else if (i
.tm
.opcode_modifier
.vexw
)
3877 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3879 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3881 /* Encode the U bit. */
3882 implied_prefix
|= 0x4;
3884 /* The third byte of the EVEX prefix. */
3885 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3887 /* The fourth byte of the EVEX prefix. */
3888 /* The zeroing-masking bit. */
3889 if (i
.mask
&& i
.mask
->zeroing
)
3890 i
.vex
.bytes
[3] |= 0x80;
3892 /* Don't always set the broadcast bit if there is no RC. */
3895 /* Encode the vector length. */
3896 unsigned int vec_length
;
3898 if (!i
.tm
.opcode_modifier
.evex
3899 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3903 /* Determine vector length from the last multi-length vector
3906 for (op
= i
.operands
; op
--;)
3907 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3908 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3909 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3911 if (i
.types
[op
].bitfield
.zmmword
)
3913 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3916 else if (i
.types
[op
].bitfield
.ymmword
)
3918 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3921 else if (i
.types
[op
].bitfield
.xmmword
)
3923 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3926 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3928 switch (i
.broadcast
->bytes
)
3931 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3934 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3937 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3946 if (op
>= MAX_OPERANDS
)
3950 switch (i
.tm
.opcode_modifier
.evex
)
3952 case EVEXLIG
: /* LL' is ignored */
3953 vec_length
= evexlig
<< 5;
3956 vec_length
= 0 << 5;
3959 vec_length
= 1 << 5;
3962 vec_length
= 2 << 5;
3968 i
.vex
.bytes
[3] |= vec_length
;
3969 /* Encode the broadcast bit. */
3971 i
.vex
.bytes
[3] |= 0x10;
3975 if (i
.rounding
->type
!= saeonly
)
3976 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3978 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3981 if (i
.mask
&& i
.mask
->mask
)
3982 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3986 process_immext (void)
3990 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3991 which is coded in the same place as an 8-bit immediate field
3992 would be. Here we fake an 8-bit immediate operand from the
3993 opcode suffix stored in tm.extension_opcode.
3995 AVX instructions also use this encoding, for some of
3996 3 argument instructions. */
3998 gas_assert (i
.imm_operands
<= 1
4000 || (is_any_vex_encoding (&i
.tm
)
4001 && i
.operands
<= 4)));
4003 exp
= &im_expressions
[i
.imm_operands
++];
4004 i
.op
[i
.operands
].imms
= exp
;
4005 i
.types
[i
.operands
] = imm8
;
4007 exp
->X_op
= O_constant
;
4008 exp
->X_add_number
= i
.tm
.extension_opcode
;
4009 i
.tm
.extension_opcode
= None
;
4016 switch (i
.tm
.opcode_modifier
.hleprefixok
)
4021 as_bad (_("invalid instruction `%s' after `%s'"),
4022 i
.tm
.name
, i
.hle_prefix
);
4025 if (i
.prefix
[LOCK_PREFIX
])
4027 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4031 case HLEPrefixRelease
:
4032 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4034 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4038 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4040 as_bad (_("memory destination needed for instruction `%s'"
4041 " after `xrelease'"), i
.tm
.name
);
4048 /* Try the shortest encoding by shortening operand size. */
4051 optimize_encoding (void)
4055 if (optimize_for_space
4056 && !is_any_vex_encoding (&i
.tm
)
4057 && i
.reg_operands
== 1
4058 && i
.imm_operands
== 1
4059 && !i
.types
[1].bitfield
.byte
4060 && i
.op
[0].imms
->X_op
== O_constant
4061 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4062 && (i
.tm
.base_opcode
== 0xa8
4063 || (i
.tm
.base_opcode
== 0xf6
4064 && i
.tm
.extension_opcode
== 0x0)))
4067 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4069 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4070 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4072 i
.types
[1].bitfield
.byte
= 1;
4073 /* Ignore the suffix. */
4075 /* Convert to byte registers. */
4076 if (i
.types
[1].bitfield
.word
)
4078 else if (i
.types
[1].bitfield
.dword
)
4082 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4087 else if (flag_code
== CODE_64BIT
4088 && !is_any_vex_encoding (&i
.tm
)
4089 && ((i
.types
[1].bitfield
.qword
4090 && i
.reg_operands
== 1
4091 && i
.imm_operands
== 1
4092 && i
.op
[0].imms
->X_op
== O_constant
4093 && ((i
.tm
.base_opcode
== 0xb8
4094 && i
.tm
.extension_opcode
== None
4095 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4096 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4097 && ((i
.tm
.base_opcode
== 0x24
4098 || i
.tm
.base_opcode
== 0xa8)
4099 || (i
.tm
.base_opcode
== 0x80
4100 && i
.tm
.extension_opcode
== 0x4)
4101 || ((i
.tm
.base_opcode
== 0xf6
4102 || (i
.tm
.base_opcode
| 1) == 0xc7)
4103 && i
.tm
.extension_opcode
== 0x0)))
4104 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4105 && i
.tm
.base_opcode
== 0x83
4106 && i
.tm
.extension_opcode
== 0x4)))
4107 || (i
.types
[0].bitfield
.qword
4108 && ((i
.reg_operands
== 2
4109 && i
.op
[0].regs
== i
.op
[1].regs
4110 && (i
.tm
.base_opcode
== 0x30
4111 || i
.tm
.base_opcode
== 0x28))
4112 || (i
.reg_operands
== 1
4114 && i
.tm
.base_opcode
== 0x30)))))
4117 andq $imm31, %r64 -> andl $imm31, %r32
4118 andq $imm7, %r64 -> andl $imm7, %r32
4119 testq $imm31, %r64 -> testl $imm31, %r32
4120 xorq %r64, %r64 -> xorl %r32, %r32
4121 subq %r64, %r64 -> subl %r32, %r32
4122 movq $imm31, %r64 -> movl $imm31, %r32
4123 movq $imm32, %r64 -> movl $imm32, %r32
4125 i
.tm
.opcode_modifier
.norex64
= 1;
4126 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4129 movq $imm31, %r64 -> movl $imm31, %r32
4130 movq $imm32, %r64 -> movl $imm32, %r32
4132 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4133 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4134 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4135 i
.types
[0].bitfield
.imm32
= 1;
4136 i
.types
[0].bitfield
.imm32s
= 0;
4137 i
.types
[0].bitfield
.imm64
= 0;
4138 i
.types
[1].bitfield
.dword
= 1;
4139 i
.types
[1].bitfield
.qword
= 0;
4140 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4143 movq $imm31, %r64 -> movl $imm31, %r32
4145 i
.tm
.base_opcode
= 0xb8;
4146 i
.tm
.extension_opcode
= None
;
4147 i
.tm
.opcode_modifier
.w
= 0;
4148 i
.tm
.opcode_modifier
.modrm
= 0;
4152 else if (optimize
> 1
4153 && !optimize_for_space
4154 && !is_any_vex_encoding (&i
.tm
)
4155 && i
.reg_operands
== 2
4156 && i
.op
[0].regs
== i
.op
[1].regs
4157 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4158 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4159 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4162 andb %rN, %rN -> testb %rN, %rN
4163 andw %rN, %rN -> testw %rN, %rN
4164 andq %rN, %rN -> testq %rN, %rN
4165 orb %rN, %rN -> testb %rN, %rN
4166 orw %rN, %rN -> testw %rN, %rN
4167 orq %rN, %rN -> testq %rN, %rN
4169 and outside of 64-bit mode
4171 andl %rN, %rN -> testl %rN, %rN
4172 orl %rN, %rN -> testl %rN, %rN
4174 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4176 else if (i
.reg_operands
== 3
4177 && i
.op
[0].regs
== i
.op
[1].regs
4178 && !i
.types
[2].bitfield
.xmmword
4179 && (i
.tm
.opcode_modifier
.vex
4180 || ((!i
.mask
|| i
.mask
->zeroing
)
4182 && is_evex_encoding (&i
.tm
)
4183 && (i
.vec_encoding
!= vex_encoding_evex
4184 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4185 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4186 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4187 && i
.types
[2].bitfield
.ymmword
))))
4188 && ((i
.tm
.base_opcode
== 0x55
4189 || i
.tm
.base_opcode
== 0x6655
4190 || i
.tm
.base_opcode
== 0x66df
4191 || i
.tm
.base_opcode
== 0x57
4192 || i
.tm
.base_opcode
== 0x6657
4193 || i
.tm
.base_opcode
== 0x66ef
4194 || i
.tm
.base_opcode
== 0x66f8
4195 || i
.tm
.base_opcode
== 0x66f9
4196 || i
.tm
.base_opcode
== 0x66fa
4197 || i
.tm
.base_opcode
== 0x66fb
4198 || i
.tm
.base_opcode
== 0x42
4199 || i
.tm
.base_opcode
== 0x6642
4200 || i
.tm
.base_opcode
== 0x47
4201 || i
.tm
.base_opcode
== 0x6647)
4202 && i
.tm
.extension_opcode
== None
))
4205 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4207 EVEX VOP %zmmM, %zmmM, %zmmN
4208 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4209 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4210 EVEX VOP %ymmM, %ymmM, %ymmN
4211 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4212 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4213 VEX VOP %ymmM, %ymmM, %ymmN
4214 -> VEX VOP %xmmM, %xmmM, %xmmN
4215 VOP, one of vpandn and vpxor:
4216 VEX VOP %ymmM, %ymmM, %ymmN
4217 -> VEX VOP %xmmM, %xmmM, %xmmN
4218 VOP, one of vpandnd and vpandnq:
4219 EVEX VOP %zmmM, %zmmM, %zmmN
4220 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4221 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4222 EVEX VOP %ymmM, %ymmM, %ymmN
4223 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4224 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4225 VOP, one of vpxord and vpxorq:
4226 EVEX VOP %zmmM, %zmmM, %zmmN
4227 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 EVEX VOP %ymmM, %ymmM, %ymmN
4230 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4231 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4232 VOP, one of kxord and kxorq:
4233 VEX VOP %kM, %kM, %kN
4234 -> VEX kxorw %kM, %kM, %kN
4235 VOP, one of kandnd and kandnq:
4236 VEX VOP %kM, %kM, %kN
4237 -> VEX kandnw %kM, %kM, %kN
4239 if (is_evex_encoding (&i
.tm
))
4241 if (i
.vec_encoding
!= vex_encoding_evex
)
4243 i
.tm
.opcode_modifier
.vex
= VEX128
;
4244 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4245 i
.tm
.opcode_modifier
.evex
= 0;
4247 else if (optimize
> 1)
4248 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4252 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4254 i
.tm
.base_opcode
&= 0xff;
4255 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4258 i
.tm
.opcode_modifier
.vex
= VEX128
;
4260 if (i
.tm
.opcode_modifier
.vex
)
4261 for (j
= 0; j
< 3; j
++)
4263 i
.types
[j
].bitfield
.xmmword
= 1;
4264 i
.types
[j
].bitfield
.ymmword
= 0;
4267 else if (i
.vec_encoding
!= vex_encoding_evex
4268 && !i
.types
[0].bitfield
.zmmword
4269 && !i
.types
[1].bitfield
.zmmword
4272 && is_evex_encoding (&i
.tm
)
4273 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4274 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4275 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4276 || (i
.tm
.base_opcode
& ~4) == 0x66db
4277 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4278 && i
.tm
.extension_opcode
== None
)
4281 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4282 vmovdqu32 and vmovdqu64:
4283 EVEX VOP %xmmM, %xmmN
4284 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4285 EVEX VOP %ymmM, %ymmN
4286 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4288 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4290 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4292 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4294 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4295 VOP, one of vpand, vpandn, vpor, vpxor:
4296 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4297 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4298 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4299 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4300 EVEX VOP{d,q} mem, %xmmM, %xmmN
4301 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4302 EVEX VOP{d,q} mem, %ymmM, %ymmN
4303 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4305 for (j
= 0; j
< i
.operands
; j
++)
4306 if (operand_type_check (i
.types
[j
], disp
)
4307 && i
.op
[j
].disps
->X_op
== O_constant
)
4309 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4310 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4311 bytes, we choose EVEX Disp8 over VEX Disp32. */
4312 int evex_disp8
, vex_disp8
;
4313 unsigned int memshift
= i
.memshift
;
4314 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4316 evex_disp8
= fits_in_disp8 (n
);
4318 vex_disp8
= fits_in_disp8 (n
);
4319 if (evex_disp8
!= vex_disp8
)
4321 i
.memshift
= memshift
;
4325 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4328 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4329 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4330 i
.tm
.opcode_modifier
.vex
4331 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4332 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4333 /* VPAND, VPOR, and VPXOR are commutative. */
4334 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4335 i
.tm
.opcode_modifier
.commutative
= 1;
4336 i
.tm
.opcode_modifier
.evex
= 0;
4337 i
.tm
.opcode_modifier
.masking
= 0;
4338 i
.tm
.opcode_modifier
.broadcast
= 0;
4339 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4342 i
.types
[j
].bitfield
.disp8
4343 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4347 /* Return non-zero for load instruction. */
4353 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4354 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4358 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4359 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4360 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4361 if (i
.tm
.opcode_modifier
.anysize
)
4364 /* pop, popf, popa. */
4365 if (strcmp (i
.tm
.name
, "pop") == 0
4366 || i
.tm
.base_opcode
== 0x9d
4367 || i
.tm
.base_opcode
== 0x61)
4370 /* movs, cmps, lods, scas. */
4371 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4375 if (base_opcode
== 0x6f
4376 || i
.tm
.base_opcode
== 0xd7)
4378 /* NB: For AMD-specific insns with implicit memory operands,
4379 they're intentionally not covered. */
4382 /* No memory operand. */
4383 if (!i
.mem_operands
)
4389 if (i
.tm
.base_opcode
== 0xae
4390 && i
.tm
.opcode_modifier
.vex
4391 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
4392 && i
.tm
.extension_opcode
== 2)
4397 /* test, not, neg, mul, imul, div, idiv. */
4398 if ((i
.tm
.base_opcode
== 0xf6 || i
.tm
.base_opcode
== 0xf7)
4399 && i
.tm
.extension_opcode
!= 1)
4403 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4406 /* add, or, adc, sbb, and, sub, xor, cmp. */
4407 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4410 /* bt, bts, btr, btc. */
4411 if (i
.tm
.base_opcode
== 0xfba
4412 && (i
.tm
.extension_opcode
>= 4 && i
.tm
.extension_opcode
<= 7))
4415 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4416 if ((base_opcode
== 0xc1
4417 || (i
.tm
.base_opcode
>= 0xd0 && i
.tm
.base_opcode
<= 0xd3))
4418 && i
.tm
.extension_opcode
!= 6)
4421 /* cmpxchg8b, cmpxchg16b, xrstors. */
4422 if (i
.tm
.base_opcode
== 0xfc7
4423 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3))
4426 /* fxrstor, ldmxcsr, xrstor. */
4427 if (i
.tm
.base_opcode
== 0xfae
4428 && (i
.tm
.extension_opcode
== 1
4429 || i
.tm
.extension_opcode
== 2
4430 || i
.tm
.extension_opcode
== 5))
4433 /* lgdt, lidt, lmsw. */
4434 if (i
.tm
.base_opcode
== 0xf01
4435 && (i
.tm
.extension_opcode
== 2
4436 || i
.tm
.extension_opcode
== 3
4437 || i
.tm
.extension_opcode
== 6))
4441 if (i
.tm
.base_opcode
== 0xfc7
4442 && i
.tm
.extension_opcode
== 6)
4445 /* Check for x87 instructions. */
4446 if (i
.tm
.base_opcode
>= 0xd8 && i
.tm
.base_opcode
<= 0xdf)
4448 /* Skip fst, fstp, fstenv, fstcw. */
4449 if (i
.tm
.base_opcode
== 0xd9
4450 && (i
.tm
.extension_opcode
== 2
4451 || i
.tm
.extension_opcode
== 3
4452 || i
.tm
.extension_opcode
== 6
4453 || i
.tm
.extension_opcode
== 7))
4456 /* Skip fisttp, fist, fistp, fstp. */
4457 if (i
.tm
.base_opcode
== 0xdb
4458 && (i
.tm
.extension_opcode
== 1
4459 || i
.tm
.extension_opcode
== 2
4460 || i
.tm
.extension_opcode
== 3
4461 || i
.tm
.extension_opcode
== 7))
4464 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4465 if (i
.tm
.base_opcode
== 0xdd
4466 && (i
.tm
.extension_opcode
== 1
4467 || i
.tm
.extension_opcode
== 2
4468 || i
.tm
.extension_opcode
== 3
4469 || i
.tm
.extension_opcode
== 6
4470 || i
.tm
.extension_opcode
== 7))
4473 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4474 if (i
.tm
.base_opcode
== 0xdf
4475 && (i
.tm
.extension_opcode
== 1
4476 || i
.tm
.extension_opcode
== 2
4477 || i
.tm
.extension_opcode
== 3
4478 || i
.tm
.extension_opcode
== 6
4479 || i
.tm
.extension_opcode
== 7))
4486 dest
= i
.operands
- 1;
4488 /* Check fake imm8 operand and 3 source operands. */
4489 if ((i
.tm
.opcode_modifier
.immext
4490 || i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4491 && i
.types
[dest
].bitfield
.imm8
)
4494 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4496 && (base_opcode
== 0x1
4497 || base_opcode
== 0x9
4498 || base_opcode
== 0x11
4499 || base_opcode
== 0x19
4500 || base_opcode
== 0x21
4501 || base_opcode
== 0x29
4502 || base_opcode
== 0x31
4503 || base_opcode
== 0x39
4504 || (i
.tm
.base_opcode
>= 0x84 && i
.tm
.base_opcode
<= 0x87)
4505 || base_opcode
== 0xfc1))
4508 /* Check for load instruction. */
4509 return (i
.types
[dest
].bitfield
.class != ClassNone
4510 || i
.types
[dest
].bitfield
.instance
== Accum
);
4513 /* Output lfence, 0xfaee8, after instruction. */
4516 insert_lfence_after (void)
4518 if (lfence_after_load
&& load_insn_p ())
4520 /* There are also two REP string instructions that require
4521 special treatment. Specifically, the compare string (CMPS)
4522 and scan string (SCAS) instructions set EFLAGS in a manner
4523 that depends on the data being compared/scanned. When used
4524 with a REP prefix, the number of iterations may therefore
4525 vary depending on this data. If the data is a program secret
4526 chosen by the adversary using an LVI method,
4527 then this data-dependent behavior may leak some aspect
4529 if (((i
.tm
.base_opcode
| 0x1) == 0xa7
4530 || (i
.tm
.base_opcode
| 0x1) == 0xaf)
4531 && i
.prefix
[REP_PREFIX
])
4533 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4536 char *p
= frag_more (3);
4543 /* Output lfence, 0xfaee8, before instruction. */
4546 insert_lfence_before (void)
4550 if (is_any_vex_encoding (&i
.tm
))
4553 if (i
.tm
.base_opcode
== 0xff
4554 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4556 /* Insert lfence before indirect branch if needed. */
4558 if (lfence_before_indirect_branch
== lfence_branch_none
)
4561 if (i
.operands
!= 1)
4564 if (i
.reg_operands
== 1)
4566 /* Indirect branch via register. Don't insert lfence with
4567 -mlfence-after-load=yes. */
4568 if (lfence_after_load
4569 || lfence_before_indirect_branch
== lfence_branch_memory
)
4572 else if (i
.mem_operands
== 1
4573 && lfence_before_indirect_branch
!= lfence_branch_register
)
4575 as_warn (_("indirect `%s` with memory operand should be avoided"),
4582 if (last_insn
.kind
!= last_insn_other
4583 && last_insn
.seg
== now_seg
)
4585 as_warn_where (last_insn
.file
, last_insn
.line
,
4586 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4587 last_insn
.name
, i
.tm
.name
);
4598 /* Output or/not/shl and lfence before near ret. */
4599 if (lfence_before_ret
!= lfence_before_ret_none
4600 && (i
.tm
.base_opcode
== 0xc2
4601 || i
.tm
.base_opcode
== 0xc3))
4603 if (last_insn
.kind
!= last_insn_other
4604 && last_insn
.seg
== now_seg
)
4606 as_warn_where (last_insn
.file
, last_insn
.line
,
4607 _("`%s` skips -mlfence-before-ret on `%s`"),
4608 last_insn
.name
, i
.tm
.name
);
4612 /* Near ret ingore operand size override under CPU64. */
4613 char prefix
= flag_code
== CODE_64BIT
4615 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
4617 if (lfence_before_ret
== lfence_before_ret_not
)
4619 /* not: 0xf71424, may add prefix
4620 for operand size override or 64-bit code. */
4621 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
4635 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
4638 if (lfence_before_ret
== lfence_before_ret_or
)
4640 /* or: 0x830c2400, may add prefix
4641 for operand size override or 64-bit code. */
4647 /* shl: 0xc1242400, may add prefix
4648 for operand size override or 64-bit code. */
4663 /* This is the guts of the machine-dependent assembler. LINE points to a
4664 machine dependent instruction. This function is supposed to emit
4665 the frags/bytes it assembles to. */
4668 md_assemble (char *line
)
4671 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4672 const insn_template
*t
;
4674 /* Initialize globals. */
4675 memset (&i
, '\0', sizeof (i
));
4676 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4677 i
.reloc
[j
] = NO_RELOC
;
4678 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4679 memset (im_expressions
, '\0', sizeof (im_expressions
));
4680 save_stack_p
= save_stack
;
4682 /* First parse an instruction mnemonic & call i386_operand for the operands.
4683 We assume that the scrubber has arranged it so that line[0] is the valid
4684 start of a (possibly prefixed) mnemonic. */
4686 line
= parse_insn (line
, mnemonic
);
4689 mnem_suffix
= i
.suffix
;
4691 line
= parse_operands (line
, mnemonic
);
4693 xfree (i
.memop1_string
);
4694 i
.memop1_string
= NULL
;
4698 /* Now we've parsed the mnemonic into a set of templates, and have the
4699 operands at hand. */
4701 /* All Intel opcodes have reversed operands except for "bound", "enter",
4702 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4703 intersegment "jmp" and "call" instructions with 2 immediate operands so
4704 that the immediate segment precedes the offset, as it does when in AT&T
4708 && (strcmp (mnemonic
, "bound") != 0)
4709 && (strcmp (mnemonic
, "invlpga") != 0)
4710 && (strncmp (mnemonic
, "monitor", 7) != 0)
4711 && (strncmp (mnemonic
, "mwait", 5) != 0)
4712 && (strcmp (mnemonic
, "tpause") != 0)
4713 && (strcmp (mnemonic
, "umwait") != 0)
4714 && !(operand_type_check (i
.types
[0], imm
)
4715 && operand_type_check (i
.types
[1], imm
)))
4718 /* The order of the immediates should be reversed
4719 for 2 immediates extrq and insertq instructions */
4720 if (i
.imm_operands
== 2
4721 && (strcmp (mnemonic
, "extrq") == 0
4722 || strcmp (mnemonic
, "insertq") == 0))
4723 swap_2_operands (0, 1);
4728 /* Don't optimize displacement for movabs since it only takes 64bit
4731 && i
.disp_encoding
!= disp_encoding_32bit
4732 && (flag_code
!= CODE_64BIT
4733 || strcmp (mnemonic
, "movabs") != 0))
4736 /* Next, we find a template that matches the given insn,
4737 making sure the overlap of the given operands types is consistent
4738 with the template operand types. */
4740 if (!(t
= match_template (mnem_suffix
)))
4743 if (sse_check
!= check_none
4744 && !i
.tm
.opcode_modifier
.noavx
4745 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4746 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4747 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4748 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4749 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4750 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4751 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4752 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4753 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4754 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4755 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4756 || i
.tm
.cpu_flags
.bitfield
.cpusha
4757 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4759 (sse_check
== check_warning
4761 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4764 if (i
.tm
.opcode_modifier
.fwait
)
4765 if (!add_prefix (FWAIT_OPCODE
))
4768 /* Check if REP prefix is OK. */
4769 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4771 as_bad (_("invalid instruction `%s' after `%s'"),
4772 i
.tm
.name
, i
.rep_prefix
);
4776 /* Check for lock without a lockable instruction. Destination operand
4777 must be memory unless it is xchg (0x86). */
4778 if (i
.prefix
[LOCK_PREFIX
]
4779 && (!i
.tm
.opcode_modifier
.islockable
4780 || i
.mem_operands
== 0
4781 || (i
.tm
.base_opcode
!= 0x86
4782 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4784 as_bad (_("expecting lockable instruction after `lock'"));
4788 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4789 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4791 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4795 /* Check if HLE prefix is OK. */
4796 if (i
.hle_prefix
&& !check_hle ())
4799 /* Check BND prefix. */
4800 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4801 as_bad (_("expecting valid branch instruction after `bnd'"));
4803 /* Check NOTRACK prefix. */
4804 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4805 as_bad (_("expecting indirect branch instruction after `notrack'"));
4807 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4809 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4810 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4811 else if (flag_code
!= CODE_16BIT
4812 ? i
.prefix
[ADDR_PREFIX
]
4813 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4814 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4817 /* Insert BND prefix. */
4818 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4820 if (!i
.prefix
[BND_PREFIX
])
4821 add_prefix (BND_PREFIX_OPCODE
);
4822 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4824 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4825 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4829 /* Check string instruction segment overrides. */
4830 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4832 gas_assert (i
.mem_operands
);
4833 if (!check_string ())
4835 i
.disp_operands
= 0;
4838 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4839 optimize_encoding ();
4841 if (!process_suffix ())
4844 /* Update operand types. */
4845 for (j
= 0; j
< i
.operands
; j
++)
4846 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4848 /* Make still unresolved immediate matches conform to size of immediate
4849 given in i.suffix. */
4850 if (!finalize_imm ())
4853 if (i
.types
[0].bitfield
.imm1
)
4854 i
.imm_operands
= 0; /* kludge for shift insns. */
4856 /* We only need to check those implicit registers for instructions
4857 with 3 operands or less. */
4858 if (i
.operands
<= 3)
4859 for (j
= 0; j
< i
.operands
; j
++)
4860 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4861 && !i
.types
[j
].bitfield
.xmmword
)
4864 /* ImmExt should be processed after SSE2AVX. */
4865 if (!i
.tm
.opcode_modifier
.sse2avx
4866 && i
.tm
.opcode_modifier
.immext
)
4869 /* For insns with operands there are more diddles to do to the opcode. */
4872 if (!process_operands ())
4875 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4877 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4878 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4881 if (is_any_vex_encoding (&i
.tm
))
4883 if (!cpu_arch_flags
.bitfield
.cpui286
)
4885 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4890 if (i
.tm
.opcode_modifier
.vex
)
4891 build_vex_prefix (t
);
4893 build_evex_prefix ();
4896 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4897 instructions may define INT_OPCODE as well, so avoid this corner
4898 case for those instructions that use MODRM. */
4899 if (i
.tm
.base_opcode
== INT_OPCODE
4900 && !i
.tm
.opcode_modifier
.modrm
4901 && i
.op
[0].imms
->X_add_number
== 3)
4903 i
.tm
.base_opcode
= INT3_OPCODE
;
4907 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4908 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4909 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4910 && i
.op
[0].disps
->X_op
== O_constant
)
4912 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4913 the absolute address given by the constant. Since ix86 jumps and
4914 calls are pc relative, we need to generate a reloc. */
4915 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4916 i
.op
[0].disps
->X_op
= O_symbol
;
4919 /* For 8 bit registers we need an empty rex prefix. Also if the
4920 instruction already has a prefix, we need to convert old
4921 registers to new ones. */
4923 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4924 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4925 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4926 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4927 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4928 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4933 i
.rex
|= REX_OPCODE
;
4934 for (x
= 0; x
< 2; x
++)
4936 /* Look for 8 bit operand that uses old registers. */
4937 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4938 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4940 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4941 /* In case it is "hi" register, give up. */
4942 if (i
.op
[x
].regs
->reg_num
> 3)
4943 as_bad (_("can't encode register '%s%s' in an "
4944 "instruction requiring REX prefix."),
4945 register_prefix
, i
.op
[x
].regs
->reg_name
);
4947 /* Otherwise it is equivalent to the extended register.
4948 Since the encoding doesn't change this is merely
4949 cosmetic cleanup for debug output. */
4951 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4956 if (i
.rex
== 0 && i
.rex_encoding
)
4958 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4959 that uses legacy register. If it is "hi" register, don't add
4960 the REX_OPCODE byte. */
4962 for (x
= 0; x
< 2; x
++)
4963 if (i
.types
[x
].bitfield
.class == Reg
4964 && i
.types
[x
].bitfield
.byte
4965 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4966 && i
.op
[x
].regs
->reg_num
> 3)
4968 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4969 i
.rex_encoding
= FALSE
;
4978 add_prefix (REX_OPCODE
| i
.rex
);
4980 insert_lfence_before ();
4982 /* We are ready to output the insn. */
4985 insert_lfence_after ();
4987 last_insn
.seg
= now_seg
;
4989 if (i
.tm
.opcode_modifier
.isprefix
)
4991 last_insn
.kind
= last_insn_prefix
;
4992 last_insn
.name
= i
.tm
.name
;
4993 last_insn
.file
= as_where (&last_insn
.line
);
4996 last_insn
.kind
= last_insn_other
;
5000 parse_insn (char *line
, char *mnemonic
)
5003 char *token_start
= l
;
5006 const insn_template
*t
;
5012 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5017 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5019 as_bad (_("no such instruction: `%s'"), token_start
);
5024 if (!is_space_char (*l
)
5025 && *l
!= END_OF_INSN
5027 || (*l
!= PREFIX_SEPARATOR
5030 as_bad (_("invalid character %s in mnemonic"),
5031 output_invalid (*l
));
5034 if (token_start
== l
)
5036 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5037 as_bad (_("expecting prefix; got nothing"));
5039 as_bad (_("expecting mnemonic; got nothing"));
5043 /* Look up instruction (or prefix) via hash table. */
5044 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5046 if (*l
!= END_OF_INSN
5047 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5048 && current_templates
5049 && current_templates
->start
->opcode_modifier
.isprefix
)
5051 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
5053 as_bad ((flag_code
!= CODE_64BIT
5054 ? _("`%s' is only supported in 64-bit mode")
5055 : _("`%s' is not supported in 64-bit mode")),
5056 current_templates
->start
->name
);
5059 /* If we are in 16-bit mode, do not allow addr16 or data16.
5060 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5061 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5062 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5063 && flag_code
!= CODE_64BIT
5064 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5065 ^ (flag_code
== CODE_16BIT
)))
5067 as_bad (_("redundant %s prefix"),
5068 current_templates
->start
->name
);
5071 if (current_templates
->start
->opcode_length
== 0)
5073 /* Handle pseudo prefixes. */
5074 switch (current_templates
->start
->base_opcode
)
5078 i
.disp_encoding
= disp_encoding_8bit
;
5082 i
.disp_encoding
= disp_encoding_32bit
;
5086 i
.dir_encoding
= dir_encoding_load
;
5090 i
.dir_encoding
= dir_encoding_store
;
5094 i
.vec_encoding
= vex_encoding_vex
;
5098 i
.vec_encoding
= vex_encoding_vex3
;
5102 i
.vec_encoding
= vex_encoding_evex
;
5106 i
.rex_encoding
= TRUE
;
5110 i
.no_optimize
= TRUE
;
5118 /* Add prefix, checking for repeated prefixes. */
5119 switch (add_prefix (current_templates
->start
->base_opcode
))
5124 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
5125 i
.notrack_prefix
= current_templates
->start
->name
;
5128 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
5129 i
.hle_prefix
= current_templates
->start
->name
;
5130 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
5131 i
.bnd_prefix
= current_templates
->start
->name
;
5133 i
.rep_prefix
= current_templates
->start
->name
;
5139 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5146 if (!current_templates
)
5148 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5149 Check if we should swap operand or force 32bit displacement in
5151 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5152 i
.dir_encoding
= dir_encoding_swap
;
5153 else if (mnem_p
- 3 == dot_p
5156 i
.disp_encoding
= disp_encoding_8bit
;
5157 else if (mnem_p
- 4 == dot_p
5161 i
.disp_encoding
= disp_encoding_32bit
;
5166 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
5169 if (!current_templates
)
5172 if (mnem_p
> mnemonic
)
5174 /* See if we can get a match by trimming off a suffix. */
5177 case WORD_MNEM_SUFFIX
:
5178 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5179 i
.suffix
= SHORT_MNEM_SUFFIX
;
5182 case BYTE_MNEM_SUFFIX
:
5183 case QWORD_MNEM_SUFFIX
:
5184 i
.suffix
= mnem_p
[-1];
5186 current_templates
= (const templates
*) hash_find (op_hash
,
5189 case SHORT_MNEM_SUFFIX
:
5190 case LONG_MNEM_SUFFIX
:
5193 i
.suffix
= mnem_p
[-1];
5195 current_templates
= (const templates
*) hash_find (op_hash
,
5204 if (intel_float_operand (mnemonic
) == 1)
5205 i
.suffix
= SHORT_MNEM_SUFFIX
;
5207 i
.suffix
= LONG_MNEM_SUFFIX
;
5209 current_templates
= (const templates
*) hash_find (op_hash
,
5216 if (!current_templates
)
5218 as_bad (_("no such instruction: `%s'"), token_start
);
5223 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5224 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5226 /* Check for a branch hint. We allow ",pt" and ",pn" for
5227 predict taken and predict not taken respectively.
5228 I'm not sure that branch hints actually do anything on loop
5229 and jcxz insns (JumpByte) for current Pentium4 chips. They
5230 may work in the future and it doesn't hurt to accept them
5232 if (l
[0] == ',' && l
[1] == 'p')
5236 if (!add_prefix (DS_PREFIX_OPCODE
))
5240 else if (l
[2] == 'n')
5242 if (!add_prefix (CS_PREFIX_OPCODE
))
5248 /* Any other comma loses. */
5251 as_bad (_("invalid character %s in mnemonic"),
5252 output_invalid (*l
));
5256 /* Check if instruction is supported on specified architecture. */
5258 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5260 supported
|= cpu_flags_match (t
);
5261 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5263 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
5264 as_warn (_("use .code16 to ensure correct addressing mode"));
5270 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
5271 as_bad (flag_code
== CODE_64BIT
5272 ? _("`%s' is not supported in 64-bit mode")
5273 : _("`%s' is only supported in 64-bit mode"),
5274 current_templates
->start
->name
);
5276 as_bad (_("`%s' is not supported on `%s%s'"),
5277 current_templates
->start
->name
,
5278 cpu_arch_name
? cpu_arch_name
: default_arch
,
5279 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5285 parse_operands (char *l
, const char *mnemonic
)
5289 /* 1 if operand is pending after ','. */
5290 unsigned int expecting_operand
= 0;
5292 /* Non-zero if operand parens not balanced. */
5293 unsigned int paren_not_balanced
;
5295 while (*l
!= END_OF_INSN
)
5297 /* Skip optional white space before operand. */
5298 if (is_space_char (*l
))
5300 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5302 as_bad (_("invalid character %s before operand %d"),
5303 output_invalid (*l
),
5307 token_start
= l
; /* After white space. */
5308 paren_not_balanced
= 0;
5309 while (paren_not_balanced
|| *l
!= ',')
5311 if (*l
== END_OF_INSN
)
5313 if (paren_not_balanced
)
5316 as_bad (_("unbalanced parenthesis in operand %d."),
5319 as_bad (_("unbalanced brackets in operand %d."),
5324 break; /* we are done */
5326 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
5328 as_bad (_("invalid character %s in operand %d"),
5329 output_invalid (*l
),
5336 ++paren_not_balanced
;
5338 --paren_not_balanced
;
5343 ++paren_not_balanced
;
5345 --paren_not_balanced
;
5349 if (l
!= token_start
)
5350 { /* Yes, we've read in another operand. */
5351 unsigned int operand_ok
;
5352 this_operand
= i
.operands
++;
5353 if (i
.operands
> MAX_OPERANDS
)
5355 as_bad (_("spurious operands; (%d operands/instruction max)"),
5359 i
.types
[this_operand
].bitfield
.unspecified
= 1;
5360 /* Now parse operand adding info to 'i' as we go along. */
5361 END_STRING_AND_SAVE (l
);
5363 if (i
.mem_operands
> 1)
5365 as_bad (_("too many memory references for `%s'"),
5372 i386_intel_operand (token_start
,
5373 intel_float_operand (mnemonic
));
5375 operand_ok
= i386_att_operand (token_start
);
5377 RESTORE_END_STRING (l
);
5383 if (expecting_operand
)
5385 expecting_operand_after_comma
:
5386 as_bad (_("expecting operand after ','; got nothing"));
5391 as_bad (_("expecting operand before ','; got nothing"));
5396 /* Now *l must be either ',' or END_OF_INSN. */
5399 if (*++l
== END_OF_INSN
)
5401 /* Just skip it, if it's \n complain. */
5402 goto expecting_operand_after_comma
;
5404 expecting_operand
= 1;
5411 swap_2_operands (int xchg1
, int xchg2
)
5413 union i386_op temp_op
;
5414 i386_operand_type temp_type
;
5415 unsigned int temp_flags
;
5416 enum bfd_reloc_code_real temp_reloc
;
5418 temp_type
= i
.types
[xchg2
];
5419 i
.types
[xchg2
] = i
.types
[xchg1
];
5420 i
.types
[xchg1
] = temp_type
;
5422 temp_flags
= i
.flags
[xchg2
];
5423 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5424 i
.flags
[xchg1
] = temp_flags
;
5426 temp_op
= i
.op
[xchg2
];
5427 i
.op
[xchg2
] = i
.op
[xchg1
];
5428 i
.op
[xchg1
] = temp_op
;
5430 temp_reloc
= i
.reloc
[xchg2
];
5431 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5432 i
.reloc
[xchg1
] = temp_reloc
;
5436 if (i
.mask
->operand
== xchg1
)
5437 i
.mask
->operand
= xchg2
;
5438 else if (i
.mask
->operand
== xchg2
)
5439 i
.mask
->operand
= xchg1
;
5443 if (i
.broadcast
->operand
== xchg1
)
5444 i
.broadcast
->operand
= xchg2
;
5445 else if (i
.broadcast
->operand
== xchg2
)
5446 i
.broadcast
->operand
= xchg1
;
5450 if (i
.rounding
->operand
== xchg1
)
5451 i
.rounding
->operand
= xchg2
;
5452 else if (i
.rounding
->operand
== xchg2
)
5453 i
.rounding
->operand
= xchg1
;
5458 swap_operands (void)
5464 swap_2_operands (1, i
.operands
- 2);
5468 swap_2_operands (0, i
.operands
- 1);
5474 if (i
.mem_operands
== 2)
5476 const seg_entry
*temp_seg
;
5477 temp_seg
= i
.seg
[0];
5478 i
.seg
[0] = i
.seg
[1];
5479 i
.seg
[1] = temp_seg
;
5483 /* Try to ensure constant immediates are represented in the smallest
5488 char guess_suffix
= 0;
5492 guess_suffix
= i
.suffix
;
5493 else if (i
.reg_operands
)
5495 /* Figure out a suffix from the last register operand specified.
5496 We can't do this properly yet, i.e. excluding special register
5497 instances, but the following works for instructions with
5498 immediates. In any case, we can't set i.suffix yet. */
5499 for (op
= i
.operands
; --op
>= 0;)
5500 if (i
.types
[op
].bitfield
.class != Reg
)
5502 else if (i
.types
[op
].bitfield
.byte
)
5504 guess_suffix
= BYTE_MNEM_SUFFIX
;
5507 else if (i
.types
[op
].bitfield
.word
)
5509 guess_suffix
= WORD_MNEM_SUFFIX
;
5512 else if (i
.types
[op
].bitfield
.dword
)
5514 guess_suffix
= LONG_MNEM_SUFFIX
;
5517 else if (i
.types
[op
].bitfield
.qword
)
5519 guess_suffix
= QWORD_MNEM_SUFFIX
;
5523 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5524 guess_suffix
= WORD_MNEM_SUFFIX
;
5526 for (op
= i
.operands
; --op
>= 0;)
5527 if (operand_type_check (i
.types
[op
], imm
))
5529 switch (i
.op
[op
].imms
->X_op
)
5532 /* If a suffix is given, this operand may be shortened. */
5533 switch (guess_suffix
)
5535 case LONG_MNEM_SUFFIX
:
5536 i
.types
[op
].bitfield
.imm32
= 1;
5537 i
.types
[op
].bitfield
.imm64
= 1;
5539 case WORD_MNEM_SUFFIX
:
5540 i
.types
[op
].bitfield
.imm16
= 1;
5541 i
.types
[op
].bitfield
.imm32
= 1;
5542 i
.types
[op
].bitfield
.imm32s
= 1;
5543 i
.types
[op
].bitfield
.imm64
= 1;
5545 case BYTE_MNEM_SUFFIX
:
5546 i
.types
[op
].bitfield
.imm8
= 1;
5547 i
.types
[op
].bitfield
.imm8s
= 1;
5548 i
.types
[op
].bitfield
.imm16
= 1;
5549 i
.types
[op
].bitfield
.imm32
= 1;
5550 i
.types
[op
].bitfield
.imm32s
= 1;
5551 i
.types
[op
].bitfield
.imm64
= 1;
5555 /* If this operand is at most 16 bits, convert it
5556 to a signed 16 bit number before trying to see
5557 whether it will fit in an even smaller size.
5558 This allows a 16-bit operand such as $0xffe0 to
5559 be recognised as within Imm8S range. */
5560 if ((i
.types
[op
].bitfield
.imm16
)
5561 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5563 i
.op
[op
].imms
->X_add_number
=
5564 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5567 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5568 if ((i
.types
[op
].bitfield
.imm32
)
5569 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5572 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5573 ^ ((offsetT
) 1 << 31))
5574 - ((offsetT
) 1 << 31));
5578 = operand_type_or (i
.types
[op
],
5579 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5581 /* We must avoid matching of Imm32 templates when 64bit
5582 only immediate is available. */
5583 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5584 i
.types
[op
].bitfield
.imm32
= 0;
5591 /* Symbols and expressions. */
5593 /* Convert symbolic operand to proper sizes for matching, but don't
5594 prevent matching a set of insns that only supports sizes other
5595 than those matching the insn suffix. */
5597 i386_operand_type mask
, allowed
;
5598 const insn_template
*t
;
5600 operand_type_set (&mask
, 0);
5601 operand_type_set (&allowed
, 0);
5603 for (t
= current_templates
->start
;
5604 t
< current_templates
->end
;
5607 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5608 allowed
= operand_type_and (allowed
, anyimm
);
5610 switch (guess_suffix
)
5612 case QWORD_MNEM_SUFFIX
:
5613 mask
.bitfield
.imm64
= 1;
5614 mask
.bitfield
.imm32s
= 1;
5616 case LONG_MNEM_SUFFIX
:
5617 mask
.bitfield
.imm32
= 1;
5619 case WORD_MNEM_SUFFIX
:
5620 mask
.bitfield
.imm16
= 1;
5622 case BYTE_MNEM_SUFFIX
:
5623 mask
.bitfield
.imm8
= 1;
5628 allowed
= operand_type_and (mask
, allowed
);
5629 if (!operand_type_all_zero (&allowed
))
5630 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5637 /* Try to use the smallest displacement type too. */
5639 optimize_disp (void)
5643 for (op
= i
.operands
; --op
>= 0;)
5644 if (operand_type_check (i
.types
[op
], disp
))
5646 if (i
.op
[op
].disps
->X_op
== O_constant
)
5648 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5650 if (i
.types
[op
].bitfield
.disp16
5651 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5653 /* If this operand is at most 16 bits, convert
5654 to a signed 16 bit number and don't use 64bit
5656 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5657 i
.types
[op
].bitfield
.disp64
= 0;
5660 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5661 if (i
.types
[op
].bitfield
.disp32
5662 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5664 /* If this operand is at most 32 bits, convert
5665 to a signed 32 bit number and don't use 64bit
5667 op_disp
&= (((offsetT
) 2 << 31) - 1);
5668 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5669 i
.types
[op
].bitfield
.disp64
= 0;
5672 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5674 i
.types
[op
].bitfield
.disp8
= 0;
5675 i
.types
[op
].bitfield
.disp16
= 0;
5676 i
.types
[op
].bitfield
.disp32
= 0;
5677 i
.types
[op
].bitfield
.disp32s
= 0;
5678 i
.types
[op
].bitfield
.disp64
= 0;
5682 else if (flag_code
== CODE_64BIT
)
5684 if (fits_in_signed_long (op_disp
))
5686 i
.types
[op
].bitfield
.disp64
= 0;
5687 i
.types
[op
].bitfield
.disp32s
= 1;
5689 if (i
.prefix
[ADDR_PREFIX
]
5690 && fits_in_unsigned_long (op_disp
))
5691 i
.types
[op
].bitfield
.disp32
= 1;
5693 if ((i
.types
[op
].bitfield
.disp32
5694 || i
.types
[op
].bitfield
.disp32s
5695 || i
.types
[op
].bitfield
.disp16
)
5696 && fits_in_disp8 (op_disp
))
5697 i
.types
[op
].bitfield
.disp8
= 1;
5699 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5700 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5702 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5703 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5704 i
.types
[op
].bitfield
.disp8
= 0;
5705 i
.types
[op
].bitfield
.disp16
= 0;
5706 i
.types
[op
].bitfield
.disp32
= 0;
5707 i
.types
[op
].bitfield
.disp32s
= 0;
5708 i
.types
[op
].bitfield
.disp64
= 0;
5711 /* We only support 64bit displacement on constants. */
5712 i
.types
[op
].bitfield
.disp64
= 0;
5716 /* Return 1 if there is a match in broadcast bytes between operand
5717 GIVEN and instruction template T. */
5720 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5722 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5723 && i
.types
[given
].bitfield
.byte
)
5724 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5725 && i
.types
[given
].bitfield
.word
)
5726 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5727 && i
.types
[given
].bitfield
.dword
)
5728 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5729 && i
.types
[given
].bitfield
.qword
));
5732 /* Check if operands are valid for the instruction. */
5735 check_VecOperands (const insn_template
*t
)
5740 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5741 any one operand are implicity requiring AVX512VL support if the actual
5742 operand size is YMMword or XMMword. Since this function runs after
5743 template matching, there's no need to check for YMMword/XMMword in
5745 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5746 if (!cpu_flags_all_zero (&cpu
)
5747 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5748 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5750 for (op
= 0; op
< t
->operands
; ++op
)
5752 if (t
->operand_types
[op
].bitfield
.zmmword
5753 && (i
.types
[op
].bitfield
.ymmword
5754 || i
.types
[op
].bitfield
.xmmword
))
5756 i
.error
= unsupported
;
5762 /* Without VSIB byte, we can't have a vector register for index. */
5763 if (!t
->opcode_modifier
.vecsib
5765 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5766 || i
.index_reg
->reg_type
.bitfield
.ymmword
5767 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5769 i
.error
= unsupported_vector_index_register
;
5773 /* Check if default mask is allowed. */
5774 if (t
->opcode_modifier
.nodefmask
5775 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5777 i
.error
= no_default_mask
;
5781 /* For VSIB byte, we need a vector register for index, and all vector
5782 registers must be distinct. */
5783 if (t
->opcode_modifier
.vecsib
)
5786 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5787 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5788 || (t
->opcode_modifier
.vecsib
== VecSIB256
5789 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5790 || (t
->opcode_modifier
.vecsib
== VecSIB512
5791 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5793 i
.error
= invalid_vsib_address
;
5797 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5798 if (i
.reg_operands
== 2 && !i
.mask
)
5800 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5801 gas_assert (i
.types
[0].bitfield
.xmmword
5802 || i
.types
[0].bitfield
.ymmword
);
5803 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5804 gas_assert (i
.types
[2].bitfield
.xmmword
5805 || i
.types
[2].bitfield
.ymmword
);
5806 if (operand_check
== check_none
)
5808 if (register_number (i
.op
[0].regs
)
5809 != register_number (i
.index_reg
)
5810 && register_number (i
.op
[2].regs
)
5811 != register_number (i
.index_reg
)
5812 && register_number (i
.op
[0].regs
)
5813 != register_number (i
.op
[2].regs
))
5815 if (operand_check
== check_error
)
5817 i
.error
= invalid_vector_register_set
;
5820 as_warn (_("mask, index, and destination registers should be distinct"));
5822 else if (i
.reg_operands
== 1 && i
.mask
)
5824 if (i
.types
[1].bitfield
.class == RegSIMD
5825 && (i
.types
[1].bitfield
.xmmword
5826 || i
.types
[1].bitfield
.ymmword
5827 || i
.types
[1].bitfield
.zmmword
)
5828 && (register_number (i
.op
[1].regs
)
5829 == register_number (i
.index_reg
)))
5831 if (operand_check
== check_error
)
5833 i
.error
= invalid_vector_register_set
;
5836 if (operand_check
!= check_none
)
5837 as_warn (_("index and destination registers should be distinct"));
5842 /* Check if broadcast is supported by the instruction and is applied
5843 to the memory operand. */
5846 i386_operand_type type
, overlap
;
5848 /* Check if specified broadcast is supported in this instruction,
5849 and its broadcast bytes match the memory operand. */
5850 op
= i
.broadcast
->operand
;
5851 if (!t
->opcode_modifier
.broadcast
5852 || !(i
.flags
[op
] & Operand_Mem
)
5853 || (!i
.types
[op
].bitfield
.unspecified
5854 && !match_broadcast_size (t
, op
)))
5857 i
.error
= unsupported_broadcast
;
5861 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5862 * i
.broadcast
->type
);
5863 operand_type_set (&type
, 0);
5864 switch (i
.broadcast
->bytes
)
5867 type
.bitfield
.word
= 1;
5870 type
.bitfield
.dword
= 1;
5873 type
.bitfield
.qword
= 1;
5876 type
.bitfield
.xmmword
= 1;
5879 type
.bitfield
.ymmword
= 1;
5882 type
.bitfield
.zmmword
= 1;
5888 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5889 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
5890 && t
->operand_types
[op
].bitfield
.byte
5891 + t
->operand_types
[op
].bitfield
.word
5892 + t
->operand_types
[op
].bitfield
.dword
5893 + t
->operand_types
[op
].bitfield
.qword
> 1)
5895 overlap
.bitfield
.xmmword
= 0;
5896 overlap
.bitfield
.ymmword
= 0;
5897 overlap
.bitfield
.zmmword
= 0;
5899 if (operand_type_all_zero (&overlap
))
5902 if (t
->opcode_modifier
.checkregsize
)
5906 type
.bitfield
.baseindex
= 1;
5907 for (j
= 0; j
< i
.operands
; ++j
)
5910 && !operand_type_register_match(i
.types
[j
],
5911 t
->operand_types
[j
],
5913 t
->operand_types
[op
]))
5918 /* If broadcast is supported in this instruction, we need to check if
5919 operand of one-element size isn't specified without broadcast. */
5920 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5922 /* Find memory operand. */
5923 for (op
= 0; op
< i
.operands
; op
++)
5924 if (i
.flags
[op
] & Operand_Mem
)
5926 gas_assert (op
< i
.operands
);
5927 /* Check size of the memory operand. */
5928 if (match_broadcast_size (t
, op
))
5930 i
.error
= broadcast_needed
;
5935 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5937 /* Check if requested masking is supported. */
5940 switch (t
->opcode_modifier
.masking
)
5944 case MERGING_MASKING
:
5945 if (i
.mask
->zeroing
)
5948 i
.error
= unsupported_masking
;
5952 case DYNAMIC_MASKING
:
5953 /* Memory destinations allow only merging masking. */
5954 if (i
.mask
->zeroing
&& i
.mem_operands
)
5956 /* Find memory operand. */
5957 for (op
= 0; op
< i
.operands
; op
++)
5958 if (i
.flags
[op
] & Operand_Mem
)
5960 gas_assert (op
< i
.operands
);
5961 if (op
== i
.operands
- 1)
5963 i
.error
= unsupported_masking
;
5973 /* Check if masking is applied to dest operand. */
5974 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5976 i
.error
= mask_not_on_destination
;
5983 if (!t
->opcode_modifier
.sae
5984 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5986 i
.error
= unsupported_rc_sae
;
5989 /* If the instruction has several immediate operands and one of
5990 them is rounding, the rounding operand should be the last
5991 immediate operand. */
5992 if (i
.imm_operands
> 1
5993 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5995 i
.error
= rc_sae_operand_not_last_imm
;
6000 /* Check vector Disp8 operand. */
6001 if (t
->opcode_modifier
.disp8memshift
6002 && i
.disp_encoding
!= disp_encoding_32bit
)
6005 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6006 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6007 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6010 const i386_operand_type
*type
= NULL
;
6013 for (op
= 0; op
< i
.operands
; op
++)
6014 if (i
.flags
[op
] & Operand_Mem
)
6016 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6017 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6018 else if (t
->operand_types
[op
].bitfield
.xmmword
6019 + t
->operand_types
[op
].bitfield
.ymmword
6020 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6021 type
= &t
->operand_types
[op
];
6022 else if (!i
.types
[op
].bitfield
.unspecified
)
6023 type
= &i
.types
[op
];
6025 else if (i
.types
[op
].bitfield
.class == RegSIMD
6026 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6028 if (i
.types
[op
].bitfield
.zmmword
)
6030 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6032 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6038 if (type
->bitfield
.zmmword
)
6040 else if (type
->bitfield
.ymmword
)
6042 else if (type
->bitfield
.xmmword
)
6046 /* For the check in fits_in_disp8(). */
6047 if (i
.memshift
== 0)
6051 for (op
= 0; op
< i
.operands
; op
++)
6052 if (operand_type_check (i
.types
[op
], disp
)
6053 && i
.op
[op
].disps
->X_op
== O_constant
)
6055 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6057 i
.types
[op
].bitfield
.disp8
= 1;
6060 i
.types
[op
].bitfield
.disp8
= 0;
6069 /* Check if operands are valid for the instruction. Update VEX
6073 VEX_check_operands (const insn_template
*t
)
6075 if (i
.vec_encoding
== vex_encoding_evex
)
6077 /* This instruction must be encoded with EVEX prefix. */
6078 if (!is_evex_encoding (t
))
6080 i
.error
= unsupported
;
6086 if (!t
->opcode_modifier
.vex
)
6088 /* This instruction template doesn't have VEX prefix. */
6089 if (i
.vec_encoding
!= vex_encoding_default
)
6091 i
.error
= unsupported
;
6097 /* Check the special Imm4 cases; must be the first operand. */
6098 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
6100 if (i
.op
[0].imms
->X_op
!= O_constant
6101 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6107 /* Turn off Imm<N> so that update_imm won't complain. */
6108 operand_type_set (&i
.types
[0], 0);
6114 static const insn_template
*
6115 match_template (char mnem_suffix
)
6117 /* Points to template once we've found it. */
6118 const insn_template
*t
;
6119 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6120 i386_operand_type overlap4
;
6121 unsigned int found_reverse_match
;
6122 i386_opcode_modifier suffix_check
;
6123 i386_operand_type operand_types
[MAX_OPERANDS
];
6124 int addr_prefix_disp
;
6125 unsigned int j
, size_match
, check_register
;
6126 enum i386_error specific_error
= 0;
6128 #if MAX_OPERANDS != 5
6129 # error "MAX_OPERANDS must be 5."
6132 found_reverse_match
= 0;
6133 addr_prefix_disp
= -1;
6135 /* Prepare for mnemonic suffix check. */
6136 memset (&suffix_check
, 0, sizeof (suffix_check
));
6137 switch (mnem_suffix
)
6139 case BYTE_MNEM_SUFFIX
:
6140 suffix_check
.no_bsuf
= 1;
6142 case WORD_MNEM_SUFFIX
:
6143 suffix_check
.no_wsuf
= 1;
6145 case SHORT_MNEM_SUFFIX
:
6146 suffix_check
.no_ssuf
= 1;
6148 case LONG_MNEM_SUFFIX
:
6149 suffix_check
.no_lsuf
= 1;
6151 case QWORD_MNEM_SUFFIX
:
6152 suffix_check
.no_qsuf
= 1;
6155 /* NB: In Intel syntax, normally we can check for memory operand
6156 size when there is no mnemonic suffix. But jmp and call have
6157 2 different encodings with Dword memory operand size, one with
6158 No_ldSuf and the other without. i.suffix is set to
6159 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6160 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
6161 suffix_check
.no_ldsuf
= 1;
6164 /* Must have right number of operands. */
6165 i
.error
= number_of_operands_mismatch
;
6167 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6169 addr_prefix_disp
= -1;
6170 found_reverse_match
= 0;
6172 if (i
.operands
!= t
->operands
)
6175 /* Check processor support. */
6176 i
.error
= unsupported
;
6177 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6180 /* Check AT&T mnemonic. */
6181 i
.error
= unsupported_with_intel_mnemonic
;
6182 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6185 /* Check AT&T/Intel syntax. */
6186 i
.error
= unsupported_syntax
;
6187 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6188 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6191 /* Check Intel64/AMD64 ISA. */
6195 /* Default: Don't accept Intel64. */
6196 if (t
->opcode_modifier
.isa64
== INTEL64
)
6200 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6201 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6205 /* -mintel64: Don't accept AMD64. */
6206 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6211 /* Check the suffix. */
6212 i
.error
= invalid_instruction_suffix
;
6213 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
6214 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
6215 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
6216 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
6217 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
6218 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
6221 size_match
= operand_size_match (t
);
6225 /* This is intentionally not
6227 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6229 as the case of a missing * on the operand is accepted (perhaps with
6230 a warning, issued further down). */
6231 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
6233 i
.error
= operand_type_mismatch
;
6237 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6238 operand_types
[j
] = t
->operand_types
[j
];
6240 /* In general, don't allow
6241 - 64-bit operands outside of 64-bit mode,
6242 - 32-bit operands on pre-386. */
6243 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
6244 if (((i
.suffix
== QWORD_MNEM_SUFFIX
6245 && flag_code
!= CODE_64BIT
6246 && (t
->base_opcode
!= 0x0fc7
6247 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
6248 || (i
.suffix
== LONG_MNEM_SUFFIX
6249 && !cpu_arch_flags
.bitfield
.cpui386
))
6251 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
6252 && !intel_float_operand (t
->name
))
6253 : intel_float_operand (t
->name
) != 2)
6254 && (t
->operands
== i
.imm_operands
6255 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
6256 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
6257 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
6258 || (operand_types
[j
].bitfield
.class != RegMMX
6259 && operand_types
[j
].bitfield
.class != RegSIMD
6260 && operand_types
[j
].bitfield
.class != RegMask
))
6261 && !t
->opcode_modifier
.vecsib
)
6264 /* Do not verify operands when there are none. */
6266 /* We've found a match; break out of loop. */
6269 if (!t
->opcode_modifier
.jump
6270 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
6272 /* There should be only one Disp operand. */
6273 for (j
= 0; j
< MAX_OPERANDS
; j
++)
6274 if (operand_type_check (operand_types
[j
], disp
))
6276 if (j
< MAX_OPERANDS
)
6278 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6280 addr_prefix_disp
= j
;
6282 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6283 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6287 override
= !override
;
6290 if (operand_types
[j
].bitfield
.disp32
6291 && operand_types
[j
].bitfield
.disp16
)
6293 operand_types
[j
].bitfield
.disp16
= override
;
6294 operand_types
[j
].bitfield
.disp32
= !override
;
6296 operand_types
[j
].bitfield
.disp32s
= 0;
6297 operand_types
[j
].bitfield
.disp64
= 0;
6301 if (operand_types
[j
].bitfield
.disp32s
6302 || operand_types
[j
].bitfield
.disp64
)
6304 operand_types
[j
].bitfield
.disp64
&= !override
;
6305 operand_types
[j
].bitfield
.disp32s
&= !override
;
6306 operand_types
[j
].bitfield
.disp32
= override
;
6308 operand_types
[j
].bitfield
.disp16
= 0;
6314 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6315 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
6318 /* We check register size if needed. */
6319 if (t
->opcode_modifier
.checkregsize
)
6321 check_register
= (1 << t
->operands
) - 1;
6323 check_register
&= ~(1 << i
.broadcast
->operand
);
6328 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
6329 switch (t
->operands
)
6332 if (!operand_type_match (overlap0
, i
.types
[0]))
6336 /* xchg %eax, %eax is a special case. It is an alias for nop
6337 only in 32bit mode and we can use opcode 0x90. In 64bit
6338 mode, we can't use 0x90 for xchg %eax, %eax since it should
6339 zero-extend %eax to %rax. */
6340 if (flag_code
== CODE_64BIT
6341 && t
->base_opcode
== 0x90
6342 && i
.types
[0].bitfield
.instance
== Accum
6343 && i
.types
[0].bitfield
.dword
6344 && i
.types
[1].bitfield
.instance
== Accum
6345 && i
.types
[1].bitfield
.dword
)
6347 /* xrelease mov %eax, <disp> is another special case. It must not
6348 match the accumulator-only encoding of mov. */
6349 if (flag_code
!= CODE_64BIT
6351 && t
->base_opcode
== 0xa0
6352 && i
.types
[0].bitfield
.instance
== Accum
6353 && (i
.flags
[1] & Operand_Mem
))
6358 if (!(size_match
& MATCH_STRAIGHT
))
6360 /* Reverse direction of operands if swapping is possible in the first
6361 place (operands need to be symmetric) and
6362 - the load form is requested, and the template is a store form,
6363 - the store form is requested, and the template is a load form,
6364 - the non-default (swapped) form is requested. */
6365 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
6366 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
6367 && !operand_type_all_zero (&overlap1
))
6368 switch (i
.dir_encoding
)
6370 case dir_encoding_load
:
6371 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6372 || t
->opcode_modifier
.regmem
)
6376 case dir_encoding_store
:
6377 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
6378 && !t
->opcode_modifier
.regmem
)
6382 case dir_encoding_swap
:
6385 case dir_encoding_default
:
6388 /* If we want store form, we skip the current load. */
6389 if ((i
.dir_encoding
== dir_encoding_store
6390 || i
.dir_encoding
== dir_encoding_swap
)
6391 && i
.mem_operands
== 0
6392 && t
->opcode_modifier
.load
)
6397 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6398 if (!operand_type_match (overlap0
, i
.types
[0])
6399 || !operand_type_match (overlap1
, i
.types
[1])
6400 || ((check_register
& 3) == 3
6401 && !operand_type_register_match (i
.types
[0],
6406 /* Check if other direction is valid ... */
6407 if (!t
->opcode_modifier
.d
)
6411 if (!(size_match
& MATCH_REVERSE
))
6413 /* Try reversing direction of operands. */
6414 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6415 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6416 if (!operand_type_match (overlap0
, i
.types
[0])
6417 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6419 && !operand_type_register_match (i
.types
[0],
6420 operand_types
[i
.operands
- 1],
6421 i
.types
[i
.operands
- 1],
6424 /* Does not match either direction. */
6427 /* found_reverse_match holds which of D or FloatR
6429 if (!t
->opcode_modifier
.d
)
6430 found_reverse_match
= 0;
6431 else if (operand_types
[0].bitfield
.tbyte
)
6432 found_reverse_match
= Opcode_FloatD
;
6433 else if (operand_types
[0].bitfield
.xmmword
6434 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6435 || operand_types
[0].bitfield
.class == RegMMX
6436 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6437 || is_any_vex_encoding(t
))
6438 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6439 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6441 found_reverse_match
= Opcode_D
;
6442 if (t
->opcode_modifier
.floatr
)
6443 found_reverse_match
|= Opcode_FloatR
;
6447 /* Found a forward 2 operand match here. */
6448 switch (t
->operands
)
6451 overlap4
= operand_type_and (i
.types
[4],
6455 overlap3
= operand_type_and (i
.types
[3],
6459 overlap2
= operand_type_and (i
.types
[2],
6464 switch (t
->operands
)
6467 if (!operand_type_match (overlap4
, i
.types
[4])
6468 || !operand_type_register_match (i
.types
[3],
6475 if (!operand_type_match (overlap3
, i
.types
[3])
6476 || ((check_register
& 0xa) == 0xa
6477 && !operand_type_register_match (i
.types
[1],
6481 || ((check_register
& 0xc) == 0xc
6482 && !operand_type_register_match (i
.types
[2],
6489 /* Here we make use of the fact that there are no
6490 reverse match 3 operand instructions. */
6491 if (!operand_type_match (overlap2
, i
.types
[2])
6492 || ((check_register
& 5) == 5
6493 && !operand_type_register_match (i
.types
[0],
6497 || ((check_register
& 6) == 6
6498 && !operand_type_register_match (i
.types
[1],
6506 /* Found either forward/reverse 2, 3 or 4 operand match here:
6507 slip through to break. */
6510 /* Check if vector and VEX operands are valid. */
6511 if (check_VecOperands (t
) || VEX_check_operands (t
))
6513 specific_error
= i
.error
;
6517 /* We've found a match; break out of loop. */
6521 if (t
== current_templates
->end
)
6523 /* We found no match. */
6524 const char *err_msg
;
6525 switch (specific_error
? specific_error
: i
.error
)
6529 case operand_size_mismatch
:
6530 err_msg
= _("operand size mismatch");
6532 case operand_type_mismatch
:
6533 err_msg
= _("operand type mismatch");
6535 case register_type_mismatch
:
6536 err_msg
= _("register type mismatch");
6538 case number_of_operands_mismatch
:
6539 err_msg
= _("number of operands mismatch");
6541 case invalid_instruction_suffix
:
6542 err_msg
= _("invalid instruction suffix");
6545 err_msg
= _("constant doesn't fit in 4 bits");
6547 case unsupported_with_intel_mnemonic
:
6548 err_msg
= _("unsupported with Intel mnemonic");
6550 case unsupported_syntax
:
6551 err_msg
= _("unsupported syntax");
6554 as_bad (_("unsupported instruction `%s'"),
6555 current_templates
->start
->name
);
6557 case invalid_vsib_address
:
6558 err_msg
= _("invalid VSIB address");
6560 case invalid_vector_register_set
:
6561 err_msg
= _("mask, index, and destination registers must be distinct");
6563 case unsupported_vector_index_register
:
6564 err_msg
= _("unsupported vector index register");
6566 case unsupported_broadcast
:
6567 err_msg
= _("unsupported broadcast");
6569 case broadcast_needed
:
6570 err_msg
= _("broadcast is needed for operand of such type");
6572 case unsupported_masking
:
6573 err_msg
= _("unsupported masking");
6575 case mask_not_on_destination
:
6576 err_msg
= _("mask not on destination operand");
6578 case no_default_mask
:
6579 err_msg
= _("default mask isn't allowed");
6581 case unsupported_rc_sae
:
6582 err_msg
= _("unsupported static rounding/sae");
6584 case rc_sae_operand_not_last_imm
:
6586 err_msg
= _("RC/SAE operand must precede immediate operands");
6588 err_msg
= _("RC/SAE operand must follow immediate operands");
6590 case invalid_register_operand
:
6591 err_msg
= _("invalid register operand");
6594 as_bad (_("%s for `%s'"), err_msg
,
6595 current_templates
->start
->name
);
6599 if (!quiet_warnings
)
6602 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6603 as_warn (_("indirect %s without `*'"), t
->name
);
6605 if (t
->opcode_modifier
.isprefix
6606 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6608 /* Warn them that a data or address size prefix doesn't
6609 affect assembly of the next line of code. */
6610 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6614 /* Copy the template we found. */
6617 if (addr_prefix_disp
!= -1)
6618 i
.tm
.operand_types
[addr_prefix_disp
]
6619 = operand_types
[addr_prefix_disp
];
6621 if (found_reverse_match
)
6623 /* If we found a reverse match we must alter the opcode direction
6624 bit and clear/flip the regmem modifier one. found_reverse_match
6625 holds bits to change (different for int & float insns). */
6627 i
.tm
.base_opcode
^= found_reverse_match
;
6629 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6630 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6632 /* Certain SIMD insns have their load forms specified in the opcode
6633 table, and hence we need to _set_ RegMem instead of clearing it.
6634 We need to avoid setting the bit though on insns like KMOVW. */
6635 i
.tm
.opcode_modifier
.regmem
6636 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6637 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6638 && !i
.tm
.opcode_modifier
.regmem
;
6647 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6648 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6650 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6652 as_bad (_("`%s' operand %u must use `%ses' segment"),
6654 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6659 /* There's only ever one segment override allowed per instruction.
6660 This instruction possibly has a legal segment override on the
6661 second operand, so copy the segment to where non-string
6662 instructions store it, allowing common code. */
6663 i
.seg
[op
] = i
.seg
[1];
6669 process_suffix (void)
6671 /* If matched instruction specifies an explicit instruction mnemonic
6673 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6674 i
.suffix
= WORD_MNEM_SUFFIX
;
6675 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6676 i
.suffix
= LONG_MNEM_SUFFIX
;
6677 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6678 i
.suffix
= QWORD_MNEM_SUFFIX
;
6679 else if (i
.reg_operands
6680 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
6681 && !i
.tm
.opcode_modifier
.addrprefixopreg
)
6683 unsigned int numop
= i
.operands
;
6685 /* movsx/movzx want only their source operand considered here, for the
6686 ambiguity checking below. The suffix will be replaced afterwards
6687 to represent the destination (register). */
6688 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6689 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6692 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6693 if (i
.tm
.base_opcode
== 0xf20f38f0
6694 && i
.tm
.operand_types
[1].bitfield
.qword
)
6697 /* If there's no instruction mnemonic suffix we try to invent one
6698 based on GPR operands. */
6701 /* We take i.suffix from the last register operand specified,
6702 Destination register type is more significant than source
6703 register type. crc32 in SSE4.2 prefers source register
6705 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6708 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6709 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6711 if (i
.types
[op
].bitfield
.class != Reg
)
6713 if (i
.types
[op
].bitfield
.byte
)
6714 i
.suffix
= BYTE_MNEM_SUFFIX
;
6715 else if (i
.types
[op
].bitfield
.word
)
6716 i
.suffix
= WORD_MNEM_SUFFIX
;
6717 else if (i
.types
[op
].bitfield
.dword
)
6718 i
.suffix
= LONG_MNEM_SUFFIX
;
6719 else if (i
.types
[op
].bitfield
.qword
)
6720 i
.suffix
= QWORD_MNEM_SUFFIX
;
6726 /* As an exception, movsx/movzx silently default to a byte source
6728 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6729 && !i
.suffix
&& !intel_syntax
)
6730 i
.suffix
= BYTE_MNEM_SUFFIX
;
6732 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6735 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6736 && i
.tm
.opcode_modifier
.no_bsuf
)
6738 else if (!check_byte_reg ())
6741 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6744 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6745 && i
.tm
.opcode_modifier
.no_lsuf
6746 && !i
.tm
.opcode_modifier
.todword
6747 && !i
.tm
.opcode_modifier
.toqword
)
6749 else if (!check_long_reg ())
6752 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6755 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6756 && i
.tm
.opcode_modifier
.no_qsuf
6757 && !i
.tm
.opcode_modifier
.todword
6758 && !i
.tm
.opcode_modifier
.toqword
)
6760 else if (!check_qword_reg ())
6763 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6766 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
6767 && i
.tm
.opcode_modifier
.no_wsuf
)
6769 else if (!check_word_reg ())
6772 else if (intel_syntax
6773 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
6774 /* Do nothing if the instruction is going to ignore the prefix. */
6779 /* Undo the movsx/movzx change done above. */
6782 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
6785 i
.suffix
= stackop_size
;
6786 if (stackop_size
== LONG_MNEM_SUFFIX
)
6788 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6789 .code16gcc directive to support 16-bit mode with
6790 32-bit address. For IRET without a suffix, generate
6791 16-bit IRET (opcode 0xcf) to return from an interrupt
6793 if (i
.tm
.base_opcode
== 0xcf)
6795 i
.suffix
= WORD_MNEM_SUFFIX
;
6796 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6798 /* Warn about changed behavior for segment register push/pop. */
6799 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6800 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6805 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6806 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6807 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6808 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6809 && i
.tm
.extension_opcode
<= 3)))
6814 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6816 i
.suffix
= QWORD_MNEM_SUFFIX
;
6821 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6822 i
.suffix
= LONG_MNEM_SUFFIX
;
6825 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6826 i
.suffix
= WORD_MNEM_SUFFIX
;
6832 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6833 /* Also cover lret/retf/iret in 64-bit mode. */
6834 || (flag_code
== CODE_64BIT
6835 && !i
.tm
.opcode_modifier
.no_lsuf
6836 && !i
.tm
.opcode_modifier
.no_qsuf
))
6837 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
6838 /* Accept FLDENV et al without suffix. */
6839 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6841 unsigned int suffixes
, evex
= 0;
6843 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6844 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6846 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6848 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6850 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6852 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6855 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6856 also suitable for AT&T syntax mode, it was requested that this be
6857 restricted to just Intel syntax. */
6858 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
) && !i
.broadcast
)
6862 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6864 if (is_evex_encoding (&i
.tm
)
6865 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6867 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6868 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6869 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6870 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6871 if (!i
.tm
.opcode_modifier
.evex
6872 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6873 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6876 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6877 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6878 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6881 /* Any properly sized operand disambiguates the insn. */
6882 if (i
.types
[op
].bitfield
.xmmword
6883 || i
.types
[op
].bitfield
.ymmword
6884 || i
.types
[op
].bitfield
.zmmword
)
6886 suffixes
&= ~(7 << 6);
6891 if ((i
.flags
[op
] & Operand_Mem
)
6892 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6894 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6896 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6898 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6900 if (is_evex_encoding (&i
.tm
))
6906 /* Are multiple suffixes / operand sizes allowed? */
6907 if (suffixes
& (suffixes
- 1))
6910 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
6911 || operand_check
== check_error
))
6913 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6916 if (operand_check
== check_error
)
6918 as_bad (_("no instruction mnemonic suffix given and "
6919 "no register operands; can't size `%s'"), i
.tm
.name
);
6922 if (operand_check
== check_warning
)
6923 as_warn (_("%s; using default for `%s'"),
6925 ? _("ambiguous operand size")
6926 : _("no instruction mnemonic suffix given and "
6927 "no register operands"),
6930 if (i
.tm
.opcode_modifier
.floatmf
)
6931 i
.suffix
= SHORT_MNEM_SUFFIX
;
6932 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6933 || (i
.tm
.base_opcode
== 0x63
6934 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6935 /* handled below */;
6937 i
.tm
.opcode_modifier
.evex
= evex
;
6938 else if (flag_code
== CODE_16BIT
)
6939 i
.suffix
= WORD_MNEM_SUFFIX
;
6940 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6941 i
.suffix
= LONG_MNEM_SUFFIX
;
6943 i
.suffix
= QWORD_MNEM_SUFFIX
;
6947 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6948 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6950 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6951 In AT&T syntax, if there is no suffix (warned about above), the default
6952 will be byte extension. */
6953 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6954 i
.tm
.base_opcode
|= 1;
6956 /* For further processing, the suffix should represent the destination
6957 (register). This is already the case when one was used with
6958 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6959 no suffix to begin with. */
6960 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6962 if (i
.types
[1].bitfield
.word
)
6963 i
.suffix
= WORD_MNEM_SUFFIX
;
6964 else if (i
.types
[1].bitfield
.qword
)
6965 i
.suffix
= QWORD_MNEM_SUFFIX
;
6967 i
.suffix
= LONG_MNEM_SUFFIX
;
6969 i
.tm
.opcode_modifier
.w
= 0;
6973 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6974 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6975 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6977 /* Change the opcode based on the operand size given by i.suffix. */
6980 /* Size floating point instruction. */
6981 case LONG_MNEM_SUFFIX
:
6982 if (i
.tm
.opcode_modifier
.floatmf
)
6984 i
.tm
.base_opcode
^= 4;
6988 case WORD_MNEM_SUFFIX
:
6989 case QWORD_MNEM_SUFFIX
:
6990 /* It's not a byte, select word/dword operation. */
6991 if (i
.tm
.opcode_modifier
.w
)
6994 i
.tm
.base_opcode
|= 8;
6996 i
.tm
.base_opcode
|= 1;
6999 case SHORT_MNEM_SUFFIX
:
7000 /* Now select between word & dword operations via the operand
7001 size prefix, except for instructions that will ignore this
7003 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7004 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7005 && !i
.tm
.opcode_modifier
.floatmf
7006 && !is_any_vex_encoding (&i
.tm
)
7007 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7008 || (flag_code
== CODE_64BIT
7009 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7011 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7013 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7014 prefix
= ADDR_PREFIX_OPCODE
;
7016 if (!add_prefix (prefix
))
7020 /* Set mode64 for an operand. */
7021 if (i
.suffix
== QWORD_MNEM_SUFFIX
7022 && flag_code
== CODE_64BIT
7023 && !i
.tm
.opcode_modifier
.norex64
7024 && !i
.tm
.opcode_modifier
.vexw
7025 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7027 && ! (i
.operands
== 2
7028 && i
.tm
.base_opcode
== 0x90
7029 && i
.tm
.extension_opcode
== None
7030 && i
.types
[0].bitfield
.instance
== Accum
7031 && i
.types
[0].bitfield
.qword
7032 && i
.types
[1].bitfield
.instance
== Accum
7033 && i
.types
[1].bitfield
.qword
))
7039 if (i
.tm
.opcode_modifier
.addrprefixopreg
)
7041 gas_assert (!i
.suffix
);
7042 gas_assert (i
.reg_operands
);
7044 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7047 /* The address size override prefix changes the size of the
7049 if (flag_code
== CODE_64BIT
7050 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7052 as_bad (_("16-bit addressing unavailable for `%s'"),
7057 if ((flag_code
== CODE_32BIT
7058 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7059 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7060 && !add_prefix (ADDR_PREFIX_OPCODE
))
7065 /* Check invalid register operand when the address size override
7066 prefix changes the size of register operands. */
7068 enum { need_word
, need_dword
, need_qword
} need
;
7070 if (flag_code
== CODE_32BIT
)
7071 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7072 else if (i
.prefix
[ADDR_PREFIX
])
7075 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7077 for (op
= 0; op
< i
.operands
; op
++)
7079 if (i
.types
[op
].bitfield
.class != Reg
)
7085 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7089 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7093 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7098 as_bad (_("invalid register operand size for `%s'"),
7109 check_byte_reg (void)
7113 for (op
= i
.operands
; --op
>= 0;)
7115 /* Skip non-register operands. */
7116 if (i
.types
[op
].bitfield
.class != Reg
)
7119 /* If this is an eight bit register, it's OK. If it's the 16 or
7120 32 bit version of an eight bit register, we will just use the
7121 low portion, and that's OK too. */
7122 if (i
.types
[op
].bitfield
.byte
)
7125 /* I/O port address operands are OK too. */
7126 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7127 && i
.tm
.operand_types
[op
].bitfield
.word
)
7130 /* crc32 only wants its source operand checked here. */
7131 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
7134 /* Any other register is bad. */
7135 if (i
.types
[op
].bitfield
.class == Reg
7136 || i
.types
[op
].bitfield
.class == RegMMX
7137 || i
.types
[op
].bitfield
.class == RegSIMD
7138 || i
.types
[op
].bitfield
.class == SReg
7139 || i
.types
[op
].bitfield
.class == RegCR
7140 || i
.types
[op
].bitfield
.class == RegDR
7141 || i
.types
[op
].bitfield
.class == RegTR
)
7143 as_bad (_("`%s%s' not allowed with `%s%c'"),
7145 i
.op
[op
].regs
->reg_name
,
7155 check_long_reg (void)
7159 for (op
= i
.operands
; --op
>= 0;)
7160 /* Skip non-register operands. */
7161 if (i
.types
[op
].bitfield
.class != Reg
)
7163 /* Reject eight bit registers, except where the template requires
7164 them. (eg. movzb) */
7165 else if (i
.types
[op
].bitfield
.byte
7166 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7167 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7168 && (i
.tm
.operand_types
[op
].bitfield
.word
7169 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7171 as_bad (_("`%s%s' not allowed with `%s%c'"),
7173 i
.op
[op
].regs
->reg_name
,
7178 /* Error if the e prefix on a general reg is missing. */
7179 else if (i
.types
[op
].bitfield
.word
7180 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7181 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7182 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7184 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7185 register_prefix
, i
.op
[op
].regs
->reg_name
,
7189 /* Warn if the r prefix on a general reg is present. */
7190 else if (i
.types
[op
].bitfield
.qword
7191 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7192 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7193 && i
.tm
.operand_types
[op
].bitfield
.dword
)
7196 && i
.tm
.opcode_modifier
.toqword
7197 && i
.types
[0].bitfield
.class != RegSIMD
)
7199 /* Convert to QWORD. We want REX byte. */
7200 i
.suffix
= QWORD_MNEM_SUFFIX
;
7204 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7205 register_prefix
, i
.op
[op
].regs
->reg_name
,
7214 check_qword_reg (void)
7218 for (op
= i
.operands
; --op
>= 0; )
7219 /* Skip non-register operands. */
7220 if (i
.types
[op
].bitfield
.class != Reg
)
7222 /* Reject eight bit registers, except where the template requires
7223 them. (eg. movzb) */
7224 else if (i
.types
[op
].bitfield
.byte
7225 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7226 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7227 && (i
.tm
.operand_types
[op
].bitfield
.word
7228 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7230 as_bad (_("`%s%s' not allowed with `%s%c'"),
7232 i
.op
[op
].regs
->reg_name
,
7237 /* Warn if the r prefix on a general reg is missing. */
7238 else if ((i
.types
[op
].bitfield
.word
7239 || i
.types
[op
].bitfield
.dword
)
7240 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7241 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7242 && i
.tm
.operand_types
[op
].bitfield
.qword
)
7244 /* Prohibit these changes in the 64bit mode, since the
7245 lowering is more complicated. */
7247 && i
.tm
.opcode_modifier
.todword
7248 && i
.types
[0].bitfield
.class != RegSIMD
)
7250 /* Convert to DWORD. We don't want REX byte. */
7251 i
.suffix
= LONG_MNEM_SUFFIX
;
7255 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7256 register_prefix
, i
.op
[op
].regs
->reg_name
,
7265 check_word_reg (void)
7268 for (op
= i
.operands
; --op
>= 0;)
7269 /* Skip non-register operands. */
7270 if (i
.types
[op
].bitfield
.class != Reg
)
7272 /* Reject eight bit registers, except where the template requires
7273 them. (eg. movzb) */
7274 else if (i
.types
[op
].bitfield
.byte
7275 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7276 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7277 && (i
.tm
.operand_types
[op
].bitfield
.word
7278 || i
.tm
.operand_types
[op
].bitfield
.dword
))
7280 as_bad (_("`%s%s' not allowed with `%s%c'"),
7282 i
.op
[op
].regs
->reg_name
,
7287 /* Error if the e or r prefix on a general reg is present. */
7288 else if ((i
.types
[op
].bitfield
.dword
7289 || i
.types
[op
].bitfield
.qword
)
7290 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
7291 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7292 && i
.tm
.operand_types
[op
].bitfield
.word
)
7294 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7295 register_prefix
, i
.op
[op
].regs
->reg_name
,
7303 update_imm (unsigned int j
)
7305 i386_operand_type overlap
= i
.types
[j
];
7306 if ((overlap
.bitfield
.imm8
7307 || overlap
.bitfield
.imm8s
7308 || overlap
.bitfield
.imm16
7309 || overlap
.bitfield
.imm32
7310 || overlap
.bitfield
.imm32s
7311 || overlap
.bitfield
.imm64
)
7312 && !operand_type_equal (&overlap
, &imm8
)
7313 && !operand_type_equal (&overlap
, &imm8s
)
7314 && !operand_type_equal (&overlap
, &imm16
)
7315 && !operand_type_equal (&overlap
, &imm32
)
7316 && !operand_type_equal (&overlap
, &imm32s
)
7317 && !operand_type_equal (&overlap
, &imm64
))
7321 i386_operand_type temp
;
7323 operand_type_set (&temp
, 0);
7324 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7326 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
7327 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
7329 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7330 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
7331 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7333 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
7334 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
7337 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
7340 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
7341 || operand_type_equal (&overlap
, &imm16_32
)
7342 || operand_type_equal (&overlap
, &imm16_32s
))
7344 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
7349 if (!operand_type_equal (&overlap
, &imm8
)
7350 && !operand_type_equal (&overlap
, &imm8s
)
7351 && !operand_type_equal (&overlap
, &imm16
)
7352 && !operand_type_equal (&overlap
, &imm32
)
7353 && !operand_type_equal (&overlap
, &imm32s
)
7354 && !operand_type_equal (&overlap
, &imm64
))
7356 as_bad (_("no instruction mnemonic suffix given; "
7357 "can't determine immediate size"));
7361 i
.types
[j
] = overlap
;
7371 /* Update the first 2 immediate operands. */
7372 n
= i
.operands
> 2 ? 2 : i
.operands
;
7375 for (j
= 0; j
< n
; j
++)
7376 if (update_imm (j
) == 0)
7379 /* The 3rd operand can't be immediate operand. */
7380 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
7387 process_operands (void)
7389 /* Default segment register this instruction will use for memory
7390 accesses. 0 means unknown. This is only for optimizing out
7391 unnecessary segment overrides. */
7392 const seg_entry
*default_seg
= 0;
7394 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
7396 unsigned int dupl
= i
.operands
;
7397 unsigned int dest
= dupl
- 1;
7400 /* The destination must be an xmm register. */
7401 gas_assert (i
.reg_operands
7402 && MAX_OPERANDS
> dupl
7403 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7405 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7406 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7408 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7410 /* Keep xmm0 for instructions with VEX prefix and 3
7412 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7413 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7418 /* We remove the first xmm0 and keep the number of
7419 operands unchanged, which in fact duplicates the
7421 for (j
= 1; j
< i
.operands
; j
++)
7423 i
.op
[j
- 1] = i
.op
[j
];
7424 i
.types
[j
- 1] = i
.types
[j
];
7425 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7426 i
.flags
[j
- 1] = i
.flags
[j
];
7430 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7432 gas_assert ((MAX_OPERANDS
- 1) > dupl
7433 && (i
.tm
.opcode_modifier
.vexsources
7436 /* Add the implicit xmm0 for instructions with VEX prefix
7438 for (j
= i
.operands
; j
> 0; j
--)
7440 i
.op
[j
] = i
.op
[j
- 1];
7441 i
.types
[j
] = i
.types
[j
- 1];
7442 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7443 i
.flags
[j
] = i
.flags
[j
- 1];
7446 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7447 i
.types
[0] = regxmm
;
7448 i
.tm
.operand_types
[0] = regxmm
;
7451 i
.reg_operands
+= 2;
7456 i
.op
[dupl
] = i
.op
[dest
];
7457 i
.types
[dupl
] = i
.types
[dest
];
7458 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7459 i
.flags
[dupl
] = i
.flags
[dest
];
7468 i
.op
[dupl
] = i
.op
[dest
];
7469 i
.types
[dupl
] = i
.types
[dest
];
7470 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7471 i
.flags
[dupl
] = i
.flags
[dest
];
7474 if (i
.tm
.opcode_modifier
.immext
)
7477 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7478 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7482 for (j
= 1; j
< i
.operands
; j
++)
7484 i
.op
[j
- 1] = i
.op
[j
];
7485 i
.types
[j
- 1] = i
.types
[j
];
7487 /* We need to adjust fields in i.tm since they are used by
7488 build_modrm_byte. */
7489 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7491 i
.flags
[j
- 1] = i
.flags
[j
];
7498 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7500 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7502 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7503 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7504 regnum
= register_number (i
.op
[1].regs
);
7505 first_reg_in_group
= regnum
& ~3;
7506 last_reg_in_group
= first_reg_in_group
+ 3;
7507 if (regnum
!= first_reg_in_group
)
7508 as_warn (_("source register `%s%s' implicitly denotes"
7509 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7510 register_prefix
, i
.op
[1].regs
->reg_name
,
7511 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7512 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7515 else if (i
.tm
.opcode_modifier
.regkludge
)
7517 /* The imul $imm, %reg instruction is converted into
7518 imul $imm, %reg, %reg, and the clr %reg instruction
7519 is converted into xor %reg, %reg. */
7521 unsigned int first_reg_op
;
7523 if (operand_type_check (i
.types
[0], reg
))
7527 /* Pretend we saw the extra register operand. */
7528 gas_assert (i
.reg_operands
== 1
7529 && i
.op
[first_reg_op
+ 1].regs
== 0);
7530 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7531 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7536 if (i
.tm
.opcode_modifier
.modrm
)
7538 /* The opcode is completed (modulo i.tm.extension_opcode which
7539 must be put into the modrm byte). Now, we make the modrm and
7540 index base bytes based on all the info we've collected. */
7542 default_seg
= build_modrm_byte ();
7544 else if (i
.types
[0].bitfield
.class == SReg
)
7546 if (flag_code
!= CODE_64BIT
7547 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7548 && i
.op
[0].regs
->reg_num
== 1
7549 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7550 && i
.op
[0].regs
->reg_num
< 4)
7552 as_bad (_("you can't `%s %s%s'"),
7553 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7556 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7558 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7559 i
.tm
.opcode_length
= 2;
7561 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7563 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7567 else if (i
.tm
.opcode_modifier
.isstring
)
7569 /* For the string instructions that allow a segment override
7570 on one of their operands, the default segment is ds. */
7573 else if (i
.short_form
)
7575 /* The register or float register operand is in operand
7577 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7579 /* Register goes in low 3 bits of opcode. */
7580 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7581 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7583 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7585 /* Warn about some common errors, but press on regardless.
7586 The first case can be generated by gcc (<= 2.8.1). */
7587 if (i
.operands
== 2)
7589 /* Reversed arguments on faddp, fsubp, etc. */
7590 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7591 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7592 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7596 /* Extraneous `l' suffix on fp insn. */
7597 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7598 register_prefix
, i
.op
[0].regs
->reg_name
);
7603 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7604 && i
.tm
.base_opcode
== 0x8d /* lea */
7605 && !is_any_vex_encoding(&i
.tm
))
7607 if (!quiet_warnings
)
7608 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7612 i
.prefix
[SEG_PREFIX
] = 0;
7616 /* If a segment was explicitly specified, and the specified segment
7617 is neither the default nor the one already recorded from a prefix,
7618 use an opcode prefix to select it. If we never figured out what
7619 the default segment is, then default_seg will be zero at this
7620 point, and the specified segment prefix will always be used. */
7622 && i
.seg
[0] != default_seg
7623 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7625 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7631 static const seg_entry
*
7632 build_modrm_byte (void)
7634 const seg_entry
*default_seg
= 0;
7635 unsigned int source
, dest
;
7638 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7641 unsigned int nds
, reg_slot
;
7644 dest
= i
.operands
- 1;
7647 /* There are 2 kinds of instructions:
7648 1. 5 operands: 4 register operands or 3 register operands
7649 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7650 VexW0 or VexW1. The destination must be either XMM, YMM or
7652 2. 4 operands: 4 register operands or 3 register operands
7653 plus 1 memory operand, with VexXDS. */
7654 gas_assert ((i
.reg_operands
== 4
7655 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7656 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7657 && i
.tm
.opcode_modifier
.vexw
7658 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7660 /* If VexW1 is set, the first non-immediate operand is the source and
7661 the second non-immediate one is encoded in the immediate operand. */
7662 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7664 source
= i
.imm_operands
;
7665 reg_slot
= i
.imm_operands
+ 1;
7669 source
= i
.imm_operands
+ 1;
7670 reg_slot
= i
.imm_operands
;
7673 if (i
.imm_operands
== 0)
7675 /* When there is no immediate operand, generate an 8bit
7676 immediate operand to encode the first operand. */
7677 exp
= &im_expressions
[i
.imm_operands
++];
7678 i
.op
[i
.operands
].imms
= exp
;
7679 i
.types
[i
.operands
] = imm8
;
7682 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7683 exp
->X_op
= O_constant
;
7684 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7685 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7689 gas_assert (i
.imm_operands
== 1);
7690 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7691 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7693 /* Turn on Imm8 again so that output_imm will generate it. */
7694 i
.types
[0].bitfield
.imm8
= 1;
7696 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7697 i
.op
[0].imms
->X_add_number
7698 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7699 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7702 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7703 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7708 /* i.reg_operands MUST be the number of real register operands;
7709 implicit registers do not count. If there are 3 register
7710 operands, it must be a instruction with VexNDS. For a
7711 instruction with VexNDD, the destination register is encoded
7712 in VEX prefix. If there are 4 register operands, it must be
7713 a instruction with VEX prefix and 3 sources. */
7714 if (i
.mem_operands
== 0
7715 && ((i
.reg_operands
== 2
7716 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7717 || (i
.reg_operands
== 3
7718 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7719 || (i
.reg_operands
== 4 && vex_3_sources
)))
7727 /* When there are 3 operands, one of them may be immediate,
7728 which may be the first or the last operand. Otherwise,
7729 the first operand must be shift count register (cl) or it
7730 is an instruction with VexNDS. */
7731 gas_assert (i
.imm_operands
== 1
7732 || (i
.imm_operands
== 0
7733 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7734 || (i
.types
[0].bitfield
.instance
== RegC
7735 && i
.types
[0].bitfield
.byte
))));
7736 if (operand_type_check (i
.types
[0], imm
)
7737 || (i
.types
[0].bitfield
.instance
== RegC
7738 && i
.types
[0].bitfield
.byte
))
7744 /* When there are 4 operands, the first two must be 8bit
7745 immediate operands. The source operand will be the 3rd
7748 For instructions with VexNDS, if the first operand
7749 an imm8, the source operand is the 2nd one. If the last
7750 operand is imm8, the source operand is the first one. */
7751 gas_assert ((i
.imm_operands
== 2
7752 && i
.types
[0].bitfield
.imm8
7753 && i
.types
[1].bitfield
.imm8
)
7754 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7755 && i
.imm_operands
== 1
7756 && (i
.types
[0].bitfield
.imm8
7757 || i
.types
[i
.operands
- 1].bitfield
.imm8
7759 if (i
.imm_operands
== 2)
7763 if (i
.types
[0].bitfield
.imm8
)
7770 if (is_evex_encoding (&i
.tm
))
7772 /* For EVEX instructions, when there are 5 operands, the
7773 first one must be immediate operand. If the second one
7774 is immediate operand, the source operand is the 3th
7775 one. If the last one is immediate operand, the source
7776 operand is the 2nd one. */
7777 gas_assert (i
.imm_operands
== 2
7778 && i
.tm
.opcode_modifier
.sae
7779 && operand_type_check (i
.types
[0], imm
));
7780 if (operand_type_check (i
.types
[1], imm
))
7782 else if (operand_type_check (i
.types
[4], imm
))
7796 /* RC/SAE operand could be between DEST and SRC. That happens
7797 when one operand is GPR and the other one is XMM/YMM/ZMM
7799 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7802 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7804 /* For instructions with VexNDS, the register-only source
7805 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7806 register. It is encoded in VEX prefix. */
7808 i386_operand_type op
;
7811 /* Check register-only source operand when two source
7812 operands are swapped. */
7813 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7814 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7822 op
= i
.tm
.operand_types
[vvvv
];
7823 if ((dest
+ 1) >= i
.operands
7824 || ((op
.bitfield
.class != Reg
7825 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7826 && op
.bitfield
.class != RegSIMD
7827 && !operand_type_equal (&op
, ®mask
)))
7829 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7835 /* One of the register operands will be encoded in the i.rm.reg
7836 field, the other in the combined i.rm.mode and i.rm.regmem
7837 fields. If no form of this instruction supports a memory
7838 destination operand, then we assume the source operand may
7839 sometimes be a memory operand and so we need to store the
7840 destination in the i.rm.reg field. */
7841 if (!i
.tm
.opcode_modifier
.regmem
7842 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7844 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7845 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7846 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7847 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7848 i
.has_regmmx
= TRUE
;
7849 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7850 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7852 if (i
.types
[dest
].bitfield
.zmmword
7853 || i
.types
[source
].bitfield
.zmmword
)
7854 i
.has_regzmm
= TRUE
;
7855 else if (i
.types
[dest
].bitfield
.ymmword
7856 || i
.types
[source
].bitfield
.ymmword
)
7857 i
.has_regymm
= TRUE
;
7859 i
.has_regxmm
= TRUE
;
7861 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7863 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7865 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7867 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7872 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7873 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7874 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7876 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7878 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7880 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7883 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7885 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7888 add_prefix (LOCK_PREFIX_OPCODE
);
7892 { /* If it's not 2 reg operands... */
7897 unsigned int fake_zero_displacement
= 0;
7900 for (op
= 0; op
< i
.operands
; op
++)
7901 if (i
.flags
[op
] & Operand_Mem
)
7903 gas_assert (op
< i
.operands
);
7905 if (i
.tm
.opcode_modifier
.vecsib
)
7907 if (i
.index_reg
->reg_num
== RegIZ
)
7910 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7913 i
.sib
.base
= NO_BASE_REGISTER
;
7914 i
.sib
.scale
= i
.log2_scale_factor
;
7915 i
.types
[op
].bitfield
.disp8
= 0;
7916 i
.types
[op
].bitfield
.disp16
= 0;
7917 i
.types
[op
].bitfield
.disp64
= 0;
7918 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7920 /* Must be 32 bit */
7921 i
.types
[op
].bitfield
.disp32
= 1;
7922 i
.types
[op
].bitfield
.disp32s
= 0;
7926 i
.types
[op
].bitfield
.disp32
= 0;
7927 i
.types
[op
].bitfield
.disp32s
= 1;
7930 i
.sib
.index
= i
.index_reg
->reg_num
;
7931 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7933 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7939 if (i
.base_reg
== 0)
7942 if (!i
.disp_operands
)
7943 fake_zero_displacement
= 1;
7944 if (i
.index_reg
== 0)
7946 i386_operand_type newdisp
;
7948 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7949 /* Operand is just <disp> */
7950 if (flag_code
== CODE_64BIT
)
7952 /* 64bit mode overwrites the 32bit absolute
7953 addressing by RIP relative addressing and
7954 absolute addressing is encoded by one of the
7955 redundant SIB forms. */
7956 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7957 i
.sib
.base
= NO_BASE_REGISTER
;
7958 i
.sib
.index
= NO_INDEX_REGISTER
;
7959 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7961 else if ((flag_code
== CODE_16BIT
)
7962 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7964 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7969 i
.rm
.regmem
= NO_BASE_REGISTER
;
7972 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7973 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7975 else if (!i
.tm
.opcode_modifier
.vecsib
)
7977 /* !i.base_reg && i.index_reg */
7978 if (i
.index_reg
->reg_num
== RegIZ
)
7979 i
.sib
.index
= NO_INDEX_REGISTER
;
7981 i
.sib
.index
= i
.index_reg
->reg_num
;
7982 i
.sib
.base
= NO_BASE_REGISTER
;
7983 i
.sib
.scale
= i
.log2_scale_factor
;
7984 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7985 i
.types
[op
].bitfield
.disp8
= 0;
7986 i
.types
[op
].bitfield
.disp16
= 0;
7987 i
.types
[op
].bitfield
.disp64
= 0;
7988 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7990 /* Must be 32 bit */
7991 i
.types
[op
].bitfield
.disp32
= 1;
7992 i
.types
[op
].bitfield
.disp32s
= 0;
7996 i
.types
[op
].bitfield
.disp32
= 0;
7997 i
.types
[op
].bitfield
.disp32s
= 1;
7999 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8003 /* RIP addressing for 64bit mode. */
8004 else if (i
.base_reg
->reg_num
== RegIP
)
8006 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8007 i
.rm
.regmem
= NO_BASE_REGISTER
;
8008 i
.types
[op
].bitfield
.disp8
= 0;
8009 i
.types
[op
].bitfield
.disp16
= 0;
8010 i
.types
[op
].bitfield
.disp32
= 0;
8011 i
.types
[op
].bitfield
.disp32s
= 1;
8012 i
.types
[op
].bitfield
.disp64
= 0;
8013 i
.flags
[op
] |= Operand_PCrel
;
8014 if (! i
.disp_operands
)
8015 fake_zero_displacement
= 1;
8017 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8019 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8020 switch (i
.base_reg
->reg_num
)
8023 if (i
.index_reg
== 0)
8025 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8026 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8030 if (i
.index_reg
== 0)
8033 if (operand_type_check (i
.types
[op
], disp
) == 0)
8035 /* fake (%bp) into 0(%bp) */
8036 i
.types
[op
].bitfield
.disp8
= 1;
8037 fake_zero_displacement
= 1;
8040 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8041 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8043 default: /* (%si) -> 4 or (%di) -> 5 */
8044 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8046 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8048 else /* i.base_reg and 32/64 bit mode */
8050 if (flag_code
== CODE_64BIT
8051 && operand_type_check (i
.types
[op
], disp
))
8053 i
.types
[op
].bitfield
.disp16
= 0;
8054 i
.types
[op
].bitfield
.disp64
= 0;
8055 if (i
.prefix
[ADDR_PREFIX
] == 0)
8057 i
.types
[op
].bitfield
.disp32
= 0;
8058 i
.types
[op
].bitfield
.disp32s
= 1;
8062 i
.types
[op
].bitfield
.disp32
= 1;
8063 i
.types
[op
].bitfield
.disp32s
= 0;
8067 if (!i
.tm
.opcode_modifier
.vecsib
)
8068 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8069 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8071 i
.sib
.base
= i
.base_reg
->reg_num
;
8072 /* x86-64 ignores REX prefix bit here to avoid decoder
8074 if (!(i
.base_reg
->reg_flags
& RegRex
)
8075 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8076 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8078 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8080 fake_zero_displacement
= 1;
8081 i
.types
[op
].bitfield
.disp8
= 1;
8083 i
.sib
.scale
= i
.log2_scale_factor
;
8084 if (i
.index_reg
== 0)
8086 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
8087 /* <disp>(%esp) becomes two byte modrm with no index
8088 register. We've already stored the code for esp
8089 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8090 Any base register besides %esp will not use the
8091 extra modrm byte. */
8092 i
.sib
.index
= NO_INDEX_REGISTER
;
8094 else if (!i
.tm
.opcode_modifier
.vecsib
)
8096 if (i
.index_reg
->reg_num
== RegIZ
)
8097 i
.sib
.index
= NO_INDEX_REGISTER
;
8099 i
.sib
.index
= i
.index_reg
->reg_num
;
8100 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8101 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8106 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8107 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8111 if (!fake_zero_displacement
8115 fake_zero_displacement
= 1;
8116 if (i
.disp_encoding
== disp_encoding_8bit
)
8117 i
.types
[op
].bitfield
.disp8
= 1;
8119 i
.types
[op
].bitfield
.disp32
= 1;
8121 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8125 if (fake_zero_displacement
)
8127 /* Fakes a zero displacement assuming that i.types[op]
8128 holds the correct displacement size. */
8131 gas_assert (i
.op
[op
].disps
== 0);
8132 exp
= &disp_expressions
[i
.disp_operands
++];
8133 i
.op
[op
].disps
= exp
;
8134 exp
->X_op
= O_constant
;
8135 exp
->X_add_number
= 0;
8136 exp
->X_add_symbol
= (symbolS
*) 0;
8137 exp
->X_op_symbol
= (symbolS
*) 0;
8145 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
8147 if (operand_type_check (i
.types
[0], imm
))
8148 i
.vex
.register_specifier
= NULL
;
8151 /* VEX.vvvv encodes one of the sources when the first
8152 operand is not an immediate. */
8153 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8154 i
.vex
.register_specifier
= i
.op
[0].regs
;
8156 i
.vex
.register_specifier
= i
.op
[1].regs
;
8159 /* Destination is a XMM register encoded in the ModRM.reg
8161 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
8162 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
8165 /* ModRM.rm and VEX.B encodes the other source. */
8166 if (!i
.mem_operands
)
8170 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
8171 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8173 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
8175 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8179 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
8181 i
.vex
.register_specifier
= i
.op
[2].regs
;
8182 if (!i
.mem_operands
)
8185 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
8186 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
8190 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8191 (if any) based on i.tm.extension_opcode. Again, we must be
8192 careful to make sure that segment/control/debug/test/MMX
8193 registers are coded into the i.rm.reg field. */
8194 else if (i
.reg_operands
)
8197 unsigned int vex_reg
= ~0;
8199 for (op
= 0; op
< i
.operands
; op
++)
8201 if (i
.types
[op
].bitfield
.class == Reg
8202 || i
.types
[op
].bitfield
.class == RegBND
8203 || i
.types
[op
].bitfield
.class == RegMask
8204 || i
.types
[op
].bitfield
.class == SReg
8205 || i
.types
[op
].bitfield
.class == RegCR
8206 || i
.types
[op
].bitfield
.class == RegDR
8207 || i
.types
[op
].bitfield
.class == RegTR
)
8209 if (i
.types
[op
].bitfield
.class == RegSIMD
)
8211 if (i
.types
[op
].bitfield
.zmmword
)
8212 i
.has_regzmm
= TRUE
;
8213 else if (i
.types
[op
].bitfield
.ymmword
)
8214 i
.has_regymm
= TRUE
;
8216 i
.has_regxmm
= TRUE
;
8219 if (i
.types
[op
].bitfield
.class == RegMMX
)
8221 i
.has_regmmx
= TRUE
;
8228 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
8230 /* For instructions with VexNDS, the register-only
8231 source operand is encoded in VEX prefix. */
8232 gas_assert (mem
!= (unsigned int) ~0);
8237 gas_assert (op
< i
.operands
);
8241 /* Check register-only source operand when two source
8242 operands are swapped. */
8243 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
8244 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
8248 gas_assert (mem
== (vex_reg
+ 1)
8249 && op
< i
.operands
);
8254 gas_assert (vex_reg
< i
.operands
);
8258 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
8260 /* For instructions with VexNDD, the register destination
8261 is encoded in VEX prefix. */
8262 if (i
.mem_operands
== 0)
8264 /* There is no memory operand. */
8265 gas_assert ((op
+ 2) == i
.operands
);
8270 /* There are only 2 non-immediate operands. */
8271 gas_assert (op
< i
.imm_operands
+ 2
8272 && i
.operands
== i
.imm_operands
+ 2);
8273 vex_reg
= i
.imm_operands
+ 1;
8277 gas_assert (op
< i
.operands
);
8279 if (vex_reg
!= (unsigned int) ~0)
8281 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
8283 if ((type
->bitfield
.class != Reg
8284 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
8285 && type
->bitfield
.class != RegSIMD
8286 && !operand_type_equal (type
, ®mask
))
8289 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
8292 /* Don't set OP operand twice. */
8295 /* If there is an extension opcode to put here, the
8296 register number must be put into the regmem field. */
8297 if (i
.tm
.extension_opcode
!= None
)
8299 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8300 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8302 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8307 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
8308 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
8310 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
8315 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8316 must set it to 3 to indicate this is a register operand
8317 in the regmem field. */
8318 if (!i
.mem_operands
)
8322 /* Fill in i.rm.reg field with extension opcode (if any). */
8323 if (i
.tm
.extension_opcode
!= None
)
8324 i
.rm
.reg
= i
.tm
.extension_opcode
;
8330 flip_code16 (unsigned int code16
)
8332 gas_assert (i
.tm
.operands
== 1);
8334 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8335 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8336 || i
.tm
.operand_types
[0].bitfield
.disp32s
8337 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8342 output_branch (void)
8348 relax_substateT subtype
;
8352 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8353 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
8356 if (i
.prefix
[DATA_PREFIX
] != 0)
8360 code16
^= flip_code16(code16
);
8362 /* Pentium4 branch hints. */
8363 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8364 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8369 if (i
.prefix
[REX_PREFIX
] != 0)
8375 /* BND prefixed jump. */
8376 if (i
.prefix
[BND_PREFIX
] != 0)
8382 if (i
.prefixes
!= 0)
8383 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8385 /* It's always a symbol; End frag & setup for relax.
8386 Make sure there is enough room in this frag for the largest
8387 instruction we may generate in md_convert_frag. This is 2
8388 bytes for the opcode and room for the prefix and largest
8390 frag_grow (prefix
+ 2 + 4);
8391 /* Prefix and 1 opcode byte go in fr_fix. */
8392 p
= frag_more (prefix
+ 1);
8393 if (i
.prefix
[DATA_PREFIX
] != 0)
8394 *p
++ = DATA_PREFIX_OPCODE
;
8395 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
8396 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
8397 *p
++ = i
.prefix
[SEG_PREFIX
];
8398 if (i
.prefix
[BND_PREFIX
] != 0)
8399 *p
++ = BND_PREFIX_OPCODE
;
8400 if (i
.prefix
[REX_PREFIX
] != 0)
8401 *p
++ = i
.prefix
[REX_PREFIX
];
8402 *p
= i
.tm
.base_opcode
;
8404 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8405 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8406 else if (cpu_arch_flags
.bitfield
.cpui386
)
8407 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8409 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8412 sym
= i
.op
[0].disps
->X_add_symbol
;
8413 off
= i
.op
[0].disps
->X_add_number
;
8415 if (i
.op
[0].disps
->X_op
!= O_constant
8416 && i
.op
[0].disps
->X_op
!= O_symbol
)
8418 /* Handle complex expressions. */
8419 sym
= make_expr_symbol (i
.op
[0].disps
);
8423 /* 1 possible extra opcode + 4 byte displacement go in var part.
8424 Pass reloc in fr_var. */
8425 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8428 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8429 /* Return TRUE iff PLT32 relocation should be used for branching to
8433 need_plt32_p (symbolS
*s
)
8435 /* PLT32 relocation is ELF only. */
8440 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8441 krtld support it. */
8445 /* Since there is no need to prepare for PLT branch on x86-64, we
8446 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8447 be used as a marker for 32-bit PC-relative branches. */
8451 /* Weak or undefined symbol need PLT32 relocation. */
8452 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8455 /* Non-global symbol doesn't need PLT32 relocation. */
8456 if (! S_IS_EXTERNAL (s
))
8459 /* Other global symbols need PLT32 relocation. NB: Symbol with
8460 non-default visibilities are treated as normal global symbol
8461 so that PLT32 relocation can be used as a marker for 32-bit
8462 PC-relative branches. It is useful for linker relaxation. */
8473 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8475 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8477 /* This is a loop or jecxz type instruction. */
8479 if (i
.prefix
[ADDR_PREFIX
] != 0)
8481 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8484 /* Pentium4 branch hints. */
8485 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8486 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8488 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8497 if (flag_code
== CODE_16BIT
)
8500 if (i
.prefix
[DATA_PREFIX
] != 0)
8502 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8504 code16
^= flip_code16(code16
);
8512 /* BND prefixed jump. */
8513 if (i
.prefix
[BND_PREFIX
] != 0)
8515 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8519 if (i
.prefix
[REX_PREFIX
] != 0)
8521 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8525 if (i
.prefixes
!= 0)
8526 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8528 p
= frag_more (i
.tm
.opcode_length
+ size
);
8529 switch (i
.tm
.opcode_length
)
8532 *p
++ = i
.tm
.base_opcode
>> 8;
8535 *p
++ = i
.tm
.base_opcode
;
8541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8543 && jump_reloc
== NO_RELOC
8544 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8545 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8548 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8550 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8551 i
.op
[0].disps
, 1, jump_reloc
);
8553 /* All jumps handled here are signed, but don't use a signed limit
8554 check for 32 and 16 bit jumps as we want to allow wrap around at
8555 4G and 64k respectively. */
8557 fixP
->fx_signed
= 1;
8561 output_interseg_jump (void)
8569 if (flag_code
== CODE_16BIT
)
8573 if (i
.prefix
[DATA_PREFIX
] != 0)
8580 gas_assert (!i
.prefix
[REX_PREFIX
]);
8586 if (i
.prefixes
!= 0)
8587 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8589 /* 1 opcode; 2 segment; offset */
8590 p
= frag_more (prefix
+ 1 + 2 + size
);
8592 if (i
.prefix
[DATA_PREFIX
] != 0)
8593 *p
++ = DATA_PREFIX_OPCODE
;
8595 if (i
.prefix
[REX_PREFIX
] != 0)
8596 *p
++ = i
.prefix
[REX_PREFIX
];
8598 *p
++ = i
.tm
.base_opcode
;
8599 if (i
.op
[1].imms
->X_op
== O_constant
)
8601 offsetT n
= i
.op
[1].imms
->X_add_number
;
8604 && !fits_in_unsigned_word (n
)
8605 && !fits_in_signed_word (n
))
8607 as_bad (_("16-bit jump out of range"));
8610 md_number_to_chars (p
, n
, size
);
8613 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8614 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8615 if (i
.op
[0].imms
->X_op
!= O_constant
)
8616 as_bad (_("can't handle non absolute segment in `%s'"),
8618 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8621 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8626 asection
*seg
= now_seg
;
8627 subsegT subseg
= now_subseg
;
8629 unsigned int alignment
, align_size_1
;
8630 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8631 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8632 unsigned int padding
;
8634 if (!IS_ELF
|| !x86_used_note
)
8637 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8639 /* The .note.gnu.property section layout:
8641 Field Length Contents
8644 n_descsz 4 The note descriptor size
8645 n_type 4 NT_GNU_PROPERTY_TYPE_0
8647 n_desc n_descsz The program property array
8651 /* Create the .note.gnu.property section. */
8652 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8653 bfd_set_section_flags (sec
,
8660 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8671 bfd_set_section_alignment (sec
, alignment
);
8672 elf_section_type (sec
) = SHT_NOTE
;
8674 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8676 isa_1_descsz_raw
= 4 + 4 + 4;
8677 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8678 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8680 feature_2_descsz_raw
= isa_1_descsz
;
8681 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8683 feature_2_descsz_raw
+= 4 + 4 + 4;
8684 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8685 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8688 descsz
= feature_2_descsz
;
8689 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8690 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8692 /* Write n_namsz. */
8693 md_number_to_chars (p
, (valueT
) 4, 4);
8695 /* Write n_descsz. */
8696 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8699 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8702 memcpy (p
+ 4 * 3, "GNU", 4);
8704 /* Write 4-byte type. */
8705 md_number_to_chars (p
+ 4 * 4,
8706 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8708 /* Write 4-byte data size. */
8709 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8711 /* Write 4-byte data. */
8712 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8714 /* Zero out paddings. */
8715 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8717 memset (p
+ 4 * 7, 0, padding
);
8719 /* Write 4-byte type. */
8720 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8721 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8723 /* Write 4-byte data size. */
8724 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8726 /* Write 4-byte data. */
8727 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8728 (valueT
) x86_feature_2_used
, 4);
8730 /* Zero out paddings. */
8731 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8733 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8735 /* We probably can't restore the current segment, for there likely
8738 subseg_set (seg
, subseg
);
8743 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8744 const char *frag_now_ptr
)
8746 unsigned int len
= 0;
8748 if (start_frag
!= frag_now
)
8750 const fragS
*fr
= start_frag
;
8755 } while (fr
&& fr
!= frag_now
);
8758 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8761 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8762 be macro-fused with conditional jumps.
8763 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8764 or is one of the following format:
8777 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
8779 /* No RIP address. */
8780 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8783 /* No VEX/EVEX encoding. */
8784 if (is_any_vex_encoding (&i
.tm
))
8787 /* add, sub without add/sub m, imm. */
8788 if (i
.tm
.base_opcode
<= 5
8789 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8790 || ((i
.tm
.base_opcode
| 3) == 0x83
8791 && (i
.tm
.extension_opcode
== 0x5
8792 || i
.tm
.extension_opcode
== 0x0)))
8794 *mf_cmp_p
= mf_cmp_alu_cmp
;
8795 return !(i
.mem_operands
&& i
.imm_operands
);
8798 /* and without and m, imm. */
8799 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8800 || ((i
.tm
.base_opcode
| 3) == 0x83
8801 && i
.tm
.extension_opcode
== 0x4))
8803 *mf_cmp_p
= mf_cmp_test_and
;
8804 return !(i
.mem_operands
&& i
.imm_operands
);
8807 /* test without test m imm. */
8808 if ((i
.tm
.base_opcode
| 1) == 0x85
8809 || (i
.tm
.base_opcode
| 1) == 0xa9
8810 || ((i
.tm
.base_opcode
| 1) == 0xf7
8811 && i
.tm
.extension_opcode
== 0))
8813 *mf_cmp_p
= mf_cmp_test_and
;
8814 return !(i
.mem_operands
&& i
.imm_operands
);
8817 /* cmp without cmp m, imm. */
8818 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8819 || ((i
.tm
.base_opcode
| 3) == 0x83
8820 && (i
.tm
.extension_opcode
== 0x7)))
8822 *mf_cmp_p
= mf_cmp_alu_cmp
;
8823 return !(i
.mem_operands
&& i
.imm_operands
);
8826 /* inc, dec without inc/dec m. */
8827 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8828 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8829 || ((i
.tm
.base_opcode
| 1) == 0xff
8830 && i
.tm
.extension_opcode
<= 0x1))
8832 *mf_cmp_p
= mf_cmp_incdec
;
8833 return !i
.mem_operands
;
8839 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8842 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
8844 /* NB: Don't work with COND_JUMP86 without i386. */
8845 if (!align_branch_power
8846 || now_seg
== absolute_section
8847 || !cpu_arch_flags
.bitfield
.cpui386
8848 || !(align_branch
& align_branch_fused_bit
))
8851 if (maybe_fused_with_jcc_p (mf_cmp_p
))
8853 if (last_insn
.kind
== last_insn_other
8854 || last_insn
.seg
!= now_seg
)
8857 as_warn_where (last_insn
.file
, last_insn
.line
,
8858 _("`%s` skips -malign-branch-boundary on `%s`"),
8859 last_insn
.name
, i
.tm
.name
);
8865 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8868 add_branch_prefix_frag_p (void)
8870 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8871 to PadLock instructions since they include prefixes in opcode. */
8872 if (!align_branch_power
8873 || !align_branch_prefix_size
8874 || now_seg
== absolute_section
8875 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8876 || !cpu_arch_flags
.bitfield
.cpui386
)
8879 /* Don't add prefix if it is a prefix or there is no operand in case
8880 that segment prefix is special. */
8881 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8884 if (last_insn
.kind
== last_insn_other
8885 || last_insn
.seg
!= now_seg
)
8889 as_warn_where (last_insn
.file
, last_insn
.line
,
8890 _("`%s` skips -malign-branch-boundary on `%s`"),
8891 last_insn
.name
, i
.tm
.name
);
8896 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8899 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
8900 enum mf_jcc_kind
*mf_jcc_p
)
8904 /* NB: Don't work with COND_JUMP86 without i386. */
8905 if (!align_branch_power
8906 || now_seg
== absolute_section
8907 || !cpu_arch_flags
.bitfield
.cpui386
)
8912 /* Check for jcc and direct jmp. */
8913 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8915 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8917 *branch_p
= align_branch_jmp
;
8918 add_padding
= align_branch
& align_branch_jmp_bit
;
8922 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8923 igore the lowest bit. */
8924 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
8925 *branch_p
= align_branch_jcc
;
8926 if ((align_branch
& align_branch_jcc_bit
))
8930 else if (is_any_vex_encoding (&i
.tm
))
8932 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8935 *branch_p
= align_branch_ret
;
8936 if ((align_branch
& align_branch_ret_bit
))
8941 /* Check for indirect jmp, direct and indirect calls. */
8942 if (i
.tm
.base_opcode
== 0xe8)
8945 *branch_p
= align_branch_call
;
8946 if ((align_branch
& align_branch_call_bit
))
8949 else if (i
.tm
.base_opcode
== 0xff
8950 && (i
.tm
.extension_opcode
== 2
8951 || i
.tm
.extension_opcode
== 4))
8953 /* Indirect call and jmp. */
8954 *branch_p
= align_branch_indirect
;
8955 if ((align_branch
& align_branch_indirect_bit
))
8962 && (i
.op
[0].disps
->X_op
== O_symbol
8963 || (i
.op
[0].disps
->X_op
== O_subtract
8964 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8966 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8967 /* No padding to call to global or undefined tls_get_addr. */
8968 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8969 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8975 && last_insn
.kind
!= last_insn_other
8976 && last_insn
.seg
== now_seg
)
8979 as_warn_where (last_insn
.file
, last_insn
.line
,
8980 _("`%s` skips -malign-branch-boundary on `%s`"),
8981 last_insn
.name
, i
.tm
.name
);
8991 fragS
*insn_start_frag
;
8992 offsetT insn_start_off
;
8993 fragS
*fragP
= NULL
;
8994 enum align_branch_kind branch
= align_branch_none
;
8995 /* The initializer is arbitrary just to avoid uninitialized error.
8996 it's actually either assigned in add_branch_padding_frag_p
8997 or never be used. */
8998 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9000 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9001 if (IS_ELF
&& x86_used_note
)
9003 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
9004 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
9005 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
9006 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
9007 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
9008 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
9009 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
9010 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
9011 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
9012 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
9013 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
9014 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
9015 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
9016 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
9017 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
9018 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
9019 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
9020 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
9021 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
9022 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
9023 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
9024 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
9025 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
9026 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
9027 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
9028 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
9029 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
9030 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
9031 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
9032 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
9033 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
9034 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
9035 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
9036 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
9037 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
9038 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
9039 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
9040 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
9041 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
9042 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
9043 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
9044 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
9045 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
9046 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
9047 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
9048 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
9049 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
9050 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
9051 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
9052 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
9054 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
9055 || i
.tm
.cpu_flags
.bitfield
.cpu287
9056 || i
.tm
.cpu_flags
.bitfield
.cpu387
9057 || i
.tm
.cpu_flags
.bitfield
.cpu687
9058 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
9059 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9061 || i
.tm
.base_opcode
== 0xf77 /* emms */
9062 || i
.tm
.base_opcode
== 0xf0e /* femms */
9063 || i
.tm
.base_opcode
== 0xf2a /* cvtpi2ps */
9064 || i
.tm
.base_opcode
== 0x660f2a /* cvtpi2pd */)
9065 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9067 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9069 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9071 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9072 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
9073 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9074 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
9075 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9076 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
9077 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9078 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
9079 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9083 /* Tie dwarf2 debug info to the address at the start of the insn.
9084 We can't do this after the insn has been output as the current
9085 frag may have been closed off. eg. by frag_var. */
9086 dwarf2_emit_insn (0);
9088 insn_start_frag
= frag_now
;
9089 insn_start_off
= frag_now_fix ();
9091 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9094 /* Branch can be 8 bytes. Leave some room for prefixes. */
9095 unsigned int max_branch_padding_size
= 14;
9097 /* Align section to boundary. */
9098 record_alignment (now_seg
, align_branch_power
);
9100 /* Make room for padding. */
9101 frag_grow (max_branch_padding_size
);
9103 /* Start of the padding. */
9108 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9109 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9112 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9113 fragP
->tc_frag_data
.branch_type
= branch
;
9114 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9118 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9120 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9121 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9123 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9124 output_interseg_jump ();
9127 /* Output normal instructions here. */
9131 unsigned int prefix
;
9132 enum mf_cmp_kind mf_cmp
;
9135 && (i
.tm
.base_opcode
== 0xfaee8
9136 || i
.tm
.base_opcode
== 0xfaef0
9137 || i
.tm
.base_opcode
== 0xfaef8))
9139 /* Encode lfence, mfence, and sfence as
9140 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9141 offsetT val
= 0x240483f0ULL
;
9143 md_number_to_chars (p
, val
, 5);
9147 /* Some processors fail on LOCK prefix. This options makes
9148 assembler ignore LOCK prefix and serves as a workaround. */
9149 if (omit_lock_prefix
)
9151 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
9153 i
.prefix
[LOCK_PREFIX
] = 0;
9157 /* Skip if this is a branch. */
9159 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9161 /* Make room for padding. */
9162 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9167 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9168 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9171 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9172 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9173 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9175 else if (add_branch_prefix_frag_p ())
9177 unsigned int max_prefix_size
= align_branch_prefix_size
;
9179 /* Make room for padding. */
9180 frag_grow (max_prefix_size
);
9185 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9186 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9189 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9192 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9193 don't need the explicit prefix. */
9194 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
9196 switch (i
.tm
.opcode_length
)
9199 if (i
.tm
.base_opcode
& 0xff000000)
9201 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
9202 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
9203 || prefix
!= REPE_PREFIX_OPCODE
9204 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
9205 add_prefix (prefix
);
9209 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
9211 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
9212 add_prefix (prefix
);
9218 /* Check for pseudo prefixes. */
9219 as_bad_where (insn_start_frag
->fr_file
,
9220 insn_start_frag
->fr_line
,
9221 _("pseudo prefix without instruction"));
9227 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9228 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9229 R_X86_64_GOTTPOFF relocation so that linker can safely
9230 perform IE->LE optimization. A dummy REX_OPCODE prefix
9231 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9232 relocation for GDesc -> IE/LE optimization. */
9233 if (x86_elf_abi
== X86_64_X32_ABI
9235 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9236 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9237 && i
.prefix
[REX_PREFIX
] == 0)
9238 add_prefix (REX_OPCODE
);
9241 /* The prefix bytes. */
9242 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9244 FRAG_APPEND_1_CHAR (*q
);
9248 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
9253 /* REX byte is encoded in VEX prefix. */
9257 FRAG_APPEND_1_CHAR (*q
);
9260 /* There should be no other prefixes for instructions
9265 /* For EVEX instructions i.vrex should become 0 after
9266 build_evex_prefix. For VEX instructions upper 16 registers
9267 aren't available, so VREX should be 0. */
9270 /* Now the VEX prefix. */
9271 p
= frag_more (i
.vex
.length
);
9272 for (j
= 0; j
< i
.vex
.length
; j
++)
9273 p
[j
] = i
.vex
.bytes
[j
];
9276 /* Now the opcode; be careful about word order here! */
9277 if (i
.tm
.opcode_length
== 1)
9279 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
9283 switch (i
.tm
.opcode_length
)
9287 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
9288 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9292 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
9302 /* Put out high byte first: can't use md_number_to_chars! */
9303 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
9304 *p
= i
.tm
.base_opcode
& 0xff;
9307 /* Now the modrm byte and sib byte (if present). */
9308 if (i
.tm
.opcode_modifier
.modrm
)
9310 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
9313 /* If i.rm.regmem == ESP (4)
9314 && i.rm.mode != (Register mode)
9316 ==> need second modrm byte. */
9317 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
9319 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
9320 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
9322 | i
.sib
.scale
<< 6));
9325 if (i
.disp_operands
)
9326 output_disp (insn_start_frag
, insn_start_off
);
9329 output_imm (insn_start_frag
, insn_start_off
);
9332 * frag_now_fix () returning plain abs_section_offset when we're in the
9333 * absolute section, and abs_section_offset not getting updated as data
9334 * gets added to the frag breaks the logic below.
9336 if (now_seg
!= absolute_section
)
9338 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
9340 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9344 /* NB: Don't add prefix with GOTPC relocation since
9345 output_disp() above depends on the fixed encoding
9346 length. Can't add prefix with TLS relocation since
9347 it breaks TLS linker optimization. */
9348 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
9349 /* Prefix count on the current instruction. */
9350 unsigned int count
= i
.vex
.length
;
9352 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
9353 /* REX byte is encoded in VEX/EVEX prefix. */
9354 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
9357 /* Count prefixes for extended opcode maps. */
9359 switch (i
.tm
.opcode_length
)
9362 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
9365 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
9377 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
9386 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
9389 /* Set the maximum prefix size in BRANCH_PREFIX
9391 if (fragP
->tc_frag_data
.max_bytes
> max
)
9392 fragP
->tc_frag_data
.max_bytes
= max
;
9393 if (fragP
->tc_frag_data
.max_bytes
> count
)
9394 fragP
->tc_frag_data
.max_bytes
-= count
;
9396 fragP
->tc_frag_data
.max_bytes
= 0;
9400 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9402 unsigned int max_prefix_size
;
9403 if (align_branch_prefix_size
> max
)
9404 max_prefix_size
= max
;
9406 max_prefix_size
= align_branch_prefix_size
;
9407 if (max_prefix_size
> count
)
9408 fragP
->tc_frag_data
.max_prefix_length
9409 = max_prefix_size
- count
;
9412 /* Use existing segment prefix if possible. Use CS
9413 segment prefix in 64-bit mode. In 32-bit mode, use SS
9414 segment prefix with ESP/EBP base register and use DS
9415 segment prefix without ESP/EBP base register. */
9416 if (i
.prefix
[SEG_PREFIX
])
9417 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
9418 else if (flag_code
== CODE_64BIT
)
9419 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
9421 && (i
.base_reg
->reg_num
== 4
9422 || i
.base_reg
->reg_num
== 5))
9423 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
9425 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
9430 /* NB: Don't work with COND_JUMP86 without i386. */
9431 if (align_branch_power
9432 && now_seg
!= absolute_section
9433 && cpu_arch_flags
.bitfield
.cpui386
)
9435 /* Terminate each frag so that we can add prefix and check for
9437 frag_wane (frag_now
);
9444 pi ("" /*line*/, &i
);
9446 #endif /* DEBUG386 */
9449 /* Return the size of the displacement operand N. */
9452 disp_size (unsigned int n
)
9456 if (i
.types
[n
].bitfield
.disp64
)
9458 else if (i
.types
[n
].bitfield
.disp8
)
9460 else if (i
.types
[n
].bitfield
.disp16
)
9465 /* Return the size of the immediate operand N. */
9468 imm_size (unsigned int n
)
9471 if (i
.types
[n
].bitfield
.imm64
)
9473 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9475 else if (i
.types
[n
].bitfield
.imm16
)
9481 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9486 for (n
= 0; n
< i
.operands
; n
++)
9488 if (operand_type_check (i
.types
[n
], disp
))
9490 if (i
.op
[n
].disps
->X_op
== O_constant
)
9492 int size
= disp_size (n
);
9493 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9495 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9497 p
= frag_more (size
);
9498 md_number_to_chars (p
, val
, size
);
9502 enum bfd_reloc_code_real reloc_type
;
9503 int size
= disp_size (n
);
9504 int sign
= i
.types
[n
].bitfield
.disp32s
;
9505 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9508 /* We can't have 8 bit displacement here. */
9509 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9511 /* The PC relative address is computed relative
9512 to the instruction boundary, so in case immediate
9513 fields follows, we need to adjust the value. */
9514 if (pcrel
&& i
.imm_operands
)
9519 for (n1
= 0; n1
< i
.operands
; n1
++)
9520 if (operand_type_check (i
.types
[n1
], imm
))
9522 /* Only one immediate is allowed for PC
9523 relative address. */
9524 gas_assert (sz
== 0);
9526 i
.op
[n
].disps
->X_add_number
-= sz
;
9528 /* We should find the immediate. */
9529 gas_assert (sz
!= 0);
9532 p
= frag_more (size
);
9533 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9535 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9536 && (((reloc_type
== BFD_RELOC_32
9537 || reloc_type
== BFD_RELOC_X86_64_32S
9538 || (reloc_type
== BFD_RELOC_64
9540 && (i
.op
[n
].disps
->X_op
== O_symbol
9541 || (i
.op
[n
].disps
->X_op
== O_add
9542 && ((symbol_get_value_expression
9543 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9545 || reloc_type
== BFD_RELOC_32_PCREL
))
9549 reloc_type
= BFD_RELOC_386_GOTPC
;
9550 i
.has_gotpc_tls_reloc
= TRUE
;
9551 i
.op
[n
].imms
->X_add_number
+=
9552 encoding_length (insn_start_frag
, insn_start_off
, p
);
9554 else if (reloc_type
== BFD_RELOC_64
)
9555 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9557 /* Don't do the adjustment for x86-64, as there
9558 the pcrel addressing is relative to the _next_
9559 insn, and that is taken care of in other code. */
9560 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9562 else if (align_branch_power
)
9566 case BFD_RELOC_386_TLS_GD
:
9567 case BFD_RELOC_386_TLS_LDM
:
9568 case BFD_RELOC_386_TLS_IE
:
9569 case BFD_RELOC_386_TLS_IE_32
:
9570 case BFD_RELOC_386_TLS_GOTIE
:
9571 case BFD_RELOC_386_TLS_GOTDESC
:
9572 case BFD_RELOC_386_TLS_DESC_CALL
:
9573 case BFD_RELOC_X86_64_TLSGD
:
9574 case BFD_RELOC_X86_64_TLSLD
:
9575 case BFD_RELOC_X86_64_GOTTPOFF
:
9576 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9577 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9578 i
.has_gotpc_tls_reloc
= TRUE
;
9583 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9584 size
, i
.op
[n
].disps
, pcrel
,
9586 /* Check for "call/jmp *mem", "mov mem, %reg",
9587 "test %reg, mem" and "binop mem, %reg" where binop
9588 is one of adc, add, and, cmp, or, sbb, sub, xor
9589 instructions without data prefix. Always generate
9590 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9591 if (i
.prefix
[DATA_PREFIX
] == 0
9592 && (generate_relax_relocations
9595 && i
.rm
.regmem
== 5))
9597 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9598 && !is_any_vex_encoding(&i
.tm
)
9599 && ((i
.operands
== 1
9600 && i
.tm
.base_opcode
== 0xff
9601 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9603 && (i
.tm
.base_opcode
== 0x8b
9604 || i
.tm
.base_opcode
== 0x85
9605 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9609 fixP
->fx_tcbit
= i
.rex
!= 0;
9611 && (i
.base_reg
->reg_num
== RegIP
))
9612 fixP
->fx_tcbit2
= 1;
9615 fixP
->fx_tcbit2
= 1;
9623 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9628 for (n
= 0; n
< i
.operands
; n
++)
9630 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9631 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9634 if (operand_type_check (i
.types
[n
], imm
))
9636 if (i
.op
[n
].imms
->X_op
== O_constant
)
9638 int size
= imm_size (n
);
9641 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9643 p
= frag_more (size
);
9644 md_number_to_chars (p
, val
, size
);
9648 /* Not absolute_section.
9649 Need a 32-bit fixup (don't support 8bit
9650 non-absolute imms). Try to support other
9652 enum bfd_reloc_code_real reloc_type
;
9653 int size
= imm_size (n
);
9656 if (i
.types
[n
].bitfield
.imm32s
9657 && (i
.suffix
== QWORD_MNEM_SUFFIX
9658 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9663 p
= frag_more (size
);
9664 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9666 /* This is tough to explain. We end up with this one if we
9667 * have operands that look like
9668 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9669 * obtain the absolute address of the GOT, and it is strongly
9670 * preferable from a performance point of view to avoid using
9671 * a runtime relocation for this. The actual sequence of
9672 * instructions often look something like:
9677 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9679 * The call and pop essentially return the absolute address
9680 * of the label .L66 and store it in %ebx. The linker itself
9681 * will ultimately change the first operand of the addl so
9682 * that %ebx points to the GOT, but to keep things simple, the
9683 * .o file must have this operand set so that it generates not
9684 * the absolute address of .L66, but the absolute address of
9685 * itself. This allows the linker itself simply treat a GOTPC
9686 * relocation as asking for a pcrel offset to the GOT to be
9687 * added in, and the addend of the relocation is stored in the
9688 * operand field for the instruction itself.
9690 * Our job here is to fix the operand so that it would add
9691 * the correct offset so that %ebx would point to itself. The
9692 * thing that is tricky is that .-.L66 will point to the
9693 * beginning of the instruction, so we need to further modify
9694 * the operand so that it will point to itself. There are
9695 * other cases where you have something like:
9697 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9699 * and here no correction would be required. Internally in
9700 * the assembler we treat operands of this form as not being
9701 * pcrel since the '.' is explicitly mentioned, and I wonder
9702 * whether it would simplify matters to do it this way. Who
9703 * knows. In earlier versions of the PIC patches, the
9704 * pcrel_adjust field was used to store the correction, but
9705 * since the expression is not pcrel, I felt it would be
9706 * confusing to do it this way. */
9708 if ((reloc_type
== BFD_RELOC_32
9709 || reloc_type
== BFD_RELOC_X86_64_32S
9710 || reloc_type
== BFD_RELOC_64
)
9712 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9713 && (i
.op
[n
].imms
->X_op
== O_symbol
9714 || (i
.op
[n
].imms
->X_op
== O_add
9715 && ((symbol_get_value_expression
9716 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9720 reloc_type
= BFD_RELOC_386_GOTPC
;
9722 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9724 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9725 i
.has_gotpc_tls_reloc
= TRUE
;
9726 i
.op
[n
].imms
->X_add_number
+=
9727 encoding_length (insn_start_frag
, insn_start_off
, p
);
9729 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9730 i
.op
[n
].imms
, 0, reloc_type
);
9736 /* x86_cons_fix_new is called via the expression parsing code when a
9737 reloc is needed. We use this hook to get the correct .got reloc. */
9738 static int cons_sign
= -1;
9741 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9742 expressionS
*exp
, bfd_reloc_code_real_type r
)
9744 r
= reloc (len
, 0, cons_sign
, r
);
9747 if (exp
->X_op
== O_secrel
)
9749 exp
->X_op
= O_symbol
;
9750 r
= BFD_RELOC_32_SECREL
;
9754 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9757 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9758 purpose of the `.dc.a' internal pseudo-op. */
9761 x86_address_bytes (void)
9763 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9765 return stdoutput
->arch_info
->bits_per_address
/ 8;
9768 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9770 # define lex_got(reloc, adjust, types) NULL
9772 /* Parse operands of the form
9773 <symbol>@GOTOFF+<nnn>
9774 and similar .plt or .got references.
9776 If we find one, set up the correct relocation in RELOC and copy the
9777 input string, minus the `@GOTOFF' into a malloc'd buffer for
9778 parsing by the calling routine. Return this buffer, and if ADJUST
9779 is non-null set it to the length of the string we removed from the
9780 input line. Otherwise return NULL. */
9782 lex_got (enum bfd_reloc_code_real
*rel
,
9784 i386_operand_type
*types
)
9786 /* Some of the relocations depend on the size of what field is to
9787 be relocated. But in our callers i386_immediate and i386_displacement
9788 we don't yet know the operand size (this will be set by insn
9789 matching). Hence we record the word32 relocation here,
9790 and adjust the reloc according to the real size in reloc(). */
9791 static const struct {
9794 const enum bfd_reloc_code_real rel
[2];
9795 const i386_operand_type types64
;
9797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9798 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9800 OPERAND_TYPE_IMM32_64
},
9802 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9803 BFD_RELOC_X86_64_PLTOFF64
},
9804 OPERAND_TYPE_IMM64
},
9805 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9806 BFD_RELOC_X86_64_PLT32
},
9807 OPERAND_TYPE_IMM32_32S_DISP32
},
9808 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9809 BFD_RELOC_X86_64_GOTPLT64
},
9810 OPERAND_TYPE_IMM64_DISP64
},
9811 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9812 BFD_RELOC_X86_64_GOTOFF64
},
9813 OPERAND_TYPE_IMM64_DISP64
},
9814 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9815 BFD_RELOC_X86_64_GOTPCREL
},
9816 OPERAND_TYPE_IMM32_32S_DISP32
},
9817 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9818 BFD_RELOC_X86_64_TLSGD
},
9819 OPERAND_TYPE_IMM32_32S_DISP32
},
9820 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9821 _dummy_first_bfd_reloc_code_real
},
9822 OPERAND_TYPE_NONE
},
9823 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9824 BFD_RELOC_X86_64_TLSLD
},
9825 OPERAND_TYPE_IMM32_32S_DISP32
},
9826 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9827 BFD_RELOC_X86_64_GOTTPOFF
},
9828 OPERAND_TYPE_IMM32_32S_DISP32
},
9829 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9830 BFD_RELOC_X86_64_TPOFF32
},
9831 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9832 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9833 _dummy_first_bfd_reloc_code_real
},
9834 OPERAND_TYPE_NONE
},
9835 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9836 BFD_RELOC_X86_64_DTPOFF32
},
9837 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9838 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9839 _dummy_first_bfd_reloc_code_real
},
9840 OPERAND_TYPE_NONE
},
9841 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9842 _dummy_first_bfd_reloc_code_real
},
9843 OPERAND_TYPE_NONE
},
9844 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9845 BFD_RELOC_X86_64_GOT32
},
9846 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9847 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9848 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9849 OPERAND_TYPE_IMM32_32S_DISP32
},
9850 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9851 BFD_RELOC_X86_64_TLSDESC_CALL
},
9852 OPERAND_TYPE_IMM32_32S_DISP32
},
9857 #if defined (OBJ_MAYBE_ELF)
9862 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9863 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9866 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9868 int len
= gotrel
[j
].len
;
9869 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9871 if (gotrel
[j
].rel
[object_64bit
] != 0)
9874 char *tmpbuf
, *past_reloc
;
9876 *rel
= gotrel
[j
].rel
[object_64bit
];
9880 if (flag_code
!= CODE_64BIT
)
9882 types
->bitfield
.imm32
= 1;
9883 types
->bitfield
.disp32
= 1;
9886 *types
= gotrel
[j
].types64
;
9889 if (j
!= 0 && GOT_symbol
== NULL
)
9890 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9892 /* The length of the first part of our input line. */
9893 first
= cp
- input_line_pointer
;
9895 /* The second part goes from after the reloc token until
9896 (and including) an end_of_line char or comma. */
9897 past_reloc
= cp
+ 1 + len
;
9899 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9901 second
= cp
+ 1 - past_reloc
;
9903 /* Allocate and copy string. The trailing NUL shouldn't
9904 be necessary, but be safe. */
9905 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9906 memcpy (tmpbuf
, input_line_pointer
, first
);
9907 if (second
!= 0 && *past_reloc
!= ' ')
9908 /* Replace the relocation token with ' ', so that
9909 errors like foo@GOTOFF1 will be detected. */
9910 tmpbuf
[first
++] = ' ';
9912 /* Increment length by 1 if the relocation token is
9917 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9918 tmpbuf
[first
+ second
] = '\0';
9922 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9923 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9928 /* Might be a symbol version string. Don't as_bad here. */
9937 /* Parse operands of the form
9938 <symbol>@SECREL32+<nnn>
9940 If we find one, set up the correct relocation in RELOC and copy the
9941 input string, minus the `@SECREL32' into a malloc'd buffer for
9942 parsing by the calling routine. Return this buffer, and if ADJUST
9943 is non-null set it to the length of the string we removed from the
9944 input line. Otherwise return NULL.
9946 This function is copied from the ELF version above adjusted for PE targets. */
9949 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9950 int *adjust ATTRIBUTE_UNUSED
,
9951 i386_operand_type
*types
)
9957 const enum bfd_reloc_code_real rel
[2];
9958 const i386_operand_type types64
;
9962 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9963 BFD_RELOC_32_SECREL
},
9964 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9970 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9971 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9974 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9976 int len
= gotrel
[j
].len
;
9978 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9980 if (gotrel
[j
].rel
[object_64bit
] != 0)
9983 char *tmpbuf
, *past_reloc
;
9985 *rel
= gotrel
[j
].rel
[object_64bit
];
9991 if (flag_code
!= CODE_64BIT
)
9993 types
->bitfield
.imm32
= 1;
9994 types
->bitfield
.disp32
= 1;
9997 *types
= gotrel
[j
].types64
;
10000 /* The length of the first part of our input line. */
10001 first
= cp
- input_line_pointer
;
10003 /* The second part goes from after the reloc token until
10004 (and including) an end_of_line char or comma. */
10005 past_reloc
= cp
+ 1 + len
;
10007 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10009 second
= cp
+ 1 - past_reloc
;
10011 /* Allocate and copy string. The trailing NUL shouldn't
10012 be necessary, but be safe. */
10013 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10014 memcpy (tmpbuf
, input_line_pointer
, first
);
10015 if (second
!= 0 && *past_reloc
!= ' ')
10016 /* Replace the relocation token with ' ', so that
10017 errors like foo@SECLREL321 will be detected. */
10018 tmpbuf
[first
++] = ' ';
10019 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10020 tmpbuf
[first
+ second
] = '\0';
10024 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10025 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10030 /* Might be a symbol version string. Don't as_bad here. */
10036 bfd_reloc_code_real_type
10037 x86_cons (expressionS
*exp
, int size
)
10039 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10041 intel_syntax
= -intel_syntax
;
10044 if (size
== 4 || (object_64bit
&& size
== 8))
10046 /* Handle @GOTOFF and the like in an expression. */
10048 char *gotfree_input_line
;
10051 save
= input_line_pointer
;
10052 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10053 if (gotfree_input_line
)
10054 input_line_pointer
= gotfree_input_line
;
10058 if (gotfree_input_line
)
10060 /* expression () has merrily parsed up to the end of line,
10061 or a comma - in the wrong buffer. Transfer how far
10062 input_line_pointer has moved to the right buffer. */
10063 input_line_pointer
= (save
10064 + (input_line_pointer
- gotfree_input_line
)
10066 free (gotfree_input_line
);
10067 if (exp
->X_op
== O_constant
10068 || exp
->X_op
== O_absent
10069 || exp
->X_op
== O_illegal
10070 || exp
->X_op
== O_register
10071 || exp
->X_op
== O_big
)
10073 char c
= *input_line_pointer
;
10074 *input_line_pointer
= 0;
10075 as_bad (_("missing or invalid expression `%s'"), save
);
10076 *input_line_pointer
= c
;
10078 else if ((got_reloc
== BFD_RELOC_386_PLT32
10079 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10080 && exp
->X_op
!= O_symbol
)
10082 char c
= *input_line_pointer
;
10083 *input_line_pointer
= 0;
10084 as_bad (_("invalid PLT expression `%s'"), save
);
10085 *input_line_pointer
= c
;
10092 intel_syntax
= -intel_syntax
;
10095 i386_intel_simplify (exp
);
10101 signed_cons (int size
)
10103 if (flag_code
== CODE_64BIT
)
10111 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
10118 if (exp
.X_op
== O_symbol
)
10119 exp
.X_op
= O_secrel
;
10121 emit_expr (&exp
, 4);
10123 while (*input_line_pointer
++ == ',');
10125 input_line_pointer
--;
10126 demand_empty_rest_of_line ();
10130 /* Handle Vector operations. */
10133 check_VecOperations (char *op_string
, char *op_end
)
10135 const reg_entry
*mask
;
10140 && (op_end
== NULL
|| op_string
< op_end
))
10143 if (*op_string
== '{')
10147 /* Check broadcasts. */
10148 if (strncmp (op_string
, "1to", 3) == 0)
10153 goto duplicated_vec_op
;
10156 if (*op_string
== '8')
10158 else if (*op_string
== '4')
10160 else if (*op_string
== '2')
10162 else if (*op_string
== '1'
10163 && *(op_string
+1) == '6')
10170 as_bad (_("Unsupported broadcast: `%s'"), saved
);
10175 broadcast_op
.type
= bcst_type
;
10176 broadcast_op
.operand
= this_operand
;
10177 broadcast_op
.bytes
= 0;
10178 i
.broadcast
= &broadcast_op
;
10180 /* Check masking operation. */
10181 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
10183 if (mask
== &bad_reg
)
10186 /* k0 can't be used for write mask. */
10187 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
10189 as_bad (_("`%s%s' can't be used for write mask"),
10190 register_prefix
, mask
->reg_name
);
10196 mask_op
.mask
= mask
;
10197 mask_op
.zeroing
= 0;
10198 mask_op
.operand
= this_operand
;
10204 goto duplicated_vec_op
;
10206 i
.mask
->mask
= mask
;
10208 /* Only "{z}" is allowed here. No need to check
10209 zeroing mask explicitly. */
10210 if (i
.mask
->operand
!= this_operand
)
10212 as_bad (_("invalid write mask `%s'"), saved
);
10217 op_string
= end_op
;
10219 /* Check zeroing-flag for masking operation. */
10220 else if (*op_string
== 'z')
10224 mask_op
.mask
= NULL
;
10225 mask_op
.zeroing
= 1;
10226 mask_op
.operand
= this_operand
;
10231 if (i
.mask
->zeroing
)
10234 as_bad (_("duplicated `%s'"), saved
);
10238 i
.mask
->zeroing
= 1;
10240 /* Only "{%k}" is allowed here. No need to check mask
10241 register explicitly. */
10242 if (i
.mask
->operand
!= this_operand
)
10244 as_bad (_("invalid zeroing-masking `%s'"),
10253 goto unknown_vec_op
;
10255 if (*op_string
!= '}')
10257 as_bad (_("missing `}' in `%s'"), saved
);
10262 /* Strip whitespace since the addition of pseudo prefixes
10263 changed how the scrubber treats '{'. */
10264 if (is_space_char (*op_string
))
10270 /* We don't know this one. */
10271 as_bad (_("unknown vector operation: `%s'"), saved
);
10275 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
10277 as_bad (_("zeroing-masking only allowed with write mask"));
10285 i386_immediate (char *imm_start
)
10287 char *save_input_line_pointer
;
10288 char *gotfree_input_line
;
10291 i386_operand_type types
;
10293 operand_type_set (&types
, ~0);
10295 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
10297 as_bad (_("at most %d immediate operands are allowed"),
10298 MAX_IMMEDIATE_OPERANDS
);
10302 exp
= &im_expressions
[i
.imm_operands
++];
10303 i
.op
[this_operand
].imms
= exp
;
10305 if (is_space_char (*imm_start
))
10308 save_input_line_pointer
= input_line_pointer
;
10309 input_line_pointer
= imm_start
;
10311 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10312 if (gotfree_input_line
)
10313 input_line_pointer
= gotfree_input_line
;
10315 exp_seg
= expression (exp
);
10317 SKIP_WHITESPACE ();
10319 /* Handle vector operations. */
10320 if (*input_line_pointer
== '{')
10322 input_line_pointer
= check_VecOperations (input_line_pointer
,
10324 if (input_line_pointer
== NULL
)
10328 if (*input_line_pointer
)
10329 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10331 input_line_pointer
= save_input_line_pointer
;
10332 if (gotfree_input_line
)
10334 free (gotfree_input_line
);
10336 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10337 exp
->X_op
= O_illegal
;
10340 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
10344 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10345 i386_operand_type types
, const char *imm_start
)
10347 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
10350 as_bad (_("missing or invalid immediate expression `%s'"),
10354 else if (exp
->X_op
== O_constant
)
10356 /* Size it properly later. */
10357 i
.types
[this_operand
].bitfield
.imm64
= 1;
10358 /* If not 64bit, sign extend val. */
10359 if (flag_code
!= CODE_64BIT
10360 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
10362 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
10364 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10365 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
10366 && exp_seg
!= absolute_section
10367 && exp_seg
!= text_section
10368 && exp_seg
!= data_section
10369 && exp_seg
!= bss_section
10370 && exp_seg
!= undefined_section
10371 && !bfd_is_com_section (exp_seg
))
10373 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10377 else if (!intel_syntax
&& exp_seg
== reg_section
)
10380 as_bad (_("illegal immediate register operand %s"), imm_start
);
10385 /* This is an address. The size of the address will be
10386 determined later, depending on destination register,
10387 suffix, or the default for the section. */
10388 i
.types
[this_operand
].bitfield
.imm8
= 1;
10389 i
.types
[this_operand
].bitfield
.imm16
= 1;
10390 i
.types
[this_operand
].bitfield
.imm32
= 1;
10391 i
.types
[this_operand
].bitfield
.imm32s
= 1;
10392 i
.types
[this_operand
].bitfield
.imm64
= 1;
10393 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10401 i386_scale (char *scale
)
10404 char *save
= input_line_pointer
;
10406 input_line_pointer
= scale
;
10407 val
= get_absolute_expression ();
10412 i
.log2_scale_factor
= 0;
10415 i
.log2_scale_factor
= 1;
10418 i
.log2_scale_factor
= 2;
10421 i
.log2_scale_factor
= 3;
10425 char sep
= *input_line_pointer
;
10427 *input_line_pointer
= '\0';
10428 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10430 *input_line_pointer
= sep
;
10431 input_line_pointer
= save
;
10435 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
10437 as_warn (_("scale factor of %d without an index register"),
10438 1 << i
.log2_scale_factor
);
10439 i
.log2_scale_factor
= 0;
10441 scale
= input_line_pointer
;
10442 input_line_pointer
= save
;
10447 i386_displacement (char *disp_start
, char *disp_end
)
10451 char *save_input_line_pointer
;
10452 char *gotfree_input_line
;
10454 i386_operand_type bigdisp
, types
= anydisp
;
10457 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10459 as_bad (_("at most %d displacement operands are allowed"),
10460 MAX_MEMORY_OPERANDS
);
10464 operand_type_set (&bigdisp
, 0);
10466 || i
.types
[this_operand
].bitfield
.baseindex
10467 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10468 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10470 i386_addressing_mode ();
10471 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10472 if (flag_code
== CODE_64BIT
)
10476 bigdisp
.bitfield
.disp32s
= 1;
10477 bigdisp
.bitfield
.disp64
= 1;
10480 bigdisp
.bitfield
.disp32
= 1;
10482 else if ((flag_code
== CODE_16BIT
) ^ override
)
10483 bigdisp
.bitfield
.disp16
= 1;
10485 bigdisp
.bitfield
.disp32
= 1;
10489 /* For PC-relative branches, the width of the displacement may be
10490 dependent upon data size, but is never dependent upon address size.
10491 Also make sure to not unintentionally match against a non-PC-relative
10492 branch template. */
10493 static templates aux_templates
;
10494 const insn_template
*t
= current_templates
->start
;
10495 bfd_boolean has_intel64
= FALSE
;
10497 aux_templates
.start
= t
;
10498 while (++t
< current_templates
->end
)
10500 if (t
->opcode_modifier
.jump
10501 != current_templates
->start
->opcode_modifier
.jump
)
10503 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10504 has_intel64
= TRUE
;
10506 if (t
< current_templates
->end
)
10508 aux_templates
.end
= t
;
10509 current_templates
= &aux_templates
;
10512 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10513 if (flag_code
== CODE_64BIT
)
10515 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10516 && (!intel64
|| !has_intel64
))
10517 bigdisp
.bitfield
.disp16
= 1;
10519 bigdisp
.bitfield
.disp32s
= 1;
10524 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10526 : LONG_MNEM_SUFFIX
));
10527 bigdisp
.bitfield
.disp32
= 1;
10528 if ((flag_code
== CODE_16BIT
) ^ override
)
10530 bigdisp
.bitfield
.disp32
= 0;
10531 bigdisp
.bitfield
.disp16
= 1;
10535 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10538 exp
= &disp_expressions
[i
.disp_operands
];
10539 i
.op
[this_operand
].disps
= exp
;
10541 save_input_line_pointer
= input_line_pointer
;
10542 input_line_pointer
= disp_start
;
10543 END_STRING_AND_SAVE (disp_end
);
10545 #ifndef GCC_ASM_O_HACK
10546 #define GCC_ASM_O_HACK 0
10549 END_STRING_AND_SAVE (disp_end
+ 1);
10550 if (i
.types
[this_operand
].bitfield
.baseIndex
10551 && displacement_string_end
[-1] == '+')
10553 /* This hack is to avoid a warning when using the "o"
10554 constraint within gcc asm statements.
10557 #define _set_tssldt_desc(n,addr,limit,type) \
10558 __asm__ __volatile__ ( \
10559 "movw %w2,%0\n\t" \
10560 "movw %w1,2+%0\n\t" \
10561 "rorl $16,%1\n\t" \
10562 "movb %b1,4+%0\n\t" \
10563 "movb %4,5+%0\n\t" \
10564 "movb $0,6+%0\n\t" \
10565 "movb %h1,7+%0\n\t" \
10567 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10569 This works great except that the output assembler ends
10570 up looking a bit weird if it turns out that there is
10571 no offset. You end up producing code that looks like:
10584 So here we provide the missing zero. */
10586 *displacement_string_end
= '0';
10589 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10590 if (gotfree_input_line
)
10591 input_line_pointer
= gotfree_input_line
;
10593 exp_seg
= expression (exp
);
10595 SKIP_WHITESPACE ();
10596 if (*input_line_pointer
)
10597 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10599 RESTORE_END_STRING (disp_end
+ 1);
10601 input_line_pointer
= save_input_line_pointer
;
10602 if (gotfree_input_line
)
10604 free (gotfree_input_line
);
10606 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10607 exp
->X_op
= O_illegal
;
10610 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10612 RESTORE_END_STRING (disp_end
);
10618 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10619 i386_operand_type types
, const char *disp_start
)
10621 i386_operand_type bigdisp
;
10624 /* We do this to make sure that the section symbol is in
10625 the symbol table. We will ultimately change the relocation
10626 to be relative to the beginning of the section. */
10627 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10628 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10629 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10631 if (exp
->X_op
!= O_symbol
)
10634 if (S_IS_LOCAL (exp
->X_add_symbol
)
10635 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10636 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10637 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10638 exp
->X_op
= O_subtract
;
10639 exp
->X_op_symbol
= GOT_symbol
;
10640 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10641 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10642 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10643 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10645 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10648 else if (exp
->X_op
== O_absent
10649 || exp
->X_op
== O_illegal
10650 || exp
->X_op
== O_big
)
10653 as_bad (_("missing or invalid displacement expression `%s'"),
10658 else if (flag_code
== CODE_64BIT
10659 && !i
.prefix
[ADDR_PREFIX
]
10660 && exp
->X_op
== O_constant
)
10662 /* Since displacement is signed extended to 64bit, don't allow
10663 disp32 and turn off disp32s if they are out of range. */
10664 i
.types
[this_operand
].bitfield
.disp32
= 0;
10665 if (!fits_in_signed_long (exp
->X_add_number
))
10667 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10668 if (i
.types
[this_operand
].bitfield
.baseindex
)
10670 as_bad (_("0x%lx out range of signed 32bit displacement"),
10671 (long) exp
->X_add_number
);
10677 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10678 else if (exp
->X_op
!= O_constant
10679 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10680 && exp_seg
!= absolute_section
10681 && exp_seg
!= text_section
10682 && exp_seg
!= data_section
10683 && exp_seg
!= bss_section
10684 && exp_seg
!= undefined_section
10685 && !bfd_is_com_section (exp_seg
))
10687 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10692 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10693 /* Constants get taken care of by optimize_disp(). */
10694 && exp
->X_op
!= O_constant
)
10695 i
.types
[this_operand
].bitfield
.disp8
= 1;
10697 /* Check if this is a displacement only operand. */
10698 bigdisp
= i
.types
[this_operand
];
10699 bigdisp
.bitfield
.disp8
= 0;
10700 bigdisp
.bitfield
.disp16
= 0;
10701 bigdisp
.bitfield
.disp32
= 0;
10702 bigdisp
.bitfield
.disp32s
= 0;
10703 bigdisp
.bitfield
.disp64
= 0;
10704 if (operand_type_all_zero (&bigdisp
))
10705 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10711 /* Return the active addressing mode, taking address override and
10712 registers forming the address into consideration. Update the
10713 address override prefix if necessary. */
10715 static enum flag_code
10716 i386_addressing_mode (void)
10718 enum flag_code addr_mode
;
10720 if (i
.prefix
[ADDR_PREFIX
])
10721 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10722 else if (flag_code
== CODE_16BIT
10723 && current_templates
->start
->cpu_flags
.bitfield
.cpumpx
10724 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10725 from md_assemble() by "is not a valid base/index expression"
10726 when there is a base and/or index. */
10727 && !i
.types
[this_operand
].bitfield
.baseindex
)
10729 /* MPX insn memory operands with neither base nor index must be forced
10730 to use 32-bit addressing in 16-bit mode. */
10731 addr_mode
= CODE_32BIT
;
10732 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10734 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
10735 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
10739 addr_mode
= flag_code
;
10741 #if INFER_ADDR_PREFIX
10742 if (i
.mem_operands
== 0)
10744 /* Infer address prefix from the first memory operand. */
10745 const reg_entry
*addr_reg
= i
.base_reg
;
10747 if (addr_reg
== NULL
)
10748 addr_reg
= i
.index_reg
;
10752 if (addr_reg
->reg_type
.bitfield
.dword
)
10753 addr_mode
= CODE_32BIT
;
10754 else if (flag_code
!= CODE_64BIT
10755 && addr_reg
->reg_type
.bitfield
.word
)
10756 addr_mode
= CODE_16BIT
;
10758 if (addr_mode
!= flag_code
)
10760 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10762 /* Change the size of any displacement too. At most one
10763 of Disp16 or Disp32 is set.
10764 FIXME. There doesn't seem to be any real need for
10765 separate Disp16 and Disp32 flags. The same goes for
10766 Imm16 and Imm32. Removing them would probably clean
10767 up the code quite a lot. */
10768 if (flag_code
!= CODE_64BIT
10769 && (i
.types
[this_operand
].bitfield
.disp16
10770 || i
.types
[this_operand
].bitfield
.disp32
))
10771 i
.types
[this_operand
]
10772 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10782 /* Make sure the memory operand we've been dealt is valid.
10783 Return 1 on success, 0 on a failure. */
10786 i386_index_check (const char *operand_string
)
10788 const char *kind
= "base/index";
10789 enum flag_code addr_mode
= i386_addressing_mode ();
10791 if (current_templates
->start
->opcode_modifier
.isstring
10792 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10793 && (current_templates
->end
[-1].opcode_modifier
.isstring
10794 || i
.mem_operands
))
10796 /* Memory operands of string insns are special in that they only allow
10797 a single register (rDI, rSI, or rBX) as their memory address. */
10798 const reg_entry
*expected_reg
;
10799 static const char *di_si
[][2] =
10805 static const char *bx
[] = { "ebx", "bx", "rbx" };
10807 kind
= "string address";
10809 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10811 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10812 - IS_STRING_ES_OP0
;
10815 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10816 || ((!i
.mem_operands
!= !intel_syntax
)
10817 && current_templates
->end
[-1].operand_types
[1]
10818 .bitfield
.baseindex
))
10820 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10823 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10825 if (i
.base_reg
!= expected_reg
10827 || operand_type_check (i
.types
[this_operand
], disp
))
10829 /* The second memory operand must have the same size as
10833 && !((addr_mode
== CODE_64BIT
10834 && i
.base_reg
->reg_type
.bitfield
.qword
)
10835 || (addr_mode
== CODE_32BIT
10836 ? i
.base_reg
->reg_type
.bitfield
.dword
10837 : i
.base_reg
->reg_type
.bitfield
.word
)))
10840 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10842 intel_syntax
? '[' : '(',
10844 expected_reg
->reg_name
,
10845 intel_syntax
? ']' : ')');
10852 as_bad (_("`%s' is not a valid %s expression"),
10853 operand_string
, kind
);
10858 if (addr_mode
!= CODE_16BIT
)
10860 /* 32-bit/64-bit checks. */
10862 && ((addr_mode
== CODE_64BIT
10863 ? !i
.base_reg
->reg_type
.bitfield
.qword
10864 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10865 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10866 || i
.base_reg
->reg_num
== RegIZ
))
10868 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10869 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10870 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10871 && ((addr_mode
== CODE_64BIT
10872 ? !i
.index_reg
->reg_type
.bitfield
.qword
10873 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10874 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10877 /* bndmk, bndldx, and bndstx have special restrictions. */
10878 if (current_templates
->start
->base_opcode
== 0xf30f1b
10879 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10881 /* They cannot use RIP-relative addressing. */
10882 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10884 as_bad (_("`%s' cannot be used here"), operand_string
);
10888 /* bndldx and bndstx ignore their scale factor. */
10889 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10890 && i
.log2_scale_factor
)
10891 as_warn (_("register scaling is being ignored here"));
10896 /* 16-bit checks. */
10898 && (!i
.base_reg
->reg_type
.bitfield
.word
10899 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10901 && (!i
.index_reg
->reg_type
.bitfield
.word
10902 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10904 && i
.base_reg
->reg_num
< 6
10905 && i
.index_reg
->reg_num
>= 6
10906 && i
.log2_scale_factor
== 0))))
10913 /* Handle vector immediates. */
10916 RC_SAE_immediate (const char *imm_start
)
10918 unsigned int match_found
, j
;
10919 const char *pstr
= imm_start
;
10927 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10929 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10933 rc_op
.type
= RC_NamesTable
[j
].type
;
10934 rc_op
.operand
= this_operand
;
10935 i
.rounding
= &rc_op
;
10939 as_bad (_("duplicated `%s'"), imm_start
);
10942 pstr
+= RC_NamesTable
[j
].len
;
10950 if (*pstr
++ != '}')
10952 as_bad (_("Missing '}': '%s'"), imm_start
);
10955 /* RC/SAE immediate string should contain nothing more. */;
10958 as_bad (_("Junk after '}': '%s'"), imm_start
);
10962 exp
= &im_expressions
[i
.imm_operands
++];
10963 i
.op
[this_operand
].imms
= exp
;
10965 exp
->X_op
= O_constant
;
10966 exp
->X_add_number
= 0;
10967 exp
->X_add_symbol
= (symbolS
*) 0;
10968 exp
->X_op_symbol
= (symbolS
*) 0;
10970 i
.types
[this_operand
].bitfield
.imm8
= 1;
10974 /* Only string instructions can have a second memory operand, so
10975 reduce current_templates to just those if it contains any. */
10977 maybe_adjust_templates (void)
10979 const insn_template
*t
;
10981 gas_assert (i
.mem_operands
== 1);
10983 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10984 if (t
->opcode_modifier
.isstring
)
10987 if (t
< current_templates
->end
)
10989 static templates aux_templates
;
10990 bfd_boolean recheck
;
10992 aux_templates
.start
= t
;
10993 for (; t
< current_templates
->end
; ++t
)
10994 if (!t
->opcode_modifier
.isstring
)
10996 aux_templates
.end
= t
;
10998 /* Determine whether to re-check the first memory operand. */
10999 recheck
= (aux_templates
.start
!= current_templates
->start
11000 || t
!= current_templates
->end
);
11002 current_templates
= &aux_templates
;
11006 i
.mem_operands
= 0;
11007 if (i
.memop1_string
!= NULL
11008 && i386_index_check (i
.memop1_string
) == 0)
11010 i
.mem_operands
= 1;
11017 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11021 i386_att_operand (char *operand_string
)
11023 const reg_entry
*r
;
11025 char *op_string
= operand_string
;
11027 if (is_space_char (*op_string
))
11030 /* We check for an absolute prefix (differentiating,
11031 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11032 if (*op_string
== ABSOLUTE_PREFIX
)
11035 if (is_space_char (*op_string
))
11037 i
.jumpabsolute
= TRUE
;
11040 /* Check if operand is a register. */
11041 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
11043 i386_operand_type temp
;
11048 /* Check for a segment override by searching for ':' after a
11049 segment register. */
11050 op_string
= end_op
;
11051 if (is_space_char (*op_string
))
11053 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
11055 switch (r
->reg_num
)
11058 i
.seg
[i
.mem_operands
] = &es
;
11061 i
.seg
[i
.mem_operands
] = &cs
;
11064 i
.seg
[i
.mem_operands
] = &ss
;
11067 i
.seg
[i
.mem_operands
] = &ds
;
11070 i
.seg
[i
.mem_operands
] = &fs
;
11073 i
.seg
[i
.mem_operands
] = &gs
;
11077 /* Skip the ':' and whitespace. */
11079 if (is_space_char (*op_string
))
11082 if (!is_digit_char (*op_string
)
11083 && !is_identifier_char (*op_string
)
11084 && *op_string
!= '('
11085 && *op_string
!= ABSOLUTE_PREFIX
)
11087 as_bad (_("bad memory operand `%s'"), op_string
);
11090 /* Handle case of %es:*foo. */
11091 if (*op_string
== ABSOLUTE_PREFIX
)
11094 if (is_space_char (*op_string
))
11096 i
.jumpabsolute
= TRUE
;
11098 goto do_memory_reference
;
11101 /* Handle vector operations. */
11102 if (*op_string
== '{')
11104 op_string
= check_VecOperations (op_string
, NULL
);
11105 if (op_string
== NULL
)
11111 as_bad (_("junk `%s' after register"), op_string
);
11114 temp
= r
->reg_type
;
11115 temp
.bitfield
.baseindex
= 0;
11116 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
11118 i
.types
[this_operand
].bitfield
.unspecified
= 0;
11119 i
.op
[this_operand
].regs
= r
;
11122 else if (*op_string
== REGISTER_PREFIX
)
11124 as_bad (_("bad register name `%s'"), op_string
);
11127 else if (*op_string
== IMMEDIATE_PREFIX
)
11130 if (i
.jumpabsolute
)
11132 as_bad (_("immediate operand illegal with absolute jump"));
11135 if (!i386_immediate (op_string
))
11138 else if (RC_SAE_immediate (operand_string
))
11140 /* If it is a RC or SAE immediate, do nothing. */
11143 else if (is_digit_char (*op_string
)
11144 || is_identifier_char (*op_string
)
11145 || *op_string
== '"'
11146 || *op_string
== '(')
11148 /* This is a memory reference of some sort. */
11151 /* Start and end of displacement string expression (if found). */
11152 char *displacement_string_start
;
11153 char *displacement_string_end
;
11156 do_memory_reference
:
11157 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
11159 if ((i
.mem_operands
== 1
11160 && !current_templates
->start
->opcode_modifier
.isstring
)
11161 || i
.mem_operands
== 2)
11163 as_bad (_("too many memory references for `%s'"),
11164 current_templates
->start
->name
);
11168 /* Check for base index form. We detect the base index form by
11169 looking for an ')' at the end of the operand, searching
11170 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11172 base_string
= op_string
+ strlen (op_string
);
11174 /* Handle vector operations. */
11175 vop_start
= strchr (op_string
, '{');
11176 if (vop_start
&& vop_start
< base_string
)
11178 if (check_VecOperations (vop_start
, base_string
) == NULL
)
11180 base_string
= vop_start
;
11184 if (is_space_char (*base_string
))
11187 /* If we only have a displacement, set-up for it to be parsed later. */
11188 displacement_string_start
= op_string
;
11189 displacement_string_end
= base_string
+ 1;
11191 if (*base_string
== ')')
11194 unsigned int parens_balanced
= 1;
11195 /* We've already checked that the number of left & right ()'s are
11196 equal, so this loop will not be infinite. */
11200 if (*base_string
== ')')
11202 if (*base_string
== '(')
11205 while (parens_balanced
);
11207 temp_string
= base_string
;
11209 /* Skip past '(' and whitespace. */
11211 if (is_space_char (*base_string
))
11214 if (*base_string
== ','
11215 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
11218 displacement_string_end
= temp_string
;
11220 i
.types
[this_operand
].bitfield
.baseindex
= 1;
11224 if (i
.base_reg
== &bad_reg
)
11226 base_string
= end_op
;
11227 if (is_space_char (*base_string
))
11231 /* There may be an index reg or scale factor here. */
11232 if (*base_string
== ',')
11235 if (is_space_char (*base_string
))
11238 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
11241 if (i
.index_reg
== &bad_reg
)
11243 base_string
= end_op
;
11244 if (is_space_char (*base_string
))
11246 if (*base_string
== ',')
11249 if (is_space_char (*base_string
))
11252 else if (*base_string
!= ')')
11254 as_bad (_("expecting `,' or `)' "
11255 "after index register in `%s'"),
11260 else if (*base_string
== REGISTER_PREFIX
)
11262 end_op
= strchr (base_string
, ',');
11265 as_bad (_("bad register name `%s'"), base_string
);
11269 /* Check for scale factor. */
11270 if (*base_string
!= ')')
11272 char *end_scale
= i386_scale (base_string
);
11277 base_string
= end_scale
;
11278 if (is_space_char (*base_string
))
11280 if (*base_string
!= ')')
11282 as_bad (_("expecting `)' "
11283 "after scale factor in `%s'"),
11288 else if (!i
.index_reg
)
11290 as_bad (_("expecting index register or scale factor "
11291 "after `,'; got '%c'"),
11296 else if (*base_string
!= ')')
11298 as_bad (_("expecting `,' or `)' "
11299 "after base register in `%s'"),
11304 else if (*base_string
== REGISTER_PREFIX
)
11306 end_op
= strchr (base_string
, ',');
11309 as_bad (_("bad register name `%s'"), base_string
);
11314 /* If there's an expression beginning the operand, parse it,
11315 assuming displacement_string_start and
11316 displacement_string_end are meaningful. */
11317 if (displacement_string_start
!= displacement_string_end
)
11319 if (!i386_displacement (displacement_string_start
,
11320 displacement_string_end
))
11324 /* Special case for (%dx) while doing input/output op. */
11326 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
11327 && i
.base_reg
->reg_type
.bitfield
.word
11328 && i
.index_reg
== 0
11329 && i
.log2_scale_factor
== 0
11330 && i
.seg
[i
.mem_operands
] == 0
11331 && !operand_type_check (i
.types
[this_operand
], disp
))
11333 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
11337 if (i386_index_check (operand_string
) == 0)
11339 i
.flags
[this_operand
] |= Operand_Mem
;
11340 if (i
.mem_operands
== 0)
11341 i
.memop1_string
= xstrdup (operand_string
);
11346 /* It's not a memory operand; argh! */
11347 as_bad (_("invalid char %s beginning operand %d `%s'"),
11348 output_invalid (*op_string
),
11353 return 1; /* Normal return. */
11356 /* Calculate the maximum variable size (i.e., excluding fr_fix)
11357 that an rs_machine_dependent frag may reach. */
11360 i386_frag_max_var (fragS
*frag
)
11362 /* The only relaxable frags are for jumps.
11363 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11364 gas_assert (frag
->fr_type
== rs_machine_dependent
);
11365 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
11368 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11370 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
11372 /* STT_GNU_IFUNC symbol must go through PLT. */
11373 if ((symbol_get_bfdsym (fr_symbol
)->flags
11374 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
11377 if (!S_IS_EXTERNAL (fr_symbol
))
11378 /* Symbol may be weak or local. */
11379 return !S_IS_WEAK (fr_symbol
);
11381 /* Global symbols with non-default visibility can't be preempted. */
11382 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
11385 if (fr_var
!= NO_RELOC
)
11386 switch ((enum bfd_reloc_code_real
) fr_var
)
11388 case BFD_RELOC_386_PLT32
:
11389 case BFD_RELOC_X86_64_PLT32
:
11390 /* Symbol with PLT relocation may be preempted. */
11396 /* Global symbols with default visibility in a shared library may be
11397 preempted by another definition. */
11402 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11403 Note also work for Skylake and Cascadelake.
11404 ---------------------------------------------------------------------
11405 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11406 | ------ | ----------- | ------- | -------- |
11408 | Jno | N | N | Y |
11409 | Jc/Jb | Y | N | Y |
11410 | Jae/Jnb | Y | N | Y |
11411 | Je/Jz | Y | Y | Y |
11412 | Jne/Jnz | Y | Y | Y |
11413 | Jna/Jbe | Y | N | Y |
11414 | Ja/Jnbe | Y | N | Y |
11416 | Jns | N | N | Y |
11417 | Jp/Jpe | N | N | Y |
11418 | Jnp/Jpo | N | N | Y |
11419 | Jl/Jnge | Y | Y | Y |
11420 | Jge/Jnl | Y | Y | Y |
11421 | Jle/Jng | Y | Y | Y |
11422 | Jg/Jnle | Y | Y | Y |
11423 --------------------------------------------------------------------- */
11425 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
11427 if (mf_cmp
== mf_cmp_alu_cmp
)
11428 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
11429 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
11430 if (mf_cmp
== mf_cmp_incdec
)
11431 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
11432 || mf_jcc
== mf_jcc_jle
);
11433 if (mf_cmp
== mf_cmp_test_and
)
11438 /* Return the next non-empty frag. */
11441 i386_next_non_empty_frag (fragS
*fragP
)
11443 /* There may be a frag with a ".fill 0" when there is no room in
11444 the current frag for frag_grow in output_insn. */
11445 for (fragP
= fragP
->fr_next
;
11447 && fragP
->fr_type
== rs_fill
11448 && fragP
->fr_fix
== 0);
11449 fragP
= fragP
->fr_next
)
11454 /* Return the next jcc frag after BRANCH_PADDING. */
11457 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
11459 fragS
*branch_fragP
;
11463 if (pad_fragP
->fr_type
== rs_machine_dependent
11464 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
11465 == BRANCH_PADDING
))
11467 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
11468 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
11470 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
11471 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
11472 pad_fragP
->tc_frag_data
.mf_type
))
11473 return branch_fragP
;
11479 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11482 i386_classify_machine_dependent_frag (fragS
*fragP
)
11486 fragS
*branch_fragP
;
11488 unsigned int max_prefix_length
;
11490 if (fragP
->tc_frag_data
.classified
)
11493 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11494 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11495 for (next_fragP
= fragP
;
11496 next_fragP
!= NULL
;
11497 next_fragP
= next_fragP
->fr_next
)
11499 next_fragP
->tc_frag_data
.classified
= 1;
11500 if (next_fragP
->fr_type
== rs_machine_dependent
)
11501 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
11503 case BRANCH_PADDING
:
11504 /* The BRANCH_PADDING frag must be followed by a branch
11506 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
11507 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11509 case FUSED_JCC_PADDING
:
11510 /* Check if this is a fused jcc:
11512 CMP like instruction
11516 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11517 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11518 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
11521 /* The BRANCH_PADDING frag is merged with the
11522 FUSED_JCC_PADDING frag. */
11523 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11524 /* CMP like instruction size. */
11525 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11526 frag_wane (pad_fragP
);
11527 /* Skip to branch_fragP. */
11528 next_fragP
= branch_fragP
;
11530 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11532 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11534 next_fragP
->fr_subtype
11535 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11536 next_fragP
->tc_frag_data
.max_bytes
11537 = next_fragP
->tc_frag_data
.max_prefix_length
;
11538 /* This will be updated in the BRANCH_PREFIX scan. */
11539 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11542 frag_wane (next_fragP
);
11547 /* Stop if there is no BRANCH_PREFIX. */
11548 if (!align_branch_prefix_size
)
11551 /* Scan for BRANCH_PREFIX. */
11552 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11554 if (fragP
->fr_type
!= rs_machine_dependent
11555 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11559 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11560 COND_JUMP_PREFIX. */
11561 max_prefix_length
= 0;
11562 for (next_fragP
= fragP
;
11563 next_fragP
!= NULL
;
11564 next_fragP
= next_fragP
->fr_next
)
11566 if (next_fragP
->fr_type
== rs_fill
)
11567 /* Skip rs_fill frags. */
11569 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11570 /* Stop for all other frags. */
11573 /* rs_machine_dependent frags. */
11574 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11577 /* Count BRANCH_PREFIX frags. */
11578 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11580 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11581 frag_wane (next_fragP
);
11585 += next_fragP
->tc_frag_data
.max_bytes
;
11587 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11589 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11590 == FUSED_JCC_PADDING
))
11592 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11593 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11597 /* Stop for other rs_machine_dependent frags. */
11601 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11603 /* Skip to the next frag. */
11604 fragP
= next_fragP
;
11608 /* Compute padding size for
11611 CMP like instruction
11613 COND_JUMP/UNCOND_JUMP
11618 COND_JUMP/UNCOND_JUMP
11622 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11624 unsigned int offset
, size
, padding_size
;
11625 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11627 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11629 address
= fragP
->fr_address
;
11630 address
+= fragP
->fr_fix
;
11632 /* CMP like instrunction size. */
11633 size
= fragP
->tc_frag_data
.cmp_size
;
11635 /* The base size of the branch frag. */
11636 size
+= branch_fragP
->fr_fix
;
11638 /* Add opcode and displacement bytes for the rs_machine_dependent
11640 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11641 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11643 /* Check if branch is within boundary and doesn't end at the last
11645 offset
= address
& ((1U << align_branch_power
) - 1);
11646 if ((offset
+ size
) >= (1U << align_branch_power
))
11647 /* Padding needed to avoid crossing boundary. */
11648 padding_size
= (1U << align_branch_power
) - offset
;
11650 /* No padding needed. */
11653 /* The return value may be saved in tc_frag_data.length which is
11655 if (!fits_in_unsigned_byte (padding_size
))
11658 return padding_size
;
11661 /* i386_generic_table_relax_frag()
11663 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11664 grow/shrink padding to align branch frags. Hand others to
11668 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11670 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11671 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11673 long padding_size
= i386_branch_padding_size (fragP
, 0);
11674 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11676 /* When the BRANCH_PREFIX frag is used, the computed address
11677 must match the actual address and there should be no padding. */
11678 if (fragP
->tc_frag_data
.padding_address
11679 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11683 /* Update the padding size. */
11685 fragP
->tc_frag_data
.length
= padding_size
;
11689 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11691 fragS
*padding_fragP
, *next_fragP
;
11692 long padding_size
, left_size
, last_size
;
11694 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11695 if (!padding_fragP
)
11696 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11697 return (fragP
->tc_frag_data
.length
11698 - fragP
->tc_frag_data
.last_length
);
11700 /* Compute the relative address of the padding frag in the very
11701 first time where the BRANCH_PREFIX frag sizes are zero. */
11702 if (!fragP
->tc_frag_data
.padding_address
)
11703 fragP
->tc_frag_data
.padding_address
11704 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11706 /* First update the last length from the previous interation. */
11707 left_size
= fragP
->tc_frag_data
.prefix_length
;
11708 for (next_fragP
= fragP
;
11709 next_fragP
!= padding_fragP
;
11710 next_fragP
= next_fragP
->fr_next
)
11711 if (next_fragP
->fr_type
== rs_machine_dependent
11712 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11717 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11721 if (max
> left_size
)
11726 next_fragP
->tc_frag_data
.last_length
= size
;
11730 next_fragP
->tc_frag_data
.last_length
= 0;
11733 /* Check the padding size for the padding frag. */
11734 padding_size
= i386_branch_padding_size
11735 (padding_fragP
, (fragP
->fr_address
11736 + fragP
->tc_frag_data
.padding_address
));
11738 last_size
= fragP
->tc_frag_data
.prefix_length
;
11739 /* Check if there is change from the last interation. */
11740 if (padding_size
== last_size
)
11742 /* Update the expected address of the padding frag. */
11743 padding_fragP
->tc_frag_data
.padding_address
11744 = (fragP
->fr_address
+ padding_size
11745 + fragP
->tc_frag_data
.padding_address
);
11749 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11751 /* No padding if there is no sufficient room. Clear the
11752 expected address of the padding frag. */
11753 padding_fragP
->tc_frag_data
.padding_address
= 0;
11757 /* Store the expected address of the padding frag. */
11758 padding_fragP
->tc_frag_data
.padding_address
11759 = (fragP
->fr_address
+ padding_size
11760 + fragP
->tc_frag_data
.padding_address
);
11762 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11764 /* Update the length for the current interation. */
11765 left_size
= padding_size
;
11766 for (next_fragP
= fragP
;
11767 next_fragP
!= padding_fragP
;
11768 next_fragP
= next_fragP
->fr_next
)
11769 if (next_fragP
->fr_type
== rs_machine_dependent
11770 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11775 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11779 if (max
> left_size
)
11784 next_fragP
->tc_frag_data
.length
= size
;
11788 next_fragP
->tc_frag_data
.length
= 0;
11791 return (fragP
->tc_frag_data
.length
11792 - fragP
->tc_frag_data
.last_length
);
11794 return relax_frag (segment
, fragP
, stretch
);
11797 /* md_estimate_size_before_relax()
11799 Called just before relax() for rs_machine_dependent frags. The x86
11800 assembler uses these frags to handle variable size jump
11803 Any symbol that is now undefined will not become defined.
11804 Return the correct fr_subtype in the frag.
11805 Return the initial "guess for variable size of frag" to caller.
11806 The guess is actually the growth beyond the fixed part. Whatever
11807 we do to grow the fixed or variable part contributes to our
11811 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11813 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11814 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11815 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11817 i386_classify_machine_dependent_frag (fragP
);
11818 return fragP
->tc_frag_data
.length
;
11821 /* We've already got fragP->fr_subtype right; all we have to do is
11822 check for un-relaxable symbols. On an ELF system, we can't relax
11823 an externally visible symbol, because it may be overridden by a
11825 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11826 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11828 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11831 #if defined (OBJ_COFF) && defined (TE_PE)
11832 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11833 && S_IS_WEAK (fragP
->fr_symbol
))
11837 /* Symbol is undefined in this segment, or we need to keep a
11838 reloc so that weak symbols can be overridden. */
11839 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11840 enum bfd_reloc_code_real reloc_type
;
11841 unsigned char *opcode
;
11844 if (fragP
->fr_var
!= NO_RELOC
)
11845 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11846 else if (size
== 2)
11847 reloc_type
= BFD_RELOC_16_PCREL
;
11848 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11849 else if (need_plt32_p (fragP
->fr_symbol
))
11850 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11853 reloc_type
= BFD_RELOC_32_PCREL
;
11855 old_fr_fix
= fragP
->fr_fix
;
11856 opcode
= (unsigned char *) fragP
->fr_opcode
;
11858 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11861 /* Make jmp (0xeb) a (d)word displacement jump. */
11863 fragP
->fr_fix
+= size
;
11864 fix_new (fragP
, old_fr_fix
, size
,
11866 fragP
->fr_offset
, 1,
11872 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11874 /* Negate the condition, and branch past an
11875 unconditional jump. */
11878 /* Insert an unconditional jump. */
11880 /* We added two extra opcode bytes, and have a two byte
11882 fragP
->fr_fix
+= 2 + 2;
11883 fix_new (fragP
, old_fr_fix
+ 2, 2,
11885 fragP
->fr_offset
, 1,
11889 /* Fall through. */
11892 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11896 fragP
->fr_fix
+= 1;
11897 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11899 fragP
->fr_offset
, 1,
11900 BFD_RELOC_8_PCREL
);
11901 fixP
->fx_signed
= 1;
11905 /* This changes the byte-displacement jump 0x7N
11906 to the (d)word-displacement jump 0x0f,0x8N. */
11907 opcode
[1] = opcode
[0] + 0x10;
11908 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11909 /* We've added an opcode byte. */
11910 fragP
->fr_fix
+= 1 + size
;
11911 fix_new (fragP
, old_fr_fix
+ 1, size
,
11913 fragP
->fr_offset
, 1,
11918 BAD_CASE (fragP
->fr_subtype
);
11922 return fragP
->fr_fix
- old_fr_fix
;
11925 /* Guess size depending on current relax state. Initially the relax
11926 state will correspond to a short jump and we return 1, because
11927 the variable part of the frag (the branch offset) is one byte
11928 long. However, we can relax a section more than once and in that
11929 case we must either set fr_subtype back to the unrelaxed state,
11930 or return the value for the appropriate branch. */
11931 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11934 /* Called after relax() is finished.
11936 In: Address of frag.
11937 fr_type == rs_machine_dependent.
11938 fr_subtype is what the address relaxed to.
11940 Out: Any fixSs and constants are set up.
11941 Caller will turn frag into a ".space 0". */
11944 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11947 unsigned char *opcode
;
11948 unsigned char *where_to_put_displacement
= NULL
;
11949 offsetT target_address
;
11950 offsetT opcode_address
;
11951 unsigned int extension
= 0;
11952 offsetT displacement_from_opcode_start
;
11954 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11955 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11956 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11958 /* Generate nop padding. */
11959 unsigned int size
= fragP
->tc_frag_data
.length
;
11962 if (size
> fragP
->tc_frag_data
.max_bytes
)
11968 const char *branch
= "branch";
11969 const char *prefix
= "";
11970 fragS
*padding_fragP
;
11971 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11974 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11975 switch (fragP
->tc_frag_data
.default_prefix
)
11980 case CS_PREFIX_OPCODE
:
11983 case DS_PREFIX_OPCODE
:
11986 case ES_PREFIX_OPCODE
:
11989 case FS_PREFIX_OPCODE
:
11992 case GS_PREFIX_OPCODE
:
11995 case SS_PREFIX_OPCODE
:
12000 msg
= _("%s:%u: add %d%s at 0x%llx to align "
12001 "%s within %d-byte boundary\n");
12003 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
12004 "align %s within %d-byte boundary\n");
12008 padding_fragP
= fragP
;
12009 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12010 "%s within %d-byte boundary\n");
12014 switch (padding_fragP
->tc_frag_data
.branch_type
)
12016 case align_branch_jcc
:
12019 case align_branch_fused
:
12020 branch
= "fused jcc";
12022 case align_branch_jmp
:
12025 case align_branch_call
:
12028 case align_branch_indirect
:
12029 branch
= "indiret branch";
12031 case align_branch_ret
:
12038 fprintf (stdout
, msg
,
12039 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
12040 (long long) fragP
->fr_address
, branch
,
12041 1 << align_branch_power
);
12043 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
12044 memset (fragP
->fr_opcode
,
12045 fragP
->tc_frag_data
.default_prefix
, size
);
12047 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
12049 fragP
->fr_fix
+= size
;
12054 opcode
= (unsigned char *) fragP
->fr_opcode
;
12056 /* Address we want to reach in file space. */
12057 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
12059 /* Address opcode resides at in file space. */
12060 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
12062 /* Displacement from opcode start to fill into instruction. */
12063 displacement_from_opcode_start
= target_address
- opcode_address
;
12065 if ((fragP
->fr_subtype
& BIG
) == 0)
12067 /* Don't have to change opcode. */
12068 extension
= 1; /* 1 opcode + 1 displacement */
12069 where_to_put_displacement
= &opcode
[1];
12073 if (no_cond_jump_promotion
12074 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
12075 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
12076 _("long jump required"));
12078 switch (fragP
->fr_subtype
)
12080 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
12081 extension
= 4; /* 1 opcode + 4 displacement */
12083 where_to_put_displacement
= &opcode
[1];
12086 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
12087 extension
= 2; /* 1 opcode + 2 displacement */
12089 where_to_put_displacement
= &opcode
[1];
12092 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
12093 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
12094 extension
= 5; /* 2 opcode + 4 displacement */
12095 opcode
[1] = opcode
[0] + 0x10;
12096 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12097 where_to_put_displacement
= &opcode
[2];
12100 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
12101 extension
= 3; /* 2 opcode + 2 displacement */
12102 opcode
[1] = opcode
[0] + 0x10;
12103 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
12104 where_to_put_displacement
= &opcode
[2];
12107 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
12112 where_to_put_displacement
= &opcode
[3];
12116 BAD_CASE (fragP
->fr_subtype
);
12121 /* If size if less then four we are sure that the operand fits,
12122 but if it's 4, then it could be that the displacement is larger
12124 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
12126 && ((addressT
) (displacement_from_opcode_start
- extension
12127 + ((addressT
) 1 << 31))
12128 > (((addressT
) 2 << 31) - 1)))
12130 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
12131 _("jump target out of range"));
12132 /* Make us emit 0. */
12133 displacement_from_opcode_start
= extension
;
12135 /* Now put displacement after opcode. */
12136 md_number_to_chars ((char *) where_to_put_displacement
,
12137 (valueT
) (displacement_from_opcode_start
- extension
),
12138 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
12139 fragP
->fr_fix
+= extension
;
12142 /* Apply a fixup (fixP) to segment data, once it has been determined
12143 by our caller that we have all the info we need to fix it up.
12145 Parameter valP is the pointer to the value of the bits.
12147 On the 386, immediates, displacements, and data pointers are all in
12148 the same (little-endian) format, so we don't need to care about which
12149 we are handling. */
12152 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12154 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
12155 valueT value
= *valP
;
12157 #if !defined (TE_Mach)
12158 if (fixP
->fx_pcrel
)
12160 switch (fixP
->fx_r_type
)
12166 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
12169 case BFD_RELOC_X86_64_32S
:
12170 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
12173 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
12176 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
12181 if (fixP
->fx_addsy
!= NULL
12182 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
12183 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
12184 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
12185 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
12186 && !use_rela_relocations
)
12188 /* This is a hack. There should be a better way to handle this.
12189 This covers for the fact that bfd_install_relocation will
12190 subtract the current location (for partial_inplace, PC relative
12191 relocations); see more below. */
12195 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
12198 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12203 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
12205 if ((sym_seg
== seg
12206 || (symbol_section_p (fixP
->fx_addsy
)
12207 && sym_seg
!= absolute_section
))
12208 && !generic_force_reloc (fixP
))
12210 /* Yes, we add the values in twice. This is because
12211 bfd_install_relocation subtracts them out again. I think
12212 bfd_install_relocation is broken, but I don't dare change
12214 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12218 #if defined (OBJ_COFF) && defined (TE_PE)
12219 /* For some reason, the PE format does not store a
12220 section address offset for a PC relative symbol. */
12221 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
12222 || S_IS_WEAK (fixP
->fx_addsy
))
12223 value
+= md_pcrel_from (fixP
);
12226 #if defined (OBJ_COFF) && defined (TE_PE)
12227 if (fixP
->fx_addsy
!= NULL
12228 && S_IS_WEAK (fixP
->fx_addsy
)
12229 /* PR 16858: Do not modify weak function references. */
12230 && ! fixP
->fx_pcrel
)
12232 #if !defined (TE_PEP)
12233 /* For x86 PE weak function symbols are neither PC-relative
12234 nor do they set S_IS_FUNCTION. So the only reliable way
12235 to detect them is to check the flags of their containing
12237 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
12238 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
12242 value
-= S_GET_VALUE (fixP
->fx_addsy
);
12246 /* Fix a few things - the dynamic linker expects certain values here,
12247 and we must not disappoint it. */
12248 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12249 if (IS_ELF
&& fixP
->fx_addsy
)
12250 switch (fixP
->fx_r_type
)
12252 case BFD_RELOC_386_PLT32
:
12253 case BFD_RELOC_X86_64_PLT32
:
12254 /* Make the jump instruction point to the address of the operand.
12255 At runtime we merely add the offset to the actual PLT entry.
12256 NB: Subtract the offset size only for jump instructions. */
12257 if (fixP
->fx_pcrel
)
12261 case BFD_RELOC_386_TLS_GD
:
12262 case BFD_RELOC_386_TLS_LDM
:
12263 case BFD_RELOC_386_TLS_IE_32
:
12264 case BFD_RELOC_386_TLS_IE
:
12265 case BFD_RELOC_386_TLS_GOTIE
:
12266 case BFD_RELOC_386_TLS_GOTDESC
:
12267 case BFD_RELOC_X86_64_TLSGD
:
12268 case BFD_RELOC_X86_64_TLSLD
:
12269 case BFD_RELOC_X86_64_GOTTPOFF
:
12270 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
12271 value
= 0; /* Fully resolved at runtime. No addend. */
12273 case BFD_RELOC_386_TLS_LE
:
12274 case BFD_RELOC_386_TLS_LDO_32
:
12275 case BFD_RELOC_386_TLS_LE_32
:
12276 case BFD_RELOC_X86_64_DTPOFF32
:
12277 case BFD_RELOC_X86_64_DTPOFF64
:
12278 case BFD_RELOC_X86_64_TPOFF32
:
12279 case BFD_RELOC_X86_64_TPOFF64
:
12280 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12283 case BFD_RELOC_386_TLS_DESC_CALL
:
12284 case BFD_RELOC_X86_64_TLSDESC_CALL
:
12285 value
= 0; /* Fully resolved at runtime. No addend. */
12286 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12290 case BFD_RELOC_VTABLE_INHERIT
:
12291 case BFD_RELOC_VTABLE_ENTRY
:
12298 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12300 #endif /* !defined (TE_Mach) */
12302 /* Are we finished with this relocation now? */
12303 if (fixP
->fx_addsy
== NULL
)
12305 #if defined (OBJ_COFF) && defined (TE_PE)
12306 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
12309 /* Remember value for tc_gen_reloc. */
12310 fixP
->fx_addnumber
= value
;
12311 /* Clear out the frag for now. */
12315 else if (use_rela_relocations
)
12317 fixP
->fx_no_overflow
= 1;
12318 /* Remember value for tc_gen_reloc. */
12319 fixP
->fx_addnumber
= value
;
12323 md_number_to_chars (p
, value
, fixP
->fx_size
);
12327 md_atof (int type
, char *litP
, int *sizeP
)
12329 /* This outputs the LITTLENUMs in REVERSE order;
12330 in accord with the bigendian 386. */
12331 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
12334 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
12337 output_invalid (int c
)
12340 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12343 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
12344 "(0x%x)", (unsigned char) c
);
12345 return output_invalid_buf
;
12348 /* Verify that @r can be used in the current context. */
12350 static bfd_boolean
check_register (const reg_entry
*r
)
12352 if (allow_pseudo_reg
)
12355 if (operand_type_all_zero (&r
->reg_type
))
12358 if ((r
->reg_type
.bitfield
.dword
12359 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
12360 || r
->reg_type
.bitfield
.class == RegCR
12361 || r
->reg_type
.bitfield
.class == RegDR
12362 || r
->reg_type
.bitfield
.class == RegTR
)
12363 && !cpu_arch_flags
.bitfield
.cpui386
)
12366 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
12369 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
12371 if (r
->reg_type
.bitfield
.zmmword
12372 || r
->reg_type
.bitfield
.class == RegMask
)
12375 if (!cpu_arch_flags
.bitfield
.cpuavx
)
12377 if (r
->reg_type
.bitfield
.ymmword
)
12380 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
12385 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
12388 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12389 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
12392 /* Upper 16 vector registers are only available with VREX in 64bit
12393 mode, and require EVEX encoding. */
12394 if (r
->reg_flags
& RegVRex
)
12396 if (!cpu_arch_flags
.bitfield
.cpuavx512f
12397 || flag_code
!= CODE_64BIT
)
12400 i
.vec_encoding
= vex_encoding_evex
;
12403 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
12404 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
12405 && flag_code
!= CODE_64BIT
)
12408 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
12415 /* REG_STRING starts *before* REGISTER_PREFIX. */
12417 static const reg_entry
*
12418 parse_real_register (char *reg_string
, char **end_op
)
12420 char *s
= reg_string
;
12422 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
12423 const reg_entry
*r
;
12425 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12426 if (*s
== REGISTER_PREFIX
)
12429 if (is_space_char (*s
))
12432 p
= reg_name_given
;
12433 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
12435 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
12436 return (const reg_entry
*) NULL
;
12440 /* For naked regs, make sure that we are not dealing with an identifier.
12441 This prevents confusing an identifier like `eax_var' with register
12443 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
12444 return (const reg_entry
*) NULL
;
12448 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
12450 /* Handle floating point regs, allowing spaces in the (i) part. */
12451 if (r
== i386_regtab
/* %st is first entry of table */)
12453 if (!cpu_arch_flags
.bitfield
.cpu8087
12454 && !cpu_arch_flags
.bitfield
.cpu287
12455 && !cpu_arch_flags
.bitfield
.cpu387
12456 && !allow_pseudo_reg
)
12457 return (const reg_entry
*) NULL
;
12459 if (is_space_char (*s
))
12464 if (is_space_char (*s
))
12466 if (*s
>= '0' && *s
<= '7')
12468 int fpr
= *s
- '0';
12470 if (is_space_char (*s
))
12475 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
12480 /* We have "%st(" then garbage. */
12481 return (const reg_entry
*) NULL
;
12485 return r
&& check_register (r
) ? r
: NULL
;
12488 /* REG_STRING starts *before* REGISTER_PREFIX. */
12490 static const reg_entry
*
12491 parse_register (char *reg_string
, char **end_op
)
12493 const reg_entry
*r
;
12495 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
12496 r
= parse_real_register (reg_string
, end_op
);
12501 char *save
= input_line_pointer
;
12505 input_line_pointer
= reg_string
;
12506 c
= get_symbol_name (®_string
);
12507 symbolP
= symbol_find (reg_string
);
12508 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
12510 const expressionS
*e
= symbol_get_value_expression (symbolP
);
12512 know (e
->X_op
== O_register
);
12513 know (e
->X_add_number
>= 0
12514 && (valueT
) e
->X_add_number
< i386_regtab_size
);
12515 r
= i386_regtab
+ e
->X_add_number
;
12516 if (!check_register (r
))
12518 as_bad (_("register '%s%s' cannot be used here"),
12519 register_prefix
, r
->reg_name
);
12522 *end_op
= input_line_pointer
;
12524 *input_line_pointer
= c
;
12525 input_line_pointer
= save
;
12531 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12533 const reg_entry
*r
;
12534 char *end
= input_line_pointer
;
12537 r
= parse_register (name
, &input_line_pointer
);
12538 if (r
&& end
<= input_line_pointer
)
12540 *nextcharP
= *input_line_pointer
;
12541 *input_line_pointer
= 0;
12544 e
->X_op
= O_register
;
12545 e
->X_add_number
= r
- i386_regtab
;
12548 e
->X_op
= O_illegal
;
12551 input_line_pointer
= end
;
12553 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12557 md_operand (expressionS
*e
)
12560 const reg_entry
*r
;
12562 switch (*input_line_pointer
)
12564 case REGISTER_PREFIX
:
12565 r
= parse_real_register (input_line_pointer
, &end
);
12568 e
->X_op
= O_register
;
12569 e
->X_add_number
= r
- i386_regtab
;
12570 input_line_pointer
= end
;
12575 gas_assert (intel_syntax
);
12576 end
= input_line_pointer
++;
12578 if (*input_line_pointer
== ']')
12580 ++input_line_pointer
;
12581 e
->X_op_symbol
= make_expr_symbol (e
);
12582 e
->X_add_symbol
= NULL
;
12583 e
->X_add_number
= 0;
12588 e
->X_op
= O_absent
;
12589 input_line_pointer
= end
;
12596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12597 const char *md_shortopts
= "kVQ:sqnO::";
12599 const char *md_shortopts
= "qnO::";
12602 #define OPTION_32 (OPTION_MD_BASE + 0)
12603 #define OPTION_64 (OPTION_MD_BASE + 1)
12604 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12605 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12606 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12607 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12608 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12609 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12610 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12611 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12612 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12613 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12614 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12615 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12616 #define OPTION_X32 (OPTION_MD_BASE + 14)
12617 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12618 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12619 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12620 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12621 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12622 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12623 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12624 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12625 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12626 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12627 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12628 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12629 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12630 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12631 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12632 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12633 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12634 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12635 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12637 struct option md_longopts
[] =
12639 {"32", no_argument
, NULL
, OPTION_32
},
12640 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12641 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12642 {"64", no_argument
, NULL
, OPTION_64
},
12644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12645 {"x32", no_argument
, NULL
, OPTION_X32
},
12646 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12647 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12649 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12650 {"march", required_argument
, NULL
, OPTION_MARCH
},
12651 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12652 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12653 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12654 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12655 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12656 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12657 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12658 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12659 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12660 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12661 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12662 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12663 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12664 # if defined (TE_PE) || defined (TE_PEP)
12665 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12667 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12668 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12669 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12670 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12671 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12672 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12673 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12674 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12675 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
12676 {"mlfence-before-indirect-branch", required_argument
, NULL
,
12677 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
12678 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
12679 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12680 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12681 {NULL
, no_argument
, NULL
, 0}
12683 size_t md_longopts_size
= sizeof (md_longopts
);
12686 md_parse_option (int c
, const char *arg
)
12689 char *arch
, *next
, *saved
, *type
;
12694 optimize_align_code
= 0;
12698 quiet_warnings
= 1;
12701 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12702 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12703 should be emitted or not. FIXME: Not implemented. */
12705 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12709 /* -V: SVR4 argument to print version ID. */
12711 print_version_id ();
12714 /* -k: Ignore for FreeBSD compatibility. */
12719 /* -s: On i386 Solaris, this tells the native assembler to use
12720 .stab instead of .stab.excl. We always use .stab anyhow. */
12723 case OPTION_MSHARED
:
12727 case OPTION_X86_USED_NOTE
:
12728 if (strcasecmp (arg
, "yes") == 0)
12730 else if (strcasecmp (arg
, "no") == 0)
12733 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12738 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12739 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12742 const char **list
, **l
;
12744 list
= bfd_target_list ();
12745 for (l
= list
; *l
!= NULL
; l
++)
12746 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12747 || strcmp (*l
, "coff-x86-64") == 0
12748 || strcmp (*l
, "pe-x86-64") == 0
12749 || strcmp (*l
, "pei-x86-64") == 0
12750 || strcmp (*l
, "mach-o-x86-64") == 0)
12752 default_arch
= "x86_64";
12756 as_fatal (_("no compiled in support for x86_64"));
12762 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12766 const char **list
, **l
;
12768 list
= bfd_target_list ();
12769 for (l
= list
; *l
!= NULL
; l
++)
12770 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12772 default_arch
= "x86_64:32";
12776 as_fatal (_("no compiled in support for 32bit x86_64"));
12780 as_fatal (_("32bit x86_64 is only supported for ELF"));
12785 default_arch
= "i386";
12788 case OPTION_DIVIDE
:
12789 #ifdef SVR4_COMMENT_CHARS
12794 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12796 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12800 i386_comment_chars
= n
;
12806 saved
= xstrdup (arg
);
12808 /* Allow -march=+nosse. */
12814 as_fatal (_("invalid -march= option: `%s'"), arg
);
12815 next
= strchr (arch
, '+');
12818 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12820 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12823 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12826 cpu_arch_name
= cpu_arch
[j
].name
;
12827 cpu_sub_arch_name
= NULL
;
12828 cpu_arch_flags
= cpu_arch
[j
].flags
;
12829 cpu_arch_isa
= cpu_arch
[j
].type
;
12830 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12831 if (!cpu_arch_tune_set
)
12833 cpu_arch_tune
= cpu_arch_isa
;
12834 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12838 else if (*cpu_arch
[j
].name
== '.'
12839 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12841 /* ISA extension. */
12842 i386_cpu_flags flags
;
12844 flags
= cpu_flags_or (cpu_arch_flags
,
12845 cpu_arch
[j
].flags
);
12847 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12849 if (cpu_sub_arch_name
)
12851 char *name
= cpu_sub_arch_name
;
12852 cpu_sub_arch_name
= concat (name
,
12854 (const char *) NULL
);
12858 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12859 cpu_arch_flags
= flags
;
12860 cpu_arch_isa_flags
= flags
;
12864 = cpu_flags_or (cpu_arch_isa_flags
,
12865 cpu_arch
[j
].flags
);
12870 if (j
>= ARRAY_SIZE (cpu_arch
))
12872 /* Disable an ISA extension. */
12873 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12874 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12876 i386_cpu_flags flags
;
12878 flags
= cpu_flags_and_not (cpu_arch_flags
,
12879 cpu_noarch
[j
].flags
);
12880 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12882 if (cpu_sub_arch_name
)
12884 char *name
= cpu_sub_arch_name
;
12885 cpu_sub_arch_name
= concat (arch
,
12886 (const char *) NULL
);
12890 cpu_sub_arch_name
= xstrdup (arch
);
12891 cpu_arch_flags
= flags
;
12892 cpu_arch_isa_flags
= flags
;
12897 if (j
>= ARRAY_SIZE (cpu_noarch
))
12898 j
= ARRAY_SIZE (cpu_arch
);
12901 if (j
>= ARRAY_SIZE (cpu_arch
))
12902 as_fatal (_("invalid -march= option: `%s'"), arg
);
12906 while (next
!= NULL
);
12912 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12913 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12915 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12917 cpu_arch_tune_set
= 1;
12918 cpu_arch_tune
= cpu_arch
[j
].type
;
12919 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12923 if (j
>= ARRAY_SIZE (cpu_arch
))
12924 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12927 case OPTION_MMNEMONIC
:
12928 if (strcasecmp (arg
, "att") == 0)
12929 intel_mnemonic
= 0;
12930 else if (strcasecmp (arg
, "intel") == 0)
12931 intel_mnemonic
= 1;
12933 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12936 case OPTION_MSYNTAX
:
12937 if (strcasecmp (arg
, "att") == 0)
12939 else if (strcasecmp (arg
, "intel") == 0)
12942 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12945 case OPTION_MINDEX_REG
:
12946 allow_index_reg
= 1;
12949 case OPTION_MNAKED_REG
:
12950 allow_naked_reg
= 1;
12953 case OPTION_MSSE2AVX
:
12957 case OPTION_MSSE_CHECK
:
12958 if (strcasecmp (arg
, "error") == 0)
12959 sse_check
= check_error
;
12960 else if (strcasecmp (arg
, "warning") == 0)
12961 sse_check
= check_warning
;
12962 else if (strcasecmp (arg
, "none") == 0)
12963 sse_check
= check_none
;
12965 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12968 case OPTION_MOPERAND_CHECK
:
12969 if (strcasecmp (arg
, "error") == 0)
12970 operand_check
= check_error
;
12971 else if (strcasecmp (arg
, "warning") == 0)
12972 operand_check
= check_warning
;
12973 else if (strcasecmp (arg
, "none") == 0)
12974 operand_check
= check_none
;
12976 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12979 case OPTION_MAVXSCALAR
:
12980 if (strcasecmp (arg
, "128") == 0)
12981 avxscalar
= vex128
;
12982 else if (strcasecmp (arg
, "256") == 0)
12983 avxscalar
= vex256
;
12985 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12988 case OPTION_MVEXWIG
:
12989 if (strcmp (arg
, "0") == 0)
12991 else if (strcmp (arg
, "1") == 0)
12994 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12997 case OPTION_MADD_BND_PREFIX
:
12998 add_bnd_prefix
= 1;
13001 case OPTION_MEVEXLIG
:
13002 if (strcmp (arg
, "128") == 0)
13003 evexlig
= evexl128
;
13004 else if (strcmp (arg
, "256") == 0)
13005 evexlig
= evexl256
;
13006 else if (strcmp (arg
, "512") == 0)
13007 evexlig
= evexl512
;
13009 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
13012 case OPTION_MEVEXRCIG
:
13013 if (strcmp (arg
, "rne") == 0)
13015 else if (strcmp (arg
, "rd") == 0)
13017 else if (strcmp (arg
, "ru") == 0)
13019 else if (strcmp (arg
, "rz") == 0)
13022 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
13025 case OPTION_MEVEXWIG
:
13026 if (strcmp (arg
, "0") == 0)
13028 else if (strcmp (arg
, "1") == 0)
13031 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
13034 # if defined (TE_PE) || defined (TE_PEP)
13035 case OPTION_MBIG_OBJ
:
13040 case OPTION_MOMIT_LOCK_PREFIX
:
13041 if (strcasecmp (arg
, "yes") == 0)
13042 omit_lock_prefix
= 1;
13043 else if (strcasecmp (arg
, "no") == 0)
13044 omit_lock_prefix
= 0;
13046 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
13049 case OPTION_MFENCE_AS_LOCK_ADD
:
13050 if (strcasecmp (arg
, "yes") == 0)
13052 else if (strcasecmp (arg
, "no") == 0)
13055 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
13058 case OPTION_MLFENCE_AFTER_LOAD
:
13059 if (strcasecmp (arg
, "yes") == 0)
13060 lfence_after_load
= 1;
13061 else if (strcasecmp (arg
, "no") == 0)
13062 lfence_after_load
= 0;
13064 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
13067 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
13068 if (strcasecmp (arg
, "all") == 0)
13070 lfence_before_indirect_branch
= lfence_branch_all
;
13071 if (lfence_before_ret
== lfence_before_ret_none
)
13072 lfence_before_ret
= lfence_before_ret_shl
;
13074 else if (strcasecmp (arg
, "memory") == 0)
13075 lfence_before_indirect_branch
= lfence_branch_memory
;
13076 else if (strcasecmp (arg
, "register") == 0)
13077 lfence_before_indirect_branch
= lfence_branch_register
;
13078 else if (strcasecmp (arg
, "none") == 0)
13079 lfence_before_indirect_branch
= lfence_branch_none
;
13081 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13085 case OPTION_MLFENCE_BEFORE_RET
:
13086 if (strcasecmp (arg
, "or") == 0)
13087 lfence_before_ret
= lfence_before_ret_or
;
13088 else if (strcasecmp (arg
, "not") == 0)
13089 lfence_before_ret
= lfence_before_ret_not
;
13090 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
13091 lfence_before_ret
= lfence_before_ret_shl
;
13092 else if (strcasecmp (arg
, "none") == 0)
13093 lfence_before_ret
= lfence_before_ret_none
;
13095 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13099 case OPTION_MRELAX_RELOCATIONS
:
13100 if (strcasecmp (arg
, "yes") == 0)
13101 generate_relax_relocations
= 1;
13102 else if (strcasecmp (arg
, "no") == 0)
13103 generate_relax_relocations
= 0;
13105 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
13108 case OPTION_MALIGN_BRANCH_BOUNDARY
:
13111 long int align
= strtoul (arg
, &end
, 0);
13116 align_branch_power
= 0;
13119 else if (align
>= 16)
13122 for (align_power
= 0;
13124 align
>>= 1, align_power
++)
13126 /* Limit alignment power to 31. */
13127 if (align
== 1 && align_power
< 32)
13129 align_branch_power
= align_power
;
13134 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
13138 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
13141 int align
= strtoul (arg
, &end
, 0);
13142 /* Some processors only support 5 prefixes. */
13143 if (*end
== '\0' && align
>= 0 && align
< 6)
13145 align_branch_prefix_size
= align
;
13148 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13153 case OPTION_MALIGN_BRANCH
:
13155 saved
= xstrdup (arg
);
13159 next
= strchr (type
, '+');
13162 if (strcasecmp (type
, "jcc") == 0)
13163 align_branch
|= align_branch_jcc_bit
;
13164 else if (strcasecmp (type
, "fused") == 0)
13165 align_branch
|= align_branch_fused_bit
;
13166 else if (strcasecmp (type
, "jmp") == 0)
13167 align_branch
|= align_branch_jmp_bit
;
13168 else if (strcasecmp (type
, "call") == 0)
13169 align_branch
|= align_branch_call_bit
;
13170 else if (strcasecmp (type
, "ret") == 0)
13171 align_branch
|= align_branch_ret_bit
;
13172 else if (strcasecmp (type
, "indirect") == 0)
13173 align_branch
|= align_branch_indirect_bit
;
13175 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
13178 while (next
!= NULL
);
13182 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
13183 align_branch_power
= 5;
13184 align_branch_prefix_size
= 5;
13185 align_branch
= (align_branch_jcc_bit
13186 | align_branch_fused_bit
13187 | align_branch_jmp_bit
);
13190 case OPTION_MAMD64
:
13194 case OPTION_MINTEL64
:
13202 /* Turn off -Os. */
13203 optimize_for_space
= 0;
13205 else if (*arg
== 's')
13207 optimize_for_space
= 1;
13208 /* Turn on all encoding optimizations. */
13209 optimize
= INT_MAX
;
13213 optimize
= atoi (arg
);
13214 /* Turn off -Os. */
13215 optimize_for_space
= 0;
13225 #define MESSAGE_TEMPLATE \
13229 output_message (FILE *stream
, char *p
, char *message
, char *start
,
13230 int *left_p
, const char *name
, int len
)
13232 int size
= sizeof (MESSAGE_TEMPLATE
);
13233 int left
= *left_p
;
13235 /* Reserve 2 spaces for ", " or ",\0" */
13238 /* Check if there is any room. */
13246 p
= mempcpy (p
, name
, len
);
13250 /* Output the current message now and start a new one. */
13253 fprintf (stream
, "%s\n", message
);
13255 left
= size
- (start
- message
) - len
- 2;
13257 gas_assert (left
>= 0);
13259 p
= mempcpy (p
, name
, len
);
13267 show_arch (FILE *stream
, int ext
, int check
)
13269 static char message
[] = MESSAGE_TEMPLATE
;
13270 char *start
= message
+ 27;
13272 int size
= sizeof (MESSAGE_TEMPLATE
);
13279 left
= size
- (start
- message
);
13280 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
13282 /* Should it be skipped? */
13283 if (cpu_arch
[j
].skip
)
13286 name
= cpu_arch
[j
].name
;
13287 len
= cpu_arch
[j
].len
;
13290 /* It is an extension. Skip if we aren't asked to show it. */
13301 /* It is an processor. Skip if we show only extension. */
13304 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
13306 /* It is an impossible processor - skip. */
13310 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
13313 /* Display disabled extensions. */
13315 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
13317 name
= cpu_noarch
[j
].name
;
13318 len
= cpu_noarch
[j
].len
;
13319 p
= output_message (stream
, p
, message
, start
, &left
, name
,
13324 fprintf (stream
, "%s\n", message
);
13328 md_show_usage (FILE *stream
)
13330 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13331 fprintf (stream
, _("\
13332 -Qy, -Qn ignored\n\
13333 -V print assembler version number\n\
13336 fprintf (stream
, _("\
13337 -n Do not optimize code alignment\n\
13338 -q quieten some warnings\n"));
13339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13340 fprintf (stream
, _("\
13343 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13344 || defined (TE_PE) || defined (TE_PEP))
13345 fprintf (stream
, _("\
13346 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13348 #ifdef SVR4_COMMENT_CHARS
13349 fprintf (stream
, _("\
13350 --divide do not treat `/' as a comment character\n"));
13352 fprintf (stream
, _("\
13353 --divide ignored\n"));
13355 fprintf (stream
, _("\
13356 -march=CPU[,+EXTENSION...]\n\
13357 generate code for CPU and EXTENSION, CPU is one of:\n"));
13358 show_arch (stream
, 0, 1);
13359 fprintf (stream
, _("\
13360 EXTENSION is combination of:\n"));
13361 show_arch (stream
, 1, 0);
13362 fprintf (stream
, _("\
13363 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13364 show_arch (stream
, 0, 0);
13365 fprintf (stream
, _("\
13366 -msse2avx encode SSE instructions with VEX prefix\n"));
13367 fprintf (stream
, _("\
13368 -msse-check=[none|error|warning] (default: warning)\n\
13369 check SSE instructions\n"));
13370 fprintf (stream
, _("\
13371 -moperand-check=[none|error|warning] (default: warning)\n\
13372 check operand combinations for validity\n"));
13373 fprintf (stream
, _("\
13374 -mavxscalar=[128|256] (default: 128)\n\
13375 encode scalar AVX instructions with specific vector\n\
13377 fprintf (stream
, _("\
13378 -mvexwig=[0|1] (default: 0)\n\
13379 encode VEX instructions with specific VEX.W value\n\
13380 for VEX.W bit ignored instructions\n"));
13381 fprintf (stream
, _("\
13382 -mevexlig=[128|256|512] (default: 128)\n\
13383 encode scalar EVEX instructions with specific vector\n\
13385 fprintf (stream
, _("\
13386 -mevexwig=[0|1] (default: 0)\n\
13387 encode EVEX instructions with specific EVEX.W value\n\
13388 for EVEX.W bit ignored instructions\n"));
13389 fprintf (stream
, _("\
13390 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13391 encode EVEX instructions with specific EVEX.RC value\n\
13392 for SAE-only ignored instructions\n"));
13393 fprintf (stream
, _("\
13394 -mmnemonic=[att|intel] "));
13395 if (SYSV386_COMPAT
)
13396 fprintf (stream
, _("(default: att)\n"));
13398 fprintf (stream
, _("(default: intel)\n"));
13399 fprintf (stream
, _("\
13400 use AT&T/Intel mnemonic\n"));
13401 fprintf (stream
, _("\
13402 -msyntax=[att|intel] (default: att)\n\
13403 use AT&T/Intel syntax\n"));
13404 fprintf (stream
, _("\
13405 -mindex-reg support pseudo index registers\n"));
13406 fprintf (stream
, _("\
13407 -mnaked-reg don't require `%%' prefix for registers\n"));
13408 fprintf (stream
, _("\
13409 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13411 fprintf (stream
, _("\
13412 -mshared disable branch optimization for shared code\n"));
13413 fprintf (stream
, _("\
13414 -mx86-used-note=[no|yes] "));
13415 if (DEFAULT_X86_USED_NOTE
)
13416 fprintf (stream
, _("(default: yes)\n"));
13418 fprintf (stream
, _("(default: no)\n"));
13419 fprintf (stream
, _("\
13420 generate x86 used ISA and feature properties\n"));
13422 #if defined (TE_PE) || defined (TE_PEP)
13423 fprintf (stream
, _("\
13424 -mbig-obj generate big object files\n"));
13426 fprintf (stream
, _("\
13427 -momit-lock-prefix=[no|yes] (default: no)\n\
13428 strip all lock prefixes\n"));
13429 fprintf (stream
, _("\
13430 -mfence-as-lock-add=[no|yes] (default: no)\n\
13431 encode lfence, mfence and sfence as\n\
13432 lock addl $0x0, (%%{re}sp)\n"));
13433 fprintf (stream
, _("\
13434 -mrelax-relocations=[no|yes] "));
13435 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
13436 fprintf (stream
, _("(default: yes)\n"));
13438 fprintf (stream
, _("(default: no)\n"));
13439 fprintf (stream
, _("\
13440 generate relax relocations\n"));
13441 fprintf (stream
, _("\
13442 -malign-branch-boundary=NUM (default: 0)\n\
13443 align branches within NUM byte boundary\n"));
13444 fprintf (stream
, _("\
13445 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13446 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13448 specify types of branches to align\n"));
13449 fprintf (stream
, _("\
13450 -malign-branch-prefix-size=NUM (default: 5)\n\
13451 align branches with NUM prefixes per instruction\n"));
13452 fprintf (stream
, _("\
13453 -mbranches-within-32B-boundaries\n\
13454 align branches within 32 byte boundary\n"));
13455 fprintf (stream
, _("\
13456 -mlfence-after-load=[no|yes] (default: no)\n\
13457 generate lfence after load\n"));
13458 fprintf (stream
, _("\
13459 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13460 generate lfence before indirect near branch\n"));
13461 fprintf (stream
, _("\
13462 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13463 generate lfence before ret\n"));
13464 fprintf (stream
, _("\
13465 -mamd64 accept only AMD64 ISA [default]\n"));
13466 fprintf (stream
, _("\
13467 -mintel64 accept only Intel64 ISA\n"));
13470 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13471 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13472 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13474 /* Pick the target format to use. */
13477 i386_target_format (void)
13479 if (!strncmp (default_arch
, "x86_64", 6))
13481 update_code_flag (CODE_64BIT
, 1);
13482 if (default_arch
[6] == '\0')
13483 x86_elf_abi
= X86_64_ABI
;
13485 x86_elf_abi
= X86_64_X32_ABI
;
13487 else if (!strcmp (default_arch
, "i386"))
13488 update_code_flag (CODE_32BIT
, 1);
13489 else if (!strcmp (default_arch
, "iamcu"))
13491 update_code_flag (CODE_32BIT
, 1);
13492 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
13494 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
13495 cpu_arch_name
= "iamcu";
13496 cpu_sub_arch_name
= NULL
;
13497 cpu_arch_flags
= iamcu_flags
;
13498 cpu_arch_isa
= PROCESSOR_IAMCU
;
13499 cpu_arch_isa_flags
= iamcu_flags
;
13500 if (!cpu_arch_tune_set
)
13502 cpu_arch_tune
= cpu_arch_isa
;
13503 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
13506 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
13507 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13511 as_fatal (_("unknown architecture"));
13513 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
13514 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13515 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
13516 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
13518 switch (OUTPUT_FLAVOR
)
13520 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13521 case bfd_target_aout_flavour
:
13522 return AOUT_TARGET_FORMAT
;
13524 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13525 # if defined (TE_PE) || defined (TE_PEP)
13526 case bfd_target_coff_flavour
:
13527 if (flag_code
== CODE_64BIT
)
13528 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
13530 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
13531 # elif defined (TE_GO32)
13532 case bfd_target_coff_flavour
:
13533 return "coff-go32";
13535 case bfd_target_coff_flavour
:
13536 return "coff-i386";
13539 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13540 case bfd_target_elf_flavour
:
13542 const char *format
;
13544 switch (x86_elf_abi
)
13547 format
= ELF_TARGET_FORMAT
;
13549 tls_get_addr
= "___tls_get_addr";
13553 use_rela_relocations
= 1;
13556 tls_get_addr
= "__tls_get_addr";
13558 format
= ELF_TARGET_FORMAT64
;
13560 case X86_64_X32_ABI
:
13561 use_rela_relocations
= 1;
13564 tls_get_addr
= "__tls_get_addr";
13566 disallow_64bit_reloc
= 1;
13567 format
= ELF_TARGET_FORMAT32
;
13570 if (cpu_arch_isa
== PROCESSOR_L1OM
)
13572 if (x86_elf_abi
!= X86_64_ABI
)
13573 as_fatal (_("Intel L1OM is 64bit only"));
13574 return ELF_TARGET_L1OM_FORMAT
;
13576 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
13578 if (x86_elf_abi
!= X86_64_ABI
)
13579 as_fatal (_("Intel K1OM is 64bit only"));
13580 return ELF_TARGET_K1OM_FORMAT
;
13582 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13584 if (x86_elf_abi
!= I386_ABI
)
13585 as_fatal (_("Intel MCU is 32bit only"));
13586 return ELF_TARGET_IAMCU_FORMAT
;
13592 #if defined (OBJ_MACH_O)
13593 case bfd_target_mach_o_flavour
:
13594 if (flag_code
== CODE_64BIT
)
13596 use_rela_relocations
= 1;
13598 return "mach-o-x86-64";
13601 return "mach-o-i386";
13609 #endif /* OBJ_MAYBE_ more than one */
13612 md_undefined_symbol (char *name
)
13614 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13615 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13616 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13617 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13621 if (symbol_find (name
))
13622 as_bad (_("GOT already in symbol table"));
13623 GOT_symbol
= symbol_new (name
, undefined_section
,
13624 (valueT
) 0, &zero_address_frag
);
13631 /* Round up a section size to the appropriate boundary. */
13634 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13636 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13637 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13639 /* For a.out, force the section size to be aligned. If we don't do
13640 this, BFD will align it for us, but it will not write out the
13641 final bytes of the section. This may be a bug in BFD, but it is
13642 easier to fix it here since that is how the other a.out targets
13646 align
= bfd_section_alignment (segment
);
13647 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13654 /* On the i386, PC-relative offsets are relative to the start of the
13655 next instruction. That is, the address of the offset, plus its
13656 size, since the offset is always the last part of the insn. */
13659 md_pcrel_from (fixS
*fixP
)
13661 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13667 s_bss (int ignore ATTRIBUTE_UNUSED
)
13671 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13673 obj_elf_section_change_hook ();
13675 temp
= get_absolute_expression ();
13676 subseg_set (bss_section
, (subsegT
) temp
);
13677 demand_empty_rest_of_line ();
13682 /* Remember constant directive. */
13685 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13687 if (last_insn
.kind
!= last_insn_directive
13688 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13690 last_insn
.seg
= now_seg
;
13691 last_insn
.kind
= last_insn_directive
;
13692 last_insn
.name
= "constant directive";
13693 last_insn
.file
= as_where (&last_insn
.line
);
13694 if (lfence_before_ret
!= lfence_before_ret_none
)
13696 if (lfence_before_indirect_branch
!= lfence_branch_none
)
13697 as_warn (_("constant directive skips -mlfence-before-ret "
13698 "and -mlfence-before-indirect-branch"));
13700 as_warn (_("constant directive skips -mlfence-before-ret"));
13702 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
13703 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13708 i386_validate_fix (fixS
*fixp
)
13710 if (fixp
->fx_subsy
)
13712 if (fixp
->fx_subsy
== GOT_symbol
)
13714 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13718 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13719 if (fixp
->fx_tcbit2
)
13720 fixp
->fx_r_type
= (fixp
->fx_tcbit
13721 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13722 : BFD_RELOC_X86_64_GOTPCRELX
);
13725 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13730 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13732 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13734 fixp
->fx_subsy
= 0;
13737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13738 else if (!object_64bit
)
13740 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13741 && fixp
->fx_tcbit2
)
13742 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13748 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13751 bfd_reloc_code_real_type code
;
13753 switch (fixp
->fx_r_type
)
13755 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13756 case BFD_RELOC_SIZE32
:
13757 case BFD_RELOC_SIZE64
:
13758 if (S_IS_DEFINED (fixp
->fx_addsy
)
13759 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13761 /* Resolve size relocation against local symbol to size of
13762 the symbol plus addend. */
13763 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13764 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13765 && !fits_in_unsigned_long (value
))
13766 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13767 _("symbol size computation overflow"));
13768 fixp
->fx_addsy
= NULL
;
13769 fixp
->fx_subsy
= NULL
;
13770 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13774 /* Fall through. */
13776 case BFD_RELOC_X86_64_PLT32
:
13777 case BFD_RELOC_X86_64_GOT32
:
13778 case BFD_RELOC_X86_64_GOTPCREL
:
13779 case BFD_RELOC_X86_64_GOTPCRELX
:
13780 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13781 case BFD_RELOC_386_PLT32
:
13782 case BFD_RELOC_386_GOT32
:
13783 case BFD_RELOC_386_GOT32X
:
13784 case BFD_RELOC_386_GOTOFF
:
13785 case BFD_RELOC_386_GOTPC
:
13786 case BFD_RELOC_386_TLS_GD
:
13787 case BFD_RELOC_386_TLS_LDM
:
13788 case BFD_RELOC_386_TLS_LDO_32
:
13789 case BFD_RELOC_386_TLS_IE_32
:
13790 case BFD_RELOC_386_TLS_IE
:
13791 case BFD_RELOC_386_TLS_GOTIE
:
13792 case BFD_RELOC_386_TLS_LE_32
:
13793 case BFD_RELOC_386_TLS_LE
:
13794 case BFD_RELOC_386_TLS_GOTDESC
:
13795 case BFD_RELOC_386_TLS_DESC_CALL
:
13796 case BFD_RELOC_X86_64_TLSGD
:
13797 case BFD_RELOC_X86_64_TLSLD
:
13798 case BFD_RELOC_X86_64_DTPOFF32
:
13799 case BFD_RELOC_X86_64_DTPOFF64
:
13800 case BFD_RELOC_X86_64_GOTTPOFF
:
13801 case BFD_RELOC_X86_64_TPOFF32
:
13802 case BFD_RELOC_X86_64_TPOFF64
:
13803 case BFD_RELOC_X86_64_GOTOFF64
:
13804 case BFD_RELOC_X86_64_GOTPC32
:
13805 case BFD_RELOC_X86_64_GOT64
:
13806 case BFD_RELOC_X86_64_GOTPCREL64
:
13807 case BFD_RELOC_X86_64_GOTPC64
:
13808 case BFD_RELOC_X86_64_GOTPLT64
:
13809 case BFD_RELOC_X86_64_PLTOFF64
:
13810 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13811 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13812 case BFD_RELOC_RVA
:
13813 case BFD_RELOC_VTABLE_ENTRY
:
13814 case BFD_RELOC_VTABLE_INHERIT
:
13816 case BFD_RELOC_32_SECREL
:
13818 code
= fixp
->fx_r_type
;
13820 case BFD_RELOC_X86_64_32S
:
13821 if (!fixp
->fx_pcrel
)
13823 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13824 code
= fixp
->fx_r_type
;
13827 /* Fall through. */
13829 if (fixp
->fx_pcrel
)
13831 switch (fixp
->fx_size
)
13834 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13835 _("can not do %d byte pc-relative relocation"),
13837 code
= BFD_RELOC_32_PCREL
;
13839 case 1: code
= BFD_RELOC_8_PCREL
; break;
13840 case 2: code
= BFD_RELOC_16_PCREL
; break;
13841 case 4: code
= BFD_RELOC_32_PCREL
; break;
13843 case 8: code
= BFD_RELOC_64_PCREL
; break;
13849 switch (fixp
->fx_size
)
13852 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13853 _("can not do %d byte relocation"),
13855 code
= BFD_RELOC_32
;
13857 case 1: code
= BFD_RELOC_8
; break;
13858 case 2: code
= BFD_RELOC_16
; break;
13859 case 4: code
= BFD_RELOC_32
; break;
13861 case 8: code
= BFD_RELOC_64
; break;
13868 if ((code
== BFD_RELOC_32
13869 || code
== BFD_RELOC_32_PCREL
13870 || code
== BFD_RELOC_X86_64_32S
)
13872 && fixp
->fx_addsy
== GOT_symbol
)
13875 code
= BFD_RELOC_386_GOTPC
;
13877 code
= BFD_RELOC_X86_64_GOTPC32
;
13879 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13881 && fixp
->fx_addsy
== GOT_symbol
)
13883 code
= BFD_RELOC_X86_64_GOTPC64
;
13886 rel
= XNEW (arelent
);
13887 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13888 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13890 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13892 if (!use_rela_relocations
)
13894 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13895 vtable entry to be used in the relocation's section offset. */
13896 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13897 rel
->address
= fixp
->fx_offset
;
13898 #if defined (OBJ_COFF) && defined (TE_PE)
13899 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13900 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13905 /* Use the rela in 64bit mode. */
13908 if (disallow_64bit_reloc
)
13911 case BFD_RELOC_X86_64_DTPOFF64
:
13912 case BFD_RELOC_X86_64_TPOFF64
:
13913 case BFD_RELOC_64_PCREL
:
13914 case BFD_RELOC_X86_64_GOTOFF64
:
13915 case BFD_RELOC_X86_64_GOT64
:
13916 case BFD_RELOC_X86_64_GOTPCREL64
:
13917 case BFD_RELOC_X86_64_GOTPC64
:
13918 case BFD_RELOC_X86_64_GOTPLT64
:
13919 case BFD_RELOC_X86_64_PLTOFF64
:
13920 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13921 _("cannot represent relocation type %s in x32 mode"),
13922 bfd_get_reloc_code_name (code
));
13928 if (!fixp
->fx_pcrel
)
13929 rel
->addend
= fixp
->fx_offset
;
13933 case BFD_RELOC_X86_64_PLT32
:
13934 case BFD_RELOC_X86_64_GOT32
:
13935 case BFD_RELOC_X86_64_GOTPCREL
:
13936 case BFD_RELOC_X86_64_GOTPCRELX
:
13937 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13938 case BFD_RELOC_X86_64_TLSGD
:
13939 case BFD_RELOC_X86_64_TLSLD
:
13940 case BFD_RELOC_X86_64_GOTTPOFF
:
13941 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13942 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13943 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13946 rel
->addend
= (section
->vma
13948 + fixp
->fx_addnumber
13949 + md_pcrel_from (fixp
));
13954 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13955 if (rel
->howto
== NULL
)
13957 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13958 _("cannot represent relocation type %s"),
13959 bfd_get_reloc_code_name (code
));
13960 /* Set howto to a garbage value so that we can keep going. */
13961 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13962 gas_assert (rel
->howto
!= NULL
);
13968 #include "tc-i386-intel.c"
13971 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13973 int saved_naked_reg
;
13974 char saved_register_dot
;
13976 saved_naked_reg
= allow_naked_reg
;
13977 allow_naked_reg
= 1;
13978 saved_register_dot
= register_chars
['.'];
13979 register_chars
['.'] = '.';
13980 allow_pseudo_reg
= 1;
13981 expression_and_evaluate (exp
);
13982 allow_pseudo_reg
= 0;
13983 register_chars
['.'] = saved_register_dot
;
13984 allow_naked_reg
= saved_naked_reg
;
13986 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13988 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13990 exp
->X_op
= O_constant
;
13991 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13992 .dw2_regnum
[flag_code
>> 1];
13995 exp
->X_op
= O_illegal
;
14000 tc_x86_frame_initial_instructions (void)
14002 static unsigned int sp_regno
[2];
14004 if (!sp_regno
[flag_code
>> 1])
14006 char *saved_input
= input_line_pointer
;
14007 char sp
[][4] = {"esp", "rsp"};
14010 input_line_pointer
= sp
[flag_code
>> 1];
14011 tc_x86_parse_to_dw2regnum (&exp
);
14012 gas_assert (exp
.X_op
== O_constant
);
14013 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
14014 input_line_pointer
= saved_input
;
14017 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
14018 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
14022 x86_dwarf2_addr_size (void)
14024 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14025 if (x86_elf_abi
== X86_64_X32_ABI
)
14028 return bfd_arch_bits_per_address (stdoutput
) / 8;
14032 i386_elf_section_type (const char *str
, size_t len
)
14034 if (flag_code
== CODE_64BIT
14035 && len
== sizeof ("unwind") - 1
14036 && strncmp (str
, "unwind", 6) == 0)
14037 return SHT_X86_64_UNWIND
;
14044 i386_solaris_fix_up_eh_frame (segT sec
)
14046 if (flag_code
== CODE_64BIT
)
14047 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
14053 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
14057 exp
.X_op
= O_secrel
;
14058 exp
.X_add_symbol
= symbol
;
14059 exp
.X_add_number
= 0;
14060 emit_expr (&exp
, size
);
14064 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14065 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14068 x86_64_section_letter (int letter
, const char **ptr_msg
)
14070 if (flag_code
== CODE_64BIT
)
14073 return SHF_X86_64_LARGE
;
14075 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14078 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
14083 x86_64_section_word (char *str
, size_t len
)
14085 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
14086 return SHF_X86_64_LARGE
;
14092 handle_large_common (int small ATTRIBUTE_UNUSED
)
14094 if (flag_code
!= CODE_64BIT
)
14096 s_comm_internal (0, elf_common_parse
);
14097 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14101 static segT lbss_section
;
14102 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
14103 asection
*saved_bss_section
= bss_section
;
14105 if (lbss_section
== NULL
)
14107 flagword applicable
;
14108 segT seg
= now_seg
;
14109 subsegT subseg
= now_subseg
;
14111 /* The .lbss section is for local .largecomm symbols. */
14112 lbss_section
= subseg_new (".lbss", 0);
14113 applicable
= bfd_applicable_section_flags (stdoutput
);
14114 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
14115 seg_info (lbss_section
)->bss
= 1;
14117 subseg_set (seg
, subseg
);
14120 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
14121 bss_section
= lbss_section
;
14123 s_comm_internal (0, elf_common_parse
);
14125 elf_com_section_ptr
= saved_com_section_ptr
;
14126 bss_section
= saved_bss_section
;
14129 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */