1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 /* Only one of NOTRACK_PREFIX and SEG_PREFIX can be used at the same
71 #define NOTRACK_PREFIX 6
72 #define REX_PREFIX 7 /* must come last. */
73 #define MAX_PREFIXES 8 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 #define ZMMWORD_MNEM_SUFFIX 'z'
90 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94 #define END_OF_INSN '\0'
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
105 const insn_template
*start
;
106 const insn_template
*end
;
110 /* 386 operand encoding bytes: see 386 book for details of this. */
113 unsigned int regmem
; /* codes register or memory operand */
114 unsigned int reg
; /* codes register operand (or extended opcode) */
115 unsigned int mode
; /* how to interpret regmem & reg */
119 /* x86-64 extension prefix. */
120 typedef int rex_byte
;
122 /* 386 opcode byte to code indirect addressing. */
131 /* x86 arch names, types and features */
134 const char *name
; /* arch name */
135 unsigned int len
; /* arch string length */
136 enum processor_type type
; /* arch type */
137 i386_cpu_flags flags
; /* cpu feature flags */
138 unsigned int skip
; /* show_arch should skip this. */
142 /* Used to turn off indicated flags. */
145 const char *name
; /* arch name */
146 unsigned int len
; /* arch string length */
147 i386_cpu_flags flags
; /* cpu feature flags */
151 static void update_code_flag (int, int);
152 static void set_code_flag (int);
153 static void set_16bit_gcc_code_flag (int);
154 static void set_intel_syntax (int);
155 static void set_intel_mnemonic (int);
156 static void set_allow_index_reg (int);
157 static void set_check (int);
158 static void set_cpu_arch (int);
160 static void pe_directive_secrel (int);
162 static void signed_cons (int);
163 static char *output_invalid (int c
);
164 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
166 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
168 static int i386_att_operand (char *);
169 static int i386_intel_operand (char *, int);
170 static int i386_intel_simplify (expressionS
*);
171 static int i386_intel_parse_name (const char *, expressionS
*);
172 static const reg_entry
*parse_register (char *, char **);
173 static char *parse_insn (char *, char *);
174 static char *parse_operands (char *, const char *);
175 static void swap_operands (void);
176 static void swap_2_operands (int, int);
177 static void optimize_imm (void);
178 static void optimize_disp (void);
179 static const insn_template
*match_template (char);
180 static int check_string (void);
181 static int process_suffix (void);
182 static int check_byte_reg (void);
183 static int check_long_reg (void);
184 static int check_qword_reg (void);
185 static int check_word_reg (void);
186 static int finalize_imm (void);
187 static int process_operands (void);
188 static const seg_entry
*build_modrm_byte (void);
189 static void output_insn (void);
190 static void output_imm (fragS
*, offsetT
);
191 static void output_disp (fragS
*, offsetT
);
193 static void s_bss (int);
195 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
196 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
199 static const char *default_arch
= DEFAULT_ARCH
;
201 /* This struct describes rounding control and SAE in the instruction. */
215 static struct RC_Operation rc_op
;
217 /* The struct describes masking, applied to OPERAND in the instruction.
218 MASK is a pointer to the corresponding mask register. ZEROING tells
219 whether merging or zeroing mask is used. */
220 struct Mask_Operation
222 const reg_entry
*mask
;
223 unsigned int zeroing
;
224 /* The operand where this operation is associated. */
228 static struct Mask_Operation mask_op
;
230 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
232 struct Broadcast_Operation
234 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
237 /* Index of broadcasted operand. */
241 static struct Broadcast_Operation broadcast_op
;
246 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
247 unsigned char bytes
[4];
249 /* Destination or source register specifier. */
250 const reg_entry
*register_specifier
;
253 /* 'md_assemble ()' gathers together information and puts it into a
260 const reg_entry
*regs
;
265 operand_size_mismatch
,
266 operand_type_mismatch
,
267 register_type_mismatch
,
268 number_of_operands_mismatch
,
269 invalid_instruction_suffix
,
272 unsupported_with_intel_mnemonic
,
275 invalid_vsib_address
,
276 invalid_vector_register_set
,
277 unsupported_vector_index_register
,
278 unsupported_broadcast
,
279 broadcast_not_on_src_operand
,
282 mask_not_on_destination
,
285 rc_sae_operand_not_last_imm
,
286 invalid_register_operand
,
292 /* TM holds the template for the insn were currently assembling. */
295 /* SUFFIX holds the instruction size suffix for byte, word, dword
296 or qword, if given. */
299 /* OPERANDS gives the number of given operands. */
300 unsigned int operands
;
302 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
303 of given register, displacement, memory operands and immediate
305 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
307 /* TYPES [i] is the type (see above #defines) which tells us how to
308 use OP[i] for the corresponding operand. */
309 i386_operand_type types
[MAX_OPERANDS
];
311 /* Displacement expression, immediate expression, or register for each
313 union i386_op op
[MAX_OPERANDS
];
315 /* Flags for operands. */
316 unsigned int flags
[MAX_OPERANDS
];
317 #define Operand_PCrel 1
319 /* Relocation type for operand */
320 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
322 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
323 the base index byte below. */
324 const reg_entry
*base_reg
;
325 const reg_entry
*index_reg
;
326 unsigned int log2_scale_factor
;
328 /* SEG gives the seg_entries of this insn. They are zero unless
329 explicit segment overrides are given. */
330 const seg_entry
*seg
[2];
332 /* Copied first memory operand string, for re-checking. */
335 /* PREFIX holds all the given prefix opcodes (usually null).
336 PREFIXES is the number of prefix opcodes. */
337 unsigned int prefixes
;
338 unsigned char prefix
[MAX_PREFIXES
];
340 /* RM and SIB are the modrm byte and the sib byte where the
341 addressing modes of this insn are encoded. */
348 /* Masking attributes. */
349 struct Mask_Operation
*mask
;
351 /* Rounding control and SAE attributes. */
352 struct RC_Operation
*rounding
;
354 /* Broadcasting attributes. */
355 struct Broadcast_Operation
*broadcast
;
357 /* Compressed disp8*N attribute. */
358 unsigned int memshift
;
360 /* Prefer load or store in encoding. */
363 dir_encoding_default
= 0,
368 /* Prefer 8bit or 32bit displacement in encoding. */
371 disp_encoding_default
= 0,
376 /* How to encode vector instructions. */
379 vex_encoding_default
= 0,
386 const char *rep_prefix
;
389 const char *hle_prefix
;
391 /* Have BND prefix. */
392 const char *bnd_prefix
;
394 /* Have NOTRACK prefix. */
395 const char *notrack_prefix
;
398 enum i386_error error
;
401 typedef struct _i386_insn i386_insn
;
403 /* Link RC type with corresponding string, that'll be looked for in
412 static const struct RC_name RC_NamesTable
[] =
414 { rne
, STRING_COMMA_LEN ("rn-sae") },
415 { rd
, STRING_COMMA_LEN ("rd-sae") },
416 { ru
, STRING_COMMA_LEN ("ru-sae") },
417 { rz
, STRING_COMMA_LEN ("rz-sae") },
418 { saeonly
, STRING_COMMA_LEN ("sae") },
421 /* List of chars besides those in app.c:symbol_chars that can start an
422 operand. Used to prevent the scrubber eating vital white-space. */
423 const char extra_symbol_chars
[] = "*%-([{}"
432 #if (defined (TE_I386AIX) \
433 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
434 && !defined (TE_GNU) \
435 && !defined (TE_LINUX) \
436 && !defined (TE_NACL) \
437 && !defined (TE_NETWARE) \
438 && !defined (TE_FreeBSD) \
439 && !defined (TE_DragonFly) \
440 && !defined (TE_NetBSD)))
441 /* This array holds the chars that always start a comment. If the
442 pre-processor is disabled, these aren't very useful. The option
443 --divide will remove '/' from this list. */
444 const char *i386_comment_chars
= "#/";
445 #define SVR4_COMMENT_CHARS 1
446 #define PREFIX_SEPARATOR '\\'
449 const char *i386_comment_chars
= "#";
450 #define PREFIX_SEPARATOR '/'
453 /* This array holds the chars that only start a comment at the beginning of
454 a line. If the line seems to have the form '# 123 filename'
455 .line and .file directives will appear in the pre-processed output.
456 Note that input_file.c hand checks for '#' at the beginning of the
457 first line of the input file. This is because the compiler outputs
458 #NO_APP at the beginning of its output.
459 Also note that comments started like this one will always work if
460 '/' isn't otherwise defined. */
461 const char line_comment_chars
[] = "#/";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant from exp in floating point
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant
472 const char FLT_CHARS
[] = "fFdDxX";
474 /* Tables for lexical analysis. */
475 static char mnemonic_chars
[256];
476 static char register_chars
[256];
477 static char operand_chars
[256];
478 static char identifier_chars
[256];
479 static char digit_chars
[256];
481 /* Lexical macros. */
482 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
483 #define is_operand_char(x) (operand_chars[(unsigned char) x])
484 #define is_register_char(x) (register_chars[(unsigned char) x])
485 #define is_space_char(x) ((x) == ' ')
486 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
487 #define is_digit_char(x) (digit_chars[(unsigned char) x])
489 /* All non-digit non-letter characters that may occur in an operand. */
490 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
492 /* md_assemble() always leaves the strings it's passed unaltered. To
493 effect this we maintain a stack of saved characters that we've smashed
494 with '\0's (indicating end of strings for various sub-fields of the
495 assembler instruction). */
496 static char save_stack
[32];
497 static char *save_stack_p
;
498 #define END_STRING_AND_SAVE(s) \
499 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
500 #define RESTORE_END_STRING(s) \
501 do { *(s) = *--save_stack_p; } while (0)
503 /* The instruction we're assembling. */
506 /* Possible templates for current insn. */
507 static const templates
*current_templates
;
509 /* Per instruction expressionS buffers: max displacements & immediates. */
510 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
511 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
513 /* Current operand we are working on. */
514 static int this_operand
= -1;
516 /* We support four different modes. FLAG_CODE variable is used to distinguish
524 static enum flag_code flag_code
;
525 static unsigned int object_64bit
;
526 static unsigned int disallow_64bit_reloc
;
527 static int use_rela_relocations
= 0;
529 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
530 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
531 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
533 /* The ELF ABI to use. */
541 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
544 #if defined (TE_PE) || defined (TE_PEP)
545 /* Use big object file format. */
546 static int use_big_obj
= 0;
549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
550 /* 1 if generating code for a shared library. */
551 static int shared
= 0;
554 /* 1 for intel syntax,
556 static int intel_syntax
= 0;
558 /* 1 for Intel64 ISA,
562 /* 1 for intel mnemonic,
563 0 if att mnemonic. */
564 static int intel_mnemonic
= !SYSV386_COMPAT
;
566 /* 1 if support old (<= 2.8.1) versions of gcc. */
567 static int old_gcc
= OLDGCC_COMPAT
;
569 /* 1 if pseudo registers are permitted. */
570 static int allow_pseudo_reg
= 0;
572 /* 1 if register prefix % not required. */
573 static int allow_naked_reg
= 0;
575 /* 1 if the assembler should add BND prefix for all control-transferring
576 instructions supporting it, even if this prefix wasn't specified
578 static int add_bnd_prefix
= 0;
580 /* 1 if pseudo index register, eiz/riz, is allowed . */
581 static int allow_index_reg
= 0;
583 /* 1 if the assembler should ignore LOCK prefix, even if it was
584 specified explicitly. */
585 static int omit_lock_prefix
= 0;
587 /* 1 if the assembler should encode lfence, mfence, and sfence as
588 "lock addl $0, (%{re}sp)". */
589 static int avoid_fence
= 0;
591 /* 1 if the assembler should generate relax relocations. */
593 static int generate_relax_relocations
594 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
596 static enum check_kind
602 sse_check
, operand_check
= check_warning
;
604 /* Register prefix used for error message. */
605 static const char *register_prefix
= "%";
607 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
608 leave, push, and pop instructions so that gcc has the same stack
609 frame as in 32 bit mode. */
610 static char stackop_size
= '\0';
612 /* Non-zero to optimize code alignment. */
613 int optimize_align_code
= 1;
615 /* Non-zero to quieten some warnings. */
616 static int quiet_warnings
= 0;
619 static const char *cpu_arch_name
= NULL
;
620 static char *cpu_sub_arch_name
= NULL
;
622 /* CPU feature flags. */
623 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
625 /* If we have selected a cpu we are generating instructions for. */
626 static int cpu_arch_tune_set
= 0;
628 /* Cpu we are generating instructions for. */
629 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
631 /* CPU feature flags of cpu we are generating instructions for. */
632 static i386_cpu_flags cpu_arch_tune_flags
;
634 /* CPU instruction set architecture used. */
635 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
637 /* CPU feature flags of instruction set architecture used. */
638 i386_cpu_flags cpu_arch_isa_flags
;
640 /* If set, conditional jumps are not automatically promoted to handle
641 larger than a byte offset. */
642 static unsigned int no_cond_jump_promotion
= 0;
644 /* Encode SSE instructions with VEX prefix. */
645 static unsigned int sse2avx
;
647 /* Encode scalar AVX instructions with specific vector length. */
654 /* Encode scalar EVEX LIG instructions with specific vector length. */
662 /* Encode EVEX WIG instructions with specific evex.w. */
669 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
670 static enum rc_type evexrcig
= rne
;
672 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
673 static symbolS
*GOT_symbol
;
675 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
676 unsigned int x86_dwarf2_return_column
;
678 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
679 int x86_cie_data_alignment
;
681 /* Interface to relax_segment.
682 There are 3 major relax states for 386 jump insns because the
683 different types of jumps add different sizes to frags when we're
684 figuring out what sort of jump to choose to reach a given label. */
687 #define UNCOND_JUMP 0
689 #define COND_JUMP86 2
694 #define SMALL16 (SMALL | CODE16)
696 #define BIG16 (BIG | CODE16)
700 #define INLINE __inline__
706 #define ENCODE_RELAX_STATE(type, size) \
707 ((relax_substateT) (((type) << 2) | (size)))
708 #define TYPE_FROM_RELAX_STATE(s) \
710 #define DISP_SIZE_FROM_RELAX_STATE(s) \
711 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
713 /* This table is used by relax_frag to promote short jumps to long
714 ones where necessary. SMALL (short) jumps may be promoted to BIG
715 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
716 don't allow a short jump in a 32 bit code segment to be promoted to
717 a 16 bit offset jump because it's slower (requires data size
718 prefix), and doesn't work, unless the destination is in the bottom
719 64k of the code segment (The top 16 bits of eip are zeroed). */
721 const relax_typeS md_relax_table
[] =
724 1) most positive reach of this state,
725 2) most negative reach of this state,
726 3) how many bytes this mode will have in the variable part of the frag
727 4) which index into the table to try if we can't fit into this one. */
729 /* UNCOND_JUMP states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
732 /* dword jmp adds 4 bytes to frag:
733 0 extra opcode bytes, 4 displacement bytes. */
735 /* word jmp adds 2 byte2 to frag:
736 0 extra opcode bytes, 2 displacement bytes. */
739 /* COND_JUMP states. */
740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
742 /* dword conditionals adds 5 bytes to frag:
743 1 extra opcode byte, 4 displacement bytes. */
745 /* word conditionals add 3 bytes to frag:
746 1 extra opcode byte, 2 displacement bytes. */
749 /* COND_JUMP86 states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
755 /* word conditionals add 4 bytes to frag:
756 1 displacement byte and a 3 byte long branch insn. */
760 static const arch_entry cpu_arch
[] =
762 /* Do not replace the first two entries - i386_target_format()
763 relies on them being there in this order. */
764 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
765 CPU_GENERIC32_FLAGS
, 0 },
766 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
767 CPU_GENERIC64_FLAGS
, 0 },
768 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
770 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
772 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
774 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
776 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
778 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
780 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
782 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
784 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
785 CPU_PENTIUMPRO_FLAGS
, 0 },
786 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
788 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
790 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
792 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
794 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
795 CPU_NOCONA_FLAGS
, 0 },
796 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
798 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
800 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
801 CPU_CORE2_FLAGS
, 1 },
802 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
803 CPU_CORE2_FLAGS
, 0 },
804 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
805 CPU_COREI7_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
808 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
810 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
811 CPU_IAMCU_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
814 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
816 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
817 CPU_ATHLON_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
820 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
822 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
824 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
825 CPU_AMDFAM10_FLAGS
, 0 },
826 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
827 CPU_BDVER1_FLAGS
, 0 },
828 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
829 CPU_BDVER2_FLAGS
, 0 },
830 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
831 CPU_BDVER3_FLAGS
, 0 },
832 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
833 CPU_BDVER4_FLAGS
, 0 },
834 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
835 CPU_ZNVER1_FLAGS
, 0 },
836 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
837 CPU_BTVER1_FLAGS
, 0 },
838 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
839 CPU_BTVER2_FLAGS
, 0 },
840 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
842 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
844 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
848 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
850 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
852 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
854 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
856 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
857 CPU_SSSE3_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
859 CPU_SSE4_1_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
861 CPU_SSE4_2_FLAGS
, 0 },
862 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
863 CPU_SSE4_2_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
868 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
869 CPU_AVX512F_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
871 CPU_AVX512CD_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
873 CPU_AVX512ER_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
875 CPU_AVX512PF_FLAGS
, 0 },
876 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
877 CPU_AVX512DQ_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
879 CPU_AVX512BW_FLAGS
, 0 },
880 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
881 CPU_AVX512VL_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
884 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
885 CPU_VMFUNC_FLAGS
, 0 },
886 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
889 CPU_XSAVE_FLAGS
, 0 },
890 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
891 CPU_XSAVEOPT_FLAGS
, 0 },
892 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
893 CPU_XSAVEC_FLAGS
, 0 },
894 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
895 CPU_XSAVES_FLAGS
, 0 },
896 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
899 CPU_PCLMUL_FLAGS
, 0 },
900 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
901 CPU_PCLMUL_FLAGS
, 1 },
902 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
903 CPU_FSGSBASE_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
905 CPU_RDRND_FLAGS
, 0 },
906 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
910 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
912 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
916 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
918 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
919 CPU_MOVBE_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
922 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
924 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
925 CPU_LZCNT_FLAGS
, 0 },
926 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
930 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
931 CPU_INVPCID_FLAGS
, 0 },
932 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
933 CPU_CLFLUSH_FLAGS
, 0 },
934 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
937 CPU_SYSCALL_FLAGS
, 0 },
938 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
939 CPU_RDTSCP_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
941 CPU_3DNOW_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
943 CPU_3DNOWA_FLAGS
, 0 },
944 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
945 CPU_PADLOCK_FLAGS
, 0 },
946 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
950 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
951 CPU_SSE4A_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
958 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
960 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
961 CPU_RDSEED_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
963 CPU_PRFCHW_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
971 CPU_CLFLUSHOPT_FLAGS
, 0 },
972 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
973 CPU_PREFETCHWT1_FLAGS
, 0 },
974 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
979 CPU_AVX512IFMA_FLAGS
, 0 },
980 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
981 CPU_AVX512VBMI_FLAGS
, 0 },
982 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
983 CPU_AVX512_4FMAPS_FLAGS
, 0 },
984 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
985 CPU_AVX512_4VNNIW_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
987 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
989 CPU_CLZERO_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
991 CPU_MWAITX_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
993 CPU_OSPKE_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
995 CPU_RDPID_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
997 CPU_PTWRITE_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN
,
1002 static const noarch_entry cpu_noarch
[] =
1004 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1005 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1006 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1007 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1008 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1009 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1010 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1011 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1012 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1013 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1014 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1015 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1016 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1017 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1018 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1019 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1020 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1021 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1022 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1023 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1024 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1025 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1026 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1027 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1028 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1029 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1033 /* Like s_lcomm_internal in gas/read.c but the alignment string
1034 is allowed to be optional. */
1037 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1044 && *input_line_pointer
== ',')
1046 align
= parse_align (needs_align
- 1);
1048 if (align
== (addressT
) -1)
1063 bss_alloc (symbolP
, size
, align
);
1068 pe_lcomm (int needs_align
)
1070 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1074 const pseudo_typeS md_pseudo_table
[] =
1076 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1077 {"align", s_align_bytes
, 0},
1079 {"align", s_align_ptwo
, 0},
1081 {"arch", set_cpu_arch
, 0},
1085 {"lcomm", pe_lcomm
, 1},
1087 {"ffloat", float_cons
, 'f'},
1088 {"dfloat", float_cons
, 'd'},
1089 {"tfloat", float_cons
, 'x'},
1091 {"slong", signed_cons
, 4},
1092 {"noopt", s_ignore
, 0},
1093 {"optim", s_ignore
, 0},
1094 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1095 {"code16", set_code_flag
, CODE_16BIT
},
1096 {"code32", set_code_flag
, CODE_32BIT
},
1097 {"code64", set_code_flag
, CODE_64BIT
},
1098 {"intel_syntax", set_intel_syntax
, 1},
1099 {"att_syntax", set_intel_syntax
, 0},
1100 {"intel_mnemonic", set_intel_mnemonic
, 1},
1101 {"att_mnemonic", set_intel_mnemonic
, 0},
1102 {"allow_index_reg", set_allow_index_reg
, 1},
1103 {"disallow_index_reg", set_allow_index_reg
, 0},
1104 {"sse_check", set_check
, 0},
1105 {"operand_check", set_check
, 1},
1106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1107 {"largecomm", handle_large_common
, 0},
1109 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1110 {"loc", dwarf2_directive_loc
, 0},
1111 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1114 {"secrel32", pe_directive_secrel
, 0},
1119 /* For interface with expression (). */
1120 extern char *input_line_pointer
;
1122 /* Hash table for instruction mnemonic lookup. */
1123 static struct hash_control
*op_hash
;
1125 /* Hash table for register lookup. */
1126 static struct hash_control
*reg_hash
;
1129 i386_align_code (fragS
*fragP
, int count
)
1131 /* Various efficient no-op patterns for aligning code labels.
1132 Note: Don't try to assemble the instructions in the comments.
1133 0L and 0w are not legal. */
1134 static const unsigned char f32_1
[] =
1136 static const unsigned char f32_2
[] =
1137 {0x66,0x90}; /* xchg %ax,%ax */
1138 static const unsigned char f32_3
[] =
1139 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1140 static const unsigned char f32_4
[] =
1141 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1142 static const unsigned char f32_5
[] =
1144 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1145 static const unsigned char f32_6
[] =
1146 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1147 static const unsigned char f32_7
[] =
1148 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1149 static const unsigned char f32_8
[] =
1151 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1152 static const unsigned char f32_9
[] =
1153 {0x89,0xf6, /* movl %esi,%esi */
1154 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1155 static const unsigned char f32_10
[] =
1156 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1157 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1158 static const unsigned char f32_11
[] =
1159 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1160 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1161 static const unsigned char f32_12
[] =
1162 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1163 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1164 static const unsigned char f32_13
[] =
1165 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1167 static const unsigned char f32_14
[] =
1168 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1169 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1170 static const unsigned char f16_3
[] =
1171 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1172 static const unsigned char f16_4
[] =
1173 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1174 static const unsigned char f16_5
[] =
1176 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1177 static const unsigned char f16_6
[] =
1178 {0x89,0xf6, /* mov %si,%si */
1179 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1180 static const unsigned char f16_7
[] =
1181 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1182 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1183 static const unsigned char f16_8
[] =
1184 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1185 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1186 static const unsigned char jump_31
[] =
1187 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1188 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1189 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1190 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1191 static const unsigned char *const f32_patt
[] = {
1192 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1193 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1195 static const unsigned char *const f16_patt
[] = {
1196 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1198 /* nopl (%[re]ax) */
1199 static const unsigned char alt_3
[] =
1201 /* nopl 0(%[re]ax) */
1202 static const unsigned char alt_4
[] =
1203 {0x0f,0x1f,0x40,0x00};
1204 /* nopl 0(%[re]ax,%[re]ax,1) */
1205 static const unsigned char alt_5
[] =
1206 {0x0f,0x1f,0x44,0x00,0x00};
1207 /* nopw 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_6
[] =
1209 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopl 0L(%[re]ax) */
1211 static const unsigned char alt_7
[] =
1212 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1213 /* nopl 0L(%[re]ax,%[re]ax,1) */
1214 static const unsigned char alt_8
[] =
1215 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1216 /* nopw 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_9
[] =
1218 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_10
[] =
1221 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 static const unsigned char *const alt_patt
[] = {
1223 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1227 /* Only align for at least a positive non-zero boundary. */
1228 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1231 /* We need to decide which NOP sequence to use for 32bit and
1232 64bit. When -mtune= is used:
1234 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1235 PROCESSOR_GENERIC32, f32_patt will be used.
1236 2. For the rest, alt_patt will be used.
1238 When -mtune= isn't used, alt_patt will be used if
1239 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1242 When -march= or .arch is used, we can't use anything beyond
1243 cpu_arch_isa_flags. */
1245 if (flag_code
== CODE_16BIT
)
1249 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1251 /* Adjust jump offset. */
1252 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1255 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1256 f16_patt
[count
- 1], count
);
1260 const unsigned char *const *patt
= NULL
;
1262 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1264 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1265 switch (cpu_arch_tune
)
1267 case PROCESSOR_UNKNOWN
:
1268 /* We use cpu_arch_isa_flags to check if we SHOULD
1269 optimize with nops. */
1270 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1275 case PROCESSOR_PENTIUM4
:
1276 case PROCESSOR_NOCONA
:
1277 case PROCESSOR_CORE
:
1278 case PROCESSOR_CORE2
:
1279 case PROCESSOR_COREI7
:
1280 case PROCESSOR_L1OM
:
1281 case PROCESSOR_K1OM
:
1282 case PROCESSOR_GENERIC64
:
1284 case PROCESSOR_ATHLON
:
1286 case PROCESSOR_AMDFAM10
:
1288 case PROCESSOR_ZNVER
:
1292 case PROCESSOR_I386
:
1293 case PROCESSOR_I486
:
1294 case PROCESSOR_PENTIUM
:
1295 case PROCESSOR_PENTIUMPRO
:
1296 case PROCESSOR_IAMCU
:
1297 case PROCESSOR_GENERIC32
:
1304 switch (fragP
->tc_frag_data
.tune
)
1306 case PROCESSOR_UNKNOWN
:
1307 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1308 PROCESSOR_UNKNOWN. */
1312 case PROCESSOR_I386
:
1313 case PROCESSOR_I486
:
1314 case PROCESSOR_PENTIUM
:
1315 case PROCESSOR_IAMCU
:
1317 case PROCESSOR_ATHLON
:
1319 case PROCESSOR_AMDFAM10
:
1321 case PROCESSOR_ZNVER
:
1323 case PROCESSOR_GENERIC32
:
1324 /* We use cpu_arch_isa_flags to check if we CAN optimize
1326 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1331 case PROCESSOR_PENTIUMPRO
:
1332 case PROCESSOR_PENTIUM4
:
1333 case PROCESSOR_NOCONA
:
1334 case PROCESSOR_CORE
:
1335 case PROCESSOR_CORE2
:
1336 case PROCESSOR_COREI7
:
1337 case PROCESSOR_L1OM
:
1338 case PROCESSOR_K1OM
:
1339 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1344 case PROCESSOR_GENERIC64
:
1350 if (patt
== f32_patt
)
1352 /* If the padding is less than 15 bytes, we use the normal
1353 ones. Otherwise, we use a jump instruction and adjust
1357 /* For 64bit, the limit is 3 bytes. */
1358 if (flag_code
== CODE_64BIT
1359 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1364 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1365 patt
[count
- 1], count
);
1368 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1370 /* Adjust jump offset. */
1371 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1376 /* Maximum length of an instruction is 10 byte. If the
1377 padding is greater than 10 bytes and we don't use jump,
1378 we have to break it into smaller pieces. */
1379 int padding
= count
;
1380 while (padding
> 10)
1383 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1388 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1389 patt
[padding
- 1], padding
);
1392 fragP
->fr_var
= count
;
1396 operand_type_all_zero (const union i386_operand_type
*x
)
1398 switch (ARRAY_SIZE(x
->array
))
1409 return !x
->array
[0];
1416 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1418 switch (ARRAY_SIZE(x
->array
))
1436 operand_type_equal (const union i386_operand_type
*x
,
1437 const union i386_operand_type
*y
)
1439 switch (ARRAY_SIZE(x
->array
))
1442 if (x
->array
[2] != y
->array
[2])
1446 if (x
->array
[1] != y
->array
[1])
1450 return x
->array
[0] == y
->array
[0];
1458 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1460 switch (ARRAY_SIZE(x
->array
))
1471 return !x
->array
[0];
1478 cpu_flags_equal (const union i386_cpu_flags
*x
,
1479 const union i386_cpu_flags
*y
)
1481 switch (ARRAY_SIZE(x
->array
))
1484 if (x
->array
[2] != y
->array
[2])
1488 if (x
->array
[1] != y
->array
[1])
1492 return x
->array
[0] == y
->array
[0];
1500 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1502 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1503 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1506 static INLINE i386_cpu_flags
1507 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1509 switch (ARRAY_SIZE (x
.array
))
1512 x
.array
[2] &= y
.array
[2];
1515 x
.array
[1] &= y
.array
[1];
1518 x
.array
[0] &= y
.array
[0];
1526 static INLINE i386_cpu_flags
1527 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1529 switch (ARRAY_SIZE (x
.array
))
1532 x
.array
[2] |= y
.array
[2];
1535 x
.array
[1] |= y
.array
[1];
1538 x
.array
[0] |= y
.array
[0];
1546 static INLINE i386_cpu_flags
1547 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1549 switch (ARRAY_SIZE (x
.array
))
1552 x
.array
[2] &= ~y
.array
[2];
1555 x
.array
[1] &= ~y
.array
[1];
1558 x
.array
[0] &= ~y
.array
[0];
1566 #define CPU_FLAGS_ARCH_MATCH 0x1
1567 #define CPU_FLAGS_64BIT_MATCH 0x2
1568 #define CPU_FLAGS_AES_MATCH 0x4
1569 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1570 #define CPU_FLAGS_AVX_MATCH 0x10
1572 #define CPU_FLAGS_32BIT_MATCH \
1573 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1574 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1575 #define CPU_FLAGS_PERFECT_MATCH \
1576 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1578 /* Return CPU flags match bits. */
1581 cpu_flags_match (const insn_template
*t
)
1583 i386_cpu_flags x
= t
->cpu_flags
;
1584 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1586 x
.bitfield
.cpu64
= 0;
1587 x
.bitfield
.cpuno64
= 0;
1589 if (cpu_flags_all_zero (&x
))
1591 /* This instruction is available on all archs. */
1592 match
|= CPU_FLAGS_32BIT_MATCH
;
1596 /* This instruction is available only on some archs. */
1597 i386_cpu_flags cpu
= cpu_arch_flags
;
1599 cpu
= cpu_flags_and (x
, cpu
);
1600 if (!cpu_flags_all_zero (&cpu
))
1602 if (x
.bitfield
.cpuavx
)
1604 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1605 if (cpu
.bitfield
.cpuavx
)
1607 /* Check SSE2AVX. */
1608 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1610 match
|= (CPU_FLAGS_ARCH_MATCH
1611 | CPU_FLAGS_AVX_MATCH
);
1613 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1614 match
|= CPU_FLAGS_AES_MATCH
;
1616 if (!x
.bitfield
.cpupclmul
1617 || cpu
.bitfield
.cpupclmul
)
1618 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1622 match
|= CPU_FLAGS_ARCH_MATCH
;
1624 else if (x
.bitfield
.cpuavx512vl
)
1626 /* Match AVX512VL. */
1627 if (cpu
.bitfield
.cpuavx512vl
)
1629 /* Need another match. */
1630 cpu
.bitfield
.cpuavx512vl
= 0;
1631 if (!cpu_flags_all_zero (&cpu
))
1632 match
|= CPU_FLAGS_32BIT_MATCH
;
1634 match
|= CPU_FLAGS_ARCH_MATCH
;
1637 match
|= CPU_FLAGS_ARCH_MATCH
;
1640 match
|= CPU_FLAGS_32BIT_MATCH
;
1646 static INLINE i386_operand_type
1647 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1649 switch (ARRAY_SIZE (x
.array
))
1652 x
.array
[2] &= y
.array
[2];
1655 x
.array
[1] &= y
.array
[1];
1658 x
.array
[0] &= y
.array
[0];
1666 static INLINE i386_operand_type
1667 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1669 switch (ARRAY_SIZE (x
.array
))
1672 x
.array
[2] |= y
.array
[2];
1675 x
.array
[1] |= y
.array
[1];
1678 x
.array
[0] |= y
.array
[0];
1686 static INLINE i386_operand_type
1687 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1689 switch (ARRAY_SIZE (x
.array
))
1692 x
.array
[2] ^= y
.array
[2];
1695 x
.array
[1] ^= y
.array
[1];
1698 x
.array
[0] ^= y
.array
[0];
1706 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1707 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1708 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1709 static const i386_operand_type inoutportreg
1710 = OPERAND_TYPE_INOUTPORTREG
;
1711 static const i386_operand_type reg16_inoutportreg
1712 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1713 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1714 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1715 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1716 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1717 static const i386_operand_type anydisp
1718 = OPERAND_TYPE_ANYDISP
;
1719 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1720 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1721 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1722 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1723 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1724 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1725 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1726 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1727 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1728 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1729 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1730 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1731 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1732 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1743 operand_type_check (i386_operand_type t
, enum operand_type c
)
1748 return (t
.bitfield
.reg8
1751 || t
.bitfield
.reg64
);
1754 return (t
.bitfield
.imm8
1758 || t
.bitfield
.imm32s
1759 || t
.bitfield
.imm64
);
1762 return (t
.bitfield
.disp8
1763 || t
.bitfield
.disp16
1764 || t
.bitfield
.disp32
1765 || t
.bitfield
.disp32s
1766 || t
.bitfield
.disp64
);
1769 return (t
.bitfield
.disp8
1770 || t
.bitfield
.disp16
1771 || t
.bitfield
.disp32
1772 || t
.bitfield
.disp32s
1773 || t
.bitfield
.disp64
1774 || t
.bitfield
.baseindex
);
1783 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1784 operand J for instruction template T. */
1787 match_reg_size (const insn_template
*t
, unsigned int j
)
1789 return !((i
.types
[j
].bitfield
.byte
1790 && !t
->operand_types
[j
].bitfield
.byte
)
1791 || (i
.types
[j
].bitfield
.word
1792 && !t
->operand_types
[j
].bitfield
.word
)
1793 || (i
.types
[j
].bitfield
.dword
1794 && !t
->operand_types
[j
].bitfield
.dword
)
1795 || (i
.types
[j
].bitfield
.qword
1796 && !t
->operand_types
[j
].bitfield
.qword
));
1799 /* Return 1 if there is no conflict in any size on operand J for
1800 instruction template T. */
1803 match_mem_size (const insn_template
*t
, unsigned int j
)
1805 return (match_reg_size (t
, j
)
1806 && !((i
.types
[j
].bitfield
.unspecified
1808 && !t
->operand_types
[j
].bitfield
.unspecified
)
1809 || (i
.types
[j
].bitfield
.fword
1810 && !t
->operand_types
[j
].bitfield
.fword
)
1811 || (i
.types
[j
].bitfield
.tbyte
1812 && !t
->operand_types
[j
].bitfield
.tbyte
)
1813 || (i
.types
[j
].bitfield
.xmmword
1814 && !t
->operand_types
[j
].bitfield
.xmmword
)
1815 || (i
.types
[j
].bitfield
.ymmword
1816 && !t
->operand_types
[j
].bitfield
.ymmword
)
1817 || (i
.types
[j
].bitfield
.zmmword
1818 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1821 /* Return 1 if there is no size conflict on any operands for
1822 instruction template T. */
1825 operand_size_match (const insn_template
*t
)
1830 /* Don't check jump instructions. */
1831 if (t
->opcode_modifier
.jump
1832 || t
->opcode_modifier
.jumpbyte
1833 || t
->opcode_modifier
.jumpdword
1834 || t
->opcode_modifier
.jumpintersegment
)
1837 /* Check memory and accumulator operand size. */
1838 for (j
= 0; j
< i
.operands
; j
++)
1840 if (t
->operand_types
[j
].bitfield
.anysize
)
1843 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1849 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1858 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1861 i
.error
= operand_size_mismatch
;
1865 /* Check reverse. */
1866 gas_assert (i
.operands
== 2);
1869 for (j
= 0; j
< 2; j
++)
1871 if (t
->operand_types
[j
].bitfield
.acc
1872 && !match_reg_size (t
, j
? 0 : 1))
1875 if (i
.types
[j
].bitfield
.mem
1876 && !match_mem_size (t
, j
? 0 : 1))
1884 operand_type_match (i386_operand_type overlap
,
1885 i386_operand_type given
)
1887 i386_operand_type temp
= overlap
;
1889 temp
.bitfield
.jumpabsolute
= 0;
1890 temp
.bitfield
.unspecified
= 0;
1891 temp
.bitfield
.byte
= 0;
1892 temp
.bitfield
.word
= 0;
1893 temp
.bitfield
.dword
= 0;
1894 temp
.bitfield
.fword
= 0;
1895 temp
.bitfield
.qword
= 0;
1896 temp
.bitfield
.tbyte
= 0;
1897 temp
.bitfield
.xmmword
= 0;
1898 temp
.bitfield
.ymmword
= 0;
1899 temp
.bitfield
.zmmword
= 0;
1900 if (operand_type_all_zero (&temp
))
1903 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1904 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1908 i
.error
= operand_type_mismatch
;
1912 /* If given types g0 and g1 are registers they must be of the same type
1913 unless the expected operand type register overlap is null.
1914 Note that Acc in a template matches every size of reg. */
1917 operand_type_register_match (i386_operand_type m0
,
1918 i386_operand_type g0
,
1919 i386_operand_type t0
,
1920 i386_operand_type m1
,
1921 i386_operand_type g1
,
1922 i386_operand_type t1
)
1924 if (!operand_type_check (g0
, reg
))
1927 if (!operand_type_check (g1
, reg
))
1930 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1931 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1932 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1933 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1936 if (m0
.bitfield
.acc
)
1938 t0
.bitfield
.reg8
= 1;
1939 t0
.bitfield
.reg16
= 1;
1940 t0
.bitfield
.reg32
= 1;
1941 t0
.bitfield
.reg64
= 1;
1944 if (m1
.bitfield
.acc
)
1946 t1
.bitfield
.reg8
= 1;
1947 t1
.bitfield
.reg16
= 1;
1948 t1
.bitfield
.reg32
= 1;
1949 t1
.bitfield
.reg64
= 1;
1952 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1953 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1954 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1955 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1958 i
.error
= register_type_mismatch
;
1963 static INLINE
unsigned int
1964 register_number (const reg_entry
*r
)
1966 unsigned int nr
= r
->reg_num
;
1968 if (r
->reg_flags
& RegRex
)
1971 if (r
->reg_flags
& RegVRex
)
1977 static INLINE
unsigned int
1978 mode_from_disp_size (i386_operand_type t
)
1980 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1982 else if (t
.bitfield
.disp16
1983 || t
.bitfield
.disp32
1984 || t
.bitfield
.disp32s
)
1991 fits_in_signed_byte (addressT num
)
1993 return num
+ 0x80 <= 0xff;
1997 fits_in_unsigned_byte (addressT num
)
2003 fits_in_unsigned_word (addressT num
)
2005 return num
<= 0xffff;
2009 fits_in_signed_word (addressT num
)
2011 return num
+ 0x8000 <= 0xffff;
2015 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2020 return num
+ 0x80000000 <= 0xffffffff;
2022 } /* fits_in_signed_long() */
2025 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2030 return num
<= 0xffffffff;
2032 } /* fits_in_unsigned_long() */
2035 fits_in_vec_disp8 (offsetT num
)
2037 int shift
= i
.memshift
;
2043 mask
= (1 << shift
) - 1;
2045 /* Return 0 if NUM isn't properly aligned. */
2049 /* Check if NUM will fit in 8bit after shift. */
2050 return fits_in_signed_byte (num
>> shift
);
2054 fits_in_imm4 (offsetT num
)
2056 return (num
& 0xf) == num
;
2059 static i386_operand_type
2060 smallest_imm_type (offsetT num
)
2062 i386_operand_type t
;
2064 operand_type_set (&t
, 0);
2065 t
.bitfield
.imm64
= 1;
2067 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2069 /* This code is disabled on the 486 because all the Imm1 forms
2070 in the opcode table are slower on the i486. They're the
2071 versions with the implicitly specified single-position
2072 displacement, which has another syntax if you really want to
2074 t
.bitfield
.imm1
= 1;
2075 t
.bitfield
.imm8
= 1;
2076 t
.bitfield
.imm8s
= 1;
2077 t
.bitfield
.imm16
= 1;
2078 t
.bitfield
.imm32
= 1;
2079 t
.bitfield
.imm32s
= 1;
2081 else if (fits_in_signed_byte (num
))
2083 t
.bitfield
.imm8
= 1;
2084 t
.bitfield
.imm8s
= 1;
2085 t
.bitfield
.imm16
= 1;
2086 t
.bitfield
.imm32
= 1;
2087 t
.bitfield
.imm32s
= 1;
2089 else if (fits_in_unsigned_byte (num
))
2091 t
.bitfield
.imm8
= 1;
2092 t
.bitfield
.imm16
= 1;
2093 t
.bitfield
.imm32
= 1;
2094 t
.bitfield
.imm32s
= 1;
2096 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2098 t
.bitfield
.imm16
= 1;
2099 t
.bitfield
.imm32
= 1;
2100 t
.bitfield
.imm32s
= 1;
2102 else if (fits_in_signed_long (num
))
2104 t
.bitfield
.imm32
= 1;
2105 t
.bitfield
.imm32s
= 1;
2107 else if (fits_in_unsigned_long (num
))
2108 t
.bitfield
.imm32
= 1;
2114 offset_in_range (offsetT val
, int size
)
2120 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2121 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2122 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2124 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2130 /* If BFD64, sign extend val for 32bit address mode. */
2131 if (flag_code
!= CODE_64BIT
2132 || i
.prefix
[ADDR_PREFIX
])
2133 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2134 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2137 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2139 char buf1
[40], buf2
[40];
2141 sprint_value (buf1
, val
);
2142 sprint_value (buf2
, val
& mask
);
2143 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2158 a. PREFIX_EXIST if attempting to add a prefix where one from the
2159 same class already exists.
2160 b. PREFIX_LOCK if lock prefix is added.
2161 c. PREFIX_REP if rep/repne prefix is added.
2162 d. PREFIX_DS if ds prefix is added.
2163 e. PREFIX_OTHER if other prefix is added.
2166 static enum PREFIX_GROUP
2167 add_prefix (unsigned int prefix
)
2169 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2172 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2173 && flag_code
== CODE_64BIT
)
2175 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2176 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2177 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2188 case DS_PREFIX_OPCODE
:
2191 case CS_PREFIX_OPCODE
:
2192 case ES_PREFIX_OPCODE
:
2193 case FS_PREFIX_OPCODE
:
2194 case GS_PREFIX_OPCODE
:
2195 case SS_PREFIX_OPCODE
:
2199 case REPNE_PREFIX_OPCODE
:
2200 case REPE_PREFIX_OPCODE
:
2205 case LOCK_PREFIX_OPCODE
:
2214 case ADDR_PREFIX_OPCODE
:
2218 case DATA_PREFIX_OPCODE
:
2222 if (i
.prefix
[q
] != 0)
2230 i
.prefix
[q
] |= prefix
;
2233 as_bad (_("same type of prefix used twice"));
2239 update_code_flag (int value
, int check
)
2241 PRINTF_LIKE ((*as_error
));
2243 flag_code
= (enum flag_code
) value
;
2244 if (flag_code
== CODE_64BIT
)
2246 cpu_arch_flags
.bitfield
.cpu64
= 1;
2247 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2251 cpu_arch_flags
.bitfield
.cpu64
= 0;
2252 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2254 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2257 as_error
= as_fatal
;
2260 (*as_error
) (_("64bit mode not supported on `%s'."),
2261 cpu_arch_name
? cpu_arch_name
: default_arch
);
2263 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2266 as_error
= as_fatal
;
2269 (*as_error
) (_("32bit mode not supported on `%s'."),
2270 cpu_arch_name
? cpu_arch_name
: default_arch
);
2272 stackop_size
= '\0';
2276 set_code_flag (int value
)
2278 update_code_flag (value
, 0);
2282 set_16bit_gcc_code_flag (int new_code_flag
)
2284 flag_code
= (enum flag_code
) new_code_flag
;
2285 if (flag_code
!= CODE_16BIT
)
2287 cpu_arch_flags
.bitfield
.cpu64
= 0;
2288 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2289 stackop_size
= LONG_MNEM_SUFFIX
;
2293 set_intel_syntax (int syntax_flag
)
2295 /* Find out if register prefixing is specified. */
2296 int ask_naked_reg
= 0;
2299 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2302 int e
= get_symbol_name (&string
);
2304 if (strcmp (string
, "prefix") == 0)
2306 else if (strcmp (string
, "noprefix") == 0)
2309 as_bad (_("bad argument to syntax directive."));
2310 (void) restore_line_pointer (e
);
2312 demand_empty_rest_of_line ();
2314 intel_syntax
= syntax_flag
;
2316 if (ask_naked_reg
== 0)
2317 allow_naked_reg
= (intel_syntax
2318 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2320 allow_naked_reg
= (ask_naked_reg
< 0);
2322 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2324 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2325 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2326 register_prefix
= allow_naked_reg
? "" : "%";
2330 set_intel_mnemonic (int mnemonic_flag
)
2332 intel_mnemonic
= mnemonic_flag
;
2336 set_allow_index_reg (int flag
)
2338 allow_index_reg
= flag
;
2342 set_check (int what
)
2344 enum check_kind
*kind
;
2349 kind
= &operand_check
;
2360 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2363 int e
= get_symbol_name (&string
);
2365 if (strcmp (string
, "none") == 0)
2367 else if (strcmp (string
, "warning") == 0)
2368 *kind
= check_warning
;
2369 else if (strcmp (string
, "error") == 0)
2370 *kind
= check_error
;
2372 as_bad (_("bad argument to %s_check directive."), str
);
2373 (void) restore_line_pointer (e
);
2376 as_bad (_("missing argument for %s_check directive"), str
);
2378 demand_empty_rest_of_line ();
2382 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2383 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2385 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2386 static const char *arch
;
2388 /* Intel LIOM is only supported on ELF. */
2394 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2395 use default_arch. */
2396 arch
= cpu_arch_name
;
2398 arch
= default_arch
;
2401 /* If we are targeting Intel MCU, we must enable it. */
2402 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2403 || new_flag
.bitfield
.cpuiamcu
)
2406 /* If we are targeting Intel L1OM, we must enable it. */
2407 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2408 || new_flag
.bitfield
.cpul1om
)
2411 /* If we are targeting Intel K1OM, we must enable it. */
2412 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2413 || new_flag
.bitfield
.cpuk1om
)
2416 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2421 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2425 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2428 int e
= get_symbol_name (&string
);
2430 i386_cpu_flags flags
;
2432 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2434 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2436 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2440 cpu_arch_name
= cpu_arch
[j
].name
;
2441 cpu_sub_arch_name
= NULL
;
2442 cpu_arch_flags
= cpu_arch
[j
].flags
;
2443 if (flag_code
== CODE_64BIT
)
2445 cpu_arch_flags
.bitfield
.cpu64
= 1;
2446 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2450 cpu_arch_flags
.bitfield
.cpu64
= 0;
2451 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2453 cpu_arch_isa
= cpu_arch
[j
].type
;
2454 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2455 if (!cpu_arch_tune_set
)
2457 cpu_arch_tune
= cpu_arch_isa
;
2458 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2463 flags
= cpu_flags_or (cpu_arch_flags
,
2466 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2468 if (cpu_sub_arch_name
)
2470 char *name
= cpu_sub_arch_name
;
2471 cpu_sub_arch_name
= concat (name
,
2473 (const char *) NULL
);
2477 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2478 cpu_arch_flags
= flags
;
2479 cpu_arch_isa_flags
= flags
;
2481 (void) restore_line_pointer (e
);
2482 demand_empty_rest_of_line ();
2487 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2489 /* Disable an ISA extension. */
2490 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2491 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2493 flags
= cpu_flags_and_not (cpu_arch_flags
,
2494 cpu_noarch
[j
].flags
);
2495 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2497 if (cpu_sub_arch_name
)
2499 char *name
= cpu_sub_arch_name
;
2500 cpu_sub_arch_name
= concat (name
, string
,
2501 (const char *) NULL
);
2505 cpu_sub_arch_name
= xstrdup (string
);
2506 cpu_arch_flags
= flags
;
2507 cpu_arch_isa_flags
= flags
;
2509 (void) restore_line_pointer (e
);
2510 demand_empty_rest_of_line ();
2514 j
= ARRAY_SIZE (cpu_arch
);
2517 if (j
>= ARRAY_SIZE (cpu_arch
))
2518 as_bad (_("no such architecture: `%s'"), string
);
2520 *input_line_pointer
= e
;
2523 as_bad (_("missing cpu architecture"));
2525 no_cond_jump_promotion
= 0;
2526 if (*input_line_pointer
== ','
2527 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2532 ++input_line_pointer
;
2533 e
= get_symbol_name (&string
);
2535 if (strcmp (string
, "nojumps") == 0)
2536 no_cond_jump_promotion
= 1;
2537 else if (strcmp (string
, "jumps") == 0)
2540 as_bad (_("no such architecture modifier: `%s'"), string
);
2542 (void) restore_line_pointer (e
);
2545 demand_empty_rest_of_line ();
2548 enum bfd_architecture
2551 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2553 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2554 || flag_code
!= CODE_64BIT
)
2555 as_fatal (_("Intel L1OM is 64bit ELF only"));
2556 return bfd_arch_l1om
;
2558 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2560 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2561 || flag_code
!= CODE_64BIT
)
2562 as_fatal (_("Intel K1OM is 64bit ELF only"));
2563 return bfd_arch_k1om
;
2565 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2567 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2568 || flag_code
== CODE_64BIT
)
2569 as_fatal (_("Intel MCU is 32bit ELF only"));
2570 return bfd_arch_iamcu
;
2573 return bfd_arch_i386
;
2579 if (!strncmp (default_arch
, "x86_64", 6))
2581 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2583 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2584 || default_arch
[6] != '\0')
2585 as_fatal (_("Intel L1OM is 64bit ELF only"));
2586 return bfd_mach_l1om
;
2588 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2590 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2591 || default_arch
[6] != '\0')
2592 as_fatal (_("Intel K1OM is 64bit ELF only"));
2593 return bfd_mach_k1om
;
2595 else if (default_arch
[6] == '\0')
2596 return bfd_mach_x86_64
;
2598 return bfd_mach_x64_32
;
2600 else if (!strcmp (default_arch
, "i386")
2601 || !strcmp (default_arch
, "iamcu"))
2603 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2605 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2606 as_fatal (_("Intel MCU is 32bit ELF only"));
2607 return bfd_mach_i386_iamcu
;
2610 return bfd_mach_i386_i386
;
2613 as_fatal (_("unknown architecture"));
2619 const char *hash_err
;
2621 /* Support pseudo prefixes like {disp32}. */
2622 lex_type
['{'] = LEX_BEGIN_NAME
;
2624 /* Initialize op_hash hash table. */
2625 op_hash
= hash_new ();
2628 const insn_template
*optab
;
2629 templates
*core_optab
;
2631 /* Setup for loop. */
2633 core_optab
= XNEW (templates
);
2634 core_optab
->start
= optab
;
2639 if (optab
->name
== NULL
2640 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2642 /* different name --> ship out current template list;
2643 add to hash table; & begin anew. */
2644 core_optab
->end
= optab
;
2645 hash_err
= hash_insert (op_hash
,
2647 (void *) core_optab
);
2650 as_fatal (_("can't hash %s: %s"),
2654 if (optab
->name
== NULL
)
2656 core_optab
= XNEW (templates
);
2657 core_optab
->start
= optab
;
2662 /* Initialize reg_hash hash table. */
2663 reg_hash
= hash_new ();
2665 const reg_entry
*regtab
;
2666 unsigned int regtab_size
= i386_regtab_size
;
2668 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2670 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2672 as_fatal (_("can't hash %s: %s"),
2678 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2683 for (c
= 0; c
< 256; c
++)
2688 mnemonic_chars
[c
] = c
;
2689 register_chars
[c
] = c
;
2690 operand_chars
[c
] = c
;
2692 else if (ISLOWER (c
))
2694 mnemonic_chars
[c
] = c
;
2695 register_chars
[c
] = c
;
2696 operand_chars
[c
] = c
;
2698 else if (ISUPPER (c
))
2700 mnemonic_chars
[c
] = TOLOWER (c
);
2701 register_chars
[c
] = mnemonic_chars
[c
];
2702 operand_chars
[c
] = c
;
2704 else if (c
== '{' || c
== '}')
2706 mnemonic_chars
[c
] = c
;
2707 operand_chars
[c
] = c
;
2710 if (ISALPHA (c
) || ISDIGIT (c
))
2711 identifier_chars
[c
] = c
;
2714 identifier_chars
[c
] = c
;
2715 operand_chars
[c
] = c
;
2720 identifier_chars
['@'] = '@';
2723 identifier_chars
['?'] = '?';
2724 operand_chars
['?'] = '?';
2726 digit_chars
['-'] = '-';
2727 mnemonic_chars
['_'] = '_';
2728 mnemonic_chars
['-'] = '-';
2729 mnemonic_chars
['.'] = '.';
2730 identifier_chars
['_'] = '_';
2731 identifier_chars
['.'] = '.';
2733 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2734 operand_chars
[(unsigned char) *p
] = *p
;
2737 if (flag_code
== CODE_64BIT
)
2739 #if defined (OBJ_COFF) && defined (TE_PE)
2740 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2743 x86_dwarf2_return_column
= 16;
2745 x86_cie_data_alignment
= -8;
2749 x86_dwarf2_return_column
= 8;
2750 x86_cie_data_alignment
= -4;
2755 i386_print_statistics (FILE *file
)
2757 hash_print_statistics (file
, "i386 opcode", op_hash
);
2758 hash_print_statistics (file
, "i386 register", reg_hash
);
2763 /* Debugging routines for md_assemble. */
2764 static void pte (insn_template
*);
2765 static void pt (i386_operand_type
);
2766 static void pe (expressionS
*);
2767 static void ps (symbolS
*);
2770 pi (char *line
, i386_insn
*x
)
2774 fprintf (stdout
, "%s: template ", line
);
2776 fprintf (stdout
, " address: base %s index %s scale %x\n",
2777 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2778 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2779 x
->log2_scale_factor
);
2780 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2781 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2782 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2783 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2784 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2785 (x
->rex
& REX_W
) != 0,
2786 (x
->rex
& REX_R
) != 0,
2787 (x
->rex
& REX_X
) != 0,
2788 (x
->rex
& REX_B
) != 0);
2789 for (j
= 0; j
< x
->operands
; j
++)
2791 fprintf (stdout
, " #%d: ", j
+ 1);
2793 fprintf (stdout
, "\n");
2794 if (x
->types
[j
].bitfield
.reg8
2795 || x
->types
[j
].bitfield
.reg16
2796 || x
->types
[j
].bitfield
.reg32
2797 || x
->types
[j
].bitfield
.reg64
2798 || x
->types
[j
].bitfield
.regmmx
2799 || x
->types
[j
].bitfield
.regxmm
2800 || x
->types
[j
].bitfield
.regymm
2801 || x
->types
[j
].bitfield
.regzmm
2802 || x
->types
[j
].bitfield
.sreg2
2803 || x
->types
[j
].bitfield
.sreg3
2804 || x
->types
[j
].bitfield
.control
2805 || x
->types
[j
].bitfield
.debug
2806 || x
->types
[j
].bitfield
.test
)
2807 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2808 if (operand_type_check (x
->types
[j
], imm
))
2810 if (operand_type_check (x
->types
[j
], disp
))
2811 pe (x
->op
[j
].disps
);
2816 pte (insn_template
*t
)
2819 fprintf (stdout
, " %d operands ", t
->operands
);
2820 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2821 if (t
->extension_opcode
!= None
)
2822 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2823 if (t
->opcode_modifier
.d
)
2824 fprintf (stdout
, "D");
2825 if (t
->opcode_modifier
.w
)
2826 fprintf (stdout
, "W");
2827 fprintf (stdout
, "\n");
2828 for (j
= 0; j
< t
->operands
; j
++)
2830 fprintf (stdout
, " #%d type ", j
+ 1);
2831 pt (t
->operand_types
[j
]);
2832 fprintf (stdout
, "\n");
2839 fprintf (stdout
, " operation %d\n", e
->X_op
);
2840 fprintf (stdout
, " add_number %ld (%lx)\n",
2841 (long) e
->X_add_number
, (long) e
->X_add_number
);
2842 if (e
->X_add_symbol
)
2844 fprintf (stdout
, " add_symbol ");
2845 ps (e
->X_add_symbol
);
2846 fprintf (stdout
, "\n");
2850 fprintf (stdout
, " op_symbol ");
2851 ps (e
->X_op_symbol
);
2852 fprintf (stdout
, "\n");
2859 fprintf (stdout
, "%s type %s%s",
2861 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2862 segment_name (S_GET_SEGMENT (s
)));
2865 static struct type_name
2867 i386_operand_type mask
;
2870 const type_names
[] =
2872 { OPERAND_TYPE_REG8
, "r8" },
2873 { OPERAND_TYPE_REG16
, "r16" },
2874 { OPERAND_TYPE_REG32
, "r32" },
2875 { OPERAND_TYPE_REG64
, "r64" },
2876 { OPERAND_TYPE_IMM8
, "i8" },
2877 { OPERAND_TYPE_IMM8
, "i8s" },
2878 { OPERAND_TYPE_IMM16
, "i16" },
2879 { OPERAND_TYPE_IMM32
, "i32" },
2880 { OPERAND_TYPE_IMM32S
, "i32s" },
2881 { OPERAND_TYPE_IMM64
, "i64" },
2882 { OPERAND_TYPE_IMM1
, "i1" },
2883 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2884 { OPERAND_TYPE_DISP8
, "d8" },
2885 { OPERAND_TYPE_DISP16
, "d16" },
2886 { OPERAND_TYPE_DISP32
, "d32" },
2887 { OPERAND_TYPE_DISP32S
, "d32s" },
2888 { OPERAND_TYPE_DISP64
, "d64" },
2889 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2890 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2891 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2892 { OPERAND_TYPE_CONTROL
, "control reg" },
2893 { OPERAND_TYPE_TEST
, "test reg" },
2894 { OPERAND_TYPE_DEBUG
, "debug reg" },
2895 { OPERAND_TYPE_FLOATREG
, "FReg" },
2896 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2897 { OPERAND_TYPE_SREG2
, "SReg2" },
2898 { OPERAND_TYPE_SREG3
, "SReg3" },
2899 { OPERAND_TYPE_ACC
, "Acc" },
2900 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2901 { OPERAND_TYPE_REGMMX
, "rMMX" },
2902 { OPERAND_TYPE_REGXMM
, "rXMM" },
2903 { OPERAND_TYPE_REGYMM
, "rYMM" },
2904 { OPERAND_TYPE_REGZMM
, "rZMM" },
2905 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2906 { OPERAND_TYPE_ESSEG
, "es" },
2910 pt (i386_operand_type t
)
2913 i386_operand_type a
;
2915 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2917 a
= operand_type_and (t
, type_names
[j
].mask
);
2918 if (!operand_type_all_zero (&a
))
2919 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2924 #endif /* DEBUG386 */
2926 static bfd_reloc_code_real_type
2927 reloc (unsigned int size
,
2930 bfd_reloc_code_real_type other
)
2932 if (other
!= NO_RELOC
)
2934 reloc_howto_type
*rel
;
2939 case BFD_RELOC_X86_64_GOT32
:
2940 return BFD_RELOC_X86_64_GOT64
;
2942 case BFD_RELOC_X86_64_GOTPLT64
:
2943 return BFD_RELOC_X86_64_GOTPLT64
;
2945 case BFD_RELOC_X86_64_PLTOFF64
:
2946 return BFD_RELOC_X86_64_PLTOFF64
;
2948 case BFD_RELOC_X86_64_GOTPC32
:
2949 other
= BFD_RELOC_X86_64_GOTPC64
;
2951 case BFD_RELOC_X86_64_GOTPCREL
:
2952 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2954 case BFD_RELOC_X86_64_TPOFF32
:
2955 other
= BFD_RELOC_X86_64_TPOFF64
;
2957 case BFD_RELOC_X86_64_DTPOFF32
:
2958 other
= BFD_RELOC_X86_64_DTPOFF64
;
2964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2965 if (other
== BFD_RELOC_SIZE32
)
2968 other
= BFD_RELOC_SIZE64
;
2971 as_bad (_("there are no pc-relative size relocations"));
2977 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2978 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2981 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2983 as_bad (_("unknown relocation (%u)"), other
);
2984 else if (size
!= bfd_get_reloc_size (rel
))
2985 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2986 bfd_get_reloc_size (rel
),
2988 else if (pcrel
&& !rel
->pc_relative
)
2989 as_bad (_("non-pc-relative relocation for pc-relative field"));
2990 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2992 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2994 as_bad (_("relocated field and relocation type differ in signedness"));
3003 as_bad (_("there are no unsigned pc-relative relocations"));
3006 case 1: return BFD_RELOC_8_PCREL
;
3007 case 2: return BFD_RELOC_16_PCREL
;
3008 case 4: return BFD_RELOC_32_PCREL
;
3009 case 8: return BFD_RELOC_64_PCREL
;
3011 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3018 case 4: return BFD_RELOC_X86_64_32S
;
3023 case 1: return BFD_RELOC_8
;
3024 case 2: return BFD_RELOC_16
;
3025 case 4: return BFD_RELOC_32
;
3026 case 8: return BFD_RELOC_64
;
3028 as_bad (_("cannot do %s %u byte relocation"),
3029 sign
> 0 ? "signed" : "unsigned", size
);
3035 /* Here we decide which fixups can be adjusted to make them relative to
3036 the beginning of the section instead of the symbol. Basically we need
3037 to make sure that the dynamic relocations are done correctly, so in
3038 some cases we force the original symbol to be used. */
3041 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3047 /* Don't adjust pc-relative references to merge sections in 64-bit
3049 if (use_rela_relocations
3050 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3054 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3055 and changed later by validate_fix. */
3056 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3057 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3060 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3061 for size relocations. */
3062 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3063 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3064 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3065 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3066 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3067 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3068 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3069 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3070 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3071 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3072 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3073 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3074 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3075 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3076 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3077 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3078 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3079 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3080 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3081 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3082 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3083 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3084 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3085 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3086 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3087 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3088 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3089 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3090 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3091 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3092 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3093 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3094 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3101 intel_float_operand (const char *mnemonic
)
3103 /* Note that the value returned is meaningful only for opcodes with (memory)
3104 operands, hence the code here is free to improperly handle opcodes that
3105 have no operands (for better performance and smaller code). */
3107 if (mnemonic
[0] != 'f')
3108 return 0; /* non-math */
3110 switch (mnemonic
[1])
3112 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3113 the fs segment override prefix not currently handled because no
3114 call path can make opcodes without operands get here */
3116 return 2 /* integer op */;
3118 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3119 return 3; /* fldcw/fldenv */
3122 if (mnemonic
[2] != 'o' /* fnop */)
3123 return 3; /* non-waiting control op */
3126 if (mnemonic
[2] == 's')
3127 return 3; /* frstor/frstpm */
3130 if (mnemonic
[2] == 'a')
3131 return 3; /* fsave */
3132 if (mnemonic
[2] == 't')
3134 switch (mnemonic
[3])
3136 case 'c': /* fstcw */
3137 case 'd': /* fstdw */
3138 case 'e': /* fstenv */
3139 case 's': /* fsts[gw] */
3145 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3146 return 0; /* fxsave/fxrstor are not really math ops */
3153 /* Build the VEX prefix. */
3156 build_vex_prefix (const insn_template
*t
)
3158 unsigned int register_specifier
;
3159 unsigned int implied_prefix
;
3160 unsigned int vector_length
;
3162 /* Check register specifier. */
3163 if (i
.vex
.register_specifier
)
3165 register_specifier
=
3166 ~register_number (i
.vex
.register_specifier
) & 0xf;
3167 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3170 register_specifier
= 0xf;
3172 /* Use 2-byte VEX prefix by swapping destination and source
3174 if (i
.vec_encoding
!= vex_encoding_vex3
3175 && i
.dir_encoding
== dir_encoding_default
3176 && i
.operands
== i
.reg_operands
3177 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3178 && i
.tm
.opcode_modifier
.load
3181 unsigned int xchg
= i
.operands
- 1;
3182 union i386_op temp_op
;
3183 i386_operand_type temp_type
;
3185 temp_type
= i
.types
[xchg
];
3186 i
.types
[xchg
] = i
.types
[0];
3187 i
.types
[0] = temp_type
;
3188 temp_op
= i
.op
[xchg
];
3189 i
.op
[xchg
] = i
.op
[0];
3192 gas_assert (i
.rm
.mode
== 3);
3196 i
.rm
.regmem
= i
.rm
.reg
;
3199 /* Use the next insn. */
3203 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3204 vector_length
= avxscalar
;
3206 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3208 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3213 case DATA_PREFIX_OPCODE
:
3216 case REPE_PREFIX_OPCODE
:
3219 case REPNE_PREFIX_OPCODE
:
3226 /* Use 2-byte VEX prefix if possible. */
3227 if (i
.vec_encoding
!= vex_encoding_vex3
3228 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3229 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3230 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3232 /* 2-byte VEX prefix. */
3236 i
.vex
.bytes
[0] = 0xc5;
3238 /* Check the REX.R bit. */
3239 r
= (i
.rex
& REX_R
) ? 0 : 1;
3240 i
.vex
.bytes
[1] = (r
<< 7
3241 | register_specifier
<< 3
3242 | vector_length
<< 2
3247 /* 3-byte VEX prefix. */
3252 switch (i
.tm
.opcode_modifier
.vexopcode
)
3256 i
.vex
.bytes
[0] = 0xc4;
3260 i
.vex
.bytes
[0] = 0xc4;
3264 i
.vex
.bytes
[0] = 0xc4;
3268 i
.vex
.bytes
[0] = 0x8f;
3272 i
.vex
.bytes
[0] = 0x8f;
3276 i
.vex
.bytes
[0] = 0x8f;
3282 /* The high 3 bits of the second VEX byte are 1's compliment
3283 of RXB bits from REX. */
3284 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3286 /* Check the REX.W bit. */
3287 w
= (i
.rex
& REX_W
) ? 1 : 0;
3288 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3291 i
.vex
.bytes
[2] = (w
<< 7
3292 | register_specifier
<< 3
3293 | vector_length
<< 2
3298 /* Build the EVEX prefix. */
3301 build_evex_prefix (void)
3303 unsigned int register_specifier
;
3304 unsigned int implied_prefix
;
3306 rex_byte vrex_used
= 0;
3308 /* Check register specifier. */
3309 if (i
.vex
.register_specifier
)
3311 gas_assert ((i
.vrex
& REX_X
) == 0);
3313 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3314 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3315 register_specifier
+= 8;
3316 /* The upper 16 registers are encoded in the fourth byte of the
3318 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3319 i
.vex
.bytes
[3] = 0x8;
3320 register_specifier
= ~register_specifier
& 0xf;
3324 register_specifier
= 0xf;
3326 /* Encode upper 16 vector index register in the fourth byte of
3328 if (!(i
.vrex
& REX_X
))
3329 i
.vex
.bytes
[3] = 0x8;
3334 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3339 case DATA_PREFIX_OPCODE
:
3342 case REPE_PREFIX_OPCODE
:
3345 case REPNE_PREFIX_OPCODE
:
3352 /* 4 byte EVEX prefix. */
3354 i
.vex
.bytes
[0] = 0x62;
3357 switch (i
.tm
.opcode_modifier
.vexopcode
)
3373 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3375 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3377 /* The fifth bit of the second EVEX byte is 1's compliment of the
3378 REX_R bit in VREX. */
3379 if (!(i
.vrex
& REX_R
))
3380 i
.vex
.bytes
[1] |= 0x10;
3384 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3386 /* When all operands are registers, the REX_X bit in REX is not
3387 used. We reuse it to encode the upper 16 registers, which is
3388 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3389 as 1's compliment. */
3390 if ((i
.vrex
& REX_B
))
3393 i
.vex
.bytes
[1] &= ~0x40;
3397 /* EVEX instructions shouldn't need the REX prefix. */
3398 i
.vrex
&= ~vrex_used
;
3399 gas_assert (i
.vrex
== 0);
3401 /* Check the REX.W bit. */
3402 w
= (i
.rex
& REX_W
) ? 1 : 0;
3403 if (i
.tm
.opcode_modifier
.vexw
)
3405 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3408 /* If w is not set it means we are dealing with WIG instruction. */
3411 if (evexwig
== evexw1
)
3415 /* Encode the U bit. */
3416 implied_prefix
|= 0x4;
3418 /* The third byte of the EVEX prefix. */
3419 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3421 /* The fourth byte of the EVEX prefix. */
3422 /* The zeroing-masking bit. */
3423 if (i
.mask
&& i
.mask
->zeroing
)
3424 i
.vex
.bytes
[3] |= 0x80;
3426 /* Don't always set the broadcast bit if there is no RC. */
3429 /* Encode the vector length. */
3430 unsigned int vec_length
;
3432 switch (i
.tm
.opcode_modifier
.evex
)
3434 case EVEXLIG
: /* LL' is ignored */
3435 vec_length
= evexlig
<< 5;
3438 vec_length
= 0 << 5;
3441 vec_length
= 1 << 5;
3444 vec_length
= 2 << 5;
3450 i
.vex
.bytes
[3] |= vec_length
;
3451 /* Encode the broadcast bit. */
3453 i
.vex
.bytes
[3] |= 0x10;
3457 if (i
.rounding
->type
!= saeonly
)
3458 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3460 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3463 if (i
.mask
&& i
.mask
->mask
)
3464 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3468 process_immext (void)
3472 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3475 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3476 with an opcode suffix which is coded in the same place as an
3477 8-bit immediate field would be.
3478 Here we check those operands and remove them afterwards. */
3481 for (x
= 0; x
< i
.operands
; x
++)
3482 if (register_number (i
.op
[x
].regs
) != x
)
3483 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3484 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3490 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3492 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3493 suffix which is coded in the same place as an 8-bit immediate
3495 Here we check those operands and remove them afterwards. */
3498 if (i
.operands
!= 3)
3501 for (x
= 0; x
< 2; x
++)
3502 if (register_number (i
.op
[x
].regs
) != x
)
3503 goto bad_register_operand
;
3505 /* Check for third operand for mwaitx/monitorx insn. */
3506 if (register_number (i
.op
[x
].regs
)
3507 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3509 bad_register_operand
:
3510 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3511 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3518 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3519 which is coded in the same place as an 8-bit immediate field
3520 would be. Here we fake an 8-bit immediate operand from the
3521 opcode suffix stored in tm.extension_opcode.
3523 AVX instructions also use this encoding, for some of
3524 3 argument instructions. */
3526 gas_assert (i
.imm_operands
<= 1
3528 || ((i
.tm
.opcode_modifier
.vex
3529 || i
.tm
.opcode_modifier
.evex
)
3530 && i
.operands
<= 4)));
3532 exp
= &im_expressions
[i
.imm_operands
++];
3533 i
.op
[i
.operands
].imms
= exp
;
3534 i
.types
[i
.operands
] = imm8
;
3536 exp
->X_op
= O_constant
;
3537 exp
->X_add_number
= i
.tm
.extension_opcode
;
3538 i
.tm
.extension_opcode
= None
;
3545 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3550 as_bad (_("invalid instruction `%s' after `%s'"),
3551 i
.tm
.name
, i
.hle_prefix
);
3554 if (i
.prefix
[LOCK_PREFIX
])
3556 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3560 case HLEPrefixRelease
:
3561 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3563 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3567 if (i
.mem_operands
== 0
3568 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3570 as_bad (_("memory destination needed for instruction `%s'"
3571 " after `xrelease'"), i
.tm
.name
);
3578 /* This is the guts of the machine-dependent assembler. LINE points to a
3579 machine dependent instruction. This function is supposed to emit
3580 the frags/bytes it assembles to. */
3583 md_assemble (char *line
)
3586 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3587 const insn_template
*t
;
3589 /* Initialize globals. */
3590 memset (&i
, '\0', sizeof (i
));
3591 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3592 i
.reloc
[j
] = NO_RELOC
;
3593 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3594 memset (im_expressions
, '\0', sizeof (im_expressions
));
3595 save_stack_p
= save_stack
;
3597 /* First parse an instruction mnemonic & call i386_operand for the operands.
3598 We assume that the scrubber has arranged it so that line[0] is the valid
3599 start of a (possibly prefixed) mnemonic. */
3601 line
= parse_insn (line
, mnemonic
);
3604 mnem_suffix
= i
.suffix
;
3606 line
= parse_operands (line
, mnemonic
);
3608 xfree (i
.memop1_string
);
3609 i
.memop1_string
= NULL
;
3613 /* Now we've parsed the mnemonic into a set of templates, and have the
3614 operands at hand. */
3616 /* All intel opcodes have reversed operands except for "bound" and
3617 "enter". We also don't reverse intersegment "jmp" and "call"
3618 instructions with 2 immediate operands so that the immediate segment
3619 precedes the offset, as it does when in AT&T mode. */
3622 && (strcmp (mnemonic
, "bound") != 0)
3623 && (strcmp (mnemonic
, "invlpga") != 0)
3624 && !(operand_type_check (i
.types
[0], imm
)
3625 && operand_type_check (i
.types
[1], imm
)))
3628 /* The order of the immediates should be reversed
3629 for 2 immediates extrq and insertq instructions */
3630 if (i
.imm_operands
== 2
3631 && (strcmp (mnemonic
, "extrq") == 0
3632 || strcmp (mnemonic
, "insertq") == 0))
3633 swap_2_operands (0, 1);
3638 /* Don't optimize displacement for movabs since it only takes 64bit
3641 && i
.disp_encoding
!= disp_encoding_32bit
3642 && (flag_code
!= CODE_64BIT
3643 || strcmp (mnemonic
, "movabs") != 0))
3646 /* Next, we find a template that matches the given insn,
3647 making sure the overlap of the given operands types is consistent
3648 with the template operand types. */
3650 if (!(t
= match_template (mnem_suffix
)))
3653 if (sse_check
!= check_none
3654 && !i
.tm
.opcode_modifier
.noavx
3655 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3656 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3657 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3658 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3659 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3660 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3662 (sse_check
== check_warning
3664 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3667 /* Zap movzx and movsx suffix. The suffix has been set from
3668 "word ptr" or "byte ptr" on the source operand in Intel syntax
3669 or extracted from mnemonic in AT&T syntax. But we'll use
3670 the destination register to choose the suffix for encoding. */
3671 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3673 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3674 there is no suffix, the default will be byte extension. */
3675 if (i
.reg_operands
!= 2
3678 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3683 if (i
.tm
.opcode_modifier
.fwait
)
3684 if (!add_prefix (FWAIT_OPCODE
))
3687 /* Check if REP prefix is OK. */
3688 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3690 as_bad (_("invalid instruction `%s' after `%s'"),
3691 i
.tm
.name
, i
.rep_prefix
);
3695 /* Check for lock without a lockable instruction. Destination operand
3696 must be memory unless it is xchg (0x86). */
3697 if (i
.prefix
[LOCK_PREFIX
]
3698 && (!i
.tm
.opcode_modifier
.islockable
3699 || i
.mem_operands
== 0
3700 || (i
.tm
.base_opcode
!= 0x86
3701 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3703 as_bad (_("expecting lockable instruction after `lock'"));
3707 /* Check if HLE prefix is OK. */
3708 if (i
.hle_prefix
&& !check_hle ())
3711 /* Check BND prefix. */
3712 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3713 as_bad (_("expecting valid branch instruction after `bnd'"));
3715 /* Check NOTRACK prefix. */
3716 if (i
.notrack_prefix
3717 && (!i
.tm
.opcode_modifier
.notrackprefixok
3718 || i
.reg_operands
!= 1
3719 || i
.disp_operands
!= 0
3720 || i
.mem_operands
!= 0
3721 || i
.imm_operands
!= 0))
3722 as_bad (_("expecting register indirect branch instruction after `notrack'"));
3724 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
3726 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
3727 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3728 else if (flag_code
!= CODE_16BIT
3729 ? i
.prefix
[ADDR_PREFIX
]
3730 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
3731 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3734 /* Insert BND prefix. */
3736 && i
.tm
.opcode_modifier
.bndprefixok
3737 && !i
.prefix
[BND_PREFIX
])
3738 add_prefix (BND_PREFIX_OPCODE
);
3740 /* Check string instruction segment overrides. */
3741 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3743 if (!check_string ())
3745 i
.disp_operands
= 0;
3748 if (!process_suffix ())
3751 /* Update operand types. */
3752 for (j
= 0; j
< i
.operands
; j
++)
3753 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3755 /* Make still unresolved immediate matches conform to size of immediate
3756 given in i.suffix. */
3757 if (!finalize_imm ())
3760 if (i
.types
[0].bitfield
.imm1
)
3761 i
.imm_operands
= 0; /* kludge for shift insns. */
3763 /* We only need to check those implicit registers for instructions
3764 with 3 operands or less. */
3765 if (i
.operands
<= 3)
3766 for (j
= 0; j
< i
.operands
; j
++)
3767 if (i
.types
[j
].bitfield
.inoutportreg
3768 || i
.types
[j
].bitfield
.shiftcount
3769 || i
.types
[j
].bitfield
.acc
3770 || i
.types
[j
].bitfield
.floatacc
)
3773 /* ImmExt should be processed after SSE2AVX. */
3774 if (!i
.tm
.opcode_modifier
.sse2avx
3775 && i
.tm
.opcode_modifier
.immext
)
3778 /* For insns with operands there are more diddles to do to the opcode. */
3781 if (!process_operands ())
3784 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3786 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3787 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3790 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3792 if (flag_code
== CODE_16BIT
)
3794 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3799 if (i
.tm
.opcode_modifier
.vex
)
3800 build_vex_prefix (t
);
3802 build_evex_prefix ();
3805 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3806 instructions may define INT_OPCODE as well, so avoid this corner
3807 case for those instructions that use MODRM. */
3808 if (i
.tm
.base_opcode
== INT_OPCODE
3809 && !i
.tm
.opcode_modifier
.modrm
3810 && i
.op
[0].imms
->X_add_number
== 3)
3812 i
.tm
.base_opcode
= INT3_OPCODE
;
3816 if ((i
.tm
.opcode_modifier
.jump
3817 || i
.tm
.opcode_modifier
.jumpbyte
3818 || i
.tm
.opcode_modifier
.jumpdword
)
3819 && i
.op
[0].disps
->X_op
== O_constant
)
3821 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3822 the absolute address given by the constant. Since ix86 jumps and
3823 calls are pc relative, we need to generate a reloc. */
3824 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3825 i
.op
[0].disps
->X_op
= O_symbol
;
3828 if (i
.tm
.opcode_modifier
.rex64
)
3831 /* For 8 bit registers we need an empty rex prefix. Also if the
3832 instruction already has a prefix, we need to convert old
3833 registers to new ones. */
3835 if ((i
.types
[0].bitfield
.reg8
3836 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3837 || (i
.types
[1].bitfield
.reg8
3838 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3839 || ((i
.types
[0].bitfield
.reg8
3840 || i
.types
[1].bitfield
.reg8
)
3845 i
.rex
|= REX_OPCODE
;
3846 for (x
= 0; x
< 2; x
++)
3848 /* Look for 8 bit operand that uses old registers. */
3849 if (i
.types
[x
].bitfield
.reg8
3850 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3852 /* In case it is "hi" register, give up. */
3853 if (i
.op
[x
].regs
->reg_num
> 3)
3854 as_bad (_("can't encode register '%s%s' in an "
3855 "instruction requiring REX prefix."),
3856 register_prefix
, i
.op
[x
].regs
->reg_name
);
3858 /* Otherwise it is equivalent to the extended register.
3859 Since the encoding doesn't change this is merely
3860 cosmetic cleanup for debug output. */
3862 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3868 add_prefix (REX_OPCODE
| i
.rex
);
3870 /* We are ready to output the insn. */
3875 parse_insn (char *line
, char *mnemonic
)
3878 char *token_start
= l
;
3881 const insn_template
*t
;
3887 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3892 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3894 as_bad (_("no such instruction: `%s'"), token_start
);
3899 if (!is_space_char (*l
)
3900 && *l
!= END_OF_INSN
3902 || (*l
!= PREFIX_SEPARATOR
3905 as_bad (_("invalid character %s in mnemonic"),
3906 output_invalid (*l
));
3909 if (token_start
== l
)
3911 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3912 as_bad (_("expecting prefix; got nothing"));
3914 as_bad (_("expecting mnemonic; got nothing"));
3918 /* Look up instruction (or prefix) via hash table. */
3919 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3921 if (*l
!= END_OF_INSN
3922 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3923 && current_templates
3924 && current_templates
->start
->opcode_modifier
.isprefix
)
3926 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3928 as_bad ((flag_code
!= CODE_64BIT
3929 ? _("`%s' is only supported in 64-bit mode")
3930 : _("`%s' is not supported in 64-bit mode")),
3931 current_templates
->start
->name
);
3934 /* If we are in 16-bit mode, do not allow addr16 or data16.
3935 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3936 if ((current_templates
->start
->opcode_modifier
.size16
3937 || current_templates
->start
->opcode_modifier
.size32
)
3938 && flag_code
!= CODE_64BIT
3939 && (current_templates
->start
->opcode_modifier
.size32
3940 ^ (flag_code
== CODE_16BIT
)))
3942 as_bad (_("redundant %s prefix"),
3943 current_templates
->start
->name
);
3946 if (current_templates
->start
->opcode_length
== 0)
3948 /* Handle pseudo prefixes. */
3949 switch (current_templates
->start
->base_opcode
)
3953 i
.disp_encoding
= disp_encoding_8bit
;
3957 i
.disp_encoding
= disp_encoding_32bit
;
3961 i
.dir_encoding
= dir_encoding_load
;
3965 i
.dir_encoding
= dir_encoding_store
;
3969 i
.vec_encoding
= vex_encoding_vex2
;
3973 i
.vec_encoding
= vex_encoding_vex3
;
3977 i
.vec_encoding
= vex_encoding_evex
;
3985 /* Add prefix, checking for repeated prefixes. */
3987 = add_prefix (current_templates
->start
->base_opcode
);
3989 && current_templates
->start
->cpu_flags
.bitfield
.cpucet
)
3991 i
.notrack_prefix
= current_templates
->start
->name
;
3992 /* Move NOTRACK_PREFIX_OPCODE to NOTRACK_PREFIX slot so
3993 that it is placed before others. */
3994 i
.prefix
[SEG_PREFIX
] = 0;
3995 i
.prefix
[NOTRACK_PREFIX
] = NOTRACK_PREFIX_OPCODE
;
4004 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4005 i
.hle_prefix
= current_templates
->start
->name
;
4006 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4007 i
.bnd_prefix
= current_templates
->start
->name
;
4009 i
.rep_prefix
= current_templates
->start
->name
;
4015 if (i
.notrack_prefix
!= NULL
)
4017 /* There must be no other prefixes after NOTRACK
4019 as_bad (_("expecting no other prefixes after `notrack'"));
4024 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4031 if (!current_templates
)
4033 /* Check if we should swap operand or force 32bit displacement in
4035 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4036 i
.dir_encoding
= dir_encoding_store
;
4037 else if (mnem_p
- 3 == dot_p
4040 i
.disp_encoding
= disp_encoding_8bit
;
4041 else if (mnem_p
- 4 == dot_p
4045 i
.disp_encoding
= disp_encoding_32bit
;
4050 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4053 if (!current_templates
)
4056 /* See if we can get a match by trimming off a suffix. */
4059 case WORD_MNEM_SUFFIX
:
4060 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4061 i
.suffix
= SHORT_MNEM_SUFFIX
;
4064 case BYTE_MNEM_SUFFIX
:
4065 case QWORD_MNEM_SUFFIX
:
4066 i
.suffix
= mnem_p
[-1];
4068 current_templates
= (const templates
*) hash_find (op_hash
,
4071 case SHORT_MNEM_SUFFIX
:
4072 case LONG_MNEM_SUFFIX
:
4075 i
.suffix
= mnem_p
[-1];
4077 current_templates
= (const templates
*) hash_find (op_hash
,
4086 if (intel_float_operand (mnemonic
) == 1)
4087 i
.suffix
= SHORT_MNEM_SUFFIX
;
4089 i
.suffix
= LONG_MNEM_SUFFIX
;
4091 current_templates
= (const templates
*) hash_find (op_hash
,
4096 if (!current_templates
)
4098 as_bad (_("no such instruction: `%s'"), token_start
);
4103 if (current_templates
->start
->opcode_modifier
.jump
4104 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4106 /* Check for a branch hint. We allow ",pt" and ",pn" for
4107 predict taken and predict not taken respectively.
4108 I'm not sure that branch hints actually do anything on loop
4109 and jcxz insns (JumpByte) for current Pentium4 chips. They
4110 may work in the future and it doesn't hurt to accept them
4112 if (l
[0] == ',' && l
[1] == 'p')
4116 if (!add_prefix (DS_PREFIX_OPCODE
))
4120 else if (l
[2] == 'n')
4122 if (!add_prefix (CS_PREFIX_OPCODE
))
4128 /* Any other comma loses. */
4131 as_bad (_("invalid character %s in mnemonic"),
4132 output_invalid (*l
));
4136 /* Check if instruction is supported on specified architecture. */
4138 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4140 supported
|= cpu_flags_match (t
);
4141 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4145 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4147 as_bad (flag_code
== CODE_64BIT
4148 ? _("`%s' is not supported in 64-bit mode")
4149 : _("`%s' is only supported in 64-bit mode"),
4150 current_templates
->start
->name
);
4153 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4155 as_bad (_("`%s' is not supported on `%s%s'"),
4156 current_templates
->start
->name
,
4157 cpu_arch_name
? cpu_arch_name
: default_arch
,
4158 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4163 if (!cpu_arch_flags
.bitfield
.cpui386
4164 && (flag_code
!= CODE_16BIT
))
4166 as_warn (_("use .code16 to ensure correct addressing mode"));
4173 parse_operands (char *l
, const char *mnemonic
)
4177 /* 1 if operand is pending after ','. */
4178 unsigned int expecting_operand
= 0;
4180 /* Non-zero if operand parens not balanced. */
4181 unsigned int paren_not_balanced
;
4183 while (*l
!= END_OF_INSN
)
4185 /* Skip optional white space before operand. */
4186 if (is_space_char (*l
))
4188 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4190 as_bad (_("invalid character %s before operand %d"),
4191 output_invalid (*l
),
4195 token_start
= l
; /* After white space. */
4196 paren_not_balanced
= 0;
4197 while (paren_not_balanced
|| *l
!= ',')
4199 if (*l
== END_OF_INSN
)
4201 if (paren_not_balanced
)
4204 as_bad (_("unbalanced parenthesis in operand %d."),
4207 as_bad (_("unbalanced brackets in operand %d."),
4212 break; /* we are done */
4214 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4216 as_bad (_("invalid character %s in operand %d"),
4217 output_invalid (*l
),
4224 ++paren_not_balanced
;
4226 --paren_not_balanced
;
4231 ++paren_not_balanced
;
4233 --paren_not_balanced
;
4237 if (l
!= token_start
)
4238 { /* Yes, we've read in another operand. */
4239 unsigned int operand_ok
;
4240 this_operand
= i
.operands
++;
4241 if (i
.operands
> MAX_OPERANDS
)
4243 as_bad (_("spurious operands; (%d operands/instruction max)"),
4247 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4248 /* Now parse operand adding info to 'i' as we go along. */
4249 END_STRING_AND_SAVE (l
);
4253 i386_intel_operand (token_start
,
4254 intel_float_operand (mnemonic
));
4256 operand_ok
= i386_att_operand (token_start
);
4258 RESTORE_END_STRING (l
);
4264 if (expecting_operand
)
4266 expecting_operand_after_comma
:
4267 as_bad (_("expecting operand after ','; got nothing"));
4272 as_bad (_("expecting operand before ','; got nothing"));
4277 /* Now *l must be either ',' or END_OF_INSN. */
4280 if (*++l
== END_OF_INSN
)
4282 /* Just skip it, if it's \n complain. */
4283 goto expecting_operand_after_comma
;
4285 expecting_operand
= 1;
4292 swap_2_operands (int xchg1
, int xchg2
)
4294 union i386_op temp_op
;
4295 i386_operand_type temp_type
;
4296 enum bfd_reloc_code_real temp_reloc
;
4298 temp_type
= i
.types
[xchg2
];
4299 i
.types
[xchg2
] = i
.types
[xchg1
];
4300 i
.types
[xchg1
] = temp_type
;
4301 temp_op
= i
.op
[xchg2
];
4302 i
.op
[xchg2
] = i
.op
[xchg1
];
4303 i
.op
[xchg1
] = temp_op
;
4304 temp_reloc
= i
.reloc
[xchg2
];
4305 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4306 i
.reloc
[xchg1
] = temp_reloc
;
4310 if (i
.mask
->operand
== xchg1
)
4311 i
.mask
->operand
= xchg2
;
4312 else if (i
.mask
->operand
== xchg2
)
4313 i
.mask
->operand
= xchg1
;
4317 if (i
.broadcast
->operand
== xchg1
)
4318 i
.broadcast
->operand
= xchg2
;
4319 else if (i
.broadcast
->operand
== xchg2
)
4320 i
.broadcast
->operand
= xchg1
;
4324 if (i
.rounding
->operand
== xchg1
)
4325 i
.rounding
->operand
= xchg2
;
4326 else if (i
.rounding
->operand
== xchg2
)
4327 i
.rounding
->operand
= xchg1
;
4332 swap_operands (void)
4338 swap_2_operands (1, i
.operands
- 2);
4342 swap_2_operands (0, i
.operands
- 1);
4348 if (i
.mem_operands
== 2)
4350 const seg_entry
*temp_seg
;
4351 temp_seg
= i
.seg
[0];
4352 i
.seg
[0] = i
.seg
[1];
4353 i
.seg
[1] = temp_seg
;
4357 /* Try to ensure constant immediates are represented in the smallest
4362 char guess_suffix
= 0;
4366 guess_suffix
= i
.suffix
;
4367 else if (i
.reg_operands
)
4369 /* Figure out a suffix from the last register operand specified.
4370 We can't do this properly yet, ie. excluding InOutPortReg,
4371 but the following works for instructions with immediates.
4372 In any case, we can't set i.suffix yet. */
4373 for (op
= i
.operands
; --op
>= 0;)
4374 if (i
.types
[op
].bitfield
.reg8
)
4376 guess_suffix
= BYTE_MNEM_SUFFIX
;
4379 else if (i
.types
[op
].bitfield
.reg16
)
4381 guess_suffix
= WORD_MNEM_SUFFIX
;
4384 else if (i
.types
[op
].bitfield
.reg32
)
4386 guess_suffix
= LONG_MNEM_SUFFIX
;
4389 else if (i
.types
[op
].bitfield
.reg64
)
4391 guess_suffix
= QWORD_MNEM_SUFFIX
;
4395 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4396 guess_suffix
= WORD_MNEM_SUFFIX
;
4398 for (op
= i
.operands
; --op
>= 0;)
4399 if (operand_type_check (i
.types
[op
], imm
))
4401 switch (i
.op
[op
].imms
->X_op
)
4404 /* If a suffix is given, this operand may be shortened. */
4405 switch (guess_suffix
)
4407 case LONG_MNEM_SUFFIX
:
4408 i
.types
[op
].bitfield
.imm32
= 1;
4409 i
.types
[op
].bitfield
.imm64
= 1;
4411 case WORD_MNEM_SUFFIX
:
4412 i
.types
[op
].bitfield
.imm16
= 1;
4413 i
.types
[op
].bitfield
.imm32
= 1;
4414 i
.types
[op
].bitfield
.imm32s
= 1;
4415 i
.types
[op
].bitfield
.imm64
= 1;
4417 case BYTE_MNEM_SUFFIX
:
4418 i
.types
[op
].bitfield
.imm8
= 1;
4419 i
.types
[op
].bitfield
.imm8s
= 1;
4420 i
.types
[op
].bitfield
.imm16
= 1;
4421 i
.types
[op
].bitfield
.imm32
= 1;
4422 i
.types
[op
].bitfield
.imm32s
= 1;
4423 i
.types
[op
].bitfield
.imm64
= 1;
4427 /* If this operand is at most 16 bits, convert it
4428 to a signed 16 bit number before trying to see
4429 whether it will fit in an even smaller size.
4430 This allows a 16-bit operand such as $0xffe0 to
4431 be recognised as within Imm8S range. */
4432 if ((i
.types
[op
].bitfield
.imm16
)
4433 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4435 i
.op
[op
].imms
->X_add_number
=
4436 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4439 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4440 if ((i
.types
[op
].bitfield
.imm32
)
4441 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4444 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4445 ^ ((offsetT
) 1 << 31))
4446 - ((offsetT
) 1 << 31));
4450 = operand_type_or (i
.types
[op
],
4451 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4453 /* We must avoid matching of Imm32 templates when 64bit
4454 only immediate is available. */
4455 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4456 i
.types
[op
].bitfield
.imm32
= 0;
4463 /* Symbols and expressions. */
4465 /* Convert symbolic operand to proper sizes for matching, but don't
4466 prevent matching a set of insns that only supports sizes other
4467 than those matching the insn suffix. */
4469 i386_operand_type mask
, allowed
;
4470 const insn_template
*t
;
4472 operand_type_set (&mask
, 0);
4473 operand_type_set (&allowed
, 0);
4475 for (t
= current_templates
->start
;
4476 t
< current_templates
->end
;
4478 allowed
= operand_type_or (allowed
,
4479 t
->operand_types
[op
]);
4480 switch (guess_suffix
)
4482 case QWORD_MNEM_SUFFIX
:
4483 mask
.bitfield
.imm64
= 1;
4484 mask
.bitfield
.imm32s
= 1;
4486 case LONG_MNEM_SUFFIX
:
4487 mask
.bitfield
.imm32
= 1;
4489 case WORD_MNEM_SUFFIX
:
4490 mask
.bitfield
.imm16
= 1;
4492 case BYTE_MNEM_SUFFIX
:
4493 mask
.bitfield
.imm8
= 1;
4498 allowed
= operand_type_and (mask
, allowed
);
4499 if (!operand_type_all_zero (&allowed
))
4500 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4507 /* Try to use the smallest displacement type too. */
4509 optimize_disp (void)
4513 for (op
= i
.operands
; --op
>= 0;)
4514 if (operand_type_check (i
.types
[op
], disp
))
4516 if (i
.op
[op
].disps
->X_op
== O_constant
)
4518 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4520 if (i
.types
[op
].bitfield
.disp16
4521 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4523 /* If this operand is at most 16 bits, convert
4524 to a signed 16 bit number and don't use 64bit
4526 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4527 i
.types
[op
].bitfield
.disp64
= 0;
4530 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4531 if (i
.types
[op
].bitfield
.disp32
4532 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4534 /* If this operand is at most 32 bits, convert
4535 to a signed 32 bit number and don't use 64bit
4537 op_disp
&= (((offsetT
) 2 << 31) - 1);
4538 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4539 i
.types
[op
].bitfield
.disp64
= 0;
4542 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4544 i
.types
[op
].bitfield
.disp8
= 0;
4545 i
.types
[op
].bitfield
.disp16
= 0;
4546 i
.types
[op
].bitfield
.disp32
= 0;
4547 i
.types
[op
].bitfield
.disp32s
= 0;
4548 i
.types
[op
].bitfield
.disp64
= 0;
4552 else if (flag_code
== CODE_64BIT
)
4554 if (fits_in_signed_long (op_disp
))
4556 i
.types
[op
].bitfield
.disp64
= 0;
4557 i
.types
[op
].bitfield
.disp32s
= 1;
4559 if (i
.prefix
[ADDR_PREFIX
]
4560 && fits_in_unsigned_long (op_disp
))
4561 i
.types
[op
].bitfield
.disp32
= 1;
4563 if ((i
.types
[op
].bitfield
.disp32
4564 || i
.types
[op
].bitfield
.disp32s
4565 || i
.types
[op
].bitfield
.disp16
)
4566 && fits_in_signed_byte (op_disp
))
4567 i
.types
[op
].bitfield
.disp8
= 1;
4569 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4570 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4572 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4573 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4574 i
.types
[op
].bitfield
.disp8
= 0;
4575 i
.types
[op
].bitfield
.disp16
= 0;
4576 i
.types
[op
].bitfield
.disp32
= 0;
4577 i
.types
[op
].bitfield
.disp32s
= 0;
4578 i
.types
[op
].bitfield
.disp64
= 0;
4581 /* We only support 64bit displacement on constants. */
4582 i
.types
[op
].bitfield
.disp64
= 0;
4586 /* Check if operands are valid for the instruction. */
4589 check_VecOperands (const insn_template
*t
)
4593 /* Without VSIB byte, we can't have a vector register for index. */
4594 if (!t
->opcode_modifier
.vecsib
4596 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4597 || i
.index_reg
->reg_type
.bitfield
.regymm
4598 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4600 i
.error
= unsupported_vector_index_register
;
4604 /* Check if default mask is allowed. */
4605 if (t
->opcode_modifier
.nodefmask
4606 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4608 i
.error
= no_default_mask
;
4612 /* For VSIB byte, we need a vector register for index, and all vector
4613 registers must be distinct. */
4614 if (t
->opcode_modifier
.vecsib
)
4617 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4618 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4619 || (t
->opcode_modifier
.vecsib
== VecSIB256
4620 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4621 || (t
->opcode_modifier
.vecsib
== VecSIB512
4622 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4624 i
.error
= invalid_vsib_address
;
4628 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4629 if (i
.reg_operands
== 2 && !i
.mask
)
4631 gas_assert (i
.types
[0].bitfield
.regxmm
4632 || i
.types
[0].bitfield
.regymm
);
4633 gas_assert (i
.types
[2].bitfield
.regxmm
4634 || i
.types
[2].bitfield
.regymm
);
4635 if (operand_check
== check_none
)
4637 if (register_number (i
.op
[0].regs
)
4638 != register_number (i
.index_reg
)
4639 && register_number (i
.op
[2].regs
)
4640 != register_number (i
.index_reg
)
4641 && register_number (i
.op
[0].regs
)
4642 != register_number (i
.op
[2].regs
))
4644 if (operand_check
== check_error
)
4646 i
.error
= invalid_vector_register_set
;
4649 as_warn (_("mask, index, and destination registers should be distinct"));
4651 else if (i
.reg_operands
== 1 && i
.mask
)
4653 if ((i
.types
[1].bitfield
.regymm
4654 || i
.types
[1].bitfield
.regzmm
)
4655 && (register_number (i
.op
[1].regs
)
4656 == register_number (i
.index_reg
)))
4658 if (operand_check
== check_error
)
4660 i
.error
= invalid_vector_register_set
;
4663 if (operand_check
!= check_none
)
4664 as_warn (_("index and destination registers should be distinct"));
4669 /* Check if broadcast is supported by the instruction and is applied
4670 to the memory operand. */
4673 int broadcasted_opnd_size
;
4675 /* Check if specified broadcast is supported in this instruction,
4676 and it's applied to memory operand of DWORD or QWORD type,
4677 depending on VecESize. */
4678 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4679 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4680 || (t
->opcode_modifier
.vecesize
== 0
4681 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4682 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4683 || (t
->opcode_modifier
.vecesize
== 1
4684 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4685 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4688 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4689 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4690 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4691 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4692 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4693 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4694 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4695 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4696 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4700 if ((broadcasted_opnd_size
== 256
4701 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4702 || (broadcasted_opnd_size
== 512
4703 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4706 i
.error
= unsupported_broadcast
;
4710 /* If broadcast is supported in this instruction, we need to check if
4711 operand of one-element size isn't specified without broadcast. */
4712 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4714 /* Find memory operand. */
4715 for (op
= 0; op
< i
.operands
; op
++)
4716 if (operand_type_check (i
.types
[op
], anymem
))
4718 gas_assert (op
< i
.operands
);
4719 /* Check size of the memory operand. */
4720 if ((t
->opcode_modifier
.vecesize
== 0
4721 && i
.types
[op
].bitfield
.dword
)
4722 || (t
->opcode_modifier
.vecesize
== 1
4723 && i
.types
[op
].bitfield
.qword
))
4725 i
.error
= broadcast_needed
;
4730 /* Check if requested masking is supported. */
4732 && (!t
->opcode_modifier
.masking
4734 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4736 i
.error
= unsupported_masking
;
4740 /* Check if masking is applied to dest operand. */
4741 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4743 i
.error
= mask_not_on_destination
;
4750 if ((i
.rounding
->type
!= saeonly
4751 && !t
->opcode_modifier
.staticrounding
)
4752 || (i
.rounding
->type
== saeonly
4753 && (t
->opcode_modifier
.staticrounding
4754 || !t
->opcode_modifier
.sae
)))
4756 i
.error
= unsupported_rc_sae
;
4759 /* If the instruction has several immediate operands and one of
4760 them is rounding, the rounding operand should be the last
4761 immediate operand. */
4762 if (i
.imm_operands
> 1
4763 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4765 i
.error
= rc_sae_operand_not_last_imm
;
4770 /* Check vector Disp8 operand. */
4771 if (t
->opcode_modifier
.disp8memshift
)
4774 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4776 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4778 for (op
= 0; op
< i
.operands
; op
++)
4779 if (operand_type_check (i
.types
[op
], disp
)
4780 && i
.op
[op
].disps
->X_op
== O_constant
)
4782 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4784 = (i
.disp_encoding
!= disp_encoding_32bit
4785 && fits_in_vec_disp8 (value
));
4786 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4789 i
.types
[op
].bitfield
.vec_disp8
= 1;
4792 /* Vector insn can only have Vec_Disp8/Disp32 in
4793 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4795 i
.types
[op
].bitfield
.disp8
= 0;
4796 if (flag_code
!= CODE_16BIT
)
4797 i
.types
[op
].bitfield
.disp16
= 0;
4800 else if (flag_code
!= CODE_16BIT
)
4802 /* One form of this instruction supports vector Disp8.
4803 Try vector Disp8 if we need to use Disp32. */
4804 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4806 i
.error
= try_vector_disp8
;
4818 /* Check if operands are valid for the instruction. Update VEX
4822 VEX_check_operands (const insn_template
*t
)
4824 if (i
.vec_encoding
== vex_encoding_evex
)
4826 /* This instruction must be encoded with EVEX prefix. */
4827 if (!t
->opcode_modifier
.evex
)
4829 i
.error
= unsupported
;
4835 if (!t
->opcode_modifier
.vex
)
4837 /* This instruction template doesn't have VEX prefix. */
4838 if (i
.vec_encoding
!= vex_encoding_default
)
4840 i
.error
= unsupported
;
4846 /* Only check VEX_Imm4, which must be the first operand. */
4847 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4849 if (i
.op
[0].imms
->X_op
!= O_constant
4850 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4856 /* Turn off Imm8 so that update_imm won't complain. */
4857 i
.types
[0] = vec_imm4
;
4863 static const insn_template
*
4864 match_template (char mnem_suffix
)
4866 /* Points to template once we've found it. */
4867 const insn_template
*t
;
4868 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4869 i386_operand_type overlap4
;
4870 unsigned int found_reverse_match
;
4871 i386_opcode_modifier suffix_check
, mnemsuf_check
;
4872 i386_operand_type operand_types
[MAX_OPERANDS
];
4873 int addr_prefix_disp
;
4875 unsigned int found_cpu_match
;
4876 unsigned int check_register
;
4877 enum i386_error specific_error
= 0;
4879 #if MAX_OPERANDS != 5
4880 # error "MAX_OPERANDS must be 5."
4883 found_reverse_match
= 0;
4884 addr_prefix_disp
= -1;
4886 memset (&suffix_check
, 0, sizeof (suffix_check
));
4887 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4888 suffix_check
.no_bsuf
= 1;
4889 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4890 suffix_check
.no_wsuf
= 1;
4891 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4892 suffix_check
.no_ssuf
= 1;
4893 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4894 suffix_check
.no_lsuf
= 1;
4895 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4896 suffix_check
.no_qsuf
= 1;
4897 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4898 suffix_check
.no_ldsuf
= 1;
4900 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
4903 switch (mnem_suffix
)
4905 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
4906 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
4907 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
4908 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
4909 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
4913 /* Must have right number of operands. */
4914 i
.error
= number_of_operands_mismatch
;
4916 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4918 addr_prefix_disp
= -1;
4920 if (i
.operands
!= t
->operands
)
4923 /* Check processor support. */
4924 i
.error
= unsupported
;
4925 found_cpu_match
= (cpu_flags_match (t
)
4926 == CPU_FLAGS_PERFECT_MATCH
);
4927 if (!found_cpu_match
)
4930 /* Check old gcc support. */
4931 i
.error
= old_gcc_only
;
4932 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4935 /* Check AT&T mnemonic. */
4936 i
.error
= unsupported_with_intel_mnemonic
;
4937 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4940 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4941 i
.error
= unsupported_syntax
;
4942 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4943 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
4944 || (intel64
&& t
->opcode_modifier
.amd64
)
4945 || (!intel64
&& t
->opcode_modifier
.intel64
))
4948 /* Check the suffix, except for some instructions in intel mode. */
4949 i
.error
= invalid_instruction_suffix
;
4950 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4951 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4952 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4953 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4954 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4955 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4956 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4958 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4959 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
4960 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
4961 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
4962 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
4963 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
4964 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
4967 if (!operand_size_match (t
))
4970 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4971 operand_types
[j
] = t
->operand_types
[j
];
4973 /* In general, don't allow 64-bit operands in 32-bit mode. */
4974 if (i
.suffix
== QWORD_MNEM_SUFFIX
4975 && flag_code
!= CODE_64BIT
4977 ? (!t
->opcode_modifier
.ignoresize
4978 && !intel_float_operand (t
->name
))
4979 : intel_float_operand (t
->name
) != 2)
4980 && ((!operand_types
[0].bitfield
.regmmx
4981 && !operand_types
[0].bitfield
.regxmm
4982 && !operand_types
[0].bitfield
.regymm
4983 && !operand_types
[0].bitfield
.regzmm
)
4984 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4985 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4986 && operand_types
[t
->operands
> 1].bitfield
.regymm
4987 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4988 && (t
->base_opcode
!= 0x0fc7
4989 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4992 /* In general, don't allow 32-bit operands on pre-386. */
4993 else if (i
.suffix
== LONG_MNEM_SUFFIX
4994 && !cpu_arch_flags
.bitfield
.cpui386
4996 ? (!t
->opcode_modifier
.ignoresize
4997 && !intel_float_operand (t
->name
))
4998 : intel_float_operand (t
->name
) != 2)
4999 && ((!operand_types
[0].bitfield
.regmmx
5000 && !operand_types
[0].bitfield
.regxmm
)
5001 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5002 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
5005 /* Do not verify operands when there are none. */
5009 /* We've found a match; break out of loop. */
5013 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5014 into Disp32/Disp16/Disp32 operand. */
5015 if (i
.prefix
[ADDR_PREFIX
] != 0)
5017 /* There should be only one Disp operand. */
5021 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5023 if (operand_types
[j
].bitfield
.disp16
)
5025 addr_prefix_disp
= j
;
5026 operand_types
[j
].bitfield
.disp32
= 1;
5027 operand_types
[j
].bitfield
.disp16
= 0;
5033 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5035 if (operand_types
[j
].bitfield
.disp32
)
5037 addr_prefix_disp
= j
;
5038 operand_types
[j
].bitfield
.disp32
= 0;
5039 operand_types
[j
].bitfield
.disp16
= 1;
5045 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5047 if (operand_types
[j
].bitfield
.disp64
)
5049 addr_prefix_disp
= j
;
5050 operand_types
[j
].bitfield
.disp64
= 0;
5051 operand_types
[j
].bitfield
.disp32
= 1;
5059 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5060 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5063 /* We check register size if needed. */
5064 check_register
= t
->opcode_modifier
.checkregsize
;
5065 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5066 switch (t
->operands
)
5069 if (!operand_type_match (overlap0
, i
.types
[0]))
5073 /* xchg %eax, %eax is a special case. It is an alias for nop
5074 only in 32bit mode and we can use opcode 0x90. In 64bit
5075 mode, we can't use 0x90 for xchg %eax, %eax since it should
5076 zero-extend %eax to %rax. */
5077 if (flag_code
== CODE_64BIT
5078 && t
->base_opcode
== 0x90
5079 && operand_type_equal (&i
.types
[0], &acc32
)
5080 && operand_type_equal (&i
.types
[1], &acc32
))
5082 /* If we want store form, we reverse direction of operands. */
5083 if (i
.dir_encoding
== dir_encoding_store
5084 && t
->opcode_modifier
.d
)
5089 /* If we want store form, we skip the current load. */
5090 if (i
.dir_encoding
== dir_encoding_store
5091 && i
.mem_operands
== 0
5092 && t
->opcode_modifier
.load
)
5097 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5098 if (!operand_type_match (overlap0
, i
.types
[0])
5099 || !operand_type_match (overlap1
, i
.types
[1])
5101 && !operand_type_register_match (overlap0
, i
.types
[0],
5103 overlap1
, i
.types
[1],
5106 /* Check if other direction is valid ... */
5107 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
5111 /* Try reversing direction of operands. */
5112 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5113 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5114 if (!operand_type_match (overlap0
, i
.types
[0])
5115 || !operand_type_match (overlap1
, i
.types
[1])
5117 && !operand_type_register_match (overlap0
,
5124 /* Does not match either direction. */
5127 /* found_reverse_match holds which of D or FloatDR
5129 if (t
->opcode_modifier
.d
)
5130 found_reverse_match
= Opcode_D
;
5131 else if (t
->opcode_modifier
.floatd
)
5132 found_reverse_match
= Opcode_FloatD
;
5134 found_reverse_match
= 0;
5135 if (t
->opcode_modifier
.floatr
)
5136 found_reverse_match
|= Opcode_FloatR
;
5140 /* Found a forward 2 operand match here. */
5141 switch (t
->operands
)
5144 overlap4
= operand_type_and (i
.types
[4],
5148 overlap3
= operand_type_and (i
.types
[3],
5152 overlap2
= operand_type_and (i
.types
[2],
5157 switch (t
->operands
)
5160 if (!operand_type_match (overlap4
, i
.types
[4])
5161 || !operand_type_register_match (overlap3
,
5170 if (!operand_type_match (overlap3
, i
.types
[3])
5172 && !operand_type_register_match (overlap2
,
5181 /* Here we make use of the fact that there are no
5182 reverse match 3 operand instructions, and all 3
5183 operand instructions only need to be checked for
5184 register consistency between operands 2 and 3. */
5185 if (!operand_type_match (overlap2
, i
.types
[2])
5187 && !operand_type_register_match (overlap1
,
5197 /* Found either forward/reverse 2, 3 or 4 operand match here:
5198 slip through to break. */
5200 if (!found_cpu_match
)
5202 found_reverse_match
= 0;
5206 /* Check if vector and VEX operands are valid. */
5207 if (check_VecOperands (t
) || VEX_check_operands (t
))
5209 specific_error
= i
.error
;
5213 /* We've found a match; break out of loop. */
5217 if (t
== current_templates
->end
)
5219 /* We found no match. */
5220 const char *err_msg
;
5221 switch (specific_error
? specific_error
: i
.error
)
5225 case operand_size_mismatch
:
5226 err_msg
= _("operand size mismatch");
5228 case operand_type_mismatch
:
5229 err_msg
= _("operand type mismatch");
5231 case register_type_mismatch
:
5232 err_msg
= _("register type mismatch");
5234 case number_of_operands_mismatch
:
5235 err_msg
= _("number of operands mismatch");
5237 case invalid_instruction_suffix
:
5238 err_msg
= _("invalid instruction suffix");
5241 err_msg
= _("constant doesn't fit in 4 bits");
5244 err_msg
= _("only supported with old gcc");
5246 case unsupported_with_intel_mnemonic
:
5247 err_msg
= _("unsupported with Intel mnemonic");
5249 case unsupported_syntax
:
5250 err_msg
= _("unsupported syntax");
5253 as_bad (_("unsupported instruction `%s'"),
5254 current_templates
->start
->name
);
5256 case invalid_vsib_address
:
5257 err_msg
= _("invalid VSIB address");
5259 case invalid_vector_register_set
:
5260 err_msg
= _("mask, index, and destination registers must be distinct");
5262 case unsupported_vector_index_register
:
5263 err_msg
= _("unsupported vector index register");
5265 case unsupported_broadcast
:
5266 err_msg
= _("unsupported broadcast");
5268 case broadcast_not_on_src_operand
:
5269 err_msg
= _("broadcast not on source memory operand");
5271 case broadcast_needed
:
5272 err_msg
= _("broadcast is needed for operand of such type");
5274 case unsupported_masking
:
5275 err_msg
= _("unsupported masking");
5277 case mask_not_on_destination
:
5278 err_msg
= _("mask not on destination operand");
5280 case no_default_mask
:
5281 err_msg
= _("default mask isn't allowed");
5283 case unsupported_rc_sae
:
5284 err_msg
= _("unsupported static rounding/sae");
5286 case rc_sae_operand_not_last_imm
:
5288 err_msg
= _("RC/SAE operand must precede immediate operands");
5290 err_msg
= _("RC/SAE operand must follow immediate operands");
5292 case invalid_register_operand
:
5293 err_msg
= _("invalid register operand");
5296 as_bad (_("%s for `%s'"), err_msg
,
5297 current_templates
->start
->name
);
5301 if (!quiet_warnings
)
5304 && (i
.types
[0].bitfield
.jumpabsolute
5305 != operand_types
[0].bitfield
.jumpabsolute
))
5307 as_warn (_("indirect %s without `*'"), t
->name
);
5310 if (t
->opcode_modifier
.isprefix
5311 && t
->opcode_modifier
.ignoresize
)
5313 /* Warn them that a data or address size prefix doesn't
5314 affect assembly of the next line of code. */
5315 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5319 /* Copy the template we found. */
5322 if (addr_prefix_disp
!= -1)
5323 i
.tm
.operand_types
[addr_prefix_disp
]
5324 = operand_types
[addr_prefix_disp
];
5326 if (found_reverse_match
)
5328 /* If we found a reverse match we must alter the opcode
5329 direction bit. found_reverse_match holds bits to change
5330 (different for int & float insns). */
5332 i
.tm
.base_opcode
^= found_reverse_match
;
5334 i
.tm
.operand_types
[0] = operand_types
[1];
5335 i
.tm
.operand_types
[1] = operand_types
[0];
5344 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5345 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5347 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5349 as_bad (_("`%s' operand %d must use `%ses' segment"),
5355 /* There's only ever one segment override allowed per instruction.
5356 This instruction possibly has a legal segment override on the
5357 second operand, so copy the segment to where non-string
5358 instructions store it, allowing common code. */
5359 i
.seg
[0] = i
.seg
[1];
5361 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5363 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5365 as_bad (_("`%s' operand %d must use `%ses' segment"),
5376 process_suffix (void)
5378 /* If matched instruction specifies an explicit instruction mnemonic
5380 if (i
.tm
.opcode_modifier
.size16
)
5381 i
.suffix
= WORD_MNEM_SUFFIX
;
5382 else if (i
.tm
.opcode_modifier
.size32
)
5383 i
.suffix
= LONG_MNEM_SUFFIX
;
5384 else if (i
.tm
.opcode_modifier
.size64
)
5385 i
.suffix
= QWORD_MNEM_SUFFIX
;
5386 else if (i
.reg_operands
)
5388 /* If there's no instruction mnemonic suffix we try to invent one
5389 based on register operands. */
5392 /* We take i.suffix from the last register operand specified,
5393 Destination register type is more significant than source
5394 register type. crc32 in SSE4.2 prefers source register
5396 if (i
.tm
.base_opcode
== 0xf20f38f1)
5398 if (i
.types
[0].bitfield
.reg16
)
5399 i
.suffix
= WORD_MNEM_SUFFIX
;
5400 else if (i
.types
[0].bitfield
.reg32
)
5401 i
.suffix
= LONG_MNEM_SUFFIX
;
5402 else if (i
.types
[0].bitfield
.reg64
)
5403 i
.suffix
= QWORD_MNEM_SUFFIX
;
5405 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5407 if (i
.types
[0].bitfield
.reg8
)
5408 i
.suffix
= BYTE_MNEM_SUFFIX
;
5415 if (i
.tm
.base_opcode
== 0xf20f38f1
5416 || i
.tm
.base_opcode
== 0xf20f38f0)
5418 /* We have to know the operand size for crc32. */
5419 as_bad (_("ambiguous memory operand size for `%s`"),
5424 for (op
= i
.operands
; --op
>= 0;)
5425 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5427 if (i
.types
[op
].bitfield
.reg8
)
5429 i
.suffix
= BYTE_MNEM_SUFFIX
;
5432 else if (i
.types
[op
].bitfield
.reg16
)
5434 i
.suffix
= WORD_MNEM_SUFFIX
;
5437 else if (i
.types
[op
].bitfield
.reg32
)
5439 i
.suffix
= LONG_MNEM_SUFFIX
;
5442 else if (i
.types
[op
].bitfield
.reg64
)
5444 i
.suffix
= QWORD_MNEM_SUFFIX
;
5450 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5453 && i
.tm
.opcode_modifier
.ignoresize
5454 && i
.tm
.opcode_modifier
.no_bsuf
)
5456 else if (!check_byte_reg ())
5459 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5462 && i
.tm
.opcode_modifier
.ignoresize
5463 && i
.tm
.opcode_modifier
.no_lsuf
)
5465 else if (!check_long_reg ())
5468 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5471 && i
.tm
.opcode_modifier
.ignoresize
5472 && i
.tm
.opcode_modifier
.no_qsuf
)
5474 else if (!check_qword_reg ())
5477 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5480 && i
.tm
.opcode_modifier
.ignoresize
5481 && i
.tm
.opcode_modifier
.no_wsuf
)
5483 else if (!check_word_reg ())
5486 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5487 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5488 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5490 /* Skip if the instruction has x/y/z suffix. match_template
5491 should check if it is a valid suffix. */
5493 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5494 /* Do nothing if the instruction is going to ignore the prefix. */
5499 else if (i
.tm
.opcode_modifier
.defaultsize
5501 /* exclude fldenv/frstor/fsave/fstenv */
5502 && i
.tm
.opcode_modifier
.no_ssuf
)
5504 i
.suffix
= stackop_size
;
5506 else if (intel_syntax
5508 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5509 || i
.tm
.opcode_modifier
.jumpbyte
5510 || i
.tm
.opcode_modifier
.jumpintersegment
5511 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5512 && i
.tm
.extension_opcode
<= 3)))
5517 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5519 i
.suffix
= QWORD_MNEM_SUFFIX
;
5524 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5525 i
.suffix
= LONG_MNEM_SUFFIX
;
5528 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5529 i
.suffix
= WORD_MNEM_SUFFIX
;
5538 if (i
.tm
.opcode_modifier
.w
)
5540 as_bad (_("no instruction mnemonic suffix given and "
5541 "no register operands; can't size instruction"));
5547 unsigned int suffixes
;
5549 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5550 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5552 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5554 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5556 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5558 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5561 /* There are more than suffix matches. */
5562 if (i
.tm
.opcode_modifier
.w
5563 || ((suffixes
& (suffixes
- 1))
5564 && !i
.tm
.opcode_modifier
.defaultsize
5565 && !i
.tm
.opcode_modifier
.ignoresize
))
5567 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5573 /* Change the opcode based on the operand size given by i.suffix;
5574 We don't need to change things for byte insns. */
5577 && i
.suffix
!= BYTE_MNEM_SUFFIX
5578 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5579 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5580 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5582 /* It's not a byte, select word/dword operation. */
5583 if (i
.tm
.opcode_modifier
.w
)
5585 if (i
.tm
.opcode_modifier
.shortform
)
5586 i
.tm
.base_opcode
|= 8;
5588 i
.tm
.base_opcode
|= 1;
5591 /* Now select between word & dword operations via the operand
5592 size prefix, except for instructions that will ignore this
5594 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5596 /* The address size override prefix changes the size of the
5598 if ((flag_code
== CODE_32BIT
5599 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5600 || (flag_code
!= CODE_32BIT
5601 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5602 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5605 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5606 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5607 && !i
.tm
.opcode_modifier
.ignoresize
5608 && !i
.tm
.opcode_modifier
.floatmf
5609 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5610 || (flag_code
== CODE_64BIT
5611 && i
.tm
.opcode_modifier
.jumpbyte
)))
5613 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5615 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5616 prefix
= ADDR_PREFIX_OPCODE
;
5618 if (!add_prefix (prefix
))
5622 /* Set mode64 for an operand. */
5623 if (i
.suffix
== QWORD_MNEM_SUFFIX
5624 && flag_code
== CODE_64BIT
5625 && !i
.tm
.opcode_modifier
.norex64
)
5627 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5628 need rex64. cmpxchg8b is also a special case. */
5629 if (! (i
.operands
== 2
5630 && i
.tm
.base_opcode
== 0x90
5631 && i
.tm
.extension_opcode
== None
5632 && operand_type_equal (&i
.types
[0], &acc64
)
5633 && operand_type_equal (&i
.types
[1], &acc64
))
5634 && ! (i
.operands
== 1
5635 && i
.tm
.base_opcode
== 0xfc7
5636 && i
.tm
.extension_opcode
== 1
5637 && !operand_type_check (i
.types
[0], reg
)
5638 && operand_type_check (i
.types
[0], anymem
)))
5642 /* Size floating point instruction. */
5643 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5644 if (i
.tm
.opcode_modifier
.floatmf
)
5645 i
.tm
.base_opcode
^= 4;
5652 check_byte_reg (void)
5656 for (op
= i
.operands
; --op
>= 0;)
5658 /* If this is an eight bit register, it's OK. If it's the 16 or
5659 32 bit version of an eight bit register, we will just use the
5660 low portion, and that's OK too. */
5661 if (i
.types
[op
].bitfield
.reg8
)
5664 /* I/O port address operands are OK too. */
5665 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5668 /* crc32 doesn't generate this warning. */
5669 if (i
.tm
.base_opcode
== 0xf20f38f0)
5672 if ((i
.types
[op
].bitfield
.reg16
5673 || i
.types
[op
].bitfield
.reg32
5674 || i
.types
[op
].bitfield
.reg64
)
5675 && i
.op
[op
].regs
->reg_num
< 4
5676 /* Prohibit these changes in 64bit mode, since the lowering
5677 would be more complicated. */
5678 && flag_code
!= CODE_64BIT
)
5680 #if REGISTER_WARNINGS
5681 if (!quiet_warnings
)
5682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5684 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5685 ? REGNAM_AL
- REGNAM_AX
5686 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5688 i
.op
[op
].regs
->reg_name
,
5693 /* Any other register is bad. */
5694 if (i
.types
[op
].bitfield
.reg16
5695 || i
.types
[op
].bitfield
.reg32
5696 || i
.types
[op
].bitfield
.reg64
5697 || i
.types
[op
].bitfield
.regmmx
5698 || i
.types
[op
].bitfield
.regxmm
5699 || i
.types
[op
].bitfield
.regymm
5700 || i
.types
[op
].bitfield
.regzmm
5701 || i
.types
[op
].bitfield
.sreg2
5702 || i
.types
[op
].bitfield
.sreg3
5703 || i
.types
[op
].bitfield
.control
5704 || i
.types
[op
].bitfield
.debug
5705 || i
.types
[op
].bitfield
.test
5706 || i
.types
[op
].bitfield
.floatreg
5707 || i
.types
[op
].bitfield
.floatacc
)
5709 as_bad (_("`%s%s' not allowed with `%s%c'"),
5711 i
.op
[op
].regs
->reg_name
,
5721 check_long_reg (void)
5725 for (op
= i
.operands
; --op
>= 0;)
5726 /* Reject eight bit registers, except where the template requires
5727 them. (eg. movzb) */
5728 if (i
.types
[op
].bitfield
.reg8
5729 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5730 || i
.tm
.operand_types
[op
].bitfield
.reg32
5731 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5733 as_bad (_("`%s%s' not allowed with `%s%c'"),
5735 i
.op
[op
].regs
->reg_name
,
5740 /* Warn if the e prefix on a general reg is missing. */
5741 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5742 && i
.types
[op
].bitfield
.reg16
5743 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5744 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5746 /* Prohibit these changes in the 64bit mode, since the
5747 lowering is more complicated. */
5748 if (flag_code
== CODE_64BIT
)
5750 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5751 register_prefix
, i
.op
[op
].regs
->reg_name
,
5755 #if REGISTER_WARNINGS
5756 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5758 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5759 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5762 /* Warn if the r prefix on a general reg is present. */
5763 else if (i
.types
[op
].bitfield
.reg64
5764 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5765 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5768 && i
.tm
.opcode_modifier
.toqword
5769 && !i
.types
[0].bitfield
.regxmm
)
5771 /* Convert to QWORD. We want REX byte. */
5772 i
.suffix
= QWORD_MNEM_SUFFIX
;
5776 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5777 register_prefix
, i
.op
[op
].regs
->reg_name
,
5786 check_qword_reg (void)
5790 for (op
= i
.operands
; --op
>= 0; )
5791 /* Reject eight bit registers, except where the template requires
5792 them. (eg. movzb) */
5793 if (i
.types
[op
].bitfield
.reg8
5794 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5795 || i
.tm
.operand_types
[op
].bitfield
.reg32
5796 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5798 as_bad (_("`%s%s' not allowed with `%s%c'"),
5800 i
.op
[op
].regs
->reg_name
,
5805 /* Warn if the r prefix on a general reg is missing. */
5806 else if ((i
.types
[op
].bitfield
.reg16
5807 || i
.types
[op
].bitfield
.reg32
)
5808 && (i
.tm
.operand_types
[op
].bitfield
.reg64
5809 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5811 /* Prohibit these changes in the 64bit mode, since the
5812 lowering is more complicated. */
5814 && i
.tm
.opcode_modifier
.todword
5815 && !i
.types
[0].bitfield
.regxmm
)
5817 /* Convert to DWORD. We don't want REX byte. */
5818 i
.suffix
= LONG_MNEM_SUFFIX
;
5822 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5823 register_prefix
, i
.op
[op
].regs
->reg_name
,
5832 check_word_reg (void)
5835 for (op
= i
.operands
; --op
>= 0;)
5836 /* Reject eight bit registers, except where the template requires
5837 them. (eg. movzb) */
5838 if (i
.types
[op
].bitfield
.reg8
5839 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5840 || i
.tm
.operand_types
[op
].bitfield
.reg32
5841 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5843 as_bad (_("`%s%s' not allowed with `%s%c'"),
5845 i
.op
[op
].regs
->reg_name
,
5850 /* Warn if the e or r prefix on a general reg is present. */
5851 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5852 && (i
.types
[op
].bitfield
.reg32
5853 || i
.types
[op
].bitfield
.reg64
)
5854 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5855 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5857 /* Prohibit these changes in the 64bit mode, since the
5858 lowering is more complicated. */
5859 if (flag_code
== CODE_64BIT
)
5861 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5862 register_prefix
, i
.op
[op
].regs
->reg_name
,
5866 #if REGISTER_WARNINGS
5867 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5869 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5870 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5877 update_imm (unsigned int j
)
5879 i386_operand_type overlap
= i
.types
[j
];
5880 if ((overlap
.bitfield
.imm8
5881 || overlap
.bitfield
.imm8s
5882 || overlap
.bitfield
.imm16
5883 || overlap
.bitfield
.imm32
5884 || overlap
.bitfield
.imm32s
5885 || overlap
.bitfield
.imm64
)
5886 && !operand_type_equal (&overlap
, &imm8
)
5887 && !operand_type_equal (&overlap
, &imm8s
)
5888 && !operand_type_equal (&overlap
, &imm16
)
5889 && !operand_type_equal (&overlap
, &imm32
)
5890 && !operand_type_equal (&overlap
, &imm32s
)
5891 && !operand_type_equal (&overlap
, &imm64
))
5895 i386_operand_type temp
;
5897 operand_type_set (&temp
, 0);
5898 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5900 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5901 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5903 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5904 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5905 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5907 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5908 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5911 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5914 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5915 || operand_type_equal (&overlap
, &imm16_32
)
5916 || operand_type_equal (&overlap
, &imm16_32s
))
5918 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5923 if (!operand_type_equal (&overlap
, &imm8
)
5924 && !operand_type_equal (&overlap
, &imm8s
)
5925 && !operand_type_equal (&overlap
, &imm16
)
5926 && !operand_type_equal (&overlap
, &imm32
)
5927 && !operand_type_equal (&overlap
, &imm32s
)
5928 && !operand_type_equal (&overlap
, &imm64
))
5930 as_bad (_("no instruction mnemonic suffix given; "
5931 "can't determine immediate size"));
5935 i
.types
[j
] = overlap
;
5945 /* Update the first 2 immediate operands. */
5946 n
= i
.operands
> 2 ? 2 : i
.operands
;
5949 for (j
= 0; j
< n
; j
++)
5950 if (update_imm (j
) == 0)
5953 /* The 3rd operand can't be immediate operand. */
5954 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5961 bad_implicit_operand (int xmm
)
5963 const char *ireg
= xmm
? "xmm0" : "ymm0";
5966 as_bad (_("the last operand of `%s' must be `%s%s'"),
5967 i
.tm
.name
, register_prefix
, ireg
);
5969 as_bad (_("the first operand of `%s' must be `%s%s'"),
5970 i
.tm
.name
, register_prefix
, ireg
);
5975 process_operands (void)
5977 /* Default segment register this instruction will use for memory
5978 accesses. 0 means unknown. This is only for optimizing out
5979 unnecessary segment overrides. */
5980 const seg_entry
*default_seg
= 0;
5982 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5984 unsigned int dupl
= i
.operands
;
5985 unsigned int dest
= dupl
- 1;
5988 /* The destination must be an xmm register. */
5989 gas_assert (i
.reg_operands
5990 && MAX_OPERANDS
> dupl
5991 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5993 if (i
.tm
.opcode_modifier
.firstxmm0
)
5995 /* The first operand is implicit and must be xmm0. */
5996 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5997 if (register_number (i
.op
[0].regs
) != 0)
5998 return bad_implicit_operand (1);
6000 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6002 /* Keep xmm0 for instructions with VEX prefix and 3
6008 /* We remove the first xmm0 and keep the number of
6009 operands unchanged, which in fact duplicates the
6011 for (j
= 1; j
< i
.operands
; j
++)
6013 i
.op
[j
- 1] = i
.op
[j
];
6014 i
.types
[j
- 1] = i
.types
[j
];
6015 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6019 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6021 gas_assert ((MAX_OPERANDS
- 1) > dupl
6022 && (i
.tm
.opcode_modifier
.vexsources
6025 /* Add the implicit xmm0 for instructions with VEX prefix
6027 for (j
= i
.operands
; j
> 0; j
--)
6029 i
.op
[j
] = i
.op
[j
- 1];
6030 i
.types
[j
] = i
.types
[j
- 1];
6031 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6034 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6035 i
.types
[0] = regxmm
;
6036 i
.tm
.operand_types
[0] = regxmm
;
6039 i
.reg_operands
+= 2;
6044 i
.op
[dupl
] = i
.op
[dest
];
6045 i
.types
[dupl
] = i
.types
[dest
];
6046 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6055 i
.op
[dupl
] = i
.op
[dest
];
6056 i
.types
[dupl
] = i
.types
[dest
];
6057 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6060 if (i
.tm
.opcode_modifier
.immext
)
6063 else if (i
.tm
.opcode_modifier
.firstxmm0
)
6067 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6068 gas_assert (i
.reg_operands
6069 && (operand_type_equal (&i
.types
[0], ®xmm
)
6070 || operand_type_equal (&i
.types
[0], ®ymm
)
6071 || operand_type_equal (&i
.types
[0], ®zmm
)));
6072 if (register_number (i
.op
[0].regs
) != 0)
6073 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
6075 for (j
= 1; j
< i
.operands
; j
++)
6077 i
.op
[j
- 1] = i
.op
[j
];
6078 i
.types
[j
- 1] = i
.types
[j
];
6080 /* We need to adjust fields in i.tm since they are used by
6081 build_modrm_byte. */
6082 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6089 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6091 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6092 gas_assert (i
.operands
>= 2
6093 && (operand_type_equal (&i
.types
[1], ®xmm
)
6094 || operand_type_equal (&i
.types
[1], ®ymm
)
6095 || operand_type_equal (&i
.types
[1], ®zmm
)));
6096 unsigned int regnum
= register_number (i
.op
[1].regs
);
6097 unsigned int first_reg_in_group
= regnum
& ~3;
6098 unsigned int last_reg_in_group
= first_reg_in_group
+ 3;
6099 if (regnum
!= first_reg_in_group
) {
6100 as_warn (_("the second source register `%s%s' implicitly denotes"
6101 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6102 register_prefix
, i
.op
[1].regs
->reg_name
,
6103 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6104 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6108 else if (i
.tm
.opcode_modifier
.regkludge
)
6110 /* The imul $imm, %reg instruction is converted into
6111 imul $imm, %reg, %reg, and the clr %reg instruction
6112 is converted into xor %reg, %reg. */
6114 unsigned int first_reg_op
;
6116 if (operand_type_check (i
.types
[0], reg
))
6120 /* Pretend we saw the extra register operand. */
6121 gas_assert (i
.reg_operands
== 1
6122 && i
.op
[first_reg_op
+ 1].regs
== 0);
6123 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6124 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6129 if (i
.tm
.opcode_modifier
.shortform
)
6131 if (i
.types
[0].bitfield
.sreg2
6132 || i
.types
[0].bitfield
.sreg3
)
6134 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6135 && i
.op
[0].regs
->reg_num
== 1)
6137 as_bad (_("you can't `pop %scs'"), register_prefix
);
6140 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6141 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6146 /* The register or float register operand is in operand
6150 if (i
.types
[0].bitfield
.floatreg
6151 || operand_type_check (i
.types
[0], reg
))
6155 /* Register goes in low 3 bits of opcode. */
6156 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6157 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6159 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6161 /* Warn about some common errors, but press on regardless.
6162 The first case can be generated by gcc (<= 2.8.1). */
6163 if (i
.operands
== 2)
6165 /* Reversed arguments on faddp, fsubp, etc. */
6166 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6167 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6168 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6172 /* Extraneous `l' suffix on fp insn. */
6173 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6174 register_prefix
, i
.op
[0].regs
->reg_name
);
6179 else if (i
.tm
.opcode_modifier
.modrm
)
6181 /* The opcode is completed (modulo i.tm.extension_opcode which
6182 must be put into the modrm byte). Now, we make the modrm and
6183 index base bytes based on all the info we've collected. */
6185 default_seg
= build_modrm_byte ();
6187 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6191 else if (i
.tm
.opcode_modifier
.isstring
)
6193 /* For the string instructions that allow a segment override
6194 on one of their operands, the default segment is ds. */
6198 if (i
.tm
.base_opcode
== 0x8d /* lea */
6201 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6203 /* If a segment was explicitly specified, and the specified segment
6204 is not the default, use an opcode prefix to select it. If we
6205 never figured out what the default segment is, then default_seg
6206 will be zero at this point, and the specified segment prefix will
6208 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6210 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6216 static const seg_entry
*
6217 build_modrm_byte (void)
6219 const seg_entry
*default_seg
= 0;
6220 unsigned int source
, dest
;
6223 /* The first operand of instructions with VEX prefix and 3 sources
6224 must be VEX_Imm4. */
6225 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6228 unsigned int nds
, reg_slot
;
6231 if (i
.tm
.opcode_modifier
.veximmext
6232 && i
.tm
.opcode_modifier
.immext
)
6234 dest
= i
.operands
- 2;
6235 gas_assert (dest
== 3);
6238 dest
= i
.operands
- 1;
6241 /* There are 2 kinds of instructions:
6242 1. 5 operands: 4 register operands or 3 register operands
6243 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6244 VexW0 or VexW1. The destination must be either XMM, YMM or
6246 2. 4 operands: 4 register operands or 3 register operands
6247 plus 1 memory operand, VexXDS, and VexImmExt */
6248 gas_assert ((i
.reg_operands
== 4
6249 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6250 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6251 && (i
.tm
.opcode_modifier
.veximmext
6252 || (i
.imm_operands
== 1
6253 && i
.types
[0].bitfield
.vec_imm4
6254 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6255 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6256 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6257 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6258 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6260 if (i
.imm_operands
== 0)
6262 /* When there is no immediate operand, generate an 8bit
6263 immediate operand to encode the first operand. */
6264 exp
= &im_expressions
[i
.imm_operands
++];
6265 i
.op
[i
.operands
].imms
= exp
;
6266 i
.types
[i
.operands
] = imm8
;
6268 /* If VexW1 is set, the first operand is the source and
6269 the second operand is encoded in the immediate operand. */
6270 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6281 /* FMA swaps REG and NDS. */
6282 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6290 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6292 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6294 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6296 exp
->X_op
= O_constant
;
6297 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6298 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6302 unsigned int imm_slot
;
6304 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6306 /* If VexW0 is set, the third operand is the source and
6307 the second operand is encoded in the immediate
6314 /* VexW1 is set, the second operand is the source and
6315 the third operand is encoded in the immediate
6321 if (i
.tm
.opcode_modifier
.immext
)
6323 /* When ImmExt is set, the immediate byte is the last
6325 imm_slot
= i
.operands
- 1;
6333 /* Turn on Imm8 so that output_imm will generate it. */
6334 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6337 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6339 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6341 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6343 i
.op
[imm_slot
].imms
->X_add_number
6344 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6345 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6348 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6349 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6351 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6353 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6358 /* i.reg_operands MUST be the number of real register operands;
6359 implicit registers do not count. If there are 3 register
6360 operands, it must be a instruction with VexNDS. For a
6361 instruction with VexNDD, the destination register is encoded
6362 in VEX prefix. If there are 4 register operands, it must be
6363 a instruction with VEX prefix and 3 sources. */
6364 if (i
.mem_operands
== 0
6365 && ((i
.reg_operands
== 2
6366 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6367 || (i
.reg_operands
== 3
6368 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6369 || (i
.reg_operands
== 4 && vex_3_sources
)))
6377 /* When there are 3 operands, one of them may be immediate,
6378 which may be the first or the last operand. Otherwise,
6379 the first operand must be shift count register (cl) or it
6380 is an instruction with VexNDS. */
6381 gas_assert (i
.imm_operands
== 1
6382 || (i
.imm_operands
== 0
6383 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6384 || i
.types
[0].bitfield
.shiftcount
)));
6385 if (operand_type_check (i
.types
[0], imm
)
6386 || i
.types
[0].bitfield
.shiftcount
)
6392 /* When there are 4 operands, the first two must be 8bit
6393 immediate operands. The source operand will be the 3rd
6396 For instructions with VexNDS, if the first operand
6397 an imm8, the source operand is the 2nd one. If the last
6398 operand is imm8, the source operand is the first one. */
6399 gas_assert ((i
.imm_operands
== 2
6400 && i
.types
[0].bitfield
.imm8
6401 && i
.types
[1].bitfield
.imm8
)
6402 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6403 && i
.imm_operands
== 1
6404 && (i
.types
[0].bitfield
.imm8
6405 || i
.types
[i
.operands
- 1].bitfield
.imm8
6407 if (i
.imm_operands
== 2)
6411 if (i
.types
[0].bitfield
.imm8
)
6418 if (i
.tm
.opcode_modifier
.evex
)
6420 /* For EVEX instructions, when there are 5 operands, the
6421 first one must be immediate operand. If the second one
6422 is immediate operand, the source operand is the 3th
6423 one. If the last one is immediate operand, the source
6424 operand is the 2nd one. */
6425 gas_assert (i
.imm_operands
== 2
6426 && i
.tm
.opcode_modifier
.sae
6427 && operand_type_check (i
.types
[0], imm
));
6428 if (operand_type_check (i
.types
[1], imm
))
6430 else if (operand_type_check (i
.types
[4], imm
))
6444 /* RC/SAE operand could be between DEST and SRC. That happens
6445 when one operand is GPR and the other one is XMM/YMM/ZMM
6447 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6450 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6452 /* For instructions with VexNDS, the register-only source
6453 operand must be 32/64bit integer, XMM, YMM or ZMM
6454 register. It is encoded in VEX prefix. We need to
6455 clear RegMem bit before calling operand_type_equal. */
6457 i386_operand_type op
;
6460 /* Check register-only source operand when two source
6461 operands are swapped. */
6462 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6463 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6471 op
= i
.tm
.operand_types
[vvvv
];
6472 op
.bitfield
.regmem
= 0;
6473 if ((dest
+ 1) >= i
.operands
6474 || (!op
.bitfield
.reg32
6475 && op
.bitfield
.reg64
6476 && !operand_type_equal (&op
, ®xmm
)
6477 && !operand_type_equal (&op
, ®ymm
)
6478 && !operand_type_equal (&op
, ®zmm
)
6479 && !operand_type_equal (&op
, ®mask
)))
6481 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6487 /* One of the register operands will be encoded in the i.tm.reg
6488 field, the other in the combined i.tm.mode and i.tm.regmem
6489 fields. If no form of this instruction supports a memory
6490 destination operand, then we assume the source operand may
6491 sometimes be a memory operand and so we need to store the
6492 destination in the i.rm.reg field. */
6493 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6494 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6496 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6497 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6498 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6500 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6502 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6504 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6509 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6510 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6511 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6513 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6515 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6517 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6520 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6522 if (!i
.types
[0].bitfield
.control
6523 && !i
.types
[1].bitfield
.control
)
6525 i
.rex
&= ~(REX_R
| REX_B
);
6526 add_prefix (LOCK_PREFIX_OPCODE
);
6530 { /* If it's not 2 reg operands... */
6535 unsigned int fake_zero_displacement
= 0;
6538 for (op
= 0; op
< i
.operands
; op
++)
6539 if (operand_type_check (i
.types
[op
], anymem
))
6541 gas_assert (op
< i
.operands
);
6543 if (i
.tm
.opcode_modifier
.vecsib
)
6545 if (i
.index_reg
->reg_num
== RegEiz
6546 || i
.index_reg
->reg_num
== RegRiz
)
6549 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6552 i
.sib
.base
= NO_BASE_REGISTER
;
6553 i
.sib
.scale
= i
.log2_scale_factor
;
6554 /* No Vec_Disp8 if there is no base. */
6555 i
.types
[op
].bitfield
.vec_disp8
= 0;
6556 i
.types
[op
].bitfield
.disp8
= 0;
6557 i
.types
[op
].bitfield
.disp16
= 0;
6558 i
.types
[op
].bitfield
.disp64
= 0;
6559 if (flag_code
!= CODE_64BIT
)
6561 /* Must be 32 bit */
6562 i
.types
[op
].bitfield
.disp32
= 1;
6563 i
.types
[op
].bitfield
.disp32s
= 0;
6567 i
.types
[op
].bitfield
.disp32
= 0;
6568 i
.types
[op
].bitfield
.disp32s
= 1;
6571 i
.sib
.index
= i
.index_reg
->reg_num
;
6572 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6574 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6580 if (i
.base_reg
== 0)
6583 if (!i
.disp_operands
)
6585 fake_zero_displacement
= 1;
6586 /* Instructions with VSIB byte need 32bit displacement
6587 if there is no base register. */
6588 if (i
.tm
.opcode_modifier
.vecsib
)
6589 i
.types
[op
].bitfield
.disp32
= 1;
6591 if (i
.index_reg
== 0)
6593 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6594 /* Operand is just <disp> */
6595 if (flag_code
== CODE_64BIT
)
6597 /* 64bit mode overwrites the 32bit absolute
6598 addressing by RIP relative addressing and
6599 absolute addressing is encoded by one of the
6600 redundant SIB forms. */
6601 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6602 i
.sib
.base
= NO_BASE_REGISTER
;
6603 i
.sib
.index
= NO_INDEX_REGISTER
;
6604 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6605 ? disp32s
: disp32
);
6607 else if ((flag_code
== CODE_16BIT
)
6608 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6610 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6611 i
.types
[op
] = disp16
;
6615 i
.rm
.regmem
= NO_BASE_REGISTER
;
6616 i
.types
[op
] = disp32
;
6619 else if (!i
.tm
.opcode_modifier
.vecsib
)
6621 /* !i.base_reg && i.index_reg */
6622 if (i
.index_reg
->reg_num
== RegEiz
6623 || i
.index_reg
->reg_num
== RegRiz
)
6624 i
.sib
.index
= NO_INDEX_REGISTER
;
6626 i
.sib
.index
= i
.index_reg
->reg_num
;
6627 i
.sib
.base
= NO_BASE_REGISTER
;
6628 i
.sib
.scale
= i
.log2_scale_factor
;
6629 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6630 /* No Vec_Disp8 if there is no base. */
6631 i
.types
[op
].bitfield
.vec_disp8
= 0;
6632 i
.types
[op
].bitfield
.disp8
= 0;
6633 i
.types
[op
].bitfield
.disp16
= 0;
6634 i
.types
[op
].bitfield
.disp64
= 0;
6635 if (flag_code
!= CODE_64BIT
)
6637 /* Must be 32 bit */
6638 i
.types
[op
].bitfield
.disp32
= 1;
6639 i
.types
[op
].bitfield
.disp32s
= 0;
6643 i
.types
[op
].bitfield
.disp32
= 0;
6644 i
.types
[op
].bitfield
.disp32s
= 1;
6646 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6650 /* RIP addressing for 64bit mode. */
6651 else if (i
.base_reg
->reg_num
== RegRip
||
6652 i
.base_reg
->reg_num
== RegEip
)
6654 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6655 i
.rm
.regmem
= NO_BASE_REGISTER
;
6656 i
.types
[op
].bitfield
.disp8
= 0;
6657 i
.types
[op
].bitfield
.disp16
= 0;
6658 i
.types
[op
].bitfield
.disp32
= 0;
6659 i
.types
[op
].bitfield
.disp32s
= 1;
6660 i
.types
[op
].bitfield
.disp64
= 0;
6661 i
.types
[op
].bitfield
.vec_disp8
= 0;
6662 i
.flags
[op
] |= Operand_PCrel
;
6663 if (! i
.disp_operands
)
6664 fake_zero_displacement
= 1;
6666 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6668 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6669 switch (i
.base_reg
->reg_num
)
6672 if (i
.index_reg
== 0)
6674 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6675 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6679 if (i
.index_reg
== 0)
6682 if (operand_type_check (i
.types
[op
], disp
) == 0)
6684 /* fake (%bp) into 0(%bp) */
6685 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6686 i
.types
[op
].bitfield
.vec_disp8
= 1;
6688 i
.types
[op
].bitfield
.disp8
= 1;
6689 fake_zero_displacement
= 1;
6692 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6693 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6695 default: /* (%si) -> 4 or (%di) -> 5 */
6696 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6698 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6700 else /* i.base_reg and 32/64 bit mode */
6702 if (flag_code
== CODE_64BIT
6703 && operand_type_check (i
.types
[op
], disp
))
6705 i386_operand_type temp
;
6706 operand_type_set (&temp
, 0);
6707 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6708 temp
.bitfield
.vec_disp8
6709 = i
.types
[op
].bitfield
.vec_disp8
;
6711 if (i
.prefix
[ADDR_PREFIX
] == 0)
6712 i
.types
[op
].bitfield
.disp32s
= 1;
6714 i
.types
[op
].bitfield
.disp32
= 1;
6717 if (!i
.tm
.opcode_modifier
.vecsib
)
6718 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6719 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6721 i
.sib
.base
= i
.base_reg
->reg_num
;
6722 /* x86-64 ignores REX prefix bit here to avoid decoder
6724 if (!(i
.base_reg
->reg_flags
& RegRex
)
6725 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6726 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6728 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6730 fake_zero_displacement
= 1;
6731 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6732 i
.types
[op
].bitfield
.vec_disp8
= 1;
6734 i
.types
[op
].bitfield
.disp8
= 1;
6736 i
.sib
.scale
= i
.log2_scale_factor
;
6737 if (i
.index_reg
== 0)
6739 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6740 /* <disp>(%esp) becomes two byte modrm with no index
6741 register. We've already stored the code for esp
6742 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6743 Any base register besides %esp will not use the
6744 extra modrm byte. */
6745 i
.sib
.index
= NO_INDEX_REGISTER
;
6747 else if (!i
.tm
.opcode_modifier
.vecsib
)
6749 if (i
.index_reg
->reg_num
== RegEiz
6750 || i
.index_reg
->reg_num
== RegRiz
)
6751 i
.sib
.index
= NO_INDEX_REGISTER
;
6753 i
.sib
.index
= i
.index_reg
->reg_num
;
6754 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6755 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6760 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6761 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6765 if (!fake_zero_displacement
6769 fake_zero_displacement
= 1;
6770 if (i
.disp_encoding
== disp_encoding_8bit
)
6771 i
.types
[op
].bitfield
.disp8
= 1;
6773 i
.types
[op
].bitfield
.disp32
= 1;
6775 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6779 if (fake_zero_displacement
)
6781 /* Fakes a zero displacement assuming that i.types[op]
6782 holds the correct displacement size. */
6785 gas_assert (i
.op
[op
].disps
== 0);
6786 exp
= &disp_expressions
[i
.disp_operands
++];
6787 i
.op
[op
].disps
= exp
;
6788 exp
->X_op
= O_constant
;
6789 exp
->X_add_number
= 0;
6790 exp
->X_add_symbol
= (symbolS
*) 0;
6791 exp
->X_op_symbol
= (symbolS
*) 0;
6799 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6801 if (operand_type_check (i
.types
[0], imm
))
6802 i
.vex
.register_specifier
= NULL
;
6805 /* VEX.vvvv encodes one of the sources when the first
6806 operand is not an immediate. */
6807 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6808 i
.vex
.register_specifier
= i
.op
[0].regs
;
6810 i
.vex
.register_specifier
= i
.op
[1].regs
;
6813 /* Destination is a XMM register encoded in the ModRM.reg
6815 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6816 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6819 /* ModRM.rm and VEX.B encodes the other source. */
6820 if (!i
.mem_operands
)
6824 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6825 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6827 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6829 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6833 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6835 i
.vex
.register_specifier
= i
.op
[2].regs
;
6836 if (!i
.mem_operands
)
6839 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6840 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6844 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6845 (if any) based on i.tm.extension_opcode. Again, we must be
6846 careful to make sure that segment/control/debug/test/MMX
6847 registers are coded into the i.rm.reg field. */
6848 else if (i
.reg_operands
)
6851 unsigned int vex_reg
= ~0;
6853 for (op
= 0; op
< i
.operands
; op
++)
6854 if (i
.types
[op
].bitfield
.reg8
6855 || i
.types
[op
].bitfield
.reg16
6856 || i
.types
[op
].bitfield
.reg32
6857 || i
.types
[op
].bitfield
.reg64
6858 || i
.types
[op
].bitfield
.regmmx
6859 || i
.types
[op
].bitfield
.regxmm
6860 || i
.types
[op
].bitfield
.regymm
6861 || i
.types
[op
].bitfield
.regbnd
6862 || i
.types
[op
].bitfield
.regzmm
6863 || i
.types
[op
].bitfield
.regmask
6864 || i
.types
[op
].bitfield
.sreg2
6865 || i
.types
[op
].bitfield
.sreg3
6866 || i
.types
[op
].bitfield
.control
6867 || i
.types
[op
].bitfield
.debug
6868 || i
.types
[op
].bitfield
.test
)
6873 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6875 /* For instructions with VexNDS, the register-only
6876 source operand is encoded in VEX prefix. */
6877 gas_assert (mem
!= (unsigned int) ~0);
6882 gas_assert (op
< i
.operands
);
6886 /* Check register-only source operand when two source
6887 operands are swapped. */
6888 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6889 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6893 gas_assert (mem
== (vex_reg
+ 1)
6894 && op
< i
.operands
);
6899 gas_assert (vex_reg
< i
.operands
);
6903 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6905 /* For instructions with VexNDD, the register destination
6906 is encoded in VEX prefix. */
6907 if (i
.mem_operands
== 0)
6909 /* There is no memory operand. */
6910 gas_assert ((op
+ 2) == i
.operands
);
6915 /* There are only 2 operands. */
6916 gas_assert (op
< 2 && i
.operands
== 2);
6921 gas_assert (op
< i
.operands
);
6923 if (vex_reg
!= (unsigned int) ~0)
6925 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6927 if (type
->bitfield
.reg32
!= 1
6928 && type
->bitfield
.reg64
!= 1
6929 && !operand_type_equal (type
, ®xmm
)
6930 && !operand_type_equal (type
, ®ymm
)
6931 && !operand_type_equal (type
, ®zmm
)
6932 && !operand_type_equal (type
, ®mask
))
6935 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6938 /* Don't set OP operand twice. */
6941 /* If there is an extension opcode to put here, the
6942 register number must be put into the regmem field. */
6943 if (i
.tm
.extension_opcode
!= None
)
6945 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6946 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6948 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6953 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6954 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6956 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6961 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6962 must set it to 3 to indicate this is a register operand
6963 in the regmem field. */
6964 if (!i
.mem_operands
)
6968 /* Fill in i.rm.reg field with extension opcode (if any). */
6969 if (i
.tm
.extension_opcode
!= None
)
6970 i
.rm
.reg
= i
.tm
.extension_opcode
;
6976 output_branch (void)
6982 relax_substateT subtype
;
6986 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6987 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6990 if (i
.prefix
[DATA_PREFIX
] != 0)
6996 /* Pentium4 branch hints. */
6997 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6998 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7003 if (i
.prefix
[REX_PREFIX
] != 0)
7009 /* BND prefixed jump. */
7010 if (i
.prefix
[BND_PREFIX
] != 0)
7012 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7016 if (i
.prefixes
!= 0 && !intel_syntax
)
7017 as_warn (_("skipping prefixes on this instruction"));
7019 /* It's always a symbol; End frag & setup for relax.
7020 Make sure there is enough room in this frag for the largest
7021 instruction we may generate in md_convert_frag. This is 2
7022 bytes for the opcode and room for the prefix and largest
7024 frag_grow (prefix
+ 2 + 4);
7025 /* Prefix and 1 opcode byte go in fr_fix. */
7026 p
= frag_more (prefix
+ 1);
7027 if (i
.prefix
[DATA_PREFIX
] != 0)
7028 *p
++ = DATA_PREFIX_OPCODE
;
7029 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7030 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7031 *p
++ = i
.prefix
[SEG_PREFIX
];
7032 if (i
.prefix
[REX_PREFIX
] != 0)
7033 *p
++ = i
.prefix
[REX_PREFIX
];
7034 *p
= i
.tm
.base_opcode
;
7036 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7037 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7038 else if (cpu_arch_flags
.bitfield
.cpui386
)
7039 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7041 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7044 sym
= i
.op
[0].disps
->X_add_symbol
;
7045 off
= i
.op
[0].disps
->X_add_number
;
7047 if (i
.op
[0].disps
->X_op
!= O_constant
7048 && i
.op
[0].disps
->X_op
!= O_symbol
)
7050 /* Handle complex expressions. */
7051 sym
= make_expr_symbol (i
.op
[0].disps
);
7055 /* 1 possible extra opcode + 4 byte displacement go in var part.
7056 Pass reloc in fr_var. */
7057 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7067 if (i
.tm
.opcode_modifier
.jumpbyte
)
7069 /* This is a loop or jecxz type instruction. */
7071 if (i
.prefix
[ADDR_PREFIX
] != 0)
7073 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7076 /* Pentium4 branch hints. */
7077 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7078 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7080 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7089 if (flag_code
== CODE_16BIT
)
7092 if (i
.prefix
[DATA_PREFIX
] != 0)
7094 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7104 if (i
.prefix
[REX_PREFIX
] != 0)
7106 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7110 /* BND prefixed jump. */
7111 if (i
.prefix
[BND_PREFIX
] != 0)
7113 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7117 if (i
.prefixes
!= 0 && !intel_syntax
)
7118 as_warn (_("skipping prefixes on this instruction"));
7120 p
= frag_more (i
.tm
.opcode_length
+ size
);
7121 switch (i
.tm
.opcode_length
)
7124 *p
++ = i
.tm
.base_opcode
>> 8;
7127 *p
++ = i
.tm
.base_opcode
;
7133 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7134 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
7136 /* All jumps handled here are signed, but don't use a signed limit
7137 check for 32 and 16 bit jumps as we want to allow wrap around at
7138 4G and 64k respectively. */
7140 fixP
->fx_signed
= 1;
7144 output_interseg_jump (void)
7152 if (flag_code
== CODE_16BIT
)
7156 if (i
.prefix
[DATA_PREFIX
] != 0)
7162 if (i
.prefix
[REX_PREFIX
] != 0)
7172 if (i
.prefixes
!= 0 && !intel_syntax
)
7173 as_warn (_("skipping prefixes on this instruction"));
7175 /* 1 opcode; 2 segment; offset */
7176 p
= frag_more (prefix
+ 1 + 2 + size
);
7178 if (i
.prefix
[DATA_PREFIX
] != 0)
7179 *p
++ = DATA_PREFIX_OPCODE
;
7181 if (i
.prefix
[REX_PREFIX
] != 0)
7182 *p
++ = i
.prefix
[REX_PREFIX
];
7184 *p
++ = i
.tm
.base_opcode
;
7185 if (i
.op
[1].imms
->X_op
== O_constant
)
7187 offsetT n
= i
.op
[1].imms
->X_add_number
;
7190 && !fits_in_unsigned_word (n
)
7191 && !fits_in_signed_word (n
))
7193 as_bad (_("16-bit jump out of range"));
7196 md_number_to_chars (p
, n
, size
);
7199 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7200 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7201 if (i
.op
[0].imms
->X_op
!= O_constant
)
7202 as_bad (_("can't handle non absolute segment in `%s'"),
7204 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7210 fragS
*insn_start_frag
;
7211 offsetT insn_start_off
;
7213 /* Tie dwarf2 debug info to the address at the start of the insn.
7214 We can't do this after the insn has been output as the current
7215 frag may have been closed off. eg. by frag_var. */
7216 dwarf2_emit_insn (0);
7218 insn_start_frag
= frag_now
;
7219 insn_start_off
= frag_now_fix ();
7222 if (i
.tm
.opcode_modifier
.jump
)
7224 else if (i
.tm
.opcode_modifier
.jumpbyte
7225 || i
.tm
.opcode_modifier
.jumpdword
)
7227 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7228 output_interseg_jump ();
7231 /* Output normal instructions here. */
7235 unsigned int prefix
;
7238 && i
.tm
.base_opcode
== 0xfae
7240 && i
.imm_operands
== 1
7241 && (i
.op
[0].imms
->X_add_number
== 0xe8
7242 || i
.op
[0].imms
->X_add_number
== 0xf0
7243 || i
.op
[0].imms
->X_add_number
== 0xf8))
7245 /* Encode lfence, mfence, and sfence as
7246 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7247 offsetT val
= 0x240483f0ULL
;
7249 md_number_to_chars (p
, val
, 5);
7253 /* Some processors fail on LOCK prefix. This options makes
7254 assembler ignore LOCK prefix and serves as a workaround. */
7255 if (omit_lock_prefix
)
7257 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7259 i
.prefix
[LOCK_PREFIX
] = 0;
7262 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7263 don't need the explicit prefix. */
7264 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7266 switch (i
.tm
.opcode_length
)
7269 if (i
.tm
.base_opcode
& 0xff000000)
7271 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7276 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7278 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7279 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7282 if (prefix
!= REPE_PREFIX_OPCODE
7283 || (i
.prefix
[REP_PREFIX
]
7284 != REPE_PREFIX_OPCODE
))
7285 add_prefix (prefix
);
7288 add_prefix (prefix
);
7297 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7298 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7299 R_X86_64_GOTTPOFF relocation so that linker can safely
7300 perform IE->LE optimization. */
7301 if (x86_elf_abi
== X86_64_X32_ABI
7303 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7304 && i
.prefix
[REX_PREFIX
] == 0)
7305 add_prefix (REX_OPCODE
);
7308 /* The prefix bytes. */
7309 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7311 FRAG_APPEND_1_CHAR (*q
);
7315 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7320 /* REX byte is encoded in VEX prefix. */
7324 FRAG_APPEND_1_CHAR (*q
);
7327 /* There should be no other prefixes for instructions
7332 /* For EVEX instructions i.vrex should become 0 after
7333 build_evex_prefix. For VEX instructions upper 16 registers
7334 aren't available, so VREX should be 0. */
7337 /* Now the VEX prefix. */
7338 p
= frag_more (i
.vex
.length
);
7339 for (j
= 0; j
< i
.vex
.length
; j
++)
7340 p
[j
] = i
.vex
.bytes
[j
];
7343 /* Now the opcode; be careful about word order here! */
7344 if (i
.tm
.opcode_length
== 1)
7346 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7350 switch (i
.tm
.opcode_length
)
7354 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7355 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7359 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7369 /* Put out high byte first: can't use md_number_to_chars! */
7370 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7371 *p
= i
.tm
.base_opcode
& 0xff;
7374 /* Now the modrm byte and sib byte (if present). */
7375 if (i
.tm
.opcode_modifier
.modrm
)
7377 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7380 /* If i.rm.regmem == ESP (4)
7381 && i.rm.mode != (Register mode)
7383 ==> need second modrm byte. */
7384 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7386 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7387 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7389 | i
.sib
.scale
<< 6));
7392 if (i
.disp_operands
)
7393 output_disp (insn_start_frag
, insn_start_off
);
7396 output_imm (insn_start_frag
, insn_start_off
);
7402 pi ("" /*line*/, &i
);
7404 #endif /* DEBUG386 */
7407 /* Return the size of the displacement operand N. */
7410 disp_size (unsigned int n
)
7414 /* Vec_Disp8 has to be 8bit. */
7415 if (i
.types
[n
].bitfield
.vec_disp8
)
7417 else if (i
.types
[n
].bitfield
.disp64
)
7419 else if (i
.types
[n
].bitfield
.disp8
)
7421 else if (i
.types
[n
].bitfield
.disp16
)
7426 /* Return the size of the immediate operand N. */
7429 imm_size (unsigned int n
)
7432 if (i
.types
[n
].bitfield
.imm64
)
7434 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7436 else if (i
.types
[n
].bitfield
.imm16
)
7442 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7447 for (n
= 0; n
< i
.operands
; n
++)
7449 if (i
.types
[n
].bitfield
.vec_disp8
7450 || operand_type_check (i
.types
[n
], disp
))
7452 if (i
.op
[n
].disps
->X_op
== O_constant
)
7454 int size
= disp_size (n
);
7455 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7457 if (i
.types
[n
].bitfield
.vec_disp8
)
7459 val
= offset_in_range (val
, size
);
7460 p
= frag_more (size
);
7461 md_number_to_chars (p
, val
, size
);
7465 enum bfd_reloc_code_real reloc_type
;
7466 int size
= disp_size (n
);
7467 int sign
= i
.types
[n
].bitfield
.disp32s
;
7468 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7471 /* We can't have 8 bit displacement here. */
7472 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7474 /* The PC relative address is computed relative
7475 to the instruction boundary, so in case immediate
7476 fields follows, we need to adjust the value. */
7477 if (pcrel
&& i
.imm_operands
)
7482 for (n1
= 0; n1
< i
.operands
; n1
++)
7483 if (operand_type_check (i
.types
[n1
], imm
))
7485 /* Only one immediate is allowed for PC
7486 relative address. */
7487 gas_assert (sz
== 0);
7489 i
.op
[n
].disps
->X_add_number
-= sz
;
7491 /* We should find the immediate. */
7492 gas_assert (sz
!= 0);
7495 p
= frag_more (size
);
7496 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7498 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7499 && (((reloc_type
== BFD_RELOC_32
7500 || reloc_type
== BFD_RELOC_X86_64_32S
7501 || (reloc_type
== BFD_RELOC_64
7503 && (i
.op
[n
].disps
->X_op
== O_symbol
7504 || (i
.op
[n
].disps
->X_op
== O_add
7505 && ((symbol_get_value_expression
7506 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7508 || reloc_type
== BFD_RELOC_32_PCREL
))
7512 if (insn_start_frag
== frag_now
)
7513 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7518 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7519 for (fr
= insn_start_frag
->fr_next
;
7520 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7522 add
+= p
- frag_now
->fr_literal
;
7527 reloc_type
= BFD_RELOC_386_GOTPC
;
7528 i
.op
[n
].imms
->X_add_number
+= add
;
7530 else if (reloc_type
== BFD_RELOC_64
)
7531 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7533 /* Don't do the adjustment for x86-64, as there
7534 the pcrel addressing is relative to the _next_
7535 insn, and that is taken care of in other code. */
7536 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7538 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7539 size
, i
.op
[n
].disps
, pcrel
,
7541 /* Check for "call/jmp *mem", "mov mem, %reg",
7542 "test %reg, mem" and "binop mem, %reg" where binop
7543 is one of adc, add, and, cmp, or, sbb, sub, xor
7544 instructions. Always generate R_386_GOT32X for
7545 "sym*GOT" operand in 32-bit mode. */
7546 if ((generate_relax_relocations
7549 && i
.rm
.regmem
== 5))
7551 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7552 && ((i
.operands
== 1
7553 && i
.tm
.base_opcode
== 0xff
7554 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7556 && (i
.tm
.base_opcode
== 0x8b
7557 || i
.tm
.base_opcode
== 0x85
7558 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7562 fixP
->fx_tcbit
= i
.rex
!= 0;
7564 && (i
.base_reg
->reg_num
== RegRip
7565 || i
.base_reg
->reg_num
== RegEip
))
7566 fixP
->fx_tcbit2
= 1;
7569 fixP
->fx_tcbit2
= 1;
7577 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7582 for (n
= 0; n
< i
.operands
; n
++)
7584 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7585 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7588 if (operand_type_check (i
.types
[n
], imm
))
7590 if (i
.op
[n
].imms
->X_op
== O_constant
)
7592 int size
= imm_size (n
);
7595 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7597 p
= frag_more (size
);
7598 md_number_to_chars (p
, val
, size
);
7602 /* Not absolute_section.
7603 Need a 32-bit fixup (don't support 8bit
7604 non-absolute imms). Try to support other
7606 enum bfd_reloc_code_real reloc_type
;
7607 int size
= imm_size (n
);
7610 if (i
.types
[n
].bitfield
.imm32s
7611 && (i
.suffix
== QWORD_MNEM_SUFFIX
7612 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7617 p
= frag_more (size
);
7618 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7620 /* This is tough to explain. We end up with this one if we
7621 * have operands that look like
7622 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7623 * obtain the absolute address of the GOT, and it is strongly
7624 * preferable from a performance point of view to avoid using
7625 * a runtime relocation for this. The actual sequence of
7626 * instructions often look something like:
7631 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7633 * The call and pop essentially return the absolute address
7634 * of the label .L66 and store it in %ebx. The linker itself
7635 * will ultimately change the first operand of the addl so
7636 * that %ebx points to the GOT, but to keep things simple, the
7637 * .o file must have this operand set so that it generates not
7638 * the absolute address of .L66, but the absolute address of
7639 * itself. This allows the linker itself simply treat a GOTPC
7640 * relocation as asking for a pcrel offset to the GOT to be
7641 * added in, and the addend of the relocation is stored in the
7642 * operand field for the instruction itself.
7644 * Our job here is to fix the operand so that it would add
7645 * the correct offset so that %ebx would point to itself. The
7646 * thing that is tricky is that .-.L66 will point to the
7647 * beginning of the instruction, so we need to further modify
7648 * the operand so that it will point to itself. There are
7649 * other cases where you have something like:
7651 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7653 * and here no correction would be required. Internally in
7654 * the assembler we treat operands of this form as not being
7655 * pcrel since the '.' is explicitly mentioned, and I wonder
7656 * whether it would simplify matters to do it this way. Who
7657 * knows. In earlier versions of the PIC patches, the
7658 * pcrel_adjust field was used to store the correction, but
7659 * since the expression is not pcrel, I felt it would be
7660 * confusing to do it this way. */
7662 if ((reloc_type
== BFD_RELOC_32
7663 || reloc_type
== BFD_RELOC_X86_64_32S
7664 || reloc_type
== BFD_RELOC_64
)
7666 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7667 && (i
.op
[n
].imms
->X_op
== O_symbol
7668 || (i
.op
[n
].imms
->X_op
== O_add
7669 && ((symbol_get_value_expression
7670 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7675 if (insn_start_frag
== frag_now
)
7676 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7681 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7682 for (fr
= insn_start_frag
->fr_next
;
7683 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7685 add
+= p
- frag_now
->fr_literal
;
7689 reloc_type
= BFD_RELOC_386_GOTPC
;
7691 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7693 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7694 i
.op
[n
].imms
->X_add_number
+= add
;
7696 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7697 i
.op
[n
].imms
, 0, reloc_type
);
7703 /* x86_cons_fix_new is called via the expression parsing code when a
7704 reloc is needed. We use this hook to get the correct .got reloc. */
7705 static int cons_sign
= -1;
7708 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7709 expressionS
*exp
, bfd_reloc_code_real_type r
)
7711 r
= reloc (len
, 0, cons_sign
, r
);
7714 if (exp
->X_op
== O_secrel
)
7716 exp
->X_op
= O_symbol
;
7717 r
= BFD_RELOC_32_SECREL
;
7721 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7724 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7725 purpose of the `.dc.a' internal pseudo-op. */
7728 x86_address_bytes (void)
7730 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7732 return stdoutput
->arch_info
->bits_per_address
/ 8;
7735 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7737 # define lex_got(reloc, adjust, types) NULL
7739 /* Parse operands of the form
7740 <symbol>@GOTOFF+<nnn>
7741 and similar .plt or .got references.
7743 If we find one, set up the correct relocation in RELOC and copy the
7744 input string, minus the `@GOTOFF' into a malloc'd buffer for
7745 parsing by the calling routine. Return this buffer, and if ADJUST
7746 is non-null set it to the length of the string we removed from the
7747 input line. Otherwise return NULL. */
7749 lex_got (enum bfd_reloc_code_real
*rel
,
7751 i386_operand_type
*types
)
7753 /* Some of the relocations depend on the size of what field is to
7754 be relocated. But in our callers i386_immediate and i386_displacement
7755 we don't yet know the operand size (this will be set by insn
7756 matching). Hence we record the word32 relocation here,
7757 and adjust the reloc according to the real size in reloc(). */
7758 static const struct {
7761 const enum bfd_reloc_code_real rel
[2];
7762 const i386_operand_type types64
;
7764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7765 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7767 OPERAND_TYPE_IMM32_64
},
7769 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7770 BFD_RELOC_X86_64_PLTOFF64
},
7771 OPERAND_TYPE_IMM64
},
7772 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7773 BFD_RELOC_X86_64_PLT32
},
7774 OPERAND_TYPE_IMM32_32S_DISP32
},
7775 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7776 BFD_RELOC_X86_64_GOTPLT64
},
7777 OPERAND_TYPE_IMM64_DISP64
},
7778 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7779 BFD_RELOC_X86_64_GOTOFF64
},
7780 OPERAND_TYPE_IMM64_DISP64
},
7781 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7782 BFD_RELOC_X86_64_GOTPCREL
},
7783 OPERAND_TYPE_IMM32_32S_DISP32
},
7784 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7785 BFD_RELOC_X86_64_TLSGD
},
7786 OPERAND_TYPE_IMM32_32S_DISP32
},
7787 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7788 _dummy_first_bfd_reloc_code_real
},
7789 OPERAND_TYPE_NONE
},
7790 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7791 BFD_RELOC_X86_64_TLSLD
},
7792 OPERAND_TYPE_IMM32_32S_DISP32
},
7793 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7794 BFD_RELOC_X86_64_GOTTPOFF
},
7795 OPERAND_TYPE_IMM32_32S_DISP32
},
7796 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7797 BFD_RELOC_X86_64_TPOFF32
},
7798 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7799 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7800 _dummy_first_bfd_reloc_code_real
},
7801 OPERAND_TYPE_NONE
},
7802 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7803 BFD_RELOC_X86_64_DTPOFF32
},
7804 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7805 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7806 _dummy_first_bfd_reloc_code_real
},
7807 OPERAND_TYPE_NONE
},
7808 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7809 _dummy_first_bfd_reloc_code_real
},
7810 OPERAND_TYPE_NONE
},
7811 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7812 BFD_RELOC_X86_64_GOT32
},
7813 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7814 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7815 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7816 OPERAND_TYPE_IMM32_32S_DISP32
},
7817 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7818 BFD_RELOC_X86_64_TLSDESC_CALL
},
7819 OPERAND_TYPE_IMM32_32S_DISP32
},
7824 #if defined (OBJ_MAYBE_ELF)
7829 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7830 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7833 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7835 int len
= gotrel
[j
].len
;
7836 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7838 if (gotrel
[j
].rel
[object_64bit
] != 0)
7841 char *tmpbuf
, *past_reloc
;
7843 *rel
= gotrel
[j
].rel
[object_64bit
];
7847 if (flag_code
!= CODE_64BIT
)
7849 types
->bitfield
.imm32
= 1;
7850 types
->bitfield
.disp32
= 1;
7853 *types
= gotrel
[j
].types64
;
7856 if (j
!= 0 && GOT_symbol
== NULL
)
7857 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7859 /* The length of the first part of our input line. */
7860 first
= cp
- input_line_pointer
;
7862 /* The second part goes from after the reloc token until
7863 (and including) an end_of_line char or comma. */
7864 past_reloc
= cp
+ 1 + len
;
7866 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7868 second
= cp
+ 1 - past_reloc
;
7870 /* Allocate and copy string. The trailing NUL shouldn't
7871 be necessary, but be safe. */
7872 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7873 memcpy (tmpbuf
, input_line_pointer
, first
);
7874 if (second
!= 0 && *past_reloc
!= ' ')
7875 /* Replace the relocation token with ' ', so that
7876 errors like foo@GOTOFF1 will be detected. */
7877 tmpbuf
[first
++] = ' ';
7879 /* Increment length by 1 if the relocation token is
7884 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7885 tmpbuf
[first
+ second
] = '\0';
7889 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7890 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7895 /* Might be a symbol version string. Don't as_bad here. */
7904 /* Parse operands of the form
7905 <symbol>@SECREL32+<nnn>
7907 If we find one, set up the correct relocation in RELOC and copy the
7908 input string, minus the `@SECREL32' into a malloc'd buffer for
7909 parsing by the calling routine. Return this buffer, and if ADJUST
7910 is non-null set it to the length of the string we removed from the
7911 input line. Otherwise return NULL.
7913 This function is copied from the ELF version above adjusted for PE targets. */
7916 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7917 int *adjust ATTRIBUTE_UNUSED
,
7918 i386_operand_type
*types
)
7924 const enum bfd_reloc_code_real rel
[2];
7925 const i386_operand_type types64
;
7929 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7930 BFD_RELOC_32_SECREL
},
7931 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7937 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7938 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7941 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7943 int len
= gotrel
[j
].len
;
7945 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7947 if (gotrel
[j
].rel
[object_64bit
] != 0)
7950 char *tmpbuf
, *past_reloc
;
7952 *rel
= gotrel
[j
].rel
[object_64bit
];
7958 if (flag_code
!= CODE_64BIT
)
7960 types
->bitfield
.imm32
= 1;
7961 types
->bitfield
.disp32
= 1;
7964 *types
= gotrel
[j
].types64
;
7967 /* The length of the first part of our input line. */
7968 first
= cp
- input_line_pointer
;
7970 /* The second part goes from after the reloc token until
7971 (and including) an end_of_line char or comma. */
7972 past_reloc
= cp
+ 1 + len
;
7974 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7976 second
= cp
+ 1 - past_reloc
;
7978 /* Allocate and copy string. The trailing NUL shouldn't
7979 be necessary, but be safe. */
7980 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7981 memcpy (tmpbuf
, input_line_pointer
, first
);
7982 if (second
!= 0 && *past_reloc
!= ' ')
7983 /* Replace the relocation token with ' ', so that
7984 errors like foo@SECLREL321 will be detected. */
7985 tmpbuf
[first
++] = ' ';
7986 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7987 tmpbuf
[first
+ second
] = '\0';
7991 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7992 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7997 /* Might be a symbol version string. Don't as_bad here. */
8003 bfd_reloc_code_real_type
8004 x86_cons (expressionS
*exp
, int size
)
8006 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8008 intel_syntax
= -intel_syntax
;
8011 if (size
== 4 || (object_64bit
&& size
== 8))
8013 /* Handle @GOTOFF and the like in an expression. */
8015 char *gotfree_input_line
;
8018 save
= input_line_pointer
;
8019 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8020 if (gotfree_input_line
)
8021 input_line_pointer
= gotfree_input_line
;
8025 if (gotfree_input_line
)
8027 /* expression () has merrily parsed up to the end of line,
8028 or a comma - in the wrong buffer. Transfer how far
8029 input_line_pointer has moved to the right buffer. */
8030 input_line_pointer
= (save
8031 + (input_line_pointer
- gotfree_input_line
)
8033 free (gotfree_input_line
);
8034 if (exp
->X_op
== O_constant
8035 || exp
->X_op
== O_absent
8036 || exp
->X_op
== O_illegal
8037 || exp
->X_op
== O_register
8038 || exp
->X_op
== O_big
)
8040 char c
= *input_line_pointer
;
8041 *input_line_pointer
= 0;
8042 as_bad (_("missing or invalid expression `%s'"), save
);
8043 *input_line_pointer
= c
;
8050 intel_syntax
= -intel_syntax
;
8053 i386_intel_simplify (exp
);
8059 signed_cons (int size
)
8061 if (flag_code
== CODE_64BIT
)
8069 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8076 if (exp
.X_op
== O_symbol
)
8077 exp
.X_op
= O_secrel
;
8079 emit_expr (&exp
, 4);
8081 while (*input_line_pointer
++ == ',');
8083 input_line_pointer
--;
8084 demand_empty_rest_of_line ();
8088 /* Handle Vector operations. */
8091 check_VecOperations (char *op_string
, char *op_end
)
8093 const reg_entry
*mask
;
8098 && (op_end
== NULL
|| op_string
< op_end
))
8101 if (*op_string
== '{')
8105 /* Check broadcasts. */
8106 if (strncmp (op_string
, "1to", 3) == 0)
8111 goto duplicated_vec_op
;
8114 if (*op_string
== '8')
8115 bcst_type
= BROADCAST_1TO8
;
8116 else if (*op_string
== '4')
8117 bcst_type
= BROADCAST_1TO4
;
8118 else if (*op_string
== '2')
8119 bcst_type
= BROADCAST_1TO2
;
8120 else if (*op_string
== '1'
8121 && *(op_string
+1) == '6')
8123 bcst_type
= BROADCAST_1TO16
;
8128 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8133 broadcast_op
.type
= bcst_type
;
8134 broadcast_op
.operand
= this_operand
;
8135 i
.broadcast
= &broadcast_op
;
8137 /* Check masking operation. */
8138 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8140 /* k0 can't be used for write mask. */
8141 if (mask
->reg_num
== 0)
8143 as_bad (_("`%s' can't be used for write mask"),
8150 mask_op
.mask
= mask
;
8151 mask_op
.zeroing
= 0;
8152 mask_op
.operand
= this_operand
;
8158 goto duplicated_vec_op
;
8160 i
.mask
->mask
= mask
;
8162 /* Only "{z}" is allowed here. No need to check
8163 zeroing mask explicitly. */
8164 if (i
.mask
->operand
!= this_operand
)
8166 as_bad (_("invalid write mask `%s'"), saved
);
8173 /* Check zeroing-flag for masking operation. */
8174 else if (*op_string
== 'z')
8178 mask_op
.mask
= NULL
;
8179 mask_op
.zeroing
= 1;
8180 mask_op
.operand
= this_operand
;
8185 if (i
.mask
->zeroing
)
8188 as_bad (_("duplicated `%s'"), saved
);
8192 i
.mask
->zeroing
= 1;
8194 /* Only "{%k}" is allowed here. No need to check mask
8195 register explicitly. */
8196 if (i
.mask
->operand
!= this_operand
)
8198 as_bad (_("invalid zeroing-masking `%s'"),
8207 goto unknown_vec_op
;
8209 if (*op_string
!= '}')
8211 as_bad (_("missing `}' in `%s'"), saved
);
8218 /* We don't know this one. */
8219 as_bad (_("unknown vector operation: `%s'"), saved
);
8227 i386_immediate (char *imm_start
)
8229 char *save_input_line_pointer
;
8230 char *gotfree_input_line
;
8233 i386_operand_type types
;
8235 operand_type_set (&types
, ~0);
8237 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8239 as_bad (_("at most %d immediate operands are allowed"),
8240 MAX_IMMEDIATE_OPERANDS
);
8244 exp
= &im_expressions
[i
.imm_operands
++];
8245 i
.op
[this_operand
].imms
= exp
;
8247 if (is_space_char (*imm_start
))
8250 save_input_line_pointer
= input_line_pointer
;
8251 input_line_pointer
= imm_start
;
8253 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8254 if (gotfree_input_line
)
8255 input_line_pointer
= gotfree_input_line
;
8257 exp_seg
= expression (exp
);
8261 /* Handle vector operations. */
8262 if (*input_line_pointer
== '{')
8264 input_line_pointer
= check_VecOperations (input_line_pointer
,
8266 if (input_line_pointer
== NULL
)
8270 if (*input_line_pointer
)
8271 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8273 input_line_pointer
= save_input_line_pointer
;
8274 if (gotfree_input_line
)
8276 free (gotfree_input_line
);
8278 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8279 exp
->X_op
= O_illegal
;
8282 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8286 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8287 i386_operand_type types
, const char *imm_start
)
8289 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8292 as_bad (_("missing or invalid immediate expression `%s'"),
8296 else if (exp
->X_op
== O_constant
)
8298 /* Size it properly later. */
8299 i
.types
[this_operand
].bitfield
.imm64
= 1;
8300 /* If not 64bit, sign extend val. */
8301 if (flag_code
!= CODE_64BIT
8302 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8304 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8306 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8307 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8308 && exp_seg
!= absolute_section
8309 && exp_seg
!= text_section
8310 && exp_seg
!= data_section
8311 && exp_seg
!= bss_section
8312 && exp_seg
!= undefined_section
8313 && !bfd_is_com_section (exp_seg
))
8315 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8319 else if (!intel_syntax
&& exp_seg
== reg_section
)
8322 as_bad (_("illegal immediate register operand %s"), imm_start
);
8327 /* This is an address. The size of the address will be
8328 determined later, depending on destination register,
8329 suffix, or the default for the section. */
8330 i
.types
[this_operand
].bitfield
.imm8
= 1;
8331 i
.types
[this_operand
].bitfield
.imm16
= 1;
8332 i
.types
[this_operand
].bitfield
.imm32
= 1;
8333 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8334 i
.types
[this_operand
].bitfield
.imm64
= 1;
8335 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8343 i386_scale (char *scale
)
8346 char *save
= input_line_pointer
;
8348 input_line_pointer
= scale
;
8349 val
= get_absolute_expression ();
8354 i
.log2_scale_factor
= 0;
8357 i
.log2_scale_factor
= 1;
8360 i
.log2_scale_factor
= 2;
8363 i
.log2_scale_factor
= 3;
8367 char sep
= *input_line_pointer
;
8369 *input_line_pointer
= '\0';
8370 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8372 *input_line_pointer
= sep
;
8373 input_line_pointer
= save
;
8377 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8379 as_warn (_("scale factor of %d without an index register"),
8380 1 << i
.log2_scale_factor
);
8381 i
.log2_scale_factor
= 0;
8383 scale
= input_line_pointer
;
8384 input_line_pointer
= save
;
8389 i386_displacement (char *disp_start
, char *disp_end
)
8393 char *save_input_line_pointer
;
8394 char *gotfree_input_line
;
8396 i386_operand_type bigdisp
, types
= anydisp
;
8399 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8401 as_bad (_("at most %d displacement operands are allowed"),
8402 MAX_MEMORY_OPERANDS
);
8406 operand_type_set (&bigdisp
, 0);
8407 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8408 || (!current_templates
->start
->opcode_modifier
.jump
8409 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8411 bigdisp
.bitfield
.disp32
= 1;
8412 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8413 if (flag_code
== CODE_64BIT
)
8417 bigdisp
.bitfield
.disp32s
= 1;
8418 bigdisp
.bitfield
.disp64
= 1;
8421 else if ((flag_code
== CODE_16BIT
) ^ override
)
8423 bigdisp
.bitfield
.disp32
= 0;
8424 bigdisp
.bitfield
.disp16
= 1;
8429 /* For PC-relative branches, the width of the displacement
8430 is dependent upon data size, not address size. */
8431 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8432 if (flag_code
== CODE_64BIT
)
8434 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8435 bigdisp
.bitfield
.disp16
= 1;
8438 bigdisp
.bitfield
.disp32
= 1;
8439 bigdisp
.bitfield
.disp32s
= 1;
8445 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8447 : LONG_MNEM_SUFFIX
));
8448 bigdisp
.bitfield
.disp32
= 1;
8449 if ((flag_code
== CODE_16BIT
) ^ override
)
8451 bigdisp
.bitfield
.disp32
= 0;
8452 bigdisp
.bitfield
.disp16
= 1;
8456 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8459 exp
= &disp_expressions
[i
.disp_operands
];
8460 i
.op
[this_operand
].disps
= exp
;
8462 save_input_line_pointer
= input_line_pointer
;
8463 input_line_pointer
= disp_start
;
8464 END_STRING_AND_SAVE (disp_end
);
8466 #ifndef GCC_ASM_O_HACK
8467 #define GCC_ASM_O_HACK 0
8470 END_STRING_AND_SAVE (disp_end
+ 1);
8471 if (i
.types
[this_operand
].bitfield
.baseIndex
8472 && displacement_string_end
[-1] == '+')
8474 /* This hack is to avoid a warning when using the "o"
8475 constraint within gcc asm statements.
8478 #define _set_tssldt_desc(n,addr,limit,type) \
8479 __asm__ __volatile__ ( \
8481 "movw %w1,2+%0\n\t" \
8483 "movb %b1,4+%0\n\t" \
8484 "movb %4,5+%0\n\t" \
8485 "movb $0,6+%0\n\t" \
8486 "movb %h1,7+%0\n\t" \
8488 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8490 This works great except that the output assembler ends
8491 up looking a bit weird if it turns out that there is
8492 no offset. You end up producing code that looks like:
8505 So here we provide the missing zero. */
8507 *displacement_string_end
= '0';
8510 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8511 if (gotfree_input_line
)
8512 input_line_pointer
= gotfree_input_line
;
8514 exp_seg
= expression (exp
);
8517 if (*input_line_pointer
)
8518 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8520 RESTORE_END_STRING (disp_end
+ 1);
8522 input_line_pointer
= save_input_line_pointer
;
8523 if (gotfree_input_line
)
8525 free (gotfree_input_line
);
8527 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8528 exp
->X_op
= O_illegal
;
8531 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8533 RESTORE_END_STRING (disp_end
);
8539 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8540 i386_operand_type types
, const char *disp_start
)
8542 i386_operand_type bigdisp
;
8545 /* We do this to make sure that the section symbol is in
8546 the symbol table. We will ultimately change the relocation
8547 to be relative to the beginning of the section. */
8548 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8549 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8550 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8552 if (exp
->X_op
!= O_symbol
)
8555 if (S_IS_LOCAL (exp
->X_add_symbol
)
8556 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8557 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8558 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8559 exp
->X_op
= O_subtract
;
8560 exp
->X_op_symbol
= GOT_symbol
;
8561 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8562 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8563 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8564 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8566 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8569 else if (exp
->X_op
== O_absent
8570 || exp
->X_op
== O_illegal
8571 || exp
->X_op
== O_big
)
8574 as_bad (_("missing or invalid displacement expression `%s'"),
8579 else if (flag_code
== CODE_64BIT
8580 && !i
.prefix
[ADDR_PREFIX
]
8581 && exp
->X_op
== O_constant
)
8583 /* Since displacement is signed extended to 64bit, don't allow
8584 disp32 and turn off disp32s if they are out of range. */
8585 i
.types
[this_operand
].bitfield
.disp32
= 0;
8586 if (!fits_in_signed_long (exp
->X_add_number
))
8588 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8589 if (i
.types
[this_operand
].bitfield
.baseindex
)
8591 as_bad (_("0x%lx out range of signed 32bit displacement"),
8592 (long) exp
->X_add_number
);
8598 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8599 else if (exp
->X_op
!= O_constant
8600 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8601 && exp_seg
!= absolute_section
8602 && exp_seg
!= text_section
8603 && exp_seg
!= data_section
8604 && exp_seg
!= bss_section
8605 && exp_seg
!= undefined_section
8606 && !bfd_is_com_section (exp_seg
))
8608 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8613 /* Check if this is a displacement only operand. */
8614 bigdisp
= i
.types
[this_operand
];
8615 bigdisp
.bitfield
.disp8
= 0;
8616 bigdisp
.bitfield
.disp16
= 0;
8617 bigdisp
.bitfield
.disp32
= 0;
8618 bigdisp
.bitfield
.disp32s
= 0;
8619 bigdisp
.bitfield
.disp64
= 0;
8620 if (operand_type_all_zero (&bigdisp
))
8621 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8627 /* Make sure the memory operand we've been dealt is valid.
8628 Return 1 on success, 0 on a failure. */
8631 i386_index_check (const char *operand_string
)
8633 const char *kind
= "base/index";
8634 enum flag_code addr_mode
;
8636 if (i
.prefix
[ADDR_PREFIX
])
8637 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8640 addr_mode
= flag_code
;
8642 #if INFER_ADDR_PREFIX
8643 if (i
.mem_operands
== 0)
8645 /* Infer address prefix from the first memory operand. */
8646 const reg_entry
*addr_reg
= i
.base_reg
;
8648 if (addr_reg
== NULL
)
8649 addr_reg
= i
.index_reg
;
8653 if (addr_reg
->reg_num
== RegEip
8654 || addr_reg
->reg_num
== RegEiz
8655 || addr_reg
->reg_type
.bitfield
.reg32
)
8656 addr_mode
= CODE_32BIT
;
8657 else if (flag_code
!= CODE_64BIT
8658 && addr_reg
->reg_type
.bitfield
.reg16
)
8659 addr_mode
= CODE_16BIT
;
8661 if (addr_mode
!= flag_code
)
8663 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8665 /* Change the size of any displacement too. At most one
8666 of Disp16 or Disp32 is set.
8667 FIXME. There doesn't seem to be any real need for
8668 separate Disp16 and Disp32 flags. The same goes for
8669 Imm16 and Imm32. Removing them would probably clean
8670 up the code quite a lot. */
8671 if (flag_code
!= CODE_64BIT
8672 && (i
.types
[this_operand
].bitfield
.disp16
8673 || i
.types
[this_operand
].bitfield
.disp32
))
8674 i
.types
[this_operand
]
8675 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8682 if (current_templates
->start
->opcode_modifier
.isstring
8683 && !current_templates
->start
->opcode_modifier
.immext
8684 && (current_templates
->end
[-1].opcode_modifier
.isstring
8687 /* Memory operands of string insns are special in that they only allow
8688 a single register (rDI, rSI, or rBX) as their memory address. */
8689 const reg_entry
*expected_reg
;
8690 static const char *di_si
[][2] =
8696 static const char *bx
[] = { "ebx", "bx", "rbx" };
8698 kind
= "string address";
8700 if (current_templates
->start
->opcode_modifier
.repprefixok
)
8702 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8704 if (!type
.bitfield
.baseindex
8705 || ((!i
.mem_operands
!= !intel_syntax
)
8706 && current_templates
->end
[-1].operand_types
[1]
8707 .bitfield
.baseindex
))
8708 type
= current_templates
->end
[-1].operand_types
[1];
8709 expected_reg
= hash_find (reg_hash
,
8710 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8714 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8716 if (i
.base_reg
!= expected_reg
8718 || operand_type_check (i
.types
[this_operand
], disp
))
8720 /* The second memory operand must have the same size as
8724 && !((addr_mode
== CODE_64BIT
8725 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8726 || (addr_mode
== CODE_32BIT
8727 ? i
.base_reg
->reg_type
.bitfield
.reg32
8728 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8731 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8733 intel_syntax
? '[' : '(',
8735 expected_reg
->reg_name
,
8736 intel_syntax
? ']' : ')');
8743 as_bad (_("`%s' is not a valid %s expression"),
8744 operand_string
, kind
);
8749 if (addr_mode
!= CODE_16BIT
)
8751 /* 32-bit/64-bit checks. */
8753 && (addr_mode
== CODE_64BIT
8754 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8755 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8757 || (i
.base_reg
->reg_num
8758 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8760 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8761 && !i
.index_reg
->reg_type
.bitfield
.regymm
8762 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8763 && ((addr_mode
== CODE_64BIT
8764 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8765 || i
.index_reg
->reg_num
== RegRiz
)
8766 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8767 || i
.index_reg
->reg_num
== RegEiz
))
8768 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8771 /* bndmk, bndldx, and bndstx have special restrictions. */
8772 if (current_templates
->start
->base_opcode
== 0xf30f1b
8773 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
8775 /* They cannot use RIP-relative addressing. */
8776 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
8778 as_bad (_("`%s' cannot be used here"), operand_string
);
8782 /* bndldx and bndstx ignore their scale factor. */
8783 if (current_templates
->start
->base_opcode
!= 0xf30f1b
8784 && i
.log2_scale_factor
)
8785 as_warn (_("register scaling is being ignored here"));
8790 /* 16-bit checks. */
8792 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8793 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8795 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8796 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8798 && i
.base_reg
->reg_num
< 6
8799 && i
.index_reg
->reg_num
>= 6
8800 && i
.log2_scale_factor
== 0))))
8807 /* Handle vector immediates. */
8810 RC_SAE_immediate (const char *imm_start
)
8812 unsigned int match_found
, j
;
8813 const char *pstr
= imm_start
;
8821 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8823 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8827 rc_op
.type
= RC_NamesTable
[j
].type
;
8828 rc_op
.operand
= this_operand
;
8829 i
.rounding
= &rc_op
;
8833 as_bad (_("duplicated `%s'"), imm_start
);
8836 pstr
+= RC_NamesTable
[j
].len
;
8846 as_bad (_("Missing '}': '%s'"), imm_start
);
8849 /* RC/SAE immediate string should contain nothing more. */;
8852 as_bad (_("Junk after '}': '%s'"), imm_start
);
8856 exp
= &im_expressions
[i
.imm_operands
++];
8857 i
.op
[this_operand
].imms
= exp
;
8859 exp
->X_op
= O_constant
;
8860 exp
->X_add_number
= 0;
8861 exp
->X_add_symbol
= (symbolS
*) 0;
8862 exp
->X_op_symbol
= (symbolS
*) 0;
8864 i
.types
[this_operand
].bitfield
.imm8
= 1;
8868 /* Only string instructions can have a second memory operand, so
8869 reduce current_templates to just those if it contains any. */
8871 maybe_adjust_templates (void)
8873 const insn_template
*t
;
8875 gas_assert (i
.mem_operands
== 1);
8877 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
8878 if (t
->opcode_modifier
.isstring
)
8881 if (t
< current_templates
->end
)
8883 static templates aux_templates
;
8884 bfd_boolean recheck
;
8886 aux_templates
.start
= t
;
8887 for (; t
< current_templates
->end
; ++t
)
8888 if (!t
->opcode_modifier
.isstring
)
8890 aux_templates
.end
= t
;
8892 /* Determine whether to re-check the first memory operand. */
8893 recheck
= (aux_templates
.start
!= current_templates
->start
8894 || t
!= current_templates
->end
);
8896 current_templates
= &aux_templates
;
8901 if (i
.memop1_string
!= NULL
8902 && i386_index_check (i
.memop1_string
) == 0)
8911 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8915 i386_att_operand (char *operand_string
)
8919 char *op_string
= operand_string
;
8921 if (is_space_char (*op_string
))
8924 /* We check for an absolute prefix (differentiating,
8925 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8926 if (*op_string
== ABSOLUTE_PREFIX
)
8929 if (is_space_char (*op_string
))
8931 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8934 /* Check if operand is a register. */
8935 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8937 i386_operand_type temp
;
8939 /* Check for a segment override by searching for ':' after a
8940 segment register. */
8942 if (is_space_char (*op_string
))
8944 if (*op_string
== ':'
8945 && (r
->reg_type
.bitfield
.sreg2
8946 || r
->reg_type
.bitfield
.sreg3
))
8951 i
.seg
[i
.mem_operands
] = &es
;
8954 i
.seg
[i
.mem_operands
] = &cs
;
8957 i
.seg
[i
.mem_operands
] = &ss
;
8960 i
.seg
[i
.mem_operands
] = &ds
;
8963 i
.seg
[i
.mem_operands
] = &fs
;
8966 i
.seg
[i
.mem_operands
] = &gs
;
8970 /* Skip the ':' and whitespace. */
8972 if (is_space_char (*op_string
))
8975 if (!is_digit_char (*op_string
)
8976 && !is_identifier_char (*op_string
)
8977 && *op_string
!= '('
8978 && *op_string
!= ABSOLUTE_PREFIX
)
8980 as_bad (_("bad memory operand `%s'"), op_string
);
8983 /* Handle case of %es:*foo. */
8984 if (*op_string
== ABSOLUTE_PREFIX
)
8987 if (is_space_char (*op_string
))
8989 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8991 goto do_memory_reference
;
8994 /* Handle vector operations. */
8995 if (*op_string
== '{')
8997 op_string
= check_VecOperations (op_string
, NULL
);
8998 if (op_string
== NULL
)
9004 as_bad (_("junk `%s' after register"), op_string
);
9008 temp
.bitfield
.baseindex
= 0;
9009 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9011 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9012 i
.op
[this_operand
].regs
= r
;
9015 else if (*op_string
== REGISTER_PREFIX
)
9017 as_bad (_("bad register name `%s'"), op_string
);
9020 else if (*op_string
== IMMEDIATE_PREFIX
)
9023 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9025 as_bad (_("immediate operand illegal with absolute jump"));
9028 if (!i386_immediate (op_string
))
9031 else if (RC_SAE_immediate (operand_string
))
9033 /* If it is a RC or SAE immediate, do nothing. */
9036 else if (is_digit_char (*op_string
)
9037 || is_identifier_char (*op_string
)
9038 || *op_string
== '"'
9039 || *op_string
== '(')
9041 /* This is a memory reference of some sort. */
9044 /* Start and end of displacement string expression (if found). */
9045 char *displacement_string_start
;
9046 char *displacement_string_end
;
9049 do_memory_reference
:
9050 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9052 if ((i
.mem_operands
== 1
9053 && !current_templates
->start
->opcode_modifier
.isstring
)
9054 || i
.mem_operands
== 2)
9056 as_bad (_("too many memory references for `%s'"),
9057 current_templates
->start
->name
);
9061 /* Check for base index form. We detect the base index form by
9062 looking for an ')' at the end of the operand, searching
9063 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9065 base_string
= op_string
+ strlen (op_string
);
9067 /* Handle vector operations. */
9068 vop_start
= strchr (op_string
, '{');
9069 if (vop_start
&& vop_start
< base_string
)
9071 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9073 base_string
= vop_start
;
9077 if (is_space_char (*base_string
))
9080 /* If we only have a displacement, set-up for it to be parsed later. */
9081 displacement_string_start
= op_string
;
9082 displacement_string_end
= base_string
+ 1;
9084 if (*base_string
== ')')
9087 unsigned int parens_balanced
= 1;
9088 /* We've already checked that the number of left & right ()'s are
9089 equal, so this loop will not be infinite. */
9093 if (*base_string
== ')')
9095 if (*base_string
== '(')
9098 while (parens_balanced
);
9100 temp_string
= base_string
;
9102 /* Skip past '(' and whitespace. */
9104 if (is_space_char (*base_string
))
9107 if (*base_string
== ','
9108 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9111 displacement_string_end
= temp_string
;
9113 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9117 base_string
= end_op
;
9118 if (is_space_char (*base_string
))
9122 /* There may be an index reg or scale factor here. */
9123 if (*base_string
== ',')
9126 if (is_space_char (*base_string
))
9129 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9132 base_string
= end_op
;
9133 if (is_space_char (*base_string
))
9135 if (*base_string
== ',')
9138 if (is_space_char (*base_string
))
9141 else if (*base_string
!= ')')
9143 as_bad (_("expecting `,' or `)' "
9144 "after index register in `%s'"),
9149 else if (*base_string
== REGISTER_PREFIX
)
9151 end_op
= strchr (base_string
, ',');
9154 as_bad (_("bad register name `%s'"), base_string
);
9158 /* Check for scale factor. */
9159 if (*base_string
!= ')')
9161 char *end_scale
= i386_scale (base_string
);
9166 base_string
= end_scale
;
9167 if (is_space_char (*base_string
))
9169 if (*base_string
!= ')')
9171 as_bad (_("expecting `)' "
9172 "after scale factor in `%s'"),
9177 else if (!i
.index_reg
)
9179 as_bad (_("expecting index register or scale factor "
9180 "after `,'; got '%c'"),
9185 else if (*base_string
!= ')')
9187 as_bad (_("expecting `,' or `)' "
9188 "after base register in `%s'"),
9193 else if (*base_string
== REGISTER_PREFIX
)
9195 end_op
= strchr (base_string
, ',');
9198 as_bad (_("bad register name `%s'"), base_string
);
9203 /* If there's an expression beginning the operand, parse it,
9204 assuming displacement_string_start and
9205 displacement_string_end are meaningful. */
9206 if (displacement_string_start
!= displacement_string_end
)
9208 if (!i386_displacement (displacement_string_start
,
9209 displacement_string_end
))
9213 /* Special case for (%dx) while doing input/output op. */
9215 && operand_type_equal (&i
.base_reg
->reg_type
,
9216 ®16_inoutportreg
)
9218 && i
.log2_scale_factor
== 0
9219 && i
.seg
[i
.mem_operands
] == 0
9220 && !operand_type_check (i
.types
[this_operand
], disp
))
9222 i
.types
[this_operand
] = inoutportreg
;
9226 if (i386_index_check (operand_string
) == 0)
9228 i
.types
[this_operand
].bitfield
.mem
= 1;
9229 if (i
.mem_operands
== 0)
9230 i
.memop1_string
= xstrdup (operand_string
);
9235 /* It's not a memory operand; argh! */
9236 as_bad (_("invalid char %s beginning operand %d `%s'"),
9237 output_invalid (*op_string
),
9242 return 1; /* Normal return. */
9245 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9246 that an rs_machine_dependent frag may reach. */
9249 i386_frag_max_var (fragS
*frag
)
9251 /* The only relaxable frags are for jumps.
9252 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9253 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9254 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9259 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9261 /* STT_GNU_IFUNC symbol must go through PLT. */
9262 if ((symbol_get_bfdsym (fr_symbol
)->flags
9263 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9266 if (!S_IS_EXTERNAL (fr_symbol
))
9267 /* Symbol may be weak or local. */
9268 return !S_IS_WEAK (fr_symbol
);
9270 /* Global symbols with non-default visibility can't be preempted. */
9271 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9274 if (fr_var
!= NO_RELOC
)
9275 switch ((enum bfd_reloc_code_real
) fr_var
)
9277 case BFD_RELOC_386_PLT32
:
9278 case BFD_RELOC_X86_64_PLT32
:
9279 /* Symbol with PLT relocation may be preempted. */
9285 /* Global symbols with default visibility in a shared library may be
9286 preempted by another definition. */
9291 /* md_estimate_size_before_relax()
9293 Called just before relax() for rs_machine_dependent frags. The x86
9294 assembler uses these frags to handle variable size jump
9297 Any symbol that is now undefined will not become defined.
9298 Return the correct fr_subtype in the frag.
9299 Return the initial "guess for variable size of frag" to caller.
9300 The guess is actually the growth beyond the fixed part. Whatever
9301 we do to grow the fixed or variable part contributes to our
9305 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9307 /* We've already got fragP->fr_subtype right; all we have to do is
9308 check for un-relaxable symbols. On an ELF system, we can't relax
9309 an externally visible symbol, because it may be overridden by a
9311 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9314 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9317 #if defined (OBJ_COFF) && defined (TE_PE)
9318 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9319 && S_IS_WEAK (fragP
->fr_symbol
))
9323 /* Symbol is undefined in this segment, or we need to keep a
9324 reloc so that weak symbols can be overridden. */
9325 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9326 enum bfd_reloc_code_real reloc_type
;
9327 unsigned char *opcode
;
9330 if (fragP
->fr_var
!= NO_RELOC
)
9331 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9333 reloc_type
= BFD_RELOC_16_PCREL
;
9335 reloc_type
= BFD_RELOC_32_PCREL
;
9337 old_fr_fix
= fragP
->fr_fix
;
9338 opcode
= (unsigned char *) fragP
->fr_opcode
;
9340 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9343 /* Make jmp (0xeb) a (d)word displacement jump. */
9345 fragP
->fr_fix
+= size
;
9346 fix_new (fragP
, old_fr_fix
, size
,
9348 fragP
->fr_offset
, 1,
9354 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9356 /* Negate the condition, and branch past an
9357 unconditional jump. */
9360 /* Insert an unconditional jump. */
9362 /* We added two extra opcode bytes, and have a two byte
9364 fragP
->fr_fix
+= 2 + 2;
9365 fix_new (fragP
, old_fr_fix
+ 2, 2,
9367 fragP
->fr_offset
, 1,
9374 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9379 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9381 fragP
->fr_offset
, 1,
9383 fixP
->fx_signed
= 1;
9387 /* This changes the byte-displacement jump 0x7N
9388 to the (d)word-displacement jump 0x0f,0x8N. */
9389 opcode
[1] = opcode
[0] + 0x10;
9390 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9391 /* We've added an opcode byte. */
9392 fragP
->fr_fix
+= 1 + size
;
9393 fix_new (fragP
, old_fr_fix
+ 1, size
,
9395 fragP
->fr_offset
, 1,
9400 BAD_CASE (fragP
->fr_subtype
);
9404 return fragP
->fr_fix
- old_fr_fix
;
9407 /* Guess size depending on current relax state. Initially the relax
9408 state will correspond to a short jump and we return 1, because
9409 the variable part of the frag (the branch offset) is one byte
9410 long. However, we can relax a section more than once and in that
9411 case we must either set fr_subtype back to the unrelaxed state,
9412 or return the value for the appropriate branch. */
9413 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9416 /* Called after relax() is finished.
9418 In: Address of frag.
9419 fr_type == rs_machine_dependent.
9420 fr_subtype is what the address relaxed to.
9422 Out: Any fixSs and constants are set up.
9423 Caller will turn frag into a ".space 0". */
9426 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9429 unsigned char *opcode
;
9430 unsigned char *where_to_put_displacement
= NULL
;
9431 offsetT target_address
;
9432 offsetT opcode_address
;
9433 unsigned int extension
= 0;
9434 offsetT displacement_from_opcode_start
;
9436 opcode
= (unsigned char *) fragP
->fr_opcode
;
9438 /* Address we want to reach in file space. */
9439 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9441 /* Address opcode resides at in file space. */
9442 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9444 /* Displacement from opcode start to fill into instruction. */
9445 displacement_from_opcode_start
= target_address
- opcode_address
;
9447 if ((fragP
->fr_subtype
& BIG
) == 0)
9449 /* Don't have to change opcode. */
9450 extension
= 1; /* 1 opcode + 1 displacement */
9451 where_to_put_displacement
= &opcode
[1];
9455 if (no_cond_jump_promotion
9456 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9457 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9458 _("long jump required"));
9460 switch (fragP
->fr_subtype
)
9462 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9463 extension
= 4; /* 1 opcode + 4 displacement */
9465 where_to_put_displacement
= &opcode
[1];
9468 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9469 extension
= 2; /* 1 opcode + 2 displacement */
9471 where_to_put_displacement
= &opcode
[1];
9474 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9475 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9476 extension
= 5; /* 2 opcode + 4 displacement */
9477 opcode
[1] = opcode
[0] + 0x10;
9478 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9479 where_to_put_displacement
= &opcode
[2];
9482 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9483 extension
= 3; /* 2 opcode + 2 displacement */
9484 opcode
[1] = opcode
[0] + 0x10;
9485 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9486 where_to_put_displacement
= &opcode
[2];
9489 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9494 where_to_put_displacement
= &opcode
[3];
9498 BAD_CASE (fragP
->fr_subtype
);
9503 /* If size if less then four we are sure that the operand fits,
9504 but if it's 4, then it could be that the displacement is larger
9506 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9508 && ((addressT
) (displacement_from_opcode_start
- extension
9509 + ((addressT
) 1 << 31))
9510 > (((addressT
) 2 << 31) - 1)))
9512 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9513 _("jump target out of range"));
9514 /* Make us emit 0. */
9515 displacement_from_opcode_start
= extension
;
9517 /* Now put displacement after opcode. */
9518 md_number_to_chars ((char *) where_to_put_displacement
,
9519 (valueT
) (displacement_from_opcode_start
- extension
),
9520 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9521 fragP
->fr_fix
+= extension
;
9524 /* Apply a fixup (fixP) to segment data, once it has been determined
9525 by our caller that we have all the info we need to fix it up.
9527 Parameter valP is the pointer to the value of the bits.
9529 On the 386, immediates, displacements, and data pointers are all in
9530 the same (little-endian) format, so we don't need to care about which
9534 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9536 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9537 valueT value
= *valP
;
9539 #if !defined (TE_Mach)
9542 switch (fixP
->fx_r_type
)
9548 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9551 case BFD_RELOC_X86_64_32S
:
9552 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9555 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9558 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9563 if (fixP
->fx_addsy
!= NULL
9564 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9565 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9566 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9567 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9568 && !use_rela_relocations
)
9570 /* This is a hack. There should be a better way to handle this.
9571 This covers for the fact that bfd_install_relocation will
9572 subtract the current location (for partial_inplace, PC relative
9573 relocations); see more below. */
9577 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9580 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9585 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9588 || (symbol_section_p (fixP
->fx_addsy
)
9589 && sym_seg
!= absolute_section
))
9590 && !generic_force_reloc (fixP
))
9592 /* Yes, we add the values in twice. This is because
9593 bfd_install_relocation subtracts them out again. I think
9594 bfd_install_relocation is broken, but I don't dare change
9596 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9600 #if defined (OBJ_COFF) && defined (TE_PE)
9601 /* For some reason, the PE format does not store a
9602 section address offset for a PC relative symbol. */
9603 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9604 || S_IS_WEAK (fixP
->fx_addsy
))
9605 value
+= md_pcrel_from (fixP
);
9608 #if defined (OBJ_COFF) && defined (TE_PE)
9609 if (fixP
->fx_addsy
!= NULL
9610 && S_IS_WEAK (fixP
->fx_addsy
)
9611 /* PR 16858: Do not modify weak function references. */
9612 && ! fixP
->fx_pcrel
)
9614 #if !defined (TE_PEP)
9615 /* For x86 PE weak function symbols are neither PC-relative
9616 nor do they set S_IS_FUNCTION. So the only reliable way
9617 to detect them is to check the flags of their containing
9619 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9620 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9624 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9628 /* Fix a few things - the dynamic linker expects certain values here,
9629 and we must not disappoint it. */
9630 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9631 if (IS_ELF
&& fixP
->fx_addsy
)
9632 switch (fixP
->fx_r_type
)
9634 case BFD_RELOC_386_PLT32
:
9635 case BFD_RELOC_X86_64_PLT32
:
9636 /* Make the jump instruction point to the address of the operand. At
9637 runtime we merely add the offset to the actual PLT entry. */
9641 case BFD_RELOC_386_TLS_GD
:
9642 case BFD_RELOC_386_TLS_LDM
:
9643 case BFD_RELOC_386_TLS_IE_32
:
9644 case BFD_RELOC_386_TLS_IE
:
9645 case BFD_RELOC_386_TLS_GOTIE
:
9646 case BFD_RELOC_386_TLS_GOTDESC
:
9647 case BFD_RELOC_X86_64_TLSGD
:
9648 case BFD_RELOC_X86_64_TLSLD
:
9649 case BFD_RELOC_X86_64_GOTTPOFF
:
9650 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9651 value
= 0; /* Fully resolved at runtime. No addend. */
9653 case BFD_RELOC_386_TLS_LE
:
9654 case BFD_RELOC_386_TLS_LDO_32
:
9655 case BFD_RELOC_386_TLS_LE_32
:
9656 case BFD_RELOC_X86_64_DTPOFF32
:
9657 case BFD_RELOC_X86_64_DTPOFF64
:
9658 case BFD_RELOC_X86_64_TPOFF32
:
9659 case BFD_RELOC_X86_64_TPOFF64
:
9660 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9663 case BFD_RELOC_386_TLS_DESC_CALL
:
9664 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9665 value
= 0; /* Fully resolved at runtime. No addend. */
9666 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9670 case BFD_RELOC_VTABLE_INHERIT
:
9671 case BFD_RELOC_VTABLE_ENTRY
:
9678 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9680 #endif /* !defined (TE_Mach) */
9682 /* Are we finished with this relocation now? */
9683 if (fixP
->fx_addsy
== NULL
)
9685 #if defined (OBJ_COFF) && defined (TE_PE)
9686 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9689 /* Remember value for tc_gen_reloc. */
9690 fixP
->fx_addnumber
= value
;
9691 /* Clear out the frag for now. */
9695 else if (use_rela_relocations
)
9697 fixP
->fx_no_overflow
= 1;
9698 /* Remember value for tc_gen_reloc. */
9699 fixP
->fx_addnumber
= value
;
9703 md_number_to_chars (p
, value
, fixP
->fx_size
);
9707 md_atof (int type
, char *litP
, int *sizeP
)
9709 /* This outputs the LITTLENUMs in REVERSE order;
9710 in accord with the bigendian 386. */
9711 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9714 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9717 output_invalid (int c
)
9720 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9723 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9724 "(0x%x)", (unsigned char) c
);
9725 return output_invalid_buf
;
9728 /* REG_STRING starts *before* REGISTER_PREFIX. */
9730 static const reg_entry
*
9731 parse_real_register (char *reg_string
, char **end_op
)
9733 char *s
= reg_string
;
9735 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9738 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9739 if (*s
== REGISTER_PREFIX
)
9742 if (is_space_char (*s
))
9746 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9748 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9749 return (const reg_entry
*) NULL
;
9753 /* For naked regs, make sure that we are not dealing with an identifier.
9754 This prevents confusing an identifier like `eax_var' with register
9756 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9757 return (const reg_entry
*) NULL
;
9761 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9763 /* Handle floating point regs, allowing spaces in the (i) part. */
9764 if (r
== i386_regtab
/* %st is first entry of table */)
9766 if (is_space_char (*s
))
9771 if (is_space_char (*s
))
9773 if (*s
>= '0' && *s
<= '7')
9777 if (is_space_char (*s
))
9782 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9787 /* We have "%st(" then garbage. */
9788 return (const reg_entry
*) NULL
;
9792 if (r
== NULL
|| allow_pseudo_reg
)
9795 if (operand_type_all_zero (&r
->reg_type
))
9796 return (const reg_entry
*) NULL
;
9798 if ((r
->reg_type
.bitfield
.reg32
9799 || r
->reg_type
.bitfield
.sreg3
9800 || r
->reg_type
.bitfield
.control
9801 || r
->reg_type
.bitfield
.debug
9802 || r
->reg_type
.bitfield
.test
)
9803 && !cpu_arch_flags
.bitfield
.cpui386
)
9804 return (const reg_entry
*) NULL
;
9806 if (r
->reg_type
.bitfield
.floatreg
9807 && !cpu_arch_flags
.bitfield
.cpu8087
9808 && !cpu_arch_flags
.bitfield
.cpu287
9809 && !cpu_arch_flags
.bitfield
.cpu387
)
9810 return (const reg_entry
*) NULL
;
9812 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
9813 return (const reg_entry
*) NULL
;
9815 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
9816 return (const reg_entry
*) NULL
;
9818 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
9819 return (const reg_entry
*) NULL
;
9821 if (r
->reg_type
.bitfield
.regzmm
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
9822 return (const reg_entry
*) NULL
;
9824 if (r
->reg_type
.bitfield
.regmask
9825 && !cpu_arch_flags
.bitfield
.cpuregmask
)
9826 return (const reg_entry
*) NULL
;
9828 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9829 if (!allow_index_reg
9830 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9831 return (const reg_entry
*) NULL
;
9833 /* Upper 16 vector register is only available with VREX in 64bit
9835 if ((r
->reg_flags
& RegVRex
))
9837 if (i
.vec_encoding
== vex_encoding_default
)
9838 i
.vec_encoding
= vex_encoding_evex
;
9840 if (!cpu_arch_flags
.bitfield
.cpuvrex
9841 || i
.vec_encoding
!= vex_encoding_evex
9842 || flag_code
!= CODE_64BIT
)
9843 return (const reg_entry
*) NULL
;
9846 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9847 || r
->reg_type
.bitfield
.reg64
)
9848 && (!cpu_arch_flags
.bitfield
.cpulm
9849 || !operand_type_equal (&r
->reg_type
, &control
))
9850 && flag_code
!= CODE_64BIT
)
9851 return (const reg_entry
*) NULL
;
9853 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9854 return (const reg_entry
*) NULL
;
9859 /* REG_STRING starts *before* REGISTER_PREFIX. */
9861 static const reg_entry
*
9862 parse_register (char *reg_string
, char **end_op
)
9866 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9867 r
= parse_real_register (reg_string
, end_op
);
9872 char *save
= input_line_pointer
;
9876 input_line_pointer
= reg_string
;
9877 c
= get_symbol_name (®_string
);
9878 symbolP
= symbol_find (reg_string
);
9879 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9881 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9883 know (e
->X_op
== O_register
);
9884 know (e
->X_add_number
>= 0
9885 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9886 r
= i386_regtab
+ e
->X_add_number
;
9887 if ((r
->reg_flags
& RegVRex
))
9888 i
.vec_encoding
= vex_encoding_evex
;
9889 *end_op
= input_line_pointer
;
9891 *input_line_pointer
= c
;
9892 input_line_pointer
= save
;
9898 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9901 char *end
= input_line_pointer
;
9904 r
= parse_register (name
, &input_line_pointer
);
9905 if (r
&& end
<= input_line_pointer
)
9907 *nextcharP
= *input_line_pointer
;
9908 *input_line_pointer
= 0;
9909 e
->X_op
= O_register
;
9910 e
->X_add_number
= r
- i386_regtab
;
9913 input_line_pointer
= end
;
9915 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9919 md_operand (expressionS
*e
)
9924 switch (*input_line_pointer
)
9926 case REGISTER_PREFIX
:
9927 r
= parse_real_register (input_line_pointer
, &end
);
9930 e
->X_op
= O_register
;
9931 e
->X_add_number
= r
- i386_regtab
;
9932 input_line_pointer
= end
;
9937 gas_assert (intel_syntax
);
9938 end
= input_line_pointer
++;
9940 if (*input_line_pointer
== ']')
9942 ++input_line_pointer
;
9943 e
->X_op_symbol
= make_expr_symbol (e
);
9944 e
->X_add_symbol
= NULL
;
9945 e
->X_add_number
= 0;
9951 input_line_pointer
= end
;
9958 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9959 const char *md_shortopts
= "kVQ:sqn";
9961 const char *md_shortopts
= "qn";
9964 #define OPTION_32 (OPTION_MD_BASE + 0)
9965 #define OPTION_64 (OPTION_MD_BASE + 1)
9966 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9967 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9968 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9969 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9970 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9971 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9972 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9973 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9974 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9975 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9976 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9977 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9978 #define OPTION_X32 (OPTION_MD_BASE + 14)
9979 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9980 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9981 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9982 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9983 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9984 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9985 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9986 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9987 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9988 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9989 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9991 struct option md_longopts
[] =
9993 {"32", no_argument
, NULL
, OPTION_32
},
9994 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9995 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9996 {"64", no_argument
, NULL
, OPTION_64
},
9998 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9999 {"x32", no_argument
, NULL
, OPTION_X32
},
10000 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10002 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10003 {"march", required_argument
, NULL
, OPTION_MARCH
},
10004 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10005 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10006 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10007 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10008 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10009 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
10010 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10011 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10012 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10013 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10014 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10015 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10016 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10017 # if defined (TE_PE) || defined (TE_PEP)
10018 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10020 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10021 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10022 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10023 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10024 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10025 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10026 {NULL
, no_argument
, NULL
, 0}
10028 size_t md_longopts_size
= sizeof (md_longopts
);
10031 md_parse_option (int c
, const char *arg
)
10034 char *arch
, *next
, *saved
;
10039 optimize_align_code
= 0;
10043 quiet_warnings
= 1;
10046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10047 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10048 should be emitted or not. FIXME: Not implemented. */
10052 /* -V: SVR4 argument to print version ID. */
10054 print_version_id ();
10057 /* -k: Ignore for FreeBSD compatibility. */
10062 /* -s: On i386 Solaris, this tells the native assembler to use
10063 .stab instead of .stab.excl. We always use .stab anyhow. */
10066 case OPTION_MSHARED
:
10070 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10071 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10074 const char **list
, **l
;
10076 list
= bfd_target_list ();
10077 for (l
= list
; *l
!= NULL
; l
++)
10078 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10079 || strcmp (*l
, "coff-x86-64") == 0
10080 || strcmp (*l
, "pe-x86-64") == 0
10081 || strcmp (*l
, "pei-x86-64") == 0
10082 || strcmp (*l
, "mach-o-x86-64") == 0)
10084 default_arch
= "x86_64";
10088 as_fatal (_("no compiled in support for x86_64"));
10094 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10098 const char **list
, **l
;
10100 list
= bfd_target_list ();
10101 for (l
= list
; *l
!= NULL
; l
++)
10102 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10104 default_arch
= "x86_64:32";
10108 as_fatal (_("no compiled in support for 32bit x86_64"));
10112 as_fatal (_("32bit x86_64 is only supported for ELF"));
10117 default_arch
= "i386";
10120 case OPTION_DIVIDE
:
10121 #ifdef SVR4_COMMENT_CHARS
10126 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10128 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10132 i386_comment_chars
= n
;
10138 saved
= xstrdup (arg
);
10140 /* Allow -march=+nosse. */
10146 as_fatal (_("invalid -march= option: `%s'"), arg
);
10147 next
= strchr (arch
, '+');
10150 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10152 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10155 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10158 cpu_arch_name
= cpu_arch
[j
].name
;
10159 cpu_sub_arch_name
= NULL
;
10160 cpu_arch_flags
= cpu_arch
[j
].flags
;
10161 cpu_arch_isa
= cpu_arch
[j
].type
;
10162 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10163 if (!cpu_arch_tune_set
)
10165 cpu_arch_tune
= cpu_arch_isa
;
10166 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10170 else if (*cpu_arch
[j
].name
== '.'
10171 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10173 /* ISA extension. */
10174 i386_cpu_flags flags
;
10176 flags
= cpu_flags_or (cpu_arch_flags
,
10177 cpu_arch
[j
].flags
);
10179 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10181 if (cpu_sub_arch_name
)
10183 char *name
= cpu_sub_arch_name
;
10184 cpu_sub_arch_name
= concat (name
,
10186 (const char *) NULL
);
10190 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10191 cpu_arch_flags
= flags
;
10192 cpu_arch_isa_flags
= flags
;
10198 if (j
>= ARRAY_SIZE (cpu_arch
))
10200 /* Disable an ISA extension. */
10201 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10202 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10204 i386_cpu_flags flags
;
10206 flags
= cpu_flags_and_not (cpu_arch_flags
,
10207 cpu_noarch
[j
].flags
);
10208 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10210 if (cpu_sub_arch_name
)
10212 char *name
= cpu_sub_arch_name
;
10213 cpu_sub_arch_name
= concat (arch
,
10214 (const char *) NULL
);
10218 cpu_sub_arch_name
= xstrdup (arch
);
10219 cpu_arch_flags
= flags
;
10220 cpu_arch_isa_flags
= flags
;
10225 if (j
>= ARRAY_SIZE (cpu_noarch
))
10226 j
= ARRAY_SIZE (cpu_arch
);
10229 if (j
>= ARRAY_SIZE (cpu_arch
))
10230 as_fatal (_("invalid -march= option: `%s'"), arg
);
10234 while (next
!= NULL
);
10240 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10241 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10243 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10245 cpu_arch_tune_set
= 1;
10246 cpu_arch_tune
= cpu_arch
[j
].type
;
10247 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10251 if (j
>= ARRAY_SIZE (cpu_arch
))
10252 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10255 case OPTION_MMNEMONIC
:
10256 if (strcasecmp (arg
, "att") == 0)
10257 intel_mnemonic
= 0;
10258 else if (strcasecmp (arg
, "intel") == 0)
10259 intel_mnemonic
= 1;
10261 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10264 case OPTION_MSYNTAX
:
10265 if (strcasecmp (arg
, "att") == 0)
10267 else if (strcasecmp (arg
, "intel") == 0)
10270 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10273 case OPTION_MINDEX_REG
:
10274 allow_index_reg
= 1;
10277 case OPTION_MNAKED_REG
:
10278 allow_naked_reg
= 1;
10281 case OPTION_MOLD_GCC
:
10285 case OPTION_MSSE2AVX
:
10289 case OPTION_MSSE_CHECK
:
10290 if (strcasecmp (arg
, "error") == 0)
10291 sse_check
= check_error
;
10292 else if (strcasecmp (arg
, "warning") == 0)
10293 sse_check
= check_warning
;
10294 else if (strcasecmp (arg
, "none") == 0)
10295 sse_check
= check_none
;
10297 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10300 case OPTION_MOPERAND_CHECK
:
10301 if (strcasecmp (arg
, "error") == 0)
10302 operand_check
= check_error
;
10303 else if (strcasecmp (arg
, "warning") == 0)
10304 operand_check
= check_warning
;
10305 else if (strcasecmp (arg
, "none") == 0)
10306 operand_check
= check_none
;
10308 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10311 case OPTION_MAVXSCALAR
:
10312 if (strcasecmp (arg
, "128") == 0)
10313 avxscalar
= vex128
;
10314 else if (strcasecmp (arg
, "256") == 0)
10315 avxscalar
= vex256
;
10317 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10320 case OPTION_MADD_BND_PREFIX
:
10321 add_bnd_prefix
= 1;
10324 case OPTION_MEVEXLIG
:
10325 if (strcmp (arg
, "128") == 0)
10326 evexlig
= evexl128
;
10327 else if (strcmp (arg
, "256") == 0)
10328 evexlig
= evexl256
;
10329 else if (strcmp (arg
, "512") == 0)
10330 evexlig
= evexl512
;
10332 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10335 case OPTION_MEVEXRCIG
:
10336 if (strcmp (arg
, "rne") == 0)
10338 else if (strcmp (arg
, "rd") == 0)
10340 else if (strcmp (arg
, "ru") == 0)
10342 else if (strcmp (arg
, "rz") == 0)
10345 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10348 case OPTION_MEVEXWIG
:
10349 if (strcmp (arg
, "0") == 0)
10351 else if (strcmp (arg
, "1") == 0)
10354 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10357 # if defined (TE_PE) || defined (TE_PEP)
10358 case OPTION_MBIG_OBJ
:
10363 case OPTION_MOMIT_LOCK_PREFIX
:
10364 if (strcasecmp (arg
, "yes") == 0)
10365 omit_lock_prefix
= 1;
10366 else if (strcasecmp (arg
, "no") == 0)
10367 omit_lock_prefix
= 0;
10369 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10372 case OPTION_MFENCE_AS_LOCK_ADD
:
10373 if (strcasecmp (arg
, "yes") == 0)
10375 else if (strcasecmp (arg
, "no") == 0)
10378 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10381 case OPTION_MRELAX_RELOCATIONS
:
10382 if (strcasecmp (arg
, "yes") == 0)
10383 generate_relax_relocations
= 1;
10384 else if (strcasecmp (arg
, "no") == 0)
10385 generate_relax_relocations
= 0;
10387 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10390 case OPTION_MAMD64
:
10394 case OPTION_MINTEL64
:
10404 #define MESSAGE_TEMPLATE \
10408 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10409 int *left_p
, const char *name
, int len
)
10411 int size
= sizeof (MESSAGE_TEMPLATE
);
10412 int left
= *left_p
;
10414 /* Reserve 2 spaces for ", " or ",\0" */
10417 /* Check if there is any room. */
10425 p
= mempcpy (p
, name
, len
);
10429 /* Output the current message now and start a new one. */
10432 fprintf (stream
, "%s\n", message
);
10434 left
= size
- (start
- message
) - len
- 2;
10436 gas_assert (left
>= 0);
10438 p
= mempcpy (p
, name
, len
);
10446 show_arch (FILE *stream
, int ext
, int check
)
10448 static char message
[] = MESSAGE_TEMPLATE
;
10449 char *start
= message
+ 27;
10451 int size
= sizeof (MESSAGE_TEMPLATE
);
10458 left
= size
- (start
- message
);
10459 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10461 /* Should it be skipped? */
10462 if (cpu_arch
[j
].skip
)
10465 name
= cpu_arch
[j
].name
;
10466 len
= cpu_arch
[j
].len
;
10469 /* It is an extension. Skip if we aren't asked to show it. */
10480 /* It is an processor. Skip if we show only extension. */
10483 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10485 /* It is an impossible processor - skip. */
10489 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10492 /* Display disabled extensions. */
10494 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10496 name
= cpu_noarch
[j
].name
;
10497 len
= cpu_noarch
[j
].len
;
10498 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10503 fprintf (stream
, "%s\n", message
);
10507 md_show_usage (FILE *stream
)
10509 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10510 fprintf (stream
, _("\
10512 -V print assembler version number\n\
10515 fprintf (stream
, _("\
10516 -n Do not optimize code alignment\n\
10517 -q quieten some warnings\n"));
10518 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10519 fprintf (stream
, _("\
10522 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10523 || defined (TE_PE) || defined (TE_PEP))
10524 fprintf (stream
, _("\
10525 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10527 #ifdef SVR4_COMMENT_CHARS
10528 fprintf (stream
, _("\
10529 --divide do not treat `/' as a comment character\n"));
10531 fprintf (stream
, _("\
10532 --divide ignored\n"));
10534 fprintf (stream
, _("\
10535 -march=CPU[,+EXTENSION...]\n\
10536 generate code for CPU and EXTENSION, CPU is one of:\n"));
10537 show_arch (stream
, 0, 1);
10538 fprintf (stream
, _("\
10539 EXTENSION is combination of:\n"));
10540 show_arch (stream
, 1, 0);
10541 fprintf (stream
, _("\
10542 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10543 show_arch (stream
, 0, 0);
10544 fprintf (stream
, _("\
10545 -msse2avx encode SSE instructions with VEX prefix\n"));
10546 fprintf (stream
, _("\
10547 -msse-check=[none|error|warning]\n\
10548 check SSE instructions\n"));
10549 fprintf (stream
, _("\
10550 -moperand-check=[none|error|warning]\n\
10551 check operand combinations for validity\n"));
10552 fprintf (stream
, _("\
10553 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10555 fprintf (stream
, _("\
10556 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10558 fprintf (stream
, _("\
10559 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10560 for EVEX.W bit ignored instructions\n"));
10561 fprintf (stream
, _("\
10562 -mevexrcig=[rne|rd|ru|rz]\n\
10563 encode EVEX instructions with specific EVEX.RC value\n\
10564 for SAE-only ignored instructions\n"));
10565 fprintf (stream
, _("\
10566 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10567 fprintf (stream
, _("\
10568 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10569 fprintf (stream
, _("\
10570 -mindex-reg support pseudo index registers\n"));
10571 fprintf (stream
, _("\
10572 -mnaked-reg don't require `%%' prefix for registers\n"));
10573 fprintf (stream
, _("\
10574 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10575 fprintf (stream
, _("\
10576 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10577 fprintf (stream
, _("\
10578 -mshared disable branch optimization for shared code\n"));
10579 # if defined (TE_PE) || defined (TE_PEP)
10580 fprintf (stream
, _("\
10581 -mbig-obj generate big object files\n"));
10583 fprintf (stream
, _("\
10584 -momit-lock-prefix=[no|yes]\n\
10585 strip all lock prefixes\n"));
10586 fprintf (stream
, _("\
10587 -mfence-as-lock-add=[no|yes]\n\
10588 encode lfence, mfence and sfence as\n\
10589 lock addl $0x0, (%%{re}sp)\n"));
10590 fprintf (stream
, _("\
10591 -mrelax-relocations=[no|yes]\n\
10592 generate relax relocations\n"));
10593 fprintf (stream
, _("\
10594 -mamd64 accept only AMD64 ISA\n"));
10595 fprintf (stream
, _("\
10596 -mintel64 accept only Intel64 ISA\n"));
10599 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10600 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10601 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10603 /* Pick the target format to use. */
10606 i386_target_format (void)
10608 if (!strncmp (default_arch
, "x86_64", 6))
10610 update_code_flag (CODE_64BIT
, 1);
10611 if (default_arch
[6] == '\0')
10612 x86_elf_abi
= X86_64_ABI
;
10614 x86_elf_abi
= X86_64_X32_ABI
;
10616 else if (!strcmp (default_arch
, "i386"))
10617 update_code_flag (CODE_32BIT
, 1);
10618 else if (!strcmp (default_arch
, "iamcu"))
10620 update_code_flag (CODE_32BIT
, 1);
10621 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10623 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10624 cpu_arch_name
= "iamcu";
10625 cpu_sub_arch_name
= NULL
;
10626 cpu_arch_flags
= iamcu_flags
;
10627 cpu_arch_isa
= PROCESSOR_IAMCU
;
10628 cpu_arch_isa_flags
= iamcu_flags
;
10629 if (!cpu_arch_tune_set
)
10631 cpu_arch_tune
= cpu_arch_isa
;
10632 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10635 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10636 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10640 as_fatal (_("unknown architecture"));
10642 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10643 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10644 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10645 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10647 switch (OUTPUT_FLAVOR
)
10649 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10650 case bfd_target_aout_flavour
:
10651 return AOUT_TARGET_FORMAT
;
10653 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10654 # if defined (TE_PE) || defined (TE_PEP)
10655 case bfd_target_coff_flavour
:
10656 if (flag_code
== CODE_64BIT
)
10657 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10660 # elif defined (TE_GO32)
10661 case bfd_target_coff_flavour
:
10662 return "coff-go32";
10664 case bfd_target_coff_flavour
:
10665 return "coff-i386";
10668 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10669 case bfd_target_elf_flavour
:
10671 const char *format
;
10673 switch (x86_elf_abi
)
10676 format
= ELF_TARGET_FORMAT
;
10679 use_rela_relocations
= 1;
10681 format
= ELF_TARGET_FORMAT64
;
10683 case X86_64_X32_ABI
:
10684 use_rela_relocations
= 1;
10686 disallow_64bit_reloc
= 1;
10687 format
= ELF_TARGET_FORMAT32
;
10690 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10692 if (x86_elf_abi
!= X86_64_ABI
)
10693 as_fatal (_("Intel L1OM is 64bit only"));
10694 return ELF_TARGET_L1OM_FORMAT
;
10696 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10698 if (x86_elf_abi
!= X86_64_ABI
)
10699 as_fatal (_("Intel K1OM is 64bit only"));
10700 return ELF_TARGET_K1OM_FORMAT
;
10702 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10704 if (x86_elf_abi
!= I386_ABI
)
10705 as_fatal (_("Intel MCU is 32bit only"));
10706 return ELF_TARGET_IAMCU_FORMAT
;
10712 #if defined (OBJ_MACH_O)
10713 case bfd_target_mach_o_flavour
:
10714 if (flag_code
== CODE_64BIT
)
10716 use_rela_relocations
= 1;
10718 return "mach-o-x86-64";
10721 return "mach-o-i386";
10729 #endif /* OBJ_MAYBE_ more than one */
10732 md_undefined_symbol (char *name
)
10734 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10735 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10736 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10737 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10741 if (symbol_find (name
))
10742 as_bad (_("GOT already in symbol table"));
10743 GOT_symbol
= symbol_new (name
, undefined_section
,
10744 (valueT
) 0, &zero_address_frag
);
10751 /* Round up a section size to the appropriate boundary. */
10754 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10756 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10757 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10759 /* For a.out, force the section size to be aligned. If we don't do
10760 this, BFD will align it for us, but it will not write out the
10761 final bytes of the section. This may be a bug in BFD, but it is
10762 easier to fix it here since that is how the other a.out targets
10766 align
= bfd_get_section_alignment (stdoutput
, segment
);
10767 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10774 /* On the i386, PC-relative offsets are relative to the start of the
10775 next instruction. That is, the address of the offset, plus its
10776 size, since the offset is always the last part of the insn. */
10779 md_pcrel_from (fixS
*fixP
)
10781 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10787 s_bss (int ignore ATTRIBUTE_UNUSED
)
10791 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10793 obj_elf_section_change_hook ();
10795 temp
= get_absolute_expression ();
10796 subseg_set (bss_section
, (subsegT
) temp
);
10797 demand_empty_rest_of_line ();
10803 i386_validate_fix (fixS
*fixp
)
10805 if (fixp
->fx_subsy
)
10807 if (fixp
->fx_subsy
== GOT_symbol
)
10809 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10814 if (fixp
->fx_tcbit2
)
10815 fixp
->fx_r_type
= (fixp
->fx_tcbit
10816 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10817 : BFD_RELOC_X86_64_GOTPCRELX
);
10820 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10825 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10827 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10829 fixp
->fx_subsy
= 0;
10832 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10833 else if (!object_64bit
)
10835 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10836 && fixp
->fx_tcbit2
)
10837 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10843 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10846 bfd_reloc_code_real_type code
;
10848 switch (fixp
->fx_r_type
)
10850 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10851 case BFD_RELOC_SIZE32
:
10852 case BFD_RELOC_SIZE64
:
10853 if (S_IS_DEFINED (fixp
->fx_addsy
)
10854 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10856 /* Resolve size relocation against local symbol to size of
10857 the symbol plus addend. */
10858 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10859 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10860 && !fits_in_unsigned_long (value
))
10861 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10862 _("symbol size computation overflow"));
10863 fixp
->fx_addsy
= NULL
;
10864 fixp
->fx_subsy
= NULL
;
10865 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10869 /* Fall through. */
10871 case BFD_RELOC_X86_64_PLT32
:
10872 case BFD_RELOC_X86_64_GOT32
:
10873 case BFD_RELOC_X86_64_GOTPCREL
:
10874 case BFD_RELOC_X86_64_GOTPCRELX
:
10875 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10876 case BFD_RELOC_386_PLT32
:
10877 case BFD_RELOC_386_GOT32
:
10878 case BFD_RELOC_386_GOT32X
:
10879 case BFD_RELOC_386_GOTOFF
:
10880 case BFD_RELOC_386_GOTPC
:
10881 case BFD_RELOC_386_TLS_GD
:
10882 case BFD_RELOC_386_TLS_LDM
:
10883 case BFD_RELOC_386_TLS_LDO_32
:
10884 case BFD_RELOC_386_TLS_IE_32
:
10885 case BFD_RELOC_386_TLS_IE
:
10886 case BFD_RELOC_386_TLS_GOTIE
:
10887 case BFD_RELOC_386_TLS_LE_32
:
10888 case BFD_RELOC_386_TLS_LE
:
10889 case BFD_RELOC_386_TLS_GOTDESC
:
10890 case BFD_RELOC_386_TLS_DESC_CALL
:
10891 case BFD_RELOC_X86_64_TLSGD
:
10892 case BFD_RELOC_X86_64_TLSLD
:
10893 case BFD_RELOC_X86_64_DTPOFF32
:
10894 case BFD_RELOC_X86_64_DTPOFF64
:
10895 case BFD_RELOC_X86_64_GOTTPOFF
:
10896 case BFD_RELOC_X86_64_TPOFF32
:
10897 case BFD_RELOC_X86_64_TPOFF64
:
10898 case BFD_RELOC_X86_64_GOTOFF64
:
10899 case BFD_RELOC_X86_64_GOTPC32
:
10900 case BFD_RELOC_X86_64_GOT64
:
10901 case BFD_RELOC_X86_64_GOTPCREL64
:
10902 case BFD_RELOC_X86_64_GOTPC64
:
10903 case BFD_RELOC_X86_64_GOTPLT64
:
10904 case BFD_RELOC_X86_64_PLTOFF64
:
10905 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10906 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10907 case BFD_RELOC_RVA
:
10908 case BFD_RELOC_VTABLE_ENTRY
:
10909 case BFD_RELOC_VTABLE_INHERIT
:
10911 case BFD_RELOC_32_SECREL
:
10913 code
= fixp
->fx_r_type
;
10915 case BFD_RELOC_X86_64_32S
:
10916 if (!fixp
->fx_pcrel
)
10918 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10919 code
= fixp
->fx_r_type
;
10922 /* Fall through. */
10924 if (fixp
->fx_pcrel
)
10926 switch (fixp
->fx_size
)
10929 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10930 _("can not do %d byte pc-relative relocation"),
10932 code
= BFD_RELOC_32_PCREL
;
10934 case 1: code
= BFD_RELOC_8_PCREL
; break;
10935 case 2: code
= BFD_RELOC_16_PCREL
; break;
10936 case 4: code
= BFD_RELOC_32_PCREL
; break;
10938 case 8: code
= BFD_RELOC_64_PCREL
; break;
10944 switch (fixp
->fx_size
)
10947 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10948 _("can not do %d byte relocation"),
10950 code
= BFD_RELOC_32
;
10952 case 1: code
= BFD_RELOC_8
; break;
10953 case 2: code
= BFD_RELOC_16
; break;
10954 case 4: code
= BFD_RELOC_32
; break;
10956 case 8: code
= BFD_RELOC_64
; break;
10963 if ((code
== BFD_RELOC_32
10964 || code
== BFD_RELOC_32_PCREL
10965 || code
== BFD_RELOC_X86_64_32S
)
10967 && fixp
->fx_addsy
== GOT_symbol
)
10970 code
= BFD_RELOC_386_GOTPC
;
10972 code
= BFD_RELOC_X86_64_GOTPC32
;
10974 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10976 && fixp
->fx_addsy
== GOT_symbol
)
10978 code
= BFD_RELOC_X86_64_GOTPC64
;
10981 rel
= XNEW (arelent
);
10982 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10983 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10985 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10987 if (!use_rela_relocations
)
10989 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10990 vtable entry to be used in the relocation's section offset. */
10991 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10992 rel
->address
= fixp
->fx_offset
;
10993 #if defined (OBJ_COFF) && defined (TE_PE)
10994 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10995 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11000 /* Use the rela in 64bit mode. */
11003 if (disallow_64bit_reloc
)
11006 case BFD_RELOC_X86_64_DTPOFF64
:
11007 case BFD_RELOC_X86_64_TPOFF64
:
11008 case BFD_RELOC_64_PCREL
:
11009 case BFD_RELOC_X86_64_GOTOFF64
:
11010 case BFD_RELOC_X86_64_GOT64
:
11011 case BFD_RELOC_X86_64_GOTPCREL64
:
11012 case BFD_RELOC_X86_64_GOTPC64
:
11013 case BFD_RELOC_X86_64_GOTPLT64
:
11014 case BFD_RELOC_X86_64_PLTOFF64
:
11015 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11016 _("cannot represent relocation type %s in x32 mode"),
11017 bfd_get_reloc_code_name (code
));
11023 if (!fixp
->fx_pcrel
)
11024 rel
->addend
= fixp
->fx_offset
;
11028 case BFD_RELOC_X86_64_PLT32
:
11029 case BFD_RELOC_X86_64_GOT32
:
11030 case BFD_RELOC_X86_64_GOTPCREL
:
11031 case BFD_RELOC_X86_64_GOTPCRELX
:
11032 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11033 case BFD_RELOC_X86_64_TLSGD
:
11034 case BFD_RELOC_X86_64_TLSLD
:
11035 case BFD_RELOC_X86_64_GOTTPOFF
:
11036 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11037 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11038 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11041 rel
->addend
= (section
->vma
11043 + fixp
->fx_addnumber
11044 + md_pcrel_from (fixp
));
11049 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11050 if (rel
->howto
== NULL
)
11052 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11053 _("cannot represent relocation type %s"),
11054 bfd_get_reloc_code_name (code
));
11055 /* Set howto to a garbage value so that we can keep going. */
11056 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11057 gas_assert (rel
->howto
!= NULL
);
11063 #include "tc-i386-intel.c"
11066 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11068 int saved_naked_reg
;
11069 char saved_register_dot
;
11071 saved_naked_reg
= allow_naked_reg
;
11072 allow_naked_reg
= 1;
11073 saved_register_dot
= register_chars
['.'];
11074 register_chars
['.'] = '.';
11075 allow_pseudo_reg
= 1;
11076 expression_and_evaluate (exp
);
11077 allow_pseudo_reg
= 0;
11078 register_chars
['.'] = saved_register_dot
;
11079 allow_naked_reg
= saved_naked_reg
;
11081 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11083 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11085 exp
->X_op
= O_constant
;
11086 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11087 .dw2_regnum
[flag_code
>> 1];
11090 exp
->X_op
= O_illegal
;
11095 tc_x86_frame_initial_instructions (void)
11097 static unsigned int sp_regno
[2];
11099 if (!sp_regno
[flag_code
>> 1])
11101 char *saved_input
= input_line_pointer
;
11102 char sp
[][4] = {"esp", "rsp"};
11105 input_line_pointer
= sp
[flag_code
>> 1];
11106 tc_x86_parse_to_dw2regnum (&exp
);
11107 gas_assert (exp
.X_op
== O_constant
);
11108 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11109 input_line_pointer
= saved_input
;
11112 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11113 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11117 x86_dwarf2_addr_size (void)
11119 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11120 if (x86_elf_abi
== X86_64_X32_ABI
)
11123 return bfd_arch_bits_per_address (stdoutput
) / 8;
11127 i386_elf_section_type (const char *str
, size_t len
)
11129 if (flag_code
== CODE_64BIT
11130 && len
== sizeof ("unwind") - 1
11131 && strncmp (str
, "unwind", 6) == 0)
11132 return SHT_X86_64_UNWIND
;
11139 i386_solaris_fix_up_eh_frame (segT sec
)
11141 if (flag_code
== CODE_64BIT
)
11142 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11148 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11152 exp
.X_op
= O_secrel
;
11153 exp
.X_add_symbol
= symbol
;
11154 exp
.X_add_number
= 0;
11155 emit_expr (&exp
, size
);
11159 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11160 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11163 x86_64_section_letter (int letter
, const char **ptr_msg
)
11165 if (flag_code
== CODE_64BIT
)
11168 return SHF_X86_64_LARGE
;
11170 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11173 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11178 x86_64_section_word (char *str
, size_t len
)
11180 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11181 return SHF_X86_64_LARGE
;
11187 handle_large_common (int small ATTRIBUTE_UNUSED
)
11189 if (flag_code
!= CODE_64BIT
)
11191 s_comm_internal (0, elf_common_parse
);
11192 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11196 static segT lbss_section
;
11197 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11198 asection
*saved_bss_section
= bss_section
;
11200 if (lbss_section
== NULL
)
11202 flagword applicable
;
11203 segT seg
= now_seg
;
11204 subsegT subseg
= now_subseg
;
11206 /* The .lbss section is for local .largecomm symbols. */
11207 lbss_section
= subseg_new (".lbss", 0);
11208 applicable
= bfd_applicable_section_flags (stdoutput
);
11209 bfd_set_section_flags (stdoutput
, lbss_section
,
11210 applicable
& SEC_ALLOC
);
11211 seg_info (lbss_section
)->bss
= 1;
11213 subseg_set (seg
, subseg
);
11216 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11217 bss_section
= lbss_section
;
11219 s_comm_internal (0, elf_common_parse
);
11221 elf_com_section_ptr
= saved_com_section_ptr
;
11222 bss_section
= saved_bss_section
;
11225 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */