1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef INFER_ADDR_PREFIX
48 #define INFER_ADDR_PREFIX 1
52 #define DEFAULT_ARCH "i386"
57 #define INLINE __inline__
63 /* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
73 #define HLE_PREFIX REP_PREFIX
74 #define BND_PREFIX REP_PREFIX
76 #define REX_PREFIX 6 /* must come last. */
77 #define MAX_PREFIXES 7 /* max prefixes per opcode */
79 /* we define the syntax here (modulo base,index,scale syntax) */
80 #define REGISTER_PREFIX '%'
81 #define IMMEDIATE_PREFIX '$'
82 #define ABSOLUTE_PREFIX '*'
84 /* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86 #define WORD_MNEM_SUFFIX 'w'
87 #define BYTE_MNEM_SUFFIX 'b'
88 #define SHORT_MNEM_SUFFIX 's'
89 #define LONG_MNEM_SUFFIX 'l'
90 #define QWORD_MNEM_SUFFIX 'q'
91 /* Intel Syntax. Use a non-ascii letter since since it never appears
93 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
95 #define END_OF_INSN '\0'
97 /* This matches the C -> StaticRounding alias in the opcode table. */
98 #define commutative staticrounding
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
109 const insn_template
*start
;
110 const insn_template
*end
;
114 /* 386 operand encoding bytes: see 386 book for details of this. */
117 unsigned int regmem
; /* codes register or memory operand */
118 unsigned int reg
; /* codes register operand (or extended opcode) */
119 unsigned int mode
; /* how to interpret regmem & reg */
123 /* x86-64 extension prefix. */
124 typedef int rex_byte
;
126 /* 386 opcode byte to code indirect addressing. */
135 /* x86 arch names, types and features */
138 const char *name
; /* arch name */
139 unsigned int len
; /* arch string length */
140 enum processor_type type
; /* arch type */
141 i386_cpu_flags flags
; /* cpu feature flags */
142 unsigned int skip
; /* show_arch should skip this. */
146 /* Used to turn off indicated flags. */
149 const char *name
; /* arch name */
150 unsigned int len
; /* arch string length */
151 i386_cpu_flags flags
; /* cpu feature flags */
155 static void update_code_flag (int, int);
156 static void set_code_flag (int);
157 static void set_16bit_gcc_code_flag (int);
158 static void set_intel_syntax (int);
159 static void set_intel_mnemonic (int);
160 static void set_allow_index_reg (int);
161 static void set_check (int);
162 static void set_cpu_arch (int);
164 static void pe_directive_secrel (int);
166 static void signed_cons (int);
167 static char *output_invalid (int c
);
168 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
170 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
172 static int i386_att_operand (char *);
173 static int i386_intel_operand (char *, int);
174 static int i386_intel_simplify (expressionS
*);
175 static int i386_intel_parse_name (const char *, expressionS
*);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static enum flag_code
i386_addressing_mode (void);
182 static void optimize_imm (void);
183 static void optimize_disp (void);
184 static const insn_template
*match_template (char);
185 static int check_string (void);
186 static int process_suffix (void);
187 static int check_byte_reg (void);
188 static int check_long_reg (void);
189 static int check_qword_reg (void);
190 static int check_word_reg (void);
191 static int finalize_imm (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
203 /* GNU_PROPERTY_X86_ISA_1_USED. */
204 static unsigned int x86_isa_1_used
;
205 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
206 static unsigned int x86_feature_2_used
;
207 /* Generate x86 used ISA and feature properties. */
208 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
211 static const char *default_arch
= DEFAULT_ARCH
;
213 /* This struct describes rounding control and SAE in the instruction. */
227 static struct RC_Operation rc_op
;
229 /* The struct describes masking, applied to OPERAND in the instruction.
230 MASK is a pointer to the corresponding mask register. ZEROING tells
231 whether merging or zeroing mask is used. */
232 struct Mask_Operation
234 const reg_entry
*mask
;
235 unsigned int zeroing
;
236 /* The operand where this operation is associated. */
240 static struct Mask_Operation mask_op
;
242 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
244 struct Broadcast_Operation
246 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
249 /* Index of broadcasted operand. */
252 /* Number of bytes to broadcast. */
256 static struct Broadcast_Operation broadcast_op
;
261 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
262 unsigned char bytes
[4];
264 /* Destination or source register specifier. */
265 const reg_entry
*register_specifier
;
268 /* 'md_assemble ()' gathers together information and puts it into a
275 const reg_entry
*regs
;
280 operand_size_mismatch
,
281 operand_type_mismatch
,
282 register_type_mismatch
,
283 number_of_operands_mismatch
,
284 invalid_instruction_suffix
,
286 unsupported_with_intel_mnemonic
,
289 invalid_vsib_address
,
290 invalid_vector_register_set
,
291 unsupported_vector_index_register
,
292 unsupported_broadcast
,
295 mask_not_on_destination
,
298 rc_sae_operand_not_last_imm
,
299 invalid_register_operand
,
304 /* TM holds the template for the insn were currently assembling. */
307 /* SUFFIX holds the instruction size suffix for byte, word, dword
308 or qword, if given. */
311 /* OPERANDS gives the number of given operands. */
312 unsigned int operands
;
314 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
315 of given register, displacement, memory operands and immediate
317 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
319 /* TYPES [i] is the type (see above #defines) which tells us how to
320 use OP[i] for the corresponding operand. */
321 i386_operand_type types
[MAX_OPERANDS
];
323 /* Displacement expression, immediate expression, or register for each
325 union i386_op op
[MAX_OPERANDS
];
327 /* Flags for operands. */
328 unsigned int flags
[MAX_OPERANDS
];
329 #define Operand_PCrel 1
330 #define Operand_Mem 2
332 /* Relocation type for operand */
333 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
335 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
336 the base index byte below. */
337 const reg_entry
*base_reg
;
338 const reg_entry
*index_reg
;
339 unsigned int log2_scale_factor
;
341 /* SEG gives the seg_entries of this insn. They are zero unless
342 explicit segment overrides are given. */
343 const seg_entry
*seg
[2];
345 /* Copied first memory operand string, for re-checking. */
348 /* PREFIX holds all the given prefix opcodes (usually null).
349 PREFIXES is the number of prefix opcodes. */
350 unsigned int prefixes
;
351 unsigned char prefix
[MAX_PREFIXES
];
353 /* Register is in low 3 bits of opcode. */
354 bfd_boolean short_form
;
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 static enum x86_64_isa
602 amd64
= 1, /* AMD64 ISA. */
603 intel64
/* Intel64 ISA. */
606 /* 1 for intel mnemonic,
607 0 if att mnemonic. */
608 static int intel_mnemonic
= !SYSV386_COMPAT
;
610 /* 1 if pseudo registers are permitted. */
611 static int allow_pseudo_reg
= 0;
613 /* 1 if register prefix % not required. */
614 static int allow_naked_reg
= 0;
616 /* 1 if the assembler should add BND prefix for all control-transferring
617 instructions supporting it, even if this prefix wasn't specified
619 static int add_bnd_prefix
= 0;
621 /* 1 if pseudo index register, eiz/riz, is allowed . */
622 static int allow_index_reg
= 0;
624 /* 1 if the assembler should ignore LOCK prefix, even if it was
625 specified explicitly. */
626 static int omit_lock_prefix
= 0;
628 /* 1 if the assembler should encode lfence, mfence, and sfence as
629 "lock addl $0, (%{re}sp)". */
630 static int avoid_fence
= 0;
632 /* Type of the previous instruction. */
647 /* 1 if the assembler should generate relax relocations. */
649 static int generate_relax_relocations
650 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
652 static enum check_kind
658 sse_check
, operand_check
= check_warning
;
660 /* Non-zero if branches should be aligned within power of 2 boundary. */
661 static int align_branch_power
= 0;
663 /* Types of branches to align. */
664 enum align_branch_kind
666 align_branch_none
= 0,
667 align_branch_jcc
= 1,
668 align_branch_fused
= 2,
669 align_branch_jmp
= 3,
670 align_branch_call
= 4,
671 align_branch_indirect
= 5,
675 /* Type bits of branches to align. */
676 enum align_branch_bit
678 align_branch_jcc_bit
= 1 << align_branch_jcc
,
679 align_branch_fused_bit
= 1 << align_branch_fused
,
680 align_branch_jmp_bit
= 1 << align_branch_jmp
,
681 align_branch_call_bit
= 1 << align_branch_call
,
682 align_branch_indirect_bit
= 1 << align_branch_indirect
,
683 align_branch_ret_bit
= 1 << align_branch_ret
686 static unsigned int align_branch
= (align_branch_jcc_bit
687 | align_branch_fused_bit
688 | align_branch_jmp_bit
);
690 /* The maximum padding size for fused jcc. CMP like instruction can
691 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
693 #define MAX_FUSED_JCC_PADDING_SIZE 20
695 /* The maximum number of prefixes added for an instruction. */
696 static unsigned int align_branch_prefix_size
= 5;
699 1. Clear the REX_W bit with register operand if possible.
700 2. Above plus use 128bit vector instruction to clear the full vector
703 static int optimize
= 0;
706 1. Clear the REX_W bit with register operand if possible.
707 2. Above plus use 128bit vector instruction to clear the full vector
709 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
712 static int optimize_for_space
= 0;
714 /* Register prefix used for error message. */
715 static const char *register_prefix
= "%";
717 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
718 leave, push, and pop instructions so that gcc has the same stack
719 frame as in 32 bit mode. */
720 static char stackop_size
= '\0';
722 /* Non-zero to optimize code alignment. */
723 int optimize_align_code
= 1;
725 /* Non-zero to quieten some warnings. */
726 static int quiet_warnings
= 0;
729 static const char *cpu_arch_name
= NULL
;
730 static char *cpu_sub_arch_name
= NULL
;
732 /* CPU feature flags. */
733 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
735 /* If we have selected a cpu we are generating instructions for. */
736 static int cpu_arch_tune_set
= 0;
738 /* Cpu we are generating instructions for. */
739 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
741 /* CPU feature flags of cpu we are generating instructions for. */
742 static i386_cpu_flags cpu_arch_tune_flags
;
744 /* CPU instruction set architecture used. */
745 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
747 /* CPU feature flags of instruction set architecture used. */
748 i386_cpu_flags cpu_arch_isa_flags
;
750 /* If set, conditional jumps are not automatically promoted to handle
751 larger than a byte offset. */
752 static unsigned int no_cond_jump_promotion
= 0;
754 /* Encode SSE instructions with VEX prefix. */
755 static unsigned int sse2avx
;
757 /* Encode scalar AVX instructions with specific vector length. */
764 /* Encode VEX WIG instructions with specific vex.w. */
771 /* Encode scalar EVEX LIG instructions with specific vector length. */
779 /* Encode EVEX WIG instructions with specific evex.w. */
786 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
787 static enum rc_type evexrcig
= rne
;
789 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
790 static symbolS
*GOT_symbol
;
792 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
793 unsigned int x86_dwarf2_return_column
;
795 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
796 int x86_cie_data_alignment
;
798 /* Interface to relax_segment.
799 There are 3 major relax states for 386 jump insns because the
800 different types of jumps add different sizes to frags when we're
801 figuring out what sort of jump to choose to reach a given label.
803 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
804 branches which are handled by md_estimate_size_before_relax() and
805 i386_generic_table_relax_frag(). */
808 #define UNCOND_JUMP 0
810 #define COND_JUMP86 2
811 #define BRANCH_PADDING 3
812 #define BRANCH_PREFIX 4
813 #define FUSED_JCC_PADDING 5
818 #define SMALL16 (SMALL | CODE16)
820 #define BIG16 (BIG | CODE16)
824 #define INLINE __inline__
830 #define ENCODE_RELAX_STATE(type, size) \
831 ((relax_substateT) (((type) << 2) | (size)))
832 #define TYPE_FROM_RELAX_STATE(s) \
834 #define DISP_SIZE_FROM_RELAX_STATE(s) \
835 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
837 /* This table is used by relax_frag to promote short jumps to long
838 ones where necessary. SMALL (short) jumps may be promoted to BIG
839 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
840 don't allow a short jump in a 32 bit code segment to be promoted to
841 a 16 bit offset jump because it's slower (requires data size
842 prefix), and doesn't work, unless the destination is in the bottom
843 64k of the code segment (The top 16 bits of eip are zeroed). */
845 const relax_typeS md_relax_table
[] =
848 1) most positive reach of this state,
849 2) most negative reach of this state,
850 3) how many bytes this mode will have in the variable part of the frag
851 4) which index into the table to try if we can't fit into this one. */
853 /* UNCOND_JUMP states. */
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
855 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
856 /* dword jmp adds 4 bytes to frag:
857 0 extra opcode bytes, 4 displacement bytes. */
859 /* word jmp adds 2 byte2 to frag:
860 0 extra opcode bytes, 2 displacement bytes. */
863 /* COND_JUMP states. */
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
865 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
866 /* dword conditionals adds 5 bytes to frag:
867 1 extra opcode byte, 4 displacement bytes. */
869 /* word conditionals add 3 bytes to frag:
870 1 extra opcode byte, 2 displacement bytes. */
873 /* COND_JUMP86 states. */
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
875 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
876 /* dword conditionals adds 5 bytes to frag:
877 1 extra opcode byte, 4 displacement bytes. */
879 /* word conditionals add 4 bytes to frag:
880 1 displacement byte and a 3 byte long branch insn. */
884 static const arch_entry cpu_arch
[] =
886 /* Do not replace the first two entries - i386_target_format()
887 relies on them being there in this order. */
888 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
889 CPU_GENERIC32_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
891 CPU_GENERIC64_FLAGS
, 0 },
892 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
898 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
900 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
902 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
904 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
906 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
908 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
909 CPU_PENTIUMPRO_FLAGS
, 0 },
910 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
912 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
914 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
916 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
918 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
919 CPU_NOCONA_FLAGS
, 0 },
920 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
922 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
924 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
925 CPU_CORE2_FLAGS
, 1 },
926 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
927 CPU_CORE2_FLAGS
, 0 },
928 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
929 CPU_COREI7_FLAGS
, 0 },
930 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
932 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
934 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
935 CPU_IAMCU_FLAGS
, 0 },
936 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
938 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
940 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
941 CPU_ATHLON_FLAGS
, 0 },
942 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
944 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
946 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
948 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
949 CPU_AMDFAM10_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
951 CPU_BDVER1_FLAGS
, 0 },
952 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
953 CPU_BDVER2_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
955 CPU_BDVER3_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
957 CPU_BDVER4_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
959 CPU_ZNVER1_FLAGS
, 0 },
960 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
961 CPU_ZNVER2_FLAGS
, 0 },
962 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
963 CPU_BTVER1_FLAGS
, 0 },
964 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
965 CPU_BTVER2_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
986 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
987 CPU_SSE4A_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
989 CPU_SSSE3_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
991 CPU_SSE4_1_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
993 CPU_SSE4_2_FLAGS
, 0 },
994 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
995 CPU_SSE4_2_FLAGS
, 0 },
996 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
998 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
1000 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512F_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512CD_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512ER_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512PF_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512DQ_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1011 CPU_AVX512BW_FLAGS
, 0 },
1012 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1013 CPU_AVX512VL_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1017 CPU_VMFUNC_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1020 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1021 CPU_XSAVE_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1023 CPU_XSAVEOPT_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1025 CPU_XSAVEC_FLAGS
, 0 },
1026 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1027 CPU_XSAVES_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1030 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1031 CPU_PCLMUL_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1033 CPU_PCLMUL_FLAGS
, 1 },
1034 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1035 CPU_FSGSBASE_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1037 CPU_RDRND_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1039 CPU_F16C_FLAGS
, 0 },
1040 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1041 CPU_BMI2_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1044 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1045 CPU_FMA4_FLAGS
, 0 },
1046 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1048 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1050 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1051 CPU_MOVBE_FLAGS
, 0 },
1052 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1053 CPU_CX16_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1056 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1057 CPU_LZCNT_FLAGS
, 0 },
1058 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1060 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1062 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1063 CPU_INVPCID_FLAGS
, 0 },
1064 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1065 CPU_CLFLUSH_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1068 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1069 CPU_SYSCALL_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1071 CPU_RDTSCP_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1073 CPU_3DNOW_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1075 CPU_3DNOWA_FLAGS
, 0 },
1076 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1077 CPU_PADLOCK_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1079 CPU_SVME_FLAGS
, 1 },
1080 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1081 CPU_SVME_FLAGS
, 0 },
1082 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1083 CPU_SSE4A_FLAGS
, 0 },
1084 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1086 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1088 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1090 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1092 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1093 CPU_RDSEED_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1095 CPU_PRFCHW_FLAGS
, 0 },
1096 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1097 CPU_SMAP_FLAGS
, 0 },
1098 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1100 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1102 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1103 CPU_CLFLUSHOPT_FLAGS
, 0 },
1104 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1105 CPU_PREFETCHWT1_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1108 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1109 CPU_CLWB_FLAGS
, 0 },
1110 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1111 CPU_AVX512IFMA_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1113 CPU_AVX512VBMI_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1115 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1117 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1119 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1121 CPU_AVX512_VBMI2_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1123 CPU_AVX512_VNNI_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1125 CPU_AVX512_BITALG_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1127 CPU_CLZERO_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1129 CPU_MWAITX_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1131 CPU_OSPKE_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1133 CPU_RDPID_FLAGS
, 0 },
1134 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1135 CPU_PTWRITE_FLAGS
, 0 },
1136 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1138 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1139 CPU_SHSTK_FLAGS
, 0 },
1140 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1141 CPU_GFNI_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1143 CPU_VAES_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1145 CPU_VPCLMULQDQ_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1147 CPU_WBNOINVD_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1149 CPU_PCONFIG_FLAGS
, 0 },
1150 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1151 CPU_WAITPKG_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1153 CPU_CLDEMOTE_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1155 CPU_MOVDIRI_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1157 CPU_MOVDIR64B_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1159 CPU_AVX512_BF16_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1161 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1163 CPU_ENQCMD_FLAGS
, 0 },
1164 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1165 CPU_RDPRU_FLAGS
, 0 },
1166 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1167 CPU_MCOMMIT_FLAGS
, 0 },
1170 static const noarch_entry cpu_noarch
[] =
1172 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1173 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1174 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1175 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1176 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1177 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1178 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1179 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1180 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS
},
1183 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1184 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1185 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1186 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1200 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1201 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1202 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1203 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1204 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1205 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1206 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1207 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1208 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1209 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1210 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1214 /* Like s_lcomm_internal in gas/read.c but the alignment string
1215 is allowed to be optional. */
1218 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1225 && *input_line_pointer
== ',')
1227 align
= parse_align (needs_align
- 1);
1229 if (align
== (addressT
) -1)
1244 bss_alloc (symbolP
, size
, align
);
1249 pe_lcomm (int needs_align
)
1251 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1255 const pseudo_typeS md_pseudo_table
[] =
1257 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1258 {"align", s_align_bytes
, 0},
1260 {"align", s_align_ptwo
, 0},
1262 {"arch", set_cpu_arch
, 0},
1266 {"lcomm", pe_lcomm
, 1},
1268 {"ffloat", float_cons
, 'f'},
1269 {"dfloat", float_cons
, 'd'},
1270 {"tfloat", float_cons
, 'x'},
1272 {"slong", signed_cons
, 4},
1273 {"noopt", s_ignore
, 0},
1274 {"optim", s_ignore
, 0},
1275 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1276 {"code16", set_code_flag
, CODE_16BIT
},
1277 {"code32", set_code_flag
, CODE_32BIT
},
1279 {"code64", set_code_flag
, CODE_64BIT
},
1281 {"intel_syntax", set_intel_syntax
, 1},
1282 {"att_syntax", set_intel_syntax
, 0},
1283 {"intel_mnemonic", set_intel_mnemonic
, 1},
1284 {"att_mnemonic", set_intel_mnemonic
, 0},
1285 {"allow_index_reg", set_allow_index_reg
, 1},
1286 {"disallow_index_reg", set_allow_index_reg
, 0},
1287 {"sse_check", set_check
, 0},
1288 {"operand_check", set_check
, 1},
1289 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1290 {"largecomm", handle_large_common
, 0},
1292 {"file", dwarf2_directive_file
, 0},
1293 {"loc", dwarf2_directive_loc
, 0},
1294 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1297 {"secrel32", pe_directive_secrel
, 0},
1302 /* For interface with expression (). */
1303 extern char *input_line_pointer
;
1305 /* Hash table for instruction mnemonic lookup. */
1306 static struct hash_control
*op_hash
;
1308 /* Hash table for register lookup. */
1309 static struct hash_control
*reg_hash
;
1311 /* Various efficient no-op patterns for aligning code labels.
1312 Note: Don't try to assemble the instructions in the comments.
1313 0L and 0w are not legal. */
1314 static const unsigned char f32_1
[] =
1316 static const unsigned char f32_2
[] =
1317 {0x66,0x90}; /* xchg %ax,%ax */
1318 static const unsigned char f32_3
[] =
1319 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1320 static const unsigned char f32_4
[] =
1321 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1322 static const unsigned char f32_6
[] =
1323 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1324 static const unsigned char f32_7
[] =
1325 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1326 static const unsigned char f16_3
[] =
1327 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1328 static const unsigned char f16_4
[] =
1329 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1330 static const unsigned char jump_disp8
[] =
1331 {0xeb}; /* jmp disp8 */
1332 static const unsigned char jump32_disp32
[] =
1333 {0xe9}; /* jmp disp32 */
1334 static const unsigned char jump16_disp32
[] =
1335 {0x66,0xe9}; /* jmp disp32 */
1336 /* 32-bit NOPs patterns. */
1337 static const unsigned char *const f32_patt
[] = {
1338 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1340 /* 16-bit NOPs patterns. */
1341 static const unsigned char *const f16_patt
[] = {
1342 f32_1
, f32_2
, f16_3
, f16_4
1344 /* nopl (%[re]ax) */
1345 static const unsigned char alt_3
[] =
1347 /* nopl 0(%[re]ax) */
1348 static const unsigned char alt_4
[] =
1349 {0x0f,0x1f,0x40,0x00};
1350 /* nopl 0(%[re]ax,%[re]ax,1) */
1351 static const unsigned char alt_5
[] =
1352 {0x0f,0x1f,0x44,0x00,0x00};
1353 /* nopw 0(%[re]ax,%[re]ax,1) */
1354 static const unsigned char alt_6
[] =
1355 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1356 /* nopl 0L(%[re]ax) */
1357 static const unsigned char alt_7
[] =
1358 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1359 /* nopl 0L(%[re]ax,%[re]ax,1) */
1360 static const unsigned char alt_8
[] =
1361 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1362 /* nopw 0L(%[re]ax,%[re]ax,1) */
1363 static const unsigned char alt_9
[] =
1364 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1365 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1366 static const unsigned char alt_10
[] =
1367 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1368 /* data16 nopw %cs:0L(%eax,%eax,1) */
1369 static const unsigned char alt_11
[] =
1370 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1371 /* 32-bit and 64-bit NOPs patterns. */
1372 static const unsigned char *const alt_patt
[] = {
1373 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1374 alt_9
, alt_10
, alt_11
1377 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1378 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1381 i386_output_nops (char *where
, const unsigned char *const *patt
,
1382 int count
, int max_single_nop_size
)
1385 /* Place the longer NOP first. */
1388 const unsigned char *nops
;
1390 if (max_single_nop_size
< 1)
1392 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1393 max_single_nop_size
);
1397 nops
= patt
[max_single_nop_size
- 1];
1399 /* Use the smaller one if the requsted one isn't available. */
1402 max_single_nop_size
--;
1403 nops
= patt
[max_single_nop_size
- 1];
1406 last
= count
% max_single_nop_size
;
1409 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1410 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1414 nops
= patt
[last
- 1];
1417 /* Use the smaller one plus one-byte NOP if the needed one
1420 nops
= patt
[last
- 1];
1421 memcpy (where
+ offset
, nops
, last
);
1422 where
[offset
+ last
] = *patt
[0];
1425 memcpy (where
+ offset
, nops
, last
);
1430 fits_in_imm7 (offsetT num
)
1432 return (num
& 0x7f) == num
;
1436 fits_in_imm31 (offsetT num
)
1438 return (num
& 0x7fffffff) == num
;
1441 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1442 single NOP instruction LIMIT. */
1445 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1447 const unsigned char *const *patt
= NULL
;
1448 int max_single_nop_size
;
1449 /* Maximum number of NOPs before switching to jump over NOPs. */
1450 int max_number_of_nops
;
1452 switch (fragP
->fr_type
)
1457 case rs_machine_dependent
:
1458 /* Allow NOP padding for jumps and calls. */
1459 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1460 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1467 /* We need to decide which NOP sequence to use for 32bit and
1468 64bit. When -mtune= is used:
1470 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1471 PROCESSOR_GENERIC32, f32_patt will be used.
1472 2. For the rest, alt_patt will be used.
1474 When -mtune= isn't used, alt_patt will be used if
1475 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1478 When -march= or .arch is used, we can't use anything beyond
1479 cpu_arch_isa_flags. */
1481 if (flag_code
== CODE_16BIT
)
1484 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1485 /* Limit number of NOPs to 2 in 16-bit mode. */
1486 max_number_of_nops
= 2;
1490 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1492 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1493 switch (cpu_arch_tune
)
1495 case PROCESSOR_UNKNOWN
:
1496 /* We use cpu_arch_isa_flags to check if we SHOULD
1497 optimize with nops. */
1498 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1503 case PROCESSOR_PENTIUM4
:
1504 case PROCESSOR_NOCONA
:
1505 case PROCESSOR_CORE
:
1506 case PROCESSOR_CORE2
:
1507 case PROCESSOR_COREI7
:
1508 case PROCESSOR_L1OM
:
1509 case PROCESSOR_K1OM
:
1510 case PROCESSOR_GENERIC64
:
1512 case PROCESSOR_ATHLON
:
1514 case PROCESSOR_AMDFAM10
:
1516 case PROCESSOR_ZNVER
:
1520 case PROCESSOR_I386
:
1521 case PROCESSOR_I486
:
1522 case PROCESSOR_PENTIUM
:
1523 case PROCESSOR_PENTIUMPRO
:
1524 case PROCESSOR_IAMCU
:
1525 case PROCESSOR_GENERIC32
:
1532 switch (fragP
->tc_frag_data
.tune
)
1534 case PROCESSOR_UNKNOWN
:
1535 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1536 PROCESSOR_UNKNOWN. */
1540 case PROCESSOR_I386
:
1541 case PROCESSOR_I486
:
1542 case PROCESSOR_PENTIUM
:
1543 case PROCESSOR_IAMCU
:
1545 case PROCESSOR_ATHLON
:
1547 case PROCESSOR_AMDFAM10
:
1549 case PROCESSOR_ZNVER
:
1551 case PROCESSOR_GENERIC32
:
1552 /* We use cpu_arch_isa_flags to check if we CAN optimize
1554 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1559 case PROCESSOR_PENTIUMPRO
:
1560 case PROCESSOR_PENTIUM4
:
1561 case PROCESSOR_NOCONA
:
1562 case PROCESSOR_CORE
:
1563 case PROCESSOR_CORE2
:
1564 case PROCESSOR_COREI7
:
1565 case PROCESSOR_L1OM
:
1566 case PROCESSOR_K1OM
:
1567 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1572 case PROCESSOR_GENERIC64
:
1578 if (patt
== f32_patt
)
1580 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1581 /* Limit number of NOPs to 2 for older processors. */
1582 max_number_of_nops
= 2;
1586 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1587 /* Limit number of NOPs to 7 for newer processors. */
1588 max_number_of_nops
= 7;
1593 limit
= max_single_nop_size
;
1595 if (fragP
->fr_type
== rs_fill_nop
)
1597 /* Output NOPs for .nop directive. */
1598 if (limit
> max_single_nop_size
)
1600 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1601 _("invalid single nop size: %d "
1602 "(expect within [0, %d])"),
1603 limit
, max_single_nop_size
);
1607 else if (fragP
->fr_type
!= rs_machine_dependent
)
1608 fragP
->fr_var
= count
;
1610 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1612 /* Generate jump over NOPs. */
1613 offsetT disp
= count
- 2;
1614 if (fits_in_imm7 (disp
))
1616 /* Use "jmp disp8" if possible. */
1618 where
[0] = jump_disp8
[0];
1624 unsigned int size_of_jump
;
1626 if (flag_code
== CODE_16BIT
)
1628 where
[0] = jump16_disp32
[0];
1629 where
[1] = jump16_disp32
[1];
1634 where
[0] = jump32_disp32
[0];
1638 count
-= size_of_jump
+ 4;
1639 if (!fits_in_imm31 (count
))
1641 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1642 _("jump over nop padding out of range"));
1646 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1647 where
+= size_of_jump
+ 4;
1651 /* Generate multiple NOPs. */
1652 i386_output_nops (where
, patt
, count
, limit
);
1656 operand_type_all_zero (const union i386_operand_type
*x
)
1658 switch (ARRAY_SIZE(x
->array
))
1669 return !x
->array
[0];
1676 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1678 switch (ARRAY_SIZE(x
->array
))
1694 x
->bitfield
.class = ClassNone
;
1695 x
->bitfield
.instance
= InstanceNone
;
1699 operand_type_equal (const union i386_operand_type
*x
,
1700 const union i386_operand_type
*y
)
1702 switch (ARRAY_SIZE(x
->array
))
1705 if (x
->array
[2] != y
->array
[2])
1709 if (x
->array
[1] != y
->array
[1])
1713 return x
->array
[0] == y
->array
[0];
1721 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1723 switch (ARRAY_SIZE(x
->array
))
1738 return !x
->array
[0];
1745 cpu_flags_equal (const union i386_cpu_flags
*x
,
1746 const union i386_cpu_flags
*y
)
1748 switch (ARRAY_SIZE(x
->array
))
1751 if (x
->array
[3] != y
->array
[3])
1755 if (x
->array
[2] != y
->array
[2])
1759 if (x
->array
[1] != y
->array
[1])
1763 return x
->array
[0] == y
->array
[0];
1771 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1773 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1774 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1777 static INLINE i386_cpu_flags
1778 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1780 switch (ARRAY_SIZE (x
.array
))
1783 x
.array
[3] &= y
.array
[3];
1786 x
.array
[2] &= y
.array
[2];
1789 x
.array
[1] &= y
.array
[1];
1792 x
.array
[0] &= y
.array
[0];
1800 static INLINE i386_cpu_flags
1801 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1803 switch (ARRAY_SIZE (x
.array
))
1806 x
.array
[3] |= y
.array
[3];
1809 x
.array
[2] |= y
.array
[2];
1812 x
.array
[1] |= y
.array
[1];
1815 x
.array
[0] |= y
.array
[0];
1823 static INLINE i386_cpu_flags
1824 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1826 switch (ARRAY_SIZE (x
.array
))
1829 x
.array
[3] &= ~y
.array
[3];
1832 x
.array
[2] &= ~y
.array
[2];
1835 x
.array
[1] &= ~y
.array
[1];
1838 x
.array
[0] &= ~y
.array
[0];
1846 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1848 #define CPU_FLAGS_ARCH_MATCH 0x1
1849 #define CPU_FLAGS_64BIT_MATCH 0x2
1851 #define CPU_FLAGS_PERFECT_MATCH \
1852 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1854 /* Return CPU flags match bits. */
1857 cpu_flags_match (const insn_template
*t
)
1859 i386_cpu_flags x
= t
->cpu_flags
;
1860 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1862 x
.bitfield
.cpu64
= 0;
1863 x
.bitfield
.cpuno64
= 0;
1865 if (cpu_flags_all_zero (&x
))
1867 /* This instruction is available on all archs. */
1868 match
|= CPU_FLAGS_ARCH_MATCH
;
1872 /* This instruction is available only on some archs. */
1873 i386_cpu_flags cpu
= cpu_arch_flags
;
1875 /* AVX512VL is no standalone feature - match it and then strip it. */
1876 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1878 x
.bitfield
.cpuavx512vl
= 0;
1880 cpu
= cpu_flags_and (x
, cpu
);
1881 if (!cpu_flags_all_zero (&cpu
))
1883 if (x
.bitfield
.cpuavx
)
1885 /* We need to check a few extra flags with AVX. */
1886 if (cpu
.bitfield
.cpuavx
1887 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1888 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1889 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1890 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1891 match
|= CPU_FLAGS_ARCH_MATCH
;
1893 else if (x
.bitfield
.cpuavx512f
)
1895 /* We need to check a few extra flags with AVX512F. */
1896 if (cpu
.bitfield
.cpuavx512f
1897 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1898 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1899 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1900 match
|= CPU_FLAGS_ARCH_MATCH
;
1903 match
|= CPU_FLAGS_ARCH_MATCH
;
1909 static INLINE i386_operand_type
1910 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1912 if (x
.bitfield
.class != y
.bitfield
.class)
1913 x
.bitfield
.class = ClassNone
;
1914 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1915 x
.bitfield
.instance
= InstanceNone
;
1917 switch (ARRAY_SIZE (x
.array
))
1920 x
.array
[2] &= y
.array
[2];
1923 x
.array
[1] &= y
.array
[1];
1926 x
.array
[0] &= y
.array
[0];
1934 static INLINE i386_operand_type
1935 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1937 gas_assert (y
.bitfield
.class == ClassNone
);
1938 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1940 switch (ARRAY_SIZE (x
.array
))
1943 x
.array
[2] &= ~y
.array
[2];
1946 x
.array
[1] &= ~y
.array
[1];
1949 x
.array
[0] &= ~y
.array
[0];
1957 static INLINE i386_operand_type
1958 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1960 gas_assert (x
.bitfield
.class == ClassNone
||
1961 y
.bitfield
.class == ClassNone
||
1962 x
.bitfield
.class == y
.bitfield
.class);
1963 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1964 y
.bitfield
.instance
== InstanceNone
||
1965 x
.bitfield
.instance
== y
.bitfield
.instance
);
1967 switch (ARRAY_SIZE (x
.array
))
1970 x
.array
[2] |= y
.array
[2];
1973 x
.array
[1] |= y
.array
[1];
1976 x
.array
[0] |= y
.array
[0];
1984 static INLINE i386_operand_type
1985 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1987 gas_assert (y
.bitfield
.class == ClassNone
);
1988 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1990 switch (ARRAY_SIZE (x
.array
))
1993 x
.array
[2] ^= y
.array
[2];
1996 x
.array
[1] ^= y
.array
[1];
1999 x
.array
[0] ^= y
.array
[0];
2007 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2008 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2009 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2010 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2011 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2012 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2013 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2014 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2015 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2016 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2017 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2018 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2019 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2020 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2021 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2022 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2023 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2034 operand_type_check (i386_operand_type t
, enum operand_type c
)
2039 return t
.bitfield
.class == Reg
;
2042 return (t
.bitfield
.imm8
2046 || t
.bitfield
.imm32s
2047 || t
.bitfield
.imm64
);
2050 return (t
.bitfield
.disp8
2051 || t
.bitfield
.disp16
2052 || t
.bitfield
.disp32
2053 || t
.bitfield
.disp32s
2054 || t
.bitfield
.disp64
);
2057 return (t
.bitfield
.disp8
2058 || t
.bitfield
.disp16
2059 || t
.bitfield
.disp32
2060 || t
.bitfield
.disp32s
2061 || t
.bitfield
.disp64
2062 || t
.bitfield
.baseindex
);
2071 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2072 between operand GIVEN and opeand WANTED for instruction template T. */
2075 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2078 return !((i
.types
[given
].bitfield
.byte
2079 && !t
->operand_types
[wanted
].bitfield
.byte
)
2080 || (i
.types
[given
].bitfield
.word
2081 && !t
->operand_types
[wanted
].bitfield
.word
)
2082 || (i
.types
[given
].bitfield
.dword
2083 && !t
->operand_types
[wanted
].bitfield
.dword
)
2084 || (i
.types
[given
].bitfield
.qword
2085 && !t
->operand_types
[wanted
].bitfield
.qword
)
2086 || (i
.types
[given
].bitfield
.tbyte
2087 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2090 /* Return 1 if there is no conflict in SIMD register between operand
2091 GIVEN and opeand WANTED for instruction template T. */
2094 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2097 return !((i
.types
[given
].bitfield
.xmmword
2098 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2099 || (i
.types
[given
].bitfield
.ymmword
2100 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2101 || (i
.types
[given
].bitfield
.zmmword
2102 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2105 /* Return 1 if there is no conflict in any size between operand GIVEN
2106 and opeand WANTED for instruction template T. */
2109 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2112 return (match_operand_size (t
, wanted
, given
)
2113 && !((i
.types
[given
].bitfield
.unspecified
2115 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2116 || (i
.types
[given
].bitfield
.fword
2117 && !t
->operand_types
[wanted
].bitfield
.fword
)
2118 /* For scalar opcode templates to allow register and memory
2119 operands at the same time, some special casing is needed
2120 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2121 down-conversion vpmov*. */
2122 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2123 && !t
->opcode_modifier
.broadcast
2124 && (t
->operand_types
[wanted
].bitfield
.byte
2125 || t
->operand_types
[wanted
].bitfield
.word
2126 || t
->operand_types
[wanted
].bitfield
.dword
2127 || t
->operand_types
[wanted
].bitfield
.qword
))
2128 ? (i
.types
[given
].bitfield
.xmmword
2129 || i
.types
[given
].bitfield
.ymmword
2130 || i
.types
[given
].bitfield
.zmmword
)
2131 : !match_simd_size(t
, wanted
, given
))));
2134 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2135 operands for instruction template T, and it has MATCH_REVERSE set if there
2136 is no size conflict on any operands for the template with operands reversed
2137 (and the template allows for reversing in the first place). */
2139 #define MATCH_STRAIGHT 1
2140 #define MATCH_REVERSE 2
2142 static INLINE
unsigned int
2143 operand_size_match (const insn_template
*t
)
2145 unsigned int j
, match
= MATCH_STRAIGHT
;
2147 /* Don't check non-absolute jump instructions. */
2148 if (t
->opcode_modifier
.jump
2149 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2152 /* Check memory and accumulator operand size. */
2153 for (j
= 0; j
< i
.operands
; j
++)
2155 if (i
.types
[j
].bitfield
.class != Reg
2156 && i
.types
[j
].bitfield
.class != RegSIMD
2157 && t
->opcode_modifier
.anysize
)
2160 if (t
->operand_types
[j
].bitfield
.class == Reg
2161 && !match_operand_size (t
, j
, j
))
2167 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2168 && !match_simd_size (t
, j
, j
))
2174 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2175 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2181 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2188 if (!t
->opcode_modifier
.d
)
2192 i
.error
= operand_size_mismatch
;
2196 /* Check reverse. */
2197 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2199 for (j
= 0; j
< i
.operands
; j
++)
2201 unsigned int given
= i
.operands
- j
- 1;
2203 if (t
->operand_types
[j
].bitfield
.class == Reg
2204 && !match_operand_size (t
, j
, given
))
2207 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2208 && !match_simd_size (t
, j
, given
))
2211 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2212 && (!match_operand_size (t
, j
, given
)
2213 || !match_simd_size (t
, j
, given
)))
2216 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2220 return match
| MATCH_REVERSE
;
2224 operand_type_match (i386_operand_type overlap
,
2225 i386_operand_type given
)
2227 i386_operand_type temp
= overlap
;
2229 temp
.bitfield
.unspecified
= 0;
2230 temp
.bitfield
.byte
= 0;
2231 temp
.bitfield
.word
= 0;
2232 temp
.bitfield
.dword
= 0;
2233 temp
.bitfield
.fword
= 0;
2234 temp
.bitfield
.qword
= 0;
2235 temp
.bitfield
.tbyte
= 0;
2236 temp
.bitfield
.xmmword
= 0;
2237 temp
.bitfield
.ymmword
= 0;
2238 temp
.bitfield
.zmmword
= 0;
2239 if (operand_type_all_zero (&temp
))
2242 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2246 i
.error
= operand_type_mismatch
;
2250 /* If given types g0 and g1 are registers they must be of the same type
2251 unless the expected operand type register overlap is null.
2252 Some Intel syntax memory operand size checking also happens here. */
2255 operand_type_register_match (i386_operand_type g0
,
2256 i386_operand_type t0
,
2257 i386_operand_type g1
,
2258 i386_operand_type t1
)
2260 if (g0
.bitfield
.class != Reg
2261 && g0
.bitfield
.class != RegSIMD
2262 && (!operand_type_check (g0
, anymem
)
2263 || g0
.bitfield
.unspecified
2264 || (t0
.bitfield
.class != Reg
2265 && t0
.bitfield
.class != RegSIMD
)))
2268 if (g1
.bitfield
.class != Reg
2269 && g1
.bitfield
.class != RegSIMD
2270 && (!operand_type_check (g1
, anymem
)
2271 || g1
.bitfield
.unspecified
2272 || (t1
.bitfield
.class != Reg
2273 && t1
.bitfield
.class != RegSIMD
)))
2276 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2277 && g0
.bitfield
.word
== g1
.bitfield
.word
2278 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2279 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2280 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2281 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2282 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2285 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2286 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2287 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2288 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2289 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2290 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2291 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2294 i
.error
= register_type_mismatch
;
2299 static INLINE
unsigned int
2300 register_number (const reg_entry
*r
)
2302 unsigned int nr
= r
->reg_num
;
2304 if (r
->reg_flags
& RegRex
)
2307 if (r
->reg_flags
& RegVRex
)
2313 static INLINE
unsigned int
2314 mode_from_disp_size (i386_operand_type t
)
2316 if (t
.bitfield
.disp8
)
2318 else if (t
.bitfield
.disp16
2319 || t
.bitfield
.disp32
2320 || t
.bitfield
.disp32s
)
2327 fits_in_signed_byte (addressT num
)
2329 return num
+ 0x80 <= 0xff;
2333 fits_in_unsigned_byte (addressT num
)
2339 fits_in_unsigned_word (addressT num
)
2341 return num
<= 0xffff;
2345 fits_in_signed_word (addressT num
)
2347 return num
+ 0x8000 <= 0xffff;
2351 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2356 return num
+ 0x80000000 <= 0xffffffff;
2358 } /* fits_in_signed_long() */
2361 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2366 return num
<= 0xffffffff;
2368 } /* fits_in_unsigned_long() */
2371 fits_in_disp8 (offsetT num
)
2373 int shift
= i
.memshift
;
2379 mask
= (1 << shift
) - 1;
2381 /* Return 0 if NUM isn't properly aligned. */
2385 /* Check if NUM will fit in 8bit after shift. */
2386 return fits_in_signed_byte (num
>> shift
);
2390 fits_in_imm4 (offsetT num
)
2392 return (num
& 0xf) == num
;
2395 static i386_operand_type
2396 smallest_imm_type (offsetT num
)
2398 i386_operand_type t
;
2400 operand_type_set (&t
, 0);
2401 t
.bitfield
.imm64
= 1;
2403 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2405 /* This code is disabled on the 486 because all the Imm1 forms
2406 in the opcode table are slower on the i486. They're the
2407 versions with the implicitly specified single-position
2408 displacement, which has another syntax if you really want to
2410 t
.bitfield
.imm1
= 1;
2411 t
.bitfield
.imm8
= 1;
2412 t
.bitfield
.imm8s
= 1;
2413 t
.bitfield
.imm16
= 1;
2414 t
.bitfield
.imm32
= 1;
2415 t
.bitfield
.imm32s
= 1;
2417 else if (fits_in_signed_byte (num
))
2419 t
.bitfield
.imm8
= 1;
2420 t
.bitfield
.imm8s
= 1;
2421 t
.bitfield
.imm16
= 1;
2422 t
.bitfield
.imm32
= 1;
2423 t
.bitfield
.imm32s
= 1;
2425 else if (fits_in_unsigned_byte (num
))
2427 t
.bitfield
.imm8
= 1;
2428 t
.bitfield
.imm16
= 1;
2429 t
.bitfield
.imm32
= 1;
2430 t
.bitfield
.imm32s
= 1;
2432 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2434 t
.bitfield
.imm16
= 1;
2435 t
.bitfield
.imm32
= 1;
2436 t
.bitfield
.imm32s
= 1;
2438 else if (fits_in_signed_long (num
))
2440 t
.bitfield
.imm32
= 1;
2441 t
.bitfield
.imm32s
= 1;
2443 else if (fits_in_unsigned_long (num
))
2444 t
.bitfield
.imm32
= 1;
2450 offset_in_range (offsetT val
, int size
)
2456 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2457 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2458 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2460 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2466 /* If BFD64, sign extend val for 32bit address mode. */
2467 if (flag_code
!= CODE_64BIT
2468 || i
.prefix
[ADDR_PREFIX
])
2469 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2470 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2473 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2475 char buf1
[40], buf2
[40];
2477 sprint_value (buf1
, val
);
2478 sprint_value (buf2
, val
& mask
);
2479 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2494 a. PREFIX_EXIST if attempting to add a prefix where one from the
2495 same class already exists.
2496 b. PREFIX_LOCK if lock prefix is added.
2497 c. PREFIX_REP if rep/repne prefix is added.
2498 d. PREFIX_DS if ds prefix is added.
2499 e. PREFIX_OTHER if other prefix is added.
2502 static enum PREFIX_GROUP
2503 add_prefix (unsigned int prefix
)
2505 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2508 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2509 && flag_code
== CODE_64BIT
)
2511 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2512 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2513 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2514 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2525 case DS_PREFIX_OPCODE
:
2528 case CS_PREFIX_OPCODE
:
2529 case ES_PREFIX_OPCODE
:
2530 case FS_PREFIX_OPCODE
:
2531 case GS_PREFIX_OPCODE
:
2532 case SS_PREFIX_OPCODE
:
2536 case REPNE_PREFIX_OPCODE
:
2537 case REPE_PREFIX_OPCODE
:
2542 case LOCK_PREFIX_OPCODE
:
2551 case ADDR_PREFIX_OPCODE
:
2555 case DATA_PREFIX_OPCODE
:
2559 if (i
.prefix
[q
] != 0)
2567 i
.prefix
[q
] |= prefix
;
2570 as_bad (_("same type of prefix used twice"));
2576 update_code_flag (int value
, int check
)
2578 PRINTF_LIKE ((*as_error
));
2580 flag_code
= (enum flag_code
) value
;
2581 if (flag_code
== CODE_64BIT
)
2583 cpu_arch_flags
.bitfield
.cpu64
= 1;
2584 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2588 cpu_arch_flags
.bitfield
.cpu64
= 0;
2589 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2591 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2594 as_error
= as_fatal
;
2597 (*as_error
) (_("64bit mode not supported on `%s'."),
2598 cpu_arch_name
? cpu_arch_name
: default_arch
);
2600 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2603 as_error
= as_fatal
;
2606 (*as_error
) (_("32bit mode not supported on `%s'."),
2607 cpu_arch_name
? cpu_arch_name
: default_arch
);
2609 stackop_size
= '\0';
2613 set_code_flag (int value
)
2615 update_code_flag (value
, 0);
2619 set_16bit_gcc_code_flag (int new_code_flag
)
2621 flag_code
= (enum flag_code
) new_code_flag
;
2622 if (flag_code
!= CODE_16BIT
)
2624 cpu_arch_flags
.bitfield
.cpu64
= 0;
2625 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2626 stackop_size
= LONG_MNEM_SUFFIX
;
2630 set_intel_syntax (int syntax_flag
)
2632 /* Find out if register prefixing is specified. */
2633 int ask_naked_reg
= 0;
2636 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2639 int e
= get_symbol_name (&string
);
2641 if (strcmp (string
, "prefix") == 0)
2643 else if (strcmp (string
, "noprefix") == 0)
2646 as_bad (_("bad argument to syntax directive."));
2647 (void) restore_line_pointer (e
);
2649 demand_empty_rest_of_line ();
2651 intel_syntax
= syntax_flag
;
2653 if (ask_naked_reg
== 0)
2654 allow_naked_reg
= (intel_syntax
2655 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2657 allow_naked_reg
= (ask_naked_reg
< 0);
2659 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2661 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2662 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2663 register_prefix
= allow_naked_reg
? "" : "%";
2667 set_intel_mnemonic (int mnemonic_flag
)
2669 intel_mnemonic
= mnemonic_flag
;
2673 set_allow_index_reg (int flag
)
2675 allow_index_reg
= flag
;
2679 set_check (int what
)
2681 enum check_kind
*kind
;
2686 kind
= &operand_check
;
2697 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2700 int e
= get_symbol_name (&string
);
2702 if (strcmp (string
, "none") == 0)
2704 else if (strcmp (string
, "warning") == 0)
2705 *kind
= check_warning
;
2706 else if (strcmp (string
, "error") == 0)
2707 *kind
= check_error
;
2709 as_bad (_("bad argument to %s_check directive."), str
);
2710 (void) restore_line_pointer (e
);
2713 as_bad (_("missing argument for %s_check directive"), str
);
2715 demand_empty_rest_of_line ();
2719 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2720 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2722 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2723 static const char *arch
;
2725 /* Intel LIOM is only supported on ELF. */
2731 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2732 use default_arch. */
2733 arch
= cpu_arch_name
;
2735 arch
= default_arch
;
2738 /* If we are targeting Intel MCU, we must enable it. */
2739 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2740 || new_flag
.bitfield
.cpuiamcu
)
2743 /* If we are targeting Intel L1OM, we must enable it. */
2744 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2745 || new_flag
.bitfield
.cpul1om
)
2748 /* If we are targeting Intel K1OM, we must enable it. */
2749 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2750 || new_flag
.bitfield
.cpuk1om
)
2753 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2758 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2762 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2765 int e
= get_symbol_name (&string
);
2767 i386_cpu_flags flags
;
2769 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2771 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2773 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2777 cpu_arch_name
= cpu_arch
[j
].name
;
2778 cpu_sub_arch_name
= NULL
;
2779 cpu_arch_flags
= cpu_arch
[j
].flags
;
2780 if (flag_code
== CODE_64BIT
)
2782 cpu_arch_flags
.bitfield
.cpu64
= 1;
2783 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2787 cpu_arch_flags
.bitfield
.cpu64
= 0;
2788 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2790 cpu_arch_isa
= cpu_arch
[j
].type
;
2791 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2792 if (!cpu_arch_tune_set
)
2794 cpu_arch_tune
= cpu_arch_isa
;
2795 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2800 flags
= cpu_flags_or (cpu_arch_flags
,
2803 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2805 if (cpu_sub_arch_name
)
2807 char *name
= cpu_sub_arch_name
;
2808 cpu_sub_arch_name
= concat (name
,
2810 (const char *) NULL
);
2814 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2815 cpu_arch_flags
= flags
;
2816 cpu_arch_isa_flags
= flags
;
2820 = cpu_flags_or (cpu_arch_isa_flags
,
2822 (void) restore_line_pointer (e
);
2823 demand_empty_rest_of_line ();
2828 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2830 /* Disable an ISA extension. */
2831 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2832 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2834 flags
= cpu_flags_and_not (cpu_arch_flags
,
2835 cpu_noarch
[j
].flags
);
2836 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2838 if (cpu_sub_arch_name
)
2840 char *name
= cpu_sub_arch_name
;
2841 cpu_sub_arch_name
= concat (name
, string
,
2842 (const char *) NULL
);
2846 cpu_sub_arch_name
= xstrdup (string
);
2847 cpu_arch_flags
= flags
;
2848 cpu_arch_isa_flags
= flags
;
2850 (void) restore_line_pointer (e
);
2851 demand_empty_rest_of_line ();
2855 j
= ARRAY_SIZE (cpu_arch
);
2858 if (j
>= ARRAY_SIZE (cpu_arch
))
2859 as_bad (_("no such architecture: `%s'"), string
);
2861 *input_line_pointer
= e
;
2864 as_bad (_("missing cpu architecture"));
2866 no_cond_jump_promotion
= 0;
2867 if (*input_line_pointer
== ','
2868 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2873 ++input_line_pointer
;
2874 e
= get_symbol_name (&string
);
2876 if (strcmp (string
, "nojumps") == 0)
2877 no_cond_jump_promotion
= 1;
2878 else if (strcmp (string
, "jumps") == 0)
2881 as_bad (_("no such architecture modifier: `%s'"), string
);
2883 (void) restore_line_pointer (e
);
2886 demand_empty_rest_of_line ();
2889 enum bfd_architecture
2892 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2894 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2895 || flag_code
!= CODE_64BIT
)
2896 as_fatal (_("Intel L1OM is 64bit ELF only"));
2897 return bfd_arch_l1om
;
2899 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2901 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2902 || flag_code
!= CODE_64BIT
)
2903 as_fatal (_("Intel K1OM is 64bit ELF only"));
2904 return bfd_arch_k1om
;
2906 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2908 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2909 || flag_code
== CODE_64BIT
)
2910 as_fatal (_("Intel MCU is 32bit ELF only"));
2911 return bfd_arch_iamcu
;
2914 return bfd_arch_i386
;
2920 if (!strncmp (default_arch
, "x86_64", 6))
2922 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2924 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2925 || default_arch
[6] != '\0')
2926 as_fatal (_("Intel L1OM is 64bit ELF only"));
2927 return bfd_mach_l1om
;
2929 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2931 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2932 || default_arch
[6] != '\0')
2933 as_fatal (_("Intel K1OM is 64bit ELF only"));
2934 return bfd_mach_k1om
;
2936 else if (default_arch
[6] == '\0')
2937 return bfd_mach_x86_64
;
2939 return bfd_mach_x64_32
;
2941 else if (!strcmp (default_arch
, "i386")
2942 || !strcmp (default_arch
, "iamcu"))
2944 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2946 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2947 as_fatal (_("Intel MCU is 32bit ELF only"));
2948 return bfd_mach_i386_iamcu
;
2951 return bfd_mach_i386_i386
;
2954 as_fatal (_("unknown architecture"));
2960 const char *hash_err
;
2962 /* Support pseudo prefixes like {disp32}. */
2963 lex_type
['{'] = LEX_BEGIN_NAME
;
2965 /* Initialize op_hash hash table. */
2966 op_hash
= hash_new ();
2969 const insn_template
*optab
;
2970 templates
*core_optab
;
2972 /* Setup for loop. */
2974 core_optab
= XNEW (templates
);
2975 core_optab
->start
= optab
;
2980 if (optab
->name
== NULL
2981 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2983 /* different name --> ship out current template list;
2984 add to hash table; & begin anew. */
2985 core_optab
->end
= optab
;
2986 hash_err
= hash_insert (op_hash
,
2988 (void *) core_optab
);
2991 as_fatal (_("can't hash %s: %s"),
2995 if (optab
->name
== NULL
)
2997 core_optab
= XNEW (templates
);
2998 core_optab
->start
= optab
;
3003 /* Initialize reg_hash hash table. */
3004 reg_hash
= hash_new ();
3006 const reg_entry
*regtab
;
3007 unsigned int regtab_size
= i386_regtab_size
;
3009 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3011 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3013 as_fatal (_("can't hash %s: %s"),
3019 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3024 for (c
= 0; c
< 256; c
++)
3029 mnemonic_chars
[c
] = c
;
3030 register_chars
[c
] = c
;
3031 operand_chars
[c
] = c
;
3033 else if (ISLOWER (c
))
3035 mnemonic_chars
[c
] = c
;
3036 register_chars
[c
] = c
;
3037 operand_chars
[c
] = c
;
3039 else if (ISUPPER (c
))
3041 mnemonic_chars
[c
] = TOLOWER (c
);
3042 register_chars
[c
] = mnemonic_chars
[c
];
3043 operand_chars
[c
] = c
;
3045 else if (c
== '{' || c
== '}')
3047 mnemonic_chars
[c
] = c
;
3048 operand_chars
[c
] = c
;
3051 if (ISALPHA (c
) || ISDIGIT (c
))
3052 identifier_chars
[c
] = c
;
3055 identifier_chars
[c
] = c
;
3056 operand_chars
[c
] = c
;
3061 identifier_chars
['@'] = '@';
3064 identifier_chars
['?'] = '?';
3065 operand_chars
['?'] = '?';
3067 digit_chars
['-'] = '-';
3068 mnemonic_chars
['_'] = '_';
3069 mnemonic_chars
['-'] = '-';
3070 mnemonic_chars
['.'] = '.';
3071 identifier_chars
['_'] = '_';
3072 identifier_chars
['.'] = '.';
3074 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3075 operand_chars
[(unsigned char) *p
] = *p
;
3078 if (flag_code
== CODE_64BIT
)
3080 #if defined (OBJ_COFF) && defined (TE_PE)
3081 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3084 x86_dwarf2_return_column
= 16;
3086 x86_cie_data_alignment
= -8;
3090 x86_dwarf2_return_column
= 8;
3091 x86_cie_data_alignment
= -4;
3094 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3095 can be turned into BRANCH_PREFIX frag. */
3096 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3101 i386_print_statistics (FILE *file
)
3103 hash_print_statistics (file
, "i386 opcode", op_hash
);
3104 hash_print_statistics (file
, "i386 register", reg_hash
);
3109 /* Debugging routines for md_assemble. */
3110 static void pte (insn_template
*);
3111 static void pt (i386_operand_type
);
3112 static void pe (expressionS
*);
3113 static void ps (symbolS
*);
3116 pi (const char *line
, i386_insn
*x
)
3120 fprintf (stdout
, "%s: template ", line
);
3122 fprintf (stdout
, " address: base %s index %s scale %x\n",
3123 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3124 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3125 x
->log2_scale_factor
);
3126 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3127 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3128 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3129 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3130 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3131 (x
->rex
& REX_W
) != 0,
3132 (x
->rex
& REX_R
) != 0,
3133 (x
->rex
& REX_X
) != 0,
3134 (x
->rex
& REX_B
) != 0);
3135 for (j
= 0; j
< x
->operands
; j
++)
3137 fprintf (stdout
, " #%d: ", j
+ 1);
3139 fprintf (stdout
, "\n");
3140 if (x
->types
[j
].bitfield
.class == Reg
3141 || x
->types
[j
].bitfield
.class == RegMMX
3142 || x
->types
[j
].bitfield
.class == RegSIMD
3143 || x
->types
[j
].bitfield
.class == SReg
3144 || x
->types
[j
].bitfield
.class == RegCR
3145 || x
->types
[j
].bitfield
.class == RegDR
3146 || x
->types
[j
].bitfield
.class == RegTR
)
3147 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3148 if (operand_type_check (x
->types
[j
], imm
))
3150 if (operand_type_check (x
->types
[j
], disp
))
3151 pe (x
->op
[j
].disps
);
3156 pte (insn_template
*t
)
3159 fprintf (stdout
, " %d operands ", t
->operands
);
3160 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3161 if (t
->extension_opcode
!= None
)
3162 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3163 if (t
->opcode_modifier
.d
)
3164 fprintf (stdout
, "D");
3165 if (t
->opcode_modifier
.w
)
3166 fprintf (stdout
, "W");
3167 fprintf (stdout
, "\n");
3168 for (j
= 0; j
< t
->operands
; j
++)
3170 fprintf (stdout
, " #%d type ", j
+ 1);
3171 pt (t
->operand_types
[j
]);
3172 fprintf (stdout
, "\n");
3179 fprintf (stdout
, " operation %d\n", e
->X_op
);
3180 fprintf (stdout
, " add_number %ld (%lx)\n",
3181 (long) e
->X_add_number
, (long) e
->X_add_number
);
3182 if (e
->X_add_symbol
)
3184 fprintf (stdout
, " add_symbol ");
3185 ps (e
->X_add_symbol
);
3186 fprintf (stdout
, "\n");
3190 fprintf (stdout
, " op_symbol ");
3191 ps (e
->X_op_symbol
);
3192 fprintf (stdout
, "\n");
3199 fprintf (stdout
, "%s type %s%s",
3201 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3202 segment_name (S_GET_SEGMENT (s
)));
3205 static struct type_name
3207 i386_operand_type mask
;
3210 const type_names
[] =
3212 { OPERAND_TYPE_REG8
, "r8" },
3213 { OPERAND_TYPE_REG16
, "r16" },
3214 { OPERAND_TYPE_REG32
, "r32" },
3215 { OPERAND_TYPE_REG64
, "r64" },
3216 { OPERAND_TYPE_ACC8
, "acc8" },
3217 { OPERAND_TYPE_ACC16
, "acc16" },
3218 { OPERAND_TYPE_ACC32
, "acc32" },
3219 { OPERAND_TYPE_ACC64
, "acc64" },
3220 { OPERAND_TYPE_IMM8
, "i8" },
3221 { OPERAND_TYPE_IMM8
, "i8s" },
3222 { OPERAND_TYPE_IMM16
, "i16" },
3223 { OPERAND_TYPE_IMM32
, "i32" },
3224 { OPERAND_TYPE_IMM32S
, "i32s" },
3225 { OPERAND_TYPE_IMM64
, "i64" },
3226 { OPERAND_TYPE_IMM1
, "i1" },
3227 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3228 { OPERAND_TYPE_DISP8
, "d8" },
3229 { OPERAND_TYPE_DISP16
, "d16" },
3230 { OPERAND_TYPE_DISP32
, "d32" },
3231 { OPERAND_TYPE_DISP32S
, "d32s" },
3232 { OPERAND_TYPE_DISP64
, "d64" },
3233 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3234 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3235 { OPERAND_TYPE_CONTROL
, "control reg" },
3236 { OPERAND_TYPE_TEST
, "test reg" },
3237 { OPERAND_TYPE_DEBUG
, "debug reg" },
3238 { OPERAND_TYPE_FLOATREG
, "FReg" },
3239 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3240 { OPERAND_TYPE_SREG
, "SReg" },
3241 { OPERAND_TYPE_REGMMX
, "rMMX" },
3242 { OPERAND_TYPE_REGXMM
, "rXMM" },
3243 { OPERAND_TYPE_REGYMM
, "rYMM" },
3244 { OPERAND_TYPE_REGZMM
, "rZMM" },
3245 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3249 pt (i386_operand_type t
)
3252 i386_operand_type a
;
3254 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3256 a
= operand_type_and (t
, type_names
[j
].mask
);
3257 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3258 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3263 #endif /* DEBUG386 */
3265 static bfd_reloc_code_real_type
3266 reloc (unsigned int size
,
3269 bfd_reloc_code_real_type other
)
3271 if (other
!= NO_RELOC
)
3273 reloc_howto_type
*rel
;
3278 case BFD_RELOC_X86_64_GOT32
:
3279 return BFD_RELOC_X86_64_GOT64
;
3281 case BFD_RELOC_X86_64_GOTPLT64
:
3282 return BFD_RELOC_X86_64_GOTPLT64
;
3284 case BFD_RELOC_X86_64_PLTOFF64
:
3285 return BFD_RELOC_X86_64_PLTOFF64
;
3287 case BFD_RELOC_X86_64_GOTPC32
:
3288 other
= BFD_RELOC_X86_64_GOTPC64
;
3290 case BFD_RELOC_X86_64_GOTPCREL
:
3291 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3293 case BFD_RELOC_X86_64_TPOFF32
:
3294 other
= BFD_RELOC_X86_64_TPOFF64
;
3296 case BFD_RELOC_X86_64_DTPOFF32
:
3297 other
= BFD_RELOC_X86_64_DTPOFF64
;
3303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3304 if (other
== BFD_RELOC_SIZE32
)
3307 other
= BFD_RELOC_SIZE64
;
3310 as_bad (_("there are no pc-relative size relocations"));
3316 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3317 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3320 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3322 as_bad (_("unknown relocation (%u)"), other
);
3323 else if (size
!= bfd_get_reloc_size (rel
))
3324 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3325 bfd_get_reloc_size (rel
),
3327 else if (pcrel
&& !rel
->pc_relative
)
3328 as_bad (_("non-pc-relative relocation for pc-relative field"));
3329 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3331 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3333 as_bad (_("relocated field and relocation type differ in signedness"));
3342 as_bad (_("there are no unsigned pc-relative relocations"));
3345 case 1: return BFD_RELOC_8_PCREL
;
3346 case 2: return BFD_RELOC_16_PCREL
;
3347 case 4: return BFD_RELOC_32_PCREL
;
3348 case 8: return BFD_RELOC_64_PCREL
;
3350 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3357 case 4: return BFD_RELOC_X86_64_32S
;
3362 case 1: return BFD_RELOC_8
;
3363 case 2: return BFD_RELOC_16
;
3364 case 4: return BFD_RELOC_32
;
3365 case 8: return BFD_RELOC_64
;
3367 as_bad (_("cannot do %s %u byte relocation"),
3368 sign
> 0 ? "signed" : "unsigned", size
);
3374 /* Here we decide which fixups can be adjusted to make them relative to
3375 the beginning of the section instead of the symbol. Basically we need
3376 to make sure that the dynamic relocations are done correctly, so in
3377 some cases we force the original symbol to be used. */
3380 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3382 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3386 /* Don't adjust pc-relative references to merge sections in 64-bit
3388 if (use_rela_relocations
3389 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3393 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3394 and changed later by validate_fix. */
3395 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3396 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3399 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3400 for size relocations. */
3401 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3402 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3403 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3404 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3405 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3410 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3411 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3412 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3413 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3414 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3415 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3425 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3426 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3427 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3428 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3429 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3430 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3431 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3438 intel_float_operand (const char *mnemonic
)
3440 /* Note that the value returned is meaningful only for opcodes with (memory)
3441 operands, hence the code here is free to improperly handle opcodes that
3442 have no operands (for better performance and smaller code). */
3444 if (mnemonic
[0] != 'f')
3445 return 0; /* non-math */
3447 switch (mnemonic
[1])
3449 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3450 the fs segment override prefix not currently handled because no
3451 call path can make opcodes without operands get here */
3453 return 2 /* integer op */;
3455 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3456 return 3; /* fldcw/fldenv */
3459 if (mnemonic
[2] != 'o' /* fnop */)
3460 return 3; /* non-waiting control op */
3463 if (mnemonic
[2] == 's')
3464 return 3; /* frstor/frstpm */
3467 if (mnemonic
[2] == 'a')
3468 return 3; /* fsave */
3469 if (mnemonic
[2] == 't')
3471 switch (mnemonic
[3])
3473 case 'c': /* fstcw */
3474 case 'd': /* fstdw */
3475 case 'e': /* fstenv */
3476 case 's': /* fsts[gw] */
3482 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3483 return 0; /* fxsave/fxrstor are not really math ops */
3490 /* Build the VEX prefix. */
3493 build_vex_prefix (const insn_template
*t
)
3495 unsigned int register_specifier
;
3496 unsigned int implied_prefix
;
3497 unsigned int vector_length
;
3500 /* Check register specifier. */
3501 if (i
.vex
.register_specifier
)
3503 register_specifier
=
3504 ~register_number (i
.vex
.register_specifier
) & 0xf;
3505 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3508 register_specifier
= 0xf;
3510 /* Use 2-byte VEX prefix by swapping destination and source operand
3511 if there are more than 1 register operand. */
3512 if (i
.reg_operands
> 1
3513 && i
.vec_encoding
!= vex_encoding_vex3
3514 && i
.dir_encoding
== dir_encoding_default
3515 && i
.operands
== i
.reg_operands
3516 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3517 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3518 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3521 unsigned int xchg
= i
.operands
- 1;
3522 union i386_op temp_op
;
3523 i386_operand_type temp_type
;
3525 temp_type
= i
.types
[xchg
];
3526 i
.types
[xchg
] = i
.types
[0];
3527 i
.types
[0] = temp_type
;
3528 temp_op
= i
.op
[xchg
];
3529 i
.op
[xchg
] = i
.op
[0];
3532 gas_assert (i
.rm
.mode
== 3);
3536 i
.rm
.regmem
= i
.rm
.reg
;
3539 if (i
.tm
.opcode_modifier
.d
)
3540 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3541 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3542 else /* Use the next insn. */
3546 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3547 are no memory operands and at least 3 register ones. */
3548 if (i
.reg_operands
>= 3
3549 && i
.vec_encoding
!= vex_encoding_vex3
3550 && i
.reg_operands
== i
.operands
- i
.imm_operands
3551 && i
.tm
.opcode_modifier
.vex
3552 && i
.tm
.opcode_modifier
.commutative
3553 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3555 && i
.vex
.register_specifier
3556 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3558 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3559 union i386_op temp_op
;
3560 i386_operand_type temp_type
;
3562 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3563 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3564 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3565 &i
.types
[i
.operands
- 3]));
3566 gas_assert (i
.rm
.mode
== 3);
3568 temp_type
= i
.types
[xchg
];
3569 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3570 i
.types
[xchg
+ 1] = temp_type
;
3571 temp_op
= i
.op
[xchg
];
3572 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3573 i
.op
[xchg
+ 1] = temp_op
;
3576 xchg
= i
.rm
.regmem
| 8;
3577 i
.rm
.regmem
= ~register_specifier
& 0xf;
3578 gas_assert (!(i
.rm
.regmem
& 8));
3579 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3580 register_specifier
= ~xchg
& 0xf;
3583 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3584 vector_length
= avxscalar
;
3585 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3591 /* Determine vector length from the last multi-length vector
3594 for (op
= t
->operands
; op
--;)
3595 if (t
->operand_types
[op
].bitfield
.xmmword
3596 && t
->operand_types
[op
].bitfield
.ymmword
3597 && i
.types
[op
].bitfield
.ymmword
)
3604 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3609 case DATA_PREFIX_OPCODE
:
3612 case REPE_PREFIX_OPCODE
:
3615 case REPNE_PREFIX_OPCODE
:
3622 /* Check the REX.W bit and VEXW. */
3623 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3624 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3625 else if (i
.tm
.opcode_modifier
.vexw
)
3626 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3628 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3630 /* Use 2-byte VEX prefix if possible. */
3632 && i
.vec_encoding
!= vex_encoding_vex3
3633 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3634 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3636 /* 2-byte VEX prefix. */
3640 i
.vex
.bytes
[0] = 0xc5;
3642 /* Check the REX.R bit. */
3643 r
= (i
.rex
& REX_R
) ? 0 : 1;
3644 i
.vex
.bytes
[1] = (r
<< 7
3645 | register_specifier
<< 3
3646 | vector_length
<< 2
3651 /* 3-byte VEX prefix. */
3656 switch (i
.tm
.opcode_modifier
.vexopcode
)
3660 i
.vex
.bytes
[0] = 0xc4;
3664 i
.vex
.bytes
[0] = 0xc4;
3668 i
.vex
.bytes
[0] = 0xc4;
3672 i
.vex
.bytes
[0] = 0x8f;
3676 i
.vex
.bytes
[0] = 0x8f;
3680 i
.vex
.bytes
[0] = 0x8f;
3686 /* The high 3 bits of the second VEX byte are 1's compliment
3687 of RXB bits from REX. */
3688 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3690 i
.vex
.bytes
[2] = (w
<< 7
3691 | register_specifier
<< 3
3692 | vector_length
<< 2
3697 static INLINE bfd_boolean
3698 is_evex_encoding (const insn_template
*t
)
3700 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3701 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3702 || t
->opcode_modifier
.sae
;
3705 static INLINE bfd_boolean
3706 is_any_vex_encoding (const insn_template
*t
)
3708 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3709 || is_evex_encoding (t
);
3712 /* Build the EVEX prefix. */
3715 build_evex_prefix (void)
3717 unsigned int register_specifier
;
3718 unsigned int implied_prefix
;
3720 rex_byte vrex_used
= 0;
3722 /* Check register specifier. */
3723 if (i
.vex
.register_specifier
)
3725 gas_assert ((i
.vrex
& REX_X
) == 0);
3727 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3728 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3729 register_specifier
+= 8;
3730 /* The upper 16 registers are encoded in the fourth byte of the
3732 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3733 i
.vex
.bytes
[3] = 0x8;
3734 register_specifier
= ~register_specifier
& 0xf;
3738 register_specifier
= 0xf;
3740 /* Encode upper 16 vector index register in the fourth byte of
3742 if (!(i
.vrex
& REX_X
))
3743 i
.vex
.bytes
[3] = 0x8;
3748 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3753 case DATA_PREFIX_OPCODE
:
3756 case REPE_PREFIX_OPCODE
:
3759 case REPNE_PREFIX_OPCODE
:
3766 /* 4 byte EVEX prefix. */
3768 i
.vex
.bytes
[0] = 0x62;
3771 switch (i
.tm
.opcode_modifier
.vexopcode
)
3787 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3789 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3791 /* The fifth bit of the second EVEX byte is 1's compliment of the
3792 REX_R bit in VREX. */
3793 if (!(i
.vrex
& REX_R
))
3794 i
.vex
.bytes
[1] |= 0x10;
3798 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3800 /* When all operands are registers, the REX_X bit in REX is not
3801 used. We reuse it to encode the upper 16 registers, which is
3802 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3803 as 1's compliment. */
3804 if ((i
.vrex
& REX_B
))
3807 i
.vex
.bytes
[1] &= ~0x40;
3811 /* EVEX instructions shouldn't need the REX prefix. */
3812 i
.vrex
&= ~vrex_used
;
3813 gas_assert (i
.vrex
== 0);
3815 /* Check the REX.W bit and VEXW. */
3816 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3817 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3818 else if (i
.tm
.opcode_modifier
.vexw
)
3819 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3821 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3823 /* Encode the U bit. */
3824 implied_prefix
|= 0x4;
3826 /* The third byte of the EVEX prefix. */
3827 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3829 /* The fourth byte of the EVEX prefix. */
3830 /* The zeroing-masking bit. */
3831 if (i
.mask
&& i
.mask
->zeroing
)
3832 i
.vex
.bytes
[3] |= 0x80;
3834 /* Don't always set the broadcast bit if there is no RC. */
3837 /* Encode the vector length. */
3838 unsigned int vec_length
;
3840 if (!i
.tm
.opcode_modifier
.evex
3841 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3845 /* Determine vector length from the last multi-length vector
3848 for (op
= i
.operands
; op
--;)
3849 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3850 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3851 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3853 if (i
.types
[op
].bitfield
.zmmword
)
3855 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3858 else if (i
.types
[op
].bitfield
.ymmword
)
3860 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3863 else if (i
.types
[op
].bitfield
.xmmword
)
3865 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3868 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3870 switch (i
.broadcast
->bytes
)
3873 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3876 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3879 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3888 if (op
>= MAX_OPERANDS
)
3892 switch (i
.tm
.opcode_modifier
.evex
)
3894 case EVEXLIG
: /* LL' is ignored */
3895 vec_length
= evexlig
<< 5;
3898 vec_length
= 0 << 5;
3901 vec_length
= 1 << 5;
3904 vec_length
= 2 << 5;
3910 i
.vex
.bytes
[3] |= vec_length
;
3911 /* Encode the broadcast bit. */
3913 i
.vex
.bytes
[3] |= 0x10;
3917 if (i
.rounding
->type
!= saeonly
)
3918 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3920 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3923 if (i
.mask
&& i
.mask
->mask
)
3924 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3928 process_immext (void)
3932 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3933 which is coded in the same place as an 8-bit immediate field
3934 would be. Here we fake an 8-bit immediate operand from the
3935 opcode suffix stored in tm.extension_opcode.
3937 AVX instructions also use this encoding, for some of
3938 3 argument instructions. */
3940 gas_assert (i
.imm_operands
<= 1
3942 || (is_any_vex_encoding (&i
.tm
)
3943 && i
.operands
<= 4)));
3945 exp
= &im_expressions
[i
.imm_operands
++];
3946 i
.op
[i
.operands
].imms
= exp
;
3947 i
.types
[i
.operands
] = imm8
;
3949 exp
->X_op
= O_constant
;
3950 exp
->X_add_number
= i
.tm
.extension_opcode
;
3951 i
.tm
.extension_opcode
= None
;
3958 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3963 as_bad (_("invalid instruction `%s' after `%s'"),
3964 i
.tm
.name
, i
.hle_prefix
);
3967 if (i
.prefix
[LOCK_PREFIX
])
3969 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3973 case HLEPrefixRelease
:
3974 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3976 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3980 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3982 as_bad (_("memory destination needed for instruction `%s'"
3983 " after `xrelease'"), i
.tm
.name
);
3990 /* Try the shortest encoding by shortening operand size. */
3993 optimize_encoding (void)
3997 if (optimize_for_space
3998 && !is_any_vex_encoding (&i
.tm
)
3999 && i
.reg_operands
== 1
4000 && i
.imm_operands
== 1
4001 && !i
.types
[1].bitfield
.byte
4002 && i
.op
[0].imms
->X_op
== O_constant
4003 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4004 && (i
.tm
.base_opcode
== 0xa8
4005 || (i
.tm
.base_opcode
== 0xf6
4006 && i
.tm
.extension_opcode
== 0x0)))
4009 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4011 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4012 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4014 i
.types
[1].bitfield
.byte
= 1;
4015 /* Ignore the suffix. */
4017 /* Convert to byte registers. */
4018 if (i
.types
[1].bitfield
.word
)
4020 else if (i
.types
[1].bitfield
.dword
)
4024 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4029 else if (flag_code
== CODE_64BIT
4030 && !is_any_vex_encoding (&i
.tm
)
4031 && ((i
.types
[1].bitfield
.qword
4032 && i
.reg_operands
== 1
4033 && i
.imm_operands
== 1
4034 && i
.op
[0].imms
->X_op
== O_constant
4035 && ((i
.tm
.base_opcode
== 0xb8
4036 && i
.tm
.extension_opcode
== None
4037 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4038 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4039 && ((i
.tm
.base_opcode
== 0x24
4040 || i
.tm
.base_opcode
== 0xa8)
4041 || (i
.tm
.base_opcode
== 0x80
4042 && i
.tm
.extension_opcode
== 0x4)
4043 || ((i
.tm
.base_opcode
== 0xf6
4044 || (i
.tm
.base_opcode
| 1) == 0xc7)
4045 && i
.tm
.extension_opcode
== 0x0)))
4046 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4047 && i
.tm
.base_opcode
== 0x83
4048 && i
.tm
.extension_opcode
== 0x4)))
4049 || (i
.types
[0].bitfield
.qword
4050 && ((i
.reg_operands
== 2
4051 && i
.op
[0].regs
== i
.op
[1].regs
4052 && (i
.tm
.base_opcode
== 0x30
4053 || i
.tm
.base_opcode
== 0x28))
4054 || (i
.reg_operands
== 1
4056 && i
.tm
.base_opcode
== 0x30)))))
4059 andq $imm31, %r64 -> andl $imm31, %r32
4060 andq $imm7, %r64 -> andl $imm7, %r32
4061 testq $imm31, %r64 -> testl $imm31, %r32
4062 xorq %r64, %r64 -> xorl %r32, %r32
4063 subq %r64, %r64 -> subl %r32, %r32
4064 movq $imm31, %r64 -> movl $imm31, %r32
4065 movq $imm32, %r64 -> movl $imm32, %r32
4067 i
.tm
.opcode_modifier
.norex64
= 1;
4068 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4071 movq $imm31, %r64 -> movl $imm31, %r32
4072 movq $imm32, %r64 -> movl $imm32, %r32
4074 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4075 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4076 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4077 i
.types
[0].bitfield
.imm32
= 1;
4078 i
.types
[0].bitfield
.imm32s
= 0;
4079 i
.types
[0].bitfield
.imm64
= 0;
4080 i
.types
[1].bitfield
.dword
= 1;
4081 i
.types
[1].bitfield
.qword
= 0;
4082 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4085 movq $imm31, %r64 -> movl $imm31, %r32
4087 i
.tm
.base_opcode
= 0xb8;
4088 i
.tm
.extension_opcode
= None
;
4089 i
.tm
.opcode_modifier
.w
= 0;
4090 i
.tm
.opcode_modifier
.modrm
= 0;
4094 else if (optimize
> 1
4095 && !optimize_for_space
4096 && !is_any_vex_encoding (&i
.tm
)
4097 && i
.reg_operands
== 2
4098 && i
.op
[0].regs
== i
.op
[1].regs
4099 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4100 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4101 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4104 andb %rN, %rN -> testb %rN, %rN
4105 andw %rN, %rN -> testw %rN, %rN
4106 andq %rN, %rN -> testq %rN, %rN
4107 orb %rN, %rN -> testb %rN, %rN
4108 orw %rN, %rN -> testw %rN, %rN
4109 orq %rN, %rN -> testq %rN, %rN
4111 and outside of 64-bit mode
4113 andl %rN, %rN -> testl %rN, %rN
4114 orl %rN, %rN -> testl %rN, %rN
4116 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4118 else if (i
.reg_operands
== 3
4119 && i
.op
[0].regs
== i
.op
[1].regs
4120 && !i
.types
[2].bitfield
.xmmword
4121 && (i
.tm
.opcode_modifier
.vex
4122 || ((!i
.mask
|| i
.mask
->zeroing
)
4124 && is_evex_encoding (&i
.tm
)
4125 && (i
.vec_encoding
!= vex_encoding_evex
4126 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4127 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4128 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4129 && i
.types
[2].bitfield
.ymmword
))))
4130 && ((i
.tm
.base_opcode
== 0x55
4131 || i
.tm
.base_opcode
== 0x6655
4132 || i
.tm
.base_opcode
== 0x66df
4133 || i
.tm
.base_opcode
== 0x57
4134 || i
.tm
.base_opcode
== 0x6657
4135 || i
.tm
.base_opcode
== 0x66ef
4136 || i
.tm
.base_opcode
== 0x66f8
4137 || i
.tm
.base_opcode
== 0x66f9
4138 || i
.tm
.base_opcode
== 0x66fa
4139 || i
.tm
.base_opcode
== 0x66fb
4140 || i
.tm
.base_opcode
== 0x42
4141 || i
.tm
.base_opcode
== 0x6642
4142 || i
.tm
.base_opcode
== 0x47
4143 || i
.tm
.base_opcode
== 0x6647)
4144 && i
.tm
.extension_opcode
== None
))
4147 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4149 EVEX VOP %zmmM, %zmmM, %zmmN
4150 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4151 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4152 EVEX VOP %ymmM, %ymmM, %ymmN
4153 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4154 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4155 VEX VOP %ymmM, %ymmM, %ymmN
4156 -> VEX VOP %xmmM, %xmmM, %xmmN
4157 VOP, one of vpandn and vpxor:
4158 VEX VOP %ymmM, %ymmM, %ymmN
4159 -> VEX VOP %xmmM, %xmmM, %xmmN
4160 VOP, one of vpandnd and vpandnq:
4161 EVEX VOP %zmmM, %zmmM, %zmmN
4162 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4163 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4164 EVEX VOP %ymmM, %ymmM, %ymmN
4165 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4166 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4167 VOP, one of vpxord and vpxorq:
4168 EVEX VOP %zmmM, %zmmM, %zmmN
4169 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4170 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4171 EVEX VOP %ymmM, %ymmM, %ymmN
4172 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4173 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4174 VOP, one of kxord and kxorq:
4175 VEX VOP %kM, %kM, %kN
4176 -> VEX kxorw %kM, %kM, %kN
4177 VOP, one of kandnd and kandnq:
4178 VEX VOP %kM, %kM, %kN
4179 -> VEX kandnw %kM, %kM, %kN
4181 if (is_evex_encoding (&i
.tm
))
4183 if (i
.vec_encoding
!= vex_encoding_evex
)
4185 i
.tm
.opcode_modifier
.vex
= VEX128
;
4186 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4187 i
.tm
.opcode_modifier
.evex
= 0;
4189 else if (optimize
> 1)
4190 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4194 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4196 i
.tm
.base_opcode
&= 0xff;
4197 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4200 i
.tm
.opcode_modifier
.vex
= VEX128
;
4202 if (i
.tm
.opcode_modifier
.vex
)
4203 for (j
= 0; j
< 3; j
++)
4205 i
.types
[j
].bitfield
.xmmword
= 1;
4206 i
.types
[j
].bitfield
.ymmword
= 0;
4209 else if (i
.vec_encoding
!= vex_encoding_evex
4210 && !i
.types
[0].bitfield
.zmmword
4211 && !i
.types
[1].bitfield
.zmmword
4214 && is_evex_encoding (&i
.tm
)
4215 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4216 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4217 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4218 || (i
.tm
.base_opcode
& ~4) == 0x66db
4219 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4220 && i
.tm
.extension_opcode
== None
)
4223 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4224 vmovdqu32 and vmovdqu64:
4225 EVEX VOP %xmmM, %xmmN
4226 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4227 EVEX VOP %ymmM, %ymmN
4228 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4230 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4232 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4234 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4236 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4237 VOP, one of vpand, vpandn, vpor, vpxor:
4238 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4239 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4240 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4241 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4242 EVEX VOP{d,q} mem, %xmmM, %xmmN
4243 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4244 EVEX VOP{d,q} mem, %ymmM, %ymmN
4245 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4247 for (j
= 0; j
< i
.operands
; j
++)
4248 if (operand_type_check (i
.types
[j
], disp
)
4249 && i
.op
[j
].disps
->X_op
== O_constant
)
4251 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4252 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4253 bytes, we choose EVEX Disp8 over VEX Disp32. */
4254 int evex_disp8
, vex_disp8
;
4255 unsigned int memshift
= i
.memshift
;
4256 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4258 evex_disp8
= fits_in_disp8 (n
);
4260 vex_disp8
= fits_in_disp8 (n
);
4261 if (evex_disp8
!= vex_disp8
)
4263 i
.memshift
= memshift
;
4267 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4270 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4271 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4272 i
.tm
.opcode_modifier
.vex
4273 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4274 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4275 /* VPAND, VPOR, and VPXOR are commutative. */
4276 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4277 i
.tm
.opcode_modifier
.commutative
= 1;
4278 i
.tm
.opcode_modifier
.evex
= 0;
4279 i
.tm
.opcode_modifier
.masking
= 0;
4280 i
.tm
.opcode_modifier
.broadcast
= 0;
4281 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4284 i
.types
[j
].bitfield
.disp8
4285 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4289 /* This is the guts of the machine-dependent assembler. LINE points to a
4290 machine dependent instruction. This function is supposed to emit
4291 the frags/bytes it assembles to. */
4294 md_assemble (char *line
)
4297 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4298 const insn_template
*t
;
4300 /* Initialize globals. */
4301 memset (&i
, '\0', sizeof (i
));
4302 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4303 i
.reloc
[j
] = NO_RELOC
;
4304 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4305 memset (im_expressions
, '\0', sizeof (im_expressions
));
4306 save_stack_p
= save_stack
;
4308 /* First parse an instruction mnemonic & call i386_operand for the operands.
4309 We assume that the scrubber has arranged it so that line[0] is the valid
4310 start of a (possibly prefixed) mnemonic. */
4312 line
= parse_insn (line
, mnemonic
);
4315 mnem_suffix
= i
.suffix
;
4317 line
= parse_operands (line
, mnemonic
);
4319 xfree (i
.memop1_string
);
4320 i
.memop1_string
= NULL
;
4324 /* Now we've parsed the mnemonic into a set of templates, and have the
4325 operands at hand. */
4327 /* All intel opcodes have reversed operands except for "bound" and
4328 "enter". We also don't reverse intersegment "jmp" and "call"
4329 instructions with 2 immediate operands so that the immediate segment
4330 precedes the offset, as it does when in AT&T mode. */
4333 && (strcmp (mnemonic
, "bound") != 0)
4334 && (strcmp (mnemonic
, "invlpga") != 0)
4335 && !(operand_type_check (i
.types
[0], imm
)
4336 && operand_type_check (i
.types
[1], imm
)))
4339 /* The order of the immediates should be reversed
4340 for 2 immediates extrq and insertq instructions */
4341 if (i
.imm_operands
== 2
4342 && (strcmp (mnemonic
, "extrq") == 0
4343 || strcmp (mnemonic
, "insertq") == 0))
4344 swap_2_operands (0, 1);
4349 /* Don't optimize displacement for movabs since it only takes 64bit
4352 && i
.disp_encoding
!= disp_encoding_32bit
4353 && (flag_code
!= CODE_64BIT
4354 || strcmp (mnemonic
, "movabs") != 0))
4357 /* Next, we find a template that matches the given insn,
4358 making sure the overlap of the given operands types is consistent
4359 with the template operand types. */
4361 if (!(t
= match_template (mnem_suffix
)))
4364 if (sse_check
!= check_none
4365 && !i
.tm
.opcode_modifier
.noavx
4366 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4367 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4368 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4369 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4371 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4372 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4373 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4374 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4375 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4376 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4377 || i
.tm
.cpu_flags
.bitfield
.cpusha
4378 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4380 (sse_check
== check_warning
4382 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4385 if (i
.tm
.opcode_modifier
.fwait
)
4386 if (!add_prefix (FWAIT_OPCODE
))
4389 /* Check if REP prefix is OK. */
4390 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4392 as_bad (_("invalid instruction `%s' after `%s'"),
4393 i
.tm
.name
, i
.rep_prefix
);
4397 /* Check for lock without a lockable instruction. Destination operand
4398 must be memory unless it is xchg (0x86). */
4399 if (i
.prefix
[LOCK_PREFIX
]
4400 && (!i
.tm
.opcode_modifier
.islockable
4401 || i
.mem_operands
== 0
4402 || (i
.tm
.base_opcode
!= 0x86
4403 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4405 as_bad (_("expecting lockable instruction after `lock'"));
4409 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4410 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4412 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4416 /* Check if HLE prefix is OK. */
4417 if (i
.hle_prefix
&& !check_hle ())
4420 /* Check BND prefix. */
4421 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4422 as_bad (_("expecting valid branch instruction after `bnd'"));
4424 /* Check NOTRACK prefix. */
4425 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4426 as_bad (_("expecting indirect branch instruction after `notrack'"));
4428 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4430 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4431 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4432 else if (flag_code
!= CODE_16BIT
4433 ? i
.prefix
[ADDR_PREFIX
]
4434 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4435 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4438 /* Insert BND prefix. */
4439 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4441 if (!i
.prefix
[BND_PREFIX
])
4442 add_prefix (BND_PREFIX_OPCODE
);
4443 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4445 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4446 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4450 /* Check string instruction segment overrides. */
4451 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4453 gas_assert (i
.mem_operands
);
4454 if (!check_string ())
4456 i
.disp_operands
= 0;
4459 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4460 optimize_encoding ();
4462 if (!process_suffix ())
4465 /* Update operand types. */
4466 for (j
= 0; j
< i
.operands
; j
++)
4467 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4469 /* Make still unresolved immediate matches conform to size of immediate
4470 given in i.suffix. */
4471 if (!finalize_imm ())
4474 if (i
.types
[0].bitfield
.imm1
)
4475 i
.imm_operands
= 0; /* kludge for shift insns. */
4477 /* We only need to check those implicit registers for instructions
4478 with 3 operands or less. */
4479 if (i
.operands
<= 3)
4480 for (j
= 0; j
< i
.operands
; j
++)
4481 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4482 && !i
.types
[j
].bitfield
.xmmword
)
4485 /* ImmExt should be processed after SSE2AVX. */
4486 if (!i
.tm
.opcode_modifier
.sse2avx
4487 && i
.tm
.opcode_modifier
.immext
)
4490 /* For insns with operands there are more diddles to do to the opcode. */
4493 if (!process_operands ())
4496 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4498 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4499 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4502 if (is_any_vex_encoding (&i
.tm
))
4504 if (!cpu_arch_flags
.bitfield
.cpui286
)
4506 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4511 if (i
.tm
.opcode_modifier
.vex
)
4512 build_vex_prefix (t
);
4514 build_evex_prefix ();
4517 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4518 instructions may define INT_OPCODE as well, so avoid this corner
4519 case for those instructions that use MODRM. */
4520 if (i
.tm
.base_opcode
== INT_OPCODE
4521 && !i
.tm
.opcode_modifier
.modrm
4522 && i
.op
[0].imms
->X_add_number
== 3)
4524 i
.tm
.base_opcode
= INT3_OPCODE
;
4528 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4529 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4530 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4531 && i
.op
[0].disps
->X_op
== O_constant
)
4533 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4534 the absolute address given by the constant. Since ix86 jumps and
4535 calls are pc relative, we need to generate a reloc. */
4536 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4537 i
.op
[0].disps
->X_op
= O_symbol
;
4540 if (i
.tm
.opcode_modifier
.rex64
)
4543 /* For 8 bit registers we need an empty rex prefix. Also if the
4544 instruction already has a prefix, we need to convert old
4545 registers to new ones. */
4547 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4548 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4549 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4550 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4551 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4552 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4557 i
.rex
|= REX_OPCODE
;
4558 for (x
= 0; x
< 2; x
++)
4560 /* Look for 8 bit operand that uses old registers. */
4561 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4562 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4564 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4565 /* In case it is "hi" register, give up. */
4566 if (i
.op
[x
].regs
->reg_num
> 3)
4567 as_bad (_("can't encode register '%s%s' in an "
4568 "instruction requiring REX prefix."),
4569 register_prefix
, i
.op
[x
].regs
->reg_name
);
4571 /* Otherwise it is equivalent to the extended register.
4572 Since the encoding doesn't change this is merely
4573 cosmetic cleanup for debug output. */
4575 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4580 if (i
.rex
== 0 && i
.rex_encoding
)
4582 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4583 that uses legacy register. If it is "hi" register, don't add
4584 the REX_OPCODE byte. */
4586 for (x
= 0; x
< 2; x
++)
4587 if (i
.types
[x
].bitfield
.class == Reg
4588 && i
.types
[x
].bitfield
.byte
4589 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4590 && i
.op
[x
].regs
->reg_num
> 3)
4592 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
4593 i
.rex_encoding
= FALSE
;
4602 add_prefix (REX_OPCODE
| i
.rex
);
4604 /* We are ready to output the insn. */
4607 last_insn
.seg
= now_seg
;
4609 if (i
.tm
.opcode_modifier
.isprefix
)
4611 last_insn
.kind
= last_insn_prefix
;
4612 last_insn
.name
= i
.tm
.name
;
4613 last_insn
.file
= as_where (&last_insn
.line
);
4616 last_insn
.kind
= last_insn_other
;
4620 parse_insn (char *line
, char *mnemonic
)
4623 char *token_start
= l
;
4626 const insn_template
*t
;
4632 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4637 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4639 as_bad (_("no such instruction: `%s'"), token_start
);
4644 if (!is_space_char (*l
)
4645 && *l
!= END_OF_INSN
4647 || (*l
!= PREFIX_SEPARATOR
4650 as_bad (_("invalid character %s in mnemonic"),
4651 output_invalid (*l
));
4654 if (token_start
== l
)
4656 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4657 as_bad (_("expecting prefix; got nothing"));
4659 as_bad (_("expecting mnemonic; got nothing"));
4663 /* Look up instruction (or prefix) via hash table. */
4664 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4666 if (*l
!= END_OF_INSN
4667 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4668 && current_templates
4669 && current_templates
->start
->opcode_modifier
.isprefix
)
4671 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4673 as_bad ((flag_code
!= CODE_64BIT
4674 ? _("`%s' is only supported in 64-bit mode")
4675 : _("`%s' is not supported in 64-bit mode")),
4676 current_templates
->start
->name
);
4679 /* If we are in 16-bit mode, do not allow addr16 or data16.
4680 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4681 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4682 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4683 && flag_code
!= CODE_64BIT
4684 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4685 ^ (flag_code
== CODE_16BIT
)))
4687 as_bad (_("redundant %s prefix"),
4688 current_templates
->start
->name
);
4691 if (current_templates
->start
->opcode_length
== 0)
4693 /* Handle pseudo prefixes. */
4694 switch (current_templates
->start
->base_opcode
)
4698 i
.disp_encoding
= disp_encoding_8bit
;
4702 i
.disp_encoding
= disp_encoding_32bit
;
4706 i
.dir_encoding
= dir_encoding_load
;
4710 i
.dir_encoding
= dir_encoding_store
;
4714 i
.vec_encoding
= vex_encoding_vex
;
4718 i
.vec_encoding
= vex_encoding_vex3
;
4722 i
.vec_encoding
= vex_encoding_evex
;
4726 i
.rex_encoding
= TRUE
;
4730 i
.no_optimize
= TRUE
;
4738 /* Add prefix, checking for repeated prefixes. */
4739 switch (add_prefix (current_templates
->start
->base_opcode
))
4744 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4745 i
.notrack_prefix
= current_templates
->start
->name
;
4748 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4749 i
.hle_prefix
= current_templates
->start
->name
;
4750 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4751 i
.bnd_prefix
= current_templates
->start
->name
;
4753 i
.rep_prefix
= current_templates
->start
->name
;
4759 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4766 if (!current_templates
)
4768 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4769 Check if we should swap operand or force 32bit displacement in
4771 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4772 i
.dir_encoding
= dir_encoding_swap
;
4773 else if (mnem_p
- 3 == dot_p
4776 i
.disp_encoding
= disp_encoding_8bit
;
4777 else if (mnem_p
- 4 == dot_p
4781 i
.disp_encoding
= disp_encoding_32bit
;
4786 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4789 if (!current_templates
)
4792 if (mnem_p
> mnemonic
)
4794 /* See if we can get a match by trimming off a suffix. */
4797 case WORD_MNEM_SUFFIX
:
4798 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4799 i
.suffix
= SHORT_MNEM_SUFFIX
;
4802 case BYTE_MNEM_SUFFIX
:
4803 case QWORD_MNEM_SUFFIX
:
4804 i
.suffix
= mnem_p
[-1];
4806 current_templates
= (const templates
*) hash_find (op_hash
,
4809 case SHORT_MNEM_SUFFIX
:
4810 case LONG_MNEM_SUFFIX
:
4813 i
.suffix
= mnem_p
[-1];
4815 current_templates
= (const templates
*) hash_find (op_hash
,
4824 if (intel_float_operand (mnemonic
) == 1)
4825 i
.suffix
= SHORT_MNEM_SUFFIX
;
4827 i
.suffix
= LONG_MNEM_SUFFIX
;
4829 current_templates
= (const templates
*) hash_find (op_hash
,
4836 if (!current_templates
)
4838 as_bad (_("no such instruction: `%s'"), token_start
);
4843 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4844 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4846 /* Check for a branch hint. We allow ",pt" and ",pn" for
4847 predict taken and predict not taken respectively.
4848 I'm not sure that branch hints actually do anything on loop
4849 and jcxz insns (JumpByte) for current Pentium4 chips. They
4850 may work in the future and it doesn't hurt to accept them
4852 if (l
[0] == ',' && l
[1] == 'p')
4856 if (!add_prefix (DS_PREFIX_OPCODE
))
4860 else if (l
[2] == 'n')
4862 if (!add_prefix (CS_PREFIX_OPCODE
))
4868 /* Any other comma loses. */
4871 as_bad (_("invalid character %s in mnemonic"),
4872 output_invalid (*l
));
4876 /* Check if instruction is supported on specified architecture. */
4878 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4880 supported
|= cpu_flags_match (t
);
4881 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4883 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4884 as_warn (_("use .code16 to ensure correct addressing mode"));
4890 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4891 as_bad (flag_code
== CODE_64BIT
4892 ? _("`%s' is not supported in 64-bit mode")
4893 : _("`%s' is only supported in 64-bit mode"),
4894 current_templates
->start
->name
);
4896 as_bad (_("`%s' is not supported on `%s%s'"),
4897 current_templates
->start
->name
,
4898 cpu_arch_name
? cpu_arch_name
: default_arch
,
4899 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4905 parse_operands (char *l
, const char *mnemonic
)
4909 /* 1 if operand is pending after ','. */
4910 unsigned int expecting_operand
= 0;
4912 /* Non-zero if operand parens not balanced. */
4913 unsigned int paren_not_balanced
;
4915 while (*l
!= END_OF_INSN
)
4917 /* Skip optional white space before operand. */
4918 if (is_space_char (*l
))
4920 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4922 as_bad (_("invalid character %s before operand %d"),
4923 output_invalid (*l
),
4927 token_start
= l
; /* After white space. */
4928 paren_not_balanced
= 0;
4929 while (paren_not_balanced
|| *l
!= ',')
4931 if (*l
== END_OF_INSN
)
4933 if (paren_not_balanced
)
4936 as_bad (_("unbalanced parenthesis in operand %d."),
4939 as_bad (_("unbalanced brackets in operand %d."),
4944 break; /* we are done */
4946 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4948 as_bad (_("invalid character %s in operand %d"),
4949 output_invalid (*l
),
4956 ++paren_not_balanced
;
4958 --paren_not_balanced
;
4963 ++paren_not_balanced
;
4965 --paren_not_balanced
;
4969 if (l
!= token_start
)
4970 { /* Yes, we've read in another operand. */
4971 unsigned int operand_ok
;
4972 this_operand
= i
.operands
++;
4973 if (i
.operands
> MAX_OPERANDS
)
4975 as_bad (_("spurious operands; (%d operands/instruction max)"),
4979 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4980 /* Now parse operand adding info to 'i' as we go along. */
4981 END_STRING_AND_SAVE (l
);
4983 if (i
.mem_operands
> 1)
4985 as_bad (_("too many memory references for `%s'"),
4992 i386_intel_operand (token_start
,
4993 intel_float_operand (mnemonic
));
4995 operand_ok
= i386_att_operand (token_start
);
4997 RESTORE_END_STRING (l
);
5003 if (expecting_operand
)
5005 expecting_operand_after_comma
:
5006 as_bad (_("expecting operand after ','; got nothing"));
5011 as_bad (_("expecting operand before ','; got nothing"));
5016 /* Now *l must be either ',' or END_OF_INSN. */
5019 if (*++l
== END_OF_INSN
)
5021 /* Just skip it, if it's \n complain. */
5022 goto expecting_operand_after_comma
;
5024 expecting_operand
= 1;
5031 swap_2_operands (int xchg1
, int xchg2
)
5033 union i386_op temp_op
;
5034 i386_operand_type temp_type
;
5035 unsigned int temp_flags
;
5036 enum bfd_reloc_code_real temp_reloc
;
5038 temp_type
= i
.types
[xchg2
];
5039 i
.types
[xchg2
] = i
.types
[xchg1
];
5040 i
.types
[xchg1
] = temp_type
;
5042 temp_flags
= i
.flags
[xchg2
];
5043 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5044 i
.flags
[xchg1
] = temp_flags
;
5046 temp_op
= i
.op
[xchg2
];
5047 i
.op
[xchg2
] = i
.op
[xchg1
];
5048 i
.op
[xchg1
] = temp_op
;
5050 temp_reloc
= i
.reloc
[xchg2
];
5051 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5052 i
.reloc
[xchg1
] = temp_reloc
;
5056 if (i
.mask
->operand
== xchg1
)
5057 i
.mask
->operand
= xchg2
;
5058 else if (i
.mask
->operand
== xchg2
)
5059 i
.mask
->operand
= xchg1
;
5063 if (i
.broadcast
->operand
== xchg1
)
5064 i
.broadcast
->operand
= xchg2
;
5065 else if (i
.broadcast
->operand
== xchg2
)
5066 i
.broadcast
->operand
= xchg1
;
5070 if (i
.rounding
->operand
== xchg1
)
5071 i
.rounding
->operand
= xchg2
;
5072 else if (i
.rounding
->operand
== xchg2
)
5073 i
.rounding
->operand
= xchg1
;
5078 swap_operands (void)
5084 swap_2_operands (1, i
.operands
- 2);
5088 swap_2_operands (0, i
.operands
- 1);
5094 if (i
.mem_operands
== 2)
5096 const seg_entry
*temp_seg
;
5097 temp_seg
= i
.seg
[0];
5098 i
.seg
[0] = i
.seg
[1];
5099 i
.seg
[1] = temp_seg
;
5103 /* Try to ensure constant immediates are represented in the smallest
5108 char guess_suffix
= 0;
5112 guess_suffix
= i
.suffix
;
5113 else if (i
.reg_operands
)
5115 /* Figure out a suffix from the last register operand specified.
5116 We can't do this properly yet, i.e. excluding special register
5117 instances, but the following works for instructions with
5118 immediates. In any case, we can't set i.suffix yet. */
5119 for (op
= i
.operands
; --op
>= 0;)
5120 if (i
.types
[op
].bitfield
.class != Reg
)
5122 else if (i
.types
[op
].bitfield
.byte
)
5124 guess_suffix
= BYTE_MNEM_SUFFIX
;
5127 else if (i
.types
[op
].bitfield
.word
)
5129 guess_suffix
= WORD_MNEM_SUFFIX
;
5132 else if (i
.types
[op
].bitfield
.dword
)
5134 guess_suffix
= LONG_MNEM_SUFFIX
;
5137 else if (i
.types
[op
].bitfield
.qword
)
5139 guess_suffix
= QWORD_MNEM_SUFFIX
;
5143 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5144 guess_suffix
= WORD_MNEM_SUFFIX
;
5146 for (op
= i
.operands
; --op
>= 0;)
5147 if (operand_type_check (i
.types
[op
], imm
))
5149 switch (i
.op
[op
].imms
->X_op
)
5152 /* If a suffix is given, this operand may be shortened. */
5153 switch (guess_suffix
)
5155 case LONG_MNEM_SUFFIX
:
5156 i
.types
[op
].bitfield
.imm32
= 1;
5157 i
.types
[op
].bitfield
.imm64
= 1;
5159 case WORD_MNEM_SUFFIX
:
5160 i
.types
[op
].bitfield
.imm16
= 1;
5161 i
.types
[op
].bitfield
.imm32
= 1;
5162 i
.types
[op
].bitfield
.imm32s
= 1;
5163 i
.types
[op
].bitfield
.imm64
= 1;
5165 case BYTE_MNEM_SUFFIX
:
5166 i
.types
[op
].bitfield
.imm8
= 1;
5167 i
.types
[op
].bitfield
.imm8s
= 1;
5168 i
.types
[op
].bitfield
.imm16
= 1;
5169 i
.types
[op
].bitfield
.imm32
= 1;
5170 i
.types
[op
].bitfield
.imm32s
= 1;
5171 i
.types
[op
].bitfield
.imm64
= 1;
5175 /* If this operand is at most 16 bits, convert it
5176 to a signed 16 bit number before trying to see
5177 whether it will fit in an even smaller size.
5178 This allows a 16-bit operand such as $0xffe0 to
5179 be recognised as within Imm8S range. */
5180 if ((i
.types
[op
].bitfield
.imm16
)
5181 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5183 i
.op
[op
].imms
->X_add_number
=
5184 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5187 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5188 if ((i
.types
[op
].bitfield
.imm32
)
5189 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5192 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5193 ^ ((offsetT
) 1 << 31))
5194 - ((offsetT
) 1 << 31));
5198 = operand_type_or (i
.types
[op
],
5199 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5201 /* We must avoid matching of Imm32 templates when 64bit
5202 only immediate is available. */
5203 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5204 i
.types
[op
].bitfield
.imm32
= 0;
5211 /* Symbols and expressions. */
5213 /* Convert symbolic operand to proper sizes for matching, but don't
5214 prevent matching a set of insns that only supports sizes other
5215 than those matching the insn suffix. */
5217 i386_operand_type mask
, allowed
;
5218 const insn_template
*t
;
5220 operand_type_set (&mask
, 0);
5221 operand_type_set (&allowed
, 0);
5223 for (t
= current_templates
->start
;
5224 t
< current_templates
->end
;
5227 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5228 allowed
= operand_type_and (allowed
, anyimm
);
5230 switch (guess_suffix
)
5232 case QWORD_MNEM_SUFFIX
:
5233 mask
.bitfield
.imm64
= 1;
5234 mask
.bitfield
.imm32s
= 1;
5236 case LONG_MNEM_SUFFIX
:
5237 mask
.bitfield
.imm32
= 1;
5239 case WORD_MNEM_SUFFIX
:
5240 mask
.bitfield
.imm16
= 1;
5242 case BYTE_MNEM_SUFFIX
:
5243 mask
.bitfield
.imm8
= 1;
5248 allowed
= operand_type_and (mask
, allowed
);
5249 if (!operand_type_all_zero (&allowed
))
5250 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5257 /* Try to use the smallest displacement type too. */
5259 optimize_disp (void)
5263 for (op
= i
.operands
; --op
>= 0;)
5264 if (operand_type_check (i
.types
[op
], disp
))
5266 if (i
.op
[op
].disps
->X_op
== O_constant
)
5268 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5270 if (i
.types
[op
].bitfield
.disp16
5271 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5273 /* If this operand is at most 16 bits, convert
5274 to a signed 16 bit number and don't use 64bit
5276 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5277 i
.types
[op
].bitfield
.disp64
= 0;
5280 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5281 if (i
.types
[op
].bitfield
.disp32
5282 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5284 /* If this operand is at most 32 bits, convert
5285 to a signed 32 bit number and don't use 64bit
5287 op_disp
&= (((offsetT
) 2 << 31) - 1);
5288 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5289 i
.types
[op
].bitfield
.disp64
= 0;
5292 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5294 i
.types
[op
].bitfield
.disp8
= 0;
5295 i
.types
[op
].bitfield
.disp16
= 0;
5296 i
.types
[op
].bitfield
.disp32
= 0;
5297 i
.types
[op
].bitfield
.disp32s
= 0;
5298 i
.types
[op
].bitfield
.disp64
= 0;
5302 else if (flag_code
== CODE_64BIT
)
5304 if (fits_in_signed_long (op_disp
))
5306 i
.types
[op
].bitfield
.disp64
= 0;
5307 i
.types
[op
].bitfield
.disp32s
= 1;
5309 if (i
.prefix
[ADDR_PREFIX
]
5310 && fits_in_unsigned_long (op_disp
))
5311 i
.types
[op
].bitfield
.disp32
= 1;
5313 if ((i
.types
[op
].bitfield
.disp32
5314 || i
.types
[op
].bitfield
.disp32s
5315 || i
.types
[op
].bitfield
.disp16
)
5316 && fits_in_disp8 (op_disp
))
5317 i
.types
[op
].bitfield
.disp8
= 1;
5319 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5320 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5322 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5323 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5324 i
.types
[op
].bitfield
.disp8
= 0;
5325 i
.types
[op
].bitfield
.disp16
= 0;
5326 i
.types
[op
].bitfield
.disp32
= 0;
5327 i
.types
[op
].bitfield
.disp32s
= 0;
5328 i
.types
[op
].bitfield
.disp64
= 0;
5331 /* We only support 64bit displacement on constants. */
5332 i
.types
[op
].bitfield
.disp64
= 0;
5336 /* Return 1 if there is a match in broadcast bytes between operand
5337 GIVEN and instruction template T. */
5340 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5342 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5343 && i
.types
[given
].bitfield
.byte
)
5344 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5345 && i
.types
[given
].bitfield
.word
)
5346 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5347 && i
.types
[given
].bitfield
.dword
)
5348 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5349 && i
.types
[given
].bitfield
.qword
));
5352 /* Check if operands are valid for the instruction. */
5355 check_VecOperands (const insn_template
*t
)
5360 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5361 any one operand are implicity requiring AVX512VL support if the actual
5362 operand size is YMMword or XMMword. Since this function runs after
5363 template matching, there's no need to check for YMMword/XMMword in
5365 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5366 if (!cpu_flags_all_zero (&cpu
)
5367 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5368 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5370 for (op
= 0; op
< t
->operands
; ++op
)
5372 if (t
->operand_types
[op
].bitfield
.zmmword
5373 && (i
.types
[op
].bitfield
.ymmword
5374 || i
.types
[op
].bitfield
.xmmword
))
5376 i
.error
= unsupported
;
5382 /* Without VSIB byte, we can't have a vector register for index. */
5383 if (!t
->opcode_modifier
.vecsib
5385 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5386 || i
.index_reg
->reg_type
.bitfield
.ymmword
5387 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5389 i
.error
= unsupported_vector_index_register
;
5393 /* Check if default mask is allowed. */
5394 if (t
->opcode_modifier
.nodefmask
5395 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5397 i
.error
= no_default_mask
;
5401 /* For VSIB byte, we need a vector register for index, and all vector
5402 registers must be distinct. */
5403 if (t
->opcode_modifier
.vecsib
)
5406 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5407 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5408 || (t
->opcode_modifier
.vecsib
== VecSIB256
5409 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5410 || (t
->opcode_modifier
.vecsib
== VecSIB512
5411 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5413 i
.error
= invalid_vsib_address
;
5417 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5418 if (i
.reg_operands
== 2 && !i
.mask
)
5420 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5421 gas_assert (i
.types
[0].bitfield
.xmmword
5422 || i
.types
[0].bitfield
.ymmword
);
5423 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5424 gas_assert (i
.types
[2].bitfield
.xmmword
5425 || i
.types
[2].bitfield
.ymmword
);
5426 if (operand_check
== check_none
)
5428 if (register_number (i
.op
[0].regs
)
5429 != register_number (i
.index_reg
)
5430 && register_number (i
.op
[2].regs
)
5431 != register_number (i
.index_reg
)
5432 && register_number (i
.op
[0].regs
)
5433 != register_number (i
.op
[2].regs
))
5435 if (operand_check
== check_error
)
5437 i
.error
= invalid_vector_register_set
;
5440 as_warn (_("mask, index, and destination registers should be distinct"));
5442 else if (i
.reg_operands
== 1 && i
.mask
)
5444 if (i
.types
[1].bitfield
.class == RegSIMD
5445 && (i
.types
[1].bitfield
.xmmword
5446 || i
.types
[1].bitfield
.ymmword
5447 || i
.types
[1].bitfield
.zmmword
)
5448 && (register_number (i
.op
[1].regs
)
5449 == register_number (i
.index_reg
)))
5451 if (operand_check
== check_error
)
5453 i
.error
= invalid_vector_register_set
;
5456 if (operand_check
!= check_none
)
5457 as_warn (_("index and destination registers should be distinct"));
5462 /* Check if broadcast is supported by the instruction and is applied
5463 to the memory operand. */
5466 i386_operand_type type
, overlap
;
5468 /* Check if specified broadcast is supported in this instruction,
5469 and its broadcast bytes match the memory operand. */
5470 op
= i
.broadcast
->operand
;
5471 if (!t
->opcode_modifier
.broadcast
5472 || !(i
.flags
[op
] & Operand_Mem
)
5473 || (!i
.types
[op
].bitfield
.unspecified
5474 && !match_broadcast_size (t
, op
)))
5477 i
.error
= unsupported_broadcast
;
5481 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5482 * i
.broadcast
->type
);
5483 operand_type_set (&type
, 0);
5484 switch (i
.broadcast
->bytes
)
5487 type
.bitfield
.word
= 1;
5490 type
.bitfield
.dword
= 1;
5493 type
.bitfield
.qword
= 1;
5496 type
.bitfield
.xmmword
= 1;
5499 type
.bitfield
.ymmword
= 1;
5502 type
.bitfield
.zmmword
= 1;
5508 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5509 if (operand_type_all_zero (&overlap
))
5512 if (t
->opcode_modifier
.checkregsize
)
5516 type
.bitfield
.baseindex
= 1;
5517 for (j
= 0; j
< i
.operands
; ++j
)
5520 && !operand_type_register_match(i
.types
[j
],
5521 t
->operand_types
[j
],
5523 t
->operand_types
[op
]))
5528 /* If broadcast is supported in this instruction, we need to check if
5529 operand of one-element size isn't specified without broadcast. */
5530 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5532 /* Find memory operand. */
5533 for (op
= 0; op
< i
.operands
; op
++)
5534 if (i
.flags
[op
] & Operand_Mem
)
5536 gas_assert (op
< i
.operands
);
5537 /* Check size of the memory operand. */
5538 if (match_broadcast_size (t
, op
))
5540 i
.error
= broadcast_needed
;
5545 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5547 /* Check if requested masking is supported. */
5550 switch (t
->opcode_modifier
.masking
)
5554 case MERGING_MASKING
:
5555 if (i
.mask
->zeroing
)
5558 i
.error
= unsupported_masking
;
5562 case DYNAMIC_MASKING
:
5563 /* Memory destinations allow only merging masking. */
5564 if (i
.mask
->zeroing
&& i
.mem_operands
)
5566 /* Find memory operand. */
5567 for (op
= 0; op
< i
.operands
; op
++)
5568 if (i
.flags
[op
] & Operand_Mem
)
5570 gas_assert (op
< i
.operands
);
5571 if (op
== i
.operands
- 1)
5573 i
.error
= unsupported_masking
;
5583 /* Check if masking is applied to dest operand. */
5584 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5586 i
.error
= mask_not_on_destination
;
5593 if (!t
->opcode_modifier
.sae
5594 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5596 i
.error
= unsupported_rc_sae
;
5599 /* If the instruction has several immediate operands and one of
5600 them is rounding, the rounding operand should be the last
5601 immediate operand. */
5602 if (i
.imm_operands
> 1
5603 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5605 i
.error
= rc_sae_operand_not_last_imm
;
5610 /* Check vector Disp8 operand. */
5611 if (t
->opcode_modifier
.disp8memshift
5612 && i
.disp_encoding
!= disp_encoding_32bit
)
5615 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5616 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5617 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5620 const i386_operand_type
*type
= NULL
;
5623 for (op
= 0; op
< i
.operands
; op
++)
5624 if (i
.flags
[op
] & Operand_Mem
)
5626 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5627 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5628 else if (t
->operand_types
[op
].bitfield
.xmmword
5629 + t
->operand_types
[op
].bitfield
.ymmword
5630 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5631 type
= &t
->operand_types
[op
];
5632 else if (!i
.types
[op
].bitfield
.unspecified
)
5633 type
= &i
.types
[op
];
5635 else if (i
.types
[op
].bitfield
.class == RegSIMD
5636 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5638 if (i
.types
[op
].bitfield
.zmmword
)
5640 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5642 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5648 if (type
->bitfield
.zmmword
)
5650 else if (type
->bitfield
.ymmword
)
5652 else if (type
->bitfield
.xmmword
)
5656 /* For the check in fits_in_disp8(). */
5657 if (i
.memshift
== 0)
5661 for (op
= 0; op
< i
.operands
; op
++)
5662 if (operand_type_check (i
.types
[op
], disp
)
5663 && i
.op
[op
].disps
->X_op
== O_constant
)
5665 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5667 i
.types
[op
].bitfield
.disp8
= 1;
5670 i
.types
[op
].bitfield
.disp8
= 0;
5679 /* Check if operands are valid for the instruction. Update VEX
5683 VEX_check_operands (const insn_template
*t
)
5685 if (i
.vec_encoding
== vex_encoding_evex
)
5687 /* This instruction must be encoded with EVEX prefix. */
5688 if (!is_evex_encoding (t
))
5690 i
.error
= unsupported
;
5696 if (!t
->opcode_modifier
.vex
)
5698 /* This instruction template doesn't have VEX prefix. */
5699 if (i
.vec_encoding
!= vex_encoding_default
)
5701 i
.error
= unsupported
;
5707 /* Check the special Imm4 cases; must be the first operand. */
5708 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5710 if (i
.op
[0].imms
->X_op
!= O_constant
5711 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5717 /* Turn off Imm<N> so that update_imm won't complain. */
5718 operand_type_set (&i
.types
[0], 0);
5724 static const insn_template
*
5725 match_template (char mnem_suffix
)
5727 /* Points to template once we've found it. */
5728 const insn_template
*t
;
5729 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5730 i386_operand_type overlap4
;
5731 unsigned int found_reverse_match
;
5732 i386_opcode_modifier suffix_check
;
5733 i386_operand_type operand_types
[MAX_OPERANDS
];
5734 int addr_prefix_disp
;
5735 unsigned int j
, size_match
, check_register
;
5736 enum i386_error specific_error
= 0;
5738 #if MAX_OPERANDS != 5
5739 # error "MAX_OPERANDS must be 5."
5742 found_reverse_match
= 0;
5743 addr_prefix_disp
= -1;
5745 /* Prepare for mnemonic suffix check. */
5746 memset (&suffix_check
, 0, sizeof (suffix_check
));
5747 switch (mnem_suffix
)
5749 case BYTE_MNEM_SUFFIX
:
5750 suffix_check
.no_bsuf
= 1;
5752 case WORD_MNEM_SUFFIX
:
5753 suffix_check
.no_wsuf
= 1;
5755 case SHORT_MNEM_SUFFIX
:
5756 suffix_check
.no_ssuf
= 1;
5758 case LONG_MNEM_SUFFIX
:
5759 suffix_check
.no_lsuf
= 1;
5761 case QWORD_MNEM_SUFFIX
:
5762 suffix_check
.no_qsuf
= 1;
5765 /* NB: In Intel syntax, normally we can check for memory operand
5766 size when there is no mnemonic suffix. But jmp and call have
5767 2 different encodings with Dword memory operand size, one with
5768 No_ldSuf and the other without. i.suffix is set to
5769 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5770 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5771 suffix_check
.no_ldsuf
= 1;
5774 /* Must have right number of operands. */
5775 i
.error
= number_of_operands_mismatch
;
5777 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5779 addr_prefix_disp
= -1;
5780 found_reverse_match
= 0;
5782 if (i
.operands
!= t
->operands
)
5785 /* Check processor support. */
5786 i
.error
= unsupported
;
5787 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
5790 /* Check AT&T mnemonic. */
5791 i
.error
= unsupported_with_intel_mnemonic
;
5792 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5795 /* Check AT&T/Intel syntax. */
5796 i
.error
= unsupported_syntax
;
5797 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5798 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
5801 /* Check Intel64/AMD64 ISA. */
5805 /* Default: Don't accept Intel64. */
5806 if (t
->opcode_modifier
.isa64
== INTEL64
)
5810 /* -mamd64: Don't accept Intel64 and Intel64 only. */
5811 if (t
->opcode_modifier
.isa64
>= INTEL64
)
5815 /* -mintel64: Don't accept AMD64. */
5816 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
5821 /* Check the suffix. */
5822 i
.error
= invalid_instruction_suffix
;
5823 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5824 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5825 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5826 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5827 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5828 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5831 size_match
= operand_size_match (t
);
5835 /* This is intentionally not
5837 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5839 as the case of a missing * on the operand is accepted (perhaps with
5840 a warning, issued further down). */
5841 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5843 i
.error
= operand_type_mismatch
;
5847 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5848 operand_types
[j
] = t
->operand_types
[j
];
5850 /* In general, don't allow 64-bit operands in 32-bit mode. */
5851 if (i
.suffix
== QWORD_MNEM_SUFFIX
5852 && flag_code
!= CODE_64BIT
5854 ? (!t
->opcode_modifier
.ignoresize
5855 && !t
->opcode_modifier
.broadcast
5856 && !intel_float_operand (t
->name
))
5857 : intel_float_operand (t
->name
) != 2)
5858 && ((operand_types
[0].bitfield
.class != RegMMX
5859 && operand_types
[0].bitfield
.class != RegSIMD
)
5860 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5861 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5862 && (t
->base_opcode
!= 0x0fc7
5863 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5866 /* In general, don't allow 32-bit operands on pre-386. */
5867 else if (i
.suffix
== LONG_MNEM_SUFFIX
5868 && !cpu_arch_flags
.bitfield
.cpui386
5870 ? (!t
->opcode_modifier
.ignoresize
5871 && !intel_float_operand (t
->name
))
5872 : intel_float_operand (t
->name
) != 2)
5873 && ((operand_types
[0].bitfield
.class != RegMMX
5874 && operand_types
[0].bitfield
.class != RegSIMD
)
5875 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5876 && operand_types
[t
->operands
> 1].bitfield
.class
5880 /* Do not verify operands when there are none. */
5884 /* We've found a match; break out of loop. */
5888 if (!t
->opcode_modifier
.jump
5889 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5891 /* There should be only one Disp operand. */
5892 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5893 if (operand_type_check (operand_types
[j
], disp
))
5895 if (j
< MAX_OPERANDS
)
5897 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5899 addr_prefix_disp
= j
;
5901 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5902 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5906 override
= !override
;
5909 if (operand_types
[j
].bitfield
.disp32
5910 && operand_types
[j
].bitfield
.disp16
)
5912 operand_types
[j
].bitfield
.disp16
= override
;
5913 operand_types
[j
].bitfield
.disp32
= !override
;
5915 operand_types
[j
].bitfield
.disp32s
= 0;
5916 operand_types
[j
].bitfield
.disp64
= 0;
5920 if (operand_types
[j
].bitfield
.disp32s
5921 || operand_types
[j
].bitfield
.disp64
)
5923 operand_types
[j
].bitfield
.disp64
&= !override
;
5924 operand_types
[j
].bitfield
.disp32s
&= !override
;
5925 operand_types
[j
].bitfield
.disp32
= override
;
5927 operand_types
[j
].bitfield
.disp16
= 0;
5933 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5934 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5937 /* We check register size if needed. */
5938 if (t
->opcode_modifier
.checkregsize
)
5940 check_register
= (1 << t
->operands
) - 1;
5942 check_register
&= ~(1 << i
.broadcast
->operand
);
5947 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5948 switch (t
->operands
)
5951 if (!operand_type_match (overlap0
, i
.types
[0]))
5955 /* xchg %eax, %eax is a special case. It is an alias for nop
5956 only in 32bit mode and we can use opcode 0x90. In 64bit
5957 mode, we can't use 0x90 for xchg %eax, %eax since it should
5958 zero-extend %eax to %rax. */
5959 if (flag_code
== CODE_64BIT
5960 && t
->base_opcode
== 0x90
5961 && i
.types
[0].bitfield
.instance
== Accum
5962 && i
.types
[0].bitfield
.dword
5963 && i
.types
[1].bitfield
.instance
== Accum
5964 && i
.types
[1].bitfield
.dword
)
5966 /* xrelease mov %eax, <disp> is another special case. It must not
5967 match the accumulator-only encoding of mov. */
5968 if (flag_code
!= CODE_64BIT
5970 && t
->base_opcode
== 0xa0
5971 && i
.types
[0].bitfield
.instance
== Accum
5972 && (i
.flags
[1] & Operand_Mem
))
5977 if (!(size_match
& MATCH_STRAIGHT
))
5979 /* Reverse direction of operands if swapping is possible in the first
5980 place (operands need to be symmetric) and
5981 - the load form is requested, and the template is a store form,
5982 - the store form is requested, and the template is a load form,
5983 - the non-default (swapped) form is requested. */
5984 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5985 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5986 && !operand_type_all_zero (&overlap1
))
5987 switch (i
.dir_encoding
)
5989 case dir_encoding_load
:
5990 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5991 || t
->opcode_modifier
.regmem
)
5995 case dir_encoding_store
:
5996 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5997 && !t
->opcode_modifier
.regmem
)
6001 case dir_encoding_swap
:
6004 case dir_encoding_default
:
6007 /* If we want store form, we skip the current load. */
6008 if ((i
.dir_encoding
== dir_encoding_store
6009 || i
.dir_encoding
== dir_encoding_swap
)
6010 && i
.mem_operands
== 0
6011 && t
->opcode_modifier
.load
)
6016 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6017 if (!operand_type_match (overlap0
, i
.types
[0])
6018 || !operand_type_match (overlap1
, i
.types
[1])
6019 || ((check_register
& 3) == 3
6020 && !operand_type_register_match (i
.types
[0],
6025 /* Check if other direction is valid ... */
6026 if (!t
->opcode_modifier
.d
)
6030 if (!(size_match
& MATCH_REVERSE
))
6032 /* Try reversing direction of operands. */
6033 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6034 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6035 if (!operand_type_match (overlap0
, i
.types
[0])
6036 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6038 && !operand_type_register_match (i
.types
[0],
6039 operand_types
[i
.operands
- 1],
6040 i
.types
[i
.operands
- 1],
6043 /* Does not match either direction. */
6046 /* found_reverse_match holds which of D or FloatR
6048 if (!t
->opcode_modifier
.d
)
6049 found_reverse_match
= 0;
6050 else if (operand_types
[0].bitfield
.tbyte
)
6051 found_reverse_match
= Opcode_FloatD
;
6052 else if (operand_types
[0].bitfield
.xmmword
6053 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6054 || operand_types
[0].bitfield
.class == RegMMX
6055 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6056 || is_any_vex_encoding(t
))
6057 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6058 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6060 found_reverse_match
= Opcode_D
;
6061 if (t
->opcode_modifier
.floatr
)
6062 found_reverse_match
|= Opcode_FloatR
;
6066 /* Found a forward 2 operand match here. */
6067 switch (t
->operands
)
6070 overlap4
= operand_type_and (i
.types
[4],
6074 overlap3
= operand_type_and (i
.types
[3],
6078 overlap2
= operand_type_and (i
.types
[2],
6083 switch (t
->operands
)
6086 if (!operand_type_match (overlap4
, i
.types
[4])
6087 || !operand_type_register_match (i
.types
[3],
6094 if (!operand_type_match (overlap3
, i
.types
[3])
6095 || ((check_register
& 0xa) == 0xa
6096 && !operand_type_register_match (i
.types
[1],
6100 || ((check_register
& 0xc) == 0xc
6101 && !operand_type_register_match (i
.types
[2],
6108 /* Here we make use of the fact that there are no
6109 reverse match 3 operand instructions. */
6110 if (!operand_type_match (overlap2
, i
.types
[2])
6111 || ((check_register
& 5) == 5
6112 && !operand_type_register_match (i
.types
[0],
6116 || ((check_register
& 6) == 6
6117 && !operand_type_register_match (i
.types
[1],
6125 /* Found either forward/reverse 2, 3 or 4 operand match here:
6126 slip through to break. */
6129 /* Check if vector and VEX operands are valid. */
6130 if (check_VecOperands (t
) || VEX_check_operands (t
))
6132 specific_error
= i
.error
;
6136 /* We've found a match; break out of loop. */
6140 if (t
== current_templates
->end
)
6142 /* We found no match. */
6143 const char *err_msg
;
6144 switch (specific_error
? specific_error
: i
.error
)
6148 case operand_size_mismatch
:
6149 err_msg
= _("operand size mismatch");
6151 case operand_type_mismatch
:
6152 err_msg
= _("operand type mismatch");
6154 case register_type_mismatch
:
6155 err_msg
= _("register type mismatch");
6157 case number_of_operands_mismatch
:
6158 err_msg
= _("number of operands mismatch");
6160 case invalid_instruction_suffix
:
6161 err_msg
= _("invalid instruction suffix");
6164 err_msg
= _("constant doesn't fit in 4 bits");
6166 case unsupported_with_intel_mnemonic
:
6167 err_msg
= _("unsupported with Intel mnemonic");
6169 case unsupported_syntax
:
6170 err_msg
= _("unsupported syntax");
6173 as_bad (_("unsupported instruction `%s'"),
6174 current_templates
->start
->name
);
6176 case invalid_vsib_address
:
6177 err_msg
= _("invalid VSIB address");
6179 case invalid_vector_register_set
:
6180 err_msg
= _("mask, index, and destination registers must be distinct");
6182 case unsupported_vector_index_register
:
6183 err_msg
= _("unsupported vector index register");
6185 case unsupported_broadcast
:
6186 err_msg
= _("unsupported broadcast");
6188 case broadcast_needed
:
6189 err_msg
= _("broadcast is needed for operand of such type");
6191 case unsupported_masking
:
6192 err_msg
= _("unsupported masking");
6194 case mask_not_on_destination
:
6195 err_msg
= _("mask not on destination operand");
6197 case no_default_mask
:
6198 err_msg
= _("default mask isn't allowed");
6200 case unsupported_rc_sae
:
6201 err_msg
= _("unsupported static rounding/sae");
6203 case rc_sae_operand_not_last_imm
:
6205 err_msg
= _("RC/SAE operand must precede immediate operands");
6207 err_msg
= _("RC/SAE operand must follow immediate operands");
6209 case invalid_register_operand
:
6210 err_msg
= _("invalid register operand");
6213 as_bad (_("%s for `%s'"), err_msg
,
6214 current_templates
->start
->name
);
6218 if (!quiet_warnings
)
6221 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6222 as_warn (_("indirect %s without `*'"), t
->name
);
6224 if (t
->opcode_modifier
.isprefix
6225 && t
->opcode_modifier
.ignoresize
)
6227 /* Warn them that a data or address size prefix doesn't
6228 affect assembly of the next line of code. */
6229 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6233 /* Copy the template we found. */
6236 if (addr_prefix_disp
!= -1)
6237 i
.tm
.operand_types
[addr_prefix_disp
]
6238 = operand_types
[addr_prefix_disp
];
6240 if (found_reverse_match
)
6242 /* If we found a reverse match we must alter the opcode direction
6243 bit and clear/flip the regmem modifier one. found_reverse_match
6244 holds bits to change (different for int & float insns). */
6246 i
.tm
.base_opcode
^= found_reverse_match
;
6248 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6249 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6251 /* Certain SIMD insns have their load forms specified in the opcode
6252 table, and hence we need to _set_ RegMem instead of clearing it.
6253 We need to avoid setting the bit though on insns like KMOVW. */
6254 i
.tm
.opcode_modifier
.regmem
6255 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6256 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6257 && !i
.tm
.opcode_modifier
.regmem
;
6266 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6267 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6269 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6271 as_bad (_("`%s' operand %u must use `%ses' segment"),
6273 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6278 /* There's only ever one segment override allowed per instruction.
6279 This instruction possibly has a legal segment override on the
6280 second operand, so copy the segment to where non-string
6281 instructions store it, allowing common code. */
6282 i
.seg
[op
] = i
.seg
[1];
6288 process_suffix (void)
6290 /* If matched instruction specifies an explicit instruction mnemonic
6292 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6293 i
.suffix
= WORD_MNEM_SUFFIX
;
6294 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6295 i
.suffix
= LONG_MNEM_SUFFIX
;
6296 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6297 i
.suffix
= QWORD_MNEM_SUFFIX
;
6298 else if (i
.reg_operands
6299 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6301 unsigned int numop
= i
.operands
;
6303 /* movsx/movzx want only their source operand considered here, for the
6304 ambiguity checking below. The suffix will be replaced afterwards
6305 to represent the destination (register). */
6306 if (((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
)
6307 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6310 /* If there's no instruction mnemonic suffix we try to invent one
6311 based on GPR operands. */
6314 /* We take i.suffix from the last register operand specified,
6315 Destination register type is more significant than source
6316 register type. crc32 in SSE4.2 prefers source register
6318 unsigned int op
= i
.tm
.base_opcode
!= 0xf20f38f0 ? i
.operands
: 1;
6321 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6322 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6324 if (i
.types
[op
].bitfield
.class != Reg
)
6326 if (i
.types
[op
].bitfield
.byte
)
6327 i
.suffix
= BYTE_MNEM_SUFFIX
;
6328 else if (i
.types
[op
].bitfield
.word
)
6329 i
.suffix
= WORD_MNEM_SUFFIX
;
6330 else if (i
.types
[op
].bitfield
.dword
)
6331 i
.suffix
= LONG_MNEM_SUFFIX
;
6332 else if (i
.types
[op
].bitfield
.qword
)
6333 i
.suffix
= QWORD_MNEM_SUFFIX
;
6339 /* As an exception, movsx/movzx silently default to a byte source
6341 if ((i
.tm
.base_opcode
| 8) == 0xfbe && i
.tm
.opcode_modifier
.w
6342 && !i
.suffix
&& !intel_syntax
)
6343 i
.suffix
= BYTE_MNEM_SUFFIX
;
6345 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6348 && i
.tm
.opcode_modifier
.ignoresize
6349 && i
.tm
.opcode_modifier
.no_bsuf
)
6351 else if (!check_byte_reg ())
6354 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6357 && i
.tm
.opcode_modifier
.ignoresize
6358 && i
.tm
.opcode_modifier
.no_lsuf
6359 && !i
.tm
.opcode_modifier
.todword
6360 && !i
.tm
.opcode_modifier
.toqword
)
6362 else if (!check_long_reg ())
6365 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6368 && i
.tm
.opcode_modifier
.ignoresize
6369 && i
.tm
.opcode_modifier
.no_qsuf
6370 && !i
.tm
.opcode_modifier
.todword
6371 && !i
.tm
.opcode_modifier
.toqword
)
6373 else if (!check_qword_reg ())
6376 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6379 && i
.tm
.opcode_modifier
.ignoresize
6380 && i
.tm
.opcode_modifier
.no_wsuf
)
6382 else if (!check_word_reg ())
6385 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6386 /* Do nothing if the instruction is going to ignore the prefix. */
6391 /* Undo the movsx/movzx change done above. */
6394 else if (i
.tm
.opcode_modifier
.defaultsize
&& !i
.suffix
)
6396 i
.suffix
= stackop_size
;
6397 if (stackop_size
== LONG_MNEM_SUFFIX
)
6399 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6400 .code16gcc directive to support 16-bit mode with
6401 32-bit address. For IRET without a suffix, generate
6402 16-bit IRET (opcode 0xcf) to return from an interrupt
6404 if (i
.tm
.base_opcode
== 0xcf)
6406 i
.suffix
= WORD_MNEM_SUFFIX
;
6407 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6409 /* Warn about changed behavior for segment register push/pop. */
6410 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6411 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6416 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6417 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6418 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6419 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6420 && i
.tm
.extension_opcode
<= 3)))
6425 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6427 i
.suffix
= QWORD_MNEM_SUFFIX
;
6432 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6433 i
.suffix
= LONG_MNEM_SUFFIX
;
6436 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6437 i
.suffix
= WORD_MNEM_SUFFIX
;
6443 && (!i
.tm
.opcode_modifier
.defaultsize
6444 /* Also cover lret/retf/iret in 64-bit mode. */
6445 || (flag_code
== CODE_64BIT
6446 && !i
.tm
.opcode_modifier
.no_lsuf
6447 && !i
.tm
.opcode_modifier
.no_qsuf
))
6448 && !i
.tm
.opcode_modifier
.ignoresize
6449 /* Accept FLDENV et al without suffix. */
6450 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
6452 unsigned int suffixes
, evex
= 0;
6454 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6455 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6457 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6459 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6461 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6463 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6466 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6467 also suitable for AT&T syntax mode, it was requested that this be
6468 restricted to just Intel syntax. */
6471 i386_cpu_flags cpu
= cpu_flags_and (i
.tm
.cpu_flags
, avx512
);
6473 if (!cpu_flags_all_zero (&cpu
) && !i
.broadcast
)
6477 for (op
= 0; op
< i
.tm
.operands
; ++op
)
6479 if (!cpu_arch_flags
.bitfield
.cpuavx512vl
)
6481 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6482 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
6483 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6484 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
6485 if (!i
.tm
.opcode_modifier
.evex
6486 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
6487 i
.tm
.opcode_modifier
.evex
= EVEX512
;
6490 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
6491 + i
.tm
.operand_types
[op
].bitfield
.ymmword
6492 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
6495 /* Any properly sized operand disambiguates the insn. */
6496 if (i
.types
[op
].bitfield
.xmmword
6497 || i
.types
[op
].bitfield
.ymmword
6498 || i
.types
[op
].bitfield
.zmmword
)
6500 suffixes
&= ~(7 << 6);
6505 if ((i
.flags
[op
] & Operand_Mem
)
6506 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
6508 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
6510 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
6512 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
6520 /* Are multiple suffixes / operand sizes allowed? */
6521 if (suffixes
& (suffixes
- 1))
6524 && (!i
.tm
.opcode_modifier
.defaultsize
6525 || operand_check
== check_error
))
6527 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6530 if (operand_check
== check_error
)
6532 as_bad (_("no instruction mnemonic suffix given and "
6533 "no register operands; can't size `%s'"), i
.tm
.name
);
6536 if (operand_check
== check_warning
)
6537 as_warn (_("%s; using default for `%s'"),
6539 ? _("ambiguous operand size")
6540 : _("no instruction mnemonic suffix given and "
6541 "no register operands"),
6544 if (i
.tm
.opcode_modifier
.floatmf
)
6545 i
.suffix
= SHORT_MNEM_SUFFIX
;
6546 else if ((i
.tm
.base_opcode
| 8) == 0xfbe
6547 || (i
.tm
.base_opcode
== 0x63
6548 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6549 /* handled below */;
6551 i
.tm
.opcode_modifier
.evex
= evex
;
6552 else if (flag_code
== CODE_16BIT
)
6553 i
.suffix
= WORD_MNEM_SUFFIX
;
6554 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
6555 i
.suffix
= LONG_MNEM_SUFFIX
;
6557 i
.suffix
= QWORD_MNEM_SUFFIX
;
6561 if ((i
.tm
.base_opcode
| 8) == 0xfbe
6562 || (i
.tm
.base_opcode
== 0x63 && i
.tm
.cpu_flags
.bitfield
.cpu64
))
6564 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6565 In AT&T syntax, if there is no suffix (warned about above), the default
6566 will be byte extension. */
6567 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
6568 i
.tm
.base_opcode
|= 1;
6570 /* For further processing, the suffix should represent the destination
6571 (register). This is already the case when one was used with
6572 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6573 no suffix to begin with. */
6574 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
6576 if (i
.types
[1].bitfield
.word
)
6577 i
.suffix
= WORD_MNEM_SUFFIX
;
6578 else if (i
.types
[1].bitfield
.qword
)
6579 i
.suffix
= QWORD_MNEM_SUFFIX
;
6581 i
.suffix
= LONG_MNEM_SUFFIX
;
6583 i
.tm
.opcode_modifier
.w
= 0;
6587 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
6588 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
6589 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
6591 /* Change the opcode based on the operand size given by i.suffix. */
6594 /* Size floating point instruction. */
6595 case LONG_MNEM_SUFFIX
:
6596 if (i
.tm
.opcode_modifier
.floatmf
)
6598 i
.tm
.base_opcode
^= 4;
6602 case WORD_MNEM_SUFFIX
:
6603 case QWORD_MNEM_SUFFIX
:
6604 /* It's not a byte, select word/dword operation. */
6605 if (i
.tm
.opcode_modifier
.w
)
6608 i
.tm
.base_opcode
|= 8;
6610 i
.tm
.base_opcode
|= 1;
6613 case SHORT_MNEM_SUFFIX
:
6614 /* Now select between word & dword operations via the operand
6615 size prefix, except for instructions that will ignore this
6617 if (i
.reg_operands
> 0
6618 && i
.types
[0].bitfield
.class == Reg
6619 && i
.tm
.opcode_modifier
.addrprefixopreg
6620 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6621 || i
.operands
== 1))
6623 /* The address size override prefix changes the size of the
6625 if ((flag_code
== CODE_32BIT
6626 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6627 || (flag_code
!= CODE_32BIT
6628 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6629 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6632 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6633 && !i
.tm
.opcode_modifier
.ignoresize
6634 && !i
.tm
.opcode_modifier
.floatmf
6635 && !is_any_vex_encoding (&i
.tm
)
6636 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6637 || (flag_code
== CODE_64BIT
6638 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6640 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6642 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6643 prefix
= ADDR_PREFIX_OPCODE
;
6645 if (!add_prefix (prefix
))
6649 /* Set mode64 for an operand. */
6650 if (i
.suffix
== QWORD_MNEM_SUFFIX
6651 && flag_code
== CODE_64BIT
6652 && !i
.tm
.opcode_modifier
.norex64
6653 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6655 && ! (i
.operands
== 2
6656 && i
.tm
.base_opcode
== 0x90
6657 && i
.tm
.extension_opcode
== None
6658 && i
.types
[0].bitfield
.instance
== Accum
6659 && i
.types
[0].bitfield
.qword
6660 && i
.types
[1].bitfield
.instance
== Accum
6661 && i
.types
[1].bitfield
.qword
))
6667 if (i
.reg_operands
!= 0
6669 && i
.tm
.opcode_modifier
.addrprefixopreg
6670 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6672 /* Check invalid register operand when the address size override
6673 prefix changes the size of register operands. */
6675 enum { need_word
, need_dword
, need_qword
} need
;
6677 if (flag_code
== CODE_32BIT
)
6678 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6681 if (i
.prefix
[ADDR_PREFIX
])
6684 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6687 for (op
= 0; op
< i
.operands
; op
++)
6688 if (i
.types
[op
].bitfield
.class == Reg
6689 && ((need
== need_word
6690 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6691 || (need
== need_dword
6692 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6693 || (need
== need_qword
6694 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6696 as_bad (_("invalid register operand size for `%s'"),
6706 check_byte_reg (void)
6710 for (op
= i
.operands
; --op
>= 0;)
6712 /* Skip non-register operands. */
6713 if (i
.types
[op
].bitfield
.class != Reg
)
6716 /* If this is an eight bit register, it's OK. If it's the 16 or
6717 32 bit version of an eight bit register, we will just use the
6718 low portion, and that's OK too. */
6719 if (i
.types
[op
].bitfield
.byte
)
6722 /* I/O port address operands are OK too. */
6723 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6724 && i
.tm
.operand_types
[op
].bitfield
.word
)
6727 /* crc32 only wants its source operand checked here. */
6728 if (i
.tm
.base_opcode
== 0xf20f38f0 && op
)
6731 /* Any other register is bad. */
6732 if (i
.types
[op
].bitfield
.class == Reg
6733 || i
.types
[op
].bitfield
.class == RegMMX
6734 || i
.types
[op
].bitfield
.class == RegSIMD
6735 || i
.types
[op
].bitfield
.class == SReg
6736 || i
.types
[op
].bitfield
.class == RegCR
6737 || i
.types
[op
].bitfield
.class == RegDR
6738 || i
.types
[op
].bitfield
.class == RegTR
)
6740 as_bad (_("`%s%s' not allowed with `%s%c'"),
6742 i
.op
[op
].regs
->reg_name
,
6752 check_long_reg (void)
6756 for (op
= i
.operands
; --op
>= 0;)
6757 /* Skip non-register operands. */
6758 if (i
.types
[op
].bitfield
.class != Reg
)
6760 /* Reject eight bit registers, except where the template requires
6761 them. (eg. movzb) */
6762 else if (i
.types
[op
].bitfield
.byte
6763 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6764 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6765 && (i
.tm
.operand_types
[op
].bitfield
.word
6766 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6768 as_bad (_("`%s%s' not allowed with `%s%c'"),
6770 i
.op
[op
].regs
->reg_name
,
6775 /* Error if the e prefix on a general reg is missing. */
6776 else if (i
.types
[op
].bitfield
.word
6777 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6778 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6779 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6781 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6782 register_prefix
, i
.op
[op
].regs
->reg_name
,
6786 /* Warn if the r prefix on a general reg is present. */
6787 else if (i
.types
[op
].bitfield
.qword
6788 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6789 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6790 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6793 && i
.tm
.opcode_modifier
.toqword
6794 && i
.types
[0].bitfield
.class != RegSIMD
)
6796 /* Convert to QWORD. We want REX byte. */
6797 i
.suffix
= QWORD_MNEM_SUFFIX
;
6801 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6802 register_prefix
, i
.op
[op
].regs
->reg_name
,
6811 check_qword_reg (void)
6815 for (op
= i
.operands
; --op
>= 0; )
6816 /* Skip non-register operands. */
6817 if (i
.types
[op
].bitfield
.class != Reg
)
6819 /* Reject eight bit registers, except where the template requires
6820 them. (eg. movzb) */
6821 else if (i
.types
[op
].bitfield
.byte
6822 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6823 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6824 && (i
.tm
.operand_types
[op
].bitfield
.word
6825 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6827 as_bad (_("`%s%s' not allowed with `%s%c'"),
6829 i
.op
[op
].regs
->reg_name
,
6834 /* Warn if the r prefix on a general reg is missing. */
6835 else if ((i
.types
[op
].bitfield
.word
6836 || i
.types
[op
].bitfield
.dword
)
6837 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6838 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6839 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6841 /* Prohibit these changes in the 64bit mode, since the
6842 lowering is more complicated. */
6844 && i
.tm
.opcode_modifier
.todword
6845 && i
.types
[0].bitfield
.class != RegSIMD
)
6847 /* Convert to DWORD. We don't want REX byte. */
6848 i
.suffix
= LONG_MNEM_SUFFIX
;
6852 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6853 register_prefix
, i
.op
[op
].regs
->reg_name
,
6862 check_word_reg (void)
6865 for (op
= i
.operands
; --op
>= 0;)
6866 /* Skip non-register operands. */
6867 if (i
.types
[op
].bitfield
.class != Reg
)
6869 /* Reject eight bit registers, except where the template requires
6870 them. (eg. movzb) */
6871 else if (i
.types
[op
].bitfield
.byte
6872 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6873 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6874 && (i
.tm
.operand_types
[op
].bitfield
.word
6875 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6877 as_bad (_("`%s%s' not allowed with `%s%c'"),
6879 i
.op
[op
].regs
->reg_name
,
6884 /* Error if the e or r prefix on a general reg is present. */
6885 else if ((i
.types
[op
].bitfield
.dword
6886 || i
.types
[op
].bitfield
.qword
)
6887 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6888 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6889 && i
.tm
.operand_types
[op
].bitfield
.word
)
6891 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6892 register_prefix
, i
.op
[op
].regs
->reg_name
,
6900 update_imm (unsigned int j
)
6902 i386_operand_type overlap
= i
.types
[j
];
6903 if ((overlap
.bitfield
.imm8
6904 || overlap
.bitfield
.imm8s
6905 || overlap
.bitfield
.imm16
6906 || overlap
.bitfield
.imm32
6907 || overlap
.bitfield
.imm32s
6908 || overlap
.bitfield
.imm64
)
6909 && !operand_type_equal (&overlap
, &imm8
)
6910 && !operand_type_equal (&overlap
, &imm8s
)
6911 && !operand_type_equal (&overlap
, &imm16
)
6912 && !operand_type_equal (&overlap
, &imm32
)
6913 && !operand_type_equal (&overlap
, &imm32s
)
6914 && !operand_type_equal (&overlap
, &imm64
))
6918 i386_operand_type temp
;
6920 operand_type_set (&temp
, 0);
6921 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6923 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6924 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6926 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6927 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6928 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6930 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6931 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6934 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6937 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6938 || operand_type_equal (&overlap
, &imm16_32
)
6939 || operand_type_equal (&overlap
, &imm16_32s
))
6941 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6946 if (!operand_type_equal (&overlap
, &imm8
)
6947 && !operand_type_equal (&overlap
, &imm8s
)
6948 && !operand_type_equal (&overlap
, &imm16
)
6949 && !operand_type_equal (&overlap
, &imm32
)
6950 && !operand_type_equal (&overlap
, &imm32s
)
6951 && !operand_type_equal (&overlap
, &imm64
))
6953 as_bad (_("no instruction mnemonic suffix given; "
6954 "can't determine immediate size"));
6958 i
.types
[j
] = overlap
;
6968 /* Update the first 2 immediate operands. */
6969 n
= i
.operands
> 2 ? 2 : i
.operands
;
6972 for (j
= 0; j
< n
; j
++)
6973 if (update_imm (j
) == 0)
6976 /* The 3rd operand can't be immediate operand. */
6977 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6984 process_operands (void)
6986 /* Default segment register this instruction will use for memory
6987 accesses. 0 means unknown. This is only for optimizing out
6988 unnecessary segment overrides. */
6989 const seg_entry
*default_seg
= 0;
6991 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6993 unsigned int dupl
= i
.operands
;
6994 unsigned int dest
= dupl
- 1;
6997 /* The destination must be an xmm register. */
6998 gas_assert (i
.reg_operands
6999 && MAX_OPERANDS
> dupl
7000 && operand_type_equal (&i
.types
[dest
], ®xmm
));
7002 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7003 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7005 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
7007 /* Keep xmm0 for instructions with VEX prefix and 3
7009 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
7010 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
7015 /* We remove the first xmm0 and keep the number of
7016 operands unchanged, which in fact duplicates the
7018 for (j
= 1; j
< i
.operands
; j
++)
7020 i
.op
[j
- 1] = i
.op
[j
];
7021 i
.types
[j
- 1] = i
.types
[j
];
7022 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7023 i
.flags
[j
- 1] = i
.flags
[j
];
7027 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
7029 gas_assert ((MAX_OPERANDS
- 1) > dupl
7030 && (i
.tm
.opcode_modifier
.vexsources
7033 /* Add the implicit xmm0 for instructions with VEX prefix
7035 for (j
= i
.operands
; j
> 0; j
--)
7037 i
.op
[j
] = i
.op
[j
- 1];
7038 i
.types
[j
] = i
.types
[j
- 1];
7039 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
7040 i
.flags
[j
] = i
.flags
[j
- 1];
7043 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
7044 i
.types
[0] = regxmm
;
7045 i
.tm
.operand_types
[0] = regxmm
;
7048 i
.reg_operands
+= 2;
7053 i
.op
[dupl
] = i
.op
[dest
];
7054 i
.types
[dupl
] = i
.types
[dest
];
7055 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7056 i
.flags
[dupl
] = i
.flags
[dest
];
7065 i
.op
[dupl
] = i
.op
[dest
];
7066 i
.types
[dupl
] = i
.types
[dest
];
7067 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7068 i
.flags
[dupl
] = i
.flags
[dest
];
7071 if (i
.tm
.opcode_modifier
.immext
)
7074 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7075 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7079 for (j
= 1; j
< i
.operands
; j
++)
7081 i
.op
[j
- 1] = i
.op
[j
];
7082 i
.types
[j
- 1] = i
.types
[j
];
7084 /* We need to adjust fields in i.tm since they are used by
7085 build_modrm_byte. */
7086 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7088 i
.flags
[j
- 1] = i
.flags
[j
];
7095 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7097 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7099 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7100 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7101 regnum
= register_number (i
.op
[1].regs
);
7102 first_reg_in_group
= regnum
& ~3;
7103 last_reg_in_group
= first_reg_in_group
+ 3;
7104 if (regnum
!= first_reg_in_group
)
7105 as_warn (_("source register `%s%s' implicitly denotes"
7106 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7107 register_prefix
, i
.op
[1].regs
->reg_name
,
7108 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7109 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7112 else if (i
.tm
.opcode_modifier
.regkludge
)
7114 /* The imul $imm, %reg instruction is converted into
7115 imul $imm, %reg, %reg, and the clr %reg instruction
7116 is converted into xor %reg, %reg. */
7118 unsigned int first_reg_op
;
7120 if (operand_type_check (i
.types
[0], reg
))
7124 /* Pretend we saw the extra register operand. */
7125 gas_assert (i
.reg_operands
== 1
7126 && i
.op
[first_reg_op
+ 1].regs
== 0);
7127 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7128 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7133 if (i
.tm
.opcode_modifier
.modrm
)
7135 /* The opcode is completed (modulo i.tm.extension_opcode which
7136 must be put into the modrm byte). Now, we make the modrm and
7137 index base bytes based on all the info we've collected. */
7139 default_seg
= build_modrm_byte ();
7141 else if (i
.types
[0].bitfield
.class == SReg
)
7143 if (flag_code
!= CODE_64BIT
7144 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7145 && i
.op
[0].regs
->reg_num
== 1
7146 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7147 && i
.op
[0].regs
->reg_num
< 4)
7149 as_bad (_("you can't `%s %s%s'"),
7150 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7153 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7155 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7156 i
.tm
.opcode_length
= 2;
7158 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7160 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7164 else if (i
.tm
.opcode_modifier
.isstring
)
7166 /* For the string instructions that allow a segment override
7167 on one of their operands, the default segment is ds. */
7170 else if (i
.short_form
)
7172 /* The register or float register operand is in operand
7174 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7176 /* Register goes in low 3 bits of opcode. */
7177 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7178 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7180 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7182 /* Warn about some common errors, but press on regardless.
7183 The first case can be generated by gcc (<= 2.8.1). */
7184 if (i
.operands
== 2)
7186 /* Reversed arguments on faddp, fsubp, etc. */
7187 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7188 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7189 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7193 /* Extraneous `l' suffix on fp insn. */
7194 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7195 register_prefix
, i
.op
[0].regs
->reg_name
);
7200 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
7201 && i
.tm
.base_opcode
== 0x8d /* lea */
7202 && !is_any_vex_encoding(&i
.tm
))
7204 if (!quiet_warnings
)
7205 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7209 i
.prefix
[SEG_PREFIX
] = 0;
7213 /* If a segment was explicitly specified, and the specified segment
7214 is neither the default nor the one already recorded from a prefix,
7215 use an opcode prefix to select it. If we never figured out what
7216 the default segment is, then default_seg will be zero at this
7217 point, and the specified segment prefix will always be used. */
7219 && i
.seg
[0] != default_seg
7220 && i
.seg
[0]->seg_prefix
!= i
.prefix
[SEG_PREFIX
])
7222 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7228 static const seg_entry
*
7229 build_modrm_byte (void)
7231 const seg_entry
*default_seg
= 0;
7232 unsigned int source
, dest
;
7235 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7238 unsigned int nds
, reg_slot
;
7241 dest
= i
.operands
- 1;
7244 /* There are 2 kinds of instructions:
7245 1. 5 operands: 4 register operands or 3 register operands
7246 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7247 VexW0 or VexW1. The destination must be either XMM, YMM or
7249 2. 4 operands: 4 register operands or 3 register operands
7250 plus 1 memory operand, with VexXDS. */
7251 gas_assert ((i
.reg_operands
== 4
7252 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7253 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7254 && i
.tm
.opcode_modifier
.vexw
7255 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7257 /* If VexW1 is set, the first non-immediate operand is the source and
7258 the second non-immediate one is encoded in the immediate operand. */
7259 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7261 source
= i
.imm_operands
;
7262 reg_slot
= i
.imm_operands
+ 1;
7266 source
= i
.imm_operands
+ 1;
7267 reg_slot
= i
.imm_operands
;
7270 if (i
.imm_operands
== 0)
7272 /* When there is no immediate operand, generate an 8bit
7273 immediate operand to encode the first operand. */
7274 exp
= &im_expressions
[i
.imm_operands
++];
7275 i
.op
[i
.operands
].imms
= exp
;
7276 i
.types
[i
.operands
] = imm8
;
7279 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7280 exp
->X_op
= O_constant
;
7281 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7282 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7286 gas_assert (i
.imm_operands
== 1);
7287 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7288 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7290 /* Turn on Imm8 again so that output_imm will generate it. */
7291 i
.types
[0].bitfield
.imm8
= 1;
7293 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7294 i
.op
[0].imms
->X_add_number
7295 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7296 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7299 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7300 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7305 /* i.reg_operands MUST be the number of real register operands;
7306 implicit registers do not count. If there are 3 register
7307 operands, it must be a instruction with VexNDS. For a
7308 instruction with VexNDD, the destination register is encoded
7309 in VEX prefix. If there are 4 register operands, it must be
7310 a instruction with VEX prefix and 3 sources. */
7311 if (i
.mem_operands
== 0
7312 && ((i
.reg_operands
== 2
7313 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7314 || (i
.reg_operands
== 3
7315 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7316 || (i
.reg_operands
== 4 && vex_3_sources
)))
7324 /* When there are 3 operands, one of them may be immediate,
7325 which may be the first or the last operand. Otherwise,
7326 the first operand must be shift count register (cl) or it
7327 is an instruction with VexNDS. */
7328 gas_assert (i
.imm_operands
== 1
7329 || (i
.imm_operands
== 0
7330 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7331 || (i
.types
[0].bitfield
.instance
== RegC
7332 && i
.types
[0].bitfield
.byte
))));
7333 if (operand_type_check (i
.types
[0], imm
)
7334 || (i
.types
[0].bitfield
.instance
== RegC
7335 && i
.types
[0].bitfield
.byte
))
7341 /* When there are 4 operands, the first two must be 8bit
7342 immediate operands. The source operand will be the 3rd
7345 For instructions with VexNDS, if the first operand
7346 an imm8, the source operand is the 2nd one. If the last
7347 operand is imm8, the source operand is the first one. */
7348 gas_assert ((i
.imm_operands
== 2
7349 && i
.types
[0].bitfield
.imm8
7350 && i
.types
[1].bitfield
.imm8
)
7351 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7352 && i
.imm_operands
== 1
7353 && (i
.types
[0].bitfield
.imm8
7354 || i
.types
[i
.operands
- 1].bitfield
.imm8
7356 if (i
.imm_operands
== 2)
7360 if (i
.types
[0].bitfield
.imm8
)
7367 if (is_evex_encoding (&i
.tm
))
7369 /* For EVEX instructions, when there are 5 operands, the
7370 first one must be immediate operand. If the second one
7371 is immediate operand, the source operand is the 3th
7372 one. If the last one is immediate operand, the source
7373 operand is the 2nd one. */
7374 gas_assert (i
.imm_operands
== 2
7375 && i
.tm
.opcode_modifier
.sae
7376 && operand_type_check (i
.types
[0], imm
));
7377 if (operand_type_check (i
.types
[1], imm
))
7379 else if (operand_type_check (i
.types
[4], imm
))
7393 /* RC/SAE operand could be between DEST and SRC. That happens
7394 when one operand is GPR and the other one is XMM/YMM/ZMM
7396 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7399 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7401 /* For instructions with VexNDS, the register-only source
7402 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7403 register. It is encoded in VEX prefix. */
7405 i386_operand_type op
;
7408 /* Check register-only source operand when two source
7409 operands are swapped. */
7410 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7411 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7419 op
= i
.tm
.operand_types
[vvvv
];
7420 if ((dest
+ 1) >= i
.operands
7421 || ((op
.bitfield
.class != Reg
7422 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7423 && op
.bitfield
.class != RegSIMD
7424 && !operand_type_equal (&op
, ®mask
)))
7426 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7432 /* One of the register operands will be encoded in the i.rm.reg
7433 field, the other in the combined i.rm.mode and i.rm.regmem
7434 fields. If no form of this instruction supports a memory
7435 destination operand, then we assume the source operand may
7436 sometimes be a memory operand and so we need to store the
7437 destination in the i.rm.reg field. */
7438 if (!i
.tm
.opcode_modifier
.regmem
7439 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7441 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7442 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7443 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7444 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7445 i
.has_regmmx
= TRUE
;
7446 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7447 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7449 if (i
.types
[dest
].bitfield
.zmmword
7450 || i
.types
[source
].bitfield
.zmmword
)
7451 i
.has_regzmm
= TRUE
;
7452 else if (i
.types
[dest
].bitfield
.ymmword
7453 || i
.types
[source
].bitfield
.ymmword
)
7454 i
.has_regymm
= TRUE
;
7456 i
.has_regxmm
= TRUE
;
7458 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7460 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7462 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7464 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7469 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7470 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7471 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7473 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7475 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7477 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7480 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7482 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7485 add_prefix (LOCK_PREFIX_OPCODE
);
7489 { /* If it's not 2 reg operands... */
7494 unsigned int fake_zero_displacement
= 0;
7497 for (op
= 0; op
< i
.operands
; op
++)
7498 if (i
.flags
[op
] & Operand_Mem
)
7500 gas_assert (op
< i
.operands
);
7502 if (i
.tm
.opcode_modifier
.vecsib
)
7504 if (i
.index_reg
->reg_num
== RegIZ
)
7507 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7510 i
.sib
.base
= NO_BASE_REGISTER
;
7511 i
.sib
.scale
= i
.log2_scale_factor
;
7512 i
.types
[op
].bitfield
.disp8
= 0;
7513 i
.types
[op
].bitfield
.disp16
= 0;
7514 i
.types
[op
].bitfield
.disp64
= 0;
7515 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7517 /* Must be 32 bit */
7518 i
.types
[op
].bitfield
.disp32
= 1;
7519 i
.types
[op
].bitfield
.disp32s
= 0;
7523 i
.types
[op
].bitfield
.disp32
= 0;
7524 i
.types
[op
].bitfield
.disp32s
= 1;
7527 i
.sib
.index
= i
.index_reg
->reg_num
;
7528 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7530 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7536 if (i
.base_reg
== 0)
7539 if (!i
.disp_operands
)
7540 fake_zero_displacement
= 1;
7541 if (i
.index_reg
== 0)
7543 i386_operand_type newdisp
;
7545 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7546 /* Operand is just <disp> */
7547 if (flag_code
== CODE_64BIT
)
7549 /* 64bit mode overwrites the 32bit absolute
7550 addressing by RIP relative addressing and
7551 absolute addressing is encoded by one of the
7552 redundant SIB forms. */
7553 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7554 i
.sib
.base
= NO_BASE_REGISTER
;
7555 i
.sib
.index
= NO_INDEX_REGISTER
;
7556 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7558 else if ((flag_code
== CODE_16BIT
)
7559 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7561 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7566 i
.rm
.regmem
= NO_BASE_REGISTER
;
7569 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7570 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7572 else if (!i
.tm
.opcode_modifier
.vecsib
)
7574 /* !i.base_reg && i.index_reg */
7575 if (i
.index_reg
->reg_num
== RegIZ
)
7576 i
.sib
.index
= NO_INDEX_REGISTER
;
7578 i
.sib
.index
= i
.index_reg
->reg_num
;
7579 i
.sib
.base
= NO_BASE_REGISTER
;
7580 i
.sib
.scale
= i
.log2_scale_factor
;
7581 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7582 i
.types
[op
].bitfield
.disp8
= 0;
7583 i
.types
[op
].bitfield
.disp16
= 0;
7584 i
.types
[op
].bitfield
.disp64
= 0;
7585 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7587 /* Must be 32 bit */
7588 i
.types
[op
].bitfield
.disp32
= 1;
7589 i
.types
[op
].bitfield
.disp32s
= 0;
7593 i
.types
[op
].bitfield
.disp32
= 0;
7594 i
.types
[op
].bitfield
.disp32s
= 1;
7596 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7600 /* RIP addressing for 64bit mode. */
7601 else if (i
.base_reg
->reg_num
== RegIP
)
7603 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7604 i
.rm
.regmem
= NO_BASE_REGISTER
;
7605 i
.types
[op
].bitfield
.disp8
= 0;
7606 i
.types
[op
].bitfield
.disp16
= 0;
7607 i
.types
[op
].bitfield
.disp32
= 0;
7608 i
.types
[op
].bitfield
.disp32s
= 1;
7609 i
.types
[op
].bitfield
.disp64
= 0;
7610 i
.flags
[op
] |= Operand_PCrel
;
7611 if (! i
.disp_operands
)
7612 fake_zero_displacement
= 1;
7614 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7616 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7617 switch (i
.base_reg
->reg_num
)
7620 if (i
.index_reg
== 0)
7622 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7623 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7627 if (i
.index_reg
== 0)
7630 if (operand_type_check (i
.types
[op
], disp
) == 0)
7632 /* fake (%bp) into 0(%bp) */
7633 i
.types
[op
].bitfield
.disp8
= 1;
7634 fake_zero_displacement
= 1;
7637 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7638 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7640 default: /* (%si) -> 4 or (%di) -> 5 */
7641 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7643 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7645 else /* i.base_reg and 32/64 bit mode */
7647 if (flag_code
== CODE_64BIT
7648 && operand_type_check (i
.types
[op
], disp
))
7650 i
.types
[op
].bitfield
.disp16
= 0;
7651 i
.types
[op
].bitfield
.disp64
= 0;
7652 if (i
.prefix
[ADDR_PREFIX
] == 0)
7654 i
.types
[op
].bitfield
.disp32
= 0;
7655 i
.types
[op
].bitfield
.disp32s
= 1;
7659 i
.types
[op
].bitfield
.disp32
= 1;
7660 i
.types
[op
].bitfield
.disp32s
= 0;
7664 if (!i
.tm
.opcode_modifier
.vecsib
)
7665 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7666 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7668 i
.sib
.base
= i
.base_reg
->reg_num
;
7669 /* x86-64 ignores REX prefix bit here to avoid decoder
7671 if (!(i
.base_reg
->reg_flags
& RegRex
)
7672 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7673 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7675 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7677 fake_zero_displacement
= 1;
7678 i
.types
[op
].bitfield
.disp8
= 1;
7680 i
.sib
.scale
= i
.log2_scale_factor
;
7681 if (i
.index_reg
== 0)
7683 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7684 /* <disp>(%esp) becomes two byte modrm with no index
7685 register. We've already stored the code for esp
7686 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7687 Any base register besides %esp will not use the
7688 extra modrm byte. */
7689 i
.sib
.index
= NO_INDEX_REGISTER
;
7691 else if (!i
.tm
.opcode_modifier
.vecsib
)
7693 if (i
.index_reg
->reg_num
== RegIZ
)
7694 i
.sib
.index
= NO_INDEX_REGISTER
;
7696 i
.sib
.index
= i
.index_reg
->reg_num
;
7697 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7698 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7703 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7704 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7708 if (!fake_zero_displacement
7712 fake_zero_displacement
= 1;
7713 if (i
.disp_encoding
== disp_encoding_8bit
)
7714 i
.types
[op
].bitfield
.disp8
= 1;
7716 i
.types
[op
].bitfield
.disp32
= 1;
7718 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7722 if (fake_zero_displacement
)
7724 /* Fakes a zero displacement assuming that i.types[op]
7725 holds the correct displacement size. */
7728 gas_assert (i
.op
[op
].disps
== 0);
7729 exp
= &disp_expressions
[i
.disp_operands
++];
7730 i
.op
[op
].disps
= exp
;
7731 exp
->X_op
= O_constant
;
7732 exp
->X_add_number
= 0;
7733 exp
->X_add_symbol
= (symbolS
*) 0;
7734 exp
->X_op_symbol
= (symbolS
*) 0;
7742 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7744 if (operand_type_check (i
.types
[0], imm
))
7745 i
.vex
.register_specifier
= NULL
;
7748 /* VEX.vvvv encodes one of the sources when the first
7749 operand is not an immediate. */
7750 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7751 i
.vex
.register_specifier
= i
.op
[0].regs
;
7753 i
.vex
.register_specifier
= i
.op
[1].regs
;
7756 /* Destination is a XMM register encoded in the ModRM.reg
7758 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7759 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7762 /* ModRM.rm and VEX.B encodes the other source. */
7763 if (!i
.mem_operands
)
7767 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7768 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7770 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7772 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7776 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7778 i
.vex
.register_specifier
= i
.op
[2].regs
;
7779 if (!i
.mem_operands
)
7782 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7783 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7787 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7788 (if any) based on i.tm.extension_opcode. Again, we must be
7789 careful to make sure that segment/control/debug/test/MMX
7790 registers are coded into the i.rm.reg field. */
7791 else if (i
.reg_operands
)
7794 unsigned int vex_reg
= ~0;
7796 for (op
= 0; op
< i
.operands
; op
++)
7798 if (i
.types
[op
].bitfield
.class == Reg
7799 || i
.types
[op
].bitfield
.class == RegBND
7800 || i
.types
[op
].bitfield
.class == RegMask
7801 || i
.types
[op
].bitfield
.class == SReg
7802 || i
.types
[op
].bitfield
.class == RegCR
7803 || i
.types
[op
].bitfield
.class == RegDR
7804 || i
.types
[op
].bitfield
.class == RegTR
)
7806 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7808 if (i
.types
[op
].bitfield
.zmmword
)
7809 i
.has_regzmm
= TRUE
;
7810 else if (i
.types
[op
].bitfield
.ymmword
)
7811 i
.has_regymm
= TRUE
;
7813 i
.has_regxmm
= TRUE
;
7816 if (i
.types
[op
].bitfield
.class == RegMMX
)
7818 i
.has_regmmx
= TRUE
;
7825 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7827 /* For instructions with VexNDS, the register-only
7828 source operand is encoded in VEX prefix. */
7829 gas_assert (mem
!= (unsigned int) ~0);
7834 gas_assert (op
< i
.operands
);
7838 /* Check register-only source operand when two source
7839 operands are swapped. */
7840 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7841 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7845 gas_assert (mem
== (vex_reg
+ 1)
7846 && op
< i
.operands
);
7851 gas_assert (vex_reg
< i
.operands
);
7855 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7857 /* For instructions with VexNDD, the register destination
7858 is encoded in VEX prefix. */
7859 if (i
.mem_operands
== 0)
7861 /* There is no memory operand. */
7862 gas_assert ((op
+ 2) == i
.operands
);
7867 /* There are only 2 non-immediate operands. */
7868 gas_assert (op
< i
.imm_operands
+ 2
7869 && i
.operands
== i
.imm_operands
+ 2);
7870 vex_reg
= i
.imm_operands
+ 1;
7874 gas_assert (op
< i
.operands
);
7876 if (vex_reg
!= (unsigned int) ~0)
7878 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7880 if ((type
->bitfield
.class != Reg
7881 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7882 && type
->bitfield
.class != RegSIMD
7883 && !operand_type_equal (type
, ®mask
))
7886 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7889 /* Don't set OP operand twice. */
7892 /* If there is an extension opcode to put here, the
7893 register number must be put into the regmem field. */
7894 if (i
.tm
.extension_opcode
!= None
)
7896 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7897 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7899 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7904 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7905 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7907 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7912 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7913 must set it to 3 to indicate this is a register operand
7914 in the regmem field. */
7915 if (!i
.mem_operands
)
7919 /* Fill in i.rm.reg field with extension opcode (if any). */
7920 if (i
.tm
.extension_opcode
!= None
)
7921 i
.rm
.reg
= i
.tm
.extension_opcode
;
7927 flip_code16 (unsigned int code16
)
7929 gas_assert (i
.tm
.operands
== 1);
7931 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7932 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7933 || i
.tm
.operand_types
[0].bitfield
.disp32s
7934 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7939 output_branch (void)
7945 relax_substateT subtype
;
7949 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7950 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7953 if (i
.prefix
[DATA_PREFIX
] != 0)
7957 code16
^= flip_code16(code16
);
7959 /* Pentium4 branch hints. */
7960 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7961 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7966 if (i
.prefix
[REX_PREFIX
] != 0)
7972 /* BND prefixed jump. */
7973 if (i
.prefix
[BND_PREFIX
] != 0)
7979 if (i
.prefixes
!= 0)
7980 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
7982 /* It's always a symbol; End frag & setup for relax.
7983 Make sure there is enough room in this frag for the largest
7984 instruction we may generate in md_convert_frag. This is 2
7985 bytes for the opcode and room for the prefix and largest
7987 frag_grow (prefix
+ 2 + 4);
7988 /* Prefix and 1 opcode byte go in fr_fix. */
7989 p
= frag_more (prefix
+ 1);
7990 if (i
.prefix
[DATA_PREFIX
] != 0)
7991 *p
++ = DATA_PREFIX_OPCODE
;
7992 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7993 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7994 *p
++ = i
.prefix
[SEG_PREFIX
];
7995 if (i
.prefix
[BND_PREFIX
] != 0)
7996 *p
++ = BND_PREFIX_OPCODE
;
7997 if (i
.prefix
[REX_PREFIX
] != 0)
7998 *p
++ = i
.prefix
[REX_PREFIX
];
7999 *p
= i
.tm
.base_opcode
;
8001 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
8002 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
8003 else if (cpu_arch_flags
.bitfield
.cpui386
)
8004 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
8006 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
8009 sym
= i
.op
[0].disps
->X_add_symbol
;
8010 off
= i
.op
[0].disps
->X_add_number
;
8012 if (i
.op
[0].disps
->X_op
!= O_constant
8013 && i
.op
[0].disps
->X_op
!= O_symbol
)
8015 /* Handle complex expressions. */
8016 sym
= make_expr_symbol (i
.op
[0].disps
);
8020 /* 1 possible extra opcode + 4 byte displacement go in var part.
8021 Pass reloc in fr_var. */
8022 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
8025 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8026 /* Return TRUE iff PLT32 relocation should be used for branching to
8030 need_plt32_p (symbolS
*s
)
8032 /* PLT32 relocation is ELF only. */
8037 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8038 krtld support it. */
8042 /* Since there is no need to prepare for PLT branch on x86-64, we
8043 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8044 be used as a marker for 32-bit PC-relative branches. */
8048 /* Weak or undefined symbol need PLT32 relocation. */
8049 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
8052 /* Non-global symbol doesn't need PLT32 relocation. */
8053 if (! S_IS_EXTERNAL (s
))
8056 /* Other global symbols need PLT32 relocation. NB: Symbol with
8057 non-default visibilities are treated as normal global symbol
8058 so that PLT32 relocation can be used as a marker for 32-bit
8059 PC-relative branches. It is useful for linker relaxation. */
8070 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8072 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8074 /* This is a loop or jecxz type instruction. */
8076 if (i
.prefix
[ADDR_PREFIX
] != 0)
8078 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8081 /* Pentium4 branch hints. */
8082 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8083 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8085 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8094 if (flag_code
== CODE_16BIT
)
8097 if (i
.prefix
[DATA_PREFIX
] != 0)
8099 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8101 code16
^= flip_code16(code16
);
8109 /* BND prefixed jump. */
8110 if (i
.prefix
[BND_PREFIX
] != 0)
8112 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8116 if (i
.prefix
[REX_PREFIX
] != 0)
8118 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8122 if (i
.prefixes
!= 0)
8123 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8125 p
= frag_more (i
.tm
.opcode_length
+ size
);
8126 switch (i
.tm
.opcode_length
)
8129 *p
++ = i
.tm
.base_opcode
>> 8;
8132 *p
++ = i
.tm
.base_opcode
;
8138 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8140 && jump_reloc
== NO_RELOC
8141 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8142 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8145 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8147 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8148 i
.op
[0].disps
, 1, jump_reloc
);
8150 /* All jumps handled here are signed, but don't use a signed limit
8151 check for 32 and 16 bit jumps as we want to allow wrap around at
8152 4G and 64k respectively. */
8154 fixP
->fx_signed
= 1;
8158 output_interseg_jump (void)
8166 if (flag_code
== CODE_16BIT
)
8170 if (i
.prefix
[DATA_PREFIX
] != 0)
8177 gas_assert (!i
.prefix
[REX_PREFIX
]);
8183 if (i
.prefixes
!= 0)
8184 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8186 /* 1 opcode; 2 segment; offset */
8187 p
= frag_more (prefix
+ 1 + 2 + size
);
8189 if (i
.prefix
[DATA_PREFIX
] != 0)
8190 *p
++ = DATA_PREFIX_OPCODE
;
8192 if (i
.prefix
[REX_PREFIX
] != 0)
8193 *p
++ = i
.prefix
[REX_PREFIX
];
8195 *p
++ = i
.tm
.base_opcode
;
8196 if (i
.op
[1].imms
->X_op
== O_constant
)
8198 offsetT n
= i
.op
[1].imms
->X_add_number
;
8201 && !fits_in_unsigned_word (n
)
8202 && !fits_in_signed_word (n
))
8204 as_bad (_("16-bit jump out of range"));
8207 md_number_to_chars (p
, n
, size
);
8210 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8211 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8212 if (i
.op
[0].imms
->X_op
!= O_constant
)
8213 as_bad (_("can't handle non absolute segment in `%s'"),
8215 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8223 asection
*seg
= now_seg
;
8224 subsegT subseg
= now_subseg
;
8226 unsigned int alignment
, align_size_1
;
8227 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8228 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8229 unsigned int padding
;
8231 if (!IS_ELF
|| !x86_used_note
)
8234 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8236 /* The .note.gnu.property section layout:
8238 Field Length Contents
8241 n_descsz 4 The note descriptor size
8242 n_type 4 NT_GNU_PROPERTY_TYPE_0
8244 n_desc n_descsz The program property array
8248 /* Create the .note.gnu.property section. */
8249 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8250 bfd_set_section_flags (sec
,
8257 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8268 bfd_set_section_alignment (sec
, alignment
);
8269 elf_section_type (sec
) = SHT_NOTE
;
8271 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8273 isa_1_descsz_raw
= 4 + 4 + 4;
8274 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8275 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8277 feature_2_descsz_raw
= isa_1_descsz
;
8278 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8280 feature_2_descsz_raw
+= 4 + 4 + 4;
8281 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8282 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8285 descsz
= feature_2_descsz
;
8286 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8287 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8289 /* Write n_namsz. */
8290 md_number_to_chars (p
, (valueT
) 4, 4);
8292 /* Write n_descsz. */
8293 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8296 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8299 memcpy (p
+ 4 * 3, "GNU", 4);
8301 /* Write 4-byte type. */
8302 md_number_to_chars (p
+ 4 * 4,
8303 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8305 /* Write 4-byte data size. */
8306 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8308 /* Write 4-byte data. */
8309 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8311 /* Zero out paddings. */
8312 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8314 memset (p
+ 4 * 7, 0, padding
);
8316 /* Write 4-byte type. */
8317 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8318 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8320 /* Write 4-byte data size. */
8321 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8323 /* Write 4-byte data. */
8324 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8325 (valueT
) x86_feature_2_used
, 4);
8327 /* Zero out paddings. */
8328 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8330 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8332 /* We probably can't restore the current segment, for there likely
8335 subseg_set (seg
, subseg
);
8340 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8341 const char *frag_now_ptr
)
8343 unsigned int len
= 0;
8345 if (start_frag
!= frag_now
)
8347 const fragS
*fr
= start_frag
;
8352 } while (fr
&& fr
!= frag_now
);
8355 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8358 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8359 be macro-fused with conditional jumps. */
8362 maybe_fused_with_jcc_p (void)
8364 /* No RIP address. */
8365 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8368 /* No VEX/EVEX encoding. */
8369 if (is_any_vex_encoding (&i
.tm
))
8372 /* and, add, sub with destination register. */
8373 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8374 || i
.tm
.base_opcode
<= 5
8375 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8376 || ((i
.tm
.base_opcode
| 3) == 0x83
8377 && ((i
.tm
.extension_opcode
| 1) == 0x5
8378 || i
.tm
.extension_opcode
== 0x0)))
8379 return (i
.types
[1].bitfield
.class == Reg
8380 || i
.types
[1].bitfield
.instance
== Accum
);
8382 /* test, cmp with any register. */
8383 if ((i
.tm
.base_opcode
| 1) == 0x85
8384 || (i
.tm
.base_opcode
| 1) == 0xa9
8385 || ((i
.tm
.base_opcode
| 1) == 0xf7
8386 && i
.tm
.extension_opcode
== 0)
8387 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8388 || ((i
.tm
.base_opcode
| 3) == 0x83
8389 && (i
.tm
.extension_opcode
== 0x7)))
8390 return (i
.types
[0].bitfield
.class == Reg
8391 || i
.types
[0].bitfield
.instance
== Accum
8392 || i
.types
[1].bitfield
.class == Reg
8393 || i
.types
[1].bitfield
.instance
== Accum
);
8395 /* inc, dec with any register. */
8396 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8397 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8398 || ((i
.tm
.base_opcode
| 1) == 0xff
8399 && i
.tm
.extension_opcode
<= 0x1))
8400 return (i
.types
[0].bitfield
.class == Reg
8401 || i
.types
[0].bitfield
.instance
== Accum
);
8406 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8409 add_fused_jcc_padding_frag_p (void)
8411 /* NB: Don't work with COND_JUMP86 without i386. */
8412 if (!align_branch_power
8413 || now_seg
== absolute_section
8414 || !cpu_arch_flags
.bitfield
.cpui386
8415 || !(align_branch
& align_branch_fused_bit
))
8418 if (maybe_fused_with_jcc_p ())
8420 if (last_insn
.kind
== last_insn_other
8421 || last_insn
.seg
!= now_seg
)
8424 as_warn_where (last_insn
.file
, last_insn
.line
,
8425 _("`%s` skips -malign-branch-boundary on `%s`"),
8426 last_insn
.name
, i
.tm
.name
);
8432 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8435 add_branch_prefix_frag_p (void)
8437 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8438 to PadLock instructions since they include prefixes in opcode. */
8439 if (!align_branch_power
8440 || !align_branch_prefix_size
8441 || now_seg
== absolute_section
8442 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8443 || !cpu_arch_flags
.bitfield
.cpui386
)
8446 /* Don't add prefix if it is a prefix or there is no operand in case
8447 that segment prefix is special. */
8448 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8451 if (last_insn
.kind
== last_insn_other
8452 || last_insn
.seg
!= now_seg
)
8456 as_warn_where (last_insn
.file
, last_insn
.line
,
8457 _("`%s` skips -malign-branch-boundary on `%s`"),
8458 last_insn
.name
, i
.tm
.name
);
8463 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8466 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8470 /* NB: Don't work with COND_JUMP86 without i386. */
8471 if (!align_branch_power
8472 || now_seg
== absolute_section
8473 || !cpu_arch_flags
.bitfield
.cpui386
)
8478 /* Check for jcc and direct jmp. */
8479 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8481 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8483 *branch_p
= align_branch_jmp
;
8484 add_padding
= align_branch
& align_branch_jmp_bit
;
8488 *branch_p
= align_branch_jcc
;
8489 if ((align_branch
& align_branch_jcc_bit
))
8493 else if (is_any_vex_encoding (&i
.tm
))
8495 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8498 *branch_p
= align_branch_ret
;
8499 if ((align_branch
& align_branch_ret_bit
))
8504 /* Check for indirect jmp, direct and indirect calls. */
8505 if (i
.tm
.base_opcode
== 0xe8)
8508 *branch_p
= align_branch_call
;
8509 if ((align_branch
& align_branch_call_bit
))
8512 else if (i
.tm
.base_opcode
== 0xff
8513 && (i
.tm
.extension_opcode
== 2
8514 || i
.tm
.extension_opcode
== 4))
8516 /* Indirect call and jmp. */
8517 *branch_p
= align_branch_indirect
;
8518 if ((align_branch
& align_branch_indirect_bit
))
8525 && (i
.op
[0].disps
->X_op
== O_symbol
8526 || (i
.op
[0].disps
->X_op
== O_subtract
8527 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8529 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8530 /* No padding to call to global or undefined tls_get_addr. */
8531 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8532 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8538 && last_insn
.kind
!= last_insn_other
8539 && last_insn
.seg
== now_seg
)
8542 as_warn_where (last_insn
.file
, last_insn
.line
,
8543 _("`%s` skips -malign-branch-boundary on `%s`"),
8544 last_insn
.name
, i
.tm
.name
);
8554 fragS
*insn_start_frag
;
8555 offsetT insn_start_off
;
8556 fragS
*fragP
= NULL
;
8557 enum align_branch_kind branch
= align_branch_none
;
8559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8560 if (IS_ELF
&& x86_used_note
)
8562 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8563 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8564 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8565 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8566 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8567 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8568 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8569 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8570 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8571 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8572 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8573 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8574 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8575 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8576 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8577 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8578 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8579 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8580 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8581 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8582 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8583 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8584 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8585 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8586 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8587 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8588 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8589 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8590 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8591 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8592 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8593 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8594 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8595 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8596 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8597 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8598 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8599 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8600 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8601 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8602 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8603 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8604 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8605 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8606 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8607 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8608 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8609 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8610 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8611 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8613 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8614 || i
.tm
.cpu_flags
.bitfield
.cpu287
8615 || i
.tm
.cpu_flags
.bitfield
.cpu387
8616 || i
.tm
.cpu_flags
.bitfield
.cpu687
8617 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8618 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8620 || i
.tm
.base_opcode
== 0xf77 /* emms */
8621 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8622 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8624 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8626 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8628 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8629 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8630 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8631 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8632 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8633 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8634 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8635 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8636 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8640 /* Tie dwarf2 debug info to the address at the start of the insn.
8641 We can't do this after the insn has been output as the current
8642 frag may have been closed off. eg. by frag_var. */
8643 dwarf2_emit_insn (0);
8645 insn_start_frag
= frag_now
;
8646 insn_start_off
= frag_now_fix ();
8648 if (add_branch_padding_frag_p (&branch
))
8651 /* Branch can be 8 bytes. Leave some room for prefixes. */
8652 unsigned int max_branch_padding_size
= 14;
8654 /* Align section to boundary. */
8655 record_alignment (now_seg
, align_branch_power
);
8657 /* Make room for padding. */
8658 frag_grow (max_branch_padding_size
);
8660 /* Start of the padding. */
8665 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8666 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8669 fragP
->tc_frag_data
.branch_type
= branch
;
8670 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8674 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8676 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8677 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8679 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8680 output_interseg_jump ();
8683 /* Output normal instructions here. */
8687 unsigned int prefix
;
8690 && (i
.tm
.base_opcode
== 0xfaee8
8691 || i
.tm
.base_opcode
== 0xfaef0
8692 || i
.tm
.base_opcode
== 0xfaef8))
8694 /* Encode lfence, mfence, and sfence as
8695 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8696 offsetT val
= 0x240483f0ULL
;
8698 md_number_to_chars (p
, val
, 5);
8702 /* Some processors fail on LOCK prefix. This options makes
8703 assembler ignore LOCK prefix and serves as a workaround. */
8704 if (omit_lock_prefix
)
8706 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8708 i
.prefix
[LOCK_PREFIX
] = 0;
8712 /* Skip if this is a branch. */
8714 else if (add_fused_jcc_padding_frag_p ())
8716 /* Make room for padding. */
8717 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8722 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8723 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8726 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8727 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8729 else if (add_branch_prefix_frag_p ())
8731 unsigned int max_prefix_size
= align_branch_prefix_size
;
8733 /* Make room for padding. */
8734 frag_grow (max_prefix_size
);
8739 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8740 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8743 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8746 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8747 don't need the explicit prefix. */
8748 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8750 switch (i
.tm
.opcode_length
)
8753 if (i
.tm
.base_opcode
& 0xff000000)
8755 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8756 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8757 || prefix
!= REPE_PREFIX_OPCODE
8758 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8759 add_prefix (prefix
);
8763 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8765 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8766 add_prefix (prefix
);
8772 /* Check for pseudo prefixes. */
8773 as_bad_where (insn_start_frag
->fr_file
,
8774 insn_start_frag
->fr_line
,
8775 _("pseudo prefix without instruction"));
8781 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8782 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8783 R_X86_64_GOTTPOFF relocation so that linker can safely
8784 perform IE->LE optimization. A dummy REX_OPCODE prefix
8785 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
8786 relocation for GDesc -> IE/LE optimization. */
8787 if (x86_elf_abi
== X86_64_X32_ABI
8789 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8790 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
8791 && i
.prefix
[REX_PREFIX
] == 0)
8792 add_prefix (REX_OPCODE
);
8795 /* The prefix bytes. */
8796 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8798 FRAG_APPEND_1_CHAR (*q
);
8802 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8807 /* REX byte is encoded in VEX prefix. */
8811 FRAG_APPEND_1_CHAR (*q
);
8814 /* There should be no other prefixes for instructions
8819 /* For EVEX instructions i.vrex should become 0 after
8820 build_evex_prefix. For VEX instructions upper 16 registers
8821 aren't available, so VREX should be 0. */
8824 /* Now the VEX prefix. */
8825 p
= frag_more (i
.vex
.length
);
8826 for (j
= 0; j
< i
.vex
.length
; j
++)
8827 p
[j
] = i
.vex
.bytes
[j
];
8830 /* Now the opcode; be careful about word order here! */
8831 if (i
.tm
.opcode_length
== 1)
8833 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8837 switch (i
.tm
.opcode_length
)
8841 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8842 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8846 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8856 /* Put out high byte first: can't use md_number_to_chars! */
8857 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8858 *p
= i
.tm
.base_opcode
& 0xff;
8861 /* Now the modrm byte and sib byte (if present). */
8862 if (i
.tm
.opcode_modifier
.modrm
)
8864 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8867 /* If i.rm.regmem == ESP (4)
8868 && i.rm.mode != (Register mode)
8870 ==> need second modrm byte. */
8871 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8873 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8874 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8876 | i
.sib
.scale
<< 6));
8879 if (i
.disp_operands
)
8880 output_disp (insn_start_frag
, insn_start_off
);
8883 output_imm (insn_start_frag
, insn_start_off
);
8886 * frag_now_fix () returning plain abs_section_offset when we're in the
8887 * absolute section, and abs_section_offset not getting updated as data
8888 * gets added to the frag breaks the logic below.
8890 if (now_seg
!= absolute_section
)
8892 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8894 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8898 /* NB: Don't add prefix with GOTPC relocation since
8899 output_disp() above depends on the fixed encoding
8900 length. Can't add prefix with TLS relocation since
8901 it breaks TLS linker optimization. */
8902 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8903 /* Prefix count on the current instruction. */
8904 unsigned int count
= i
.vex
.length
;
8906 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8907 /* REX byte is encoded in VEX/EVEX prefix. */
8908 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8911 /* Count prefixes for extended opcode maps. */
8913 switch (i
.tm
.opcode_length
)
8916 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8919 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8931 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8940 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8943 /* Set the maximum prefix size in BRANCH_PREFIX
8945 if (fragP
->tc_frag_data
.max_bytes
> max
)
8946 fragP
->tc_frag_data
.max_bytes
= max
;
8947 if (fragP
->tc_frag_data
.max_bytes
> count
)
8948 fragP
->tc_frag_data
.max_bytes
-= count
;
8950 fragP
->tc_frag_data
.max_bytes
= 0;
8954 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8956 unsigned int max_prefix_size
;
8957 if (align_branch_prefix_size
> max
)
8958 max_prefix_size
= max
;
8960 max_prefix_size
= align_branch_prefix_size
;
8961 if (max_prefix_size
> count
)
8962 fragP
->tc_frag_data
.max_prefix_length
8963 = max_prefix_size
- count
;
8966 /* Use existing segment prefix if possible. Use CS
8967 segment prefix in 64-bit mode. In 32-bit mode, use SS
8968 segment prefix with ESP/EBP base register and use DS
8969 segment prefix without ESP/EBP base register. */
8970 if (i
.prefix
[SEG_PREFIX
])
8971 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8972 else if (flag_code
== CODE_64BIT
)
8973 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8975 && (i
.base_reg
->reg_num
== 4
8976 || i
.base_reg
->reg_num
== 5))
8977 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8979 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8984 /* NB: Don't work with COND_JUMP86 without i386. */
8985 if (align_branch_power
8986 && now_seg
!= absolute_section
8987 && cpu_arch_flags
.bitfield
.cpui386
)
8989 /* Terminate each frag so that we can add prefix and check for
8991 frag_wane (frag_now
);
8998 pi ("" /*line*/, &i
);
9000 #endif /* DEBUG386 */
9003 /* Return the size of the displacement operand N. */
9006 disp_size (unsigned int n
)
9010 if (i
.types
[n
].bitfield
.disp64
)
9012 else if (i
.types
[n
].bitfield
.disp8
)
9014 else if (i
.types
[n
].bitfield
.disp16
)
9019 /* Return the size of the immediate operand N. */
9022 imm_size (unsigned int n
)
9025 if (i
.types
[n
].bitfield
.imm64
)
9027 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
9029 else if (i
.types
[n
].bitfield
.imm16
)
9035 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
9040 for (n
= 0; n
< i
.operands
; n
++)
9042 if (operand_type_check (i
.types
[n
], disp
))
9044 if (i
.op
[n
].disps
->X_op
== O_constant
)
9046 int size
= disp_size (n
);
9047 offsetT val
= i
.op
[n
].disps
->X_add_number
;
9049 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
9051 p
= frag_more (size
);
9052 md_number_to_chars (p
, val
, size
);
9056 enum bfd_reloc_code_real reloc_type
;
9057 int size
= disp_size (n
);
9058 int sign
= i
.types
[n
].bitfield
.disp32s
;
9059 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
9062 /* We can't have 8 bit displacement here. */
9063 gas_assert (!i
.types
[n
].bitfield
.disp8
);
9065 /* The PC relative address is computed relative
9066 to the instruction boundary, so in case immediate
9067 fields follows, we need to adjust the value. */
9068 if (pcrel
&& i
.imm_operands
)
9073 for (n1
= 0; n1
< i
.operands
; n1
++)
9074 if (operand_type_check (i
.types
[n1
], imm
))
9076 /* Only one immediate is allowed for PC
9077 relative address. */
9078 gas_assert (sz
== 0);
9080 i
.op
[n
].disps
->X_add_number
-= sz
;
9082 /* We should find the immediate. */
9083 gas_assert (sz
!= 0);
9086 p
= frag_more (size
);
9087 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9089 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9090 && (((reloc_type
== BFD_RELOC_32
9091 || reloc_type
== BFD_RELOC_X86_64_32S
9092 || (reloc_type
== BFD_RELOC_64
9094 && (i
.op
[n
].disps
->X_op
== O_symbol
9095 || (i
.op
[n
].disps
->X_op
== O_add
9096 && ((symbol_get_value_expression
9097 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9099 || reloc_type
== BFD_RELOC_32_PCREL
))
9103 reloc_type
= BFD_RELOC_386_GOTPC
;
9104 i
.has_gotpc_tls_reloc
= TRUE
;
9105 i
.op
[n
].imms
->X_add_number
+=
9106 encoding_length (insn_start_frag
, insn_start_off
, p
);
9108 else if (reloc_type
== BFD_RELOC_64
)
9109 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9111 /* Don't do the adjustment for x86-64, as there
9112 the pcrel addressing is relative to the _next_
9113 insn, and that is taken care of in other code. */
9114 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9116 else if (align_branch_power
)
9120 case BFD_RELOC_386_TLS_GD
:
9121 case BFD_RELOC_386_TLS_LDM
:
9122 case BFD_RELOC_386_TLS_IE
:
9123 case BFD_RELOC_386_TLS_IE_32
:
9124 case BFD_RELOC_386_TLS_GOTIE
:
9125 case BFD_RELOC_386_TLS_GOTDESC
:
9126 case BFD_RELOC_386_TLS_DESC_CALL
:
9127 case BFD_RELOC_X86_64_TLSGD
:
9128 case BFD_RELOC_X86_64_TLSLD
:
9129 case BFD_RELOC_X86_64_GOTTPOFF
:
9130 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9131 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9132 i
.has_gotpc_tls_reloc
= TRUE
;
9137 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9138 size
, i
.op
[n
].disps
, pcrel
,
9140 /* Check for "call/jmp *mem", "mov mem, %reg",
9141 "test %reg, mem" and "binop mem, %reg" where binop
9142 is one of adc, add, and, cmp, or, sbb, sub, xor
9143 instructions without data prefix. Always generate
9144 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9145 if (i
.prefix
[DATA_PREFIX
] == 0
9146 && (generate_relax_relocations
9149 && i
.rm
.regmem
== 5))
9151 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9152 && !is_any_vex_encoding(&i
.tm
)
9153 && ((i
.operands
== 1
9154 && i
.tm
.base_opcode
== 0xff
9155 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9157 && (i
.tm
.base_opcode
== 0x8b
9158 || i
.tm
.base_opcode
== 0x85
9159 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
9163 fixP
->fx_tcbit
= i
.rex
!= 0;
9165 && (i
.base_reg
->reg_num
== RegIP
))
9166 fixP
->fx_tcbit2
= 1;
9169 fixP
->fx_tcbit2
= 1;
9177 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9182 for (n
= 0; n
< i
.operands
; n
++)
9184 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9185 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9188 if (operand_type_check (i
.types
[n
], imm
))
9190 if (i
.op
[n
].imms
->X_op
== O_constant
)
9192 int size
= imm_size (n
);
9195 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9197 p
= frag_more (size
);
9198 md_number_to_chars (p
, val
, size
);
9202 /* Not absolute_section.
9203 Need a 32-bit fixup (don't support 8bit
9204 non-absolute imms). Try to support other
9206 enum bfd_reloc_code_real reloc_type
;
9207 int size
= imm_size (n
);
9210 if (i
.types
[n
].bitfield
.imm32s
9211 && (i
.suffix
== QWORD_MNEM_SUFFIX
9212 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9217 p
= frag_more (size
);
9218 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9220 /* This is tough to explain. We end up with this one if we
9221 * have operands that look like
9222 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9223 * obtain the absolute address of the GOT, and it is strongly
9224 * preferable from a performance point of view to avoid using
9225 * a runtime relocation for this. The actual sequence of
9226 * instructions often look something like:
9231 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9233 * The call and pop essentially return the absolute address
9234 * of the label .L66 and store it in %ebx. The linker itself
9235 * will ultimately change the first operand of the addl so
9236 * that %ebx points to the GOT, but to keep things simple, the
9237 * .o file must have this operand set so that it generates not
9238 * the absolute address of .L66, but the absolute address of
9239 * itself. This allows the linker itself simply treat a GOTPC
9240 * relocation as asking for a pcrel offset to the GOT to be
9241 * added in, and the addend of the relocation is stored in the
9242 * operand field for the instruction itself.
9244 * Our job here is to fix the operand so that it would add
9245 * the correct offset so that %ebx would point to itself. The
9246 * thing that is tricky is that .-.L66 will point to the
9247 * beginning of the instruction, so we need to further modify
9248 * the operand so that it will point to itself. There are
9249 * other cases where you have something like:
9251 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9253 * and here no correction would be required. Internally in
9254 * the assembler we treat operands of this form as not being
9255 * pcrel since the '.' is explicitly mentioned, and I wonder
9256 * whether it would simplify matters to do it this way. Who
9257 * knows. In earlier versions of the PIC patches, the
9258 * pcrel_adjust field was used to store the correction, but
9259 * since the expression is not pcrel, I felt it would be
9260 * confusing to do it this way. */
9262 if ((reloc_type
== BFD_RELOC_32
9263 || reloc_type
== BFD_RELOC_X86_64_32S
9264 || reloc_type
== BFD_RELOC_64
)
9266 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9267 && (i
.op
[n
].imms
->X_op
== O_symbol
9268 || (i
.op
[n
].imms
->X_op
== O_add
9269 && ((symbol_get_value_expression
9270 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9274 reloc_type
= BFD_RELOC_386_GOTPC
;
9276 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9278 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9279 i
.has_gotpc_tls_reloc
= TRUE
;
9280 i
.op
[n
].imms
->X_add_number
+=
9281 encoding_length (insn_start_frag
, insn_start_off
, p
);
9283 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9284 i
.op
[n
].imms
, 0, reloc_type
);
9290 /* x86_cons_fix_new is called via the expression parsing code when a
9291 reloc is needed. We use this hook to get the correct .got reloc. */
9292 static int cons_sign
= -1;
9295 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9296 expressionS
*exp
, bfd_reloc_code_real_type r
)
9298 r
= reloc (len
, 0, cons_sign
, r
);
9301 if (exp
->X_op
== O_secrel
)
9303 exp
->X_op
= O_symbol
;
9304 r
= BFD_RELOC_32_SECREL
;
9308 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9311 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9312 purpose of the `.dc.a' internal pseudo-op. */
9315 x86_address_bytes (void)
9317 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9319 return stdoutput
->arch_info
->bits_per_address
/ 8;
9322 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9324 # define lex_got(reloc, adjust, types) NULL
9326 /* Parse operands of the form
9327 <symbol>@GOTOFF+<nnn>
9328 and similar .plt or .got references.
9330 If we find one, set up the correct relocation in RELOC and copy the
9331 input string, minus the `@GOTOFF' into a malloc'd buffer for
9332 parsing by the calling routine. Return this buffer, and if ADJUST
9333 is non-null set it to the length of the string we removed from the
9334 input line. Otherwise return NULL. */
9336 lex_got (enum bfd_reloc_code_real
*rel
,
9338 i386_operand_type
*types
)
9340 /* Some of the relocations depend on the size of what field is to
9341 be relocated. But in our callers i386_immediate and i386_displacement
9342 we don't yet know the operand size (this will be set by insn
9343 matching). Hence we record the word32 relocation here,
9344 and adjust the reloc according to the real size in reloc(). */
9345 static const struct {
9348 const enum bfd_reloc_code_real rel
[2];
9349 const i386_operand_type types64
;
9351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9352 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9354 OPERAND_TYPE_IMM32_64
},
9356 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9357 BFD_RELOC_X86_64_PLTOFF64
},
9358 OPERAND_TYPE_IMM64
},
9359 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9360 BFD_RELOC_X86_64_PLT32
},
9361 OPERAND_TYPE_IMM32_32S_DISP32
},
9362 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9363 BFD_RELOC_X86_64_GOTPLT64
},
9364 OPERAND_TYPE_IMM64_DISP64
},
9365 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9366 BFD_RELOC_X86_64_GOTOFF64
},
9367 OPERAND_TYPE_IMM64_DISP64
},
9368 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9369 BFD_RELOC_X86_64_GOTPCREL
},
9370 OPERAND_TYPE_IMM32_32S_DISP32
},
9371 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9372 BFD_RELOC_X86_64_TLSGD
},
9373 OPERAND_TYPE_IMM32_32S_DISP32
},
9374 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9375 _dummy_first_bfd_reloc_code_real
},
9376 OPERAND_TYPE_NONE
},
9377 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9378 BFD_RELOC_X86_64_TLSLD
},
9379 OPERAND_TYPE_IMM32_32S_DISP32
},
9380 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9381 BFD_RELOC_X86_64_GOTTPOFF
},
9382 OPERAND_TYPE_IMM32_32S_DISP32
},
9383 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9384 BFD_RELOC_X86_64_TPOFF32
},
9385 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9386 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9387 _dummy_first_bfd_reloc_code_real
},
9388 OPERAND_TYPE_NONE
},
9389 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9390 BFD_RELOC_X86_64_DTPOFF32
},
9391 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9392 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9393 _dummy_first_bfd_reloc_code_real
},
9394 OPERAND_TYPE_NONE
},
9395 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9396 _dummy_first_bfd_reloc_code_real
},
9397 OPERAND_TYPE_NONE
},
9398 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9399 BFD_RELOC_X86_64_GOT32
},
9400 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9401 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9402 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9403 OPERAND_TYPE_IMM32_32S_DISP32
},
9404 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9405 BFD_RELOC_X86_64_TLSDESC_CALL
},
9406 OPERAND_TYPE_IMM32_32S_DISP32
},
9411 #if defined (OBJ_MAYBE_ELF)
9416 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9417 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9420 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9422 int len
= gotrel
[j
].len
;
9423 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9425 if (gotrel
[j
].rel
[object_64bit
] != 0)
9428 char *tmpbuf
, *past_reloc
;
9430 *rel
= gotrel
[j
].rel
[object_64bit
];
9434 if (flag_code
!= CODE_64BIT
)
9436 types
->bitfield
.imm32
= 1;
9437 types
->bitfield
.disp32
= 1;
9440 *types
= gotrel
[j
].types64
;
9443 if (j
!= 0 && GOT_symbol
== NULL
)
9444 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9446 /* The length of the first part of our input line. */
9447 first
= cp
- input_line_pointer
;
9449 /* The second part goes from after the reloc token until
9450 (and including) an end_of_line char or comma. */
9451 past_reloc
= cp
+ 1 + len
;
9453 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9455 second
= cp
+ 1 - past_reloc
;
9457 /* Allocate and copy string. The trailing NUL shouldn't
9458 be necessary, but be safe. */
9459 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9460 memcpy (tmpbuf
, input_line_pointer
, first
);
9461 if (second
!= 0 && *past_reloc
!= ' ')
9462 /* Replace the relocation token with ' ', so that
9463 errors like foo@GOTOFF1 will be detected. */
9464 tmpbuf
[first
++] = ' ';
9466 /* Increment length by 1 if the relocation token is
9471 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9472 tmpbuf
[first
+ second
] = '\0';
9476 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9477 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9482 /* Might be a symbol version string. Don't as_bad here. */
9491 /* Parse operands of the form
9492 <symbol>@SECREL32+<nnn>
9494 If we find one, set up the correct relocation in RELOC and copy the
9495 input string, minus the `@SECREL32' into a malloc'd buffer for
9496 parsing by the calling routine. Return this buffer, and if ADJUST
9497 is non-null set it to the length of the string we removed from the
9498 input line. Otherwise return NULL.
9500 This function is copied from the ELF version above adjusted for PE targets. */
9503 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9504 int *adjust ATTRIBUTE_UNUSED
,
9505 i386_operand_type
*types
)
9511 const enum bfd_reloc_code_real rel
[2];
9512 const i386_operand_type types64
;
9516 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9517 BFD_RELOC_32_SECREL
},
9518 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9524 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9525 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9528 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9530 int len
= gotrel
[j
].len
;
9532 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9534 if (gotrel
[j
].rel
[object_64bit
] != 0)
9537 char *tmpbuf
, *past_reloc
;
9539 *rel
= gotrel
[j
].rel
[object_64bit
];
9545 if (flag_code
!= CODE_64BIT
)
9547 types
->bitfield
.imm32
= 1;
9548 types
->bitfield
.disp32
= 1;
9551 *types
= gotrel
[j
].types64
;
9554 /* The length of the first part of our input line. */
9555 first
= cp
- input_line_pointer
;
9557 /* The second part goes from after the reloc token until
9558 (and including) an end_of_line char or comma. */
9559 past_reloc
= cp
+ 1 + len
;
9561 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9563 second
= cp
+ 1 - past_reloc
;
9565 /* Allocate and copy string. The trailing NUL shouldn't
9566 be necessary, but be safe. */
9567 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9568 memcpy (tmpbuf
, input_line_pointer
, first
);
9569 if (second
!= 0 && *past_reloc
!= ' ')
9570 /* Replace the relocation token with ' ', so that
9571 errors like foo@SECLREL321 will be detected. */
9572 tmpbuf
[first
++] = ' ';
9573 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9574 tmpbuf
[first
+ second
] = '\0';
9578 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9579 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9584 /* Might be a symbol version string. Don't as_bad here. */
9590 bfd_reloc_code_real_type
9591 x86_cons (expressionS
*exp
, int size
)
9593 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9595 intel_syntax
= -intel_syntax
;
9598 if (size
== 4 || (object_64bit
&& size
== 8))
9600 /* Handle @GOTOFF and the like in an expression. */
9602 char *gotfree_input_line
;
9605 save
= input_line_pointer
;
9606 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9607 if (gotfree_input_line
)
9608 input_line_pointer
= gotfree_input_line
;
9612 if (gotfree_input_line
)
9614 /* expression () has merrily parsed up to the end of line,
9615 or a comma - in the wrong buffer. Transfer how far
9616 input_line_pointer has moved to the right buffer. */
9617 input_line_pointer
= (save
9618 + (input_line_pointer
- gotfree_input_line
)
9620 free (gotfree_input_line
);
9621 if (exp
->X_op
== O_constant
9622 || exp
->X_op
== O_absent
9623 || exp
->X_op
== O_illegal
9624 || exp
->X_op
== O_register
9625 || exp
->X_op
== O_big
)
9627 char c
= *input_line_pointer
;
9628 *input_line_pointer
= 0;
9629 as_bad (_("missing or invalid expression `%s'"), save
);
9630 *input_line_pointer
= c
;
9632 else if ((got_reloc
== BFD_RELOC_386_PLT32
9633 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9634 && exp
->X_op
!= O_symbol
)
9636 char c
= *input_line_pointer
;
9637 *input_line_pointer
= 0;
9638 as_bad (_("invalid PLT expression `%s'"), save
);
9639 *input_line_pointer
= c
;
9646 intel_syntax
= -intel_syntax
;
9649 i386_intel_simplify (exp
);
9655 signed_cons (int size
)
9657 if (flag_code
== CODE_64BIT
)
9665 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9672 if (exp
.X_op
== O_symbol
)
9673 exp
.X_op
= O_secrel
;
9675 emit_expr (&exp
, 4);
9677 while (*input_line_pointer
++ == ',');
9679 input_line_pointer
--;
9680 demand_empty_rest_of_line ();
9684 /* Handle Vector operations. */
9687 check_VecOperations (char *op_string
, char *op_end
)
9689 const reg_entry
*mask
;
9694 && (op_end
== NULL
|| op_string
< op_end
))
9697 if (*op_string
== '{')
9701 /* Check broadcasts. */
9702 if (strncmp (op_string
, "1to", 3) == 0)
9707 goto duplicated_vec_op
;
9710 if (*op_string
== '8')
9712 else if (*op_string
== '4')
9714 else if (*op_string
== '2')
9716 else if (*op_string
== '1'
9717 && *(op_string
+1) == '6')
9724 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9729 broadcast_op
.type
= bcst_type
;
9730 broadcast_op
.operand
= this_operand
;
9731 broadcast_op
.bytes
= 0;
9732 i
.broadcast
= &broadcast_op
;
9734 /* Check masking operation. */
9735 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9737 /* k0 can't be used for write mask. */
9738 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9740 as_bad (_("`%s%s' can't be used for write mask"),
9741 register_prefix
, mask
->reg_name
);
9747 mask_op
.mask
= mask
;
9748 mask_op
.zeroing
= 0;
9749 mask_op
.operand
= this_operand
;
9755 goto duplicated_vec_op
;
9757 i
.mask
->mask
= mask
;
9759 /* Only "{z}" is allowed here. No need to check
9760 zeroing mask explicitly. */
9761 if (i
.mask
->operand
!= this_operand
)
9763 as_bad (_("invalid write mask `%s'"), saved
);
9770 /* Check zeroing-flag for masking operation. */
9771 else if (*op_string
== 'z')
9775 mask_op
.mask
= NULL
;
9776 mask_op
.zeroing
= 1;
9777 mask_op
.operand
= this_operand
;
9782 if (i
.mask
->zeroing
)
9785 as_bad (_("duplicated `%s'"), saved
);
9789 i
.mask
->zeroing
= 1;
9791 /* Only "{%k}" is allowed here. No need to check mask
9792 register explicitly. */
9793 if (i
.mask
->operand
!= this_operand
)
9795 as_bad (_("invalid zeroing-masking `%s'"),
9804 goto unknown_vec_op
;
9806 if (*op_string
!= '}')
9808 as_bad (_("missing `}' in `%s'"), saved
);
9813 /* Strip whitespace since the addition of pseudo prefixes
9814 changed how the scrubber treats '{'. */
9815 if (is_space_char (*op_string
))
9821 /* We don't know this one. */
9822 as_bad (_("unknown vector operation: `%s'"), saved
);
9826 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9828 as_bad (_("zeroing-masking only allowed with write mask"));
9836 i386_immediate (char *imm_start
)
9838 char *save_input_line_pointer
;
9839 char *gotfree_input_line
;
9842 i386_operand_type types
;
9844 operand_type_set (&types
, ~0);
9846 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9848 as_bad (_("at most %d immediate operands are allowed"),
9849 MAX_IMMEDIATE_OPERANDS
);
9853 exp
= &im_expressions
[i
.imm_operands
++];
9854 i
.op
[this_operand
].imms
= exp
;
9856 if (is_space_char (*imm_start
))
9859 save_input_line_pointer
= input_line_pointer
;
9860 input_line_pointer
= imm_start
;
9862 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9863 if (gotfree_input_line
)
9864 input_line_pointer
= gotfree_input_line
;
9866 exp_seg
= expression (exp
);
9870 /* Handle vector operations. */
9871 if (*input_line_pointer
== '{')
9873 input_line_pointer
= check_VecOperations (input_line_pointer
,
9875 if (input_line_pointer
== NULL
)
9879 if (*input_line_pointer
)
9880 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9882 input_line_pointer
= save_input_line_pointer
;
9883 if (gotfree_input_line
)
9885 free (gotfree_input_line
);
9887 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9888 exp
->X_op
= O_illegal
;
9891 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9895 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9896 i386_operand_type types
, const char *imm_start
)
9898 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9901 as_bad (_("missing or invalid immediate expression `%s'"),
9905 else if (exp
->X_op
== O_constant
)
9907 /* Size it properly later. */
9908 i
.types
[this_operand
].bitfield
.imm64
= 1;
9909 /* If not 64bit, sign extend val. */
9910 if (flag_code
!= CODE_64BIT
9911 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9913 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9915 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9916 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9917 && exp_seg
!= absolute_section
9918 && exp_seg
!= text_section
9919 && exp_seg
!= data_section
9920 && exp_seg
!= bss_section
9921 && exp_seg
!= undefined_section
9922 && !bfd_is_com_section (exp_seg
))
9924 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9928 else if (!intel_syntax
&& exp_seg
== reg_section
)
9931 as_bad (_("illegal immediate register operand %s"), imm_start
);
9936 /* This is an address. The size of the address will be
9937 determined later, depending on destination register,
9938 suffix, or the default for the section. */
9939 i
.types
[this_operand
].bitfield
.imm8
= 1;
9940 i
.types
[this_operand
].bitfield
.imm16
= 1;
9941 i
.types
[this_operand
].bitfield
.imm32
= 1;
9942 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9943 i
.types
[this_operand
].bitfield
.imm64
= 1;
9944 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9952 i386_scale (char *scale
)
9955 char *save
= input_line_pointer
;
9957 input_line_pointer
= scale
;
9958 val
= get_absolute_expression ();
9963 i
.log2_scale_factor
= 0;
9966 i
.log2_scale_factor
= 1;
9969 i
.log2_scale_factor
= 2;
9972 i
.log2_scale_factor
= 3;
9976 char sep
= *input_line_pointer
;
9978 *input_line_pointer
= '\0';
9979 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9981 *input_line_pointer
= sep
;
9982 input_line_pointer
= save
;
9986 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9988 as_warn (_("scale factor of %d without an index register"),
9989 1 << i
.log2_scale_factor
);
9990 i
.log2_scale_factor
= 0;
9992 scale
= input_line_pointer
;
9993 input_line_pointer
= save
;
9998 i386_displacement (char *disp_start
, char *disp_end
)
10002 char *save_input_line_pointer
;
10003 char *gotfree_input_line
;
10005 i386_operand_type bigdisp
, types
= anydisp
;
10008 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
10010 as_bad (_("at most %d displacement operands are allowed"),
10011 MAX_MEMORY_OPERANDS
);
10015 operand_type_set (&bigdisp
, 0);
10017 || i
.types
[this_operand
].bitfield
.baseindex
10018 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
10019 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
10021 i386_addressing_mode ();
10022 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
10023 if (flag_code
== CODE_64BIT
)
10027 bigdisp
.bitfield
.disp32s
= 1;
10028 bigdisp
.bitfield
.disp64
= 1;
10031 bigdisp
.bitfield
.disp32
= 1;
10033 else if ((flag_code
== CODE_16BIT
) ^ override
)
10034 bigdisp
.bitfield
.disp16
= 1;
10036 bigdisp
.bitfield
.disp32
= 1;
10040 /* For PC-relative branches, the width of the displacement may be
10041 dependent upon data size, but is never dependent upon address size.
10042 Also make sure to not unintentionally match against a non-PC-relative
10043 branch template. */
10044 static templates aux_templates
;
10045 const insn_template
*t
= current_templates
->start
;
10046 bfd_boolean has_intel64
= FALSE
;
10048 aux_templates
.start
= t
;
10049 while (++t
< current_templates
->end
)
10051 if (t
->opcode_modifier
.jump
10052 != current_templates
->start
->opcode_modifier
.jump
)
10054 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
10055 has_intel64
= TRUE
;
10057 if (t
< current_templates
->end
)
10059 aux_templates
.end
= t
;
10060 current_templates
= &aux_templates
;
10063 override
= (i
.prefix
[DATA_PREFIX
] != 0);
10064 if (flag_code
== CODE_64BIT
)
10066 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10067 && (!intel64
|| !has_intel64
))
10068 bigdisp
.bitfield
.disp16
= 1;
10070 bigdisp
.bitfield
.disp32s
= 1;
10075 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10077 : LONG_MNEM_SUFFIX
));
10078 bigdisp
.bitfield
.disp32
= 1;
10079 if ((flag_code
== CODE_16BIT
) ^ override
)
10081 bigdisp
.bitfield
.disp32
= 0;
10082 bigdisp
.bitfield
.disp16
= 1;
10086 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10089 exp
= &disp_expressions
[i
.disp_operands
];
10090 i
.op
[this_operand
].disps
= exp
;
10092 save_input_line_pointer
= input_line_pointer
;
10093 input_line_pointer
= disp_start
;
10094 END_STRING_AND_SAVE (disp_end
);
10096 #ifndef GCC_ASM_O_HACK
10097 #define GCC_ASM_O_HACK 0
10100 END_STRING_AND_SAVE (disp_end
+ 1);
10101 if (i
.types
[this_operand
].bitfield
.baseIndex
10102 && displacement_string_end
[-1] == '+')
10104 /* This hack is to avoid a warning when using the "o"
10105 constraint within gcc asm statements.
10108 #define _set_tssldt_desc(n,addr,limit,type) \
10109 __asm__ __volatile__ ( \
10110 "movw %w2,%0\n\t" \
10111 "movw %w1,2+%0\n\t" \
10112 "rorl $16,%1\n\t" \
10113 "movb %b1,4+%0\n\t" \
10114 "movb %4,5+%0\n\t" \
10115 "movb $0,6+%0\n\t" \
10116 "movb %h1,7+%0\n\t" \
10118 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10120 This works great except that the output assembler ends
10121 up looking a bit weird if it turns out that there is
10122 no offset. You end up producing code that looks like:
10135 So here we provide the missing zero. */
10137 *displacement_string_end
= '0';
10140 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10141 if (gotfree_input_line
)
10142 input_line_pointer
= gotfree_input_line
;
10144 exp_seg
= expression (exp
);
10146 SKIP_WHITESPACE ();
10147 if (*input_line_pointer
)
10148 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10150 RESTORE_END_STRING (disp_end
+ 1);
10152 input_line_pointer
= save_input_line_pointer
;
10153 if (gotfree_input_line
)
10155 free (gotfree_input_line
);
10157 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10158 exp
->X_op
= O_illegal
;
10161 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10163 RESTORE_END_STRING (disp_end
);
10169 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10170 i386_operand_type types
, const char *disp_start
)
10172 i386_operand_type bigdisp
;
10175 /* We do this to make sure that the section symbol is in
10176 the symbol table. We will ultimately change the relocation
10177 to be relative to the beginning of the section. */
10178 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10179 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10180 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10182 if (exp
->X_op
!= O_symbol
)
10185 if (S_IS_LOCAL (exp
->X_add_symbol
)
10186 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10187 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10188 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10189 exp
->X_op
= O_subtract
;
10190 exp
->X_op_symbol
= GOT_symbol
;
10191 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10192 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10193 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10194 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10196 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10199 else if (exp
->X_op
== O_absent
10200 || exp
->X_op
== O_illegal
10201 || exp
->X_op
== O_big
)
10204 as_bad (_("missing or invalid displacement expression `%s'"),
10209 else if (flag_code
== CODE_64BIT
10210 && !i
.prefix
[ADDR_PREFIX
]
10211 && exp
->X_op
== O_constant
)
10213 /* Since displacement is signed extended to 64bit, don't allow
10214 disp32 and turn off disp32s if they are out of range. */
10215 i
.types
[this_operand
].bitfield
.disp32
= 0;
10216 if (!fits_in_signed_long (exp
->X_add_number
))
10218 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10219 if (i
.types
[this_operand
].bitfield
.baseindex
)
10221 as_bad (_("0x%lx out range of signed 32bit displacement"),
10222 (long) exp
->X_add_number
);
10228 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10229 else if (exp
->X_op
!= O_constant
10230 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10231 && exp_seg
!= absolute_section
10232 && exp_seg
!= text_section
10233 && exp_seg
!= data_section
10234 && exp_seg
!= bss_section
10235 && exp_seg
!= undefined_section
10236 && !bfd_is_com_section (exp_seg
))
10238 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10243 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10244 /* Constants get taken care of by optimize_disp(). */
10245 && exp
->X_op
!= O_constant
)
10246 i
.types
[this_operand
].bitfield
.disp8
= 1;
10248 /* Check if this is a displacement only operand. */
10249 bigdisp
= i
.types
[this_operand
];
10250 bigdisp
.bitfield
.disp8
= 0;
10251 bigdisp
.bitfield
.disp16
= 0;
10252 bigdisp
.bitfield
.disp32
= 0;
10253 bigdisp
.bitfield
.disp32s
= 0;
10254 bigdisp
.bitfield
.disp64
= 0;
10255 if (operand_type_all_zero (&bigdisp
))
10256 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10262 /* Return the active addressing mode, taking address override and
10263 registers forming the address into consideration. Update the
10264 address override prefix if necessary. */
10266 static enum flag_code
10267 i386_addressing_mode (void)
10269 enum flag_code addr_mode
;
10271 if (i
.prefix
[ADDR_PREFIX
])
10272 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10275 addr_mode
= flag_code
;
10277 #if INFER_ADDR_PREFIX
10278 if (i
.mem_operands
== 0)
10280 /* Infer address prefix from the first memory operand. */
10281 const reg_entry
*addr_reg
= i
.base_reg
;
10283 if (addr_reg
== NULL
)
10284 addr_reg
= i
.index_reg
;
10288 if (addr_reg
->reg_type
.bitfield
.dword
)
10289 addr_mode
= CODE_32BIT
;
10290 else if (flag_code
!= CODE_64BIT
10291 && addr_reg
->reg_type
.bitfield
.word
)
10292 addr_mode
= CODE_16BIT
;
10294 if (addr_mode
!= flag_code
)
10296 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10298 /* Change the size of any displacement too. At most one
10299 of Disp16 or Disp32 is set.
10300 FIXME. There doesn't seem to be any real need for
10301 separate Disp16 and Disp32 flags. The same goes for
10302 Imm16 and Imm32. Removing them would probably clean
10303 up the code quite a lot. */
10304 if (flag_code
!= CODE_64BIT
10305 && (i
.types
[this_operand
].bitfield
.disp16
10306 || i
.types
[this_operand
].bitfield
.disp32
))
10307 i
.types
[this_operand
]
10308 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10318 /* Make sure the memory operand we've been dealt is valid.
10319 Return 1 on success, 0 on a failure. */
10322 i386_index_check (const char *operand_string
)
10324 const char *kind
= "base/index";
10325 enum flag_code addr_mode
= i386_addressing_mode ();
10327 if (current_templates
->start
->opcode_modifier
.isstring
10328 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10329 && (current_templates
->end
[-1].opcode_modifier
.isstring
10330 || i
.mem_operands
))
10332 /* Memory operands of string insns are special in that they only allow
10333 a single register (rDI, rSI, or rBX) as their memory address. */
10334 const reg_entry
*expected_reg
;
10335 static const char *di_si
[][2] =
10341 static const char *bx
[] = { "ebx", "bx", "rbx" };
10343 kind
= "string address";
10345 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10347 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10348 - IS_STRING_ES_OP0
;
10351 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10352 || ((!i
.mem_operands
!= !intel_syntax
)
10353 && current_templates
->end
[-1].operand_types
[1]
10354 .bitfield
.baseindex
))
10356 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10359 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10361 if (i
.base_reg
!= expected_reg
10363 || operand_type_check (i
.types
[this_operand
], disp
))
10365 /* The second memory operand must have the same size as
10369 && !((addr_mode
== CODE_64BIT
10370 && i
.base_reg
->reg_type
.bitfield
.qword
)
10371 || (addr_mode
== CODE_32BIT
10372 ? i
.base_reg
->reg_type
.bitfield
.dword
10373 : i
.base_reg
->reg_type
.bitfield
.word
)))
10376 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10378 intel_syntax
? '[' : '(',
10380 expected_reg
->reg_name
,
10381 intel_syntax
? ']' : ')');
10388 as_bad (_("`%s' is not a valid %s expression"),
10389 operand_string
, kind
);
10394 if (addr_mode
!= CODE_16BIT
)
10396 /* 32-bit/64-bit checks. */
10398 && ((addr_mode
== CODE_64BIT
10399 ? !i
.base_reg
->reg_type
.bitfield
.qword
10400 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10401 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10402 || i
.base_reg
->reg_num
== RegIZ
))
10404 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10405 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10406 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10407 && ((addr_mode
== CODE_64BIT
10408 ? !i
.index_reg
->reg_type
.bitfield
.qword
10409 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10410 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10413 /* bndmk, bndldx, and bndstx have special restrictions. */
10414 if (current_templates
->start
->base_opcode
== 0xf30f1b
10415 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10417 /* They cannot use RIP-relative addressing. */
10418 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10420 as_bad (_("`%s' cannot be used here"), operand_string
);
10424 /* bndldx and bndstx ignore their scale factor. */
10425 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10426 && i
.log2_scale_factor
)
10427 as_warn (_("register scaling is being ignored here"));
10432 /* 16-bit checks. */
10434 && (!i
.base_reg
->reg_type
.bitfield
.word
10435 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10437 && (!i
.index_reg
->reg_type
.bitfield
.word
10438 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10440 && i
.base_reg
->reg_num
< 6
10441 && i
.index_reg
->reg_num
>= 6
10442 && i
.log2_scale_factor
== 0))))
10449 /* Handle vector immediates. */
10452 RC_SAE_immediate (const char *imm_start
)
10454 unsigned int match_found
, j
;
10455 const char *pstr
= imm_start
;
10463 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10465 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10469 rc_op
.type
= RC_NamesTable
[j
].type
;
10470 rc_op
.operand
= this_operand
;
10471 i
.rounding
= &rc_op
;
10475 as_bad (_("duplicated `%s'"), imm_start
);
10478 pstr
+= RC_NamesTable
[j
].len
;
10486 if (*pstr
++ != '}')
10488 as_bad (_("Missing '}': '%s'"), imm_start
);
10491 /* RC/SAE immediate string should contain nothing more. */;
10494 as_bad (_("Junk after '}': '%s'"), imm_start
);
10498 exp
= &im_expressions
[i
.imm_operands
++];
10499 i
.op
[this_operand
].imms
= exp
;
10501 exp
->X_op
= O_constant
;
10502 exp
->X_add_number
= 0;
10503 exp
->X_add_symbol
= (symbolS
*) 0;
10504 exp
->X_op_symbol
= (symbolS
*) 0;
10506 i
.types
[this_operand
].bitfield
.imm8
= 1;
10510 /* Only string instructions can have a second memory operand, so
10511 reduce current_templates to just those if it contains any. */
10513 maybe_adjust_templates (void)
10515 const insn_template
*t
;
10517 gas_assert (i
.mem_operands
== 1);
10519 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10520 if (t
->opcode_modifier
.isstring
)
10523 if (t
< current_templates
->end
)
10525 static templates aux_templates
;
10526 bfd_boolean recheck
;
10528 aux_templates
.start
= t
;
10529 for (; t
< current_templates
->end
; ++t
)
10530 if (!t
->opcode_modifier
.isstring
)
10532 aux_templates
.end
= t
;
10534 /* Determine whether to re-check the first memory operand. */
10535 recheck
= (aux_templates
.start
!= current_templates
->start
10536 || t
!= current_templates
->end
);
10538 current_templates
= &aux_templates
;
10542 i
.mem_operands
= 0;
10543 if (i
.memop1_string
!= NULL
10544 && i386_index_check (i
.memop1_string
) == 0)
10546 i
.mem_operands
= 1;
10553 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10557 i386_att_operand (char *operand_string
)
10559 const reg_entry
*r
;
10561 char *op_string
= operand_string
;
10563 if (is_space_char (*op_string
))
10566 /* We check for an absolute prefix (differentiating,
10567 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10568 if (*op_string
== ABSOLUTE_PREFIX
)
10571 if (is_space_char (*op_string
))
10573 i
.jumpabsolute
= TRUE
;
10576 /* Check if operand is a register. */
10577 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10579 i386_operand_type temp
;
10581 /* Check for a segment override by searching for ':' after a
10582 segment register. */
10583 op_string
= end_op
;
10584 if (is_space_char (*op_string
))
10586 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10588 switch (r
->reg_num
)
10591 i
.seg
[i
.mem_operands
] = &es
;
10594 i
.seg
[i
.mem_operands
] = &cs
;
10597 i
.seg
[i
.mem_operands
] = &ss
;
10600 i
.seg
[i
.mem_operands
] = &ds
;
10603 i
.seg
[i
.mem_operands
] = &fs
;
10606 i
.seg
[i
.mem_operands
] = &gs
;
10610 /* Skip the ':' and whitespace. */
10612 if (is_space_char (*op_string
))
10615 if (!is_digit_char (*op_string
)
10616 && !is_identifier_char (*op_string
)
10617 && *op_string
!= '('
10618 && *op_string
!= ABSOLUTE_PREFIX
)
10620 as_bad (_("bad memory operand `%s'"), op_string
);
10623 /* Handle case of %es:*foo. */
10624 if (*op_string
== ABSOLUTE_PREFIX
)
10627 if (is_space_char (*op_string
))
10629 i
.jumpabsolute
= TRUE
;
10631 goto do_memory_reference
;
10634 /* Handle vector operations. */
10635 if (*op_string
== '{')
10637 op_string
= check_VecOperations (op_string
, NULL
);
10638 if (op_string
== NULL
)
10644 as_bad (_("junk `%s' after register"), op_string
);
10647 temp
= r
->reg_type
;
10648 temp
.bitfield
.baseindex
= 0;
10649 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10651 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10652 i
.op
[this_operand
].regs
= r
;
10655 else if (*op_string
== REGISTER_PREFIX
)
10657 as_bad (_("bad register name `%s'"), op_string
);
10660 else if (*op_string
== IMMEDIATE_PREFIX
)
10663 if (i
.jumpabsolute
)
10665 as_bad (_("immediate operand illegal with absolute jump"));
10668 if (!i386_immediate (op_string
))
10671 else if (RC_SAE_immediate (operand_string
))
10673 /* If it is a RC or SAE immediate, do nothing. */
10676 else if (is_digit_char (*op_string
)
10677 || is_identifier_char (*op_string
)
10678 || *op_string
== '"'
10679 || *op_string
== '(')
10681 /* This is a memory reference of some sort. */
10684 /* Start and end of displacement string expression (if found). */
10685 char *displacement_string_start
;
10686 char *displacement_string_end
;
10689 do_memory_reference
:
10690 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10692 if ((i
.mem_operands
== 1
10693 && !current_templates
->start
->opcode_modifier
.isstring
)
10694 || i
.mem_operands
== 2)
10696 as_bad (_("too many memory references for `%s'"),
10697 current_templates
->start
->name
);
10701 /* Check for base index form. We detect the base index form by
10702 looking for an ')' at the end of the operand, searching
10703 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10705 base_string
= op_string
+ strlen (op_string
);
10707 /* Handle vector operations. */
10708 vop_start
= strchr (op_string
, '{');
10709 if (vop_start
&& vop_start
< base_string
)
10711 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10713 base_string
= vop_start
;
10717 if (is_space_char (*base_string
))
10720 /* If we only have a displacement, set-up for it to be parsed later. */
10721 displacement_string_start
= op_string
;
10722 displacement_string_end
= base_string
+ 1;
10724 if (*base_string
== ')')
10727 unsigned int parens_balanced
= 1;
10728 /* We've already checked that the number of left & right ()'s are
10729 equal, so this loop will not be infinite. */
10733 if (*base_string
== ')')
10735 if (*base_string
== '(')
10738 while (parens_balanced
);
10740 temp_string
= base_string
;
10742 /* Skip past '(' and whitespace. */
10744 if (is_space_char (*base_string
))
10747 if (*base_string
== ','
10748 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10751 displacement_string_end
= temp_string
;
10753 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10757 base_string
= end_op
;
10758 if (is_space_char (*base_string
))
10762 /* There may be an index reg or scale factor here. */
10763 if (*base_string
== ',')
10766 if (is_space_char (*base_string
))
10769 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10772 base_string
= end_op
;
10773 if (is_space_char (*base_string
))
10775 if (*base_string
== ',')
10778 if (is_space_char (*base_string
))
10781 else if (*base_string
!= ')')
10783 as_bad (_("expecting `,' or `)' "
10784 "after index register in `%s'"),
10789 else if (*base_string
== REGISTER_PREFIX
)
10791 end_op
= strchr (base_string
, ',');
10794 as_bad (_("bad register name `%s'"), base_string
);
10798 /* Check for scale factor. */
10799 if (*base_string
!= ')')
10801 char *end_scale
= i386_scale (base_string
);
10806 base_string
= end_scale
;
10807 if (is_space_char (*base_string
))
10809 if (*base_string
!= ')')
10811 as_bad (_("expecting `)' "
10812 "after scale factor in `%s'"),
10817 else if (!i
.index_reg
)
10819 as_bad (_("expecting index register or scale factor "
10820 "after `,'; got '%c'"),
10825 else if (*base_string
!= ')')
10827 as_bad (_("expecting `,' or `)' "
10828 "after base register in `%s'"),
10833 else if (*base_string
== REGISTER_PREFIX
)
10835 end_op
= strchr (base_string
, ',');
10838 as_bad (_("bad register name `%s'"), base_string
);
10843 /* If there's an expression beginning the operand, parse it,
10844 assuming displacement_string_start and
10845 displacement_string_end are meaningful. */
10846 if (displacement_string_start
!= displacement_string_end
)
10848 if (!i386_displacement (displacement_string_start
,
10849 displacement_string_end
))
10853 /* Special case for (%dx) while doing input/output op. */
10855 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10856 && i
.base_reg
->reg_type
.bitfield
.word
10857 && i
.index_reg
== 0
10858 && i
.log2_scale_factor
== 0
10859 && i
.seg
[i
.mem_operands
] == 0
10860 && !operand_type_check (i
.types
[this_operand
], disp
))
10862 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10866 if (i386_index_check (operand_string
) == 0)
10868 i
.flags
[this_operand
] |= Operand_Mem
;
10869 if (i
.mem_operands
== 0)
10870 i
.memop1_string
= xstrdup (operand_string
);
10875 /* It's not a memory operand; argh! */
10876 as_bad (_("invalid char %s beginning operand %d `%s'"),
10877 output_invalid (*op_string
),
10882 return 1; /* Normal return. */
10885 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10886 that an rs_machine_dependent frag may reach. */
10889 i386_frag_max_var (fragS
*frag
)
10891 /* The only relaxable frags are for jumps.
10892 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10893 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10894 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10897 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10899 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10901 /* STT_GNU_IFUNC symbol must go through PLT. */
10902 if ((symbol_get_bfdsym (fr_symbol
)->flags
10903 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10906 if (!S_IS_EXTERNAL (fr_symbol
))
10907 /* Symbol may be weak or local. */
10908 return !S_IS_WEAK (fr_symbol
);
10910 /* Global symbols with non-default visibility can't be preempted. */
10911 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10914 if (fr_var
!= NO_RELOC
)
10915 switch ((enum bfd_reloc_code_real
) fr_var
)
10917 case BFD_RELOC_386_PLT32
:
10918 case BFD_RELOC_X86_64_PLT32
:
10919 /* Symbol with PLT relocation may be preempted. */
10925 /* Global symbols with default visibility in a shared library may be
10926 preempted by another definition. */
10931 /* Return the next non-empty frag. */
10934 i386_next_non_empty_frag (fragS
*fragP
)
10936 /* There may be a frag with a ".fill 0" when there is no room in
10937 the current frag for frag_grow in output_insn. */
10938 for (fragP
= fragP
->fr_next
;
10940 && fragP
->fr_type
== rs_fill
10941 && fragP
->fr_fix
== 0);
10942 fragP
= fragP
->fr_next
)
10947 /* Return the next jcc frag after BRANCH_PADDING. */
10950 i386_next_jcc_frag (fragS
*fragP
)
10955 if (fragP
->fr_type
== rs_machine_dependent
10956 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10957 == BRANCH_PADDING
))
10959 fragP
= i386_next_non_empty_frag (fragP
);
10960 if (fragP
->fr_type
!= rs_machine_dependent
)
10962 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10969 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10972 i386_classify_machine_dependent_frag (fragS
*fragP
)
10976 fragS
*branch_fragP
;
10978 unsigned int max_prefix_length
;
10980 if (fragP
->tc_frag_data
.classified
)
10983 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10984 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10985 for (next_fragP
= fragP
;
10986 next_fragP
!= NULL
;
10987 next_fragP
= next_fragP
->fr_next
)
10989 next_fragP
->tc_frag_data
.classified
= 1;
10990 if (next_fragP
->fr_type
== rs_machine_dependent
)
10991 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10993 case BRANCH_PADDING
:
10994 /* The BRANCH_PADDING frag must be followed by a branch
10996 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10997 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10999 case FUSED_JCC_PADDING
:
11000 /* Check if this is a fused jcc:
11002 CMP like instruction
11006 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
11007 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
11008 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
11011 /* The BRANCH_PADDING frag is merged with the
11012 FUSED_JCC_PADDING frag. */
11013 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
11014 /* CMP like instruction size. */
11015 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
11016 frag_wane (pad_fragP
);
11017 /* Skip to branch_fragP. */
11018 next_fragP
= branch_fragP
;
11020 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
11022 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11024 next_fragP
->fr_subtype
11025 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
11026 next_fragP
->tc_frag_data
.max_bytes
11027 = next_fragP
->tc_frag_data
.max_prefix_length
;
11028 /* This will be updated in the BRANCH_PREFIX scan. */
11029 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
11032 frag_wane (next_fragP
);
11037 /* Stop if there is no BRANCH_PREFIX. */
11038 if (!align_branch_prefix_size
)
11041 /* Scan for BRANCH_PREFIX. */
11042 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
11044 if (fragP
->fr_type
!= rs_machine_dependent
11045 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11049 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11050 COND_JUMP_PREFIX. */
11051 max_prefix_length
= 0;
11052 for (next_fragP
= fragP
;
11053 next_fragP
!= NULL
;
11054 next_fragP
= next_fragP
->fr_next
)
11056 if (next_fragP
->fr_type
== rs_fill
)
11057 /* Skip rs_fill frags. */
11059 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
11060 /* Stop for all other frags. */
11063 /* rs_machine_dependent frags. */
11064 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11067 /* Count BRANCH_PREFIX frags. */
11068 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11070 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11071 frag_wane (next_fragP
);
11075 += next_fragP
->tc_frag_data
.max_bytes
;
11077 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11079 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11080 == FUSED_JCC_PADDING
))
11082 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11083 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11087 /* Stop for other rs_machine_dependent frags. */
11091 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11093 /* Skip to the next frag. */
11094 fragP
= next_fragP
;
11098 /* Compute padding size for
11101 CMP like instruction
11103 COND_JUMP/UNCOND_JUMP
11108 COND_JUMP/UNCOND_JUMP
11112 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11114 unsigned int offset
, size
, padding_size
;
11115 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11117 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11119 address
= fragP
->fr_address
;
11120 address
+= fragP
->fr_fix
;
11122 /* CMP like instrunction size. */
11123 size
= fragP
->tc_frag_data
.cmp_size
;
11125 /* The base size of the branch frag. */
11126 size
+= branch_fragP
->fr_fix
;
11128 /* Add opcode and displacement bytes for the rs_machine_dependent
11130 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11131 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11133 /* Check if branch is within boundary and doesn't end at the last
11135 offset
= address
& ((1U << align_branch_power
) - 1);
11136 if ((offset
+ size
) >= (1U << align_branch_power
))
11137 /* Padding needed to avoid crossing boundary. */
11138 padding_size
= (1U << align_branch_power
) - offset
;
11140 /* No padding needed. */
11143 /* The return value may be saved in tc_frag_data.length which is
11145 if (!fits_in_unsigned_byte (padding_size
))
11148 return padding_size
;
11151 /* i386_generic_table_relax_frag()
11153 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11154 grow/shrink padding to align branch frags. Hand others to
11158 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11160 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11161 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11163 long padding_size
= i386_branch_padding_size (fragP
, 0);
11164 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11166 /* When the BRANCH_PREFIX frag is used, the computed address
11167 must match the actual address and there should be no padding. */
11168 if (fragP
->tc_frag_data
.padding_address
11169 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11173 /* Update the padding size. */
11175 fragP
->tc_frag_data
.length
= padding_size
;
11179 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11181 fragS
*padding_fragP
, *next_fragP
;
11182 long padding_size
, left_size
, last_size
;
11184 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11185 if (!padding_fragP
)
11186 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11187 return (fragP
->tc_frag_data
.length
11188 - fragP
->tc_frag_data
.last_length
);
11190 /* Compute the relative address of the padding frag in the very
11191 first time where the BRANCH_PREFIX frag sizes are zero. */
11192 if (!fragP
->tc_frag_data
.padding_address
)
11193 fragP
->tc_frag_data
.padding_address
11194 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11196 /* First update the last length from the previous interation. */
11197 left_size
= fragP
->tc_frag_data
.prefix_length
;
11198 for (next_fragP
= fragP
;
11199 next_fragP
!= padding_fragP
;
11200 next_fragP
= next_fragP
->fr_next
)
11201 if (next_fragP
->fr_type
== rs_machine_dependent
11202 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11207 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11211 if (max
> left_size
)
11216 next_fragP
->tc_frag_data
.last_length
= size
;
11220 next_fragP
->tc_frag_data
.last_length
= 0;
11223 /* Check the padding size for the padding frag. */
11224 padding_size
= i386_branch_padding_size
11225 (padding_fragP
, (fragP
->fr_address
11226 + fragP
->tc_frag_data
.padding_address
));
11228 last_size
= fragP
->tc_frag_data
.prefix_length
;
11229 /* Check if there is change from the last interation. */
11230 if (padding_size
== last_size
)
11232 /* Update the expected address of the padding frag. */
11233 padding_fragP
->tc_frag_data
.padding_address
11234 = (fragP
->fr_address
+ padding_size
11235 + fragP
->tc_frag_data
.padding_address
);
11239 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11241 /* No padding if there is no sufficient room. Clear the
11242 expected address of the padding frag. */
11243 padding_fragP
->tc_frag_data
.padding_address
= 0;
11247 /* Store the expected address of the padding frag. */
11248 padding_fragP
->tc_frag_data
.padding_address
11249 = (fragP
->fr_address
+ padding_size
11250 + fragP
->tc_frag_data
.padding_address
);
11252 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11254 /* Update the length for the current interation. */
11255 left_size
= padding_size
;
11256 for (next_fragP
= fragP
;
11257 next_fragP
!= padding_fragP
;
11258 next_fragP
= next_fragP
->fr_next
)
11259 if (next_fragP
->fr_type
== rs_machine_dependent
11260 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11265 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11269 if (max
> left_size
)
11274 next_fragP
->tc_frag_data
.length
= size
;
11278 next_fragP
->tc_frag_data
.length
= 0;
11281 return (fragP
->tc_frag_data
.length
11282 - fragP
->tc_frag_data
.last_length
);
11284 return relax_frag (segment
, fragP
, stretch
);
11287 /* md_estimate_size_before_relax()
11289 Called just before relax() for rs_machine_dependent frags. The x86
11290 assembler uses these frags to handle variable size jump
11293 Any symbol that is now undefined will not become defined.
11294 Return the correct fr_subtype in the frag.
11295 Return the initial "guess for variable size of frag" to caller.
11296 The guess is actually the growth beyond the fixed part. Whatever
11297 we do to grow the fixed or variable part contributes to our
11301 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11303 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11304 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11305 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11307 i386_classify_machine_dependent_frag (fragP
);
11308 return fragP
->tc_frag_data
.length
;
11311 /* We've already got fragP->fr_subtype right; all we have to do is
11312 check for un-relaxable symbols. On an ELF system, we can't relax
11313 an externally visible symbol, because it may be overridden by a
11315 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11316 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11318 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11321 #if defined (OBJ_COFF) && defined (TE_PE)
11322 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11323 && S_IS_WEAK (fragP
->fr_symbol
))
11327 /* Symbol is undefined in this segment, or we need to keep a
11328 reloc so that weak symbols can be overridden. */
11329 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11330 enum bfd_reloc_code_real reloc_type
;
11331 unsigned char *opcode
;
11334 if (fragP
->fr_var
!= NO_RELOC
)
11335 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11336 else if (size
== 2)
11337 reloc_type
= BFD_RELOC_16_PCREL
;
11338 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11339 else if (need_plt32_p (fragP
->fr_symbol
))
11340 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11343 reloc_type
= BFD_RELOC_32_PCREL
;
11345 old_fr_fix
= fragP
->fr_fix
;
11346 opcode
= (unsigned char *) fragP
->fr_opcode
;
11348 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11351 /* Make jmp (0xeb) a (d)word displacement jump. */
11353 fragP
->fr_fix
+= size
;
11354 fix_new (fragP
, old_fr_fix
, size
,
11356 fragP
->fr_offset
, 1,
11362 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11364 /* Negate the condition, and branch past an
11365 unconditional jump. */
11368 /* Insert an unconditional jump. */
11370 /* We added two extra opcode bytes, and have a two byte
11372 fragP
->fr_fix
+= 2 + 2;
11373 fix_new (fragP
, old_fr_fix
+ 2, 2,
11375 fragP
->fr_offset
, 1,
11379 /* Fall through. */
11382 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11386 fragP
->fr_fix
+= 1;
11387 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11389 fragP
->fr_offset
, 1,
11390 BFD_RELOC_8_PCREL
);
11391 fixP
->fx_signed
= 1;
11395 /* This changes the byte-displacement jump 0x7N
11396 to the (d)word-displacement jump 0x0f,0x8N. */
11397 opcode
[1] = opcode
[0] + 0x10;
11398 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11399 /* We've added an opcode byte. */
11400 fragP
->fr_fix
+= 1 + size
;
11401 fix_new (fragP
, old_fr_fix
+ 1, size
,
11403 fragP
->fr_offset
, 1,
11408 BAD_CASE (fragP
->fr_subtype
);
11412 return fragP
->fr_fix
- old_fr_fix
;
11415 /* Guess size depending on current relax state. Initially the relax
11416 state will correspond to a short jump and we return 1, because
11417 the variable part of the frag (the branch offset) is one byte
11418 long. However, we can relax a section more than once and in that
11419 case we must either set fr_subtype back to the unrelaxed state,
11420 or return the value for the appropriate branch. */
11421 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11424 /* Called after relax() is finished.
11426 In: Address of frag.
11427 fr_type == rs_machine_dependent.
11428 fr_subtype is what the address relaxed to.
11430 Out: Any fixSs and constants are set up.
11431 Caller will turn frag into a ".space 0". */
11434 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11437 unsigned char *opcode
;
11438 unsigned char *where_to_put_displacement
= NULL
;
11439 offsetT target_address
;
11440 offsetT opcode_address
;
11441 unsigned int extension
= 0;
11442 offsetT displacement_from_opcode_start
;
11444 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11445 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11446 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11448 /* Generate nop padding. */
11449 unsigned int size
= fragP
->tc_frag_data
.length
;
11452 if (size
> fragP
->tc_frag_data
.max_bytes
)
11458 const char *branch
= "branch";
11459 const char *prefix
= "";
11460 fragS
*padding_fragP
;
11461 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11464 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11465 switch (fragP
->tc_frag_data
.default_prefix
)
11470 case CS_PREFIX_OPCODE
:
11473 case DS_PREFIX_OPCODE
:
11476 case ES_PREFIX_OPCODE
:
11479 case FS_PREFIX_OPCODE
:
11482 case GS_PREFIX_OPCODE
:
11485 case SS_PREFIX_OPCODE
:
11490 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11491 "%s within %d-byte boundary\n");
11493 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11494 "align %s within %d-byte boundary\n");
11498 padding_fragP
= fragP
;
11499 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11500 "%s within %d-byte boundary\n");
11504 switch (padding_fragP
->tc_frag_data
.branch_type
)
11506 case align_branch_jcc
:
11509 case align_branch_fused
:
11510 branch
= "fused jcc";
11512 case align_branch_jmp
:
11515 case align_branch_call
:
11518 case align_branch_indirect
:
11519 branch
= "indiret branch";
11521 case align_branch_ret
:
11528 fprintf (stdout
, msg
,
11529 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11530 (long long) fragP
->fr_address
, branch
,
11531 1 << align_branch_power
);
11533 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11534 memset (fragP
->fr_opcode
,
11535 fragP
->tc_frag_data
.default_prefix
, size
);
11537 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11539 fragP
->fr_fix
+= size
;
11544 opcode
= (unsigned char *) fragP
->fr_opcode
;
11546 /* Address we want to reach in file space. */
11547 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11549 /* Address opcode resides at in file space. */
11550 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11552 /* Displacement from opcode start to fill into instruction. */
11553 displacement_from_opcode_start
= target_address
- opcode_address
;
11555 if ((fragP
->fr_subtype
& BIG
) == 0)
11557 /* Don't have to change opcode. */
11558 extension
= 1; /* 1 opcode + 1 displacement */
11559 where_to_put_displacement
= &opcode
[1];
11563 if (no_cond_jump_promotion
11564 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11565 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11566 _("long jump required"));
11568 switch (fragP
->fr_subtype
)
11570 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11571 extension
= 4; /* 1 opcode + 4 displacement */
11573 where_to_put_displacement
= &opcode
[1];
11576 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11577 extension
= 2; /* 1 opcode + 2 displacement */
11579 where_to_put_displacement
= &opcode
[1];
11582 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11583 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11584 extension
= 5; /* 2 opcode + 4 displacement */
11585 opcode
[1] = opcode
[0] + 0x10;
11586 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11587 where_to_put_displacement
= &opcode
[2];
11590 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11591 extension
= 3; /* 2 opcode + 2 displacement */
11592 opcode
[1] = opcode
[0] + 0x10;
11593 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11594 where_to_put_displacement
= &opcode
[2];
11597 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11602 where_to_put_displacement
= &opcode
[3];
11606 BAD_CASE (fragP
->fr_subtype
);
11611 /* If size if less then four we are sure that the operand fits,
11612 but if it's 4, then it could be that the displacement is larger
11614 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11616 && ((addressT
) (displacement_from_opcode_start
- extension
11617 + ((addressT
) 1 << 31))
11618 > (((addressT
) 2 << 31) - 1)))
11620 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11621 _("jump target out of range"));
11622 /* Make us emit 0. */
11623 displacement_from_opcode_start
= extension
;
11625 /* Now put displacement after opcode. */
11626 md_number_to_chars ((char *) where_to_put_displacement
,
11627 (valueT
) (displacement_from_opcode_start
- extension
),
11628 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11629 fragP
->fr_fix
+= extension
;
11632 /* Apply a fixup (fixP) to segment data, once it has been determined
11633 by our caller that we have all the info we need to fix it up.
11635 Parameter valP is the pointer to the value of the bits.
11637 On the 386, immediates, displacements, and data pointers are all in
11638 the same (little-endian) format, so we don't need to care about which
11639 we are handling. */
11642 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11644 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11645 valueT value
= *valP
;
11647 #if !defined (TE_Mach)
11648 if (fixP
->fx_pcrel
)
11650 switch (fixP
->fx_r_type
)
11656 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11659 case BFD_RELOC_X86_64_32S
:
11660 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11663 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11666 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11671 if (fixP
->fx_addsy
!= NULL
11672 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11673 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11674 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11675 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11676 && !use_rela_relocations
)
11678 /* This is a hack. There should be a better way to handle this.
11679 This covers for the fact that bfd_install_relocation will
11680 subtract the current location (for partial_inplace, PC relative
11681 relocations); see more below. */
11685 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11688 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11690 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11693 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11695 if ((sym_seg
== seg
11696 || (symbol_section_p (fixP
->fx_addsy
)
11697 && sym_seg
!= absolute_section
))
11698 && !generic_force_reloc (fixP
))
11700 /* Yes, we add the values in twice. This is because
11701 bfd_install_relocation subtracts them out again. I think
11702 bfd_install_relocation is broken, but I don't dare change
11704 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11708 #if defined (OBJ_COFF) && defined (TE_PE)
11709 /* For some reason, the PE format does not store a
11710 section address offset for a PC relative symbol. */
11711 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11712 || S_IS_WEAK (fixP
->fx_addsy
))
11713 value
+= md_pcrel_from (fixP
);
11716 #if defined (OBJ_COFF) && defined (TE_PE)
11717 if (fixP
->fx_addsy
!= NULL
11718 && S_IS_WEAK (fixP
->fx_addsy
)
11719 /* PR 16858: Do not modify weak function references. */
11720 && ! fixP
->fx_pcrel
)
11722 #if !defined (TE_PEP)
11723 /* For x86 PE weak function symbols are neither PC-relative
11724 nor do they set S_IS_FUNCTION. So the only reliable way
11725 to detect them is to check the flags of their containing
11727 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11728 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11732 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11736 /* Fix a few things - the dynamic linker expects certain values here,
11737 and we must not disappoint it. */
11738 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11739 if (IS_ELF
&& fixP
->fx_addsy
)
11740 switch (fixP
->fx_r_type
)
11742 case BFD_RELOC_386_PLT32
:
11743 case BFD_RELOC_X86_64_PLT32
:
11744 /* Make the jump instruction point to the address of the operand.
11745 At runtime we merely add the offset to the actual PLT entry.
11746 NB: Subtract the offset size only for jump instructions. */
11747 if (fixP
->fx_pcrel
)
11751 case BFD_RELOC_386_TLS_GD
:
11752 case BFD_RELOC_386_TLS_LDM
:
11753 case BFD_RELOC_386_TLS_IE_32
:
11754 case BFD_RELOC_386_TLS_IE
:
11755 case BFD_RELOC_386_TLS_GOTIE
:
11756 case BFD_RELOC_386_TLS_GOTDESC
:
11757 case BFD_RELOC_X86_64_TLSGD
:
11758 case BFD_RELOC_X86_64_TLSLD
:
11759 case BFD_RELOC_X86_64_GOTTPOFF
:
11760 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11761 value
= 0; /* Fully resolved at runtime. No addend. */
11763 case BFD_RELOC_386_TLS_LE
:
11764 case BFD_RELOC_386_TLS_LDO_32
:
11765 case BFD_RELOC_386_TLS_LE_32
:
11766 case BFD_RELOC_X86_64_DTPOFF32
:
11767 case BFD_RELOC_X86_64_DTPOFF64
:
11768 case BFD_RELOC_X86_64_TPOFF32
:
11769 case BFD_RELOC_X86_64_TPOFF64
:
11770 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11773 case BFD_RELOC_386_TLS_DESC_CALL
:
11774 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11775 value
= 0; /* Fully resolved at runtime. No addend. */
11776 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11780 case BFD_RELOC_VTABLE_INHERIT
:
11781 case BFD_RELOC_VTABLE_ENTRY
:
11788 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11790 #endif /* !defined (TE_Mach) */
11792 /* Are we finished with this relocation now? */
11793 if (fixP
->fx_addsy
== NULL
)
11795 #if defined (OBJ_COFF) && defined (TE_PE)
11796 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11799 /* Remember value for tc_gen_reloc. */
11800 fixP
->fx_addnumber
= value
;
11801 /* Clear out the frag for now. */
11805 else if (use_rela_relocations
)
11807 fixP
->fx_no_overflow
= 1;
11808 /* Remember value for tc_gen_reloc. */
11809 fixP
->fx_addnumber
= value
;
11813 md_number_to_chars (p
, value
, fixP
->fx_size
);
11817 md_atof (int type
, char *litP
, int *sizeP
)
11819 /* This outputs the LITTLENUMs in REVERSE order;
11820 in accord with the bigendian 386. */
11821 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11824 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11827 output_invalid (int c
)
11830 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11833 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11834 "(0x%x)", (unsigned char) c
);
11835 return output_invalid_buf
;
11838 /* REG_STRING starts *before* REGISTER_PREFIX. */
11840 static const reg_entry
*
11841 parse_real_register (char *reg_string
, char **end_op
)
11843 char *s
= reg_string
;
11845 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11846 const reg_entry
*r
;
11848 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11849 if (*s
== REGISTER_PREFIX
)
11852 if (is_space_char (*s
))
11855 p
= reg_name_given
;
11856 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11858 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11859 return (const reg_entry
*) NULL
;
11863 /* For naked regs, make sure that we are not dealing with an identifier.
11864 This prevents confusing an identifier like `eax_var' with register
11866 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11867 return (const reg_entry
*) NULL
;
11871 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11873 /* Handle floating point regs, allowing spaces in the (i) part. */
11874 if (r
== i386_regtab
/* %st is first entry of table */)
11876 if (!cpu_arch_flags
.bitfield
.cpu8087
11877 && !cpu_arch_flags
.bitfield
.cpu287
11878 && !cpu_arch_flags
.bitfield
.cpu387
)
11879 return (const reg_entry
*) NULL
;
11881 if (is_space_char (*s
))
11886 if (is_space_char (*s
))
11888 if (*s
>= '0' && *s
<= '7')
11890 int fpr
= *s
- '0';
11892 if (is_space_char (*s
))
11897 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11902 /* We have "%st(" then garbage. */
11903 return (const reg_entry
*) NULL
;
11907 if (r
== NULL
|| allow_pseudo_reg
)
11910 if (operand_type_all_zero (&r
->reg_type
))
11911 return (const reg_entry
*) NULL
;
11913 if ((r
->reg_type
.bitfield
.dword
11914 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11915 || r
->reg_type
.bitfield
.class == RegCR
11916 || r
->reg_type
.bitfield
.class == RegDR
11917 || r
->reg_type
.bitfield
.class == RegTR
)
11918 && !cpu_arch_flags
.bitfield
.cpui386
)
11919 return (const reg_entry
*) NULL
;
11921 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11922 return (const reg_entry
*) NULL
;
11924 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11926 if (r
->reg_type
.bitfield
.zmmword
11927 || r
->reg_type
.bitfield
.class == RegMask
)
11928 return (const reg_entry
*) NULL
;
11930 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11932 if (r
->reg_type
.bitfield
.ymmword
)
11933 return (const reg_entry
*) NULL
;
11935 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11936 return (const reg_entry
*) NULL
;
11940 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11941 return (const reg_entry
*) NULL
;
11943 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11944 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11945 return (const reg_entry
*) NULL
;
11947 /* Upper 16 vector registers are only available with VREX in 64bit
11948 mode, and require EVEX encoding. */
11949 if (r
->reg_flags
& RegVRex
)
11951 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11952 || flag_code
!= CODE_64BIT
)
11953 return (const reg_entry
*) NULL
;
11955 i
.vec_encoding
= vex_encoding_evex
;
11958 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11959 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11960 && flag_code
!= CODE_64BIT
)
11961 return (const reg_entry
*) NULL
;
11963 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11965 return (const reg_entry
*) NULL
;
11970 /* REG_STRING starts *before* REGISTER_PREFIX. */
11972 static const reg_entry
*
11973 parse_register (char *reg_string
, char **end_op
)
11975 const reg_entry
*r
;
11977 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11978 r
= parse_real_register (reg_string
, end_op
);
11983 char *save
= input_line_pointer
;
11987 input_line_pointer
= reg_string
;
11988 c
= get_symbol_name (®_string
);
11989 symbolP
= symbol_find (reg_string
);
11990 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11992 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11994 know (e
->X_op
== O_register
);
11995 know (e
->X_add_number
>= 0
11996 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11997 r
= i386_regtab
+ e
->X_add_number
;
11998 if ((r
->reg_flags
& RegVRex
))
11999 i
.vec_encoding
= vex_encoding_evex
;
12000 *end_op
= input_line_pointer
;
12002 *input_line_pointer
= c
;
12003 input_line_pointer
= save
;
12009 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
12011 const reg_entry
*r
;
12012 char *end
= input_line_pointer
;
12015 r
= parse_register (name
, &input_line_pointer
);
12016 if (r
&& end
<= input_line_pointer
)
12018 *nextcharP
= *input_line_pointer
;
12019 *input_line_pointer
= 0;
12020 e
->X_op
= O_register
;
12021 e
->X_add_number
= r
- i386_regtab
;
12024 input_line_pointer
= end
;
12026 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
12030 md_operand (expressionS
*e
)
12033 const reg_entry
*r
;
12035 switch (*input_line_pointer
)
12037 case REGISTER_PREFIX
:
12038 r
= parse_real_register (input_line_pointer
, &end
);
12041 e
->X_op
= O_register
;
12042 e
->X_add_number
= r
- i386_regtab
;
12043 input_line_pointer
= end
;
12048 gas_assert (intel_syntax
);
12049 end
= input_line_pointer
++;
12051 if (*input_line_pointer
== ']')
12053 ++input_line_pointer
;
12054 e
->X_op_symbol
= make_expr_symbol (e
);
12055 e
->X_add_symbol
= NULL
;
12056 e
->X_add_number
= 0;
12061 e
->X_op
= O_absent
;
12062 input_line_pointer
= end
;
12069 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12070 const char *md_shortopts
= "kVQ:sqnO::";
12072 const char *md_shortopts
= "qnO::";
12075 #define OPTION_32 (OPTION_MD_BASE + 0)
12076 #define OPTION_64 (OPTION_MD_BASE + 1)
12077 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12078 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12079 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12080 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12081 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12082 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12083 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12084 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12085 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12086 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12087 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12088 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12089 #define OPTION_X32 (OPTION_MD_BASE + 14)
12090 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12091 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12092 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12093 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12094 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12095 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12096 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12097 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12098 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12099 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12100 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12101 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12102 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12103 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12104 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12105 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12107 struct option md_longopts
[] =
12109 {"32", no_argument
, NULL
, OPTION_32
},
12110 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12111 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12112 {"64", no_argument
, NULL
, OPTION_64
},
12114 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12115 {"x32", no_argument
, NULL
, OPTION_X32
},
12116 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12117 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12119 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12120 {"march", required_argument
, NULL
, OPTION_MARCH
},
12121 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12122 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12123 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12124 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12125 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12126 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12127 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12128 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12129 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12130 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12131 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12132 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12133 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12134 # if defined (TE_PE) || defined (TE_PEP)
12135 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12137 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12138 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12139 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12140 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12141 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12142 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12143 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12144 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12145 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12146 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12147 {NULL
, no_argument
, NULL
, 0}
12149 size_t md_longopts_size
= sizeof (md_longopts
);
12152 md_parse_option (int c
, const char *arg
)
12155 char *arch
, *next
, *saved
, *type
;
12160 optimize_align_code
= 0;
12164 quiet_warnings
= 1;
12167 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12168 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12169 should be emitted or not. FIXME: Not implemented. */
12171 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12175 /* -V: SVR4 argument to print version ID. */
12177 print_version_id ();
12180 /* -k: Ignore for FreeBSD compatibility. */
12185 /* -s: On i386 Solaris, this tells the native assembler to use
12186 .stab instead of .stab.excl. We always use .stab anyhow. */
12189 case OPTION_MSHARED
:
12193 case OPTION_X86_USED_NOTE
:
12194 if (strcasecmp (arg
, "yes") == 0)
12196 else if (strcasecmp (arg
, "no") == 0)
12199 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12204 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12205 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12208 const char **list
, **l
;
12210 list
= bfd_target_list ();
12211 for (l
= list
; *l
!= NULL
; l
++)
12212 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12213 || strcmp (*l
, "coff-x86-64") == 0
12214 || strcmp (*l
, "pe-x86-64") == 0
12215 || strcmp (*l
, "pei-x86-64") == 0
12216 || strcmp (*l
, "mach-o-x86-64") == 0)
12218 default_arch
= "x86_64";
12222 as_fatal (_("no compiled in support for x86_64"));
12228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12232 const char **list
, **l
;
12234 list
= bfd_target_list ();
12235 for (l
= list
; *l
!= NULL
; l
++)
12236 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12238 default_arch
= "x86_64:32";
12242 as_fatal (_("no compiled in support for 32bit x86_64"));
12246 as_fatal (_("32bit x86_64 is only supported for ELF"));
12251 default_arch
= "i386";
12254 case OPTION_DIVIDE
:
12255 #ifdef SVR4_COMMENT_CHARS
12260 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12262 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12266 i386_comment_chars
= n
;
12272 saved
= xstrdup (arg
);
12274 /* Allow -march=+nosse. */
12280 as_fatal (_("invalid -march= option: `%s'"), arg
);
12281 next
= strchr (arch
, '+');
12284 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12286 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12289 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12292 cpu_arch_name
= cpu_arch
[j
].name
;
12293 cpu_sub_arch_name
= NULL
;
12294 cpu_arch_flags
= cpu_arch
[j
].flags
;
12295 cpu_arch_isa
= cpu_arch
[j
].type
;
12296 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12297 if (!cpu_arch_tune_set
)
12299 cpu_arch_tune
= cpu_arch_isa
;
12300 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12304 else if (*cpu_arch
[j
].name
== '.'
12305 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12307 /* ISA extension. */
12308 i386_cpu_flags flags
;
12310 flags
= cpu_flags_or (cpu_arch_flags
,
12311 cpu_arch
[j
].flags
);
12313 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12315 if (cpu_sub_arch_name
)
12317 char *name
= cpu_sub_arch_name
;
12318 cpu_sub_arch_name
= concat (name
,
12320 (const char *) NULL
);
12324 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12325 cpu_arch_flags
= flags
;
12326 cpu_arch_isa_flags
= flags
;
12330 = cpu_flags_or (cpu_arch_isa_flags
,
12331 cpu_arch
[j
].flags
);
12336 if (j
>= ARRAY_SIZE (cpu_arch
))
12338 /* Disable an ISA extension. */
12339 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12340 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12342 i386_cpu_flags flags
;
12344 flags
= cpu_flags_and_not (cpu_arch_flags
,
12345 cpu_noarch
[j
].flags
);
12346 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12348 if (cpu_sub_arch_name
)
12350 char *name
= cpu_sub_arch_name
;
12351 cpu_sub_arch_name
= concat (arch
,
12352 (const char *) NULL
);
12356 cpu_sub_arch_name
= xstrdup (arch
);
12357 cpu_arch_flags
= flags
;
12358 cpu_arch_isa_flags
= flags
;
12363 if (j
>= ARRAY_SIZE (cpu_noarch
))
12364 j
= ARRAY_SIZE (cpu_arch
);
12367 if (j
>= ARRAY_SIZE (cpu_arch
))
12368 as_fatal (_("invalid -march= option: `%s'"), arg
);
12372 while (next
!= NULL
);
12378 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12379 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12381 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12383 cpu_arch_tune_set
= 1;
12384 cpu_arch_tune
= cpu_arch
[j
].type
;
12385 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12389 if (j
>= ARRAY_SIZE (cpu_arch
))
12390 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12393 case OPTION_MMNEMONIC
:
12394 if (strcasecmp (arg
, "att") == 0)
12395 intel_mnemonic
= 0;
12396 else if (strcasecmp (arg
, "intel") == 0)
12397 intel_mnemonic
= 1;
12399 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12402 case OPTION_MSYNTAX
:
12403 if (strcasecmp (arg
, "att") == 0)
12405 else if (strcasecmp (arg
, "intel") == 0)
12408 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12411 case OPTION_MINDEX_REG
:
12412 allow_index_reg
= 1;
12415 case OPTION_MNAKED_REG
:
12416 allow_naked_reg
= 1;
12419 case OPTION_MSSE2AVX
:
12423 case OPTION_MSSE_CHECK
:
12424 if (strcasecmp (arg
, "error") == 0)
12425 sse_check
= check_error
;
12426 else if (strcasecmp (arg
, "warning") == 0)
12427 sse_check
= check_warning
;
12428 else if (strcasecmp (arg
, "none") == 0)
12429 sse_check
= check_none
;
12431 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12434 case OPTION_MOPERAND_CHECK
:
12435 if (strcasecmp (arg
, "error") == 0)
12436 operand_check
= check_error
;
12437 else if (strcasecmp (arg
, "warning") == 0)
12438 operand_check
= check_warning
;
12439 else if (strcasecmp (arg
, "none") == 0)
12440 operand_check
= check_none
;
12442 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12445 case OPTION_MAVXSCALAR
:
12446 if (strcasecmp (arg
, "128") == 0)
12447 avxscalar
= vex128
;
12448 else if (strcasecmp (arg
, "256") == 0)
12449 avxscalar
= vex256
;
12451 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12454 case OPTION_MVEXWIG
:
12455 if (strcmp (arg
, "0") == 0)
12457 else if (strcmp (arg
, "1") == 0)
12460 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12463 case OPTION_MADD_BND_PREFIX
:
12464 add_bnd_prefix
= 1;
12467 case OPTION_MEVEXLIG
:
12468 if (strcmp (arg
, "128") == 0)
12469 evexlig
= evexl128
;
12470 else if (strcmp (arg
, "256") == 0)
12471 evexlig
= evexl256
;
12472 else if (strcmp (arg
, "512") == 0)
12473 evexlig
= evexl512
;
12475 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12478 case OPTION_MEVEXRCIG
:
12479 if (strcmp (arg
, "rne") == 0)
12481 else if (strcmp (arg
, "rd") == 0)
12483 else if (strcmp (arg
, "ru") == 0)
12485 else if (strcmp (arg
, "rz") == 0)
12488 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12491 case OPTION_MEVEXWIG
:
12492 if (strcmp (arg
, "0") == 0)
12494 else if (strcmp (arg
, "1") == 0)
12497 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12500 # if defined (TE_PE) || defined (TE_PEP)
12501 case OPTION_MBIG_OBJ
:
12506 case OPTION_MOMIT_LOCK_PREFIX
:
12507 if (strcasecmp (arg
, "yes") == 0)
12508 omit_lock_prefix
= 1;
12509 else if (strcasecmp (arg
, "no") == 0)
12510 omit_lock_prefix
= 0;
12512 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12515 case OPTION_MFENCE_AS_LOCK_ADD
:
12516 if (strcasecmp (arg
, "yes") == 0)
12518 else if (strcasecmp (arg
, "no") == 0)
12521 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12524 case OPTION_MRELAX_RELOCATIONS
:
12525 if (strcasecmp (arg
, "yes") == 0)
12526 generate_relax_relocations
= 1;
12527 else if (strcasecmp (arg
, "no") == 0)
12528 generate_relax_relocations
= 0;
12530 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12533 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12536 long int align
= strtoul (arg
, &end
, 0);
12541 align_branch_power
= 0;
12544 else if (align
>= 16)
12547 for (align_power
= 0;
12549 align
>>= 1, align_power
++)
12551 /* Limit alignment power to 31. */
12552 if (align
== 1 && align_power
< 32)
12554 align_branch_power
= align_power
;
12559 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12563 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12566 int align
= strtoul (arg
, &end
, 0);
12567 /* Some processors only support 5 prefixes. */
12568 if (*end
== '\0' && align
>= 0 && align
< 6)
12570 align_branch_prefix_size
= align
;
12573 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12578 case OPTION_MALIGN_BRANCH
:
12580 saved
= xstrdup (arg
);
12584 next
= strchr (type
, '+');
12587 if (strcasecmp (type
, "jcc") == 0)
12588 align_branch
|= align_branch_jcc_bit
;
12589 else if (strcasecmp (type
, "fused") == 0)
12590 align_branch
|= align_branch_fused_bit
;
12591 else if (strcasecmp (type
, "jmp") == 0)
12592 align_branch
|= align_branch_jmp_bit
;
12593 else if (strcasecmp (type
, "call") == 0)
12594 align_branch
|= align_branch_call_bit
;
12595 else if (strcasecmp (type
, "ret") == 0)
12596 align_branch
|= align_branch_ret_bit
;
12597 else if (strcasecmp (type
, "indirect") == 0)
12598 align_branch
|= align_branch_indirect_bit
;
12600 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12603 while (next
!= NULL
);
12607 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12608 align_branch_power
= 5;
12609 align_branch_prefix_size
= 5;
12610 align_branch
= (align_branch_jcc_bit
12611 | align_branch_fused_bit
12612 | align_branch_jmp_bit
);
12615 case OPTION_MAMD64
:
12619 case OPTION_MINTEL64
:
12627 /* Turn off -Os. */
12628 optimize_for_space
= 0;
12630 else if (*arg
== 's')
12632 optimize_for_space
= 1;
12633 /* Turn on all encoding optimizations. */
12634 optimize
= INT_MAX
;
12638 optimize
= atoi (arg
);
12639 /* Turn off -Os. */
12640 optimize_for_space
= 0;
12650 #define MESSAGE_TEMPLATE \
12654 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12655 int *left_p
, const char *name
, int len
)
12657 int size
= sizeof (MESSAGE_TEMPLATE
);
12658 int left
= *left_p
;
12660 /* Reserve 2 spaces for ", " or ",\0" */
12663 /* Check if there is any room. */
12671 p
= mempcpy (p
, name
, len
);
12675 /* Output the current message now and start a new one. */
12678 fprintf (stream
, "%s\n", message
);
12680 left
= size
- (start
- message
) - len
- 2;
12682 gas_assert (left
>= 0);
12684 p
= mempcpy (p
, name
, len
);
12692 show_arch (FILE *stream
, int ext
, int check
)
12694 static char message
[] = MESSAGE_TEMPLATE
;
12695 char *start
= message
+ 27;
12697 int size
= sizeof (MESSAGE_TEMPLATE
);
12704 left
= size
- (start
- message
);
12705 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12707 /* Should it be skipped? */
12708 if (cpu_arch
[j
].skip
)
12711 name
= cpu_arch
[j
].name
;
12712 len
= cpu_arch
[j
].len
;
12715 /* It is an extension. Skip if we aren't asked to show it. */
12726 /* It is an processor. Skip if we show only extension. */
12729 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12731 /* It is an impossible processor - skip. */
12735 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12738 /* Display disabled extensions. */
12740 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12742 name
= cpu_noarch
[j
].name
;
12743 len
= cpu_noarch
[j
].len
;
12744 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12749 fprintf (stream
, "%s\n", message
);
12753 md_show_usage (FILE *stream
)
12755 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12756 fprintf (stream
, _("\
12757 -Qy, -Qn ignored\n\
12758 -V print assembler version number\n\
12761 fprintf (stream
, _("\
12762 -n Do not optimize code alignment\n\
12763 -q quieten some warnings\n"));
12764 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12765 fprintf (stream
, _("\
12768 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12769 || defined (TE_PE) || defined (TE_PEP))
12770 fprintf (stream
, _("\
12771 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12773 #ifdef SVR4_COMMENT_CHARS
12774 fprintf (stream
, _("\
12775 --divide do not treat `/' as a comment character\n"));
12777 fprintf (stream
, _("\
12778 --divide ignored\n"));
12780 fprintf (stream
, _("\
12781 -march=CPU[,+EXTENSION...]\n\
12782 generate code for CPU and EXTENSION, CPU is one of:\n"));
12783 show_arch (stream
, 0, 1);
12784 fprintf (stream
, _("\
12785 EXTENSION is combination of:\n"));
12786 show_arch (stream
, 1, 0);
12787 fprintf (stream
, _("\
12788 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12789 show_arch (stream
, 0, 0);
12790 fprintf (stream
, _("\
12791 -msse2avx encode SSE instructions with VEX prefix\n"));
12792 fprintf (stream
, _("\
12793 -msse-check=[none|error|warning] (default: warning)\n\
12794 check SSE instructions\n"));
12795 fprintf (stream
, _("\
12796 -moperand-check=[none|error|warning] (default: warning)\n\
12797 check operand combinations for validity\n"));
12798 fprintf (stream
, _("\
12799 -mavxscalar=[128|256] (default: 128)\n\
12800 encode scalar AVX instructions with specific vector\n\
12802 fprintf (stream
, _("\
12803 -mvexwig=[0|1] (default: 0)\n\
12804 encode VEX instructions with specific VEX.W value\n\
12805 for VEX.W bit ignored instructions\n"));
12806 fprintf (stream
, _("\
12807 -mevexlig=[128|256|512] (default: 128)\n\
12808 encode scalar EVEX instructions with specific vector\n\
12810 fprintf (stream
, _("\
12811 -mevexwig=[0|1] (default: 0)\n\
12812 encode EVEX instructions with specific EVEX.W value\n\
12813 for EVEX.W bit ignored instructions\n"));
12814 fprintf (stream
, _("\
12815 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12816 encode EVEX instructions with specific EVEX.RC value\n\
12817 for SAE-only ignored instructions\n"));
12818 fprintf (stream
, _("\
12819 -mmnemonic=[att|intel] "));
12820 if (SYSV386_COMPAT
)
12821 fprintf (stream
, _("(default: att)\n"));
12823 fprintf (stream
, _("(default: intel)\n"));
12824 fprintf (stream
, _("\
12825 use AT&T/Intel mnemonic\n"));
12826 fprintf (stream
, _("\
12827 -msyntax=[att|intel] (default: att)\n\
12828 use AT&T/Intel syntax\n"));
12829 fprintf (stream
, _("\
12830 -mindex-reg support pseudo index registers\n"));
12831 fprintf (stream
, _("\
12832 -mnaked-reg don't require `%%' prefix for registers\n"));
12833 fprintf (stream
, _("\
12834 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12836 fprintf (stream
, _("\
12837 -mshared disable branch optimization for shared code\n"));
12838 fprintf (stream
, _("\
12839 -mx86-used-note=[no|yes] "));
12840 if (DEFAULT_X86_USED_NOTE
)
12841 fprintf (stream
, _("(default: yes)\n"));
12843 fprintf (stream
, _("(default: no)\n"));
12844 fprintf (stream
, _("\
12845 generate x86 used ISA and feature properties\n"));
12847 #if defined (TE_PE) || defined (TE_PEP)
12848 fprintf (stream
, _("\
12849 -mbig-obj generate big object files\n"));
12851 fprintf (stream
, _("\
12852 -momit-lock-prefix=[no|yes] (default: no)\n\
12853 strip all lock prefixes\n"));
12854 fprintf (stream
, _("\
12855 -mfence-as-lock-add=[no|yes] (default: no)\n\
12856 encode lfence, mfence and sfence as\n\
12857 lock addl $0x0, (%%{re}sp)\n"));
12858 fprintf (stream
, _("\
12859 -mrelax-relocations=[no|yes] "));
12860 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12861 fprintf (stream
, _("(default: yes)\n"));
12863 fprintf (stream
, _("(default: no)\n"));
12864 fprintf (stream
, _("\
12865 generate relax relocations\n"));
12866 fprintf (stream
, _("\
12867 -malign-branch-boundary=NUM (default: 0)\n\
12868 align branches within NUM byte boundary\n"));
12869 fprintf (stream
, _("\
12870 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12871 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12873 specify types of branches to align\n"));
12874 fprintf (stream
, _("\
12875 -malign-branch-prefix-size=NUM (default: 5)\n\
12876 align branches with NUM prefixes per instruction\n"));
12877 fprintf (stream
, _("\
12878 -mbranches-within-32B-boundaries\n\
12879 align branches within 32 byte boundary\n"));
12880 fprintf (stream
, _("\
12881 -mamd64 accept only AMD64 ISA [default]\n"));
12882 fprintf (stream
, _("\
12883 -mintel64 accept only Intel64 ISA\n"));
12886 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12887 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12888 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12890 /* Pick the target format to use. */
12893 i386_target_format (void)
12895 if (!strncmp (default_arch
, "x86_64", 6))
12897 update_code_flag (CODE_64BIT
, 1);
12898 if (default_arch
[6] == '\0')
12899 x86_elf_abi
= X86_64_ABI
;
12901 x86_elf_abi
= X86_64_X32_ABI
;
12903 else if (!strcmp (default_arch
, "i386"))
12904 update_code_flag (CODE_32BIT
, 1);
12905 else if (!strcmp (default_arch
, "iamcu"))
12907 update_code_flag (CODE_32BIT
, 1);
12908 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12910 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12911 cpu_arch_name
= "iamcu";
12912 cpu_sub_arch_name
= NULL
;
12913 cpu_arch_flags
= iamcu_flags
;
12914 cpu_arch_isa
= PROCESSOR_IAMCU
;
12915 cpu_arch_isa_flags
= iamcu_flags
;
12916 if (!cpu_arch_tune_set
)
12918 cpu_arch_tune
= cpu_arch_isa
;
12919 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12922 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12923 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12927 as_fatal (_("unknown architecture"));
12929 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12930 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12931 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12932 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12934 switch (OUTPUT_FLAVOR
)
12936 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12937 case bfd_target_aout_flavour
:
12938 return AOUT_TARGET_FORMAT
;
12940 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12941 # if defined (TE_PE) || defined (TE_PEP)
12942 case bfd_target_coff_flavour
:
12943 if (flag_code
== CODE_64BIT
)
12944 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12947 # elif defined (TE_GO32)
12948 case bfd_target_coff_flavour
:
12949 return "coff-go32";
12951 case bfd_target_coff_flavour
:
12952 return "coff-i386";
12955 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12956 case bfd_target_elf_flavour
:
12958 const char *format
;
12960 switch (x86_elf_abi
)
12963 format
= ELF_TARGET_FORMAT
;
12965 tls_get_addr
= "___tls_get_addr";
12969 use_rela_relocations
= 1;
12972 tls_get_addr
= "__tls_get_addr";
12974 format
= ELF_TARGET_FORMAT64
;
12976 case X86_64_X32_ABI
:
12977 use_rela_relocations
= 1;
12980 tls_get_addr
= "__tls_get_addr";
12982 disallow_64bit_reloc
= 1;
12983 format
= ELF_TARGET_FORMAT32
;
12986 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12988 if (x86_elf_abi
!= X86_64_ABI
)
12989 as_fatal (_("Intel L1OM is 64bit only"));
12990 return ELF_TARGET_L1OM_FORMAT
;
12992 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12994 if (x86_elf_abi
!= X86_64_ABI
)
12995 as_fatal (_("Intel K1OM is 64bit only"));
12996 return ELF_TARGET_K1OM_FORMAT
;
12998 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
13000 if (x86_elf_abi
!= I386_ABI
)
13001 as_fatal (_("Intel MCU is 32bit only"));
13002 return ELF_TARGET_IAMCU_FORMAT
;
13008 #if defined (OBJ_MACH_O)
13009 case bfd_target_mach_o_flavour
:
13010 if (flag_code
== CODE_64BIT
)
13012 use_rela_relocations
= 1;
13014 return "mach-o-x86-64";
13017 return "mach-o-i386";
13025 #endif /* OBJ_MAYBE_ more than one */
13028 md_undefined_symbol (char *name
)
13030 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
13031 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
13032 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
13033 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
13037 if (symbol_find (name
))
13038 as_bad (_("GOT already in symbol table"));
13039 GOT_symbol
= symbol_new (name
, undefined_section
,
13040 (valueT
) 0, &zero_address_frag
);
13047 /* Round up a section size to the appropriate boundary. */
13050 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
13052 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13053 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
13055 /* For a.out, force the section size to be aligned. If we don't do
13056 this, BFD will align it for us, but it will not write out the
13057 final bytes of the section. This may be a bug in BFD, but it is
13058 easier to fix it here since that is how the other a.out targets
13062 align
= bfd_section_alignment (segment
);
13063 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13070 /* On the i386, PC-relative offsets are relative to the start of the
13071 next instruction. That is, the address of the offset, plus its
13072 size, since the offset is always the last part of the insn. */
13075 md_pcrel_from (fixS
*fixP
)
13077 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13083 s_bss (int ignore ATTRIBUTE_UNUSED
)
13087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13089 obj_elf_section_change_hook ();
13091 temp
= get_absolute_expression ();
13092 subseg_set (bss_section
, (subsegT
) temp
);
13093 demand_empty_rest_of_line ();
13098 /* Remember constant directive. */
13101 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13103 if (last_insn
.kind
!= last_insn_directive
13104 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13106 last_insn
.seg
= now_seg
;
13107 last_insn
.kind
= last_insn_directive
;
13108 last_insn
.name
= "constant directive";
13109 last_insn
.file
= as_where (&last_insn
.line
);
13114 i386_validate_fix (fixS
*fixp
)
13116 if (fixp
->fx_subsy
)
13118 if (fixp
->fx_subsy
== GOT_symbol
)
13120 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13124 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13125 if (fixp
->fx_tcbit2
)
13126 fixp
->fx_r_type
= (fixp
->fx_tcbit
13127 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13128 : BFD_RELOC_X86_64_GOTPCRELX
);
13131 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13136 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13138 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13140 fixp
->fx_subsy
= 0;
13143 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13144 else if (!object_64bit
)
13146 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13147 && fixp
->fx_tcbit2
)
13148 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13154 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13157 bfd_reloc_code_real_type code
;
13159 switch (fixp
->fx_r_type
)
13161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13162 case BFD_RELOC_SIZE32
:
13163 case BFD_RELOC_SIZE64
:
13164 if (S_IS_DEFINED (fixp
->fx_addsy
)
13165 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13167 /* Resolve size relocation against local symbol to size of
13168 the symbol plus addend. */
13169 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13170 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13171 && !fits_in_unsigned_long (value
))
13172 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13173 _("symbol size computation overflow"));
13174 fixp
->fx_addsy
= NULL
;
13175 fixp
->fx_subsy
= NULL
;
13176 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13180 /* Fall through. */
13182 case BFD_RELOC_X86_64_PLT32
:
13183 case BFD_RELOC_X86_64_GOT32
:
13184 case BFD_RELOC_X86_64_GOTPCREL
:
13185 case BFD_RELOC_X86_64_GOTPCRELX
:
13186 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13187 case BFD_RELOC_386_PLT32
:
13188 case BFD_RELOC_386_GOT32
:
13189 case BFD_RELOC_386_GOT32X
:
13190 case BFD_RELOC_386_GOTOFF
:
13191 case BFD_RELOC_386_GOTPC
:
13192 case BFD_RELOC_386_TLS_GD
:
13193 case BFD_RELOC_386_TLS_LDM
:
13194 case BFD_RELOC_386_TLS_LDO_32
:
13195 case BFD_RELOC_386_TLS_IE_32
:
13196 case BFD_RELOC_386_TLS_IE
:
13197 case BFD_RELOC_386_TLS_GOTIE
:
13198 case BFD_RELOC_386_TLS_LE_32
:
13199 case BFD_RELOC_386_TLS_LE
:
13200 case BFD_RELOC_386_TLS_GOTDESC
:
13201 case BFD_RELOC_386_TLS_DESC_CALL
:
13202 case BFD_RELOC_X86_64_TLSGD
:
13203 case BFD_RELOC_X86_64_TLSLD
:
13204 case BFD_RELOC_X86_64_DTPOFF32
:
13205 case BFD_RELOC_X86_64_DTPOFF64
:
13206 case BFD_RELOC_X86_64_GOTTPOFF
:
13207 case BFD_RELOC_X86_64_TPOFF32
:
13208 case BFD_RELOC_X86_64_TPOFF64
:
13209 case BFD_RELOC_X86_64_GOTOFF64
:
13210 case BFD_RELOC_X86_64_GOTPC32
:
13211 case BFD_RELOC_X86_64_GOT64
:
13212 case BFD_RELOC_X86_64_GOTPCREL64
:
13213 case BFD_RELOC_X86_64_GOTPC64
:
13214 case BFD_RELOC_X86_64_GOTPLT64
:
13215 case BFD_RELOC_X86_64_PLTOFF64
:
13216 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13217 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13218 case BFD_RELOC_RVA
:
13219 case BFD_RELOC_VTABLE_ENTRY
:
13220 case BFD_RELOC_VTABLE_INHERIT
:
13222 case BFD_RELOC_32_SECREL
:
13224 code
= fixp
->fx_r_type
;
13226 case BFD_RELOC_X86_64_32S
:
13227 if (!fixp
->fx_pcrel
)
13229 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13230 code
= fixp
->fx_r_type
;
13233 /* Fall through. */
13235 if (fixp
->fx_pcrel
)
13237 switch (fixp
->fx_size
)
13240 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13241 _("can not do %d byte pc-relative relocation"),
13243 code
= BFD_RELOC_32_PCREL
;
13245 case 1: code
= BFD_RELOC_8_PCREL
; break;
13246 case 2: code
= BFD_RELOC_16_PCREL
; break;
13247 case 4: code
= BFD_RELOC_32_PCREL
; break;
13249 case 8: code
= BFD_RELOC_64_PCREL
; break;
13255 switch (fixp
->fx_size
)
13258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13259 _("can not do %d byte relocation"),
13261 code
= BFD_RELOC_32
;
13263 case 1: code
= BFD_RELOC_8
; break;
13264 case 2: code
= BFD_RELOC_16
; break;
13265 case 4: code
= BFD_RELOC_32
; break;
13267 case 8: code
= BFD_RELOC_64
; break;
13274 if ((code
== BFD_RELOC_32
13275 || code
== BFD_RELOC_32_PCREL
13276 || code
== BFD_RELOC_X86_64_32S
)
13278 && fixp
->fx_addsy
== GOT_symbol
)
13281 code
= BFD_RELOC_386_GOTPC
;
13283 code
= BFD_RELOC_X86_64_GOTPC32
;
13285 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13287 && fixp
->fx_addsy
== GOT_symbol
)
13289 code
= BFD_RELOC_X86_64_GOTPC64
;
13292 rel
= XNEW (arelent
);
13293 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13294 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13296 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13298 if (!use_rela_relocations
)
13300 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13301 vtable entry to be used in the relocation's section offset. */
13302 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13303 rel
->address
= fixp
->fx_offset
;
13304 #if defined (OBJ_COFF) && defined (TE_PE)
13305 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13306 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13311 /* Use the rela in 64bit mode. */
13314 if (disallow_64bit_reloc
)
13317 case BFD_RELOC_X86_64_DTPOFF64
:
13318 case BFD_RELOC_X86_64_TPOFF64
:
13319 case BFD_RELOC_64_PCREL
:
13320 case BFD_RELOC_X86_64_GOTOFF64
:
13321 case BFD_RELOC_X86_64_GOT64
:
13322 case BFD_RELOC_X86_64_GOTPCREL64
:
13323 case BFD_RELOC_X86_64_GOTPC64
:
13324 case BFD_RELOC_X86_64_GOTPLT64
:
13325 case BFD_RELOC_X86_64_PLTOFF64
:
13326 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13327 _("cannot represent relocation type %s in x32 mode"),
13328 bfd_get_reloc_code_name (code
));
13334 if (!fixp
->fx_pcrel
)
13335 rel
->addend
= fixp
->fx_offset
;
13339 case BFD_RELOC_X86_64_PLT32
:
13340 case BFD_RELOC_X86_64_GOT32
:
13341 case BFD_RELOC_X86_64_GOTPCREL
:
13342 case BFD_RELOC_X86_64_GOTPCRELX
:
13343 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13344 case BFD_RELOC_X86_64_TLSGD
:
13345 case BFD_RELOC_X86_64_TLSLD
:
13346 case BFD_RELOC_X86_64_GOTTPOFF
:
13347 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13348 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13349 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13352 rel
->addend
= (section
->vma
13354 + fixp
->fx_addnumber
13355 + md_pcrel_from (fixp
));
13360 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13361 if (rel
->howto
== NULL
)
13363 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13364 _("cannot represent relocation type %s"),
13365 bfd_get_reloc_code_name (code
));
13366 /* Set howto to a garbage value so that we can keep going. */
13367 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13368 gas_assert (rel
->howto
!= NULL
);
13374 #include "tc-i386-intel.c"
13377 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13379 int saved_naked_reg
;
13380 char saved_register_dot
;
13382 saved_naked_reg
= allow_naked_reg
;
13383 allow_naked_reg
= 1;
13384 saved_register_dot
= register_chars
['.'];
13385 register_chars
['.'] = '.';
13386 allow_pseudo_reg
= 1;
13387 expression_and_evaluate (exp
);
13388 allow_pseudo_reg
= 0;
13389 register_chars
['.'] = saved_register_dot
;
13390 allow_naked_reg
= saved_naked_reg
;
13392 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13394 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13396 exp
->X_op
= O_constant
;
13397 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13398 .dw2_regnum
[flag_code
>> 1];
13401 exp
->X_op
= O_illegal
;
13406 tc_x86_frame_initial_instructions (void)
13408 static unsigned int sp_regno
[2];
13410 if (!sp_regno
[flag_code
>> 1])
13412 char *saved_input
= input_line_pointer
;
13413 char sp
[][4] = {"esp", "rsp"};
13416 input_line_pointer
= sp
[flag_code
>> 1];
13417 tc_x86_parse_to_dw2regnum (&exp
);
13418 gas_assert (exp
.X_op
== O_constant
);
13419 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13420 input_line_pointer
= saved_input
;
13423 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13424 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13428 x86_dwarf2_addr_size (void)
13430 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13431 if (x86_elf_abi
== X86_64_X32_ABI
)
13434 return bfd_arch_bits_per_address (stdoutput
) / 8;
13438 i386_elf_section_type (const char *str
, size_t len
)
13440 if (flag_code
== CODE_64BIT
13441 && len
== sizeof ("unwind") - 1
13442 && strncmp (str
, "unwind", 6) == 0)
13443 return SHT_X86_64_UNWIND
;
13450 i386_solaris_fix_up_eh_frame (segT sec
)
13452 if (flag_code
== CODE_64BIT
)
13453 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13459 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13463 exp
.X_op
= O_secrel
;
13464 exp
.X_add_symbol
= symbol
;
13465 exp
.X_add_number
= 0;
13466 emit_expr (&exp
, size
);
13470 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13471 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13474 x86_64_section_letter (int letter
, const char **ptr_msg
)
13476 if (flag_code
== CODE_64BIT
)
13479 return SHF_X86_64_LARGE
;
13481 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13484 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13489 x86_64_section_word (char *str
, size_t len
)
13491 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13492 return SHF_X86_64_LARGE
;
13498 handle_large_common (int small ATTRIBUTE_UNUSED
)
13500 if (flag_code
!= CODE_64BIT
)
13502 s_comm_internal (0, elf_common_parse
);
13503 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13507 static segT lbss_section
;
13508 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13509 asection
*saved_bss_section
= bss_section
;
13511 if (lbss_section
== NULL
)
13513 flagword applicable
;
13514 segT seg
= now_seg
;
13515 subsegT subseg
= now_subseg
;
13517 /* The .lbss section is for local .largecomm symbols. */
13518 lbss_section
= subseg_new (".lbss", 0);
13519 applicable
= bfd_applicable_section_flags (stdoutput
);
13520 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13521 seg_info (lbss_section
)->bss
= 1;
13523 subseg_set (seg
, subseg
);
13526 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13527 bss_section
= lbss_section
;
13529 s_comm_internal (0, elf_common_parse
);
13531 elf_com_section_ptr
= saved_com_section_ptr
;
13532 bss_section
= saved_bss_section
;
13535 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */