1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
317 static const char *cpu_sub_arch_name
= NULL
;
319 /* CPU feature flags. */
320 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
322 /* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324 static unsigned int no_cond_jump_promotion
= 0;
326 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327 static symbolS
*GOT_symbol
;
329 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
330 unsigned int x86_dwarf2_return_column
;
332 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333 int x86_cie_data_alignment
;
335 /* Interface to relax_segment.
336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
341 #define UNCOND_JUMP 0
343 #define COND_JUMP86 2
348 #define SMALL16 (SMALL | CODE16)
350 #define BIG16 (BIG | CODE16)
354 #define INLINE __inline__
360 #define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362 #define TYPE_FROM_RELAX_STATE(s) \
364 #define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
367 /* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
375 const relax_typeS md_relax_table
[] =
378 1) most positive reach of this state,
379 2) most negative reach of this state,
380 3) how many bytes this mode will have in the variable part of the frag
381 4) which index into the table to try if we can't fit into this one. */
383 /* UNCOND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 3 bytes to frag:
400 1 extra opcode byte, 2 displacement bytes. */
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
414 static const arch_entry cpu_arch
[] = {
416 {"i186", Cpu086
|Cpu186
},
417 {"i286", Cpu086
|Cpu186
|Cpu286
},
418 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
419 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
420 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
421 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
422 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
423 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
424 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
425 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
426 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
427 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
428 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
429 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
430 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
431 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
433 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
434 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
435 {".3dnow", CpuMMX
|Cpu3dnow
},
436 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
437 {".padlock", CpuPadLock
},
441 const pseudo_typeS md_pseudo_table
[] =
443 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes
, 0},
446 {"align", s_align_ptwo
, 0},
448 {"arch", set_cpu_arch
, 0},
452 {"ffloat", float_cons
, 'f'},
453 {"dfloat", float_cons
, 'd'},
454 {"tfloat", float_cons
, 'x'},
456 {"noopt", s_ignore
, 0},
457 {"optim", s_ignore
, 0},
458 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
459 {"code16", set_code_flag
, CODE_16BIT
},
460 {"code32", set_code_flag
, CODE_32BIT
},
461 {"code64", set_code_flag
, CODE_64BIT
},
462 {"intel_syntax", set_intel_syntax
, 1},
463 {"att_syntax", set_intel_syntax
, 0},
464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
465 {"loc", dwarf2_directive_loc
, 0},
467 {"secrel32", pe_directive_secrel
, 0},
472 /* For interface with expression (). */
473 extern char *input_line_pointer
;
475 /* Hash table for instruction mnemonic lookup. */
476 static struct hash_control
*op_hash
;
478 /* Hash table for register lookup. */
479 static struct hash_control
*reg_hash
;
482 i386_align_code (fragP
, count
)
486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
489 static const char f32_1
[] =
491 static const char f32_2
[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3
[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4
[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5
[] =
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6
[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7
[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8
[] =
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9
[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10
[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11
[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12
[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13
[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14
[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15
[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
528 static const char f16_3
[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
530 static const char f16_4
[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5
[] =
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6
[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7
[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8
[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt
[] = {
545 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
546 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
548 static const char *const f16_patt
[] = {
549 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
550 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
553 if (count
<= 0 || count
> 15)
556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code
== CODE_64BIT
)
561 int nnops
= (count
+ 3) / 4;
562 int len
= count
/ nnops
;
563 int remains
= count
- nnops
* len
;
566 for (i
= 0; i
< remains
; i
++)
568 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
569 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
572 for (; i
< nnops
; i
++)
574 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
575 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
580 if (flag_code
== CODE_16BIT
)
582 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
583 f16_patt
[count
- 1], count
);
585 /* Adjust jump offset. */
586 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
589 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
590 f32_patt
[count
- 1], count
);
591 fragP
->fr_var
= count
;
594 static INLINE
unsigned int
595 mode_from_disp_size (t
)
598 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
602 fits_in_signed_byte (num
)
605 return (num
>= -128) && (num
<= 127);
609 fits_in_unsigned_byte (num
)
612 return (num
& 0xff) == num
;
616 fits_in_unsigned_word (num
)
619 return (num
& 0xffff) == num
;
623 fits_in_signed_word (num
)
626 return (-32768 <= num
) && (num
<= 32767);
629 fits_in_signed_long (num
)
630 offsetT num ATTRIBUTE_UNUSED
;
635 return (!(((offsetT
) -1 << 31) & num
)
636 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
638 } /* fits_in_signed_long() */
640 fits_in_unsigned_long (num
)
641 offsetT num ATTRIBUTE_UNUSED
;
646 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
648 } /* fits_in_unsigned_long() */
651 smallest_imm_type (num
)
654 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
662 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
664 return (fits_in_signed_byte (num
)
665 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
666 : fits_in_unsigned_byte (num
)
667 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
668 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
669 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
670 : fits_in_signed_long (num
)
671 ? (Imm32
| Imm32S
| Imm64
)
672 : fits_in_unsigned_long (num
)
678 offset_in_range (val
, size
)
686 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
687 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
688 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
690 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
695 /* If BFD64, sign extend val. */
696 if (!use_rela_relocations
)
697 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
698 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
700 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
702 char buf1
[40], buf2
[40];
704 sprint_value (buf1
, val
);
705 sprint_value (buf2
, val
& mask
);
706 as_warn (_("%s shortened to %s"), buf1
, buf2
);
711 /* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
722 && flag_code
== CODE_64BIT
)
730 case CS_PREFIX_OPCODE
:
731 case DS_PREFIX_OPCODE
:
732 case ES_PREFIX_OPCODE
:
733 case FS_PREFIX_OPCODE
:
734 case GS_PREFIX_OPCODE
:
735 case SS_PREFIX_OPCODE
:
739 case REPNE_PREFIX_OPCODE
:
740 case REPE_PREFIX_OPCODE
:
743 case LOCK_PREFIX_OPCODE
:
751 case ADDR_PREFIX_OPCODE
:
755 case DATA_PREFIX_OPCODE
:
760 if (i
.prefix
[q
] != 0)
762 as_bad (_("same type of prefix used twice"));
767 i
.prefix
[q
] = prefix
;
772 set_code_flag (value
)
776 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
777 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
778 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
780 as_bad (_("64bit mode not supported on this CPU."));
782 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
784 as_bad (_("32bit mode not supported on this CPU."));
790 set_16bit_gcc_code_flag (new_code_flag
)
793 flag_code
= new_code_flag
;
794 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
795 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
796 stackop_size
= LONG_MNEM_SUFFIX
;
800 set_intel_syntax (syntax_flag
)
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg
= 0;
807 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
809 char *string
= input_line_pointer
;
810 int e
= get_symbol_end ();
812 if (strcmp (string
, "prefix") == 0)
814 else if (strcmp (string
, "noprefix") == 0)
817 as_bad (_("bad argument to syntax directive."));
818 *input_line_pointer
= e
;
820 demand_empty_rest_of_line ();
822 intel_syntax
= syntax_flag
;
824 if (ask_naked_reg
== 0)
825 allow_naked_reg
= (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
828 allow_naked_reg
= (ask_naked_reg
< 0);
830 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
831 identifier_chars
['$'] = intel_syntax
? '$' : 0;
836 int dummy ATTRIBUTE_UNUSED
;
840 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
842 char *string
= input_line_pointer
;
843 int e
= get_symbol_end ();
846 for (i
= 0; cpu_arch
[i
].name
; i
++)
848 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
852 cpu_arch_name
= cpu_arch
[i
].name
;
853 cpu_sub_arch_name
= NULL
;
854 cpu_arch_flags
= (cpu_arch
[i
].flags
855 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
858 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
860 cpu_sub_arch_name
= cpu_arch
[i
].name
;
861 cpu_arch_flags
|= cpu_arch
[i
].flags
;
863 *input_line_pointer
= e
;
864 demand_empty_rest_of_line ();
868 if (!cpu_arch
[i
].name
)
869 as_bad (_("no such architecture: `%s'"), string
);
871 *input_line_pointer
= e
;
874 as_bad (_("missing cpu architecture"));
876 no_cond_jump_promotion
= 0;
877 if (*input_line_pointer
== ','
878 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
880 char *string
= ++input_line_pointer
;
881 int e
= get_symbol_end ();
883 if (strcmp (string
, "nojumps") == 0)
884 no_cond_jump_promotion
= 1;
885 else if (strcmp (string
, "jumps") == 0)
888 as_bad (_("no such architecture modifier: `%s'"), string
);
890 *input_line_pointer
= e
;
893 demand_empty_rest_of_line ();
899 if (!strcmp (default_arch
, "x86_64"))
900 return bfd_mach_x86_64
;
901 else if (!strcmp (default_arch
, "i386"))
902 return bfd_mach_i386_i386
;
904 as_fatal (_("Unknown architecture"));
910 const char *hash_err
;
912 /* Initialize op_hash hash table. */
913 op_hash
= hash_new ();
916 const template *optab
;
917 templates
*core_optab
;
919 /* Setup for loop. */
921 core_optab
= (templates
*) xmalloc (sizeof (templates
));
922 core_optab
->start
= optab
;
927 if (optab
->name
== NULL
928 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
930 /* different name --> ship out current template list;
931 add to hash table; & begin anew. */
932 core_optab
->end
= optab
;
933 hash_err
= hash_insert (op_hash
,
938 as_fatal (_("Internal Error: Can't hash %s: %s"),
942 if (optab
->name
== NULL
)
944 core_optab
= (templates
*) xmalloc (sizeof (templates
));
945 core_optab
->start
= optab
;
950 /* Initialize reg_hash hash table. */
951 reg_hash
= hash_new ();
953 const reg_entry
*regtab
;
955 for (regtab
= i386_regtab
;
956 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
959 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
961 as_fatal (_("Internal Error: Can't hash %s: %s"),
967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
972 for (c
= 0; c
< 256; c
++)
977 mnemonic_chars
[c
] = c
;
978 register_chars
[c
] = c
;
979 operand_chars
[c
] = c
;
981 else if (ISLOWER (c
))
983 mnemonic_chars
[c
] = c
;
984 register_chars
[c
] = c
;
985 operand_chars
[c
] = c
;
987 else if (ISUPPER (c
))
989 mnemonic_chars
[c
] = TOLOWER (c
);
990 register_chars
[c
] = mnemonic_chars
[c
];
991 operand_chars
[c
] = c
;
994 if (ISALPHA (c
) || ISDIGIT (c
))
995 identifier_chars
[c
] = c
;
998 identifier_chars
[c
] = c
;
999 operand_chars
[c
] = c
;
1004 identifier_chars
['@'] = '@';
1007 identifier_chars
['?'] = '?';
1008 operand_chars
['?'] = '?';
1010 digit_chars
['-'] = '-';
1011 mnemonic_chars
['-'] = '-';
1012 identifier_chars
['_'] = '_';
1013 identifier_chars
['.'] = '.';
1015 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1016 operand_chars
[(unsigned char) *p
] = *p
;
1019 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1020 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1022 record_alignment (text_section
, 2);
1023 record_alignment (data_section
, 2);
1024 record_alignment (bss_section
, 2);
1028 if (flag_code
== CODE_64BIT
)
1030 x86_dwarf2_return_column
= 16;
1031 x86_cie_data_alignment
= -8;
1035 x86_dwarf2_return_column
= 8;
1036 x86_cie_data_alignment
= -4;
1041 i386_print_statistics (file
)
1044 hash_print_statistics (file
, "i386 opcode", op_hash
);
1045 hash_print_statistics (file
, "i386 register", reg_hash
);
1050 /* Debugging routines for md_assemble. */
1051 static void pi
PARAMS ((char *, i386_insn
*));
1052 static void pte
PARAMS ((template *));
1053 static void pt
PARAMS ((unsigned int));
1054 static void pe
PARAMS ((expressionS
*));
1055 static void ps
PARAMS ((symbolS
*));
1064 fprintf (stdout
, "%s: template ", line
);
1066 fprintf (stdout
, " address: base %s index %s scale %x\n",
1067 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1068 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1069 x
->log2_scale_factor
);
1070 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1071 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1072 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1073 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1074 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1075 (x
->rex
& REX_MODE64
) != 0,
1076 (x
->rex
& REX_EXTX
) != 0,
1077 (x
->rex
& REX_EXTY
) != 0,
1078 (x
->rex
& REX_EXTZ
) != 0);
1079 for (i
= 0; i
< x
->operands
; i
++)
1081 fprintf (stdout
, " #%d: ", i
+ 1);
1083 fprintf (stdout
, "\n");
1085 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1086 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1087 if (x
->types
[i
] & Imm
)
1089 if (x
->types
[i
] & Disp
)
1090 pe (x
->op
[i
].disps
);
1099 fprintf (stdout
, " %d operands ", t
->operands
);
1100 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1101 if (t
->extension_opcode
!= None
)
1102 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1103 if (t
->opcode_modifier
& D
)
1104 fprintf (stdout
, "D");
1105 if (t
->opcode_modifier
& W
)
1106 fprintf (stdout
, "W");
1107 fprintf (stdout
, "\n");
1108 for (i
= 0; i
< t
->operands
; i
++)
1110 fprintf (stdout
, " #%d type ", i
+ 1);
1111 pt (t
->operand_types
[i
]);
1112 fprintf (stdout
, "\n");
1120 fprintf (stdout
, " operation %d\n", e
->X_op
);
1121 fprintf (stdout
, " add_number %ld (%lx)\n",
1122 (long) e
->X_add_number
, (long) e
->X_add_number
);
1123 if (e
->X_add_symbol
)
1125 fprintf (stdout
, " add_symbol ");
1126 ps (e
->X_add_symbol
);
1127 fprintf (stdout
, "\n");
1131 fprintf (stdout
, " op_symbol ");
1132 ps (e
->X_op_symbol
);
1133 fprintf (stdout
, "\n");
1141 fprintf (stdout
, "%s type %s%s",
1143 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1144 segment_name (S_GET_SEGMENT (s
)));
1153 static const type_names
[] =
1166 { BaseIndex
, "BaseIndex" },
1170 { Disp32S
, "d32s" },
1172 { InOutPortReg
, "InOutPortReg" },
1173 { ShiftCount
, "ShiftCount" },
1174 { Control
, "control reg" },
1175 { Test
, "test reg" },
1176 { Debug
, "debug reg" },
1177 { FloatReg
, "FReg" },
1178 { FloatAcc
, "FAcc" },
1182 { JumpAbsolute
, "Jump Absolute" },
1193 const struct type_name
*ty
;
1195 for (ty
= type_names
; ty
->mask
; ty
++)
1197 fprintf (stdout
, "%s, ", ty
->tname
);
1201 #endif /* DEBUG386 */
1203 static bfd_reloc_code_real_type reloc
1204 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1206 static bfd_reloc_code_real_type
1207 reloc (size
, pcrel
, sign
, other
)
1211 bfd_reloc_code_real_type other
;
1213 if (other
!= NO_RELOC
)
1219 as_bad (_("There are no unsigned pc-relative relocations"));
1222 case 1: return BFD_RELOC_8_PCREL
;
1223 case 2: return BFD_RELOC_16_PCREL
;
1224 case 4: return BFD_RELOC_32_PCREL
;
1226 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1233 case 4: return BFD_RELOC_X86_64_32S
;
1238 case 1: return BFD_RELOC_8
;
1239 case 2: return BFD_RELOC_16
;
1240 case 4: return BFD_RELOC_32
;
1241 case 8: return BFD_RELOC_64
;
1243 as_bad (_("can not do %s %d byte relocation"),
1244 sign
? "signed" : "unsigned", size
);
1248 return BFD_RELOC_NONE
;
1251 /* Here we decide which fixups can be adjusted to make them relative to
1252 the beginning of the section instead of the symbol. Basically we need
1253 to make sure that the dynamic relocations are done correctly, so in
1254 some cases we force the original symbol to be used. */
1257 tc_i386_fix_adjustable (fixP
)
1258 fixS
*fixP ATTRIBUTE_UNUSED
;
1260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1261 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1264 /* Don't adjust pc-relative references to merge sections in 64-bit
1266 if (use_rela_relocations
1267 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1271 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1272 and changed later by validate_fix. */
1273 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1274 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1277 /* adjust_reloc_syms doesn't know about the GOT. */
1278 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1279 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1280 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1281 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1282 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1283 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1284 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1285 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1286 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1287 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1288 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1289 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1290 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1291 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1292 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1293 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1294 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1295 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1296 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1297 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1298 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1304 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1307 intel_float_operand (mnemonic
)
1308 const char *mnemonic
;
1310 /* Note that the value returned is meaningful only for opcodes with (memory)
1311 operands, hence the code here is free to improperly handle opcodes that
1312 have no operands (for better performance and smaller code). */
1314 if (mnemonic
[0] != 'f')
1315 return 0; /* non-math */
1317 switch (mnemonic
[1])
1319 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1320 the fs segment override prefix not currently handled because no
1321 call path can make opcodes without operands get here */
1323 return 2 /* integer op */;
1325 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1326 return 3; /* fldcw/fldenv */
1329 if (mnemonic
[2] != 'o' /* fnop */)
1330 return 3; /* non-waiting control op */
1333 if (mnemonic
[2] == 's')
1334 return 3; /* frstor/frstpm */
1337 if (mnemonic
[2] == 'a')
1338 return 3; /* fsave */
1339 if (mnemonic
[2] == 't')
1341 switch (mnemonic
[3])
1343 case 'c': /* fstcw */
1344 case 'd': /* fstdw */
1345 case 'e': /* fstenv */
1346 case 's': /* fsts[gw] */
1352 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1353 return 0; /* fxsave/fxrstor are not really math ops */
1360 /* This is the guts of the machine-dependent assembler. LINE points to a
1361 machine dependent instruction. This function is supposed to emit
1362 the frags/bytes it assembles to. */
1369 char mnemonic
[MAX_MNEM_SIZE
];
1371 /* Initialize globals. */
1372 memset (&i
, '\0', sizeof (i
));
1373 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1374 i
.reloc
[j
] = NO_RELOC
;
1375 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1376 memset (im_expressions
, '\0', sizeof (im_expressions
));
1377 save_stack_p
= save_stack
;
1379 /* First parse an instruction mnemonic & call i386_operand for the operands.
1380 We assume that the scrubber has arranged it so that line[0] is the valid
1381 start of a (possibly prefixed) mnemonic. */
1383 line
= parse_insn (line
, mnemonic
);
1387 line
= parse_operands (line
, mnemonic
);
1391 /* Now we've parsed the mnemonic into a set of templates, and have the
1392 operands at hand. */
1394 /* All intel opcodes have reversed operands except for "bound" and
1395 "enter". We also don't reverse intersegment "jmp" and "call"
1396 instructions with 2 immediate operands so that the immediate segment
1397 precedes the offset, as it does when in AT&T mode. "enter" and the
1398 intersegment "jmp" and "call" instructions are the only ones that
1399 have two immediate operands. */
1400 if (intel_syntax
&& i
.operands
> 1
1401 && (strcmp (mnemonic
, "bound") != 0)
1402 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1408 if (i
.disp_operands
)
1411 /* Next, we find a template that matches the given insn,
1412 making sure the overlap of the given operands types is consistent
1413 with the template operand types. */
1415 if (!match_template ())
1420 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1422 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1423 i
.tm
.base_opcode
^= FloatR
;
1425 /* Zap movzx and movsx suffix. The suffix may have been set from
1426 "word ptr" or "byte ptr" on the source operand, but we'll use
1427 the suffix later to choose the destination register. */
1428 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1430 if (i
.reg_operands
< 2
1432 && (~i
.tm
.opcode_modifier
1439 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1445 if (i
.tm
.opcode_modifier
& FWait
)
1446 if (!add_prefix (FWAIT_OPCODE
))
1449 /* Check string instruction segment overrides. */
1450 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1452 if (!check_string ())
1456 if (!process_suffix ())
1459 /* Make still unresolved immediate matches conform to size of immediate
1460 given in i.suffix. */
1461 if (!finalize_imm ())
1464 if (i
.types
[0] & Imm1
)
1465 i
.imm_operands
= 0; /* kludge for shift insns. */
1466 if (i
.types
[0] & ImplicitRegister
)
1468 if (i
.types
[1] & ImplicitRegister
)
1470 if (i
.types
[2] & ImplicitRegister
)
1473 if (i
.tm
.opcode_modifier
& ImmExt
)
1477 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1479 /* These Intel Prescott New Instructions have the fixed
1480 operands with an opcode suffix which is coded in the same
1481 place as an 8-bit immediate field would be. Here we check
1482 those operands and remove them afterwards. */
1485 for (x
= 0; x
< i
.operands
; x
++)
1486 if (i
.op
[x
].regs
->reg_num
!= x
)
1487 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1488 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1492 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1493 opcode suffix which is coded in the same place as an 8-bit
1494 immediate field would be. Here we fake an 8-bit immediate
1495 operand from the opcode suffix stored in tm.extension_opcode. */
1497 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1499 exp
= &im_expressions
[i
.imm_operands
++];
1500 i
.op
[i
.operands
].imms
= exp
;
1501 i
.types
[i
.operands
++] = Imm8
;
1502 exp
->X_op
= O_constant
;
1503 exp
->X_add_number
= i
.tm
.extension_opcode
;
1504 i
.tm
.extension_opcode
= None
;
1507 /* For insns with operands there are more diddles to do to the opcode. */
1510 if (!process_operands ())
1513 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1515 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1516 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1519 /* Handle conversion of 'int $3' --> special int3 insn. */
1520 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1522 i
.tm
.base_opcode
= INT3_OPCODE
;
1526 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1527 && i
.op
[0].disps
->X_op
== O_constant
)
1529 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1530 the absolute address given by the constant. Since ix86 jumps and
1531 calls are pc relative, we need to generate a reloc. */
1532 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1533 i
.op
[0].disps
->X_op
= O_symbol
;
1536 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1537 i
.rex
|= REX_MODE64
;
1539 /* For 8 bit registers we need an empty rex prefix. Also if the
1540 instruction already has a prefix, we need to convert old
1541 registers to new ones. */
1543 if (((i
.types
[0] & Reg8
) != 0
1544 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1545 || ((i
.types
[1] & Reg8
) != 0
1546 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1547 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1552 i
.rex
|= REX_OPCODE
;
1553 for (x
= 0; x
< 2; x
++)
1555 /* Look for 8 bit operand that uses old registers. */
1556 if ((i
.types
[x
] & Reg8
) != 0
1557 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1559 /* In case it is "hi" register, give up. */
1560 if (i
.op
[x
].regs
->reg_num
> 3)
1561 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1562 i
.op
[x
].regs
->reg_name
);
1564 /* Otherwise it is equivalent to the extended register.
1565 Since the encoding doesn't change this is merely
1566 cosmetic cleanup for debug output. */
1568 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1574 add_prefix (REX_OPCODE
| i
.rex
);
1576 /* We are ready to output the insn. */
1581 parse_insn (line
, mnemonic
)
1586 char *token_start
= l
;
1591 /* Non-zero if we found a prefix only acceptable with string insns. */
1592 const char *expecting_string_instruction
= NULL
;
1597 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1600 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1602 as_bad (_("no such instruction: `%s'"), token_start
);
1607 if (!is_space_char (*l
)
1608 && *l
!= END_OF_INSN
1609 && *l
!= PREFIX_SEPARATOR
1612 as_bad (_("invalid character %s in mnemonic"),
1613 output_invalid (*l
));
1616 if (token_start
== l
)
1618 if (*l
== PREFIX_SEPARATOR
)
1619 as_bad (_("expecting prefix; got nothing"));
1621 as_bad (_("expecting mnemonic; got nothing"));
1625 /* Look up instruction (or prefix) via hash table. */
1626 current_templates
= hash_find (op_hash
, mnemonic
);
1628 if (*l
!= END_OF_INSN
1629 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1630 && current_templates
1631 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1633 /* If we are in 16-bit mode, do not allow addr16 or data16.
1634 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1635 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1636 && flag_code
!= CODE_64BIT
1637 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1638 ^ (flag_code
== CODE_16BIT
)))
1640 as_bad (_("redundant %s prefix"),
1641 current_templates
->start
->name
);
1644 /* Add prefix, checking for repeated prefixes. */
1645 switch (add_prefix (current_templates
->start
->base_opcode
))
1650 expecting_string_instruction
= current_templates
->start
->name
;
1653 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1660 if (!current_templates
)
1662 /* See if we can get a match by trimming off a suffix. */
1665 case WORD_MNEM_SUFFIX
:
1666 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1667 i
.suffix
= SHORT_MNEM_SUFFIX
;
1669 case BYTE_MNEM_SUFFIX
:
1670 case QWORD_MNEM_SUFFIX
:
1671 i
.suffix
= mnem_p
[-1];
1673 current_templates
= hash_find (op_hash
, mnemonic
);
1675 case SHORT_MNEM_SUFFIX
:
1676 case LONG_MNEM_SUFFIX
:
1679 i
.suffix
= mnem_p
[-1];
1681 current_templates
= hash_find (op_hash
, mnemonic
);
1689 if (intel_float_operand (mnemonic
) == 1)
1690 i
.suffix
= SHORT_MNEM_SUFFIX
;
1692 i
.suffix
= LONG_MNEM_SUFFIX
;
1694 current_templates
= hash_find (op_hash
, mnemonic
);
1698 if (!current_templates
)
1700 as_bad (_("no such instruction: `%s'"), token_start
);
1705 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1707 /* Check for a branch hint. We allow ",pt" and ",pn" for
1708 predict taken and predict not taken respectively.
1709 I'm not sure that branch hints actually do anything on loop
1710 and jcxz insns (JumpByte) for current Pentium4 chips. They
1711 may work in the future and it doesn't hurt to accept them
1713 if (l
[0] == ',' && l
[1] == 'p')
1717 if (!add_prefix (DS_PREFIX_OPCODE
))
1721 else if (l
[2] == 'n')
1723 if (!add_prefix (CS_PREFIX_OPCODE
))
1729 /* Any other comma loses. */
1732 as_bad (_("invalid character %s in mnemonic"),
1733 output_invalid (*l
));
1737 /* Check if instruction is supported on specified architecture. */
1739 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1741 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1742 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1744 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1747 if (!(supported
& 2))
1749 as_bad (flag_code
== CODE_64BIT
1750 ? _("`%s' is not supported in 64-bit mode")
1751 : _("`%s' is only supported in 64-bit mode"),
1752 current_templates
->start
->name
);
1755 if (!(supported
& 1))
1757 as_warn (_("`%s' is not supported on `%s%s'"),
1758 current_templates
->start
->name
,
1760 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1762 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1764 as_warn (_("use .code16 to ensure correct addressing mode"));
1767 /* Check for rep/repne without a string instruction. */
1768 if (expecting_string_instruction
)
1770 static templates override
;
1772 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1773 if (t
->opcode_modifier
& IsString
)
1775 if (t
>= current_templates
->end
)
1777 as_bad (_("expecting string instruction after `%s'"),
1778 expecting_string_instruction
);
1781 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1782 if (!(t
->opcode_modifier
& IsString
))
1785 current_templates
= &override
;
1792 parse_operands (l
, mnemonic
)
1794 const char *mnemonic
;
1798 /* 1 if operand is pending after ','. */
1799 unsigned int expecting_operand
= 0;
1801 /* Non-zero if operand parens not balanced. */
1802 unsigned int paren_not_balanced
;
1804 while (*l
!= END_OF_INSN
)
1806 /* Skip optional white space before operand. */
1807 if (is_space_char (*l
))
1809 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1811 as_bad (_("invalid character %s before operand %d"),
1812 output_invalid (*l
),
1816 token_start
= l
; /* after white space */
1817 paren_not_balanced
= 0;
1818 while (paren_not_balanced
|| *l
!= ',')
1820 if (*l
== END_OF_INSN
)
1822 if (paren_not_balanced
)
1825 as_bad (_("unbalanced parenthesis in operand %d."),
1828 as_bad (_("unbalanced brackets in operand %d."),
1833 break; /* we are done */
1835 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1837 as_bad (_("invalid character %s in operand %d"),
1838 output_invalid (*l
),
1845 ++paren_not_balanced
;
1847 --paren_not_balanced
;
1852 ++paren_not_balanced
;
1854 --paren_not_balanced
;
1858 if (l
!= token_start
)
1859 { /* Yes, we've read in another operand. */
1860 unsigned int operand_ok
;
1861 this_operand
= i
.operands
++;
1862 if (i
.operands
> MAX_OPERANDS
)
1864 as_bad (_("spurious operands; (%d operands/instruction max)"),
1868 /* Now parse operand adding info to 'i' as we go along. */
1869 END_STRING_AND_SAVE (l
);
1873 i386_intel_operand (token_start
,
1874 intel_float_operand (mnemonic
));
1876 operand_ok
= i386_operand (token_start
);
1878 RESTORE_END_STRING (l
);
1884 if (expecting_operand
)
1886 expecting_operand_after_comma
:
1887 as_bad (_("expecting operand after ','; got nothing"));
1892 as_bad (_("expecting operand before ','; got nothing"));
1897 /* Now *l must be either ',' or END_OF_INSN. */
1900 if (*++l
== END_OF_INSN
)
1902 /* Just skip it, if it's \n complain. */
1903 goto expecting_operand_after_comma
;
1905 expecting_operand
= 1;
1914 union i386_op temp_op
;
1915 unsigned int temp_type
;
1916 enum bfd_reloc_code_real temp_reloc
;
1920 if (i
.operands
== 2)
1925 else if (i
.operands
== 3)
1930 temp_type
= i
.types
[xchg2
];
1931 i
.types
[xchg2
] = i
.types
[xchg1
];
1932 i
.types
[xchg1
] = temp_type
;
1933 temp_op
= i
.op
[xchg2
];
1934 i
.op
[xchg2
] = i
.op
[xchg1
];
1935 i
.op
[xchg1
] = temp_op
;
1936 temp_reloc
= i
.reloc
[xchg2
];
1937 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1938 i
.reloc
[xchg1
] = temp_reloc
;
1940 if (i
.mem_operands
== 2)
1942 const seg_entry
*temp_seg
;
1943 temp_seg
= i
.seg
[0];
1944 i
.seg
[0] = i
.seg
[1];
1945 i
.seg
[1] = temp_seg
;
1949 /* Try to ensure constant immediates are represented in the smallest
1954 char guess_suffix
= 0;
1958 guess_suffix
= i
.suffix
;
1959 else if (i
.reg_operands
)
1961 /* Figure out a suffix from the last register operand specified.
1962 We can't do this properly yet, ie. excluding InOutPortReg,
1963 but the following works for instructions with immediates.
1964 In any case, we can't set i.suffix yet. */
1965 for (op
= i
.operands
; --op
>= 0;)
1966 if (i
.types
[op
] & Reg
)
1968 if (i
.types
[op
] & Reg8
)
1969 guess_suffix
= BYTE_MNEM_SUFFIX
;
1970 else if (i
.types
[op
] & Reg16
)
1971 guess_suffix
= WORD_MNEM_SUFFIX
;
1972 else if (i
.types
[op
] & Reg32
)
1973 guess_suffix
= LONG_MNEM_SUFFIX
;
1974 else if (i
.types
[op
] & Reg64
)
1975 guess_suffix
= QWORD_MNEM_SUFFIX
;
1979 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1980 guess_suffix
= WORD_MNEM_SUFFIX
;
1982 for (op
= i
.operands
; --op
>= 0;)
1983 if (i
.types
[op
] & Imm
)
1985 switch (i
.op
[op
].imms
->X_op
)
1988 /* If a suffix is given, this operand may be shortened. */
1989 switch (guess_suffix
)
1991 case LONG_MNEM_SUFFIX
:
1992 i
.types
[op
] |= Imm32
| Imm64
;
1994 case WORD_MNEM_SUFFIX
:
1995 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1997 case BYTE_MNEM_SUFFIX
:
1998 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2002 /* If this operand is at most 16 bits, convert it
2003 to a signed 16 bit number before trying to see
2004 whether it will fit in an even smaller size.
2005 This allows a 16-bit operand such as $0xffe0 to
2006 be recognised as within Imm8S range. */
2007 if ((i
.types
[op
] & Imm16
)
2008 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2010 i
.op
[op
].imms
->X_add_number
=
2011 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2013 if ((i
.types
[op
] & Imm32
)
2014 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2017 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2018 ^ ((offsetT
) 1 << 31))
2019 - ((offsetT
) 1 << 31));
2021 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2023 /* We must avoid matching of Imm32 templates when 64bit
2024 only immediate is available. */
2025 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2026 i
.types
[op
] &= ~Imm32
;
2033 /* Symbols and expressions. */
2035 /* Convert symbolic operand to proper sizes for matching. */
2036 switch (guess_suffix
)
2038 case QWORD_MNEM_SUFFIX
:
2039 i
.types
[op
] = Imm64
| Imm32S
;
2041 case LONG_MNEM_SUFFIX
:
2042 i
.types
[op
] = Imm32
;
2044 case WORD_MNEM_SUFFIX
:
2045 i
.types
[op
] = Imm16
;
2047 case BYTE_MNEM_SUFFIX
:
2048 i
.types
[op
] = Imm8
| Imm8S
;
2056 /* Try to use the smallest displacement type too. */
2062 for (op
= i
.operands
; --op
>= 0;)
2063 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
2065 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2067 if (i
.types
[op
] & Disp16
)
2069 /* We know this operand is at most 16 bits, so
2070 convert to a signed 16 bit number before trying
2071 to see whether it will fit in an even smaller
2074 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2076 else if (i
.types
[op
] & Disp32
)
2078 /* We know this operand is at most 32 bits, so convert to a
2079 signed 32 bit number before trying to see whether it will
2080 fit in an even smaller size. */
2081 disp
&= (((offsetT
) 2 << 31) - 1);
2082 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2084 if (flag_code
== CODE_64BIT
)
2086 if (fits_in_signed_long (disp
))
2087 i
.types
[op
] |= Disp32S
;
2088 if (fits_in_unsigned_long (disp
))
2089 i
.types
[op
] |= Disp32
;
2091 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2092 && fits_in_signed_byte (disp
))
2093 i
.types
[op
] |= Disp8
;
2100 /* Points to template once we've found it. */
2102 unsigned int overlap0
, overlap1
, overlap2
;
2103 unsigned int found_reverse_match
;
2106 #define MATCH(overlap, given, template) \
2107 ((overlap & ~JumpAbsolute) \
2108 && (((given) & (BaseIndex | JumpAbsolute)) \
2109 == ((overlap) & (BaseIndex | JumpAbsolute))))
2111 /* If given types r0 and r1 are registers they must be of the same type
2112 unless the expected operand type register overlap is null.
2113 Note that Acc in a template matches every size of reg. */
2114 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2115 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2116 || ((g0) & Reg) == ((g1) & Reg) \
2117 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2122 found_reverse_match
= 0;
2123 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2125 : (i
.suffix
== WORD_MNEM_SUFFIX
2127 : (i
.suffix
== SHORT_MNEM_SUFFIX
2129 : (i
.suffix
== LONG_MNEM_SUFFIX
2131 : (i
.suffix
== QWORD_MNEM_SUFFIX
2133 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2134 ? No_xSuf
: 0))))));
2136 t
= current_templates
->start
;
2137 if (i
.suffix
== QWORD_MNEM_SUFFIX
2138 && flag_code
!= CODE_64BIT
2140 ? !(t
->opcode_modifier
& IgnoreSize
)
2141 && !intel_float_operand (t
->name
)
2142 : intel_float_operand (t
->name
) != 2)
2143 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2144 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2145 && (t
->base_opcode
!= 0x0fc7
2146 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2147 t
= current_templates
->end
;
2148 for (; t
< current_templates
->end
; t
++)
2150 /* Must have right number of operands. */
2151 if (i
.operands
!= t
->operands
)
2154 /* Check the suffix, except for some instructions in intel mode. */
2155 if ((t
->opcode_modifier
& suffix_check
)
2157 && (t
->opcode_modifier
& IgnoreSize
)))
2160 /* Do not verify operands when there are none. */
2161 else if (!t
->operands
)
2163 if (t
->cpu_flags
& ~cpu_arch_flags
)
2165 /* We've found a match; break out of loop. */
2169 overlap0
= i
.types
[0] & t
->operand_types
[0];
2170 switch (t
->operands
)
2173 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2178 overlap1
= i
.types
[1] & t
->operand_types
[1];
2179 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2180 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2181 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2182 t
->operand_types
[0],
2183 overlap1
, i
.types
[1],
2184 t
->operand_types
[1]))
2186 /* Check if other direction is valid ... */
2187 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2190 /* Try reversing direction of operands. */
2191 overlap0
= i
.types
[0] & t
->operand_types
[1];
2192 overlap1
= i
.types
[1] & t
->operand_types
[0];
2193 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2194 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2195 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2196 t
->operand_types
[1],
2197 overlap1
, i
.types
[1],
2198 t
->operand_types
[0]))
2200 /* Does not match either direction. */
2203 /* found_reverse_match holds which of D or FloatDR
2205 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2207 /* Found a forward 2 operand match here. */
2208 else if (t
->operands
== 3)
2210 /* Here we make use of the fact that there are no
2211 reverse match 3 operand instructions, and all 3
2212 operand instructions only need to be checked for
2213 register consistency between operands 2 and 3. */
2214 overlap2
= i
.types
[2] & t
->operand_types
[2];
2215 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2216 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2217 t
->operand_types
[1],
2218 overlap2
, i
.types
[2],
2219 t
->operand_types
[2]))
2223 /* Found either forward/reverse 2 or 3 operand match here:
2224 slip through to break. */
2226 if (t
->cpu_flags
& ~cpu_arch_flags
)
2228 found_reverse_match
= 0;
2231 /* We've found a match; break out of loop. */
2235 if (t
== current_templates
->end
)
2237 /* We found no match. */
2238 as_bad (_("suffix or operands invalid for `%s'"),
2239 current_templates
->start
->name
);
2243 if (!quiet_warnings
)
2246 && ((i
.types
[0] & JumpAbsolute
)
2247 != (t
->operand_types
[0] & JumpAbsolute
)))
2249 as_warn (_("indirect %s without `*'"), t
->name
);
2252 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2253 == (IsPrefix
| IgnoreSize
))
2255 /* Warn them that a data or address size prefix doesn't
2256 affect assembly of the next line of code. */
2257 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2261 /* Copy the template we found. */
2263 if (found_reverse_match
)
2265 /* If we found a reverse match we must alter the opcode
2266 direction bit. found_reverse_match holds bits to change
2267 (different for int & float insns). */
2269 i
.tm
.base_opcode
^= found_reverse_match
;
2271 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2272 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2281 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2282 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2284 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2286 as_bad (_("`%s' operand %d must use `%%es' segment"),
2291 /* There's only ever one segment override allowed per instruction.
2292 This instruction possibly has a legal segment override on the
2293 second operand, so copy the segment to where non-string
2294 instructions store it, allowing common code. */
2295 i
.seg
[0] = i
.seg
[1];
2297 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2299 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2301 as_bad (_("`%s' operand %d must use `%%es' segment"),
2311 process_suffix (void)
2313 /* If matched instruction specifies an explicit instruction mnemonic
2315 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2317 if (i
.tm
.opcode_modifier
& Size16
)
2318 i
.suffix
= WORD_MNEM_SUFFIX
;
2319 else if (i
.tm
.opcode_modifier
& Size64
)
2320 i
.suffix
= QWORD_MNEM_SUFFIX
;
2322 i
.suffix
= LONG_MNEM_SUFFIX
;
2324 else if (i
.reg_operands
)
2326 /* If there's no instruction mnemonic suffix we try to invent one
2327 based on register operands. */
2330 /* We take i.suffix from the last register operand specified,
2331 Destination register type is more significant than source
2335 for (op
= i
.operands
; --op
>= 0;)
2336 if ((i
.types
[op
] & Reg
)
2337 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2339 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2340 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2341 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2346 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2348 if (!check_byte_reg ())
2351 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2353 if (!check_long_reg ())
2356 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2358 if (!check_qword_reg ())
2361 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2363 if (!check_word_reg ())
2366 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2367 /* Do nothing if the instruction is going to ignore the prefix. */
2372 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2374 /* exclude fldenv/frstor/fsave/fstenv */
2375 && (i
.tm
.opcode_modifier
& No_sSuf
))
2377 i
.suffix
= stackop_size
;
2379 else if (intel_syntax
2381 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2382 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2383 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2384 && i
.tm
.extension_opcode
<= 3)))
2389 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2391 i
.suffix
= QWORD_MNEM_SUFFIX
;
2395 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2396 i
.suffix
= LONG_MNEM_SUFFIX
;
2399 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2400 i
.suffix
= WORD_MNEM_SUFFIX
;
2409 if (i
.tm
.opcode_modifier
& W
)
2411 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2417 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2425 if ((i
.tm
.opcode_modifier
& W
)
2426 || ((suffixes
& (suffixes
- 1))
2427 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2429 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2435 /* Change the opcode based on the operand size given by i.suffix;
2436 We don't need to change things for byte insns. */
2438 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2440 /* It's not a byte, select word/dword operation. */
2441 if (i
.tm
.opcode_modifier
& W
)
2443 if (i
.tm
.opcode_modifier
& ShortForm
)
2444 i
.tm
.base_opcode
|= 8;
2446 i
.tm
.base_opcode
|= 1;
2449 /* Now select between word & dword operations via the operand
2450 size prefix, except for instructions that will ignore this
2452 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2453 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2454 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2455 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2456 || (flag_code
== CODE_64BIT
2457 && (i
.tm
.opcode_modifier
& JumpByte
))))
2459 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2461 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2462 prefix
= ADDR_PREFIX_OPCODE
;
2464 if (!add_prefix (prefix
))
2468 /* Set mode64 for an operand. */
2469 if (i
.suffix
== QWORD_MNEM_SUFFIX
2470 && flag_code
== CODE_64BIT
2471 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2472 i
.rex
|= REX_MODE64
;
2474 /* Size floating point instruction. */
2475 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2476 if (i
.tm
.opcode_modifier
& FloatMF
)
2477 i
.tm
.base_opcode
^= 4;
2484 check_byte_reg (void)
2488 for (op
= i
.operands
; --op
>= 0;)
2490 /* If this is an eight bit register, it's OK. If it's the 16 or
2491 32 bit version of an eight bit register, we will just use the
2492 low portion, and that's OK too. */
2493 if (i
.types
[op
] & Reg8
)
2496 /* movzx and movsx should not generate this warning. */
2498 && (i
.tm
.base_opcode
== 0xfb7
2499 || i
.tm
.base_opcode
== 0xfb6
2500 || i
.tm
.base_opcode
== 0x63
2501 || i
.tm
.base_opcode
== 0xfbe
2502 || i
.tm
.base_opcode
== 0xfbf))
2505 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2507 /* Prohibit these changes in the 64bit mode, since the
2508 lowering is more complicated. */
2509 if (flag_code
== CODE_64BIT
2510 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2512 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2513 i
.op
[op
].regs
->reg_name
,
2517 #if REGISTER_WARNINGS
2519 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2520 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2521 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2522 ? REGNAM_AL
- REGNAM_AX
2523 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2524 i
.op
[op
].regs
->reg_name
,
2529 /* Any other register is bad. */
2530 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2532 | Control
| Debug
| Test
2533 | FloatReg
| FloatAcc
))
2535 as_bad (_("`%%%s' not allowed with `%s%c'"),
2536 i
.op
[op
].regs
->reg_name
,
2550 for (op
= i
.operands
; --op
>= 0;)
2551 /* Reject eight bit registers, except where the template requires
2552 them. (eg. movzb) */
2553 if ((i
.types
[op
] & Reg8
) != 0
2554 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2556 as_bad (_("`%%%s' not allowed with `%s%c'"),
2557 i
.op
[op
].regs
->reg_name
,
2562 /* Warn if the e prefix on a general reg is missing. */
2563 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2564 && (i
.types
[op
] & Reg16
) != 0
2565 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2567 /* Prohibit these changes in the 64bit mode, since the
2568 lowering is more complicated. */
2569 if (flag_code
== CODE_64BIT
)
2571 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2572 i
.op
[op
].regs
->reg_name
,
2576 #if REGISTER_WARNINGS
2578 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2579 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2580 i
.op
[op
].regs
->reg_name
,
2584 /* Warn if the r prefix on a general reg is missing. */
2585 else if ((i
.types
[op
] & Reg64
) != 0
2586 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2588 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2589 i
.op
[op
].regs
->reg_name
,
2601 for (op
= i
.operands
; --op
>= 0; )
2602 /* Reject eight bit registers, except where the template requires
2603 them. (eg. movzb) */
2604 if ((i
.types
[op
] & Reg8
) != 0
2605 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2607 as_bad (_("`%%%s' not allowed with `%s%c'"),
2608 i
.op
[op
].regs
->reg_name
,
2613 /* Warn if the e prefix on a general reg is missing. */
2614 else if (((i
.types
[op
] & Reg16
) != 0
2615 || (i
.types
[op
] & Reg32
) != 0)
2616 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2618 /* Prohibit these changes in the 64bit mode, since the
2619 lowering is more complicated. */
2620 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2621 i
.op
[op
].regs
->reg_name
,
2632 for (op
= i
.operands
; --op
>= 0;)
2633 /* Reject eight bit registers, except where the template requires
2634 them. (eg. movzb) */
2635 if ((i
.types
[op
] & Reg8
) != 0
2636 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2638 as_bad (_("`%%%s' not allowed with `%s%c'"),
2639 i
.op
[op
].regs
->reg_name
,
2644 /* Warn if the e prefix on a general reg is present. */
2645 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2646 && (i
.types
[op
] & Reg32
) != 0
2647 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2649 /* Prohibit these changes in the 64bit mode, since the
2650 lowering is more complicated. */
2651 if (flag_code
== CODE_64BIT
)
2653 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2654 i
.op
[op
].regs
->reg_name
,
2659 #if REGISTER_WARNINGS
2660 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2661 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2662 i
.op
[op
].regs
->reg_name
,
2672 unsigned int overlap0
, overlap1
, overlap2
;
2674 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2675 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2676 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2677 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2678 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2682 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2684 : (i
.suffix
== WORD_MNEM_SUFFIX
2686 : (i
.suffix
== QWORD_MNEM_SUFFIX
2690 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2691 || overlap0
== (Imm16
| Imm32
)
2692 || overlap0
== (Imm16
| Imm32S
))
2694 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2697 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2698 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2699 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2701 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2705 i
.types
[0] = overlap0
;
2707 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2708 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2709 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2710 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2711 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2715 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2717 : (i
.suffix
== WORD_MNEM_SUFFIX
2719 : (i
.suffix
== QWORD_MNEM_SUFFIX
2723 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2724 || overlap1
== (Imm16
| Imm32
)
2725 || overlap1
== (Imm16
| Imm32S
))
2727 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2730 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2731 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2732 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2734 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2738 i
.types
[1] = overlap1
;
2740 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2741 assert ((overlap2
& Imm
) == 0);
2742 i
.types
[2] = overlap2
;
2750 /* Default segment register this instruction will use for memory
2751 accesses. 0 means unknown. This is only for optimizing out
2752 unnecessary segment overrides. */
2753 const seg_entry
*default_seg
= 0;
2755 /* The imul $imm, %reg instruction is converted into
2756 imul $imm, %reg, %reg, and the clr %reg instruction
2757 is converted into xor %reg, %reg. */
2758 if (i
.tm
.opcode_modifier
& regKludge
)
2760 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2761 /* Pretend we saw the extra register operand. */
2762 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2763 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2764 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2768 if (i
.tm
.opcode_modifier
& ShortForm
)
2770 /* The register or float register operand is in operand 0 or 1. */
2771 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2772 /* Register goes in low 3 bits of opcode. */
2773 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2774 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2776 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2778 /* Warn about some common errors, but press on regardless.
2779 The first case can be generated by gcc (<= 2.8.1). */
2780 if (i
.operands
== 2)
2782 /* Reversed arguments on faddp, fsubp, etc. */
2783 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2784 i
.op
[1].regs
->reg_name
,
2785 i
.op
[0].regs
->reg_name
);
2789 /* Extraneous `l' suffix on fp insn. */
2790 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2791 i
.op
[0].regs
->reg_name
);
2795 else if (i
.tm
.opcode_modifier
& Modrm
)
2797 /* The opcode is completed (modulo i.tm.extension_opcode which
2798 must be put into the modrm byte). Now, we make the modrm and
2799 index base bytes based on all the info we've collected. */
2801 default_seg
= build_modrm_byte ();
2803 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2805 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2806 && i
.op
[0].regs
->reg_num
== 1)
2808 as_bad (_("you can't `pop %%cs'"));
2811 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2812 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2815 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2819 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2821 /* For the string instructions that allow a segment override
2822 on one of their operands, the default segment is ds. */
2826 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2827 as_warn (_("segment override on `lea' is ineffectual"));
2829 /* If a segment was explicitly specified, and the specified segment
2830 is not the default, use an opcode prefix to select it. If we
2831 never figured out what the default segment is, then default_seg
2832 will be zero at this point, and the specified segment prefix will
2834 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2836 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2842 static const seg_entry
*
2845 const seg_entry
*default_seg
= 0;
2847 /* i.reg_operands MUST be the number of real register operands;
2848 implicit registers do not count. */
2849 if (i
.reg_operands
== 2)
2851 unsigned int source
, dest
;
2852 source
= ((i
.types
[0]
2853 & (Reg
| RegMMX
| RegXMM
2855 | Control
| Debug
| Test
))
2860 /* One of the register operands will be encoded in the i.tm.reg
2861 field, the other in the combined i.tm.mode and i.tm.regmem
2862 fields. If no form of this instruction supports a memory
2863 destination operand, then we assume the source operand may
2864 sometimes be a memory operand and so we need to store the
2865 destination in the i.rm.reg field. */
2866 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2868 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2869 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2870 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2872 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2877 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2878 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2879 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2881 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2884 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2886 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2888 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2889 add_prefix (LOCK_PREFIX_OPCODE
);
2893 { /* If it's not 2 reg operands... */
2896 unsigned int fake_zero_displacement
= 0;
2897 unsigned int op
= ((i
.types
[0] & AnyMem
)
2899 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2903 if (i
.base_reg
== 0)
2906 if (!i
.disp_operands
)
2907 fake_zero_displacement
= 1;
2908 if (i
.index_reg
== 0)
2910 /* Operand is just <disp> */
2911 if (flag_code
== CODE_64BIT
)
2913 /* 64bit mode overwrites the 32bit absolute
2914 addressing by RIP relative addressing and
2915 absolute addressing is encoded by one of the
2916 redundant SIB forms. */
2917 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2918 i
.sib
.base
= NO_BASE_REGISTER
;
2919 i
.sib
.index
= NO_INDEX_REGISTER
;
2920 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2922 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2924 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2925 i
.types
[op
] = Disp16
;
2929 i
.rm
.regmem
= NO_BASE_REGISTER
;
2930 i
.types
[op
] = Disp32
;
2933 else /* !i.base_reg && i.index_reg */
2935 i
.sib
.index
= i
.index_reg
->reg_num
;
2936 i
.sib
.base
= NO_BASE_REGISTER
;
2937 i
.sib
.scale
= i
.log2_scale_factor
;
2938 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2939 i
.types
[op
] &= ~Disp
;
2940 if (flag_code
!= CODE_64BIT
)
2941 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2943 i
.types
[op
] |= Disp32S
;
2944 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2948 /* RIP addressing for 64bit mode. */
2949 else if (i
.base_reg
->reg_type
== BaseIndex
)
2951 i
.rm
.regmem
= NO_BASE_REGISTER
;
2952 i
.types
[op
] &= ~ Disp
;
2953 i
.types
[op
] |= Disp32S
;
2954 i
.flags
[op
] = Operand_PCrel
;
2955 if (! i
.disp_operands
)
2956 fake_zero_displacement
= 1;
2958 else if (i
.base_reg
->reg_type
& Reg16
)
2960 switch (i
.base_reg
->reg_num
)
2963 if (i
.index_reg
== 0)
2965 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2966 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2970 if (i
.index_reg
== 0)
2973 if ((i
.types
[op
] & Disp
) == 0)
2975 /* fake (%bp) into 0(%bp) */
2976 i
.types
[op
] |= Disp8
;
2977 fake_zero_displacement
= 1;
2980 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2981 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2983 default: /* (%si) -> 4 or (%di) -> 5 */
2984 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2986 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2988 else /* i.base_reg and 32/64 bit mode */
2990 if (flag_code
== CODE_64BIT
2991 && (i
.types
[op
] & Disp
))
2992 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
2994 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2995 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2997 i
.sib
.base
= i
.base_reg
->reg_num
;
2998 /* x86-64 ignores REX prefix bit here to avoid decoder
3000 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3003 if (i
.disp_operands
== 0)
3005 fake_zero_displacement
= 1;
3006 i
.types
[op
] |= Disp8
;
3009 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3013 i
.sib
.scale
= i
.log2_scale_factor
;
3014 if (i
.index_reg
== 0)
3016 /* <disp>(%esp) becomes two byte modrm with no index
3017 register. We've already stored the code for esp
3018 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3019 Any base register besides %esp will not use the
3020 extra modrm byte. */
3021 i
.sib
.index
= NO_INDEX_REGISTER
;
3022 #if !SCALE1_WHEN_NO_INDEX
3023 /* Another case where we force the second modrm byte. */
3024 if (i
.log2_scale_factor
)
3025 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3030 i
.sib
.index
= i
.index_reg
->reg_num
;
3031 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3032 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3035 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3038 if (fake_zero_displacement
)
3040 /* Fakes a zero displacement assuming that i.types[op]
3041 holds the correct displacement size. */
3044 assert (i
.op
[op
].disps
== 0);
3045 exp
= &disp_expressions
[i
.disp_operands
++];
3046 i
.op
[op
].disps
= exp
;
3047 exp
->X_op
= O_constant
;
3048 exp
->X_add_number
= 0;
3049 exp
->X_add_symbol
= (symbolS
*) 0;
3050 exp
->X_op_symbol
= (symbolS
*) 0;
3054 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3055 (if any) based on i.tm.extension_opcode. Again, we must be
3056 careful to make sure that segment/control/debug/test/MMX
3057 registers are coded into the i.rm.reg field. */
3062 & (Reg
| RegMMX
| RegXMM
3064 | Control
| Debug
| Test
))
3067 & (Reg
| RegMMX
| RegXMM
3069 | Control
| Debug
| Test
))
3072 /* If there is an extension opcode to put here, the register
3073 number must be put into the regmem field. */
3074 if (i
.tm
.extension_opcode
!= None
)
3076 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3077 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3082 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3083 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3087 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3088 must set it to 3 to indicate this is a register operand
3089 in the regmem field. */
3090 if (!i
.mem_operands
)
3094 /* Fill in i.rm.reg field with extension opcode (if any). */
3095 if (i
.tm
.extension_opcode
!= None
)
3096 i
.rm
.reg
= i
.tm
.extension_opcode
;
3107 relax_substateT subtype
;
3112 if (flag_code
== CODE_16BIT
)
3116 if (i
.prefix
[DATA_PREFIX
] != 0)
3122 /* Pentium4 branch hints. */
3123 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3124 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3129 if (i
.prefix
[REX_PREFIX
] != 0)
3135 if (i
.prefixes
!= 0 && !intel_syntax
)
3136 as_warn (_("skipping prefixes on this instruction"));
3138 /* It's always a symbol; End frag & setup for relax.
3139 Make sure there is enough room in this frag for the largest
3140 instruction we may generate in md_convert_frag. This is 2
3141 bytes for the opcode and room for the prefix and largest
3143 frag_grow (prefix
+ 2 + 4);
3144 /* Prefix and 1 opcode byte go in fr_fix. */
3145 p
= frag_more (prefix
+ 1);
3146 if (i
.prefix
[DATA_PREFIX
] != 0)
3147 *p
++ = DATA_PREFIX_OPCODE
;
3148 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3149 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3150 *p
++ = i
.prefix
[SEG_PREFIX
];
3151 if (i
.prefix
[REX_PREFIX
] != 0)
3152 *p
++ = i
.prefix
[REX_PREFIX
];
3153 *p
= i
.tm
.base_opcode
;
3155 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3156 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3157 else if ((cpu_arch_flags
& Cpu386
) != 0)
3158 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3160 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3163 sym
= i
.op
[0].disps
->X_add_symbol
;
3164 off
= i
.op
[0].disps
->X_add_number
;
3166 if (i
.op
[0].disps
->X_op
!= O_constant
3167 && i
.op
[0].disps
->X_op
!= O_symbol
)
3169 /* Handle complex expressions. */
3170 sym
= make_expr_symbol (i
.op
[0].disps
);
3174 /* 1 possible extra opcode + 4 byte displacement go in var part.
3175 Pass reloc in fr_var. */
3176 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3186 if (i
.tm
.opcode_modifier
& JumpByte
)
3188 /* This is a loop or jecxz type instruction. */
3190 if (i
.prefix
[ADDR_PREFIX
] != 0)
3192 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3195 /* Pentium4 branch hints. */
3196 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3197 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3199 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3208 if (flag_code
== CODE_16BIT
)
3211 if (i
.prefix
[DATA_PREFIX
] != 0)
3213 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3223 if (i
.prefix
[REX_PREFIX
] != 0)
3225 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3229 if (i
.prefixes
!= 0 && !intel_syntax
)
3230 as_warn (_("skipping prefixes on this instruction"));
3232 p
= frag_more (1 + size
);
3233 *p
++ = i
.tm
.base_opcode
;
3235 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3236 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3238 /* All jumps handled here are signed, but don't use a signed limit
3239 check for 32 and 16 bit jumps as we want to allow wrap around at
3240 4G and 64k respectively. */
3242 fixP
->fx_signed
= 1;
3246 output_interseg_jump ()
3254 if (flag_code
== CODE_16BIT
)
3258 if (i
.prefix
[DATA_PREFIX
] != 0)
3264 if (i
.prefix
[REX_PREFIX
] != 0)
3274 if (i
.prefixes
!= 0 && !intel_syntax
)
3275 as_warn (_("skipping prefixes on this instruction"));
3277 /* 1 opcode; 2 segment; offset */
3278 p
= frag_more (prefix
+ 1 + 2 + size
);
3280 if (i
.prefix
[DATA_PREFIX
] != 0)
3281 *p
++ = DATA_PREFIX_OPCODE
;
3283 if (i
.prefix
[REX_PREFIX
] != 0)
3284 *p
++ = i
.prefix
[REX_PREFIX
];
3286 *p
++ = i
.tm
.base_opcode
;
3287 if (i
.op
[1].imms
->X_op
== O_constant
)
3289 offsetT n
= i
.op
[1].imms
->X_add_number
;
3292 && !fits_in_unsigned_word (n
)
3293 && !fits_in_signed_word (n
))
3295 as_bad (_("16-bit jump out of range"));
3298 md_number_to_chars (p
, n
, size
);
3301 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3302 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3303 if (i
.op
[0].imms
->X_op
!= O_constant
)
3304 as_bad (_("can't handle non absolute segment in `%s'"),
3306 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3312 fragS
*insn_start_frag
;
3313 offsetT insn_start_off
;
3315 /* Tie dwarf2 debug info to the address at the start of the insn.
3316 We can't do this after the insn has been output as the current
3317 frag may have been closed off. eg. by frag_var. */
3318 dwarf2_emit_insn (0);
3320 insn_start_frag
= frag_now
;
3321 insn_start_off
= frag_now_fix ();
3324 if (i
.tm
.opcode_modifier
& Jump
)
3326 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3328 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3329 output_interseg_jump ();
3332 /* Output normal instructions here. */
3336 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3337 more higher byte to specify a prefix the instruction
3339 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3341 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3343 unsigned int prefix
;
3344 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3346 if (prefix
!= REPE_PREFIX_OPCODE
3347 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3348 add_prefix (prefix
);
3351 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3354 /* The prefix bytes. */
3356 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3362 md_number_to_chars (p
, (valueT
) *q
, 1);
3366 /* Now the opcode; be careful about word order here! */
3367 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3369 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3375 /* Put out high byte first: can't use md_number_to_chars! */
3376 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3377 *p
= i
.tm
.base_opcode
& 0xff;
3380 /* Now the modrm byte and sib byte (if present). */
3381 if (i
.tm
.opcode_modifier
& Modrm
)
3384 md_number_to_chars (p
,
3385 (valueT
) (i
.rm
.regmem
<< 0
3389 /* If i.rm.regmem == ESP (4)
3390 && i.rm.mode != (Register mode)
3392 ==> need second modrm byte. */
3393 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3395 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3398 md_number_to_chars (p
,
3399 (valueT
) (i
.sib
.base
<< 0
3401 | i
.sib
.scale
<< 6),
3406 if (i
.disp_operands
)
3407 output_disp (insn_start_frag
, insn_start_off
);
3410 output_imm (insn_start_frag
, insn_start_off
);
3418 #endif /* DEBUG386 */
3422 output_disp (insn_start_frag
, insn_start_off
)
3423 fragS
*insn_start_frag
;
3424 offsetT insn_start_off
;
3429 for (n
= 0; n
< i
.operands
; n
++)
3431 if (i
.types
[n
] & Disp
)
3433 if (i
.op
[n
].disps
->X_op
== O_constant
)
3439 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3442 if (i
.types
[n
] & Disp8
)
3444 if (i
.types
[n
] & Disp64
)
3447 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3449 p
= frag_more (size
);
3450 md_number_to_chars (p
, val
, size
);
3454 enum bfd_reloc_code_real reloc_type
;
3457 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3459 /* The PC relative address is computed relative
3460 to the instruction boundary, so in case immediate
3461 fields follows, we need to adjust the value. */
3462 if (pcrel
&& i
.imm_operands
)
3467 for (n1
= 0; n1
< i
.operands
; n1
++)
3468 if (i
.types
[n1
] & Imm
)
3470 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3473 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3475 if (i
.types
[n1
] & Imm64
)
3480 /* We should find the immediate. */
3481 if (n1
== i
.operands
)
3483 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3486 if (i
.types
[n
] & Disp32S
)
3489 if (i
.types
[n
] & (Disp16
| Disp64
))
3492 if (i
.types
[n
] & Disp64
)
3496 p
= frag_more (size
);
3497 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3498 if (reloc_type
== BFD_RELOC_32
3500 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3501 && (i
.op
[n
].disps
->X_op
== O_symbol
3502 || (i
.op
[n
].disps
->X_op
== O_add
3503 && ((symbol_get_value_expression
3504 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3509 if (insn_start_frag
== frag_now
)
3510 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3515 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3516 for (fr
= insn_start_frag
->fr_next
;
3517 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3519 add
+= p
- frag_now
->fr_literal
;
3522 /* We don't support dynamic linking on x86-64 yet. */
3523 if (flag_code
== CODE_64BIT
)
3525 reloc_type
= BFD_RELOC_386_GOTPC
;
3526 i
.op
[n
].disps
->X_add_number
+= add
;
3528 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3529 i
.op
[n
].disps
, pcrel
, reloc_type
);
3536 output_imm (insn_start_frag
, insn_start_off
)
3537 fragS
*insn_start_frag
;
3538 offsetT insn_start_off
;
3543 for (n
= 0; n
< i
.operands
; n
++)
3545 if (i
.types
[n
] & Imm
)
3547 if (i
.op
[n
].imms
->X_op
== O_constant
)
3553 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3556 if (i
.types
[n
] & (Imm8
| Imm8S
))
3558 else if (i
.types
[n
] & Imm64
)
3561 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3563 p
= frag_more (size
);
3564 md_number_to_chars (p
, val
, size
);
3568 /* Not absolute_section.
3569 Need a 32-bit fixup (don't support 8bit
3570 non-absolute imms). Try to support other
3572 enum bfd_reloc_code_real reloc_type
;
3576 if ((i
.types
[n
] & (Imm32S
))
3577 && (i
.suffix
== QWORD_MNEM_SUFFIX
3578 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3580 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3583 if (i
.types
[n
] & (Imm8
| Imm8S
))
3585 if (i
.types
[n
] & Imm64
)
3589 p
= frag_more (size
);
3590 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3592 /* This is tough to explain. We end up with this one if we
3593 * have operands that look like
3594 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3595 * obtain the absolute address of the GOT, and it is strongly
3596 * preferable from a performance point of view to avoid using
3597 * a runtime relocation for this. The actual sequence of
3598 * instructions often look something like:
3603 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3605 * The call and pop essentially return the absolute address
3606 * of the label .L66 and store it in %ebx. The linker itself
3607 * will ultimately change the first operand of the addl so
3608 * that %ebx points to the GOT, but to keep things simple, the
3609 * .o file must have this operand set so that it generates not
3610 * the absolute address of .L66, but the absolute address of
3611 * itself. This allows the linker itself simply treat a GOTPC
3612 * relocation as asking for a pcrel offset to the GOT to be
3613 * added in, and the addend of the relocation is stored in the
3614 * operand field for the instruction itself.
3616 * Our job here is to fix the operand so that it would add
3617 * the correct offset so that %ebx would point to itself. The
3618 * thing that is tricky is that .-.L66 will point to the
3619 * beginning of the instruction, so we need to further modify
3620 * the operand so that it will point to itself. There are
3621 * other cases where you have something like:
3623 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3625 * and here no correction would be required. Internally in
3626 * the assembler we treat operands of this form as not being
3627 * pcrel since the '.' is explicitly mentioned, and I wonder
3628 * whether it would simplify matters to do it this way. Who
3629 * knows. In earlier versions of the PIC patches, the
3630 * pcrel_adjust field was used to store the correction, but
3631 * since the expression is not pcrel, I felt it would be
3632 * confusing to do it this way. */
3634 if (reloc_type
== BFD_RELOC_32
3636 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3637 && (i
.op
[n
].imms
->X_op
== O_symbol
3638 || (i
.op
[n
].imms
->X_op
== O_add
3639 && ((symbol_get_value_expression
3640 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3645 if (insn_start_frag
== frag_now
)
3646 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3651 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3652 for (fr
= insn_start_frag
->fr_next
;
3653 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3655 add
+= p
- frag_now
->fr_literal
;
3658 /* We don't support dynamic linking on x86-64 yet. */
3659 if (flag_code
== CODE_64BIT
)
3661 reloc_type
= BFD_RELOC_386_GOTPC
;
3662 i
.op
[n
].imms
->X_add_number
+= add
;
3664 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3665 i
.op
[n
].imms
, 0, reloc_type
);
3672 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3674 /* Parse operands of the form
3675 <symbol>@GOTOFF+<nnn>
3676 and similar .plt or .got references.
3678 If we find one, set up the correct relocation in RELOC and copy the
3679 input string, minus the `@GOTOFF' into a malloc'd buffer for
3680 parsing by the calling routine. Return this buffer, and if ADJUST
3681 is non-null set it to the length of the string we removed from the
3682 input line. Otherwise return NULL. */
3684 lex_got (reloc
, adjust
)
3685 enum bfd_reloc_code_real
*reloc
;
3688 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3689 static const struct {
3691 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3693 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3694 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3695 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3696 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3697 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3698 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3699 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3700 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3701 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3702 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3703 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3704 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3705 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3710 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3711 if (is_end_of_line
[(unsigned char) *cp
])
3714 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3718 len
= strlen (gotrel
[j
].str
);
3719 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3721 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3724 char *tmpbuf
, *past_reloc
;
3726 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3730 if (GOT_symbol
== NULL
)
3731 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3733 /* Replace the relocation token with ' ', so that
3734 errors like foo@GOTOFF1 will be detected. */
3736 /* The length of the first part of our input line. */
3737 first
= cp
- input_line_pointer
;
3739 /* The second part goes from after the reloc token until
3740 (and including) an end_of_line char. Don't use strlen
3741 here as the end_of_line char may not be a NUL. */
3742 past_reloc
= cp
+ 1 + len
;
3743 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3745 second
= cp
- past_reloc
;
3747 /* Allocate and copy string. The trailing NUL shouldn't
3748 be necessary, but be safe. */
3749 tmpbuf
= xmalloc (first
+ second
+ 2);
3750 memcpy (tmpbuf
, input_line_pointer
, first
);
3751 tmpbuf
[first
] = ' ';
3752 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3753 tmpbuf
[first
+ second
+ 1] = '\0';
3757 as_bad (_("@%s reloc is not supported in %s bit mode"),
3758 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3763 /* Might be a symbol version string. Don't as_bad here. */
3767 /* x86_cons_fix_new is called via the expression parsing code when a
3768 reloc is needed. We use this hook to get the correct .got reloc. */
3769 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3772 x86_cons_fix_new (frag
, off
, len
, exp
)
3778 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3779 got_reloc
= NO_RELOC
;
3780 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3784 x86_cons (exp
, size
)
3790 /* Handle @GOTOFF and the like in an expression. */
3792 char *gotfree_input_line
;
3795 save
= input_line_pointer
;
3796 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3797 if (gotfree_input_line
)
3798 input_line_pointer
= gotfree_input_line
;
3802 if (gotfree_input_line
)
3804 /* expression () has merrily parsed up to the end of line,
3805 or a comma - in the wrong buffer. Transfer how far
3806 input_line_pointer has moved to the right buffer. */
3807 input_line_pointer
= (save
3808 + (input_line_pointer
- gotfree_input_line
)
3810 free (gotfree_input_line
);
3821 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3827 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3829 if (exp
->X_op
== O_secrel
)
3831 exp
->X_op
= O_symbol
;
3832 r
= BFD_RELOC_32_SECREL
;
3835 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3839 pe_directive_secrel (dummy
)
3840 int dummy ATTRIBUTE_UNUSED
;
3847 if (exp
.X_op
== O_symbol
)
3848 exp
.X_op
= O_secrel
;
3850 emit_expr (&exp
, 4);
3852 while (*input_line_pointer
++ == ',');
3854 input_line_pointer
--;
3855 demand_empty_rest_of_line ();
3860 static int i386_immediate
PARAMS ((char *));
3863 i386_immediate (imm_start
)
3866 char *save_input_line_pointer
;
3868 char *gotfree_input_line
;
3873 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3875 as_bad (_("only 1 or 2 immediate operands are allowed"));
3879 exp
= &im_expressions
[i
.imm_operands
++];
3880 i
.op
[this_operand
].imms
= exp
;
3882 if (is_space_char (*imm_start
))
3885 save_input_line_pointer
= input_line_pointer
;
3886 input_line_pointer
= imm_start
;
3889 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3890 if (gotfree_input_line
)
3891 input_line_pointer
= gotfree_input_line
;
3894 exp_seg
= expression (exp
);
3897 if (*input_line_pointer
)
3898 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3900 input_line_pointer
= save_input_line_pointer
;
3902 if (gotfree_input_line
)
3903 free (gotfree_input_line
);
3906 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3908 /* Missing or bad expr becomes absolute 0. */
3909 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3911 exp
->X_op
= O_constant
;
3912 exp
->X_add_number
= 0;
3913 exp
->X_add_symbol
= (symbolS
*) 0;
3914 exp
->X_op_symbol
= (symbolS
*) 0;
3916 else if (exp
->X_op
== O_constant
)
3918 /* Size it properly later. */
3919 i
.types
[this_operand
] |= Imm64
;
3920 /* If BFD64, sign extend val. */
3921 if (!use_rela_relocations
)
3922 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3923 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3925 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3926 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3927 && exp_seg
!= absolute_section
3928 && exp_seg
!= text_section
3929 && exp_seg
!= data_section
3930 && exp_seg
!= bss_section
3931 && exp_seg
!= undefined_section
3932 && !bfd_is_com_section (exp_seg
))
3934 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3940 /* This is an address. The size of the address will be
3941 determined later, depending on destination register,
3942 suffix, or the default for the section. */
3943 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3949 static char *i386_scale
PARAMS ((char *));
3956 char *save
= input_line_pointer
;
3958 input_line_pointer
= scale
;
3959 val
= get_absolute_expression ();
3964 i
.log2_scale_factor
= 0;
3967 i
.log2_scale_factor
= 1;
3970 i
.log2_scale_factor
= 2;
3973 i
.log2_scale_factor
= 3;
3977 char sep
= *input_line_pointer
;
3979 *input_line_pointer
= '\0';
3980 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3982 *input_line_pointer
= sep
;
3983 input_line_pointer
= save
;
3987 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3989 as_warn (_("scale factor of %d without an index register"),
3990 1 << i
.log2_scale_factor
);
3991 #if SCALE1_WHEN_NO_INDEX
3992 i
.log2_scale_factor
= 0;
3995 scale
= input_line_pointer
;
3996 input_line_pointer
= save
;
4000 static int i386_displacement
PARAMS ((char *, char *));
4003 i386_displacement (disp_start
, disp_end
)
4009 char *save_input_line_pointer
;
4011 char *gotfree_input_line
;
4013 int bigdisp
= Disp32
;
4015 if (flag_code
== CODE_64BIT
)
4017 if (i
.prefix
[ADDR_PREFIX
] == 0)
4020 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4022 i
.types
[this_operand
] |= bigdisp
;
4024 exp
= &disp_expressions
[i
.disp_operands
];
4025 i
.op
[this_operand
].disps
= exp
;
4027 save_input_line_pointer
= input_line_pointer
;
4028 input_line_pointer
= disp_start
;
4029 END_STRING_AND_SAVE (disp_end
);
4031 #ifndef GCC_ASM_O_HACK
4032 #define GCC_ASM_O_HACK 0
4035 END_STRING_AND_SAVE (disp_end
+ 1);
4036 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4037 && displacement_string_end
[-1] == '+')
4039 /* This hack is to avoid a warning when using the "o"
4040 constraint within gcc asm statements.
4043 #define _set_tssldt_desc(n,addr,limit,type) \
4044 __asm__ __volatile__ ( \
4046 "movw %w1,2+%0\n\t" \
4048 "movb %b1,4+%0\n\t" \
4049 "movb %4,5+%0\n\t" \
4050 "movb $0,6+%0\n\t" \
4051 "movb %h1,7+%0\n\t" \
4053 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4055 This works great except that the output assembler ends
4056 up looking a bit weird if it turns out that there is
4057 no offset. You end up producing code that looks like:
4070 So here we provide the missing zero. */
4072 *displacement_string_end
= '0';
4076 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
4077 if (gotfree_input_line
)
4078 input_line_pointer
= gotfree_input_line
;
4081 exp_seg
= expression (exp
);
4084 if (*input_line_pointer
)
4085 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4087 RESTORE_END_STRING (disp_end
+ 1);
4089 RESTORE_END_STRING (disp_end
);
4090 input_line_pointer
= save_input_line_pointer
;
4092 if (gotfree_input_line
)
4093 free (gotfree_input_line
);
4096 /* We do this to make sure that the section symbol is in
4097 the symbol table. We will ultimately change the relocation
4098 to be relative to the beginning of the section. */
4099 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4100 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4102 if (exp
->X_op
!= O_symbol
)
4104 as_bad (_("bad expression used with @%s"),
4105 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4111 if (S_IS_LOCAL (exp
->X_add_symbol
)
4112 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4113 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4114 exp
->X_op
= O_subtract
;
4115 exp
->X_op_symbol
= GOT_symbol
;
4116 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4117 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4119 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4122 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4124 /* Missing or bad expr becomes absolute 0. */
4125 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4127 exp
->X_op
= O_constant
;
4128 exp
->X_add_number
= 0;
4129 exp
->X_add_symbol
= (symbolS
*) 0;
4130 exp
->X_op_symbol
= (symbolS
*) 0;
4133 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4134 if (exp
->X_op
!= O_constant
4135 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4136 && exp_seg
!= absolute_section
4137 && exp_seg
!= text_section
4138 && exp_seg
!= data_section
4139 && exp_seg
!= bss_section
4140 && exp_seg
!= undefined_section
4141 && !bfd_is_com_section (exp_seg
))
4143 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4147 else if (flag_code
== CODE_64BIT
)
4148 i
.types
[this_operand
] |= Disp32S
| Disp32
;
4152 static int i386_index_check
PARAMS ((const char *));
4154 /* Make sure the memory operand we've been dealt is valid.
4155 Return 1 on success, 0 on a failure. */
4158 i386_index_check (operand_string
)
4159 const char *operand_string
;
4162 #if INFER_ADDR_PREFIX
4168 if (flag_code
== CODE_64BIT
)
4170 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4173 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4174 && (i
.base_reg
->reg_type
!= BaseIndex
4177 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4178 != (RegXX
| BaseIndex
))))
4183 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4187 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4188 != (Reg16
| BaseIndex
)))
4190 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4191 != (Reg16
| BaseIndex
))
4193 && i
.base_reg
->reg_num
< 6
4194 && i
.index_reg
->reg_num
>= 6
4195 && i
.log2_scale_factor
== 0))))
4202 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4204 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4205 != (Reg32
| BaseIndex
))))
4211 #if INFER_ADDR_PREFIX
4212 if (i
.prefix
[ADDR_PREFIX
] == 0)
4214 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4216 /* Change the size of any displacement too. At most one of
4217 Disp16 or Disp32 is set.
4218 FIXME. There doesn't seem to be any real need for separate
4219 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4220 Removing them would probably clean up the code quite a lot. */
4221 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4222 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4227 as_bad (_("`%s' is not a valid base/index expression"),
4231 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4233 flag_code_names
[flag_code
]);
4238 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4242 i386_operand (operand_string
)
4243 char *operand_string
;
4247 char *op_string
= operand_string
;
4249 if (is_space_char (*op_string
))
4252 /* We check for an absolute prefix (differentiating,
4253 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4254 if (*op_string
== ABSOLUTE_PREFIX
)
4257 if (is_space_char (*op_string
))
4259 i
.types
[this_operand
] |= JumpAbsolute
;
4262 /* Check if operand is a register. */
4263 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4264 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4266 /* Check for a segment override by searching for ':' after a
4267 segment register. */
4269 if (is_space_char (*op_string
))
4271 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4276 i
.seg
[i
.mem_operands
] = &es
;
4279 i
.seg
[i
.mem_operands
] = &cs
;
4282 i
.seg
[i
.mem_operands
] = &ss
;
4285 i
.seg
[i
.mem_operands
] = &ds
;
4288 i
.seg
[i
.mem_operands
] = &fs
;
4291 i
.seg
[i
.mem_operands
] = &gs
;
4295 /* Skip the ':' and whitespace. */
4297 if (is_space_char (*op_string
))
4300 if (!is_digit_char (*op_string
)
4301 && !is_identifier_char (*op_string
)
4302 && *op_string
!= '('
4303 && *op_string
!= ABSOLUTE_PREFIX
)
4305 as_bad (_("bad memory operand `%s'"), op_string
);
4308 /* Handle case of %es:*foo. */
4309 if (*op_string
== ABSOLUTE_PREFIX
)
4312 if (is_space_char (*op_string
))
4314 i
.types
[this_operand
] |= JumpAbsolute
;
4316 goto do_memory_reference
;
4320 as_bad (_("junk `%s' after register"), op_string
);
4323 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4324 i
.op
[this_operand
].regs
= r
;
4327 else if (*op_string
== REGISTER_PREFIX
)
4329 as_bad (_("bad register name `%s'"), op_string
);
4332 else if (*op_string
== IMMEDIATE_PREFIX
)
4335 if (i
.types
[this_operand
] & JumpAbsolute
)
4337 as_bad (_("immediate operand illegal with absolute jump"));
4340 if (!i386_immediate (op_string
))
4343 else if (is_digit_char (*op_string
)
4344 || is_identifier_char (*op_string
)
4345 || *op_string
== '(')
4347 /* This is a memory reference of some sort. */
4350 /* Start and end of displacement string expression (if found). */
4351 char *displacement_string_start
;
4352 char *displacement_string_end
;
4354 do_memory_reference
:
4355 if ((i
.mem_operands
== 1
4356 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4357 || i
.mem_operands
== 2)
4359 as_bad (_("too many memory references for `%s'"),
4360 current_templates
->start
->name
);
4364 /* Check for base index form. We detect the base index form by
4365 looking for an ')' at the end of the operand, searching
4366 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4368 base_string
= op_string
+ strlen (op_string
);
4371 if (is_space_char (*base_string
))
4374 /* If we only have a displacement, set-up for it to be parsed later. */
4375 displacement_string_start
= op_string
;
4376 displacement_string_end
= base_string
+ 1;
4378 if (*base_string
== ')')
4381 unsigned int parens_balanced
= 1;
4382 /* We've already checked that the number of left & right ()'s are
4383 equal, so this loop will not be infinite. */
4387 if (*base_string
== ')')
4389 if (*base_string
== '(')
4392 while (parens_balanced
);
4394 temp_string
= base_string
;
4396 /* Skip past '(' and whitespace. */
4398 if (is_space_char (*base_string
))
4401 if (*base_string
== ','
4402 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4403 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4405 displacement_string_end
= temp_string
;
4407 i
.types
[this_operand
] |= BaseIndex
;
4411 base_string
= end_op
;
4412 if (is_space_char (*base_string
))
4416 /* There may be an index reg or scale factor here. */
4417 if (*base_string
== ',')
4420 if (is_space_char (*base_string
))
4423 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4424 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4426 base_string
= end_op
;
4427 if (is_space_char (*base_string
))
4429 if (*base_string
== ',')
4432 if (is_space_char (*base_string
))
4435 else if (*base_string
!= ')')
4437 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4442 else if (*base_string
== REGISTER_PREFIX
)
4444 as_bad (_("bad register name `%s'"), base_string
);
4448 /* Check for scale factor. */
4449 if (*base_string
!= ')')
4451 char *end_scale
= i386_scale (base_string
);
4456 base_string
= end_scale
;
4457 if (is_space_char (*base_string
))
4459 if (*base_string
!= ')')
4461 as_bad (_("expecting `)' after scale factor in `%s'"),
4466 else if (!i
.index_reg
)
4468 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4473 else if (*base_string
!= ')')
4475 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4480 else if (*base_string
== REGISTER_PREFIX
)
4482 as_bad (_("bad register name `%s'"), base_string
);
4487 /* If there's an expression beginning the operand, parse it,
4488 assuming displacement_string_start and
4489 displacement_string_end are meaningful. */
4490 if (displacement_string_start
!= displacement_string_end
)
4492 if (!i386_displacement (displacement_string_start
,
4493 displacement_string_end
))
4497 /* Special case for (%dx) while doing input/output op. */
4499 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4501 && i
.log2_scale_factor
== 0
4502 && i
.seg
[i
.mem_operands
] == 0
4503 && (i
.types
[this_operand
] & Disp
) == 0)
4505 i
.types
[this_operand
] = InOutPortReg
;
4509 if (i386_index_check (operand_string
) == 0)
4515 /* It's not a memory operand; argh! */
4516 as_bad (_("invalid char %s beginning operand %d `%s'"),
4517 output_invalid (*op_string
),
4522 return 1; /* Normal return. */
4525 /* md_estimate_size_before_relax()
4527 Called just before relax() for rs_machine_dependent frags. The x86
4528 assembler uses these frags to handle variable size jump
4531 Any symbol that is now undefined will not become defined.
4532 Return the correct fr_subtype in the frag.
4533 Return the initial "guess for variable size of frag" to caller.
4534 The guess is actually the growth beyond the fixed part. Whatever
4535 we do to grow the fixed or variable part contributes to our
4539 md_estimate_size_before_relax (fragP
, segment
)
4543 /* We've already got fragP->fr_subtype right; all we have to do is
4544 check for un-relaxable symbols. On an ELF system, we can't relax
4545 an externally visible symbol, because it may be overridden by a
4547 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4549 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4550 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4551 || S_IS_WEAK (fragP
->fr_symbol
)))
4555 /* Symbol is undefined in this segment, or we need to keep a
4556 reloc so that weak symbols can be overridden. */
4557 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4558 enum bfd_reloc_code_real reloc_type
;
4559 unsigned char *opcode
;
4562 if (fragP
->fr_var
!= NO_RELOC
)
4563 reloc_type
= fragP
->fr_var
;
4565 reloc_type
= BFD_RELOC_16_PCREL
;
4567 reloc_type
= BFD_RELOC_32_PCREL
;
4569 old_fr_fix
= fragP
->fr_fix
;
4570 opcode
= (unsigned char *) fragP
->fr_opcode
;
4572 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4575 /* Make jmp (0xeb) a (d)word displacement jump. */
4577 fragP
->fr_fix
+= size
;
4578 fix_new (fragP
, old_fr_fix
, size
,
4580 fragP
->fr_offset
, 1,
4586 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4588 /* Negate the condition, and branch past an
4589 unconditional jump. */
4592 /* Insert an unconditional jump. */
4594 /* We added two extra opcode bytes, and have a two byte
4596 fragP
->fr_fix
+= 2 + 2;
4597 fix_new (fragP
, old_fr_fix
+ 2, 2,
4599 fragP
->fr_offset
, 1,
4606 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4611 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4613 fragP
->fr_offset
, 1,
4615 fixP
->fx_signed
= 1;
4619 /* This changes the byte-displacement jump 0x7N
4620 to the (d)word-displacement jump 0x0f,0x8N. */
4621 opcode
[1] = opcode
[0] + 0x10;
4622 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4623 /* We've added an opcode byte. */
4624 fragP
->fr_fix
+= 1 + size
;
4625 fix_new (fragP
, old_fr_fix
+ 1, size
,
4627 fragP
->fr_offset
, 1,
4632 BAD_CASE (fragP
->fr_subtype
);
4636 return fragP
->fr_fix
- old_fr_fix
;
4639 /* Guess size depending on current relax state. Initially the relax
4640 state will correspond to a short jump and we return 1, because
4641 the variable part of the frag (the branch offset) is one byte
4642 long. However, we can relax a section more than once and in that
4643 case we must either set fr_subtype back to the unrelaxed state,
4644 or return the value for the appropriate branch. */
4645 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4648 /* Called after relax() is finished.
4650 In: Address of frag.
4651 fr_type == rs_machine_dependent.
4652 fr_subtype is what the address relaxed to.
4654 Out: Any fixSs and constants are set up.
4655 Caller will turn frag into a ".space 0". */
4658 md_convert_frag (abfd
, sec
, fragP
)
4659 bfd
*abfd ATTRIBUTE_UNUSED
;
4660 segT sec ATTRIBUTE_UNUSED
;
4663 unsigned char *opcode
;
4664 unsigned char *where_to_put_displacement
= NULL
;
4665 offsetT target_address
;
4666 offsetT opcode_address
;
4667 unsigned int extension
= 0;
4668 offsetT displacement_from_opcode_start
;
4670 opcode
= (unsigned char *) fragP
->fr_opcode
;
4672 /* Address we want to reach in file space. */
4673 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4675 /* Address opcode resides at in file space. */
4676 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4678 /* Displacement from opcode start to fill into instruction. */
4679 displacement_from_opcode_start
= target_address
- opcode_address
;
4681 if ((fragP
->fr_subtype
& BIG
) == 0)
4683 /* Don't have to change opcode. */
4684 extension
= 1; /* 1 opcode + 1 displacement */
4685 where_to_put_displacement
= &opcode
[1];
4689 if (no_cond_jump_promotion
4690 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4691 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4693 switch (fragP
->fr_subtype
)
4695 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4696 extension
= 4; /* 1 opcode + 4 displacement */
4698 where_to_put_displacement
= &opcode
[1];
4701 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4702 extension
= 2; /* 1 opcode + 2 displacement */
4704 where_to_put_displacement
= &opcode
[1];
4707 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4708 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4709 extension
= 5; /* 2 opcode + 4 displacement */
4710 opcode
[1] = opcode
[0] + 0x10;
4711 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4712 where_to_put_displacement
= &opcode
[2];
4715 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4716 extension
= 3; /* 2 opcode + 2 displacement */
4717 opcode
[1] = opcode
[0] + 0x10;
4718 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4719 where_to_put_displacement
= &opcode
[2];
4722 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4727 where_to_put_displacement
= &opcode
[3];
4731 BAD_CASE (fragP
->fr_subtype
);
4736 /* Now put displacement after opcode. */
4737 md_number_to_chars ((char *) where_to_put_displacement
,
4738 (valueT
) (displacement_from_opcode_start
- extension
),
4739 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4740 fragP
->fr_fix
+= extension
;
4743 /* Size of byte displacement jmp. */
4744 int md_short_jump_size
= 2;
4746 /* Size of dword displacement jmp. */
4747 int md_long_jump_size
= 5;
4749 /* Size of relocation record. */
4750 const int md_reloc_size
= 8;
4753 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4755 addressT from_addr
, to_addr
;
4756 fragS
*frag ATTRIBUTE_UNUSED
;
4757 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4761 offset
= to_addr
- (from_addr
+ 2);
4762 /* Opcode for byte-disp jump. */
4763 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4764 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4768 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4770 addressT from_addr
, to_addr
;
4771 fragS
*frag ATTRIBUTE_UNUSED
;
4772 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4776 offset
= to_addr
- (from_addr
+ 5);
4777 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4778 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4781 /* Apply a fixup (fixS) to segment data, once it has been determined
4782 by our caller that we have all the info we need to fix it up.
4784 On the 386, immediates, displacements, and data pointers are all in
4785 the same (little-endian) format, so we don't need to care about which
4789 md_apply_fix3 (fixP
, valP
, seg
)
4790 /* The fix we're to put in. */
4792 /* Pointer to the value of the bits. */
4794 /* Segment fix is from. */
4795 segT seg ATTRIBUTE_UNUSED
;
4797 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4798 valueT value
= *valP
;
4800 #if !defined (TE_Mach)
4803 switch (fixP
->fx_r_type
)
4809 case BFD_RELOC_X86_64_32S
:
4810 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4813 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4816 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4821 if (fixP
->fx_addsy
!= NULL
4822 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4823 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4824 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4825 && !use_rela_relocations
)
4827 /* This is a hack. There should be a better way to handle this.
4828 This covers for the fact that bfd_install_relocation will
4829 subtract the current location (for partial_inplace, PC relative
4830 relocations); see more below. */
4832 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4834 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4837 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4839 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4840 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4842 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4845 || (symbol_section_p (fixP
->fx_addsy
)
4846 && sym_seg
!= absolute_section
))
4847 && !generic_force_reloc (fixP
))
4849 /* Yes, we add the values in twice. This is because
4850 bfd_install_relocation subtracts them out again. I think
4851 bfd_install_relocation is broken, but I don't dare change
4853 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4857 #if defined (OBJ_COFF) && defined (TE_PE)
4858 /* For some reason, the PE format does not store a
4859 section address offset for a PC relative symbol. */
4860 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4861 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4862 || S_IS_WEAK (fixP
->fx_addsy
)
4865 value
+= md_pcrel_from (fixP
);
4869 /* Fix a few things - the dynamic linker expects certain values here,
4870 and we must not disappoint it. */
4871 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4872 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4874 switch (fixP
->fx_r_type
)
4876 case BFD_RELOC_386_PLT32
:
4877 case BFD_RELOC_X86_64_PLT32
:
4878 /* Make the jump instruction point to the address of the operand. At
4879 runtime we merely add the offset to the actual PLT entry. */
4883 case BFD_RELOC_386_TLS_GD
:
4884 case BFD_RELOC_386_TLS_LDM
:
4885 case BFD_RELOC_386_TLS_IE_32
:
4886 case BFD_RELOC_386_TLS_IE
:
4887 case BFD_RELOC_386_TLS_GOTIE
:
4888 case BFD_RELOC_X86_64_TLSGD
:
4889 case BFD_RELOC_X86_64_TLSLD
:
4890 case BFD_RELOC_X86_64_GOTTPOFF
:
4891 value
= 0; /* Fully resolved at runtime. No addend. */
4893 case BFD_RELOC_386_TLS_LE
:
4894 case BFD_RELOC_386_TLS_LDO_32
:
4895 case BFD_RELOC_386_TLS_LE_32
:
4896 case BFD_RELOC_X86_64_DTPOFF32
:
4897 case BFD_RELOC_X86_64_TPOFF32
:
4898 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4901 case BFD_RELOC_386_GOT32
:
4902 case BFD_RELOC_X86_64_GOT32
:
4903 value
= 0; /* Fully resolved at runtime. No addend. */
4906 case BFD_RELOC_VTABLE_INHERIT
:
4907 case BFD_RELOC_VTABLE_ENTRY
:
4914 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4916 #endif /* !defined (TE_Mach) */
4918 /* Are we finished with this relocation now? */
4919 if (fixP
->fx_addsy
== NULL
)
4921 else if (use_rela_relocations
)
4923 fixP
->fx_no_overflow
= 1;
4924 /* Remember value for tc_gen_reloc. */
4925 fixP
->fx_addnumber
= value
;
4929 md_number_to_chars (p
, value
, fixP
->fx_size
);
4932 #define MAX_LITTLENUMS 6
4934 /* Turn the string pointed to by litP into a floating point constant
4935 of type TYPE, and emit the appropriate bytes. The number of
4936 LITTLENUMS emitted is stored in *SIZEP. An error message is
4937 returned, or NULL on OK. */
4940 md_atof (type
, litP
, sizeP
)
4946 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4947 LITTLENUM_TYPE
*wordP
;
4969 return _("Bad call to md_atof ()");
4971 t
= atof_ieee (input_line_pointer
, type
, words
);
4973 input_line_pointer
= t
;
4975 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4976 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4977 the bigendian 386. */
4978 for (wordP
= words
+ prec
- 1; prec
--;)
4980 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4981 litP
+= sizeof (LITTLENUM_TYPE
);
4986 static char output_invalid_buf
[8];
4993 sprintf (output_invalid_buf
, "'%c'", c
);
4995 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4996 return output_invalid_buf
;
4999 /* REG_STRING starts *before* REGISTER_PREFIX. */
5001 static const reg_entry
*
5002 parse_register (reg_string
, end_op
)
5006 char *s
= reg_string
;
5008 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5011 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5012 if (*s
== REGISTER_PREFIX
)
5015 if (is_space_char (*s
))
5019 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5021 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5022 return (const reg_entry
*) NULL
;
5026 /* For naked regs, make sure that we are not dealing with an identifier.
5027 This prevents confusing an identifier like `eax_var' with register
5029 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5030 return (const reg_entry
*) NULL
;
5034 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5036 /* Handle floating point regs, allowing spaces in the (i) part. */
5037 if (r
== i386_regtab
/* %st is first entry of table */)
5039 if (is_space_char (*s
))
5044 if (is_space_char (*s
))
5046 if (*s
>= '0' && *s
<= '7')
5048 r
= &i386_float_regtab
[*s
- '0'];
5050 if (is_space_char (*s
))
5058 /* We have "%st(" then garbage. */
5059 return (const reg_entry
*) NULL
;
5064 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5065 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5066 && flag_code
!= CODE_64BIT
)
5067 return (const reg_entry
*) NULL
;
5072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5073 const char *md_shortopts
= "kVQ:sqn";
5075 const char *md_shortopts
= "qn";
5078 struct option md_longopts
[] = {
5079 #define OPTION_32 (OPTION_MD_BASE + 0)
5080 {"32", no_argument
, NULL
, OPTION_32
},
5081 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5082 #define OPTION_64 (OPTION_MD_BASE + 1)
5083 {"64", no_argument
, NULL
, OPTION_64
},
5085 {NULL
, no_argument
, NULL
, 0}
5087 size_t md_longopts_size
= sizeof (md_longopts
);
5090 md_parse_option (c
, arg
)
5092 char *arg ATTRIBUTE_UNUSED
;
5097 optimize_align_code
= 0;
5104 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5105 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5106 should be emitted or not. FIXME: Not implemented. */
5110 /* -V: SVR4 argument to print version ID. */
5112 print_version_id ();
5115 /* -k: Ignore for FreeBSD compatibility. */
5120 /* -s: On i386 Solaris, this tells the native assembler to use
5121 .stab instead of .stab.excl. We always use .stab anyhow. */
5126 const char **list
, **l
;
5128 list
= bfd_target_list ();
5129 for (l
= list
; *l
!= NULL
; l
++)
5130 if (strcmp (*l
, "elf64-x86-64") == 0)
5132 default_arch
= "x86_64";
5136 as_fatal (_("No compiled in support for x86_64"));
5143 default_arch
= "i386";
5153 md_show_usage (stream
)
5156 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5157 fprintf (stream
, _("\
5159 -V print assembler version number\n\
5161 -n Do not optimize code alignment\n\
5162 -q quieten some warnings\n\
5165 fprintf (stream
, _("\
5166 -n Do not optimize code alignment\n\
5167 -q quieten some warnings\n"));
5171 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5172 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5174 /* Pick the target format to use. */
5177 i386_target_format ()
5179 if (!strcmp (default_arch
, "x86_64"))
5180 set_code_flag (CODE_64BIT
);
5181 else if (!strcmp (default_arch
, "i386"))
5182 set_code_flag (CODE_32BIT
);
5184 as_fatal (_("Unknown architecture"));
5185 switch (OUTPUT_FLAVOR
)
5187 #ifdef OBJ_MAYBE_AOUT
5188 case bfd_target_aout_flavour
:
5189 return AOUT_TARGET_FORMAT
;
5191 #ifdef OBJ_MAYBE_COFF
5192 case bfd_target_coff_flavour
:
5195 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5196 case bfd_target_elf_flavour
:
5198 if (flag_code
== CODE_64BIT
)
5199 use_rela_relocations
= 1;
5200 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5209 #endif /* OBJ_MAYBE_ more than one */
5211 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5212 void i386_elf_emit_arch_note ()
5214 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5215 && cpu_arch_name
!= NULL
)
5218 asection
*seg
= now_seg
;
5219 subsegT subseg
= now_subseg
;
5220 Elf_Internal_Note i_note
;
5221 Elf_External_Note e_note
;
5222 asection
*note_secp
;
5225 /* Create the .note section. */
5226 note_secp
= subseg_new (".note", 0);
5227 bfd_set_section_flags (stdoutput
,
5229 SEC_HAS_CONTENTS
| SEC_READONLY
);
5231 /* Process the arch string. */
5232 len
= strlen (cpu_arch_name
);
5234 i_note
.namesz
= len
+ 1;
5236 i_note
.type
= NT_ARCH
;
5237 p
= frag_more (sizeof (e_note
.namesz
));
5238 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5239 p
= frag_more (sizeof (e_note
.descsz
));
5240 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5241 p
= frag_more (sizeof (e_note
.type
));
5242 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5243 p
= frag_more (len
+ 1);
5244 strcpy (p
, cpu_arch_name
);
5246 frag_align (2, 0, 0);
5248 subseg_set (seg
, subseg
);
5254 md_undefined_symbol (name
)
5257 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5258 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5259 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5260 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5264 if (symbol_find (name
))
5265 as_bad (_("GOT already in symbol table"));
5266 GOT_symbol
= symbol_new (name
, undefined_section
,
5267 (valueT
) 0, &zero_address_frag
);
5274 /* Round up a section size to the appropriate boundary. */
5277 md_section_align (segment
, size
)
5278 segT segment ATTRIBUTE_UNUSED
;
5281 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5282 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5284 /* For a.out, force the section size to be aligned. If we don't do
5285 this, BFD will align it for us, but it will not write out the
5286 final bytes of the section. This may be a bug in BFD, but it is
5287 easier to fix it here since that is how the other a.out targets
5291 align
= bfd_get_section_alignment (stdoutput
, segment
);
5292 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5299 /* On the i386, PC-relative offsets are relative to the start of the
5300 next instruction. That is, the address of the offset, plus its
5301 size, since the offset is always the last part of the insn. */
5304 md_pcrel_from (fixP
)
5307 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5314 int ignore ATTRIBUTE_UNUSED
;
5318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5320 obj_elf_section_change_hook ();
5322 temp
= get_absolute_expression ();
5323 subseg_set (bss_section
, (subsegT
) temp
);
5324 demand_empty_rest_of_line ();
5330 i386_validate_fix (fixp
)
5333 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5335 /* GOTOFF relocation are nonsense in 64bit mode. */
5336 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5338 if (flag_code
!= CODE_64BIT
)
5340 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5344 if (flag_code
== CODE_64BIT
)
5346 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5353 tc_gen_reloc (section
, fixp
)
5354 asection
*section ATTRIBUTE_UNUSED
;
5358 bfd_reloc_code_real_type code
;
5360 switch (fixp
->fx_r_type
)
5362 case BFD_RELOC_X86_64_PLT32
:
5363 case BFD_RELOC_X86_64_GOT32
:
5364 case BFD_RELOC_X86_64_GOTPCREL
:
5365 case BFD_RELOC_386_PLT32
:
5366 case BFD_RELOC_386_GOT32
:
5367 case BFD_RELOC_386_GOTOFF
:
5368 case BFD_RELOC_386_GOTPC
:
5369 case BFD_RELOC_386_TLS_GD
:
5370 case BFD_RELOC_386_TLS_LDM
:
5371 case BFD_RELOC_386_TLS_LDO_32
:
5372 case BFD_RELOC_386_TLS_IE_32
:
5373 case BFD_RELOC_386_TLS_IE
:
5374 case BFD_RELOC_386_TLS_GOTIE
:
5375 case BFD_RELOC_386_TLS_LE_32
:
5376 case BFD_RELOC_386_TLS_LE
:
5377 case BFD_RELOC_X86_64_TLSGD
:
5378 case BFD_RELOC_X86_64_TLSLD
:
5379 case BFD_RELOC_X86_64_DTPOFF32
:
5380 case BFD_RELOC_X86_64_GOTTPOFF
:
5381 case BFD_RELOC_X86_64_TPOFF32
:
5383 case BFD_RELOC_VTABLE_ENTRY
:
5384 case BFD_RELOC_VTABLE_INHERIT
:
5386 case BFD_RELOC_32_SECREL
:
5388 code
= fixp
->fx_r_type
;
5390 case BFD_RELOC_X86_64_32S
:
5391 if (!fixp
->fx_pcrel
)
5393 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5394 code
= fixp
->fx_r_type
;
5400 switch (fixp
->fx_size
)
5403 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5404 _("can not do %d byte pc-relative relocation"),
5406 code
= BFD_RELOC_32_PCREL
;
5408 case 1: code
= BFD_RELOC_8_PCREL
; break;
5409 case 2: code
= BFD_RELOC_16_PCREL
; break;
5410 case 4: code
= BFD_RELOC_32_PCREL
; break;
5415 switch (fixp
->fx_size
)
5418 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5419 _("can not do %d byte relocation"),
5421 code
= BFD_RELOC_32
;
5423 case 1: code
= BFD_RELOC_8
; break;
5424 case 2: code
= BFD_RELOC_16
; break;
5425 case 4: code
= BFD_RELOC_32
; break;
5427 case 8: code
= BFD_RELOC_64
; break;
5434 if (code
== BFD_RELOC_32
5436 && fixp
->fx_addsy
== GOT_symbol
)
5438 /* We don't support GOTPC on 64bit targets. */
5439 if (flag_code
== CODE_64BIT
)
5441 code
= BFD_RELOC_386_GOTPC
;
5444 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5445 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5446 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5448 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5450 if (!use_rela_relocations
)
5452 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5453 vtable entry to be used in the relocation's section offset. */
5454 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5455 rel
->address
= fixp
->fx_offset
;
5459 /* Use the rela in 64bit mode. */
5462 if (!fixp
->fx_pcrel
)
5463 rel
->addend
= fixp
->fx_offset
;
5467 case BFD_RELOC_X86_64_PLT32
:
5468 case BFD_RELOC_X86_64_GOT32
:
5469 case BFD_RELOC_X86_64_GOTPCREL
:
5470 case BFD_RELOC_X86_64_TLSGD
:
5471 case BFD_RELOC_X86_64_TLSLD
:
5472 case BFD_RELOC_X86_64_GOTTPOFF
:
5473 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5476 rel
->addend
= (section
->vma
5478 + fixp
->fx_addnumber
5479 + md_pcrel_from (fixp
));
5484 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5485 if (rel
->howto
== NULL
)
5487 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5488 _("cannot represent relocation type %s"),
5489 bfd_get_reloc_code_name (code
));
5490 /* Set howto to a garbage value so that we can keep going. */
5491 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5492 assert (rel
->howto
!= NULL
);
5499 /* Parse operands using Intel syntax. This implements a recursive descent
5500 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5503 FIXME: We do not recognize the full operand grammar defined in the MASM
5504 documentation. In particular, all the structure/union and
5505 high-level macro operands are missing.
5507 Uppercase words are terminals, lower case words are non-terminals.
5508 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5509 bars '|' denote choices. Most grammar productions are implemented in
5510 functions called 'intel_<production>'.
5512 Initial production is 'expr'.
5518 binOp & | AND | \| | OR | ^ | XOR
5520 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5522 constant digits [[ radixOverride ]]
5524 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5562 => expr expr cmpOp e04
5565 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5566 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5568 hexdigit a | b | c | d | e | f
5569 | A | B | C | D | E | F
5575 mulOp * | / | % | MOD | << | SHL | >> | SHR
5579 register specialRegister
5583 segmentRegister CS | DS | ES | FS | GS | SS
5585 specialRegister CR0 | CR2 | CR3 | CR4
5586 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5587 | TR3 | TR4 | TR5 | TR6 | TR7
5589 We simplify the grammar in obvious places (e.g., register parsing is
5590 done by calling parse_register) and eliminate immediate left recursion
5591 to implement a recursive-descent parser.
5595 expr' cmpOp e04 expr'
5646 /* Parsing structure for the intel syntax parser. Used to implement the
5647 semantic actions for the operand grammar. */
5648 struct intel_parser_s
5650 char *op_string
; /* The string being parsed. */
5651 int got_a_float
; /* Whether the operand is a float. */
5652 int op_modifier
; /* Operand modifier. */
5653 int is_mem
; /* 1 if operand is memory reference. */
5654 int in_offset
; /* >=1 if parsing operand of offset. */
5655 int in_bracket
; /* >=1 if parsing operand in brackets. */
5656 const reg_entry
*reg
; /* Last register reference found. */
5657 char *disp
; /* Displacement string being built. */
5658 char *next_operand
; /* Resume point when splitting operands. */
5661 static struct intel_parser_s intel_parser
;
5663 /* Token structure for parsing intel syntax. */
5666 int code
; /* Token code. */
5667 const reg_entry
*reg
; /* Register entry for register tokens. */
5668 char *str
; /* String representation. */
5671 static struct intel_token cur_token
, prev_token
;
5673 /* Token codes for the intel parser. Since T_SHORT is already used
5674 by COFF, undefine it first to prevent a warning. */
5693 /* Prototypes for intel parser functions. */
5694 static int intel_match_token
PARAMS ((int code
));
5695 static void intel_get_token
PARAMS ((void));
5696 static void intel_putback_token
PARAMS ((void));
5697 static int intel_expr
PARAMS ((void));
5698 static int intel_e04
PARAMS ((void));
5699 static int intel_e05
PARAMS ((void));
5700 static int intel_e06
PARAMS ((void));
5701 static int intel_e09
PARAMS ((void));
5702 static int intel_bracket_expr
PARAMS ((void));
5703 static int intel_e10
PARAMS ((void));
5704 static int intel_e11
PARAMS ((void));
5707 i386_intel_operand (operand_string
, got_a_float
)
5708 char *operand_string
;
5714 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5715 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5719 /* Initialize token holders. */
5720 cur_token
.code
= prev_token
.code
= T_NIL
;
5721 cur_token
.reg
= prev_token
.reg
= NULL
;
5722 cur_token
.str
= prev_token
.str
= NULL
;
5724 /* Initialize parser structure. */
5725 intel_parser
.got_a_float
= got_a_float
;
5726 intel_parser
.op_modifier
= 0;
5727 intel_parser
.is_mem
= 0;
5728 intel_parser
.in_offset
= 0;
5729 intel_parser
.in_bracket
= 0;
5730 intel_parser
.reg
= NULL
;
5731 intel_parser
.disp
[0] = '\0';
5732 intel_parser
.next_operand
= NULL
;
5734 /* Read the first token and start the parser. */
5736 ret
= intel_expr ();
5741 if (cur_token
.code
!= T_NIL
)
5743 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5744 current_templates
->start
->name
, cur_token
.str
);
5747 /* If we found a memory reference, hand it over to i386_displacement
5748 to fill in the rest of the operand fields. */
5749 else if (intel_parser
.is_mem
)
5751 if ((i
.mem_operands
== 1
5752 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5753 || i
.mem_operands
== 2)
5755 as_bad (_("too many memory references for '%s'"),
5756 current_templates
->start
->name
);
5761 char *s
= intel_parser
.disp
;
5764 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5765 /* See the comments in intel_bracket_expr. */
5766 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5768 /* Add the displacement expression. */
5770 ret
= i386_displacement (s
, s
+ strlen (s
));
5773 /* Swap base and index in 16-bit memory operands like
5774 [si+bx]. Since i386_index_check is also used in AT&T
5775 mode we have to do that here. */
5778 && (i
.base_reg
->reg_type
& Reg16
)
5779 && (i
.index_reg
->reg_type
& Reg16
)
5780 && i
.base_reg
->reg_num
>= 6
5781 && i
.index_reg
->reg_num
< 6)
5783 const reg_entry
*base
= i
.index_reg
;
5785 i
.index_reg
= i
.base_reg
;
5788 ret
= i386_index_check (operand_string
);
5793 /* Constant and OFFSET expressions are handled by i386_immediate. */
5794 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5795 || intel_parser
.reg
== NULL
)
5796 ret
= i386_immediate (intel_parser
.disp
);
5798 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5800 if (!ret
|| !intel_parser
.next_operand
)
5802 intel_parser
.op_string
= intel_parser
.next_operand
;
5803 this_operand
= i
.operands
++;
5807 free (intel_parser
.disp
);
5812 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5816 expr' cmpOp e04 expr'
5821 /* XXX Implement the comparison operators. */
5822 return intel_e04 ();
5839 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5840 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5842 if (cur_token
.code
== '+')
5844 else if (cur_token
.code
== '-')
5845 nregs
= NUM_ADDRESS_REGS
;
5849 strcat (intel_parser
.disp
, cur_token
.str
);
5850 intel_match_token (cur_token
.code
);
5861 int nregs
= ~NUM_ADDRESS_REGS
;
5868 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
5872 str
[0] = cur_token
.code
;
5874 strcat (intel_parser
.disp
, str
);
5879 intel_match_token (cur_token
.code
);
5884 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5885 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
5896 int nregs
= ~NUM_ADDRESS_REGS
;
5903 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
5907 str
[0] = cur_token
.code
;
5909 strcat (intel_parser
.disp
, str
);
5911 else if (cur_token
.code
== T_SHL
)
5912 strcat (intel_parser
.disp
, "<<");
5913 else if (cur_token
.code
== T_SHR
)
5914 strcat (intel_parser
.disp
, ">>");
5918 intel_match_token (cur_token
.code
);
5923 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5924 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
5942 int nregs
= ~NUM_ADDRESS_REGS
;
5947 /* Don't consume constants here. */
5948 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5950 /* Need to look one token ahead - if the next token
5951 is a constant, the current token is its sign. */
5954 intel_match_token (cur_token
.code
);
5955 next_code
= cur_token
.code
;
5956 intel_putback_token ();
5957 if (next_code
== T_CONST
)
5961 /* e09 OFFSET e09 */
5962 if (cur_token
.code
== T_OFFSET
)
5965 ++intel_parser
.in_offset
;
5969 else if (cur_token
.code
== T_SHORT
)
5970 intel_parser
.op_modifier
|= 1 << T_SHORT
;
5973 else if (cur_token
.code
== '+')
5974 strcat (intel_parser
.disp
, "+");
5979 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
5985 str
[0] = cur_token
.code
;
5987 strcat (intel_parser
.disp
, str
);
5994 intel_match_token (cur_token
.code
);
6002 /* e09' PTR e10 e09' */
6003 if (cur_token
.code
== T_PTR
)
6007 if (prev_token
.code
== T_BYTE
)
6008 suffix
= BYTE_MNEM_SUFFIX
;
6010 else if (prev_token
.code
== T_WORD
)
6012 if (current_templates
->start
->name
[0] == 'l'
6013 && current_templates
->start
->name
[2] == 's'
6014 && current_templates
->start
->name
[3] == 0)
6015 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6016 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6017 suffix
= SHORT_MNEM_SUFFIX
;
6019 suffix
= WORD_MNEM_SUFFIX
;
6022 else if (prev_token
.code
== T_DWORD
)
6024 if (current_templates
->start
->name
[0] == 'l'
6025 && current_templates
->start
->name
[2] == 's'
6026 && current_templates
->start
->name
[3] == 0)
6027 suffix
= WORD_MNEM_SUFFIX
;
6028 else if (flag_code
== CODE_16BIT
6029 && (current_templates
->start
->opcode_modifier
6030 & (Jump
|JumpDword
|JumpInterSegment
)))
6031 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6032 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6033 suffix
= SHORT_MNEM_SUFFIX
;
6035 suffix
= LONG_MNEM_SUFFIX
;
6038 else if (prev_token
.code
== T_FWORD
)
6040 if (current_templates
->start
->name
[0] == 'l'
6041 && current_templates
->start
->name
[2] == 's'
6042 && current_templates
->start
->name
[3] == 0)
6043 suffix
= LONG_MNEM_SUFFIX
;
6044 else if (!intel_parser
.got_a_float
)
6046 if (flag_code
== CODE_16BIT
)
6047 add_prefix (DATA_PREFIX_OPCODE
);
6048 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6051 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6054 else if (prev_token
.code
== T_QWORD
)
6056 if (intel_parser
.got_a_float
== 1) /* "f..." */
6057 suffix
= LONG_MNEM_SUFFIX
;
6059 suffix
= QWORD_MNEM_SUFFIX
;
6062 else if (prev_token
.code
== T_TBYTE
)
6064 if (intel_parser
.got_a_float
== 1)
6065 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6067 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6070 else if (prev_token
.code
== T_XMMWORD
)
6072 /* XXX ignored for now, but accepted since gcc uses it */
6078 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6082 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6086 else if (i
.suffix
!= suffix
)
6088 as_bad (_("Conflicting operand modifiers"));
6094 /* e09' : e10 e09' */
6095 else if (cur_token
.code
== ':')
6097 if (prev_token
.code
!= T_REG
)
6099 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6100 segment/group identifier (which we don't have), using comma
6101 as the operand separator there is even less consistent, since
6102 there all branches only have a single operand. */
6103 if (this_operand
!= 0
6104 || intel_parser
.in_offset
6105 || intel_parser
.in_bracket
6106 || (!(current_templates
->start
->opcode_modifier
6107 & (Jump
|JumpDword
|JumpInterSegment
))
6108 && !(current_templates
->start
->operand_types
[0]
6110 return intel_match_token (T_NIL
);
6111 /* Remember the start of the 2nd operand and terminate 1st
6113 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6114 another expression), but it gets at least the simplest case
6115 (a plain number or symbol on the left side) right. */
6116 intel_parser
.next_operand
= intel_parser
.op_string
;
6117 *--intel_parser
.op_string
= '\0';
6118 return intel_match_token (':');
6126 intel_match_token (cur_token
.code
);
6132 --intel_parser
.in_offset
;
6135 if (NUM_ADDRESS_REGS
> nregs
)
6137 as_bad (_("Invalid operand to `OFFSET'"));
6140 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6143 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6144 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6149 intel_bracket_expr ()
6151 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6152 const char *start
= intel_parser
.op_string
;
6155 if (i
.op
[this_operand
].regs
)
6156 return intel_match_token (T_NIL
);
6158 intel_match_token ('[');
6160 /* Mark as a memory operand only if it's not already known to be an
6161 offset expression. If it's an offset expression, we need to keep
6163 if (!intel_parser
.in_offset
)
6165 ++intel_parser
.in_bracket
;
6166 /* Unfortunately gas always diverged from MASM in a respect that can't
6167 be easily fixed without risking to break code sequences likely to be
6168 encountered (the testsuite even check for this): MASM doesn't consider
6169 an expression inside brackets unconditionally as a memory reference.
6170 When that is e.g. a constant, an offset expression, or the sum of the
6171 two, this is still taken as a constant load. gas, however, always
6172 treated these as memory references. As a compromise, we'll try to make
6173 offset expressions inside brackets work the MASM way (since that's
6174 less likely to be found in real world code), but make constants alone
6175 continue to work the traditional gas way. In either case, issue a
6177 intel_parser
.op_modifier
&= ~was_offset
;
6180 strcat (intel_parser
.disp
, "[");
6182 /* Add a '+' to the displacement string if necessary. */
6183 if (*intel_parser
.disp
!= '\0'
6184 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6185 strcat (intel_parser
.disp
, "+");
6188 && (len
= intel_parser
.op_string
- start
- 1,
6189 intel_match_token (']')))
6191 /* Preserve brackets when the operand is an offset expression. */
6192 if (intel_parser
.in_offset
)
6193 strcat (intel_parser
.disp
, "]");
6196 --intel_parser
.in_bracket
;
6197 if (i
.base_reg
|| i
.index_reg
)
6198 intel_parser
.is_mem
= 1;
6199 if (!intel_parser
.is_mem
)
6201 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6202 /* Defer the warning until all of the operand was parsed. */
6203 intel_parser
.is_mem
= -1;
6204 else if (!quiet_warnings
)
6205 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6208 intel_parser
.op_modifier
|= was_offset
;
6225 while (cur_token
.code
== '[')
6227 if (!intel_bracket_expr ())
6252 switch (cur_token
.code
)
6256 intel_match_token ('(');
6257 strcat (intel_parser
.disp
, "(");
6259 if (intel_expr () && intel_match_token (')'))
6261 strcat (intel_parser
.disp
, ")");
6268 /* Operands for jump/call inside brackets denote absolute addresses.
6269 XXX This shouldn't be needed anymore (or if it should rather live
6270 in intel_bracket_expr). */
6271 if (current_templates
->start
->opcode_modifier
6272 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6273 i
.types
[this_operand
] |= JumpAbsolute
;
6275 return intel_bracket_expr ();
6280 strcat (intel_parser
.disp
, cur_token
.str
);
6281 intel_match_token (cur_token
.code
);
6283 /* Mark as a memory operand only if it's not already known to be an
6284 offset expression. */
6285 if (!intel_parser
.in_offset
)
6286 intel_parser
.is_mem
= 1;
6293 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6295 intel_match_token (T_REG
);
6297 /* Check for segment change. */
6298 if (cur_token
.code
== ':')
6300 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6302 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6305 else if (i
.seg
[i
.mem_operands
])
6306 as_warn (_("Extra segment override ignored"));
6309 if (!intel_parser
.in_offset
)
6310 intel_parser
.is_mem
= 1;
6311 switch (reg
->reg_num
)
6314 i
.seg
[i
.mem_operands
] = &es
;
6317 i
.seg
[i
.mem_operands
] = &cs
;
6320 i
.seg
[i
.mem_operands
] = &ss
;
6323 i
.seg
[i
.mem_operands
] = &ds
;
6326 i
.seg
[i
.mem_operands
] = &fs
;
6329 i
.seg
[i
.mem_operands
] = &gs
;
6335 /* Not a segment register. Check for register scaling. */
6336 else if (cur_token
.code
== '*')
6338 if (!intel_parser
.in_bracket
)
6340 as_bad (_("Register scaling only allowed in memory operands"));
6344 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6345 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6346 else if (i
.index_reg
)
6347 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6349 /* What follows must be a valid scale. */
6350 intel_match_token ('*');
6352 i
.types
[this_operand
] |= BaseIndex
;
6354 /* Set the scale after setting the register (otherwise,
6355 i386_scale will complain) */
6356 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6358 char *str
, sign
= cur_token
.code
;
6359 intel_match_token (cur_token
.code
);
6360 if (cur_token
.code
!= T_CONST
)
6362 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6366 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6367 strcpy (str
+ 1, cur_token
.str
);
6369 if (!i386_scale (str
))
6373 else if (!i386_scale (cur_token
.str
))
6375 intel_match_token (cur_token
.code
);
6378 /* No scaling. If this is a memory operand, the register is either a
6379 base register (first occurrence) or an index register (second
6381 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6386 else if (!i
.index_reg
)
6390 as_bad (_("Too many register references in memory operand"));
6394 i
.types
[this_operand
] |= BaseIndex
;
6397 /* Offset modifier. Add the register to the displacement string to be
6398 parsed as an immediate expression after we're done. */
6399 else if (intel_parser
.in_offset
)
6401 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6402 strcat (intel_parser
.disp
, reg
->reg_name
);
6405 /* It's neither base nor index nor offset. */
6406 else if (!intel_parser
.is_mem
)
6408 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6409 i
.op
[this_operand
].regs
= reg
;
6414 as_bad (_("Invalid use of register"));
6418 /* Since registers are not part of the displacement string (except
6419 when we're parsing offset operands), we may need to remove any
6420 preceding '+' from the displacement string. */
6421 if (*intel_parser
.disp
!= '\0'
6422 && !intel_parser
.in_offset
)
6424 char *s
= intel_parser
.disp
;
6425 s
+= strlen (s
) - 1;
6448 intel_match_token (cur_token
.code
);
6450 if (cur_token
.code
== T_PTR
)
6453 /* It must have been an identifier. */
6454 intel_putback_token ();
6455 cur_token
.code
= T_ID
;
6461 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6465 /* The identifier represents a memory reference only if it's not
6466 preceded by an offset modifier and if it's not an equate. */
6467 symbolP
= symbol_find(cur_token
.str
);
6468 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6469 intel_parser
.is_mem
= 1;
6477 char *save_str
, sign
= 0;
6479 /* Allow constants that start with `+' or `-'. */
6480 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6482 sign
= cur_token
.code
;
6483 intel_match_token (cur_token
.code
);
6484 if (cur_token
.code
!= T_CONST
)
6486 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6492 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6493 strcpy (save_str
+ !!sign
, cur_token
.str
);
6497 /* Get the next token to check for register scaling. */
6498 intel_match_token (cur_token
.code
);
6500 /* Check if this constant is a scaling factor for an index register. */
6501 if (cur_token
.code
== '*')
6503 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6505 const reg_entry
*reg
= cur_token
.reg
;
6507 if (!intel_parser
.in_bracket
)
6509 as_bad (_("Register scaling only allowed in memory operands"));
6513 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6514 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6515 else if (i
.index_reg
)
6516 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6518 /* The constant is followed by `* reg', so it must be
6521 i
.types
[this_operand
] |= BaseIndex
;
6523 /* Set the scale after setting the register (otherwise,
6524 i386_scale will complain) */
6525 if (!i386_scale (save_str
))
6527 intel_match_token (T_REG
);
6529 /* Since registers are not part of the displacement
6530 string, we may need to remove any preceding '+' from
6531 the displacement string. */
6532 if (*intel_parser
.disp
!= '\0')
6534 char *s
= intel_parser
.disp
;
6535 s
+= strlen (s
) - 1;
6545 /* The constant was not used for register scaling. Since we have
6546 already consumed the token following `*' we now need to put it
6547 back in the stream. */
6548 intel_putback_token ();
6551 /* Add the constant to the displacement string. */
6552 strcat (intel_parser
.disp
, save_str
);
6559 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6563 /* Match the given token against cur_token. If they match, read the next
6564 token from the operand string. */
6566 intel_match_token (code
)
6569 if (cur_token
.code
== code
)
6576 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6581 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6586 const reg_entry
*reg
;
6587 struct intel_token new_token
;
6589 new_token
.code
= T_NIL
;
6590 new_token
.reg
= NULL
;
6591 new_token
.str
= NULL
;
6593 /* Free the memory allocated to the previous token and move
6594 cur_token to prev_token. */
6596 free (prev_token
.str
);
6598 prev_token
= cur_token
;
6600 /* Skip whitespace. */
6601 while (is_space_char (*intel_parser
.op_string
))
6602 intel_parser
.op_string
++;
6604 /* Return an empty token if we find nothing else on the line. */
6605 if (*intel_parser
.op_string
== '\0')
6607 cur_token
= new_token
;
6611 /* The new token cannot be larger than the remainder of the operand
6613 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6614 new_token
.str
[0] = '\0';
6616 if (strchr ("0123456789", *intel_parser
.op_string
))
6618 char *p
= new_token
.str
;
6619 char *q
= intel_parser
.op_string
;
6620 new_token
.code
= T_CONST
;
6622 /* Allow any kind of identifier char to encompass floating point and
6623 hexadecimal numbers. */
6624 while (is_identifier_char (*q
))
6628 /* Recognize special symbol names [0-9][bf]. */
6629 if (strlen (intel_parser
.op_string
) == 2
6630 && (intel_parser
.op_string
[1] == 'b'
6631 || intel_parser
.op_string
[1] == 'f'))
6632 new_token
.code
= T_ID
;
6635 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6636 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6638 new_token
.code
= T_REG
;
6639 new_token
.reg
= reg
;
6641 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6643 new_token
.str
[0] = REGISTER_PREFIX
;
6644 new_token
.str
[1] = '\0';
6647 strcat (new_token
.str
, reg
->reg_name
);
6650 else if (is_identifier_char (*intel_parser
.op_string
))
6652 char *p
= new_token
.str
;
6653 char *q
= intel_parser
.op_string
;
6655 /* A '.' or '$' followed by an identifier char is an identifier.
6656 Otherwise, it's operator '.' followed by an expression. */
6657 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6659 new_token
.code
= '.';
6660 new_token
.str
[0] = '.';
6661 new_token
.str
[1] = '\0';
6665 while (is_identifier_char (*q
) || *q
== '@')
6669 if (strcasecmp (new_token
.str
, "NOT") == 0)
6670 new_token
.code
= '~';
6672 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6673 new_token
.code
= '%';
6675 else if (strcasecmp (new_token
.str
, "AND") == 0)
6676 new_token
.code
= '&';
6678 else if (strcasecmp (new_token
.str
, "OR") == 0)
6679 new_token
.code
= '|';
6681 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6682 new_token
.code
= '^';
6684 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6685 new_token
.code
= T_SHL
;
6687 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6688 new_token
.code
= T_SHR
;
6690 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6691 new_token
.code
= T_BYTE
;
6693 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6694 new_token
.code
= T_WORD
;
6696 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6697 new_token
.code
= T_DWORD
;
6699 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6700 new_token
.code
= T_FWORD
;
6702 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6703 new_token
.code
= T_QWORD
;
6705 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6706 /* XXX remove (gcc still uses it) */
6707 || strcasecmp (new_token
.str
, "XWORD") == 0)
6708 new_token
.code
= T_TBYTE
;
6710 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6711 || strcasecmp (new_token
.str
, "OWORD") == 0)
6712 new_token
.code
= T_XMMWORD
;
6714 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6715 new_token
.code
= T_PTR
;
6717 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6718 new_token
.code
= T_SHORT
;
6720 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6722 new_token
.code
= T_OFFSET
;
6724 /* ??? This is not mentioned in the MASM grammar but gcc
6725 makes use of it with -mintel-syntax. OFFSET may be
6726 followed by FLAT: */
6727 if (strncasecmp (q
, " FLAT:", 6) == 0)
6728 strcat (new_token
.str
, " FLAT:");
6731 /* ??? This is not mentioned in the MASM grammar. */
6732 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6734 new_token
.code
= T_OFFSET
;
6736 strcat (new_token
.str
, ":");
6738 as_bad (_("`:' expected"));
6742 new_token
.code
= T_ID
;
6746 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6748 new_token
.code
= *intel_parser
.op_string
;
6749 new_token
.str
[0] = *intel_parser
.op_string
;
6750 new_token
.str
[1] = '\0';
6753 else if (strchr ("<>", *intel_parser
.op_string
)
6754 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6756 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6757 new_token
.str
[0] = *intel_parser
.op_string
;
6758 new_token
.str
[1] = *intel_parser
.op_string
;
6759 new_token
.str
[2] = '\0';
6763 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6765 intel_parser
.op_string
+= strlen (new_token
.str
);
6766 cur_token
= new_token
;
6769 /* Put cur_token back into the token stream and make cur_token point to
6772 intel_putback_token ()
6774 if (cur_token
.code
!= T_NIL
)
6776 intel_parser
.op_string
-= strlen (cur_token
.str
);
6777 free (cur_token
.str
);
6779 cur_token
= prev_token
;
6781 /* Forget prev_token. */
6782 prev_token
.code
= T_NIL
;
6783 prev_token
.reg
= NULL
;
6784 prev_token
.str
= NULL
;
6788 tc_x86_regname_to_dw2regnum (const char *regname
)
6790 unsigned int regnum
;
6791 unsigned int regnames_count
;
6792 char *regnames_32
[] =
6794 "eax", "ecx", "edx", "ebx",
6795 "esp", "ebp", "esi", "edi",
6798 char *regnames_64
[] =
6800 "rax", "rbx", "rcx", "rdx",
6801 "rdi", "rsi", "rbp", "rsp",
6802 "r8", "r9", "r10", "r11",
6803 "r12", "r13", "r14", "r15",
6808 if (flag_code
== CODE_64BIT
)
6810 regnames
= regnames_64
;
6811 regnames_count
= ARRAY_SIZE (regnames_64
);
6815 regnames
= regnames_32
;
6816 regnames_count
= ARRAY_SIZE (regnames_32
);
6819 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6820 if (strcmp (regname
, regnames
[regnum
]) == 0)
6827 tc_x86_frame_initial_instructions (void)
6829 static unsigned int sp_regno
;
6832 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6835 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6836 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6840 i386_elf_section_type (const char *str
, size_t len
)
6842 if (flag_code
== CODE_64BIT
6843 && len
== sizeof ("unwind") - 1
6844 && strncmp (str
, "unwind", 6) == 0)
6845 return SHT_X86_64_UNWIND
;
6852 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
6856 expr
.X_op
= O_secrel
;
6857 expr
.X_add_symbol
= symbol
;
6858 expr
.X_add_number
= 0;
6859 emit_expr (&expr
, size
);