1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
33 #include "dwarf2dbg.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
55 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
56 static int fits_in_signed_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
58 static int fits_in_unsigned_word
PARAMS ((offsetT
));
59 static int fits_in_signed_word
PARAMS ((offsetT
));
60 static int fits_in_unsigned_long
PARAMS ((offsetT
));
61 static int fits_in_signed_long
PARAMS ((offsetT
));
62 static int smallest_imm_type
PARAMS ((offsetT
));
63 static offsetT offset_in_range
PARAMS ((offsetT
, int));
64 static int add_prefix
PARAMS ((unsigned int));
65 static void set_code_flag
PARAMS ((int));
66 static void set_16bit_gcc_code_flag
PARAMS ((int));
67 static void set_intel_syntax
PARAMS ((int));
68 static void set_cpu_arch
PARAMS ((int));
71 static bfd_reloc_code_real_type reloc
72 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
73 #define RELOC_ENUM enum bfd_reloc_code_real
75 #define RELOC_ENUM int
79 #define DEFAULT_ARCH "i386"
81 static char *default_arch
= DEFAULT_ARCH
;
83 /* 'md_assemble ()' gathers together information and puts it into a
90 const reg_entry
*regs
;
95 /* TM holds the template for the insn were currently assembling. */
98 /* SUFFIX holds the instruction mnemonic suffix if given.
99 (e.g. 'l' for 'movl') */
102 /* OPERANDS gives the number of given operands. */
103 unsigned int operands
;
105 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
106 of given register, displacement, memory operands and immediate
108 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
110 /* TYPES [i] is the type (see above #defines) which tells us how to
111 use OP[i] for the corresponding operand. */
112 unsigned int types
[MAX_OPERANDS
];
114 /* Displacement expression, immediate expression, or register for each
116 union i386_op op
[MAX_OPERANDS
];
118 /* Flags for operands. */
119 unsigned int flags
[MAX_OPERANDS
];
120 #define Operand_PCrel 1
122 /* Relocation type for operand */
123 RELOC_ENUM reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
243 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
245 static enum flag_code flag_code
;
246 static int use_rela_relocations
= 0;
248 /* The names used to print error messages. */
249 static const char *flag_code_names
[] =
256 /* 1 for intel syntax,
258 static int intel_syntax
= 0;
260 /* 1 if register prefix % not required. */
261 static int allow_naked_reg
= 0;
263 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
264 leave, push, and pop instructions so that gcc has the same stack
265 frame as in 32 bit mode. */
266 static char stackop_size
= '\0';
268 /* Non-zero to quieten some warnings. */
269 static int quiet_warnings
= 0;
272 static const char *cpu_arch_name
= NULL
;
274 /* CPU feature flags. */
275 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
277 /* If set, conditional jumps are not automatically promoted to handle
278 larger than a byte offset. */
279 static unsigned int no_cond_jump_promotion
= 0;
281 /* Interface to relax_segment.
282 There are 3 major relax states for 386 jump insns because the
283 different types of jumps add different sizes to frags when we're
284 figuring out what sort of jump to choose to reach a given label. */
287 #define UNCOND_JUMP 1
289 #define COND_JUMP86 3
294 #define SMALL16 (SMALL|CODE16)
296 #define BIG16 (BIG|CODE16)
300 #define INLINE __inline__
306 #define ENCODE_RELAX_STATE(type, size) \
307 ((relax_substateT) (((type) << 2) | (size)))
308 #define TYPE_FROM_RELAX_STATE(s) \
310 #define DISP_SIZE_FROM_RELAX_STATE(s) \
311 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
313 /* This table is used by relax_frag to promote short jumps to long
314 ones where necessary. SMALL (short) jumps may be promoted to BIG
315 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
316 don't allow a short jump in a 32 bit code segment to be promoted to
317 a 16 bit offset jump because it's slower (requires data size
318 prefix), and doesn't work, unless the destination is in the bottom
319 64k of the code segment (The top 16 bits of eip are zeroed). */
321 const relax_typeS md_relax_table
[] =
324 1) most positive reach of this state,
325 2) most negative reach of this state,
326 3) how many bytes this mode will add to the size of the current frag
327 4) which index into the table to try if we can't fit into this one. */
333 /* UNCOND_JUMP states. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
343 /* COND_JUMP states. */
344 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
345 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
346 /* dword conditionals adds 4 bytes to frag:
347 1 extra opcode byte, 3 extra displacement bytes. */
349 /* word conditionals add 2 bytes to frag:
350 1 extra opcode byte, 1 extra displacement byte. */
353 /* COND_JUMP86 states. */
354 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
355 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
356 /* dword conditionals adds 4 bytes to frag:
357 1 extra opcode byte, 3 extra displacement bytes. */
359 /* word conditionals add 3 bytes to frag:
360 1 extra opcode byte, 2 extra displacement bytes. */
364 static const arch_entry cpu_arch
[] = {
366 {"i186", Cpu086
|Cpu186
},
367 {"i286", Cpu086
|Cpu186
|Cpu286
},
368 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
369 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
370 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
371 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
372 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
373 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
374 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
375 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
376 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
377 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
382 i386_align_code (fragP
, count
)
386 /* Various efficient no-op patterns for aligning code labels.
387 Note: Don't try to assemble the instructions in the comments.
388 0L and 0w are not legal. */
389 static const char f32_1
[] =
391 static const char f32_2
[] =
392 {0x89,0xf6}; /* movl %esi,%esi */
393 static const char f32_3
[] =
394 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
395 static const char f32_4
[] =
396 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
397 static const char f32_5
[] =
399 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
400 static const char f32_6
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
402 static const char f32_7
[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
404 static const char f32_8
[] =
406 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
407 static const char f32_9
[] =
408 {0x89,0xf6, /* movl %esi,%esi */
409 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
410 static const char f32_10
[] =
411 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
412 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
413 static const char f32_11
[] =
414 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
415 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
416 static const char f32_12
[] =
417 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
418 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
419 static const char f32_13
[] =
420 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
421 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
422 static const char f32_14
[] =
423 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
424 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
425 static const char f32_15
[] =
426 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
427 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
428 static const char f16_3
[] =
429 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
430 static const char f16_4
[] =
431 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
432 static const char f16_5
[] =
434 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
435 static const char f16_6
[] =
436 {0x89,0xf6, /* mov %si,%si */
437 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
438 static const char f16_7
[] =
439 {0x8d,0x74,0x00, /* lea 0(%si),%si */
440 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
441 static const char f16_8
[] =
442 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
443 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
444 static const char *const f32_patt
[] = {
445 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
446 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
448 static const char *const f16_patt
[] = {
449 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
450 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
453 /* ??? We can't use these fillers for x86_64, since they often kills the
454 upper halves. Solve later. */
455 if (flag_code
== CODE_64BIT
)
458 if (count
> 0 && count
<= 15)
460 if (flag_code
== CODE_16BIT
)
462 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
463 f16_patt
[count
- 1], count
);
465 /* Adjust jump offset. */
466 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
469 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
470 f32_patt
[count
- 1], count
);
471 fragP
->fr_var
= count
;
475 static char *output_invalid
PARAMS ((int c
));
476 static int i386_operand
PARAMS ((char *operand_string
));
477 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
478 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
482 static void s_bss
PARAMS ((int));
485 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
487 static INLINE
unsigned int
488 mode_from_disp_size (t
)
491 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
495 fits_in_signed_byte (num
)
498 return (num
>= -128) && (num
<= 127);
502 fits_in_unsigned_byte (num
)
505 return (num
& 0xff) == num
;
509 fits_in_unsigned_word (num
)
512 return (num
& 0xffff) == num
;
516 fits_in_signed_word (num
)
519 return (-32768 <= num
) && (num
<= 32767);
522 fits_in_signed_long (num
)
523 offsetT num ATTRIBUTE_UNUSED
;
528 return (!(((offsetT
) -1 << 31) & num
)
529 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
531 } /* fits_in_signed_long() */
533 fits_in_unsigned_long (num
)
534 offsetT num ATTRIBUTE_UNUSED
;
539 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
541 } /* fits_in_unsigned_long() */
544 smallest_imm_type (num
)
547 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
548 && !(cpu_arch_flags
& (CpuUnknown
)))
550 /* This code is disabled on the 486 because all the Imm1 forms
551 in the opcode table are slower on the i486. They're the
552 versions with the implicitly specified single-position
553 displacement, which has another syntax if you really want to
556 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
558 return (fits_in_signed_byte (num
)
559 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
560 : fits_in_unsigned_byte (num
)
561 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
562 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
563 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
564 : fits_in_signed_long (num
)
565 ? (Imm32
| Imm32S
| Imm64
)
566 : fits_in_unsigned_long (num
)
572 offset_in_range (val
, size
)
580 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
581 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
582 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
584 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
589 /* If BFD64, sign extend val. */
590 if (!use_rela_relocations
)
591 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
592 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
594 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
596 char buf1
[40], buf2
[40];
598 sprint_value (buf1
, val
);
599 sprint_value (buf2
, val
& mask
);
600 as_warn (_("%s shortened to %s"), buf1
, buf2
);
605 /* Returns 0 if attempting to add a prefix where one from the same
606 class already exists, 1 if non rep/repne added, 2 if rep/repne
615 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
623 case CS_PREFIX_OPCODE
:
624 case DS_PREFIX_OPCODE
:
625 case ES_PREFIX_OPCODE
:
626 case FS_PREFIX_OPCODE
:
627 case GS_PREFIX_OPCODE
:
628 case SS_PREFIX_OPCODE
:
632 case REPNE_PREFIX_OPCODE
:
633 case REPE_PREFIX_OPCODE
:
636 case LOCK_PREFIX_OPCODE
:
644 case ADDR_PREFIX_OPCODE
:
648 case DATA_PREFIX_OPCODE
:
655 as_bad (_("same type of prefix used twice"));
660 i
.prefix
[q
] = prefix
;
665 set_code_flag (value
)
669 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
670 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
671 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
673 as_bad (_("64bit mode not supported on this CPU."));
675 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
677 as_bad (_("32bit mode not supported on this CPU."));
683 set_16bit_gcc_code_flag (new_code_flag
)
686 flag_code
= new_code_flag
;
687 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
688 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
693 set_intel_syntax (syntax_flag
)
696 /* Find out if register prefixing is specified. */
697 int ask_naked_reg
= 0;
700 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
702 char *string
= input_line_pointer
;
703 int e
= get_symbol_end ();
705 if (strcmp (string
, "prefix") == 0)
707 else if (strcmp (string
, "noprefix") == 0)
710 as_bad (_("bad argument to syntax directive."));
711 *input_line_pointer
= e
;
713 demand_empty_rest_of_line ();
715 intel_syntax
= syntax_flag
;
717 if (ask_naked_reg
== 0)
720 allow_naked_reg
= (intel_syntax
721 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
723 /* Conservative default. */
728 allow_naked_reg
= (ask_naked_reg
< 0);
733 int dummy ATTRIBUTE_UNUSED
;
737 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
739 char *string
= input_line_pointer
;
740 int e
= get_symbol_end ();
743 for (i
= 0; cpu_arch
[i
].name
; i
++)
745 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
747 cpu_arch_name
= cpu_arch
[i
].name
;
748 cpu_arch_flags
= (cpu_arch
[i
].flags
749 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
753 if (!cpu_arch
[i
].name
)
754 as_bad (_("no such architecture: `%s'"), string
);
756 *input_line_pointer
= e
;
759 as_bad (_("missing cpu architecture"));
761 no_cond_jump_promotion
= 0;
762 if (*input_line_pointer
== ','
763 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
765 char *string
= ++input_line_pointer
;
766 int e
= get_symbol_end ();
768 if (strcmp (string
, "nojumps") == 0)
769 no_cond_jump_promotion
= 1;
770 else if (strcmp (string
, "jumps") == 0)
773 as_bad (_("no such architecture modifier: `%s'"), string
);
775 *input_line_pointer
= e
;
778 demand_empty_rest_of_line ();
781 const pseudo_typeS md_pseudo_table
[] =
783 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
784 {"align", s_align_bytes
, 0},
786 {"align", s_align_ptwo
, 0},
788 {"arch", set_cpu_arch
, 0},
792 {"ffloat", float_cons
, 'f'},
793 {"dfloat", float_cons
, 'd'},
794 {"tfloat", float_cons
, 'x'},
796 {"noopt", s_ignore
, 0},
797 {"optim", s_ignore
, 0},
798 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
799 {"code16", set_code_flag
, CODE_16BIT
},
800 {"code32", set_code_flag
, CODE_32BIT
},
801 {"code64", set_code_flag
, CODE_64BIT
},
802 {"intel_syntax", set_intel_syntax
, 1},
803 {"att_syntax", set_intel_syntax
, 0},
804 {"file", dwarf2_directive_file
, 0},
805 {"loc", dwarf2_directive_loc
, 0},
809 /* For interface with expression (). */
810 extern char *input_line_pointer
;
812 /* Hash table for instruction mnemonic lookup. */
813 static struct hash_control
*op_hash
;
815 /* Hash table for register lookup. */
816 static struct hash_control
*reg_hash
;
822 if (!strcmp (default_arch
, "x86_64"))
823 return bfd_mach_x86_64
;
824 else if (!strcmp (default_arch
, "i386"))
825 return bfd_mach_i386_i386
;
827 as_fatal (_("Unknown architecture"));
834 const char *hash_err
;
836 /* Initialize op_hash hash table. */
837 op_hash
= hash_new ();
840 register const template *optab
;
841 register templates
*core_optab
;
843 /* Setup for loop. */
845 core_optab
= (templates
*) xmalloc (sizeof (templates
));
846 core_optab
->start
= optab
;
851 if (optab
->name
== NULL
852 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
854 /* different name --> ship out current template list;
855 add to hash table; & begin anew. */
856 core_optab
->end
= optab
;
857 hash_err
= hash_insert (op_hash
,
862 as_fatal (_("Internal Error: Can't hash %s: %s"),
866 if (optab
->name
== NULL
)
868 core_optab
= (templates
*) xmalloc (sizeof (templates
));
869 core_optab
->start
= optab
;
874 /* Initialize reg_hash hash table. */
875 reg_hash
= hash_new ();
877 register const reg_entry
*regtab
;
879 for (regtab
= i386_regtab
;
880 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
883 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
885 as_fatal (_("Internal Error: Can't hash %s: %s"),
891 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
896 for (c
= 0; c
< 256; c
++)
901 mnemonic_chars
[c
] = c
;
902 register_chars
[c
] = c
;
903 operand_chars
[c
] = c
;
905 else if (islower (c
))
907 mnemonic_chars
[c
] = c
;
908 register_chars
[c
] = c
;
909 operand_chars
[c
] = c
;
911 else if (isupper (c
))
913 mnemonic_chars
[c
] = tolower (c
);
914 register_chars
[c
] = mnemonic_chars
[c
];
915 operand_chars
[c
] = c
;
918 if (isalpha (c
) || isdigit (c
))
919 identifier_chars
[c
] = c
;
922 identifier_chars
[c
] = c
;
923 operand_chars
[c
] = c
;
928 identifier_chars
['@'] = '@';
930 digit_chars
['-'] = '-';
931 identifier_chars
['_'] = '_';
932 identifier_chars
['.'] = '.';
934 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
935 operand_chars
[(unsigned char) *p
] = *p
;
938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
939 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
941 record_alignment (text_section
, 2);
942 record_alignment (data_section
, 2);
943 record_alignment (bss_section
, 2);
949 i386_print_statistics (file
)
952 hash_print_statistics (file
, "i386 opcode", op_hash
);
953 hash_print_statistics (file
, "i386 register", reg_hash
);
958 /* Debugging routines for md_assemble. */
959 static void pi
PARAMS ((char *, i386_insn
*));
960 static void pte
PARAMS ((template *));
961 static void pt
PARAMS ((unsigned int));
962 static void pe
PARAMS ((expressionS
*));
963 static void ps
PARAMS ((symbolS
*));
972 fprintf (stdout
, "%s: template ", line
);
974 fprintf (stdout
, " address: base %s index %s scale %x\n",
975 x
->base_reg
? x
->base_reg
->reg_name
: "none",
976 x
->index_reg
? x
->index_reg
->reg_name
: "none",
977 x
->log2_scale_factor
);
978 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
979 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
980 fprintf (stdout
, " sib: base %x index %x scale %x\n",
981 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
982 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
983 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
984 for (i
= 0; i
< x
->operands
; i
++)
986 fprintf (stdout
, " #%d: ", i
+ 1);
988 fprintf (stdout
, "\n");
990 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
991 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
992 if (x
->types
[i
] & Imm
)
994 if (x
->types
[i
] & Disp
)
1004 fprintf (stdout
, " %d operands ", t
->operands
);
1005 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1006 if (t
->extension_opcode
!= None
)
1007 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1008 if (t
->opcode_modifier
& D
)
1009 fprintf (stdout
, "D");
1010 if (t
->opcode_modifier
& W
)
1011 fprintf (stdout
, "W");
1012 fprintf (stdout
, "\n");
1013 for (i
= 0; i
< t
->operands
; i
++)
1015 fprintf (stdout
, " #%d type ", i
+ 1);
1016 pt (t
->operand_types
[i
]);
1017 fprintf (stdout
, "\n");
1025 fprintf (stdout
, " operation %d\n", e
->X_op
);
1026 fprintf (stdout
, " add_number %ld (%lx)\n",
1027 (long) e
->X_add_number
, (long) e
->X_add_number
);
1028 if (e
->X_add_symbol
)
1030 fprintf (stdout
, " add_symbol ");
1031 ps (e
->X_add_symbol
);
1032 fprintf (stdout
, "\n");
1036 fprintf (stdout
, " op_symbol ");
1037 ps (e
->X_op_symbol
);
1038 fprintf (stdout
, "\n");
1046 fprintf (stdout
, "%s type %s%s",
1048 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1049 segment_name (S_GET_SEGMENT (s
)));
1071 { BaseIndex
, "BaseIndex" },
1075 { Disp32S
, "d32s" },
1077 { InOutPortReg
, "InOutPortReg" },
1078 { ShiftCount
, "ShiftCount" },
1079 { Control
, "control reg" },
1080 { Test
, "test reg" },
1081 { Debug
, "debug reg" },
1082 { FloatReg
, "FReg" },
1083 { FloatAcc
, "FAcc" },
1087 { JumpAbsolute
, "Jump Absolute" },
1098 register struct type_name
*ty
;
1100 for (ty
= type_names
; ty
->mask
; ty
++)
1102 fprintf (stdout
, "%s, ", ty
->tname
);
1106 #endif /* DEBUG386 */
1109 tc_i386_force_relocation (fixp
)
1112 #ifdef BFD_ASSEMBLER
1113 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1114 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1119 return fixp
->fx_r_type
== 7;
1123 #ifdef BFD_ASSEMBLER
1125 static bfd_reloc_code_real_type
1126 reloc (size
, pcrel
, sign
, other
)
1130 bfd_reloc_code_real_type other
;
1132 if (other
!= NO_RELOC
)
1138 as_bad (_("There are no unsigned pc-relative relocations"));
1141 case 1: return BFD_RELOC_8_PCREL
;
1142 case 2: return BFD_RELOC_16_PCREL
;
1143 case 4: return BFD_RELOC_32_PCREL
;
1145 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1152 case 4: return BFD_RELOC_X86_64_32S
;
1157 case 1: return BFD_RELOC_8
;
1158 case 2: return BFD_RELOC_16
;
1159 case 4: return BFD_RELOC_32
;
1160 case 8: return BFD_RELOC_64
;
1162 as_bad (_("can not do %s %d byte relocation"),
1163 sign
? "signed" : "unsigned", size
);
1167 return BFD_RELOC_NONE
;
1170 /* Here we decide which fixups can be adjusted to make them relative to
1171 the beginning of the section instead of the symbol. Basically we need
1172 to make sure that the dynamic relocations are done correctly, so in
1173 some cases we force the original symbol to be used. */
1176 tc_i386_fix_adjustable (fixP
)
1179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1180 /* Prevent all adjustments to global symbols, or else dynamic
1181 linking will not work correctly. */
1182 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1183 || S_IS_WEAK (fixP
->fx_addsy
))
1186 /* adjust_reloc_syms doesn't know about the GOT. */
1187 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1188 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1189 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1190 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1191 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1192 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1193 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1194 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1199 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1200 #define BFD_RELOC_16 0
1201 #define BFD_RELOC_32 0
1202 #define BFD_RELOC_16_PCREL 0
1203 #define BFD_RELOC_32_PCREL 0
1204 #define BFD_RELOC_386_PLT32 0
1205 #define BFD_RELOC_386_GOT32 0
1206 #define BFD_RELOC_386_GOTOFF 0
1207 #define BFD_RELOC_X86_64_PLT32 0
1208 #define BFD_RELOC_X86_64_GOT32 0
1209 #define BFD_RELOC_X86_64_GOTPCREL 0
1212 static int intel_float_operand
PARAMS ((char *mnemonic
));
1215 intel_float_operand (mnemonic
)
1218 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1221 if (mnemonic
[0] == 'f')
1227 /* This is the guts of the machine-dependent assembler. LINE points to a
1228 machine dependent instruction. This function is supposed to emit
1229 the frags/bytes it assembles to. */
1235 /* Points to template once we've found it. */
1238 /* Count the size of the instruction generated. Does not include
1239 variable part of jump insns before relax. */
1244 char mnemonic
[MAX_MNEM_SIZE
];
1246 /* Initialize globals. */
1247 memset (&i
, '\0', sizeof (i
));
1248 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1249 i
.reloc
[j
] = NO_RELOC
;
1250 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1251 memset (im_expressions
, '\0', sizeof (im_expressions
));
1252 save_stack_p
= save_stack
;
1254 /* First parse an instruction mnemonic & call i386_operand for the operands.
1255 We assume that the scrubber has arranged it so that line[0] is the valid
1256 start of a (possibly prefixed) mnemonic. */
1259 char *token_start
= l
;
1262 /* Non-zero if we found a prefix only acceptable with string insns. */
1263 const char *expecting_string_instruction
= NULL
;
1268 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1271 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1273 as_bad (_("no such instruction: `%s'"), token_start
);
1278 if (!is_space_char (*l
)
1279 && *l
!= END_OF_INSN
1280 && *l
!= PREFIX_SEPARATOR
)
1282 as_bad (_("invalid character %s in mnemonic"),
1283 output_invalid (*l
));
1286 if (token_start
== l
)
1288 if (*l
== PREFIX_SEPARATOR
)
1289 as_bad (_("expecting prefix; got nothing"));
1291 as_bad (_("expecting mnemonic; got nothing"));
1295 /* Look up instruction (or prefix) via hash table. */
1296 current_templates
= hash_find (op_hash
, mnemonic
);
1298 if (*l
!= END_OF_INSN
1299 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1300 && current_templates
1301 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1303 /* If we are in 16-bit mode, do not allow addr16 or data16.
1304 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1305 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1306 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1307 ^ (flag_code
== CODE_16BIT
)))
1309 as_bad (_("redundant %s prefix"),
1310 current_templates
->start
->name
);
1313 /* Add prefix, checking for repeated prefixes. */
1314 switch (add_prefix (current_templates
->start
->base_opcode
))
1319 expecting_string_instruction
= current_templates
->start
->name
;
1322 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1329 if (!current_templates
)
1331 /* See if we can get a match by trimming off a suffix. */
1334 case WORD_MNEM_SUFFIX
:
1335 case BYTE_MNEM_SUFFIX
:
1336 case QWORD_MNEM_SUFFIX
:
1337 i
.suffix
= mnem_p
[-1];
1339 current_templates
= hash_find (op_hash
, mnemonic
);
1341 case SHORT_MNEM_SUFFIX
:
1342 case LONG_MNEM_SUFFIX
:
1345 i
.suffix
= mnem_p
[-1];
1347 current_templates
= hash_find (op_hash
, mnemonic
);
1355 if (intel_float_operand (mnemonic
))
1356 i
.suffix
= SHORT_MNEM_SUFFIX
;
1358 i
.suffix
= LONG_MNEM_SUFFIX
;
1360 current_templates
= hash_find (op_hash
, mnemonic
);
1364 if (!current_templates
)
1366 as_bad (_("no such instruction: `%s'"), token_start
);
1371 /* Check if instruction is supported on specified architecture. */
1372 if (cpu_arch_flags
!= 0)
1374 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1375 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1377 as_warn (_("`%s' is not supported on `%s'"),
1378 current_templates
->start
->name
, cpu_arch_name
);
1380 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1382 as_warn (_("use .code16 to ensure correct addressing mode"));
1386 /* Check for rep/repne without a string instruction. */
1387 if (expecting_string_instruction
1388 && !(current_templates
->start
->opcode_modifier
& IsString
))
1390 as_bad (_("expecting string instruction after `%s'"),
1391 expecting_string_instruction
);
1395 /* There may be operands to parse. */
1396 if (*l
!= END_OF_INSN
)
1398 /* 1 if operand is pending after ','. */
1399 unsigned int expecting_operand
= 0;
1401 /* Non-zero if operand parens not balanced. */
1402 unsigned int paren_not_balanced
;
1406 /* Skip optional white space before operand. */
1407 if (is_space_char (*l
))
1409 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1411 as_bad (_("invalid character %s before operand %d"),
1412 output_invalid (*l
),
1416 token_start
= l
; /* after white space */
1417 paren_not_balanced
= 0;
1418 while (paren_not_balanced
|| *l
!= ',')
1420 if (*l
== END_OF_INSN
)
1422 if (paren_not_balanced
)
1425 as_bad (_("unbalanced parenthesis in operand %d."),
1428 as_bad (_("unbalanced brackets in operand %d."),
1433 break; /* we are done */
1435 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1437 as_bad (_("invalid character %s in operand %d"),
1438 output_invalid (*l
),
1445 ++paren_not_balanced
;
1447 --paren_not_balanced
;
1452 ++paren_not_balanced
;
1454 --paren_not_balanced
;
1458 if (l
!= token_start
)
1459 { /* Yes, we've read in another operand. */
1460 unsigned int operand_ok
;
1461 this_operand
= i
.operands
++;
1462 if (i
.operands
> MAX_OPERANDS
)
1464 as_bad (_("spurious operands; (%d operands/instruction max)"),
1468 /* Now parse operand adding info to 'i' as we go along. */
1469 END_STRING_AND_SAVE (l
);
1473 i386_intel_operand (token_start
,
1474 intel_float_operand (mnemonic
));
1476 operand_ok
= i386_operand (token_start
);
1478 RESTORE_END_STRING (l
);
1484 if (expecting_operand
)
1486 expecting_operand_after_comma
:
1487 as_bad (_("expecting operand after ','; got nothing"));
1492 as_bad (_("expecting operand before ','; got nothing"));
1497 /* Now *l must be either ',' or END_OF_INSN. */
1500 if (*++l
== END_OF_INSN
)
1502 /* Just skip it, if it's \n complain. */
1503 goto expecting_operand_after_comma
;
1505 expecting_operand
= 1;
1508 while (*l
!= END_OF_INSN
);
1512 /* Now we've parsed the mnemonic into a set of templates, and have the
1515 Next, we find a template that matches the given insn,
1516 making sure the overlap of the given operands types is consistent
1517 with the template operand types. */
1519 #define MATCH(overlap, given, template) \
1520 ((overlap & ~JumpAbsolute) \
1521 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1523 /* If given types r0 and r1 are registers they must be of the same type
1524 unless the expected operand type register overlap is null.
1525 Note that Acc in a template matches every size of reg. */
1526 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1527 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1528 ((g0) & Reg) == ((g1) & Reg) || \
1529 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1532 register unsigned int overlap0
, overlap1
;
1533 unsigned int overlap2
;
1534 unsigned int found_reverse_match
;
1537 /* All intel opcodes have reversed operands except for "bound" and
1538 "enter". We also don't reverse intersegment "jmp" and "call"
1539 instructions with 2 immediate operands so that the immediate segment
1540 precedes the offset, as it does when in AT&T mode. "enter" and the
1541 intersegment "jmp" and "call" instructions are the only ones that
1542 have two immediate operands. */
1543 if (intel_syntax
&& i
.operands
> 1
1544 && (strcmp (mnemonic
, "bound") != 0)
1545 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1547 union i386_op temp_op
;
1548 unsigned int temp_type
;
1549 RELOC_ENUM temp_reloc
;
1553 if (i
.operands
== 2)
1558 else if (i
.operands
== 3)
1563 temp_type
= i
.types
[xchg2
];
1564 i
.types
[xchg2
] = i
.types
[xchg1
];
1565 i
.types
[xchg1
] = temp_type
;
1566 temp_op
= i
.op
[xchg2
];
1567 i
.op
[xchg2
] = i
.op
[xchg1
];
1568 i
.op
[xchg1
] = temp_op
;
1569 temp_reloc
= i
.reloc
[xchg2
];
1570 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1571 i
.reloc
[xchg1
] = temp_reloc
;
1573 if (i
.mem_operands
== 2)
1575 const seg_entry
*temp_seg
;
1576 temp_seg
= i
.seg
[0];
1577 i
.seg
[0] = i
.seg
[1];
1578 i
.seg
[1] = temp_seg
;
1584 /* Try to ensure constant immediates are represented in the smallest
1586 char guess_suffix
= 0;
1590 guess_suffix
= i
.suffix
;
1591 else if (i
.reg_operands
)
1593 /* Figure out a suffix from the last register operand specified.
1594 We can't do this properly yet, ie. excluding InOutPortReg,
1595 but the following works for instructions with immediates.
1596 In any case, we can't set i.suffix yet. */
1597 for (op
= i
.operands
; --op
>= 0;)
1598 if (i
.types
[op
] & Reg
)
1600 if (i
.types
[op
] & Reg8
)
1601 guess_suffix
= BYTE_MNEM_SUFFIX
;
1602 else if (i
.types
[op
] & Reg16
)
1603 guess_suffix
= WORD_MNEM_SUFFIX
;
1604 else if (i
.types
[op
] & Reg32
)
1605 guess_suffix
= LONG_MNEM_SUFFIX
;
1606 else if (i
.types
[op
] & Reg64
)
1607 guess_suffix
= QWORD_MNEM_SUFFIX
;
1611 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1612 guess_suffix
= WORD_MNEM_SUFFIX
;
1614 for (op
= i
.operands
; --op
>= 0;)
1615 if (i
.types
[op
] & Imm
)
1617 switch (i
.op
[op
].imms
->X_op
)
1620 /* If a suffix is given, this operand may be shortened. */
1621 switch (guess_suffix
)
1623 case LONG_MNEM_SUFFIX
:
1624 i
.types
[op
] |= Imm32
| Imm64
;
1626 case WORD_MNEM_SUFFIX
:
1627 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1629 case BYTE_MNEM_SUFFIX
:
1630 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1634 /* If this operand is at most 16 bits, convert it
1635 to a signed 16 bit number before trying to see
1636 whether it will fit in an even smaller size.
1637 This allows a 16-bit operand such as $0xffe0 to
1638 be recognised as within Imm8S range. */
1639 if ((i
.types
[op
] & Imm16
)
1640 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1642 i
.op
[op
].imms
->X_add_number
=
1643 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1645 if ((i
.types
[op
] & Imm32
)
1646 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1648 i
.op
[op
].imms
->X_add_number
=
1649 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1651 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1652 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1653 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1654 i
.types
[op
] &= ~Imm32
;
1659 /* Symbols and expressions. */
1661 /* Convert symbolic operand to proper sizes for matching. */
1662 switch (guess_suffix
)
1664 case QWORD_MNEM_SUFFIX
:
1665 i
.types
[op
] = Imm64
| Imm32S
;
1667 case LONG_MNEM_SUFFIX
:
1668 i
.types
[op
] = Imm32
| Imm64
;
1670 case WORD_MNEM_SUFFIX
:
1671 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1674 case BYTE_MNEM_SUFFIX
:
1675 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1684 if (i
.disp_operands
)
1686 /* Try to use the smallest displacement type too. */
1689 for (op
= i
.operands
; --op
>= 0;)
1690 if ((i
.types
[op
] & Disp
)
1691 && i
.op
[op
].disps
->X_op
== O_constant
)
1693 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1695 if (i
.types
[op
] & Disp16
)
1697 /* We know this operand is at most 16 bits, so
1698 convert to a signed 16 bit number before trying
1699 to see whether it will fit in an even smaller
1702 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1704 else if (i
.types
[op
] & Disp32
)
1706 /* We know this operand is at most 32 bits, so convert to a
1707 signed 32 bit number before trying to see whether it will
1708 fit in an even smaller size. */
1709 disp
&= (((offsetT
) 2 << 31) - 1);
1710 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1712 if (flag_code
== CODE_64BIT
)
1714 if (fits_in_signed_long (disp
))
1715 i
.types
[op
] |= Disp32S
;
1716 if (fits_in_unsigned_long (disp
))
1717 i
.types
[op
] |= Disp32
;
1719 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1720 && fits_in_signed_byte (disp
))
1721 i
.types
[op
] |= Disp8
;
1728 found_reverse_match
= 0;
1729 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1731 : (i
.suffix
== WORD_MNEM_SUFFIX
1733 : (i
.suffix
== SHORT_MNEM_SUFFIX
1735 : (i
.suffix
== LONG_MNEM_SUFFIX
1737 : (i
.suffix
== QWORD_MNEM_SUFFIX
1739 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1741 for (t
= current_templates
->start
;
1742 t
< current_templates
->end
;
1745 /* Must have right number of operands. */
1746 if (i
.operands
!= t
->operands
)
1749 /* Check the suffix, except for some instructions in intel mode. */
1750 if ((t
->opcode_modifier
& suffix_check
)
1752 && (t
->opcode_modifier
& IgnoreSize
))
1754 && t
->base_opcode
== 0xd9
1755 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1756 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1759 /* Do not verify operands when there are none. */
1760 else if (!t
->operands
)
1762 if (t
->cpu_flags
& ~cpu_arch_flags
)
1764 /* We've found a match; break out of loop. */
1768 overlap0
= i
.types
[0] & t
->operand_types
[0];
1769 switch (t
->operands
)
1772 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1777 overlap1
= i
.types
[1] & t
->operand_types
[1];
1778 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1779 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1780 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1781 t
->operand_types
[0],
1782 overlap1
, i
.types
[1],
1783 t
->operand_types
[1]))
1785 /* Check if other direction is valid ... */
1786 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1789 /* Try reversing direction of operands. */
1790 overlap0
= i
.types
[0] & t
->operand_types
[1];
1791 overlap1
= i
.types
[1] & t
->operand_types
[0];
1792 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1793 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1794 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1795 t
->operand_types
[1],
1796 overlap1
, i
.types
[1],
1797 t
->operand_types
[0]))
1799 /* Does not match either direction. */
1802 /* found_reverse_match holds which of D or FloatDR
1804 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1806 /* Found a forward 2 operand match here. */
1807 else if (t
->operands
== 3)
1809 /* Here we make use of the fact that there are no
1810 reverse match 3 operand instructions, and all 3
1811 operand instructions only need to be checked for
1812 register consistency between operands 2 and 3. */
1813 overlap2
= i
.types
[2] & t
->operand_types
[2];
1814 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1815 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1816 t
->operand_types
[1],
1817 overlap2
, i
.types
[2],
1818 t
->operand_types
[2]))
1822 /* Found either forward/reverse 2 or 3 operand match here:
1823 slip through to break. */
1825 if (t
->cpu_flags
& ~cpu_arch_flags
)
1827 found_reverse_match
= 0;
1830 /* We've found a match; break out of loop. */
1833 if (t
== current_templates
->end
)
1835 /* We found no match. */
1836 as_bad (_("suffix or operands invalid for `%s'"),
1837 current_templates
->start
->name
);
1841 if (!quiet_warnings
)
1844 && ((i
.types
[0] & JumpAbsolute
)
1845 != (t
->operand_types
[0] & JumpAbsolute
)))
1847 as_warn (_("indirect %s without `*'"), t
->name
);
1850 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1851 == (IsPrefix
|IgnoreSize
))
1853 /* Warn them that a data or address size prefix doesn't
1854 affect assembly of the next line of code. */
1855 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1859 /* Copy the template we found. */
1861 if (found_reverse_match
)
1863 /* If we found a reverse match we must alter the opcode
1864 direction bit. found_reverse_match holds bits to change
1865 (different for int & float insns). */
1867 i
.tm
.base_opcode
^= found_reverse_match
;
1869 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1870 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1873 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1876 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1877 i
.tm
.base_opcode
^= FloatR
;
1879 if (i
.tm
.opcode_modifier
& FWait
)
1880 if (! add_prefix (FWAIT_OPCODE
))
1883 /* Check string instruction segment overrides. */
1884 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1886 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1887 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1889 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1891 as_bad (_("`%s' operand %d must use `%%es' segment"),
1896 /* There's only ever one segment override allowed per instruction.
1897 This instruction possibly has a legal segment override on the
1898 second operand, so copy the segment to where non-string
1899 instructions store it, allowing common code. */
1900 i
.seg
[0] = i
.seg
[1];
1902 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1904 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1906 as_bad (_("`%s' operand %d must use `%%es' segment"),
1914 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1917 for (op
= i
.operands
; --op
>= 0;)
1918 if ((i
.types
[op
] & Reg
)
1919 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1921 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1922 i
.op
[op
].regs
->reg_name
);
1927 /* If matched instruction specifies an explicit instruction mnemonic
1929 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1931 if (i
.tm
.opcode_modifier
& Size16
)
1932 i
.suffix
= WORD_MNEM_SUFFIX
;
1933 else if (i
.tm
.opcode_modifier
& Size64
)
1934 i
.suffix
= QWORD_MNEM_SUFFIX
;
1936 i
.suffix
= LONG_MNEM_SUFFIX
;
1938 else if (i
.reg_operands
)
1940 /* If there's no instruction mnemonic suffix we try to invent one
1941 based on register operands. */
1944 /* We take i.suffix from the last register operand specified,
1945 Destination register type is more significant than source
1948 for (op
= i
.operands
; --op
>= 0;)
1949 if ((i
.types
[op
] & Reg
)
1950 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1952 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1953 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1954 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1959 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1962 for (op
= i
.operands
; --op
>= 0;)
1964 /* If this is an eight bit register, it's OK. If it's
1965 the 16 or 32 bit version of an eight bit register,
1966 we will just use the low portion, and that's OK too. */
1967 if (i
.types
[op
] & Reg8
)
1970 /* movzx and movsx should not generate this warning. */
1972 && (i
.tm
.base_opcode
== 0xfb7
1973 || i
.tm
.base_opcode
== 0xfb6
1974 || i
.tm
.base_opcode
== 0x63
1975 || i
.tm
.base_opcode
== 0xfbe
1976 || i
.tm
.base_opcode
== 0xfbf))
1979 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1981 /* Check that the template allows eight bit regs
1982 This kills insns such as `orb $1,%edx', which
1983 maybe should be allowed. */
1984 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1988 /* Prohibit these changes in the 64bit mode, since
1989 the lowering is more complicated. */
1990 if (flag_code
== CODE_64BIT
1991 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1992 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1993 i
.op
[op
].regs
->reg_name
,
1995 #if REGISTER_WARNINGS
1997 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1998 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2000 + (i
.types
[op
] & Reg16
2001 ? REGNAM_AL
- REGNAM_AX
2002 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2003 i
.op
[op
].regs
->reg_name
,
2008 /* Any other register is bad. */
2009 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2011 | Control
| Debug
| Test
2012 | FloatReg
| FloatAcc
))
2014 as_bad (_("`%%%s' not allowed with `%s%c'"),
2015 i
.op
[op
].regs
->reg_name
,
2022 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2026 for (op
= i
.operands
; --op
>= 0;)
2027 /* Reject eight bit registers, except where the template
2028 requires them. (eg. movzb) */
2029 if ((i
.types
[op
] & Reg8
) != 0
2030 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2032 as_bad (_("`%%%s' not allowed with `%s%c'"),
2033 i
.op
[op
].regs
->reg_name
,
2038 /* Warn if the e prefix on a general reg is missing. */
2039 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2040 && (i
.types
[op
] & Reg16
) != 0
2041 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2043 /* Prohibit these changes in the 64bit mode, since
2044 the lowering is more complicated. */
2045 if (flag_code
== CODE_64BIT
)
2046 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2047 i
.op
[op
].regs
->reg_name
,
2049 #if REGISTER_WARNINGS
2051 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2052 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2053 i
.op
[op
].regs
->reg_name
,
2057 /* Warn if the r prefix on a general reg is missing. */
2058 else if ((i
.types
[op
] & Reg64
) != 0
2059 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2061 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2062 i
.op
[op
].regs
->reg_name
,
2066 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2070 for (op
= i
.operands
; --op
>= 0; )
2071 /* Reject eight bit registers, except where the template
2072 requires them. (eg. movzb) */
2073 if ((i
.types
[op
] & Reg8
) != 0
2074 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2076 as_bad (_("`%%%s' not allowed with `%s%c'"),
2077 i
.op
[op
].regs
->reg_name
,
2082 /* Warn if the e prefix on a general reg is missing. */
2083 else if (((i
.types
[op
] & Reg16
) != 0
2084 || (i
.types
[op
] & Reg32
) != 0)
2085 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2087 /* Prohibit these changes in the 64bit mode, since
2088 the lowering is more complicated. */
2089 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2090 i
.op
[op
].regs
->reg_name
,
2094 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2097 for (op
= i
.operands
; --op
>= 0;)
2098 /* Reject eight bit registers, except where the template
2099 requires them. (eg. movzb) */
2100 if ((i
.types
[op
] & Reg8
) != 0
2101 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2103 as_bad (_("`%%%s' not allowed with `%s%c'"),
2104 i
.op
[op
].regs
->reg_name
,
2109 /* Warn if the e prefix on a general reg is present. */
2110 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2111 && (i
.types
[op
] & Reg32
) != 0
2112 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2114 /* Prohibit these changes in the 64bit mode, since
2115 the lowering is more complicated. */
2116 if (flag_code
== CODE_64BIT
)
2117 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2118 i
.op
[op
].regs
->reg_name
,
2121 #if REGISTER_WARNINGS
2122 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2123 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2124 i
.op
[op
].regs
->reg_name
,
2129 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2130 /* Do nothing if the instruction is going to ignore the prefix. */
2135 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2137 i
.suffix
= stackop_size
;
2139 /* Make still unresolved immediate matches conform to size of immediate
2140 given in i.suffix. Note: overlap2 cannot be an immediate! */
2141 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2142 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2143 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2144 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2148 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2149 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2150 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2152 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2153 || overlap0
== (Imm16
| Imm32
)
2154 || overlap0
== (Imm16
| Imm32S
))
2157 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2159 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2160 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2161 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2163 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2167 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2168 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2169 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2170 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2174 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2175 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2176 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2178 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2179 || overlap1
== (Imm16
| Imm32
)
2180 || overlap1
== (Imm16
| Imm32S
))
2183 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2185 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2186 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2187 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2189 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2193 assert ((overlap2
& Imm
) == 0);
2195 i
.types
[0] = overlap0
;
2196 if (overlap0
& ImplicitRegister
)
2198 if (overlap0
& Imm1
)
2199 i
.imm_operands
= 0; /* kludge for shift insns. */
2201 i
.types
[1] = overlap1
;
2202 if (overlap1
& ImplicitRegister
)
2205 i
.types
[2] = overlap2
;
2206 if (overlap2
& ImplicitRegister
)
2209 /* Finalize opcode. First, we change the opcode based on the operand
2210 size given by i.suffix: We need not change things for byte insns. */
2212 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2214 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2218 /* For movzx and movsx, need to check the register type. */
2220 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2221 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2223 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2225 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2226 if (!add_prefix (prefix
))
2230 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2232 /* It's not a byte, select word/dword operation. */
2233 if (i
.tm
.opcode_modifier
& W
)
2235 if (i
.tm
.opcode_modifier
& ShortForm
)
2236 i
.tm
.base_opcode
|= 8;
2238 i
.tm
.base_opcode
|= 1;
2240 /* Now select between word & dword operations via the operand
2241 size prefix, except for instructions that will ignore this
2243 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2244 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2245 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2247 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2248 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2249 prefix
= ADDR_PREFIX_OPCODE
;
2251 if (! add_prefix (prefix
))
2255 /* Set mode64 for an operand. */
2256 if (i
.suffix
== QWORD_MNEM_SUFFIX
2257 && !(i
.tm
.opcode_modifier
& NoRex64
))
2260 if (flag_code
< CODE_64BIT
)
2262 as_bad (_("64bit operations available only in 64bit modes."));
2267 /* Size floating point instruction. */
2268 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2270 if (i
.tm
.opcode_modifier
& FloatMF
)
2271 i
.tm
.base_opcode
^= 4;
2275 if (i
.tm
.opcode_modifier
& ImmExt
)
2277 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2278 opcode suffix which is coded in the same place as an 8-bit
2279 immediate field would be. Here we fake an 8-bit immediate
2280 operand from the opcode suffix stored in tm.extension_opcode. */
2284 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2286 exp
= &im_expressions
[i
.imm_operands
++];
2287 i
.op
[i
.operands
].imms
= exp
;
2288 i
.types
[i
.operands
++] = Imm8
;
2289 exp
->X_op
= O_constant
;
2290 exp
->X_add_number
= i
.tm
.extension_opcode
;
2291 i
.tm
.extension_opcode
= None
;
2294 /* For insns with operands there are more diddles to do to the opcode. */
2297 /* Default segment register this instruction will use
2298 for memory accesses. 0 means unknown.
2299 This is only for optimizing out unnecessary segment overrides. */
2300 const seg_entry
*default_seg
= 0;
2302 /* The imul $imm, %reg instruction is converted into
2303 imul $imm, %reg, %reg, and the clr %reg instruction
2304 is converted into xor %reg, %reg. */
2305 if (i
.tm
.opcode_modifier
& regKludge
)
2307 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2308 /* Pretend we saw the extra register operand. */
2309 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2310 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2311 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2315 if (i
.tm
.opcode_modifier
& ShortForm
)
2317 /* The register or float register operand is in operand 0 or 1. */
2318 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2319 /* Register goes in low 3 bits of opcode. */
2320 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2321 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2323 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2325 /* Warn about some common errors, but press on regardless.
2326 The first case can be generated by gcc (<= 2.8.1). */
2327 if (i
.operands
== 2)
2329 /* Reversed arguments on faddp, fsubp, etc. */
2330 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2331 i
.op
[1].regs
->reg_name
,
2332 i
.op
[0].regs
->reg_name
);
2336 /* Extraneous `l' suffix on fp insn. */
2337 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2338 i
.op
[0].regs
->reg_name
);
2342 else if (i
.tm
.opcode_modifier
& Modrm
)
2344 /* The opcode is completed (modulo i.tm.extension_opcode which
2345 must be put into the modrm byte).
2346 Now, we make the modrm & index base bytes based on all the
2347 info we've collected. */
2349 /* i.reg_operands MUST be the number of real register operands;
2350 implicit registers do not count. */
2351 if (i
.reg_operands
== 2)
2353 unsigned int source
, dest
;
2354 source
= ((i
.types
[0]
2355 & (Reg
| RegMMX
| RegXMM
2357 | Control
| Debug
| Test
))
2362 /* One of the register operands will be encoded in the
2363 i.tm.reg field, the other in the combined i.tm.mode
2364 and i.tm.regmem fields. If no form of this
2365 instruction supports a memory destination operand,
2366 then we assume the source operand may sometimes be
2367 a memory operand and so we need to store the
2368 destination in the i.rm.reg field. */
2369 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2371 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2372 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2373 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2375 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2380 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2381 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2382 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2384 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2389 { /* If it's not 2 reg operands... */
2392 unsigned int fake_zero_displacement
= 0;
2393 unsigned int op
= ((i
.types
[0] & AnyMem
)
2395 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2402 if (! i
.disp_operands
)
2403 fake_zero_displacement
= 1;
2406 /* Operand is just <disp> */
2407 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2409 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2410 i
.types
[op
] &= ~Disp
;
2411 i
.types
[op
] |= Disp16
;
2413 else if (flag_code
!= CODE_64BIT
)
2415 i
.rm
.regmem
= NO_BASE_REGISTER
;
2416 i
.types
[op
] &= ~Disp
;
2417 i
.types
[op
] |= Disp32
;
2421 /* 64bit mode overwrites the 32bit
2422 absolute addressing by RIP relative
2423 addressing and absolute addressing
2424 is encoded by one of the redundant
2427 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2428 i
.sib
.base
= NO_BASE_REGISTER
;
2429 i
.sib
.index
= NO_INDEX_REGISTER
;
2430 i
.types
[op
] &= ~Disp
;
2431 i
.types
[op
] |= Disp32S
;
2434 else /* ! i.base_reg && i.index_reg */
2436 i
.sib
.index
= i
.index_reg
->reg_num
;
2437 i
.sib
.base
= NO_BASE_REGISTER
;
2438 i
.sib
.scale
= i
.log2_scale_factor
;
2439 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2440 i
.types
[op
] &= ~Disp
;
2441 if (flag_code
!= CODE_64BIT
)
2442 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2444 i
.types
[op
] |= Disp32S
;
2445 if (i
.index_reg
->reg_flags
& RegRex
)
2449 /* RIP addressing for 64bit mode. */
2450 else if (i
.base_reg
->reg_type
== BaseIndex
)
2452 i
.rm
.regmem
= NO_BASE_REGISTER
;
2453 i
.types
[op
] &= ~Disp
;
2454 i
.types
[op
] |= Disp32S
;
2455 i
.flags
[op
] = Operand_PCrel
;
2457 else if (i
.base_reg
->reg_type
& Reg16
)
2459 switch (i
.base_reg
->reg_num
)
2464 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2465 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2472 if ((i
.types
[op
] & Disp
) == 0)
2474 /* fake (%bp) into 0(%bp) */
2475 i
.types
[op
] |= Disp8
;
2476 fake_zero_displacement
= 1;
2479 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2480 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2482 default: /* (%si) -> 4 or (%di) -> 5 */
2483 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2485 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2487 else /* i.base_reg and 32/64 bit mode */
2489 if (flag_code
== CODE_64BIT
2490 && (i
.types
[op
] & Disp
))
2492 if (i
.types
[op
] & Disp8
)
2493 i
.types
[op
] = Disp8
| Disp32S
;
2495 i
.types
[op
] = Disp32S
;
2497 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2498 if (i
.base_reg
->reg_flags
& RegRex
)
2500 i
.sib
.base
= i
.base_reg
->reg_num
;
2501 /* x86-64 ignores REX prefix bit here to avoid
2502 decoder complications. */
2503 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2506 if (i
.disp_operands
== 0)
2508 fake_zero_displacement
= 1;
2509 i
.types
[op
] |= Disp8
;
2512 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2516 i
.sib
.scale
= i
.log2_scale_factor
;
2519 /* <disp>(%esp) becomes two byte modrm
2520 with no index register. We've already
2521 stored the code for esp in i.rm.regmem
2522 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2523 base register besides %esp will not use
2524 the extra modrm byte. */
2525 i
.sib
.index
= NO_INDEX_REGISTER
;
2526 #if ! SCALE1_WHEN_NO_INDEX
2527 /* Another case where we force the second
2529 if (i
.log2_scale_factor
)
2530 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2535 i
.sib
.index
= i
.index_reg
->reg_num
;
2536 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2537 if (i
.index_reg
->reg_flags
& RegRex
)
2540 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2543 if (fake_zero_displacement
)
2545 /* Fakes a zero displacement assuming that i.types[op]
2546 holds the correct displacement size. */
2549 assert (i
.op
[op
].disps
== 0);
2550 exp
= &disp_expressions
[i
.disp_operands
++];
2551 i
.op
[op
].disps
= exp
;
2552 exp
->X_op
= O_constant
;
2553 exp
->X_add_number
= 0;
2554 exp
->X_add_symbol
= (symbolS
*) 0;
2555 exp
->X_op_symbol
= (symbolS
*) 0;
2559 /* Fill in i.rm.reg or i.rm.regmem field with register
2560 operand (if any) based on i.tm.extension_opcode.
2561 Again, we must be careful to make sure that
2562 segment/control/debug/test/MMX registers are coded
2563 into the i.rm.reg field. */
2568 & (Reg
| RegMMX
| RegXMM
2570 | Control
| Debug
| Test
))
2573 & (Reg
| RegMMX
| RegXMM
2575 | Control
| Debug
| Test
))
2578 /* If there is an extension opcode to put here, the
2579 register number must be put into the regmem field. */
2580 if (i
.tm
.extension_opcode
!= None
)
2582 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2583 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2588 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2589 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2593 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2594 we must set it to 3 to indicate this is a register
2595 operand in the regmem field. */
2596 if (!i
.mem_operands
)
2600 /* Fill in i.rm.reg field with extension opcode (if any). */
2601 if (i
.tm
.extension_opcode
!= None
)
2602 i
.rm
.reg
= i
.tm
.extension_opcode
;
2605 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2607 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2608 && i
.op
[0].regs
->reg_num
== 1)
2610 as_bad (_("you can't `pop %%cs'"));
2613 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2614 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2617 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2621 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2623 /* For the string instructions that allow a segment override
2624 on one of their operands, the default segment is ds. */
2628 /* If a segment was explicitly specified,
2629 and the specified segment is not the default,
2630 use an opcode prefix to select it.
2631 If we never figured out what the default segment is,
2632 then default_seg will be zero at this point,
2633 and the specified segment prefix will always be used. */
2634 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2636 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2640 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2642 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2643 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2647 /* Handle conversion of 'int $3' --> special int3 insn. */
2648 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2650 i
.tm
.base_opcode
= INT3_OPCODE
;
2654 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2655 && i
.op
[0].disps
->X_op
== O_constant
)
2657 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2658 the absolute address given by the constant. Since ix86 jumps and
2659 calls are pc relative, we need to generate a reloc. */
2660 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2661 i
.op
[0].disps
->X_op
= O_symbol
;
2664 if (i
.tm
.opcode_modifier
& Rex64
)
2667 /* For 8bit registers we would need an empty rex prefix.
2668 Also in the case instruction is already having prefix,
2669 we need to convert old registers to new ones. */
2671 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2672 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2673 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2674 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2678 for (x
= 0; x
< 2; x
++)
2680 /* Look for 8bit operand that does use old registers. */
2681 if (i
.types
[x
] & Reg8
2682 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2684 /* In case it is "hi" register, give up. */
2685 if (i
.op
[x
].regs
->reg_num
> 3)
2686 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2687 i
.op
[x
].regs
->reg_name
);
2689 /* Otherwise it is equivalent to the extended register.
2690 Since the encoding don't change this is merely cosmetical
2691 cleanup for debug output. */
2693 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2698 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2700 | (i
.rex
.mode64
? 8 : 0)
2701 | (i
.rex
.extX
? 4 : 0)
2702 | (i
.rex
.extY
? 2 : 0)
2703 | (i
.rex
.extZ
? 1 : 0));
2705 /* We are ready to output the insn. */
2710 if (i
.tm
.opcode_modifier
& Jump
)
2716 if (flag_code
== CODE_16BIT
)
2720 if (i
.prefix
[DATA_PREFIX
])
2726 if (i
.prefix
[REX_PREFIX
])
2732 if (i
.prefixes
!= 0 && !intel_syntax
)
2733 as_warn (_("skipping prefixes on this instruction"));
2735 /* It's always a symbol; End frag & setup for relax.
2736 Make sure there is enough room in this frag for the largest
2737 instruction we may generate in md_convert_frag. This is 2
2738 bytes for the opcode and room for the prefix and largest
2740 frag_grow (prefix
+ 2 + 4);
2741 insn_size
+= prefix
+ 1;
2742 /* Prefix and 1 opcode byte go in fr_fix. */
2743 p
= frag_more (prefix
+ 1);
2744 if (i
.prefix
[DATA_PREFIX
])
2745 *p
++ = DATA_PREFIX_OPCODE
;
2746 if (i
.prefix
[REX_PREFIX
])
2747 *p
++ = i
.prefix
[REX_PREFIX
];
2748 *p
= i
.tm
.base_opcode
;
2749 /* 1 possible extra opcode + displacement go in var part.
2750 Pass reloc in fr_var. */
2751 frag_var (rs_machine_dependent
,
2754 ((unsigned char) *p
== JUMP_PC_RELATIVE
2755 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2756 : ((cpu_arch_flags
& Cpu386
) != 0
2757 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2758 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2759 i
.op
[0].disps
->X_add_symbol
,
2760 i
.op
[0].disps
->X_add_number
,
2763 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2767 if (i
.tm
.opcode_modifier
& JumpByte
)
2769 /* This is a loop or jecxz type instruction. */
2771 if (i
.prefix
[ADDR_PREFIX
])
2774 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2783 if (flag_code
== CODE_16BIT
)
2786 if (i
.prefix
[DATA_PREFIX
])
2789 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2799 if (i
.prefix
[REX_PREFIX
])
2801 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2806 if (i
.prefixes
!= 0 && !intel_syntax
)
2807 as_warn (_("skipping prefixes on this instruction"));
2809 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2811 insn_size
+= 1 + size
;
2812 p
= frag_more (1 + size
);
2816 /* Opcode can be at most two bytes. */
2817 insn_size
+= 2 + size
;
2818 p
= frag_more (2 + size
);
2819 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2821 *p
++ = i
.tm
.base_opcode
& 0xff;
2823 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2824 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
2826 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2833 if (flag_code
== CODE_16BIT
)
2837 if (i
.prefix
[DATA_PREFIX
])
2843 if (i
.prefix
[REX_PREFIX
])
2853 if (i
.prefixes
!= 0 && !intel_syntax
)
2854 as_warn (_("skipping prefixes on this instruction"));
2856 /* 1 opcode; 2 segment; offset */
2857 insn_size
+= prefix
+ 1 + 2 + size
;
2858 p
= frag_more (prefix
+ 1 + 2 + size
);
2860 if (i
.prefix
[DATA_PREFIX
])
2861 *p
++ = DATA_PREFIX_OPCODE
;
2863 if (i
.prefix
[REX_PREFIX
])
2864 *p
++ = i
.prefix
[REX_PREFIX
];
2866 *p
++ = i
.tm
.base_opcode
;
2867 if (i
.op
[1].imms
->X_op
== O_constant
)
2869 offsetT n
= i
.op
[1].imms
->X_add_number
;
2872 && !fits_in_unsigned_word (n
)
2873 && !fits_in_signed_word (n
))
2875 as_bad (_("16-bit jump out of range"));
2878 md_number_to_chars (p
, n
, size
);
2881 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2882 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
2883 if (i
.op
[0].imms
->X_op
!= O_constant
)
2884 as_bad (_("can't handle non absolute segment in `%s'"),
2886 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2890 /* Output normal instructions here. */
2893 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2894 byte for the SSE instructions to specify prefix they require. */
2895 if (i
.tm
.base_opcode
& 0xff0000)
2896 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2898 /* The prefix bytes. */
2900 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2907 md_number_to_chars (p
, (valueT
) *q
, 1);
2911 /* Now the opcode; be careful about word order here! */
2912 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2915 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2921 /* Put out high byte first: can't use md_number_to_chars! */
2922 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2923 *p
= i
.tm
.base_opcode
& 0xff;
2926 /* Now the modrm byte and sib byte (if present). */
2927 if (i
.tm
.opcode_modifier
& Modrm
)
2931 md_number_to_chars (p
,
2932 (valueT
) (i
.rm
.regmem
<< 0
2936 /* If i.rm.regmem == ESP (4)
2937 && i.rm.mode != (Register mode)
2939 ==> need second modrm byte. */
2940 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2942 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2946 md_number_to_chars (p
,
2947 (valueT
) (i
.sib
.base
<< 0
2949 | i
.sib
.scale
<< 6),
2954 if (i
.disp_operands
)
2956 register unsigned int n
;
2958 for (n
= 0; n
< i
.operands
; n
++)
2960 if (i
.types
[n
] & Disp
)
2962 if (i
.op
[n
].disps
->X_op
== O_constant
)
2968 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2971 if (i
.types
[n
] & Disp8
)
2973 if (i
.types
[n
] & Disp64
)
2976 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2979 p
= frag_more (size
);
2980 md_number_to_chars (p
, val
, size
);
2986 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2988 /* The PC relative address is computed relative
2989 to the instruction boundary, so in case immediate
2990 fields follows, we need to adjust the value. */
2991 if (pcrel
&& i
.imm_operands
)
2994 register unsigned int n1
;
2996 for (n1
= 0; n1
< i
.operands
; n1
++)
2997 if (i
.types
[n1
] & Imm
)
2999 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3002 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3004 if (i
.types
[n1
] & Imm64
)
3009 /* We should find the immediate. */
3010 if (n1
== i
.operands
)
3012 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3015 if (i
.types
[n
] & Disp32S
)
3018 if (i
.types
[n
] & (Disp16
| Disp64
))
3021 if (i
.types
[n
] & Disp64
)
3026 p
= frag_more (size
);
3027 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3028 i
.op
[n
].disps
, pcrel
,
3029 reloc (size
, pcrel
, sign
, i
.reloc
[n
]));
3035 /* Output immediate. */
3038 register unsigned int n
;
3040 for (n
= 0; n
< i
.operands
; n
++)
3042 if (i
.types
[n
] & Imm
)
3044 if (i
.op
[n
].imms
->X_op
== O_constant
)
3050 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3053 if (i
.types
[n
] & (Imm8
| Imm8S
))
3055 else if (i
.types
[n
] & Imm64
)
3058 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3061 p
= frag_more (size
);
3062 md_number_to_chars (p
, val
, size
);
3066 /* Not absolute_section.
3067 Need a 32-bit fixup (don't support 8bit
3068 non-absolute imms). Try to support other
3070 RELOC_ENUM reloc_type
;
3074 if ((i
.types
[n
] & (Imm32S
))
3075 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3077 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3080 if (i
.types
[n
] & (Imm8
| Imm8S
))
3082 if (i
.types
[n
] & Imm64
)
3087 p
= frag_more (size
);
3088 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3089 #ifdef BFD_ASSEMBLER
3090 if (reloc_type
== BFD_RELOC_32
3092 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3093 && (i
.op
[n
].imms
->X_op
== O_symbol
3094 || (i
.op
[n
].imms
->X_op
== O_add
3095 && ((symbol_get_value_expression
3096 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3099 /* We don't support dynamic linking on x86-64 yet. */
3100 if (flag_code
== CODE_64BIT
)
3102 reloc_type
= BFD_RELOC_386_GOTPC
;
3103 i
.op
[n
].imms
->X_add_number
+= 3;
3106 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3107 i
.op
[n
].imms
, 0, reloc_type
);
3114 dwarf2_emit_insn (insn_size
);
3121 #endif /* DEBUG386 */
3126 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3128 /* Parse operands of the form
3129 <symbol>@GOTOFF+<nnn>
3130 and similar .plt or .got references.
3132 If we find one, set up the correct relocation in RELOC and copy the
3133 input string, minus the `@GOTOFF' into a malloc'd buffer for
3134 parsing by the calling routine. Return this buffer, and if ADJUST
3135 is non-null set it to the length of the string we removed from the
3136 input line. Otherwise return NULL. */
3138 lex_got (reloc
, adjust
)
3142 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3143 static const struct {
3145 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3147 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3148 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3149 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3150 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3155 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3156 if (is_end_of_line
[(unsigned char) *cp
])
3159 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3163 len
= strlen (gotrel
[j
].str
);
3164 if (strncmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3166 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3171 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3173 if (GOT_symbol
== NULL
)
3174 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3176 /* Replace the relocation token with ' ', so that
3177 errors like foo@GOTOFF1 will be detected. */
3178 first
= cp
- input_line_pointer
;
3179 tmpbuf
= xmalloc (strlen (input_line_pointer
));
3180 memcpy (tmpbuf
, input_line_pointer
, first
);
3181 tmpbuf
[first
] = ' ';
3182 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3188 as_bad (_("@%s reloc is not supported in %s bit mode"),
3189 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3194 /* Might be a symbol version string. Don't as_bad here. */
3198 /* x86_cons_fix_new is called via the expression parsing code when a
3199 reloc is needed. We use this hook to get the correct .got reloc. */
3200 static RELOC_ENUM got_reloc
= NO_RELOC
;
3203 x86_cons_fix_new (frag
, off
, len
, exp
)
3209 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3210 got_reloc
= NO_RELOC
;
3211 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3215 x86_cons (exp
, size
)
3221 /* Handle @GOTOFF and the like in an expression. */
3223 char *gotfree_input_line
;
3226 save
= input_line_pointer
;
3227 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3228 if (gotfree_input_line
)
3229 input_line_pointer
= gotfree_input_line
;
3233 if (gotfree_input_line
)
3235 /* expression () has merrily parsed up to the end of line,
3236 or a comma - in the wrong buffer. Transfer how far
3237 input_line_pointer has moved to the right buffer. */
3238 input_line_pointer
= (save
3239 + (input_line_pointer
- gotfree_input_line
)
3241 free (gotfree_input_line
);
3249 static int i386_immediate
PARAMS ((char *));
3252 i386_immediate (imm_start
)
3255 char *save_input_line_pointer
;
3257 char *gotfree_input_line
;
3262 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3264 as_bad (_("only 1 or 2 immediate operands are allowed"));
3268 exp
= &im_expressions
[i
.imm_operands
++];
3269 i
.op
[this_operand
].imms
= exp
;
3271 if (is_space_char (*imm_start
))
3274 save_input_line_pointer
= input_line_pointer
;
3275 input_line_pointer
= imm_start
;
3278 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3279 if (gotfree_input_line
)
3280 input_line_pointer
= gotfree_input_line
;
3283 exp_seg
= expression (exp
);
3286 if (*input_line_pointer
)
3287 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3289 input_line_pointer
= save_input_line_pointer
;
3291 if (gotfree_input_line
)
3292 free (gotfree_input_line
);
3295 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3297 /* Missing or bad expr becomes absolute 0. */
3298 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3300 exp
->X_op
= O_constant
;
3301 exp
->X_add_number
= 0;
3302 exp
->X_add_symbol
= (symbolS
*) 0;
3303 exp
->X_op_symbol
= (symbolS
*) 0;
3305 else if (exp
->X_op
== O_constant
)
3307 /* Size it properly later. */
3308 i
.types
[this_operand
] |= Imm64
;
3309 /* If BFD64, sign extend val. */
3310 if (!use_rela_relocations
)
3311 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3312 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3314 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3316 #ifdef BFD_ASSEMBLER
3317 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3319 && exp_seg
!= text_section
3320 && exp_seg
!= data_section
3321 && exp_seg
!= bss_section
3322 && exp_seg
!= undefined_section
3323 #ifdef BFD_ASSEMBLER
3324 && !bfd_is_com_section (exp_seg
)
3328 #ifdef BFD_ASSEMBLER
3329 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3331 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3338 /* This is an address. The size of the address will be
3339 determined later, depending on destination register,
3340 suffix, or the default for the section. */
3341 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3347 static char *i386_scale
PARAMS ((char *));
3354 char *save
= input_line_pointer
;
3356 input_line_pointer
= scale
;
3357 val
= get_absolute_expression ();
3363 i
.log2_scale_factor
= 0;
3366 i
.log2_scale_factor
= 1;
3369 i
.log2_scale_factor
= 2;
3372 i
.log2_scale_factor
= 3;
3375 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3377 input_line_pointer
= save
;
3380 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3382 as_warn (_("scale factor of %d without an index register"),
3383 1 << i
.log2_scale_factor
);
3384 #if SCALE1_WHEN_NO_INDEX
3385 i
.log2_scale_factor
= 0;
3388 scale
= input_line_pointer
;
3389 input_line_pointer
= save
;
3393 static int i386_displacement
PARAMS ((char *, char *));
3396 i386_displacement (disp_start
, disp_end
)
3400 register expressionS
*exp
;
3402 char *save_input_line_pointer
;
3404 char *gotfree_input_line
;
3406 int bigdisp
= Disp32
;
3408 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3410 if (flag_code
== CODE_64BIT
)
3412 i
.types
[this_operand
] |= bigdisp
;
3414 exp
= &disp_expressions
[i
.disp_operands
];
3415 i
.op
[this_operand
].disps
= exp
;
3417 save_input_line_pointer
= input_line_pointer
;
3418 input_line_pointer
= disp_start
;
3419 END_STRING_AND_SAVE (disp_end
);
3421 #ifndef GCC_ASM_O_HACK
3422 #define GCC_ASM_O_HACK 0
3425 END_STRING_AND_SAVE (disp_end
+ 1);
3426 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3427 && displacement_string_end
[-1] == '+')
3429 /* This hack is to avoid a warning when using the "o"
3430 constraint within gcc asm statements.
3433 #define _set_tssldt_desc(n,addr,limit,type) \
3434 __asm__ __volatile__ ( \
3436 "movw %w1,2+%0\n\t" \
3438 "movb %b1,4+%0\n\t" \
3439 "movb %4,5+%0\n\t" \
3440 "movb $0,6+%0\n\t" \
3441 "movb %h1,7+%0\n\t" \
3443 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3445 This works great except that the output assembler ends
3446 up looking a bit weird if it turns out that there is
3447 no offset. You end up producing code that looks like:
3460 So here we provide the missing zero. */
3462 *displacement_string_end
= '0';
3466 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3467 if (gotfree_input_line
)
3468 input_line_pointer
= gotfree_input_line
;
3471 exp_seg
= expression (exp
);
3473 #ifdef BFD_ASSEMBLER
3474 /* We do this to make sure that the section symbol is in
3475 the symbol table. We will ultimately change the relocation
3476 to be relative to the beginning of the section. */
3477 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3478 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3480 if (S_IS_LOCAL (exp
->X_add_symbol
)
3481 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3482 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3483 assert (exp
->X_op
== O_symbol
);
3484 exp
->X_op
= O_subtract
;
3485 exp
->X_op_symbol
= GOT_symbol
;
3486 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3487 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3489 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3494 if (*input_line_pointer
)
3495 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3497 RESTORE_END_STRING (disp_end
+ 1);
3499 RESTORE_END_STRING (disp_end
);
3500 input_line_pointer
= save_input_line_pointer
;
3502 if (gotfree_input_line
)
3503 free (gotfree_input_line
);
3506 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3508 /* Missing or bad expr becomes absolute 0. */
3509 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3511 exp
->X_op
= O_constant
;
3512 exp
->X_add_number
= 0;
3513 exp
->X_add_symbol
= (symbolS
*) 0;
3514 exp
->X_op_symbol
= (symbolS
*) 0;
3517 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3518 if (exp
->X_op
!= O_constant
3519 #ifdef BFD_ASSEMBLER
3520 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3522 && exp_seg
!= text_section
3523 && exp_seg
!= data_section
3524 && exp_seg
!= bss_section
3525 && exp_seg
!= undefined_section
)
3527 #ifdef BFD_ASSEMBLER
3528 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3530 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3535 else if (flag_code
== CODE_64BIT
)
3536 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3540 static int i386_index_check
PARAMS ((const char *));
3542 /* Make sure the memory operand we've been dealt is valid.
3543 Return 1 on success, 0 on a failure. */
3546 i386_index_check (operand_string
)
3547 const char *operand_string
;
3550 #if INFER_ADDR_PREFIX
3556 if (flag_code
== CODE_64BIT
)
3560 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3561 && (i
.base_reg
->reg_type
!= BaseIndex
3564 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3565 != (Reg64
|BaseIndex
))))
3570 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3574 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3575 != (Reg16
|BaseIndex
)))
3577 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3578 != (Reg16
|BaseIndex
))
3580 && i
.base_reg
->reg_num
< 6
3581 && i
.index_reg
->reg_num
>= 6
3582 && i
.log2_scale_factor
== 0))))
3589 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3591 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3592 != (Reg32
|BaseIndex
))))
3598 #if INFER_ADDR_PREFIX
3599 if (flag_code
!= CODE_64BIT
3600 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3602 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3604 /* Change the size of any displacement too. At most one of
3605 Disp16 or Disp32 is set.
3606 FIXME. There doesn't seem to be any real need for separate
3607 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3608 Removing them would probably clean up the code quite a lot. */
3609 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3610 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3615 as_bad (_("`%s' is not a valid base/index expression"),
3619 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3621 flag_code_names
[flag_code
]);
3627 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3631 i386_operand (operand_string
)
3632 char *operand_string
;
3636 char *op_string
= operand_string
;
3638 if (is_space_char (*op_string
))
3641 /* We check for an absolute prefix (differentiating,
3642 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3643 if (*op_string
== ABSOLUTE_PREFIX
)
3646 if (is_space_char (*op_string
))
3648 i
.types
[this_operand
] |= JumpAbsolute
;
3651 /* Check if operand is a register. */
3652 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3653 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3655 /* Check for a segment override by searching for ':' after a
3656 segment register. */
3658 if (is_space_char (*op_string
))
3660 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3665 i
.seg
[i
.mem_operands
] = &es
;
3668 i
.seg
[i
.mem_operands
] = &cs
;
3671 i
.seg
[i
.mem_operands
] = &ss
;
3674 i
.seg
[i
.mem_operands
] = &ds
;
3677 i
.seg
[i
.mem_operands
] = &fs
;
3680 i
.seg
[i
.mem_operands
] = &gs
;
3684 /* Skip the ':' and whitespace. */
3686 if (is_space_char (*op_string
))
3689 if (!is_digit_char (*op_string
)
3690 && !is_identifier_char (*op_string
)
3691 && *op_string
!= '('
3692 && *op_string
!= ABSOLUTE_PREFIX
)
3694 as_bad (_("bad memory operand `%s'"), op_string
);
3697 /* Handle case of %es:*foo. */
3698 if (*op_string
== ABSOLUTE_PREFIX
)
3701 if (is_space_char (*op_string
))
3703 i
.types
[this_operand
] |= JumpAbsolute
;
3705 goto do_memory_reference
;
3709 as_bad (_("junk `%s' after register"), op_string
);
3712 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3713 i
.op
[this_operand
].regs
= r
;
3716 else if (*op_string
== REGISTER_PREFIX
)
3718 as_bad (_("bad register name `%s'"), op_string
);
3721 else if (*op_string
== IMMEDIATE_PREFIX
)
3724 if (i
.types
[this_operand
] & JumpAbsolute
)
3726 as_bad (_("immediate operand illegal with absolute jump"));
3729 if (!i386_immediate (op_string
))
3732 else if (is_digit_char (*op_string
)
3733 || is_identifier_char (*op_string
)
3734 || *op_string
== '(')
3736 /* This is a memory reference of some sort. */
3739 /* Start and end of displacement string expression (if found). */
3740 char *displacement_string_start
;
3741 char *displacement_string_end
;
3743 do_memory_reference
:
3744 if ((i
.mem_operands
== 1
3745 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3746 || i
.mem_operands
== 2)
3748 as_bad (_("too many memory references for `%s'"),
3749 current_templates
->start
->name
);
3753 /* Check for base index form. We detect the base index form by
3754 looking for an ')' at the end of the operand, searching
3755 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3757 base_string
= op_string
+ strlen (op_string
);
3760 if (is_space_char (*base_string
))
3763 /* If we only have a displacement, set-up for it to be parsed later. */
3764 displacement_string_start
= op_string
;
3765 displacement_string_end
= base_string
+ 1;
3767 if (*base_string
== ')')
3770 unsigned int parens_balanced
= 1;
3771 /* We've already checked that the number of left & right ()'s are
3772 equal, so this loop will not be infinite. */
3776 if (*base_string
== ')')
3778 if (*base_string
== '(')
3781 while (parens_balanced
);
3783 temp_string
= base_string
;
3785 /* Skip past '(' and whitespace. */
3787 if (is_space_char (*base_string
))
3790 if (*base_string
== ','
3791 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3792 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3794 displacement_string_end
= temp_string
;
3796 i
.types
[this_operand
] |= BaseIndex
;
3800 base_string
= end_op
;
3801 if (is_space_char (*base_string
))
3805 /* There may be an index reg or scale factor here. */
3806 if (*base_string
== ',')
3809 if (is_space_char (*base_string
))
3812 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3813 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3815 base_string
= end_op
;
3816 if (is_space_char (*base_string
))
3818 if (*base_string
== ',')
3821 if (is_space_char (*base_string
))
3824 else if (*base_string
!= ')')
3826 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3831 else if (*base_string
== REGISTER_PREFIX
)
3833 as_bad (_("bad register name `%s'"), base_string
);
3837 /* Check for scale factor. */
3838 if (*base_string
!= ')')
3840 char *end_scale
= i386_scale (base_string
);
3845 base_string
= end_scale
;
3846 if (is_space_char (*base_string
))
3848 if (*base_string
!= ')')
3850 as_bad (_("expecting `)' after scale factor in `%s'"),
3855 else if (!i
.index_reg
)
3857 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3862 else if (*base_string
!= ')')
3864 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3869 else if (*base_string
== REGISTER_PREFIX
)
3871 as_bad (_("bad register name `%s'"), base_string
);
3876 /* If there's an expression beginning the operand, parse it,
3877 assuming displacement_string_start and
3878 displacement_string_end are meaningful. */
3879 if (displacement_string_start
!= displacement_string_end
)
3881 if (!i386_displacement (displacement_string_start
,
3882 displacement_string_end
))
3886 /* Special case for (%dx) while doing input/output op. */
3888 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3890 && i
.log2_scale_factor
== 0
3891 && i
.seg
[i
.mem_operands
] == 0
3892 && (i
.types
[this_operand
] & Disp
) == 0)
3894 i
.types
[this_operand
] = InOutPortReg
;
3898 if (i386_index_check (operand_string
) == 0)
3904 /* It's not a memory operand; argh! */
3905 as_bad (_("invalid char %s beginning operand %d `%s'"),
3906 output_invalid (*op_string
),
3911 return 1; /* Normal return. */
3914 /* md_estimate_size_before_relax()
3916 Called just before relax() for rs_machine_dependent frags. The x86
3917 assembler uses these frags to handle variable size jump
3920 Any symbol that is now undefined will not become defined.
3921 Return the correct fr_subtype in the frag.
3922 Return the initial "guess for variable size of frag" to caller.
3923 The guess is actually the growth beyond the fixed part. Whatever
3924 we do to grow the fixed or variable part contributes to our
3928 md_estimate_size_before_relax (fragP
, segment
)
3929 register fragS
*fragP
;
3930 register segT segment
;
3932 /* We've already got fragP->fr_subtype right; all we have to do is
3933 check for un-relaxable symbols. On an ELF system, we can't relax
3934 an externally visible symbol, because it may be overridden by a
3936 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3938 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3939 || S_IS_WEAK (fragP
->fr_symbol
)
3943 /* Symbol is undefined in this segment, or we need to keep a
3944 reloc so that weak symbols can be overridden. */
3945 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3946 RELOC_ENUM reloc_type
;
3947 unsigned char *opcode
;
3950 if (fragP
->fr_var
!= NO_RELOC
)
3951 reloc_type
= fragP
->fr_var
;
3953 reloc_type
= BFD_RELOC_16_PCREL
;
3955 reloc_type
= BFD_RELOC_32_PCREL
;
3957 old_fr_fix
= fragP
->fr_fix
;
3958 opcode
= (unsigned char *) fragP
->fr_opcode
;
3960 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3963 /* Make jmp (0xeb) a (d)word displacement jump. */
3965 fragP
->fr_fix
+= size
;
3966 fix_new (fragP
, old_fr_fix
, size
,
3968 fragP
->fr_offset
, 1,
3973 if (no_cond_jump_promotion
)
3977 /* Negate the condition, and branch past an
3978 unconditional jump. */
3981 /* Insert an unconditional jump. */
3983 /* We added two extra opcode bytes, and have a two byte
3985 fragP
->fr_fix
+= 2 + 2;
3986 fix_new (fragP
, old_fr_fix
+ 2, 2,
3988 fragP
->fr_offset
, 1,
3995 if (no_cond_jump_promotion
)
3997 /* This changes the byte-displacement jump 0x7N
3998 to the (d)word-displacement jump 0x0f,0x8N. */
3999 opcode
[1] = opcode
[0] + 0x10;
4000 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4001 /* We've added an opcode byte. */
4002 fragP
->fr_fix
+= 1 + size
;
4003 fix_new (fragP
, old_fr_fix
+ 1, size
,
4005 fragP
->fr_offset
, 1,
4010 BAD_CASE (fragP
->fr_subtype
);
4014 return fragP
->fr_fix
- old_fr_fix
;
4016 /* Guess a short jump. */
4020 /* Called after relax() is finished.
4022 In: Address of frag.
4023 fr_type == rs_machine_dependent.
4024 fr_subtype is what the address relaxed to.
4026 Out: Any fixSs and constants are set up.
4027 Caller will turn frag into a ".space 0". */
4029 #ifndef BFD_ASSEMBLER
4031 md_convert_frag (headers
, sec
, fragP
)
4032 object_headers
*headers ATTRIBUTE_UNUSED
;
4033 segT sec ATTRIBUTE_UNUSED
;
4034 register fragS
*fragP
;
4037 md_convert_frag (abfd
, sec
, fragP
)
4038 bfd
*abfd ATTRIBUTE_UNUSED
;
4039 segT sec ATTRIBUTE_UNUSED
;
4040 register fragS
*fragP
;
4043 register unsigned char *opcode
;
4044 unsigned char *where_to_put_displacement
= NULL
;
4045 offsetT target_address
;
4046 offsetT opcode_address
;
4047 unsigned int extension
= 0;
4048 offsetT displacement_from_opcode_start
;
4050 opcode
= (unsigned char *) fragP
->fr_opcode
;
4052 /* Address we want to reach in file space. */
4053 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4054 #ifdef BFD_ASSEMBLER
4055 /* Not needed otherwise? */
4056 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
4059 /* Address opcode resides at in file space. */
4060 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4062 /* Displacement from opcode start to fill into instruction. */
4063 displacement_from_opcode_start
= target_address
- opcode_address
;
4065 if ((fragP
->fr_subtype
& BIG
) == 0)
4067 /* Don't have to change opcode. */
4068 extension
= 1; /* 1 opcode + 1 displacement */
4069 where_to_put_displacement
= &opcode
[1];
4073 if (no_cond_jump_promotion
4074 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4075 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4077 switch (fragP
->fr_subtype
)
4079 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4080 extension
= 4; /* 1 opcode + 4 displacement */
4082 where_to_put_displacement
= &opcode
[1];
4085 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4086 extension
= 2; /* 1 opcode + 2 displacement */
4088 where_to_put_displacement
= &opcode
[1];
4091 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4092 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4093 extension
= 5; /* 2 opcode + 4 displacement */
4094 opcode
[1] = opcode
[0] + 0x10;
4095 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4096 where_to_put_displacement
= &opcode
[2];
4099 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4100 extension
= 3; /* 2 opcode + 2 displacement */
4101 opcode
[1] = opcode
[0] + 0x10;
4102 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4103 where_to_put_displacement
= &opcode
[2];
4106 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4111 where_to_put_displacement
= &opcode
[3];
4115 BAD_CASE (fragP
->fr_subtype
);
4120 /* Now put displacement after opcode. */
4121 md_number_to_chars ((char *) where_to_put_displacement
,
4122 (valueT
) (displacement_from_opcode_start
- extension
),
4123 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4124 fragP
->fr_fix
+= extension
;
4127 /* Size of byte displacement jmp. */
4128 int md_short_jump_size
= 2;
4130 /* Size of dword displacement jmp. */
4131 int md_long_jump_size
= 5;
4133 /* Size of relocation record. */
4134 const int md_reloc_size
= 8;
4137 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4139 addressT from_addr
, to_addr
;
4140 fragS
*frag ATTRIBUTE_UNUSED
;
4141 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4145 offset
= to_addr
- (from_addr
+ 2);
4146 /* Opcode for byte-disp jump. */
4147 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4148 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4152 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4154 addressT from_addr
, to_addr
;
4155 fragS
*frag ATTRIBUTE_UNUSED
;
4156 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4160 offset
= to_addr
- (from_addr
+ 5);
4161 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4162 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4165 /* Apply a fixup (fixS) to segment data, once it has been determined
4166 by our caller that we have all the info we need to fix it up.
4168 On the 386, immediates, displacements, and data pointers are all in
4169 the same (little-endian) format, so we don't need to care about which
4173 md_apply_fix3 (fixP
, valp
, seg
)
4174 /* The fix we're to put in. */
4177 /* Pointer to the value of the bits. */
4180 /* Segment fix is from. */
4181 segT seg ATTRIBUTE_UNUSED
;
4183 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4184 valueT value
= *valp
;
4186 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4189 switch (fixP
->fx_r_type
)
4195 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4198 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4201 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4206 /* This is a hack. There should be a better way to handle this.
4207 This covers for the fact that bfd_install_relocation will
4208 subtract the current location (for partial_inplace, PC relative
4209 relocations); see more below. */
4210 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4211 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4212 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4213 && fixP
->fx_addsy
&& !use_rela_relocations
)
4216 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4218 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4221 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4223 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4224 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4226 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4229 || (symbol_section_p (fixP
->fx_addsy
)
4230 && fseg
!= absolute_section
))
4231 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4232 && ! S_IS_WEAK (fixP
->fx_addsy
)
4233 && S_IS_DEFINED (fixP
->fx_addsy
)
4234 && ! S_IS_COMMON (fixP
->fx_addsy
))
4236 /* Yes, we add the values in twice. This is because
4237 bfd_perform_relocation subtracts them out again. I think
4238 bfd_perform_relocation is broken, but I don't dare change
4240 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4244 #if defined (OBJ_COFF) && defined (TE_PE)
4245 /* For some reason, the PE format does not store a section
4246 address offset for a PC relative symbol. */
4247 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4248 value
+= md_pcrel_from (fixP
);
4252 /* Fix a few things - the dynamic linker expects certain values here,
4253 and we must not dissappoint it. */
4254 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4255 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4257 switch (fixP
->fx_r_type
)
4259 case BFD_RELOC_386_PLT32
:
4260 case BFD_RELOC_X86_64_PLT32
:
4261 /* Make the jump instruction point to the address of the operand. At
4262 runtime we merely add the offset to the actual PLT entry. */
4265 case BFD_RELOC_386_GOTPC
:
4267 /* This is tough to explain. We end up with this one if we have
4268 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4269 * here is to obtain the absolute address of the GOT, and it is strongly
4270 * preferable from a performance point of view to avoid using a runtime
4271 * relocation for this. The actual sequence of instructions often look
4277 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4279 * The call and pop essentially return the absolute address of
4280 * the label .L66 and store it in %ebx. The linker itself will
4281 * ultimately change the first operand of the addl so that %ebx points to
4282 * the GOT, but to keep things simple, the .o file must have this operand
4283 * set so that it generates not the absolute address of .L66, but the
4284 * absolute address of itself. This allows the linker itself simply
4285 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4286 * added in, and the addend of the relocation is stored in the operand
4287 * field for the instruction itself.
4289 * Our job here is to fix the operand so that it would add the correct
4290 * offset so that %ebx would point to itself. The thing that is tricky is
4291 * that .-.L66 will point to the beginning of the instruction, so we need
4292 * to further modify the operand so that it will point to itself.
4293 * There are other cases where you have something like:
4295 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4297 * and here no correction would be required. Internally in the assembler
4298 * we treat operands of this form as not being pcrel since the '.' is
4299 * explicitly mentioned, and I wonder whether it would simplify matters
4300 * to do it this way. Who knows. In earlier versions of the PIC patches,
4301 * the pcrel_adjust field was used to store the correction, but since the
4302 * expression is not pcrel, I felt it would be confusing to do it this
4307 case BFD_RELOC_386_GOT32
:
4308 case BFD_RELOC_X86_64_GOT32
:
4309 value
= 0; /* Fully resolved at runtime. No addend. */
4311 case BFD_RELOC_386_GOTOFF
:
4312 case BFD_RELOC_X86_64_GOTPCREL
:
4315 case BFD_RELOC_VTABLE_INHERIT
:
4316 case BFD_RELOC_VTABLE_ENTRY
:
4323 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4325 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4327 #ifndef BFD_ASSEMBLER
4328 md_number_to_chars (p
, value
, fixP
->fx_size
);
4330 /* Are we finished with this relocation now? */
4331 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4333 else if (use_rela_relocations
)
4335 fixP
->fx_no_overflow
= 1;
4338 md_number_to_chars (p
, value
, fixP
->fx_size
);
4344 #define MAX_LITTLENUMS 6
4346 /* Turn the string pointed to by litP into a floating point constant
4347 of type TYPE, and emit the appropriate bytes. The number of
4348 LITTLENUMS emitted is stored in *SIZEP. An error message is
4349 returned, or NULL on OK. */
4352 md_atof (type
, litP
, sizeP
)
4358 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4359 LITTLENUM_TYPE
*wordP
;
4381 return _("Bad call to md_atof ()");
4383 t
= atof_ieee (input_line_pointer
, type
, words
);
4385 input_line_pointer
= t
;
4387 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4388 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4389 the bigendian 386. */
4390 for (wordP
= words
+ prec
- 1; prec
--;)
4392 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4393 litP
+= sizeof (LITTLENUM_TYPE
);
4398 char output_invalid_buf
[8];
4405 sprintf (output_invalid_buf
, "'%c'", c
);
4407 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4408 return output_invalid_buf
;
4411 /* REG_STRING starts *before* REGISTER_PREFIX. */
4413 static const reg_entry
*
4414 parse_register (reg_string
, end_op
)
4418 char *s
= reg_string
;
4420 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4423 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4424 if (*s
== REGISTER_PREFIX
)
4427 if (is_space_char (*s
))
4431 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4433 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4434 return (const reg_entry
*) NULL
;
4438 /* For naked regs, make sure that we are not dealing with an identifier.
4439 This prevents confusing an identifier like `eax_var' with register
4441 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4442 return (const reg_entry
*) NULL
;
4446 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4448 /* Handle floating point regs, allowing spaces in the (i) part. */
4449 if (r
== i386_regtab
/* %st is first entry of table */)
4451 if (is_space_char (*s
))
4456 if (is_space_char (*s
))
4458 if (*s
>= '0' && *s
<= '7')
4460 r
= &i386_float_regtab
[*s
- '0'];
4462 if (is_space_char (*s
))
4470 /* We have "%st(" then garbage. */
4471 return (const reg_entry
*) NULL
;
4478 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4479 const char *md_shortopts
= "kVQ:sq";
4481 const char *md_shortopts
= "q";
4484 struct option md_longopts
[] = {
4485 #define OPTION_32 (OPTION_MD_BASE + 0)
4486 {"32", no_argument
, NULL
, OPTION_32
},
4487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4488 #define OPTION_64 (OPTION_MD_BASE + 1)
4489 {"64", no_argument
, NULL
, OPTION_64
},
4491 {NULL
, no_argument
, NULL
, 0}
4493 size_t md_longopts_size
= sizeof (md_longopts
);
4496 md_parse_option (c
, arg
)
4498 char *arg ATTRIBUTE_UNUSED
;
4506 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4507 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4508 should be emitted or not. FIXME: Not implemented. */
4512 /* -V: SVR4 argument to print version ID. */
4514 print_version_id ();
4517 /* -k: Ignore for FreeBSD compatibility. */
4522 /* -s: On i386 Solaris, this tells the native assembler to use
4523 .stab instead of .stab.excl. We always use .stab anyhow. */
4528 const char **list
, **l
;
4530 list
= bfd_target_list ();
4531 for (l
= list
; *l
!= NULL
; l
++)
4532 if (strcmp (*l
, "elf64-x86-64") == 0)
4534 default_arch
= "x86_64";
4538 as_fatal (_("No compiled in support for x86_64"));
4545 default_arch
= "i386";
4555 md_show_usage (stream
)
4558 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4559 fprintf (stream
, _("\
4561 -V print assembler version number\n\
4563 -q quieten some warnings\n\
4566 fprintf (stream
, _("\
4567 -q quieten some warnings\n"));
4571 #ifdef BFD_ASSEMBLER
4572 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4573 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4575 /* Pick the target format to use. */
4578 i386_target_format ()
4580 if (!strcmp (default_arch
, "x86_64"))
4581 set_code_flag (CODE_64BIT
);
4582 else if (!strcmp (default_arch
, "i386"))
4583 set_code_flag (CODE_32BIT
);
4585 as_fatal (_("Unknown architecture"));
4586 switch (OUTPUT_FLAVOR
)
4588 #ifdef OBJ_MAYBE_AOUT
4589 case bfd_target_aout_flavour
:
4590 return AOUT_TARGET_FORMAT
;
4592 #ifdef OBJ_MAYBE_COFF
4593 case bfd_target_coff_flavour
:
4596 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4597 case bfd_target_elf_flavour
:
4599 if (flag_code
== CODE_64BIT
)
4600 use_rela_relocations
= 1;
4601 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4610 #endif /* OBJ_MAYBE_ more than one */
4611 #endif /* BFD_ASSEMBLER */
4614 md_undefined_symbol (name
)
4617 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4618 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4619 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4620 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4624 if (symbol_find (name
))
4625 as_bad (_("GOT already in symbol table"));
4626 GOT_symbol
= symbol_new (name
, undefined_section
,
4627 (valueT
) 0, &zero_address_frag
);
4634 /* Round up a section size to the appropriate boundary. */
4637 md_section_align (segment
, size
)
4638 segT segment ATTRIBUTE_UNUSED
;
4641 #ifdef BFD_ASSEMBLER
4642 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4643 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4645 /* For a.out, force the section size to be aligned. If we don't do
4646 this, BFD will align it for us, but it will not write out the
4647 final bytes of the section. This may be a bug in BFD, but it is
4648 easier to fix it here since that is how the other a.out targets
4652 align
= bfd_get_section_alignment (stdoutput
, segment
);
4653 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4661 /* On the i386, PC-relative offsets are relative to the start of the
4662 next instruction. That is, the address of the offset, plus its
4663 size, since the offset is always the last part of the insn. */
4666 md_pcrel_from (fixP
)
4669 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4676 int ignore ATTRIBUTE_UNUSED
;
4680 temp
= get_absolute_expression ();
4681 subseg_set (bss_section
, (subsegT
) temp
);
4682 demand_empty_rest_of_line ();
4687 #ifdef BFD_ASSEMBLER
4690 i386_validate_fix (fixp
)
4693 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4695 /* GOTOFF relocation are nonsense in 64bit mode. */
4696 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4698 if (flag_code
!= CODE_64BIT
)
4700 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4704 if (flag_code
== CODE_64BIT
)
4706 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4713 tc_gen_reloc (section
, fixp
)
4714 asection
*section ATTRIBUTE_UNUSED
;
4718 bfd_reloc_code_real_type code
;
4720 switch (fixp
->fx_r_type
)
4722 case BFD_RELOC_X86_64_PLT32
:
4723 case BFD_RELOC_X86_64_GOT32
:
4724 case BFD_RELOC_X86_64_GOTPCREL
:
4725 case BFD_RELOC_386_PLT32
:
4726 case BFD_RELOC_386_GOT32
:
4727 case BFD_RELOC_386_GOTOFF
:
4728 case BFD_RELOC_386_GOTPC
:
4729 case BFD_RELOC_X86_64_32S
:
4731 case BFD_RELOC_VTABLE_ENTRY
:
4732 case BFD_RELOC_VTABLE_INHERIT
:
4733 code
= fixp
->fx_r_type
;
4738 switch (fixp
->fx_size
)
4741 as_bad (_("can not do %d byte pc-relative relocation"),
4743 code
= BFD_RELOC_32_PCREL
;
4745 case 1: code
= BFD_RELOC_8_PCREL
; break;
4746 case 2: code
= BFD_RELOC_16_PCREL
; break;
4747 case 4: code
= BFD_RELOC_32_PCREL
; break;
4752 switch (fixp
->fx_size
)
4755 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4756 code
= BFD_RELOC_32
;
4758 case 1: code
= BFD_RELOC_8
; break;
4759 case 2: code
= BFD_RELOC_16
; break;
4760 case 4: code
= BFD_RELOC_32
; break;
4761 case 8: code
= BFD_RELOC_64
; break;
4767 if (code
== BFD_RELOC_32
4769 && fixp
->fx_addsy
== GOT_symbol
)
4771 /* We don't support GOTPC on 64bit targets. */
4772 if (flag_code
== CODE_64BIT
)
4774 code
= BFD_RELOC_386_GOTPC
;
4777 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4778 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4779 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4781 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4782 if (!use_rela_relocations
)
4784 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4785 vtable entry to be used in the relocation's section offset. */
4786 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4787 rel
->address
= fixp
->fx_offset
;
4790 rel
->addend
= fixp
->fx_addnumber
;
4794 /* Use the rela in 64bit mode. */
4797 rel
->addend
= fixp
->fx_offset
;
4799 rel
->addend
-= fixp
->fx_size
;
4802 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4803 if (rel
->howto
== NULL
)
4805 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4806 _("cannot represent relocation type %s"),
4807 bfd_get_reloc_code_name (code
));
4808 /* Set howto to a garbage value so that we can keep going. */
4809 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4810 assert (rel
->howto
!= NULL
);
4816 #else /* ! BFD_ASSEMBLER */
4818 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4820 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4823 relax_addressT segment_address_in_file
;
4825 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4826 Out: GNU LD relocation length code: 0, 1, or 2. */
4828 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4831 know (fixP
->fx_addsy
!= NULL
);
4833 md_number_to_chars (where
,
4834 (valueT
) (fixP
->fx_frag
->fr_address
4835 + fixP
->fx_where
- segment_address_in_file
),
4838 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4839 ? S_GET_TYPE (fixP
->fx_addsy
)
4840 : fixP
->fx_addsy
->sy_number
);
4842 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4843 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4844 where
[4] = r_symbolnum
& 0x0ff;
4845 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4846 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4847 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4850 #endif /* OBJ_AOUT or OBJ_BOUT. */
4852 #if defined (I386COFF)
4855 tc_coff_fix2rtype (fixP
)
4858 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4861 return (fixP
->fx_pcrel
?
4862 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4863 fixP
->fx_size
== 2 ? R_PCRWORD
:
4865 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4866 fixP
->fx_size
== 2 ? R_RELWORD
:
4871 tc_coff_sizemachdep (frag
)
4875 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4880 #endif /* I386COFF */
4882 #endif /* ! BFD_ASSEMBLER */
4884 /* Parse operands using Intel syntax. This implements a recursive descent
4885 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4888 FIXME: We do not recognize the full operand grammar defined in the MASM
4889 documentation. In particular, all the structure/union and
4890 high-level macro operands are missing.
4892 Uppercase words are terminals, lower case words are non-terminals.
4893 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4894 bars '|' denote choices. Most grammar productions are implemented in
4895 functions called 'intel_<production>'.
4897 Initial production is 'expr'.
4903 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4905 constant digits [[ radixOverride ]]
4907 dataType BYTE | WORD | DWORD | QWORD | XWORD
4940 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4941 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4943 hexdigit a | b | c | d | e | f
4944 | A | B | C | D | E | F
4954 register specialRegister
4958 segmentRegister CS | DS | ES | FS | GS | SS
4960 specialRegister CR0 | CR2 | CR3
4961 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4962 | TR3 | TR4 | TR5 | TR6 | TR7
4964 We simplify the grammar in obvious places (e.g., register parsing is
4965 done by calling parse_register) and eliminate immediate left recursion
4966 to implement a recursive-descent parser.
5006 /* Parsing structure for the intel syntax parser. Used to implement the
5007 semantic actions for the operand grammar. */
5008 struct intel_parser_s
5010 char *op_string
; /* The string being parsed. */
5011 int got_a_float
; /* Whether the operand is a float. */
5012 int op_modifier
; /* Operand modifier. */
5013 int is_mem
; /* 1 if operand is memory reference. */
5014 const reg_entry
*reg
; /* Last register reference found. */
5015 char *disp
; /* Displacement string being built. */
5018 static struct intel_parser_s intel_parser
;
5020 /* Token structure for parsing intel syntax. */
5023 int code
; /* Token code. */
5024 const reg_entry
*reg
; /* Register entry for register tokens. */
5025 char *str
; /* String representation. */
5028 static struct intel_token cur_token
, prev_token
;
5030 /* Token codes for the intel parser. Since T_SHORT is already used
5031 by COFF, undefine it first to prevent a warning. */
5046 /* Prototypes for intel parser functions. */
5047 static int intel_match_token
PARAMS ((int code
));
5048 static void intel_get_token
PARAMS ((void));
5049 static void intel_putback_token
PARAMS ((void));
5050 static int intel_expr
PARAMS ((void));
5051 static int intel_e05
PARAMS ((void));
5052 static int intel_e05_1
PARAMS ((void));
5053 static int intel_e06
PARAMS ((void));
5054 static int intel_e06_1
PARAMS ((void));
5055 static int intel_e09
PARAMS ((void));
5056 static int intel_e09_1
PARAMS ((void));
5057 static int intel_e10
PARAMS ((void));
5058 static int intel_e10_1
PARAMS ((void));
5059 static int intel_e11
PARAMS ((void));
5062 i386_intel_operand (operand_string
, got_a_float
)
5063 char *operand_string
;
5069 /* Initialize token holders. */
5070 cur_token
.code
= prev_token
.code
= T_NIL
;
5071 cur_token
.reg
= prev_token
.reg
= NULL
;
5072 cur_token
.str
= prev_token
.str
= NULL
;
5074 /* Initialize parser structure. */
5075 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5078 strcpy (intel_parser
.op_string
, operand_string
);
5079 intel_parser
.got_a_float
= got_a_float
;
5080 intel_parser
.op_modifier
= -1;
5081 intel_parser
.is_mem
= 0;
5082 intel_parser
.reg
= NULL
;
5083 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5084 if (intel_parser
.disp
== NULL
)
5086 intel_parser
.disp
[0] = '\0';
5088 /* Read the first token and start the parser. */
5090 ret
= intel_expr ();
5094 /* If we found a memory reference, hand it over to i386_displacement
5095 to fill in the rest of the operand fields. */
5096 if (intel_parser
.is_mem
)
5098 if ((i
.mem_operands
== 1
5099 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5100 || i
.mem_operands
== 2)
5102 as_bad (_("too many memory references for '%s'"),
5103 current_templates
->start
->name
);
5108 char *s
= intel_parser
.disp
;
5111 /* Add the displacement expression. */
5113 ret
= i386_displacement (s
, s
+ strlen (s
))
5114 && i386_index_check (s
);
5118 /* Constant and OFFSET expressions are handled by i386_immediate. */
5119 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5120 || intel_parser
.reg
== NULL
)
5121 ret
= i386_immediate (intel_parser
.disp
);
5125 free (intel_parser
.disp
);
5135 /* expr SHORT e05 */
5136 if (cur_token
.code
== T_SHORT
)
5138 intel_parser
.op_modifier
= SHORT
;
5139 intel_match_token (T_SHORT
);
5141 return (intel_e05 ());
5146 return intel_e05 ();
5156 return (intel_e06 () && intel_e05_1 ());
5162 /* e05' addOp e06 e05' */
5163 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5165 strcat (intel_parser
.disp
, cur_token
.str
);
5166 intel_match_token (cur_token
.code
);
5168 return (intel_e06 () && intel_e05_1 ());
5183 return (intel_e09 () && intel_e06_1 ());
5189 /* e06' mulOp e09 e06' */
5190 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5192 strcat (intel_parser
.disp
, cur_token
.str
);
5193 intel_match_token (cur_token
.code
);
5195 return (intel_e09 () && intel_e06_1 ());
5203 /* e09 OFFSET e10 e09'
5212 /* e09 OFFSET e10 e09' */
5213 if (cur_token
.code
== T_OFFSET
)
5215 intel_parser
.is_mem
= 0;
5216 intel_parser
.op_modifier
= OFFSET_FLAT
;
5217 intel_match_token (T_OFFSET
);
5219 return (intel_e10 () && intel_e09_1 ());
5224 return (intel_e10 () && intel_e09_1 ());
5230 /* e09' PTR e10 e09' */
5231 if (cur_token
.code
== T_PTR
)
5233 if (prev_token
.code
== T_BYTE
)
5234 i
.suffix
= BYTE_MNEM_SUFFIX
;
5236 else if (prev_token
.code
== T_WORD
)
5238 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5239 i
.suffix
= SHORT_MNEM_SUFFIX
;
5241 i
.suffix
= WORD_MNEM_SUFFIX
;
5244 else if (prev_token
.code
== T_DWORD
)
5246 if (intel_parser
.got_a_float
== 1) /* "f..." */
5247 i
.suffix
= SHORT_MNEM_SUFFIX
;
5249 i
.suffix
= LONG_MNEM_SUFFIX
;
5252 else if (prev_token
.code
== T_QWORD
)
5254 if (intel_parser
.got_a_float
== 1) /* "f..." */
5255 i
.suffix
= LONG_MNEM_SUFFIX
;
5257 i
.suffix
= QWORD_MNEM_SUFFIX
;
5260 else if (prev_token
.code
== T_XWORD
)
5261 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5265 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5269 intel_match_token (T_PTR
);
5271 return (intel_e10 () && intel_e09_1 ());
5274 /* e09 : e10 e09' */
5275 else if (cur_token
.code
== ':')
5277 /* Mark as a memory operand only if it's not already known to be an
5278 offset expression. */
5279 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5280 intel_parser
.is_mem
= 1;
5282 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5297 return (intel_e11 () && intel_e10_1 ());
5303 /* e10' [ expr ] e10' */
5304 if (cur_token
.code
== '[')
5306 intel_match_token ('[');
5308 /* Mark as a memory operand only if it's not already known to be an
5309 offset expression. If it's an offset expression, we need to keep
5311 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5312 intel_parser
.is_mem
= 1;
5314 strcat (intel_parser
.disp
, "[");
5316 /* Add a '+' to the displacement string if necessary. */
5317 if (*intel_parser
.disp
!= '\0'
5318 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5319 strcat (intel_parser
.disp
, "+");
5321 if (intel_expr () && intel_match_token (']'))
5323 /* Preserve brackets when the operand is an offset expression. */
5324 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5325 strcat (intel_parser
.disp
, "]");
5327 return intel_e10_1 ();
5354 if (cur_token
.code
== '(')
5356 intel_match_token ('(');
5357 strcat (intel_parser
.disp
, "(");
5359 if (intel_expr () && intel_match_token (')'))
5361 strcat (intel_parser
.disp
, ")");
5369 else if (cur_token
.code
== '[')
5371 intel_match_token ('[');
5373 /* Mark as a memory operand only if it's not already known to be an
5374 offset expression. If it's an offset expression, we need to keep
5376 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5377 intel_parser
.is_mem
= 1;
5379 strcat (intel_parser
.disp
, "[");
5381 /* Operands for jump/call inside brackets denote absolute addresses. */
5382 if (current_templates
->start
->opcode_modifier
& Jump
5383 || current_templates
->start
->opcode_modifier
& JumpDword
5384 || current_templates
->start
->opcode_modifier
& JumpByte
5385 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5386 i
.types
[this_operand
] |= JumpAbsolute
;
5388 /* Add a '+' to the displacement string if necessary. */
5389 if (*intel_parser
.disp
!= '\0'
5390 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5391 strcat (intel_parser
.disp
, "+");
5393 if (intel_expr () && intel_match_token (']'))
5395 /* Preserve brackets when the operand is an offset expression. */
5396 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5397 strcat (intel_parser
.disp
, "]");
5410 else if (cur_token
.code
== T_BYTE
5411 || cur_token
.code
== T_WORD
5412 || cur_token
.code
== T_DWORD
5413 || cur_token
.code
== T_QWORD
5414 || cur_token
.code
== T_XWORD
)
5416 intel_match_token (cur_token
.code
);
5423 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5425 strcat (intel_parser
.disp
, cur_token
.str
);
5426 intel_match_token (cur_token
.code
);
5428 /* Mark as a memory operand only if it's not already known to be an
5429 offset expression. */
5430 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5431 intel_parser
.is_mem
= 1;
5437 else if (cur_token
.code
== T_REG
)
5439 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5441 intel_match_token (T_REG
);
5443 /* Check for segment change. */
5444 if (cur_token
.code
== ':')
5446 if (reg
->reg_type
& (SReg2
| SReg3
))
5448 switch (reg
->reg_num
)
5451 i
.seg
[i
.mem_operands
] = &es
;
5454 i
.seg
[i
.mem_operands
] = &cs
;
5457 i
.seg
[i
.mem_operands
] = &ss
;
5460 i
.seg
[i
.mem_operands
] = &ds
;
5463 i
.seg
[i
.mem_operands
] = &fs
;
5466 i
.seg
[i
.mem_operands
] = &gs
;
5472 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5477 /* Not a segment register. Check for register scaling. */
5478 else if (cur_token
.code
== '*')
5480 if (!intel_parser
.is_mem
)
5482 as_bad (_("Register scaling only allowed in memory operands."));
5486 /* What follows must be a valid scale. */
5487 if (intel_match_token ('*')
5488 && strchr ("01248", *cur_token
.str
))
5491 i
.types
[this_operand
] |= BaseIndex
;
5493 /* Set the scale after setting the register (otherwise,
5494 i386_scale will complain) */
5495 i386_scale (cur_token
.str
);
5496 intel_match_token (T_CONST
);
5500 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5506 /* No scaling. If this is a memory operand, the register is either a
5507 base register (first occurrence) or an index register (second
5509 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5511 if (i
.base_reg
&& i
.index_reg
)
5513 as_bad (_("Too many register references in memory operand.\n"));
5517 if (i
.base_reg
== NULL
)
5522 i
.types
[this_operand
] |= BaseIndex
;
5525 /* Offset modifier. Add the register to the displacement string to be
5526 parsed as an immediate expression after we're done. */
5527 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5528 strcat (intel_parser
.disp
, reg
->reg_name
);
5530 /* It's neither base nor index nor offset. */
5533 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5534 i
.op
[this_operand
].regs
= reg
;
5538 /* Since registers are not part of the displacement string (except
5539 when we're parsing offset operands), we may need to remove any
5540 preceding '+' from the displacement string. */
5541 if (*intel_parser
.disp
!= '\0'
5542 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5544 char *s
= intel_parser
.disp
;
5545 s
+= strlen (s
) - 1;
5554 else if (cur_token
.code
== T_ID
)
5556 /* Add the identifier to the displacement string. */
5557 strcat (intel_parser
.disp
, cur_token
.str
);
5558 intel_match_token (T_ID
);
5560 /* The identifier represents a memory reference only if it's not
5561 preceded by an offset modifier. */
5562 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5563 intel_parser
.is_mem
= 1;
5569 else if (cur_token
.code
== T_CONST
5570 || cur_token
.code
== '-'
5571 || cur_token
.code
== '+')
5575 /* Allow constants that start with `+' or `-'. */
5576 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5578 strcat (intel_parser
.disp
, cur_token
.str
);
5579 intel_match_token (cur_token
.code
);
5580 if (cur_token
.code
!= T_CONST
)
5582 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5588 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5589 if (save_str
== NULL
)
5591 strcpy (save_str
, cur_token
.str
);
5593 /* Get the next token to check for register scaling. */
5594 intel_match_token (cur_token
.code
);
5596 /* Check if this constant is a scaling factor for an index register. */
5597 if (cur_token
.code
== '*')
5599 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5601 if (!intel_parser
.is_mem
)
5603 as_bad (_("Register scaling only allowed in memory operands."));
5607 /* The constant is followed by `* reg', so it must be
5609 if (strchr ("01248", *save_str
))
5611 i
.index_reg
= cur_token
.reg
;
5612 i
.types
[this_operand
] |= BaseIndex
;
5614 /* Set the scale after setting the register (otherwise,
5615 i386_scale will complain) */
5616 i386_scale (save_str
);
5617 intel_match_token (T_REG
);
5619 /* Since registers are not part of the displacement
5620 string, we may need to remove any preceding '+' from
5621 the displacement string. */
5622 if (*intel_parser
.disp
!= '\0')
5624 char *s
= intel_parser
.disp
;
5625 s
+= strlen (s
) - 1;
5638 /* The constant was not used for register scaling. Since we have
5639 already consumed the token following `*' we now need to put it
5640 back in the stream. */
5642 intel_putback_token ();
5645 /* Add the constant to the displacement string. */
5646 strcat (intel_parser
.disp
, save_str
);
5652 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5656 /* Match the given token against cur_token. If they match, read the next
5657 token from the operand string. */
5659 intel_match_token (code
)
5662 if (cur_token
.code
== code
)
5669 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5674 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5679 const reg_entry
*reg
;
5680 struct intel_token new_token
;
5682 new_token
.code
= T_NIL
;
5683 new_token
.reg
= NULL
;
5684 new_token
.str
= NULL
;
5686 /* Free the memory allocated to the previous token and move
5687 cur_token to prev_token. */
5689 free (prev_token
.str
);
5691 prev_token
= cur_token
;
5693 /* Skip whitespace. */
5694 while (is_space_char (*intel_parser
.op_string
))
5695 intel_parser
.op_string
++;
5697 /* Return an empty token if we find nothing else on the line. */
5698 if (*intel_parser
.op_string
== '\0')
5700 cur_token
= new_token
;
5704 /* The new token cannot be larger than the remainder of the operand
5706 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5707 if (new_token
.str
== NULL
)
5709 new_token
.str
[0] = '\0';
5711 if (strchr ("0123456789", *intel_parser
.op_string
))
5713 char *p
= new_token
.str
;
5714 char *q
= intel_parser
.op_string
;
5715 new_token
.code
= T_CONST
;
5717 /* Allow any kind of identifier char to encompass floating point and
5718 hexadecimal numbers. */
5719 while (is_identifier_char (*q
))
5723 /* Recognize special symbol names [0-9][bf]. */
5724 if (strlen (intel_parser
.op_string
) == 2
5725 && (intel_parser
.op_string
[1] == 'b'
5726 || intel_parser
.op_string
[1] == 'f'))
5727 new_token
.code
= T_ID
;
5730 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5732 new_token
.code
= *intel_parser
.op_string
;
5733 new_token
.str
[0] = *intel_parser
.op_string
;
5734 new_token
.str
[1] = '\0';
5737 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5738 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5740 new_token
.code
= T_REG
;
5741 new_token
.reg
= reg
;
5743 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5745 new_token
.str
[0] = REGISTER_PREFIX
;
5746 new_token
.str
[1] = '\0';
5749 strcat (new_token
.str
, reg
->reg_name
);
5752 else if (is_identifier_char (*intel_parser
.op_string
))
5754 char *p
= new_token
.str
;
5755 char *q
= intel_parser
.op_string
;
5757 /* A '.' or '$' followed by an identifier char is an identifier.
5758 Otherwise, it's operator '.' followed by an expression. */
5759 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5761 new_token
.code
= *q
;
5762 new_token
.str
[0] = *q
;
5763 new_token
.str
[1] = '\0';
5767 while (is_identifier_char (*q
) || *q
== '@')
5771 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5772 new_token
.code
= T_BYTE
;
5774 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5775 new_token
.code
= T_WORD
;
5777 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5778 new_token
.code
= T_DWORD
;
5780 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5781 new_token
.code
= T_QWORD
;
5783 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5784 new_token
.code
= T_XWORD
;
5786 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5787 new_token
.code
= T_PTR
;
5789 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5790 new_token
.code
= T_SHORT
;
5792 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5794 new_token
.code
= T_OFFSET
;
5796 /* ??? This is not mentioned in the MASM grammar but gcc
5797 makes use of it with -mintel-syntax. OFFSET may be
5798 followed by FLAT: */
5799 if (strncasecmp (q
, " FLAT:", 6) == 0)
5800 strcat (new_token
.str
, " FLAT:");
5803 /* ??? This is not mentioned in the MASM grammar. */
5804 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5805 new_token
.code
= T_OFFSET
;
5808 new_token
.code
= T_ID
;
5813 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5815 intel_parser
.op_string
+= strlen (new_token
.str
);
5816 cur_token
= new_token
;
5819 /* Put cur_token back into the token stream and make cur_token point to
5822 intel_putback_token ()
5824 intel_parser
.op_string
-= strlen (cur_token
.str
);
5825 free (cur_token
.str
);
5826 cur_token
= prev_token
;
5828 /* Forget prev_token. */
5829 prev_token
.code
= T_NIL
;
5830 prev_token
.reg
= NULL
;
5831 prev_token
.str
= NULL
;