1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_GENERIC64
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".movbe", PROCESSOR_UNKNOWN
,
646 { ".ept", PROCESSOR_UNKNOWN
,
648 { ".clflush", PROCESSOR_UNKNOWN
,
650 { ".syscall", PROCESSOR_UNKNOWN
,
652 { ".rdtscp", PROCESSOR_UNKNOWN
,
654 { ".3dnow", PROCESSOR_UNKNOWN
,
656 { ".3dnowa", PROCESSOR_UNKNOWN
,
658 { ".padlock", PROCESSOR_UNKNOWN
,
660 { ".pacifica", PROCESSOR_UNKNOWN
,
662 { ".svme", PROCESSOR_UNKNOWN
,
664 { ".sse4a", PROCESSOR_UNKNOWN
,
666 { ".abm", PROCESSOR_UNKNOWN
,
671 /* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
675 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
682 && *input_line_pointer
== ',')
684 align
= parse_align (needs_align
- 1);
686 if (align
== (addressT
) -1)
701 bss_alloc (symbolP
, size
, align
);
706 pe_lcomm (int needs_align
)
708 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
712 const pseudo_typeS md_pseudo_table
[] =
714 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes
, 0},
717 {"align", s_align_ptwo
, 0},
719 {"arch", set_cpu_arch
, 0},
723 {"lcomm", pe_lcomm
, 1},
725 {"ffloat", float_cons
, 'f'},
726 {"dfloat", float_cons
, 'd'},
727 {"tfloat", float_cons
, 'x'},
729 {"slong", signed_cons
, 4},
730 {"noopt", s_ignore
, 0},
731 {"optim", s_ignore
, 0},
732 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
733 {"code16", set_code_flag
, CODE_16BIT
},
734 {"code32", set_code_flag
, CODE_32BIT
},
735 {"code64", set_code_flag
, CODE_64BIT
},
736 {"intel_syntax", set_intel_syntax
, 1},
737 {"att_syntax", set_intel_syntax
, 0},
738 {"intel_mnemonic", set_intel_mnemonic
, 1},
739 {"att_mnemonic", set_intel_mnemonic
, 0},
740 {"allow_index_reg", set_allow_index_reg
, 1},
741 {"disallow_index_reg", set_allow_index_reg
, 0},
742 {"sse_check", set_sse_check
, 0},
743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common
, 0},
746 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
747 {"loc", dwarf2_directive_loc
, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
751 {"secrel32", pe_directive_secrel
, 0},
756 /* For interface with expression (). */
757 extern char *input_line_pointer
;
759 /* Hash table for instruction mnemonic lookup. */
760 static struct hash_control
*op_hash
;
762 /* Hash table for register lookup. */
763 static struct hash_control
*reg_hash
;
766 i386_align_code (fragS
*fragP
, int count
)
768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
771 static const char f32_1
[] =
773 static const char f32_2
[] =
774 {0x66,0x90}; /* xchg %ax,%ax */
775 static const char f32_3
[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4
[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5
[] =
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7
[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8
[] =
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9
[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10
[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11
[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14
[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f16_3
[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
809 static const char f16_4
[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5
[] =
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6
[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7
[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8
[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char jump_31
[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
828 static const char *const f32_patt
[] = {
829 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
830 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
832 static const char *const f16_patt
[] = {
833 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
836 static const char alt_3
[] =
838 /* nopl 0(%[re]ax) */
839 static const char alt_4
[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5
[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6
[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7
[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8
[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9
[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10
[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14
[] =
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15
[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11
[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12
[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
916 static const char alt_short_13
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 static const char alt_short_14
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt
[] = {
930 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
931 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
932 alt_short_14
, alt_short_15
934 static const char *const alt_long_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
937 alt_long_14
, alt_long_15
940 /* Only align for at least a positive non-zero boundary. */
941 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
962 if (flag_code
== CODE_16BIT
)
966 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
968 /* Adjust jump offset. */
969 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
972 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 f16_patt
[count
- 1], count
);
977 const char *const *patt
= NULL
;
979 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune
)
984 case PROCESSOR_UNKNOWN
:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
987 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
988 patt
= alt_long_patt
;
992 case PROCESSOR_PENTIUMPRO
:
993 case PROCESSOR_PENTIUM4
:
994 case PROCESSOR_NOCONA
:
996 case PROCESSOR_CORE2
:
997 case PROCESSOR_COREI7
:
998 case PROCESSOR_GENERIC64
:
999 patt
= alt_long_patt
;
1002 case PROCESSOR_ATHLON
:
1004 case PROCESSOR_AMDFAM10
:
1005 patt
= alt_short_patt
;
1007 case PROCESSOR_I386
:
1008 case PROCESSOR_I486
:
1009 case PROCESSOR_PENTIUM
:
1010 case PROCESSOR_GENERIC32
:
1017 switch (fragP
->tc_frag_data
.tune
)
1019 case PROCESSOR_UNKNOWN
:
1020 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1021 PROCESSOR_UNKNOWN. */
1025 case PROCESSOR_I386
:
1026 case PROCESSOR_I486
:
1027 case PROCESSOR_PENTIUM
:
1029 case PROCESSOR_ATHLON
:
1031 case PROCESSOR_AMDFAM10
:
1032 case PROCESSOR_GENERIC32
:
1033 /* We use cpu_arch_isa_flags to check if we CAN optimize
1035 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1036 patt
= alt_short_patt
;
1040 case PROCESSOR_PENTIUMPRO
:
1041 case PROCESSOR_PENTIUM4
:
1042 case PROCESSOR_NOCONA
:
1043 case PROCESSOR_CORE
:
1044 case PROCESSOR_CORE2
:
1045 case PROCESSOR_COREI7
:
1046 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1047 patt
= alt_long_patt
;
1051 case PROCESSOR_GENERIC64
:
1052 patt
= alt_long_patt
;
1057 if (patt
== f32_patt
)
1059 /* If the padding is less than 15 bytes, we use the normal
1060 ones. Otherwise, we use a jump instruction and adjust
1064 /* For 64bit, the limit is 3 bytes. */
1065 if (flag_code
== CODE_64BIT
1066 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1071 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1072 patt
[count
- 1], count
);
1075 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1077 /* Adjust jump offset. */
1078 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1083 /* Maximum length of an instruction is 15 byte. If the
1084 padding is greater than 15 bytes and we don't use jump,
1085 we have to break it into smaller pieces. */
1086 int padding
= count
;
1087 while (padding
> 15)
1090 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1095 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1096 patt
[padding
- 1], padding
);
1099 fragP
->fr_var
= count
;
1103 operand_type_all_zero (const union i386_operand_type
*x
)
1105 switch (ARRAY_SIZE(x
->array
))
1114 return !x
->array
[0];
1121 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1123 switch (ARRAY_SIZE(x
->array
))
1138 operand_type_equal (const union i386_operand_type
*x
,
1139 const union i386_operand_type
*y
)
1141 switch (ARRAY_SIZE(x
->array
))
1144 if (x
->array
[2] != y
->array
[2])
1147 if (x
->array
[1] != y
->array
[1])
1150 return x
->array
[0] == y
->array
[0];
1158 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1160 switch (ARRAY_SIZE(x
->array
))
1169 return !x
->array
[0];
1176 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1178 switch (ARRAY_SIZE(x
->array
))
1193 cpu_flags_equal (const union i386_cpu_flags
*x
,
1194 const union i386_cpu_flags
*y
)
1196 switch (ARRAY_SIZE(x
->array
))
1199 if (x
->array
[2] != y
->array
[2])
1202 if (x
->array
[1] != y
->array
[1])
1205 return x
->array
[0] == y
->array
[0];
1213 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1215 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1216 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1219 static INLINE i386_cpu_flags
1220 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1222 switch (ARRAY_SIZE (x
.array
))
1225 x
.array
[2] &= y
.array
[2];
1227 x
.array
[1] &= y
.array
[1];
1229 x
.array
[0] &= y
.array
[0];
1237 static INLINE i386_cpu_flags
1238 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1240 switch (ARRAY_SIZE (x
.array
))
1243 x
.array
[2] |= y
.array
[2];
1245 x
.array
[1] |= y
.array
[1];
1247 x
.array
[0] |= y
.array
[0];
1255 static INLINE i386_cpu_flags
1256 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1258 switch (ARRAY_SIZE (x
.array
))
1261 x
.array
[2] &= ~y
.array
[2];
1263 x
.array
[1] &= ~y
.array
[1];
1265 x
.array
[0] &= ~y
.array
[0];
1273 #define CPU_FLAGS_ARCH_MATCH 0x1
1274 #define CPU_FLAGS_64BIT_MATCH 0x2
1275 #define CPU_FLAGS_AES_MATCH 0x4
1276 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1277 #define CPU_FLAGS_AVX_MATCH 0x10
1279 #define CPU_FLAGS_32BIT_MATCH \
1280 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1281 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1282 #define CPU_FLAGS_PERFECT_MATCH \
1283 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1285 /* Return CPU flags match bits. */
1288 cpu_flags_match (const template *t
)
1290 i386_cpu_flags x
= t
->cpu_flags
;
1291 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1293 x
.bitfield
.cpu64
= 0;
1294 x
.bitfield
.cpuno64
= 0;
1296 if (cpu_flags_all_zero (&x
))
1298 /* This instruction is available on all archs. */
1299 match
|= CPU_FLAGS_32BIT_MATCH
;
1303 /* This instruction is available only on some archs. */
1304 i386_cpu_flags cpu
= cpu_arch_flags
;
1306 cpu
.bitfield
.cpu64
= 0;
1307 cpu
.bitfield
.cpuno64
= 0;
1308 cpu
= cpu_flags_and (x
, cpu
);
1309 if (!cpu_flags_all_zero (&cpu
))
1311 if (x
.bitfield
.cpuavx
)
1313 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1314 if (cpu
.bitfield
.cpuavx
)
1316 /* Check SSE2AVX. */
1317 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1319 match
|= (CPU_FLAGS_ARCH_MATCH
1320 | CPU_FLAGS_AVX_MATCH
);
1322 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1323 match
|= CPU_FLAGS_AES_MATCH
;
1325 if (!x
.bitfield
.cpupclmul
1326 || cpu
.bitfield
.cpupclmul
)
1327 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1331 match
|= CPU_FLAGS_ARCH_MATCH
;
1334 match
|= CPU_FLAGS_32BIT_MATCH
;
1340 static INLINE i386_operand_type
1341 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1343 switch (ARRAY_SIZE (x
.array
))
1346 x
.array
[2] &= y
.array
[2];
1348 x
.array
[1] &= y
.array
[1];
1350 x
.array
[0] &= y
.array
[0];
1358 static INLINE i386_operand_type
1359 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1361 switch (ARRAY_SIZE (x
.array
))
1364 x
.array
[2] |= y
.array
[2];
1366 x
.array
[1] |= y
.array
[1];
1368 x
.array
[0] |= y
.array
[0];
1376 static INLINE i386_operand_type
1377 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1379 switch (ARRAY_SIZE (x
.array
))
1382 x
.array
[2] ^= y
.array
[2];
1384 x
.array
[1] ^= y
.array
[1];
1386 x
.array
[0] ^= y
.array
[0];
1394 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1395 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1396 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1397 static const i386_operand_type inoutportreg
1398 = OPERAND_TYPE_INOUTPORTREG
;
1399 static const i386_operand_type reg16_inoutportreg
1400 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1401 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1402 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1403 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1404 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1405 static const i386_operand_type anydisp
1406 = OPERAND_TYPE_ANYDISP
;
1407 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1408 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1409 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1410 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1411 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1412 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1413 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1414 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1415 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1416 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1417 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1428 operand_type_check (i386_operand_type t
, enum operand_type c
)
1433 return (t
.bitfield
.reg8
1436 || t
.bitfield
.reg64
);
1439 return (t
.bitfield
.imm8
1443 || t
.bitfield
.imm32s
1444 || t
.bitfield
.imm64
);
1447 return (t
.bitfield
.disp8
1448 || t
.bitfield
.disp16
1449 || t
.bitfield
.disp32
1450 || t
.bitfield
.disp32s
1451 || t
.bitfield
.disp64
);
1454 return (t
.bitfield
.disp8
1455 || t
.bitfield
.disp16
1456 || t
.bitfield
.disp32
1457 || t
.bitfield
.disp32s
1458 || t
.bitfield
.disp64
1459 || t
.bitfield
.baseindex
);
1468 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1469 operand J for instruction template T. */
1472 match_reg_size (const template *t
, unsigned int j
)
1474 return !((i
.types
[j
].bitfield
.byte
1475 && !t
->operand_types
[j
].bitfield
.byte
)
1476 || (i
.types
[j
].bitfield
.word
1477 && !t
->operand_types
[j
].bitfield
.word
)
1478 || (i
.types
[j
].bitfield
.dword
1479 && !t
->operand_types
[j
].bitfield
.dword
)
1480 || (i
.types
[j
].bitfield
.qword
1481 && !t
->operand_types
[j
].bitfield
.qword
));
1484 /* Return 1 if there is no conflict in any size on operand J for
1485 instruction template T. */
1488 match_mem_size (const template *t
, unsigned int j
)
1490 return (match_reg_size (t
, j
)
1491 && !((i
.types
[j
].bitfield
.unspecified
1492 && !t
->operand_types
[j
].bitfield
.unspecified
)
1493 || (i
.types
[j
].bitfield
.fword
1494 && !t
->operand_types
[j
].bitfield
.fword
)
1495 || (i
.types
[j
].bitfield
.tbyte
1496 && !t
->operand_types
[j
].bitfield
.tbyte
)
1497 || (i
.types
[j
].bitfield
.xmmword
1498 && !t
->operand_types
[j
].bitfield
.xmmword
)
1499 || (i
.types
[j
].bitfield
.ymmword
1500 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1503 /* Return 1 if there is no size conflict on any operands for
1504 instruction template T. */
1507 operand_size_match (const template *t
)
1512 /* Don't check jump instructions. */
1513 if (t
->opcode_modifier
.jump
1514 || t
->opcode_modifier
.jumpbyte
1515 || t
->opcode_modifier
.jumpdword
1516 || t
->opcode_modifier
.jumpintersegment
)
1519 /* Check memory and accumulator operand size. */
1520 for (j
= 0; j
< i
.operands
; j
++)
1522 if (t
->operand_types
[j
].bitfield
.anysize
)
1525 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1531 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1539 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1542 /* Check reverse. */
1543 gas_assert (i
.operands
== 2);
1546 for (j
= 0; j
< 2; j
++)
1548 if (t
->operand_types
[j
].bitfield
.acc
1549 && !match_reg_size (t
, j
? 0 : 1))
1555 if (i
.types
[j
].bitfield
.mem
1556 && !match_mem_size (t
, j
? 0 : 1))
1567 operand_type_match (i386_operand_type overlap
,
1568 i386_operand_type given
)
1570 i386_operand_type temp
= overlap
;
1572 temp
.bitfield
.jumpabsolute
= 0;
1573 temp
.bitfield
.unspecified
= 0;
1574 temp
.bitfield
.byte
= 0;
1575 temp
.bitfield
.word
= 0;
1576 temp
.bitfield
.dword
= 0;
1577 temp
.bitfield
.fword
= 0;
1578 temp
.bitfield
.qword
= 0;
1579 temp
.bitfield
.tbyte
= 0;
1580 temp
.bitfield
.xmmword
= 0;
1581 temp
.bitfield
.ymmword
= 0;
1582 if (operand_type_all_zero (&temp
))
1585 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1586 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1589 /* If given types g0 and g1 are registers they must be of the same type
1590 unless the expected operand type register overlap is null.
1591 Note that Acc in a template matches every size of reg. */
1594 operand_type_register_match (i386_operand_type m0
,
1595 i386_operand_type g0
,
1596 i386_operand_type t0
,
1597 i386_operand_type m1
,
1598 i386_operand_type g1
,
1599 i386_operand_type t1
)
1601 if (!operand_type_check (g0
, reg
))
1604 if (!operand_type_check (g1
, reg
))
1607 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1608 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1609 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1610 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1613 if (m0
.bitfield
.acc
)
1615 t0
.bitfield
.reg8
= 1;
1616 t0
.bitfield
.reg16
= 1;
1617 t0
.bitfield
.reg32
= 1;
1618 t0
.bitfield
.reg64
= 1;
1621 if (m1
.bitfield
.acc
)
1623 t1
.bitfield
.reg8
= 1;
1624 t1
.bitfield
.reg16
= 1;
1625 t1
.bitfield
.reg32
= 1;
1626 t1
.bitfield
.reg64
= 1;
1629 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1630 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1631 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1632 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1635 static INLINE
unsigned int
1636 mode_from_disp_size (i386_operand_type t
)
1638 if (t
.bitfield
.disp8
)
1640 else if (t
.bitfield
.disp16
1641 || t
.bitfield
.disp32
1642 || t
.bitfield
.disp32s
)
1649 fits_in_signed_byte (offsetT num
)
1651 return (num
>= -128) && (num
<= 127);
1655 fits_in_unsigned_byte (offsetT num
)
1657 return (num
& 0xff) == num
;
1661 fits_in_unsigned_word (offsetT num
)
1663 return (num
& 0xffff) == num
;
1667 fits_in_signed_word (offsetT num
)
1669 return (-32768 <= num
) && (num
<= 32767);
1673 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1678 return (!(((offsetT
) -1 << 31) & num
)
1679 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1681 } /* fits_in_signed_long() */
1684 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1689 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1691 } /* fits_in_unsigned_long() */
1693 static i386_operand_type
1694 smallest_imm_type (offsetT num
)
1696 i386_operand_type t
;
1698 operand_type_set (&t
, 0);
1699 t
.bitfield
.imm64
= 1;
1701 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1703 /* This code is disabled on the 486 because all the Imm1 forms
1704 in the opcode table are slower on the i486. They're the
1705 versions with the implicitly specified single-position
1706 displacement, which has another syntax if you really want to
1708 t
.bitfield
.imm1
= 1;
1709 t
.bitfield
.imm8
= 1;
1710 t
.bitfield
.imm8s
= 1;
1711 t
.bitfield
.imm16
= 1;
1712 t
.bitfield
.imm32
= 1;
1713 t
.bitfield
.imm32s
= 1;
1715 else if (fits_in_signed_byte (num
))
1717 t
.bitfield
.imm8
= 1;
1718 t
.bitfield
.imm8s
= 1;
1719 t
.bitfield
.imm16
= 1;
1720 t
.bitfield
.imm32
= 1;
1721 t
.bitfield
.imm32s
= 1;
1723 else if (fits_in_unsigned_byte (num
))
1725 t
.bitfield
.imm8
= 1;
1726 t
.bitfield
.imm16
= 1;
1727 t
.bitfield
.imm32
= 1;
1728 t
.bitfield
.imm32s
= 1;
1730 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1732 t
.bitfield
.imm16
= 1;
1733 t
.bitfield
.imm32
= 1;
1734 t
.bitfield
.imm32s
= 1;
1736 else if (fits_in_signed_long (num
))
1738 t
.bitfield
.imm32
= 1;
1739 t
.bitfield
.imm32s
= 1;
1741 else if (fits_in_unsigned_long (num
))
1742 t
.bitfield
.imm32
= 1;
1748 offset_in_range (offsetT val
, int size
)
1754 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1755 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1756 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1758 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1763 /* If BFD64, sign extend val. */
1764 if (!use_rela_relocations
)
1765 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1766 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1768 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1770 char buf1
[40], buf2
[40];
1772 sprint_value (buf1
, val
);
1773 sprint_value (buf2
, val
& mask
);
1774 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1779 /* Returns 0 if attempting to add a prefix where one from the same
1780 class already exists, 1 if non rep/repne added, 2 if rep/repne
1783 add_prefix (unsigned int prefix
)
1788 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1789 && flag_code
== CODE_64BIT
)
1791 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1792 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1793 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1804 case CS_PREFIX_OPCODE
:
1805 case DS_PREFIX_OPCODE
:
1806 case ES_PREFIX_OPCODE
:
1807 case FS_PREFIX_OPCODE
:
1808 case GS_PREFIX_OPCODE
:
1809 case SS_PREFIX_OPCODE
:
1813 case REPNE_PREFIX_OPCODE
:
1814 case REPE_PREFIX_OPCODE
:
1817 case LOCK_PREFIX_OPCODE
:
1825 case ADDR_PREFIX_OPCODE
:
1829 case DATA_PREFIX_OPCODE
:
1833 if (i
.prefix
[q
] != 0)
1841 i
.prefix
[q
] |= prefix
;
1844 as_bad (_("same type of prefix used twice"));
1850 set_code_flag (int value
)
1853 if (flag_code
== CODE_64BIT
)
1855 cpu_arch_flags
.bitfield
.cpu64
= 1;
1856 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1860 cpu_arch_flags
.bitfield
.cpu64
= 0;
1861 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1863 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1865 as_bad (_("64bit mode not supported on this CPU."));
1867 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1869 as_bad (_("32bit mode not supported on this CPU."));
1871 stackop_size
= '\0';
1875 set_16bit_gcc_code_flag (int new_code_flag
)
1877 flag_code
= new_code_flag
;
1878 if (flag_code
!= CODE_16BIT
)
1880 cpu_arch_flags
.bitfield
.cpu64
= 0;
1881 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1882 stackop_size
= LONG_MNEM_SUFFIX
;
1886 set_intel_syntax (int syntax_flag
)
1888 /* Find out if register prefixing is specified. */
1889 int ask_naked_reg
= 0;
1892 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1894 char *string
= input_line_pointer
;
1895 int e
= get_symbol_end ();
1897 if (strcmp (string
, "prefix") == 0)
1899 else if (strcmp (string
, "noprefix") == 0)
1902 as_bad (_("bad argument to syntax directive."));
1903 *input_line_pointer
= e
;
1905 demand_empty_rest_of_line ();
1907 intel_syntax
= syntax_flag
;
1909 if (ask_naked_reg
== 0)
1910 allow_naked_reg
= (intel_syntax
1911 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1913 allow_naked_reg
= (ask_naked_reg
< 0);
1915 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1917 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1918 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1919 register_prefix
= allow_naked_reg
? "" : "%";
1923 set_intel_mnemonic (int mnemonic_flag
)
1925 intel_mnemonic
= mnemonic_flag
;
1929 set_allow_index_reg (int flag
)
1931 allow_index_reg
= flag
;
1935 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1939 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1941 char *string
= input_line_pointer
;
1942 int e
= get_symbol_end ();
1944 if (strcmp (string
, "none") == 0)
1945 sse_check
= sse_check_none
;
1946 else if (strcmp (string
, "warning") == 0)
1947 sse_check
= sse_check_warning
;
1948 else if (strcmp (string
, "error") == 0)
1949 sse_check
= sse_check_error
;
1951 as_bad (_("bad argument to sse_check directive."));
1952 *input_line_pointer
= e
;
1955 as_bad (_("missing argument for sse_check directive"));
1957 demand_empty_rest_of_line ();
1961 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1962 i386_cpu_flags
new ATTRIBUTE_UNUSED
)
1964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1965 static const char *arch
;
1967 /* Intel LIOM is only supported on ELF. */
1973 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1974 use default_arch. */
1975 arch
= cpu_arch_name
;
1977 arch
= default_arch
;
1980 /* If we are targeting Intel L1OM, wm must enable it. */
1981 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1982 || new.bitfield
.cpul1om
)
1985 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1990 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1994 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1996 char *string
= input_line_pointer
;
1997 int e
= get_symbol_end ();
1999 i386_cpu_flags flags
;
2001 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2003 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2005 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2009 cpu_arch_name
= cpu_arch
[i
].name
;
2010 cpu_sub_arch_name
= NULL
;
2011 cpu_arch_flags
= cpu_arch
[i
].flags
;
2012 if (flag_code
== CODE_64BIT
)
2014 cpu_arch_flags
.bitfield
.cpu64
= 1;
2015 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2019 cpu_arch_flags
.bitfield
.cpu64
= 0;
2020 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2022 cpu_arch_isa
= cpu_arch
[i
].type
;
2023 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2024 if (!cpu_arch_tune_set
)
2026 cpu_arch_tune
= cpu_arch_isa
;
2027 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2032 if (strncmp (string
+ 1, "no", 2))
2033 flags
= cpu_flags_or (cpu_arch_flags
,
2036 flags
= cpu_flags_and_not (cpu_arch_flags
,
2038 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2040 if (cpu_sub_arch_name
)
2042 char *name
= cpu_sub_arch_name
;
2043 cpu_sub_arch_name
= concat (name
,
2045 (const char *) NULL
);
2049 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2050 cpu_arch_flags
= flags
;
2052 *input_line_pointer
= e
;
2053 demand_empty_rest_of_line ();
2057 if (i
>= ARRAY_SIZE (cpu_arch
))
2058 as_bad (_("no such architecture: `%s'"), string
);
2060 *input_line_pointer
= e
;
2063 as_bad (_("missing cpu architecture"));
2065 no_cond_jump_promotion
= 0;
2066 if (*input_line_pointer
== ','
2067 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2069 char *string
= ++input_line_pointer
;
2070 int e
= get_symbol_end ();
2072 if (strcmp (string
, "nojumps") == 0)
2073 no_cond_jump_promotion
= 1;
2074 else if (strcmp (string
, "jumps") == 0)
2077 as_bad (_("no such architecture modifier: `%s'"), string
);
2079 *input_line_pointer
= e
;
2082 demand_empty_rest_of_line ();
2085 enum bfd_architecture
2088 if (cpu_arch_isa_flags
.bitfield
.cpul1om
)
2090 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2091 || flag_code
!= CODE_64BIT
)
2092 as_fatal (_("Intel L1OM is 64bit ELF only"));
2093 return bfd_arch_l1om
;
2096 return bfd_arch_i386
;
2102 if (!strcmp (default_arch
, "x86_64"))
2104 if (cpu_arch_isa_flags
.bitfield
.cpul1om
)
2106 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2107 as_fatal (_("Intel L1OM is 64bit ELF only"));
2108 return bfd_mach_l1om
;
2111 return bfd_mach_x86_64
;
2113 else if (!strcmp (default_arch
, "i386"))
2114 return bfd_mach_i386_i386
;
2116 as_fatal (_("Unknown architecture"));
2122 const char *hash_err
;
2124 /* Initialize op_hash hash table. */
2125 op_hash
= hash_new ();
2128 const template *optab
;
2129 templates
*core_optab
;
2131 /* Setup for loop. */
2133 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2134 core_optab
->start
= optab
;
2139 if (optab
->name
== NULL
2140 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2142 /* different name --> ship out current template list;
2143 add to hash table; & begin anew. */
2144 core_optab
->end
= optab
;
2145 hash_err
= hash_insert (op_hash
,
2147 (void *) core_optab
);
2150 as_fatal (_("Internal Error: Can't hash %s: %s"),
2154 if (optab
->name
== NULL
)
2156 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2157 core_optab
->start
= optab
;
2162 /* Initialize reg_hash hash table. */
2163 reg_hash
= hash_new ();
2165 const reg_entry
*regtab
;
2166 unsigned int regtab_size
= i386_regtab_size
;
2168 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2170 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2172 as_fatal (_("Internal Error: Can't hash %s: %s"),
2178 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2183 for (c
= 0; c
< 256; c
++)
2188 mnemonic_chars
[c
] = c
;
2189 register_chars
[c
] = c
;
2190 operand_chars
[c
] = c
;
2192 else if (ISLOWER (c
))
2194 mnemonic_chars
[c
] = c
;
2195 register_chars
[c
] = c
;
2196 operand_chars
[c
] = c
;
2198 else if (ISUPPER (c
))
2200 mnemonic_chars
[c
] = TOLOWER (c
);
2201 register_chars
[c
] = mnemonic_chars
[c
];
2202 operand_chars
[c
] = c
;
2205 if (ISALPHA (c
) || ISDIGIT (c
))
2206 identifier_chars
[c
] = c
;
2209 identifier_chars
[c
] = c
;
2210 operand_chars
[c
] = c
;
2215 identifier_chars
['@'] = '@';
2218 identifier_chars
['?'] = '?';
2219 operand_chars
['?'] = '?';
2221 digit_chars
['-'] = '-';
2222 mnemonic_chars
['_'] = '_';
2223 mnemonic_chars
['-'] = '-';
2224 mnemonic_chars
['.'] = '.';
2225 identifier_chars
['_'] = '_';
2226 identifier_chars
['.'] = '.';
2228 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2229 operand_chars
[(unsigned char) *p
] = *p
;
2232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2235 record_alignment (text_section
, 2);
2236 record_alignment (data_section
, 2);
2237 record_alignment (bss_section
, 2);
2241 if (flag_code
== CODE_64BIT
)
2243 x86_dwarf2_return_column
= 16;
2244 x86_cie_data_alignment
= -8;
2248 x86_dwarf2_return_column
= 8;
2249 x86_cie_data_alignment
= -4;
2254 i386_print_statistics (FILE *file
)
2256 hash_print_statistics (file
, "i386 opcode", op_hash
);
2257 hash_print_statistics (file
, "i386 register", reg_hash
);
2262 /* Debugging routines for md_assemble. */
2263 static void pte (template *);
2264 static void pt (i386_operand_type
);
2265 static void pe (expressionS
*);
2266 static void ps (symbolS
*);
2269 pi (char *line
, i386_insn
*x
)
2273 fprintf (stdout
, "%s: template ", line
);
2275 fprintf (stdout
, " address: base %s index %s scale %x\n",
2276 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2277 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2278 x
->log2_scale_factor
);
2279 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2280 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2281 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2282 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2283 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2284 (x
->rex
& REX_W
) != 0,
2285 (x
->rex
& REX_R
) != 0,
2286 (x
->rex
& REX_X
) != 0,
2287 (x
->rex
& REX_B
) != 0);
2288 for (i
= 0; i
< x
->operands
; i
++)
2290 fprintf (stdout
, " #%d: ", i
+ 1);
2292 fprintf (stdout
, "\n");
2293 if (x
->types
[i
].bitfield
.reg8
2294 || x
->types
[i
].bitfield
.reg16
2295 || x
->types
[i
].bitfield
.reg32
2296 || x
->types
[i
].bitfield
.reg64
2297 || x
->types
[i
].bitfield
.regmmx
2298 || x
->types
[i
].bitfield
.regxmm
2299 || x
->types
[i
].bitfield
.regymm
2300 || x
->types
[i
].bitfield
.sreg2
2301 || x
->types
[i
].bitfield
.sreg3
2302 || x
->types
[i
].bitfield
.control
2303 || x
->types
[i
].bitfield
.debug
2304 || x
->types
[i
].bitfield
.test
)
2305 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2306 if (operand_type_check (x
->types
[i
], imm
))
2308 if (operand_type_check (x
->types
[i
], disp
))
2309 pe (x
->op
[i
].disps
);
2317 fprintf (stdout
, " %d operands ", t
->operands
);
2318 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2319 if (t
->extension_opcode
!= None
)
2320 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2321 if (t
->opcode_modifier
.d
)
2322 fprintf (stdout
, "D");
2323 if (t
->opcode_modifier
.w
)
2324 fprintf (stdout
, "W");
2325 fprintf (stdout
, "\n");
2326 for (i
= 0; i
< t
->operands
; i
++)
2328 fprintf (stdout
, " #%d type ", i
+ 1);
2329 pt (t
->operand_types
[i
]);
2330 fprintf (stdout
, "\n");
2337 fprintf (stdout
, " operation %d\n", e
->X_op
);
2338 fprintf (stdout
, " add_number %ld (%lx)\n",
2339 (long) e
->X_add_number
, (long) e
->X_add_number
);
2340 if (e
->X_add_symbol
)
2342 fprintf (stdout
, " add_symbol ");
2343 ps (e
->X_add_symbol
);
2344 fprintf (stdout
, "\n");
2348 fprintf (stdout
, " op_symbol ");
2349 ps (e
->X_op_symbol
);
2350 fprintf (stdout
, "\n");
2357 fprintf (stdout
, "%s type %s%s",
2359 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2360 segment_name (S_GET_SEGMENT (s
)));
2363 static struct type_name
2365 i386_operand_type mask
;
2368 const type_names
[] =
2370 { OPERAND_TYPE_REG8
, "r8" },
2371 { OPERAND_TYPE_REG16
, "r16" },
2372 { OPERAND_TYPE_REG32
, "r32" },
2373 { OPERAND_TYPE_REG64
, "r64" },
2374 { OPERAND_TYPE_IMM8
, "i8" },
2375 { OPERAND_TYPE_IMM8
, "i8s" },
2376 { OPERAND_TYPE_IMM16
, "i16" },
2377 { OPERAND_TYPE_IMM32
, "i32" },
2378 { OPERAND_TYPE_IMM32S
, "i32s" },
2379 { OPERAND_TYPE_IMM64
, "i64" },
2380 { OPERAND_TYPE_IMM1
, "i1" },
2381 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2382 { OPERAND_TYPE_DISP8
, "d8" },
2383 { OPERAND_TYPE_DISP16
, "d16" },
2384 { OPERAND_TYPE_DISP32
, "d32" },
2385 { OPERAND_TYPE_DISP32S
, "d32s" },
2386 { OPERAND_TYPE_DISP64
, "d64" },
2387 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2388 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2389 { OPERAND_TYPE_CONTROL
, "control reg" },
2390 { OPERAND_TYPE_TEST
, "test reg" },
2391 { OPERAND_TYPE_DEBUG
, "debug reg" },
2392 { OPERAND_TYPE_FLOATREG
, "FReg" },
2393 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2394 { OPERAND_TYPE_SREG2
, "SReg2" },
2395 { OPERAND_TYPE_SREG3
, "SReg3" },
2396 { OPERAND_TYPE_ACC
, "Acc" },
2397 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2398 { OPERAND_TYPE_REGMMX
, "rMMX" },
2399 { OPERAND_TYPE_REGXMM
, "rXMM" },
2400 { OPERAND_TYPE_REGYMM
, "rYMM" },
2401 { OPERAND_TYPE_ESSEG
, "es" },
2405 pt (i386_operand_type t
)
2408 i386_operand_type a
;
2410 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2412 a
= operand_type_and (t
, type_names
[j
].mask
);
2413 if (!operand_type_all_zero (&a
))
2414 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2419 #endif /* DEBUG386 */
2421 static bfd_reloc_code_real_type
2422 reloc (unsigned int size
,
2425 bfd_reloc_code_real_type other
)
2427 if (other
!= NO_RELOC
)
2429 reloc_howto_type
*reloc
;
2434 case BFD_RELOC_X86_64_GOT32
:
2435 return BFD_RELOC_X86_64_GOT64
;
2437 case BFD_RELOC_X86_64_PLTOFF64
:
2438 return BFD_RELOC_X86_64_PLTOFF64
;
2440 case BFD_RELOC_X86_64_GOTPC32
:
2441 other
= BFD_RELOC_X86_64_GOTPC64
;
2443 case BFD_RELOC_X86_64_GOTPCREL
:
2444 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2446 case BFD_RELOC_X86_64_TPOFF32
:
2447 other
= BFD_RELOC_X86_64_TPOFF64
;
2449 case BFD_RELOC_X86_64_DTPOFF32
:
2450 other
= BFD_RELOC_X86_64_DTPOFF64
;
2456 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2457 if (size
== 4 && flag_code
!= CODE_64BIT
)
2460 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2462 as_bad (_("unknown relocation (%u)"), other
);
2463 else if (size
!= bfd_get_reloc_size (reloc
))
2464 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2465 bfd_get_reloc_size (reloc
),
2467 else if (pcrel
&& !reloc
->pc_relative
)
2468 as_bad (_("non-pc-relative relocation for pc-relative field"));
2469 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2471 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2473 as_bad (_("relocated field and relocation type differ in signedness"));
2482 as_bad (_("there are no unsigned pc-relative relocations"));
2485 case 1: return BFD_RELOC_8_PCREL
;
2486 case 2: return BFD_RELOC_16_PCREL
;
2487 case 4: return BFD_RELOC_32_PCREL
;
2488 case 8: return BFD_RELOC_64_PCREL
;
2490 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2497 case 4: return BFD_RELOC_X86_64_32S
;
2502 case 1: return BFD_RELOC_8
;
2503 case 2: return BFD_RELOC_16
;
2504 case 4: return BFD_RELOC_32
;
2505 case 8: return BFD_RELOC_64
;
2507 as_bad (_("cannot do %s %u byte relocation"),
2508 sign
> 0 ? "signed" : "unsigned", size
);
2514 /* Here we decide which fixups can be adjusted to make them relative to
2515 the beginning of the section instead of the symbol. Basically we need
2516 to make sure that the dynamic relocations are done correctly, so in
2517 some cases we force the original symbol to be used. */
2520 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2526 /* Don't adjust pc-relative references to merge sections in 64-bit
2528 if (use_rela_relocations
2529 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2533 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2534 and changed later by validate_fix. */
2535 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2536 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2539 /* adjust_reloc_syms doesn't know about the GOT. */
2540 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2541 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2542 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2543 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2544 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2545 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2546 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2547 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2553 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2554 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2555 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2556 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2557 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2566 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2567 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2574 intel_float_operand (const char *mnemonic
)
2576 /* Note that the value returned is meaningful only for opcodes with (memory)
2577 operands, hence the code here is free to improperly handle opcodes that
2578 have no operands (for better performance and smaller code). */
2580 if (mnemonic
[0] != 'f')
2581 return 0; /* non-math */
2583 switch (mnemonic
[1])
2585 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2586 the fs segment override prefix not currently handled because no
2587 call path can make opcodes without operands get here */
2589 return 2 /* integer op */;
2591 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2592 return 3; /* fldcw/fldenv */
2595 if (mnemonic
[2] != 'o' /* fnop */)
2596 return 3; /* non-waiting control op */
2599 if (mnemonic
[2] == 's')
2600 return 3; /* frstor/frstpm */
2603 if (mnemonic
[2] == 'a')
2604 return 3; /* fsave */
2605 if (mnemonic
[2] == 't')
2607 switch (mnemonic
[3])
2609 case 'c': /* fstcw */
2610 case 'd': /* fstdw */
2611 case 'e': /* fstenv */
2612 case 's': /* fsts[gw] */
2618 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2619 return 0; /* fxsave/fxrstor are not really math ops */
2626 /* Build the VEX prefix. */
2629 build_vex_prefix (const template *t
)
2631 unsigned int register_specifier
;
2632 unsigned int implied_prefix
;
2633 unsigned int vector_length
;
2635 /* Check register specifier. */
2636 if (i
.vex
.register_specifier
)
2638 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2639 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2640 register_specifier
+= 8;
2641 register_specifier
= ~register_specifier
& 0xf;
2644 register_specifier
= 0xf;
2646 /* Use 2-byte VEX prefix by swappping destination and source
2649 && i
.operands
== i
.reg_operands
2650 && i
.tm
.opcode_modifier
.vex0f
2651 && i
.tm
.opcode_modifier
.s
2654 unsigned int xchg
= i
.operands
- 1;
2655 union i386_op temp_op
;
2656 i386_operand_type temp_type
;
2658 temp_type
= i
.types
[xchg
];
2659 i
.types
[xchg
] = i
.types
[0];
2660 i
.types
[0] = temp_type
;
2661 temp_op
= i
.op
[xchg
];
2662 i
.op
[xchg
] = i
.op
[0];
2665 gas_assert (i
.rm
.mode
== 3);
2669 i
.rm
.regmem
= i
.rm
.reg
;
2672 /* Use the next insn. */
2676 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2678 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2683 case DATA_PREFIX_OPCODE
:
2686 case REPE_PREFIX_OPCODE
:
2689 case REPNE_PREFIX_OPCODE
:
2696 /* Use 2-byte VEX prefix if possible. */
2697 if (i
.tm
.opcode_modifier
.vex0f
2698 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2700 /* 2-byte VEX prefix. */
2704 i
.vex
.bytes
[0] = 0xc5;
2706 /* Check the REX.R bit. */
2707 r
= (i
.rex
& REX_R
) ? 0 : 1;
2708 i
.vex
.bytes
[1] = (r
<< 7
2709 | register_specifier
<< 3
2710 | vector_length
<< 2
2715 /* 3-byte VEX prefix. */
2718 if (i
.tm
.opcode_modifier
.vex0f
)
2720 else if (i
.tm
.opcode_modifier
.vex0f38
)
2722 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2728 i
.vex
.bytes
[0] = 0xc4;
2730 /* The high 3 bits of the second VEX byte are 1's compliment
2731 of RXB bits from REX. */
2732 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2734 /* Check the REX.W bit. */
2735 w
= (i
.rex
& REX_W
) ? 1 : 0;
2736 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2741 if (i
.tm
.opcode_modifier
.vexw1
)
2745 i
.vex
.bytes
[2] = (w
<< 7
2746 | register_specifier
<< 3
2747 | vector_length
<< 2
2753 process_immext (void)
2757 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2759 /* SSE3 Instructions have the fixed operands with an opcode
2760 suffix which is coded in the same place as an 8-bit immediate
2761 field would be. Here we check those operands and remove them
2765 for (x
= 0; x
< i
.operands
; x
++)
2766 if (i
.op
[x
].regs
->reg_num
!= x
)
2767 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2768 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2774 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2775 which is coded in the same place as an 8-bit immediate field
2776 would be. Here we fake an 8-bit immediate operand from the
2777 opcode suffix stored in tm.extension_opcode.
2779 AVX instructions also use this encoding, for some of
2780 3 argument instructions. */
2782 gas_assert (i
.imm_operands
== 0
2784 || (i
.tm
.opcode_modifier
.vex
2785 && i
.operands
<= 4)));
2787 exp
= &im_expressions
[i
.imm_operands
++];
2788 i
.op
[i
.operands
].imms
= exp
;
2789 i
.types
[i
.operands
] = imm8
;
2791 exp
->X_op
= O_constant
;
2792 exp
->X_add_number
= i
.tm
.extension_opcode
;
2793 i
.tm
.extension_opcode
= None
;
2796 /* This is the guts of the machine-dependent assembler. LINE points to a
2797 machine dependent instruction. This function is supposed to emit
2798 the frags/bytes it assembles to. */
2801 md_assemble (char *line
)
2804 char mnemonic
[MAX_MNEM_SIZE
];
2807 /* Initialize globals. */
2808 memset (&i
, '\0', sizeof (i
));
2809 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2810 i
.reloc
[j
] = NO_RELOC
;
2811 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2812 memset (im_expressions
, '\0', sizeof (im_expressions
));
2813 save_stack_p
= save_stack
;
2815 /* First parse an instruction mnemonic & call i386_operand for the operands.
2816 We assume that the scrubber has arranged it so that line[0] is the valid
2817 start of a (possibly prefixed) mnemonic. */
2819 line
= parse_insn (line
, mnemonic
);
2823 line
= parse_operands (line
, mnemonic
);
2828 /* Now we've parsed the mnemonic into a set of templates, and have the
2829 operands at hand. */
2831 /* All intel opcodes have reversed operands except for "bound" and
2832 "enter". We also don't reverse intersegment "jmp" and "call"
2833 instructions with 2 immediate operands so that the immediate segment
2834 precedes the offset, as it does when in AT&T mode. */
2837 && (strcmp (mnemonic
, "bound") != 0)
2838 && (strcmp (mnemonic
, "invlpga") != 0)
2839 && !(operand_type_check (i
.types
[0], imm
)
2840 && operand_type_check (i
.types
[1], imm
)))
2843 /* The order of the immediates should be reversed
2844 for 2 immediates extrq and insertq instructions */
2845 if (i
.imm_operands
== 2
2846 && (strcmp (mnemonic
, "extrq") == 0
2847 || strcmp (mnemonic
, "insertq") == 0))
2848 swap_2_operands (0, 1);
2853 /* Don't optimize displacement for movabs since it only takes 64bit
2856 && (flag_code
!= CODE_64BIT
2857 || strcmp (mnemonic
, "movabs") != 0))
2860 /* Next, we find a template that matches the given insn,
2861 making sure the overlap of the given operands types is consistent
2862 with the template operand types. */
2864 if (!(t
= match_template ()))
2867 if (sse_check
!= sse_check_none
2868 && !i
.tm
.opcode_modifier
.noavx
2869 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2870 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2871 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2872 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2873 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2874 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2876 (sse_check
== sse_check_warning
2878 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2881 /* Zap movzx and movsx suffix. The suffix has been set from
2882 "word ptr" or "byte ptr" on the source operand in Intel syntax
2883 or extracted from mnemonic in AT&T syntax. But we'll use
2884 the destination register to choose the suffix for encoding. */
2885 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2887 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2888 there is no suffix, the default will be byte extension. */
2889 if (i
.reg_operands
!= 2
2892 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2897 if (i
.tm
.opcode_modifier
.fwait
)
2898 if (!add_prefix (FWAIT_OPCODE
))
2901 /* Check string instruction segment overrides. */
2902 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2904 if (!check_string ())
2906 i
.disp_operands
= 0;
2909 if (!process_suffix ())
2912 /* Update operand types. */
2913 for (j
= 0; j
< i
.operands
; j
++)
2914 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2916 /* Make still unresolved immediate matches conform to size of immediate
2917 given in i.suffix. */
2918 if (!finalize_imm ())
2921 if (i
.types
[0].bitfield
.imm1
)
2922 i
.imm_operands
= 0; /* kludge for shift insns. */
2924 /* We only need to check those implicit registers for instructions
2925 with 3 operands or less. */
2926 if (i
.operands
<= 3)
2927 for (j
= 0; j
< i
.operands
; j
++)
2928 if (i
.types
[j
].bitfield
.inoutportreg
2929 || i
.types
[j
].bitfield
.shiftcount
2930 || i
.types
[j
].bitfield
.acc
2931 || i
.types
[j
].bitfield
.floatacc
)
2934 /* ImmExt should be processed after SSE2AVX. */
2935 if (!i
.tm
.opcode_modifier
.sse2avx
2936 && i
.tm
.opcode_modifier
.immext
)
2939 /* For insns with operands there are more diddles to do to the opcode. */
2942 if (!process_operands ())
2945 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2947 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2948 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2951 if (i
.tm
.opcode_modifier
.vex
)
2952 build_vex_prefix (t
);
2954 /* Handle conversion of 'int $3' --> special int3 insn. */
2955 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2957 i
.tm
.base_opcode
= INT3_OPCODE
;
2961 if ((i
.tm
.opcode_modifier
.jump
2962 || i
.tm
.opcode_modifier
.jumpbyte
2963 || i
.tm
.opcode_modifier
.jumpdword
)
2964 && i
.op
[0].disps
->X_op
== O_constant
)
2966 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2967 the absolute address given by the constant. Since ix86 jumps and
2968 calls are pc relative, we need to generate a reloc. */
2969 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2970 i
.op
[0].disps
->X_op
= O_symbol
;
2973 if (i
.tm
.opcode_modifier
.rex64
)
2976 /* For 8 bit registers we need an empty rex prefix. Also if the
2977 instruction already has a prefix, we need to convert old
2978 registers to new ones. */
2980 if ((i
.types
[0].bitfield
.reg8
2981 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2982 || (i
.types
[1].bitfield
.reg8
2983 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2984 || ((i
.types
[0].bitfield
.reg8
2985 || i
.types
[1].bitfield
.reg8
)
2990 i
.rex
|= REX_OPCODE
;
2991 for (x
= 0; x
< 2; x
++)
2993 /* Look for 8 bit operand that uses old registers. */
2994 if (i
.types
[x
].bitfield
.reg8
2995 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2997 /* In case it is "hi" register, give up. */
2998 if (i
.op
[x
].regs
->reg_num
> 3)
2999 as_bad (_("can't encode register '%s%s' in an "
3000 "instruction requiring REX prefix."),
3001 register_prefix
, i
.op
[x
].regs
->reg_name
);
3003 /* Otherwise it is equivalent to the extended register.
3004 Since the encoding doesn't change this is merely
3005 cosmetic cleanup for debug output. */
3007 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3013 add_prefix (REX_OPCODE
| i
.rex
);
3015 /* We are ready to output the insn. */
3020 parse_insn (char *line
, char *mnemonic
)
3023 char *token_start
= l
;
3029 /* Non-zero if we found a prefix only acceptable with string insns. */
3030 const char *expecting_string_instruction
= NULL
;
3035 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3040 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3042 as_bad (_("no such instruction: `%s'"), token_start
);
3047 if (!is_space_char (*l
)
3048 && *l
!= END_OF_INSN
3050 || (*l
!= PREFIX_SEPARATOR
3053 as_bad (_("invalid character %s in mnemonic"),
3054 output_invalid (*l
));
3057 if (token_start
== l
)
3059 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3060 as_bad (_("expecting prefix; got nothing"));
3062 as_bad (_("expecting mnemonic; got nothing"));
3066 /* Look up instruction (or prefix) via hash table. */
3067 current_templates
= hash_find (op_hash
, mnemonic
);
3069 if (*l
!= END_OF_INSN
3070 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3071 && current_templates
3072 && current_templates
->start
->opcode_modifier
.isprefix
)
3074 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3076 as_bad ((flag_code
!= CODE_64BIT
3077 ? _("`%s' is only supported in 64-bit mode")
3078 : _("`%s' is not supported in 64-bit mode")),
3079 current_templates
->start
->name
);
3082 /* If we are in 16-bit mode, do not allow addr16 or data16.
3083 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3084 if ((current_templates
->start
->opcode_modifier
.size16
3085 || current_templates
->start
->opcode_modifier
.size32
)
3086 && flag_code
!= CODE_64BIT
3087 && (current_templates
->start
->opcode_modifier
.size32
3088 ^ (flag_code
== CODE_16BIT
)))
3090 as_bad (_("redundant %s prefix"),
3091 current_templates
->start
->name
);
3094 /* Add prefix, checking for repeated prefixes. */
3095 switch (add_prefix (current_templates
->start
->base_opcode
))
3100 expecting_string_instruction
= current_templates
->start
->name
;
3103 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3110 if (!current_templates
)
3112 /* Check if we should swap operand in encoding. */
3113 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3119 current_templates
= hash_find (op_hash
, mnemonic
);
3122 if (!current_templates
)
3125 /* See if we can get a match by trimming off a suffix. */
3128 case WORD_MNEM_SUFFIX
:
3129 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3130 i
.suffix
= SHORT_MNEM_SUFFIX
;
3132 case BYTE_MNEM_SUFFIX
:
3133 case QWORD_MNEM_SUFFIX
:
3134 i
.suffix
= mnem_p
[-1];
3136 current_templates
= hash_find (op_hash
, mnemonic
);
3138 case SHORT_MNEM_SUFFIX
:
3139 case LONG_MNEM_SUFFIX
:
3142 i
.suffix
= mnem_p
[-1];
3144 current_templates
= hash_find (op_hash
, mnemonic
);
3152 if (intel_float_operand (mnemonic
) == 1)
3153 i
.suffix
= SHORT_MNEM_SUFFIX
;
3155 i
.suffix
= LONG_MNEM_SUFFIX
;
3157 current_templates
= hash_find (op_hash
, mnemonic
);
3161 if (!current_templates
)
3163 as_bad (_("no such instruction: `%s'"), token_start
);
3168 if (current_templates
->start
->opcode_modifier
.jump
3169 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3171 /* Check for a branch hint. We allow ",pt" and ",pn" for
3172 predict taken and predict not taken respectively.
3173 I'm not sure that branch hints actually do anything on loop
3174 and jcxz insns (JumpByte) for current Pentium4 chips. They
3175 may work in the future and it doesn't hurt to accept them
3177 if (l
[0] == ',' && l
[1] == 'p')
3181 if (!add_prefix (DS_PREFIX_OPCODE
))
3185 else if (l
[2] == 'n')
3187 if (!add_prefix (CS_PREFIX_OPCODE
))
3193 /* Any other comma loses. */
3196 as_bad (_("invalid character %s in mnemonic"),
3197 output_invalid (*l
));
3201 /* Check if instruction is supported on specified architecture. */
3203 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3205 supported
|= cpu_flags_match (t
);
3206 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3210 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3212 as_bad (flag_code
== CODE_64BIT
3213 ? _("`%s' is not supported in 64-bit mode")
3214 : _("`%s' is only supported in 64-bit mode"),
3215 current_templates
->start
->name
);
3218 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3220 as_bad (_("`%s' is not supported on `%s%s'"),
3221 current_templates
->start
->name
,
3222 cpu_arch_name
? cpu_arch_name
: default_arch
,
3223 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3228 if (!cpu_arch_flags
.bitfield
.cpui386
3229 && (flag_code
!= CODE_16BIT
))
3231 as_warn (_("use .code16 to ensure correct addressing mode"));
3234 /* Check for rep/repne without a string instruction. */
3235 if (expecting_string_instruction
)
3237 static templates override
;
3239 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3240 if (t
->opcode_modifier
.isstring
)
3242 if (t
>= current_templates
->end
)
3244 as_bad (_("expecting string instruction after `%s'"),
3245 expecting_string_instruction
);
3248 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3249 if (!t
->opcode_modifier
.isstring
)
3252 current_templates
= &override
;
3259 parse_operands (char *l
, const char *mnemonic
)
3263 /* 1 if operand is pending after ','. */
3264 unsigned int expecting_operand
= 0;
3266 /* Non-zero if operand parens not balanced. */
3267 unsigned int paren_not_balanced
;
3269 while (*l
!= END_OF_INSN
)
3271 /* Skip optional white space before operand. */
3272 if (is_space_char (*l
))
3274 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3276 as_bad (_("invalid character %s before operand %d"),
3277 output_invalid (*l
),
3281 token_start
= l
; /* after white space */
3282 paren_not_balanced
= 0;
3283 while (paren_not_balanced
|| *l
!= ',')
3285 if (*l
== END_OF_INSN
)
3287 if (paren_not_balanced
)
3290 as_bad (_("unbalanced parenthesis in operand %d."),
3293 as_bad (_("unbalanced brackets in operand %d."),
3298 break; /* we are done */
3300 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3302 as_bad (_("invalid character %s in operand %d"),
3303 output_invalid (*l
),
3310 ++paren_not_balanced
;
3312 --paren_not_balanced
;
3317 ++paren_not_balanced
;
3319 --paren_not_balanced
;
3323 if (l
!= token_start
)
3324 { /* Yes, we've read in another operand. */
3325 unsigned int operand_ok
;
3326 this_operand
= i
.operands
++;
3327 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3328 if (i
.operands
> MAX_OPERANDS
)
3330 as_bad (_("spurious operands; (%d operands/instruction max)"),
3334 /* Now parse operand adding info to 'i' as we go along. */
3335 END_STRING_AND_SAVE (l
);
3339 i386_intel_operand (token_start
,
3340 intel_float_operand (mnemonic
));
3342 operand_ok
= i386_att_operand (token_start
);
3344 RESTORE_END_STRING (l
);
3350 if (expecting_operand
)
3352 expecting_operand_after_comma
:
3353 as_bad (_("expecting operand after ','; got nothing"));
3358 as_bad (_("expecting operand before ','; got nothing"));
3363 /* Now *l must be either ',' or END_OF_INSN. */
3366 if (*++l
== END_OF_INSN
)
3368 /* Just skip it, if it's \n complain. */
3369 goto expecting_operand_after_comma
;
3371 expecting_operand
= 1;
3378 swap_2_operands (int xchg1
, int xchg2
)
3380 union i386_op temp_op
;
3381 i386_operand_type temp_type
;
3382 enum bfd_reloc_code_real temp_reloc
;
3384 temp_type
= i
.types
[xchg2
];
3385 i
.types
[xchg2
] = i
.types
[xchg1
];
3386 i
.types
[xchg1
] = temp_type
;
3387 temp_op
= i
.op
[xchg2
];
3388 i
.op
[xchg2
] = i
.op
[xchg1
];
3389 i
.op
[xchg1
] = temp_op
;
3390 temp_reloc
= i
.reloc
[xchg2
];
3391 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3392 i
.reloc
[xchg1
] = temp_reloc
;
3396 swap_operands (void)
3402 swap_2_operands (1, i
.operands
- 2);
3405 swap_2_operands (0, i
.operands
- 1);
3411 if (i
.mem_operands
== 2)
3413 const seg_entry
*temp_seg
;
3414 temp_seg
= i
.seg
[0];
3415 i
.seg
[0] = i
.seg
[1];
3416 i
.seg
[1] = temp_seg
;
3420 /* Try to ensure constant immediates are represented in the smallest
3425 char guess_suffix
= 0;
3429 guess_suffix
= i
.suffix
;
3430 else if (i
.reg_operands
)
3432 /* Figure out a suffix from the last register operand specified.
3433 We can't do this properly yet, ie. excluding InOutPortReg,
3434 but the following works for instructions with immediates.
3435 In any case, we can't set i.suffix yet. */
3436 for (op
= i
.operands
; --op
>= 0;)
3437 if (i
.types
[op
].bitfield
.reg8
)
3439 guess_suffix
= BYTE_MNEM_SUFFIX
;
3442 else if (i
.types
[op
].bitfield
.reg16
)
3444 guess_suffix
= WORD_MNEM_SUFFIX
;
3447 else if (i
.types
[op
].bitfield
.reg32
)
3449 guess_suffix
= LONG_MNEM_SUFFIX
;
3452 else if (i
.types
[op
].bitfield
.reg64
)
3454 guess_suffix
= QWORD_MNEM_SUFFIX
;
3458 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3459 guess_suffix
= WORD_MNEM_SUFFIX
;
3461 for (op
= i
.operands
; --op
>= 0;)
3462 if (operand_type_check (i
.types
[op
], imm
))
3464 switch (i
.op
[op
].imms
->X_op
)
3467 /* If a suffix is given, this operand may be shortened. */
3468 switch (guess_suffix
)
3470 case LONG_MNEM_SUFFIX
:
3471 i
.types
[op
].bitfield
.imm32
= 1;
3472 i
.types
[op
].bitfield
.imm64
= 1;
3474 case WORD_MNEM_SUFFIX
:
3475 i
.types
[op
].bitfield
.imm16
= 1;
3476 i
.types
[op
].bitfield
.imm32
= 1;
3477 i
.types
[op
].bitfield
.imm32s
= 1;
3478 i
.types
[op
].bitfield
.imm64
= 1;
3480 case BYTE_MNEM_SUFFIX
:
3481 i
.types
[op
].bitfield
.imm8
= 1;
3482 i
.types
[op
].bitfield
.imm8s
= 1;
3483 i
.types
[op
].bitfield
.imm16
= 1;
3484 i
.types
[op
].bitfield
.imm32
= 1;
3485 i
.types
[op
].bitfield
.imm32s
= 1;
3486 i
.types
[op
].bitfield
.imm64
= 1;
3490 /* If this operand is at most 16 bits, convert it
3491 to a signed 16 bit number before trying to see
3492 whether it will fit in an even smaller size.
3493 This allows a 16-bit operand such as $0xffe0 to
3494 be recognised as within Imm8S range. */
3495 if ((i
.types
[op
].bitfield
.imm16
)
3496 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3498 i
.op
[op
].imms
->X_add_number
=
3499 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3501 if ((i
.types
[op
].bitfield
.imm32
)
3502 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3505 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3506 ^ ((offsetT
) 1 << 31))
3507 - ((offsetT
) 1 << 31));
3510 = operand_type_or (i
.types
[op
],
3511 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3513 /* We must avoid matching of Imm32 templates when 64bit
3514 only immediate is available. */
3515 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3516 i
.types
[op
].bitfield
.imm32
= 0;
3523 /* Symbols and expressions. */
3525 /* Convert symbolic operand to proper sizes for matching, but don't
3526 prevent matching a set of insns that only supports sizes other
3527 than those matching the insn suffix. */
3529 i386_operand_type mask
, allowed
;
3532 operand_type_set (&mask
, 0);
3533 operand_type_set (&allowed
, 0);
3535 for (t
= current_templates
->start
;
3536 t
< current_templates
->end
;
3538 allowed
= operand_type_or (allowed
,
3539 t
->operand_types
[op
]);
3540 switch (guess_suffix
)
3542 case QWORD_MNEM_SUFFIX
:
3543 mask
.bitfield
.imm64
= 1;
3544 mask
.bitfield
.imm32s
= 1;
3546 case LONG_MNEM_SUFFIX
:
3547 mask
.bitfield
.imm32
= 1;
3549 case WORD_MNEM_SUFFIX
:
3550 mask
.bitfield
.imm16
= 1;
3552 case BYTE_MNEM_SUFFIX
:
3553 mask
.bitfield
.imm8
= 1;
3558 allowed
= operand_type_and (mask
, allowed
);
3559 if (!operand_type_all_zero (&allowed
))
3560 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3567 /* Try to use the smallest displacement type too. */
3569 optimize_disp (void)
3573 for (op
= i
.operands
; --op
>= 0;)
3574 if (operand_type_check (i
.types
[op
], disp
))
3576 if (i
.op
[op
].disps
->X_op
== O_constant
)
3578 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3580 if (i
.types
[op
].bitfield
.disp16
3581 && (disp
& ~(offsetT
) 0xffff) == 0)
3583 /* If this operand is at most 16 bits, convert
3584 to a signed 16 bit number and don't use 64bit
3586 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3587 i
.types
[op
].bitfield
.disp64
= 0;
3589 if (i
.types
[op
].bitfield
.disp32
3590 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3592 /* If this operand is at most 32 bits, convert
3593 to a signed 32 bit number and don't use 64bit
3595 disp
&= (((offsetT
) 2 << 31) - 1);
3596 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3597 i
.types
[op
].bitfield
.disp64
= 0;
3599 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3601 i
.types
[op
].bitfield
.disp8
= 0;
3602 i
.types
[op
].bitfield
.disp16
= 0;
3603 i
.types
[op
].bitfield
.disp32
= 0;
3604 i
.types
[op
].bitfield
.disp32s
= 0;
3605 i
.types
[op
].bitfield
.disp64
= 0;
3609 else if (flag_code
== CODE_64BIT
)
3611 if (fits_in_signed_long (disp
))
3613 i
.types
[op
].bitfield
.disp64
= 0;
3614 i
.types
[op
].bitfield
.disp32s
= 1;
3616 if (fits_in_unsigned_long (disp
))
3617 i
.types
[op
].bitfield
.disp32
= 1;
3619 if ((i
.types
[op
].bitfield
.disp32
3620 || i
.types
[op
].bitfield
.disp32s
3621 || i
.types
[op
].bitfield
.disp16
)
3622 && fits_in_signed_byte (disp
))
3623 i
.types
[op
].bitfield
.disp8
= 1;
3625 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3626 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3628 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3629 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3630 i
.types
[op
].bitfield
.disp8
= 0;
3631 i
.types
[op
].bitfield
.disp16
= 0;
3632 i
.types
[op
].bitfield
.disp32
= 0;
3633 i
.types
[op
].bitfield
.disp32s
= 0;
3634 i
.types
[op
].bitfield
.disp64
= 0;
3637 /* We only support 64bit displacement on constants. */
3638 i
.types
[op
].bitfield
.disp64
= 0;
3642 static const template *
3643 match_template (void)
3645 /* Points to template once we've found it. */
3647 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3648 i386_operand_type overlap4
;
3649 unsigned int found_reverse_match
;
3650 i386_opcode_modifier suffix_check
;
3651 i386_operand_type operand_types
[MAX_OPERANDS
];
3652 int addr_prefix_disp
;
3654 unsigned int found_cpu_match
;
3655 unsigned int check_register
;
3657 #if MAX_OPERANDS != 5
3658 # error "MAX_OPERANDS must be 5."
3661 found_reverse_match
= 0;
3662 addr_prefix_disp
= -1;
3664 memset (&suffix_check
, 0, sizeof (suffix_check
));
3665 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3666 suffix_check
.no_bsuf
= 1;
3667 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3668 suffix_check
.no_wsuf
= 1;
3669 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3670 suffix_check
.no_ssuf
= 1;
3671 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3672 suffix_check
.no_lsuf
= 1;
3673 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3674 suffix_check
.no_qsuf
= 1;
3675 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3676 suffix_check
.no_ldsuf
= 1;
3678 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3680 addr_prefix_disp
= -1;
3682 /* Must have right number of operands. */
3683 if (i
.operands
!= t
->operands
)
3686 /* Check processor support. */
3687 found_cpu_match
= (cpu_flags_match (t
)
3688 == CPU_FLAGS_PERFECT_MATCH
);
3689 if (!found_cpu_match
)
3692 /* Check old gcc support. */
3693 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3696 /* Check AT&T mnemonic. */
3697 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3700 /* Check AT&T syntax Intel syntax. */
3701 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3702 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3705 /* Check the suffix, except for some instructions in intel mode. */
3706 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3707 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3708 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3709 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3710 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3711 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3712 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3715 if (!operand_size_match (t
))
3718 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3719 operand_types
[j
] = t
->operand_types
[j
];
3721 /* In general, don't allow 64-bit operands in 32-bit mode. */
3722 if (i
.suffix
== QWORD_MNEM_SUFFIX
3723 && flag_code
!= CODE_64BIT
3725 ? (!t
->opcode_modifier
.ignoresize
3726 && !intel_float_operand (t
->name
))
3727 : intel_float_operand (t
->name
) != 2)
3728 && ((!operand_types
[0].bitfield
.regmmx
3729 && !operand_types
[0].bitfield
.regxmm
3730 && !operand_types
[0].bitfield
.regymm
)
3731 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3732 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3733 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3734 && (t
->base_opcode
!= 0x0fc7
3735 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3738 /* In general, don't allow 32-bit operands on pre-386. */
3739 else if (i
.suffix
== LONG_MNEM_SUFFIX
3740 && !cpu_arch_flags
.bitfield
.cpui386
3742 ? (!t
->opcode_modifier
.ignoresize
3743 && !intel_float_operand (t
->name
))
3744 : intel_float_operand (t
->name
) != 2)
3745 && ((!operand_types
[0].bitfield
.regmmx
3746 && !operand_types
[0].bitfield
.regxmm
)
3747 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3748 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3751 /* Do not verify operands when there are none. */
3755 /* We've found a match; break out of loop. */
3759 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3760 into Disp32/Disp16/Disp32 operand. */
3761 if (i
.prefix
[ADDR_PREFIX
] != 0)
3763 /* There should be only one Disp operand. */
3767 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3769 if (operand_types
[j
].bitfield
.disp16
)
3771 addr_prefix_disp
= j
;
3772 operand_types
[j
].bitfield
.disp32
= 1;
3773 operand_types
[j
].bitfield
.disp16
= 0;
3779 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3781 if (operand_types
[j
].bitfield
.disp32
)
3783 addr_prefix_disp
= j
;
3784 operand_types
[j
].bitfield
.disp32
= 0;
3785 operand_types
[j
].bitfield
.disp16
= 1;
3791 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3793 if (operand_types
[j
].bitfield
.disp64
)
3795 addr_prefix_disp
= j
;
3796 operand_types
[j
].bitfield
.disp64
= 0;
3797 operand_types
[j
].bitfield
.disp32
= 1;
3805 /* We check register size only if size of operands can be
3806 encoded the canonical way. */
3807 check_register
= t
->opcode_modifier
.w
;
3808 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3809 switch (t
->operands
)
3812 if (!operand_type_match (overlap0
, i
.types
[0]))
3816 /* xchg %eax, %eax is a special case. It is an aliase for nop
3817 only in 32bit mode and we can use opcode 0x90. In 64bit
3818 mode, we can't use 0x90 for xchg %eax, %eax since it should
3819 zero-extend %eax to %rax. */
3820 if (flag_code
== CODE_64BIT
3821 && t
->base_opcode
== 0x90
3822 && operand_type_equal (&i
.types
[0], &acc32
)
3823 && operand_type_equal (&i
.types
[1], &acc32
))
3827 /* If we swap operand in encoding, we either match
3828 the next one or reverse direction of operands. */
3829 if (t
->opcode_modifier
.s
)
3831 else if (t
->opcode_modifier
.d
)
3836 /* If we swap operand in encoding, we match the next one. */
3837 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3841 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3842 if (!operand_type_match (overlap0
, i
.types
[0])
3843 || !operand_type_match (overlap1
, i
.types
[1])
3845 && !operand_type_register_match (overlap0
, i
.types
[0],
3847 overlap1
, i
.types
[1],
3850 /* Check if other direction is valid ... */
3851 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3855 /* Try reversing direction of operands. */
3856 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3857 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3858 if (!operand_type_match (overlap0
, i
.types
[0])
3859 || !operand_type_match (overlap1
, i
.types
[1])
3861 && !operand_type_register_match (overlap0
,
3868 /* Does not match either direction. */
3871 /* found_reverse_match holds which of D or FloatDR
3873 if (t
->opcode_modifier
.d
)
3874 found_reverse_match
= Opcode_D
;
3875 else if (t
->opcode_modifier
.floatd
)
3876 found_reverse_match
= Opcode_FloatD
;
3878 found_reverse_match
= 0;
3879 if (t
->opcode_modifier
.floatr
)
3880 found_reverse_match
|= Opcode_FloatR
;
3884 /* Found a forward 2 operand match here. */
3885 switch (t
->operands
)
3888 overlap4
= operand_type_and (i
.types
[4],
3891 overlap3
= operand_type_and (i
.types
[3],
3894 overlap2
= operand_type_and (i
.types
[2],
3899 switch (t
->operands
)
3902 if (!operand_type_match (overlap4
, i
.types
[4])
3903 || !operand_type_register_match (overlap3
,
3911 if (!operand_type_match (overlap3
, i
.types
[3])
3913 && !operand_type_register_match (overlap2
,
3921 /* Here we make use of the fact that there are no
3922 reverse match 3 operand instructions, and all 3
3923 operand instructions only need to be checked for
3924 register consistency between operands 2 and 3. */
3925 if (!operand_type_match (overlap2
, i
.types
[2])
3927 && !operand_type_register_match (overlap1
,
3937 /* Found either forward/reverse 2, 3 or 4 operand match here:
3938 slip through to break. */
3940 if (!found_cpu_match
)
3942 found_reverse_match
= 0;
3946 /* We've found a match; break out of loop. */
3950 if (t
== current_templates
->end
)
3952 /* We found no match. */
3954 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3955 current_templates
->start
->name
);
3957 as_bad (_("suffix or operands invalid for `%s'"),
3958 current_templates
->start
->name
);
3962 if (!quiet_warnings
)
3965 && (i
.types
[0].bitfield
.jumpabsolute
3966 != operand_types
[0].bitfield
.jumpabsolute
))
3968 as_warn (_("indirect %s without `*'"), t
->name
);
3971 if (t
->opcode_modifier
.isprefix
3972 && t
->opcode_modifier
.ignoresize
)
3974 /* Warn them that a data or address size prefix doesn't
3975 affect assembly of the next line of code. */
3976 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3980 /* Copy the template we found. */
3983 if (addr_prefix_disp
!= -1)
3984 i
.tm
.operand_types
[addr_prefix_disp
]
3985 = operand_types
[addr_prefix_disp
];
3987 if (found_reverse_match
)
3989 /* If we found a reverse match we must alter the opcode
3990 direction bit. found_reverse_match holds bits to change
3991 (different for int & float insns). */
3993 i
.tm
.base_opcode
^= found_reverse_match
;
3995 i
.tm
.operand_types
[0] = operand_types
[1];
3996 i
.tm
.operand_types
[1] = operand_types
[0];
4005 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4006 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4008 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4010 as_bad (_("`%s' operand %d must use `%ses' segment"),
4016 /* There's only ever one segment override allowed per instruction.
4017 This instruction possibly has a legal segment override on the
4018 second operand, so copy the segment to where non-string
4019 instructions store it, allowing common code. */
4020 i
.seg
[0] = i
.seg
[1];
4022 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4024 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4026 as_bad (_("`%s' operand %d must use `%ses' segment"),
4037 process_suffix (void)
4039 /* If matched instruction specifies an explicit instruction mnemonic
4041 if (i
.tm
.opcode_modifier
.size16
)
4042 i
.suffix
= WORD_MNEM_SUFFIX
;
4043 else if (i
.tm
.opcode_modifier
.size32
)
4044 i
.suffix
= LONG_MNEM_SUFFIX
;
4045 else if (i
.tm
.opcode_modifier
.size64
)
4046 i
.suffix
= QWORD_MNEM_SUFFIX
;
4047 else if (i
.reg_operands
)
4049 /* If there's no instruction mnemonic suffix we try to invent one
4050 based on register operands. */
4053 /* We take i.suffix from the last register operand specified,
4054 Destination register type is more significant than source
4055 register type. crc32 in SSE4.2 prefers source register
4057 if (i
.tm
.base_opcode
== 0xf20f38f1)
4059 if (i
.types
[0].bitfield
.reg16
)
4060 i
.suffix
= WORD_MNEM_SUFFIX
;
4061 else if (i
.types
[0].bitfield
.reg32
)
4062 i
.suffix
= LONG_MNEM_SUFFIX
;
4063 else if (i
.types
[0].bitfield
.reg64
)
4064 i
.suffix
= QWORD_MNEM_SUFFIX
;
4066 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4068 if (i
.types
[0].bitfield
.reg8
)
4069 i
.suffix
= BYTE_MNEM_SUFFIX
;
4076 if (i
.tm
.base_opcode
== 0xf20f38f1
4077 || i
.tm
.base_opcode
== 0xf20f38f0)
4079 /* We have to know the operand size for crc32. */
4080 as_bad (_("ambiguous memory operand size for `%s`"),
4085 for (op
= i
.operands
; --op
>= 0;)
4086 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4088 if (i
.types
[op
].bitfield
.reg8
)
4090 i
.suffix
= BYTE_MNEM_SUFFIX
;
4093 else if (i
.types
[op
].bitfield
.reg16
)
4095 i
.suffix
= WORD_MNEM_SUFFIX
;
4098 else if (i
.types
[op
].bitfield
.reg32
)
4100 i
.suffix
= LONG_MNEM_SUFFIX
;
4103 else if (i
.types
[op
].bitfield
.reg64
)
4105 i
.suffix
= QWORD_MNEM_SUFFIX
;
4111 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4113 if (!check_byte_reg ())
4116 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4118 if (!check_long_reg ())
4121 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4124 && i
.tm
.opcode_modifier
.ignoresize
4125 && i
.tm
.opcode_modifier
.no_qsuf
)
4127 else if (!check_qword_reg ())
4130 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4132 if (!check_word_reg ())
4135 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4136 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4138 /* Skip if the instruction has x/y suffix. match_template
4139 should check if it is a valid suffix. */
4141 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4142 /* Do nothing if the instruction is going to ignore the prefix. */
4147 else if (i
.tm
.opcode_modifier
.defaultsize
4149 /* exclude fldenv/frstor/fsave/fstenv */
4150 && i
.tm
.opcode_modifier
.no_ssuf
)
4152 i
.suffix
= stackop_size
;
4154 else if (intel_syntax
4156 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4157 || i
.tm
.opcode_modifier
.jumpbyte
4158 || i
.tm
.opcode_modifier
.jumpintersegment
4159 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4160 && i
.tm
.extension_opcode
<= 3)))
4165 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4167 i
.suffix
= QWORD_MNEM_SUFFIX
;
4171 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4172 i
.suffix
= LONG_MNEM_SUFFIX
;
4175 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4176 i
.suffix
= WORD_MNEM_SUFFIX
;
4185 if (i
.tm
.opcode_modifier
.w
)
4187 as_bad (_("no instruction mnemonic suffix given and "
4188 "no register operands; can't size instruction"));
4194 unsigned int suffixes
;
4196 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4197 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4199 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4201 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4203 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4205 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4208 /* There are more than suffix matches. */
4209 if (i
.tm
.opcode_modifier
.w
4210 || ((suffixes
& (suffixes
- 1))
4211 && !i
.tm
.opcode_modifier
.defaultsize
4212 && !i
.tm
.opcode_modifier
.ignoresize
))
4214 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4220 /* Change the opcode based on the operand size given by i.suffix;
4221 We don't need to change things for byte insns. */
4224 && i
.suffix
!= BYTE_MNEM_SUFFIX
4225 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4226 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4228 /* It's not a byte, select word/dword operation. */
4229 if (i
.tm
.opcode_modifier
.w
)
4231 if (i
.tm
.opcode_modifier
.shortform
)
4232 i
.tm
.base_opcode
|= 8;
4234 i
.tm
.base_opcode
|= 1;
4237 /* Now select between word & dword operations via the operand
4238 size prefix, except for instructions that will ignore this
4240 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4242 /* The address size override prefix changes the size of the
4244 if ((flag_code
== CODE_32BIT
4245 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4246 || (flag_code
!= CODE_32BIT
4247 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4248 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4251 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4252 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4253 && !i
.tm
.opcode_modifier
.ignoresize
4254 && !i
.tm
.opcode_modifier
.floatmf
4255 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4256 || (flag_code
== CODE_64BIT
4257 && i
.tm
.opcode_modifier
.jumpbyte
)))
4259 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4261 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4262 prefix
= ADDR_PREFIX_OPCODE
;
4264 if (!add_prefix (prefix
))
4268 /* Set mode64 for an operand. */
4269 if (i
.suffix
== QWORD_MNEM_SUFFIX
4270 && flag_code
== CODE_64BIT
4271 && !i
.tm
.opcode_modifier
.norex64
)
4273 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4274 need rex64. cmpxchg8b is also a special case. */
4275 if (! (i
.operands
== 2
4276 && i
.tm
.base_opcode
== 0x90
4277 && i
.tm
.extension_opcode
== None
4278 && operand_type_equal (&i
.types
[0], &acc64
)
4279 && operand_type_equal (&i
.types
[1], &acc64
))
4280 && ! (i
.operands
== 1
4281 && i
.tm
.base_opcode
== 0xfc7
4282 && i
.tm
.extension_opcode
== 1
4283 && !operand_type_check (i
.types
[0], reg
)
4284 && operand_type_check (i
.types
[0], anymem
)))
4288 /* Size floating point instruction. */
4289 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4290 if (i
.tm
.opcode_modifier
.floatmf
)
4291 i
.tm
.base_opcode
^= 4;
4298 check_byte_reg (void)
4302 for (op
= i
.operands
; --op
>= 0;)
4304 /* If this is an eight bit register, it's OK. If it's the 16 or
4305 32 bit version of an eight bit register, we will just use the
4306 low portion, and that's OK too. */
4307 if (i
.types
[op
].bitfield
.reg8
)
4310 /* Don't generate this warning if not needed. */
4311 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4314 /* crc32 doesn't generate this warning. */
4315 if (i
.tm
.base_opcode
== 0xf20f38f0)
4318 if ((i
.types
[op
].bitfield
.reg16
4319 || i
.types
[op
].bitfield
.reg32
4320 || i
.types
[op
].bitfield
.reg64
)
4321 && i
.op
[op
].regs
->reg_num
< 4)
4323 /* Prohibit these changes in the 64bit mode, since the
4324 lowering is more complicated. */
4325 if (flag_code
== CODE_64BIT
4326 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4328 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4329 register_prefix
, i
.op
[op
].regs
->reg_name
,
4333 #if REGISTER_WARNINGS
4335 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4336 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4338 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4339 ? REGNAM_AL
- REGNAM_AX
4340 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4342 i
.op
[op
].regs
->reg_name
,
4347 /* Any other register is bad. */
4348 if (i
.types
[op
].bitfield
.reg16
4349 || i
.types
[op
].bitfield
.reg32
4350 || i
.types
[op
].bitfield
.reg64
4351 || i
.types
[op
].bitfield
.regmmx
4352 || i
.types
[op
].bitfield
.regxmm
4353 || i
.types
[op
].bitfield
.regymm
4354 || i
.types
[op
].bitfield
.sreg2
4355 || i
.types
[op
].bitfield
.sreg3
4356 || i
.types
[op
].bitfield
.control
4357 || i
.types
[op
].bitfield
.debug
4358 || i
.types
[op
].bitfield
.test
4359 || i
.types
[op
].bitfield
.floatreg
4360 || i
.types
[op
].bitfield
.floatacc
)
4362 as_bad (_("`%s%s' not allowed with `%s%c'"),
4364 i
.op
[op
].regs
->reg_name
,
4374 check_long_reg (void)
4378 for (op
= i
.operands
; --op
>= 0;)
4379 /* Reject eight bit registers, except where the template requires
4380 them. (eg. movzb) */
4381 if (i
.types
[op
].bitfield
.reg8
4382 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4383 || i
.tm
.operand_types
[op
].bitfield
.reg32
4384 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4386 as_bad (_("`%s%s' not allowed with `%s%c'"),
4388 i
.op
[op
].regs
->reg_name
,
4393 /* Warn if the e prefix on a general reg is missing. */
4394 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4395 && i
.types
[op
].bitfield
.reg16
4396 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4397 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4399 /* Prohibit these changes in the 64bit mode, since the
4400 lowering is more complicated. */
4401 if (flag_code
== CODE_64BIT
)
4403 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4404 register_prefix
, i
.op
[op
].regs
->reg_name
,
4408 #if REGISTER_WARNINGS
4410 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4412 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4414 i
.op
[op
].regs
->reg_name
,
4418 /* Warn if the r prefix on a general reg is missing. */
4419 else if (i
.types
[op
].bitfield
.reg64
4420 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4421 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4424 && i
.tm
.opcode_modifier
.toqword
4425 && !i
.types
[0].bitfield
.regxmm
)
4427 /* Convert to QWORD. We want REX byte. */
4428 i
.suffix
= QWORD_MNEM_SUFFIX
;
4432 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4433 register_prefix
, i
.op
[op
].regs
->reg_name
,
4442 check_qword_reg (void)
4446 for (op
= i
.operands
; --op
>= 0; )
4447 /* Reject eight bit registers, except where the template requires
4448 them. (eg. movzb) */
4449 if (i
.types
[op
].bitfield
.reg8
4450 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4451 || i
.tm
.operand_types
[op
].bitfield
.reg32
4452 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4454 as_bad (_("`%s%s' not allowed with `%s%c'"),
4456 i
.op
[op
].regs
->reg_name
,
4461 /* Warn if the e prefix on a general reg is missing. */
4462 else if ((i
.types
[op
].bitfield
.reg16
4463 || i
.types
[op
].bitfield
.reg32
)
4464 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4465 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4467 /* Prohibit these changes in the 64bit mode, since the
4468 lowering is more complicated. */
4470 && i
.tm
.opcode_modifier
.todword
4471 && !i
.types
[0].bitfield
.regxmm
)
4473 /* Convert to DWORD. We don't want REX byte. */
4474 i
.suffix
= LONG_MNEM_SUFFIX
;
4478 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4479 register_prefix
, i
.op
[op
].regs
->reg_name
,
4488 check_word_reg (void)
4491 for (op
= i
.operands
; --op
>= 0;)
4492 /* Reject eight bit registers, except where the template requires
4493 them. (eg. movzb) */
4494 if (i
.types
[op
].bitfield
.reg8
4495 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4496 || i
.tm
.operand_types
[op
].bitfield
.reg32
4497 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4499 as_bad (_("`%s%s' not allowed with `%s%c'"),
4501 i
.op
[op
].regs
->reg_name
,
4506 /* Warn if the e prefix on a general reg is present. */
4507 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4508 && i
.types
[op
].bitfield
.reg32
4509 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4510 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4512 /* Prohibit these changes in the 64bit mode, since the
4513 lowering is more complicated. */
4514 if (flag_code
== CODE_64BIT
)
4516 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4517 register_prefix
, i
.op
[op
].regs
->reg_name
,
4522 #if REGISTER_WARNINGS
4523 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4525 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4527 i
.op
[op
].regs
->reg_name
,
4535 update_imm (unsigned int j
)
4537 i386_operand_type overlap
= i
.types
[j
];
4538 if ((overlap
.bitfield
.imm8
4539 || overlap
.bitfield
.imm8s
4540 || overlap
.bitfield
.imm16
4541 || overlap
.bitfield
.imm32
4542 || overlap
.bitfield
.imm32s
4543 || overlap
.bitfield
.imm64
)
4544 && !operand_type_equal (&overlap
, &imm8
)
4545 && !operand_type_equal (&overlap
, &imm8s
)
4546 && !operand_type_equal (&overlap
, &imm16
)
4547 && !operand_type_equal (&overlap
, &imm32
)
4548 && !operand_type_equal (&overlap
, &imm32s
)
4549 && !operand_type_equal (&overlap
, &imm64
))
4553 i386_operand_type temp
;
4555 operand_type_set (&temp
, 0);
4556 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4558 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4559 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4561 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4562 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4563 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4565 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4566 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4569 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4572 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4573 || operand_type_equal (&overlap
, &imm16_32
)
4574 || operand_type_equal (&overlap
, &imm16_32s
))
4576 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4581 if (!operand_type_equal (&overlap
, &imm8
)
4582 && !operand_type_equal (&overlap
, &imm8s
)
4583 && !operand_type_equal (&overlap
, &imm16
)
4584 && !operand_type_equal (&overlap
, &imm32
)
4585 && !operand_type_equal (&overlap
, &imm32s
)
4586 && !operand_type_equal (&overlap
, &imm64
))
4588 as_bad (_("no instruction mnemonic suffix given; "
4589 "can't determine immediate size"));
4593 i
.types
[j
] = overlap
;
4603 /* Update the first 2 immediate operands. */
4604 n
= i
.operands
> 2 ? 2 : i
.operands
;
4607 for (j
= 0; j
< n
; j
++)
4608 if (update_imm (j
) == 0)
4611 /* The 3rd operand can't be immediate operand. */
4612 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4619 bad_implicit_operand (int xmm
)
4621 const char *reg
= xmm
? "xmm0" : "ymm0";
4623 as_bad (_("the last operand of `%s' must be `%s%s'"),
4624 i
.tm
.name
, register_prefix
, reg
);
4626 as_bad (_("the first operand of `%s' must be `%s%s'"),
4627 i
.tm
.name
, register_prefix
, reg
);
4632 process_operands (void)
4634 /* Default segment register this instruction will use for memory
4635 accesses. 0 means unknown. This is only for optimizing out
4636 unnecessary segment overrides. */
4637 const seg_entry
*default_seg
= 0;
4639 if (i
.tm
.opcode_modifier
.sse2avx
4640 && (i
.tm
.opcode_modifier
.vexnds
4641 || i
.tm
.opcode_modifier
.vexndd
))
4643 unsigned int dup
= i
.operands
;
4644 unsigned int dest
= dup
- 1;
4647 /* The destination must be an xmm register. */
4648 gas_assert (i
.reg_operands
4649 && MAX_OPERANDS
> dup
4650 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4652 if (i
.tm
.opcode_modifier
.firstxmm0
)
4654 /* The first operand is implicit and must be xmm0. */
4655 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4656 if (i
.op
[0].regs
->reg_num
!= 0)
4657 return bad_implicit_operand (1);
4659 if (i
.tm
.opcode_modifier
.vex3sources
)
4661 /* Keep xmm0 for instructions with VEX prefix and 3
4667 /* We remove the first xmm0 and keep the number of
4668 operands unchanged, which in fact duplicates the
4670 for (j
= 1; j
< i
.operands
; j
++)
4672 i
.op
[j
- 1] = i
.op
[j
];
4673 i
.types
[j
- 1] = i
.types
[j
];
4674 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4678 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4680 gas_assert ((MAX_OPERANDS
- 1) > dup
4681 && i
.tm
.opcode_modifier
.vex3sources
);
4683 /* Add the implicit xmm0 for instructions with VEX prefix
4685 for (j
= i
.operands
; j
> 0; j
--)
4687 i
.op
[j
] = i
.op
[j
- 1];
4688 i
.types
[j
] = i
.types
[j
- 1];
4689 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4692 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4693 i
.types
[0] = regxmm
;
4694 i
.tm
.operand_types
[0] = regxmm
;
4697 i
.reg_operands
+= 2;
4702 i
.op
[dup
] = i
.op
[dest
];
4703 i
.types
[dup
] = i
.types
[dest
];
4704 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4713 i
.op
[dup
] = i
.op
[dest
];
4714 i
.types
[dup
] = i
.types
[dest
];
4715 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4718 if (i
.tm
.opcode_modifier
.immext
)
4721 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4725 /* The first operand is implicit and must be xmm0/ymm0. */
4726 gas_assert (i
.reg_operands
4727 && (operand_type_equal (&i
.types
[0], ®xmm
)
4728 || operand_type_equal (&i
.types
[0], ®ymm
)));
4729 if (i
.op
[0].regs
->reg_num
!= 0)
4730 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4732 for (j
= 1; j
< i
.operands
; j
++)
4734 i
.op
[j
- 1] = i
.op
[j
];
4735 i
.types
[j
- 1] = i
.types
[j
];
4737 /* We need to adjust fields in i.tm since they are used by
4738 build_modrm_byte. */
4739 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4746 else if (i
.tm
.opcode_modifier
.regkludge
)
4748 /* The imul $imm, %reg instruction is converted into
4749 imul $imm, %reg, %reg, and the clr %reg instruction
4750 is converted into xor %reg, %reg. */
4752 unsigned int first_reg_op
;
4754 if (operand_type_check (i
.types
[0], reg
))
4758 /* Pretend we saw the extra register operand. */
4759 gas_assert (i
.reg_operands
== 1
4760 && i
.op
[first_reg_op
+ 1].regs
== 0);
4761 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4762 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4767 if (i
.tm
.opcode_modifier
.shortform
)
4769 if (i
.types
[0].bitfield
.sreg2
4770 || i
.types
[0].bitfield
.sreg3
)
4772 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4773 && i
.op
[0].regs
->reg_num
== 1)
4775 as_bad (_("you can't `pop %scs'"), register_prefix
);
4778 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4779 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4784 /* The register or float register operand is in operand
4788 if (i
.types
[0].bitfield
.floatreg
4789 || operand_type_check (i
.types
[0], reg
))
4793 /* Register goes in low 3 bits of opcode. */
4794 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4795 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4797 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4799 /* Warn about some common errors, but press on regardless.
4800 The first case can be generated by gcc (<= 2.8.1). */
4801 if (i
.operands
== 2)
4803 /* Reversed arguments on faddp, fsubp, etc. */
4804 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4805 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4806 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4810 /* Extraneous `l' suffix on fp insn. */
4811 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4812 register_prefix
, i
.op
[0].regs
->reg_name
);
4817 else if (i
.tm
.opcode_modifier
.modrm
)
4819 /* The opcode is completed (modulo i.tm.extension_opcode which
4820 must be put into the modrm byte). Now, we make the modrm and
4821 index base bytes based on all the info we've collected. */
4823 default_seg
= build_modrm_byte ();
4825 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4829 else if (i
.tm
.opcode_modifier
.isstring
)
4831 /* For the string instructions that allow a segment override
4832 on one of their operands, the default segment is ds. */
4836 if (i
.tm
.base_opcode
== 0x8d /* lea */
4839 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4841 /* If a segment was explicitly specified, and the specified segment
4842 is not the default, use an opcode prefix to select it. If we
4843 never figured out what the default segment is, then default_seg
4844 will be zero at this point, and the specified segment prefix will
4846 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4848 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4854 static const seg_entry
*
4855 build_modrm_byte (void)
4857 const seg_entry
*default_seg
= 0;
4858 unsigned int source
, dest
;
4861 /* The first operand of instructions with VEX prefix and 3 sources
4862 must be VEX_Imm4. */
4863 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4866 unsigned int nds
, reg
;
4868 if (i
.tm
.opcode_modifier
.veximmext
4869 && i
.tm
.opcode_modifier
.immext
)
4871 dest
= i
.operands
- 2;
4872 gas_assert (dest
== 3);
4875 dest
= i
.operands
- 1;
4878 /* This instruction must have 4 register operands
4879 or 3 register operands plus 1 memory operand.
4880 It must have VexNDS and VexImmExt. */
4881 gas_assert ((i
.reg_operands
== 4
4882 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4883 && i
.tm
.opcode_modifier
.vexnds
4884 && i
.tm
.opcode_modifier
.veximmext
4885 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4886 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4888 /* Generate an 8bit immediate operand to encode the register
4890 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4891 i
.op
[i
.operands
].imms
= exp
;
4892 i
.types
[i
.operands
] = imm8
;
4894 /* If VexW1 is set, the first operand is the source and
4895 the second operand is encoded in the immediate operand. */
4896 if (i
.tm
.opcode_modifier
.vexw1
)
4906 /* FMA4 swaps REG and NDS. */
4907 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4914 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4915 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4917 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4918 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4920 exp
->X_op
= O_constant
;
4922 = ((i
.op
[reg
].regs
->reg_num
4923 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4924 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4929 /* i.reg_operands MUST be the number of real register operands;
4930 implicit registers do not count. If there are 3 register
4931 operands, it must be a instruction with VexNDS. For a
4932 instruction with VexNDD, the destination register is encoded
4933 in VEX prefix. If there are 4 register operands, it must be
4934 a instruction with VEX prefix and 3 sources. */
4935 if (i
.mem_operands
== 0
4936 && ((i
.reg_operands
== 2
4937 && !i
.tm
.opcode_modifier
.vexndd
)
4938 || (i
.reg_operands
== 3
4939 && i
.tm
.opcode_modifier
.vexnds
)
4940 || (i
.reg_operands
== 4 && vex_3_sources
)))
4948 /* When there are 3 operands, one of them may be immediate,
4949 which may be the first or the last operand. Otherwise,
4950 the first operand must be shift count register (cl) or it
4951 is an instruction with VexNDS. */
4952 gas_assert (i
.imm_operands
== 1
4953 || (i
.imm_operands
== 0
4954 && (i
.tm
.opcode_modifier
.vexnds
4955 || i
.types
[0].bitfield
.shiftcount
)));
4956 if (operand_type_check (i
.types
[0], imm
)
4957 || i
.types
[0].bitfield
.shiftcount
)
4963 /* When there are 4 operands, the first two must be 8bit
4964 immediate operands. The source operand will be the 3rd
4967 For instructions with VexNDS, if the first operand
4968 an imm8, the source operand is the 2nd one. If the last
4969 operand is imm8, the source operand is the first one. */
4970 gas_assert ((i
.imm_operands
== 2
4971 && i
.types
[0].bitfield
.imm8
4972 && i
.types
[1].bitfield
.imm8
)
4973 || (i
.tm
.opcode_modifier
.vexnds
4974 && i
.imm_operands
== 1
4975 && (i
.types
[0].bitfield
.imm8
4976 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4977 if (i
.tm
.opcode_modifier
.vexnds
)
4979 if (i
.types
[0].bitfield
.imm8
)
4997 if (i
.tm
.opcode_modifier
.vexnds
)
4999 /* For instructions with VexNDS, the register-only
5000 source operand must be XMM or YMM register. It is
5001 encoded in VEX prefix. We need to clear RegMem bit
5002 before calling operand_type_equal. */
5003 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5004 op
.bitfield
.regmem
= 0;
5005 if ((dest
+ 1) >= i
.operands
5006 || (!operand_type_equal (&op
, ®xmm
)
5007 && !operand_type_equal (&op
, ®ymm
)))
5009 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5015 /* One of the register operands will be encoded in the i.tm.reg
5016 field, the other in the combined i.tm.mode and i.tm.regmem
5017 fields. If no form of this instruction supports a memory
5018 destination operand, then we assume the source operand may
5019 sometimes be a memory operand and so we need to store the
5020 destination in the i.rm.reg field. */
5021 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5022 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5024 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5025 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5026 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5028 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5033 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5034 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5035 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5037 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5040 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5042 if (!i
.types
[0].bitfield
.control
5043 && !i
.types
[1].bitfield
.control
)
5045 i
.rex
&= ~(REX_R
| REX_B
);
5046 add_prefix (LOCK_PREFIX_OPCODE
);
5050 { /* If it's not 2 reg operands... */
5055 unsigned int fake_zero_displacement
= 0;
5058 for (op
= 0; op
< i
.operands
; op
++)
5059 if (operand_type_check (i
.types
[op
], anymem
))
5061 gas_assert (op
< i
.operands
);
5065 if (i
.base_reg
== 0)
5068 if (!i
.disp_operands
)
5069 fake_zero_displacement
= 1;
5070 if (i
.index_reg
== 0)
5072 /* Operand is just <disp> */
5073 if (flag_code
== CODE_64BIT
)
5075 /* 64bit mode overwrites the 32bit absolute
5076 addressing by RIP relative addressing and
5077 absolute addressing is encoded by one of the
5078 redundant SIB forms. */
5079 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5080 i
.sib
.base
= NO_BASE_REGISTER
;
5081 i
.sib
.index
= NO_INDEX_REGISTER
;
5082 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5083 ? disp32s
: disp32
);
5085 else if ((flag_code
== CODE_16BIT
)
5086 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5088 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5089 i
.types
[op
] = disp16
;
5093 i
.rm
.regmem
= NO_BASE_REGISTER
;
5094 i
.types
[op
] = disp32
;
5097 else /* !i.base_reg && i.index_reg */
5099 if (i
.index_reg
->reg_num
== RegEiz
5100 || i
.index_reg
->reg_num
== RegRiz
)
5101 i
.sib
.index
= NO_INDEX_REGISTER
;
5103 i
.sib
.index
= i
.index_reg
->reg_num
;
5104 i
.sib
.base
= NO_BASE_REGISTER
;
5105 i
.sib
.scale
= i
.log2_scale_factor
;
5106 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5107 i
.types
[op
].bitfield
.disp8
= 0;
5108 i
.types
[op
].bitfield
.disp16
= 0;
5109 i
.types
[op
].bitfield
.disp64
= 0;
5110 if (flag_code
!= CODE_64BIT
)
5112 /* Must be 32 bit */
5113 i
.types
[op
].bitfield
.disp32
= 1;
5114 i
.types
[op
].bitfield
.disp32s
= 0;
5118 i
.types
[op
].bitfield
.disp32
= 0;
5119 i
.types
[op
].bitfield
.disp32s
= 1;
5121 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5125 /* RIP addressing for 64bit mode. */
5126 else if (i
.base_reg
->reg_num
== RegRip
||
5127 i
.base_reg
->reg_num
== RegEip
)
5129 i
.rm
.regmem
= NO_BASE_REGISTER
;
5130 i
.types
[op
].bitfield
.disp8
= 0;
5131 i
.types
[op
].bitfield
.disp16
= 0;
5132 i
.types
[op
].bitfield
.disp32
= 0;
5133 i
.types
[op
].bitfield
.disp32s
= 1;
5134 i
.types
[op
].bitfield
.disp64
= 0;
5135 i
.flags
[op
] |= Operand_PCrel
;
5136 if (! i
.disp_operands
)
5137 fake_zero_displacement
= 1;
5139 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5141 switch (i
.base_reg
->reg_num
)
5144 if (i
.index_reg
== 0)
5146 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5147 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5151 if (i
.index_reg
== 0)
5154 if (operand_type_check (i
.types
[op
], disp
) == 0)
5156 /* fake (%bp) into 0(%bp) */
5157 i
.types
[op
].bitfield
.disp8
= 1;
5158 fake_zero_displacement
= 1;
5161 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5162 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5164 default: /* (%si) -> 4 or (%di) -> 5 */
5165 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5167 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5169 else /* i.base_reg and 32/64 bit mode */
5171 if (flag_code
== CODE_64BIT
5172 && operand_type_check (i
.types
[op
], disp
))
5174 i386_operand_type temp
;
5175 operand_type_set (&temp
, 0);
5176 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5178 if (i
.prefix
[ADDR_PREFIX
] == 0)
5179 i
.types
[op
].bitfield
.disp32s
= 1;
5181 i
.types
[op
].bitfield
.disp32
= 1;
5184 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5185 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5187 i
.sib
.base
= i
.base_reg
->reg_num
;
5188 /* x86-64 ignores REX prefix bit here to avoid decoder
5190 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5193 if (i
.disp_operands
== 0)
5195 fake_zero_displacement
= 1;
5196 i
.types
[op
].bitfield
.disp8
= 1;
5199 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5203 i
.sib
.scale
= i
.log2_scale_factor
;
5204 if (i
.index_reg
== 0)
5206 /* <disp>(%esp) becomes two byte modrm with no index
5207 register. We've already stored the code for esp
5208 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5209 Any base register besides %esp will not use the
5210 extra modrm byte. */
5211 i
.sib
.index
= NO_INDEX_REGISTER
;
5215 if (i
.index_reg
->reg_num
== RegEiz
5216 || i
.index_reg
->reg_num
== RegRiz
)
5217 i
.sib
.index
= NO_INDEX_REGISTER
;
5219 i
.sib
.index
= i
.index_reg
->reg_num
;
5220 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5221 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5226 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5227 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5230 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5233 if (fake_zero_displacement
)
5235 /* Fakes a zero displacement assuming that i.types[op]
5236 holds the correct displacement size. */
5239 gas_assert (i
.op
[op
].disps
== 0);
5240 exp
= &disp_expressions
[i
.disp_operands
++];
5241 i
.op
[op
].disps
= exp
;
5242 exp
->X_op
= O_constant
;
5243 exp
->X_add_number
= 0;
5244 exp
->X_add_symbol
= (symbolS
*) 0;
5245 exp
->X_op_symbol
= (symbolS
*) 0;
5253 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5254 (if any) based on i.tm.extension_opcode. Again, we must be
5255 careful to make sure that segment/control/debug/test/MMX
5256 registers are coded into the i.rm.reg field. */
5260 unsigned int vex_reg
= ~0;
5262 for (op
= 0; op
< i
.operands
; op
++)
5263 if (i
.types
[op
].bitfield
.reg8
5264 || i
.types
[op
].bitfield
.reg16
5265 || i
.types
[op
].bitfield
.reg32
5266 || i
.types
[op
].bitfield
.reg64
5267 || i
.types
[op
].bitfield
.regmmx
5268 || i
.types
[op
].bitfield
.regxmm
5269 || i
.types
[op
].bitfield
.regymm
5270 || i
.types
[op
].bitfield
.sreg2
5271 || i
.types
[op
].bitfield
.sreg3
5272 || i
.types
[op
].bitfield
.control
5273 || i
.types
[op
].bitfield
.debug
5274 || i
.types
[op
].bitfield
.test
)
5279 else if (i
.tm
.opcode_modifier
.vexnds
)
5281 /* For instructions with VexNDS, the register-only
5282 source operand is encoded in VEX prefix. */
5283 gas_assert (mem
!= (unsigned int) ~0);
5288 gas_assert (op
< i
.operands
);
5293 gas_assert (vex_reg
< i
.operands
);
5296 else if (i
.tm
.opcode_modifier
.vexndd
)
5298 /* For instructions with VexNDD, there should be
5299 no memory operand and the register destination
5300 is encoded in VEX prefix. */
5301 gas_assert (i
.mem_operands
== 0
5302 && (op
+ 2) == i
.operands
);
5306 gas_assert (op
< i
.operands
);
5308 if (vex_reg
!= (unsigned int) ~0)
5310 gas_assert (i
.reg_operands
== 2);
5312 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5314 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5317 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5320 /* If there is an extension opcode to put here, the
5321 register number must be put into the regmem field. */
5322 if (i
.tm
.extension_opcode
!= None
)
5324 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5325 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5330 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5331 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5335 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5336 must set it to 3 to indicate this is a register operand
5337 in the regmem field. */
5338 if (!i
.mem_operands
)
5342 /* Fill in i.rm.reg field with extension opcode (if any). */
5343 if (i
.tm
.extension_opcode
!= None
)
5344 i
.rm
.reg
= i
.tm
.extension_opcode
;
5350 output_branch (void)
5355 relax_substateT subtype
;
5360 if (flag_code
== CODE_16BIT
)
5364 if (i
.prefix
[DATA_PREFIX
] != 0)
5370 /* Pentium4 branch hints. */
5371 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5372 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5377 if (i
.prefix
[REX_PREFIX
] != 0)
5383 if (i
.prefixes
!= 0 && !intel_syntax
)
5384 as_warn (_("skipping prefixes on this instruction"));
5386 /* It's always a symbol; End frag & setup for relax.
5387 Make sure there is enough room in this frag for the largest
5388 instruction we may generate in md_convert_frag. This is 2
5389 bytes for the opcode and room for the prefix and largest
5391 frag_grow (prefix
+ 2 + 4);
5392 /* Prefix and 1 opcode byte go in fr_fix. */
5393 p
= frag_more (prefix
+ 1);
5394 if (i
.prefix
[DATA_PREFIX
] != 0)
5395 *p
++ = DATA_PREFIX_OPCODE
;
5396 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5397 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5398 *p
++ = i
.prefix
[SEG_PREFIX
];
5399 if (i
.prefix
[REX_PREFIX
] != 0)
5400 *p
++ = i
.prefix
[REX_PREFIX
];
5401 *p
= i
.tm
.base_opcode
;
5403 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5404 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5405 else if (cpu_arch_flags
.bitfield
.cpui386
)
5406 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5408 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5411 sym
= i
.op
[0].disps
->X_add_symbol
;
5412 off
= i
.op
[0].disps
->X_add_number
;
5414 if (i
.op
[0].disps
->X_op
!= O_constant
5415 && i
.op
[0].disps
->X_op
!= O_symbol
)
5417 /* Handle complex expressions. */
5418 sym
= make_expr_symbol (i
.op
[0].disps
);
5422 /* 1 possible extra opcode + 4 byte displacement go in var part.
5423 Pass reloc in fr_var. */
5424 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5434 if (i
.tm
.opcode_modifier
.jumpbyte
)
5436 /* This is a loop or jecxz type instruction. */
5438 if (i
.prefix
[ADDR_PREFIX
] != 0)
5440 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5443 /* Pentium4 branch hints. */
5444 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5445 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5447 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5456 if (flag_code
== CODE_16BIT
)
5459 if (i
.prefix
[DATA_PREFIX
] != 0)
5461 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5471 if (i
.prefix
[REX_PREFIX
] != 0)
5473 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5477 if (i
.prefixes
!= 0 && !intel_syntax
)
5478 as_warn (_("skipping prefixes on this instruction"));
5480 p
= frag_more (1 + size
);
5481 *p
++ = i
.tm
.base_opcode
;
5483 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5484 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5486 /* All jumps handled here are signed, but don't use a signed limit
5487 check for 32 and 16 bit jumps as we want to allow wrap around at
5488 4G and 64k respectively. */
5490 fixP
->fx_signed
= 1;
5494 output_interseg_jump (void)
5502 if (flag_code
== CODE_16BIT
)
5506 if (i
.prefix
[DATA_PREFIX
] != 0)
5512 if (i
.prefix
[REX_PREFIX
] != 0)
5522 if (i
.prefixes
!= 0 && !intel_syntax
)
5523 as_warn (_("skipping prefixes on this instruction"));
5525 /* 1 opcode; 2 segment; offset */
5526 p
= frag_more (prefix
+ 1 + 2 + size
);
5528 if (i
.prefix
[DATA_PREFIX
] != 0)
5529 *p
++ = DATA_PREFIX_OPCODE
;
5531 if (i
.prefix
[REX_PREFIX
] != 0)
5532 *p
++ = i
.prefix
[REX_PREFIX
];
5534 *p
++ = i
.tm
.base_opcode
;
5535 if (i
.op
[1].imms
->X_op
== O_constant
)
5537 offsetT n
= i
.op
[1].imms
->X_add_number
;
5540 && !fits_in_unsigned_word (n
)
5541 && !fits_in_signed_word (n
))
5543 as_bad (_("16-bit jump out of range"));
5546 md_number_to_chars (p
, n
, size
);
5549 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5550 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5551 if (i
.op
[0].imms
->X_op
!= O_constant
)
5552 as_bad (_("can't handle non absolute segment in `%s'"),
5554 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5560 fragS
*insn_start_frag
;
5561 offsetT insn_start_off
;
5563 /* Tie dwarf2 debug info to the address at the start of the insn.
5564 We can't do this after the insn has been output as the current
5565 frag may have been closed off. eg. by frag_var. */
5566 dwarf2_emit_insn (0);
5568 insn_start_frag
= frag_now
;
5569 insn_start_off
= frag_now_fix ();
5572 if (i
.tm
.opcode_modifier
.jump
)
5574 else if (i
.tm
.opcode_modifier
.jumpbyte
5575 || i
.tm
.opcode_modifier
.jumpdword
)
5577 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5578 output_interseg_jump ();
5581 /* Output normal instructions here. */
5585 unsigned int prefix
;
5587 /* Since the VEX prefix contains the implicit prefix, we don't
5588 need the explicit prefix. */
5589 if (!i
.tm
.opcode_modifier
.vex
)
5591 switch (i
.tm
.opcode_length
)
5594 if (i
.tm
.base_opcode
& 0xff000000)
5596 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5601 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5603 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5604 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5607 if (prefix
!= REPE_PREFIX_OPCODE
5608 || (i
.prefix
[LOCKREP_PREFIX
]
5609 != REPE_PREFIX_OPCODE
))
5610 add_prefix (prefix
);
5613 add_prefix (prefix
);
5622 /* The prefix bytes. */
5623 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5625 FRAG_APPEND_1_CHAR (*q
);
5628 if (i
.tm
.opcode_modifier
.vex
)
5630 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5635 /* REX byte is encoded in VEX prefix. */
5639 FRAG_APPEND_1_CHAR (*q
);
5642 /* There should be no other prefixes for instructions
5647 /* Now the VEX prefix. */
5648 p
= frag_more (i
.vex
.length
);
5649 for (j
= 0; j
< i
.vex
.length
; j
++)
5650 p
[j
] = i
.vex
.bytes
[j
];
5653 /* Now the opcode; be careful about word order here! */
5654 if (i
.tm
.opcode_length
== 1)
5656 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5660 switch (i
.tm
.opcode_length
)
5664 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5674 /* Put out high byte first: can't use md_number_to_chars! */
5675 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5676 *p
= i
.tm
.base_opcode
& 0xff;
5679 /* Now the modrm byte and sib byte (if present). */
5680 if (i
.tm
.opcode_modifier
.modrm
)
5682 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5685 /* If i.rm.regmem == ESP (4)
5686 && i.rm.mode != (Register mode)
5688 ==> need second modrm byte. */
5689 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5691 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5692 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5694 | i
.sib
.scale
<< 6));
5697 if (i
.disp_operands
)
5698 output_disp (insn_start_frag
, insn_start_off
);
5701 output_imm (insn_start_frag
, insn_start_off
);
5707 pi ("" /*line*/, &i
);
5709 #endif /* DEBUG386 */
5712 /* Return the size of the displacement operand N. */
5715 disp_size (unsigned int n
)
5718 if (i
.types
[n
].bitfield
.disp64
)
5720 else if (i
.types
[n
].bitfield
.disp8
)
5722 else if (i
.types
[n
].bitfield
.disp16
)
5727 /* Return the size of the immediate operand N. */
5730 imm_size (unsigned int n
)
5733 if (i
.types
[n
].bitfield
.imm64
)
5735 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5737 else if (i
.types
[n
].bitfield
.imm16
)
5743 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5748 for (n
= 0; n
< i
.operands
; n
++)
5750 if (operand_type_check (i
.types
[n
], disp
))
5752 if (i
.op
[n
].disps
->X_op
== O_constant
)
5754 int size
= disp_size (n
);
5757 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5759 p
= frag_more (size
);
5760 md_number_to_chars (p
, val
, size
);
5764 enum bfd_reloc_code_real reloc_type
;
5765 int size
= disp_size (n
);
5766 int sign
= i
.types
[n
].bitfield
.disp32s
;
5767 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5769 /* We can't have 8 bit displacement here. */
5770 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5772 /* The PC relative address is computed relative
5773 to the instruction boundary, so in case immediate
5774 fields follows, we need to adjust the value. */
5775 if (pcrel
&& i
.imm_operands
)
5780 for (n1
= 0; n1
< i
.operands
; n1
++)
5781 if (operand_type_check (i
.types
[n1
], imm
))
5783 /* Only one immediate is allowed for PC
5784 relative address. */
5785 gas_assert (sz
== 0);
5787 i
.op
[n
].disps
->X_add_number
-= sz
;
5789 /* We should find the immediate. */
5790 gas_assert (sz
!= 0);
5793 p
= frag_more (size
);
5794 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5796 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5797 && (((reloc_type
== BFD_RELOC_32
5798 || reloc_type
== BFD_RELOC_X86_64_32S
5799 || (reloc_type
== BFD_RELOC_64
5801 && (i
.op
[n
].disps
->X_op
== O_symbol
5802 || (i
.op
[n
].disps
->X_op
== O_add
5803 && ((symbol_get_value_expression
5804 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5806 || reloc_type
== BFD_RELOC_32_PCREL
))
5810 if (insn_start_frag
== frag_now
)
5811 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5816 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5817 for (fr
= insn_start_frag
->fr_next
;
5818 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5820 add
+= p
- frag_now
->fr_literal
;
5825 reloc_type
= BFD_RELOC_386_GOTPC
;
5826 i
.op
[n
].imms
->X_add_number
+= add
;
5828 else if (reloc_type
== BFD_RELOC_64
)
5829 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5831 /* Don't do the adjustment for x86-64, as there
5832 the pcrel addressing is relative to the _next_
5833 insn, and that is taken care of in other code. */
5834 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5836 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5837 i
.op
[n
].disps
, pcrel
, reloc_type
);
5844 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5849 for (n
= 0; n
< i
.operands
; n
++)
5851 if (operand_type_check (i
.types
[n
], imm
))
5853 if (i
.op
[n
].imms
->X_op
== O_constant
)
5855 int size
= imm_size (n
);
5858 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5860 p
= frag_more (size
);
5861 md_number_to_chars (p
, val
, size
);
5865 /* Not absolute_section.
5866 Need a 32-bit fixup (don't support 8bit
5867 non-absolute imms). Try to support other
5869 enum bfd_reloc_code_real reloc_type
;
5870 int size
= imm_size (n
);
5873 if (i
.types
[n
].bitfield
.imm32s
5874 && (i
.suffix
== QWORD_MNEM_SUFFIX
5875 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5880 p
= frag_more (size
);
5881 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5883 /* This is tough to explain. We end up with this one if we
5884 * have operands that look like
5885 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5886 * obtain the absolute address of the GOT, and it is strongly
5887 * preferable from a performance point of view to avoid using
5888 * a runtime relocation for this. The actual sequence of
5889 * instructions often look something like:
5894 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5896 * The call and pop essentially return the absolute address
5897 * of the label .L66 and store it in %ebx. The linker itself
5898 * will ultimately change the first operand of the addl so
5899 * that %ebx points to the GOT, but to keep things simple, the
5900 * .o file must have this operand set so that it generates not
5901 * the absolute address of .L66, but the absolute address of
5902 * itself. This allows the linker itself simply treat a GOTPC
5903 * relocation as asking for a pcrel offset to the GOT to be
5904 * added in, and the addend of the relocation is stored in the
5905 * operand field for the instruction itself.
5907 * Our job here is to fix the operand so that it would add
5908 * the correct offset so that %ebx would point to itself. The
5909 * thing that is tricky is that .-.L66 will point to the
5910 * beginning of the instruction, so we need to further modify
5911 * the operand so that it will point to itself. There are
5912 * other cases where you have something like:
5914 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5916 * and here no correction would be required. Internally in
5917 * the assembler we treat operands of this form as not being
5918 * pcrel since the '.' is explicitly mentioned, and I wonder
5919 * whether it would simplify matters to do it this way. Who
5920 * knows. In earlier versions of the PIC patches, the
5921 * pcrel_adjust field was used to store the correction, but
5922 * since the expression is not pcrel, I felt it would be
5923 * confusing to do it this way. */
5925 if ((reloc_type
== BFD_RELOC_32
5926 || reloc_type
== BFD_RELOC_X86_64_32S
5927 || reloc_type
== BFD_RELOC_64
)
5929 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5930 && (i
.op
[n
].imms
->X_op
== O_symbol
5931 || (i
.op
[n
].imms
->X_op
== O_add
5932 && ((symbol_get_value_expression
5933 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5938 if (insn_start_frag
== frag_now
)
5939 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5944 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5945 for (fr
= insn_start_frag
->fr_next
;
5946 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5948 add
+= p
- frag_now
->fr_literal
;
5952 reloc_type
= BFD_RELOC_386_GOTPC
;
5954 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5956 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5957 i
.op
[n
].imms
->X_add_number
+= add
;
5959 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5960 i
.op
[n
].imms
, 0, reloc_type
);
5966 /* x86_cons_fix_new is called via the expression parsing code when a
5967 reloc is needed. We use this hook to get the correct .got reloc. */
5968 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5969 static int cons_sign
= -1;
5972 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5975 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5977 got_reloc
= NO_RELOC
;
5980 if (exp
->X_op
== O_secrel
)
5982 exp
->X_op
= O_symbol
;
5983 r
= BFD_RELOC_32_SECREL
;
5987 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5990 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5991 # define lex_got(reloc, adjust, types) NULL
5993 /* Parse operands of the form
5994 <symbol>@GOTOFF+<nnn>
5995 and similar .plt or .got references.
5997 If we find one, set up the correct relocation in RELOC and copy the
5998 input string, minus the `@GOTOFF' into a malloc'd buffer for
5999 parsing by the calling routine. Return this buffer, and if ADJUST
6000 is non-null set it to the length of the string we removed from the
6001 input line. Otherwise return NULL. */
6003 lex_got (enum bfd_reloc_code_real
*reloc
,
6005 i386_operand_type
*types
)
6007 /* Some of the relocations depend on the size of what field is to
6008 be relocated. But in our callers i386_immediate and i386_displacement
6009 we don't yet know the operand size (this will be set by insn
6010 matching). Hence we record the word32 relocation here,
6011 and adjust the reloc according to the real size in reloc(). */
6012 static const struct {
6014 const enum bfd_reloc_code_real rel
[2];
6015 const i386_operand_type types64
;
6018 BFD_RELOC_X86_64_PLTOFF64
},
6019 OPERAND_TYPE_IMM64
},
6020 { "PLT", { BFD_RELOC_386_PLT32
,
6021 BFD_RELOC_X86_64_PLT32
},
6022 OPERAND_TYPE_IMM32_32S_DISP32
},
6024 BFD_RELOC_X86_64_GOTPLT64
},
6025 OPERAND_TYPE_IMM64_DISP64
},
6026 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6027 BFD_RELOC_X86_64_GOTOFF64
},
6028 OPERAND_TYPE_IMM64_DISP64
},
6030 BFD_RELOC_X86_64_GOTPCREL
},
6031 OPERAND_TYPE_IMM32_32S_DISP32
},
6032 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6033 BFD_RELOC_X86_64_TLSGD
},
6034 OPERAND_TYPE_IMM32_32S_DISP32
},
6035 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6037 OPERAND_TYPE_NONE
},
6039 BFD_RELOC_X86_64_TLSLD
},
6040 OPERAND_TYPE_IMM32_32S_DISP32
},
6041 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6042 BFD_RELOC_X86_64_GOTTPOFF
},
6043 OPERAND_TYPE_IMM32_32S_DISP32
},
6044 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6045 BFD_RELOC_X86_64_TPOFF32
},
6046 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6047 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6049 OPERAND_TYPE_NONE
},
6050 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6051 BFD_RELOC_X86_64_DTPOFF32
},
6053 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6054 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6056 OPERAND_TYPE_NONE
},
6057 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6059 OPERAND_TYPE_NONE
},
6060 { "GOT", { BFD_RELOC_386_GOT32
,
6061 BFD_RELOC_X86_64_GOT32
},
6062 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6063 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6064 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6065 OPERAND_TYPE_IMM32_32S_DISP32
},
6066 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6067 BFD_RELOC_X86_64_TLSDESC_CALL
},
6068 OPERAND_TYPE_IMM32_32S_DISP32
},
6076 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6077 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6080 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6084 len
= strlen (gotrel
[j
].str
);
6085 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6087 if (gotrel
[j
].rel
[object_64bit
] != 0)
6090 char *tmpbuf
, *past_reloc
;
6092 *reloc
= gotrel
[j
].rel
[object_64bit
];
6098 if (flag_code
!= CODE_64BIT
)
6100 types
->bitfield
.imm32
= 1;
6101 types
->bitfield
.disp32
= 1;
6104 *types
= gotrel
[j
].types64
;
6107 if (GOT_symbol
== NULL
)
6108 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6110 /* The length of the first part of our input line. */
6111 first
= cp
- input_line_pointer
;
6113 /* The second part goes from after the reloc token until
6114 (and including) an end_of_line char or comma. */
6115 past_reloc
= cp
+ 1 + len
;
6117 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6119 second
= cp
+ 1 - past_reloc
;
6121 /* Allocate and copy string. The trailing NUL shouldn't
6122 be necessary, but be safe. */
6123 tmpbuf
= xmalloc (first
+ second
+ 2);
6124 memcpy (tmpbuf
, input_line_pointer
, first
);
6125 if (second
!= 0 && *past_reloc
!= ' ')
6126 /* Replace the relocation token with ' ', so that
6127 errors like foo@GOTOFF1 will be detected. */
6128 tmpbuf
[first
++] = ' ';
6129 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6130 tmpbuf
[first
+ second
] = '\0';
6134 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6135 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6140 /* Might be a symbol version string. Don't as_bad here. */
6145 x86_cons (expressionS
*exp
, int size
)
6147 intel_syntax
= -intel_syntax
;
6149 if (size
== 4 || (object_64bit
&& size
== 8))
6151 /* Handle @GOTOFF and the like in an expression. */
6153 char *gotfree_input_line
;
6156 save
= input_line_pointer
;
6157 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6158 if (gotfree_input_line
)
6159 input_line_pointer
= gotfree_input_line
;
6163 if (gotfree_input_line
)
6165 /* expression () has merrily parsed up to the end of line,
6166 or a comma - in the wrong buffer. Transfer how far
6167 input_line_pointer has moved to the right buffer. */
6168 input_line_pointer
= (save
6169 + (input_line_pointer
- gotfree_input_line
)
6171 free (gotfree_input_line
);
6172 if (exp
->X_op
== O_constant
6173 || exp
->X_op
== O_absent
6174 || exp
->X_op
== O_illegal
6175 || exp
->X_op
== O_register
6176 || exp
->X_op
== O_big
)
6178 char c
= *input_line_pointer
;
6179 *input_line_pointer
= 0;
6180 as_bad (_("missing or invalid expression `%s'"), save
);
6181 *input_line_pointer
= c
;
6188 intel_syntax
= -intel_syntax
;
6191 i386_intel_simplify (exp
);
6195 static void signed_cons (int size
)
6197 if (flag_code
== CODE_64BIT
)
6205 pe_directive_secrel (dummy
)
6206 int dummy ATTRIBUTE_UNUSED
;
6213 if (exp
.X_op
== O_symbol
)
6214 exp
.X_op
= O_secrel
;
6216 emit_expr (&exp
, 4);
6218 while (*input_line_pointer
++ == ',');
6220 input_line_pointer
--;
6221 demand_empty_rest_of_line ();
6226 i386_immediate (char *imm_start
)
6228 char *save_input_line_pointer
;
6229 char *gotfree_input_line
;
6232 i386_operand_type types
;
6234 operand_type_set (&types
, ~0);
6236 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6238 as_bad (_("at most %d immediate operands are allowed"),
6239 MAX_IMMEDIATE_OPERANDS
);
6243 exp
= &im_expressions
[i
.imm_operands
++];
6244 i
.op
[this_operand
].imms
= exp
;
6246 if (is_space_char (*imm_start
))
6249 save_input_line_pointer
= input_line_pointer
;
6250 input_line_pointer
= imm_start
;
6252 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6253 if (gotfree_input_line
)
6254 input_line_pointer
= gotfree_input_line
;
6256 exp_seg
= expression (exp
);
6259 if (*input_line_pointer
)
6260 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6262 input_line_pointer
= save_input_line_pointer
;
6263 if (gotfree_input_line
)
6265 free (gotfree_input_line
);
6267 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6268 exp
->X_op
= O_illegal
;
6271 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6275 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6276 i386_operand_type types
, const char *imm_start
)
6278 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6280 as_bad (_("missing or invalid immediate expression `%s'"),
6284 else if (exp
->X_op
== O_constant
)
6286 /* Size it properly later. */
6287 i
.types
[this_operand
].bitfield
.imm64
= 1;
6288 /* If BFD64, sign extend val. */
6289 if (!use_rela_relocations
6290 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6292 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6294 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6295 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6296 && exp_seg
!= absolute_section
6297 && exp_seg
!= text_section
6298 && exp_seg
!= data_section
6299 && exp_seg
!= bss_section
6300 && exp_seg
!= undefined_section
6301 && !bfd_is_com_section (exp_seg
))
6303 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6307 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6309 as_bad (_("illegal immediate register operand %s"), imm_start
);
6314 /* This is an address. The size of the address will be
6315 determined later, depending on destination register,
6316 suffix, or the default for the section. */
6317 i
.types
[this_operand
].bitfield
.imm8
= 1;
6318 i
.types
[this_operand
].bitfield
.imm16
= 1;
6319 i
.types
[this_operand
].bitfield
.imm32
= 1;
6320 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6321 i
.types
[this_operand
].bitfield
.imm64
= 1;
6322 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6330 i386_scale (char *scale
)
6333 char *save
= input_line_pointer
;
6335 input_line_pointer
= scale
;
6336 val
= get_absolute_expression ();
6341 i
.log2_scale_factor
= 0;
6344 i
.log2_scale_factor
= 1;
6347 i
.log2_scale_factor
= 2;
6350 i
.log2_scale_factor
= 3;
6354 char sep
= *input_line_pointer
;
6356 *input_line_pointer
= '\0';
6357 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6359 *input_line_pointer
= sep
;
6360 input_line_pointer
= save
;
6364 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6366 as_warn (_("scale factor of %d without an index register"),
6367 1 << i
.log2_scale_factor
);
6368 i
.log2_scale_factor
= 0;
6370 scale
= input_line_pointer
;
6371 input_line_pointer
= save
;
6376 i386_displacement (char *disp_start
, char *disp_end
)
6380 char *save_input_line_pointer
;
6381 char *gotfree_input_line
;
6383 i386_operand_type bigdisp
, types
= anydisp
;
6386 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6388 as_bad (_("at most %d displacement operands are allowed"),
6389 MAX_MEMORY_OPERANDS
);
6393 operand_type_set (&bigdisp
, 0);
6394 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6395 || (!current_templates
->start
->opcode_modifier
.jump
6396 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6398 bigdisp
.bitfield
.disp32
= 1;
6399 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6400 if (flag_code
== CODE_64BIT
)
6404 bigdisp
.bitfield
.disp32s
= 1;
6405 bigdisp
.bitfield
.disp64
= 1;
6408 else if ((flag_code
== CODE_16BIT
) ^ override
)
6410 bigdisp
.bitfield
.disp32
= 0;
6411 bigdisp
.bitfield
.disp16
= 1;
6416 /* For PC-relative branches, the width of the displacement
6417 is dependent upon data size, not address size. */
6418 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6419 if (flag_code
== CODE_64BIT
)
6421 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6422 bigdisp
.bitfield
.disp16
= 1;
6425 bigdisp
.bitfield
.disp32
= 1;
6426 bigdisp
.bitfield
.disp32s
= 1;
6432 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6434 : LONG_MNEM_SUFFIX
));
6435 bigdisp
.bitfield
.disp32
= 1;
6436 if ((flag_code
== CODE_16BIT
) ^ override
)
6438 bigdisp
.bitfield
.disp32
= 0;
6439 bigdisp
.bitfield
.disp16
= 1;
6443 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6446 exp
= &disp_expressions
[i
.disp_operands
];
6447 i
.op
[this_operand
].disps
= exp
;
6449 save_input_line_pointer
= input_line_pointer
;
6450 input_line_pointer
= disp_start
;
6451 END_STRING_AND_SAVE (disp_end
);
6453 #ifndef GCC_ASM_O_HACK
6454 #define GCC_ASM_O_HACK 0
6457 END_STRING_AND_SAVE (disp_end
+ 1);
6458 if (i
.types
[this_operand
].bitfield
.baseIndex
6459 && displacement_string_end
[-1] == '+')
6461 /* This hack is to avoid a warning when using the "o"
6462 constraint within gcc asm statements.
6465 #define _set_tssldt_desc(n,addr,limit,type) \
6466 __asm__ __volatile__ ( \
6468 "movw %w1,2+%0\n\t" \
6470 "movb %b1,4+%0\n\t" \
6471 "movb %4,5+%0\n\t" \
6472 "movb $0,6+%0\n\t" \
6473 "movb %h1,7+%0\n\t" \
6475 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6477 This works great except that the output assembler ends
6478 up looking a bit weird if it turns out that there is
6479 no offset. You end up producing code that looks like:
6492 So here we provide the missing zero. */
6494 *displacement_string_end
= '0';
6497 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6498 if (gotfree_input_line
)
6499 input_line_pointer
= gotfree_input_line
;
6501 exp_seg
= expression (exp
);
6504 if (*input_line_pointer
)
6505 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6507 RESTORE_END_STRING (disp_end
+ 1);
6509 input_line_pointer
= save_input_line_pointer
;
6510 if (gotfree_input_line
)
6512 free (gotfree_input_line
);
6514 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6515 exp
->X_op
= O_illegal
;
6518 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6520 RESTORE_END_STRING (disp_end
);
6526 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6527 i386_operand_type types
, const char *disp_start
)
6529 i386_operand_type bigdisp
;
6532 /* We do this to make sure that the section symbol is in
6533 the symbol table. We will ultimately change the relocation
6534 to be relative to the beginning of the section. */
6535 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6536 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6537 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6539 if (exp
->X_op
!= O_symbol
)
6542 if (S_IS_LOCAL (exp
->X_add_symbol
)
6543 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6544 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6545 exp
->X_op
= O_subtract
;
6546 exp
->X_op_symbol
= GOT_symbol
;
6547 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6548 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6549 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6550 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6552 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6555 else if (exp
->X_op
== O_absent
6556 || exp
->X_op
== O_illegal
6557 || exp
->X_op
== O_big
)
6560 as_bad (_("missing or invalid displacement expression `%s'"),
6565 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6566 else if (exp
->X_op
!= O_constant
6567 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6568 && exp_seg
!= absolute_section
6569 && exp_seg
!= text_section
6570 && exp_seg
!= data_section
6571 && exp_seg
!= bss_section
6572 && exp_seg
!= undefined_section
6573 && !bfd_is_com_section (exp_seg
))
6575 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6580 /* Check if this is a displacement only operand. */
6581 bigdisp
= i
.types
[this_operand
];
6582 bigdisp
.bitfield
.disp8
= 0;
6583 bigdisp
.bitfield
.disp16
= 0;
6584 bigdisp
.bitfield
.disp32
= 0;
6585 bigdisp
.bitfield
.disp32s
= 0;
6586 bigdisp
.bitfield
.disp64
= 0;
6587 if (operand_type_all_zero (&bigdisp
))
6588 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6594 /* Make sure the memory operand we've been dealt is valid.
6595 Return 1 on success, 0 on a failure. */
6598 i386_index_check (const char *operand_string
)
6601 const char *kind
= "base/index";
6602 #if INFER_ADDR_PREFIX
6608 if (current_templates
->start
->opcode_modifier
.isstring
6609 && !current_templates
->start
->opcode_modifier
.immext
6610 && (current_templates
->end
[-1].opcode_modifier
.isstring
6613 /* Memory operands of string insns are special in that they only allow
6614 a single register (rDI, rSI, or rBX) as their memory address. */
6615 unsigned int expected
;
6617 kind
= "string address";
6619 if (current_templates
->start
->opcode_modifier
.w
)
6621 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6623 if (!type
.bitfield
.baseindex
6624 || ((!i
.mem_operands
!= !intel_syntax
)
6625 && current_templates
->end
[-1].operand_types
[1]
6626 .bitfield
.baseindex
))
6627 type
= current_templates
->end
[-1].operand_types
[1];
6628 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6631 expected
= 3 /* rBX */;
6633 if (!i
.base_reg
|| i
.index_reg
6634 || operand_type_check (i
.types
[this_operand
], disp
))
6636 else if (!(flag_code
== CODE_64BIT
6637 ? i
.prefix
[ADDR_PREFIX
]
6638 ? i
.base_reg
->reg_type
.bitfield
.reg32
6639 : i
.base_reg
->reg_type
.bitfield
.reg64
6640 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6641 ? i
.base_reg
->reg_type
.bitfield
.reg32
6642 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6644 else if (i
.base_reg
->reg_num
!= expected
)
6651 for (j
= 0; j
< i386_regtab_size
; ++j
)
6652 if ((flag_code
== CODE_64BIT
6653 ? i
.prefix
[ADDR_PREFIX
]
6654 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6655 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6656 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6657 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6658 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6659 && i386_regtab
[j
].reg_num
== expected
)
6661 gas_assert (j
< i386_regtab_size
);
6662 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6664 intel_syntax
? '[' : '(',
6666 i386_regtab
[j
].reg_name
,
6667 intel_syntax
? ']' : ')');
6671 else if (flag_code
== CODE_64BIT
)
6674 && ((i
.prefix
[ADDR_PREFIX
] == 0
6675 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6676 || (i
.prefix
[ADDR_PREFIX
]
6677 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6679 || i
.base_reg
->reg_num
!=
6680 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6682 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6683 || (i
.prefix
[ADDR_PREFIX
] == 0
6684 && i
.index_reg
->reg_num
!= RegRiz
6685 && !i
.index_reg
->reg_type
.bitfield
.reg64
6687 || (i
.prefix
[ADDR_PREFIX
]
6688 && i
.index_reg
->reg_num
!= RegEiz
6689 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6694 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6698 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6699 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6701 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6702 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6704 && i
.base_reg
->reg_num
< 6
6705 && i
.index_reg
->reg_num
>= 6
6706 && i
.log2_scale_factor
== 0))))
6713 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6715 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6716 && i
.index_reg
->reg_num
!= RegEiz
)
6717 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6723 #if INFER_ADDR_PREFIX
6724 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6726 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6728 /* Change the size of any displacement too. At most one of
6729 Disp16 or Disp32 is set.
6730 FIXME. There doesn't seem to be any real need for separate
6731 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6732 Removing them would probably clean up the code quite a lot. */
6733 if (flag_code
!= CODE_64BIT
6734 && (i
.types
[this_operand
].bitfield
.disp16
6735 || i
.types
[this_operand
].bitfield
.disp32
))
6736 i
.types
[this_operand
]
6737 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6742 as_bad (_("`%s' is not a valid %s expression"),
6747 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6749 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6750 ? flag_code
== CODE_32BIT
6759 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6763 i386_att_operand (char *operand_string
)
6767 char *op_string
= operand_string
;
6769 if (is_space_char (*op_string
))
6772 /* We check for an absolute prefix (differentiating,
6773 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6774 if (*op_string
== ABSOLUTE_PREFIX
)
6777 if (is_space_char (*op_string
))
6779 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6782 /* Check if operand is a register. */
6783 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6785 i386_operand_type temp
;
6787 /* Check for a segment override by searching for ':' after a
6788 segment register. */
6790 if (is_space_char (*op_string
))
6792 if (*op_string
== ':'
6793 && (r
->reg_type
.bitfield
.sreg2
6794 || r
->reg_type
.bitfield
.sreg3
))
6799 i
.seg
[i
.mem_operands
] = &es
;
6802 i
.seg
[i
.mem_operands
] = &cs
;
6805 i
.seg
[i
.mem_operands
] = &ss
;
6808 i
.seg
[i
.mem_operands
] = &ds
;
6811 i
.seg
[i
.mem_operands
] = &fs
;
6814 i
.seg
[i
.mem_operands
] = &gs
;
6818 /* Skip the ':' and whitespace. */
6820 if (is_space_char (*op_string
))
6823 if (!is_digit_char (*op_string
)
6824 && !is_identifier_char (*op_string
)
6825 && *op_string
!= '('
6826 && *op_string
!= ABSOLUTE_PREFIX
)
6828 as_bad (_("bad memory operand `%s'"), op_string
);
6831 /* Handle case of %es:*foo. */
6832 if (*op_string
== ABSOLUTE_PREFIX
)
6835 if (is_space_char (*op_string
))
6837 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6839 goto do_memory_reference
;
6843 as_bad (_("junk `%s' after register"), op_string
);
6847 temp
.bitfield
.baseindex
= 0;
6848 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6850 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6851 i
.op
[this_operand
].regs
= r
;
6854 else if (*op_string
== REGISTER_PREFIX
)
6856 as_bad (_("bad register name `%s'"), op_string
);
6859 else if (*op_string
== IMMEDIATE_PREFIX
)
6862 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6864 as_bad (_("immediate operand illegal with absolute jump"));
6867 if (!i386_immediate (op_string
))
6870 else if (is_digit_char (*op_string
)
6871 || is_identifier_char (*op_string
)
6872 || *op_string
== '(')
6874 /* This is a memory reference of some sort. */
6877 /* Start and end of displacement string expression (if found). */
6878 char *displacement_string_start
;
6879 char *displacement_string_end
;
6881 do_memory_reference
:
6882 if ((i
.mem_operands
== 1
6883 && !current_templates
->start
->opcode_modifier
.isstring
)
6884 || i
.mem_operands
== 2)
6886 as_bad (_("too many memory references for `%s'"),
6887 current_templates
->start
->name
);
6891 /* Check for base index form. We detect the base index form by
6892 looking for an ')' at the end of the operand, searching
6893 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6895 base_string
= op_string
+ strlen (op_string
);
6898 if (is_space_char (*base_string
))
6901 /* If we only have a displacement, set-up for it to be parsed later. */
6902 displacement_string_start
= op_string
;
6903 displacement_string_end
= base_string
+ 1;
6905 if (*base_string
== ')')
6908 unsigned int parens_balanced
= 1;
6909 /* We've already checked that the number of left & right ()'s are
6910 equal, so this loop will not be infinite. */
6914 if (*base_string
== ')')
6916 if (*base_string
== '(')
6919 while (parens_balanced
);
6921 temp_string
= base_string
;
6923 /* Skip past '(' and whitespace. */
6925 if (is_space_char (*base_string
))
6928 if (*base_string
== ','
6929 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6932 displacement_string_end
= temp_string
;
6934 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6938 base_string
= end_op
;
6939 if (is_space_char (*base_string
))
6943 /* There may be an index reg or scale factor here. */
6944 if (*base_string
== ',')
6947 if (is_space_char (*base_string
))
6950 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6953 base_string
= end_op
;
6954 if (is_space_char (*base_string
))
6956 if (*base_string
== ',')
6959 if (is_space_char (*base_string
))
6962 else if (*base_string
!= ')')
6964 as_bad (_("expecting `,' or `)' "
6965 "after index register in `%s'"),
6970 else if (*base_string
== REGISTER_PREFIX
)
6972 as_bad (_("bad register name `%s'"), base_string
);
6976 /* Check for scale factor. */
6977 if (*base_string
!= ')')
6979 char *end_scale
= i386_scale (base_string
);
6984 base_string
= end_scale
;
6985 if (is_space_char (*base_string
))
6987 if (*base_string
!= ')')
6989 as_bad (_("expecting `)' "
6990 "after scale factor in `%s'"),
6995 else if (!i
.index_reg
)
6997 as_bad (_("expecting index register or scale factor "
6998 "after `,'; got '%c'"),
7003 else if (*base_string
!= ')')
7005 as_bad (_("expecting `,' or `)' "
7006 "after base register in `%s'"),
7011 else if (*base_string
== REGISTER_PREFIX
)
7013 as_bad (_("bad register name `%s'"), base_string
);
7018 /* If there's an expression beginning the operand, parse it,
7019 assuming displacement_string_start and
7020 displacement_string_end are meaningful. */
7021 if (displacement_string_start
!= displacement_string_end
)
7023 if (!i386_displacement (displacement_string_start
,
7024 displacement_string_end
))
7028 /* Special case for (%dx) while doing input/output op. */
7030 && operand_type_equal (&i
.base_reg
->reg_type
,
7031 ®16_inoutportreg
)
7033 && i
.log2_scale_factor
== 0
7034 && i
.seg
[i
.mem_operands
] == 0
7035 && !operand_type_check (i
.types
[this_operand
], disp
))
7037 i
.types
[this_operand
] = inoutportreg
;
7041 if (i386_index_check (operand_string
) == 0)
7043 i
.types
[this_operand
].bitfield
.mem
= 1;
7048 /* It's not a memory operand; argh! */
7049 as_bad (_("invalid char %s beginning operand %d `%s'"),
7050 output_invalid (*op_string
),
7055 return 1; /* Normal return. */
7058 /* md_estimate_size_before_relax()
7060 Called just before relax() for rs_machine_dependent frags. The x86
7061 assembler uses these frags to handle variable size jump
7064 Any symbol that is now undefined will not become defined.
7065 Return the correct fr_subtype in the frag.
7066 Return the initial "guess for variable size of frag" to caller.
7067 The guess is actually the growth beyond the fixed part. Whatever
7068 we do to grow the fixed or variable part contributes to our
7072 md_estimate_size_before_relax (fragP
, segment
)
7076 /* We've already got fragP->fr_subtype right; all we have to do is
7077 check for un-relaxable symbols. On an ELF system, we can't relax
7078 an externally visible symbol, because it may be overridden by a
7080 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7081 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7083 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7084 || S_IS_WEAK (fragP
->fr_symbol
)
7085 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7086 & BSF_GNU_INDIRECT_FUNCTION
))))
7088 #if defined (OBJ_COFF) && defined (TE_PE)
7089 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7090 && S_IS_WEAK (fragP
->fr_symbol
))
7094 /* Symbol is undefined in this segment, or we need to keep a
7095 reloc so that weak symbols can be overridden. */
7096 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7097 enum bfd_reloc_code_real reloc_type
;
7098 unsigned char *opcode
;
7101 if (fragP
->fr_var
!= NO_RELOC
)
7102 reloc_type
= fragP
->fr_var
;
7104 reloc_type
= BFD_RELOC_16_PCREL
;
7106 reloc_type
= BFD_RELOC_32_PCREL
;
7108 old_fr_fix
= fragP
->fr_fix
;
7109 opcode
= (unsigned char *) fragP
->fr_opcode
;
7111 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7114 /* Make jmp (0xeb) a (d)word displacement jump. */
7116 fragP
->fr_fix
+= size
;
7117 fix_new (fragP
, old_fr_fix
, size
,
7119 fragP
->fr_offset
, 1,
7125 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7127 /* Negate the condition, and branch past an
7128 unconditional jump. */
7131 /* Insert an unconditional jump. */
7133 /* We added two extra opcode bytes, and have a two byte
7135 fragP
->fr_fix
+= 2 + 2;
7136 fix_new (fragP
, old_fr_fix
+ 2, 2,
7138 fragP
->fr_offset
, 1,
7145 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7150 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7152 fragP
->fr_offset
, 1,
7154 fixP
->fx_signed
= 1;
7158 /* This changes the byte-displacement jump 0x7N
7159 to the (d)word-displacement jump 0x0f,0x8N. */
7160 opcode
[1] = opcode
[0] + 0x10;
7161 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7162 /* We've added an opcode byte. */
7163 fragP
->fr_fix
+= 1 + size
;
7164 fix_new (fragP
, old_fr_fix
+ 1, size
,
7166 fragP
->fr_offset
, 1,
7171 BAD_CASE (fragP
->fr_subtype
);
7175 return fragP
->fr_fix
- old_fr_fix
;
7178 /* Guess size depending on current relax state. Initially the relax
7179 state will correspond to a short jump and we return 1, because
7180 the variable part of the frag (the branch offset) is one byte
7181 long. However, we can relax a section more than once and in that
7182 case we must either set fr_subtype back to the unrelaxed state,
7183 or return the value for the appropriate branch. */
7184 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7187 /* Called after relax() is finished.
7189 In: Address of frag.
7190 fr_type == rs_machine_dependent.
7191 fr_subtype is what the address relaxed to.
7193 Out: Any fixSs and constants are set up.
7194 Caller will turn frag into a ".space 0". */
7197 md_convert_frag (abfd
, sec
, fragP
)
7198 bfd
*abfd ATTRIBUTE_UNUSED
;
7199 segT sec ATTRIBUTE_UNUSED
;
7202 unsigned char *opcode
;
7203 unsigned char *where_to_put_displacement
= NULL
;
7204 offsetT target_address
;
7205 offsetT opcode_address
;
7206 unsigned int extension
= 0;
7207 offsetT displacement_from_opcode_start
;
7209 opcode
= (unsigned char *) fragP
->fr_opcode
;
7211 /* Address we want to reach in file space. */
7212 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7214 /* Address opcode resides at in file space. */
7215 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7217 /* Displacement from opcode start to fill into instruction. */
7218 displacement_from_opcode_start
= target_address
- opcode_address
;
7220 if ((fragP
->fr_subtype
& BIG
) == 0)
7222 /* Don't have to change opcode. */
7223 extension
= 1; /* 1 opcode + 1 displacement */
7224 where_to_put_displacement
= &opcode
[1];
7228 if (no_cond_jump_promotion
7229 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7230 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7231 _("long jump required"));
7233 switch (fragP
->fr_subtype
)
7235 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7236 extension
= 4; /* 1 opcode + 4 displacement */
7238 where_to_put_displacement
= &opcode
[1];
7241 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7242 extension
= 2; /* 1 opcode + 2 displacement */
7244 where_to_put_displacement
= &opcode
[1];
7247 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7248 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7249 extension
= 5; /* 2 opcode + 4 displacement */
7250 opcode
[1] = opcode
[0] + 0x10;
7251 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7252 where_to_put_displacement
= &opcode
[2];
7255 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7256 extension
= 3; /* 2 opcode + 2 displacement */
7257 opcode
[1] = opcode
[0] + 0x10;
7258 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7259 where_to_put_displacement
= &opcode
[2];
7262 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7267 where_to_put_displacement
= &opcode
[3];
7271 BAD_CASE (fragP
->fr_subtype
);
7276 /* If size if less then four we are sure that the operand fits,
7277 but if it's 4, then it could be that the displacement is larger
7279 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7281 && ((addressT
) (displacement_from_opcode_start
- extension
7282 + ((addressT
) 1 << 31))
7283 > (((addressT
) 2 << 31) - 1)))
7285 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7286 _("jump target out of range"));
7287 /* Make us emit 0. */
7288 displacement_from_opcode_start
= extension
;
7290 /* Now put displacement after opcode. */
7291 md_number_to_chars ((char *) where_to_put_displacement
,
7292 (valueT
) (displacement_from_opcode_start
- extension
),
7293 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7294 fragP
->fr_fix
+= extension
;
7297 /* Apply a fixup (fixS) to segment data, once it has been determined
7298 by our caller that we have all the info we need to fix it up.
7300 On the 386, immediates, displacements, and data pointers are all in
7301 the same (little-endian) format, so we don't need to care about which
7305 md_apply_fix (fixP
, valP
, seg
)
7306 /* The fix we're to put in. */
7308 /* Pointer to the value of the bits. */
7310 /* Segment fix is from. */
7311 segT seg ATTRIBUTE_UNUSED
;
7313 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7314 valueT value
= *valP
;
7316 #if !defined (TE_Mach)
7319 switch (fixP
->fx_r_type
)
7325 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7328 case BFD_RELOC_X86_64_32S
:
7329 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7332 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7335 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7340 if (fixP
->fx_addsy
!= NULL
7341 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7342 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7343 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7344 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7345 && !use_rela_relocations
)
7347 /* This is a hack. There should be a better way to handle this.
7348 This covers for the fact that bfd_install_relocation will
7349 subtract the current location (for partial_inplace, PC relative
7350 relocations); see more below. */
7354 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7357 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7359 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7362 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7365 || (symbol_section_p (fixP
->fx_addsy
)
7366 && sym_seg
!= absolute_section
))
7367 && !generic_force_reloc (fixP
))
7369 /* Yes, we add the values in twice. This is because
7370 bfd_install_relocation subtracts them out again. I think
7371 bfd_install_relocation is broken, but I don't dare change
7373 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7377 #if defined (OBJ_COFF) && defined (TE_PE)
7378 /* For some reason, the PE format does not store a
7379 section address offset for a PC relative symbol. */
7380 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7381 || S_IS_WEAK (fixP
->fx_addsy
))
7382 value
+= md_pcrel_from (fixP
);
7385 #if defined (OBJ_COFF) && defined (TE_PE)
7386 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7388 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7392 /* Fix a few things - the dynamic linker expects certain values here,
7393 and we must not disappoint it. */
7394 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7395 if (IS_ELF
&& fixP
->fx_addsy
)
7396 switch (fixP
->fx_r_type
)
7398 case BFD_RELOC_386_PLT32
:
7399 case BFD_RELOC_X86_64_PLT32
:
7400 /* Make the jump instruction point to the address of the operand. At
7401 runtime we merely add the offset to the actual PLT entry. */
7405 case BFD_RELOC_386_TLS_GD
:
7406 case BFD_RELOC_386_TLS_LDM
:
7407 case BFD_RELOC_386_TLS_IE_32
:
7408 case BFD_RELOC_386_TLS_IE
:
7409 case BFD_RELOC_386_TLS_GOTIE
:
7410 case BFD_RELOC_386_TLS_GOTDESC
:
7411 case BFD_RELOC_X86_64_TLSGD
:
7412 case BFD_RELOC_X86_64_TLSLD
:
7413 case BFD_RELOC_X86_64_GOTTPOFF
:
7414 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7415 value
= 0; /* Fully resolved at runtime. No addend. */
7417 case BFD_RELOC_386_TLS_LE
:
7418 case BFD_RELOC_386_TLS_LDO_32
:
7419 case BFD_RELOC_386_TLS_LE_32
:
7420 case BFD_RELOC_X86_64_DTPOFF32
:
7421 case BFD_RELOC_X86_64_DTPOFF64
:
7422 case BFD_RELOC_X86_64_TPOFF32
:
7423 case BFD_RELOC_X86_64_TPOFF64
:
7424 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7427 case BFD_RELOC_386_TLS_DESC_CALL
:
7428 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7429 value
= 0; /* Fully resolved at runtime. No addend. */
7430 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7434 case BFD_RELOC_386_GOT32
:
7435 case BFD_RELOC_X86_64_GOT32
:
7436 value
= 0; /* Fully resolved at runtime. No addend. */
7439 case BFD_RELOC_VTABLE_INHERIT
:
7440 case BFD_RELOC_VTABLE_ENTRY
:
7447 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7449 #endif /* !defined (TE_Mach) */
7451 /* Are we finished with this relocation now? */
7452 if (fixP
->fx_addsy
== NULL
)
7454 #if defined (OBJ_COFF) && defined (TE_PE)
7455 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7458 /* Remember value for tc_gen_reloc. */
7459 fixP
->fx_addnumber
= value
;
7460 /* Clear out the frag for now. */
7464 else if (use_rela_relocations
)
7466 fixP
->fx_no_overflow
= 1;
7467 /* Remember value for tc_gen_reloc. */
7468 fixP
->fx_addnumber
= value
;
7472 md_number_to_chars (p
, value
, fixP
->fx_size
);
7476 md_atof (int type
, char *litP
, int *sizeP
)
7478 /* This outputs the LITTLENUMs in REVERSE order;
7479 in accord with the bigendian 386. */
7480 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7483 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7486 output_invalid (int c
)
7489 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7492 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7493 "(0x%x)", (unsigned char) c
);
7494 return output_invalid_buf
;
7497 /* REG_STRING starts *before* REGISTER_PREFIX. */
7499 static const reg_entry
*
7500 parse_real_register (char *reg_string
, char **end_op
)
7502 char *s
= reg_string
;
7504 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7507 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7508 if (*s
== REGISTER_PREFIX
)
7511 if (is_space_char (*s
))
7515 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7517 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7518 return (const reg_entry
*) NULL
;
7522 /* For naked regs, make sure that we are not dealing with an identifier.
7523 This prevents confusing an identifier like `eax_var' with register
7525 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7526 return (const reg_entry
*) NULL
;
7530 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7532 /* Handle floating point regs, allowing spaces in the (i) part. */
7533 if (r
== i386_regtab
/* %st is first entry of table */)
7535 if (is_space_char (*s
))
7540 if (is_space_char (*s
))
7542 if (*s
>= '0' && *s
<= '7')
7546 if (is_space_char (*s
))
7551 r
= hash_find (reg_hash
, "st(0)");
7556 /* We have "%st(" then garbage. */
7557 return (const reg_entry
*) NULL
;
7561 if (r
== NULL
|| allow_pseudo_reg
)
7564 if (operand_type_all_zero (&r
->reg_type
))
7565 return (const reg_entry
*) NULL
;
7567 if ((r
->reg_type
.bitfield
.reg32
7568 || r
->reg_type
.bitfield
.sreg3
7569 || r
->reg_type
.bitfield
.control
7570 || r
->reg_type
.bitfield
.debug
7571 || r
->reg_type
.bitfield
.test
)
7572 && !cpu_arch_flags
.bitfield
.cpui386
)
7573 return (const reg_entry
*) NULL
;
7575 if (r
->reg_type
.bitfield
.floatreg
7576 && !cpu_arch_flags
.bitfield
.cpu8087
7577 && !cpu_arch_flags
.bitfield
.cpu287
7578 && !cpu_arch_flags
.bitfield
.cpu387
)
7579 return (const reg_entry
*) NULL
;
7581 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7582 return (const reg_entry
*) NULL
;
7584 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7585 return (const reg_entry
*) NULL
;
7587 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7588 return (const reg_entry
*) NULL
;
7590 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7591 if (!allow_index_reg
7592 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7593 return (const reg_entry
*) NULL
;
7595 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7596 || r
->reg_type
.bitfield
.reg64
)
7597 && (!cpu_arch_flags
.bitfield
.cpulm
7598 || !operand_type_equal (&r
->reg_type
, &control
))
7599 && flag_code
!= CODE_64BIT
)
7600 return (const reg_entry
*) NULL
;
7602 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7603 return (const reg_entry
*) NULL
;
7608 /* REG_STRING starts *before* REGISTER_PREFIX. */
7610 static const reg_entry
*
7611 parse_register (char *reg_string
, char **end_op
)
7615 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7616 r
= parse_real_register (reg_string
, end_op
);
7621 char *save
= input_line_pointer
;
7625 input_line_pointer
= reg_string
;
7626 c
= get_symbol_end ();
7627 symbolP
= symbol_find (reg_string
);
7628 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7630 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7632 know (e
->X_op
== O_register
);
7633 know (e
->X_add_number
>= 0
7634 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7635 r
= i386_regtab
+ e
->X_add_number
;
7636 *end_op
= input_line_pointer
;
7638 *input_line_pointer
= c
;
7639 input_line_pointer
= save
;
7645 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7648 char *end
= input_line_pointer
;
7651 r
= parse_register (name
, &input_line_pointer
);
7652 if (r
&& end
<= input_line_pointer
)
7654 *nextcharP
= *input_line_pointer
;
7655 *input_line_pointer
= 0;
7656 e
->X_op
= O_register
;
7657 e
->X_add_number
= r
- i386_regtab
;
7660 input_line_pointer
= end
;
7662 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7666 md_operand (expressionS
*e
)
7671 switch (*input_line_pointer
)
7673 case REGISTER_PREFIX
:
7674 r
= parse_real_register (input_line_pointer
, &end
);
7677 e
->X_op
= O_register
;
7678 e
->X_add_number
= r
- i386_regtab
;
7679 input_line_pointer
= end
;
7684 gas_assert (intel_syntax
);
7685 end
= input_line_pointer
++;
7687 if (*input_line_pointer
== ']')
7689 ++input_line_pointer
;
7690 e
->X_op_symbol
= make_expr_symbol (e
);
7691 e
->X_add_symbol
= NULL
;
7692 e
->X_add_number
= 0;
7698 input_line_pointer
= end
;
7705 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7706 const char *md_shortopts
= "kVQ:sqn";
7708 const char *md_shortopts
= "qn";
7711 #define OPTION_32 (OPTION_MD_BASE + 0)
7712 #define OPTION_64 (OPTION_MD_BASE + 1)
7713 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7714 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7715 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7716 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7717 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7718 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7719 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7720 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7721 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7722 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7724 struct option md_longopts
[] =
7726 {"32", no_argument
, NULL
, OPTION_32
},
7727 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7728 || defined (TE_PE) || defined (TE_PEP))
7729 {"64", no_argument
, NULL
, OPTION_64
},
7731 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7732 {"march", required_argument
, NULL
, OPTION_MARCH
},
7733 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7734 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7735 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7736 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7737 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7738 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7739 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7740 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7741 {NULL
, no_argument
, NULL
, 0}
7743 size_t md_longopts_size
= sizeof (md_longopts
);
7746 md_parse_option (int c
, char *arg
)
7754 optimize_align_code
= 0;
7761 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7762 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7763 should be emitted or not. FIXME: Not implemented. */
7767 /* -V: SVR4 argument to print version ID. */
7769 print_version_id ();
7772 /* -k: Ignore for FreeBSD compatibility. */
7777 /* -s: On i386 Solaris, this tells the native assembler to use
7778 .stab instead of .stab.excl. We always use .stab anyhow. */
7781 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7782 || defined (TE_PE) || defined (TE_PEP))
7785 const char **list
, **l
;
7787 list
= bfd_target_list ();
7788 for (l
= list
; *l
!= NULL
; l
++)
7789 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7790 || strcmp (*l
, "coff-x86-64") == 0
7791 || strcmp (*l
, "pe-x86-64") == 0
7792 || strcmp (*l
, "pei-x86-64") == 0)
7794 default_arch
= "x86_64";
7798 as_fatal (_("No compiled in support for x86_64"));
7805 default_arch
= "i386";
7809 #ifdef SVR4_COMMENT_CHARS
7814 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7816 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7820 i386_comment_chars
= n
;
7826 arch
= xstrdup (arg
);
7830 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7831 next
= strchr (arch
, '+');
7834 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7836 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7839 cpu_arch_name
= cpu_arch
[i
].name
;
7840 cpu_sub_arch_name
= NULL
;
7841 cpu_arch_flags
= cpu_arch
[i
].flags
;
7842 cpu_arch_isa
= cpu_arch
[i
].type
;
7843 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7844 if (!cpu_arch_tune_set
)
7846 cpu_arch_tune
= cpu_arch_isa
;
7847 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7851 else if (*cpu_arch
[i
].name
== '.'
7852 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7854 /* ISA entension. */
7855 i386_cpu_flags flags
;
7857 if (strncmp (arch
, "no", 2))
7858 flags
= cpu_flags_or (cpu_arch_flags
,
7861 flags
= cpu_flags_and_not (cpu_arch_flags
,
7863 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7865 if (cpu_sub_arch_name
)
7867 char *name
= cpu_sub_arch_name
;
7868 cpu_sub_arch_name
= concat (name
,
7870 (const char *) NULL
);
7874 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7875 cpu_arch_flags
= flags
;
7881 if (i
>= ARRAY_SIZE (cpu_arch
))
7882 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7886 while (next
!= NULL
);
7891 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7892 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7894 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7896 cpu_arch_tune_set
= 1;
7897 cpu_arch_tune
= cpu_arch
[i
].type
;
7898 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7902 if (i
>= ARRAY_SIZE (cpu_arch
))
7903 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7906 case OPTION_MMNEMONIC
:
7907 if (strcasecmp (arg
, "att") == 0)
7909 else if (strcasecmp (arg
, "intel") == 0)
7912 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7915 case OPTION_MSYNTAX
:
7916 if (strcasecmp (arg
, "att") == 0)
7918 else if (strcasecmp (arg
, "intel") == 0)
7921 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7924 case OPTION_MINDEX_REG
:
7925 allow_index_reg
= 1;
7928 case OPTION_MNAKED_REG
:
7929 allow_naked_reg
= 1;
7932 case OPTION_MOLD_GCC
:
7936 case OPTION_MSSE2AVX
:
7940 case OPTION_MSSE_CHECK
:
7941 if (strcasecmp (arg
, "error") == 0)
7942 sse_check
= sse_check_error
;
7943 else if (strcasecmp (arg
, "warning") == 0)
7944 sse_check
= sse_check_warning
;
7945 else if (strcasecmp (arg
, "none") == 0)
7946 sse_check
= sse_check_none
;
7948 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7958 md_show_usage (stream
)
7961 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7962 fprintf (stream
, _("\
7964 -V print assembler version number\n\
7967 fprintf (stream
, _("\
7968 -n Do not optimize code alignment\n\
7969 -q quieten some warnings\n"));
7970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7971 fprintf (stream
, _("\
7974 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7975 || defined (TE_PE) || defined (TE_PEP))
7976 fprintf (stream
, _("\
7977 --32/--64 generate 32bit/64bit code\n"));
7979 #ifdef SVR4_COMMENT_CHARS
7980 fprintf (stream
, _("\
7981 --divide do not treat `/' as a comment character\n"));
7983 fprintf (stream
, _("\
7984 --divide ignored\n"));
7986 fprintf (stream
, _("\
7987 -march=CPU[,+EXTENSION...]\n\
7988 generate code for CPU and EXTENSION, CPU is one of:\n\
7989 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7990 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7991 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
7992 amdfam10, generic32, generic64\n\
7993 EXTENSION is combination of:\n\
7994 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
7995 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
7996 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7997 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
7998 svme, abm, padlock, fma4\n"));
7999 fprintf (stream
, _("\
8000 -mtune=CPU optimize for CPU, CPU is one of:\n\
8001 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8002 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8003 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8004 amdfam10, generic32, generic64\n"));
8005 fprintf (stream
, _("\
8006 -msse2avx encode SSE instructions with VEX prefix\n"));
8007 fprintf (stream
, _("\
8008 -msse-check=[none|error|warning]\n\
8009 check SSE instructions\n"));
8010 fprintf (stream
, _("\
8011 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8012 fprintf (stream
, _("\
8013 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8014 fprintf (stream
, _("\
8015 -mindex-reg support pseudo index registers\n"));
8016 fprintf (stream
, _("\
8017 -mnaked-reg don't require `%%' prefix for registers\n"));
8018 fprintf (stream
, _("\
8019 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8022 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8023 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8024 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8026 /* Pick the target format to use. */
8029 i386_target_format (void)
8031 if (!strcmp (default_arch
, "x86_64"))
8033 set_code_flag (CODE_64BIT
);
8034 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8036 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8037 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8038 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8039 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8040 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8041 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8042 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8043 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8044 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8045 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8046 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8048 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8050 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8051 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8052 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8053 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8054 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8055 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8056 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8057 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8058 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8059 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8062 else if (!strcmp (default_arch
, "i386"))
8064 set_code_flag (CODE_32BIT
);
8065 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8067 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8068 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8069 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8071 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8073 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8074 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8075 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8079 as_fatal (_("Unknown architecture"));
8080 switch (OUTPUT_FLAVOR
)
8082 #if defined (TE_PE) || defined (TE_PEP)
8083 case bfd_target_coff_flavour
:
8084 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8086 #ifdef OBJ_MAYBE_AOUT
8087 case bfd_target_aout_flavour
:
8088 return AOUT_TARGET_FORMAT
;
8091 case bfd_target_coff_flavour
:
8093 #elif defined (OBJ_MAYBE_COFF)
8094 case bfd_target_coff_flavour
:
8097 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8098 case bfd_target_elf_flavour
:
8100 if (flag_code
== CODE_64BIT
)
8103 use_rela_relocations
= 1;
8105 if (cpu_arch_isa_flags
.bitfield
.cpul1om
)
8107 if (flag_code
!= CODE_64BIT
)
8108 as_fatal (_("Intel L1OM is 64bit only"));
8109 return ELF_TARGET_L1OM_FORMAT
;
8112 return (flag_code
== CODE_64BIT
8113 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8116 #if defined (OBJ_MACH_O)
8117 case bfd_target_mach_o_flavour
:
8118 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8126 #endif /* OBJ_MAYBE_ more than one */
8128 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8130 i386_elf_emit_arch_note (void)
8132 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8135 asection
*seg
= now_seg
;
8136 subsegT subseg
= now_subseg
;
8137 Elf_Internal_Note i_note
;
8138 Elf_External_Note e_note
;
8139 asection
*note_secp
;
8142 /* Create the .note section. */
8143 note_secp
= subseg_new (".note", 0);
8144 bfd_set_section_flags (stdoutput
,
8146 SEC_HAS_CONTENTS
| SEC_READONLY
);
8148 /* Process the arch string. */
8149 len
= strlen (cpu_arch_name
);
8151 i_note
.namesz
= len
+ 1;
8153 i_note
.type
= NT_ARCH
;
8154 p
= frag_more (sizeof (e_note
.namesz
));
8155 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8156 p
= frag_more (sizeof (e_note
.descsz
));
8157 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8158 p
= frag_more (sizeof (e_note
.type
));
8159 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8160 p
= frag_more (len
+ 1);
8161 strcpy (p
, cpu_arch_name
);
8163 frag_align (2, 0, 0);
8165 subseg_set (seg
, subseg
);
8171 md_undefined_symbol (name
)
8174 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8175 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8176 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8177 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8181 if (symbol_find (name
))
8182 as_bad (_("GOT already in symbol table"));
8183 GOT_symbol
= symbol_new (name
, undefined_section
,
8184 (valueT
) 0, &zero_address_frag
);
8191 /* Round up a section size to the appropriate boundary. */
8194 md_section_align (segment
, size
)
8195 segT segment ATTRIBUTE_UNUSED
;
8198 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8199 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8201 /* For a.out, force the section size to be aligned. If we don't do
8202 this, BFD will align it for us, but it will not write out the
8203 final bytes of the section. This may be a bug in BFD, but it is
8204 easier to fix it here since that is how the other a.out targets
8208 align
= bfd_get_section_alignment (stdoutput
, segment
);
8209 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8216 /* On the i386, PC-relative offsets are relative to the start of the
8217 next instruction. That is, the address of the offset, plus its
8218 size, since the offset is always the last part of the insn. */
8221 md_pcrel_from (fixS
*fixP
)
8223 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8229 s_bss (int ignore ATTRIBUTE_UNUSED
)
8233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8235 obj_elf_section_change_hook ();
8237 temp
= get_absolute_expression ();
8238 subseg_set (bss_section
, (subsegT
) temp
);
8239 demand_empty_rest_of_line ();
8245 i386_validate_fix (fixS
*fixp
)
8247 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8249 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8253 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8258 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8260 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8267 tc_gen_reloc (section
, fixp
)
8268 asection
*section ATTRIBUTE_UNUSED
;
8272 bfd_reloc_code_real_type code
;
8274 switch (fixp
->fx_r_type
)
8276 case BFD_RELOC_X86_64_PLT32
:
8277 case BFD_RELOC_X86_64_GOT32
:
8278 case BFD_RELOC_X86_64_GOTPCREL
:
8279 case BFD_RELOC_386_PLT32
:
8280 case BFD_RELOC_386_GOT32
:
8281 case BFD_RELOC_386_GOTOFF
:
8282 case BFD_RELOC_386_GOTPC
:
8283 case BFD_RELOC_386_TLS_GD
:
8284 case BFD_RELOC_386_TLS_LDM
:
8285 case BFD_RELOC_386_TLS_LDO_32
:
8286 case BFD_RELOC_386_TLS_IE_32
:
8287 case BFD_RELOC_386_TLS_IE
:
8288 case BFD_RELOC_386_TLS_GOTIE
:
8289 case BFD_RELOC_386_TLS_LE_32
:
8290 case BFD_RELOC_386_TLS_LE
:
8291 case BFD_RELOC_386_TLS_GOTDESC
:
8292 case BFD_RELOC_386_TLS_DESC_CALL
:
8293 case BFD_RELOC_X86_64_TLSGD
:
8294 case BFD_RELOC_X86_64_TLSLD
:
8295 case BFD_RELOC_X86_64_DTPOFF32
:
8296 case BFD_RELOC_X86_64_DTPOFF64
:
8297 case BFD_RELOC_X86_64_GOTTPOFF
:
8298 case BFD_RELOC_X86_64_TPOFF32
:
8299 case BFD_RELOC_X86_64_TPOFF64
:
8300 case BFD_RELOC_X86_64_GOTOFF64
:
8301 case BFD_RELOC_X86_64_GOTPC32
:
8302 case BFD_RELOC_X86_64_GOT64
:
8303 case BFD_RELOC_X86_64_GOTPCREL64
:
8304 case BFD_RELOC_X86_64_GOTPC64
:
8305 case BFD_RELOC_X86_64_GOTPLT64
:
8306 case BFD_RELOC_X86_64_PLTOFF64
:
8307 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8308 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8310 case BFD_RELOC_VTABLE_ENTRY
:
8311 case BFD_RELOC_VTABLE_INHERIT
:
8313 case BFD_RELOC_32_SECREL
:
8315 code
= fixp
->fx_r_type
;
8317 case BFD_RELOC_X86_64_32S
:
8318 if (!fixp
->fx_pcrel
)
8320 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8321 code
= fixp
->fx_r_type
;
8327 switch (fixp
->fx_size
)
8330 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8331 _("can not do %d byte pc-relative relocation"),
8333 code
= BFD_RELOC_32_PCREL
;
8335 case 1: code
= BFD_RELOC_8_PCREL
; break;
8336 case 2: code
= BFD_RELOC_16_PCREL
; break;
8337 case 4: code
= BFD_RELOC_32_PCREL
; break;
8339 case 8: code
= BFD_RELOC_64_PCREL
; break;
8345 switch (fixp
->fx_size
)
8348 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8349 _("can not do %d byte relocation"),
8351 code
= BFD_RELOC_32
;
8353 case 1: code
= BFD_RELOC_8
; break;
8354 case 2: code
= BFD_RELOC_16
; break;
8355 case 4: code
= BFD_RELOC_32
; break;
8357 case 8: code
= BFD_RELOC_64
; break;
8364 if ((code
== BFD_RELOC_32
8365 || code
== BFD_RELOC_32_PCREL
8366 || code
== BFD_RELOC_X86_64_32S
)
8368 && fixp
->fx_addsy
== GOT_symbol
)
8371 code
= BFD_RELOC_386_GOTPC
;
8373 code
= BFD_RELOC_X86_64_GOTPC32
;
8375 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8377 && fixp
->fx_addsy
== GOT_symbol
)
8379 code
= BFD_RELOC_X86_64_GOTPC64
;
8382 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8383 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8384 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8386 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8388 if (!use_rela_relocations
)
8390 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8391 vtable entry to be used in the relocation's section offset. */
8392 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8393 rel
->address
= fixp
->fx_offset
;
8394 #if defined (OBJ_COFF) && defined (TE_PE)
8395 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8396 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8401 /* Use the rela in 64bit mode. */
8404 if (!fixp
->fx_pcrel
)
8405 rel
->addend
= fixp
->fx_offset
;
8409 case BFD_RELOC_X86_64_PLT32
:
8410 case BFD_RELOC_X86_64_GOT32
:
8411 case BFD_RELOC_X86_64_GOTPCREL
:
8412 case BFD_RELOC_X86_64_TLSGD
:
8413 case BFD_RELOC_X86_64_TLSLD
:
8414 case BFD_RELOC_X86_64_GOTTPOFF
:
8415 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8416 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8417 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8420 rel
->addend
= (section
->vma
8422 + fixp
->fx_addnumber
8423 + md_pcrel_from (fixp
));
8428 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8429 if (rel
->howto
== NULL
)
8431 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8432 _("cannot represent relocation type %s"),
8433 bfd_get_reloc_code_name (code
));
8434 /* Set howto to a garbage value so that we can keep going. */
8435 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8436 gas_assert (rel
->howto
!= NULL
);
8442 #include "tc-i386-intel.c"
8445 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8447 int saved_naked_reg
;
8448 char saved_register_dot
;
8450 saved_naked_reg
= allow_naked_reg
;
8451 allow_naked_reg
= 1;
8452 saved_register_dot
= register_chars
['.'];
8453 register_chars
['.'] = '.';
8454 allow_pseudo_reg
= 1;
8455 expression_and_evaluate (exp
);
8456 allow_pseudo_reg
= 0;
8457 register_chars
['.'] = saved_register_dot
;
8458 allow_naked_reg
= saved_naked_reg
;
8460 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8462 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8464 exp
->X_op
= O_constant
;
8465 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8466 .dw2_regnum
[flag_code
>> 1];
8469 exp
->X_op
= O_illegal
;
8474 tc_x86_frame_initial_instructions (void)
8476 static unsigned int sp_regno
[2];
8478 if (!sp_regno
[flag_code
>> 1])
8480 char *saved_input
= input_line_pointer
;
8481 char sp
[][4] = {"esp", "rsp"};
8484 input_line_pointer
= sp
[flag_code
>> 1];
8485 tc_x86_parse_to_dw2regnum (&exp
);
8486 gas_assert (exp
.X_op
== O_constant
);
8487 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8488 input_line_pointer
= saved_input
;
8491 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8492 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8496 i386_elf_section_type (const char *str
, size_t len
)
8498 if (flag_code
== CODE_64BIT
8499 && len
== sizeof ("unwind") - 1
8500 && strncmp (str
, "unwind", 6) == 0)
8501 return SHT_X86_64_UNWIND
;
8508 i386_solaris_fix_up_eh_frame (segT sec
)
8510 if (flag_code
== CODE_64BIT
)
8511 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8517 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8521 expr
.X_op
= O_secrel
;
8522 expr
.X_add_symbol
= symbol
;
8523 expr
.X_add_number
= 0;
8524 emit_expr (&expr
, size
);
8528 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8529 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8532 x86_64_section_letter (int letter
, char **ptr_msg
)
8534 if (flag_code
== CODE_64BIT
)
8537 return SHF_X86_64_LARGE
;
8539 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8542 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8547 x86_64_section_word (char *str
, size_t len
)
8549 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8550 return SHF_X86_64_LARGE
;
8556 handle_large_common (int small ATTRIBUTE_UNUSED
)
8558 if (flag_code
!= CODE_64BIT
)
8560 s_comm_internal (0, elf_common_parse
);
8561 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8565 static segT lbss_section
;
8566 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8567 asection
*saved_bss_section
= bss_section
;
8569 if (lbss_section
== NULL
)
8571 flagword applicable
;
8573 subsegT subseg
= now_subseg
;
8575 /* The .lbss section is for local .largecomm symbols. */
8576 lbss_section
= subseg_new (".lbss", 0);
8577 applicable
= bfd_applicable_section_flags (stdoutput
);
8578 bfd_set_section_flags (stdoutput
, lbss_section
,
8579 applicable
& SEC_ALLOC
);
8580 seg_info (lbss_section
)->bss
= 1;
8582 subseg_set (seg
, subseg
);
8585 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8586 bss_section
= lbss_section
;
8588 s_comm_internal (0, elf_common_parse
);
8590 elf_com_section_ptr
= saved_com_section_ptr
;
8591 bss_section
= saved_bss_section
;
8594 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */