1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template
*start
;
100 const insn_template
*end
;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem
; /* codes register or memory operand */
108 unsigned int reg
; /* codes register operand (or extended opcode) */
109 unsigned int mode
; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte
;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name
; /* arch name */
129 unsigned int len
; /* arch string length */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
132 unsigned int skip
; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name
; /* arch name */
140 unsigned int len
; /* arch string length */
141 i386_cpu_flags flags
; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c
);
158 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
160 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS
*);
165 static int i386_intel_parse_name (const char *, expressionS
*);
166 static const reg_entry
*parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template
*match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry
*build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS
*, offsetT
);
185 static void output_disp (fragS
*, offsetT
);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
193 static const char *default_arch
= DEFAULT_ARCH
;
195 /* This struct describes rounding control and SAE in the instruction. */
209 static struct RC_Operation rc_op
;
211 /* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214 struct Mask_Operation
216 const reg_entry
*mask
;
217 unsigned int zeroing
;
218 /* The operand where this operation is associated. */
222 static struct Mask_Operation mask_op
;
224 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 struct Broadcast_Operation
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
231 /* Index of broadcasted operand. */
235 static struct Broadcast_Operation broadcast_op
;
240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes
[4];
243 /* Destination or source register specifier. */
244 const reg_entry
*register_specifier
;
247 /* 'md_assemble ()' gathers together information and puts it into a
254 const reg_entry
*regs
;
259 operand_size_mismatch
,
260 operand_type_mismatch
,
261 register_type_mismatch
,
262 number_of_operands_mismatch
,
263 invalid_instruction_suffix
,
266 unsupported_with_intel_mnemonic
,
269 invalid_vsib_address
,
270 invalid_vector_register_set
,
271 unsupported_vector_index_register
,
272 unsupported_broadcast
,
273 broadcast_not_on_src_operand
,
276 mask_not_on_destination
,
279 rc_sae_operand_not_last_imm
,
280 invalid_register_operand
,
285 /* TM holds the template for the insn were currently assembling. */
288 /* SUFFIX holds the instruction size suffix for byte, word, dword
289 or qword, if given. */
292 /* OPERANDS gives the number of given operands. */
293 unsigned int operands
;
295 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
296 of given register, displacement, memory operands and immediate
298 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
300 /* TYPES [i] is the type (see above #defines) which tells us how to
301 use OP[i] for the corresponding operand. */
302 i386_operand_type types
[MAX_OPERANDS
];
304 /* Displacement expression, immediate expression, or register for each
306 union i386_op op
[MAX_OPERANDS
];
308 /* Flags for operands. */
309 unsigned int flags
[MAX_OPERANDS
];
310 #define Operand_PCrel 1
312 /* Relocation type for operand */
313 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
315 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
316 the base index byte below. */
317 const reg_entry
*base_reg
;
318 const reg_entry
*index_reg
;
319 unsigned int log2_scale_factor
;
321 /* SEG gives the seg_entries of this insn. They are zero unless
322 explicit segment overrides are given. */
323 const seg_entry
*seg
[2];
325 /* Copied first memory operand string, for re-checking. */
328 /* PREFIX holds all the given prefix opcodes (usually null).
329 PREFIXES is the number of prefix opcodes. */
330 unsigned int prefixes
;
331 unsigned char prefix
[MAX_PREFIXES
];
333 /* RM and SIB are the modrm byte and the sib byte where the
334 addressing modes of this insn are encoded. */
341 /* Masking attributes. */
342 struct Mask_Operation
*mask
;
344 /* Rounding control and SAE attributes. */
345 struct RC_Operation
*rounding
;
347 /* Broadcasting attributes. */
348 struct Broadcast_Operation
*broadcast
;
350 /* Compressed disp8*N attribute. */
351 unsigned int memshift
;
353 /* Prefer load or store in encoding. */
356 dir_encoding_default
= 0,
361 /* Prefer 8bit or 32bit displacement in encoding. */
364 disp_encoding_default
= 0,
369 /* Prefer the REX byte in encoding. */
370 bfd_boolean rex_encoding
;
372 /* Disable instruction size optimization. */
373 bfd_boolean no_optimize
;
375 /* How to encode vector instructions. */
378 vex_encoding_default
= 0,
385 const char *rep_prefix
;
388 const char *hle_prefix
;
390 /* Have BND prefix. */
391 const char *bnd_prefix
;
393 /* Have NOTRACK prefix. */
394 const char *notrack_prefix
;
397 enum i386_error error
;
400 typedef struct _i386_insn i386_insn
;
402 /* Link RC type with corresponding string, that'll be looked for in
411 static const struct RC_name RC_NamesTable
[] =
413 { rne
, STRING_COMMA_LEN ("rn-sae") },
414 { rd
, STRING_COMMA_LEN ("rd-sae") },
415 { ru
, STRING_COMMA_LEN ("ru-sae") },
416 { rz
, STRING_COMMA_LEN ("rz-sae") },
417 { saeonly
, STRING_COMMA_LEN ("sae") },
420 /* List of chars besides those in app.c:symbol_chars that can start an
421 operand. Used to prevent the scrubber eating vital white-space. */
422 const char extra_symbol_chars
[] = "*%-([{}"
431 #if (defined (TE_I386AIX) \
432 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
433 && !defined (TE_GNU) \
434 && !defined (TE_LINUX) \
435 && !defined (TE_NACL) \
436 && !defined (TE_NETWARE) \
437 && !defined (TE_FreeBSD) \
438 && !defined (TE_DragonFly) \
439 && !defined (TE_NetBSD)))
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. The option
442 --divide will remove '/' from this list. */
443 const char *i386_comment_chars
= "#/";
444 #define SVR4_COMMENT_CHARS 1
445 #define PREFIX_SEPARATOR '\\'
448 const char *i386_comment_chars
= "#";
449 #define PREFIX_SEPARATOR '/'
452 /* This array holds the chars that only start a comment at the beginning of
453 a line. If the line seems to have the form '# 123 filename'
454 .line and .file directives will appear in the pre-processed output.
455 Note that input_file.c hand checks for '#' at the beginning of the
456 first line of the input file. This is because the compiler outputs
457 #NO_APP at the beginning of its output.
458 Also note that comments started like this one will always work if
459 '/' isn't otherwise defined. */
460 const char line_comment_chars
[] = "#/";
462 const char line_separator_chars
[] = ";";
464 /* Chars that can be used to separate mant from exp in floating point
466 const char EXP_CHARS
[] = "eE";
468 /* Chars that mean this number is a floating point constant
471 const char FLT_CHARS
[] = "fFdDxX";
473 /* Tables for lexical analysis. */
474 static char mnemonic_chars
[256];
475 static char register_chars
[256];
476 static char operand_chars
[256];
477 static char identifier_chars
[256];
478 static char digit_chars
[256];
480 /* Lexical macros. */
481 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
482 #define is_operand_char(x) (operand_chars[(unsigned char) x])
483 #define is_register_char(x) (register_chars[(unsigned char) x])
484 #define is_space_char(x) ((x) == ' ')
485 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
486 #define is_digit_char(x) (digit_chars[(unsigned char) x])
488 /* All non-digit non-letter characters that may occur in an operand. */
489 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
491 /* md_assemble() always leaves the strings it's passed unaltered. To
492 effect this we maintain a stack of saved characters that we've smashed
493 with '\0's (indicating end of strings for various sub-fields of the
494 assembler instruction). */
495 static char save_stack
[32];
496 static char *save_stack_p
;
497 #define END_STRING_AND_SAVE(s) \
498 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
499 #define RESTORE_END_STRING(s) \
500 do { *(s) = *--save_stack_p; } while (0)
502 /* The instruction we're assembling. */
505 /* Possible templates for current insn. */
506 static const templates
*current_templates
;
508 /* Per instruction expressionS buffers: max displacements & immediates. */
509 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
510 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
512 /* Current operand we are working on. */
513 static int this_operand
= -1;
515 /* We support four different modes. FLAG_CODE variable is used to distinguish
523 static enum flag_code flag_code
;
524 static unsigned int object_64bit
;
525 static unsigned int disallow_64bit_reloc
;
526 static int use_rela_relocations
= 0;
528 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
529 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
532 /* The ELF ABI to use. */
540 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
543 #if defined (TE_PE) || defined (TE_PEP)
544 /* Use big object file format. */
545 static int use_big_obj
= 0;
548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
549 /* 1 if generating code for a shared library. */
550 static int shared
= 0;
553 /* 1 for intel syntax,
555 static int intel_syntax
= 0;
557 /* 1 for Intel64 ISA,
561 /* 1 for intel mnemonic,
562 0 if att mnemonic. */
563 static int intel_mnemonic
= !SYSV386_COMPAT
;
565 /* 1 if support old (<= 2.8.1) versions of gcc. */
566 static int old_gcc
= OLDGCC_COMPAT
;
568 /* 1 if pseudo registers are permitted. */
569 static int allow_pseudo_reg
= 0;
571 /* 1 if register prefix % not required. */
572 static int allow_naked_reg
= 0;
574 /* 1 if the assembler should add BND prefix for all control-transferring
575 instructions supporting it, even if this prefix wasn't specified
577 static int add_bnd_prefix
= 0;
579 /* 1 if pseudo index register, eiz/riz, is allowed . */
580 static int allow_index_reg
= 0;
582 /* 1 if the assembler should ignore LOCK prefix, even if it was
583 specified explicitly. */
584 static int omit_lock_prefix
= 0;
586 /* 1 if the assembler should encode lfence, mfence, and sfence as
587 "lock addl $0, (%{re}sp)". */
588 static int avoid_fence
= 0;
590 /* 1 if the assembler should generate relax relocations. */
592 static int generate_relax_relocations
593 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
595 static enum check_kind
601 sse_check
, operand_check
= check_warning
;
604 1. Clear the REX_W bit with register operand if possible.
605 2. Above plus use 128bit vector instruction to clear the full vector
608 static int optimize
= 0;
611 1. Clear the REX_W bit with register operand if possible.
612 2. Above plus use 128bit vector instruction to clear the full vector
614 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
617 static int optimize_for_space
= 0;
619 /* Register prefix used for error message. */
620 static const char *register_prefix
= "%";
622 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
623 leave, push, and pop instructions so that gcc has the same stack
624 frame as in 32 bit mode. */
625 static char stackop_size
= '\0';
627 /* Non-zero to optimize code alignment. */
628 int optimize_align_code
= 1;
630 /* Non-zero to quieten some warnings. */
631 static int quiet_warnings
= 0;
634 static const char *cpu_arch_name
= NULL
;
635 static char *cpu_sub_arch_name
= NULL
;
637 /* CPU feature flags. */
638 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
640 /* If we have selected a cpu we are generating instructions for. */
641 static int cpu_arch_tune_set
= 0;
643 /* Cpu we are generating instructions for. */
644 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
646 /* CPU feature flags of cpu we are generating instructions for. */
647 static i386_cpu_flags cpu_arch_tune_flags
;
649 /* CPU instruction set architecture used. */
650 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
652 /* CPU feature flags of instruction set architecture used. */
653 i386_cpu_flags cpu_arch_isa_flags
;
655 /* If set, conditional jumps are not automatically promoted to handle
656 larger than a byte offset. */
657 static unsigned int no_cond_jump_promotion
= 0;
659 /* Encode SSE instructions with VEX prefix. */
660 static unsigned int sse2avx
;
662 /* Encode scalar AVX instructions with specific vector length. */
669 /* Encode scalar EVEX LIG instructions with specific vector length. */
677 /* Encode EVEX WIG instructions with specific evex.w. */
684 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
685 static enum rc_type evexrcig
= rne
;
687 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
688 static symbolS
*GOT_symbol
;
690 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
691 unsigned int x86_dwarf2_return_column
;
693 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
694 int x86_cie_data_alignment
;
696 /* Interface to relax_segment.
697 There are 3 major relax states for 386 jump insns because the
698 different types of jumps add different sizes to frags when we're
699 figuring out what sort of jump to choose to reach a given label. */
702 #define UNCOND_JUMP 0
704 #define COND_JUMP86 2
709 #define SMALL16 (SMALL | CODE16)
711 #define BIG16 (BIG | CODE16)
715 #define INLINE __inline__
721 #define ENCODE_RELAX_STATE(type, size) \
722 ((relax_substateT) (((type) << 2) | (size)))
723 #define TYPE_FROM_RELAX_STATE(s) \
725 #define DISP_SIZE_FROM_RELAX_STATE(s) \
726 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
728 /* This table is used by relax_frag to promote short jumps to long
729 ones where necessary. SMALL (short) jumps may be promoted to BIG
730 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
731 don't allow a short jump in a 32 bit code segment to be promoted to
732 a 16 bit offset jump because it's slower (requires data size
733 prefix), and doesn't work, unless the destination is in the bottom
734 64k of the code segment (The top 16 bits of eip are zeroed). */
736 const relax_typeS md_relax_table
[] =
739 1) most positive reach of this state,
740 2) most negative reach of this state,
741 3) how many bytes this mode will have in the variable part of the frag
742 4) which index into the table to try if we can't fit into this one. */
744 /* UNCOND_JUMP states. */
745 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
747 /* dword jmp adds 4 bytes to frag:
748 0 extra opcode bytes, 4 displacement bytes. */
750 /* word jmp adds 2 byte2 to frag:
751 0 extra opcode bytes, 2 displacement bytes. */
754 /* COND_JUMP states. */
755 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
756 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
757 /* dword conditionals adds 5 bytes to frag:
758 1 extra opcode byte, 4 displacement bytes. */
760 /* word conditionals add 3 bytes to frag:
761 1 extra opcode byte, 2 displacement bytes. */
764 /* COND_JUMP86 states. */
765 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
766 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
767 /* dword conditionals adds 5 bytes to frag:
768 1 extra opcode byte, 4 displacement bytes. */
770 /* word conditionals add 4 bytes to frag:
771 1 displacement byte and a 3 byte long branch insn. */
775 static const arch_entry cpu_arch
[] =
777 /* Do not replace the first two entries - i386_target_format()
778 relies on them being there in this order. */
779 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
780 CPU_GENERIC32_FLAGS
, 0 },
781 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
782 CPU_GENERIC64_FLAGS
, 0 },
783 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
785 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
787 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
789 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
791 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
793 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
795 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
797 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
799 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
800 CPU_PENTIUMPRO_FLAGS
, 0 },
801 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
803 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
805 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
807 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
809 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
810 CPU_NOCONA_FLAGS
, 0 },
811 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
813 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
815 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
816 CPU_CORE2_FLAGS
, 1 },
817 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
818 CPU_CORE2_FLAGS
, 0 },
819 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
820 CPU_COREI7_FLAGS
, 0 },
821 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
823 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
825 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
826 CPU_IAMCU_FLAGS
, 0 },
827 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
829 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
831 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
832 CPU_ATHLON_FLAGS
, 0 },
833 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
835 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
837 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
839 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
840 CPU_AMDFAM10_FLAGS
, 0 },
841 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
842 CPU_BDVER1_FLAGS
, 0 },
843 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
844 CPU_BDVER2_FLAGS
, 0 },
845 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
846 CPU_BDVER3_FLAGS
, 0 },
847 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
848 CPU_BDVER4_FLAGS
, 0 },
849 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
850 CPU_ZNVER1_FLAGS
, 0 },
851 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
852 CPU_BTVER1_FLAGS
, 0 },
853 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
854 CPU_BTVER2_FLAGS
, 0 },
855 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
857 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
859 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
861 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
863 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
865 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
867 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
869 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
871 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
872 CPU_SSSE3_FLAGS
, 0 },
873 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
874 CPU_SSE4_1_FLAGS
, 0 },
875 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
876 CPU_SSE4_2_FLAGS
, 0 },
877 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
878 CPU_SSE4_2_FLAGS
, 0 },
879 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
881 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
883 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
884 CPU_AVX512F_FLAGS
, 0 },
885 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
886 CPU_AVX512CD_FLAGS
, 0 },
887 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
888 CPU_AVX512ER_FLAGS
, 0 },
889 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
890 CPU_AVX512PF_FLAGS
, 0 },
891 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
892 CPU_AVX512DQ_FLAGS
, 0 },
893 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
894 CPU_AVX512BW_FLAGS
, 0 },
895 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
896 CPU_AVX512VL_FLAGS
, 0 },
897 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
899 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
900 CPU_VMFUNC_FLAGS
, 0 },
901 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
903 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
904 CPU_XSAVE_FLAGS
, 0 },
905 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
906 CPU_XSAVEOPT_FLAGS
, 0 },
907 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
908 CPU_XSAVEC_FLAGS
, 0 },
909 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
910 CPU_XSAVES_FLAGS
, 0 },
911 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
913 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
914 CPU_PCLMUL_FLAGS
, 0 },
915 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
916 CPU_PCLMUL_FLAGS
, 1 },
917 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
918 CPU_FSGSBASE_FLAGS
, 0 },
919 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
920 CPU_RDRND_FLAGS
, 0 },
921 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
923 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
925 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
927 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
929 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
931 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
933 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
934 CPU_MOVBE_FLAGS
, 0 },
935 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
937 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
939 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
940 CPU_LZCNT_FLAGS
, 0 },
941 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
943 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
945 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
946 CPU_INVPCID_FLAGS
, 0 },
947 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
948 CPU_CLFLUSH_FLAGS
, 0 },
949 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
951 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
952 CPU_SYSCALL_FLAGS
, 0 },
953 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
954 CPU_RDTSCP_FLAGS
, 0 },
955 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
956 CPU_3DNOW_FLAGS
, 0 },
957 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
958 CPU_3DNOWA_FLAGS
, 0 },
959 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
960 CPU_PADLOCK_FLAGS
, 0 },
961 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
963 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
965 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
966 CPU_SSE4A_FLAGS
, 0 },
967 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
976 CPU_RDSEED_FLAGS
, 0 },
977 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
978 CPU_PRFCHW_FLAGS
, 0 },
979 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
983 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
986 CPU_CLFLUSHOPT_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
988 CPU_PREFETCHWT1_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
991 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
993 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
994 CPU_AVX512IFMA_FLAGS
, 0 },
995 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
996 CPU_AVX512VBMI_FLAGS
, 0 },
997 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
998 CPU_AVX512_4FMAPS_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1000 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1002 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1004 CPU_AVX512_VBMI2_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1006 CPU_AVX512_VNNI_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1008 CPU_AVX512_BITALG_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1010 CPU_CLZERO_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1012 CPU_MWAITX_FLAGS
, 0 },
1013 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1014 CPU_OSPKE_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1016 CPU_RDPID_FLAGS
, 0 },
1017 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1018 CPU_PTWRITE_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1021 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1022 CPU_SHSTK_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1024 CPU_GFNI_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1026 CPU_VAES_FLAGS
, 0 },
1027 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1028 CPU_VPCLMULQDQ_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1030 CPU_WBNOINVD_FLAGS
, 0 },
1031 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1032 CPU_PCONFIG_FLAGS
, 0 },
1035 static const noarch_entry cpu_noarch
[] =
1037 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1038 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1039 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1040 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1041 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1042 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1043 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1044 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1045 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1046 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1047 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1048 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1049 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1050 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1051 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1052 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1053 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1054 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1055 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1056 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1057 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1058 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1059 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1060 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1061 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1062 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1063 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1064 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1065 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1066 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1067 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1071 /* Like s_lcomm_internal in gas/read.c but the alignment string
1072 is allowed to be optional. */
1075 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1082 && *input_line_pointer
== ',')
1084 align
= parse_align (needs_align
- 1);
1086 if (align
== (addressT
) -1)
1101 bss_alloc (symbolP
, size
, align
);
1106 pe_lcomm (int needs_align
)
1108 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1112 const pseudo_typeS md_pseudo_table
[] =
1114 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1115 {"align", s_align_bytes
, 0},
1117 {"align", s_align_ptwo
, 0},
1119 {"arch", set_cpu_arch
, 0},
1123 {"lcomm", pe_lcomm
, 1},
1125 {"ffloat", float_cons
, 'f'},
1126 {"dfloat", float_cons
, 'd'},
1127 {"tfloat", float_cons
, 'x'},
1129 {"slong", signed_cons
, 4},
1130 {"noopt", s_ignore
, 0},
1131 {"optim", s_ignore
, 0},
1132 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1133 {"code16", set_code_flag
, CODE_16BIT
},
1134 {"code32", set_code_flag
, CODE_32BIT
},
1136 {"code64", set_code_flag
, CODE_64BIT
},
1138 {"intel_syntax", set_intel_syntax
, 1},
1139 {"att_syntax", set_intel_syntax
, 0},
1140 {"intel_mnemonic", set_intel_mnemonic
, 1},
1141 {"att_mnemonic", set_intel_mnemonic
, 0},
1142 {"allow_index_reg", set_allow_index_reg
, 1},
1143 {"disallow_index_reg", set_allow_index_reg
, 0},
1144 {"sse_check", set_check
, 0},
1145 {"operand_check", set_check
, 1},
1146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1147 {"largecomm", handle_large_common
, 0},
1149 {"file", dwarf2_directive_file
, 0},
1150 {"loc", dwarf2_directive_loc
, 0},
1151 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1154 {"secrel32", pe_directive_secrel
, 0},
1159 /* For interface with expression (). */
1160 extern char *input_line_pointer
;
1162 /* Hash table for instruction mnemonic lookup. */
1163 static struct hash_control
*op_hash
;
1165 /* Hash table for register lookup. */
1166 static struct hash_control
*reg_hash
;
1168 /* Various efficient no-op patterns for aligning code labels.
1169 Note: Don't try to assemble the instructions in the comments.
1170 0L and 0w are not legal. */
1171 static const unsigned char f32_1
[] =
1173 static const unsigned char f32_2
[] =
1174 {0x66,0x90}; /* xchg %ax,%ax */
1175 static const unsigned char f32_3
[] =
1176 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1177 static const unsigned char f32_4
[] =
1178 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1179 static const unsigned char f32_6
[] =
1180 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1181 static const unsigned char f32_7
[] =
1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1183 static const unsigned char f16_3
[] =
1184 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1185 static const unsigned char f16_4
[] =
1186 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1187 static const unsigned char jump_disp8
[] =
1188 {0xeb}; /* jmp disp8 */
1189 static const unsigned char jump32_disp32
[] =
1190 {0xe9}; /* jmp disp32 */
1191 static const unsigned char jump16_disp32
[] =
1192 {0x66,0xe9}; /* jmp disp32 */
1193 /* 32-bit NOPs patterns. */
1194 static const unsigned char *const f32_patt
[] = {
1195 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1197 /* 16-bit NOPs patterns. */
1198 static const unsigned char *const f16_patt
[] = {
1199 f32_1
, f32_2
, f16_3
, f16_4
1201 /* nopl (%[re]ax) */
1202 static const unsigned char alt_3
[] =
1204 /* nopl 0(%[re]ax) */
1205 static const unsigned char alt_4
[] =
1206 {0x0f,0x1f,0x40,0x00};
1207 /* nopl 0(%[re]ax,%[re]ax,1) */
1208 static const unsigned char alt_5
[] =
1209 {0x0f,0x1f,0x44,0x00,0x00};
1210 /* nopw 0(%[re]ax,%[re]ax,1) */
1211 static const unsigned char alt_6
[] =
1212 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1213 /* nopl 0L(%[re]ax) */
1214 static const unsigned char alt_7
[] =
1215 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1216 /* nopl 0L(%[re]ax,%[re]ax,1) */
1217 static const unsigned char alt_8
[] =
1218 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1219 /* nopw 0L(%[re]ax,%[re]ax,1) */
1220 static const unsigned char alt_9
[] =
1221 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1223 static const unsigned char alt_10
[] =
1224 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* data16 nopw %cs:0L(%eax,%eax,1) */
1226 static const unsigned char alt_11
[] =
1227 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* 32-bit and 64-bit NOPs patterns. */
1229 static const unsigned char *const alt_patt
[] = {
1230 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1231 alt_9
, alt_10
, alt_11
1234 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1235 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1238 i386_output_nops (char *where
, const unsigned char *const *patt
,
1239 int count
, int max_single_nop_size
)
1242 /* Place the longer NOP first. */
1245 const unsigned char *nops
= patt
[max_single_nop_size
- 1];
1247 /* Use the smaller one if the requsted one isn't available. */
1250 max_single_nop_size
--;
1251 nops
= patt
[max_single_nop_size
- 1];
1254 last
= count
% max_single_nop_size
;
1257 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1258 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1262 nops
= patt
[last
- 1];
1265 /* Use the smaller one plus one-byte NOP if the needed one
1268 nops
= patt
[last
- 1];
1269 memcpy (where
+ offset
, nops
, last
);
1270 where
[offset
+ last
] = *patt
[0];
1273 memcpy (where
+ offset
, nops
, last
);
1278 fits_in_imm7 (offsetT num
)
1280 return (num
& 0x7f) == num
;
1284 fits_in_imm31 (offsetT num
)
1286 return (num
& 0x7fffffff) == num
;
1289 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1290 single NOP instruction LIMIT. */
1293 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1295 const unsigned char *const *patt
= NULL
;
1296 int max_single_nop_size
;
1297 /* Maximum number of NOPs before switching to jump over NOPs. */
1298 int max_number_of_nops
;
1300 switch (fragP
->fr_type
)
1309 /* We need to decide which NOP sequence to use for 32bit and
1310 64bit. When -mtune= is used:
1312 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1313 PROCESSOR_GENERIC32, f32_patt will be used.
1314 2. For the rest, alt_patt will be used.
1316 When -mtune= isn't used, alt_patt will be used if
1317 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1320 When -march= or .arch is used, we can't use anything beyond
1321 cpu_arch_isa_flags. */
1323 if (flag_code
== CODE_16BIT
)
1326 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1327 /* Limit number of NOPs to 2 in 16-bit mode. */
1328 max_number_of_nops
= 2;
1332 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1334 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1335 switch (cpu_arch_tune
)
1337 case PROCESSOR_UNKNOWN
:
1338 /* We use cpu_arch_isa_flags to check if we SHOULD
1339 optimize with nops. */
1340 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1345 case PROCESSOR_PENTIUM4
:
1346 case PROCESSOR_NOCONA
:
1347 case PROCESSOR_CORE
:
1348 case PROCESSOR_CORE2
:
1349 case PROCESSOR_COREI7
:
1350 case PROCESSOR_L1OM
:
1351 case PROCESSOR_K1OM
:
1352 case PROCESSOR_GENERIC64
:
1354 case PROCESSOR_ATHLON
:
1356 case PROCESSOR_AMDFAM10
:
1358 case PROCESSOR_ZNVER
:
1362 case PROCESSOR_I386
:
1363 case PROCESSOR_I486
:
1364 case PROCESSOR_PENTIUM
:
1365 case PROCESSOR_PENTIUMPRO
:
1366 case PROCESSOR_IAMCU
:
1367 case PROCESSOR_GENERIC32
:
1374 switch (fragP
->tc_frag_data
.tune
)
1376 case PROCESSOR_UNKNOWN
:
1377 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1378 PROCESSOR_UNKNOWN. */
1382 case PROCESSOR_I386
:
1383 case PROCESSOR_I486
:
1384 case PROCESSOR_PENTIUM
:
1385 case PROCESSOR_IAMCU
:
1387 case PROCESSOR_ATHLON
:
1389 case PROCESSOR_AMDFAM10
:
1391 case PROCESSOR_ZNVER
:
1393 case PROCESSOR_GENERIC32
:
1394 /* We use cpu_arch_isa_flags to check if we CAN optimize
1396 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1401 case PROCESSOR_PENTIUMPRO
:
1402 case PROCESSOR_PENTIUM4
:
1403 case PROCESSOR_NOCONA
:
1404 case PROCESSOR_CORE
:
1405 case PROCESSOR_CORE2
:
1406 case PROCESSOR_COREI7
:
1407 case PROCESSOR_L1OM
:
1408 case PROCESSOR_K1OM
:
1409 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1414 case PROCESSOR_GENERIC64
:
1420 if (patt
== f32_patt
)
1422 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1423 /* Limit number of NOPs to 2 for older processors. */
1424 max_number_of_nops
= 2;
1428 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1429 /* Limit number of NOPs to 7 for newer processors. */
1430 max_number_of_nops
= 7;
1435 limit
= max_single_nop_size
;
1437 if (fragP
->fr_type
== rs_fill_nop
)
1439 /* Output NOPs for .nop directive. */
1440 if (limit
> max_single_nop_size
)
1442 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1443 _("invalid single nop size: %d "
1444 "(expect within [0, %d])"),
1445 limit
, max_single_nop_size
);
1450 fragP
->fr_var
= count
;
1452 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1454 /* Generate jump over NOPs. */
1455 offsetT disp
= count
- 2;
1456 if (fits_in_imm7 (disp
))
1458 /* Use "jmp disp8" if possible. */
1460 where
[0] = jump_disp8
[0];
1466 unsigned int size_of_jump
;
1468 if (flag_code
== CODE_16BIT
)
1470 where
[0] = jump16_disp32
[0];
1471 where
[1] = jump16_disp32
[1];
1476 where
[0] = jump32_disp32
[0];
1480 count
-= size_of_jump
+ 4;
1481 if (!fits_in_imm31 (count
))
1483 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1484 _("jump over nop padding out of range"));
1488 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1489 where
+= size_of_jump
+ 4;
1493 /* Generate multiple NOPs. */
1494 i386_output_nops (where
, patt
, count
, limit
);
1498 operand_type_all_zero (const union i386_operand_type
*x
)
1500 switch (ARRAY_SIZE(x
->array
))
1511 return !x
->array
[0];
1518 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1520 switch (ARRAY_SIZE(x
->array
))
1538 operand_type_equal (const union i386_operand_type
*x
,
1539 const union i386_operand_type
*y
)
1541 switch (ARRAY_SIZE(x
->array
))
1544 if (x
->array
[2] != y
->array
[2])
1548 if (x
->array
[1] != y
->array
[1])
1552 return x
->array
[0] == y
->array
[0];
1560 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1562 switch (ARRAY_SIZE(x
->array
))
1577 return !x
->array
[0];
1584 cpu_flags_equal (const union i386_cpu_flags
*x
,
1585 const union i386_cpu_flags
*y
)
1587 switch (ARRAY_SIZE(x
->array
))
1590 if (x
->array
[3] != y
->array
[3])
1594 if (x
->array
[2] != y
->array
[2])
1598 if (x
->array
[1] != y
->array
[1])
1602 return x
->array
[0] == y
->array
[0];
1610 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1612 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1613 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1616 static INLINE i386_cpu_flags
1617 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1619 switch (ARRAY_SIZE (x
.array
))
1622 x
.array
[3] &= y
.array
[3];
1625 x
.array
[2] &= y
.array
[2];
1628 x
.array
[1] &= y
.array
[1];
1631 x
.array
[0] &= y
.array
[0];
1639 static INLINE i386_cpu_flags
1640 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1642 switch (ARRAY_SIZE (x
.array
))
1645 x
.array
[3] |= y
.array
[3];
1648 x
.array
[2] |= y
.array
[2];
1651 x
.array
[1] |= y
.array
[1];
1654 x
.array
[0] |= y
.array
[0];
1662 static INLINE i386_cpu_flags
1663 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1665 switch (ARRAY_SIZE (x
.array
))
1668 x
.array
[3] &= ~y
.array
[3];
1671 x
.array
[2] &= ~y
.array
[2];
1674 x
.array
[1] &= ~y
.array
[1];
1677 x
.array
[0] &= ~y
.array
[0];
1685 #define CPU_FLAGS_ARCH_MATCH 0x1
1686 #define CPU_FLAGS_64BIT_MATCH 0x2
1688 #define CPU_FLAGS_PERFECT_MATCH \
1689 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1691 /* Return CPU flags match bits. */
1694 cpu_flags_match (const insn_template
*t
)
1696 i386_cpu_flags x
= t
->cpu_flags
;
1697 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1699 x
.bitfield
.cpu64
= 0;
1700 x
.bitfield
.cpuno64
= 0;
1702 if (cpu_flags_all_zero (&x
))
1704 /* This instruction is available on all archs. */
1705 match
|= CPU_FLAGS_ARCH_MATCH
;
1709 /* This instruction is available only on some archs. */
1710 i386_cpu_flags cpu
= cpu_arch_flags
;
1712 /* AVX512VL is no standalone feature - match it and then strip it. */
1713 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1715 x
.bitfield
.cpuavx512vl
= 0;
1717 cpu
= cpu_flags_and (x
, cpu
);
1718 if (!cpu_flags_all_zero (&cpu
))
1720 if (x
.bitfield
.cpuavx
)
1722 /* We need to check a few extra flags with AVX. */
1723 if (cpu
.bitfield
.cpuavx
1724 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1725 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1726 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1727 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1728 match
|= CPU_FLAGS_ARCH_MATCH
;
1730 else if (x
.bitfield
.cpuavx512f
)
1732 /* We need to check a few extra flags with AVX512F. */
1733 if (cpu
.bitfield
.cpuavx512f
1734 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1735 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1736 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1737 match
|= CPU_FLAGS_ARCH_MATCH
;
1740 match
|= CPU_FLAGS_ARCH_MATCH
;
1746 static INLINE i386_operand_type
1747 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1749 switch (ARRAY_SIZE (x
.array
))
1752 x
.array
[2] &= y
.array
[2];
1755 x
.array
[1] &= y
.array
[1];
1758 x
.array
[0] &= y
.array
[0];
1766 static INLINE i386_operand_type
1767 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1769 switch (ARRAY_SIZE (x
.array
))
1772 x
.array
[2] &= ~y
.array
[2];
1775 x
.array
[1] &= ~y
.array
[1];
1778 x
.array
[0] &= ~y
.array
[0];
1786 static INLINE i386_operand_type
1787 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1789 switch (ARRAY_SIZE (x
.array
))
1792 x
.array
[2] |= y
.array
[2];
1795 x
.array
[1] |= y
.array
[1];
1798 x
.array
[0] |= y
.array
[0];
1806 static INLINE i386_operand_type
1807 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1809 switch (ARRAY_SIZE (x
.array
))
1812 x
.array
[2] ^= y
.array
[2];
1815 x
.array
[1] ^= y
.array
[1];
1818 x
.array
[0] ^= y
.array
[0];
1826 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1827 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1828 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1829 static const i386_operand_type inoutportreg
1830 = OPERAND_TYPE_INOUTPORTREG
;
1831 static const i386_operand_type reg16_inoutportreg
1832 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1833 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1834 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1835 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1836 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1837 static const i386_operand_type anydisp
1838 = OPERAND_TYPE_ANYDISP
;
1839 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1840 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1841 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1842 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1843 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1844 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1845 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1846 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1847 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1848 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1849 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1850 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1861 operand_type_check (i386_operand_type t
, enum operand_type c
)
1866 return t
.bitfield
.reg
;
1869 return (t
.bitfield
.imm8
1873 || t
.bitfield
.imm32s
1874 || t
.bitfield
.imm64
);
1877 return (t
.bitfield
.disp8
1878 || t
.bitfield
.disp16
1879 || t
.bitfield
.disp32
1880 || t
.bitfield
.disp32s
1881 || t
.bitfield
.disp64
);
1884 return (t
.bitfield
.disp8
1885 || t
.bitfield
.disp16
1886 || t
.bitfield
.disp32
1887 || t
.bitfield
.disp32s
1888 || t
.bitfield
.disp64
1889 || t
.bitfield
.baseindex
);
1898 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1899 operand J for instruction template T. */
1902 match_reg_size (const insn_template
*t
, unsigned int j
)
1904 return !((i
.types
[j
].bitfield
.byte
1905 && !t
->operand_types
[j
].bitfield
.byte
)
1906 || (i
.types
[j
].bitfield
.word
1907 && !t
->operand_types
[j
].bitfield
.word
)
1908 || (i
.types
[j
].bitfield
.dword
1909 && !t
->operand_types
[j
].bitfield
.dword
)
1910 || (i
.types
[j
].bitfield
.qword
1911 && !t
->operand_types
[j
].bitfield
.qword
)
1912 || (i
.types
[j
].bitfield
.tbyte
1913 && !t
->operand_types
[j
].bitfield
.tbyte
));
1916 /* Return 1 if there is no conflict in SIMD register on
1917 operand J for instruction template T. */
1920 match_simd_size (const insn_template
*t
, unsigned int j
)
1922 return !((i
.types
[j
].bitfield
.xmmword
1923 && !t
->operand_types
[j
].bitfield
.xmmword
)
1924 || (i
.types
[j
].bitfield
.ymmword
1925 && !t
->operand_types
[j
].bitfield
.ymmword
)
1926 || (i
.types
[j
].bitfield
.zmmword
1927 && !t
->operand_types
[j
].bitfield
.zmmword
));
1930 /* Return 1 if there is no conflict in any size on operand J for
1931 instruction template T. */
1934 match_mem_size (const insn_template
*t
, unsigned int j
)
1936 return (match_reg_size (t
, j
)
1937 && !((i
.types
[j
].bitfield
.unspecified
1939 && !t
->operand_types
[j
].bitfield
.unspecified
)
1940 || (i
.types
[j
].bitfield
.fword
1941 && !t
->operand_types
[j
].bitfield
.fword
)
1942 /* For scalar opcode templates to allow register and memory
1943 operands at the same time, some special casing is needed
1945 || ((t
->operand_types
[j
].bitfield
.regsimd
1946 && !t
->opcode_modifier
.broadcast
1947 && (t
->operand_types
[j
].bitfield
.dword
1948 || t
->operand_types
[j
].bitfield
.qword
))
1949 ? (i
.types
[j
].bitfield
.xmmword
1950 || i
.types
[j
].bitfield
.ymmword
1951 || i
.types
[j
].bitfield
.zmmword
)
1952 : !match_simd_size(t
, j
))));
1955 /* Return 1 if there is no size conflict on any operands for
1956 instruction template T. */
1959 operand_size_match (const insn_template
*t
)
1964 /* Don't check jump instructions. */
1965 if (t
->opcode_modifier
.jump
1966 || t
->opcode_modifier
.jumpbyte
1967 || t
->opcode_modifier
.jumpdword
1968 || t
->opcode_modifier
.jumpintersegment
)
1971 /* Check memory and accumulator operand size. */
1972 for (j
= 0; j
< i
.operands
; j
++)
1974 if (!i
.types
[j
].bitfield
.reg
&& !i
.types
[j
].bitfield
.regsimd
1975 && t
->operand_types
[j
].bitfield
.anysize
)
1978 if (t
->operand_types
[j
].bitfield
.reg
1979 && !match_reg_size (t
, j
))
1985 if (t
->operand_types
[j
].bitfield
.regsimd
1986 && !match_simd_size (t
, j
))
1992 if (t
->operand_types
[j
].bitfield
.acc
1993 && (!match_reg_size (t
, j
) || !match_simd_size (t
, j
)))
1999 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
2008 else if (!t
->opcode_modifier
.d
)
2011 i
.error
= operand_size_mismatch
;
2015 /* Check reverse. */
2016 gas_assert (i
.operands
== 2);
2019 for (j
= 0; j
< 2; j
++)
2021 if ((t
->operand_types
[j
].bitfield
.reg
2022 || t
->operand_types
[j
].bitfield
.acc
)
2023 && !match_reg_size (t
, j
? 0 : 1))
2026 if (i
.types
[j
].bitfield
.mem
2027 && !match_mem_size (t
, j
? 0 : 1))
2035 operand_type_match (i386_operand_type overlap
,
2036 i386_operand_type given
)
2038 i386_operand_type temp
= overlap
;
2040 temp
.bitfield
.jumpabsolute
= 0;
2041 temp
.bitfield
.unspecified
= 0;
2042 temp
.bitfield
.byte
= 0;
2043 temp
.bitfield
.word
= 0;
2044 temp
.bitfield
.dword
= 0;
2045 temp
.bitfield
.fword
= 0;
2046 temp
.bitfield
.qword
= 0;
2047 temp
.bitfield
.tbyte
= 0;
2048 temp
.bitfield
.xmmword
= 0;
2049 temp
.bitfield
.ymmword
= 0;
2050 temp
.bitfield
.zmmword
= 0;
2051 if (operand_type_all_zero (&temp
))
2054 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
2055 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
2059 i
.error
= operand_type_mismatch
;
2063 /* If given types g0 and g1 are registers they must be of the same type
2064 unless the expected operand type register overlap is null.
2065 Memory operand size of certain SIMD instructions is also being checked
2069 operand_type_register_match (i386_operand_type g0
,
2070 i386_operand_type t0
,
2071 i386_operand_type g1
,
2072 i386_operand_type t1
)
2074 if (!g0
.bitfield
.reg
2075 && !g0
.bitfield
.regsimd
2076 && (!operand_type_check (g0
, anymem
)
2077 || g0
.bitfield
.unspecified
2078 || !t0
.bitfield
.regsimd
))
2081 if (!g1
.bitfield
.reg
2082 && !g1
.bitfield
.regsimd
2083 && (!operand_type_check (g1
, anymem
)
2084 || g1
.bitfield
.unspecified
2085 || !t1
.bitfield
.regsimd
))
2088 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2089 && g0
.bitfield
.word
== g1
.bitfield
.word
2090 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2091 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2092 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2093 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2094 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2097 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2098 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2099 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2100 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2101 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2102 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2103 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2106 i
.error
= register_type_mismatch
;
2111 static INLINE
unsigned int
2112 register_number (const reg_entry
*r
)
2114 unsigned int nr
= r
->reg_num
;
2116 if (r
->reg_flags
& RegRex
)
2119 if (r
->reg_flags
& RegVRex
)
2125 static INLINE
unsigned int
2126 mode_from_disp_size (i386_operand_type t
)
2128 if (t
.bitfield
.disp8
)
2130 else if (t
.bitfield
.disp16
2131 || t
.bitfield
.disp32
2132 || t
.bitfield
.disp32s
)
2139 fits_in_signed_byte (addressT num
)
2141 return num
+ 0x80 <= 0xff;
2145 fits_in_unsigned_byte (addressT num
)
2151 fits_in_unsigned_word (addressT num
)
2153 return num
<= 0xffff;
2157 fits_in_signed_word (addressT num
)
2159 return num
+ 0x8000 <= 0xffff;
2163 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2168 return num
+ 0x80000000 <= 0xffffffff;
2170 } /* fits_in_signed_long() */
2173 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2178 return num
<= 0xffffffff;
2180 } /* fits_in_unsigned_long() */
2183 fits_in_disp8 (offsetT num
)
2185 int shift
= i
.memshift
;
2191 mask
= (1 << shift
) - 1;
2193 /* Return 0 if NUM isn't properly aligned. */
2197 /* Check if NUM will fit in 8bit after shift. */
2198 return fits_in_signed_byte (num
>> shift
);
2202 fits_in_imm4 (offsetT num
)
2204 return (num
& 0xf) == num
;
2207 static i386_operand_type
2208 smallest_imm_type (offsetT num
)
2210 i386_operand_type t
;
2212 operand_type_set (&t
, 0);
2213 t
.bitfield
.imm64
= 1;
2215 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2217 /* This code is disabled on the 486 because all the Imm1 forms
2218 in the opcode table are slower on the i486. They're the
2219 versions with the implicitly specified single-position
2220 displacement, which has another syntax if you really want to
2222 t
.bitfield
.imm1
= 1;
2223 t
.bitfield
.imm8
= 1;
2224 t
.bitfield
.imm8s
= 1;
2225 t
.bitfield
.imm16
= 1;
2226 t
.bitfield
.imm32
= 1;
2227 t
.bitfield
.imm32s
= 1;
2229 else if (fits_in_signed_byte (num
))
2231 t
.bitfield
.imm8
= 1;
2232 t
.bitfield
.imm8s
= 1;
2233 t
.bitfield
.imm16
= 1;
2234 t
.bitfield
.imm32
= 1;
2235 t
.bitfield
.imm32s
= 1;
2237 else if (fits_in_unsigned_byte (num
))
2239 t
.bitfield
.imm8
= 1;
2240 t
.bitfield
.imm16
= 1;
2241 t
.bitfield
.imm32
= 1;
2242 t
.bitfield
.imm32s
= 1;
2244 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2246 t
.bitfield
.imm16
= 1;
2247 t
.bitfield
.imm32
= 1;
2248 t
.bitfield
.imm32s
= 1;
2250 else if (fits_in_signed_long (num
))
2252 t
.bitfield
.imm32
= 1;
2253 t
.bitfield
.imm32s
= 1;
2255 else if (fits_in_unsigned_long (num
))
2256 t
.bitfield
.imm32
= 1;
2262 offset_in_range (offsetT val
, int size
)
2268 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2269 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2270 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2272 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2278 /* If BFD64, sign extend val for 32bit address mode. */
2279 if (flag_code
!= CODE_64BIT
2280 || i
.prefix
[ADDR_PREFIX
])
2281 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2282 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2285 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2287 char buf1
[40], buf2
[40];
2289 sprint_value (buf1
, val
);
2290 sprint_value (buf2
, val
& mask
);
2291 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2306 a. PREFIX_EXIST if attempting to add a prefix where one from the
2307 same class already exists.
2308 b. PREFIX_LOCK if lock prefix is added.
2309 c. PREFIX_REP if rep/repne prefix is added.
2310 d. PREFIX_DS if ds prefix is added.
2311 e. PREFIX_OTHER if other prefix is added.
2314 static enum PREFIX_GROUP
2315 add_prefix (unsigned int prefix
)
2317 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2320 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2321 && flag_code
== CODE_64BIT
)
2323 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2324 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2325 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2336 case DS_PREFIX_OPCODE
:
2339 case CS_PREFIX_OPCODE
:
2340 case ES_PREFIX_OPCODE
:
2341 case FS_PREFIX_OPCODE
:
2342 case GS_PREFIX_OPCODE
:
2343 case SS_PREFIX_OPCODE
:
2347 case REPNE_PREFIX_OPCODE
:
2348 case REPE_PREFIX_OPCODE
:
2353 case LOCK_PREFIX_OPCODE
:
2362 case ADDR_PREFIX_OPCODE
:
2366 case DATA_PREFIX_OPCODE
:
2370 if (i
.prefix
[q
] != 0)
2378 i
.prefix
[q
] |= prefix
;
2381 as_bad (_("same type of prefix used twice"));
2387 update_code_flag (int value
, int check
)
2389 PRINTF_LIKE ((*as_error
));
2391 flag_code
= (enum flag_code
) value
;
2392 if (flag_code
== CODE_64BIT
)
2394 cpu_arch_flags
.bitfield
.cpu64
= 1;
2395 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2399 cpu_arch_flags
.bitfield
.cpu64
= 0;
2400 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2402 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2405 as_error
= as_fatal
;
2408 (*as_error
) (_("64bit mode not supported on `%s'."),
2409 cpu_arch_name
? cpu_arch_name
: default_arch
);
2411 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2414 as_error
= as_fatal
;
2417 (*as_error
) (_("32bit mode not supported on `%s'."),
2418 cpu_arch_name
? cpu_arch_name
: default_arch
);
2420 stackop_size
= '\0';
2424 set_code_flag (int value
)
2426 update_code_flag (value
, 0);
2430 set_16bit_gcc_code_flag (int new_code_flag
)
2432 flag_code
= (enum flag_code
) new_code_flag
;
2433 if (flag_code
!= CODE_16BIT
)
2435 cpu_arch_flags
.bitfield
.cpu64
= 0;
2436 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2437 stackop_size
= LONG_MNEM_SUFFIX
;
2441 set_intel_syntax (int syntax_flag
)
2443 /* Find out if register prefixing is specified. */
2444 int ask_naked_reg
= 0;
2447 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2450 int e
= get_symbol_name (&string
);
2452 if (strcmp (string
, "prefix") == 0)
2454 else if (strcmp (string
, "noprefix") == 0)
2457 as_bad (_("bad argument to syntax directive."));
2458 (void) restore_line_pointer (e
);
2460 demand_empty_rest_of_line ();
2462 intel_syntax
= syntax_flag
;
2464 if (ask_naked_reg
== 0)
2465 allow_naked_reg
= (intel_syntax
2466 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2468 allow_naked_reg
= (ask_naked_reg
< 0);
2470 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2472 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2473 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2474 register_prefix
= allow_naked_reg
? "" : "%";
2478 set_intel_mnemonic (int mnemonic_flag
)
2480 intel_mnemonic
= mnemonic_flag
;
2484 set_allow_index_reg (int flag
)
2486 allow_index_reg
= flag
;
2490 set_check (int what
)
2492 enum check_kind
*kind
;
2497 kind
= &operand_check
;
2508 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2511 int e
= get_symbol_name (&string
);
2513 if (strcmp (string
, "none") == 0)
2515 else if (strcmp (string
, "warning") == 0)
2516 *kind
= check_warning
;
2517 else if (strcmp (string
, "error") == 0)
2518 *kind
= check_error
;
2520 as_bad (_("bad argument to %s_check directive."), str
);
2521 (void) restore_line_pointer (e
);
2524 as_bad (_("missing argument for %s_check directive"), str
);
2526 demand_empty_rest_of_line ();
2530 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2531 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2533 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2534 static const char *arch
;
2536 /* Intel LIOM is only supported on ELF. */
2542 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2543 use default_arch. */
2544 arch
= cpu_arch_name
;
2546 arch
= default_arch
;
2549 /* If we are targeting Intel MCU, we must enable it. */
2550 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2551 || new_flag
.bitfield
.cpuiamcu
)
2554 /* If we are targeting Intel L1OM, we must enable it. */
2555 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2556 || new_flag
.bitfield
.cpul1om
)
2559 /* If we are targeting Intel K1OM, we must enable it. */
2560 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2561 || new_flag
.bitfield
.cpuk1om
)
2564 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2569 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2573 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2576 int e
= get_symbol_name (&string
);
2578 i386_cpu_flags flags
;
2580 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2582 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2584 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2588 cpu_arch_name
= cpu_arch
[j
].name
;
2589 cpu_sub_arch_name
= NULL
;
2590 cpu_arch_flags
= cpu_arch
[j
].flags
;
2591 if (flag_code
== CODE_64BIT
)
2593 cpu_arch_flags
.bitfield
.cpu64
= 1;
2594 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2598 cpu_arch_flags
.bitfield
.cpu64
= 0;
2599 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2601 cpu_arch_isa
= cpu_arch
[j
].type
;
2602 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2603 if (!cpu_arch_tune_set
)
2605 cpu_arch_tune
= cpu_arch_isa
;
2606 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2611 flags
= cpu_flags_or (cpu_arch_flags
,
2614 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2616 if (cpu_sub_arch_name
)
2618 char *name
= cpu_sub_arch_name
;
2619 cpu_sub_arch_name
= concat (name
,
2621 (const char *) NULL
);
2625 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2626 cpu_arch_flags
= flags
;
2627 cpu_arch_isa_flags
= flags
;
2629 (void) restore_line_pointer (e
);
2630 demand_empty_rest_of_line ();
2635 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2637 /* Disable an ISA extension. */
2638 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2639 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2641 flags
= cpu_flags_and_not (cpu_arch_flags
,
2642 cpu_noarch
[j
].flags
);
2643 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2645 if (cpu_sub_arch_name
)
2647 char *name
= cpu_sub_arch_name
;
2648 cpu_sub_arch_name
= concat (name
, string
,
2649 (const char *) NULL
);
2653 cpu_sub_arch_name
= xstrdup (string
);
2654 cpu_arch_flags
= flags
;
2655 cpu_arch_isa_flags
= flags
;
2657 (void) restore_line_pointer (e
);
2658 demand_empty_rest_of_line ();
2662 j
= ARRAY_SIZE (cpu_arch
);
2665 if (j
>= ARRAY_SIZE (cpu_arch
))
2666 as_bad (_("no such architecture: `%s'"), string
);
2668 *input_line_pointer
= e
;
2671 as_bad (_("missing cpu architecture"));
2673 no_cond_jump_promotion
= 0;
2674 if (*input_line_pointer
== ','
2675 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2680 ++input_line_pointer
;
2681 e
= get_symbol_name (&string
);
2683 if (strcmp (string
, "nojumps") == 0)
2684 no_cond_jump_promotion
= 1;
2685 else if (strcmp (string
, "jumps") == 0)
2688 as_bad (_("no such architecture modifier: `%s'"), string
);
2690 (void) restore_line_pointer (e
);
2693 demand_empty_rest_of_line ();
2696 enum bfd_architecture
2699 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2701 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2702 || flag_code
!= CODE_64BIT
)
2703 as_fatal (_("Intel L1OM is 64bit ELF only"));
2704 return bfd_arch_l1om
;
2706 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2708 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2709 || flag_code
!= CODE_64BIT
)
2710 as_fatal (_("Intel K1OM is 64bit ELF only"));
2711 return bfd_arch_k1om
;
2713 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2715 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2716 || flag_code
== CODE_64BIT
)
2717 as_fatal (_("Intel MCU is 32bit ELF only"));
2718 return bfd_arch_iamcu
;
2721 return bfd_arch_i386
;
2727 if (!strncmp (default_arch
, "x86_64", 6))
2729 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2731 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2732 || default_arch
[6] != '\0')
2733 as_fatal (_("Intel L1OM is 64bit ELF only"));
2734 return bfd_mach_l1om
;
2736 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2738 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2739 || default_arch
[6] != '\0')
2740 as_fatal (_("Intel K1OM is 64bit ELF only"));
2741 return bfd_mach_k1om
;
2743 else if (default_arch
[6] == '\0')
2744 return bfd_mach_x86_64
;
2746 return bfd_mach_x64_32
;
2748 else if (!strcmp (default_arch
, "i386")
2749 || !strcmp (default_arch
, "iamcu"))
2751 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2753 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2754 as_fatal (_("Intel MCU is 32bit ELF only"));
2755 return bfd_mach_i386_iamcu
;
2758 return bfd_mach_i386_i386
;
2761 as_fatal (_("unknown architecture"));
2767 const char *hash_err
;
2769 /* Support pseudo prefixes like {disp32}. */
2770 lex_type
['{'] = LEX_BEGIN_NAME
;
2772 /* Initialize op_hash hash table. */
2773 op_hash
= hash_new ();
2776 const insn_template
*optab
;
2777 templates
*core_optab
;
2779 /* Setup for loop. */
2781 core_optab
= XNEW (templates
);
2782 core_optab
->start
= optab
;
2787 if (optab
->name
== NULL
2788 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2790 /* different name --> ship out current template list;
2791 add to hash table; & begin anew. */
2792 core_optab
->end
= optab
;
2793 hash_err
= hash_insert (op_hash
,
2795 (void *) core_optab
);
2798 as_fatal (_("can't hash %s: %s"),
2802 if (optab
->name
== NULL
)
2804 core_optab
= XNEW (templates
);
2805 core_optab
->start
= optab
;
2810 /* Initialize reg_hash hash table. */
2811 reg_hash
= hash_new ();
2813 const reg_entry
*regtab
;
2814 unsigned int regtab_size
= i386_regtab_size
;
2816 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2818 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2820 as_fatal (_("can't hash %s: %s"),
2826 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2831 for (c
= 0; c
< 256; c
++)
2836 mnemonic_chars
[c
] = c
;
2837 register_chars
[c
] = c
;
2838 operand_chars
[c
] = c
;
2840 else if (ISLOWER (c
))
2842 mnemonic_chars
[c
] = c
;
2843 register_chars
[c
] = c
;
2844 operand_chars
[c
] = c
;
2846 else if (ISUPPER (c
))
2848 mnemonic_chars
[c
] = TOLOWER (c
);
2849 register_chars
[c
] = mnemonic_chars
[c
];
2850 operand_chars
[c
] = c
;
2852 else if (c
== '{' || c
== '}')
2854 mnemonic_chars
[c
] = c
;
2855 operand_chars
[c
] = c
;
2858 if (ISALPHA (c
) || ISDIGIT (c
))
2859 identifier_chars
[c
] = c
;
2862 identifier_chars
[c
] = c
;
2863 operand_chars
[c
] = c
;
2868 identifier_chars
['@'] = '@';
2871 identifier_chars
['?'] = '?';
2872 operand_chars
['?'] = '?';
2874 digit_chars
['-'] = '-';
2875 mnemonic_chars
['_'] = '_';
2876 mnemonic_chars
['-'] = '-';
2877 mnemonic_chars
['.'] = '.';
2878 identifier_chars
['_'] = '_';
2879 identifier_chars
['.'] = '.';
2881 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2882 operand_chars
[(unsigned char) *p
] = *p
;
2885 if (flag_code
== CODE_64BIT
)
2887 #if defined (OBJ_COFF) && defined (TE_PE)
2888 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2891 x86_dwarf2_return_column
= 16;
2893 x86_cie_data_alignment
= -8;
2897 x86_dwarf2_return_column
= 8;
2898 x86_cie_data_alignment
= -4;
2903 i386_print_statistics (FILE *file
)
2905 hash_print_statistics (file
, "i386 opcode", op_hash
);
2906 hash_print_statistics (file
, "i386 register", reg_hash
);
2911 /* Debugging routines for md_assemble. */
2912 static void pte (insn_template
*);
2913 static void pt (i386_operand_type
);
2914 static void pe (expressionS
*);
2915 static void ps (symbolS
*);
2918 pi (char *line
, i386_insn
*x
)
2922 fprintf (stdout
, "%s: template ", line
);
2924 fprintf (stdout
, " address: base %s index %s scale %x\n",
2925 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2926 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2927 x
->log2_scale_factor
);
2928 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2929 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2930 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2931 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2932 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2933 (x
->rex
& REX_W
) != 0,
2934 (x
->rex
& REX_R
) != 0,
2935 (x
->rex
& REX_X
) != 0,
2936 (x
->rex
& REX_B
) != 0);
2937 for (j
= 0; j
< x
->operands
; j
++)
2939 fprintf (stdout
, " #%d: ", j
+ 1);
2941 fprintf (stdout
, "\n");
2942 if (x
->types
[j
].bitfield
.reg
2943 || x
->types
[j
].bitfield
.regmmx
2944 || x
->types
[j
].bitfield
.regsimd
2945 || x
->types
[j
].bitfield
.sreg2
2946 || x
->types
[j
].bitfield
.sreg3
2947 || x
->types
[j
].bitfield
.control
2948 || x
->types
[j
].bitfield
.debug
2949 || x
->types
[j
].bitfield
.test
)
2950 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2951 if (operand_type_check (x
->types
[j
], imm
))
2953 if (operand_type_check (x
->types
[j
], disp
))
2954 pe (x
->op
[j
].disps
);
2959 pte (insn_template
*t
)
2962 fprintf (stdout
, " %d operands ", t
->operands
);
2963 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2964 if (t
->extension_opcode
!= None
)
2965 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2966 if (t
->opcode_modifier
.d
)
2967 fprintf (stdout
, "D");
2968 if (t
->opcode_modifier
.w
)
2969 fprintf (stdout
, "W");
2970 fprintf (stdout
, "\n");
2971 for (j
= 0; j
< t
->operands
; j
++)
2973 fprintf (stdout
, " #%d type ", j
+ 1);
2974 pt (t
->operand_types
[j
]);
2975 fprintf (stdout
, "\n");
2982 fprintf (stdout
, " operation %d\n", e
->X_op
);
2983 fprintf (stdout
, " add_number %ld (%lx)\n",
2984 (long) e
->X_add_number
, (long) e
->X_add_number
);
2985 if (e
->X_add_symbol
)
2987 fprintf (stdout
, " add_symbol ");
2988 ps (e
->X_add_symbol
);
2989 fprintf (stdout
, "\n");
2993 fprintf (stdout
, " op_symbol ");
2994 ps (e
->X_op_symbol
);
2995 fprintf (stdout
, "\n");
3002 fprintf (stdout
, "%s type %s%s",
3004 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3005 segment_name (S_GET_SEGMENT (s
)));
3008 static struct type_name
3010 i386_operand_type mask
;
3013 const type_names
[] =
3015 { OPERAND_TYPE_REG8
, "r8" },
3016 { OPERAND_TYPE_REG16
, "r16" },
3017 { OPERAND_TYPE_REG32
, "r32" },
3018 { OPERAND_TYPE_REG64
, "r64" },
3019 { OPERAND_TYPE_IMM8
, "i8" },
3020 { OPERAND_TYPE_IMM8
, "i8s" },
3021 { OPERAND_TYPE_IMM16
, "i16" },
3022 { OPERAND_TYPE_IMM32
, "i32" },
3023 { OPERAND_TYPE_IMM32S
, "i32s" },
3024 { OPERAND_TYPE_IMM64
, "i64" },
3025 { OPERAND_TYPE_IMM1
, "i1" },
3026 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3027 { OPERAND_TYPE_DISP8
, "d8" },
3028 { OPERAND_TYPE_DISP16
, "d16" },
3029 { OPERAND_TYPE_DISP32
, "d32" },
3030 { OPERAND_TYPE_DISP32S
, "d32s" },
3031 { OPERAND_TYPE_DISP64
, "d64" },
3032 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3033 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3034 { OPERAND_TYPE_CONTROL
, "control reg" },
3035 { OPERAND_TYPE_TEST
, "test reg" },
3036 { OPERAND_TYPE_DEBUG
, "debug reg" },
3037 { OPERAND_TYPE_FLOATREG
, "FReg" },
3038 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3039 { OPERAND_TYPE_SREG2
, "SReg2" },
3040 { OPERAND_TYPE_SREG3
, "SReg3" },
3041 { OPERAND_TYPE_ACC
, "Acc" },
3042 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
3043 { OPERAND_TYPE_REGMMX
, "rMMX" },
3044 { OPERAND_TYPE_REGXMM
, "rXMM" },
3045 { OPERAND_TYPE_REGYMM
, "rYMM" },
3046 { OPERAND_TYPE_REGZMM
, "rZMM" },
3047 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3048 { OPERAND_TYPE_ESSEG
, "es" },
3052 pt (i386_operand_type t
)
3055 i386_operand_type a
;
3057 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3059 a
= operand_type_and (t
, type_names
[j
].mask
);
3060 if (!operand_type_all_zero (&a
))
3061 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3066 #endif /* DEBUG386 */
3068 static bfd_reloc_code_real_type
3069 reloc (unsigned int size
,
3072 bfd_reloc_code_real_type other
)
3074 if (other
!= NO_RELOC
)
3076 reloc_howto_type
*rel
;
3081 case BFD_RELOC_X86_64_GOT32
:
3082 return BFD_RELOC_X86_64_GOT64
;
3084 case BFD_RELOC_X86_64_GOTPLT64
:
3085 return BFD_RELOC_X86_64_GOTPLT64
;
3087 case BFD_RELOC_X86_64_PLTOFF64
:
3088 return BFD_RELOC_X86_64_PLTOFF64
;
3090 case BFD_RELOC_X86_64_GOTPC32
:
3091 other
= BFD_RELOC_X86_64_GOTPC64
;
3093 case BFD_RELOC_X86_64_GOTPCREL
:
3094 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3096 case BFD_RELOC_X86_64_TPOFF32
:
3097 other
= BFD_RELOC_X86_64_TPOFF64
;
3099 case BFD_RELOC_X86_64_DTPOFF32
:
3100 other
= BFD_RELOC_X86_64_DTPOFF64
;
3106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3107 if (other
== BFD_RELOC_SIZE32
)
3110 other
= BFD_RELOC_SIZE64
;
3113 as_bad (_("there are no pc-relative size relocations"));
3119 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3120 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3123 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3125 as_bad (_("unknown relocation (%u)"), other
);
3126 else if (size
!= bfd_get_reloc_size (rel
))
3127 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3128 bfd_get_reloc_size (rel
),
3130 else if (pcrel
&& !rel
->pc_relative
)
3131 as_bad (_("non-pc-relative relocation for pc-relative field"));
3132 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3134 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3136 as_bad (_("relocated field and relocation type differ in signedness"));
3145 as_bad (_("there are no unsigned pc-relative relocations"));
3148 case 1: return BFD_RELOC_8_PCREL
;
3149 case 2: return BFD_RELOC_16_PCREL
;
3150 case 4: return BFD_RELOC_32_PCREL
;
3151 case 8: return BFD_RELOC_64_PCREL
;
3153 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3160 case 4: return BFD_RELOC_X86_64_32S
;
3165 case 1: return BFD_RELOC_8
;
3166 case 2: return BFD_RELOC_16
;
3167 case 4: return BFD_RELOC_32
;
3168 case 8: return BFD_RELOC_64
;
3170 as_bad (_("cannot do %s %u byte relocation"),
3171 sign
> 0 ? "signed" : "unsigned", size
);
3177 /* Here we decide which fixups can be adjusted to make them relative to
3178 the beginning of the section instead of the symbol. Basically we need
3179 to make sure that the dynamic relocations are done correctly, so in
3180 some cases we force the original symbol to be used. */
3183 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3189 /* Don't adjust pc-relative references to merge sections in 64-bit
3191 if (use_rela_relocations
3192 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3196 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3197 and changed later by validate_fix. */
3198 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3199 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3202 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3203 for size relocations. */
3204 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3205 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3206 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3207 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3208 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3209 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3210 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3211 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3212 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3213 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3214 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3215 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3216 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3217 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3218 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3219 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3220 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3221 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3222 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3223 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3224 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3225 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3226 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3227 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3228 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3229 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3230 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3231 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3232 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3233 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3234 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3235 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3236 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3243 intel_float_operand (const char *mnemonic
)
3245 /* Note that the value returned is meaningful only for opcodes with (memory)
3246 operands, hence the code here is free to improperly handle opcodes that
3247 have no operands (for better performance and smaller code). */
3249 if (mnemonic
[0] != 'f')
3250 return 0; /* non-math */
3252 switch (mnemonic
[1])
3254 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3255 the fs segment override prefix not currently handled because no
3256 call path can make opcodes without operands get here */
3258 return 2 /* integer op */;
3260 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3261 return 3; /* fldcw/fldenv */
3264 if (mnemonic
[2] != 'o' /* fnop */)
3265 return 3; /* non-waiting control op */
3268 if (mnemonic
[2] == 's')
3269 return 3; /* frstor/frstpm */
3272 if (mnemonic
[2] == 'a')
3273 return 3; /* fsave */
3274 if (mnemonic
[2] == 't')
3276 switch (mnemonic
[3])
3278 case 'c': /* fstcw */
3279 case 'd': /* fstdw */
3280 case 'e': /* fstenv */
3281 case 's': /* fsts[gw] */
3287 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3288 return 0; /* fxsave/fxrstor are not really math ops */
3295 /* Build the VEX prefix. */
3298 build_vex_prefix (const insn_template
*t
)
3300 unsigned int register_specifier
;
3301 unsigned int implied_prefix
;
3302 unsigned int vector_length
;
3304 /* Check register specifier. */
3305 if (i
.vex
.register_specifier
)
3307 register_specifier
=
3308 ~register_number (i
.vex
.register_specifier
) & 0xf;
3309 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3312 register_specifier
= 0xf;
3314 /* Use 2-byte VEX prefix by swapping destination and source
3316 if (i
.vec_encoding
!= vex_encoding_vex3
3317 && i
.dir_encoding
== dir_encoding_default
3318 && i
.operands
== i
.reg_operands
3319 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3320 && i
.tm
.opcode_modifier
.load
3323 unsigned int xchg
= i
.operands
- 1;
3324 union i386_op temp_op
;
3325 i386_operand_type temp_type
;
3327 temp_type
= i
.types
[xchg
];
3328 i
.types
[xchg
] = i
.types
[0];
3329 i
.types
[0] = temp_type
;
3330 temp_op
= i
.op
[xchg
];
3331 i
.op
[xchg
] = i
.op
[0];
3334 gas_assert (i
.rm
.mode
== 3);
3338 i
.rm
.regmem
= i
.rm
.reg
;
3341 /* Use the next insn. */
3345 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3346 vector_length
= avxscalar
;
3347 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3354 for (op
= 0; op
< t
->operands
; ++op
)
3355 if (t
->operand_types
[op
].bitfield
.xmmword
3356 && t
->operand_types
[op
].bitfield
.ymmword
3357 && i
.types
[op
].bitfield
.ymmword
)
3364 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3369 case DATA_PREFIX_OPCODE
:
3372 case REPE_PREFIX_OPCODE
:
3375 case REPNE_PREFIX_OPCODE
:
3382 /* Use 2-byte VEX prefix if possible. */
3383 if (i
.vec_encoding
!= vex_encoding_vex3
3384 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3385 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3386 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3388 /* 2-byte VEX prefix. */
3392 i
.vex
.bytes
[0] = 0xc5;
3394 /* Check the REX.R bit. */
3395 r
= (i
.rex
& REX_R
) ? 0 : 1;
3396 i
.vex
.bytes
[1] = (r
<< 7
3397 | register_specifier
<< 3
3398 | vector_length
<< 2
3403 /* 3-byte VEX prefix. */
3408 switch (i
.tm
.opcode_modifier
.vexopcode
)
3412 i
.vex
.bytes
[0] = 0xc4;
3416 i
.vex
.bytes
[0] = 0xc4;
3420 i
.vex
.bytes
[0] = 0xc4;
3424 i
.vex
.bytes
[0] = 0x8f;
3428 i
.vex
.bytes
[0] = 0x8f;
3432 i
.vex
.bytes
[0] = 0x8f;
3438 /* The high 3 bits of the second VEX byte are 1's compliment
3439 of RXB bits from REX. */
3440 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3442 /* Check the REX.W bit. */
3443 w
= (i
.rex
& REX_W
) ? 1 : 0;
3444 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3447 i
.vex
.bytes
[2] = (w
<< 7
3448 | register_specifier
<< 3
3449 | vector_length
<< 2
3454 /* Build the EVEX prefix. */
3457 build_evex_prefix (void)
3459 unsigned int register_specifier
;
3460 unsigned int implied_prefix
;
3462 rex_byte vrex_used
= 0;
3464 /* Check register specifier. */
3465 if (i
.vex
.register_specifier
)
3467 gas_assert ((i
.vrex
& REX_X
) == 0);
3469 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3470 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3471 register_specifier
+= 8;
3472 /* The upper 16 registers are encoded in the fourth byte of the
3474 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3475 i
.vex
.bytes
[3] = 0x8;
3476 register_specifier
= ~register_specifier
& 0xf;
3480 register_specifier
= 0xf;
3482 /* Encode upper 16 vector index register in the fourth byte of
3484 if (!(i
.vrex
& REX_X
))
3485 i
.vex
.bytes
[3] = 0x8;
3490 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3495 case DATA_PREFIX_OPCODE
:
3498 case REPE_PREFIX_OPCODE
:
3501 case REPNE_PREFIX_OPCODE
:
3508 /* 4 byte EVEX prefix. */
3510 i
.vex
.bytes
[0] = 0x62;
3513 switch (i
.tm
.opcode_modifier
.vexopcode
)
3529 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3531 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3533 /* The fifth bit of the second EVEX byte is 1's compliment of the
3534 REX_R bit in VREX. */
3535 if (!(i
.vrex
& REX_R
))
3536 i
.vex
.bytes
[1] |= 0x10;
3540 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3542 /* When all operands are registers, the REX_X bit in REX is not
3543 used. We reuse it to encode the upper 16 registers, which is
3544 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3545 as 1's compliment. */
3546 if ((i
.vrex
& REX_B
))
3549 i
.vex
.bytes
[1] &= ~0x40;
3553 /* EVEX instructions shouldn't need the REX prefix. */
3554 i
.vrex
&= ~vrex_used
;
3555 gas_assert (i
.vrex
== 0);
3557 /* Check the REX.W bit. */
3558 w
= (i
.rex
& REX_W
) ? 1 : 0;
3559 if (i
.tm
.opcode_modifier
.vexw
)
3561 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3564 /* If w is not set it means we are dealing with WIG instruction. */
3567 if (evexwig
== evexw1
)
3571 /* Encode the U bit. */
3572 implied_prefix
|= 0x4;
3574 /* The third byte of the EVEX prefix. */
3575 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3577 /* The fourth byte of the EVEX prefix. */
3578 /* The zeroing-masking bit. */
3579 if (i
.mask
&& i
.mask
->zeroing
)
3580 i
.vex
.bytes
[3] |= 0x80;
3582 /* Don't always set the broadcast bit if there is no RC. */
3585 /* Encode the vector length. */
3586 unsigned int vec_length
;
3588 switch (i
.tm
.opcode_modifier
.evex
)
3590 case EVEXLIG
: /* LL' is ignored */
3591 vec_length
= evexlig
<< 5;
3594 vec_length
= 0 << 5;
3597 vec_length
= 1 << 5;
3600 vec_length
= 2 << 5;
3606 i
.vex
.bytes
[3] |= vec_length
;
3607 /* Encode the broadcast bit. */
3609 i
.vex
.bytes
[3] |= 0x10;
3613 if (i
.rounding
->type
!= saeonly
)
3614 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3616 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3619 if (i
.mask
&& i
.mask
->mask
)
3620 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3624 process_immext (void)
3628 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3631 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3632 with an opcode suffix which is coded in the same place as an
3633 8-bit immediate field would be.
3634 Here we check those operands and remove them afterwards. */
3637 for (x
= 0; x
< i
.operands
; x
++)
3638 if (register_number (i
.op
[x
].regs
) != x
)
3639 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3640 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3646 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3648 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3649 suffix which is coded in the same place as an 8-bit immediate
3651 Here we check those operands and remove them afterwards. */
3654 if (i
.operands
!= 3)
3657 for (x
= 0; x
< 2; x
++)
3658 if (register_number (i
.op
[x
].regs
) != x
)
3659 goto bad_register_operand
;
3661 /* Check for third operand for mwaitx/monitorx insn. */
3662 if (register_number (i
.op
[x
].regs
)
3663 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3665 bad_register_operand
:
3666 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3667 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3674 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3675 which is coded in the same place as an 8-bit immediate field
3676 would be. Here we fake an 8-bit immediate operand from the
3677 opcode suffix stored in tm.extension_opcode.
3679 AVX instructions also use this encoding, for some of
3680 3 argument instructions. */
3682 gas_assert (i
.imm_operands
<= 1
3684 || ((i
.tm
.opcode_modifier
.vex
3685 || i
.tm
.opcode_modifier
.evex
)
3686 && i
.operands
<= 4)));
3688 exp
= &im_expressions
[i
.imm_operands
++];
3689 i
.op
[i
.operands
].imms
= exp
;
3690 i
.types
[i
.operands
] = imm8
;
3692 exp
->X_op
= O_constant
;
3693 exp
->X_add_number
= i
.tm
.extension_opcode
;
3694 i
.tm
.extension_opcode
= None
;
3701 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3706 as_bad (_("invalid instruction `%s' after `%s'"),
3707 i
.tm
.name
, i
.hle_prefix
);
3710 if (i
.prefix
[LOCK_PREFIX
])
3712 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3716 case HLEPrefixRelease
:
3717 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3719 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3723 if (i
.mem_operands
== 0
3724 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3726 as_bad (_("memory destination needed for instruction `%s'"
3727 " after `xrelease'"), i
.tm
.name
);
3734 /* Try the shortest encoding by shortening operand size. */
3737 optimize_encoding (void)
3741 if (optimize_for_space
3742 && i
.reg_operands
== 1
3743 && i
.imm_operands
== 1
3744 && !i
.types
[1].bitfield
.byte
3745 && i
.op
[0].imms
->X_op
== O_constant
3746 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3747 && ((i
.tm
.base_opcode
== 0xa8
3748 && i
.tm
.extension_opcode
== None
)
3749 || (i
.tm
.base_opcode
== 0xf6
3750 && i
.tm
.extension_opcode
== 0x0)))
3753 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3755 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
3756 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
3758 i
.types
[1].bitfield
.byte
= 1;
3759 /* Ignore the suffix. */
3761 if (base_regnum
>= 4
3762 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
3764 /* Handle SP, BP, SI and DI registers. */
3765 if (i
.types
[1].bitfield
.word
)
3767 else if (i
.types
[1].bitfield
.dword
)
3775 else if (flag_code
== CODE_64BIT
3776 && ((i
.reg_operands
== 1
3777 && i
.imm_operands
== 1
3778 && i
.op
[0].imms
->X_op
== O_constant
3779 && ((i
.tm
.base_opcode
== 0xb0
3780 && i
.tm
.extension_opcode
== None
3781 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
3782 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
3783 && (((i
.tm
.base_opcode
== 0x24
3784 || i
.tm
.base_opcode
== 0xa8)
3785 && i
.tm
.extension_opcode
== None
)
3786 || (i
.tm
.base_opcode
== 0x80
3787 && i
.tm
.extension_opcode
== 0x4)
3788 || ((i
.tm
.base_opcode
== 0xf6
3789 || i
.tm
.base_opcode
== 0xc6)
3790 && i
.tm
.extension_opcode
== 0x0)))))
3791 || (i
.reg_operands
== 2
3792 && i
.op
[0].regs
== i
.op
[1].regs
3793 && ((i
.tm
.base_opcode
== 0x30
3794 || i
.tm
.base_opcode
== 0x28)
3795 && i
.tm
.extension_opcode
== None
)))
3796 && i
.types
[1].bitfield
.qword
)
3799 andq $imm31, %r64 -> andl $imm31, %r32
3800 testq $imm31, %r64 -> testl $imm31, %r32
3801 xorq %r64, %r64 -> xorl %r32, %r32
3802 subq %r64, %r64 -> subl %r32, %r32
3803 movq $imm31, %r64 -> movl $imm31, %r32
3804 movq $imm32, %r64 -> movl $imm32, %r32
3806 i
.tm
.opcode_modifier
.norex64
= 1;
3807 if (i
.tm
.base_opcode
== 0xb0 || i
.tm
.base_opcode
== 0xc6)
3810 movq $imm31, %r64 -> movl $imm31, %r32
3811 movq $imm32, %r64 -> movl $imm32, %r32
3813 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
3814 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
3815 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
3816 i
.types
[0].bitfield
.imm32
= 1;
3817 i
.types
[0].bitfield
.imm32s
= 0;
3818 i
.types
[0].bitfield
.imm64
= 0;
3819 i
.types
[1].bitfield
.dword
= 1;
3820 i
.types
[1].bitfield
.qword
= 0;
3821 if (i
.tm
.base_opcode
== 0xc6)
3824 movq $imm31, %r64 -> movl $imm31, %r32
3826 i
.tm
.base_opcode
= 0xb0;
3827 i
.tm
.extension_opcode
= None
;
3828 i
.tm
.opcode_modifier
.shortform
= 1;
3829 i
.tm
.opcode_modifier
.modrm
= 0;
3833 else if (optimize
> 1
3834 && i
.reg_operands
== 3
3835 && i
.op
[0].regs
== i
.op
[1].regs
3836 && !i
.types
[2].bitfield
.xmmword
3837 && (i
.tm
.opcode_modifier
.vex
3840 && i
.tm
.opcode_modifier
.evex
3841 && cpu_arch_flags
.bitfield
.cpuavx512vl
))
3842 && ((i
.tm
.base_opcode
== 0x55
3843 || i
.tm
.base_opcode
== 0x6655
3844 || i
.tm
.base_opcode
== 0x66df
3845 || i
.tm
.base_opcode
== 0x57
3846 || i
.tm
.base_opcode
== 0x6657
3847 || i
.tm
.base_opcode
== 0x66ef
3848 || i
.tm
.base_opcode
== 0x66f8
3849 || i
.tm
.base_opcode
== 0x66f9
3850 || i
.tm
.base_opcode
== 0x66fa
3851 || i
.tm
.base_opcode
== 0x66fb)
3852 && i
.tm
.extension_opcode
== None
))
3855 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3857 EVEX VOP %zmmM, %zmmM, %zmmN
3858 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3859 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3860 EVEX VOP %ymmM, %ymmM, %ymmN
3861 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3862 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3863 VEX VOP %ymmM, %ymmM, %ymmN
3864 -> VEX VOP %xmmM, %xmmM, %xmmN
3865 VOP, one of vpandn and vpxor:
3866 VEX VOP %ymmM, %ymmM, %ymmN
3867 -> VEX VOP %xmmM, %xmmM, %xmmN
3868 VOP, one of vpandnd and vpandnq:
3869 EVEX VOP %zmmM, %zmmM, %zmmN
3870 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3871 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3872 EVEX VOP %ymmM, %ymmM, %ymmN
3873 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3874 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3875 VOP, one of vpxord and vpxorq:
3876 EVEX VOP %zmmM, %zmmM, %zmmN
3877 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3878 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3879 EVEX VOP %ymmM, %ymmM, %ymmN
3880 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3883 if (i
.tm
.opcode_modifier
.evex
)
3885 /* If only lower 16 vector registers are used, we can use
3887 for (j
= 0; j
< 3; j
++)
3888 if (register_number (i
.op
[j
].regs
) > 15)
3892 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3895 i
.tm
.opcode_modifier
.vex
= VEX128
;
3896 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
3897 i
.tm
.opcode_modifier
.evex
= 0;
3901 i
.tm
.opcode_modifier
.vex
= VEX128
;
3903 if (i
.tm
.opcode_modifier
.vex
)
3904 for (j
= 0; j
< 3; j
++)
3906 i
.types
[j
].bitfield
.xmmword
= 1;
3907 i
.types
[j
].bitfield
.ymmword
= 0;
3912 /* This is the guts of the machine-dependent assembler. LINE points to a
3913 machine dependent instruction. This function is supposed to emit
3914 the frags/bytes it assembles to. */
3917 md_assemble (char *line
)
3920 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
3921 const insn_template
*t
;
3923 /* Initialize globals. */
3924 memset (&i
, '\0', sizeof (i
));
3925 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3926 i
.reloc
[j
] = NO_RELOC
;
3927 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3928 memset (im_expressions
, '\0', sizeof (im_expressions
));
3929 save_stack_p
= save_stack
;
3931 /* First parse an instruction mnemonic & call i386_operand for the operands.
3932 We assume that the scrubber has arranged it so that line[0] is the valid
3933 start of a (possibly prefixed) mnemonic. */
3935 line
= parse_insn (line
, mnemonic
);
3938 mnem_suffix
= i
.suffix
;
3940 line
= parse_operands (line
, mnemonic
);
3942 xfree (i
.memop1_string
);
3943 i
.memop1_string
= NULL
;
3947 /* Now we've parsed the mnemonic into a set of templates, and have the
3948 operands at hand. */
3950 /* All intel opcodes have reversed operands except for "bound" and
3951 "enter". We also don't reverse intersegment "jmp" and "call"
3952 instructions with 2 immediate operands so that the immediate segment
3953 precedes the offset, as it does when in AT&T mode. */
3956 && (strcmp (mnemonic
, "bound") != 0)
3957 && (strcmp (mnemonic
, "invlpga") != 0)
3958 && !(operand_type_check (i
.types
[0], imm
)
3959 && operand_type_check (i
.types
[1], imm
)))
3962 /* The order of the immediates should be reversed
3963 for 2 immediates extrq and insertq instructions */
3964 if (i
.imm_operands
== 2
3965 && (strcmp (mnemonic
, "extrq") == 0
3966 || strcmp (mnemonic
, "insertq") == 0))
3967 swap_2_operands (0, 1);
3972 /* Don't optimize displacement for movabs since it only takes 64bit
3975 && i
.disp_encoding
!= disp_encoding_32bit
3976 && (flag_code
!= CODE_64BIT
3977 || strcmp (mnemonic
, "movabs") != 0))
3980 /* Next, we find a template that matches the given insn,
3981 making sure the overlap of the given operands types is consistent
3982 with the template operand types. */
3984 if (!(t
= match_template (mnem_suffix
)))
3987 if (sse_check
!= check_none
3988 && !i
.tm
.opcode_modifier
.noavx
3989 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
3990 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3991 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3992 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3993 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3994 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3995 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
3996 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
3997 || i
.tm
.cpu_flags
.bitfield
.cpuaes
3998 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4000 (sse_check
== check_warning
4002 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4005 /* Zap movzx and movsx suffix. The suffix has been set from
4006 "word ptr" or "byte ptr" on the source operand in Intel syntax
4007 or extracted from mnemonic in AT&T syntax. But we'll use
4008 the destination register to choose the suffix for encoding. */
4009 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4011 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4012 there is no suffix, the default will be byte extension. */
4013 if (i
.reg_operands
!= 2
4016 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4021 if (i
.tm
.opcode_modifier
.fwait
)
4022 if (!add_prefix (FWAIT_OPCODE
))
4025 /* Check if REP prefix is OK. */
4026 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4028 as_bad (_("invalid instruction `%s' after `%s'"),
4029 i
.tm
.name
, i
.rep_prefix
);
4033 /* Check for lock without a lockable instruction. Destination operand
4034 must be memory unless it is xchg (0x86). */
4035 if (i
.prefix
[LOCK_PREFIX
]
4036 && (!i
.tm
.opcode_modifier
.islockable
4037 || i
.mem_operands
== 0
4038 || (i
.tm
.base_opcode
!= 0x86
4039 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
4041 as_bad (_("expecting lockable instruction after `lock'"));
4045 /* Check if HLE prefix is OK. */
4046 if (i
.hle_prefix
&& !check_hle ())
4049 /* Check BND prefix. */
4050 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4051 as_bad (_("expecting valid branch instruction after `bnd'"));
4053 /* Check NOTRACK prefix. */
4054 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4055 as_bad (_("expecting indirect branch instruction after `notrack'"));
4057 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4059 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4060 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4061 else if (flag_code
!= CODE_16BIT
4062 ? i
.prefix
[ADDR_PREFIX
]
4063 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4064 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4067 /* Insert BND prefix. */
4069 && i
.tm
.opcode_modifier
.bndprefixok
4070 && !i
.prefix
[BND_PREFIX
])
4071 add_prefix (BND_PREFIX_OPCODE
);
4073 /* Check string instruction segment overrides. */
4074 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
4076 if (!check_string ())
4078 i
.disp_operands
= 0;
4081 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4082 optimize_encoding ();
4084 if (!process_suffix ())
4087 /* Update operand types. */
4088 for (j
= 0; j
< i
.operands
; j
++)
4089 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4091 /* Make still unresolved immediate matches conform to size of immediate
4092 given in i.suffix. */
4093 if (!finalize_imm ())
4096 if (i
.types
[0].bitfield
.imm1
)
4097 i
.imm_operands
= 0; /* kludge for shift insns. */
4099 /* We only need to check those implicit registers for instructions
4100 with 3 operands or less. */
4101 if (i
.operands
<= 3)
4102 for (j
= 0; j
< i
.operands
; j
++)
4103 if (i
.types
[j
].bitfield
.inoutportreg
4104 || i
.types
[j
].bitfield
.shiftcount
4105 || (i
.types
[j
].bitfield
.acc
&& !i
.types
[j
].bitfield
.xmmword
))
4108 /* ImmExt should be processed after SSE2AVX. */
4109 if (!i
.tm
.opcode_modifier
.sse2avx
4110 && i
.tm
.opcode_modifier
.immext
)
4113 /* For insns with operands there are more diddles to do to the opcode. */
4116 if (!process_operands ())
4119 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4121 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4122 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4125 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
4127 if (flag_code
== CODE_16BIT
)
4129 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4134 if (i
.tm
.opcode_modifier
.vex
)
4135 build_vex_prefix (t
);
4137 build_evex_prefix ();
4140 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4141 instructions may define INT_OPCODE as well, so avoid this corner
4142 case for those instructions that use MODRM. */
4143 if (i
.tm
.base_opcode
== INT_OPCODE
4144 && !i
.tm
.opcode_modifier
.modrm
4145 && i
.op
[0].imms
->X_add_number
== 3)
4147 i
.tm
.base_opcode
= INT3_OPCODE
;
4151 if ((i
.tm
.opcode_modifier
.jump
4152 || i
.tm
.opcode_modifier
.jumpbyte
4153 || i
.tm
.opcode_modifier
.jumpdword
)
4154 && i
.op
[0].disps
->X_op
== O_constant
)
4156 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4157 the absolute address given by the constant. Since ix86 jumps and
4158 calls are pc relative, we need to generate a reloc. */
4159 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4160 i
.op
[0].disps
->X_op
= O_symbol
;
4163 if (i
.tm
.opcode_modifier
.rex64
)
4166 /* For 8 bit registers we need an empty rex prefix. Also if the
4167 instruction already has a prefix, we need to convert old
4168 registers to new ones. */
4170 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
4171 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4172 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
4173 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4174 || (((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
4175 || (i
.types
[1].bitfield
.reg
&& i
.types
[1].bitfield
.byte
))
4180 i
.rex
|= REX_OPCODE
;
4181 for (x
= 0; x
< 2; x
++)
4183 /* Look for 8 bit operand that uses old registers. */
4184 if (i
.types
[x
].bitfield
.reg
&& i
.types
[x
].bitfield
.byte
4185 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4187 /* In case it is "hi" register, give up. */
4188 if (i
.op
[x
].regs
->reg_num
> 3)
4189 as_bad (_("can't encode register '%s%s' in an "
4190 "instruction requiring REX prefix."),
4191 register_prefix
, i
.op
[x
].regs
->reg_name
);
4193 /* Otherwise it is equivalent to the extended register.
4194 Since the encoding doesn't change this is merely
4195 cosmetic cleanup for debug output. */
4197 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4202 if (i
.rex
== 0 && i
.rex_encoding
)
4204 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4205 that uses legacy register. If it is "hi" register, don't add
4206 the REX_OPCODE byte. */
4208 for (x
= 0; x
< 2; x
++)
4209 if (i
.types
[x
].bitfield
.reg
4210 && i
.types
[x
].bitfield
.byte
4211 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4212 && i
.op
[x
].regs
->reg_num
> 3)
4214 i
.rex_encoding
= FALSE
;
4223 add_prefix (REX_OPCODE
| i
.rex
);
4225 /* We are ready to output the insn. */
4230 parse_insn (char *line
, char *mnemonic
)
4233 char *token_start
= l
;
4236 const insn_template
*t
;
4242 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4247 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4249 as_bad (_("no such instruction: `%s'"), token_start
);
4254 if (!is_space_char (*l
)
4255 && *l
!= END_OF_INSN
4257 || (*l
!= PREFIX_SEPARATOR
4260 as_bad (_("invalid character %s in mnemonic"),
4261 output_invalid (*l
));
4264 if (token_start
== l
)
4266 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4267 as_bad (_("expecting prefix; got nothing"));
4269 as_bad (_("expecting mnemonic; got nothing"));
4273 /* Look up instruction (or prefix) via hash table. */
4274 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4276 if (*l
!= END_OF_INSN
4277 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4278 && current_templates
4279 && current_templates
->start
->opcode_modifier
.isprefix
)
4281 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4283 as_bad ((flag_code
!= CODE_64BIT
4284 ? _("`%s' is only supported in 64-bit mode")
4285 : _("`%s' is not supported in 64-bit mode")),
4286 current_templates
->start
->name
);
4289 /* If we are in 16-bit mode, do not allow addr16 or data16.
4290 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4291 if ((current_templates
->start
->opcode_modifier
.size16
4292 || current_templates
->start
->opcode_modifier
.size32
)
4293 && flag_code
!= CODE_64BIT
4294 && (current_templates
->start
->opcode_modifier
.size32
4295 ^ (flag_code
== CODE_16BIT
)))
4297 as_bad (_("redundant %s prefix"),
4298 current_templates
->start
->name
);
4301 if (current_templates
->start
->opcode_length
== 0)
4303 /* Handle pseudo prefixes. */
4304 switch (current_templates
->start
->base_opcode
)
4308 i
.disp_encoding
= disp_encoding_8bit
;
4312 i
.disp_encoding
= disp_encoding_32bit
;
4316 i
.dir_encoding
= dir_encoding_load
;
4320 i
.dir_encoding
= dir_encoding_store
;
4324 i
.vec_encoding
= vex_encoding_vex2
;
4328 i
.vec_encoding
= vex_encoding_vex3
;
4332 i
.vec_encoding
= vex_encoding_evex
;
4336 i
.rex_encoding
= TRUE
;
4340 i
.no_optimize
= TRUE
;
4348 /* Add prefix, checking for repeated prefixes. */
4349 switch (add_prefix (current_templates
->start
->base_opcode
))
4354 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4355 i
.notrack_prefix
= current_templates
->start
->name
;
4358 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4359 i
.hle_prefix
= current_templates
->start
->name
;
4360 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4361 i
.bnd_prefix
= current_templates
->start
->name
;
4363 i
.rep_prefix
= current_templates
->start
->name
;
4369 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4376 if (!current_templates
)
4378 /* Check if we should swap operand or force 32bit displacement in
4380 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4381 i
.dir_encoding
= dir_encoding_store
;
4382 else if (mnem_p
- 3 == dot_p
4385 i
.disp_encoding
= disp_encoding_8bit
;
4386 else if (mnem_p
- 4 == dot_p
4390 i
.disp_encoding
= disp_encoding_32bit
;
4395 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4398 if (!current_templates
)
4401 /* See if we can get a match by trimming off a suffix. */
4404 case WORD_MNEM_SUFFIX
:
4405 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4406 i
.suffix
= SHORT_MNEM_SUFFIX
;
4409 case BYTE_MNEM_SUFFIX
:
4410 case QWORD_MNEM_SUFFIX
:
4411 i
.suffix
= mnem_p
[-1];
4413 current_templates
= (const templates
*) hash_find (op_hash
,
4416 case SHORT_MNEM_SUFFIX
:
4417 case LONG_MNEM_SUFFIX
:
4420 i
.suffix
= mnem_p
[-1];
4422 current_templates
= (const templates
*) hash_find (op_hash
,
4431 if (intel_float_operand (mnemonic
) == 1)
4432 i
.suffix
= SHORT_MNEM_SUFFIX
;
4434 i
.suffix
= LONG_MNEM_SUFFIX
;
4436 current_templates
= (const templates
*) hash_find (op_hash
,
4441 if (!current_templates
)
4443 as_bad (_("no such instruction: `%s'"), token_start
);
4448 if (current_templates
->start
->opcode_modifier
.jump
4449 || current_templates
->start
->opcode_modifier
.jumpbyte
)
4451 /* Check for a branch hint. We allow ",pt" and ",pn" for
4452 predict taken and predict not taken respectively.
4453 I'm not sure that branch hints actually do anything on loop
4454 and jcxz insns (JumpByte) for current Pentium4 chips. They
4455 may work in the future and it doesn't hurt to accept them
4457 if (l
[0] == ',' && l
[1] == 'p')
4461 if (!add_prefix (DS_PREFIX_OPCODE
))
4465 else if (l
[2] == 'n')
4467 if (!add_prefix (CS_PREFIX_OPCODE
))
4473 /* Any other comma loses. */
4476 as_bad (_("invalid character %s in mnemonic"),
4477 output_invalid (*l
));
4481 /* Check if instruction is supported on specified architecture. */
4483 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4485 supported
|= cpu_flags_match (t
);
4486 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4488 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4489 as_warn (_("use .code16 to ensure correct addressing mode"));
4495 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4496 as_bad (flag_code
== CODE_64BIT
4497 ? _("`%s' is not supported in 64-bit mode")
4498 : _("`%s' is only supported in 64-bit mode"),
4499 current_templates
->start
->name
);
4501 as_bad (_("`%s' is not supported on `%s%s'"),
4502 current_templates
->start
->name
,
4503 cpu_arch_name
? cpu_arch_name
: default_arch
,
4504 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4510 parse_operands (char *l
, const char *mnemonic
)
4514 /* 1 if operand is pending after ','. */
4515 unsigned int expecting_operand
= 0;
4517 /* Non-zero if operand parens not balanced. */
4518 unsigned int paren_not_balanced
;
4520 while (*l
!= END_OF_INSN
)
4522 /* Skip optional white space before operand. */
4523 if (is_space_char (*l
))
4525 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4527 as_bad (_("invalid character %s before operand %d"),
4528 output_invalid (*l
),
4532 token_start
= l
; /* After white space. */
4533 paren_not_balanced
= 0;
4534 while (paren_not_balanced
|| *l
!= ',')
4536 if (*l
== END_OF_INSN
)
4538 if (paren_not_balanced
)
4541 as_bad (_("unbalanced parenthesis in operand %d."),
4544 as_bad (_("unbalanced brackets in operand %d."),
4549 break; /* we are done */
4551 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4553 as_bad (_("invalid character %s in operand %d"),
4554 output_invalid (*l
),
4561 ++paren_not_balanced
;
4563 --paren_not_balanced
;
4568 ++paren_not_balanced
;
4570 --paren_not_balanced
;
4574 if (l
!= token_start
)
4575 { /* Yes, we've read in another operand. */
4576 unsigned int operand_ok
;
4577 this_operand
= i
.operands
++;
4578 if (i
.operands
> MAX_OPERANDS
)
4580 as_bad (_("spurious operands; (%d operands/instruction max)"),
4584 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4585 /* Now parse operand adding info to 'i' as we go along. */
4586 END_STRING_AND_SAVE (l
);
4590 i386_intel_operand (token_start
,
4591 intel_float_operand (mnemonic
));
4593 operand_ok
= i386_att_operand (token_start
);
4595 RESTORE_END_STRING (l
);
4601 if (expecting_operand
)
4603 expecting_operand_after_comma
:
4604 as_bad (_("expecting operand after ','; got nothing"));
4609 as_bad (_("expecting operand before ','; got nothing"));
4614 /* Now *l must be either ',' or END_OF_INSN. */
4617 if (*++l
== END_OF_INSN
)
4619 /* Just skip it, if it's \n complain. */
4620 goto expecting_operand_after_comma
;
4622 expecting_operand
= 1;
4629 swap_2_operands (int xchg1
, int xchg2
)
4631 union i386_op temp_op
;
4632 i386_operand_type temp_type
;
4633 enum bfd_reloc_code_real temp_reloc
;
4635 temp_type
= i
.types
[xchg2
];
4636 i
.types
[xchg2
] = i
.types
[xchg1
];
4637 i
.types
[xchg1
] = temp_type
;
4638 temp_op
= i
.op
[xchg2
];
4639 i
.op
[xchg2
] = i
.op
[xchg1
];
4640 i
.op
[xchg1
] = temp_op
;
4641 temp_reloc
= i
.reloc
[xchg2
];
4642 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4643 i
.reloc
[xchg1
] = temp_reloc
;
4647 if (i
.mask
->operand
== xchg1
)
4648 i
.mask
->operand
= xchg2
;
4649 else if (i
.mask
->operand
== xchg2
)
4650 i
.mask
->operand
= xchg1
;
4654 if (i
.broadcast
->operand
== xchg1
)
4655 i
.broadcast
->operand
= xchg2
;
4656 else if (i
.broadcast
->operand
== xchg2
)
4657 i
.broadcast
->operand
= xchg1
;
4661 if (i
.rounding
->operand
== xchg1
)
4662 i
.rounding
->operand
= xchg2
;
4663 else if (i
.rounding
->operand
== xchg2
)
4664 i
.rounding
->operand
= xchg1
;
4669 swap_operands (void)
4675 swap_2_operands (1, i
.operands
- 2);
4679 swap_2_operands (0, i
.operands
- 1);
4685 if (i
.mem_operands
== 2)
4687 const seg_entry
*temp_seg
;
4688 temp_seg
= i
.seg
[0];
4689 i
.seg
[0] = i
.seg
[1];
4690 i
.seg
[1] = temp_seg
;
4694 /* Try to ensure constant immediates are represented in the smallest
4699 char guess_suffix
= 0;
4703 guess_suffix
= i
.suffix
;
4704 else if (i
.reg_operands
)
4706 /* Figure out a suffix from the last register operand specified.
4707 We can't do this properly yet, ie. excluding InOutPortReg,
4708 but the following works for instructions with immediates.
4709 In any case, we can't set i.suffix yet. */
4710 for (op
= i
.operands
; --op
>= 0;)
4711 if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.byte
)
4713 guess_suffix
= BYTE_MNEM_SUFFIX
;
4716 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.word
)
4718 guess_suffix
= WORD_MNEM_SUFFIX
;
4721 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.dword
)
4723 guess_suffix
= LONG_MNEM_SUFFIX
;
4726 else if (i
.types
[op
].bitfield
.reg
&& i
.types
[op
].bitfield
.qword
)
4728 guess_suffix
= QWORD_MNEM_SUFFIX
;
4732 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4733 guess_suffix
= WORD_MNEM_SUFFIX
;
4735 for (op
= i
.operands
; --op
>= 0;)
4736 if (operand_type_check (i
.types
[op
], imm
))
4738 switch (i
.op
[op
].imms
->X_op
)
4741 /* If a suffix is given, this operand may be shortened. */
4742 switch (guess_suffix
)
4744 case LONG_MNEM_SUFFIX
:
4745 i
.types
[op
].bitfield
.imm32
= 1;
4746 i
.types
[op
].bitfield
.imm64
= 1;
4748 case WORD_MNEM_SUFFIX
:
4749 i
.types
[op
].bitfield
.imm16
= 1;
4750 i
.types
[op
].bitfield
.imm32
= 1;
4751 i
.types
[op
].bitfield
.imm32s
= 1;
4752 i
.types
[op
].bitfield
.imm64
= 1;
4754 case BYTE_MNEM_SUFFIX
:
4755 i
.types
[op
].bitfield
.imm8
= 1;
4756 i
.types
[op
].bitfield
.imm8s
= 1;
4757 i
.types
[op
].bitfield
.imm16
= 1;
4758 i
.types
[op
].bitfield
.imm32
= 1;
4759 i
.types
[op
].bitfield
.imm32s
= 1;
4760 i
.types
[op
].bitfield
.imm64
= 1;
4764 /* If this operand is at most 16 bits, convert it
4765 to a signed 16 bit number before trying to see
4766 whether it will fit in an even smaller size.
4767 This allows a 16-bit operand such as $0xffe0 to
4768 be recognised as within Imm8S range. */
4769 if ((i
.types
[op
].bitfield
.imm16
)
4770 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4772 i
.op
[op
].imms
->X_add_number
=
4773 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4776 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4777 if ((i
.types
[op
].bitfield
.imm32
)
4778 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4781 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4782 ^ ((offsetT
) 1 << 31))
4783 - ((offsetT
) 1 << 31));
4787 = operand_type_or (i
.types
[op
],
4788 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4790 /* We must avoid matching of Imm32 templates when 64bit
4791 only immediate is available. */
4792 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4793 i
.types
[op
].bitfield
.imm32
= 0;
4800 /* Symbols and expressions. */
4802 /* Convert symbolic operand to proper sizes for matching, but don't
4803 prevent matching a set of insns that only supports sizes other
4804 than those matching the insn suffix. */
4806 i386_operand_type mask
, allowed
;
4807 const insn_template
*t
;
4809 operand_type_set (&mask
, 0);
4810 operand_type_set (&allowed
, 0);
4812 for (t
= current_templates
->start
;
4813 t
< current_templates
->end
;
4815 allowed
= operand_type_or (allowed
,
4816 t
->operand_types
[op
]);
4817 switch (guess_suffix
)
4819 case QWORD_MNEM_SUFFIX
:
4820 mask
.bitfield
.imm64
= 1;
4821 mask
.bitfield
.imm32s
= 1;
4823 case LONG_MNEM_SUFFIX
:
4824 mask
.bitfield
.imm32
= 1;
4826 case WORD_MNEM_SUFFIX
:
4827 mask
.bitfield
.imm16
= 1;
4829 case BYTE_MNEM_SUFFIX
:
4830 mask
.bitfield
.imm8
= 1;
4835 allowed
= operand_type_and (mask
, allowed
);
4836 if (!operand_type_all_zero (&allowed
))
4837 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4844 /* Try to use the smallest displacement type too. */
4846 optimize_disp (void)
4850 for (op
= i
.operands
; --op
>= 0;)
4851 if (operand_type_check (i
.types
[op
], disp
))
4853 if (i
.op
[op
].disps
->X_op
== O_constant
)
4855 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4857 if (i
.types
[op
].bitfield
.disp16
4858 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4860 /* If this operand is at most 16 bits, convert
4861 to a signed 16 bit number and don't use 64bit
4863 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4864 i
.types
[op
].bitfield
.disp64
= 0;
4867 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4868 if (i
.types
[op
].bitfield
.disp32
4869 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4871 /* If this operand is at most 32 bits, convert
4872 to a signed 32 bit number and don't use 64bit
4874 op_disp
&= (((offsetT
) 2 << 31) - 1);
4875 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4876 i
.types
[op
].bitfield
.disp64
= 0;
4879 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4881 i
.types
[op
].bitfield
.disp8
= 0;
4882 i
.types
[op
].bitfield
.disp16
= 0;
4883 i
.types
[op
].bitfield
.disp32
= 0;
4884 i
.types
[op
].bitfield
.disp32s
= 0;
4885 i
.types
[op
].bitfield
.disp64
= 0;
4889 else if (flag_code
== CODE_64BIT
)
4891 if (fits_in_signed_long (op_disp
))
4893 i
.types
[op
].bitfield
.disp64
= 0;
4894 i
.types
[op
].bitfield
.disp32s
= 1;
4896 if (i
.prefix
[ADDR_PREFIX
]
4897 && fits_in_unsigned_long (op_disp
))
4898 i
.types
[op
].bitfield
.disp32
= 1;
4900 if ((i
.types
[op
].bitfield
.disp32
4901 || i
.types
[op
].bitfield
.disp32s
4902 || i
.types
[op
].bitfield
.disp16
)
4903 && fits_in_disp8 (op_disp
))
4904 i
.types
[op
].bitfield
.disp8
= 1;
4906 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4907 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4909 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4910 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4911 i
.types
[op
].bitfield
.disp8
= 0;
4912 i
.types
[op
].bitfield
.disp16
= 0;
4913 i
.types
[op
].bitfield
.disp32
= 0;
4914 i
.types
[op
].bitfield
.disp32s
= 0;
4915 i
.types
[op
].bitfield
.disp64
= 0;
4918 /* We only support 64bit displacement on constants. */
4919 i
.types
[op
].bitfield
.disp64
= 0;
4923 /* Check if operands are valid for the instruction. */
4926 check_VecOperands (const insn_template
*t
)
4930 /* Without VSIB byte, we can't have a vector register for index. */
4931 if (!t
->opcode_modifier
.vecsib
4933 && (i
.index_reg
->reg_type
.bitfield
.xmmword
4934 || i
.index_reg
->reg_type
.bitfield
.ymmword
4935 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
4937 i
.error
= unsupported_vector_index_register
;
4941 /* Check if default mask is allowed. */
4942 if (t
->opcode_modifier
.nodefmask
4943 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4945 i
.error
= no_default_mask
;
4949 /* For VSIB byte, we need a vector register for index, and all vector
4950 registers must be distinct. */
4951 if (t
->opcode_modifier
.vecsib
)
4954 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4955 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
4956 || (t
->opcode_modifier
.vecsib
== VecSIB256
4957 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
4958 || (t
->opcode_modifier
.vecsib
== VecSIB512
4959 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
4961 i
.error
= invalid_vsib_address
;
4965 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4966 if (i
.reg_operands
== 2 && !i
.mask
)
4968 gas_assert (i
.types
[0].bitfield
.regsimd
);
4969 gas_assert (i
.types
[0].bitfield
.xmmword
4970 || i
.types
[0].bitfield
.ymmword
);
4971 gas_assert (i
.types
[2].bitfield
.regsimd
);
4972 gas_assert (i
.types
[2].bitfield
.xmmword
4973 || i
.types
[2].bitfield
.ymmword
);
4974 if (operand_check
== check_none
)
4976 if (register_number (i
.op
[0].regs
)
4977 != register_number (i
.index_reg
)
4978 && register_number (i
.op
[2].regs
)
4979 != register_number (i
.index_reg
)
4980 && register_number (i
.op
[0].regs
)
4981 != register_number (i
.op
[2].regs
))
4983 if (operand_check
== check_error
)
4985 i
.error
= invalid_vector_register_set
;
4988 as_warn (_("mask, index, and destination registers should be distinct"));
4990 else if (i
.reg_operands
== 1 && i
.mask
)
4992 if (i
.types
[1].bitfield
.regsimd
4993 && (i
.types
[1].bitfield
.xmmword
4994 || i
.types
[1].bitfield
.ymmword
4995 || i
.types
[1].bitfield
.zmmword
)
4996 && (register_number (i
.op
[1].regs
)
4997 == register_number (i
.index_reg
)))
4999 if (operand_check
== check_error
)
5001 i
.error
= invalid_vector_register_set
;
5004 if (operand_check
!= check_none
)
5005 as_warn (_("index and destination registers should be distinct"));
5010 /* Check if broadcast is supported by the instruction and is applied
5011 to the memory operand. */
5014 int broadcasted_opnd_size
;
5016 /* Check if specified broadcast is supported in this instruction,
5017 and it's applied to memory operand of DWORD or QWORD type,
5018 depending on VecESize. */
5019 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
5020 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
5021 || (t
->opcode_modifier
.vecesize
== 0
5022 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
5023 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
5024 || (t
->opcode_modifier
.vecesize
== 1
5025 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
5026 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
5029 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
5030 if (i
.broadcast
->type
== BROADCAST_1TO16
)
5031 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
5032 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
5033 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
5034 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
5035 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
5036 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
5037 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
5041 if ((broadcasted_opnd_size
== 256
5042 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
5043 || (broadcasted_opnd_size
== 512
5044 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
5047 i
.error
= unsupported_broadcast
;
5051 /* If broadcast is supported in this instruction, we need to check if
5052 operand of one-element size isn't specified without broadcast. */
5053 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5055 /* Find memory operand. */
5056 for (op
= 0; op
< i
.operands
; op
++)
5057 if (operand_type_check (i
.types
[op
], anymem
))
5059 gas_assert (op
< i
.operands
);
5060 /* Check size of the memory operand. */
5061 if ((t
->opcode_modifier
.vecesize
== 0
5062 && i
.types
[op
].bitfield
.dword
)
5063 || (t
->opcode_modifier
.vecesize
== 1
5064 && i
.types
[op
].bitfield
.qword
))
5066 i
.error
= broadcast_needed
;
5071 /* Check if requested masking is supported. */
5073 && (!t
->opcode_modifier
.masking
5075 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
5077 i
.error
= unsupported_masking
;
5081 /* Check if masking is applied to dest operand. */
5082 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5084 i
.error
= mask_not_on_destination
;
5091 if ((i
.rounding
->type
!= saeonly
5092 && !t
->opcode_modifier
.staticrounding
)
5093 || (i
.rounding
->type
== saeonly
5094 && (t
->opcode_modifier
.staticrounding
5095 || !t
->opcode_modifier
.sae
)))
5097 i
.error
= unsupported_rc_sae
;
5100 /* If the instruction has several immediate operands and one of
5101 them is rounding, the rounding operand should be the last
5102 immediate operand. */
5103 if (i
.imm_operands
> 1
5104 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5106 i
.error
= rc_sae_operand_not_last_imm
;
5111 /* Check vector Disp8 operand. */
5112 if (t
->opcode_modifier
.disp8memshift
5113 && i
.disp_encoding
!= disp_encoding_32bit
)
5116 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
5118 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5120 for (op
= 0; op
< i
.operands
; op
++)
5121 if (operand_type_check (i
.types
[op
], disp
)
5122 && i
.op
[op
].disps
->X_op
== O_constant
)
5124 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5126 i
.types
[op
].bitfield
.disp8
= 1;
5129 i
.types
[op
].bitfield
.disp8
= 0;
5138 /* Check if operands are valid for the instruction. Update VEX
5142 VEX_check_operands (const insn_template
*t
)
5144 if (i
.vec_encoding
== vex_encoding_evex
)
5146 /* This instruction must be encoded with EVEX prefix. */
5147 if (!t
->opcode_modifier
.evex
)
5149 i
.error
= unsupported
;
5155 if (!t
->opcode_modifier
.vex
)
5157 /* This instruction template doesn't have VEX prefix. */
5158 if (i
.vec_encoding
!= vex_encoding_default
)
5160 i
.error
= unsupported
;
5166 /* Only check VEX_Imm4, which must be the first operand. */
5167 if (t
->operand_types
[0].bitfield
.vec_imm4
)
5169 if (i
.op
[0].imms
->X_op
!= O_constant
5170 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5176 /* Turn off Imm8 so that update_imm won't complain. */
5177 i
.types
[0] = vec_imm4
;
5183 static const insn_template
*
5184 match_template (char mnem_suffix
)
5186 /* Points to template once we've found it. */
5187 const insn_template
*t
;
5188 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5189 i386_operand_type overlap4
;
5190 unsigned int found_reverse_match
;
5191 i386_opcode_modifier suffix_check
, mnemsuf_check
;
5192 i386_operand_type operand_types
[MAX_OPERANDS
];
5193 int addr_prefix_disp
;
5195 unsigned int found_cpu_match
;
5196 unsigned int check_register
;
5197 enum i386_error specific_error
= 0;
5199 #if MAX_OPERANDS != 5
5200 # error "MAX_OPERANDS must be 5."
5203 found_reverse_match
= 0;
5204 addr_prefix_disp
= -1;
5206 memset (&suffix_check
, 0, sizeof (suffix_check
));
5207 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5208 suffix_check
.no_bsuf
= 1;
5209 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5210 suffix_check
.no_wsuf
= 1;
5211 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
5212 suffix_check
.no_ssuf
= 1;
5213 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5214 suffix_check
.no_lsuf
= 1;
5215 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5216 suffix_check
.no_qsuf
= 1;
5217 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5218 suffix_check
.no_ldsuf
= 1;
5220 memset (&mnemsuf_check
, 0, sizeof (mnemsuf_check
));
5223 switch (mnem_suffix
)
5225 case BYTE_MNEM_SUFFIX
: mnemsuf_check
.no_bsuf
= 1; break;
5226 case WORD_MNEM_SUFFIX
: mnemsuf_check
.no_wsuf
= 1; break;
5227 case SHORT_MNEM_SUFFIX
: mnemsuf_check
.no_ssuf
= 1; break;
5228 case LONG_MNEM_SUFFIX
: mnemsuf_check
.no_lsuf
= 1; break;
5229 case QWORD_MNEM_SUFFIX
: mnemsuf_check
.no_qsuf
= 1; break;
5233 /* Must have right number of operands. */
5234 i
.error
= number_of_operands_mismatch
;
5236 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5238 addr_prefix_disp
= -1;
5240 if (i
.operands
!= t
->operands
)
5243 /* Check processor support. */
5244 i
.error
= unsupported
;
5245 found_cpu_match
= (cpu_flags_match (t
)
5246 == CPU_FLAGS_PERFECT_MATCH
);
5247 if (!found_cpu_match
)
5250 /* Check old gcc support. */
5251 i
.error
= old_gcc_only
;
5252 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
5255 /* Check AT&T mnemonic. */
5256 i
.error
= unsupported_with_intel_mnemonic
;
5257 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5260 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5261 i
.error
= unsupported_syntax
;
5262 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5263 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5264 || (intel64
&& t
->opcode_modifier
.amd64
)
5265 || (!intel64
&& t
->opcode_modifier
.intel64
))
5268 /* Check the suffix, except for some instructions in intel mode. */
5269 i
.error
= invalid_instruction_suffix
;
5270 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
5271 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5272 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5273 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5274 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5275 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5276 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
5278 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5279 if ((t
->opcode_modifier
.no_bsuf
&& mnemsuf_check
.no_bsuf
)
5280 || (t
->opcode_modifier
.no_wsuf
&& mnemsuf_check
.no_wsuf
)
5281 || (t
->opcode_modifier
.no_lsuf
&& mnemsuf_check
.no_lsuf
)
5282 || (t
->opcode_modifier
.no_ssuf
&& mnemsuf_check
.no_ssuf
)
5283 || (t
->opcode_modifier
.no_qsuf
&& mnemsuf_check
.no_qsuf
)
5284 || (t
->opcode_modifier
.no_ldsuf
&& mnemsuf_check
.no_ldsuf
))
5287 if (!operand_size_match (t
))
5290 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5291 operand_types
[j
] = t
->operand_types
[j
];
5293 /* In general, don't allow 64-bit operands in 32-bit mode. */
5294 if (i
.suffix
== QWORD_MNEM_SUFFIX
5295 && flag_code
!= CODE_64BIT
5297 ? (!t
->opcode_modifier
.ignoresize
5298 && !intel_float_operand (t
->name
))
5299 : intel_float_operand (t
->name
) != 2)
5300 && ((!operand_types
[0].bitfield
.regmmx
5301 && !operand_types
[0].bitfield
.regsimd
)
5302 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5303 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
))
5304 && (t
->base_opcode
!= 0x0fc7
5305 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5308 /* In general, don't allow 32-bit operands on pre-386. */
5309 else if (i
.suffix
== LONG_MNEM_SUFFIX
5310 && !cpu_arch_flags
.bitfield
.cpui386
5312 ? (!t
->opcode_modifier
.ignoresize
5313 && !intel_float_operand (t
->name
))
5314 : intel_float_operand (t
->name
) != 2)
5315 && ((!operand_types
[0].bitfield
.regmmx
5316 && !operand_types
[0].bitfield
.regsimd
)
5317 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
5318 && !operand_types
[t
->operands
> 1].bitfield
.regsimd
)))
5321 /* Do not verify operands when there are none. */
5325 /* We've found a match; break out of loop. */
5329 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5330 into Disp32/Disp16/Disp32 operand. */
5331 if (i
.prefix
[ADDR_PREFIX
] != 0)
5333 /* There should be only one Disp operand. */
5337 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5339 if (operand_types
[j
].bitfield
.disp16
)
5341 addr_prefix_disp
= j
;
5342 operand_types
[j
].bitfield
.disp32
= 1;
5343 operand_types
[j
].bitfield
.disp16
= 0;
5349 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5351 if (operand_types
[j
].bitfield
.disp32
)
5353 addr_prefix_disp
= j
;
5354 operand_types
[j
].bitfield
.disp32
= 0;
5355 operand_types
[j
].bitfield
.disp16
= 1;
5361 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5363 if (operand_types
[j
].bitfield
.disp64
)
5365 addr_prefix_disp
= j
;
5366 operand_types
[j
].bitfield
.disp64
= 0;
5367 operand_types
[j
].bitfield
.disp32
= 1;
5375 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5376 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5379 /* We check register size if needed. */
5380 check_register
= t
->opcode_modifier
.checkregsize
;
5381 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5382 switch (t
->operands
)
5385 if (!operand_type_match (overlap0
, i
.types
[0]))
5389 /* xchg %eax, %eax is a special case. It is an alias for nop
5390 only in 32bit mode and we can use opcode 0x90. In 64bit
5391 mode, we can't use 0x90 for xchg %eax, %eax since it should
5392 zero-extend %eax to %rax. */
5393 if (flag_code
== CODE_64BIT
5394 && t
->base_opcode
== 0x90
5395 && operand_type_equal (&i
.types
[0], &acc32
)
5396 && operand_type_equal (&i
.types
[1], &acc32
))
5398 /* If we want store form, we reverse direction of operands. */
5399 if (i
.dir_encoding
== dir_encoding_store
5400 && t
->opcode_modifier
.d
)
5405 /* If we want store form, we skip the current load. */
5406 if (i
.dir_encoding
== dir_encoding_store
5407 && i
.mem_operands
== 0
5408 && t
->opcode_modifier
.load
)
5413 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
5414 if (!operand_type_match (overlap0
, i
.types
[0])
5415 || !operand_type_match (overlap1
, i
.types
[1])
5417 && !operand_type_register_match (i
.types
[0],
5422 /* Check if other direction is valid ... */
5423 if (!t
->opcode_modifier
.d
)
5427 /* Try reversing direction of operands. */
5428 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
5429 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
5430 if (!operand_type_match (overlap0
, i
.types
[0])
5431 || !operand_type_match (overlap1
, i
.types
[1])
5433 && !operand_type_register_match (i
.types
[0],
5438 /* Does not match either direction. */
5441 /* found_reverse_match holds which of D or FloatR
5443 if (!t
->opcode_modifier
.d
)
5444 found_reverse_match
= 0;
5445 else if (operand_types
[0].bitfield
.tbyte
)
5446 found_reverse_match
= Opcode_FloatD
;
5448 found_reverse_match
= Opcode_D
;
5449 if (t
->opcode_modifier
.floatr
)
5450 found_reverse_match
|= Opcode_FloatR
;
5454 /* Found a forward 2 operand match here. */
5455 switch (t
->operands
)
5458 overlap4
= operand_type_and (i
.types
[4],
5462 overlap3
= operand_type_and (i
.types
[3],
5466 overlap2
= operand_type_and (i
.types
[2],
5471 switch (t
->operands
)
5474 if (!operand_type_match (overlap4
, i
.types
[4])
5475 || !operand_type_register_match (i
.types
[3],
5482 if (!operand_type_match (overlap3
, i
.types
[3])
5484 && !operand_type_register_match (i
.types
[2],
5491 /* Here we make use of the fact that there are no
5492 reverse match 3 operand instructions. */
5493 if (!operand_type_match (overlap2
, i
.types
[2])
5495 && (!operand_type_register_match (i
.types
[0],
5499 || !operand_type_register_match (i
.types
[1],
5502 operand_types
[2]))))
5507 /* Found either forward/reverse 2, 3 or 4 operand match here:
5508 slip through to break. */
5510 if (!found_cpu_match
)
5512 found_reverse_match
= 0;
5516 /* Check if vector and VEX operands are valid. */
5517 if (check_VecOperands (t
) || VEX_check_operands (t
))
5519 specific_error
= i
.error
;
5523 /* We've found a match; break out of loop. */
5527 if (t
== current_templates
->end
)
5529 /* We found no match. */
5530 const char *err_msg
;
5531 switch (specific_error
? specific_error
: i
.error
)
5535 case operand_size_mismatch
:
5536 err_msg
= _("operand size mismatch");
5538 case operand_type_mismatch
:
5539 err_msg
= _("operand type mismatch");
5541 case register_type_mismatch
:
5542 err_msg
= _("register type mismatch");
5544 case number_of_operands_mismatch
:
5545 err_msg
= _("number of operands mismatch");
5547 case invalid_instruction_suffix
:
5548 err_msg
= _("invalid instruction suffix");
5551 err_msg
= _("constant doesn't fit in 4 bits");
5554 err_msg
= _("only supported with old gcc");
5556 case unsupported_with_intel_mnemonic
:
5557 err_msg
= _("unsupported with Intel mnemonic");
5559 case unsupported_syntax
:
5560 err_msg
= _("unsupported syntax");
5563 as_bad (_("unsupported instruction `%s'"),
5564 current_templates
->start
->name
);
5566 case invalid_vsib_address
:
5567 err_msg
= _("invalid VSIB address");
5569 case invalid_vector_register_set
:
5570 err_msg
= _("mask, index, and destination registers must be distinct");
5572 case unsupported_vector_index_register
:
5573 err_msg
= _("unsupported vector index register");
5575 case unsupported_broadcast
:
5576 err_msg
= _("unsupported broadcast");
5578 case broadcast_not_on_src_operand
:
5579 err_msg
= _("broadcast not on source memory operand");
5581 case broadcast_needed
:
5582 err_msg
= _("broadcast is needed for operand of such type");
5584 case unsupported_masking
:
5585 err_msg
= _("unsupported masking");
5587 case mask_not_on_destination
:
5588 err_msg
= _("mask not on destination operand");
5590 case no_default_mask
:
5591 err_msg
= _("default mask isn't allowed");
5593 case unsupported_rc_sae
:
5594 err_msg
= _("unsupported static rounding/sae");
5596 case rc_sae_operand_not_last_imm
:
5598 err_msg
= _("RC/SAE operand must precede immediate operands");
5600 err_msg
= _("RC/SAE operand must follow immediate operands");
5602 case invalid_register_operand
:
5603 err_msg
= _("invalid register operand");
5606 as_bad (_("%s for `%s'"), err_msg
,
5607 current_templates
->start
->name
);
5611 if (!quiet_warnings
)
5614 && (i
.types
[0].bitfield
.jumpabsolute
5615 != operand_types
[0].bitfield
.jumpabsolute
))
5617 as_warn (_("indirect %s without `*'"), t
->name
);
5620 if (t
->opcode_modifier
.isprefix
5621 && t
->opcode_modifier
.ignoresize
)
5623 /* Warn them that a data or address size prefix doesn't
5624 affect assembly of the next line of code. */
5625 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5629 /* Copy the template we found. */
5632 if (addr_prefix_disp
!= -1)
5633 i
.tm
.operand_types
[addr_prefix_disp
]
5634 = operand_types
[addr_prefix_disp
];
5636 if (found_reverse_match
)
5638 /* If we found a reverse match we must alter the opcode
5639 direction bit. found_reverse_match holds bits to change
5640 (different for int & float insns). */
5642 i
.tm
.base_opcode
^= found_reverse_match
;
5644 i
.tm
.operand_types
[0] = operand_types
[1];
5645 i
.tm
.operand_types
[1] = operand_types
[0];
5654 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5655 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5657 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5659 as_bad (_("`%s' operand %d must use `%ses' segment"),
5665 /* There's only ever one segment override allowed per instruction.
5666 This instruction possibly has a legal segment override on the
5667 second operand, so copy the segment to where non-string
5668 instructions store it, allowing common code. */
5669 i
.seg
[0] = i
.seg
[1];
5671 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5673 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5675 as_bad (_("`%s' operand %d must use `%ses' segment"),
5686 process_suffix (void)
5688 /* If matched instruction specifies an explicit instruction mnemonic
5690 if (i
.tm
.opcode_modifier
.size16
)
5691 i
.suffix
= WORD_MNEM_SUFFIX
;
5692 else if (i
.tm
.opcode_modifier
.size32
)
5693 i
.suffix
= LONG_MNEM_SUFFIX
;
5694 else if (i
.tm
.opcode_modifier
.size64
)
5695 i
.suffix
= QWORD_MNEM_SUFFIX
;
5696 else if (i
.reg_operands
)
5698 /* If there's no instruction mnemonic suffix we try to invent one
5699 based on register operands. */
5702 /* We take i.suffix from the last register operand specified,
5703 Destination register type is more significant than source
5704 register type. crc32 in SSE4.2 prefers source register
5706 if (i
.tm
.base_opcode
== 0xf20f38f1)
5708 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.word
)
5709 i
.suffix
= WORD_MNEM_SUFFIX
;
5710 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.dword
)
5711 i
.suffix
= LONG_MNEM_SUFFIX
;
5712 else if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.qword
)
5713 i
.suffix
= QWORD_MNEM_SUFFIX
;
5715 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5717 if (i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.byte
)
5718 i
.suffix
= BYTE_MNEM_SUFFIX
;
5725 if (i
.tm
.base_opcode
== 0xf20f38f1
5726 || i
.tm
.base_opcode
== 0xf20f38f0)
5728 /* We have to know the operand size for crc32. */
5729 as_bad (_("ambiguous memory operand size for `%s`"),
5734 for (op
= i
.operands
; --op
>= 0;)
5735 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
5736 && !i
.tm
.operand_types
[op
].bitfield
.shiftcount
)
5738 if (!i
.types
[op
].bitfield
.reg
)
5740 if (i
.types
[op
].bitfield
.byte
)
5741 i
.suffix
= BYTE_MNEM_SUFFIX
;
5742 else if (i
.types
[op
].bitfield
.word
)
5743 i
.suffix
= WORD_MNEM_SUFFIX
;
5744 else if (i
.types
[op
].bitfield
.dword
)
5745 i
.suffix
= LONG_MNEM_SUFFIX
;
5746 else if (i
.types
[op
].bitfield
.qword
)
5747 i
.suffix
= QWORD_MNEM_SUFFIX
;
5754 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5757 && i
.tm
.opcode_modifier
.ignoresize
5758 && i
.tm
.opcode_modifier
.no_bsuf
)
5760 else if (!check_byte_reg ())
5763 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5766 && i
.tm
.opcode_modifier
.ignoresize
5767 && i
.tm
.opcode_modifier
.no_lsuf
)
5769 else if (!check_long_reg ())
5772 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5775 && i
.tm
.opcode_modifier
.ignoresize
5776 && i
.tm
.opcode_modifier
.no_qsuf
)
5778 else if (!check_qword_reg ())
5781 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5784 && i
.tm
.opcode_modifier
.ignoresize
5785 && i
.tm
.opcode_modifier
.no_wsuf
)
5787 else if (!check_word_reg ())
5790 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5791 /* Do nothing if the instruction is going to ignore the prefix. */
5796 else if (i
.tm
.opcode_modifier
.defaultsize
5798 /* exclude fldenv/frstor/fsave/fstenv */
5799 && i
.tm
.opcode_modifier
.no_ssuf
)
5801 i
.suffix
= stackop_size
;
5803 else if (intel_syntax
5805 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5806 || i
.tm
.opcode_modifier
.jumpbyte
5807 || i
.tm
.opcode_modifier
.jumpintersegment
5808 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5809 && i
.tm
.extension_opcode
<= 3)))
5814 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5816 i
.suffix
= QWORD_MNEM_SUFFIX
;
5821 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5822 i
.suffix
= LONG_MNEM_SUFFIX
;
5825 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5826 i
.suffix
= WORD_MNEM_SUFFIX
;
5835 if (i
.tm
.opcode_modifier
.w
)
5837 as_bad (_("no instruction mnemonic suffix given and "
5838 "no register operands; can't size instruction"));
5844 unsigned int suffixes
;
5846 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5847 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5849 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5851 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5853 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5855 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
5858 /* There are more than suffix matches. */
5859 if (i
.tm
.opcode_modifier
.w
5860 || ((suffixes
& (suffixes
- 1))
5861 && !i
.tm
.opcode_modifier
.defaultsize
5862 && !i
.tm
.opcode_modifier
.ignoresize
))
5864 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5870 /* Change the opcode based on the operand size given by i.suffix. */
5873 /* Size floating point instruction. */
5874 case LONG_MNEM_SUFFIX
:
5875 if (i
.tm
.opcode_modifier
.floatmf
)
5877 i
.tm
.base_opcode
^= 4;
5881 case WORD_MNEM_SUFFIX
:
5882 case QWORD_MNEM_SUFFIX
:
5883 /* It's not a byte, select word/dword operation. */
5884 if (i
.tm
.opcode_modifier
.w
)
5886 if (i
.tm
.opcode_modifier
.shortform
)
5887 i
.tm
.base_opcode
|= 8;
5889 i
.tm
.base_opcode
|= 1;
5892 case SHORT_MNEM_SUFFIX
:
5893 /* Now select between word & dword operations via the operand
5894 size prefix, except for instructions that will ignore this
5896 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5898 /* The address size override prefix changes the size of the
5900 if ((flag_code
== CODE_32BIT
5901 && i
.op
->regs
[0].reg_type
.bitfield
.word
)
5902 || (flag_code
!= CODE_32BIT
5903 && i
.op
->regs
[0].reg_type
.bitfield
.dword
))
5904 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5907 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5908 && !i
.tm
.opcode_modifier
.ignoresize
5909 && !i
.tm
.opcode_modifier
.floatmf
5910 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5911 || (flag_code
== CODE_64BIT
5912 && i
.tm
.opcode_modifier
.jumpbyte
)))
5914 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5916 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5917 prefix
= ADDR_PREFIX_OPCODE
;
5919 if (!add_prefix (prefix
))
5923 /* Set mode64 for an operand. */
5924 if (i
.suffix
== QWORD_MNEM_SUFFIX
5925 && flag_code
== CODE_64BIT
5926 && !i
.tm
.opcode_modifier
.norex64
5927 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5929 && ! (i
.operands
== 2
5930 && i
.tm
.base_opcode
== 0x90
5931 && i
.tm
.extension_opcode
== None
5932 && operand_type_equal (&i
.types
[0], &acc64
)
5933 && operand_type_equal (&i
.types
[1], &acc64
)))
5943 check_byte_reg (void)
5947 for (op
= i
.operands
; --op
>= 0;)
5949 /* Skip non-register operands. */
5950 if (!i
.types
[op
].bitfield
.reg
)
5953 /* If this is an eight bit register, it's OK. If it's the 16 or
5954 32 bit version of an eight bit register, we will just use the
5955 low portion, and that's OK too. */
5956 if (i
.types
[op
].bitfield
.byte
)
5959 /* I/O port address operands are OK too. */
5960 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5963 /* crc32 doesn't generate this warning. */
5964 if (i
.tm
.base_opcode
== 0xf20f38f0)
5967 if ((i
.types
[op
].bitfield
.word
5968 || i
.types
[op
].bitfield
.dword
5969 || i
.types
[op
].bitfield
.qword
)
5970 && i
.op
[op
].regs
->reg_num
< 4
5971 /* Prohibit these changes in 64bit mode, since the lowering
5972 would be more complicated. */
5973 && flag_code
!= CODE_64BIT
)
5975 #if REGISTER_WARNINGS
5976 if (!quiet_warnings
)
5977 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5979 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
5980 ? REGNAM_AL
- REGNAM_AX
5981 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5983 i
.op
[op
].regs
->reg_name
,
5988 /* Any other register is bad. */
5989 if (i
.types
[op
].bitfield
.reg
5990 || i
.types
[op
].bitfield
.regmmx
5991 || i
.types
[op
].bitfield
.regsimd
5992 || i
.types
[op
].bitfield
.sreg2
5993 || i
.types
[op
].bitfield
.sreg3
5994 || i
.types
[op
].bitfield
.control
5995 || i
.types
[op
].bitfield
.debug
5996 || i
.types
[op
].bitfield
.test
)
5998 as_bad (_("`%s%s' not allowed with `%s%c'"),
6000 i
.op
[op
].regs
->reg_name
,
6010 check_long_reg (void)
6014 for (op
= i
.operands
; --op
>= 0;)
6015 /* Skip non-register operands. */
6016 if (!i
.types
[op
].bitfield
.reg
)
6018 /* Reject eight bit registers, except where the template requires
6019 them. (eg. movzb) */
6020 else if (i
.types
[op
].bitfield
.byte
6021 && (i
.tm
.operand_types
[op
].bitfield
.reg
6022 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6023 && (i
.tm
.operand_types
[op
].bitfield
.word
6024 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6026 as_bad (_("`%s%s' not allowed with `%s%c'"),
6028 i
.op
[op
].regs
->reg_name
,
6033 /* Warn if the e prefix on a general reg is missing. */
6034 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6035 && i
.types
[op
].bitfield
.word
6036 && (i
.tm
.operand_types
[op
].bitfield
.reg
6037 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6038 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6040 /* Prohibit these changes in the 64bit mode, since the
6041 lowering is more complicated. */
6042 if (flag_code
== CODE_64BIT
)
6044 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6045 register_prefix
, i
.op
[op
].regs
->reg_name
,
6049 #if REGISTER_WARNINGS
6050 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6052 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6053 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6056 /* Warn if the r prefix on a general reg is present. */
6057 else if (i
.types
[op
].bitfield
.qword
6058 && (i
.tm
.operand_types
[op
].bitfield
.reg
6059 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6060 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6063 && i
.tm
.opcode_modifier
.toqword
6064 && !i
.types
[0].bitfield
.regsimd
)
6066 /* Convert to QWORD. We want REX byte. */
6067 i
.suffix
= QWORD_MNEM_SUFFIX
;
6071 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6072 register_prefix
, i
.op
[op
].regs
->reg_name
,
6081 check_qword_reg (void)
6085 for (op
= i
.operands
; --op
>= 0; )
6086 /* Skip non-register operands. */
6087 if (!i
.types
[op
].bitfield
.reg
)
6089 /* Reject eight bit registers, except where the template requires
6090 them. (eg. movzb) */
6091 else if (i
.types
[op
].bitfield
.byte
6092 && (i
.tm
.operand_types
[op
].bitfield
.reg
6093 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6094 && (i
.tm
.operand_types
[op
].bitfield
.word
6095 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6097 as_bad (_("`%s%s' not allowed with `%s%c'"),
6099 i
.op
[op
].regs
->reg_name
,
6104 /* Warn if the r prefix on a general reg is missing. */
6105 else if ((i
.types
[op
].bitfield
.word
6106 || i
.types
[op
].bitfield
.dword
)
6107 && (i
.tm
.operand_types
[op
].bitfield
.reg
6108 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6109 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6111 /* Prohibit these changes in the 64bit mode, since the
6112 lowering is more complicated. */
6114 && i
.tm
.opcode_modifier
.todword
6115 && !i
.types
[0].bitfield
.regsimd
)
6117 /* Convert to DWORD. We don't want REX byte. */
6118 i
.suffix
= LONG_MNEM_SUFFIX
;
6122 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6123 register_prefix
, i
.op
[op
].regs
->reg_name
,
6132 check_word_reg (void)
6135 for (op
= i
.operands
; --op
>= 0;)
6136 /* Skip non-register operands. */
6137 if (!i
.types
[op
].bitfield
.reg
)
6139 /* Reject eight bit registers, except where the template requires
6140 them. (eg. movzb) */
6141 else if (i
.types
[op
].bitfield
.byte
6142 && (i
.tm
.operand_types
[op
].bitfield
.reg
6143 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6144 && (i
.tm
.operand_types
[op
].bitfield
.word
6145 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6147 as_bad (_("`%s%s' not allowed with `%s%c'"),
6149 i
.op
[op
].regs
->reg_name
,
6154 /* Warn if the e or r prefix on a general reg is present. */
6155 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6156 && (i
.types
[op
].bitfield
.dword
6157 || i
.types
[op
].bitfield
.qword
)
6158 && (i
.tm
.operand_types
[op
].bitfield
.reg
6159 || i
.tm
.operand_types
[op
].bitfield
.acc
)
6160 && i
.tm
.operand_types
[op
].bitfield
.word
)
6162 /* Prohibit these changes in the 64bit mode, since the
6163 lowering is more complicated. */
6164 if (flag_code
== CODE_64BIT
)
6166 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6167 register_prefix
, i
.op
[op
].regs
->reg_name
,
6171 #if REGISTER_WARNINGS
6172 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6174 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6175 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6182 update_imm (unsigned int j
)
6184 i386_operand_type overlap
= i
.types
[j
];
6185 if ((overlap
.bitfield
.imm8
6186 || overlap
.bitfield
.imm8s
6187 || overlap
.bitfield
.imm16
6188 || overlap
.bitfield
.imm32
6189 || overlap
.bitfield
.imm32s
6190 || overlap
.bitfield
.imm64
)
6191 && !operand_type_equal (&overlap
, &imm8
)
6192 && !operand_type_equal (&overlap
, &imm8s
)
6193 && !operand_type_equal (&overlap
, &imm16
)
6194 && !operand_type_equal (&overlap
, &imm32
)
6195 && !operand_type_equal (&overlap
, &imm32s
)
6196 && !operand_type_equal (&overlap
, &imm64
))
6200 i386_operand_type temp
;
6202 operand_type_set (&temp
, 0);
6203 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6205 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6206 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6208 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6209 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6210 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6212 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6213 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6216 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6219 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6220 || operand_type_equal (&overlap
, &imm16_32
)
6221 || operand_type_equal (&overlap
, &imm16_32s
))
6223 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6228 if (!operand_type_equal (&overlap
, &imm8
)
6229 && !operand_type_equal (&overlap
, &imm8s
)
6230 && !operand_type_equal (&overlap
, &imm16
)
6231 && !operand_type_equal (&overlap
, &imm32
)
6232 && !operand_type_equal (&overlap
, &imm32s
)
6233 && !operand_type_equal (&overlap
, &imm64
))
6235 as_bad (_("no instruction mnemonic suffix given; "
6236 "can't determine immediate size"));
6240 i
.types
[j
] = overlap
;
6250 /* Update the first 2 immediate operands. */
6251 n
= i
.operands
> 2 ? 2 : i
.operands
;
6254 for (j
= 0; j
< n
; j
++)
6255 if (update_imm (j
) == 0)
6258 /* The 3rd operand can't be immediate operand. */
6259 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6266 process_operands (void)
6268 /* Default segment register this instruction will use for memory
6269 accesses. 0 means unknown. This is only for optimizing out
6270 unnecessary segment overrides. */
6271 const seg_entry
*default_seg
= 0;
6273 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6275 unsigned int dupl
= i
.operands
;
6276 unsigned int dest
= dupl
- 1;
6279 /* The destination must be an xmm register. */
6280 gas_assert (i
.reg_operands
6281 && MAX_OPERANDS
> dupl
6282 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6284 if (i
.tm
.operand_types
[0].bitfield
.acc
6285 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6287 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6289 /* Keep xmm0 for instructions with VEX prefix and 3
6291 i
.tm
.operand_types
[0].bitfield
.acc
= 0;
6292 i
.tm
.operand_types
[0].bitfield
.regsimd
= 1;
6297 /* We remove the first xmm0 and keep the number of
6298 operands unchanged, which in fact duplicates the
6300 for (j
= 1; j
< i
.operands
; j
++)
6302 i
.op
[j
- 1] = i
.op
[j
];
6303 i
.types
[j
- 1] = i
.types
[j
];
6304 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6308 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6310 gas_assert ((MAX_OPERANDS
- 1) > dupl
6311 && (i
.tm
.opcode_modifier
.vexsources
6314 /* Add the implicit xmm0 for instructions with VEX prefix
6316 for (j
= i
.operands
; j
> 0; j
--)
6318 i
.op
[j
] = i
.op
[j
- 1];
6319 i
.types
[j
] = i
.types
[j
- 1];
6320 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6323 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6324 i
.types
[0] = regxmm
;
6325 i
.tm
.operand_types
[0] = regxmm
;
6328 i
.reg_operands
+= 2;
6333 i
.op
[dupl
] = i
.op
[dest
];
6334 i
.types
[dupl
] = i
.types
[dest
];
6335 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6344 i
.op
[dupl
] = i
.op
[dest
];
6345 i
.types
[dupl
] = i
.types
[dest
];
6346 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
6349 if (i
.tm
.opcode_modifier
.immext
)
6352 else if (i
.tm
.operand_types
[0].bitfield
.acc
6353 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6357 for (j
= 1; j
< i
.operands
; j
++)
6359 i
.op
[j
- 1] = i
.op
[j
];
6360 i
.types
[j
- 1] = i
.types
[j
];
6362 /* We need to adjust fields in i.tm since they are used by
6363 build_modrm_byte. */
6364 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6371 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
6373 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
6375 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6376 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.regsimd
);
6377 regnum
= register_number (i
.op
[1].regs
);
6378 first_reg_in_group
= regnum
& ~3;
6379 last_reg_in_group
= first_reg_in_group
+ 3;
6380 if (regnum
!= first_reg_in_group
)
6381 as_warn (_("source register `%s%s' implicitly denotes"
6382 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6383 register_prefix
, i
.op
[1].regs
->reg_name
,
6384 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
6385 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
6388 else if (i
.tm
.opcode_modifier
.regkludge
)
6390 /* The imul $imm, %reg instruction is converted into
6391 imul $imm, %reg, %reg, and the clr %reg instruction
6392 is converted into xor %reg, %reg. */
6394 unsigned int first_reg_op
;
6396 if (operand_type_check (i
.types
[0], reg
))
6400 /* Pretend we saw the extra register operand. */
6401 gas_assert (i
.reg_operands
== 1
6402 && i
.op
[first_reg_op
+ 1].regs
== 0);
6403 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
6404 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
6409 if (i
.tm
.opcode_modifier
.shortform
)
6411 if (i
.types
[0].bitfield
.sreg2
6412 || i
.types
[0].bitfield
.sreg3
)
6414 if (i
.tm
.base_opcode
== POP_SEG_SHORT
6415 && i
.op
[0].regs
->reg_num
== 1)
6417 as_bad (_("you can't `pop %scs'"), register_prefix
);
6420 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
6421 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
6426 /* The register or float register operand is in operand
6430 if ((i
.types
[0].bitfield
.reg
&& i
.types
[0].bitfield
.tbyte
)
6431 || operand_type_check (i
.types
[0], reg
))
6435 /* Register goes in low 3 bits of opcode. */
6436 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
6437 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6439 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
6441 /* Warn about some common errors, but press on regardless.
6442 The first case can be generated by gcc (<= 2.8.1). */
6443 if (i
.operands
== 2)
6445 /* Reversed arguments on faddp, fsubp, etc. */
6446 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
6447 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
6448 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
6452 /* Extraneous `l' suffix on fp insn. */
6453 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
6454 register_prefix
, i
.op
[0].regs
->reg_name
);
6459 else if (i
.tm
.opcode_modifier
.modrm
)
6461 /* The opcode is completed (modulo i.tm.extension_opcode which
6462 must be put into the modrm byte). Now, we make the modrm and
6463 index base bytes based on all the info we've collected. */
6465 default_seg
= build_modrm_byte ();
6467 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
6471 else if (i
.tm
.opcode_modifier
.isstring
)
6473 /* For the string instructions that allow a segment override
6474 on one of their operands, the default segment is ds. */
6478 if (i
.tm
.base_opcode
== 0x8d /* lea */
6481 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
6483 /* If a segment was explicitly specified, and the specified segment
6484 is not the default, use an opcode prefix to select it. If we
6485 never figured out what the default segment is, then default_seg
6486 will be zero at this point, and the specified segment prefix will
6488 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6490 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6496 static const seg_entry
*
6497 build_modrm_byte (void)
6499 const seg_entry
*default_seg
= 0;
6500 unsigned int source
, dest
;
6503 /* The first operand of instructions with VEX prefix and 3 sources
6504 must be VEX_Imm4. */
6505 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6508 unsigned int nds
, reg_slot
;
6511 if (i
.tm
.opcode_modifier
.veximmext
6512 && i
.tm
.opcode_modifier
.immext
)
6514 dest
= i
.operands
- 2;
6515 gas_assert (dest
== 3);
6518 dest
= i
.operands
- 1;
6521 /* There are 2 kinds of instructions:
6522 1. 5 operands: 4 register operands or 3 register operands
6523 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6524 VexW0 or VexW1. The destination must be either XMM, YMM or
6526 2. 4 operands: 4 register operands or 3 register operands
6527 plus 1 memory operand, VexXDS, and VexImmExt */
6528 gas_assert ((i
.reg_operands
== 4
6529 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6530 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6531 && (i
.tm
.opcode_modifier
.veximmext
6532 || (i
.imm_operands
== 1
6533 && i
.types
[0].bitfield
.vec_imm4
6534 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6535 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6536 && i
.tm
.operand_types
[dest
].bitfield
.regsimd
)));
6538 if (i
.imm_operands
== 0)
6540 /* When there is no immediate operand, generate an 8bit
6541 immediate operand to encode the first operand. */
6542 exp
= &im_expressions
[i
.imm_operands
++];
6543 i
.op
[i
.operands
].imms
= exp
;
6544 i
.types
[i
.operands
] = imm8
;
6546 /* If VexW1 is set, the first operand is the source and
6547 the second operand is encoded in the immediate operand. */
6548 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6559 /* FMA swaps REG and NDS. */
6560 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6568 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6569 exp
->X_op
= O_constant
;
6570 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6571 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6575 unsigned int imm_slot
;
6577 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6579 /* If VexW0 is set, the third operand is the source and
6580 the second operand is encoded in the immediate
6587 /* VexW1 is set, the second operand is the source and
6588 the third operand is encoded in the immediate
6594 if (i
.tm
.opcode_modifier
.immext
)
6596 /* When ImmExt is set, the immediate byte is the last
6598 imm_slot
= i
.operands
- 1;
6606 /* Turn on Imm8 so that output_imm will generate it. */
6607 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6610 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.regsimd
);
6611 i
.op
[imm_slot
].imms
->X_add_number
6612 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6613 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6616 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.regsimd
);
6617 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6622 /* i.reg_operands MUST be the number of real register operands;
6623 implicit registers do not count. If there are 3 register
6624 operands, it must be a instruction with VexNDS. For a
6625 instruction with VexNDD, the destination register is encoded
6626 in VEX prefix. If there are 4 register operands, it must be
6627 a instruction with VEX prefix and 3 sources. */
6628 if (i
.mem_operands
== 0
6629 && ((i
.reg_operands
== 2
6630 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6631 || (i
.reg_operands
== 3
6632 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6633 || (i
.reg_operands
== 4 && vex_3_sources
)))
6641 /* When there are 3 operands, one of them may be immediate,
6642 which may be the first or the last operand. Otherwise,
6643 the first operand must be shift count register (cl) or it
6644 is an instruction with VexNDS. */
6645 gas_assert (i
.imm_operands
== 1
6646 || (i
.imm_operands
== 0
6647 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6648 || i
.types
[0].bitfield
.shiftcount
)));
6649 if (operand_type_check (i
.types
[0], imm
)
6650 || i
.types
[0].bitfield
.shiftcount
)
6656 /* When there are 4 operands, the first two must be 8bit
6657 immediate operands. The source operand will be the 3rd
6660 For instructions with VexNDS, if the first operand
6661 an imm8, the source operand is the 2nd one. If the last
6662 operand is imm8, the source operand is the first one. */
6663 gas_assert ((i
.imm_operands
== 2
6664 && i
.types
[0].bitfield
.imm8
6665 && i
.types
[1].bitfield
.imm8
)
6666 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6667 && i
.imm_operands
== 1
6668 && (i
.types
[0].bitfield
.imm8
6669 || i
.types
[i
.operands
- 1].bitfield
.imm8
6671 if (i
.imm_operands
== 2)
6675 if (i
.types
[0].bitfield
.imm8
)
6682 if (i
.tm
.opcode_modifier
.evex
)
6684 /* For EVEX instructions, when there are 5 operands, the
6685 first one must be immediate operand. If the second one
6686 is immediate operand, the source operand is the 3th
6687 one. If the last one is immediate operand, the source
6688 operand is the 2nd one. */
6689 gas_assert (i
.imm_operands
== 2
6690 && i
.tm
.opcode_modifier
.sae
6691 && operand_type_check (i
.types
[0], imm
));
6692 if (operand_type_check (i
.types
[1], imm
))
6694 else if (operand_type_check (i
.types
[4], imm
))
6708 /* RC/SAE operand could be between DEST and SRC. That happens
6709 when one operand is GPR and the other one is XMM/YMM/ZMM
6711 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6714 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6716 /* For instructions with VexNDS, the register-only source
6717 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6718 register. It is encoded in VEX prefix. We need to
6719 clear RegMem bit before calling operand_type_equal. */
6721 i386_operand_type op
;
6724 /* Check register-only source operand when two source
6725 operands are swapped. */
6726 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6727 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6735 op
= i
.tm
.operand_types
[vvvv
];
6736 op
.bitfield
.regmem
= 0;
6737 if ((dest
+ 1) >= i
.operands
6738 || ((!op
.bitfield
.reg
6739 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
6740 && !op
.bitfield
.regsimd
6741 && !operand_type_equal (&op
, ®mask
)))
6743 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6749 /* One of the register operands will be encoded in the i.tm.reg
6750 field, the other in the combined i.tm.mode and i.tm.regmem
6751 fields. If no form of this instruction supports a memory
6752 destination operand, then we assume the source operand may
6753 sometimes be a memory operand and so we need to store the
6754 destination in the i.rm.reg field. */
6755 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6756 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6758 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6759 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6760 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6762 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6764 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6766 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6771 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6772 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6773 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6775 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6777 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6779 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6782 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6784 if (!i
.types
[0].bitfield
.control
6785 && !i
.types
[1].bitfield
.control
)
6787 i
.rex
&= ~(REX_R
| REX_B
);
6788 add_prefix (LOCK_PREFIX_OPCODE
);
6792 { /* If it's not 2 reg operands... */
6797 unsigned int fake_zero_displacement
= 0;
6800 for (op
= 0; op
< i
.operands
; op
++)
6801 if (operand_type_check (i
.types
[op
], anymem
))
6803 gas_assert (op
< i
.operands
);
6805 if (i
.tm
.opcode_modifier
.vecsib
)
6807 if (i
.index_reg
->reg_num
== RegEiz
6808 || i
.index_reg
->reg_num
== RegRiz
)
6811 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6814 i
.sib
.base
= NO_BASE_REGISTER
;
6815 i
.sib
.scale
= i
.log2_scale_factor
;
6816 i
.types
[op
].bitfield
.disp8
= 0;
6817 i
.types
[op
].bitfield
.disp16
= 0;
6818 i
.types
[op
].bitfield
.disp64
= 0;
6819 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6821 /* Must be 32 bit */
6822 i
.types
[op
].bitfield
.disp32
= 1;
6823 i
.types
[op
].bitfield
.disp32s
= 0;
6827 i
.types
[op
].bitfield
.disp32
= 0;
6828 i
.types
[op
].bitfield
.disp32s
= 1;
6831 i
.sib
.index
= i
.index_reg
->reg_num
;
6832 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6834 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6840 if (i
.base_reg
== 0)
6843 if (!i
.disp_operands
)
6844 fake_zero_displacement
= 1;
6845 if (i
.index_reg
== 0)
6847 i386_operand_type newdisp
;
6849 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6850 /* Operand is just <disp> */
6851 if (flag_code
== CODE_64BIT
)
6853 /* 64bit mode overwrites the 32bit absolute
6854 addressing by RIP relative addressing and
6855 absolute addressing is encoded by one of the
6856 redundant SIB forms. */
6857 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6858 i
.sib
.base
= NO_BASE_REGISTER
;
6859 i
.sib
.index
= NO_INDEX_REGISTER
;
6860 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
6862 else if ((flag_code
== CODE_16BIT
)
6863 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6865 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6870 i
.rm
.regmem
= NO_BASE_REGISTER
;
6873 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6874 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
6876 else if (!i
.tm
.opcode_modifier
.vecsib
)
6878 /* !i.base_reg && i.index_reg */
6879 if (i
.index_reg
->reg_num
== RegEiz
6880 || i
.index_reg
->reg_num
== RegRiz
)
6881 i
.sib
.index
= NO_INDEX_REGISTER
;
6883 i
.sib
.index
= i
.index_reg
->reg_num
;
6884 i
.sib
.base
= NO_BASE_REGISTER
;
6885 i
.sib
.scale
= i
.log2_scale_factor
;
6886 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6887 i
.types
[op
].bitfield
.disp8
= 0;
6888 i
.types
[op
].bitfield
.disp16
= 0;
6889 i
.types
[op
].bitfield
.disp64
= 0;
6890 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
6892 /* Must be 32 bit */
6893 i
.types
[op
].bitfield
.disp32
= 1;
6894 i
.types
[op
].bitfield
.disp32s
= 0;
6898 i
.types
[op
].bitfield
.disp32
= 0;
6899 i
.types
[op
].bitfield
.disp32s
= 1;
6901 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6905 /* RIP addressing for 64bit mode. */
6906 else if (i
.base_reg
->reg_num
== RegRip
||
6907 i
.base_reg
->reg_num
== RegEip
)
6909 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6910 i
.rm
.regmem
= NO_BASE_REGISTER
;
6911 i
.types
[op
].bitfield
.disp8
= 0;
6912 i
.types
[op
].bitfield
.disp16
= 0;
6913 i
.types
[op
].bitfield
.disp32
= 0;
6914 i
.types
[op
].bitfield
.disp32s
= 1;
6915 i
.types
[op
].bitfield
.disp64
= 0;
6916 i
.flags
[op
] |= Operand_PCrel
;
6917 if (! i
.disp_operands
)
6918 fake_zero_displacement
= 1;
6920 else if (i
.base_reg
->reg_type
.bitfield
.word
)
6922 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6923 switch (i
.base_reg
->reg_num
)
6926 if (i
.index_reg
== 0)
6928 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6929 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6933 if (i
.index_reg
== 0)
6936 if (operand_type_check (i
.types
[op
], disp
) == 0)
6938 /* fake (%bp) into 0(%bp) */
6939 i
.types
[op
].bitfield
.disp8
= 1;
6940 fake_zero_displacement
= 1;
6943 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6944 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6946 default: /* (%si) -> 4 or (%di) -> 5 */
6947 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6949 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6951 else /* i.base_reg and 32/64 bit mode */
6953 if (flag_code
== CODE_64BIT
6954 && operand_type_check (i
.types
[op
], disp
))
6956 i
.types
[op
].bitfield
.disp16
= 0;
6957 i
.types
[op
].bitfield
.disp64
= 0;
6958 if (i
.prefix
[ADDR_PREFIX
] == 0)
6960 i
.types
[op
].bitfield
.disp32
= 0;
6961 i
.types
[op
].bitfield
.disp32s
= 1;
6965 i
.types
[op
].bitfield
.disp32
= 1;
6966 i
.types
[op
].bitfield
.disp32s
= 0;
6970 if (!i
.tm
.opcode_modifier
.vecsib
)
6971 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6972 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6974 i
.sib
.base
= i
.base_reg
->reg_num
;
6975 /* x86-64 ignores REX prefix bit here to avoid decoder
6977 if (!(i
.base_reg
->reg_flags
& RegRex
)
6978 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6979 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6981 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6983 fake_zero_displacement
= 1;
6984 i
.types
[op
].bitfield
.disp8
= 1;
6986 i
.sib
.scale
= i
.log2_scale_factor
;
6987 if (i
.index_reg
== 0)
6989 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6990 /* <disp>(%esp) becomes two byte modrm with no index
6991 register. We've already stored the code for esp
6992 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6993 Any base register besides %esp will not use the
6994 extra modrm byte. */
6995 i
.sib
.index
= NO_INDEX_REGISTER
;
6997 else if (!i
.tm
.opcode_modifier
.vecsib
)
6999 if (i
.index_reg
->reg_num
== RegEiz
7000 || i
.index_reg
->reg_num
== RegRiz
)
7001 i
.sib
.index
= NO_INDEX_REGISTER
;
7003 i
.sib
.index
= i
.index_reg
->reg_num
;
7004 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7005 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7010 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7011 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7015 if (!fake_zero_displacement
7019 fake_zero_displacement
= 1;
7020 if (i
.disp_encoding
== disp_encoding_8bit
)
7021 i
.types
[op
].bitfield
.disp8
= 1;
7023 i
.types
[op
].bitfield
.disp32
= 1;
7025 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7029 if (fake_zero_displacement
)
7031 /* Fakes a zero displacement assuming that i.types[op]
7032 holds the correct displacement size. */
7035 gas_assert (i
.op
[op
].disps
== 0);
7036 exp
= &disp_expressions
[i
.disp_operands
++];
7037 i
.op
[op
].disps
= exp
;
7038 exp
->X_op
= O_constant
;
7039 exp
->X_add_number
= 0;
7040 exp
->X_add_symbol
= (symbolS
*) 0;
7041 exp
->X_op_symbol
= (symbolS
*) 0;
7049 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7051 if (operand_type_check (i
.types
[0], imm
))
7052 i
.vex
.register_specifier
= NULL
;
7055 /* VEX.vvvv encodes one of the sources when the first
7056 operand is not an immediate. */
7057 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7058 i
.vex
.register_specifier
= i
.op
[0].regs
;
7060 i
.vex
.register_specifier
= i
.op
[1].regs
;
7063 /* Destination is a XMM register encoded in the ModRM.reg
7065 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7066 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7069 /* ModRM.rm and VEX.B encodes the other source. */
7070 if (!i
.mem_operands
)
7074 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7075 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7077 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7079 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7083 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7085 i
.vex
.register_specifier
= i
.op
[2].regs
;
7086 if (!i
.mem_operands
)
7089 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7090 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7094 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7095 (if any) based on i.tm.extension_opcode. Again, we must be
7096 careful to make sure that segment/control/debug/test/MMX
7097 registers are coded into the i.rm.reg field. */
7098 else if (i
.reg_operands
)
7101 unsigned int vex_reg
= ~0;
7103 for (op
= 0; op
< i
.operands
; op
++)
7104 if (i
.types
[op
].bitfield
.reg
7105 || i
.types
[op
].bitfield
.regmmx
7106 || i
.types
[op
].bitfield
.regsimd
7107 || i
.types
[op
].bitfield
.regbnd
7108 || i
.types
[op
].bitfield
.regmask
7109 || i
.types
[op
].bitfield
.sreg2
7110 || i
.types
[op
].bitfield
.sreg3
7111 || i
.types
[op
].bitfield
.control
7112 || i
.types
[op
].bitfield
.debug
7113 || i
.types
[op
].bitfield
.test
)
7118 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7120 /* For instructions with VexNDS, the register-only
7121 source operand is encoded in VEX prefix. */
7122 gas_assert (mem
!= (unsigned int) ~0);
7127 gas_assert (op
< i
.operands
);
7131 /* Check register-only source operand when two source
7132 operands are swapped. */
7133 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7134 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7138 gas_assert (mem
== (vex_reg
+ 1)
7139 && op
< i
.operands
);
7144 gas_assert (vex_reg
< i
.operands
);
7148 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7150 /* For instructions with VexNDD, the register destination
7151 is encoded in VEX prefix. */
7152 if (i
.mem_operands
== 0)
7154 /* There is no memory operand. */
7155 gas_assert ((op
+ 2) == i
.operands
);
7160 /* There are only 2 operands. */
7161 gas_assert (op
< 2 && i
.operands
== 2);
7166 gas_assert (op
< i
.operands
);
7168 if (vex_reg
!= (unsigned int) ~0)
7170 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7172 if ((!type
->bitfield
.reg
7173 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7174 && !type
->bitfield
.regsimd
7175 && !operand_type_equal (type
, ®mask
))
7178 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7181 /* Don't set OP operand twice. */
7184 /* If there is an extension opcode to put here, the
7185 register number must be put into the regmem field. */
7186 if (i
.tm
.extension_opcode
!= None
)
7188 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7189 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7191 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7196 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7197 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7199 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7204 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7205 must set it to 3 to indicate this is a register operand
7206 in the regmem field. */
7207 if (!i
.mem_operands
)
7211 /* Fill in i.rm.reg field with extension opcode (if any). */
7212 if (i
.tm
.extension_opcode
!= None
)
7213 i
.rm
.reg
= i
.tm
.extension_opcode
;
7219 output_branch (void)
7225 relax_substateT subtype
;
7229 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7230 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7233 if (i
.prefix
[DATA_PREFIX
] != 0)
7239 /* Pentium4 branch hints. */
7240 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7241 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7246 if (i
.prefix
[REX_PREFIX
] != 0)
7252 /* BND prefixed jump. */
7253 if (i
.prefix
[BND_PREFIX
] != 0)
7255 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7259 if (i
.prefixes
!= 0 && !intel_syntax
)
7260 as_warn (_("skipping prefixes on this instruction"));
7262 /* It's always a symbol; End frag & setup for relax.
7263 Make sure there is enough room in this frag for the largest
7264 instruction we may generate in md_convert_frag. This is 2
7265 bytes for the opcode and room for the prefix and largest
7267 frag_grow (prefix
+ 2 + 4);
7268 /* Prefix and 1 opcode byte go in fr_fix. */
7269 p
= frag_more (prefix
+ 1);
7270 if (i
.prefix
[DATA_PREFIX
] != 0)
7271 *p
++ = DATA_PREFIX_OPCODE
;
7272 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7273 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7274 *p
++ = i
.prefix
[SEG_PREFIX
];
7275 if (i
.prefix
[REX_PREFIX
] != 0)
7276 *p
++ = i
.prefix
[REX_PREFIX
];
7277 *p
= i
.tm
.base_opcode
;
7279 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7280 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7281 else if (cpu_arch_flags
.bitfield
.cpui386
)
7282 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7284 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7287 sym
= i
.op
[0].disps
->X_add_symbol
;
7288 off
= i
.op
[0].disps
->X_add_number
;
7290 if (i
.op
[0].disps
->X_op
!= O_constant
7291 && i
.op
[0].disps
->X_op
!= O_symbol
)
7293 /* Handle complex expressions. */
7294 sym
= make_expr_symbol (i
.op
[0].disps
);
7298 /* 1 possible extra opcode + 4 byte displacement go in var part.
7299 Pass reloc in fr_var. */
7300 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7304 /* Return TRUE iff PLT32 relocation should be used for branching to
7308 need_plt32_p (symbolS
*s
)
7310 /* PLT32 relocation is ELF only. */
7314 /* Since there is no need to prepare for PLT branch on x86-64, we
7315 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7316 be used as a marker for 32-bit PC-relative branches. */
7320 /* Weak or undefined symbol need PLT32 relocation. */
7321 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7324 /* Non-global symbol doesn't need PLT32 relocation. */
7325 if (! S_IS_EXTERNAL (s
))
7328 /* Other global symbols need PLT32 relocation. NB: Symbol with
7329 non-default visibilities are treated as normal global symbol
7330 so that PLT32 relocation can be used as a marker for 32-bit
7331 PC-relative branches. It is useful for linker relaxation. */
7342 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7344 if (i
.tm
.opcode_modifier
.jumpbyte
)
7346 /* This is a loop or jecxz type instruction. */
7348 if (i
.prefix
[ADDR_PREFIX
] != 0)
7350 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
7353 /* Pentium4 branch hints. */
7354 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7355 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7357 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
7366 if (flag_code
== CODE_16BIT
)
7369 if (i
.prefix
[DATA_PREFIX
] != 0)
7371 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
7381 if (i
.prefix
[REX_PREFIX
] != 0)
7383 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
7387 /* BND prefixed jump. */
7388 if (i
.prefix
[BND_PREFIX
] != 0)
7390 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7394 if (i
.prefixes
!= 0 && !intel_syntax
)
7395 as_warn (_("skipping prefixes on this instruction"));
7397 p
= frag_more (i
.tm
.opcode_length
+ size
);
7398 switch (i
.tm
.opcode_length
)
7401 *p
++ = i
.tm
.base_opcode
>> 8;
7404 *p
++ = i
.tm
.base_opcode
;
7410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7412 && jump_reloc
== NO_RELOC
7413 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
7414 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
7417 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
7419 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7420 i
.op
[0].disps
, 1, jump_reloc
);
7422 /* All jumps handled here are signed, but don't use a signed limit
7423 check for 32 and 16 bit jumps as we want to allow wrap around at
7424 4G and 64k respectively. */
7426 fixP
->fx_signed
= 1;
7430 output_interseg_jump (void)
7438 if (flag_code
== CODE_16BIT
)
7442 if (i
.prefix
[DATA_PREFIX
] != 0)
7448 if (i
.prefix
[REX_PREFIX
] != 0)
7458 if (i
.prefixes
!= 0 && !intel_syntax
)
7459 as_warn (_("skipping prefixes on this instruction"));
7461 /* 1 opcode; 2 segment; offset */
7462 p
= frag_more (prefix
+ 1 + 2 + size
);
7464 if (i
.prefix
[DATA_PREFIX
] != 0)
7465 *p
++ = DATA_PREFIX_OPCODE
;
7467 if (i
.prefix
[REX_PREFIX
] != 0)
7468 *p
++ = i
.prefix
[REX_PREFIX
];
7470 *p
++ = i
.tm
.base_opcode
;
7471 if (i
.op
[1].imms
->X_op
== O_constant
)
7473 offsetT n
= i
.op
[1].imms
->X_add_number
;
7476 && !fits_in_unsigned_word (n
)
7477 && !fits_in_signed_word (n
))
7479 as_bad (_("16-bit jump out of range"));
7482 md_number_to_chars (p
, n
, size
);
7485 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7486 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
7487 if (i
.op
[0].imms
->X_op
!= O_constant
)
7488 as_bad (_("can't handle non absolute segment in `%s'"),
7490 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7496 fragS
*insn_start_frag
;
7497 offsetT insn_start_off
;
7499 /* Tie dwarf2 debug info to the address at the start of the insn.
7500 We can't do this after the insn has been output as the current
7501 frag may have been closed off. eg. by frag_var. */
7502 dwarf2_emit_insn (0);
7504 insn_start_frag
= frag_now
;
7505 insn_start_off
= frag_now_fix ();
7508 if (i
.tm
.opcode_modifier
.jump
)
7510 else if (i
.tm
.opcode_modifier
.jumpbyte
7511 || i
.tm
.opcode_modifier
.jumpdword
)
7513 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7514 output_interseg_jump ();
7517 /* Output normal instructions here. */
7521 unsigned int prefix
;
7524 && i
.tm
.base_opcode
== 0xfae
7526 && i
.imm_operands
== 1
7527 && (i
.op
[0].imms
->X_add_number
== 0xe8
7528 || i
.op
[0].imms
->X_add_number
== 0xf0
7529 || i
.op
[0].imms
->X_add_number
== 0xf8))
7531 /* Encode lfence, mfence, and sfence as
7532 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7533 offsetT val
= 0x240483f0ULL
;
7535 md_number_to_chars (p
, val
, 5);
7539 /* Some processors fail on LOCK prefix. This options makes
7540 assembler ignore LOCK prefix and serves as a workaround. */
7541 if (omit_lock_prefix
)
7543 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7545 i
.prefix
[LOCK_PREFIX
] = 0;
7548 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7549 don't need the explicit prefix. */
7550 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7552 switch (i
.tm
.opcode_length
)
7555 if (i
.tm
.base_opcode
& 0xff000000)
7557 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7562 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7564 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7565 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7568 if (prefix
!= REPE_PREFIX_OPCODE
7569 || (i
.prefix
[REP_PREFIX
]
7570 != REPE_PREFIX_OPCODE
))
7571 add_prefix (prefix
);
7574 add_prefix (prefix
);
7580 /* Check for pseudo prefixes. */
7581 as_bad_where (insn_start_frag
->fr_file
,
7582 insn_start_frag
->fr_line
,
7583 _("pseudo prefix without instruction"));
7589 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7590 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7591 R_X86_64_GOTTPOFF relocation so that linker can safely
7592 perform IE->LE optimization. */
7593 if (x86_elf_abi
== X86_64_X32_ABI
7595 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7596 && i
.prefix
[REX_PREFIX
] == 0)
7597 add_prefix (REX_OPCODE
);
7600 /* The prefix bytes. */
7601 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7603 FRAG_APPEND_1_CHAR (*q
);
7607 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7612 /* REX byte is encoded in VEX prefix. */
7616 FRAG_APPEND_1_CHAR (*q
);
7619 /* There should be no other prefixes for instructions
7624 /* For EVEX instructions i.vrex should become 0 after
7625 build_evex_prefix. For VEX instructions upper 16 registers
7626 aren't available, so VREX should be 0. */
7629 /* Now the VEX prefix. */
7630 p
= frag_more (i
.vex
.length
);
7631 for (j
= 0; j
< i
.vex
.length
; j
++)
7632 p
[j
] = i
.vex
.bytes
[j
];
7635 /* Now the opcode; be careful about word order here! */
7636 if (i
.tm
.opcode_length
== 1)
7638 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7642 switch (i
.tm
.opcode_length
)
7646 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7647 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7651 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7661 /* Put out high byte first: can't use md_number_to_chars! */
7662 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7663 *p
= i
.tm
.base_opcode
& 0xff;
7666 /* Now the modrm byte and sib byte (if present). */
7667 if (i
.tm
.opcode_modifier
.modrm
)
7669 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7672 /* If i.rm.regmem == ESP (4)
7673 && i.rm.mode != (Register mode)
7675 ==> need second modrm byte. */
7676 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7678 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
7679 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7681 | i
.sib
.scale
<< 6));
7684 if (i
.disp_operands
)
7685 output_disp (insn_start_frag
, insn_start_off
);
7688 output_imm (insn_start_frag
, insn_start_off
);
7694 pi ("" /*line*/, &i
);
7696 #endif /* DEBUG386 */
7699 /* Return the size of the displacement operand N. */
7702 disp_size (unsigned int n
)
7706 if (i
.types
[n
].bitfield
.disp64
)
7708 else if (i
.types
[n
].bitfield
.disp8
)
7710 else if (i
.types
[n
].bitfield
.disp16
)
7715 /* Return the size of the immediate operand N. */
7718 imm_size (unsigned int n
)
7721 if (i
.types
[n
].bitfield
.imm64
)
7723 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7725 else if (i
.types
[n
].bitfield
.imm16
)
7731 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7736 for (n
= 0; n
< i
.operands
; n
++)
7738 if (operand_type_check (i
.types
[n
], disp
))
7740 if (i
.op
[n
].disps
->X_op
== O_constant
)
7742 int size
= disp_size (n
);
7743 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7745 val
= offset_in_range (val
>> i
.memshift
, size
);
7746 p
= frag_more (size
);
7747 md_number_to_chars (p
, val
, size
);
7751 enum bfd_reloc_code_real reloc_type
;
7752 int size
= disp_size (n
);
7753 int sign
= i
.types
[n
].bitfield
.disp32s
;
7754 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7757 /* We can't have 8 bit displacement here. */
7758 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7760 /* The PC relative address is computed relative
7761 to the instruction boundary, so in case immediate
7762 fields follows, we need to adjust the value. */
7763 if (pcrel
&& i
.imm_operands
)
7768 for (n1
= 0; n1
< i
.operands
; n1
++)
7769 if (operand_type_check (i
.types
[n1
], imm
))
7771 /* Only one immediate is allowed for PC
7772 relative address. */
7773 gas_assert (sz
== 0);
7775 i
.op
[n
].disps
->X_add_number
-= sz
;
7777 /* We should find the immediate. */
7778 gas_assert (sz
!= 0);
7781 p
= frag_more (size
);
7782 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7784 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7785 && (((reloc_type
== BFD_RELOC_32
7786 || reloc_type
== BFD_RELOC_X86_64_32S
7787 || (reloc_type
== BFD_RELOC_64
7789 && (i
.op
[n
].disps
->X_op
== O_symbol
7790 || (i
.op
[n
].disps
->X_op
== O_add
7791 && ((symbol_get_value_expression
7792 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7794 || reloc_type
== BFD_RELOC_32_PCREL
))
7798 if (insn_start_frag
== frag_now
)
7799 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7804 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7805 for (fr
= insn_start_frag
->fr_next
;
7806 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7808 add
+= p
- frag_now
->fr_literal
;
7813 reloc_type
= BFD_RELOC_386_GOTPC
;
7814 i
.op
[n
].imms
->X_add_number
+= add
;
7816 else if (reloc_type
== BFD_RELOC_64
)
7817 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7819 /* Don't do the adjustment for x86-64, as there
7820 the pcrel addressing is relative to the _next_
7821 insn, and that is taken care of in other code. */
7822 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7824 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7825 size
, i
.op
[n
].disps
, pcrel
,
7827 /* Check for "call/jmp *mem", "mov mem, %reg",
7828 "test %reg, mem" and "binop mem, %reg" where binop
7829 is one of adc, add, and, cmp, or, sbb, sub, xor
7830 instructions. Always generate R_386_GOT32X for
7831 "sym*GOT" operand in 32-bit mode. */
7832 if ((generate_relax_relocations
7835 && i
.rm
.regmem
== 5))
7837 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7838 && ((i
.operands
== 1
7839 && i
.tm
.base_opcode
== 0xff
7840 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7842 && (i
.tm
.base_opcode
== 0x8b
7843 || i
.tm
.base_opcode
== 0x85
7844 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7848 fixP
->fx_tcbit
= i
.rex
!= 0;
7850 && (i
.base_reg
->reg_num
== RegRip
7851 || i
.base_reg
->reg_num
== RegEip
))
7852 fixP
->fx_tcbit2
= 1;
7855 fixP
->fx_tcbit2
= 1;
7863 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7868 for (n
= 0; n
< i
.operands
; n
++)
7870 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7871 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7874 if (operand_type_check (i
.types
[n
], imm
))
7876 if (i
.op
[n
].imms
->X_op
== O_constant
)
7878 int size
= imm_size (n
);
7881 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7883 p
= frag_more (size
);
7884 md_number_to_chars (p
, val
, size
);
7888 /* Not absolute_section.
7889 Need a 32-bit fixup (don't support 8bit
7890 non-absolute imms). Try to support other
7892 enum bfd_reloc_code_real reloc_type
;
7893 int size
= imm_size (n
);
7896 if (i
.types
[n
].bitfield
.imm32s
7897 && (i
.suffix
== QWORD_MNEM_SUFFIX
7898 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7903 p
= frag_more (size
);
7904 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7906 /* This is tough to explain. We end up with this one if we
7907 * have operands that look like
7908 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7909 * obtain the absolute address of the GOT, and it is strongly
7910 * preferable from a performance point of view to avoid using
7911 * a runtime relocation for this. The actual sequence of
7912 * instructions often look something like:
7917 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7919 * The call and pop essentially return the absolute address
7920 * of the label .L66 and store it in %ebx. The linker itself
7921 * will ultimately change the first operand of the addl so
7922 * that %ebx points to the GOT, but to keep things simple, the
7923 * .o file must have this operand set so that it generates not
7924 * the absolute address of .L66, but the absolute address of
7925 * itself. This allows the linker itself simply treat a GOTPC
7926 * relocation as asking for a pcrel offset to the GOT to be
7927 * added in, and the addend of the relocation is stored in the
7928 * operand field for the instruction itself.
7930 * Our job here is to fix the operand so that it would add
7931 * the correct offset so that %ebx would point to itself. The
7932 * thing that is tricky is that .-.L66 will point to the
7933 * beginning of the instruction, so we need to further modify
7934 * the operand so that it will point to itself. There are
7935 * other cases where you have something like:
7937 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7939 * and here no correction would be required. Internally in
7940 * the assembler we treat operands of this form as not being
7941 * pcrel since the '.' is explicitly mentioned, and I wonder
7942 * whether it would simplify matters to do it this way. Who
7943 * knows. In earlier versions of the PIC patches, the
7944 * pcrel_adjust field was used to store the correction, but
7945 * since the expression is not pcrel, I felt it would be
7946 * confusing to do it this way. */
7948 if ((reloc_type
== BFD_RELOC_32
7949 || reloc_type
== BFD_RELOC_X86_64_32S
7950 || reloc_type
== BFD_RELOC_64
)
7952 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7953 && (i
.op
[n
].imms
->X_op
== O_symbol
7954 || (i
.op
[n
].imms
->X_op
== O_add
7955 && ((symbol_get_value_expression
7956 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7961 if (insn_start_frag
== frag_now
)
7962 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7967 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7968 for (fr
= insn_start_frag
->fr_next
;
7969 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7971 add
+= p
- frag_now
->fr_literal
;
7975 reloc_type
= BFD_RELOC_386_GOTPC
;
7977 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7979 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7980 i
.op
[n
].imms
->X_add_number
+= add
;
7982 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7983 i
.op
[n
].imms
, 0, reloc_type
);
7989 /* x86_cons_fix_new is called via the expression parsing code when a
7990 reloc is needed. We use this hook to get the correct .got reloc. */
7991 static int cons_sign
= -1;
7994 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7995 expressionS
*exp
, bfd_reloc_code_real_type r
)
7997 r
= reloc (len
, 0, cons_sign
, r
);
8000 if (exp
->X_op
== O_secrel
)
8002 exp
->X_op
= O_symbol
;
8003 r
= BFD_RELOC_32_SECREL
;
8007 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
8010 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8011 purpose of the `.dc.a' internal pseudo-op. */
8014 x86_address_bytes (void)
8016 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
8018 return stdoutput
->arch_info
->bits_per_address
/ 8;
8021 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8023 # define lex_got(reloc, adjust, types) NULL
8025 /* Parse operands of the form
8026 <symbol>@GOTOFF+<nnn>
8027 and similar .plt or .got references.
8029 If we find one, set up the correct relocation in RELOC and copy the
8030 input string, minus the `@GOTOFF' into a malloc'd buffer for
8031 parsing by the calling routine. Return this buffer, and if ADJUST
8032 is non-null set it to the length of the string we removed from the
8033 input line. Otherwise return NULL. */
8035 lex_got (enum bfd_reloc_code_real
*rel
,
8037 i386_operand_type
*types
)
8039 /* Some of the relocations depend on the size of what field is to
8040 be relocated. But in our callers i386_immediate and i386_displacement
8041 we don't yet know the operand size (this will be set by insn
8042 matching). Hence we record the word32 relocation here,
8043 and adjust the reloc according to the real size in reloc(). */
8044 static const struct {
8047 const enum bfd_reloc_code_real rel
[2];
8048 const i386_operand_type types64
;
8050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8051 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
8053 OPERAND_TYPE_IMM32_64
},
8055 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
8056 BFD_RELOC_X86_64_PLTOFF64
},
8057 OPERAND_TYPE_IMM64
},
8058 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
8059 BFD_RELOC_X86_64_PLT32
},
8060 OPERAND_TYPE_IMM32_32S_DISP32
},
8061 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
8062 BFD_RELOC_X86_64_GOTPLT64
},
8063 OPERAND_TYPE_IMM64_DISP64
},
8064 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
8065 BFD_RELOC_X86_64_GOTOFF64
},
8066 OPERAND_TYPE_IMM64_DISP64
},
8067 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
8068 BFD_RELOC_X86_64_GOTPCREL
},
8069 OPERAND_TYPE_IMM32_32S_DISP32
},
8070 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
8071 BFD_RELOC_X86_64_TLSGD
},
8072 OPERAND_TYPE_IMM32_32S_DISP32
},
8073 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
8074 _dummy_first_bfd_reloc_code_real
},
8075 OPERAND_TYPE_NONE
},
8076 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
8077 BFD_RELOC_X86_64_TLSLD
},
8078 OPERAND_TYPE_IMM32_32S_DISP32
},
8079 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
8080 BFD_RELOC_X86_64_GOTTPOFF
},
8081 OPERAND_TYPE_IMM32_32S_DISP32
},
8082 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
8083 BFD_RELOC_X86_64_TPOFF32
},
8084 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8085 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
8086 _dummy_first_bfd_reloc_code_real
},
8087 OPERAND_TYPE_NONE
},
8088 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
8089 BFD_RELOC_X86_64_DTPOFF32
},
8090 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8091 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
8092 _dummy_first_bfd_reloc_code_real
},
8093 OPERAND_TYPE_NONE
},
8094 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
8095 _dummy_first_bfd_reloc_code_real
},
8096 OPERAND_TYPE_NONE
},
8097 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
8098 BFD_RELOC_X86_64_GOT32
},
8099 OPERAND_TYPE_IMM32_32S_64_DISP32
},
8100 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
8101 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
8102 OPERAND_TYPE_IMM32_32S_DISP32
},
8103 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
8104 BFD_RELOC_X86_64_TLSDESC_CALL
},
8105 OPERAND_TYPE_IMM32_32S_DISP32
},
8110 #if defined (OBJ_MAYBE_ELF)
8115 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8116 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8119 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8121 int len
= gotrel
[j
].len
;
8122 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8124 if (gotrel
[j
].rel
[object_64bit
] != 0)
8127 char *tmpbuf
, *past_reloc
;
8129 *rel
= gotrel
[j
].rel
[object_64bit
];
8133 if (flag_code
!= CODE_64BIT
)
8135 types
->bitfield
.imm32
= 1;
8136 types
->bitfield
.disp32
= 1;
8139 *types
= gotrel
[j
].types64
;
8142 if (j
!= 0 && GOT_symbol
== NULL
)
8143 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
8145 /* The length of the first part of our input line. */
8146 first
= cp
- input_line_pointer
;
8148 /* The second part goes from after the reloc token until
8149 (and including) an end_of_line char or comma. */
8150 past_reloc
= cp
+ 1 + len
;
8152 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8154 second
= cp
+ 1 - past_reloc
;
8156 /* Allocate and copy string. The trailing NUL shouldn't
8157 be necessary, but be safe. */
8158 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8159 memcpy (tmpbuf
, input_line_pointer
, first
);
8160 if (second
!= 0 && *past_reloc
!= ' ')
8161 /* Replace the relocation token with ' ', so that
8162 errors like foo@GOTOFF1 will be detected. */
8163 tmpbuf
[first
++] = ' ';
8165 /* Increment length by 1 if the relocation token is
8170 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8171 tmpbuf
[first
+ second
] = '\0';
8175 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8176 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8181 /* Might be a symbol version string. Don't as_bad here. */
8190 /* Parse operands of the form
8191 <symbol>@SECREL32+<nnn>
8193 If we find one, set up the correct relocation in RELOC and copy the
8194 input string, minus the `@SECREL32' into a malloc'd buffer for
8195 parsing by the calling routine. Return this buffer, and if ADJUST
8196 is non-null set it to the length of the string we removed from the
8197 input line. Otherwise return NULL.
8199 This function is copied from the ELF version above adjusted for PE targets. */
8202 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
8203 int *adjust ATTRIBUTE_UNUSED
,
8204 i386_operand_type
*types
)
8210 const enum bfd_reloc_code_real rel
[2];
8211 const i386_operand_type types64
;
8215 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
8216 BFD_RELOC_32_SECREL
},
8217 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
8223 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
8224 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
8227 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
8229 int len
= gotrel
[j
].len
;
8231 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
8233 if (gotrel
[j
].rel
[object_64bit
] != 0)
8236 char *tmpbuf
, *past_reloc
;
8238 *rel
= gotrel
[j
].rel
[object_64bit
];
8244 if (flag_code
!= CODE_64BIT
)
8246 types
->bitfield
.imm32
= 1;
8247 types
->bitfield
.disp32
= 1;
8250 *types
= gotrel
[j
].types64
;
8253 /* The length of the first part of our input line. */
8254 first
= cp
- input_line_pointer
;
8256 /* The second part goes from after the reloc token until
8257 (and including) an end_of_line char or comma. */
8258 past_reloc
= cp
+ 1 + len
;
8260 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
8262 second
= cp
+ 1 - past_reloc
;
8264 /* Allocate and copy string. The trailing NUL shouldn't
8265 be necessary, but be safe. */
8266 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
8267 memcpy (tmpbuf
, input_line_pointer
, first
);
8268 if (second
!= 0 && *past_reloc
!= ' ')
8269 /* Replace the relocation token with ' ', so that
8270 errors like foo@SECLREL321 will be detected. */
8271 tmpbuf
[first
++] = ' ';
8272 memcpy (tmpbuf
+ first
, past_reloc
, second
);
8273 tmpbuf
[first
+ second
] = '\0';
8277 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8278 gotrel
[j
].str
, 1 << (5 + object_64bit
));
8283 /* Might be a symbol version string. Don't as_bad here. */
8289 bfd_reloc_code_real_type
8290 x86_cons (expressionS
*exp
, int size
)
8292 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
8294 intel_syntax
= -intel_syntax
;
8297 if (size
== 4 || (object_64bit
&& size
== 8))
8299 /* Handle @GOTOFF and the like in an expression. */
8301 char *gotfree_input_line
;
8304 save
= input_line_pointer
;
8305 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
8306 if (gotfree_input_line
)
8307 input_line_pointer
= gotfree_input_line
;
8311 if (gotfree_input_line
)
8313 /* expression () has merrily parsed up to the end of line,
8314 or a comma - in the wrong buffer. Transfer how far
8315 input_line_pointer has moved to the right buffer. */
8316 input_line_pointer
= (save
8317 + (input_line_pointer
- gotfree_input_line
)
8319 free (gotfree_input_line
);
8320 if (exp
->X_op
== O_constant
8321 || exp
->X_op
== O_absent
8322 || exp
->X_op
== O_illegal
8323 || exp
->X_op
== O_register
8324 || exp
->X_op
== O_big
)
8326 char c
= *input_line_pointer
;
8327 *input_line_pointer
= 0;
8328 as_bad (_("missing or invalid expression `%s'"), save
);
8329 *input_line_pointer
= c
;
8336 intel_syntax
= -intel_syntax
;
8339 i386_intel_simplify (exp
);
8345 signed_cons (int size
)
8347 if (flag_code
== CODE_64BIT
)
8355 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
8362 if (exp
.X_op
== O_symbol
)
8363 exp
.X_op
= O_secrel
;
8365 emit_expr (&exp
, 4);
8367 while (*input_line_pointer
++ == ',');
8369 input_line_pointer
--;
8370 demand_empty_rest_of_line ();
8374 /* Handle Vector operations. */
8377 check_VecOperations (char *op_string
, char *op_end
)
8379 const reg_entry
*mask
;
8384 && (op_end
== NULL
|| op_string
< op_end
))
8387 if (*op_string
== '{')
8391 /* Check broadcasts. */
8392 if (strncmp (op_string
, "1to", 3) == 0)
8397 goto duplicated_vec_op
;
8400 if (*op_string
== '8')
8401 bcst_type
= BROADCAST_1TO8
;
8402 else if (*op_string
== '4')
8403 bcst_type
= BROADCAST_1TO4
;
8404 else if (*op_string
== '2')
8405 bcst_type
= BROADCAST_1TO2
;
8406 else if (*op_string
== '1'
8407 && *(op_string
+1) == '6')
8409 bcst_type
= BROADCAST_1TO16
;
8414 as_bad (_("Unsupported broadcast: `%s'"), saved
);
8419 broadcast_op
.type
= bcst_type
;
8420 broadcast_op
.operand
= this_operand
;
8421 i
.broadcast
= &broadcast_op
;
8423 /* Check masking operation. */
8424 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
8426 /* k0 can't be used for write mask. */
8427 if (!mask
->reg_type
.bitfield
.regmask
|| mask
->reg_num
== 0)
8429 as_bad (_("`%s%s' can't be used for write mask"),
8430 register_prefix
, mask
->reg_name
);
8436 mask_op
.mask
= mask
;
8437 mask_op
.zeroing
= 0;
8438 mask_op
.operand
= this_operand
;
8444 goto duplicated_vec_op
;
8446 i
.mask
->mask
= mask
;
8448 /* Only "{z}" is allowed here. No need to check
8449 zeroing mask explicitly. */
8450 if (i
.mask
->operand
!= this_operand
)
8452 as_bad (_("invalid write mask `%s'"), saved
);
8459 /* Check zeroing-flag for masking operation. */
8460 else if (*op_string
== 'z')
8464 mask_op
.mask
= NULL
;
8465 mask_op
.zeroing
= 1;
8466 mask_op
.operand
= this_operand
;
8471 if (i
.mask
->zeroing
)
8474 as_bad (_("duplicated `%s'"), saved
);
8478 i
.mask
->zeroing
= 1;
8480 /* Only "{%k}" is allowed here. No need to check mask
8481 register explicitly. */
8482 if (i
.mask
->operand
!= this_operand
)
8484 as_bad (_("invalid zeroing-masking `%s'"),
8493 goto unknown_vec_op
;
8495 if (*op_string
!= '}')
8497 as_bad (_("missing `}' in `%s'"), saved
);
8504 /* We don't know this one. */
8505 as_bad (_("unknown vector operation: `%s'"), saved
);
8509 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
8511 as_bad (_("zeroing-masking only allowed with write mask"));
8519 i386_immediate (char *imm_start
)
8521 char *save_input_line_pointer
;
8522 char *gotfree_input_line
;
8525 i386_operand_type types
;
8527 operand_type_set (&types
, ~0);
8529 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8531 as_bad (_("at most %d immediate operands are allowed"),
8532 MAX_IMMEDIATE_OPERANDS
);
8536 exp
= &im_expressions
[i
.imm_operands
++];
8537 i
.op
[this_operand
].imms
= exp
;
8539 if (is_space_char (*imm_start
))
8542 save_input_line_pointer
= input_line_pointer
;
8543 input_line_pointer
= imm_start
;
8545 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8546 if (gotfree_input_line
)
8547 input_line_pointer
= gotfree_input_line
;
8549 exp_seg
= expression (exp
);
8553 /* Handle vector operations. */
8554 if (*input_line_pointer
== '{')
8556 input_line_pointer
= check_VecOperations (input_line_pointer
,
8558 if (input_line_pointer
== NULL
)
8562 if (*input_line_pointer
)
8563 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8565 input_line_pointer
= save_input_line_pointer
;
8566 if (gotfree_input_line
)
8568 free (gotfree_input_line
);
8570 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8571 exp
->X_op
= O_illegal
;
8574 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8578 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8579 i386_operand_type types
, const char *imm_start
)
8581 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8584 as_bad (_("missing or invalid immediate expression `%s'"),
8588 else if (exp
->X_op
== O_constant
)
8590 /* Size it properly later. */
8591 i
.types
[this_operand
].bitfield
.imm64
= 1;
8592 /* If not 64bit, sign extend val. */
8593 if (flag_code
!= CODE_64BIT
8594 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8596 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8598 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8599 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8600 && exp_seg
!= absolute_section
8601 && exp_seg
!= text_section
8602 && exp_seg
!= data_section
8603 && exp_seg
!= bss_section
8604 && exp_seg
!= undefined_section
8605 && !bfd_is_com_section (exp_seg
))
8607 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8611 else if (!intel_syntax
&& exp_seg
== reg_section
)
8614 as_bad (_("illegal immediate register operand %s"), imm_start
);
8619 /* This is an address. The size of the address will be
8620 determined later, depending on destination register,
8621 suffix, or the default for the section. */
8622 i
.types
[this_operand
].bitfield
.imm8
= 1;
8623 i
.types
[this_operand
].bitfield
.imm16
= 1;
8624 i
.types
[this_operand
].bitfield
.imm32
= 1;
8625 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8626 i
.types
[this_operand
].bitfield
.imm64
= 1;
8627 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8635 i386_scale (char *scale
)
8638 char *save
= input_line_pointer
;
8640 input_line_pointer
= scale
;
8641 val
= get_absolute_expression ();
8646 i
.log2_scale_factor
= 0;
8649 i
.log2_scale_factor
= 1;
8652 i
.log2_scale_factor
= 2;
8655 i
.log2_scale_factor
= 3;
8659 char sep
= *input_line_pointer
;
8661 *input_line_pointer
= '\0';
8662 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8664 *input_line_pointer
= sep
;
8665 input_line_pointer
= save
;
8669 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8671 as_warn (_("scale factor of %d without an index register"),
8672 1 << i
.log2_scale_factor
);
8673 i
.log2_scale_factor
= 0;
8675 scale
= input_line_pointer
;
8676 input_line_pointer
= save
;
8681 i386_displacement (char *disp_start
, char *disp_end
)
8685 char *save_input_line_pointer
;
8686 char *gotfree_input_line
;
8688 i386_operand_type bigdisp
, types
= anydisp
;
8691 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8693 as_bad (_("at most %d displacement operands are allowed"),
8694 MAX_MEMORY_OPERANDS
);
8698 operand_type_set (&bigdisp
, 0);
8699 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8700 || (!current_templates
->start
->opcode_modifier
.jump
8701 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8703 bigdisp
.bitfield
.disp32
= 1;
8704 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8705 if (flag_code
== CODE_64BIT
)
8709 bigdisp
.bitfield
.disp32s
= 1;
8710 bigdisp
.bitfield
.disp64
= 1;
8713 else if ((flag_code
== CODE_16BIT
) ^ override
)
8715 bigdisp
.bitfield
.disp32
= 0;
8716 bigdisp
.bitfield
.disp16
= 1;
8721 /* For PC-relative branches, the width of the displacement
8722 is dependent upon data size, not address size. */
8723 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8724 if (flag_code
== CODE_64BIT
)
8726 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8727 bigdisp
.bitfield
.disp16
= 1;
8730 bigdisp
.bitfield
.disp32
= 1;
8731 bigdisp
.bitfield
.disp32s
= 1;
8737 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8739 : LONG_MNEM_SUFFIX
));
8740 bigdisp
.bitfield
.disp32
= 1;
8741 if ((flag_code
== CODE_16BIT
) ^ override
)
8743 bigdisp
.bitfield
.disp32
= 0;
8744 bigdisp
.bitfield
.disp16
= 1;
8748 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8751 exp
= &disp_expressions
[i
.disp_operands
];
8752 i
.op
[this_operand
].disps
= exp
;
8754 save_input_line_pointer
= input_line_pointer
;
8755 input_line_pointer
= disp_start
;
8756 END_STRING_AND_SAVE (disp_end
);
8758 #ifndef GCC_ASM_O_HACK
8759 #define GCC_ASM_O_HACK 0
8762 END_STRING_AND_SAVE (disp_end
+ 1);
8763 if (i
.types
[this_operand
].bitfield
.baseIndex
8764 && displacement_string_end
[-1] == '+')
8766 /* This hack is to avoid a warning when using the "o"
8767 constraint within gcc asm statements.
8770 #define _set_tssldt_desc(n,addr,limit,type) \
8771 __asm__ __volatile__ ( \
8773 "movw %w1,2+%0\n\t" \
8775 "movb %b1,4+%0\n\t" \
8776 "movb %4,5+%0\n\t" \
8777 "movb $0,6+%0\n\t" \
8778 "movb %h1,7+%0\n\t" \
8780 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8782 This works great except that the output assembler ends
8783 up looking a bit weird if it turns out that there is
8784 no offset. You end up producing code that looks like:
8797 So here we provide the missing zero. */
8799 *displacement_string_end
= '0';
8802 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8803 if (gotfree_input_line
)
8804 input_line_pointer
= gotfree_input_line
;
8806 exp_seg
= expression (exp
);
8809 if (*input_line_pointer
)
8810 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8812 RESTORE_END_STRING (disp_end
+ 1);
8814 input_line_pointer
= save_input_line_pointer
;
8815 if (gotfree_input_line
)
8817 free (gotfree_input_line
);
8819 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8820 exp
->X_op
= O_illegal
;
8823 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8825 RESTORE_END_STRING (disp_end
);
8831 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8832 i386_operand_type types
, const char *disp_start
)
8834 i386_operand_type bigdisp
;
8837 /* We do this to make sure that the section symbol is in
8838 the symbol table. We will ultimately change the relocation
8839 to be relative to the beginning of the section. */
8840 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8841 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8842 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8844 if (exp
->X_op
!= O_symbol
)
8847 if (S_IS_LOCAL (exp
->X_add_symbol
)
8848 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8849 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8850 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8851 exp
->X_op
= O_subtract
;
8852 exp
->X_op_symbol
= GOT_symbol
;
8853 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8854 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8855 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8856 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8858 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8861 else if (exp
->X_op
== O_absent
8862 || exp
->X_op
== O_illegal
8863 || exp
->X_op
== O_big
)
8866 as_bad (_("missing or invalid displacement expression `%s'"),
8871 else if (flag_code
== CODE_64BIT
8872 && !i
.prefix
[ADDR_PREFIX
]
8873 && exp
->X_op
== O_constant
)
8875 /* Since displacement is signed extended to 64bit, don't allow
8876 disp32 and turn off disp32s if they are out of range. */
8877 i
.types
[this_operand
].bitfield
.disp32
= 0;
8878 if (!fits_in_signed_long (exp
->X_add_number
))
8880 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8881 if (i
.types
[this_operand
].bitfield
.baseindex
)
8883 as_bad (_("0x%lx out range of signed 32bit displacement"),
8884 (long) exp
->X_add_number
);
8890 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8891 else if (exp
->X_op
!= O_constant
8892 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8893 && exp_seg
!= absolute_section
8894 && exp_seg
!= text_section
8895 && exp_seg
!= data_section
8896 && exp_seg
!= bss_section
8897 && exp_seg
!= undefined_section
8898 && !bfd_is_com_section (exp_seg
))
8900 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8905 /* Check if this is a displacement only operand. */
8906 bigdisp
= i
.types
[this_operand
];
8907 bigdisp
.bitfield
.disp8
= 0;
8908 bigdisp
.bitfield
.disp16
= 0;
8909 bigdisp
.bitfield
.disp32
= 0;
8910 bigdisp
.bitfield
.disp32s
= 0;
8911 bigdisp
.bitfield
.disp64
= 0;
8912 if (operand_type_all_zero (&bigdisp
))
8913 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8919 /* Return the active addressing mode, taking address override and
8920 registers forming the address into consideration. Update the
8921 address override prefix if necessary. */
8923 static enum flag_code
8924 i386_addressing_mode (void)
8926 enum flag_code addr_mode
;
8928 if (i
.prefix
[ADDR_PREFIX
])
8929 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8932 addr_mode
= flag_code
;
8934 #if INFER_ADDR_PREFIX
8935 if (i
.mem_operands
== 0)
8937 /* Infer address prefix from the first memory operand. */
8938 const reg_entry
*addr_reg
= i
.base_reg
;
8940 if (addr_reg
== NULL
)
8941 addr_reg
= i
.index_reg
;
8945 if (addr_reg
->reg_num
== RegEip
8946 || addr_reg
->reg_num
== RegEiz
8947 || addr_reg
->reg_type
.bitfield
.dword
)
8948 addr_mode
= CODE_32BIT
;
8949 else if (flag_code
!= CODE_64BIT
8950 && addr_reg
->reg_type
.bitfield
.word
)
8951 addr_mode
= CODE_16BIT
;
8953 if (addr_mode
!= flag_code
)
8955 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8957 /* Change the size of any displacement too. At most one
8958 of Disp16 or Disp32 is set.
8959 FIXME. There doesn't seem to be any real need for
8960 separate Disp16 and Disp32 flags. The same goes for
8961 Imm16 and Imm32. Removing them would probably clean
8962 up the code quite a lot. */
8963 if (flag_code
!= CODE_64BIT
8964 && (i
.types
[this_operand
].bitfield
.disp16
8965 || i
.types
[this_operand
].bitfield
.disp32
))
8966 i
.types
[this_operand
]
8967 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8977 /* Make sure the memory operand we've been dealt is valid.
8978 Return 1 on success, 0 on a failure. */
8981 i386_index_check (const char *operand_string
)
8983 const char *kind
= "base/index";
8984 enum flag_code addr_mode
= i386_addressing_mode ();
8986 if (current_templates
->start
->opcode_modifier
.isstring
8987 && !current_templates
->start
->opcode_modifier
.immext
8988 && (current_templates
->end
[-1].opcode_modifier
.isstring
8991 /* Memory operands of string insns are special in that they only allow
8992 a single register (rDI, rSI, or rBX) as their memory address. */
8993 const reg_entry
*expected_reg
;
8994 static const char *di_si
[][2] =
9000 static const char *bx
[] = { "ebx", "bx", "rbx" };
9002 kind
= "string address";
9004 if (current_templates
->start
->opcode_modifier
.repprefixok
)
9006 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
9008 if (!type
.bitfield
.baseindex
9009 || ((!i
.mem_operands
!= !intel_syntax
)
9010 && current_templates
->end
[-1].operand_types
[1]
9011 .bitfield
.baseindex
))
9012 type
= current_templates
->end
[-1].operand_types
[1];
9013 expected_reg
= hash_find (reg_hash
,
9014 di_si
[addr_mode
][type
.bitfield
.esseg
]);
9018 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
9020 if (i
.base_reg
!= expected_reg
9022 || operand_type_check (i
.types
[this_operand
], disp
))
9024 /* The second memory operand must have the same size as
9028 && !((addr_mode
== CODE_64BIT
9029 && i
.base_reg
->reg_type
.bitfield
.qword
)
9030 || (addr_mode
== CODE_32BIT
9031 ? i
.base_reg
->reg_type
.bitfield
.dword
9032 : i
.base_reg
->reg_type
.bitfield
.word
)))
9035 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9037 intel_syntax
? '[' : '(',
9039 expected_reg
->reg_name
,
9040 intel_syntax
? ']' : ')');
9047 as_bad (_("`%s' is not a valid %s expression"),
9048 operand_string
, kind
);
9053 if (addr_mode
!= CODE_16BIT
)
9055 /* 32-bit/64-bit checks. */
9057 && (addr_mode
== CODE_64BIT
9058 ? !i
.base_reg
->reg_type
.bitfield
.qword
9059 : !i
.base_reg
->reg_type
.bitfield
.dword
)
9061 || (i
.base_reg
->reg_num
9062 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
9064 && !i
.index_reg
->reg_type
.bitfield
.xmmword
9065 && !i
.index_reg
->reg_type
.bitfield
.ymmword
9066 && !i
.index_reg
->reg_type
.bitfield
.zmmword
9067 && ((addr_mode
== CODE_64BIT
9068 ? !(i
.index_reg
->reg_type
.bitfield
.qword
9069 || i
.index_reg
->reg_num
== RegRiz
)
9070 : !(i
.index_reg
->reg_type
.bitfield
.dword
9071 || i
.index_reg
->reg_num
== RegEiz
))
9072 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
9075 /* bndmk, bndldx, and bndstx have special restrictions. */
9076 if (current_templates
->start
->base_opcode
== 0xf30f1b
9077 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
9079 /* They cannot use RIP-relative addressing. */
9080 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegRip
)
9082 as_bad (_("`%s' cannot be used here"), operand_string
);
9086 /* bndldx and bndstx ignore their scale factor. */
9087 if (current_templates
->start
->base_opcode
!= 0xf30f1b
9088 && i
.log2_scale_factor
)
9089 as_warn (_("register scaling is being ignored here"));
9094 /* 16-bit checks. */
9096 && (!i
.base_reg
->reg_type
.bitfield
.word
9097 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
9099 && (!i
.index_reg
->reg_type
.bitfield
.word
9100 || !i
.index_reg
->reg_type
.bitfield
.baseindex
9102 && i
.base_reg
->reg_num
< 6
9103 && i
.index_reg
->reg_num
>= 6
9104 && i
.log2_scale_factor
== 0))))
9111 /* Handle vector immediates. */
9114 RC_SAE_immediate (const char *imm_start
)
9116 unsigned int match_found
, j
;
9117 const char *pstr
= imm_start
;
9125 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
9127 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
9131 rc_op
.type
= RC_NamesTable
[j
].type
;
9132 rc_op
.operand
= this_operand
;
9133 i
.rounding
= &rc_op
;
9137 as_bad (_("duplicated `%s'"), imm_start
);
9140 pstr
+= RC_NamesTable
[j
].len
;
9150 as_bad (_("Missing '}': '%s'"), imm_start
);
9153 /* RC/SAE immediate string should contain nothing more. */;
9156 as_bad (_("Junk after '}': '%s'"), imm_start
);
9160 exp
= &im_expressions
[i
.imm_operands
++];
9161 i
.op
[this_operand
].imms
= exp
;
9163 exp
->X_op
= O_constant
;
9164 exp
->X_add_number
= 0;
9165 exp
->X_add_symbol
= (symbolS
*) 0;
9166 exp
->X_op_symbol
= (symbolS
*) 0;
9168 i
.types
[this_operand
].bitfield
.imm8
= 1;
9172 /* Only string instructions can have a second memory operand, so
9173 reduce current_templates to just those if it contains any. */
9175 maybe_adjust_templates (void)
9177 const insn_template
*t
;
9179 gas_assert (i
.mem_operands
== 1);
9181 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
9182 if (t
->opcode_modifier
.isstring
)
9185 if (t
< current_templates
->end
)
9187 static templates aux_templates
;
9188 bfd_boolean recheck
;
9190 aux_templates
.start
= t
;
9191 for (; t
< current_templates
->end
; ++t
)
9192 if (!t
->opcode_modifier
.isstring
)
9194 aux_templates
.end
= t
;
9196 /* Determine whether to re-check the first memory operand. */
9197 recheck
= (aux_templates
.start
!= current_templates
->start
9198 || t
!= current_templates
->end
);
9200 current_templates
= &aux_templates
;
9205 if (i
.memop1_string
!= NULL
9206 && i386_index_check (i
.memop1_string
) == 0)
9215 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9219 i386_att_operand (char *operand_string
)
9223 char *op_string
= operand_string
;
9225 if (is_space_char (*op_string
))
9228 /* We check for an absolute prefix (differentiating,
9229 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9230 if (*op_string
== ABSOLUTE_PREFIX
)
9233 if (is_space_char (*op_string
))
9235 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9238 /* Check if operand is a register. */
9239 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
9241 i386_operand_type temp
;
9243 /* Check for a segment override by searching for ':' after a
9244 segment register. */
9246 if (is_space_char (*op_string
))
9248 if (*op_string
== ':'
9249 && (r
->reg_type
.bitfield
.sreg2
9250 || r
->reg_type
.bitfield
.sreg3
))
9255 i
.seg
[i
.mem_operands
] = &es
;
9258 i
.seg
[i
.mem_operands
] = &cs
;
9261 i
.seg
[i
.mem_operands
] = &ss
;
9264 i
.seg
[i
.mem_operands
] = &ds
;
9267 i
.seg
[i
.mem_operands
] = &fs
;
9270 i
.seg
[i
.mem_operands
] = &gs
;
9274 /* Skip the ':' and whitespace. */
9276 if (is_space_char (*op_string
))
9279 if (!is_digit_char (*op_string
)
9280 && !is_identifier_char (*op_string
)
9281 && *op_string
!= '('
9282 && *op_string
!= ABSOLUTE_PREFIX
)
9284 as_bad (_("bad memory operand `%s'"), op_string
);
9287 /* Handle case of %es:*foo. */
9288 if (*op_string
== ABSOLUTE_PREFIX
)
9291 if (is_space_char (*op_string
))
9293 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9295 goto do_memory_reference
;
9298 /* Handle vector operations. */
9299 if (*op_string
== '{')
9301 op_string
= check_VecOperations (op_string
, NULL
);
9302 if (op_string
== NULL
)
9308 as_bad (_("junk `%s' after register"), op_string
);
9312 temp
.bitfield
.baseindex
= 0;
9313 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9315 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9316 i
.op
[this_operand
].regs
= r
;
9319 else if (*op_string
== REGISTER_PREFIX
)
9321 as_bad (_("bad register name `%s'"), op_string
);
9324 else if (*op_string
== IMMEDIATE_PREFIX
)
9327 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
9329 as_bad (_("immediate operand illegal with absolute jump"));
9332 if (!i386_immediate (op_string
))
9335 else if (RC_SAE_immediate (operand_string
))
9337 /* If it is a RC or SAE immediate, do nothing. */
9340 else if (is_digit_char (*op_string
)
9341 || is_identifier_char (*op_string
)
9342 || *op_string
== '"'
9343 || *op_string
== '(')
9345 /* This is a memory reference of some sort. */
9348 /* Start and end of displacement string expression (if found). */
9349 char *displacement_string_start
;
9350 char *displacement_string_end
;
9353 do_memory_reference
:
9354 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
9356 if ((i
.mem_operands
== 1
9357 && !current_templates
->start
->opcode_modifier
.isstring
)
9358 || i
.mem_operands
== 2)
9360 as_bad (_("too many memory references for `%s'"),
9361 current_templates
->start
->name
);
9365 /* Check for base index form. We detect the base index form by
9366 looking for an ')' at the end of the operand, searching
9367 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9369 base_string
= op_string
+ strlen (op_string
);
9371 /* Handle vector operations. */
9372 vop_start
= strchr (op_string
, '{');
9373 if (vop_start
&& vop_start
< base_string
)
9375 if (check_VecOperations (vop_start
, base_string
) == NULL
)
9377 base_string
= vop_start
;
9381 if (is_space_char (*base_string
))
9384 /* If we only have a displacement, set-up for it to be parsed later. */
9385 displacement_string_start
= op_string
;
9386 displacement_string_end
= base_string
+ 1;
9388 if (*base_string
== ')')
9391 unsigned int parens_balanced
= 1;
9392 /* We've already checked that the number of left & right ()'s are
9393 equal, so this loop will not be infinite. */
9397 if (*base_string
== ')')
9399 if (*base_string
== '(')
9402 while (parens_balanced
);
9404 temp_string
= base_string
;
9406 /* Skip past '(' and whitespace. */
9408 if (is_space_char (*base_string
))
9411 if (*base_string
== ','
9412 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
9415 displacement_string_end
= temp_string
;
9417 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9421 base_string
= end_op
;
9422 if (is_space_char (*base_string
))
9426 /* There may be an index reg or scale factor here. */
9427 if (*base_string
== ',')
9430 if (is_space_char (*base_string
))
9433 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
9436 base_string
= end_op
;
9437 if (is_space_char (*base_string
))
9439 if (*base_string
== ',')
9442 if (is_space_char (*base_string
))
9445 else if (*base_string
!= ')')
9447 as_bad (_("expecting `,' or `)' "
9448 "after index register in `%s'"),
9453 else if (*base_string
== REGISTER_PREFIX
)
9455 end_op
= strchr (base_string
, ',');
9458 as_bad (_("bad register name `%s'"), base_string
);
9462 /* Check for scale factor. */
9463 if (*base_string
!= ')')
9465 char *end_scale
= i386_scale (base_string
);
9470 base_string
= end_scale
;
9471 if (is_space_char (*base_string
))
9473 if (*base_string
!= ')')
9475 as_bad (_("expecting `)' "
9476 "after scale factor in `%s'"),
9481 else if (!i
.index_reg
)
9483 as_bad (_("expecting index register or scale factor "
9484 "after `,'; got '%c'"),
9489 else if (*base_string
!= ')')
9491 as_bad (_("expecting `,' or `)' "
9492 "after base register in `%s'"),
9497 else if (*base_string
== REGISTER_PREFIX
)
9499 end_op
= strchr (base_string
, ',');
9502 as_bad (_("bad register name `%s'"), base_string
);
9507 /* If there's an expression beginning the operand, parse it,
9508 assuming displacement_string_start and
9509 displacement_string_end are meaningful. */
9510 if (displacement_string_start
!= displacement_string_end
)
9512 if (!i386_displacement (displacement_string_start
,
9513 displacement_string_end
))
9517 /* Special case for (%dx) while doing input/output op. */
9519 && operand_type_equal (&i
.base_reg
->reg_type
,
9520 ®16_inoutportreg
)
9522 && i
.log2_scale_factor
== 0
9523 && i
.seg
[i
.mem_operands
] == 0
9524 && !operand_type_check (i
.types
[this_operand
], disp
))
9526 i
.types
[this_operand
] = inoutportreg
;
9530 if (i386_index_check (operand_string
) == 0)
9532 i
.types
[this_operand
].bitfield
.mem
= 1;
9533 if (i
.mem_operands
== 0)
9534 i
.memop1_string
= xstrdup (operand_string
);
9539 /* It's not a memory operand; argh! */
9540 as_bad (_("invalid char %s beginning operand %d `%s'"),
9541 output_invalid (*op_string
),
9546 return 1; /* Normal return. */
9549 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9550 that an rs_machine_dependent frag may reach. */
9553 i386_frag_max_var (fragS
*frag
)
9555 /* The only relaxable frags are for jumps.
9556 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9557 gas_assert (frag
->fr_type
== rs_machine_dependent
);
9558 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
9561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9563 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
9565 /* STT_GNU_IFUNC symbol must go through PLT. */
9566 if ((symbol_get_bfdsym (fr_symbol
)->flags
9567 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
9570 if (!S_IS_EXTERNAL (fr_symbol
))
9571 /* Symbol may be weak or local. */
9572 return !S_IS_WEAK (fr_symbol
);
9574 /* Global symbols with non-default visibility can't be preempted. */
9575 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9578 if (fr_var
!= NO_RELOC
)
9579 switch ((enum bfd_reloc_code_real
) fr_var
)
9581 case BFD_RELOC_386_PLT32
:
9582 case BFD_RELOC_X86_64_PLT32
:
9583 /* Symbol with PLT relocation may be preempted. */
9589 /* Global symbols with default visibility in a shared library may be
9590 preempted by another definition. */
9595 /* md_estimate_size_before_relax()
9597 Called just before relax() for rs_machine_dependent frags. The x86
9598 assembler uses these frags to handle variable size jump
9601 Any symbol that is now undefined will not become defined.
9602 Return the correct fr_subtype in the frag.
9603 Return the initial "guess for variable size of frag" to caller.
9604 The guess is actually the growth beyond the fixed part. Whatever
9605 we do to grow the fixed or variable part contributes to our
9609 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9611 /* We've already got fragP->fr_subtype right; all we have to do is
9612 check for un-relaxable symbols. On an ELF system, we can't relax
9613 an externally visible symbol, because it may be overridden by a
9615 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9618 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9621 #if defined (OBJ_COFF) && defined (TE_PE)
9622 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9623 && S_IS_WEAK (fragP
->fr_symbol
))
9627 /* Symbol is undefined in this segment, or we need to keep a
9628 reloc so that weak symbols can be overridden. */
9629 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9630 enum bfd_reloc_code_real reloc_type
;
9631 unsigned char *opcode
;
9634 if (fragP
->fr_var
!= NO_RELOC
)
9635 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9637 reloc_type
= BFD_RELOC_16_PCREL
;
9638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9639 else if (need_plt32_p (fragP
->fr_symbol
))
9640 reloc_type
= BFD_RELOC_X86_64_PLT32
;
9643 reloc_type
= BFD_RELOC_32_PCREL
;
9645 old_fr_fix
= fragP
->fr_fix
;
9646 opcode
= (unsigned char *) fragP
->fr_opcode
;
9648 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9651 /* Make jmp (0xeb) a (d)word displacement jump. */
9653 fragP
->fr_fix
+= size
;
9654 fix_new (fragP
, old_fr_fix
, size
,
9656 fragP
->fr_offset
, 1,
9662 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9664 /* Negate the condition, and branch past an
9665 unconditional jump. */
9668 /* Insert an unconditional jump. */
9670 /* We added two extra opcode bytes, and have a two byte
9672 fragP
->fr_fix
+= 2 + 2;
9673 fix_new (fragP
, old_fr_fix
+ 2, 2,
9675 fragP
->fr_offset
, 1,
9682 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9687 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9689 fragP
->fr_offset
, 1,
9691 fixP
->fx_signed
= 1;
9695 /* This changes the byte-displacement jump 0x7N
9696 to the (d)word-displacement jump 0x0f,0x8N. */
9697 opcode
[1] = opcode
[0] + 0x10;
9698 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9699 /* We've added an opcode byte. */
9700 fragP
->fr_fix
+= 1 + size
;
9701 fix_new (fragP
, old_fr_fix
+ 1, size
,
9703 fragP
->fr_offset
, 1,
9708 BAD_CASE (fragP
->fr_subtype
);
9712 return fragP
->fr_fix
- old_fr_fix
;
9715 /* Guess size depending on current relax state. Initially the relax
9716 state will correspond to a short jump and we return 1, because
9717 the variable part of the frag (the branch offset) is one byte
9718 long. However, we can relax a section more than once and in that
9719 case we must either set fr_subtype back to the unrelaxed state,
9720 or return the value for the appropriate branch. */
9721 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9724 /* Called after relax() is finished.
9726 In: Address of frag.
9727 fr_type == rs_machine_dependent.
9728 fr_subtype is what the address relaxed to.
9730 Out: Any fixSs and constants are set up.
9731 Caller will turn frag into a ".space 0". */
9734 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9737 unsigned char *opcode
;
9738 unsigned char *where_to_put_displacement
= NULL
;
9739 offsetT target_address
;
9740 offsetT opcode_address
;
9741 unsigned int extension
= 0;
9742 offsetT displacement_from_opcode_start
;
9744 opcode
= (unsigned char *) fragP
->fr_opcode
;
9746 /* Address we want to reach in file space. */
9747 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9749 /* Address opcode resides at in file space. */
9750 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9752 /* Displacement from opcode start to fill into instruction. */
9753 displacement_from_opcode_start
= target_address
- opcode_address
;
9755 if ((fragP
->fr_subtype
& BIG
) == 0)
9757 /* Don't have to change opcode. */
9758 extension
= 1; /* 1 opcode + 1 displacement */
9759 where_to_put_displacement
= &opcode
[1];
9763 if (no_cond_jump_promotion
9764 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9765 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9766 _("long jump required"));
9768 switch (fragP
->fr_subtype
)
9770 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9771 extension
= 4; /* 1 opcode + 4 displacement */
9773 where_to_put_displacement
= &opcode
[1];
9776 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9777 extension
= 2; /* 1 opcode + 2 displacement */
9779 where_to_put_displacement
= &opcode
[1];
9782 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9783 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9784 extension
= 5; /* 2 opcode + 4 displacement */
9785 opcode
[1] = opcode
[0] + 0x10;
9786 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9787 where_to_put_displacement
= &opcode
[2];
9790 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9791 extension
= 3; /* 2 opcode + 2 displacement */
9792 opcode
[1] = opcode
[0] + 0x10;
9793 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9794 where_to_put_displacement
= &opcode
[2];
9797 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9802 where_to_put_displacement
= &opcode
[3];
9806 BAD_CASE (fragP
->fr_subtype
);
9811 /* If size if less then four we are sure that the operand fits,
9812 but if it's 4, then it could be that the displacement is larger
9814 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9816 && ((addressT
) (displacement_from_opcode_start
- extension
9817 + ((addressT
) 1 << 31))
9818 > (((addressT
) 2 << 31) - 1)))
9820 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9821 _("jump target out of range"));
9822 /* Make us emit 0. */
9823 displacement_from_opcode_start
= extension
;
9825 /* Now put displacement after opcode. */
9826 md_number_to_chars ((char *) where_to_put_displacement
,
9827 (valueT
) (displacement_from_opcode_start
- extension
),
9828 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9829 fragP
->fr_fix
+= extension
;
9832 /* Apply a fixup (fixP) to segment data, once it has been determined
9833 by our caller that we have all the info we need to fix it up.
9835 Parameter valP is the pointer to the value of the bits.
9837 On the 386, immediates, displacements, and data pointers are all in
9838 the same (little-endian) format, so we don't need to care about which
9842 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9844 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9845 valueT value
= *valP
;
9847 #if !defined (TE_Mach)
9850 switch (fixP
->fx_r_type
)
9856 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9859 case BFD_RELOC_X86_64_32S
:
9860 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9863 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9866 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9871 if (fixP
->fx_addsy
!= NULL
9872 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9873 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9874 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9875 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9876 && !use_rela_relocations
)
9878 /* This is a hack. There should be a better way to handle this.
9879 This covers for the fact that bfd_install_relocation will
9880 subtract the current location (for partial_inplace, PC relative
9881 relocations); see more below. */
9885 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9888 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9890 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9893 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9896 || (symbol_section_p (fixP
->fx_addsy
)
9897 && sym_seg
!= absolute_section
))
9898 && !generic_force_reloc (fixP
))
9900 /* Yes, we add the values in twice. This is because
9901 bfd_install_relocation subtracts them out again. I think
9902 bfd_install_relocation is broken, but I don't dare change
9904 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9908 #if defined (OBJ_COFF) && defined (TE_PE)
9909 /* For some reason, the PE format does not store a
9910 section address offset for a PC relative symbol. */
9911 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9912 || S_IS_WEAK (fixP
->fx_addsy
))
9913 value
+= md_pcrel_from (fixP
);
9916 #if defined (OBJ_COFF) && defined (TE_PE)
9917 if (fixP
->fx_addsy
!= NULL
9918 && S_IS_WEAK (fixP
->fx_addsy
)
9919 /* PR 16858: Do not modify weak function references. */
9920 && ! fixP
->fx_pcrel
)
9922 #if !defined (TE_PEP)
9923 /* For x86 PE weak function symbols are neither PC-relative
9924 nor do they set S_IS_FUNCTION. So the only reliable way
9925 to detect them is to check the flags of their containing
9927 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9928 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9932 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9936 /* Fix a few things - the dynamic linker expects certain values here,
9937 and we must not disappoint it. */
9938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9939 if (IS_ELF
&& fixP
->fx_addsy
)
9940 switch (fixP
->fx_r_type
)
9942 case BFD_RELOC_386_PLT32
:
9943 case BFD_RELOC_X86_64_PLT32
:
9944 /* Make the jump instruction point to the address of the operand. At
9945 runtime we merely add the offset to the actual PLT entry. */
9949 case BFD_RELOC_386_TLS_GD
:
9950 case BFD_RELOC_386_TLS_LDM
:
9951 case BFD_RELOC_386_TLS_IE_32
:
9952 case BFD_RELOC_386_TLS_IE
:
9953 case BFD_RELOC_386_TLS_GOTIE
:
9954 case BFD_RELOC_386_TLS_GOTDESC
:
9955 case BFD_RELOC_X86_64_TLSGD
:
9956 case BFD_RELOC_X86_64_TLSLD
:
9957 case BFD_RELOC_X86_64_GOTTPOFF
:
9958 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9959 value
= 0; /* Fully resolved at runtime. No addend. */
9961 case BFD_RELOC_386_TLS_LE
:
9962 case BFD_RELOC_386_TLS_LDO_32
:
9963 case BFD_RELOC_386_TLS_LE_32
:
9964 case BFD_RELOC_X86_64_DTPOFF32
:
9965 case BFD_RELOC_X86_64_DTPOFF64
:
9966 case BFD_RELOC_X86_64_TPOFF32
:
9967 case BFD_RELOC_X86_64_TPOFF64
:
9968 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9971 case BFD_RELOC_386_TLS_DESC_CALL
:
9972 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9973 value
= 0; /* Fully resolved at runtime. No addend. */
9974 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9978 case BFD_RELOC_VTABLE_INHERIT
:
9979 case BFD_RELOC_VTABLE_ENTRY
:
9986 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9988 #endif /* !defined (TE_Mach) */
9990 /* Are we finished with this relocation now? */
9991 if (fixP
->fx_addsy
== NULL
)
9993 #if defined (OBJ_COFF) && defined (TE_PE)
9994 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9997 /* Remember value for tc_gen_reloc. */
9998 fixP
->fx_addnumber
= value
;
9999 /* Clear out the frag for now. */
10003 else if (use_rela_relocations
)
10005 fixP
->fx_no_overflow
= 1;
10006 /* Remember value for tc_gen_reloc. */
10007 fixP
->fx_addnumber
= value
;
10011 md_number_to_chars (p
, value
, fixP
->fx_size
);
10015 md_atof (int type
, char *litP
, int *sizeP
)
10017 /* This outputs the LITTLENUMs in REVERSE order;
10018 in accord with the bigendian 386. */
10019 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
10022 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
10025 output_invalid (int c
)
10028 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10031 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
10032 "(0x%x)", (unsigned char) c
);
10033 return output_invalid_buf
;
10036 /* REG_STRING starts *before* REGISTER_PREFIX. */
10038 static const reg_entry
*
10039 parse_real_register (char *reg_string
, char **end_op
)
10041 char *s
= reg_string
;
10043 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
10044 const reg_entry
*r
;
10046 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10047 if (*s
== REGISTER_PREFIX
)
10050 if (is_space_char (*s
))
10053 p
= reg_name_given
;
10054 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
10056 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
10057 return (const reg_entry
*) NULL
;
10061 /* For naked regs, make sure that we are not dealing with an identifier.
10062 This prevents confusing an identifier like `eax_var' with register
10064 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
10065 return (const reg_entry
*) NULL
;
10069 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
10071 /* Handle floating point regs, allowing spaces in the (i) part. */
10072 if (r
== i386_regtab
/* %st is first entry of table */)
10074 if (is_space_char (*s
))
10079 if (is_space_char (*s
))
10081 if (*s
>= '0' && *s
<= '7')
10083 int fpr
= *s
- '0';
10085 if (is_space_char (*s
))
10090 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
10095 /* We have "%st(" then garbage. */
10096 return (const reg_entry
*) NULL
;
10100 if (r
== NULL
|| allow_pseudo_reg
)
10103 if (operand_type_all_zero (&r
->reg_type
))
10104 return (const reg_entry
*) NULL
;
10106 if ((r
->reg_type
.bitfield
.dword
10107 || r
->reg_type
.bitfield
.sreg3
10108 || r
->reg_type
.bitfield
.control
10109 || r
->reg_type
.bitfield
.debug
10110 || r
->reg_type
.bitfield
.test
)
10111 && !cpu_arch_flags
.bitfield
.cpui386
)
10112 return (const reg_entry
*) NULL
;
10114 if (r
->reg_type
.bitfield
.tbyte
10115 && !cpu_arch_flags
.bitfield
.cpu8087
10116 && !cpu_arch_flags
.bitfield
.cpu287
10117 && !cpu_arch_flags
.bitfield
.cpu387
)
10118 return (const reg_entry
*) NULL
;
10120 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpuregmmx
)
10121 return (const reg_entry
*) NULL
;
10123 if (r
->reg_type
.bitfield
.xmmword
&& !cpu_arch_flags
.bitfield
.cpuregxmm
)
10124 return (const reg_entry
*) NULL
;
10126 if (r
->reg_type
.bitfield
.ymmword
&& !cpu_arch_flags
.bitfield
.cpuregymm
)
10127 return (const reg_entry
*) NULL
;
10129 if (r
->reg_type
.bitfield
.zmmword
&& !cpu_arch_flags
.bitfield
.cpuregzmm
)
10130 return (const reg_entry
*) NULL
;
10132 if (r
->reg_type
.bitfield
.regmask
10133 && !cpu_arch_flags
.bitfield
.cpuregmask
)
10134 return (const reg_entry
*) NULL
;
10136 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10137 if (!allow_index_reg
10138 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
10139 return (const reg_entry
*) NULL
;
10141 /* Upper 16 vector register is only available with VREX in 64bit
10143 if ((r
->reg_flags
& RegVRex
))
10145 if (i
.vec_encoding
== vex_encoding_default
)
10146 i
.vec_encoding
= vex_encoding_evex
;
10148 if (!cpu_arch_flags
.bitfield
.cpuvrex
10149 || i
.vec_encoding
!= vex_encoding_evex
10150 || flag_code
!= CODE_64BIT
)
10151 return (const reg_entry
*) NULL
;
10154 if (((r
->reg_flags
& (RegRex64
| RegRex
))
10155 || r
->reg_type
.bitfield
.qword
)
10156 && (!cpu_arch_flags
.bitfield
.cpulm
10157 || !operand_type_equal (&r
->reg_type
, &control
))
10158 && flag_code
!= CODE_64BIT
)
10159 return (const reg_entry
*) NULL
;
10161 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
10162 return (const reg_entry
*) NULL
;
10167 /* REG_STRING starts *before* REGISTER_PREFIX. */
10169 static const reg_entry
*
10170 parse_register (char *reg_string
, char **end_op
)
10172 const reg_entry
*r
;
10174 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
10175 r
= parse_real_register (reg_string
, end_op
);
10180 char *save
= input_line_pointer
;
10184 input_line_pointer
= reg_string
;
10185 c
= get_symbol_name (®_string
);
10186 symbolP
= symbol_find (reg_string
);
10187 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
10189 const expressionS
*e
= symbol_get_value_expression (symbolP
);
10191 know (e
->X_op
== O_register
);
10192 know (e
->X_add_number
>= 0
10193 && (valueT
) e
->X_add_number
< i386_regtab_size
);
10194 r
= i386_regtab
+ e
->X_add_number
;
10195 if ((r
->reg_flags
& RegVRex
))
10196 i
.vec_encoding
= vex_encoding_evex
;
10197 *end_op
= input_line_pointer
;
10199 *input_line_pointer
= c
;
10200 input_line_pointer
= save
;
10206 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
10208 const reg_entry
*r
;
10209 char *end
= input_line_pointer
;
10212 r
= parse_register (name
, &input_line_pointer
);
10213 if (r
&& end
<= input_line_pointer
)
10215 *nextcharP
= *input_line_pointer
;
10216 *input_line_pointer
= 0;
10217 e
->X_op
= O_register
;
10218 e
->X_add_number
= r
- i386_regtab
;
10221 input_line_pointer
= end
;
10223 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
10227 md_operand (expressionS
*e
)
10230 const reg_entry
*r
;
10232 switch (*input_line_pointer
)
10234 case REGISTER_PREFIX
:
10235 r
= parse_real_register (input_line_pointer
, &end
);
10238 e
->X_op
= O_register
;
10239 e
->X_add_number
= r
- i386_regtab
;
10240 input_line_pointer
= end
;
10245 gas_assert (intel_syntax
);
10246 end
= input_line_pointer
++;
10248 if (*input_line_pointer
== ']')
10250 ++input_line_pointer
;
10251 e
->X_op_symbol
= make_expr_symbol (e
);
10252 e
->X_add_symbol
= NULL
;
10253 e
->X_add_number
= 0;
10258 e
->X_op
= O_absent
;
10259 input_line_pointer
= end
;
10266 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10267 const char *md_shortopts
= "kVQ:sqnO::";
10269 const char *md_shortopts
= "qnO::";
10272 #define OPTION_32 (OPTION_MD_BASE + 0)
10273 #define OPTION_64 (OPTION_MD_BASE + 1)
10274 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10275 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10276 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10277 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10278 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10279 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10280 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10281 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10282 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10283 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10284 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10285 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10286 #define OPTION_X32 (OPTION_MD_BASE + 14)
10287 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10288 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10289 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10290 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10291 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10292 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10293 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10294 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10295 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10296 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10297 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10299 struct option md_longopts
[] =
10301 {"32", no_argument
, NULL
, OPTION_32
},
10302 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10303 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10304 {"64", no_argument
, NULL
, OPTION_64
},
10306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10307 {"x32", no_argument
, NULL
, OPTION_X32
},
10308 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10310 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
10311 {"march", required_argument
, NULL
, OPTION_MARCH
},
10312 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10313 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
10314 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
10315 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
10316 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
10317 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
10318 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
10319 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
10320 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
10321 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
10322 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
10323 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
10324 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
10325 # if defined (TE_PE) || defined (TE_PEP)
10326 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
10328 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
10329 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
10330 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
10331 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
10332 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
10333 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
10334 {NULL
, no_argument
, NULL
, 0}
10336 size_t md_longopts_size
= sizeof (md_longopts
);
10339 md_parse_option (int c
, const char *arg
)
10342 char *arch
, *next
, *saved
;
10347 optimize_align_code
= 0;
10351 quiet_warnings
= 1;
10354 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10355 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10356 should be emitted or not. FIXME: Not implemented. */
10360 /* -V: SVR4 argument to print version ID. */
10362 print_version_id ();
10365 /* -k: Ignore for FreeBSD compatibility. */
10370 /* -s: On i386 Solaris, this tells the native assembler to use
10371 .stab instead of .stab.excl. We always use .stab anyhow. */
10374 case OPTION_MSHARED
:
10378 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10379 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10382 const char **list
, **l
;
10384 list
= bfd_target_list ();
10385 for (l
= list
; *l
!= NULL
; l
++)
10386 if (CONST_STRNEQ (*l
, "elf64-x86-64")
10387 || strcmp (*l
, "coff-x86-64") == 0
10388 || strcmp (*l
, "pe-x86-64") == 0
10389 || strcmp (*l
, "pei-x86-64") == 0
10390 || strcmp (*l
, "mach-o-x86-64") == 0)
10392 default_arch
= "x86_64";
10396 as_fatal (_("no compiled in support for x86_64"));
10402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10406 const char **list
, **l
;
10408 list
= bfd_target_list ();
10409 for (l
= list
; *l
!= NULL
; l
++)
10410 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
10412 default_arch
= "x86_64:32";
10416 as_fatal (_("no compiled in support for 32bit x86_64"));
10420 as_fatal (_("32bit x86_64 is only supported for ELF"));
10425 default_arch
= "i386";
10428 case OPTION_DIVIDE
:
10429 #ifdef SVR4_COMMENT_CHARS
10434 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
10436 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
10440 i386_comment_chars
= n
;
10446 saved
= xstrdup (arg
);
10448 /* Allow -march=+nosse. */
10454 as_fatal (_("invalid -march= option: `%s'"), arg
);
10455 next
= strchr (arch
, '+');
10458 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10460 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
10463 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10466 cpu_arch_name
= cpu_arch
[j
].name
;
10467 cpu_sub_arch_name
= NULL
;
10468 cpu_arch_flags
= cpu_arch
[j
].flags
;
10469 cpu_arch_isa
= cpu_arch
[j
].type
;
10470 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
10471 if (!cpu_arch_tune_set
)
10473 cpu_arch_tune
= cpu_arch_isa
;
10474 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10478 else if (*cpu_arch
[j
].name
== '.'
10479 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
10481 /* ISA extension. */
10482 i386_cpu_flags flags
;
10484 flags
= cpu_flags_or (cpu_arch_flags
,
10485 cpu_arch
[j
].flags
);
10487 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10489 if (cpu_sub_arch_name
)
10491 char *name
= cpu_sub_arch_name
;
10492 cpu_sub_arch_name
= concat (name
,
10494 (const char *) NULL
);
10498 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
10499 cpu_arch_flags
= flags
;
10500 cpu_arch_isa_flags
= flags
;
10506 if (j
>= ARRAY_SIZE (cpu_arch
))
10508 /* Disable an ISA extension. */
10509 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10510 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
10512 i386_cpu_flags flags
;
10514 flags
= cpu_flags_and_not (cpu_arch_flags
,
10515 cpu_noarch
[j
].flags
);
10516 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
10518 if (cpu_sub_arch_name
)
10520 char *name
= cpu_sub_arch_name
;
10521 cpu_sub_arch_name
= concat (arch
,
10522 (const char *) NULL
);
10526 cpu_sub_arch_name
= xstrdup (arch
);
10527 cpu_arch_flags
= flags
;
10528 cpu_arch_isa_flags
= flags
;
10533 if (j
>= ARRAY_SIZE (cpu_noarch
))
10534 j
= ARRAY_SIZE (cpu_arch
);
10537 if (j
>= ARRAY_SIZE (cpu_arch
))
10538 as_fatal (_("invalid -march= option: `%s'"), arg
);
10542 while (next
!= NULL
);
10548 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10549 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10551 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
10553 cpu_arch_tune_set
= 1;
10554 cpu_arch_tune
= cpu_arch
[j
].type
;
10555 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
10559 if (j
>= ARRAY_SIZE (cpu_arch
))
10560 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
10563 case OPTION_MMNEMONIC
:
10564 if (strcasecmp (arg
, "att") == 0)
10565 intel_mnemonic
= 0;
10566 else if (strcasecmp (arg
, "intel") == 0)
10567 intel_mnemonic
= 1;
10569 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
10572 case OPTION_MSYNTAX
:
10573 if (strcasecmp (arg
, "att") == 0)
10575 else if (strcasecmp (arg
, "intel") == 0)
10578 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10581 case OPTION_MINDEX_REG
:
10582 allow_index_reg
= 1;
10585 case OPTION_MNAKED_REG
:
10586 allow_naked_reg
= 1;
10589 case OPTION_MOLD_GCC
:
10593 case OPTION_MSSE2AVX
:
10597 case OPTION_MSSE_CHECK
:
10598 if (strcasecmp (arg
, "error") == 0)
10599 sse_check
= check_error
;
10600 else if (strcasecmp (arg
, "warning") == 0)
10601 sse_check
= check_warning
;
10602 else if (strcasecmp (arg
, "none") == 0)
10603 sse_check
= check_none
;
10605 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10608 case OPTION_MOPERAND_CHECK
:
10609 if (strcasecmp (arg
, "error") == 0)
10610 operand_check
= check_error
;
10611 else if (strcasecmp (arg
, "warning") == 0)
10612 operand_check
= check_warning
;
10613 else if (strcasecmp (arg
, "none") == 0)
10614 operand_check
= check_none
;
10616 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10619 case OPTION_MAVXSCALAR
:
10620 if (strcasecmp (arg
, "128") == 0)
10621 avxscalar
= vex128
;
10622 else if (strcasecmp (arg
, "256") == 0)
10623 avxscalar
= vex256
;
10625 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10628 case OPTION_MADD_BND_PREFIX
:
10629 add_bnd_prefix
= 1;
10632 case OPTION_MEVEXLIG
:
10633 if (strcmp (arg
, "128") == 0)
10634 evexlig
= evexl128
;
10635 else if (strcmp (arg
, "256") == 0)
10636 evexlig
= evexl256
;
10637 else if (strcmp (arg
, "512") == 0)
10638 evexlig
= evexl512
;
10640 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10643 case OPTION_MEVEXRCIG
:
10644 if (strcmp (arg
, "rne") == 0)
10646 else if (strcmp (arg
, "rd") == 0)
10648 else if (strcmp (arg
, "ru") == 0)
10650 else if (strcmp (arg
, "rz") == 0)
10653 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10656 case OPTION_MEVEXWIG
:
10657 if (strcmp (arg
, "0") == 0)
10659 else if (strcmp (arg
, "1") == 0)
10662 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10665 # if defined (TE_PE) || defined (TE_PEP)
10666 case OPTION_MBIG_OBJ
:
10671 case OPTION_MOMIT_LOCK_PREFIX
:
10672 if (strcasecmp (arg
, "yes") == 0)
10673 omit_lock_prefix
= 1;
10674 else if (strcasecmp (arg
, "no") == 0)
10675 omit_lock_prefix
= 0;
10677 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10680 case OPTION_MFENCE_AS_LOCK_ADD
:
10681 if (strcasecmp (arg
, "yes") == 0)
10683 else if (strcasecmp (arg
, "no") == 0)
10686 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10689 case OPTION_MRELAX_RELOCATIONS
:
10690 if (strcasecmp (arg
, "yes") == 0)
10691 generate_relax_relocations
= 1;
10692 else if (strcasecmp (arg
, "no") == 0)
10693 generate_relax_relocations
= 0;
10695 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10698 case OPTION_MAMD64
:
10702 case OPTION_MINTEL64
:
10710 /* Turn off -Os. */
10711 optimize_for_space
= 0;
10713 else if (*arg
== 's')
10715 optimize_for_space
= 1;
10716 /* Turn on all encoding optimizations. */
10721 optimize
= atoi (arg
);
10722 /* Turn off -Os. */
10723 optimize_for_space
= 0;
10733 #define MESSAGE_TEMPLATE \
10737 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10738 int *left_p
, const char *name
, int len
)
10740 int size
= sizeof (MESSAGE_TEMPLATE
);
10741 int left
= *left_p
;
10743 /* Reserve 2 spaces for ", " or ",\0" */
10746 /* Check if there is any room. */
10754 p
= mempcpy (p
, name
, len
);
10758 /* Output the current message now and start a new one. */
10761 fprintf (stream
, "%s\n", message
);
10763 left
= size
- (start
- message
) - len
- 2;
10765 gas_assert (left
>= 0);
10767 p
= mempcpy (p
, name
, len
);
10775 show_arch (FILE *stream
, int ext
, int check
)
10777 static char message
[] = MESSAGE_TEMPLATE
;
10778 char *start
= message
+ 27;
10780 int size
= sizeof (MESSAGE_TEMPLATE
);
10787 left
= size
- (start
- message
);
10788 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10790 /* Should it be skipped? */
10791 if (cpu_arch
[j
].skip
)
10794 name
= cpu_arch
[j
].name
;
10795 len
= cpu_arch
[j
].len
;
10798 /* It is an extension. Skip if we aren't asked to show it. */
10809 /* It is an processor. Skip if we show only extension. */
10812 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10814 /* It is an impossible processor - skip. */
10818 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10821 /* Display disabled extensions. */
10823 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10825 name
= cpu_noarch
[j
].name
;
10826 len
= cpu_noarch
[j
].len
;
10827 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10832 fprintf (stream
, "%s\n", message
);
10836 md_show_usage (FILE *stream
)
10838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10839 fprintf (stream
, _("\
10841 -V print assembler version number\n\
10844 fprintf (stream
, _("\
10845 -n Do not optimize code alignment\n\
10846 -q quieten some warnings\n"));
10847 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10848 fprintf (stream
, _("\
10851 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10852 || defined (TE_PE) || defined (TE_PEP))
10853 fprintf (stream
, _("\
10854 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10856 #ifdef SVR4_COMMENT_CHARS
10857 fprintf (stream
, _("\
10858 --divide do not treat `/' as a comment character\n"));
10860 fprintf (stream
, _("\
10861 --divide ignored\n"));
10863 fprintf (stream
, _("\
10864 -march=CPU[,+EXTENSION...]\n\
10865 generate code for CPU and EXTENSION, CPU is one of:\n"));
10866 show_arch (stream
, 0, 1);
10867 fprintf (stream
, _("\
10868 EXTENSION is combination of:\n"));
10869 show_arch (stream
, 1, 0);
10870 fprintf (stream
, _("\
10871 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10872 show_arch (stream
, 0, 0);
10873 fprintf (stream
, _("\
10874 -msse2avx encode SSE instructions with VEX prefix\n"));
10875 fprintf (stream
, _("\
10876 -msse-check=[none|error|warning]\n\
10877 check SSE instructions\n"));
10878 fprintf (stream
, _("\
10879 -moperand-check=[none|error|warning]\n\
10880 check operand combinations for validity\n"));
10881 fprintf (stream
, _("\
10882 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10884 fprintf (stream
, _("\
10885 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10887 fprintf (stream
, _("\
10888 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10889 for EVEX.W bit ignored instructions\n"));
10890 fprintf (stream
, _("\
10891 -mevexrcig=[rne|rd|ru|rz]\n\
10892 encode EVEX instructions with specific EVEX.RC value\n\
10893 for SAE-only ignored instructions\n"));
10894 fprintf (stream
, _("\
10895 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10896 fprintf (stream
, _("\
10897 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10898 fprintf (stream
, _("\
10899 -mindex-reg support pseudo index registers\n"));
10900 fprintf (stream
, _("\
10901 -mnaked-reg don't require `%%' prefix for registers\n"));
10902 fprintf (stream
, _("\
10903 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10904 fprintf (stream
, _("\
10905 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10906 fprintf (stream
, _("\
10907 -mshared disable branch optimization for shared code\n"));
10908 # if defined (TE_PE) || defined (TE_PEP)
10909 fprintf (stream
, _("\
10910 -mbig-obj generate big object files\n"));
10912 fprintf (stream
, _("\
10913 -momit-lock-prefix=[no|yes]\n\
10914 strip all lock prefixes\n"));
10915 fprintf (stream
, _("\
10916 -mfence-as-lock-add=[no|yes]\n\
10917 encode lfence, mfence and sfence as\n\
10918 lock addl $0x0, (%%{re}sp)\n"));
10919 fprintf (stream
, _("\
10920 -mrelax-relocations=[no|yes]\n\
10921 generate relax relocations\n"));
10922 fprintf (stream
, _("\
10923 -mamd64 accept only AMD64 ISA\n"));
10924 fprintf (stream
, _("\
10925 -mintel64 accept only Intel64 ISA\n"));
10928 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10929 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10930 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10932 /* Pick the target format to use. */
10935 i386_target_format (void)
10937 if (!strncmp (default_arch
, "x86_64", 6))
10939 update_code_flag (CODE_64BIT
, 1);
10940 if (default_arch
[6] == '\0')
10941 x86_elf_abi
= X86_64_ABI
;
10943 x86_elf_abi
= X86_64_X32_ABI
;
10945 else if (!strcmp (default_arch
, "i386"))
10946 update_code_flag (CODE_32BIT
, 1);
10947 else if (!strcmp (default_arch
, "iamcu"))
10949 update_code_flag (CODE_32BIT
, 1);
10950 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10952 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10953 cpu_arch_name
= "iamcu";
10954 cpu_sub_arch_name
= NULL
;
10955 cpu_arch_flags
= iamcu_flags
;
10956 cpu_arch_isa
= PROCESSOR_IAMCU
;
10957 cpu_arch_isa_flags
= iamcu_flags
;
10958 if (!cpu_arch_tune_set
)
10960 cpu_arch_tune
= cpu_arch_isa
;
10961 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10964 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
10965 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10969 as_fatal (_("unknown architecture"));
10971 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10972 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10973 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10974 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10976 switch (OUTPUT_FLAVOR
)
10978 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10979 case bfd_target_aout_flavour
:
10980 return AOUT_TARGET_FORMAT
;
10982 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10983 # if defined (TE_PE) || defined (TE_PEP)
10984 case bfd_target_coff_flavour
:
10985 if (flag_code
== CODE_64BIT
)
10986 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10989 # elif defined (TE_GO32)
10990 case bfd_target_coff_flavour
:
10991 return "coff-go32";
10993 case bfd_target_coff_flavour
:
10994 return "coff-i386";
10997 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10998 case bfd_target_elf_flavour
:
11000 const char *format
;
11002 switch (x86_elf_abi
)
11005 format
= ELF_TARGET_FORMAT
;
11008 use_rela_relocations
= 1;
11010 format
= ELF_TARGET_FORMAT64
;
11012 case X86_64_X32_ABI
:
11013 use_rela_relocations
= 1;
11015 disallow_64bit_reloc
= 1;
11016 format
= ELF_TARGET_FORMAT32
;
11019 if (cpu_arch_isa
== PROCESSOR_L1OM
)
11021 if (x86_elf_abi
!= X86_64_ABI
)
11022 as_fatal (_("Intel L1OM is 64bit only"));
11023 return ELF_TARGET_L1OM_FORMAT
;
11025 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
11027 if (x86_elf_abi
!= X86_64_ABI
)
11028 as_fatal (_("Intel K1OM is 64bit only"));
11029 return ELF_TARGET_K1OM_FORMAT
;
11031 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
11033 if (x86_elf_abi
!= I386_ABI
)
11034 as_fatal (_("Intel MCU is 32bit only"));
11035 return ELF_TARGET_IAMCU_FORMAT
;
11041 #if defined (OBJ_MACH_O)
11042 case bfd_target_mach_o_flavour
:
11043 if (flag_code
== CODE_64BIT
)
11045 use_rela_relocations
= 1;
11047 return "mach-o-x86-64";
11050 return "mach-o-i386";
11058 #endif /* OBJ_MAYBE_ more than one */
11061 md_undefined_symbol (char *name
)
11063 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
11064 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
11065 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
11066 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
11070 if (symbol_find (name
))
11071 as_bad (_("GOT already in symbol table"));
11072 GOT_symbol
= symbol_new (name
, undefined_section
,
11073 (valueT
) 0, &zero_address_frag
);
11080 /* Round up a section size to the appropriate boundary. */
11083 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
11085 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11086 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
11088 /* For a.out, force the section size to be aligned. If we don't do
11089 this, BFD will align it for us, but it will not write out the
11090 final bytes of the section. This may be a bug in BFD, but it is
11091 easier to fix it here since that is how the other a.out targets
11095 align
= bfd_get_section_alignment (stdoutput
, segment
);
11096 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
11103 /* On the i386, PC-relative offsets are relative to the start of the
11104 next instruction. That is, the address of the offset, plus its
11105 size, since the offset is always the last part of the insn. */
11108 md_pcrel_from (fixS
*fixP
)
11110 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11116 s_bss (int ignore ATTRIBUTE_UNUSED
)
11120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11122 obj_elf_section_change_hook ();
11124 temp
= get_absolute_expression ();
11125 subseg_set (bss_section
, (subsegT
) temp
);
11126 demand_empty_rest_of_line ();
11132 i386_validate_fix (fixS
*fixp
)
11134 if (fixp
->fx_subsy
)
11136 if (fixp
->fx_subsy
== GOT_symbol
)
11138 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
11142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11143 if (fixp
->fx_tcbit2
)
11144 fixp
->fx_r_type
= (fixp
->fx_tcbit
11145 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11146 : BFD_RELOC_X86_64_GOTPCRELX
);
11149 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
11154 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
11156 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
11158 fixp
->fx_subsy
= 0;
11161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11162 else if (!object_64bit
)
11164 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
11165 && fixp
->fx_tcbit2
)
11166 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
11172 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
11175 bfd_reloc_code_real_type code
;
11177 switch (fixp
->fx_r_type
)
11179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11180 case BFD_RELOC_SIZE32
:
11181 case BFD_RELOC_SIZE64
:
11182 if (S_IS_DEFINED (fixp
->fx_addsy
)
11183 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
11185 /* Resolve size relocation against local symbol to size of
11186 the symbol plus addend. */
11187 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
11188 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
11189 && !fits_in_unsigned_long (value
))
11190 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11191 _("symbol size computation overflow"));
11192 fixp
->fx_addsy
= NULL
;
11193 fixp
->fx_subsy
= NULL
;
11194 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
11198 /* Fall through. */
11200 case BFD_RELOC_X86_64_PLT32
:
11201 case BFD_RELOC_X86_64_GOT32
:
11202 case BFD_RELOC_X86_64_GOTPCREL
:
11203 case BFD_RELOC_X86_64_GOTPCRELX
:
11204 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11205 case BFD_RELOC_386_PLT32
:
11206 case BFD_RELOC_386_GOT32
:
11207 case BFD_RELOC_386_GOT32X
:
11208 case BFD_RELOC_386_GOTOFF
:
11209 case BFD_RELOC_386_GOTPC
:
11210 case BFD_RELOC_386_TLS_GD
:
11211 case BFD_RELOC_386_TLS_LDM
:
11212 case BFD_RELOC_386_TLS_LDO_32
:
11213 case BFD_RELOC_386_TLS_IE_32
:
11214 case BFD_RELOC_386_TLS_IE
:
11215 case BFD_RELOC_386_TLS_GOTIE
:
11216 case BFD_RELOC_386_TLS_LE_32
:
11217 case BFD_RELOC_386_TLS_LE
:
11218 case BFD_RELOC_386_TLS_GOTDESC
:
11219 case BFD_RELOC_386_TLS_DESC_CALL
:
11220 case BFD_RELOC_X86_64_TLSGD
:
11221 case BFD_RELOC_X86_64_TLSLD
:
11222 case BFD_RELOC_X86_64_DTPOFF32
:
11223 case BFD_RELOC_X86_64_DTPOFF64
:
11224 case BFD_RELOC_X86_64_GOTTPOFF
:
11225 case BFD_RELOC_X86_64_TPOFF32
:
11226 case BFD_RELOC_X86_64_TPOFF64
:
11227 case BFD_RELOC_X86_64_GOTOFF64
:
11228 case BFD_RELOC_X86_64_GOTPC32
:
11229 case BFD_RELOC_X86_64_GOT64
:
11230 case BFD_RELOC_X86_64_GOTPCREL64
:
11231 case BFD_RELOC_X86_64_GOTPC64
:
11232 case BFD_RELOC_X86_64_GOTPLT64
:
11233 case BFD_RELOC_X86_64_PLTOFF64
:
11234 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11235 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11236 case BFD_RELOC_RVA
:
11237 case BFD_RELOC_VTABLE_ENTRY
:
11238 case BFD_RELOC_VTABLE_INHERIT
:
11240 case BFD_RELOC_32_SECREL
:
11242 code
= fixp
->fx_r_type
;
11244 case BFD_RELOC_X86_64_32S
:
11245 if (!fixp
->fx_pcrel
)
11247 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11248 code
= fixp
->fx_r_type
;
11251 /* Fall through. */
11253 if (fixp
->fx_pcrel
)
11255 switch (fixp
->fx_size
)
11258 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11259 _("can not do %d byte pc-relative relocation"),
11261 code
= BFD_RELOC_32_PCREL
;
11263 case 1: code
= BFD_RELOC_8_PCREL
; break;
11264 case 2: code
= BFD_RELOC_16_PCREL
; break;
11265 case 4: code
= BFD_RELOC_32_PCREL
; break;
11267 case 8: code
= BFD_RELOC_64_PCREL
; break;
11273 switch (fixp
->fx_size
)
11276 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11277 _("can not do %d byte relocation"),
11279 code
= BFD_RELOC_32
;
11281 case 1: code
= BFD_RELOC_8
; break;
11282 case 2: code
= BFD_RELOC_16
; break;
11283 case 4: code
= BFD_RELOC_32
; break;
11285 case 8: code
= BFD_RELOC_64
; break;
11292 if ((code
== BFD_RELOC_32
11293 || code
== BFD_RELOC_32_PCREL
11294 || code
== BFD_RELOC_X86_64_32S
)
11296 && fixp
->fx_addsy
== GOT_symbol
)
11299 code
= BFD_RELOC_386_GOTPC
;
11301 code
= BFD_RELOC_X86_64_GOTPC32
;
11303 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
11305 && fixp
->fx_addsy
== GOT_symbol
)
11307 code
= BFD_RELOC_X86_64_GOTPC64
;
11310 rel
= XNEW (arelent
);
11311 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
11312 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11314 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11316 if (!use_rela_relocations
)
11318 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11319 vtable entry to be used in the relocation's section offset. */
11320 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11321 rel
->address
= fixp
->fx_offset
;
11322 #if defined (OBJ_COFF) && defined (TE_PE)
11323 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
11324 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
11329 /* Use the rela in 64bit mode. */
11332 if (disallow_64bit_reloc
)
11335 case BFD_RELOC_X86_64_DTPOFF64
:
11336 case BFD_RELOC_X86_64_TPOFF64
:
11337 case BFD_RELOC_64_PCREL
:
11338 case BFD_RELOC_X86_64_GOTOFF64
:
11339 case BFD_RELOC_X86_64_GOT64
:
11340 case BFD_RELOC_X86_64_GOTPCREL64
:
11341 case BFD_RELOC_X86_64_GOTPC64
:
11342 case BFD_RELOC_X86_64_GOTPLT64
:
11343 case BFD_RELOC_X86_64_PLTOFF64
:
11344 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11345 _("cannot represent relocation type %s in x32 mode"),
11346 bfd_get_reloc_code_name (code
));
11352 if (!fixp
->fx_pcrel
)
11353 rel
->addend
= fixp
->fx_offset
;
11357 case BFD_RELOC_X86_64_PLT32
:
11358 case BFD_RELOC_X86_64_GOT32
:
11359 case BFD_RELOC_X86_64_GOTPCREL
:
11360 case BFD_RELOC_X86_64_GOTPCRELX
:
11361 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
11362 case BFD_RELOC_X86_64_TLSGD
:
11363 case BFD_RELOC_X86_64_TLSLD
:
11364 case BFD_RELOC_X86_64_GOTTPOFF
:
11365 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11366 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11367 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
11370 rel
->addend
= (section
->vma
11372 + fixp
->fx_addnumber
11373 + md_pcrel_from (fixp
));
11378 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11379 if (rel
->howto
== NULL
)
11381 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11382 _("cannot represent relocation type %s"),
11383 bfd_get_reloc_code_name (code
));
11384 /* Set howto to a garbage value so that we can keep going. */
11385 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
11386 gas_assert (rel
->howto
!= NULL
);
11392 #include "tc-i386-intel.c"
11395 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
11397 int saved_naked_reg
;
11398 char saved_register_dot
;
11400 saved_naked_reg
= allow_naked_reg
;
11401 allow_naked_reg
= 1;
11402 saved_register_dot
= register_chars
['.'];
11403 register_chars
['.'] = '.';
11404 allow_pseudo_reg
= 1;
11405 expression_and_evaluate (exp
);
11406 allow_pseudo_reg
= 0;
11407 register_chars
['.'] = saved_register_dot
;
11408 allow_naked_reg
= saved_naked_reg
;
11410 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
11412 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
11414 exp
->X_op
= O_constant
;
11415 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
11416 .dw2_regnum
[flag_code
>> 1];
11419 exp
->X_op
= O_illegal
;
11424 tc_x86_frame_initial_instructions (void)
11426 static unsigned int sp_regno
[2];
11428 if (!sp_regno
[flag_code
>> 1])
11430 char *saved_input
= input_line_pointer
;
11431 char sp
[][4] = {"esp", "rsp"};
11434 input_line_pointer
= sp
[flag_code
>> 1];
11435 tc_x86_parse_to_dw2regnum (&exp
);
11436 gas_assert (exp
.X_op
== O_constant
);
11437 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
11438 input_line_pointer
= saved_input
;
11441 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
11442 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
11446 x86_dwarf2_addr_size (void)
11448 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11449 if (x86_elf_abi
== X86_64_X32_ABI
)
11452 return bfd_arch_bits_per_address (stdoutput
) / 8;
11456 i386_elf_section_type (const char *str
, size_t len
)
11458 if (flag_code
== CODE_64BIT
11459 && len
== sizeof ("unwind") - 1
11460 && strncmp (str
, "unwind", 6) == 0)
11461 return SHT_X86_64_UNWIND
;
11468 i386_solaris_fix_up_eh_frame (segT sec
)
11470 if (flag_code
== CODE_64BIT
)
11471 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
11477 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
11481 exp
.X_op
= O_secrel
;
11482 exp
.X_add_symbol
= symbol
;
11483 exp
.X_add_number
= 0;
11484 emit_expr (&exp
, size
);
11488 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11489 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11492 x86_64_section_letter (int letter
, const char **ptr_msg
)
11494 if (flag_code
== CODE_64BIT
)
11497 return SHF_X86_64_LARGE
;
11499 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11502 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
11507 x86_64_section_word (char *str
, size_t len
)
11509 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
11510 return SHF_X86_64_LARGE
;
11516 handle_large_common (int small ATTRIBUTE_UNUSED
)
11518 if (flag_code
!= CODE_64BIT
)
11520 s_comm_internal (0, elf_common_parse
);
11521 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11525 static segT lbss_section
;
11526 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
11527 asection
*saved_bss_section
= bss_section
;
11529 if (lbss_section
== NULL
)
11531 flagword applicable
;
11532 segT seg
= now_seg
;
11533 subsegT subseg
= now_subseg
;
11535 /* The .lbss section is for local .largecomm symbols. */
11536 lbss_section
= subseg_new (".lbss", 0);
11537 applicable
= bfd_applicable_section_flags (stdoutput
);
11538 bfd_set_section_flags (stdoutput
, lbss_section
,
11539 applicable
& SEC_ALLOC
);
11540 seg_info (lbss_section
)->bss
= 1;
11542 subseg_set (seg
, subseg
);
11545 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
11546 bss_section
= lbss_section
;
11548 s_comm_internal (0, elf_common_parse
);
11550 elf_com_section_ptr
= saved_com_section_ptr
;
11551 bss_section
= saved_bss_section
;
11554 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */