1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
114 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
115 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
118 static const char *default_arch
= DEFAULT_ARCH
;
120 /* 'md_assemble ()' gathers together information and puts it into a
127 const reg_entry
*regs
;
132 /* TM holds the template for the insn were currently assembling. */
135 /* SUFFIX holds the instruction mnemonic suffix if given.
136 (e.g. 'l' for 'movl') */
139 /* OPERANDS gives the number of given operands. */
140 unsigned int operands
;
142 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
143 of given register, displacement, memory operands and immediate
145 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
147 /* TYPES [i] is the type (see above #defines) which tells us how to
148 use OP[i] for the corresponding operand. */
149 unsigned int types
[MAX_OPERANDS
];
151 /* Displacement expression, immediate expression, or register for each
153 union i386_op op
[MAX_OPERANDS
];
155 /* Flags for operands. */
156 unsigned int flags
[MAX_OPERANDS
];
157 #define Operand_PCrel 1
159 /* Relocation type for operand */
160 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
162 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
163 the base index byte below. */
164 const reg_entry
*base_reg
;
165 const reg_entry
*index_reg
;
166 unsigned int log2_scale_factor
;
168 /* SEG gives the seg_entries of this insn. They are zero unless
169 explicit segment overrides are given. */
170 const seg_entry
*seg
[2];
172 /* PREFIX holds all the given prefix opcodes (usually null).
173 PREFIXES is the number of prefix opcodes. */
174 unsigned int prefixes
;
175 unsigned char prefix
[MAX_PREFIXES
];
177 /* RM and SIB are the modrm byte and the sib byte where the
178 addressing modes of this insn are encoded. */
185 typedef struct _i386_insn i386_insn
;
187 /* List of chars besides those in app.c:symbol_chars that can start an
188 operand. Used to prevent the scrubber eating vital white-space. */
189 const char extra_symbol_chars
[] = "*%-(["
198 #if (defined (TE_I386AIX) \
199 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
200 && !defined (TE_LINUX) \
201 && !defined (TE_NETWARE) \
202 && !defined (TE_FreeBSD) \
203 && !defined (TE_NetBSD)))
204 /* This array holds the chars that always start a comment. If the
205 pre-processor is disabled, these aren't very useful. */
206 const char comment_chars
[] = "#/";
207 #define PREFIX_SEPARATOR '\\'
209 /* This array holds the chars that only start a comment at the beginning of
210 a line. If the line seems to have the form '# 123 filename'
211 .line and .file directives will appear in the pre-processed output.
212 Note that input_file.c hand checks for '#' at the beginning of the
213 first line of the input file. This is because the compiler outputs
214 #NO_APP at the beginning of its output.
215 Also note that comments started like this one will always work if
216 '/' isn't otherwise defined. */
217 const char line_comment_chars
[] = "#";
220 /* Putting '/' here makes it impossible to use the divide operator.
221 However, we need it for compatibility with SVR4 systems. */
222 const char comment_chars
[] = "#";
223 #define PREFIX_SEPARATOR '/'
225 const char line_comment_chars
[] = "/#";
228 const char line_separator_chars
[] = ";";
230 /* Chars that can be used to separate mant from exp in floating point
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant
237 const char FLT_CHARS
[] = "fFdDxX";
239 /* Tables for lexical analysis. */
240 static char mnemonic_chars
[256];
241 static char register_chars
[256];
242 static char operand_chars
[256];
243 static char identifier_chars
[256];
244 static char digit_chars
[256];
246 /* Lexical macros. */
247 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248 #define is_operand_char(x) (operand_chars[(unsigned char) x])
249 #define is_register_char(x) (register_chars[(unsigned char) x])
250 #define is_space_char(x) ((x) == ' ')
251 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252 #define is_digit_char(x) (digit_chars[(unsigned char) x])
254 /* All non-digit non-letter characters that may occur in an operand. */
255 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
257 /* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
260 assembler instruction). */
261 static char save_stack
[32];
262 static char *save_stack_p
;
263 #define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265 #define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
268 /* The instruction we're assembling. */
271 /* Possible templates for current insn. */
272 static const templates
*current_templates
;
274 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
275 static expressionS disp_expressions
[2], im_expressions
[2];
277 /* Current operand we are working on. */
278 static int this_operand
;
280 /* We support four different modes. FLAG_CODE variable is used to distinguish
287 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
289 static enum flag_code flag_code
;
290 static int use_rela_relocations
= 0;
292 /* The names used to print error messages. */
293 static const char *flag_code_names
[] =
300 /* 1 for intel syntax,
302 static int intel_syntax
= 0;
304 /* 1 if register prefix % not required. */
305 static int allow_naked_reg
= 0;
307 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
308 leave, push, and pop instructions so that gcc has the same stack
309 frame as in 32 bit mode. */
310 static char stackop_size
= '\0';
312 /* Non-zero to optimize code alignment. */
313 int optimize_align_code
= 1;
315 /* Non-zero to quieten some warnings. */
316 static int quiet_warnings
= 0;
319 static const char *cpu_arch_name
= NULL
;
320 static const char *cpu_sub_arch_name
= NULL
;
322 /* CPU feature flags. */
323 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
325 /* If set, conditional jumps are not automatically promoted to handle
326 larger than a byte offset. */
327 static unsigned int no_cond_jump_promotion
= 0;
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
330 static symbolS
*GOT_symbol
;
332 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
333 unsigned int x86_dwarf2_return_column
;
335 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
336 int x86_cie_data_alignment
;
338 /* Interface to relax_segment.
339 There are 3 major relax states for 386 jump insns because the
340 different types of jumps add different sizes to frags when we're
341 figuring out what sort of jump to choose to reach a given label. */
344 #define UNCOND_JUMP 0
346 #define COND_JUMP86 2
351 #define SMALL16 (SMALL | CODE16)
353 #define BIG16 (BIG | CODE16)
357 #define INLINE __inline__
363 #define ENCODE_RELAX_STATE(type, size) \
364 ((relax_substateT) (((type) << 2) | (size)))
365 #define TYPE_FROM_RELAX_STATE(s) \
367 #define DISP_SIZE_FROM_RELAX_STATE(s) \
368 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
370 /* This table is used by relax_frag to promote short jumps to long
371 ones where necessary. SMALL (short) jumps may be promoted to BIG
372 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
373 don't allow a short jump in a 32 bit code segment to be promoted to
374 a 16 bit offset jump because it's slower (requires data size
375 prefix), and doesn't work, unless the destination is in the bottom
376 64k of the code segment (The top 16 bits of eip are zeroed). */
378 const relax_typeS md_relax_table
[] =
381 1) most positive reach of this state,
382 2) most negative reach of this state,
383 3) how many bytes this mode will have in the variable part of the frag
384 4) which index into the table to try if we can't fit into this one. */
386 /* UNCOND_JUMP states. */
387 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
389 /* dword jmp adds 4 bytes to frag:
390 0 extra opcode bytes, 4 displacement bytes. */
392 /* word jmp adds 2 byte2 to frag:
393 0 extra opcode bytes, 2 displacement bytes. */
396 /* COND_JUMP states. */
397 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
399 /* dword conditionals adds 5 bytes to frag:
400 1 extra opcode byte, 4 displacement bytes. */
402 /* word conditionals add 3 bytes to frag:
403 1 extra opcode byte, 2 displacement bytes. */
406 /* COND_JUMP86 states. */
407 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
409 /* dword conditionals adds 5 bytes to frag:
410 1 extra opcode byte, 4 displacement bytes. */
412 /* word conditionals add 4 bytes to frag:
413 1 displacement byte and a 3 byte long branch insn. */
417 static const arch_entry cpu_arch
[] = {
419 {"i186", Cpu086
|Cpu186
},
420 {"i286", Cpu086
|Cpu186
|Cpu286
},
421 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
422 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
423 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
424 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
425 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
426 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
427 {"pentiumii", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
428 {"pentiumiii",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
429 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
430 {"prescott", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuPNI
},
431 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
432 {"k6_2", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
433 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
434 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
435 {"opteron", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
437 {".sse", CpuMMX
|CpuMMX2
|CpuSSE
},
438 {".sse2", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
439 {".sse3", CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
440 {".3dnow", CpuMMX
|Cpu3dnow
},
441 {".3dnowa", CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
442 {".padlock", CpuPadLock
},
443 {".pacifica", CpuSVME
},
448 const pseudo_typeS md_pseudo_table
[] =
450 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
451 {"align", s_align_bytes
, 0},
453 {"align", s_align_ptwo
, 0},
455 {"arch", set_cpu_arch
, 0},
459 {"ffloat", float_cons
, 'f'},
460 {"dfloat", float_cons
, 'd'},
461 {"tfloat", float_cons
, 'x'},
463 {"noopt", s_ignore
, 0},
464 {"optim", s_ignore
, 0},
465 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
466 {"code16", set_code_flag
, CODE_16BIT
},
467 {"code32", set_code_flag
, CODE_32BIT
},
468 {"code64", set_code_flag
, CODE_64BIT
},
469 {"intel_syntax", set_intel_syntax
, 1},
470 {"att_syntax", set_intel_syntax
, 0},
471 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
472 {"loc", dwarf2_directive_loc
, 0},
473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common
, 0},
477 {"secrel32", pe_directive_secrel
, 0},
482 /* For interface with expression (). */
483 extern char *input_line_pointer
;
485 /* Hash table for instruction mnemonic lookup. */
486 static struct hash_control
*op_hash
;
488 /* Hash table for register lookup. */
489 static struct hash_control
*reg_hash
;
492 i386_align_code (fragP
, count
)
496 /* Various efficient no-op patterns for aligning code labels.
497 Note: Don't try to assemble the instructions in the comments.
498 0L and 0w are not legal. */
499 static const char f32_1
[] =
501 static const char f32_2
[] =
502 {0x89,0xf6}; /* movl %esi,%esi */
503 static const char f32_3
[] =
504 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
505 static const char f32_4
[] =
506 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
507 static const char f32_5
[] =
509 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
510 static const char f32_6
[] =
511 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
512 static const char f32_7
[] =
513 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
514 static const char f32_8
[] =
516 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
517 static const char f32_9
[] =
518 {0x89,0xf6, /* movl %esi,%esi */
519 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
520 static const char f32_10
[] =
521 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
522 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
523 static const char f32_11
[] =
524 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_12
[] =
527 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
528 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
529 static const char f32_13
[] =
530 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
531 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
532 static const char f32_14
[] =
533 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
534 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
535 static const char f32_15
[] =
536 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
537 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
538 static const char f16_3
[] =
539 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
540 static const char f16_4
[] =
541 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
542 static const char f16_5
[] =
544 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
545 static const char f16_6
[] =
546 {0x89,0xf6, /* mov %si,%si */
547 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
548 static const char f16_7
[] =
549 {0x8d,0x74,0x00, /* lea 0(%si),%si */
550 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
551 static const char f16_8
[] =
552 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
553 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
554 static const char *const f32_patt
[] = {
555 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
556 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
558 static const char *const f16_patt
[] = {
559 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
560 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
563 if (count
<= 0 || count
> 15)
566 /* The recommended way to pad 64bit code is to use NOPs preceded by
567 maximally four 0x66 prefixes. Balance the size of nops. */
568 if (flag_code
== CODE_64BIT
)
571 int nnops
= (count
+ 3) / 4;
572 int len
= count
/ nnops
;
573 int remains
= count
- nnops
* len
;
576 for (i
= 0; i
< remains
; i
++)
578 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
579 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
582 for (; i
< nnops
; i
++)
584 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
585 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
590 if (flag_code
== CODE_16BIT
)
592 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
593 f16_patt
[count
- 1], count
);
595 /* Adjust jump offset. */
596 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
599 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
600 f32_patt
[count
- 1], count
);
601 fragP
->fr_var
= count
;
604 static INLINE
unsigned int
605 mode_from_disp_size (t
)
608 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
612 fits_in_signed_byte (num
)
615 return (num
>= -128) && (num
<= 127);
619 fits_in_unsigned_byte (num
)
622 return (num
& 0xff) == num
;
626 fits_in_unsigned_word (num
)
629 return (num
& 0xffff) == num
;
633 fits_in_signed_word (num
)
636 return (-32768 <= num
) && (num
<= 32767);
639 fits_in_signed_long (num
)
640 offsetT num ATTRIBUTE_UNUSED
;
645 return (!(((offsetT
) -1 << 31) & num
)
646 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
648 } /* fits_in_signed_long() */
650 fits_in_unsigned_long (num
)
651 offsetT num ATTRIBUTE_UNUSED
;
656 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
658 } /* fits_in_unsigned_long() */
661 smallest_imm_type (num
)
664 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
666 /* This code is disabled on the 486 because all the Imm1 forms
667 in the opcode table are slower on the i486. They're the
668 versions with the implicitly specified single-position
669 displacement, which has another syntax if you really want to
672 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
674 return (fits_in_signed_byte (num
)
675 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
676 : fits_in_unsigned_byte (num
)
677 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
678 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
679 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
680 : fits_in_signed_long (num
)
681 ? (Imm32
| Imm32S
| Imm64
)
682 : fits_in_unsigned_long (num
)
688 offset_in_range (val
, size
)
696 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
697 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
698 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
700 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
705 /* If BFD64, sign extend val. */
706 if (!use_rela_relocations
)
707 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
708 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
710 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
712 char buf1
[40], buf2
[40];
714 sprint_value (buf1
, val
);
715 sprint_value (buf2
, val
& mask
);
716 as_warn (_("%s shortened to %s"), buf1
, buf2
);
721 /* Returns 0 if attempting to add a prefix where one from the same
722 class already exists, 1 if non rep/repne added, 2 if rep/repne
731 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
732 && flag_code
== CODE_64BIT
)
740 case CS_PREFIX_OPCODE
:
741 case DS_PREFIX_OPCODE
:
742 case ES_PREFIX_OPCODE
:
743 case FS_PREFIX_OPCODE
:
744 case GS_PREFIX_OPCODE
:
745 case SS_PREFIX_OPCODE
:
749 case REPNE_PREFIX_OPCODE
:
750 case REPE_PREFIX_OPCODE
:
753 case LOCK_PREFIX_OPCODE
:
761 case ADDR_PREFIX_OPCODE
:
765 case DATA_PREFIX_OPCODE
:
770 if (i
.prefix
[q
] != 0)
772 as_bad (_("same type of prefix used twice"));
777 i
.prefix
[q
] = prefix
;
782 set_code_flag (value
)
786 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
787 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
788 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
790 as_bad (_("64bit mode not supported on this CPU."));
792 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
794 as_bad (_("32bit mode not supported on this CPU."));
800 set_16bit_gcc_code_flag (new_code_flag
)
803 flag_code
= new_code_flag
;
804 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
805 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
806 stackop_size
= LONG_MNEM_SUFFIX
;
810 set_intel_syntax (syntax_flag
)
813 /* Find out if register prefixing is specified. */
814 int ask_naked_reg
= 0;
817 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
819 char *string
= input_line_pointer
;
820 int e
= get_symbol_end ();
822 if (strcmp (string
, "prefix") == 0)
824 else if (strcmp (string
, "noprefix") == 0)
827 as_bad (_("bad argument to syntax directive."));
828 *input_line_pointer
= e
;
830 demand_empty_rest_of_line ();
832 intel_syntax
= syntax_flag
;
834 if (ask_naked_reg
== 0)
835 allow_naked_reg
= (intel_syntax
836 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
838 allow_naked_reg
= (ask_naked_reg
< 0);
840 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
841 identifier_chars
['$'] = intel_syntax
? '$' : 0;
846 int dummy ATTRIBUTE_UNUSED
;
850 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
852 char *string
= input_line_pointer
;
853 int e
= get_symbol_end ();
856 for (i
= 0; cpu_arch
[i
].name
; i
++)
858 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
862 cpu_arch_name
= cpu_arch
[i
].name
;
863 cpu_sub_arch_name
= NULL
;
864 cpu_arch_flags
= (cpu_arch
[i
].flags
865 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
868 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
870 cpu_sub_arch_name
= cpu_arch
[i
].name
;
871 cpu_arch_flags
|= cpu_arch
[i
].flags
;
873 *input_line_pointer
= e
;
874 demand_empty_rest_of_line ();
878 if (!cpu_arch
[i
].name
)
879 as_bad (_("no such architecture: `%s'"), string
);
881 *input_line_pointer
= e
;
884 as_bad (_("missing cpu architecture"));
886 no_cond_jump_promotion
= 0;
887 if (*input_line_pointer
== ','
888 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
890 char *string
= ++input_line_pointer
;
891 int e
= get_symbol_end ();
893 if (strcmp (string
, "nojumps") == 0)
894 no_cond_jump_promotion
= 1;
895 else if (strcmp (string
, "jumps") == 0)
898 as_bad (_("no such architecture modifier: `%s'"), string
);
900 *input_line_pointer
= e
;
903 demand_empty_rest_of_line ();
909 if (!strcmp (default_arch
, "x86_64"))
910 return bfd_mach_x86_64
;
911 else if (!strcmp (default_arch
, "i386"))
912 return bfd_mach_i386_i386
;
914 as_fatal (_("Unknown architecture"));
920 const char *hash_err
;
922 /* Initialize op_hash hash table. */
923 op_hash
= hash_new ();
926 const template *optab
;
927 templates
*core_optab
;
929 /* Setup for loop. */
931 core_optab
= (templates
*) xmalloc (sizeof (templates
));
932 core_optab
->start
= optab
;
937 if (optab
->name
== NULL
938 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
940 /* different name --> ship out current template list;
941 add to hash table; & begin anew. */
942 core_optab
->end
= optab
;
943 hash_err
= hash_insert (op_hash
,
948 as_fatal (_("Internal Error: Can't hash %s: %s"),
952 if (optab
->name
== NULL
)
954 core_optab
= (templates
*) xmalloc (sizeof (templates
));
955 core_optab
->start
= optab
;
960 /* Initialize reg_hash hash table. */
961 reg_hash
= hash_new ();
963 const reg_entry
*regtab
;
965 for (regtab
= i386_regtab
;
966 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
969 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
971 as_fatal (_("Internal Error: Can't hash %s: %s"),
977 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
982 for (c
= 0; c
< 256; c
++)
987 mnemonic_chars
[c
] = c
;
988 register_chars
[c
] = c
;
989 operand_chars
[c
] = c
;
991 else if (ISLOWER (c
))
993 mnemonic_chars
[c
] = c
;
994 register_chars
[c
] = c
;
995 operand_chars
[c
] = c
;
997 else if (ISUPPER (c
))
999 mnemonic_chars
[c
] = TOLOWER (c
);
1000 register_chars
[c
] = mnemonic_chars
[c
];
1001 operand_chars
[c
] = c
;
1004 if (ISALPHA (c
) || ISDIGIT (c
))
1005 identifier_chars
[c
] = c
;
1008 identifier_chars
[c
] = c
;
1009 operand_chars
[c
] = c
;
1014 identifier_chars
['@'] = '@';
1017 identifier_chars
['?'] = '?';
1018 operand_chars
['?'] = '?';
1020 digit_chars
['-'] = '-';
1021 mnemonic_chars
['-'] = '-';
1022 identifier_chars
['_'] = '_';
1023 identifier_chars
['.'] = '.';
1025 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1026 operand_chars
[(unsigned char) *p
] = *p
;
1029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1032 record_alignment (text_section
, 2);
1033 record_alignment (data_section
, 2);
1034 record_alignment (bss_section
, 2);
1038 if (flag_code
== CODE_64BIT
)
1040 x86_dwarf2_return_column
= 16;
1041 x86_cie_data_alignment
= -8;
1045 x86_dwarf2_return_column
= 8;
1046 x86_cie_data_alignment
= -4;
1051 i386_print_statistics (file
)
1054 hash_print_statistics (file
, "i386 opcode", op_hash
);
1055 hash_print_statistics (file
, "i386 register", reg_hash
);
1060 /* Debugging routines for md_assemble. */
1061 static void pi
PARAMS ((char *, i386_insn
*));
1062 static void pte
PARAMS ((template *));
1063 static void pt
PARAMS ((unsigned int));
1064 static void pe
PARAMS ((expressionS
*));
1065 static void ps
PARAMS ((symbolS
*));
1074 fprintf (stdout
, "%s: template ", line
);
1076 fprintf (stdout
, " address: base %s index %s scale %x\n",
1077 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1078 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1079 x
->log2_scale_factor
);
1080 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1081 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1082 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1083 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1084 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1085 (x
->rex
& REX_MODE64
) != 0,
1086 (x
->rex
& REX_EXTX
) != 0,
1087 (x
->rex
& REX_EXTY
) != 0,
1088 (x
->rex
& REX_EXTZ
) != 0);
1089 for (i
= 0; i
< x
->operands
; i
++)
1091 fprintf (stdout
, " #%d: ", i
+ 1);
1093 fprintf (stdout
, "\n");
1095 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1096 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1097 if (x
->types
[i
] & Imm
)
1099 if (x
->types
[i
] & Disp
)
1100 pe (x
->op
[i
].disps
);
1109 fprintf (stdout
, " %d operands ", t
->operands
);
1110 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1111 if (t
->extension_opcode
!= None
)
1112 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1113 if (t
->opcode_modifier
& D
)
1114 fprintf (stdout
, "D");
1115 if (t
->opcode_modifier
& W
)
1116 fprintf (stdout
, "W");
1117 fprintf (stdout
, "\n");
1118 for (i
= 0; i
< t
->operands
; i
++)
1120 fprintf (stdout
, " #%d type ", i
+ 1);
1121 pt (t
->operand_types
[i
]);
1122 fprintf (stdout
, "\n");
1130 fprintf (stdout
, " operation %d\n", e
->X_op
);
1131 fprintf (stdout
, " add_number %ld (%lx)\n",
1132 (long) e
->X_add_number
, (long) e
->X_add_number
);
1133 if (e
->X_add_symbol
)
1135 fprintf (stdout
, " add_symbol ");
1136 ps (e
->X_add_symbol
);
1137 fprintf (stdout
, "\n");
1141 fprintf (stdout
, " op_symbol ");
1142 ps (e
->X_op_symbol
);
1143 fprintf (stdout
, "\n");
1151 fprintf (stdout
, "%s type %s%s",
1153 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1154 segment_name (S_GET_SEGMENT (s
)));
1163 static const type_names
[] =
1176 { BaseIndex
, "BaseIndex" },
1180 { Disp32S
, "d32s" },
1182 { InOutPortReg
, "InOutPortReg" },
1183 { ShiftCount
, "ShiftCount" },
1184 { Control
, "control reg" },
1185 { Test
, "test reg" },
1186 { Debug
, "debug reg" },
1187 { FloatReg
, "FReg" },
1188 { FloatAcc
, "FAcc" },
1192 { JumpAbsolute
, "Jump Absolute" },
1203 const struct type_name
*ty
;
1205 for (ty
= type_names
; ty
->mask
; ty
++)
1207 fprintf (stdout
, "%s, ", ty
->tname
);
1211 #endif /* DEBUG386 */
1213 static bfd_reloc_code_real_type
1214 reloc (unsigned int size
,
1217 bfd_reloc_code_real_type other
)
1219 if (other
!= NO_RELOC
)
1221 reloc_howto_type
*reloc
;
1226 case BFD_RELOC_X86_64_TPOFF32
:
1227 other
= BFD_RELOC_X86_64_TPOFF64
;
1229 case BFD_RELOC_X86_64_DTPOFF32
:
1230 other
= BFD_RELOC_X86_64_DTPOFF64
;
1235 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1237 as_bad (_("unknown relocation (%u)"), other
);
1238 else if (size
!= bfd_get_reloc_size (reloc
))
1239 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1240 bfd_get_reloc_size (reloc
),
1242 else if (pcrel
&& !reloc
->pc_relative
)
1243 as_bad (_("non-pc-relative relocation for pc-relative field"));
1244 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1246 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1248 as_bad (_("relocated field and relocation type differ in signedness"));
1257 as_bad (_("there are no unsigned pc-relative relocations"));
1260 case 1: return BFD_RELOC_8_PCREL
;
1261 case 2: return BFD_RELOC_16_PCREL
;
1262 case 4: return BFD_RELOC_32_PCREL
;
1263 case 8: return BFD_RELOC_64_PCREL
;
1265 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1272 case 4: return BFD_RELOC_X86_64_32S
;
1277 case 1: return BFD_RELOC_8
;
1278 case 2: return BFD_RELOC_16
;
1279 case 4: return BFD_RELOC_32
;
1280 case 8: return BFD_RELOC_64
;
1282 as_bad (_("cannot do %s %u byte relocation"),
1283 sign
> 0 ? "signed" : "unsigned", size
);
1287 return BFD_RELOC_NONE
;
1290 /* Here we decide which fixups can be adjusted to make them relative to
1291 the beginning of the section instead of the symbol. Basically we need
1292 to make sure that the dynamic relocations are done correctly, so in
1293 some cases we force the original symbol to be used. */
1296 tc_i386_fix_adjustable (fixP
)
1297 fixS
*fixP ATTRIBUTE_UNUSED
;
1299 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1303 /* Don't adjust pc-relative references to merge sections in 64-bit
1305 if (use_rela_relocations
1306 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1310 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1311 and changed later by validate_fix. */
1312 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1313 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1316 /* adjust_reloc_syms doesn't know about the GOT. */
1317 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1318 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1319 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1320 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1321 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1322 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1323 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1324 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1325 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1326 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1327 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1328 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1329 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1330 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1331 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1332 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1333 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1334 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1335 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1336 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1337 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1338 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1339 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1340 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1346 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1349 intel_float_operand (mnemonic
)
1350 const char *mnemonic
;
1352 /* Note that the value returned is meaningful only for opcodes with (memory)
1353 operands, hence the code here is free to improperly handle opcodes that
1354 have no operands (for better performance and smaller code). */
1356 if (mnemonic
[0] != 'f')
1357 return 0; /* non-math */
1359 switch (mnemonic
[1])
1361 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1362 the fs segment override prefix not currently handled because no
1363 call path can make opcodes without operands get here */
1365 return 2 /* integer op */;
1367 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1368 return 3; /* fldcw/fldenv */
1371 if (mnemonic
[2] != 'o' /* fnop */)
1372 return 3; /* non-waiting control op */
1375 if (mnemonic
[2] == 's')
1376 return 3; /* frstor/frstpm */
1379 if (mnemonic
[2] == 'a')
1380 return 3; /* fsave */
1381 if (mnemonic
[2] == 't')
1383 switch (mnemonic
[3])
1385 case 'c': /* fstcw */
1386 case 'd': /* fstdw */
1387 case 'e': /* fstenv */
1388 case 's': /* fsts[gw] */
1394 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1395 return 0; /* fxsave/fxrstor are not really math ops */
1402 /* This is the guts of the machine-dependent assembler. LINE points to a
1403 machine dependent instruction. This function is supposed to emit
1404 the frags/bytes it assembles to. */
1411 char mnemonic
[MAX_MNEM_SIZE
];
1413 /* Initialize globals. */
1414 memset (&i
, '\0', sizeof (i
));
1415 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1416 i
.reloc
[j
] = NO_RELOC
;
1417 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1418 memset (im_expressions
, '\0', sizeof (im_expressions
));
1419 save_stack_p
= save_stack
;
1421 /* First parse an instruction mnemonic & call i386_operand for the operands.
1422 We assume that the scrubber has arranged it so that line[0] is the valid
1423 start of a (possibly prefixed) mnemonic. */
1425 line
= parse_insn (line
, mnemonic
);
1429 line
= parse_operands (line
, mnemonic
);
1433 /* Now we've parsed the mnemonic into a set of templates, and have the
1434 operands at hand. */
1436 /* All intel opcodes have reversed operands except for "bound" and
1437 "enter". We also don't reverse intersegment "jmp" and "call"
1438 instructions with 2 immediate operands so that the immediate segment
1439 precedes the offset, as it does when in AT&T mode. "enter" and the
1440 intersegment "jmp" and "call" instructions are the only ones that
1441 have two immediate operands. */
1442 if (intel_syntax
&& i
.operands
> 1
1443 && (strcmp (mnemonic
, "bound") != 0)
1444 && (strcmp (mnemonic
, "invlpga") != 0)
1445 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1451 /* Don't optimize displacement for movabs since it only takes 64bit
1454 && (flag_code
!= CODE_64BIT
1455 || strcmp (mnemonic
, "movabs") != 0))
1458 /* Next, we find a template that matches the given insn,
1459 making sure the overlap of the given operands types is consistent
1460 with the template operand types. */
1462 if (!match_template ())
1467 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1469 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1470 i
.tm
.base_opcode
^= FloatR
;
1472 /* Zap movzx and movsx suffix. The suffix may have been set from
1473 "word ptr" or "byte ptr" on the source operand, but we'll use
1474 the suffix later to choose the destination register. */
1475 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1477 if (i
.reg_operands
< 2
1479 && (~i
.tm
.opcode_modifier
1486 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1492 if (i
.tm
.opcode_modifier
& FWait
)
1493 if (!add_prefix (FWAIT_OPCODE
))
1496 /* Check string instruction segment overrides. */
1497 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1499 if (!check_string ())
1503 if (!process_suffix ())
1506 /* Make still unresolved immediate matches conform to size of immediate
1507 given in i.suffix. */
1508 if (!finalize_imm ())
1511 if (i
.types
[0] & Imm1
)
1512 i
.imm_operands
= 0; /* kludge for shift insns. */
1513 if (i
.types
[0] & ImplicitRegister
)
1515 if (i
.types
[1] & ImplicitRegister
)
1517 if (i
.types
[2] & ImplicitRegister
)
1520 if (i
.tm
.opcode_modifier
& ImmExt
)
1524 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1526 /* These Intel Prescott New Instructions have the fixed
1527 operands with an opcode suffix which is coded in the same
1528 place as an 8-bit immediate field would be. Here we check
1529 those operands and remove them afterwards. */
1532 for (x
= 0; x
< i
.operands
; x
++)
1533 if (i
.op
[x
].regs
->reg_num
!= x
)
1534 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1535 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1539 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1540 opcode suffix which is coded in the same place as an 8-bit
1541 immediate field would be. Here we fake an 8-bit immediate
1542 operand from the opcode suffix stored in tm.extension_opcode. */
1544 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1546 exp
= &im_expressions
[i
.imm_operands
++];
1547 i
.op
[i
.operands
].imms
= exp
;
1548 i
.types
[i
.operands
++] = Imm8
;
1549 exp
->X_op
= O_constant
;
1550 exp
->X_add_number
= i
.tm
.extension_opcode
;
1551 i
.tm
.extension_opcode
= None
;
1554 /* For insns with operands there are more diddles to do to the opcode. */
1557 if (!process_operands ())
1560 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1562 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1563 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1566 /* Handle conversion of 'int $3' --> special int3 insn. */
1567 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1569 i
.tm
.base_opcode
= INT3_OPCODE
;
1573 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1574 && i
.op
[0].disps
->X_op
== O_constant
)
1576 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1577 the absolute address given by the constant. Since ix86 jumps and
1578 calls are pc relative, we need to generate a reloc. */
1579 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1580 i
.op
[0].disps
->X_op
= O_symbol
;
1583 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1584 i
.rex
|= REX_MODE64
;
1586 /* For 8 bit registers we need an empty rex prefix. Also if the
1587 instruction already has a prefix, we need to convert old
1588 registers to new ones. */
1590 if (((i
.types
[0] & Reg8
) != 0
1591 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1592 || ((i
.types
[1] & Reg8
) != 0
1593 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1594 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1599 i
.rex
|= REX_OPCODE
;
1600 for (x
= 0; x
< 2; x
++)
1602 /* Look for 8 bit operand that uses old registers. */
1603 if ((i
.types
[x
] & Reg8
) != 0
1604 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1606 /* In case it is "hi" register, give up. */
1607 if (i
.op
[x
].regs
->reg_num
> 3)
1608 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1609 i
.op
[x
].regs
->reg_name
);
1611 /* Otherwise it is equivalent to the extended register.
1612 Since the encoding doesn't change this is merely
1613 cosmetic cleanup for debug output. */
1615 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1621 add_prefix (REX_OPCODE
| i
.rex
);
1623 /* We are ready to output the insn. */
1628 parse_insn (line
, mnemonic
)
1633 char *token_start
= l
;
1638 /* Non-zero if we found a prefix only acceptable with string insns. */
1639 const char *expecting_string_instruction
= NULL
;
1644 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1647 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1649 as_bad (_("no such instruction: `%s'"), token_start
);
1654 if (!is_space_char (*l
)
1655 && *l
!= END_OF_INSN
1657 || (*l
!= PREFIX_SEPARATOR
1660 as_bad (_("invalid character %s in mnemonic"),
1661 output_invalid (*l
));
1664 if (token_start
== l
)
1666 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1667 as_bad (_("expecting prefix; got nothing"));
1669 as_bad (_("expecting mnemonic; got nothing"));
1673 /* Look up instruction (or prefix) via hash table. */
1674 current_templates
= hash_find (op_hash
, mnemonic
);
1676 if (*l
!= END_OF_INSN
1677 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1678 && current_templates
1679 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1681 if (current_templates
->start
->cpu_flags
1682 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1684 as_bad ((flag_code
!= CODE_64BIT
1685 ? _("`%s' is only supported in 64-bit mode")
1686 : _("`%s' is not supported in 64-bit mode")),
1687 current_templates
->start
->name
);
1690 /* If we are in 16-bit mode, do not allow addr16 or data16.
1691 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1692 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1693 && flag_code
!= CODE_64BIT
1694 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1695 ^ (flag_code
== CODE_16BIT
)))
1697 as_bad (_("redundant %s prefix"),
1698 current_templates
->start
->name
);
1701 /* Add prefix, checking for repeated prefixes. */
1702 switch (add_prefix (current_templates
->start
->base_opcode
))
1707 expecting_string_instruction
= current_templates
->start
->name
;
1710 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1717 if (!current_templates
)
1719 /* See if we can get a match by trimming off a suffix. */
1722 case WORD_MNEM_SUFFIX
:
1723 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
1724 i
.suffix
= SHORT_MNEM_SUFFIX
;
1726 case BYTE_MNEM_SUFFIX
:
1727 case QWORD_MNEM_SUFFIX
:
1728 i
.suffix
= mnem_p
[-1];
1730 current_templates
= hash_find (op_hash
, mnemonic
);
1732 case SHORT_MNEM_SUFFIX
:
1733 case LONG_MNEM_SUFFIX
:
1736 i
.suffix
= mnem_p
[-1];
1738 current_templates
= hash_find (op_hash
, mnemonic
);
1746 if (intel_float_operand (mnemonic
) == 1)
1747 i
.suffix
= SHORT_MNEM_SUFFIX
;
1749 i
.suffix
= LONG_MNEM_SUFFIX
;
1751 current_templates
= hash_find (op_hash
, mnemonic
);
1755 if (!current_templates
)
1757 as_bad (_("no such instruction: `%s'"), token_start
);
1762 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1764 /* Check for a branch hint. We allow ",pt" and ",pn" for
1765 predict taken and predict not taken respectively.
1766 I'm not sure that branch hints actually do anything on loop
1767 and jcxz insns (JumpByte) for current Pentium4 chips. They
1768 may work in the future and it doesn't hurt to accept them
1770 if (l
[0] == ',' && l
[1] == 'p')
1774 if (!add_prefix (DS_PREFIX_OPCODE
))
1778 else if (l
[2] == 'n')
1780 if (!add_prefix (CS_PREFIX_OPCODE
))
1786 /* Any other comma loses. */
1789 as_bad (_("invalid character %s in mnemonic"),
1790 output_invalid (*l
));
1794 /* Check if instruction is supported on specified architecture. */
1796 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1798 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1799 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
1801 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
1804 if (!(supported
& 2))
1806 as_bad (flag_code
== CODE_64BIT
1807 ? _("`%s' is not supported in 64-bit mode")
1808 : _("`%s' is only supported in 64-bit mode"),
1809 current_templates
->start
->name
);
1812 if (!(supported
& 1))
1814 as_warn (_("`%s' is not supported on `%s%s'"),
1815 current_templates
->start
->name
,
1817 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
1819 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1821 as_warn (_("use .code16 to ensure correct addressing mode"));
1824 /* Check for rep/repne without a string instruction. */
1825 if (expecting_string_instruction
)
1827 static templates override
;
1829 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
1830 if (t
->opcode_modifier
& IsString
)
1832 if (t
>= current_templates
->end
)
1834 as_bad (_("expecting string instruction after `%s'"),
1835 expecting_string_instruction
);
1838 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
1839 if (!(t
->opcode_modifier
& IsString
))
1842 current_templates
= &override
;
1849 parse_operands (l
, mnemonic
)
1851 const char *mnemonic
;
1855 /* 1 if operand is pending after ','. */
1856 unsigned int expecting_operand
= 0;
1858 /* Non-zero if operand parens not balanced. */
1859 unsigned int paren_not_balanced
;
1861 while (*l
!= END_OF_INSN
)
1863 /* Skip optional white space before operand. */
1864 if (is_space_char (*l
))
1866 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1868 as_bad (_("invalid character %s before operand %d"),
1869 output_invalid (*l
),
1873 token_start
= l
; /* after white space */
1874 paren_not_balanced
= 0;
1875 while (paren_not_balanced
|| *l
!= ',')
1877 if (*l
== END_OF_INSN
)
1879 if (paren_not_balanced
)
1882 as_bad (_("unbalanced parenthesis in operand %d."),
1885 as_bad (_("unbalanced brackets in operand %d."),
1890 break; /* we are done */
1892 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1894 as_bad (_("invalid character %s in operand %d"),
1895 output_invalid (*l
),
1902 ++paren_not_balanced
;
1904 --paren_not_balanced
;
1909 ++paren_not_balanced
;
1911 --paren_not_balanced
;
1915 if (l
!= token_start
)
1916 { /* Yes, we've read in another operand. */
1917 unsigned int operand_ok
;
1918 this_operand
= i
.operands
++;
1919 if (i
.operands
> MAX_OPERANDS
)
1921 as_bad (_("spurious operands; (%d operands/instruction max)"),
1925 /* Now parse operand adding info to 'i' as we go along. */
1926 END_STRING_AND_SAVE (l
);
1930 i386_intel_operand (token_start
,
1931 intel_float_operand (mnemonic
));
1933 operand_ok
= i386_operand (token_start
);
1935 RESTORE_END_STRING (l
);
1941 if (expecting_operand
)
1943 expecting_operand_after_comma
:
1944 as_bad (_("expecting operand after ','; got nothing"));
1949 as_bad (_("expecting operand before ','; got nothing"));
1954 /* Now *l must be either ',' or END_OF_INSN. */
1957 if (*++l
== END_OF_INSN
)
1959 /* Just skip it, if it's \n complain. */
1960 goto expecting_operand_after_comma
;
1962 expecting_operand
= 1;
1971 union i386_op temp_op
;
1972 unsigned int temp_type
;
1973 enum bfd_reloc_code_real temp_reloc
;
1977 if (i
.operands
== 2)
1982 else if (i
.operands
== 3)
1987 temp_type
= i
.types
[xchg2
];
1988 i
.types
[xchg2
] = i
.types
[xchg1
];
1989 i
.types
[xchg1
] = temp_type
;
1990 temp_op
= i
.op
[xchg2
];
1991 i
.op
[xchg2
] = i
.op
[xchg1
];
1992 i
.op
[xchg1
] = temp_op
;
1993 temp_reloc
= i
.reloc
[xchg2
];
1994 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1995 i
.reloc
[xchg1
] = temp_reloc
;
1997 if (i
.mem_operands
== 2)
1999 const seg_entry
*temp_seg
;
2000 temp_seg
= i
.seg
[0];
2001 i
.seg
[0] = i
.seg
[1];
2002 i
.seg
[1] = temp_seg
;
2006 /* Try to ensure constant immediates are represented in the smallest
2011 char guess_suffix
= 0;
2015 guess_suffix
= i
.suffix
;
2016 else if (i
.reg_operands
)
2018 /* Figure out a suffix from the last register operand specified.
2019 We can't do this properly yet, ie. excluding InOutPortReg,
2020 but the following works for instructions with immediates.
2021 In any case, we can't set i.suffix yet. */
2022 for (op
= i
.operands
; --op
>= 0;)
2023 if (i
.types
[op
] & Reg
)
2025 if (i
.types
[op
] & Reg8
)
2026 guess_suffix
= BYTE_MNEM_SUFFIX
;
2027 else if (i
.types
[op
] & Reg16
)
2028 guess_suffix
= WORD_MNEM_SUFFIX
;
2029 else if (i
.types
[op
] & Reg32
)
2030 guess_suffix
= LONG_MNEM_SUFFIX
;
2031 else if (i
.types
[op
] & Reg64
)
2032 guess_suffix
= QWORD_MNEM_SUFFIX
;
2036 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2037 guess_suffix
= WORD_MNEM_SUFFIX
;
2039 for (op
= i
.operands
; --op
>= 0;)
2040 if (i
.types
[op
] & Imm
)
2042 switch (i
.op
[op
].imms
->X_op
)
2045 /* If a suffix is given, this operand may be shortened. */
2046 switch (guess_suffix
)
2048 case LONG_MNEM_SUFFIX
:
2049 i
.types
[op
] |= Imm32
| Imm64
;
2051 case WORD_MNEM_SUFFIX
:
2052 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2054 case BYTE_MNEM_SUFFIX
:
2055 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2059 /* If this operand is at most 16 bits, convert it
2060 to a signed 16 bit number before trying to see
2061 whether it will fit in an even smaller size.
2062 This allows a 16-bit operand such as $0xffe0 to
2063 be recognised as within Imm8S range. */
2064 if ((i
.types
[op
] & Imm16
)
2065 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2067 i
.op
[op
].imms
->X_add_number
=
2068 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2070 if ((i
.types
[op
] & Imm32
)
2071 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2074 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2075 ^ ((offsetT
) 1 << 31))
2076 - ((offsetT
) 1 << 31));
2078 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2080 /* We must avoid matching of Imm32 templates when 64bit
2081 only immediate is available. */
2082 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2083 i
.types
[op
] &= ~Imm32
;
2090 /* Symbols and expressions. */
2092 /* Convert symbolic operand to proper sizes for matching, but don't
2093 prevent matching a set of insns that only supports sizes other
2094 than those matching the insn suffix. */
2096 unsigned int mask
, allowed
= 0;
2099 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2100 allowed
|= t
->operand_types
[op
];
2101 switch (guess_suffix
)
2103 case QWORD_MNEM_SUFFIX
:
2104 mask
= Imm64
| Imm32S
;
2106 case LONG_MNEM_SUFFIX
:
2109 case WORD_MNEM_SUFFIX
:
2112 case BYTE_MNEM_SUFFIX
:
2120 i
.types
[op
] &= mask
;
2127 /* Try to use the smallest displacement type too. */
2133 for (op
= i
.operands
; --op
>= 0;)
2134 if (i
.types
[op
] & Disp
)
2136 if (i
.op
[op
].disps
->X_op
== O_constant
)
2138 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2140 if ((i
.types
[op
] & Disp16
)
2141 && (disp
& ~(offsetT
) 0xffff) == 0)
2143 /* If this operand is at most 16 bits, convert
2144 to a signed 16 bit number and don't use 64bit
2146 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2147 i
.types
[op
] &= ~Disp64
;
2149 if ((i
.types
[op
] & Disp32
)
2150 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2152 /* If this operand is at most 32 bits, convert
2153 to a signed 32 bit number and don't use 64bit
2155 disp
&= (((offsetT
) 2 << 31) - 1);
2156 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2157 i
.types
[op
] &= ~Disp64
;
2159 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2161 i
.types
[op
] &= ~Disp
;
2165 else if (flag_code
== CODE_64BIT
)
2167 if (fits_in_signed_long (disp
))
2169 i
.types
[op
] &= ~Disp64
;
2170 i
.types
[op
] |= Disp32S
;
2172 if (fits_in_unsigned_long (disp
))
2173 i
.types
[op
] |= Disp32
;
2175 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2176 && fits_in_signed_byte (disp
))
2177 i
.types
[op
] |= Disp8
;
2180 /* We only support 64bit displacement on constants. */
2181 i
.types
[op
] &= ~Disp64
;
2188 /* Points to template once we've found it. */
2190 unsigned int overlap0
, overlap1
, overlap2
;
2191 unsigned int found_reverse_match
;
2194 #define MATCH(overlap, given, template) \
2195 ((overlap & ~JumpAbsolute) \
2196 && (((given) & (BaseIndex | JumpAbsolute)) \
2197 == ((overlap) & (BaseIndex | JumpAbsolute))))
2199 /* If given types r0 and r1 are registers they must be of the same type
2200 unless the expected operand type register overlap is null.
2201 Note that Acc in a template matches every size of reg. */
2202 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2203 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2204 || ((g0) & Reg) == ((g1) & Reg) \
2205 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2210 found_reverse_match
= 0;
2211 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2213 : (i
.suffix
== WORD_MNEM_SUFFIX
2215 : (i
.suffix
== SHORT_MNEM_SUFFIX
2217 : (i
.suffix
== LONG_MNEM_SUFFIX
2219 : (i
.suffix
== QWORD_MNEM_SUFFIX
2221 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2222 ? No_xSuf
: 0))))));
2224 t
= current_templates
->start
;
2225 if (i
.suffix
== QWORD_MNEM_SUFFIX
2226 && flag_code
!= CODE_64BIT
2228 ? !(t
->opcode_modifier
& IgnoreSize
)
2229 && !intel_float_operand (t
->name
)
2230 : intel_float_operand (t
->name
) != 2)
2231 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2232 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2233 && (t
->base_opcode
!= 0x0fc7
2234 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2235 t
= current_templates
->end
;
2236 for (; t
< current_templates
->end
; t
++)
2238 /* Must have right number of operands. */
2239 if (i
.operands
!= t
->operands
)
2242 /* Check the suffix, except for some instructions in intel mode. */
2243 if ((t
->opcode_modifier
& suffix_check
)
2245 && (t
->opcode_modifier
& IgnoreSize
)))
2248 /* Do not verify operands when there are none. */
2249 else if (!t
->operands
)
2251 if (t
->cpu_flags
& ~cpu_arch_flags
)
2253 /* We've found a match; break out of loop. */
2257 overlap0
= i
.types
[0] & t
->operand_types
[0];
2258 switch (t
->operands
)
2261 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2266 overlap1
= i
.types
[1] & t
->operand_types
[1];
2267 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2268 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2269 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2270 t
->operand_types
[0],
2271 overlap1
, i
.types
[1],
2272 t
->operand_types
[1]))
2274 /* Check if other direction is valid ... */
2275 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2278 /* Try reversing direction of operands. */
2279 overlap0
= i
.types
[0] & t
->operand_types
[1];
2280 overlap1
= i
.types
[1] & t
->operand_types
[0];
2281 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2282 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2283 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2284 t
->operand_types
[1],
2285 overlap1
, i
.types
[1],
2286 t
->operand_types
[0]))
2288 /* Does not match either direction. */
2291 /* found_reverse_match holds which of D or FloatDR
2293 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2295 /* Found a forward 2 operand match here. */
2296 else if (t
->operands
== 3)
2298 /* Here we make use of the fact that there are no
2299 reverse match 3 operand instructions, and all 3
2300 operand instructions only need to be checked for
2301 register consistency between operands 2 and 3. */
2302 overlap2
= i
.types
[2] & t
->operand_types
[2];
2303 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2304 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2305 t
->operand_types
[1],
2306 overlap2
, i
.types
[2],
2307 t
->operand_types
[2]))
2311 /* Found either forward/reverse 2 or 3 operand match here:
2312 slip through to break. */
2314 if (t
->cpu_flags
& ~cpu_arch_flags
)
2316 found_reverse_match
= 0;
2319 /* We've found a match; break out of loop. */
2323 if (t
== current_templates
->end
)
2325 /* We found no match. */
2326 as_bad (_("suffix or operands invalid for `%s'"),
2327 current_templates
->start
->name
);
2331 if (!quiet_warnings
)
2334 && ((i
.types
[0] & JumpAbsolute
)
2335 != (t
->operand_types
[0] & JumpAbsolute
)))
2337 as_warn (_("indirect %s without `*'"), t
->name
);
2340 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2341 == (IsPrefix
| IgnoreSize
))
2343 /* Warn them that a data or address size prefix doesn't
2344 affect assembly of the next line of code. */
2345 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2349 /* Copy the template we found. */
2351 if (found_reverse_match
)
2353 /* If we found a reverse match we must alter the opcode
2354 direction bit. found_reverse_match holds bits to change
2355 (different for int & float insns). */
2357 i
.tm
.base_opcode
^= found_reverse_match
;
2359 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2360 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2369 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2370 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2372 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2374 as_bad (_("`%s' operand %d must use `%%es' segment"),
2379 /* There's only ever one segment override allowed per instruction.
2380 This instruction possibly has a legal segment override on the
2381 second operand, so copy the segment to where non-string
2382 instructions store it, allowing common code. */
2383 i
.seg
[0] = i
.seg
[1];
2385 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2387 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2389 as_bad (_("`%s' operand %d must use `%%es' segment"),
2399 process_suffix (void)
2401 /* If matched instruction specifies an explicit instruction mnemonic
2403 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2405 if (i
.tm
.opcode_modifier
& Size16
)
2406 i
.suffix
= WORD_MNEM_SUFFIX
;
2407 else if (i
.tm
.opcode_modifier
& Size64
)
2408 i
.suffix
= QWORD_MNEM_SUFFIX
;
2410 i
.suffix
= LONG_MNEM_SUFFIX
;
2412 else if (i
.reg_operands
)
2414 /* If there's no instruction mnemonic suffix we try to invent one
2415 based on register operands. */
2418 /* We take i.suffix from the last register operand specified,
2419 Destination register type is more significant than source
2423 for (op
= i
.operands
; --op
>= 0;)
2424 if ((i
.types
[op
] & Reg
)
2425 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2427 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2428 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2429 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2434 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2436 if (!check_byte_reg ())
2439 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2441 if (!check_long_reg ())
2444 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2446 if (!check_qword_reg ())
2449 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2451 if (!check_word_reg ())
2454 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2455 /* Do nothing if the instruction is going to ignore the prefix. */
2460 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2462 /* exclude fldenv/frstor/fsave/fstenv */
2463 && (i
.tm
.opcode_modifier
& No_sSuf
))
2465 i
.suffix
= stackop_size
;
2467 else if (intel_syntax
2469 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2470 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2471 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2472 && i
.tm
.extension_opcode
<= 3)))
2477 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2479 i
.suffix
= QWORD_MNEM_SUFFIX
;
2483 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2484 i
.suffix
= LONG_MNEM_SUFFIX
;
2487 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2488 i
.suffix
= WORD_MNEM_SUFFIX
;
2497 if (i
.tm
.opcode_modifier
& W
)
2499 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2505 unsigned int suffixes
= ~i
.tm
.opcode_modifier
2513 if ((i
.tm
.opcode_modifier
& W
)
2514 || ((suffixes
& (suffixes
- 1))
2515 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2517 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2523 /* Change the opcode based on the operand size given by i.suffix;
2524 We don't need to change things for byte insns. */
2526 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2528 /* It's not a byte, select word/dword operation. */
2529 if (i
.tm
.opcode_modifier
& W
)
2531 if (i
.tm
.opcode_modifier
& ShortForm
)
2532 i
.tm
.base_opcode
|= 8;
2534 i
.tm
.base_opcode
|= 1;
2537 /* Now select between word & dword operations via the operand
2538 size prefix, except for instructions that will ignore this
2540 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2541 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2542 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2543 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2544 || (flag_code
== CODE_64BIT
2545 && (i
.tm
.opcode_modifier
& JumpByte
))))
2547 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2549 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2550 prefix
= ADDR_PREFIX_OPCODE
;
2552 if (!add_prefix (prefix
))
2556 /* Set mode64 for an operand. */
2557 if (i
.suffix
== QWORD_MNEM_SUFFIX
2558 && flag_code
== CODE_64BIT
2559 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2560 i
.rex
|= REX_MODE64
;
2562 /* Size floating point instruction. */
2563 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2564 if (i
.tm
.opcode_modifier
& FloatMF
)
2565 i
.tm
.base_opcode
^= 4;
2572 check_byte_reg (void)
2576 for (op
= i
.operands
; --op
>= 0;)
2578 /* If this is an eight bit register, it's OK. If it's the 16 or
2579 32 bit version of an eight bit register, we will just use the
2580 low portion, and that's OK too. */
2581 if (i
.types
[op
] & Reg8
)
2584 /* movzx and movsx should not generate this warning. */
2586 && (i
.tm
.base_opcode
== 0xfb7
2587 || i
.tm
.base_opcode
== 0xfb6
2588 || i
.tm
.base_opcode
== 0x63
2589 || i
.tm
.base_opcode
== 0xfbe
2590 || i
.tm
.base_opcode
== 0xfbf))
2593 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
2595 /* Prohibit these changes in the 64bit mode, since the
2596 lowering is more complicated. */
2597 if (flag_code
== CODE_64BIT
2598 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2600 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2601 i
.op
[op
].regs
->reg_name
,
2605 #if REGISTER_WARNINGS
2607 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2608 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2609 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2610 ? REGNAM_AL
- REGNAM_AX
2611 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2612 i
.op
[op
].regs
->reg_name
,
2617 /* Any other register is bad. */
2618 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2620 | Control
| Debug
| Test
2621 | FloatReg
| FloatAcc
))
2623 as_bad (_("`%%%s' not allowed with `%s%c'"),
2624 i
.op
[op
].regs
->reg_name
,
2638 for (op
= i
.operands
; --op
>= 0;)
2639 /* Reject eight bit registers, except where the template requires
2640 them. (eg. movzb) */
2641 if ((i
.types
[op
] & Reg8
) != 0
2642 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2644 as_bad (_("`%%%s' not allowed with `%s%c'"),
2645 i
.op
[op
].regs
->reg_name
,
2650 /* Warn if the e prefix on a general reg is missing. */
2651 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2652 && (i
.types
[op
] & Reg16
) != 0
2653 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2655 /* Prohibit these changes in the 64bit mode, since the
2656 lowering is more complicated. */
2657 if (flag_code
== CODE_64BIT
)
2659 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2660 i
.op
[op
].regs
->reg_name
,
2664 #if REGISTER_WARNINGS
2666 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2667 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2668 i
.op
[op
].regs
->reg_name
,
2672 /* Warn if the r prefix on a general reg is missing. */
2673 else if ((i
.types
[op
] & Reg64
) != 0
2674 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2676 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2677 i
.op
[op
].regs
->reg_name
,
2689 for (op
= i
.operands
; --op
>= 0; )
2690 /* Reject eight bit registers, except where the template requires
2691 them. (eg. movzb) */
2692 if ((i
.types
[op
] & Reg8
) != 0
2693 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2695 as_bad (_("`%%%s' not allowed with `%s%c'"),
2696 i
.op
[op
].regs
->reg_name
,
2701 /* Warn if the e prefix on a general reg is missing. */
2702 else if (((i
.types
[op
] & Reg16
) != 0
2703 || (i
.types
[op
] & Reg32
) != 0)
2704 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2706 /* Prohibit these changes in the 64bit mode, since the
2707 lowering is more complicated. */
2708 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2709 i
.op
[op
].regs
->reg_name
,
2720 for (op
= i
.operands
; --op
>= 0;)
2721 /* Reject eight bit registers, except where the template requires
2722 them. (eg. movzb) */
2723 if ((i
.types
[op
] & Reg8
) != 0
2724 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2726 as_bad (_("`%%%s' not allowed with `%s%c'"),
2727 i
.op
[op
].regs
->reg_name
,
2732 /* Warn if the e prefix on a general reg is present. */
2733 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2734 && (i
.types
[op
] & Reg32
) != 0
2735 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2737 /* Prohibit these changes in the 64bit mode, since the
2738 lowering is more complicated. */
2739 if (flag_code
== CODE_64BIT
)
2741 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2742 i
.op
[op
].regs
->reg_name
,
2747 #if REGISTER_WARNINGS
2748 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2749 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2750 i
.op
[op
].regs
->reg_name
,
2760 unsigned int overlap0
, overlap1
, overlap2
;
2762 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2763 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2764 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2765 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2766 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2770 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2772 : (i
.suffix
== WORD_MNEM_SUFFIX
2774 : (i
.suffix
== QWORD_MNEM_SUFFIX
2778 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2779 || overlap0
== (Imm16
| Imm32
)
2780 || overlap0
== (Imm16
| Imm32S
))
2782 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2785 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2786 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2787 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2789 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2793 i
.types
[0] = overlap0
;
2795 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2796 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
2797 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2798 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2799 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2803 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2805 : (i
.suffix
== WORD_MNEM_SUFFIX
2807 : (i
.suffix
== QWORD_MNEM_SUFFIX
2811 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2812 || overlap1
== (Imm16
| Imm32
)
2813 || overlap1
== (Imm16
| Imm32S
))
2815 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2818 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2819 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2820 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2822 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2826 i
.types
[1] = overlap1
;
2828 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2829 assert ((overlap2
& Imm
) == 0);
2830 i
.types
[2] = overlap2
;
2838 /* Default segment register this instruction will use for memory
2839 accesses. 0 means unknown. This is only for optimizing out
2840 unnecessary segment overrides. */
2841 const seg_entry
*default_seg
= 0;
2843 /* The imul $imm, %reg instruction is converted into
2844 imul $imm, %reg, %reg, and the clr %reg instruction
2845 is converted into xor %reg, %reg. */
2846 if (i
.tm
.opcode_modifier
& regKludge
)
2848 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2849 /* Pretend we saw the extra register operand. */
2850 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2851 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2852 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2856 if (i
.tm
.opcode_modifier
& ShortForm
)
2858 /* The register or float register operand is in operand 0 or 1. */
2859 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2860 /* Register goes in low 3 bits of opcode. */
2861 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2862 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2864 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2866 /* Warn about some common errors, but press on regardless.
2867 The first case can be generated by gcc (<= 2.8.1). */
2868 if (i
.operands
== 2)
2870 /* Reversed arguments on faddp, fsubp, etc. */
2871 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2872 i
.op
[1].regs
->reg_name
,
2873 i
.op
[0].regs
->reg_name
);
2877 /* Extraneous `l' suffix on fp insn. */
2878 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2879 i
.op
[0].regs
->reg_name
);
2883 else if (i
.tm
.opcode_modifier
& Modrm
)
2885 /* The opcode is completed (modulo i.tm.extension_opcode which
2886 must be put into the modrm byte). Now, we make the modrm and
2887 index base bytes based on all the info we've collected. */
2889 default_seg
= build_modrm_byte ();
2891 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2893 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2894 && i
.op
[0].regs
->reg_num
== 1)
2896 as_bad (_("you can't `pop %%cs'"));
2899 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2900 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2903 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2907 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2909 /* For the string instructions that allow a segment override
2910 on one of their operands, the default segment is ds. */
2914 if ((i
.tm
.base_opcode
== 0x8d /* lea */
2915 || (i
.tm
.cpu_flags
& CpuSVME
))
2916 && i
.seg
[0] && !quiet_warnings
)
2917 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
2919 /* If a segment was explicitly specified, and the specified segment
2920 is not the default, use an opcode prefix to select it. If we
2921 never figured out what the default segment is, then default_seg
2922 will be zero at this point, and the specified segment prefix will
2924 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2926 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2932 static const seg_entry
*
2935 const seg_entry
*default_seg
= 0;
2937 /* i.reg_operands MUST be the number of real register operands;
2938 implicit registers do not count. */
2939 if (i
.reg_operands
== 2)
2941 unsigned int source
, dest
;
2942 source
= ((i
.types
[0]
2943 & (Reg
| RegMMX
| RegXMM
2945 | Control
| Debug
| Test
))
2950 /* One of the register operands will be encoded in the i.tm.reg
2951 field, the other in the combined i.tm.mode and i.tm.regmem
2952 fields. If no form of this instruction supports a memory
2953 destination operand, then we assume the source operand may
2954 sometimes be a memory operand and so we need to store the
2955 destination in the i.rm.reg field. */
2956 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2958 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2959 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2960 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2962 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2967 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2968 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2969 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2971 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2974 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_EXTX
| REX_EXTZ
)))
2976 if (!((i
.types
[0] | i
.types
[1]) & Control
))
2978 i
.rex
&= ~(REX_EXTX
| REX_EXTZ
);
2979 add_prefix (LOCK_PREFIX_OPCODE
);
2983 { /* If it's not 2 reg operands... */
2986 unsigned int fake_zero_displacement
= 0;
2987 unsigned int op
= ((i
.types
[0] & AnyMem
)
2989 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2993 if (i
.base_reg
== 0)
2996 if (!i
.disp_operands
)
2997 fake_zero_displacement
= 1;
2998 if (i
.index_reg
== 0)
3000 /* Operand is just <disp> */
3001 if (flag_code
== CODE_64BIT
)
3003 /* 64bit mode overwrites the 32bit absolute
3004 addressing by RIP relative addressing and
3005 absolute addressing is encoded by one of the
3006 redundant SIB forms. */
3007 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3008 i
.sib
.base
= NO_BASE_REGISTER
;
3009 i
.sib
.index
= NO_INDEX_REGISTER
;
3010 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
3012 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3014 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3015 i
.types
[op
] = Disp16
;
3019 i
.rm
.regmem
= NO_BASE_REGISTER
;
3020 i
.types
[op
] = Disp32
;
3023 else /* !i.base_reg && i.index_reg */
3025 i
.sib
.index
= i
.index_reg
->reg_num
;
3026 i
.sib
.base
= NO_BASE_REGISTER
;
3027 i
.sib
.scale
= i
.log2_scale_factor
;
3028 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3029 i
.types
[op
] &= ~Disp
;
3030 if (flag_code
!= CODE_64BIT
)
3031 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3033 i
.types
[op
] |= Disp32S
;
3034 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3038 /* RIP addressing for 64bit mode. */
3039 else if (i
.base_reg
->reg_type
== BaseIndex
)
3041 i
.rm
.regmem
= NO_BASE_REGISTER
;
3042 i
.types
[op
] &= ~ Disp
;
3043 i
.types
[op
] |= Disp32S
;
3044 i
.flags
[op
] = Operand_PCrel
;
3045 if (! i
.disp_operands
)
3046 fake_zero_displacement
= 1;
3048 else if (i
.base_reg
->reg_type
& Reg16
)
3050 switch (i
.base_reg
->reg_num
)
3053 if (i
.index_reg
== 0)
3055 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3056 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3060 if (i
.index_reg
== 0)
3063 if ((i
.types
[op
] & Disp
) == 0)
3065 /* fake (%bp) into 0(%bp) */
3066 i
.types
[op
] |= Disp8
;
3067 fake_zero_displacement
= 1;
3070 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3071 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3073 default: /* (%si) -> 4 or (%di) -> 5 */
3074 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3076 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3078 else /* i.base_reg and 32/64 bit mode */
3080 if (flag_code
== CODE_64BIT
3081 && (i
.types
[op
] & Disp
))
3082 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
3084 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3085 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3087 i
.sib
.base
= i
.base_reg
->reg_num
;
3088 /* x86-64 ignores REX prefix bit here to avoid decoder
3090 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3093 if (i
.disp_operands
== 0)
3095 fake_zero_displacement
= 1;
3096 i
.types
[op
] |= Disp8
;
3099 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3103 i
.sib
.scale
= i
.log2_scale_factor
;
3104 if (i
.index_reg
== 0)
3106 /* <disp>(%esp) becomes two byte modrm with no index
3107 register. We've already stored the code for esp
3108 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3109 Any base register besides %esp will not use the
3110 extra modrm byte. */
3111 i
.sib
.index
= NO_INDEX_REGISTER
;
3112 #if !SCALE1_WHEN_NO_INDEX
3113 /* Another case where we force the second modrm byte. */
3114 if (i
.log2_scale_factor
)
3115 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3120 i
.sib
.index
= i
.index_reg
->reg_num
;
3121 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3122 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3125 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3128 if (fake_zero_displacement
)
3130 /* Fakes a zero displacement assuming that i.types[op]
3131 holds the correct displacement size. */
3134 assert (i
.op
[op
].disps
== 0);
3135 exp
= &disp_expressions
[i
.disp_operands
++];
3136 i
.op
[op
].disps
= exp
;
3137 exp
->X_op
= O_constant
;
3138 exp
->X_add_number
= 0;
3139 exp
->X_add_symbol
= (symbolS
*) 0;
3140 exp
->X_op_symbol
= (symbolS
*) 0;
3144 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3145 (if any) based on i.tm.extension_opcode. Again, we must be
3146 careful to make sure that segment/control/debug/test/MMX
3147 registers are coded into the i.rm.reg field. */
3152 & (Reg
| RegMMX
| RegXMM
3154 | Control
| Debug
| Test
))
3157 & (Reg
| RegMMX
| RegXMM
3159 | Control
| Debug
| Test
))
3162 /* If there is an extension opcode to put here, the register
3163 number must be put into the regmem field. */
3164 if (i
.tm
.extension_opcode
!= None
)
3166 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3167 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3172 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3173 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3177 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3178 must set it to 3 to indicate this is a register operand
3179 in the regmem field. */
3180 if (!i
.mem_operands
)
3184 /* Fill in i.rm.reg field with extension opcode (if any). */
3185 if (i
.tm
.extension_opcode
!= None
)
3186 i
.rm
.reg
= i
.tm
.extension_opcode
;
3197 relax_substateT subtype
;
3202 if (flag_code
== CODE_16BIT
)
3206 if (i
.prefix
[DATA_PREFIX
] != 0)
3212 /* Pentium4 branch hints. */
3213 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3214 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3219 if (i
.prefix
[REX_PREFIX
] != 0)
3225 if (i
.prefixes
!= 0 && !intel_syntax
)
3226 as_warn (_("skipping prefixes on this instruction"));
3228 /* It's always a symbol; End frag & setup for relax.
3229 Make sure there is enough room in this frag for the largest
3230 instruction we may generate in md_convert_frag. This is 2
3231 bytes for the opcode and room for the prefix and largest
3233 frag_grow (prefix
+ 2 + 4);
3234 /* Prefix and 1 opcode byte go in fr_fix. */
3235 p
= frag_more (prefix
+ 1);
3236 if (i
.prefix
[DATA_PREFIX
] != 0)
3237 *p
++ = DATA_PREFIX_OPCODE
;
3238 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3239 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3240 *p
++ = i
.prefix
[SEG_PREFIX
];
3241 if (i
.prefix
[REX_PREFIX
] != 0)
3242 *p
++ = i
.prefix
[REX_PREFIX
];
3243 *p
= i
.tm
.base_opcode
;
3245 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3246 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3247 else if ((cpu_arch_flags
& Cpu386
) != 0)
3248 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3250 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3253 sym
= i
.op
[0].disps
->X_add_symbol
;
3254 off
= i
.op
[0].disps
->X_add_number
;
3256 if (i
.op
[0].disps
->X_op
!= O_constant
3257 && i
.op
[0].disps
->X_op
!= O_symbol
)
3259 /* Handle complex expressions. */
3260 sym
= make_expr_symbol (i
.op
[0].disps
);
3264 /* 1 possible extra opcode + 4 byte displacement go in var part.
3265 Pass reloc in fr_var. */
3266 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3276 if (i
.tm
.opcode_modifier
& JumpByte
)
3278 /* This is a loop or jecxz type instruction. */
3280 if (i
.prefix
[ADDR_PREFIX
] != 0)
3282 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3285 /* Pentium4 branch hints. */
3286 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3287 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3289 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3298 if (flag_code
== CODE_16BIT
)
3301 if (i
.prefix
[DATA_PREFIX
] != 0)
3303 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3313 if (i
.prefix
[REX_PREFIX
] != 0)
3315 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3319 if (i
.prefixes
!= 0 && !intel_syntax
)
3320 as_warn (_("skipping prefixes on this instruction"));
3322 p
= frag_more (1 + size
);
3323 *p
++ = i
.tm
.base_opcode
;
3325 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3326 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3328 /* All jumps handled here are signed, but don't use a signed limit
3329 check for 32 and 16 bit jumps as we want to allow wrap around at
3330 4G and 64k respectively. */
3332 fixP
->fx_signed
= 1;
3336 output_interseg_jump ()
3344 if (flag_code
== CODE_16BIT
)
3348 if (i
.prefix
[DATA_PREFIX
] != 0)
3354 if (i
.prefix
[REX_PREFIX
] != 0)
3364 if (i
.prefixes
!= 0 && !intel_syntax
)
3365 as_warn (_("skipping prefixes on this instruction"));
3367 /* 1 opcode; 2 segment; offset */
3368 p
= frag_more (prefix
+ 1 + 2 + size
);
3370 if (i
.prefix
[DATA_PREFIX
] != 0)
3371 *p
++ = DATA_PREFIX_OPCODE
;
3373 if (i
.prefix
[REX_PREFIX
] != 0)
3374 *p
++ = i
.prefix
[REX_PREFIX
];
3376 *p
++ = i
.tm
.base_opcode
;
3377 if (i
.op
[1].imms
->X_op
== O_constant
)
3379 offsetT n
= i
.op
[1].imms
->X_add_number
;
3382 && !fits_in_unsigned_word (n
)
3383 && !fits_in_signed_word (n
))
3385 as_bad (_("16-bit jump out of range"));
3388 md_number_to_chars (p
, n
, size
);
3391 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3392 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3393 if (i
.op
[0].imms
->X_op
!= O_constant
)
3394 as_bad (_("can't handle non absolute segment in `%s'"),
3396 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3402 fragS
*insn_start_frag
;
3403 offsetT insn_start_off
;
3405 /* Tie dwarf2 debug info to the address at the start of the insn.
3406 We can't do this after the insn has been output as the current
3407 frag may have been closed off. eg. by frag_var. */
3408 dwarf2_emit_insn (0);
3410 insn_start_frag
= frag_now
;
3411 insn_start_off
= frag_now_fix ();
3414 if (i
.tm
.opcode_modifier
& Jump
)
3416 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3418 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3419 output_interseg_jump ();
3422 /* Output normal instructions here. */
3426 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3427 more higher byte to specify a prefix the instruction
3429 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3431 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3433 unsigned int prefix
;
3434 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3436 if (prefix
!= REPE_PREFIX_OPCODE
3437 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3438 add_prefix (prefix
);
3441 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3444 /* The prefix bytes. */
3446 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3452 md_number_to_chars (p
, (valueT
) *q
, 1);
3456 /* Now the opcode; be careful about word order here! */
3457 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3459 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3465 /* Put out high byte first: can't use md_number_to_chars! */
3466 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3467 *p
= i
.tm
.base_opcode
& 0xff;
3470 /* Now the modrm byte and sib byte (if present). */
3471 if (i
.tm
.opcode_modifier
& Modrm
)
3474 md_number_to_chars (p
,
3475 (valueT
) (i
.rm
.regmem
<< 0
3479 /* If i.rm.regmem == ESP (4)
3480 && i.rm.mode != (Register mode)
3482 ==> need second modrm byte. */
3483 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3485 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3488 md_number_to_chars (p
,
3489 (valueT
) (i
.sib
.base
<< 0
3491 | i
.sib
.scale
<< 6),
3496 if (i
.disp_operands
)
3497 output_disp (insn_start_frag
, insn_start_off
);
3500 output_imm (insn_start_frag
, insn_start_off
);
3508 #endif /* DEBUG386 */
3512 output_disp (insn_start_frag
, insn_start_off
)
3513 fragS
*insn_start_frag
;
3514 offsetT insn_start_off
;
3519 for (n
= 0; n
< i
.operands
; n
++)
3521 if (i
.types
[n
] & Disp
)
3523 if (i
.op
[n
].disps
->X_op
== O_constant
)
3529 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3532 if (i
.types
[n
] & Disp8
)
3534 if (i
.types
[n
] & Disp64
)
3537 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3539 p
= frag_more (size
);
3540 md_number_to_chars (p
, val
, size
);
3544 enum bfd_reloc_code_real reloc_type
;
3547 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3549 /* The PC relative address is computed relative
3550 to the instruction boundary, so in case immediate
3551 fields follows, we need to adjust the value. */
3552 if (pcrel
&& i
.imm_operands
)
3557 for (n1
= 0; n1
< i
.operands
; n1
++)
3558 if (i
.types
[n1
] & Imm
)
3560 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3563 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3565 if (i
.types
[n1
] & Imm64
)
3570 /* We should find the immediate. */
3571 if (n1
== i
.operands
)
3573 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3576 if (i
.types
[n
] & Disp32S
)
3579 if (i
.types
[n
] & (Disp16
| Disp64
))
3582 if (i
.types
[n
] & Disp64
)
3586 p
= frag_more (size
);
3587 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3589 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3590 && (((reloc_type
== BFD_RELOC_32
3591 || reloc_type
== BFD_RELOC_X86_64_32S
)
3592 && (i
.op
[n
].disps
->X_op
== O_symbol
3593 || (i
.op
[n
].disps
->X_op
== O_add
3594 && ((symbol_get_value_expression
3595 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3597 || reloc_type
== BFD_RELOC_32_PCREL
))
3601 if (insn_start_frag
== frag_now
)
3602 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3607 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3608 for (fr
= insn_start_frag
->fr_next
;
3609 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3611 add
+= p
- frag_now
->fr_literal
;
3614 if (flag_code
!= CODE_64BIT
)
3615 reloc_type
= BFD_RELOC_386_GOTPC
;
3617 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3618 i
.op
[n
].disps
->X_add_number
+= add
;
3620 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3621 i
.op
[n
].disps
, pcrel
, reloc_type
);
3628 output_imm (insn_start_frag
, insn_start_off
)
3629 fragS
*insn_start_frag
;
3630 offsetT insn_start_off
;
3635 for (n
= 0; n
< i
.operands
; n
++)
3637 if (i
.types
[n
] & Imm
)
3639 if (i
.op
[n
].imms
->X_op
== O_constant
)
3645 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3648 if (i
.types
[n
] & (Imm8
| Imm8S
))
3650 else if (i
.types
[n
] & Imm64
)
3653 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3655 p
= frag_more (size
);
3656 md_number_to_chars (p
, val
, size
);
3660 /* Not absolute_section.
3661 Need a 32-bit fixup (don't support 8bit
3662 non-absolute imms). Try to support other
3664 enum bfd_reloc_code_real reloc_type
;
3668 if ((i
.types
[n
] & (Imm32S
))
3669 && (i
.suffix
== QWORD_MNEM_SUFFIX
3670 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
3672 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3675 if (i
.types
[n
] & (Imm8
| Imm8S
))
3677 if (i
.types
[n
] & Imm64
)
3681 p
= frag_more (size
);
3682 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3684 /* This is tough to explain. We end up with this one if we
3685 * have operands that look like
3686 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3687 * obtain the absolute address of the GOT, and it is strongly
3688 * preferable from a performance point of view to avoid using
3689 * a runtime relocation for this. The actual sequence of
3690 * instructions often look something like:
3695 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3697 * The call and pop essentially return the absolute address
3698 * of the label .L66 and store it in %ebx. The linker itself
3699 * will ultimately change the first operand of the addl so
3700 * that %ebx points to the GOT, but to keep things simple, the
3701 * .o file must have this operand set so that it generates not
3702 * the absolute address of .L66, but the absolute address of
3703 * itself. This allows the linker itself simply treat a GOTPC
3704 * relocation as asking for a pcrel offset to the GOT to be
3705 * added in, and the addend of the relocation is stored in the
3706 * operand field for the instruction itself.
3708 * Our job here is to fix the operand so that it would add
3709 * the correct offset so that %ebx would point to itself. The
3710 * thing that is tricky is that .-.L66 will point to the
3711 * beginning of the instruction, so we need to further modify
3712 * the operand so that it will point to itself. There are
3713 * other cases where you have something like:
3715 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3717 * and here no correction would be required. Internally in
3718 * the assembler we treat operands of this form as not being
3719 * pcrel since the '.' is explicitly mentioned, and I wonder
3720 * whether it would simplify matters to do it this way. Who
3721 * knows. In earlier versions of the PIC patches, the
3722 * pcrel_adjust field was used to store the correction, but
3723 * since the expression is not pcrel, I felt it would be
3724 * confusing to do it this way. */
3726 if ((reloc_type
== BFD_RELOC_32
3727 || reloc_type
== BFD_RELOC_X86_64_32S
)
3729 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3730 && (i
.op
[n
].imms
->X_op
== O_symbol
3731 || (i
.op
[n
].imms
->X_op
== O_add
3732 && ((symbol_get_value_expression
3733 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3738 if (insn_start_frag
== frag_now
)
3739 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3744 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3745 for (fr
= insn_start_frag
->fr_next
;
3746 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3748 add
+= p
- frag_now
->fr_literal
;
3751 if (flag_code
!= CODE_64BIT
)
3752 reloc_type
= BFD_RELOC_386_GOTPC
;
3754 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
3755 i
.op
[n
].imms
->X_add_number
+= add
;
3757 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3758 i
.op
[n
].imms
, 0, reloc_type
);
3764 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3765 # define lex_got(reloc, adjust, types) NULL
3767 /* Parse operands of the form
3768 <symbol>@GOTOFF+<nnn>
3769 and similar .plt or .got references.
3771 If we find one, set up the correct relocation in RELOC and copy the
3772 input string, minus the `@GOTOFF' into a malloc'd buffer for
3773 parsing by the calling routine. Return this buffer, and if ADJUST
3774 is non-null set it to the length of the string we removed from the
3775 input line. Otherwise return NULL. */
3777 lex_got (enum bfd_reloc_code_real
*reloc
,
3779 unsigned int *types
)
3781 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3782 static const struct {
3784 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3785 const unsigned int types64
;
3787 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
}, Imm32
|Imm32S
|Disp32
},
3788 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, BFD_RELOC_X86_64_GOTOFF64
}, Imm64
|Disp64
},
3789 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
}, Imm32
|Imm32S
|Disp32
},
3790 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
}, Imm32
|Imm32S
|Disp32
},
3791 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 }, 0 },
3792 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
}, Imm32
|Imm32S
|Disp32
},
3793 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
}, Imm32
|Imm32S
|Disp32
},
3794 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3795 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 }, 0 },
3796 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
}, Imm32
|Imm32S
|Imm64
|Disp32
|Disp64
},
3797 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 }, 0 },
3798 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 }, 0 },
3799 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
}, Imm32
|Imm32S
|Disp32
}
3807 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3808 if (is_end_of_line
[(unsigned char) *cp
])
3811 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3815 len
= strlen (gotrel
[j
].str
);
3816 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3818 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3821 char *tmpbuf
, *past_reloc
;
3823 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3829 if (flag_code
!= CODE_64BIT
)
3830 *types
= Imm32
|Disp32
;
3832 *types
= gotrel
[j
].types64
;
3835 if (GOT_symbol
== NULL
)
3836 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3838 /* Replace the relocation token with ' ', so that
3839 errors like foo@GOTOFF1 will be detected. */
3841 /* The length of the first part of our input line. */
3842 first
= cp
- input_line_pointer
;
3844 /* The second part goes from after the reloc token until
3845 (and including) an end_of_line char. Don't use strlen
3846 here as the end_of_line char may not be a NUL. */
3847 past_reloc
= cp
+ 1 + len
;
3848 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3850 second
= cp
- past_reloc
;
3852 /* Allocate and copy string. The trailing NUL shouldn't
3853 be necessary, but be safe. */
3854 tmpbuf
= xmalloc (first
+ second
+ 2);
3855 memcpy (tmpbuf
, input_line_pointer
, first
);
3856 tmpbuf
[first
] = ' ';
3857 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3858 tmpbuf
[first
+ second
+ 1] = '\0';
3862 as_bad (_("@%s reloc is not supported in %s bit mode"),
3863 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3868 /* Might be a symbol version string. Don't as_bad here. */
3872 /* x86_cons_fix_new is called via the expression parsing code when a
3873 reloc is needed. We use this hook to get the correct .got reloc. */
3874 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3877 x86_cons_fix_new (frag
, off
, len
, exp
)
3883 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, got_reloc
);
3884 got_reloc
= NO_RELOC
;
3885 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3889 x86_cons (exp
, size
)
3893 if (size
== 4 || (flag_code
== CODE_64BIT
&& size
== 8))
3895 /* Handle @GOTOFF and the like in an expression. */
3897 char *gotfree_input_line
;
3900 save
= input_line_pointer
;
3901 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
3902 if (gotfree_input_line
)
3903 input_line_pointer
= gotfree_input_line
;
3907 if (gotfree_input_line
)
3909 /* expression () has merrily parsed up to the end of line,
3910 or a comma - in the wrong buffer. Transfer how far
3911 input_line_pointer has moved to the right buffer. */
3912 input_line_pointer
= (save
3913 + (input_line_pointer
- gotfree_input_line
)
3915 free (gotfree_input_line
);
3926 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3932 enum bfd_reloc_code_real r
= reloc (len
, 0, -1, NO_RELOC
);
3934 if (exp
->X_op
== O_secrel
)
3936 exp
->X_op
= O_symbol
;
3937 r
= BFD_RELOC_32_SECREL
;
3940 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3944 pe_directive_secrel (dummy
)
3945 int dummy ATTRIBUTE_UNUSED
;
3952 if (exp
.X_op
== O_symbol
)
3953 exp
.X_op
= O_secrel
;
3955 emit_expr (&exp
, 4);
3957 while (*input_line_pointer
++ == ',');
3959 input_line_pointer
--;
3960 demand_empty_rest_of_line ();
3965 static int i386_immediate
PARAMS ((char *));
3968 i386_immediate (imm_start
)
3971 char *save_input_line_pointer
;
3972 char *gotfree_input_line
;
3975 unsigned int types
= ~0U;
3977 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3979 as_bad (_("only 1 or 2 immediate operands are allowed"));
3983 exp
= &im_expressions
[i
.imm_operands
++];
3984 i
.op
[this_operand
].imms
= exp
;
3986 if (is_space_char (*imm_start
))
3989 save_input_line_pointer
= input_line_pointer
;
3990 input_line_pointer
= imm_start
;
3992 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
3993 if (gotfree_input_line
)
3994 input_line_pointer
= gotfree_input_line
;
3996 exp_seg
= expression (exp
);
3999 if (*input_line_pointer
)
4000 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4002 input_line_pointer
= save_input_line_pointer
;
4003 if (gotfree_input_line
)
4004 free (gotfree_input_line
);
4006 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4008 /* Missing or bad expr becomes absolute 0. */
4009 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4011 exp
->X_op
= O_constant
;
4012 exp
->X_add_number
= 0;
4013 exp
->X_add_symbol
= (symbolS
*) 0;
4014 exp
->X_op_symbol
= (symbolS
*) 0;
4016 else if (exp
->X_op
== O_constant
)
4018 /* Size it properly later. */
4019 i
.types
[this_operand
] |= Imm64
;
4020 /* If BFD64, sign extend val. */
4021 if (!use_rela_relocations
)
4022 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4023 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4025 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4026 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4027 && exp_seg
!= absolute_section
4028 && exp_seg
!= text_section
4029 && exp_seg
!= data_section
4030 && exp_seg
!= bss_section
4031 && exp_seg
!= undefined_section
4032 && !bfd_is_com_section (exp_seg
))
4034 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4040 /* This is an address. The size of the address will be
4041 determined later, depending on destination register,
4042 suffix, or the default for the section. */
4043 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4044 i
.types
[this_operand
] &= types
;
4050 static char *i386_scale
PARAMS ((char *));
4057 char *save
= input_line_pointer
;
4059 input_line_pointer
= scale
;
4060 val
= get_absolute_expression ();
4065 i
.log2_scale_factor
= 0;
4068 i
.log2_scale_factor
= 1;
4071 i
.log2_scale_factor
= 2;
4074 i
.log2_scale_factor
= 3;
4078 char sep
= *input_line_pointer
;
4080 *input_line_pointer
= '\0';
4081 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4083 *input_line_pointer
= sep
;
4084 input_line_pointer
= save
;
4088 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4090 as_warn (_("scale factor of %d without an index register"),
4091 1 << i
.log2_scale_factor
);
4092 #if SCALE1_WHEN_NO_INDEX
4093 i
.log2_scale_factor
= 0;
4096 scale
= input_line_pointer
;
4097 input_line_pointer
= save
;
4101 static int i386_displacement
PARAMS ((char *, char *));
4104 i386_displacement (disp_start
, disp_end
)
4110 char *save_input_line_pointer
;
4111 char *gotfree_input_line
;
4112 int bigdisp
= Disp32
;
4113 unsigned int types
= Disp
;
4115 if (flag_code
== CODE_64BIT
)
4117 if (i
.prefix
[ADDR_PREFIX
] == 0)
4118 bigdisp
= Disp64
| Disp32S
| Disp32
;
4120 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4122 i
.types
[this_operand
] |= bigdisp
;
4124 exp
= &disp_expressions
[i
.disp_operands
];
4125 i
.op
[this_operand
].disps
= exp
;
4127 save_input_line_pointer
= input_line_pointer
;
4128 input_line_pointer
= disp_start
;
4129 END_STRING_AND_SAVE (disp_end
);
4131 #ifndef GCC_ASM_O_HACK
4132 #define GCC_ASM_O_HACK 0
4135 END_STRING_AND_SAVE (disp_end
+ 1);
4136 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4137 && displacement_string_end
[-1] == '+')
4139 /* This hack is to avoid a warning when using the "o"
4140 constraint within gcc asm statements.
4143 #define _set_tssldt_desc(n,addr,limit,type) \
4144 __asm__ __volatile__ ( \
4146 "movw %w1,2+%0\n\t" \
4148 "movb %b1,4+%0\n\t" \
4149 "movb %4,5+%0\n\t" \
4150 "movb $0,6+%0\n\t" \
4151 "movb %h1,7+%0\n\t" \
4153 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4155 This works great except that the output assembler ends
4156 up looking a bit weird if it turns out that there is
4157 no offset. You end up producing code that looks like:
4170 So here we provide the missing zero. */
4172 *displacement_string_end
= '0';
4175 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4176 if (gotfree_input_line
)
4177 input_line_pointer
= gotfree_input_line
;
4179 exp_seg
= expression (exp
);
4182 if (*input_line_pointer
)
4183 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4185 RESTORE_END_STRING (disp_end
+ 1);
4187 RESTORE_END_STRING (disp_end
);
4188 input_line_pointer
= save_input_line_pointer
;
4189 if (gotfree_input_line
)
4190 free (gotfree_input_line
);
4192 /* We do this to make sure that the section symbol is in
4193 the symbol table. We will ultimately change the relocation
4194 to be relative to the beginning of the section. */
4195 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4196 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4197 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4199 if (exp
->X_op
!= O_symbol
)
4201 as_bad (_("bad expression used with @%s"),
4202 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4208 if (S_IS_LOCAL (exp
->X_add_symbol
)
4209 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4210 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4211 exp
->X_op
= O_subtract
;
4212 exp
->X_op_symbol
= GOT_symbol
;
4213 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4214 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4215 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4216 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4218 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4221 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4223 /* Missing or bad expr becomes absolute 0. */
4224 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4226 exp
->X_op
= O_constant
;
4227 exp
->X_add_number
= 0;
4228 exp
->X_add_symbol
= (symbolS
*) 0;
4229 exp
->X_op_symbol
= (symbolS
*) 0;
4232 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4233 if (exp
->X_op
!= O_constant
4234 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4235 && exp_seg
!= absolute_section
4236 && exp_seg
!= text_section
4237 && exp_seg
!= data_section
4238 && exp_seg
!= bss_section
4239 && exp_seg
!= undefined_section
4240 && !bfd_is_com_section (exp_seg
))
4242 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4247 if (!(i
.types
[this_operand
] & ~Disp
))
4248 i
.types
[this_operand
] &= types
;
4253 static int i386_index_check
PARAMS ((const char *));
4255 /* Make sure the memory operand we've been dealt is valid.
4256 Return 1 on success, 0 on a failure. */
4259 i386_index_check (operand_string
)
4260 const char *operand_string
;
4263 #if INFER_ADDR_PREFIX
4269 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4270 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4272 /* Memory operands of SVME insns are special in that they only allow
4273 rAX as their memory address and ignore any segment override. */
4276 /* SKINIT is even more restrictive: it always requires EAX. */
4277 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4279 else if (flag_code
== CODE_64BIT
)
4280 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4282 RegXX
= (flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4286 || !(i
.base_reg
->reg_type
& Acc
)
4287 || !(i
.base_reg
->reg_type
& RegXX
)
4289 || (i
.types
[0] & Disp
))
4292 else if (flag_code
== CODE_64BIT
)
4294 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4297 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4298 && (i
.base_reg
->reg_type
!= BaseIndex
4301 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4302 != (RegXX
| BaseIndex
))))
4307 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4311 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4312 != (Reg16
| BaseIndex
)))
4314 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4315 != (Reg16
| BaseIndex
))
4317 && i
.base_reg
->reg_num
< 6
4318 && i
.index_reg
->reg_num
>= 6
4319 && i
.log2_scale_factor
== 0))))
4326 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4328 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4329 != (Reg32
| BaseIndex
))))
4335 #if INFER_ADDR_PREFIX
4336 if (i
.prefix
[ADDR_PREFIX
] == 0)
4338 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4340 /* Change the size of any displacement too. At most one of
4341 Disp16 or Disp32 is set.
4342 FIXME. There doesn't seem to be any real need for separate
4343 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4344 Removing them would probably clean up the code quite a lot. */
4345 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4346 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4351 as_bad (_("`%s' is not a valid base/index expression"),
4355 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4357 flag_code_names
[flag_code
]);
4362 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4366 i386_operand (operand_string
)
4367 char *operand_string
;
4371 char *op_string
= operand_string
;
4373 if (is_space_char (*op_string
))
4376 /* We check for an absolute prefix (differentiating,
4377 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4378 if (*op_string
== ABSOLUTE_PREFIX
)
4381 if (is_space_char (*op_string
))
4383 i
.types
[this_operand
] |= JumpAbsolute
;
4386 /* Check if operand is a register. */
4387 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4388 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4390 /* Check for a segment override by searching for ':' after a
4391 segment register. */
4393 if (is_space_char (*op_string
))
4395 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4400 i
.seg
[i
.mem_operands
] = &es
;
4403 i
.seg
[i
.mem_operands
] = &cs
;
4406 i
.seg
[i
.mem_operands
] = &ss
;
4409 i
.seg
[i
.mem_operands
] = &ds
;
4412 i
.seg
[i
.mem_operands
] = &fs
;
4415 i
.seg
[i
.mem_operands
] = &gs
;
4419 /* Skip the ':' and whitespace. */
4421 if (is_space_char (*op_string
))
4424 if (!is_digit_char (*op_string
)
4425 && !is_identifier_char (*op_string
)
4426 && *op_string
!= '('
4427 && *op_string
!= ABSOLUTE_PREFIX
)
4429 as_bad (_("bad memory operand `%s'"), op_string
);
4432 /* Handle case of %es:*foo. */
4433 if (*op_string
== ABSOLUTE_PREFIX
)
4436 if (is_space_char (*op_string
))
4438 i
.types
[this_operand
] |= JumpAbsolute
;
4440 goto do_memory_reference
;
4444 as_bad (_("junk `%s' after register"), op_string
);
4447 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4448 i
.op
[this_operand
].regs
= r
;
4451 else if (*op_string
== REGISTER_PREFIX
)
4453 as_bad (_("bad register name `%s'"), op_string
);
4456 else if (*op_string
== IMMEDIATE_PREFIX
)
4459 if (i
.types
[this_operand
] & JumpAbsolute
)
4461 as_bad (_("immediate operand illegal with absolute jump"));
4464 if (!i386_immediate (op_string
))
4467 else if (is_digit_char (*op_string
)
4468 || is_identifier_char (*op_string
)
4469 || *op_string
== '(')
4471 /* This is a memory reference of some sort. */
4474 /* Start and end of displacement string expression (if found). */
4475 char *displacement_string_start
;
4476 char *displacement_string_end
;
4478 do_memory_reference
:
4479 if ((i
.mem_operands
== 1
4480 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4481 || i
.mem_operands
== 2)
4483 as_bad (_("too many memory references for `%s'"),
4484 current_templates
->start
->name
);
4488 /* Check for base index form. We detect the base index form by
4489 looking for an ')' at the end of the operand, searching
4490 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4492 base_string
= op_string
+ strlen (op_string
);
4495 if (is_space_char (*base_string
))
4498 /* If we only have a displacement, set-up for it to be parsed later. */
4499 displacement_string_start
= op_string
;
4500 displacement_string_end
= base_string
+ 1;
4502 if (*base_string
== ')')
4505 unsigned int parens_balanced
= 1;
4506 /* We've already checked that the number of left & right ()'s are
4507 equal, so this loop will not be infinite. */
4511 if (*base_string
== ')')
4513 if (*base_string
== '(')
4516 while (parens_balanced
);
4518 temp_string
= base_string
;
4520 /* Skip past '(' and whitespace. */
4522 if (is_space_char (*base_string
))
4525 if (*base_string
== ','
4526 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4527 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4529 displacement_string_end
= temp_string
;
4531 i
.types
[this_operand
] |= BaseIndex
;
4535 base_string
= end_op
;
4536 if (is_space_char (*base_string
))
4540 /* There may be an index reg or scale factor here. */
4541 if (*base_string
== ',')
4544 if (is_space_char (*base_string
))
4547 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4548 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4550 base_string
= end_op
;
4551 if (is_space_char (*base_string
))
4553 if (*base_string
== ',')
4556 if (is_space_char (*base_string
))
4559 else if (*base_string
!= ')')
4561 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4566 else if (*base_string
== REGISTER_PREFIX
)
4568 as_bad (_("bad register name `%s'"), base_string
);
4572 /* Check for scale factor. */
4573 if (*base_string
!= ')')
4575 char *end_scale
= i386_scale (base_string
);
4580 base_string
= end_scale
;
4581 if (is_space_char (*base_string
))
4583 if (*base_string
!= ')')
4585 as_bad (_("expecting `)' after scale factor in `%s'"),
4590 else if (!i
.index_reg
)
4592 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4597 else if (*base_string
!= ')')
4599 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4604 else if (*base_string
== REGISTER_PREFIX
)
4606 as_bad (_("bad register name `%s'"), base_string
);
4611 /* If there's an expression beginning the operand, parse it,
4612 assuming displacement_string_start and
4613 displacement_string_end are meaningful. */
4614 if (displacement_string_start
!= displacement_string_end
)
4616 if (!i386_displacement (displacement_string_start
,
4617 displacement_string_end
))
4621 /* Special case for (%dx) while doing input/output op. */
4623 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4625 && i
.log2_scale_factor
== 0
4626 && i
.seg
[i
.mem_operands
] == 0
4627 && (i
.types
[this_operand
] & Disp
) == 0)
4629 i
.types
[this_operand
] = InOutPortReg
;
4633 if (i386_index_check (operand_string
) == 0)
4639 /* It's not a memory operand; argh! */
4640 as_bad (_("invalid char %s beginning operand %d `%s'"),
4641 output_invalid (*op_string
),
4646 return 1; /* Normal return. */
4649 /* md_estimate_size_before_relax()
4651 Called just before relax() for rs_machine_dependent frags. The x86
4652 assembler uses these frags to handle variable size jump
4655 Any symbol that is now undefined will not become defined.
4656 Return the correct fr_subtype in the frag.
4657 Return the initial "guess for variable size of frag" to caller.
4658 The guess is actually the growth beyond the fixed part. Whatever
4659 we do to grow the fixed or variable part contributes to our
4663 md_estimate_size_before_relax (fragP
, segment
)
4667 /* We've already got fragP->fr_subtype right; all we have to do is
4668 check for un-relaxable symbols. On an ELF system, we can't relax
4669 an externally visible symbol, because it may be overridden by a
4671 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4674 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4675 || S_IS_WEAK (fragP
->fr_symbol
)))
4679 /* Symbol is undefined in this segment, or we need to keep a
4680 reloc so that weak symbols can be overridden. */
4681 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4682 enum bfd_reloc_code_real reloc_type
;
4683 unsigned char *opcode
;
4686 if (fragP
->fr_var
!= NO_RELOC
)
4687 reloc_type
= fragP
->fr_var
;
4689 reloc_type
= BFD_RELOC_16_PCREL
;
4691 reloc_type
= BFD_RELOC_32_PCREL
;
4693 old_fr_fix
= fragP
->fr_fix
;
4694 opcode
= (unsigned char *) fragP
->fr_opcode
;
4696 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4699 /* Make jmp (0xeb) a (d)word displacement jump. */
4701 fragP
->fr_fix
+= size
;
4702 fix_new (fragP
, old_fr_fix
, size
,
4704 fragP
->fr_offset
, 1,
4710 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4712 /* Negate the condition, and branch past an
4713 unconditional jump. */
4716 /* Insert an unconditional jump. */
4718 /* We added two extra opcode bytes, and have a two byte
4720 fragP
->fr_fix
+= 2 + 2;
4721 fix_new (fragP
, old_fr_fix
+ 2, 2,
4723 fragP
->fr_offset
, 1,
4730 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4735 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4737 fragP
->fr_offset
, 1,
4739 fixP
->fx_signed
= 1;
4743 /* This changes the byte-displacement jump 0x7N
4744 to the (d)word-displacement jump 0x0f,0x8N. */
4745 opcode
[1] = opcode
[0] + 0x10;
4746 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4747 /* We've added an opcode byte. */
4748 fragP
->fr_fix
+= 1 + size
;
4749 fix_new (fragP
, old_fr_fix
+ 1, size
,
4751 fragP
->fr_offset
, 1,
4756 BAD_CASE (fragP
->fr_subtype
);
4760 return fragP
->fr_fix
- old_fr_fix
;
4763 /* Guess size depending on current relax state. Initially the relax
4764 state will correspond to a short jump and we return 1, because
4765 the variable part of the frag (the branch offset) is one byte
4766 long. However, we can relax a section more than once and in that
4767 case we must either set fr_subtype back to the unrelaxed state,
4768 or return the value for the appropriate branch. */
4769 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4772 /* Called after relax() is finished.
4774 In: Address of frag.
4775 fr_type == rs_machine_dependent.
4776 fr_subtype is what the address relaxed to.
4778 Out: Any fixSs and constants are set up.
4779 Caller will turn frag into a ".space 0". */
4782 md_convert_frag (abfd
, sec
, fragP
)
4783 bfd
*abfd ATTRIBUTE_UNUSED
;
4784 segT sec ATTRIBUTE_UNUSED
;
4787 unsigned char *opcode
;
4788 unsigned char *where_to_put_displacement
= NULL
;
4789 offsetT target_address
;
4790 offsetT opcode_address
;
4791 unsigned int extension
= 0;
4792 offsetT displacement_from_opcode_start
;
4794 opcode
= (unsigned char *) fragP
->fr_opcode
;
4796 /* Address we want to reach in file space. */
4797 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4799 /* Address opcode resides at in file space. */
4800 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4802 /* Displacement from opcode start to fill into instruction. */
4803 displacement_from_opcode_start
= target_address
- opcode_address
;
4805 if ((fragP
->fr_subtype
& BIG
) == 0)
4807 /* Don't have to change opcode. */
4808 extension
= 1; /* 1 opcode + 1 displacement */
4809 where_to_put_displacement
= &opcode
[1];
4813 if (no_cond_jump_promotion
4814 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4815 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4817 switch (fragP
->fr_subtype
)
4819 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4820 extension
= 4; /* 1 opcode + 4 displacement */
4822 where_to_put_displacement
= &opcode
[1];
4825 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4826 extension
= 2; /* 1 opcode + 2 displacement */
4828 where_to_put_displacement
= &opcode
[1];
4831 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4832 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4833 extension
= 5; /* 2 opcode + 4 displacement */
4834 opcode
[1] = opcode
[0] + 0x10;
4835 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4836 where_to_put_displacement
= &opcode
[2];
4839 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4840 extension
= 3; /* 2 opcode + 2 displacement */
4841 opcode
[1] = opcode
[0] + 0x10;
4842 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4843 where_to_put_displacement
= &opcode
[2];
4846 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4851 where_to_put_displacement
= &opcode
[3];
4855 BAD_CASE (fragP
->fr_subtype
);
4860 /* Now put displacement after opcode. */
4861 md_number_to_chars ((char *) where_to_put_displacement
,
4862 (valueT
) (displacement_from_opcode_start
- extension
),
4863 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4864 fragP
->fr_fix
+= extension
;
4867 /* Size of byte displacement jmp. */
4868 int md_short_jump_size
= 2;
4870 /* Size of dword displacement jmp. */
4871 int md_long_jump_size
= 5;
4873 /* Size of relocation record. */
4874 const int md_reloc_size
= 8;
4877 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4879 addressT from_addr
, to_addr
;
4880 fragS
*frag ATTRIBUTE_UNUSED
;
4881 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4885 offset
= to_addr
- (from_addr
+ 2);
4886 /* Opcode for byte-disp jump. */
4887 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4888 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4892 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4894 addressT from_addr
, to_addr
;
4895 fragS
*frag ATTRIBUTE_UNUSED
;
4896 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4900 offset
= to_addr
- (from_addr
+ 5);
4901 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4902 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4905 /* Apply a fixup (fixS) to segment data, once it has been determined
4906 by our caller that we have all the info we need to fix it up.
4908 On the 386, immediates, displacements, and data pointers are all in
4909 the same (little-endian) format, so we don't need to care about which
4913 md_apply_fix (fixP
, valP
, seg
)
4914 /* The fix we're to put in. */
4916 /* Pointer to the value of the bits. */
4918 /* Segment fix is from. */
4919 segT seg ATTRIBUTE_UNUSED
;
4921 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4922 valueT value
= *valP
;
4924 #if !defined (TE_Mach)
4927 switch (fixP
->fx_r_type
)
4933 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
4936 case BFD_RELOC_X86_64_32S
:
4937 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4940 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4943 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4948 if (fixP
->fx_addsy
!= NULL
4949 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4950 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
4951 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4952 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4953 && !use_rela_relocations
)
4955 /* This is a hack. There should be a better way to handle this.
4956 This covers for the fact that bfd_install_relocation will
4957 subtract the current location (for partial_inplace, PC relative
4958 relocations); see more below. */
4962 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4965 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4970 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4973 || (symbol_section_p (fixP
->fx_addsy
)
4974 && sym_seg
!= absolute_section
))
4975 && !generic_force_reloc (fixP
))
4977 /* Yes, we add the values in twice. This is because
4978 bfd_install_relocation subtracts them out again. I think
4979 bfd_install_relocation is broken, but I don't dare change
4981 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4985 #if defined (OBJ_COFF) && defined (TE_PE)
4986 /* For some reason, the PE format does not store a
4987 section address offset for a PC relative symbol. */
4988 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
4989 #if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4990 || S_IS_WEAK (fixP
->fx_addsy
)
4993 value
+= md_pcrel_from (fixP
);
4997 /* Fix a few things - the dynamic linker expects certain values here,
4998 and we must not disappoint it. */
4999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5000 if (IS_ELF
&& fixP
->fx_addsy
)
5001 switch (fixP
->fx_r_type
)
5003 case BFD_RELOC_386_PLT32
:
5004 case BFD_RELOC_X86_64_PLT32
:
5005 /* Make the jump instruction point to the address of the operand. At
5006 runtime we merely add the offset to the actual PLT entry. */
5010 case BFD_RELOC_386_TLS_GD
:
5011 case BFD_RELOC_386_TLS_LDM
:
5012 case BFD_RELOC_386_TLS_IE_32
:
5013 case BFD_RELOC_386_TLS_IE
:
5014 case BFD_RELOC_386_TLS_GOTIE
:
5015 case BFD_RELOC_X86_64_TLSGD
:
5016 case BFD_RELOC_X86_64_TLSLD
:
5017 case BFD_RELOC_X86_64_GOTTPOFF
:
5018 value
= 0; /* Fully resolved at runtime. No addend. */
5020 case BFD_RELOC_386_TLS_LE
:
5021 case BFD_RELOC_386_TLS_LDO_32
:
5022 case BFD_RELOC_386_TLS_LE_32
:
5023 case BFD_RELOC_X86_64_DTPOFF32
:
5024 case BFD_RELOC_X86_64_DTPOFF64
:
5025 case BFD_RELOC_X86_64_TPOFF32
:
5026 case BFD_RELOC_X86_64_TPOFF64
:
5027 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5030 case BFD_RELOC_386_GOT32
:
5031 case BFD_RELOC_X86_64_GOT32
:
5032 value
= 0; /* Fully resolved at runtime. No addend. */
5035 case BFD_RELOC_VTABLE_INHERIT
:
5036 case BFD_RELOC_VTABLE_ENTRY
:
5043 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5045 #endif /* !defined (TE_Mach) */
5047 /* Are we finished with this relocation now? */
5048 if (fixP
->fx_addsy
== NULL
)
5050 else if (use_rela_relocations
)
5052 fixP
->fx_no_overflow
= 1;
5053 /* Remember value for tc_gen_reloc. */
5054 fixP
->fx_addnumber
= value
;
5058 md_number_to_chars (p
, value
, fixP
->fx_size
);
5061 #define MAX_LITTLENUMS 6
5063 /* Turn the string pointed to by litP into a floating point constant
5064 of type TYPE, and emit the appropriate bytes. The number of
5065 LITTLENUMS emitted is stored in *SIZEP. An error message is
5066 returned, or NULL on OK. */
5069 md_atof (type
, litP
, sizeP
)
5075 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5076 LITTLENUM_TYPE
*wordP
;
5098 return _("Bad call to md_atof ()");
5100 t
= atof_ieee (input_line_pointer
, type
, words
);
5102 input_line_pointer
= t
;
5104 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5105 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5106 the bigendian 386. */
5107 for (wordP
= words
+ prec
- 1; prec
--;)
5109 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5110 litP
+= sizeof (LITTLENUM_TYPE
);
5115 static char output_invalid_buf
[8];
5122 sprintf (output_invalid_buf
, "'%c'", c
);
5124 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
5125 return output_invalid_buf
;
5128 /* REG_STRING starts *before* REGISTER_PREFIX. */
5130 static const reg_entry
*
5131 parse_register (reg_string
, end_op
)
5135 char *s
= reg_string
;
5137 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5140 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5141 if (*s
== REGISTER_PREFIX
)
5144 if (is_space_char (*s
))
5148 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5150 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5151 return (const reg_entry
*) NULL
;
5155 /* For naked regs, make sure that we are not dealing with an identifier.
5156 This prevents confusing an identifier like `eax_var' with register
5158 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5159 return (const reg_entry
*) NULL
;
5163 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5165 /* Handle floating point regs, allowing spaces in the (i) part. */
5166 if (r
== i386_regtab
/* %st is first entry of table */)
5168 if (is_space_char (*s
))
5173 if (is_space_char (*s
))
5175 if (*s
>= '0' && *s
<= '7')
5177 r
= &i386_float_regtab
[*s
- '0'];
5179 if (is_space_char (*s
))
5187 /* We have "%st(" then garbage. */
5188 return (const reg_entry
*) NULL
;
5193 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5194 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5195 && flag_code
!= CODE_64BIT
)
5196 return (const reg_entry
*) NULL
;
5201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5202 const char *md_shortopts
= "kVQ:sqn";
5204 const char *md_shortopts
= "qn";
5207 struct option md_longopts
[] = {
5208 #define OPTION_32 (OPTION_MD_BASE + 0)
5209 {"32", no_argument
, NULL
, OPTION_32
},
5210 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5211 #define OPTION_64 (OPTION_MD_BASE + 1)
5212 {"64", no_argument
, NULL
, OPTION_64
},
5214 {NULL
, no_argument
, NULL
, 0}
5216 size_t md_longopts_size
= sizeof (md_longopts
);
5219 md_parse_option (c
, arg
)
5221 char *arg ATTRIBUTE_UNUSED
;
5226 optimize_align_code
= 0;
5233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5234 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5235 should be emitted or not. FIXME: Not implemented. */
5239 /* -V: SVR4 argument to print version ID. */
5241 print_version_id ();
5244 /* -k: Ignore for FreeBSD compatibility. */
5249 /* -s: On i386 Solaris, this tells the native assembler to use
5250 .stab instead of .stab.excl. We always use .stab anyhow. */
5255 const char **list
, **l
;
5257 list
= bfd_target_list ();
5258 for (l
= list
; *l
!= NULL
; l
++)
5259 if (strcmp (*l
, "elf64-x86-64") == 0)
5261 default_arch
= "x86_64";
5265 as_fatal (_("No compiled in support for x86_64"));
5272 default_arch
= "i386";
5282 md_show_usage (stream
)
5285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5286 fprintf (stream
, _("\
5288 -V print assembler version number\n\
5290 -n Do not optimize code alignment\n\
5291 -q quieten some warnings\n\
5294 fprintf (stream
, _("\
5295 -n Do not optimize code alignment\n\
5296 -q quieten some warnings\n"));
5300 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5301 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5303 /* Pick the target format to use. */
5306 i386_target_format ()
5308 if (!strcmp (default_arch
, "x86_64"))
5309 set_code_flag (CODE_64BIT
);
5310 else if (!strcmp (default_arch
, "i386"))
5311 set_code_flag (CODE_32BIT
);
5313 as_fatal (_("Unknown architecture"));
5314 switch (OUTPUT_FLAVOR
)
5316 #ifdef OBJ_MAYBE_AOUT
5317 case bfd_target_aout_flavour
:
5318 return AOUT_TARGET_FORMAT
;
5320 #ifdef OBJ_MAYBE_COFF
5321 case bfd_target_coff_flavour
:
5324 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5325 case bfd_target_elf_flavour
:
5327 if (flag_code
== CODE_64BIT
)
5328 use_rela_relocations
= 1;
5329 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5338 #endif /* OBJ_MAYBE_ more than one */
5340 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5341 void i386_elf_emit_arch_note ()
5343 if (IS_ELF
&& cpu_arch_name
!= NULL
)
5346 asection
*seg
= now_seg
;
5347 subsegT subseg
= now_subseg
;
5348 Elf_Internal_Note i_note
;
5349 Elf_External_Note e_note
;
5350 asection
*note_secp
;
5353 /* Create the .note section. */
5354 note_secp
= subseg_new (".note", 0);
5355 bfd_set_section_flags (stdoutput
,
5357 SEC_HAS_CONTENTS
| SEC_READONLY
);
5359 /* Process the arch string. */
5360 len
= strlen (cpu_arch_name
);
5362 i_note
.namesz
= len
+ 1;
5364 i_note
.type
= NT_ARCH
;
5365 p
= frag_more (sizeof (e_note
.namesz
));
5366 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5367 p
= frag_more (sizeof (e_note
.descsz
));
5368 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5369 p
= frag_more (sizeof (e_note
.type
));
5370 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5371 p
= frag_more (len
+ 1);
5372 strcpy (p
, cpu_arch_name
);
5374 frag_align (2, 0, 0);
5376 subseg_set (seg
, subseg
);
5382 md_undefined_symbol (name
)
5385 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5386 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5387 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5388 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5392 if (symbol_find (name
))
5393 as_bad (_("GOT already in symbol table"));
5394 GOT_symbol
= symbol_new (name
, undefined_section
,
5395 (valueT
) 0, &zero_address_frag
);
5402 /* Round up a section size to the appropriate boundary. */
5405 md_section_align (segment
, size
)
5406 segT segment ATTRIBUTE_UNUSED
;
5409 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5410 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5412 /* For a.out, force the section size to be aligned. If we don't do
5413 this, BFD will align it for us, but it will not write out the
5414 final bytes of the section. This may be a bug in BFD, but it is
5415 easier to fix it here since that is how the other a.out targets
5419 align
= bfd_get_section_alignment (stdoutput
, segment
);
5420 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5427 /* On the i386, PC-relative offsets are relative to the start of the
5428 next instruction. That is, the address of the offset, plus its
5429 size, since the offset is always the last part of the insn. */
5432 md_pcrel_from (fixP
)
5435 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5442 int ignore ATTRIBUTE_UNUSED
;
5446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5448 obj_elf_section_change_hook ();
5450 temp
= get_absolute_expression ();
5451 subseg_set (bss_section
, (subsegT
) temp
);
5452 demand_empty_rest_of_line ();
5458 i386_validate_fix (fixp
)
5461 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5463 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5465 if (flag_code
!= CODE_64BIT
)
5467 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5471 if (flag_code
!= CODE_64BIT
)
5472 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5474 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
5481 tc_gen_reloc (section
, fixp
)
5482 asection
*section ATTRIBUTE_UNUSED
;
5486 bfd_reloc_code_real_type code
;
5488 switch (fixp
->fx_r_type
)
5490 case BFD_RELOC_X86_64_PLT32
:
5491 case BFD_RELOC_X86_64_GOT32
:
5492 case BFD_RELOC_X86_64_GOTPCREL
:
5493 case BFD_RELOC_386_PLT32
:
5494 case BFD_RELOC_386_GOT32
:
5495 case BFD_RELOC_386_GOTOFF
:
5496 case BFD_RELOC_386_GOTPC
:
5497 case BFD_RELOC_386_TLS_GD
:
5498 case BFD_RELOC_386_TLS_LDM
:
5499 case BFD_RELOC_386_TLS_LDO_32
:
5500 case BFD_RELOC_386_TLS_IE_32
:
5501 case BFD_RELOC_386_TLS_IE
:
5502 case BFD_RELOC_386_TLS_GOTIE
:
5503 case BFD_RELOC_386_TLS_LE_32
:
5504 case BFD_RELOC_386_TLS_LE
:
5505 case BFD_RELOC_X86_64_TLSGD
:
5506 case BFD_RELOC_X86_64_TLSLD
:
5507 case BFD_RELOC_X86_64_DTPOFF32
:
5508 case BFD_RELOC_X86_64_DTPOFF64
:
5509 case BFD_RELOC_X86_64_GOTTPOFF
:
5510 case BFD_RELOC_X86_64_TPOFF32
:
5511 case BFD_RELOC_X86_64_TPOFF64
:
5512 case BFD_RELOC_X86_64_GOTOFF64
:
5513 case BFD_RELOC_X86_64_GOTPC32
:
5515 case BFD_RELOC_VTABLE_ENTRY
:
5516 case BFD_RELOC_VTABLE_INHERIT
:
5518 case BFD_RELOC_32_SECREL
:
5520 code
= fixp
->fx_r_type
;
5522 case BFD_RELOC_X86_64_32S
:
5523 if (!fixp
->fx_pcrel
)
5525 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5526 code
= fixp
->fx_r_type
;
5532 switch (fixp
->fx_size
)
5535 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5536 _("can not do %d byte pc-relative relocation"),
5538 code
= BFD_RELOC_32_PCREL
;
5540 case 1: code
= BFD_RELOC_8_PCREL
; break;
5541 case 2: code
= BFD_RELOC_16_PCREL
; break;
5542 case 4: code
= BFD_RELOC_32_PCREL
; break;
5544 case 8: code
= BFD_RELOC_64_PCREL
; break;
5550 switch (fixp
->fx_size
)
5553 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5554 _("can not do %d byte relocation"),
5556 code
= BFD_RELOC_32
;
5558 case 1: code
= BFD_RELOC_8
; break;
5559 case 2: code
= BFD_RELOC_16
; break;
5560 case 4: code
= BFD_RELOC_32
; break;
5562 case 8: code
= BFD_RELOC_64
; break;
5569 if ((code
== BFD_RELOC_32
|| code
== BFD_RELOC_32_PCREL
)
5571 && fixp
->fx_addsy
== GOT_symbol
)
5573 if (flag_code
!= CODE_64BIT
)
5574 code
= BFD_RELOC_386_GOTPC
;
5576 code
= BFD_RELOC_X86_64_GOTPC32
;
5579 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5580 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5581 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5583 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5585 if (!use_rela_relocations
)
5587 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5588 vtable entry to be used in the relocation's section offset. */
5589 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5590 rel
->address
= fixp
->fx_offset
;
5594 /* Use the rela in 64bit mode. */
5597 if (!fixp
->fx_pcrel
)
5598 rel
->addend
= fixp
->fx_offset
;
5602 case BFD_RELOC_X86_64_PLT32
:
5603 case BFD_RELOC_X86_64_GOT32
:
5604 case BFD_RELOC_X86_64_GOTPCREL
:
5605 case BFD_RELOC_X86_64_TLSGD
:
5606 case BFD_RELOC_X86_64_TLSLD
:
5607 case BFD_RELOC_X86_64_GOTTPOFF
:
5608 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5611 rel
->addend
= (section
->vma
5613 + fixp
->fx_addnumber
5614 + md_pcrel_from (fixp
));
5619 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5620 if (rel
->howto
== NULL
)
5622 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5623 _("cannot represent relocation type %s"),
5624 bfd_get_reloc_code_name (code
));
5625 /* Set howto to a garbage value so that we can keep going. */
5626 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5627 assert (rel
->howto
!= NULL
);
5634 /* Parse operands using Intel syntax. This implements a recursive descent
5635 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5638 FIXME: We do not recognize the full operand grammar defined in the MASM
5639 documentation. In particular, all the structure/union and
5640 high-level macro operands are missing.
5642 Uppercase words are terminals, lower case words are non-terminals.
5643 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5644 bars '|' denote choices. Most grammar productions are implemented in
5645 functions called 'intel_<production>'.
5647 Initial production is 'expr'.
5653 binOp & | AND | \| | OR | ^ | XOR
5655 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5657 constant digits [[ radixOverride ]]
5659 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5697 => expr expr cmpOp e04
5700 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5701 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5703 hexdigit a | b | c | d | e | f
5704 | A | B | C | D | E | F
5710 mulOp * | / | % | MOD | << | SHL | >> | SHR
5714 register specialRegister
5718 segmentRegister CS | DS | ES | FS | GS | SS
5720 specialRegister CR0 | CR2 | CR3 | CR4
5721 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5722 | TR3 | TR4 | TR5 | TR6 | TR7
5724 We simplify the grammar in obvious places (e.g., register parsing is
5725 done by calling parse_register) and eliminate immediate left recursion
5726 to implement a recursive-descent parser.
5730 expr' cmpOp e04 expr'
5781 /* Parsing structure for the intel syntax parser. Used to implement the
5782 semantic actions for the operand grammar. */
5783 struct intel_parser_s
5785 char *op_string
; /* The string being parsed. */
5786 int got_a_float
; /* Whether the operand is a float. */
5787 int op_modifier
; /* Operand modifier. */
5788 int is_mem
; /* 1 if operand is memory reference. */
5789 int in_offset
; /* >=1 if parsing operand of offset. */
5790 int in_bracket
; /* >=1 if parsing operand in brackets. */
5791 const reg_entry
*reg
; /* Last register reference found. */
5792 char *disp
; /* Displacement string being built. */
5793 char *next_operand
; /* Resume point when splitting operands. */
5796 static struct intel_parser_s intel_parser
;
5798 /* Token structure for parsing intel syntax. */
5801 int code
; /* Token code. */
5802 const reg_entry
*reg
; /* Register entry for register tokens. */
5803 char *str
; /* String representation. */
5806 static struct intel_token cur_token
, prev_token
;
5808 /* Token codes for the intel parser. Since T_SHORT is already used
5809 by COFF, undefine it first to prevent a warning. */
5828 /* Prototypes for intel parser functions. */
5829 static int intel_match_token
PARAMS ((int code
));
5830 static void intel_get_token
PARAMS ((void));
5831 static void intel_putback_token
PARAMS ((void));
5832 static int intel_expr
PARAMS ((void));
5833 static int intel_e04
PARAMS ((void));
5834 static int intel_e05
PARAMS ((void));
5835 static int intel_e06
PARAMS ((void));
5836 static int intel_e09
PARAMS ((void));
5837 static int intel_bracket_expr
PARAMS ((void));
5838 static int intel_e10
PARAMS ((void));
5839 static int intel_e11
PARAMS ((void));
5842 i386_intel_operand (operand_string
, got_a_float
)
5843 char *operand_string
;
5849 p
= intel_parser
.op_string
= xstrdup (operand_string
);
5850 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
5854 /* Initialize token holders. */
5855 cur_token
.code
= prev_token
.code
= T_NIL
;
5856 cur_token
.reg
= prev_token
.reg
= NULL
;
5857 cur_token
.str
= prev_token
.str
= NULL
;
5859 /* Initialize parser structure. */
5860 intel_parser
.got_a_float
= got_a_float
;
5861 intel_parser
.op_modifier
= 0;
5862 intel_parser
.is_mem
= 0;
5863 intel_parser
.in_offset
= 0;
5864 intel_parser
.in_bracket
= 0;
5865 intel_parser
.reg
= NULL
;
5866 intel_parser
.disp
[0] = '\0';
5867 intel_parser
.next_operand
= NULL
;
5869 /* Read the first token and start the parser. */
5871 ret
= intel_expr ();
5876 if (cur_token
.code
!= T_NIL
)
5878 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5879 current_templates
->start
->name
, cur_token
.str
);
5882 /* If we found a memory reference, hand it over to i386_displacement
5883 to fill in the rest of the operand fields. */
5884 else if (intel_parser
.is_mem
)
5886 if ((i
.mem_operands
== 1
5887 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5888 || i
.mem_operands
== 2)
5890 as_bad (_("too many memory references for '%s'"),
5891 current_templates
->start
->name
);
5896 char *s
= intel_parser
.disp
;
5899 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
5900 /* See the comments in intel_bracket_expr. */
5901 as_warn (_("Treating `%s' as memory reference"), operand_string
);
5903 /* Add the displacement expression. */
5905 ret
= i386_displacement (s
, s
+ strlen (s
));
5908 /* Swap base and index in 16-bit memory operands like
5909 [si+bx]. Since i386_index_check is also used in AT&T
5910 mode we have to do that here. */
5913 && (i
.base_reg
->reg_type
& Reg16
)
5914 && (i
.index_reg
->reg_type
& Reg16
)
5915 && i
.base_reg
->reg_num
>= 6
5916 && i
.index_reg
->reg_num
< 6)
5918 const reg_entry
*base
= i
.index_reg
;
5920 i
.index_reg
= i
.base_reg
;
5923 ret
= i386_index_check (operand_string
);
5928 /* Constant and OFFSET expressions are handled by i386_immediate. */
5929 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
5930 || intel_parser
.reg
== NULL
)
5931 ret
= i386_immediate (intel_parser
.disp
);
5933 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
5935 if (!ret
|| !intel_parser
.next_operand
)
5937 intel_parser
.op_string
= intel_parser
.next_operand
;
5938 this_operand
= i
.operands
++;
5942 free (intel_parser
.disp
);
5947 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5951 expr' cmpOp e04 expr'
5956 /* XXX Implement the comparison operators. */
5957 return intel_e04 ();
5974 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
5975 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
5977 if (cur_token
.code
== '+')
5979 else if (cur_token
.code
== '-')
5980 nregs
= NUM_ADDRESS_REGS
;
5984 strcat (intel_parser
.disp
, cur_token
.str
);
5985 intel_match_token (cur_token
.code
);
5996 int nregs
= ~NUM_ADDRESS_REGS
;
6003 if (cur_token
.code
== '&' || cur_token
.code
== '|' || cur_token
.code
== '^')
6007 str
[0] = cur_token
.code
;
6009 strcat (intel_parser
.disp
, str
);
6014 intel_match_token (cur_token
.code
);
6019 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6020 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6031 int nregs
= ~NUM_ADDRESS_REGS
;
6038 if (cur_token
.code
== '*' || cur_token
.code
== '/' || cur_token
.code
== '%')
6042 str
[0] = cur_token
.code
;
6044 strcat (intel_parser
.disp
, str
);
6046 else if (cur_token
.code
== T_SHL
)
6047 strcat (intel_parser
.disp
, "<<");
6048 else if (cur_token
.code
== T_SHR
)
6049 strcat (intel_parser
.disp
, ">>");
6053 intel_match_token (cur_token
.code
);
6058 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6059 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6077 int nregs
= ~NUM_ADDRESS_REGS
;
6082 /* Don't consume constants here. */
6083 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6085 /* Need to look one token ahead - if the next token
6086 is a constant, the current token is its sign. */
6089 intel_match_token (cur_token
.code
);
6090 next_code
= cur_token
.code
;
6091 intel_putback_token ();
6092 if (next_code
== T_CONST
)
6096 /* e09 OFFSET e09 */
6097 if (cur_token
.code
== T_OFFSET
)
6100 ++intel_parser
.in_offset
;
6104 else if (cur_token
.code
== T_SHORT
)
6105 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6108 else if (cur_token
.code
== '+')
6109 strcat (intel_parser
.disp
, "+");
6114 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6120 str
[0] = cur_token
.code
;
6122 strcat (intel_parser
.disp
, str
);
6129 intel_match_token (cur_token
.code
);
6137 /* e09' PTR e10 e09' */
6138 if (cur_token
.code
== T_PTR
)
6142 if (prev_token
.code
== T_BYTE
)
6143 suffix
= BYTE_MNEM_SUFFIX
;
6145 else if (prev_token
.code
== T_WORD
)
6147 if (current_templates
->start
->name
[0] == 'l'
6148 && current_templates
->start
->name
[2] == 's'
6149 && current_templates
->start
->name
[3] == 0)
6150 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6151 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
6152 suffix
= SHORT_MNEM_SUFFIX
;
6154 suffix
= WORD_MNEM_SUFFIX
;
6157 else if (prev_token
.code
== T_DWORD
)
6159 if (current_templates
->start
->name
[0] == 'l'
6160 && current_templates
->start
->name
[2] == 's'
6161 && current_templates
->start
->name
[3] == 0)
6162 suffix
= WORD_MNEM_SUFFIX
;
6163 else if (flag_code
== CODE_16BIT
6164 && (current_templates
->start
->opcode_modifier
6165 & (Jump
|JumpDword
|JumpInterSegment
)))
6166 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6167 else if (intel_parser
.got_a_float
== 1) /* "f..." */
6168 suffix
= SHORT_MNEM_SUFFIX
;
6170 suffix
= LONG_MNEM_SUFFIX
;
6173 else if (prev_token
.code
== T_FWORD
)
6175 if (current_templates
->start
->name
[0] == 'l'
6176 && current_templates
->start
->name
[2] == 's'
6177 && current_templates
->start
->name
[3] == 0)
6178 suffix
= LONG_MNEM_SUFFIX
;
6179 else if (!intel_parser
.got_a_float
)
6181 if (flag_code
== CODE_16BIT
)
6182 add_prefix (DATA_PREFIX_OPCODE
);
6183 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6186 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6189 else if (prev_token
.code
== T_QWORD
)
6191 if (intel_parser
.got_a_float
== 1) /* "f..." */
6192 suffix
= LONG_MNEM_SUFFIX
;
6194 suffix
= QWORD_MNEM_SUFFIX
;
6197 else if (prev_token
.code
== T_TBYTE
)
6199 if (intel_parser
.got_a_float
== 1)
6200 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
6202 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
6205 else if (prev_token
.code
== T_XMMWORD
)
6207 /* XXX ignored for now, but accepted since gcc uses it */
6213 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
6217 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
6221 else if (i
.suffix
!= suffix
)
6223 as_bad (_("Conflicting operand modifiers"));
6229 /* e09' : e10 e09' */
6230 else if (cur_token
.code
== ':')
6232 if (prev_token
.code
!= T_REG
)
6234 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6235 segment/group identifier (which we don't have), using comma
6236 as the operand separator there is even less consistent, since
6237 there all branches only have a single operand. */
6238 if (this_operand
!= 0
6239 || intel_parser
.in_offset
6240 || intel_parser
.in_bracket
6241 || (!(current_templates
->start
->opcode_modifier
6242 & (Jump
|JumpDword
|JumpInterSegment
))
6243 && !(current_templates
->start
->operand_types
[0]
6245 return intel_match_token (T_NIL
);
6246 /* Remember the start of the 2nd operand and terminate 1st
6248 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6249 another expression), but it gets at least the simplest case
6250 (a plain number or symbol on the left side) right. */
6251 intel_parser
.next_operand
= intel_parser
.op_string
;
6252 *--intel_parser
.op_string
= '\0';
6253 return intel_match_token (':');
6261 intel_match_token (cur_token
.code
);
6267 --intel_parser
.in_offset
;
6270 if (NUM_ADDRESS_REGS
> nregs
)
6272 as_bad (_("Invalid operand to `OFFSET'"));
6275 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
6278 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6279 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
6284 intel_bracket_expr ()
6286 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
6287 const char *start
= intel_parser
.op_string
;
6290 if (i
.op
[this_operand
].regs
)
6291 return intel_match_token (T_NIL
);
6293 intel_match_token ('[');
6295 /* Mark as a memory operand only if it's not already known to be an
6296 offset expression. If it's an offset expression, we need to keep
6298 if (!intel_parser
.in_offset
)
6300 ++intel_parser
.in_bracket
;
6301 /* Unfortunately gas always diverged from MASM in a respect that can't
6302 be easily fixed without risking to break code sequences likely to be
6303 encountered (the testsuite even check for this): MASM doesn't consider
6304 an expression inside brackets unconditionally as a memory reference.
6305 When that is e.g. a constant, an offset expression, or the sum of the
6306 two, this is still taken as a constant load. gas, however, always
6307 treated these as memory references. As a compromise, we'll try to make
6308 offset expressions inside brackets work the MASM way (since that's
6309 less likely to be found in real world code), but make constants alone
6310 continue to work the traditional gas way. In either case, issue a
6312 intel_parser
.op_modifier
&= ~was_offset
;
6315 strcat (intel_parser
.disp
, "[");
6317 /* Add a '+' to the displacement string if necessary. */
6318 if (*intel_parser
.disp
!= '\0'
6319 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
6320 strcat (intel_parser
.disp
, "+");
6323 && (len
= intel_parser
.op_string
- start
- 1,
6324 intel_match_token (']')))
6326 /* Preserve brackets when the operand is an offset expression. */
6327 if (intel_parser
.in_offset
)
6328 strcat (intel_parser
.disp
, "]");
6331 --intel_parser
.in_bracket
;
6332 if (i
.base_reg
|| i
.index_reg
)
6333 intel_parser
.is_mem
= 1;
6334 if (!intel_parser
.is_mem
)
6336 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
6337 /* Defer the warning until all of the operand was parsed. */
6338 intel_parser
.is_mem
= -1;
6339 else if (!quiet_warnings
)
6340 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len
, start
, len
, start
);
6343 intel_parser
.op_modifier
|= was_offset
;
6360 while (cur_token
.code
== '[')
6362 if (!intel_bracket_expr ())
6387 switch (cur_token
.code
)
6391 intel_match_token ('(');
6392 strcat (intel_parser
.disp
, "(");
6394 if (intel_expr () && intel_match_token (')'))
6396 strcat (intel_parser
.disp
, ")");
6403 /* Operands for jump/call inside brackets denote absolute addresses.
6404 XXX This shouldn't be needed anymore (or if it should rather live
6405 in intel_bracket_expr). */
6406 if (current_templates
->start
->opcode_modifier
6407 & (Jump
|JumpDword
|JumpByte
|JumpInterSegment
))
6408 i
.types
[this_operand
] |= JumpAbsolute
;
6410 return intel_bracket_expr ();
6415 strcat (intel_parser
.disp
, cur_token
.str
);
6416 intel_match_token (cur_token
.code
);
6418 /* Mark as a memory operand only if it's not already known to be an
6419 offset expression. */
6420 if (!intel_parser
.in_offset
)
6421 intel_parser
.is_mem
= 1;
6428 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
6430 intel_match_token (T_REG
);
6432 /* Check for segment change. */
6433 if (cur_token
.code
== ':')
6435 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
6437 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
6440 else if (i
.seg
[i
.mem_operands
])
6441 as_warn (_("Extra segment override ignored"));
6444 if (!intel_parser
.in_offset
)
6445 intel_parser
.is_mem
= 1;
6446 switch (reg
->reg_num
)
6449 i
.seg
[i
.mem_operands
] = &es
;
6452 i
.seg
[i
.mem_operands
] = &cs
;
6455 i
.seg
[i
.mem_operands
] = &ss
;
6458 i
.seg
[i
.mem_operands
] = &ds
;
6461 i
.seg
[i
.mem_operands
] = &fs
;
6464 i
.seg
[i
.mem_operands
] = &gs
;
6470 /* Not a segment register. Check for register scaling. */
6471 else if (cur_token
.code
== '*')
6473 if (!intel_parser
.in_bracket
)
6475 as_bad (_("Register scaling only allowed in memory operands"));
6479 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
6480 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6481 else if (i
.index_reg
)
6482 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6484 /* What follows must be a valid scale. */
6485 intel_match_token ('*');
6487 i
.types
[this_operand
] |= BaseIndex
;
6489 /* Set the scale after setting the register (otherwise,
6490 i386_scale will complain) */
6491 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6493 char *str
, sign
= cur_token
.code
;
6494 intel_match_token (cur_token
.code
);
6495 if (cur_token
.code
!= T_CONST
)
6497 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6501 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6502 strcpy (str
+ 1, cur_token
.str
);
6504 if (!i386_scale (str
))
6508 else if (!i386_scale (cur_token
.str
))
6510 intel_match_token (cur_token
.code
);
6513 /* No scaling. If this is a memory operand, the register is either a
6514 base register (first occurrence) or an index register (second
6516 else if (intel_parser
.in_bracket
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
6521 else if (!i
.index_reg
)
6525 as_bad (_("Too many register references in memory operand"));
6529 i
.types
[this_operand
] |= BaseIndex
;
6532 /* Offset modifier. Add the register to the displacement string to be
6533 parsed as an immediate expression after we're done. */
6534 else if (intel_parser
.in_offset
)
6536 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6537 strcat (intel_parser
.disp
, reg
->reg_name
);
6540 /* It's neither base nor index nor offset. */
6541 else if (!intel_parser
.is_mem
)
6543 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6544 i
.op
[this_operand
].regs
= reg
;
6549 as_bad (_("Invalid use of register"));
6553 /* Since registers are not part of the displacement string (except
6554 when we're parsing offset operands), we may need to remove any
6555 preceding '+' from the displacement string. */
6556 if (*intel_parser
.disp
!= '\0'
6557 && !intel_parser
.in_offset
)
6559 char *s
= intel_parser
.disp
;
6560 s
+= strlen (s
) - 1;
6583 intel_match_token (cur_token
.code
);
6585 if (cur_token
.code
== T_PTR
)
6588 /* It must have been an identifier. */
6589 intel_putback_token ();
6590 cur_token
.code
= T_ID
;
6596 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
6600 /* The identifier represents a memory reference only if it's not
6601 preceded by an offset modifier and if it's not an equate. */
6602 symbolP
= symbol_find(cur_token
.str
);
6603 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
6604 intel_parser
.is_mem
= 1;
6612 char *save_str
, sign
= 0;
6614 /* Allow constants that start with `+' or `-'. */
6615 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6617 sign
= cur_token
.code
;
6618 intel_match_token (cur_token
.code
);
6619 if (cur_token
.code
!= T_CONST
)
6621 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6627 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
6628 strcpy (save_str
+ !!sign
, cur_token
.str
);
6632 /* Get the next token to check for register scaling. */
6633 intel_match_token (cur_token
.code
);
6635 /* Check if this constant is a scaling factor for an index register. */
6636 if (cur_token
.code
== '*')
6638 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6640 const reg_entry
*reg
= cur_token
.reg
;
6642 if (!intel_parser
.in_bracket
)
6644 as_bad (_("Register scaling only allowed in memory operands"));
6648 if (reg
->reg_type
& Reg16
) /* Disallow things like [1*si]. */
6649 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
6650 else if (i
.index_reg
)
6651 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
6653 /* The constant is followed by `* reg', so it must be
6656 i
.types
[this_operand
] |= BaseIndex
;
6658 /* Set the scale after setting the register (otherwise,
6659 i386_scale will complain) */
6660 if (!i386_scale (save_str
))
6662 intel_match_token (T_REG
);
6664 /* Since registers are not part of the displacement
6665 string, we may need to remove any preceding '+' from
6666 the displacement string. */
6667 if (*intel_parser
.disp
!= '\0')
6669 char *s
= intel_parser
.disp
;
6670 s
+= strlen (s
) - 1;
6680 /* The constant was not used for register scaling. Since we have
6681 already consumed the token following `*' we now need to put it
6682 back in the stream. */
6683 intel_putback_token ();
6686 /* Add the constant to the displacement string. */
6687 strcat (intel_parser
.disp
, save_str
);
6694 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6698 /* Match the given token against cur_token. If they match, read the next
6699 token from the operand string. */
6701 intel_match_token (code
)
6704 if (cur_token
.code
== code
)
6711 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6716 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6721 const reg_entry
*reg
;
6722 struct intel_token new_token
;
6724 new_token
.code
= T_NIL
;
6725 new_token
.reg
= NULL
;
6726 new_token
.str
= NULL
;
6728 /* Free the memory allocated to the previous token and move
6729 cur_token to prev_token. */
6731 free (prev_token
.str
);
6733 prev_token
= cur_token
;
6735 /* Skip whitespace. */
6736 while (is_space_char (*intel_parser
.op_string
))
6737 intel_parser
.op_string
++;
6739 /* Return an empty token if we find nothing else on the line. */
6740 if (*intel_parser
.op_string
== '\0')
6742 cur_token
= new_token
;
6746 /* The new token cannot be larger than the remainder of the operand
6748 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
6749 new_token
.str
[0] = '\0';
6751 if (strchr ("0123456789", *intel_parser
.op_string
))
6753 char *p
= new_token
.str
;
6754 char *q
= intel_parser
.op_string
;
6755 new_token
.code
= T_CONST
;
6757 /* Allow any kind of identifier char to encompass floating point and
6758 hexadecimal numbers. */
6759 while (is_identifier_char (*q
))
6763 /* Recognize special symbol names [0-9][bf]. */
6764 if (strlen (intel_parser
.op_string
) == 2
6765 && (intel_parser
.op_string
[1] == 'b'
6766 || intel_parser
.op_string
[1] == 'f'))
6767 new_token
.code
= T_ID
;
6770 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6771 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6773 new_token
.code
= T_REG
;
6774 new_token
.reg
= reg
;
6776 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6778 new_token
.str
[0] = REGISTER_PREFIX
;
6779 new_token
.str
[1] = '\0';
6782 strcat (new_token
.str
, reg
->reg_name
);
6785 else if (is_identifier_char (*intel_parser
.op_string
))
6787 char *p
= new_token
.str
;
6788 char *q
= intel_parser
.op_string
;
6790 /* A '.' or '$' followed by an identifier char is an identifier.
6791 Otherwise, it's operator '.' followed by an expression. */
6792 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6794 new_token
.code
= '.';
6795 new_token
.str
[0] = '.';
6796 new_token
.str
[1] = '\0';
6800 while (is_identifier_char (*q
) || *q
== '@')
6804 if (strcasecmp (new_token
.str
, "NOT") == 0)
6805 new_token
.code
= '~';
6807 else if (strcasecmp (new_token
.str
, "MOD") == 0)
6808 new_token
.code
= '%';
6810 else if (strcasecmp (new_token
.str
, "AND") == 0)
6811 new_token
.code
= '&';
6813 else if (strcasecmp (new_token
.str
, "OR") == 0)
6814 new_token
.code
= '|';
6816 else if (strcasecmp (new_token
.str
, "XOR") == 0)
6817 new_token
.code
= '^';
6819 else if (strcasecmp (new_token
.str
, "SHL") == 0)
6820 new_token
.code
= T_SHL
;
6822 else if (strcasecmp (new_token
.str
, "SHR") == 0)
6823 new_token
.code
= T_SHR
;
6825 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
6826 new_token
.code
= T_BYTE
;
6828 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6829 new_token
.code
= T_WORD
;
6831 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6832 new_token
.code
= T_DWORD
;
6834 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
6835 new_token
.code
= T_FWORD
;
6837 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6838 new_token
.code
= T_QWORD
;
6840 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
6841 /* XXX remove (gcc still uses it) */
6842 || strcasecmp (new_token
.str
, "XWORD") == 0)
6843 new_token
.code
= T_TBYTE
;
6845 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
6846 || strcasecmp (new_token
.str
, "OWORD") == 0)
6847 new_token
.code
= T_XMMWORD
;
6849 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6850 new_token
.code
= T_PTR
;
6852 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6853 new_token
.code
= T_SHORT
;
6855 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6857 new_token
.code
= T_OFFSET
;
6859 /* ??? This is not mentioned in the MASM grammar but gcc
6860 makes use of it with -mintel-syntax. OFFSET may be
6861 followed by FLAT: */
6862 if (strncasecmp (q
, " FLAT:", 6) == 0)
6863 strcat (new_token
.str
, " FLAT:");
6866 /* ??? This is not mentioned in the MASM grammar. */
6867 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6869 new_token
.code
= T_OFFSET
;
6871 strcat (new_token
.str
, ":");
6873 as_bad (_("`:' expected"));
6877 new_token
.code
= T_ID
;
6881 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
6883 new_token
.code
= *intel_parser
.op_string
;
6884 new_token
.str
[0] = *intel_parser
.op_string
;
6885 new_token
.str
[1] = '\0';
6888 else if (strchr ("<>", *intel_parser
.op_string
)
6889 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6891 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
6892 new_token
.str
[0] = *intel_parser
.op_string
;
6893 new_token
.str
[1] = *intel_parser
.op_string
;
6894 new_token
.str
[2] = '\0';
6898 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6900 intel_parser
.op_string
+= strlen (new_token
.str
);
6901 cur_token
= new_token
;
6904 /* Put cur_token back into the token stream and make cur_token point to
6907 intel_putback_token ()
6909 if (cur_token
.code
!= T_NIL
)
6911 intel_parser
.op_string
-= strlen (cur_token
.str
);
6912 free (cur_token
.str
);
6914 cur_token
= prev_token
;
6916 /* Forget prev_token. */
6917 prev_token
.code
= T_NIL
;
6918 prev_token
.reg
= NULL
;
6919 prev_token
.str
= NULL
;
6923 tc_x86_regname_to_dw2regnum (const char *regname
)
6925 unsigned int regnum
;
6926 unsigned int regnames_count
;
6927 static const char *const regnames_32
[] =
6929 "eax", "ecx", "edx", "ebx",
6930 "esp", "ebp", "esi", "edi",
6931 "eip", "eflags", NULL
,
6932 "st0", "st1", "st2", "st3",
6933 "st4", "st5", "st6", "st7",
6935 "xmm0", "xmm1", "xmm2", "xmm3",
6936 "xmm4", "xmm5", "xmm6", "xmm7",
6937 "mm0", "mm1", "mm2", "mm3",
6938 "mm4", "mm5", "mm6", "mm7"
6940 static const char *const regnames_64
[] =
6942 "rax", "rdx", "rcx", "rbx",
6943 "rsi", "rdi", "rbp", "rsp",
6944 "r8", "r9", "r10", "r11",
6945 "r12", "r13", "r14", "r15",
6947 "xmm0", "xmm1", "xmm2", "xmm3",
6948 "xmm4", "xmm5", "xmm6", "xmm7",
6949 "xmm8", "xmm9", "xmm10", "xmm11",
6950 "xmm12", "xmm13", "xmm14", "xmm15",
6951 "st0", "st1", "st2", "st3",
6952 "st4", "st5", "st6", "st7",
6953 "mm0", "mm1", "mm2", "mm3",
6954 "mm4", "mm5", "mm6", "mm7"
6956 const char *const *regnames
;
6958 if (flag_code
== CODE_64BIT
)
6960 regnames
= regnames_64
;
6961 regnames_count
= ARRAY_SIZE (regnames_64
);
6965 regnames
= regnames_32
;
6966 regnames_count
= ARRAY_SIZE (regnames_32
);
6969 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6970 if (regnames
[regnum
] != NULL
6971 && strcmp (regname
, regnames
[regnum
]) == 0)
6978 tc_x86_frame_initial_instructions (void)
6980 static unsigned int sp_regno
;
6983 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6986 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6987 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6991 i386_elf_section_type (const char *str
, size_t len
)
6993 if (flag_code
== CODE_64BIT
6994 && len
== sizeof ("unwind") - 1
6995 && strncmp (str
, "unwind", 6) == 0)
6996 return SHT_X86_64_UNWIND
;
7003 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7007 expr
.X_op
= O_secrel
;
7008 expr
.X_add_symbol
= symbol
;
7009 expr
.X_add_number
= 0;
7010 emit_expr (&expr
, size
);
7014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7015 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7018 x86_64_section_letter (int letter
, char **ptr_msg
)
7020 if (flag_code
== CODE_64BIT
)
7023 return SHF_X86_64_LARGE
;
7025 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7028 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7033 x86_64_section_word (char *str
, size_t len
)
7035 if (len
== 5 && flag_code
== CODE_64BIT
&& strncmp (str
, "large", 5) == 0)
7036 return SHF_X86_64_LARGE
;
7042 handle_large_common (int small ATTRIBUTE_UNUSED
)
7044 if (flag_code
!= CODE_64BIT
)
7046 s_comm_internal (0, elf_common_parse
);
7047 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7051 static segT lbss_section
;
7052 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7053 asection
*saved_bss_section
= bss_section
;
7055 if (lbss_section
== NULL
)
7057 flagword applicable
;
7059 subsegT subseg
= now_subseg
;
7061 /* The .lbss section is for local .largecomm symbols. */
7062 lbss_section
= subseg_new (".lbss", 0);
7063 applicable
= bfd_applicable_section_flags (stdoutput
);
7064 bfd_set_section_flags (stdoutput
, lbss_section
,
7065 applicable
& SEC_ALLOC
);
7066 seg_info (lbss_section
)->bss
= 1;
7068 subseg_set (seg
, subseg
);
7071 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7072 bss_section
= lbss_section
;
7074 s_comm_internal (0, elf_common_parse
);
7076 elf_com_section_ptr
= saved_com_section_ptr
;
7077 bss_section
= saved_bss_section
;
7080 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */