1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
136 unsigned int negated
; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c
);
153 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
155 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS
*);
160 static int i386_intel_parse_name (const char *, expressionS
*);
161 static const reg_entry
*parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template
*match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry
*build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS
*, offsetT
);
180 static void output_disp (fragS
*, offsetT
);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
188 static const char *default_arch
= DEFAULT_ARCH
;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op
;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry
*mask
;
212 unsigned int zeroing
;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op
;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op
;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes
[4];
238 /* Destination or source register specifier. */
239 const reg_entry
*register_specifier
;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry
*regs
;
254 operand_size_mismatch
,
255 operand_type_mismatch
,
256 register_type_mismatch
,
257 number_of_operands_mismatch
,
258 invalid_instruction_suffix
,
261 unsupported_with_intel_mnemonic
,
264 invalid_vsib_address
,
265 invalid_vector_register_set
,
266 unsupported_vector_index_register
,
267 unsupported_broadcast
,
268 broadcast_not_on_src_operand
,
271 mask_not_on_destination
,
274 rc_sae_operand_not_last_imm
,
275 invalid_register_operand
,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands
;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types
[MAX_OPERANDS
];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op
[MAX_OPERANDS
];
304 /* Flags for operands. */
305 unsigned int flags
[MAX_OPERANDS
];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry
*base_reg
;
314 const reg_entry
*index_reg
;
315 unsigned int log2_scale_factor
;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry
*seg
[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes
;
324 unsigned char prefix
[MAX_PREFIXES
];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation
*mask
;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation
*rounding
;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation
*broadcast
;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift
;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand
;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default
= 0,
358 const char *rep_prefix
;
361 const char *hle_prefix
;
363 /* Have BND prefix. */
364 const char *bnd_prefix
;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error
;
373 typedef struct _i386_insn i386_insn
;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable
[] =
386 { rne
, STRING_COMMA_LEN ("rn-sae") },
387 { rd
, STRING_COMMA_LEN ("rd-sae") },
388 { ru
, STRING_COMMA_LEN ("ru-sae") },
389 { rz
, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly
, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars
[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars
= "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars
= "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars
[] = "#/";
435 const char line_separator_chars
[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS
[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS
[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars
[256];
448 static char register_chars
[256];
449 static char operand_chars
[256];
450 static char identifier_chars
[256];
451 static char digit_chars
[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack
[32];
469 static char *save_stack_p
;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates
*current_templates
;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
483 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
485 /* Current operand we are working on. */
486 static int this_operand
= -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code
;
497 static unsigned int object_64bit
;
498 static unsigned int disallow_64bit_reloc
;
499 static int use_rela_relocations
= 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj
= 0;
521 /* 1 for intel syntax,
523 static int intel_syntax
= 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic
= !SYSV386_COMPAT
;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc
= OLDGCC_COMPAT
;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg
= 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg
= 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix
= 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg
= 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix
= 0;
550 static enum check_kind
556 sse_check
, operand_check
= check_warning
;
558 /* Register prefix used for error message. */
559 static const char *register_prefix
= "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size
= '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code
= 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings
= 0;
573 static const char *cpu_arch_name
= NULL
;
574 static char *cpu_sub_arch_name
= NULL
;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set
= 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags
;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags
;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion
= 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx
;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig
= rne
;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS
*GOT_symbol
;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column
;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment
;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table
[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch
[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
719 CPU_GENERIC32_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
721 CPU_GENERIC64_FLAGS
, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
723 CPU_NONE_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
725 CPU_I186_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
727 CPU_I286_FLAGS
, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
729 CPU_I386_FLAGS
, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
731 CPU_I486_FLAGS
, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
733 CPU_I586_FLAGS
, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
735 CPU_I686_FLAGS
, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
737 CPU_I586_FLAGS
, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
739 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
741 CPU_P2_FLAGS
, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
743 CPU_P3_FLAGS
, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
745 CPU_P4_FLAGS
, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
747 CPU_CORE_FLAGS
, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
749 CPU_NOCONA_FLAGS
, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
751 CPU_CORE_FLAGS
, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
753 CPU_CORE_FLAGS
, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
755 CPU_CORE2_FLAGS
, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
757 CPU_CORE2_FLAGS
, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
759 CPU_COREI7_FLAGS
, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
761 CPU_L1OM_FLAGS
, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
763 CPU_K1OM_FLAGS
, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
765 CPU_K6_FLAGS
, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
767 CPU_K6_2_FLAGS
, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
769 CPU_ATHLON_FLAGS
, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
771 CPU_K8_FLAGS
, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
773 CPU_K8_FLAGS
, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
775 CPU_K8_FLAGS
, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
777 CPU_AMDFAM10_FLAGS
, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
779 CPU_BDVER1_FLAGS
, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
781 CPU_BDVER2_FLAGS
, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
783 CPU_BDVER3_FLAGS
, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
785 CPU_BDVER4_FLAGS
, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
787 CPU_BTVER1_FLAGS
, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
789 CPU_BTVER2_FLAGS
, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
791 CPU_8087_FLAGS
, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
793 CPU_287_FLAGS
, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
795 CPU_387_FLAGS
, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
797 CPU_ANY87_FLAGS
, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
799 CPU_MMX_FLAGS
, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
801 CPU_3DNOWA_FLAGS
, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
803 CPU_SSE_FLAGS
, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
805 CPU_SSE2_FLAGS
, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
807 CPU_SSE3_FLAGS
, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
809 CPU_SSSE3_FLAGS
, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
811 CPU_SSE4_1_FLAGS
, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
813 CPU_SSE4_2_FLAGS
, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
815 CPU_SSE4_2_FLAGS
, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
817 CPU_ANY_SSE_FLAGS
, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
819 CPU_AVX_FLAGS
, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
821 CPU_AVX2_FLAGS
, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
823 CPU_AVX512F_FLAGS
, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
825 CPU_AVX512CD_FLAGS
, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
827 CPU_AVX512ER_FLAGS
, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
829 CPU_AVX512PF_FLAGS
, 0, 0 },
830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
831 CPU_AVX512DQ_FLAGS
, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
833 CPU_AVX512BW_FLAGS
, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
835 CPU_AVX512VL_FLAGS
, 0, 0 },
836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
837 CPU_ANY_AVX_FLAGS
, 0, 1 },
838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
839 CPU_VMX_FLAGS
, 0, 0 },
840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
841 CPU_VMFUNC_FLAGS
, 0, 0 },
842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
843 CPU_SMX_FLAGS
, 0, 0 },
844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
845 CPU_XSAVE_FLAGS
, 0, 0 },
846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
847 CPU_XSAVEOPT_FLAGS
, 0, 0 },
848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
849 CPU_XSAVEC_FLAGS
, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
851 CPU_XSAVES_FLAGS
, 0, 0 },
852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
853 CPU_AES_FLAGS
, 0, 0 },
854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
855 CPU_PCLMUL_FLAGS
, 0, 0 },
856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
857 CPU_PCLMUL_FLAGS
, 1, 0 },
858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
859 CPU_FSGSBASE_FLAGS
, 0, 0 },
860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
861 CPU_RDRND_FLAGS
, 0, 0 },
862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
863 CPU_F16C_FLAGS
, 0, 0 },
864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
865 CPU_BMI2_FLAGS
, 0, 0 },
866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
867 CPU_FMA_FLAGS
, 0, 0 },
868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
869 CPU_FMA4_FLAGS
, 0, 0 },
870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
871 CPU_XOP_FLAGS
, 0, 0 },
872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
873 CPU_LWP_FLAGS
, 0, 0 },
874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
875 CPU_MOVBE_FLAGS
, 0, 0 },
876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
877 CPU_CX16_FLAGS
, 0, 0 },
878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
879 CPU_EPT_FLAGS
, 0, 0 },
880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
881 CPU_LZCNT_FLAGS
, 0, 0 },
882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
883 CPU_HLE_FLAGS
, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
885 CPU_RTM_FLAGS
, 0, 0 },
886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
887 CPU_INVPCID_FLAGS
, 0, 0 },
888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
889 CPU_CLFLUSH_FLAGS
, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
891 CPU_NOP_FLAGS
, 0, 0 },
892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
893 CPU_SYSCALL_FLAGS
, 0, 0 },
894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
895 CPU_RDTSCP_FLAGS
, 0, 0 },
896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
897 CPU_3DNOW_FLAGS
, 0, 0 },
898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
899 CPU_3DNOWA_FLAGS
, 0, 0 },
900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
901 CPU_PADLOCK_FLAGS
, 0, 0 },
902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
903 CPU_SVME_FLAGS
, 1, 0 },
904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
905 CPU_SVME_FLAGS
, 0, 0 },
906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
907 CPU_SSE4A_FLAGS
, 0, 0 },
908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
909 CPU_ABM_FLAGS
, 0, 0 },
910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
911 CPU_BMI_FLAGS
, 0, 0 },
912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
913 CPU_TBM_FLAGS
, 0, 0 },
914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
915 CPU_ADX_FLAGS
, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
917 CPU_RDSEED_FLAGS
, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
919 CPU_PRFCHW_FLAGS
, 0, 0 },
920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
921 CPU_SMAP_FLAGS
, 0, 0 },
922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
923 CPU_MPX_FLAGS
, 0, 0 },
924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
925 CPU_SHA_FLAGS
, 0, 0 },
926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
927 CPU_CLFLUSHOPT_FLAGS
, 0, 0 },
928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
929 CPU_PREFETCHWT1_FLAGS
, 0, 0 },
930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
931 CPU_SE1_FLAGS
, 0, 0 },
932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
933 CPU_CLWB_FLAGS
, 0, 0 },
934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
935 CPU_PCOMMIT_FLAGS
, 0, 0 },
936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
937 CPU_AVX512IFMA_FLAGS
, 0, 0 },
938 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
939 CPU_AVX512VBMI_FLAGS
, 0, 0 },
943 /* Like s_lcomm_internal in gas/read.c but the alignment string
944 is allowed to be optional. */
947 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
954 && *input_line_pointer
== ',')
956 align
= parse_align (needs_align
- 1);
958 if (align
== (addressT
) -1)
973 bss_alloc (symbolP
, size
, align
);
978 pe_lcomm (int needs_align
)
980 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
984 const pseudo_typeS md_pseudo_table
[] =
986 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
987 {"align", s_align_bytes
, 0},
989 {"align", s_align_ptwo
, 0},
991 {"arch", set_cpu_arch
, 0},
995 {"lcomm", pe_lcomm
, 1},
997 {"ffloat", float_cons
, 'f'},
998 {"dfloat", float_cons
, 'd'},
999 {"tfloat", float_cons
, 'x'},
1001 {"slong", signed_cons
, 4},
1002 {"noopt", s_ignore
, 0},
1003 {"optim", s_ignore
, 0},
1004 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1005 {"code16", set_code_flag
, CODE_16BIT
},
1006 {"code32", set_code_flag
, CODE_32BIT
},
1007 {"code64", set_code_flag
, CODE_64BIT
},
1008 {"intel_syntax", set_intel_syntax
, 1},
1009 {"att_syntax", set_intel_syntax
, 0},
1010 {"intel_mnemonic", set_intel_mnemonic
, 1},
1011 {"att_mnemonic", set_intel_mnemonic
, 0},
1012 {"allow_index_reg", set_allow_index_reg
, 1},
1013 {"disallow_index_reg", set_allow_index_reg
, 0},
1014 {"sse_check", set_check
, 0},
1015 {"operand_check", set_check
, 1},
1016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1017 {"largecomm", handle_large_common
, 0},
1019 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1020 {"loc", dwarf2_directive_loc
, 0},
1021 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1024 {"secrel32", pe_directive_secrel
, 0},
1029 /* For interface with expression (). */
1030 extern char *input_line_pointer
;
1032 /* Hash table for instruction mnemonic lookup. */
1033 static struct hash_control
*op_hash
;
1035 /* Hash table for register lookup. */
1036 static struct hash_control
*reg_hash
;
1039 i386_align_code (fragS
*fragP
, int count
)
1041 /* Various efficient no-op patterns for aligning code labels.
1042 Note: Don't try to assemble the instructions in the comments.
1043 0L and 0w are not legal. */
1044 static const char f32_1
[] =
1046 static const char f32_2
[] =
1047 {0x66,0x90}; /* xchg %ax,%ax */
1048 static const char f32_3
[] =
1049 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1050 static const char f32_4
[] =
1051 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1052 static const char f32_5
[] =
1054 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1055 static const char f32_6
[] =
1056 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1057 static const char f32_7
[] =
1058 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1059 static const char f32_8
[] =
1061 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1062 static const char f32_9
[] =
1063 {0x89,0xf6, /* movl %esi,%esi */
1064 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1065 static const char f32_10
[] =
1066 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1067 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1068 static const char f32_11
[] =
1069 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1070 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1071 static const char f32_12
[] =
1072 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1073 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1074 static const char f32_13
[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_14
[] =
1078 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f16_3
[] =
1081 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1082 static const char f16_4
[] =
1083 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1084 static const char f16_5
[] =
1086 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1087 static const char f16_6
[] =
1088 {0x89,0xf6, /* mov %si,%si */
1089 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1090 static const char f16_7
[] =
1091 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1092 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1093 static const char f16_8
[] =
1094 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1095 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1096 static const char jump_31
[] =
1097 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1099 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1100 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1101 static const char *const f32_patt
[] = {
1102 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1103 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1105 static const char *const f16_patt
[] = {
1106 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1108 /* nopl (%[re]ax) */
1109 static const char alt_3
[] =
1111 /* nopl 0(%[re]ax) */
1112 static const char alt_4
[] =
1113 {0x0f,0x1f,0x40,0x00};
1114 /* nopl 0(%[re]ax,%[re]ax,1) */
1115 static const char alt_5
[] =
1116 {0x0f,0x1f,0x44,0x00,0x00};
1117 /* nopw 0(%[re]ax,%[re]ax,1) */
1118 static const char alt_6
[] =
1119 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1120 /* nopl 0L(%[re]ax) */
1121 static const char alt_7
[] =
1122 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1123 /* nopl 0L(%[re]ax,%[re]ax,1) */
1124 static const char alt_8
[] =
1125 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* nopw 0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_9
[] =
1128 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_10
[] =
1131 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1133 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_long_11
[] =
1136 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_12
[] =
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1147 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1148 static const char alt_long_13
[] =
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1157 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1158 static const char alt_long_14
[] =
1163 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1170 static const char alt_long_15
[] =
1176 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1177 /* nopl 0(%[re]ax,%[re]ax,1)
1178 nopw 0(%[re]ax,%[re]ax,1) */
1179 static const char alt_short_11
[] =
1180 {0x0f,0x1f,0x44,0x00,0x00,
1181 0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopw 0(%[re]ax,%[re]ax,1)
1183 nopw 0(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_12
[] =
1185 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1186 0x66,0x0f,0x1f,0x44,0x00,0x00};
1187 /* nopw 0(%[re]ax,%[re]ax,1)
1189 static const char alt_short_13
[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1191 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1194 static const char alt_short_14
[] =
1195 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1196 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1198 nopl 0L(%[re]ax,%[re]ax,1) */
1199 static const char alt_short_15
[] =
1200 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1201 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1202 static const char *const alt_short_patt
[] = {
1203 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1204 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1205 alt_short_14
, alt_short_15
1207 static const char *const alt_long_patt
[] = {
1208 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1209 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1210 alt_long_14
, alt_long_15
1213 /* Only align for at least a positive non-zero boundary. */
1214 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1217 /* We need to decide which NOP sequence to use for 32bit and
1218 64bit. When -mtune= is used:
1220 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1221 PROCESSOR_GENERIC32, f32_patt will be used.
1222 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1223 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1224 PROCESSOR_GENERIC64, alt_long_patt will be used.
1225 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1226 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1229 When -mtune= isn't used, alt_long_patt will be used if
1230 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1233 When -march= or .arch is used, we can't use anything beyond
1234 cpu_arch_isa_flags. */
1236 if (flag_code
== CODE_16BIT
)
1240 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1242 /* Adjust jump offset. */
1243 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1246 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1247 f16_patt
[count
- 1], count
);
1251 const char *const *patt
= NULL
;
1253 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1255 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1256 switch (cpu_arch_tune
)
1258 case PROCESSOR_UNKNOWN
:
1259 /* We use cpu_arch_isa_flags to check if we SHOULD
1260 optimize with nops. */
1261 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1262 patt
= alt_long_patt
;
1266 case PROCESSOR_PENTIUM4
:
1267 case PROCESSOR_NOCONA
:
1268 case PROCESSOR_CORE
:
1269 case PROCESSOR_CORE2
:
1270 case PROCESSOR_COREI7
:
1271 case PROCESSOR_L1OM
:
1272 case PROCESSOR_K1OM
:
1273 case PROCESSOR_GENERIC64
:
1274 patt
= alt_long_patt
;
1277 case PROCESSOR_ATHLON
:
1279 case PROCESSOR_AMDFAM10
:
1282 patt
= alt_short_patt
;
1284 case PROCESSOR_I386
:
1285 case PROCESSOR_I486
:
1286 case PROCESSOR_PENTIUM
:
1287 case PROCESSOR_PENTIUMPRO
:
1288 case PROCESSOR_GENERIC32
:
1295 switch (fragP
->tc_frag_data
.tune
)
1297 case PROCESSOR_UNKNOWN
:
1298 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1299 PROCESSOR_UNKNOWN. */
1303 case PROCESSOR_I386
:
1304 case PROCESSOR_I486
:
1305 case PROCESSOR_PENTIUM
:
1307 case PROCESSOR_ATHLON
:
1309 case PROCESSOR_AMDFAM10
:
1312 case PROCESSOR_GENERIC32
:
1313 /* We use cpu_arch_isa_flags to check if we CAN optimize
1315 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1316 patt
= alt_short_patt
;
1320 case PROCESSOR_PENTIUMPRO
:
1321 case PROCESSOR_PENTIUM4
:
1322 case PROCESSOR_NOCONA
:
1323 case PROCESSOR_CORE
:
1324 case PROCESSOR_CORE2
:
1325 case PROCESSOR_COREI7
:
1326 case PROCESSOR_L1OM
:
1327 case PROCESSOR_K1OM
:
1328 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1329 patt
= alt_long_patt
;
1333 case PROCESSOR_GENERIC64
:
1334 patt
= alt_long_patt
;
1339 if (patt
== f32_patt
)
1341 /* If the padding is less than 15 bytes, we use the normal
1342 ones. Otherwise, we use a jump instruction and adjust
1346 /* For 64bit, the limit is 3 bytes. */
1347 if (flag_code
== CODE_64BIT
1348 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1353 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1354 patt
[count
- 1], count
);
1357 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1359 /* Adjust jump offset. */
1360 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1365 /* Maximum length of an instruction is 15 byte. If the
1366 padding is greater than 15 bytes and we don't use jump,
1367 we have to break it into smaller pieces. */
1368 int padding
= count
;
1369 while (padding
> 15)
1372 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1377 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1378 patt
[padding
- 1], padding
);
1381 fragP
->fr_var
= count
;
1385 operand_type_all_zero (const union i386_operand_type
*x
)
1387 switch (ARRAY_SIZE(x
->array
))
1396 return !x
->array
[0];
1403 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1405 switch (ARRAY_SIZE(x
->array
))
1420 operand_type_equal (const union i386_operand_type
*x
,
1421 const union i386_operand_type
*y
)
1423 switch (ARRAY_SIZE(x
->array
))
1426 if (x
->array
[2] != y
->array
[2])
1429 if (x
->array
[1] != y
->array
[1])
1432 return x
->array
[0] == y
->array
[0];
1440 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1442 switch (ARRAY_SIZE(x
->array
))
1451 return !x
->array
[0];
1458 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1460 switch (ARRAY_SIZE(x
->array
))
1475 cpu_flags_equal (const union i386_cpu_flags
*x
,
1476 const union i386_cpu_flags
*y
)
1478 switch (ARRAY_SIZE(x
->array
))
1481 if (x
->array
[2] != y
->array
[2])
1484 if (x
->array
[1] != y
->array
[1])
1487 return x
->array
[0] == y
->array
[0];
1495 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1497 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1498 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1501 static INLINE i386_cpu_flags
1502 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1504 switch (ARRAY_SIZE (x
.array
))
1507 x
.array
[2] &= y
.array
[2];
1509 x
.array
[1] &= y
.array
[1];
1511 x
.array
[0] &= y
.array
[0];
1519 static INLINE i386_cpu_flags
1520 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1522 switch (ARRAY_SIZE (x
.array
))
1525 x
.array
[2] |= y
.array
[2];
1527 x
.array
[1] |= y
.array
[1];
1529 x
.array
[0] |= y
.array
[0];
1537 static INLINE i386_cpu_flags
1538 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1540 switch (ARRAY_SIZE (x
.array
))
1543 x
.array
[2] &= ~y
.array
[2];
1545 x
.array
[1] &= ~y
.array
[1];
1547 x
.array
[0] &= ~y
.array
[0];
1555 #define CPU_FLAGS_ARCH_MATCH 0x1
1556 #define CPU_FLAGS_64BIT_MATCH 0x2
1557 #define CPU_FLAGS_AES_MATCH 0x4
1558 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1559 #define CPU_FLAGS_AVX_MATCH 0x10
1561 #define CPU_FLAGS_32BIT_MATCH \
1562 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1563 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1564 #define CPU_FLAGS_PERFECT_MATCH \
1565 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1567 /* Return CPU flags match bits. */
1570 cpu_flags_match (const insn_template
*t
)
1572 i386_cpu_flags x
= t
->cpu_flags
;
1573 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1575 x
.bitfield
.cpu64
= 0;
1576 x
.bitfield
.cpuno64
= 0;
1578 if (cpu_flags_all_zero (&x
))
1580 /* This instruction is available on all archs. */
1581 match
|= CPU_FLAGS_32BIT_MATCH
;
1585 /* This instruction is available only on some archs. */
1586 i386_cpu_flags cpu
= cpu_arch_flags
;
1588 cpu
.bitfield
.cpu64
= 0;
1589 cpu
.bitfield
.cpuno64
= 0;
1590 cpu
= cpu_flags_and (x
, cpu
);
1591 if (!cpu_flags_all_zero (&cpu
))
1593 if (x
.bitfield
.cpuavx
)
1595 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1596 if (cpu
.bitfield
.cpuavx
)
1598 /* Check SSE2AVX. */
1599 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1601 match
|= (CPU_FLAGS_ARCH_MATCH
1602 | CPU_FLAGS_AVX_MATCH
);
1604 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1605 match
|= CPU_FLAGS_AES_MATCH
;
1607 if (!x
.bitfield
.cpupclmul
1608 || cpu
.bitfield
.cpupclmul
)
1609 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1613 match
|= CPU_FLAGS_ARCH_MATCH
;
1616 match
|= CPU_FLAGS_32BIT_MATCH
;
1622 static INLINE i386_operand_type
1623 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1625 switch (ARRAY_SIZE (x
.array
))
1628 x
.array
[2] &= y
.array
[2];
1630 x
.array
[1] &= y
.array
[1];
1632 x
.array
[0] &= y
.array
[0];
1640 static INLINE i386_operand_type
1641 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1643 switch (ARRAY_SIZE (x
.array
))
1646 x
.array
[2] |= y
.array
[2];
1648 x
.array
[1] |= y
.array
[1];
1650 x
.array
[0] |= y
.array
[0];
1658 static INLINE i386_operand_type
1659 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1661 switch (ARRAY_SIZE (x
.array
))
1664 x
.array
[2] ^= y
.array
[2];
1666 x
.array
[1] ^= y
.array
[1];
1668 x
.array
[0] ^= y
.array
[0];
1676 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1677 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1678 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1679 static const i386_operand_type inoutportreg
1680 = OPERAND_TYPE_INOUTPORTREG
;
1681 static const i386_operand_type reg16_inoutportreg
1682 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1683 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1684 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1685 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1686 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1687 static const i386_operand_type anydisp
1688 = OPERAND_TYPE_ANYDISP
;
1689 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1690 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1691 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1692 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1693 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1694 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1695 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1696 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1697 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1698 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1699 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1700 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1701 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1702 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1713 operand_type_check (i386_operand_type t
, enum operand_type c
)
1718 return (t
.bitfield
.reg8
1721 || t
.bitfield
.reg64
);
1724 return (t
.bitfield
.imm8
1728 || t
.bitfield
.imm32s
1729 || t
.bitfield
.imm64
);
1732 return (t
.bitfield
.disp8
1733 || t
.bitfield
.disp16
1734 || t
.bitfield
.disp32
1735 || t
.bitfield
.disp32s
1736 || t
.bitfield
.disp64
);
1739 return (t
.bitfield
.disp8
1740 || t
.bitfield
.disp16
1741 || t
.bitfield
.disp32
1742 || t
.bitfield
.disp32s
1743 || t
.bitfield
.disp64
1744 || t
.bitfield
.baseindex
);
1753 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1754 operand J for instruction template T. */
1757 match_reg_size (const insn_template
*t
, unsigned int j
)
1759 return !((i
.types
[j
].bitfield
.byte
1760 && !t
->operand_types
[j
].bitfield
.byte
)
1761 || (i
.types
[j
].bitfield
.word
1762 && !t
->operand_types
[j
].bitfield
.word
)
1763 || (i
.types
[j
].bitfield
.dword
1764 && !t
->operand_types
[j
].bitfield
.dword
)
1765 || (i
.types
[j
].bitfield
.qword
1766 && !t
->operand_types
[j
].bitfield
.qword
));
1769 /* Return 1 if there is no conflict in any size on operand J for
1770 instruction template T. */
1773 match_mem_size (const insn_template
*t
, unsigned int j
)
1775 return (match_reg_size (t
, j
)
1776 && !((i
.types
[j
].bitfield
.unspecified
1777 && !t
->operand_types
[j
].bitfield
.unspecified
)
1778 || (i
.types
[j
].bitfield
.fword
1779 && !t
->operand_types
[j
].bitfield
.fword
)
1780 || (i
.types
[j
].bitfield
.tbyte
1781 && !t
->operand_types
[j
].bitfield
.tbyte
)
1782 || (i
.types
[j
].bitfield
.xmmword
1783 && !t
->operand_types
[j
].bitfield
.xmmword
)
1784 || (i
.types
[j
].bitfield
.ymmword
1785 && !t
->operand_types
[j
].bitfield
.ymmword
)
1786 || (i
.types
[j
].bitfield
.zmmword
1787 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1790 /* Return 1 if there is no size conflict on any operands for
1791 instruction template T. */
1794 operand_size_match (const insn_template
*t
)
1799 /* Don't check jump instructions. */
1800 if (t
->opcode_modifier
.jump
1801 || t
->opcode_modifier
.jumpbyte
1802 || t
->opcode_modifier
.jumpdword
1803 || t
->opcode_modifier
.jumpintersegment
)
1806 /* Check memory and accumulator operand size. */
1807 for (j
= 0; j
< i
.operands
; j
++)
1809 if (t
->operand_types
[j
].bitfield
.anysize
)
1812 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1818 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1827 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1830 i
.error
= operand_size_mismatch
;
1834 /* Check reverse. */
1835 gas_assert (i
.operands
== 2);
1838 for (j
= 0; j
< 2; j
++)
1840 if (t
->operand_types
[j
].bitfield
.acc
1841 && !match_reg_size (t
, j
? 0 : 1))
1844 if (i
.types
[j
].bitfield
.mem
1845 && !match_mem_size (t
, j
? 0 : 1))
1853 operand_type_match (i386_operand_type overlap
,
1854 i386_operand_type given
)
1856 i386_operand_type temp
= overlap
;
1858 temp
.bitfield
.jumpabsolute
= 0;
1859 temp
.bitfield
.unspecified
= 0;
1860 temp
.bitfield
.byte
= 0;
1861 temp
.bitfield
.word
= 0;
1862 temp
.bitfield
.dword
= 0;
1863 temp
.bitfield
.fword
= 0;
1864 temp
.bitfield
.qword
= 0;
1865 temp
.bitfield
.tbyte
= 0;
1866 temp
.bitfield
.xmmword
= 0;
1867 temp
.bitfield
.ymmword
= 0;
1868 temp
.bitfield
.zmmword
= 0;
1869 if (operand_type_all_zero (&temp
))
1872 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1873 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1877 i
.error
= operand_type_mismatch
;
1881 /* If given types g0 and g1 are registers they must be of the same type
1882 unless the expected operand type register overlap is null.
1883 Note that Acc in a template matches every size of reg. */
1886 operand_type_register_match (i386_operand_type m0
,
1887 i386_operand_type g0
,
1888 i386_operand_type t0
,
1889 i386_operand_type m1
,
1890 i386_operand_type g1
,
1891 i386_operand_type t1
)
1893 if (!operand_type_check (g0
, reg
))
1896 if (!operand_type_check (g1
, reg
))
1899 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1900 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1901 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1902 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1905 if (m0
.bitfield
.acc
)
1907 t0
.bitfield
.reg8
= 1;
1908 t0
.bitfield
.reg16
= 1;
1909 t0
.bitfield
.reg32
= 1;
1910 t0
.bitfield
.reg64
= 1;
1913 if (m1
.bitfield
.acc
)
1915 t1
.bitfield
.reg8
= 1;
1916 t1
.bitfield
.reg16
= 1;
1917 t1
.bitfield
.reg32
= 1;
1918 t1
.bitfield
.reg64
= 1;
1921 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1922 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1923 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1924 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1927 i
.error
= register_type_mismatch
;
1932 static INLINE
unsigned int
1933 register_number (const reg_entry
*r
)
1935 unsigned int nr
= r
->reg_num
;
1937 if (r
->reg_flags
& RegRex
)
1943 static INLINE
unsigned int
1944 mode_from_disp_size (i386_operand_type t
)
1946 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1948 else if (t
.bitfield
.disp16
1949 || t
.bitfield
.disp32
1950 || t
.bitfield
.disp32s
)
1957 fits_in_signed_byte (addressT num
)
1959 return num
+ 0x80 <= 0xff;
1963 fits_in_unsigned_byte (addressT num
)
1969 fits_in_unsigned_word (addressT num
)
1971 return num
<= 0xffff;
1975 fits_in_signed_word (addressT num
)
1977 return num
+ 0x8000 <= 0xffff;
1981 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1986 return num
+ 0x80000000 <= 0xffffffff;
1988 } /* fits_in_signed_long() */
1991 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1996 return num
<= 0xffffffff;
1998 } /* fits_in_unsigned_long() */
2001 fits_in_vec_disp8 (offsetT num
)
2003 int shift
= i
.memshift
;
2009 mask
= (1 << shift
) - 1;
2011 /* Return 0 if NUM isn't properly aligned. */
2015 /* Check if NUM will fit in 8bit after shift. */
2016 return fits_in_signed_byte (num
>> shift
);
2020 fits_in_imm4 (offsetT num
)
2022 return (num
& 0xf) == num
;
2025 static i386_operand_type
2026 smallest_imm_type (offsetT num
)
2028 i386_operand_type t
;
2030 operand_type_set (&t
, 0);
2031 t
.bitfield
.imm64
= 1;
2033 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2035 /* This code is disabled on the 486 because all the Imm1 forms
2036 in the opcode table are slower on the i486. They're the
2037 versions with the implicitly specified single-position
2038 displacement, which has another syntax if you really want to
2040 t
.bitfield
.imm1
= 1;
2041 t
.bitfield
.imm8
= 1;
2042 t
.bitfield
.imm8s
= 1;
2043 t
.bitfield
.imm16
= 1;
2044 t
.bitfield
.imm32
= 1;
2045 t
.bitfield
.imm32s
= 1;
2047 else if (fits_in_signed_byte (num
))
2049 t
.bitfield
.imm8
= 1;
2050 t
.bitfield
.imm8s
= 1;
2051 t
.bitfield
.imm16
= 1;
2052 t
.bitfield
.imm32
= 1;
2053 t
.bitfield
.imm32s
= 1;
2055 else if (fits_in_unsigned_byte (num
))
2057 t
.bitfield
.imm8
= 1;
2058 t
.bitfield
.imm16
= 1;
2059 t
.bitfield
.imm32
= 1;
2060 t
.bitfield
.imm32s
= 1;
2062 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2064 t
.bitfield
.imm16
= 1;
2065 t
.bitfield
.imm32
= 1;
2066 t
.bitfield
.imm32s
= 1;
2068 else if (fits_in_signed_long (num
))
2070 t
.bitfield
.imm32
= 1;
2071 t
.bitfield
.imm32s
= 1;
2073 else if (fits_in_unsigned_long (num
))
2074 t
.bitfield
.imm32
= 1;
2080 offset_in_range (offsetT val
, int size
)
2086 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2087 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2088 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2090 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2096 /* If BFD64, sign extend val for 32bit address mode. */
2097 if (flag_code
!= CODE_64BIT
2098 || i
.prefix
[ADDR_PREFIX
])
2099 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2100 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2103 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2105 char buf1
[40], buf2
[40];
2107 sprint_value (buf1
, val
);
2108 sprint_value (buf2
, val
& mask
);
2109 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2123 a. PREFIX_EXIST if attempting to add a prefix where one from the
2124 same class already exists.
2125 b. PREFIX_LOCK if lock prefix is added.
2126 c. PREFIX_REP if rep/repne prefix is added.
2127 d. PREFIX_OTHER if other prefix is added.
2130 static enum PREFIX_GROUP
2131 add_prefix (unsigned int prefix
)
2133 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2136 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2137 && flag_code
== CODE_64BIT
)
2139 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2140 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2141 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2152 case CS_PREFIX_OPCODE
:
2153 case DS_PREFIX_OPCODE
:
2154 case ES_PREFIX_OPCODE
:
2155 case FS_PREFIX_OPCODE
:
2156 case GS_PREFIX_OPCODE
:
2157 case SS_PREFIX_OPCODE
:
2161 case REPNE_PREFIX_OPCODE
:
2162 case REPE_PREFIX_OPCODE
:
2167 case LOCK_PREFIX_OPCODE
:
2176 case ADDR_PREFIX_OPCODE
:
2180 case DATA_PREFIX_OPCODE
:
2184 if (i
.prefix
[q
] != 0)
2192 i
.prefix
[q
] |= prefix
;
2195 as_bad (_("same type of prefix used twice"));
2201 update_code_flag (int value
, int check
)
2203 PRINTF_LIKE ((*as_error
));
2205 flag_code
= (enum flag_code
) value
;
2206 if (flag_code
== CODE_64BIT
)
2208 cpu_arch_flags
.bitfield
.cpu64
= 1;
2209 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2213 cpu_arch_flags
.bitfield
.cpu64
= 0;
2214 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2216 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2219 as_error
= as_fatal
;
2222 (*as_error
) (_("64bit mode not supported on `%s'."),
2223 cpu_arch_name
? cpu_arch_name
: default_arch
);
2225 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2228 as_error
= as_fatal
;
2231 (*as_error
) (_("32bit mode not supported on `%s'."),
2232 cpu_arch_name
? cpu_arch_name
: default_arch
);
2234 stackop_size
= '\0';
2238 set_code_flag (int value
)
2240 update_code_flag (value
, 0);
2244 set_16bit_gcc_code_flag (int new_code_flag
)
2246 flag_code
= (enum flag_code
) new_code_flag
;
2247 if (flag_code
!= CODE_16BIT
)
2249 cpu_arch_flags
.bitfield
.cpu64
= 0;
2250 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2251 stackop_size
= LONG_MNEM_SUFFIX
;
2255 set_intel_syntax (int syntax_flag
)
2257 /* Find out if register prefixing is specified. */
2258 int ask_naked_reg
= 0;
2261 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2263 char *string
= input_line_pointer
;
2264 int e
= get_symbol_end ();
2266 if (strcmp (string
, "prefix") == 0)
2268 else if (strcmp (string
, "noprefix") == 0)
2271 as_bad (_("bad argument to syntax directive."));
2272 *input_line_pointer
= e
;
2274 demand_empty_rest_of_line ();
2276 intel_syntax
= syntax_flag
;
2278 if (ask_naked_reg
== 0)
2279 allow_naked_reg
= (intel_syntax
2280 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2282 allow_naked_reg
= (ask_naked_reg
< 0);
2284 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2286 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2287 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2288 register_prefix
= allow_naked_reg
? "" : "%";
2292 set_intel_mnemonic (int mnemonic_flag
)
2294 intel_mnemonic
= mnemonic_flag
;
2298 set_allow_index_reg (int flag
)
2300 allow_index_reg
= flag
;
2304 set_check (int what
)
2306 enum check_kind
*kind
;
2311 kind
= &operand_check
;
2322 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2324 char *string
= input_line_pointer
;
2325 int e
= get_symbol_end ();
2327 if (strcmp (string
, "none") == 0)
2329 else if (strcmp (string
, "warning") == 0)
2330 *kind
= check_warning
;
2331 else if (strcmp (string
, "error") == 0)
2332 *kind
= check_error
;
2334 as_bad (_("bad argument to %s_check directive."), str
);
2335 *input_line_pointer
= e
;
2338 as_bad (_("missing argument for %s_check directive"), str
);
2340 demand_empty_rest_of_line ();
2344 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2345 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2348 static const char *arch
;
2350 /* Intel LIOM is only supported on ELF. */
2356 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2357 use default_arch. */
2358 arch
= cpu_arch_name
;
2360 arch
= default_arch
;
2363 /* If we are targeting Intel L1OM, we must enable it. */
2364 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2365 || new_flag
.bitfield
.cpul1om
)
2368 /* If we are targeting Intel K1OM, we must enable it. */
2369 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2370 || new_flag
.bitfield
.cpuk1om
)
2373 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2378 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2382 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2384 char *string
= input_line_pointer
;
2385 int e
= get_symbol_end ();
2387 i386_cpu_flags flags
;
2389 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2391 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2393 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2397 cpu_arch_name
= cpu_arch
[j
].name
;
2398 cpu_sub_arch_name
= NULL
;
2399 cpu_arch_flags
= cpu_arch
[j
].flags
;
2400 if (flag_code
== CODE_64BIT
)
2402 cpu_arch_flags
.bitfield
.cpu64
= 1;
2403 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2407 cpu_arch_flags
.bitfield
.cpu64
= 0;
2408 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2410 cpu_arch_isa
= cpu_arch
[j
].type
;
2411 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2412 if (!cpu_arch_tune_set
)
2414 cpu_arch_tune
= cpu_arch_isa
;
2415 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2420 if (!cpu_arch
[j
].negated
)
2421 flags
= cpu_flags_or (cpu_arch_flags
,
2424 flags
= cpu_flags_and_not (cpu_arch_flags
,
2426 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2428 if (cpu_sub_arch_name
)
2430 char *name
= cpu_sub_arch_name
;
2431 cpu_sub_arch_name
= concat (name
,
2433 (const char *) NULL
);
2437 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2438 cpu_arch_flags
= flags
;
2439 cpu_arch_isa_flags
= flags
;
2441 *input_line_pointer
= e
;
2442 demand_empty_rest_of_line ();
2446 if (j
>= ARRAY_SIZE (cpu_arch
))
2447 as_bad (_("no such architecture: `%s'"), string
);
2449 *input_line_pointer
= e
;
2452 as_bad (_("missing cpu architecture"));
2454 no_cond_jump_promotion
= 0;
2455 if (*input_line_pointer
== ','
2456 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2458 char *string
= ++input_line_pointer
;
2459 int e
= get_symbol_end ();
2461 if (strcmp (string
, "nojumps") == 0)
2462 no_cond_jump_promotion
= 1;
2463 else if (strcmp (string
, "jumps") == 0)
2466 as_bad (_("no such architecture modifier: `%s'"), string
);
2468 *input_line_pointer
= e
;
2471 demand_empty_rest_of_line ();
2474 enum bfd_architecture
2477 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2479 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2480 || flag_code
!= CODE_64BIT
)
2481 as_fatal (_("Intel L1OM is 64bit ELF only"));
2482 return bfd_arch_l1om
;
2484 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2486 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2487 || flag_code
!= CODE_64BIT
)
2488 as_fatal (_("Intel K1OM is 64bit ELF only"));
2489 return bfd_arch_k1om
;
2492 return bfd_arch_i386
;
2498 if (!strncmp (default_arch
, "x86_64", 6))
2500 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2502 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2503 || default_arch
[6] != '\0')
2504 as_fatal (_("Intel L1OM is 64bit ELF only"));
2505 return bfd_mach_l1om
;
2507 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2509 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2510 || default_arch
[6] != '\0')
2511 as_fatal (_("Intel K1OM is 64bit ELF only"));
2512 return bfd_mach_k1om
;
2514 else if (default_arch
[6] == '\0')
2515 return bfd_mach_x86_64
;
2517 return bfd_mach_x64_32
;
2519 else if (!strcmp (default_arch
, "i386"))
2520 return bfd_mach_i386_i386
;
2522 as_fatal (_("unknown architecture"));
2528 const char *hash_err
;
2530 /* Initialize op_hash hash table. */
2531 op_hash
= hash_new ();
2534 const insn_template
*optab
;
2535 templates
*core_optab
;
2537 /* Setup for loop. */
2539 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2540 core_optab
->start
= optab
;
2545 if (optab
->name
== NULL
2546 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2548 /* different name --> ship out current template list;
2549 add to hash table; & begin anew. */
2550 core_optab
->end
= optab
;
2551 hash_err
= hash_insert (op_hash
,
2553 (void *) core_optab
);
2556 as_fatal (_("can't hash %s: %s"),
2560 if (optab
->name
== NULL
)
2562 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2563 core_optab
->start
= optab
;
2568 /* Initialize reg_hash hash table. */
2569 reg_hash
= hash_new ();
2571 const reg_entry
*regtab
;
2572 unsigned int regtab_size
= i386_regtab_size
;
2574 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2576 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2578 as_fatal (_("can't hash %s: %s"),
2584 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2589 for (c
= 0; c
< 256; c
++)
2594 mnemonic_chars
[c
] = c
;
2595 register_chars
[c
] = c
;
2596 operand_chars
[c
] = c
;
2598 else if (ISLOWER (c
))
2600 mnemonic_chars
[c
] = c
;
2601 register_chars
[c
] = c
;
2602 operand_chars
[c
] = c
;
2604 else if (ISUPPER (c
))
2606 mnemonic_chars
[c
] = TOLOWER (c
);
2607 register_chars
[c
] = mnemonic_chars
[c
];
2608 operand_chars
[c
] = c
;
2610 else if (c
== '{' || c
== '}')
2611 operand_chars
[c
] = c
;
2613 if (ISALPHA (c
) || ISDIGIT (c
))
2614 identifier_chars
[c
] = c
;
2617 identifier_chars
[c
] = c
;
2618 operand_chars
[c
] = c
;
2623 identifier_chars
['@'] = '@';
2626 identifier_chars
['?'] = '?';
2627 operand_chars
['?'] = '?';
2629 digit_chars
['-'] = '-';
2630 mnemonic_chars
['_'] = '_';
2631 mnemonic_chars
['-'] = '-';
2632 mnemonic_chars
['.'] = '.';
2633 identifier_chars
['_'] = '_';
2634 identifier_chars
['.'] = '.';
2636 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2637 operand_chars
[(unsigned char) *p
] = *p
;
2640 if (flag_code
== CODE_64BIT
)
2642 #if defined (OBJ_COFF) && defined (TE_PE)
2643 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2646 x86_dwarf2_return_column
= 16;
2648 x86_cie_data_alignment
= -8;
2652 x86_dwarf2_return_column
= 8;
2653 x86_cie_data_alignment
= -4;
2658 i386_print_statistics (FILE *file
)
2660 hash_print_statistics (file
, "i386 opcode", op_hash
);
2661 hash_print_statistics (file
, "i386 register", reg_hash
);
2666 /* Debugging routines for md_assemble. */
2667 static void pte (insn_template
*);
2668 static void pt (i386_operand_type
);
2669 static void pe (expressionS
*);
2670 static void ps (symbolS
*);
2673 pi (char *line
, i386_insn
*x
)
2677 fprintf (stdout
, "%s: template ", line
);
2679 fprintf (stdout
, " address: base %s index %s scale %x\n",
2680 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2681 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2682 x
->log2_scale_factor
);
2683 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2684 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2685 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2686 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2687 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2688 (x
->rex
& REX_W
) != 0,
2689 (x
->rex
& REX_R
) != 0,
2690 (x
->rex
& REX_X
) != 0,
2691 (x
->rex
& REX_B
) != 0);
2692 for (j
= 0; j
< x
->operands
; j
++)
2694 fprintf (stdout
, " #%d: ", j
+ 1);
2696 fprintf (stdout
, "\n");
2697 if (x
->types
[j
].bitfield
.reg8
2698 || x
->types
[j
].bitfield
.reg16
2699 || x
->types
[j
].bitfield
.reg32
2700 || x
->types
[j
].bitfield
.reg64
2701 || x
->types
[j
].bitfield
.regmmx
2702 || x
->types
[j
].bitfield
.regxmm
2703 || x
->types
[j
].bitfield
.regymm
2704 || x
->types
[j
].bitfield
.regzmm
2705 || x
->types
[j
].bitfield
.sreg2
2706 || x
->types
[j
].bitfield
.sreg3
2707 || x
->types
[j
].bitfield
.control
2708 || x
->types
[j
].bitfield
.debug
2709 || x
->types
[j
].bitfield
.test
)
2710 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2711 if (operand_type_check (x
->types
[j
], imm
))
2713 if (operand_type_check (x
->types
[j
], disp
))
2714 pe (x
->op
[j
].disps
);
2719 pte (insn_template
*t
)
2722 fprintf (stdout
, " %d operands ", t
->operands
);
2723 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2724 if (t
->extension_opcode
!= None
)
2725 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2726 if (t
->opcode_modifier
.d
)
2727 fprintf (stdout
, "D");
2728 if (t
->opcode_modifier
.w
)
2729 fprintf (stdout
, "W");
2730 fprintf (stdout
, "\n");
2731 for (j
= 0; j
< t
->operands
; j
++)
2733 fprintf (stdout
, " #%d type ", j
+ 1);
2734 pt (t
->operand_types
[j
]);
2735 fprintf (stdout
, "\n");
2742 fprintf (stdout
, " operation %d\n", e
->X_op
);
2743 fprintf (stdout
, " add_number %ld (%lx)\n",
2744 (long) e
->X_add_number
, (long) e
->X_add_number
);
2745 if (e
->X_add_symbol
)
2747 fprintf (stdout
, " add_symbol ");
2748 ps (e
->X_add_symbol
);
2749 fprintf (stdout
, "\n");
2753 fprintf (stdout
, " op_symbol ");
2754 ps (e
->X_op_symbol
);
2755 fprintf (stdout
, "\n");
2762 fprintf (stdout
, "%s type %s%s",
2764 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2765 segment_name (S_GET_SEGMENT (s
)));
2768 static struct type_name
2770 i386_operand_type mask
;
2773 const type_names
[] =
2775 { OPERAND_TYPE_REG8
, "r8" },
2776 { OPERAND_TYPE_REG16
, "r16" },
2777 { OPERAND_TYPE_REG32
, "r32" },
2778 { OPERAND_TYPE_REG64
, "r64" },
2779 { OPERAND_TYPE_IMM8
, "i8" },
2780 { OPERAND_TYPE_IMM8
, "i8s" },
2781 { OPERAND_TYPE_IMM16
, "i16" },
2782 { OPERAND_TYPE_IMM32
, "i32" },
2783 { OPERAND_TYPE_IMM32S
, "i32s" },
2784 { OPERAND_TYPE_IMM64
, "i64" },
2785 { OPERAND_TYPE_IMM1
, "i1" },
2786 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2787 { OPERAND_TYPE_DISP8
, "d8" },
2788 { OPERAND_TYPE_DISP16
, "d16" },
2789 { OPERAND_TYPE_DISP32
, "d32" },
2790 { OPERAND_TYPE_DISP32S
, "d32s" },
2791 { OPERAND_TYPE_DISP64
, "d64" },
2792 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2793 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2794 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2795 { OPERAND_TYPE_CONTROL
, "control reg" },
2796 { OPERAND_TYPE_TEST
, "test reg" },
2797 { OPERAND_TYPE_DEBUG
, "debug reg" },
2798 { OPERAND_TYPE_FLOATREG
, "FReg" },
2799 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2800 { OPERAND_TYPE_SREG2
, "SReg2" },
2801 { OPERAND_TYPE_SREG3
, "SReg3" },
2802 { OPERAND_TYPE_ACC
, "Acc" },
2803 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2804 { OPERAND_TYPE_REGMMX
, "rMMX" },
2805 { OPERAND_TYPE_REGXMM
, "rXMM" },
2806 { OPERAND_TYPE_REGYMM
, "rYMM" },
2807 { OPERAND_TYPE_REGZMM
, "rZMM" },
2808 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2809 { OPERAND_TYPE_ESSEG
, "es" },
2813 pt (i386_operand_type t
)
2816 i386_operand_type a
;
2818 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2820 a
= operand_type_and (t
, type_names
[j
].mask
);
2821 if (!operand_type_all_zero (&a
))
2822 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2827 #endif /* DEBUG386 */
2829 static bfd_reloc_code_real_type
2830 reloc (unsigned int size
,
2834 bfd_reloc_code_real_type other
)
2836 if (other
!= NO_RELOC
)
2838 reloc_howto_type
*rel
;
2843 case BFD_RELOC_X86_64_GOT32
:
2844 return BFD_RELOC_X86_64_GOT64
;
2846 case BFD_RELOC_X86_64_GOTPLT64
:
2847 return BFD_RELOC_X86_64_GOTPLT64
;
2849 case BFD_RELOC_X86_64_PLTOFF64
:
2850 return BFD_RELOC_X86_64_PLTOFF64
;
2852 case BFD_RELOC_X86_64_GOTPC32
:
2853 other
= BFD_RELOC_X86_64_GOTPC64
;
2855 case BFD_RELOC_X86_64_GOTPCREL
:
2856 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2858 case BFD_RELOC_X86_64_TPOFF32
:
2859 other
= BFD_RELOC_X86_64_TPOFF64
;
2861 case BFD_RELOC_X86_64_DTPOFF32
:
2862 other
= BFD_RELOC_X86_64_DTPOFF64
;
2868 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2869 if (other
== BFD_RELOC_SIZE32
)
2872 other
= BFD_RELOC_SIZE64
;
2875 as_bad (_("there are no pc-relative size relocations"));
2881 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2882 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2885 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2887 as_bad (_("unknown relocation (%u)"), other
);
2888 else if (size
!= bfd_get_reloc_size (rel
))
2889 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2890 bfd_get_reloc_size (rel
),
2892 else if (pcrel
&& !rel
->pc_relative
)
2893 as_bad (_("non-pc-relative relocation for pc-relative field"));
2894 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2896 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2898 as_bad (_("relocated field and relocation type differ in signedness"));
2907 as_bad (_("there are no unsigned pc-relative relocations"));
2910 case 1: return BFD_RELOC_8_PCREL
;
2911 case 2: return BFD_RELOC_16_PCREL
;
2912 case 4: return (bnd_prefix
&& object_64bit
2913 ? BFD_RELOC_X86_64_PC32_BND
2914 : BFD_RELOC_32_PCREL
);
2915 case 8: return BFD_RELOC_64_PCREL
;
2917 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2924 case 4: return BFD_RELOC_X86_64_32S
;
2929 case 1: return BFD_RELOC_8
;
2930 case 2: return BFD_RELOC_16
;
2931 case 4: return BFD_RELOC_32
;
2932 case 8: return BFD_RELOC_64
;
2934 as_bad (_("cannot do %s %u byte relocation"),
2935 sign
> 0 ? "signed" : "unsigned", size
);
2941 /* Here we decide which fixups can be adjusted to make them relative to
2942 the beginning of the section instead of the symbol. Basically we need
2943 to make sure that the dynamic relocations are done correctly, so in
2944 some cases we force the original symbol to be used. */
2947 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2949 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2953 /* Don't adjust pc-relative references to merge sections in 64-bit
2955 if (use_rela_relocations
2956 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2960 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2961 and changed later by validate_fix. */
2962 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2963 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2966 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2967 for size relocations. */
2968 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
2969 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
2970 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2971 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2972 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2973 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2974 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2975 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2976 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2977 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2978 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2979 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2980 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2981 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2982 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2983 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2984 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2985 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2986 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2987 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2988 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2989 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2990 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2991 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2992 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2993 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2994 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2995 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2996 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2997 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3004 intel_float_operand (const char *mnemonic
)
3006 /* Note that the value returned is meaningful only for opcodes with (memory)
3007 operands, hence the code here is free to improperly handle opcodes that
3008 have no operands (for better performance and smaller code). */
3010 if (mnemonic
[0] != 'f')
3011 return 0; /* non-math */
3013 switch (mnemonic
[1])
3015 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3016 the fs segment override prefix not currently handled because no
3017 call path can make opcodes without operands get here */
3019 return 2 /* integer op */;
3021 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3022 return 3; /* fldcw/fldenv */
3025 if (mnemonic
[2] != 'o' /* fnop */)
3026 return 3; /* non-waiting control op */
3029 if (mnemonic
[2] == 's')
3030 return 3; /* frstor/frstpm */
3033 if (mnemonic
[2] == 'a')
3034 return 3; /* fsave */
3035 if (mnemonic
[2] == 't')
3037 switch (mnemonic
[3])
3039 case 'c': /* fstcw */
3040 case 'd': /* fstdw */
3041 case 'e': /* fstenv */
3042 case 's': /* fsts[gw] */
3048 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3049 return 0; /* fxsave/fxrstor are not really math ops */
3056 /* Build the VEX prefix. */
3059 build_vex_prefix (const insn_template
*t
)
3061 unsigned int register_specifier
;
3062 unsigned int implied_prefix
;
3063 unsigned int vector_length
;
3065 /* Check register specifier. */
3066 if (i
.vex
.register_specifier
)
3068 register_specifier
=
3069 ~register_number (i
.vex
.register_specifier
) & 0xf;
3070 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3073 register_specifier
= 0xf;
3075 /* Use 2-byte VEX prefix by swappping destination and source
3078 && i
.operands
== i
.reg_operands
3079 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3080 && i
.tm
.opcode_modifier
.s
3083 unsigned int xchg
= i
.operands
- 1;
3084 union i386_op temp_op
;
3085 i386_operand_type temp_type
;
3087 temp_type
= i
.types
[xchg
];
3088 i
.types
[xchg
] = i
.types
[0];
3089 i
.types
[0] = temp_type
;
3090 temp_op
= i
.op
[xchg
];
3091 i
.op
[xchg
] = i
.op
[0];
3094 gas_assert (i
.rm
.mode
== 3);
3098 i
.rm
.regmem
= i
.rm
.reg
;
3101 /* Use the next insn. */
3105 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3106 vector_length
= avxscalar
;
3108 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3110 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3115 case DATA_PREFIX_OPCODE
:
3118 case REPE_PREFIX_OPCODE
:
3121 case REPNE_PREFIX_OPCODE
:
3128 /* Use 2-byte VEX prefix if possible. */
3129 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3130 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3131 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3133 /* 2-byte VEX prefix. */
3137 i
.vex
.bytes
[0] = 0xc5;
3139 /* Check the REX.R bit. */
3140 r
= (i
.rex
& REX_R
) ? 0 : 1;
3141 i
.vex
.bytes
[1] = (r
<< 7
3142 | register_specifier
<< 3
3143 | vector_length
<< 2
3148 /* 3-byte VEX prefix. */
3153 switch (i
.tm
.opcode_modifier
.vexopcode
)
3157 i
.vex
.bytes
[0] = 0xc4;
3161 i
.vex
.bytes
[0] = 0xc4;
3165 i
.vex
.bytes
[0] = 0xc4;
3169 i
.vex
.bytes
[0] = 0x8f;
3173 i
.vex
.bytes
[0] = 0x8f;
3177 i
.vex
.bytes
[0] = 0x8f;
3183 /* The high 3 bits of the second VEX byte are 1's compliment
3184 of RXB bits from REX. */
3185 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3187 /* Check the REX.W bit. */
3188 w
= (i
.rex
& REX_W
) ? 1 : 0;
3189 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3192 i
.vex
.bytes
[2] = (w
<< 7
3193 | register_specifier
<< 3
3194 | vector_length
<< 2
3199 /* Build the EVEX prefix. */
3202 build_evex_prefix (void)
3204 unsigned int register_specifier
;
3205 unsigned int implied_prefix
;
3207 rex_byte vrex_used
= 0;
3209 /* Check register specifier. */
3210 if (i
.vex
.register_specifier
)
3212 gas_assert ((i
.vrex
& REX_X
) == 0);
3214 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3215 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3216 register_specifier
+= 8;
3217 /* The upper 16 registers are encoded in the fourth byte of the
3219 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3220 i
.vex
.bytes
[3] = 0x8;
3221 register_specifier
= ~register_specifier
& 0xf;
3225 register_specifier
= 0xf;
3227 /* Encode upper 16 vector index register in the fourth byte of
3229 if (!(i
.vrex
& REX_X
))
3230 i
.vex
.bytes
[3] = 0x8;
3235 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3240 case DATA_PREFIX_OPCODE
:
3243 case REPE_PREFIX_OPCODE
:
3246 case REPNE_PREFIX_OPCODE
:
3253 /* 4 byte EVEX prefix. */
3255 i
.vex
.bytes
[0] = 0x62;
3258 switch (i
.tm
.opcode_modifier
.vexopcode
)
3274 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3276 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3278 /* The fifth bit of the second EVEX byte is 1's compliment of the
3279 REX_R bit in VREX. */
3280 if (!(i
.vrex
& REX_R
))
3281 i
.vex
.bytes
[1] |= 0x10;
3285 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3287 /* When all operands are registers, the REX_X bit in REX is not
3288 used. We reuse it to encode the upper 16 registers, which is
3289 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3290 as 1's compliment. */
3291 if ((i
.vrex
& REX_B
))
3294 i
.vex
.bytes
[1] &= ~0x40;
3298 /* EVEX instructions shouldn't need the REX prefix. */
3299 i
.vrex
&= ~vrex_used
;
3300 gas_assert (i
.vrex
== 0);
3302 /* Check the REX.W bit. */
3303 w
= (i
.rex
& REX_W
) ? 1 : 0;
3304 if (i
.tm
.opcode_modifier
.vexw
)
3306 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3309 /* If w is not set it means we are dealing with WIG instruction. */
3312 if (evexwig
== evexw1
)
3316 /* Encode the U bit. */
3317 implied_prefix
|= 0x4;
3319 /* The third byte of the EVEX prefix. */
3320 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3322 /* The fourth byte of the EVEX prefix. */
3323 /* The zeroing-masking bit. */
3324 if (i
.mask
&& i
.mask
->zeroing
)
3325 i
.vex
.bytes
[3] |= 0x80;
3327 /* Don't always set the broadcast bit if there is no RC. */
3330 /* Encode the vector length. */
3331 unsigned int vec_length
;
3333 switch (i
.tm
.opcode_modifier
.evex
)
3335 case EVEXLIG
: /* LL' is ignored */
3336 vec_length
= evexlig
<< 5;
3339 vec_length
= 0 << 5;
3342 vec_length
= 1 << 5;
3345 vec_length
= 2 << 5;
3351 i
.vex
.bytes
[3] |= vec_length
;
3352 /* Encode the broadcast bit. */
3354 i
.vex
.bytes
[3] |= 0x10;
3358 if (i
.rounding
->type
!= saeonly
)
3359 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3361 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3364 if (i
.mask
&& i
.mask
->mask
)
3365 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3369 process_immext (void)
3373 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3376 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3377 with an opcode suffix which is coded in the same place as an
3378 8-bit immediate field would be.
3379 Here we check those operands and remove them afterwards. */
3382 for (x
= 0; x
< i
.operands
; x
++)
3383 if (register_number (i
.op
[x
].regs
) != x
)
3384 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3385 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3391 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3392 which is coded in the same place as an 8-bit immediate field
3393 would be. Here we fake an 8-bit immediate operand from the
3394 opcode suffix stored in tm.extension_opcode.
3396 AVX instructions also use this encoding, for some of
3397 3 argument instructions. */
3399 gas_assert (i
.imm_operands
<= 1
3401 || ((i
.tm
.opcode_modifier
.vex
3402 || i
.tm
.opcode_modifier
.evex
)
3403 && i
.operands
<= 4)));
3405 exp
= &im_expressions
[i
.imm_operands
++];
3406 i
.op
[i
.operands
].imms
= exp
;
3407 i
.types
[i
.operands
] = imm8
;
3409 exp
->X_op
= O_constant
;
3410 exp
->X_add_number
= i
.tm
.extension_opcode
;
3411 i
.tm
.extension_opcode
= None
;
3418 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3423 as_bad (_("invalid instruction `%s' after `%s'"),
3424 i
.tm
.name
, i
.hle_prefix
);
3427 if (i
.prefix
[LOCK_PREFIX
])
3429 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3433 case HLEPrefixRelease
:
3434 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3436 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3440 if (i
.mem_operands
== 0
3441 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3443 as_bad (_("memory destination needed for instruction `%s'"
3444 " after `xrelease'"), i
.tm
.name
);
3451 /* This is the guts of the machine-dependent assembler. LINE points to a
3452 machine dependent instruction. This function is supposed to emit
3453 the frags/bytes it assembles to. */
3456 md_assemble (char *line
)
3459 char mnemonic
[MAX_MNEM_SIZE
];
3460 const insn_template
*t
;
3462 /* Initialize globals. */
3463 memset (&i
, '\0', sizeof (i
));
3464 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3465 i
.reloc
[j
] = NO_RELOC
;
3466 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3467 memset (im_expressions
, '\0', sizeof (im_expressions
));
3468 save_stack_p
= save_stack
;
3470 /* First parse an instruction mnemonic & call i386_operand for the operands.
3471 We assume that the scrubber has arranged it so that line[0] is the valid
3472 start of a (possibly prefixed) mnemonic. */
3474 line
= parse_insn (line
, mnemonic
);
3478 line
= parse_operands (line
, mnemonic
);
3483 /* Now we've parsed the mnemonic into a set of templates, and have the
3484 operands at hand. */
3486 /* All intel opcodes have reversed operands except for "bound" and
3487 "enter". We also don't reverse intersegment "jmp" and "call"
3488 instructions with 2 immediate operands so that the immediate segment
3489 precedes the offset, as it does when in AT&T mode. */
3492 && (strcmp (mnemonic
, "bound") != 0)
3493 && (strcmp (mnemonic
, "invlpga") != 0)
3494 && !(operand_type_check (i
.types
[0], imm
)
3495 && operand_type_check (i
.types
[1], imm
)))
3498 /* The order of the immediates should be reversed
3499 for 2 immediates extrq and insertq instructions */
3500 if (i
.imm_operands
== 2
3501 && (strcmp (mnemonic
, "extrq") == 0
3502 || strcmp (mnemonic
, "insertq") == 0))
3503 swap_2_operands (0, 1);
3508 /* Don't optimize displacement for movabs since it only takes 64bit
3511 && i
.disp_encoding
!= disp_encoding_32bit
3512 && (flag_code
!= CODE_64BIT
3513 || strcmp (mnemonic
, "movabs") != 0))
3516 /* Next, we find a template that matches the given insn,
3517 making sure the overlap of the given operands types is consistent
3518 with the template operand types. */
3520 if (!(t
= match_template ()))
3523 if (sse_check
!= check_none
3524 && !i
.tm
.opcode_modifier
.noavx
3525 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3526 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3527 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3528 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3529 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3530 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3532 (sse_check
== check_warning
3534 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3537 /* Zap movzx and movsx suffix. The suffix has been set from
3538 "word ptr" or "byte ptr" on the source operand in Intel syntax
3539 or extracted from mnemonic in AT&T syntax. But we'll use
3540 the destination register to choose the suffix for encoding. */
3541 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3543 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3544 there is no suffix, the default will be byte extension. */
3545 if (i
.reg_operands
!= 2
3548 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3553 if (i
.tm
.opcode_modifier
.fwait
)
3554 if (!add_prefix (FWAIT_OPCODE
))
3557 /* Check if REP prefix is OK. */
3558 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3560 as_bad (_("invalid instruction `%s' after `%s'"),
3561 i
.tm
.name
, i
.rep_prefix
);
3565 /* Check for lock without a lockable instruction. Destination operand
3566 must be memory unless it is xchg (0x86). */
3567 if (i
.prefix
[LOCK_PREFIX
]
3568 && (!i
.tm
.opcode_modifier
.islockable
3569 || i
.mem_operands
== 0
3570 || (i
.tm
.base_opcode
!= 0x86
3571 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3573 as_bad (_("expecting lockable instruction after `lock'"));
3577 /* Check if HLE prefix is OK. */
3578 if (i
.hle_prefix
&& !check_hle ())
3581 /* Check BND prefix. */
3582 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3583 as_bad (_("expecting valid branch instruction after `bnd'"));
3585 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3586 && flag_code
== CODE_64BIT
3587 && i
.prefix
[ADDR_PREFIX
])
3588 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3590 /* Insert BND prefix. */
3592 && i
.tm
.opcode_modifier
.bndprefixok
3593 && !i
.prefix
[BND_PREFIX
])
3594 add_prefix (BND_PREFIX_OPCODE
);
3596 /* Check string instruction segment overrides. */
3597 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3599 if (!check_string ())
3601 i
.disp_operands
= 0;
3604 if (!process_suffix ())
3607 /* Update operand types. */
3608 for (j
= 0; j
< i
.operands
; j
++)
3609 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3611 /* Make still unresolved immediate matches conform to size of immediate
3612 given in i.suffix. */
3613 if (!finalize_imm ())
3616 if (i
.types
[0].bitfield
.imm1
)
3617 i
.imm_operands
= 0; /* kludge for shift insns. */
3619 /* We only need to check those implicit registers for instructions
3620 with 3 operands or less. */
3621 if (i
.operands
<= 3)
3622 for (j
= 0; j
< i
.operands
; j
++)
3623 if (i
.types
[j
].bitfield
.inoutportreg
3624 || i
.types
[j
].bitfield
.shiftcount
3625 || i
.types
[j
].bitfield
.acc
3626 || i
.types
[j
].bitfield
.floatacc
)
3629 /* ImmExt should be processed after SSE2AVX. */
3630 if (!i
.tm
.opcode_modifier
.sse2avx
3631 && i
.tm
.opcode_modifier
.immext
)
3634 /* For insns with operands there are more diddles to do to the opcode. */
3637 if (!process_operands ())
3640 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3642 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3643 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3646 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3648 if (flag_code
== CODE_16BIT
)
3650 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3655 if (i
.tm
.opcode_modifier
.vex
)
3656 build_vex_prefix (t
);
3658 build_evex_prefix ();
3661 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3662 instructions may define INT_OPCODE as well, so avoid this corner
3663 case for those instructions that use MODRM. */
3664 if (i
.tm
.base_opcode
== INT_OPCODE
3665 && !i
.tm
.opcode_modifier
.modrm
3666 && i
.op
[0].imms
->X_add_number
== 3)
3668 i
.tm
.base_opcode
= INT3_OPCODE
;
3672 if ((i
.tm
.opcode_modifier
.jump
3673 || i
.tm
.opcode_modifier
.jumpbyte
3674 || i
.tm
.opcode_modifier
.jumpdword
)
3675 && i
.op
[0].disps
->X_op
== O_constant
)
3677 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3678 the absolute address given by the constant. Since ix86 jumps and
3679 calls are pc relative, we need to generate a reloc. */
3680 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3681 i
.op
[0].disps
->X_op
= O_symbol
;
3684 if (i
.tm
.opcode_modifier
.rex64
)
3687 /* For 8 bit registers we need an empty rex prefix. Also if the
3688 instruction already has a prefix, we need to convert old
3689 registers to new ones. */
3691 if ((i
.types
[0].bitfield
.reg8
3692 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3693 || (i
.types
[1].bitfield
.reg8
3694 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3695 || ((i
.types
[0].bitfield
.reg8
3696 || i
.types
[1].bitfield
.reg8
)
3701 i
.rex
|= REX_OPCODE
;
3702 for (x
= 0; x
< 2; x
++)
3704 /* Look for 8 bit operand that uses old registers. */
3705 if (i
.types
[x
].bitfield
.reg8
3706 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3708 /* In case it is "hi" register, give up. */
3709 if (i
.op
[x
].regs
->reg_num
> 3)
3710 as_bad (_("can't encode register '%s%s' in an "
3711 "instruction requiring REX prefix."),
3712 register_prefix
, i
.op
[x
].regs
->reg_name
);
3714 /* Otherwise it is equivalent to the extended register.
3715 Since the encoding doesn't change this is merely
3716 cosmetic cleanup for debug output. */
3718 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3724 add_prefix (REX_OPCODE
| i
.rex
);
3726 /* We are ready to output the insn. */
3731 parse_insn (char *line
, char *mnemonic
)
3734 char *token_start
= l
;
3737 const insn_template
*t
;
3743 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3748 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3750 as_bad (_("no such instruction: `%s'"), token_start
);
3755 if (!is_space_char (*l
)
3756 && *l
!= END_OF_INSN
3758 || (*l
!= PREFIX_SEPARATOR
3761 as_bad (_("invalid character %s in mnemonic"),
3762 output_invalid (*l
));
3765 if (token_start
== l
)
3767 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3768 as_bad (_("expecting prefix; got nothing"));
3770 as_bad (_("expecting mnemonic; got nothing"));
3774 /* Look up instruction (or prefix) via hash table. */
3775 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3777 if (*l
!= END_OF_INSN
3778 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3779 && current_templates
3780 && current_templates
->start
->opcode_modifier
.isprefix
)
3782 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3784 as_bad ((flag_code
!= CODE_64BIT
3785 ? _("`%s' is only supported in 64-bit mode")
3786 : _("`%s' is not supported in 64-bit mode")),
3787 current_templates
->start
->name
);
3790 /* If we are in 16-bit mode, do not allow addr16 or data16.
3791 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3792 if ((current_templates
->start
->opcode_modifier
.size16
3793 || current_templates
->start
->opcode_modifier
.size32
)
3794 && flag_code
!= CODE_64BIT
3795 && (current_templates
->start
->opcode_modifier
.size32
3796 ^ (flag_code
== CODE_16BIT
)))
3798 as_bad (_("redundant %s prefix"),
3799 current_templates
->start
->name
);
3802 /* Add prefix, checking for repeated prefixes. */
3803 switch (add_prefix (current_templates
->start
->base_opcode
))
3808 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3809 i
.hle_prefix
= current_templates
->start
->name
;
3810 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3811 i
.bnd_prefix
= current_templates
->start
->name
;
3813 i
.rep_prefix
= current_templates
->start
->name
;
3818 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3825 if (!current_templates
)
3827 /* Check if we should swap operand or force 32bit displacement in
3829 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3831 else if (mnem_p
- 3 == dot_p
3834 i
.disp_encoding
= disp_encoding_8bit
;
3835 else if (mnem_p
- 4 == dot_p
3839 i
.disp_encoding
= disp_encoding_32bit
;
3844 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3847 if (!current_templates
)
3850 /* See if we can get a match by trimming off a suffix. */
3853 case WORD_MNEM_SUFFIX
:
3854 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3855 i
.suffix
= SHORT_MNEM_SUFFIX
;
3857 case BYTE_MNEM_SUFFIX
:
3858 case QWORD_MNEM_SUFFIX
:
3859 i
.suffix
= mnem_p
[-1];
3861 current_templates
= (const templates
*) hash_find (op_hash
,
3864 case SHORT_MNEM_SUFFIX
:
3865 case LONG_MNEM_SUFFIX
:
3868 i
.suffix
= mnem_p
[-1];
3870 current_templates
= (const templates
*) hash_find (op_hash
,
3879 if (intel_float_operand (mnemonic
) == 1)
3880 i
.suffix
= SHORT_MNEM_SUFFIX
;
3882 i
.suffix
= LONG_MNEM_SUFFIX
;
3884 current_templates
= (const templates
*) hash_find (op_hash
,
3889 if (!current_templates
)
3891 as_bad (_("no such instruction: `%s'"), token_start
);
3896 if (current_templates
->start
->opcode_modifier
.jump
3897 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3899 /* Check for a branch hint. We allow ",pt" and ",pn" for
3900 predict taken and predict not taken respectively.
3901 I'm not sure that branch hints actually do anything on loop
3902 and jcxz insns (JumpByte) for current Pentium4 chips. They
3903 may work in the future and it doesn't hurt to accept them
3905 if (l
[0] == ',' && l
[1] == 'p')
3909 if (!add_prefix (DS_PREFIX_OPCODE
))
3913 else if (l
[2] == 'n')
3915 if (!add_prefix (CS_PREFIX_OPCODE
))
3921 /* Any other comma loses. */
3924 as_bad (_("invalid character %s in mnemonic"),
3925 output_invalid (*l
));
3929 /* Check if instruction is supported on specified architecture. */
3931 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3933 supported
|= cpu_flags_match (t
);
3934 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3938 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3940 as_bad (flag_code
== CODE_64BIT
3941 ? _("`%s' is not supported in 64-bit mode")
3942 : _("`%s' is only supported in 64-bit mode"),
3943 current_templates
->start
->name
);
3946 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3948 as_bad (_("`%s' is not supported on `%s%s'"),
3949 current_templates
->start
->name
,
3950 cpu_arch_name
? cpu_arch_name
: default_arch
,
3951 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3956 if (!cpu_arch_flags
.bitfield
.cpui386
3957 && (flag_code
!= CODE_16BIT
))
3959 as_warn (_("use .code16 to ensure correct addressing mode"));
3966 parse_operands (char *l
, const char *mnemonic
)
3970 /* 1 if operand is pending after ','. */
3971 unsigned int expecting_operand
= 0;
3973 /* Non-zero if operand parens not balanced. */
3974 unsigned int paren_not_balanced
;
3976 while (*l
!= END_OF_INSN
)
3978 /* Skip optional white space before operand. */
3979 if (is_space_char (*l
))
3981 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3983 as_bad (_("invalid character %s before operand %d"),
3984 output_invalid (*l
),
3988 token_start
= l
; /* after white space */
3989 paren_not_balanced
= 0;
3990 while (paren_not_balanced
|| *l
!= ',')
3992 if (*l
== END_OF_INSN
)
3994 if (paren_not_balanced
)
3997 as_bad (_("unbalanced parenthesis in operand %d."),
4000 as_bad (_("unbalanced brackets in operand %d."),
4005 break; /* we are done */
4007 else if (!is_operand_char (*l
) && !is_space_char (*l
))
4009 as_bad (_("invalid character %s in operand %d"),
4010 output_invalid (*l
),
4017 ++paren_not_balanced
;
4019 --paren_not_balanced
;
4024 ++paren_not_balanced
;
4026 --paren_not_balanced
;
4030 if (l
!= token_start
)
4031 { /* Yes, we've read in another operand. */
4032 unsigned int operand_ok
;
4033 this_operand
= i
.operands
++;
4034 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4035 if (i
.operands
> MAX_OPERANDS
)
4037 as_bad (_("spurious operands; (%d operands/instruction max)"),
4041 /* Now parse operand adding info to 'i' as we go along. */
4042 END_STRING_AND_SAVE (l
);
4046 i386_intel_operand (token_start
,
4047 intel_float_operand (mnemonic
));
4049 operand_ok
= i386_att_operand (token_start
);
4051 RESTORE_END_STRING (l
);
4057 if (expecting_operand
)
4059 expecting_operand_after_comma
:
4060 as_bad (_("expecting operand after ','; got nothing"));
4065 as_bad (_("expecting operand before ','; got nothing"));
4070 /* Now *l must be either ',' or END_OF_INSN. */
4073 if (*++l
== END_OF_INSN
)
4075 /* Just skip it, if it's \n complain. */
4076 goto expecting_operand_after_comma
;
4078 expecting_operand
= 1;
4085 swap_2_operands (int xchg1
, int xchg2
)
4087 union i386_op temp_op
;
4088 i386_operand_type temp_type
;
4089 enum bfd_reloc_code_real temp_reloc
;
4091 temp_type
= i
.types
[xchg2
];
4092 i
.types
[xchg2
] = i
.types
[xchg1
];
4093 i
.types
[xchg1
] = temp_type
;
4094 temp_op
= i
.op
[xchg2
];
4095 i
.op
[xchg2
] = i
.op
[xchg1
];
4096 i
.op
[xchg1
] = temp_op
;
4097 temp_reloc
= i
.reloc
[xchg2
];
4098 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4099 i
.reloc
[xchg1
] = temp_reloc
;
4103 if (i
.mask
->operand
== xchg1
)
4104 i
.mask
->operand
= xchg2
;
4105 else if (i
.mask
->operand
== xchg2
)
4106 i
.mask
->operand
= xchg1
;
4110 if (i
.broadcast
->operand
== xchg1
)
4111 i
.broadcast
->operand
= xchg2
;
4112 else if (i
.broadcast
->operand
== xchg2
)
4113 i
.broadcast
->operand
= xchg1
;
4117 if (i
.rounding
->operand
== xchg1
)
4118 i
.rounding
->operand
= xchg2
;
4119 else if (i
.rounding
->operand
== xchg2
)
4120 i
.rounding
->operand
= xchg1
;
4125 swap_operands (void)
4131 swap_2_operands (1, i
.operands
- 2);
4134 swap_2_operands (0, i
.operands
- 1);
4140 if (i
.mem_operands
== 2)
4142 const seg_entry
*temp_seg
;
4143 temp_seg
= i
.seg
[0];
4144 i
.seg
[0] = i
.seg
[1];
4145 i
.seg
[1] = temp_seg
;
4149 /* Try to ensure constant immediates are represented in the smallest
4154 char guess_suffix
= 0;
4158 guess_suffix
= i
.suffix
;
4159 else if (i
.reg_operands
)
4161 /* Figure out a suffix from the last register operand specified.
4162 We can't do this properly yet, ie. excluding InOutPortReg,
4163 but the following works for instructions with immediates.
4164 In any case, we can't set i.suffix yet. */
4165 for (op
= i
.operands
; --op
>= 0;)
4166 if (i
.types
[op
].bitfield
.reg8
)
4168 guess_suffix
= BYTE_MNEM_SUFFIX
;
4171 else if (i
.types
[op
].bitfield
.reg16
)
4173 guess_suffix
= WORD_MNEM_SUFFIX
;
4176 else if (i
.types
[op
].bitfield
.reg32
)
4178 guess_suffix
= LONG_MNEM_SUFFIX
;
4181 else if (i
.types
[op
].bitfield
.reg64
)
4183 guess_suffix
= QWORD_MNEM_SUFFIX
;
4187 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4188 guess_suffix
= WORD_MNEM_SUFFIX
;
4190 for (op
= i
.operands
; --op
>= 0;)
4191 if (operand_type_check (i
.types
[op
], imm
))
4193 switch (i
.op
[op
].imms
->X_op
)
4196 /* If a suffix is given, this operand may be shortened. */
4197 switch (guess_suffix
)
4199 case LONG_MNEM_SUFFIX
:
4200 i
.types
[op
].bitfield
.imm32
= 1;
4201 i
.types
[op
].bitfield
.imm64
= 1;
4203 case WORD_MNEM_SUFFIX
:
4204 i
.types
[op
].bitfield
.imm16
= 1;
4205 i
.types
[op
].bitfield
.imm32
= 1;
4206 i
.types
[op
].bitfield
.imm32s
= 1;
4207 i
.types
[op
].bitfield
.imm64
= 1;
4209 case BYTE_MNEM_SUFFIX
:
4210 i
.types
[op
].bitfield
.imm8
= 1;
4211 i
.types
[op
].bitfield
.imm8s
= 1;
4212 i
.types
[op
].bitfield
.imm16
= 1;
4213 i
.types
[op
].bitfield
.imm32
= 1;
4214 i
.types
[op
].bitfield
.imm32s
= 1;
4215 i
.types
[op
].bitfield
.imm64
= 1;
4219 /* If this operand is at most 16 bits, convert it
4220 to a signed 16 bit number before trying to see
4221 whether it will fit in an even smaller size.
4222 This allows a 16-bit operand such as $0xffe0 to
4223 be recognised as within Imm8S range. */
4224 if ((i
.types
[op
].bitfield
.imm16
)
4225 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4227 i
.op
[op
].imms
->X_add_number
=
4228 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4230 if ((i
.types
[op
].bitfield
.imm32
)
4231 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4234 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4235 ^ ((offsetT
) 1 << 31))
4236 - ((offsetT
) 1 << 31));
4239 = operand_type_or (i
.types
[op
],
4240 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4242 /* We must avoid matching of Imm32 templates when 64bit
4243 only immediate is available. */
4244 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4245 i
.types
[op
].bitfield
.imm32
= 0;
4252 /* Symbols and expressions. */
4254 /* Convert symbolic operand to proper sizes for matching, but don't
4255 prevent matching a set of insns that only supports sizes other
4256 than those matching the insn suffix. */
4258 i386_operand_type mask
, allowed
;
4259 const insn_template
*t
;
4261 operand_type_set (&mask
, 0);
4262 operand_type_set (&allowed
, 0);
4264 for (t
= current_templates
->start
;
4265 t
< current_templates
->end
;
4267 allowed
= operand_type_or (allowed
,
4268 t
->operand_types
[op
]);
4269 switch (guess_suffix
)
4271 case QWORD_MNEM_SUFFIX
:
4272 mask
.bitfield
.imm64
= 1;
4273 mask
.bitfield
.imm32s
= 1;
4275 case LONG_MNEM_SUFFIX
:
4276 mask
.bitfield
.imm32
= 1;
4278 case WORD_MNEM_SUFFIX
:
4279 mask
.bitfield
.imm16
= 1;
4281 case BYTE_MNEM_SUFFIX
:
4282 mask
.bitfield
.imm8
= 1;
4287 allowed
= operand_type_and (mask
, allowed
);
4288 if (!operand_type_all_zero (&allowed
))
4289 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4296 /* Try to use the smallest displacement type too. */
4298 optimize_disp (void)
4302 for (op
= i
.operands
; --op
>= 0;)
4303 if (operand_type_check (i
.types
[op
], disp
))
4305 if (i
.op
[op
].disps
->X_op
== O_constant
)
4307 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4309 if (i
.types
[op
].bitfield
.disp16
4310 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4312 /* If this operand is at most 16 bits, convert
4313 to a signed 16 bit number and don't use 64bit
4315 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4316 i
.types
[op
].bitfield
.disp64
= 0;
4318 if (i
.types
[op
].bitfield
.disp32
4319 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4321 /* If this operand is at most 32 bits, convert
4322 to a signed 32 bit number and don't use 64bit
4324 op_disp
&= (((offsetT
) 2 << 31) - 1);
4325 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4326 i
.types
[op
].bitfield
.disp64
= 0;
4328 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4330 i
.types
[op
].bitfield
.disp8
= 0;
4331 i
.types
[op
].bitfield
.disp16
= 0;
4332 i
.types
[op
].bitfield
.disp32
= 0;
4333 i
.types
[op
].bitfield
.disp32s
= 0;
4334 i
.types
[op
].bitfield
.disp64
= 0;
4338 else if (flag_code
== CODE_64BIT
)
4340 if (fits_in_signed_long (op_disp
))
4342 i
.types
[op
].bitfield
.disp64
= 0;
4343 i
.types
[op
].bitfield
.disp32s
= 1;
4345 if (i
.prefix
[ADDR_PREFIX
]
4346 && fits_in_unsigned_long (op_disp
))
4347 i
.types
[op
].bitfield
.disp32
= 1;
4349 if ((i
.types
[op
].bitfield
.disp32
4350 || i
.types
[op
].bitfield
.disp32s
4351 || i
.types
[op
].bitfield
.disp16
)
4352 && fits_in_signed_byte (op_disp
))
4353 i
.types
[op
].bitfield
.disp8
= 1;
4355 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4356 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4358 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4359 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4360 i
.types
[op
].bitfield
.disp8
= 0;
4361 i
.types
[op
].bitfield
.disp16
= 0;
4362 i
.types
[op
].bitfield
.disp32
= 0;
4363 i
.types
[op
].bitfield
.disp32s
= 0;
4364 i
.types
[op
].bitfield
.disp64
= 0;
4367 /* We only support 64bit displacement on constants. */
4368 i
.types
[op
].bitfield
.disp64
= 0;
4372 /* Check if operands are valid for the instruction. */
4375 check_VecOperands (const insn_template
*t
)
4379 /* Without VSIB byte, we can't have a vector register for index. */
4380 if (!t
->opcode_modifier
.vecsib
4382 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4383 || i
.index_reg
->reg_type
.bitfield
.regymm
4384 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4386 i
.error
= unsupported_vector_index_register
;
4390 /* Check if default mask is allowed. */
4391 if (t
->opcode_modifier
.nodefmask
4392 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4394 i
.error
= no_default_mask
;
4398 /* For VSIB byte, we need a vector register for index, and all vector
4399 registers must be distinct. */
4400 if (t
->opcode_modifier
.vecsib
)
4403 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4404 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4405 || (t
->opcode_modifier
.vecsib
== VecSIB256
4406 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4407 || (t
->opcode_modifier
.vecsib
== VecSIB512
4408 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4410 i
.error
= invalid_vsib_address
;
4414 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4415 if (i
.reg_operands
== 2 && !i
.mask
)
4417 gas_assert (i
.types
[0].bitfield
.regxmm
4418 || i
.types
[0].bitfield
.regymm
);
4419 gas_assert (i
.types
[2].bitfield
.regxmm
4420 || i
.types
[2].bitfield
.regymm
);
4421 if (operand_check
== check_none
)
4423 if (register_number (i
.op
[0].regs
)
4424 != register_number (i
.index_reg
)
4425 && register_number (i
.op
[2].regs
)
4426 != register_number (i
.index_reg
)
4427 && register_number (i
.op
[0].regs
)
4428 != register_number (i
.op
[2].regs
))
4430 if (operand_check
== check_error
)
4432 i
.error
= invalid_vector_register_set
;
4435 as_warn (_("mask, index, and destination registers should be distinct"));
4437 else if (i
.reg_operands
== 1 && i
.mask
)
4439 if ((i
.types
[1].bitfield
.regymm
4440 || i
.types
[1].bitfield
.regzmm
)
4441 && (register_number (i
.op
[1].regs
)
4442 == register_number (i
.index_reg
)))
4444 if (operand_check
== check_error
)
4446 i
.error
= invalid_vector_register_set
;
4449 if (operand_check
!= check_none
)
4450 as_warn (_("index and destination registers should be distinct"));
4455 /* Check if broadcast is supported by the instruction and is applied
4456 to the memory operand. */
4459 int broadcasted_opnd_size
;
4461 /* Check if specified broadcast is supported in this instruction,
4462 and it's applied to memory operand of DWORD or QWORD type,
4463 depending on VecESize. */
4464 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4465 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4466 || (t
->opcode_modifier
.vecesize
== 0
4467 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4468 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4469 || (t
->opcode_modifier
.vecesize
== 1
4470 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4471 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4474 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4475 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4476 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4477 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4478 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4479 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4480 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4481 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4482 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4486 if ((broadcasted_opnd_size
== 256
4487 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4488 || (broadcasted_opnd_size
== 512
4489 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4492 i
.error
= unsupported_broadcast
;
4496 /* If broadcast is supported in this instruction, we need to check if
4497 operand of one-element size isn't specified without broadcast. */
4498 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4500 /* Find memory operand. */
4501 for (op
= 0; op
< i
.operands
; op
++)
4502 if (operand_type_check (i
.types
[op
], anymem
))
4504 gas_assert (op
< i
.operands
);
4505 /* Check size of the memory operand. */
4506 if ((t
->opcode_modifier
.vecesize
== 0
4507 && i
.types
[op
].bitfield
.dword
)
4508 || (t
->opcode_modifier
.vecesize
== 1
4509 && i
.types
[op
].bitfield
.qword
))
4511 i
.error
= broadcast_needed
;
4516 /* Check if requested masking is supported. */
4518 && (!t
->opcode_modifier
.masking
4520 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4522 i
.error
= unsupported_masking
;
4526 /* Check if masking is applied to dest operand. */
4527 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4529 i
.error
= mask_not_on_destination
;
4536 if ((i
.rounding
->type
!= saeonly
4537 && !t
->opcode_modifier
.staticrounding
)
4538 || (i
.rounding
->type
== saeonly
4539 && (t
->opcode_modifier
.staticrounding
4540 || !t
->opcode_modifier
.sae
)))
4542 i
.error
= unsupported_rc_sae
;
4545 /* If the instruction has several immediate operands and one of
4546 them is rounding, the rounding operand should be the last
4547 immediate operand. */
4548 if (i
.imm_operands
> 1
4549 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4551 i
.error
= rc_sae_operand_not_last_imm
;
4556 /* Check vector Disp8 operand. */
4557 if (t
->opcode_modifier
.disp8memshift
)
4560 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4562 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4564 for (op
= 0; op
< i
.operands
; op
++)
4565 if (operand_type_check (i
.types
[op
], disp
)
4566 && i
.op
[op
].disps
->X_op
== O_constant
)
4568 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4569 int vec_disp8_ok
= fits_in_vec_disp8 (value
);
4570 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4573 i
.types
[op
].bitfield
.vec_disp8
= 1;
4576 /* Vector insn can only have Vec_Disp8/Disp32 in
4577 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4579 i
.types
[op
].bitfield
.disp8
= 0;
4580 if (flag_code
!= CODE_16BIT
)
4581 i
.types
[op
].bitfield
.disp16
= 0;
4584 else if (flag_code
!= CODE_16BIT
)
4586 /* One form of this instruction supports vector Disp8.
4587 Try vector Disp8 if we need to use Disp32. */
4588 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4590 i
.error
= try_vector_disp8
;
4602 /* Check if operands are valid for the instruction. Update VEX
4606 VEX_check_operands (const insn_template
*t
)
4608 /* VREX is only valid with EVEX prefix. */
4609 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4611 i
.error
= invalid_register_operand
;
4615 if (!t
->opcode_modifier
.vex
)
4618 /* Only check VEX_Imm4, which must be the first operand. */
4619 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4621 if (i
.op
[0].imms
->X_op
!= O_constant
4622 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4628 /* Turn off Imm8 so that update_imm won't complain. */
4629 i
.types
[0] = vec_imm4
;
4635 static const insn_template
*
4636 match_template (void)
4638 /* Points to template once we've found it. */
4639 const insn_template
*t
;
4640 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4641 i386_operand_type overlap4
;
4642 unsigned int found_reverse_match
;
4643 i386_opcode_modifier suffix_check
;
4644 i386_operand_type operand_types
[MAX_OPERANDS
];
4645 int addr_prefix_disp
;
4647 unsigned int found_cpu_match
;
4648 unsigned int check_register
;
4649 enum i386_error specific_error
= 0;
4651 #if MAX_OPERANDS != 5
4652 # error "MAX_OPERANDS must be 5."
4655 found_reverse_match
= 0;
4656 addr_prefix_disp
= -1;
4658 memset (&suffix_check
, 0, sizeof (suffix_check
));
4659 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4660 suffix_check
.no_bsuf
= 1;
4661 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4662 suffix_check
.no_wsuf
= 1;
4663 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4664 suffix_check
.no_ssuf
= 1;
4665 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4666 suffix_check
.no_lsuf
= 1;
4667 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4668 suffix_check
.no_qsuf
= 1;
4669 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4670 suffix_check
.no_ldsuf
= 1;
4672 /* Must have right number of operands. */
4673 i
.error
= number_of_operands_mismatch
;
4675 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4677 addr_prefix_disp
= -1;
4679 if (i
.operands
!= t
->operands
)
4682 /* Check processor support. */
4683 i
.error
= unsupported
;
4684 found_cpu_match
= (cpu_flags_match (t
)
4685 == CPU_FLAGS_PERFECT_MATCH
);
4686 if (!found_cpu_match
)
4689 /* Check old gcc support. */
4690 i
.error
= old_gcc_only
;
4691 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4694 /* Check AT&T mnemonic. */
4695 i
.error
= unsupported_with_intel_mnemonic
;
4696 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4699 /* Check AT&T/Intel syntax. */
4700 i
.error
= unsupported_syntax
;
4701 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4702 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4705 /* Check the suffix, except for some instructions in intel mode. */
4706 i
.error
= invalid_instruction_suffix
;
4707 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4708 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4709 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4710 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4711 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4712 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4713 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4716 if (!operand_size_match (t
))
4719 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4720 operand_types
[j
] = t
->operand_types
[j
];
4722 /* In general, don't allow 64-bit operands in 32-bit mode. */
4723 if (i
.suffix
== QWORD_MNEM_SUFFIX
4724 && flag_code
!= CODE_64BIT
4726 ? (!t
->opcode_modifier
.ignoresize
4727 && !intel_float_operand (t
->name
))
4728 : intel_float_operand (t
->name
) != 2)
4729 && ((!operand_types
[0].bitfield
.regmmx
4730 && !operand_types
[0].bitfield
.regxmm
4731 && !operand_types
[0].bitfield
.regymm
4732 && !operand_types
[0].bitfield
.regzmm
)
4733 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4734 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4735 && operand_types
[t
->operands
> 1].bitfield
.regymm
4736 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4737 && (t
->base_opcode
!= 0x0fc7
4738 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4741 /* In general, don't allow 32-bit operands on pre-386. */
4742 else if (i
.suffix
== LONG_MNEM_SUFFIX
4743 && !cpu_arch_flags
.bitfield
.cpui386
4745 ? (!t
->opcode_modifier
.ignoresize
4746 && !intel_float_operand (t
->name
))
4747 : intel_float_operand (t
->name
) != 2)
4748 && ((!operand_types
[0].bitfield
.regmmx
4749 && !operand_types
[0].bitfield
.regxmm
)
4750 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4751 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4754 /* Do not verify operands when there are none. */
4758 /* We've found a match; break out of loop. */
4762 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4763 into Disp32/Disp16/Disp32 operand. */
4764 if (i
.prefix
[ADDR_PREFIX
] != 0)
4766 /* There should be only one Disp operand. */
4770 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4772 if (operand_types
[j
].bitfield
.disp16
)
4774 addr_prefix_disp
= j
;
4775 operand_types
[j
].bitfield
.disp32
= 1;
4776 operand_types
[j
].bitfield
.disp16
= 0;
4782 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4784 if (operand_types
[j
].bitfield
.disp32
)
4786 addr_prefix_disp
= j
;
4787 operand_types
[j
].bitfield
.disp32
= 0;
4788 operand_types
[j
].bitfield
.disp16
= 1;
4794 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4796 if (operand_types
[j
].bitfield
.disp64
)
4798 addr_prefix_disp
= j
;
4799 operand_types
[j
].bitfield
.disp64
= 0;
4800 operand_types
[j
].bitfield
.disp32
= 1;
4808 /* We check register size if needed. */
4809 check_register
= t
->opcode_modifier
.checkregsize
;
4810 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4811 switch (t
->operands
)
4814 if (!operand_type_match (overlap0
, i
.types
[0]))
4818 /* xchg %eax, %eax is a special case. It is an aliase for nop
4819 only in 32bit mode and we can use opcode 0x90. In 64bit
4820 mode, we can't use 0x90 for xchg %eax, %eax since it should
4821 zero-extend %eax to %rax. */
4822 if (flag_code
== CODE_64BIT
4823 && t
->base_opcode
== 0x90
4824 && operand_type_equal (&i
.types
[0], &acc32
)
4825 && operand_type_equal (&i
.types
[1], &acc32
))
4829 /* If we swap operand in encoding, we either match
4830 the next one or reverse direction of operands. */
4831 if (t
->opcode_modifier
.s
)
4833 else if (t
->opcode_modifier
.d
)
4838 /* If we swap operand in encoding, we match the next one. */
4839 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4843 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4844 if (!operand_type_match (overlap0
, i
.types
[0])
4845 || !operand_type_match (overlap1
, i
.types
[1])
4847 && !operand_type_register_match (overlap0
, i
.types
[0],
4849 overlap1
, i
.types
[1],
4852 /* Check if other direction is valid ... */
4853 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4857 /* Try reversing direction of operands. */
4858 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4859 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4860 if (!operand_type_match (overlap0
, i
.types
[0])
4861 || !operand_type_match (overlap1
, i
.types
[1])
4863 && !operand_type_register_match (overlap0
,
4870 /* Does not match either direction. */
4873 /* found_reverse_match holds which of D or FloatDR
4875 if (t
->opcode_modifier
.d
)
4876 found_reverse_match
= Opcode_D
;
4877 else if (t
->opcode_modifier
.floatd
)
4878 found_reverse_match
= Opcode_FloatD
;
4880 found_reverse_match
= 0;
4881 if (t
->opcode_modifier
.floatr
)
4882 found_reverse_match
|= Opcode_FloatR
;
4886 /* Found a forward 2 operand match here. */
4887 switch (t
->operands
)
4890 overlap4
= operand_type_and (i
.types
[4],
4893 overlap3
= operand_type_and (i
.types
[3],
4896 overlap2
= operand_type_and (i
.types
[2],
4901 switch (t
->operands
)
4904 if (!operand_type_match (overlap4
, i
.types
[4])
4905 || !operand_type_register_match (overlap3
,
4913 if (!operand_type_match (overlap3
, i
.types
[3])
4915 && !operand_type_register_match (overlap2
,
4923 /* Here we make use of the fact that there are no
4924 reverse match 3 operand instructions, and all 3
4925 operand instructions only need to be checked for
4926 register consistency between operands 2 and 3. */
4927 if (!operand_type_match (overlap2
, i
.types
[2])
4929 && !operand_type_register_match (overlap1
,
4939 /* Found either forward/reverse 2, 3 or 4 operand match here:
4940 slip through to break. */
4942 if (!found_cpu_match
)
4944 found_reverse_match
= 0;
4948 /* Check if vector and VEX operands are valid. */
4949 if (check_VecOperands (t
) || VEX_check_operands (t
))
4951 specific_error
= i
.error
;
4955 /* We've found a match; break out of loop. */
4959 if (t
== current_templates
->end
)
4961 /* We found no match. */
4962 const char *err_msg
;
4963 switch (specific_error
? specific_error
: i
.error
)
4967 case operand_size_mismatch
:
4968 err_msg
= _("operand size mismatch");
4970 case operand_type_mismatch
:
4971 err_msg
= _("operand type mismatch");
4973 case register_type_mismatch
:
4974 err_msg
= _("register type mismatch");
4976 case number_of_operands_mismatch
:
4977 err_msg
= _("number of operands mismatch");
4979 case invalid_instruction_suffix
:
4980 err_msg
= _("invalid instruction suffix");
4983 err_msg
= _("constant doesn't fit in 4 bits");
4986 err_msg
= _("only supported with old gcc");
4988 case unsupported_with_intel_mnemonic
:
4989 err_msg
= _("unsupported with Intel mnemonic");
4991 case unsupported_syntax
:
4992 err_msg
= _("unsupported syntax");
4995 as_bad (_("unsupported instruction `%s'"),
4996 current_templates
->start
->name
);
4998 case invalid_vsib_address
:
4999 err_msg
= _("invalid VSIB address");
5001 case invalid_vector_register_set
:
5002 err_msg
= _("mask, index, and destination registers must be distinct");
5004 case unsupported_vector_index_register
:
5005 err_msg
= _("unsupported vector index register");
5007 case unsupported_broadcast
:
5008 err_msg
= _("unsupported broadcast");
5010 case broadcast_not_on_src_operand
:
5011 err_msg
= _("broadcast not on source memory operand");
5013 case broadcast_needed
:
5014 err_msg
= _("broadcast is needed for operand of such type");
5016 case unsupported_masking
:
5017 err_msg
= _("unsupported masking");
5019 case mask_not_on_destination
:
5020 err_msg
= _("mask not on destination operand");
5022 case no_default_mask
:
5023 err_msg
= _("default mask isn't allowed");
5025 case unsupported_rc_sae
:
5026 err_msg
= _("unsupported static rounding/sae");
5028 case rc_sae_operand_not_last_imm
:
5030 err_msg
= _("RC/SAE operand must precede immediate operands");
5032 err_msg
= _("RC/SAE operand must follow immediate operands");
5034 case invalid_register_operand
:
5035 err_msg
= _("invalid register operand");
5038 as_bad (_("%s for `%s'"), err_msg
,
5039 current_templates
->start
->name
);
5043 if (!quiet_warnings
)
5046 && (i
.types
[0].bitfield
.jumpabsolute
5047 != operand_types
[0].bitfield
.jumpabsolute
))
5049 as_warn (_("indirect %s without `*'"), t
->name
);
5052 if (t
->opcode_modifier
.isprefix
5053 && t
->opcode_modifier
.ignoresize
)
5055 /* Warn them that a data or address size prefix doesn't
5056 affect assembly of the next line of code. */
5057 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5061 /* Copy the template we found. */
5064 if (addr_prefix_disp
!= -1)
5065 i
.tm
.operand_types
[addr_prefix_disp
]
5066 = operand_types
[addr_prefix_disp
];
5068 if (found_reverse_match
)
5070 /* If we found a reverse match we must alter the opcode
5071 direction bit. found_reverse_match holds bits to change
5072 (different for int & float insns). */
5074 i
.tm
.base_opcode
^= found_reverse_match
;
5076 i
.tm
.operand_types
[0] = operand_types
[1];
5077 i
.tm
.operand_types
[1] = operand_types
[0];
5086 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5087 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5089 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5091 as_bad (_("`%s' operand %d must use `%ses' segment"),
5097 /* There's only ever one segment override allowed per instruction.
5098 This instruction possibly has a legal segment override on the
5099 second operand, so copy the segment to where non-string
5100 instructions store it, allowing common code. */
5101 i
.seg
[0] = i
.seg
[1];
5103 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5105 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5107 as_bad (_("`%s' operand %d must use `%ses' segment"),
5118 process_suffix (void)
5120 /* If matched instruction specifies an explicit instruction mnemonic
5122 if (i
.tm
.opcode_modifier
.size16
)
5123 i
.suffix
= WORD_MNEM_SUFFIX
;
5124 else if (i
.tm
.opcode_modifier
.size32
)
5125 i
.suffix
= LONG_MNEM_SUFFIX
;
5126 else if (i
.tm
.opcode_modifier
.size64
)
5127 i
.suffix
= QWORD_MNEM_SUFFIX
;
5128 else if (i
.reg_operands
)
5130 /* If there's no instruction mnemonic suffix we try to invent one
5131 based on register operands. */
5134 /* We take i.suffix from the last register operand specified,
5135 Destination register type is more significant than source
5136 register type. crc32 in SSE4.2 prefers source register
5138 if (i
.tm
.base_opcode
== 0xf20f38f1)
5140 if (i
.types
[0].bitfield
.reg16
)
5141 i
.suffix
= WORD_MNEM_SUFFIX
;
5142 else if (i
.types
[0].bitfield
.reg32
)
5143 i
.suffix
= LONG_MNEM_SUFFIX
;
5144 else if (i
.types
[0].bitfield
.reg64
)
5145 i
.suffix
= QWORD_MNEM_SUFFIX
;
5147 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5149 if (i
.types
[0].bitfield
.reg8
)
5150 i
.suffix
= BYTE_MNEM_SUFFIX
;
5157 if (i
.tm
.base_opcode
== 0xf20f38f1
5158 || i
.tm
.base_opcode
== 0xf20f38f0)
5160 /* We have to know the operand size for crc32. */
5161 as_bad (_("ambiguous memory operand size for `%s`"),
5166 for (op
= i
.operands
; --op
>= 0;)
5167 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5169 if (i
.types
[op
].bitfield
.reg8
)
5171 i
.suffix
= BYTE_MNEM_SUFFIX
;
5174 else if (i
.types
[op
].bitfield
.reg16
)
5176 i
.suffix
= WORD_MNEM_SUFFIX
;
5179 else if (i
.types
[op
].bitfield
.reg32
)
5181 i
.suffix
= LONG_MNEM_SUFFIX
;
5184 else if (i
.types
[op
].bitfield
.reg64
)
5186 i
.suffix
= QWORD_MNEM_SUFFIX
;
5192 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5195 && i
.tm
.opcode_modifier
.ignoresize
5196 && i
.tm
.opcode_modifier
.no_bsuf
)
5198 else if (!check_byte_reg ())
5201 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5204 && i
.tm
.opcode_modifier
.ignoresize
5205 && i
.tm
.opcode_modifier
.no_lsuf
)
5207 else if (!check_long_reg ())
5210 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5213 && i
.tm
.opcode_modifier
.ignoresize
5214 && i
.tm
.opcode_modifier
.no_qsuf
)
5216 else if (!check_qword_reg ())
5219 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5222 && i
.tm
.opcode_modifier
.ignoresize
5223 && i
.tm
.opcode_modifier
.no_wsuf
)
5225 else if (!check_word_reg ())
5228 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5229 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5230 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5232 /* Skip if the instruction has x/y/z suffix. match_template
5233 should check if it is a valid suffix. */
5235 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5236 /* Do nothing if the instruction is going to ignore the prefix. */
5241 else if (i
.tm
.opcode_modifier
.defaultsize
5243 /* exclude fldenv/frstor/fsave/fstenv */
5244 && i
.tm
.opcode_modifier
.no_ssuf
)
5246 i
.suffix
= stackop_size
;
5248 else if (intel_syntax
5250 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5251 || i
.tm
.opcode_modifier
.jumpbyte
5252 || i
.tm
.opcode_modifier
.jumpintersegment
5253 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5254 && i
.tm
.extension_opcode
<= 3)))
5259 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5261 i
.suffix
= QWORD_MNEM_SUFFIX
;
5265 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5266 i
.suffix
= LONG_MNEM_SUFFIX
;
5269 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5270 i
.suffix
= WORD_MNEM_SUFFIX
;
5279 if (i
.tm
.opcode_modifier
.w
)
5281 as_bad (_("no instruction mnemonic suffix given and "
5282 "no register operands; can't size instruction"));
5288 unsigned int suffixes
;
5290 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5291 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5293 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5295 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5297 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5299 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5302 /* There are more than suffix matches. */
5303 if (i
.tm
.opcode_modifier
.w
5304 || ((suffixes
& (suffixes
- 1))
5305 && !i
.tm
.opcode_modifier
.defaultsize
5306 && !i
.tm
.opcode_modifier
.ignoresize
))
5308 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5314 /* Change the opcode based on the operand size given by i.suffix;
5315 We don't need to change things for byte insns. */
5318 && i
.suffix
!= BYTE_MNEM_SUFFIX
5319 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5320 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5321 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5323 /* It's not a byte, select word/dword operation. */
5324 if (i
.tm
.opcode_modifier
.w
)
5326 if (i
.tm
.opcode_modifier
.shortform
)
5327 i
.tm
.base_opcode
|= 8;
5329 i
.tm
.base_opcode
|= 1;
5332 /* Now select between word & dword operations via the operand
5333 size prefix, except for instructions that will ignore this
5335 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5337 /* The address size override prefix changes the size of the
5339 if ((flag_code
== CODE_32BIT
5340 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5341 || (flag_code
!= CODE_32BIT
5342 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5343 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5346 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5347 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5348 && !i
.tm
.opcode_modifier
.ignoresize
5349 && !i
.tm
.opcode_modifier
.floatmf
5350 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5351 || (flag_code
== CODE_64BIT
5352 && i
.tm
.opcode_modifier
.jumpbyte
)))
5354 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5356 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5357 prefix
= ADDR_PREFIX_OPCODE
;
5359 if (!add_prefix (prefix
))
5363 /* Set mode64 for an operand. */
5364 if (i
.suffix
== QWORD_MNEM_SUFFIX
5365 && flag_code
== CODE_64BIT
5366 && !i
.tm
.opcode_modifier
.norex64
)
5368 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5369 need rex64. cmpxchg8b is also a special case. */
5370 if (! (i
.operands
== 2
5371 && i
.tm
.base_opcode
== 0x90
5372 && i
.tm
.extension_opcode
== None
5373 && operand_type_equal (&i
.types
[0], &acc64
)
5374 && operand_type_equal (&i
.types
[1], &acc64
))
5375 && ! (i
.operands
== 1
5376 && i
.tm
.base_opcode
== 0xfc7
5377 && i
.tm
.extension_opcode
== 1
5378 && !operand_type_check (i
.types
[0], reg
)
5379 && operand_type_check (i
.types
[0], anymem
)))
5383 /* Size floating point instruction. */
5384 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5385 if (i
.tm
.opcode_modifier
.floatmf
)
5386 i
.tm
.base_opcode
^= 4;
5393 check_byte_reg (void)
5397 for (op
= i
.operands
; --op
>= 0;)
5399 /* If this is an eight bit register, it's OK. If it's the 16 or
5400 32 bit version of an eight bit register, we will just use the
5401 low portion, and that's OK too. */
5402 if (i
.types
[op
].bitfield
.reg8
)
5405 /* I/O port address operands are OK too. */
5406 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5409 /* crc32 doesn't generate this warning. */
5410 if (i
.tm
.base_opcode
== 0xf20f38f0)
5413 if ((i
.types
[op
].bitfield
.reg16
5414 || i
.types
[op
].bitfield
.reg32
5415 || i
.types
[op
].bitfield
.reg64
)
5416 && i
.op
[op
].regs
->reg_num
< 4
5417 /* Prohibit these changes in 64bit mode, since the lowering
5418 would be more complicated. */
5419 && flag_code
!= CODE_64BIT
)
5421 #if REGISTER_WARNINGS
5422 if (!quiet_warnings
)
5423 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5425 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5426 ? REGNAM_AL
- REGNAM_AX
5427 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5429 i
.op
[op
].regs
->reg_name
,
5434 /* Any other register is bad. */
5435 if (i
.types
[op
].bitfield
.reg16
5436 || i
.types
[op
].bitfield
.reg32
5437 || i
.types
[op
].bitfield
.reg64
5438 || i
.types
[op
].bitfield
.regmmx
5439 || i
.types
[op
].bitfield
.regxmm
5440 || i
.types
[op
].bitfield
.regymm
5441 || i
.types
[op
].bitfield
.regzmm
5442 || i
.types
[op
].bitfield
.sreg2
5443 || i
.types
[op
].bitfield
.sreg3
5444 || i
.types
[op
].bitfield
.control
5445 || i
.types
[op
].bitfield
.debug
5446 || i
.types
[op
].bitfield
.test
5447 || i
.types
[op
].bitfield
.floatreg
5448 || i
.types
[op
].bitfield
.floatacc
)
5450 as_bad (_("`%s%s' not allowed with `%s%c'"),
5452 i
.op
[op
].regs
->reg_name
,
5462 check_long_reg (void)
5466 for (op
= i
.operands
; --op
>= 0;)
5467 /* Reject eight bit registers, except where the template requires
5468 them. (eg. movzb) */
5469 if (i
.types
[op
].bitfield
.reg8
5470 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5471 || i
.tm
.operand_types
[op
].bitfield
.reg32
5472 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5474 as_bad (_("`%s%s' not allowed with `%s%c'"),
5476 i
.op
[op
].regs
->reg_name
,
5481 /* Warn if the e prefix on a general reg is missing. */
5482 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5483 && i
.types
[op
].bitfield
.reg16
5484 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5485 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5487 /* Prohibit these changes in the 64bit mode, since the
5488 lowering is more complicated. */
5489 if (flag_code
== CODE_64BIT
)
5491 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5492 register_prefix
, i
.op
[op
].regs
->reg_name
,
5496 #if REGISTER_WARNINGS
5497 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5499 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5500 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5503 /* Warn if the r prefix on a general reg is present. */
5504 else if (i
.types
[op
].bitfield
.reg64
5505 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5506 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5509 && i
.tm
.opcode_modifier
.toqword
5510 && !i
.types
[0].bitfield
.regxmm
)
5512 /* Convert to QWORD. We want REX byte. */
5513 i
.suffix
= QWORD_MNEM_SUFFIX
;
5517 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5518 register_prefix
, i
.op
[op
].regs
->reg_name
,
5527 check_qword_reg (void)
5531 for (op
= i
.operands
; --op
>= 0; )
5532 /* Reject eight bit registers, except where the template requires
5533 them. (eg. movzb) */
5534 if (i
.types
[op
].bitfield
.reg8
5535 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5536 || i
.tm
.operand_types
[op
].bitfield
.reg32
5537 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5539 as_bad (_("`%s%s' not allowed with `%s%c'"),
5541 i
.op
[op
].regs
->reg_name
,
5546 /* Warn if the r prefix on a general reg is missing. */
5547 else if ((i
.types
[op
].bitfield
.reg16
5548 || i
.types
[op
].bitfield
.reg32
)
5549 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5550 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5552 /* Prohibit these changes in the 64bit mode, since the
5553 lowering is more complicated. */
5555 && i
.tm
.opcode_modifier
.todword
5556 && !i
.types
[0].bitfield
.regxmm
)
5558 /* Convert to DWORD. We don't want REX byte. */
5559 i
.suffix
= LONG_MNEM_SUFFIX
;
5563 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5564 register_prefix
, i
.op
[op
].regs
->reg_name
,
5573 check_word_reg (void)
5576 for (op
= i
.operands
; --op
>= 0;)
5577 /* Reject eight bit registers, except where the template requires
5578 them. (eg. movzb) */
5579 if (i
.types
[op
].bitfield
.reg8
5580 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5581 || i
.tm
.operand_types
[op
].bitfield
.reg32
5582 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5584 as_bad (_("`%s%s' not allowed with `%s%c'"),
5586 i
.op
[op
].regs
->reg_name
,
5591 /* Warn if the e or r prefix on a general reg is present. */
5592 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5593 && (i
.types
[op
].bitfield
.reg32
5594 || i
.types
[op
].bitfield
.reg64
)
5595 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5596 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5598 /* Prohibit these changes in the 64bit mode, since the
5599 lowering is more complicated. */
5600 if (flag_code
== CODE_64BIT
)
5602 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5603 register_prefix
, i
.op
[op
].regs
->reg_name
,
5607 #if REGISTER_WARNINGS
5608 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5610 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5611 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5618 update_imm (unsigned int j
)
5620 i386_operand_type overlap
= i
.types
[j
];
5621 if ((overlap
.bitfield
.imm8
5622 || overlap
.bitfield
.imm8s
5623 || overlap
.bitfield
.imm16
5624 || overlap
.bitfield
.imm32
5625 || overlap
.bitfield
.imm32s
5626 || overlap
.bitfield
.imm64
)
5627 && !operand_type_equal (&overlap
, &imm8
)
5628 && !operand_type_equal (&overlap
, &imm8s
)
5629 && !operand_type_equal (&overlap
, &imm16
)
5630 && !operand_type_equal (&overlap
, &imm32
)
5631 && !operand_type_equal (&overlap
, &imm32s
)
5632 && !operand_type_equal (&overlap
, &imm64
))
5636 i386_operand_type temp
;
5638 operand_type_set (&temp
, 0);
5639 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5641 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5642 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5644 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5645 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5646 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5648 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5649 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5652 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5655 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5656 || operand_type_equal (&overlap
, &imm16_32
)
5657 || operand_type_equal (&overlap
, &imm16_32s
))
5659 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5664 if (!operand_type_equal (&overlap
, &imm8
)
5665 && !operand_type_equal (&overlap
, &imm8s
)
5666 && !operand_type_equal (&overlap
, &imm16
)
5667 && !operand_type_equal (&overlap
, &imm32
)
5668 && !operand_type_equal (&overlap
, &imm32s
)
5669 && !operand_type_equal (&overlap
, &imm64
))
5671 as_bad (_("no instruction mnemonic suffix given; "
5672 "can't determine immediate size"));
5676 i
.types
[j
] = overlap
;
5686 /* Update the first 2 immediate operands. */
5687 n
= i
.operands
> 2 ? 2 : i
.operands
;
5690 for (j
= 0; j
< n
; j
++)
5691 if (update_imm (j
) == 0)
5694 /* The 3rd operand can't be immediate operand. */
5695 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5702 bad_implicit_operand (int xmm
)
5704 const char *ireg
= xmm
? "xmm0" : "ymm0";
5707 as_bad (_("the last operand of `%s' must be `%s%s'"),
5708 i
.tm
.name
, register_prefix
, ireg
);
5710 as_bad (_("the first operand of `%s' must be `%s%s'"),
5711 i
.tm
.name
, register_prefix
, ireg
);
5716 process_operands (void)
5718 /* Default segment register this instruction will use for memory
5719 accesses. 0 means unknown. This is only for optimizing out
5720 unnecessary segment overrides. */
5721 const seg_entry
*default_seg
= 0;
5723 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5725 unsigned int dupl
= i
.operands
;
5726 unsigned int dest
= dupl
- 1;
5729 /* The destination must be an xmm register. */
5730 gas_assert (i
.reg_operands
5731 && MAX_OPERANDS
> dupl
5732 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5734 if (i
.tm
.opcode_modifier
.firstxmm0
)
5736 /* The first operand is implicit and must be xmm0. */
5737 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5738 if (register_number (i
.op
[0].regs
) != 0)
5739 return bad_implicit_operand (1);
5741 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5743 /* Keep xmm0 for instructions with VEX prefix and 3
5749 /* We remove the first xmm0 and keep the number of
5750 operands unchanged, which in fact duplicates the
5752 for (j
= 1; j
< i
.operands
; j
++)
5754 i
.op
[j
- 1] = i
.op
[j
];
5755 i
.types
[j
- 1] = i
.types
[j
];
5756 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5760 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5762 gas_assert ((MAX_OPERANDS
- 1) > dupl
5763 && (i
.tm
.opcode_modifier
.vexsources
5766 /* Add the implicit xmm0 for instructions with VEX prefix
5768 for (j
= i
.operands
; j
> 0; j
--)
5770 i
.op
[j
] = i
.op
[j
- 1];
5771 i
.types
[j
] = i
.types
[j
- 1];
5772 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5775 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5776 i
.types
[0] = regxmm
;
5777 i
.tm
.operand_types
[0] = regxmm
;
5780 i
.reg_operands
+= 2;
5785 i
.op
[dupl
] = i
.op
[dest
];
5786 i
.types
[dupl
] = i
.types
[dest
];
5787 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5796 i
.op
[dupl
] = i
.op
[dest
];
5797 i
.types
[dupl
] = i
.types
[dest
];
5798 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5801 if (i
.tm
.opcode_modifier
.immext
)
5804 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5808 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5809 gas_assert (i
.reg_operands
5810 && (operand_type_equal (&i
.types
[0], ®xmm
)
5811 || operand_type_equal (&i
.types
[0], ®ymm
)
5812 || operand_type_equal (&i
.types
[0], ®zmm
)));
5813 if (register_number (i
.op
[0].regs
) != 0)
5814 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5816 for (j
= 1; j
< i
.operands
; j
++)
5818 i
.op
[j
- 1] = i
.op
[j
];
5819 i
.types
[j
- 1] = i
.types
[j
];
5821 /* We need to adjust fields in i.tm since they are used by
5822 build_modrm_byte. */
5823 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5830 else if (i
.tm
.opcode_modifier
.regkludge
)
5832 /* The imul $imm, %reg instruction is converted into
5833 imul $imm, %reg, %reg, and the clr %reg instruction
5834 is converted into xor %reg, %reg. */
5836 unsigned int first_reg_op
;
5838 if (operand_type_check (i
.types
[0], reg
))
5842 /* Pretend we saw the extra register operand. */
5843 gas_assert (i
.reg_operands
== 1
5844 && i
.op
[first_reg_op
+ 1].regs
== 0);
5845 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5846 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5851 if (i
.tm
.opcode_modifier
.shortform
)
5853 if (i
.types
[0].bitfield
.sreg2
5854 || i
.types
[0].bitfield
.sreg3
)
5856 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5857 && i
.op
[0].regs
->reg_num
== 1)
5859 as_bad (_("you can't `pop %scs'"), register_prefix
);
5862 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5863 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5868 /* The register or float register operand is in operand
5872 if (i
.types
[0].bitfield
.floatreg
5873 || operand_type_check (i
.types
[0], reg
))
5877 /* Register goes in low 3 bits of opcode. */
5878 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5879 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5881 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5883 /* Warn about some common errors, but press on regardless.
5884 The first case can be generated by gcc (<= 2.8.1). */
5885 if (i
.operands
== 2)
5887 /* Reversed arguments on faddp, fsubp, etc. */
5888 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5889 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5890 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5894 /* Extraneous `l' suffix on fp insn. */
5895 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5896 register_prefix
, i
.op
[0].regs
->reg_name
);
5901 else if (i
.tm
.opcode_modifier
.modrm
)
5903 /* The opcode is completed (modulo i.tm.extension_opcode which
5904 must be put into the modrm byte). Now, we make the modrm and
5905 index base bytes based on all the info we've collected. */
5907 default_seg
= build_modrm_byte ();
5909 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5913 else if (i
.tm
.opcode_modifier
.isstring
)
5915 /* For the string instructions that allow a segment override
5916 on one of their operands, the default segment is ds. */
5920 if (i
.tm
.base_opcode
== 0x8d /* lea */
5923 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5925 /* If a segment was explicitly specified, and the specified segment
5926 is not the default, use an opcode prefix to select it. If we
5927 never figured out what the default segment is, then default_seg
5928 will be zero at this point, and the specified segment prefix will
5930 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5932 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5938 static const seg_entry
*
5939 build_modrm_byte (void)
5941 const seg_entry
*default_seg
= 0;
5942 unsigned int source
, dest
;
5945 /* The first operand of instructions with VEX prefix and 3 sources
5946 must be VEX_Imm4. */
5947 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5950 unsigned int nds
, reg_slot
;
5953 if (i
.tm
.opcode_modifier
.veximmext
5954 && i
.tm
.opcode_modifier
.immext
)
5956 dest
= i
.operands
- 2;
5957 gas_assert (dest
== 3);
5960 dest
= i
.operands
- 1;
5963 /* There are 2 kinds of instructions:
5964 1. 5 operands: 4 register operands or 3 register operands
5965 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5966 VexW0 or VexW1. The destination must be either XMM, YMM or
5968 2. 4 operands: 4 register operands or 3 register operands
5969 plus 1 memory operand, VexXDS, and VexImmExt */
5970 gas_assert ((i
.reg_operands
== 4
5971 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5972 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5973 && (i
.tm
.opcode_modifier
.veximmext
5974 || (i
.imm_operands
== 1
5975 && i
.types
[0].bitfield
.vec_imm4
5976 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5977 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5978 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5979 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
5980 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
5982 if (i
.imm_operands
== 0)
5984 /* When there is no immediate operand, generate an 8bit
5985 immediate operand to encode the first operand. */
5986 exp
= &im_expressions
[i
.imm_operands
++];
5987 i
.op
[i
.operands
].imms
= exp
;
5988 i
.types
[i
.operands
] = imm8
;
5990 /* If VexW1 is set, the first operand is the source and
5991 the second operand is encoded in the immediate operand. */
5992 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6003 /* FMA swaps REG and NDS. */
6004 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6012 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6014 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6016 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6018 exp
->X_op
= O_constant
;
6019 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6020 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6024 unsigned int imm_slot
;
6026 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6028 /* If VexW0 is set, the third operand is the source and
6029 the second operand is encoded in the immediate
6036 /* VexW1 is set, the second operand is the source and
6037 the third operand is encoded in the immediate
6043 if (i
.tm
.opcode_modifier
.immext
)
6045 /* When ImmExt is set, the immdiate byte is the last
6047 imm_slot
= i
.operands
- 1;
6055 /* Turn on Imm8 so that output_imm will generate it. */
6056 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6059 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6061 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6063 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6065 i
.op
[imm_slot
].imms
->X_add_number
6066 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6067 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6070 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6071 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6073 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6075 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6080 /* i.reg_operands MUST be the number of real register operands;
6081 implicit registers do not count. If there are 3 register
6082 operands, it must be a instruction with VexNDS. For a
6083 instruction with VexNDD, the destination register is encoded
6084 in VEX prefix. If there are 4 register operands, it must be
6085 a instruction with VEX prefix and 3 sources. */
6086 if (i
.mem_operands
== 0
6087 && ((i
.reg_operands
== 2
6088 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6089 || (i
.reg_operands
== 3
6090 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6091 || (i
.reg_operands
== 4 && vex_3_sources
)))
6099 /* When there are 3 operands, one of them may be immediate,
6100 which may be the first or the last operand. Otherwise,
6101 the first operand must be shift count register (cl) or it
6102 is an instruction with VexNDS. */
6103 gas_assert (i
.imm_operands
== 1
6104 || (i
.imm_operands
== 0
6105 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6106 || i
.types
[0].bitfield
.shiftcount
)));
6107 if (operand_type_check (i
.types
[0], imm
)
6108 || i
.types
[0].bitfield
.shiftcount
)
6114 /* When there are 4 operands, the first two must be 8bit
6115 immediate operands. The source operand will be the 3rd
6118 For instructions with VexNDS, if the first operand
6119 an imm8, the source operand is the 2nd one. If the last
6120 operand is imm8, the source operand is the first one. */
6121 gas_assert ((i
.imm_operands
== 2
6122 && i
.types
[0].bitfield
.imm8
6123 && i
.types
[1].bitfield
.imm8
)
6124 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6125 && i
.imm_operands
== 1
6126 && (i
.types
[0].bitfield
.imm8
6127 || i
.types
[i
.operands
- 1].bitfield
.imm8
6129 if (i
.imm_operands
== 2)
6133 if (i
.types
[0].bitfield
.imm8
)
6140 if (i
.tm
.opcode_modifier
.evex
)
6142 /* For EVEX instructions, when there are 5 operands, the
6143 first one must be immediate operand. If the second one
6144 is immediate operand, the source operand is the 3th
6145 one. If the last one is immediate operand, the source
6146 operand is the 2nd one. */
6147 gas_assert (i
.imm_operands
== 2
6148 && i
.tm
.opcode_modifier
.sae
6149 && operand_type_check (i
.types
[0], imm
));
6150 if (operand_type_check (i
.types
[1], imm
))
6152 else if (operand_type_check (i
.types
[4], imm
))
6166 /* RC/SAE operand could be between DEST and SRC. That happens
6167 when one operand is GPR and the other one is XMM/YMM/ZMM
6169 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6172 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6174 /* For instructions with VexNDS, the register-only source
6175 operand must be 32/64bit integer, XMM, YMM or ZMM
6176 register. It is encoded in VEX prefix. We need to
6177 clear RegMem bit before calling operand_type_equal. */
6179 i386_operand_type op
;
6182 /* Check register-only source operand when two source
6183 operands are swapped. */
6184 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6185 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6193 op
= i
.tm
.operand_types
[vvvv
];
6194 op
.bitfield
.regmem
= 0;
6195 if ((dest
+ 1) >= i
.operands
6196 || (!op
.bitfield
.reg32
6197 && op
.bitfield
.reg64
6198 && !operand_type_equal (&op
, ®xmm
)
6199 && !operand_type_equal (&op
, ®ymm
)
6200 && !operand_type_equal (&op
, ®zmm
)
6201 && !operand_type_equal (&op
, ®mask
)))
6203 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6209 /* One of the register operands will be encoded in the i.tm.reg
6210 field, the other in the combined i.tm.mode and i.tm.regmem
6211 fields. If no form of this instruction supports a memory
6212 destination operand, then we assume the source operand may
6213 sometimes be a memory operand and so we need to store the
6214 destination in the i.rm.reg field. */
6215 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6216 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6218 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6219 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6220 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6222 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6224 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6226 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6231 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6232 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6233 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6235 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6237 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6239 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6242 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6244 if (!i
.types
[0].bitfield
.control
6245 && !i
.types
[1].bitfield
.control
)
6247 i
.rex
&= ~(REX_R
| REX_B
);
6248 add_prefix (LOCK_PREFIX_OPCODE
);
6252 { /* If it's not 2 reg operands... */
6257 unsigned int fake_zero_displacement
= 0;
6260 for (op
= 0; op
< i
.operands
; op
++)
6261 if (operand_type_check (i
.types
[op
], anymem
))
6263 gas_assert (op
< i
.operands
);
6265 if (i
.tm
.opcode_modifier
.vecsib
)
6267 if (i
.index_reg
->reg_num
== RegEiz
6268 || i
.index_reg
->reg_num
== RegRiz
)
6271 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6274 i
.sib
.base
= NO_BASE_REGISTER
;
6275 i
.sib
.scale
= i
.log2_scale_factor
;
6276 /* No Vec_Disp8 if there is no base. */
6277 i
.types
[op
].bitfield
.vec_disp8
= 0;
6278 i
.types
[op
].bitfield
.disp8
= 0;
6279 i
.types
[op
].bitfield
.disp16
= 0;
6280 i
.types
[op
].bitfield
.disp64
= 0;
6281 if (flag_code
!= CODE_64BIT
)
6283 /* Must be 32 bit */
6284 i
.types
[op
].bitfield
.disp32
= 1;
6285 i
.types
[op
].bitfield
.disp32s
= 0;
6289 i
.types
[op
].bitfield
.disp32
= 0;
6290 i
.types
[op
].bitfield
.disp32s
= 1;
6293 i
.sib
.index
= i
.index_reg
->reg_num
;
6294 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6296 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6302 if (i
.base_reg
== 0)
6305 if (!i
.disp_operands
)
6307 fake_zero_displacement
= 1;
6308 /* Instructions with VSIB byte need 32bit displacement
6309 if there is no base register. */
6310 if (i
.tm
.opcode_modifier
.vecsib
)
6311 i
.types
[op
].bitfield
.disp32
= 1;
6313 if (i
.index_reg
== 0)
6315 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6316 /* Operand is just <disp> */
6317 if (flag_code
== CODE_64BIT
)
6319 /* 64bit mode overwrites the 32bit absolute
6320 addressing by RIP relative addressing and
6321 absolute addressing is encoded by one of the
6322 redundant SIB forms. */
6323 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6324 i
.sib
.base
= NO_BASE_REGISTER
;
6325 i
.sib
.index
= NO_INDEX_REGISTER
;
6326 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6327 ? disp32s
: disp32
);
6329 else if ((flag_code
== CODE_16BIT
)
6330 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6332 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6333 i
.types
[op
] = disp16
;
6337 i
.rm
.regmem
= NO_BASE_REGISTER
;
6338 i
.types
[op
] = disp32
;
6341 else if (!i
.tm
.opcode_modifier
.vecsib
)
6343 /* !i.base_reg && i.index_reg */
6344 if (i
.index_reg
->reg_num
== RegEiz
6345 || i
.index_reg
->reg_num
== RegRiz
)
6346 i
.sib
.index
= NO_INDEX_REGISTER
;
6348 i
.sib
.index
= i
.index_reg
->reg_num
;
6349 i
.sib
.base
= NO_BASE_REGISTER
;
6350 i
.sib
.scale
= i
.log2_scale_factor
;
6351 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6352 /* No Vec_Disp8 if there is no base. */
6353 i
.types
[op
].bitfield
.vec_disp8
= 0;
6354 i
.types
[op
].bitfield
.disp8
= 0;
6355 i
.types
[op
].bitfield
.disp16
= 0;
6356 i
.types
[op
].bitfield
.disp64
= 0;
6357 if (flag_code
!= CODE_64BIT
)
6359 /* Must be 32 bit */
6360 i
.types
[op
].bitfield
.disp32
= 1;
6361 i
.types
[op
].bitfield
.disp32s
= 0;
6365 i
.types
[op
].bitfield
.disp32
= 0;
6366 i
.types
[op
].bitfield
.disp32s
= 1;
6368 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6372 /* RIP addressing for 64bit mode. */
6373 else if (i
.base_reg
->reg_num
== RegRip
||
6374 i
.base_reg
->reg_num
== RegEip
)
6376 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6377 i
.rm
.regmem
= NO_BASE_REGISTER
;
6378 i
.types
[op
].bitfield
.disp8
= 0;
6379 i
.types
[op
].bitfield
.disp16
= 0;
6380 i
.types
[op
].bitfield
.disp32
= 0;
6381 i
.types
[op
].bitfield
.disp32s
= 1;
6382 i
.types
[op
].bitfield
.disp64
= 0;
6383 i
.types
[op
].bitfield
.vec_disp8
= 0;
6384 i
.flags
[op
] |= Operand_PCrel
;
6385 if (! i
.disp_operands
)
6386 fake_zero_displacement
= 1;
6388 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6390 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6391 switch (i
.base_reg
->reg_num
)
6394 if (i
.index_reg
== 0)
6396 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6397 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6401 if (i
.index_reg
== 0)
6404 if (operand_type_check (i
.types
[op
], disp
) == 0)
6406 /* fake (%bp) into 0(%bp) */
6407 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6408 i
.types
[op
].bitfield
.vec_disp8
= 1;
6410 i
.types
[op
].bitfield
.disp8
= 1;
6411 fake_zero_displacement
= 1;
6414 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6415 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6417 default: /* (%si) -> 4 or (%di) -> 5 */
6418 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6420 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6422 else /* i.base_reg and 32/64 bit mode */
6424 if (flag_code
== CODE_64BIT
6425 && operand_type_check (i
.types
[op
], disp
))
6427 i386_operand_type temp
;
6428 operand_type_set (&temp
, 0);
6429 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6430 temp
.bitfield
.vec_disp8
6431 = i
.types
[op
].bitfield
.vec_disp8
;
6433 if (i
.prefix
[ADDR_PREFIX
] == 0)
6434 i
.types
[op
].bitfield
.disp32s
= 1;
6436 i
.types
[op
].bitfield
.disp32
= 1;
6439 if (!i
.tm
.opcode_modifier
.vecsib
)
6440 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6441 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6443 i
.sib
.base
= i
.base_reg
->reg_num
;
6444 /* x86-64 ignores REX prefix bit here to avoid decoder
6446 if (!(i
.base_reg
->reg_flags
& RegRex
)
6447 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6448 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6450 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6452 fake_zero_displacement
= 1;
6453 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6454 i
.types
[op
].bitfield
.vec_disp8
= 1;
6456 i
.types
[op
].bitfield
.disp8
= 1;
6458 i
.sib
.scale
= i
.log2_scale_factor
;
6459 if (i
.index_reg
== 0)
6461 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6462 /* <disp>(%esp) becomes two byte modrm with no index
6463 register. We've already stored the code for esp
6464 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6465 Any base register besides %esp will not use the
6466 extra modrm byte. */
6467 i
.sib
.index
= NO_INDEX_REGISTER
;
6469 else if (!i
.tm
.opcode_modifier
.vecsib
)
6471 if (i
.index_reg
->reg_num
== RegEiz
6472 || i
.index_reg
->reg_num
== RegRiz
)
6473 i
.sib
.index
= NO_INDEX_REGISTER
;
6475 i
.sib
.index
= i
.index_reg
->reg_num
;
6476 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6477 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6482 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6483 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6487 if (!fake_zero_displacement
6491 fake_zero_displacement
= 1;
6492 if (i
.disp_encoding
== disp_encoding_8bit
)
6493 i
.types
[op
].bitfield
.disp8
= 1;
6495 i
.types
[op
].bitfield
.disp32
= 1;
6497 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6501 if (fake_zero_displacement
)
6503 /* Fakes a zero displacement assuming that i.types[op]
6504 holds the correct displacement size. */
6507 gas_assert (i
.op
[op
].disps
== 0);
6508 exp
= &disp_expressions
[i
.disp_operands
++];
6509 i
.op
[op
].disps
= exp
;
6510 exp
->X_op
= O_constant
;
6511 exp
->X_add_number
= 0;
6512 exp
->X_add_symbol
= (symbolS
*) 0;
6513 exp
->X_op_symbol
= (symbolS
*) 0;
6521 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6523 if (operand_type_check (i
.types
[0], imm
))
6524 i
.vex
.register_specifier
= NULL
;
6527 /* VEX.vvvv encodes one of the sources when the first
6528 operand is not an immediate. */
6529 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6530 i
.vex
.register_specifier
= i
.op
[0].regs
;
6532 i
.vex
.register_specifier
= i
.op
[1].regs
;
6535 /* Destination is a XMM register encoded in the ModRM.reg
6537 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6538 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6541 /* ModRM.rm and VEX.B encodes the other source. */
6542 if (!i
.mem_operands
)
6546 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6547 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6549 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6551 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6555 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6557 i
.vex
.register_specifier
= i
.op
[2].regs
;
6558 if (!i
.mem_operands
)
6561 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6562 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6566 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6567 (if any) based on i.tm.extension_opcode. Again, we must be
6568 careful to make sure that segment/control/debug/test/MMX
6569 registers are coded into the i.rm.reg field. */
6570 else if (i
.reg_operands
)
6573 unsigned int vex_reg
= ~0;
6575 for (op
= 0; op
< i
.operands
; op
++)
6576 if (i
.types
[op
].bitfield
.reg8
6577 || i
.types
[op
].bitfield
.reg16
6578 || i
.types
[op
].bitfield
.reg32
6579 || i
.types
[op
].bitfield
.reg64
6580 || i
.types
[op
].bitfield
.regmmx
6581 || i
.types
[op
].bitfield
.regxmm
6582 || i
.types
[op
].bitfield
.regymm
6583 || i
.types
[op
].bitfield
.regbnd
6584 || i
.types
[op
].bitfield
.regzmm
6585 || i
.types
[op
].bitfield
.regmask
6586 || i
.types
[op
].bitfield
.sreg2
6587 || i
.types
[op
].bitfield
.sreg3
6588 || i
.types
[op
].bitfield
.control
6589 || i
.types
[op
].bitfield
.debug
6590 || i
.types
[op
].bitfield
.test
)
6595 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6597 /* For instructions with VexNDS, the register-only
6598 source operand is encoded in VEX prefix. */
6599 gas_assert (mem
!= (unsigned int) ~0);
6604 gas_assert (op
< i
.operands
);
6608 /* Check register-only source operand when two source
6609 operands are swapped. */
6610 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6611 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6615 gas_assert (mem
== (vex_reg
+ 1)
6616 && op
< i
.operands
);
6621 gas_assert (vex_reg
< i
.operands
);
6625 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6627 /* For instructions with VexNDD, the register destination
6628 is encoded in VEX prefix. */
6629 if (i
.mem_operands
== 0)
6631 /* There is no memory operand. */
6632 gas_assert ((op
+ 2) == i
.operands
);
6637 /* There are only 2 operands. */
6638 gas_assert (op
< 2 && i
.operands
== 2);
6643 gas_assert (op
< i
.operands
);
6645 if (vex_reg
!= (unsigned int) ~0)
6647 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6649 if (type
->bitfield
.reg32
!= 1
6650 && type
->bitfield
.reg64
!= 1
6651 && !operand_type_equal (type
, ®xmm
)
6652 && !operand_type_equal (type
, ®ymm
)
6653 && !operand_type_equal (type
, ®zmm
)
6654 && !operand_type_equal (type
, ®mask
))
6657 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6660 /* Don't set OP operand twice. */
6663 /* If there is an extension opcode to put here, the
6664 register number must be put into the regmem field. */
6665 if (i
.tm
.extension_opcode
!= None
)
6667 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6668 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6670 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6675 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6676 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6678 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6683 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6684 must set it to 3 to indicate this is a register operand
6685 in the regmem field. */
6686 if (!i
.mem_operands
)
6690 /* Fill in i.rm.reg field with extension opcode (if any). */
6691 if (i
.tm
.extension_opcode
!= None
)
6692 i
.rm
.reg
= i
.tm
.extension_opcode
;
6698 output_branch (void)
6704 relax_substateT subtype
;
6708 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6709 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6712 if (i
.prefix
[DATA_PREFIX
] != 0)
6718 /* Pentium4 branch hints. */
6719 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6720 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6725 if (i
.prefix
[REX_PREFIX
] != 0)
6731 /* BND prefixed jump. */
6732 if (i
.prefix
[BND_PREFIX
] != 0)
6734 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6738 if (i
.prefixes
!= 0 && !intel_syntax
)
6739 as_warn (_("skipping prefixes on this instruction"));
6741 /* It's always a symbol; End frag & setup for relax.
6742 Make sure there is enough room in this frag for the largest
6743 instruction we may generate in md_convert_frag. This is 2
6744 bytes for the opcode and room for the prefix and largest
6746 frag_grow (prefix
+ 2 + 4);
6747 /* Prefix and 1 opcode byte go in fr_fix. */
6748 p
= frag_more (prefix
+ 1);
6749 if (i
.prefix
[DATA_PREFIX
] != 0)
6750 *p
++ = DATA_PREFIX_OPCODE
;
6751 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6752 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6753 *p
++ = i
.prefix
[SEG_PREFIX
];
6754 if (i
.prefix
[REX_PREFIX
] != 0)
6755 *p
++ = i
.prefix
[REX_PREFIX
];
6756 *p
= i
.tm
.base_opcode
;
6758 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6759 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6760 else if (cpu_arch_flags
.bitfield
.cpui386
)
6761 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6763 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6766 sym
= i
.op
[0].disps
->X_add_symbol
;
6767 off
= i
.op
[0].disps
->X_add_number
;
6769 if (i
.op
[0].disps
->X_op
!= O_constant
6770 && i
.op
[0].disps
->X_op
!= O_symbol
)
6772 /* Handle complex expressions. */
6773 sym
= make_expr_symbol (i
.op
[0].disps
);
6777 /* 1 possible extra opcode + 4 byte displacement go in var part.
6778 Pass reloc in fr_var. */
6779 frag_var (rs_machine_dependent
, 5,
6781 || i
.reloc
[0] != NO_RELOC
6782 || (i
.bnd_prefix
== NULL
&& !add_bnd_prefix
))
6784 : BFD_RELOC_X86_64_PC32_BND
),
6785 subtype
, sym
, off
, p
);
6795 if (i
.tm
.opcode_modifier
.jumpbyte
)
6797 /* This is a loop or jecxz type instruction. */
6799 if (i
.prefix
[ADDR_PREFIX
] != 0)
6801 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6804 /* Pentium4 branch hints. */
6805 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6806 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6808 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6817 if (flag_code
== CODE_16BIT
)
6820 if (i
.prefix
[DATA_PREFIX
] != 0)
6822 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6832 if (i
.prefix
[REX_PREFIX
] != 0)
6834 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6838 /* BND prefixed jump. */
6839 if (i
.prefix
[BND_PREFIX
] != 0)
6841 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6845 if (i
.prefixes
!= 0 && !intel_syntax
)
6846 as_warn (_("skipping prefixes on this instruction"));
6848 p
= frag_more (i
.tm
.opcode_length
+ size
);
6849 switch (i
.tm
.opcode_length
)
6852 *p
++ = i
.tm
.base_opcode
>> 8;
6854 *p
++ = i
.tm
.base_opcode
;
6860 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6861 i
.op
[0].disps
, 1, reloc (size
, 1, 1,
6862 (i
.bnd_prefix
!= NULL
6866 /* All jumps handled here are signed, but don't use a signed limit
6867 check for 32 and 16 bit jumps as we want to allow wrap around at
6868 4G and 64k respectively. */
6870 fixP
->fx_signed
= 1;
6874 output_interseg_jump (void)
6882 if (flag_code
== CODE_16BIT
)
6886 if (i
.prefix
[DATA_PREFIX
] != 0)
6892 if (i
.prefix
[REX_PREFIX
] != 0)
6902 if (i
.prefixes
!= 0 && !intel_syntax
)
6903 as_warn (_("skipping prefixes on this instruction"));
6905 /* 1 opcode; 2 segment; offset */
6906 p
= frag_more (prefix
+ 1 + 2 + size
);
6908 if (i
.prefix
[DATA_PREFIX
] != 0)
6909 *p
++ = DATA_PREFIX_OPCODE
;
6911 if (i
.prefix
[REX_PREFIX
] != 0)
6912 *p
++ = i
.prefix
[REX_PREFIX
];
6914 *p
++ = i
.tm
.base_opcode
;
6915 if (i
.op
[1].imms
->X_op
== O_constant
)
6917 offsetT n
= i
.op
[1].imms
->X_add_number
;
6920 && !fits_in_unsigned_word (n
)
6921 && !fits_in_signed_word (n
))
6923 as_bad (_("16-bit jump out of range"));
6926 md_number_to_chars (p
, n
, size
);
6929 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6930 i
.op
[1].imms
, 0, reloc (size
, 0, 0, 0, i
.reloc
[1]));
6931 if (i
.op
[0].imms
->X_op
!= O_constant
)
6932 as_bad (_("can't handle non absolute segment in `%s'"),
6934 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
6940 fragS
*insn_start_frag
;
6941 offsetT insn_start_off
;
6943 /* Tie dwarf2 debug info to the address at the start of the insn.
6944 We can't do this after the insn has been output as the current
6945 frag may have been closed off. eg. by frag_var. */
6946 dwarf2_emit_insn (0);
6948 insn_start_frag
= frag_now
;
6949 insn_start_off
= frag_now_fix ();
6952 if (i
.tm
.opcode_modifier
.jump
)
6954 else if (i
.tm
.opcode_modifier
.jumpbyte
6955 || i
.tm
.opcode_modifier
.jumpdword
)
6957 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6958 output_interseg_jump ();
6961 /* Output normal instructions here. */
6965 unsigned int prefix
;
6967 /* Some processors fail on LOCK prefix. This options makes
6968 assembler ignore LOCK prefix and serves as a workaround. */
6969 if (omit_lock_prefix
)
6971 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
6973 i
.prefix
[LOCK_PREFIX
] = 0;
6976 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6977 don't need the explicit prefix. */
6978 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
6980 switch (i
.tm
.opcode_length
)
6983 if (i
.tm
.base_opcode
& 0xff000000)
6985 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6990 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6992 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6993 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6996 if (prefix
!= REPE_PREFIX_OPCODE
6997 || (i
.prefix
[REP_PREFIX
]
6998 != REPE_PREFIX_OPCODE
))
6999 add_prefix (prefix
);
7002 add_prefix (prefix
);
7011 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7012 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7013 R_X86_64_GOTTPOFF relocation so that linker can safely
7014 perform IE->LE optimization. */
7015 if (x86_elf_abi
== X86_64_X32_ABI
7017 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7018 && i
.prefix
[REX_PREFIX
] == 0)
7019 add_prefix (REX_OPCODE
);
7022 /* The prefix bytes. */
7023 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7025 FRAG_APPEND_1_CHAR (*q
);
7029 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7034 /* REX byte is encoded in VEX prefix. */
7038 FRAG_APPEND_1_CHAR (*q
);
7041 /* There should be no other prefixes for instructions
7046 /* For EVEX instructions i.vrex should become 0 after
7047 build_evex_prefix. For VEX instructions upper 16 registers
7048 aren't available, so VREX should be 0. */
7051 /* Now the VEX prefix. */
7052 p
= frag_more (i
.vex
.length
);
7053 for (j
= 0; j
< i
.vex
.length
; j
++)
7054 p
[j
] = i
.vex
.bytes
[j
];
7057 /* Now the opcode; be careful about word order here! */
7058 if (i
.tm
.opcode_length
== 1)
7060 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7064 switch (i
.tm
.opcode_length
)
7068 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7069 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7073 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7083 /* Put out high byte first: can't use md_number_to_chars! */
7084 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7085 *p
= i
.tm
.base_opcode
& 0xff;
7088 /* Now the modrm byte and sib byte (if present). */
7089 if (i
.tm
.opcode_modifier
.modrm
)
7091 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7094 /* If i.rm.regmem == ESP (4)
7095 && i.rm.mode != (Register mode)
7097 ==> need second modrm byte. */
7098 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7100 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7101 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7103 | i
.sib
.scale
<< 6));
7106 if (i
.disp_operands
)
7107 output_disp (insn_start_frag
, insn_start_off
);
7110 output_imm (insn_start_frag
, insn_start_off
);
7116 pi ("" /*line*/, &i
);
7118 #endif /* DEBUG386 */
7121 /* Return the size of the displacement operand N. */
7124 disp_size (unsigned int n
)
7128 /* Vec_Disp8 has to be 8bit. */
7129 if (i
.types
[n
].bitfield
.vec_disp8
)
7131 else if (i
.types
[n
].bitfield
.disp64
)
7133 else if (i
.types
[n
].bitfield
.disp8
)
7135 else if (i
.types
[n
].bitfield
.disp16
)
7140 /* Return the size of the immediate operand N. */
7143 imm_size (unsigned int n
)
7146 if (i
.types
[n
].bitfield
.imm64
)
7148 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7150 else if (i
.types
[n
].bitfield
.imm16
)
7156 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7161 for (n
= 0; n
< i
.operands
; n
++)
7163 if (i
.types
[n
].bitfield
.vec_disp8
7164 || operand_type_check (i
.types
[n
], disp
))
7166 if (i
.op
[n
].disps
->X_op
== O_constant
)
7168 int size
= disp_size (n
);
7169 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7171 if (i
.types
[n
].bitfield
.vec_disp8
)
7173 val
= offset_in_range (val
, size
);
7174 p
= frag_more (size
);
7175 md_number_to_chars (p
, val
, size
);
7179 enum bfd_reloc_code_real reloc_type
;
7180 int size
= disp_size (n
);
7181 int sign
= i
.types
[n
].bitfield
.disp32s
;
7182 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7184 /* We can't have 8 bit displacement here. */
7185 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7187 /* The PC relative address is computed relative
7188 to the instruction boundary, so in case immediate
7189 fields follows, we need to adjust the value. */
7190 if (pcrel
&& i
.imm_operands
)
7195 for (n1
= 0; n1
< i
.operands
; n1
++)
7196 if (operand_type_check (i
.types
[n1
], imm
))
7198 /* Only one immediate is allowed for PC
7199 relative address. */
7200 gas_assert (sz
== 0);
7202 i
.op
[n
].disps
->X_add_number
-= sz
;
7204 /* We should find the immediate. */
7205 gas_assert (sz
!= 0);
7208 p
= frag_more (size
);
7209 reloc_type
= reloc (size
, pcrel
, sign
,
7210 (i
.bnd_prefix
!= NULL
7214 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7215 && (((reloc_type
== BFD_RELOC_32
7216 || reloc_type
== BFD_RELOC_X86_64_32S
7217 || (reloc_type
== BFD_RELOC_64
7219 && (i
.op
[n
].disps
->X_op
== O_symbol
7220 || (i
.op
[n
].disps
->X_op
== O_add
7221 && ((symbol_get_value_expression
7222 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7224 || reloc_type
== BFD_RELOC_32_PCREL
))
7228 if (insn_start_frag
== frag_now
)
7229 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7234 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7235 for (fr
= insn_start_frag
->fr_next
;
7236 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7238 add
+= p
- frag_now
->fr_literal
;
7243 reloc_type
= BFD_RELOC_386_GOTPC
;
7244 i
.op
[n
].imms
->X_add_number
+= add
;
7246 else if (reloc_type
== BFD_RELOC_64
)
7247 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7249 /* Don't do the adjustment for x86-64, as there
7250 the pcrel addressing is relative to the _next_
7251 insn, and that is taken care of in other code. */
7252 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7254 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7255 i
.op
[n
].disps
, pcrel
, reloc_type
);
7262 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7267 for (n
= 0; n
< i
.operands
; n
++)
7269 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7270 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7273 if (operand_type_check (i
.types
[n
], imm
))
7275 if (i
.op
[n
].imms
->X_op
== O_constant
)
7277 int size
= imm_size (n
);
7280 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7282 p
= frag_more (size
);
7283 md_number_to_chars (p
, val
, size
);
7287 /* Not absolute_section.
7288 Need a 32-bit fixup (don't support 8bit
7289 non-absolute imms). Try to support other
7291 enum bfd_reloc_code_real reloc_type
;
7292 int size
= imm_size (n
);
7295 if (i
.types
[n
].bitfield
.imm32s
7296 && (i
.suffix
== QWORD_MNEM_SUFFIX
7297 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7302 p
= frag_more (size
);
7303 reloc_type
= reloc (size
, 0, sign
, 0, i
.reloc
[n
]);
7305 /* This is tough to explain. We end up with this one if we
7306 * have operands that look like
7307 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7308 * obtain the absolute address of the GOT, and it is strongly
7309 * preferable from a performance point of view to avoid using
7310 * a runtime relocation for this. The actual sequence of
7311 * instructions often look something like:
7316 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7318 * The call and pop essentially return the absolute address
7319 * of the label .L66 and store it in %ebx. The linker itself
7320 * will ultimately change the first operand of the addl so
7321 * that %ebx points to the GOT, but to keep things simple, the
7322 * .o file must have this operand set so that it generates not
7323 * the absolute address of .L66, but the absolute address of
7324 * itself. This allows the linker itself simply treat a GOTPC
7325 * relocation as asking for a pcrel offset to the GOT to be
7326 * added in, and the addend of the relocation is stored in the
7327 * operand field for the instruction itself.
7329 * Our job here is to fix the operand so that it would add
7330 * the correct offset so that %ebx would point to itself. The
7331 * thing that is tricky is that .-.L66 will point to the
7332 * beginning of the instruction, so we need to further modify
7333 * the operand so that it will point to itself. There are
7334 * other cases where you have something like:
7336 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7338 * and here no correction would be required. Internally in
7339 * the assembler we treat operands of this form as not being
7340 * pcrel since the '.' is explicitly mentioned, and I wonder
7341 * whether it would simplify matters to do it this way. Who
7342 * knows. In earlier versions of the PIC patches, the
7343 * pcrel_adjust field was used to store the correction, but
7344 * since the expression is not pcrel, I felt it would be
7345 * confusing to do it this way. */
7347 if ((reloc_type
== BFD_RELOC_32
7348 || reloc_type
== BFD_RELOC_X86_64_32S
7349 || reloc_type
== BFD_RELOC_64
)
7351 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7352 && (i
.op
[n
].imms
->X_op
== O_symbol
7353 || (i
.op
[n
].imms
->X_op
== O_add
7354 && ((symbol_get_value_expression
7355 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7360 if (insn_start_frag
== frag_now
)
7361 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7366 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7367 for (fr
= insn_start_frag
->fr_next
;
7368 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7370 add
+= p
- frag_now
->fr_literal
;
7374 reloc_type
= BFD_RELOC_386_GOTPC
;
7376 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7378 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7379 i
.op
[n
].imms
->X_add_number
+= add
;
7381 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7382 i
.op
[n
].imms
, 0, reloc_type
);
7388 /* x86_cons_fix_new is called via the expression parsing code when a
7389 reloc is needed. We use this hook to get the correct .got reloc. */
7390 static int cons_sign
= -1;
7393 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7394 expressionS
*exp
, bfd_reloc_code_real_type r
)
7396 r
= reloc (len
, 0, cons_sign
, 0, r
);
7399 if (exp
->X_op
== O_secrel
)
7401 exp
->X_op
= O_symbol
;
7402 r
= BFD_RELOC_32_SECREL
;
7406 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7409 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7410 purpose of the `.dc.a' internal pseudo-op. */
7413 x86_address_bytes (void)
7415 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7417 return stdoutput
->arch_info
->bits_per_address
/ 8;
7420 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7422 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7424 /* Parse operands of the form
7425 <symbol>@GOTOFF+<nnn>
7426 and similar .plt or .got references.
7428 If we find one, set up the correct relocation in RELOC and copy the
7429 input string, minus the `@GOTOFF' into a malloc'd buffer for
7430 parsing by the calling routine. Return this buffer, and if ADJUST
7431 is non-null set it to the length of the string we removed from the
7432 input line. Otherwise return NULL. */
7434 lex_got (enum bfd_reloc_code_real
*rel
,
7436 i386_operand_type
*types
,
7439 /* Some of the relocations depend on the size of what field is to
7440 be relocated. But in our callers i386_immediate and i386_displacement
7441 we don't yet know the operand size (this will be set by insn
7442 matching). Hence we record the word32 relocation here,
7443 and adjust the reloc according to the real size in reloc(). */
7444 static const struct {
7447 const enum bfd_reloc_code_real rel
[2];
7448 const i386_operand_type types64
;
7450 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7451 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7453 OPERAND_TYPE_IMM32_64
},
7455 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7456 BFD_RELOC_X86_64_PLTOFF64
},
7457 OPERAND_TYPE_IMM64
},
7458 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7459 BFD_RELOC_X86_64_PLT32
},
7460 OPERAND_TYPE_IMM32_32S_DISP32
},
7461 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7462 BFD_RELOC_X86_64_GOTPLT64
},
7463 OPERAND_TYPE_IMM64_DISP64
},
7464 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7465 BFD_RELOC_X86_64_GOTOFF64
},
7466 OPERAND_TYPE_IMM64_DISP64
},
7467 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7468 BFD_RELOC_X86_64_GOTPCREL
},
7469 OPERAND_TYPE_IMM32_32S_DISP32
},
7470 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7471 BFD_RELOC_X86_64_TLSGD
},
7472 OPERAND_TYPE_IMM32_32S_DISP32
},
7473 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7474 _dummy_first_bfd_reloc_code_real
},
7475 OPERAND_TYPE_NONE
},
7476 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7477 BFD_RELOC_X86_64_TLSLD
},
7478 OPERAND_TYPE_IMM32_32S_DISP32
},
7479 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7480 BFD_RELOC_X86_64_GOTTPOFF
},
7481 OPERAND_TYPE_IMM32_32S_DISP32
},
7482 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7483 BFD_RELOC_X86_64_TPOFF32
},
7484 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7485 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7486 _dummy_first_bfd_reloc_code_real
},
7487 OPERAND_TYPE_NONE
},
7488 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7489 BFD_RELOC_X86_64_DTPOFF32
},
7490 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7491 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7492 _dummy_first_bfd_reloc_code_real
},
7493 OPERAND_TYPE_NONE
},
7494 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7495 _dummy_first_bfd_reloc_code_real
},
7496 OPERAND_TYPE_NONE
},
7497 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7498 BFD_RELOC_X86_64_GOT32
},
7499 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7500 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7501 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7502 OPERAND_TYPE_IMM32_32S_DISP32
},
7503 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7504 BFD_RELOC_X86_64_TLSDESC_CALL
},
7505 OPERAND_TYPE_IMM32_32S_DISP32
},
7510 #if defined (OBJ_MAYBE_ELF)
7515 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7516 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7519 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7521 int len
= gotrel
[j
].len
;
7522 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7524 if (gotrel
[j
].rel
[object_64bit
] != 0)
7527 char *tmpbuf
, *past_reloc
;
7529 *rel
= gotrel
[j
].rel
[object_64bit
];
7533 if (flag_code
!= CODE_64BIT
)
7535 types
->bitfield
.imm32
= 1;
7536 types
->bitfield
.disp32
= 1;
7539 *types
= gotrel
[j
].types64
;
7542 if (j
!= 0 && GOT_symbol
== NULL
)
7543 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7545 /* The length of the first part of our input line. */
7546 first
= cp
- input_line_pointer
;
7548 /* The second part goes from after the reloc token until
7549 (and including) an end_of_line char or comma. */
7550 past_reloc
= cp
+ 1 + len
;
7552 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7554 second
= cp
+ 1 - past_reloc
;
7556 /* Allocate and copy string. The trailing NUL shouldn't
7557 be necessary, but be safe. */
7558 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7559 memcpy (tmpbuf
, input_line_pointer
, first
);
7560 if (second
!= 0 && *past_reloc
!= ' ')
7561 /* Replace the relocation token with ' ', so that
7562 errors like foo@GOTOFF1 will be detected. */
7563 tmpbuf
[first
++] = ' ';
7565 /* Increment length by 1 if the relocation token is
7570 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7571 tmpbuf
[first
+ second
] = '\0';
7572 if (bnd_prefix
&& *rel
== BFD_RELOC_X86_64_PLT32
)
7573 *rel
= BFD_RELOC_X86_64_PLT32_BND
;
7577 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7578 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7583 /* Might be a symbol version string. Don't as_bad here. */
7592 /* Parse operands of the form
7593 <symbol>@SECREL32+<nnn>
7595 If we find one, set up the correct relocation in RELOC and copy the
7596 input string, minus the `@SECREL32' into a malloc'd buffer for
7597 parsing by the calling routine. Return this buffer, and if ADJUST
7598 is non-null set it to the length of the string we removed from the
7599 input line. Otherwise return NULL.
7601 This function is copied from the ELF version above adjusted for PE targets. */
7604 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7605 int *adjust ATTRIBUTE_UNUSED
,
7606 i386_operand_type
*types
,
7607 int bnd_prefix ATTRIBUTE_UNUSED
)
7613 const enum bfd_reloc_code_real rel
[2];
7614 const i386_operand_type types64
;
7618 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7619 BFD_RELOC_32_SECREL
},
7620 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7626 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7627 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7630 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7632 int len
= gotrel
[j
].len
;
7634 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7636 if (gotrel
[j
].rel
[object_64bit
] != 0)
7639 char *tmpbuf
, *past_reloc
;
7641 *rel
= gotrel
[j
].rel
[object_64bit
];
7647 if (flag_code
!= CODE_64BIT
)
7649 types
->bitfield
.imm32
= 1;
7650 types
->bitfield
.disp32
= 1;
7653 *types
= gotrel
[j
].types64
;
7656 /* The length of the first part of our input line. */
7657 first
= cp
- input_line_pointer
;
7659 /* The second part goes from after the reloc token until
7660 (and including) an end_of_line char or comma. */
7661 past_reloc
= cp
+ 1 + len
;
7663 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7665 second
= cp
+ 1 - past_reloc
;
7667 /* Allocate and copy string. The trailing NUL shouldn't
7668 be necessary, but be safe. */
7669 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
7670 memcpy (tmpbuf
, input_line_pointer
, first
);
7671 if (second
!= 0 && *past_reloc
!= ' ')
7672 /* Replace the relocation token with ' ', so that
7673 errors like foo@SECLREL321 will be detected. */
7674 tmpbuf
[first
++] = ' ';
7675 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7676 tmpbuf
[first
+ second
] = '\0';
7680 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7681 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7686 /* Might be a symbol version string. Don't as_bad here. */
7692 bfd_reloc_code_real_type
7693 x86_cons (expressionS
*exp
, int size
)
7695 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7697 intel_syntax
= -intel_syntax
;
7700 if (size
== 4 || (object_64bit
&& size
== 8))
7702 /* Handle @GOTOFF and the like in an expression. */
7704 char *gotfree_input_line
;
7707 save
= input_line_pointer
;
7708 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
, 0);
7709 if (gotfree_input_line
)
7710 input_line_pointer
= gotfree_input_line
;
7714 if (gotfree_input_line
)
7716 /* expression () has merrily parsed up to the end of line,
7717 or a comma - in the wrong buffer. Transfer how far
7718 input_line_pointer has moved to the right buffer. */
7719 input_line_pointer
= (save
7720 + (input_line_pointer
- gotfree_input_line
)
7722 free (gotfree_input_line
);
7723 if (exp
->X_op
== O_constant
7724 || exp
->X_op
== O_absent
7725 || exp
->X_op
== O_illegal
7726 || exp
->X_op
== O_register
7727 || exp
->X_op
== O_big
)
7729 char c
= *input_line_pointer
;
7730 *input_line_pointer
= 0;
7731 as_bad (_("missing or invalid expression `%s'"), save
);
7732 *input_line_pointer
= c
;
7739 intel_syntax
= -intel_syntax
;
7742 i386_intel_simplify (exp
);
7748 signed_cons (int size
)
7750 if (flag_code
== CODE_64BIT
)
7758 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7765 if (exp
.X_op
== O_symbol
)
7766 exp
.X_op
= O_secrel
;
7768 emit_expr (&exp
, 4);
7770 while (*input_line_pointer
++ == ',');
7772 input_line_pointer
--;
7773 demand_empty_rest_of_line ();
7777 /* Handle Vector operations. */
7780 check_VecOperations (char *op_string
, char *op_end
)
7782 const reg_entry
*mask
;
7787 && (op_end
== NULL
|| op_string
< op_end
))
7790 if (*op_string
== '{')
7794 /* Check broadcasts. */
7795 if (strncmp (op_string
, "1to", 3) == 0)
7800 goto duplicated_vec_op
;
7803 if (*op_string
== '8')
7804 bcst_type
= BROADCAST_1TO8
;
7805 else if (*op_string
== '4')
7806 bcst_type
= BROADCAST_1TO4
;
7807 else if (*op_string
== '2')
7808 bcst_type
= BROADCAST_1TO2
;
7809 else if (*op_string
== '1'
7810 && *(op_string
+1) == '6')
7812 bcst_type
= BROADCAST_1TO16
;
7817 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7822 broadcast_op
.type
= bcst_type
;
7823 broadcast_op
.operand
= this_operand
;
7824 i
.broadcast
= &broadcast_op
;
7826 /* Check masking operation. */
7827 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7829 /* k0 can't be used for write mask. */
7830 if (mask
->reg_num
== 0)
7832 as_bad (_("`%s' can't be used for write mask"),
7839 mask_op
.mask
= mask
;
7840 mask_op
.zeroing
= 0;
7841 mask_op
.operand
= this_operand
;
7847 goto duplicated_vec_op
;
7849 i
.mask
->mask
= mask
;
7851 /* Only "{z}" is allowed here. No need to check
7852 zeroing mask explicitly. */
7853 if (i
.mask
->operand
!= this_operand
)
7855 as_bad (_("invalid write mask `%s'"), saved
);
7862 /* Check zeroing-flag for masking operation. */
7863 else if (*op_string
== 'z')
7867 mask_op
.mask
= NULL
;
7868 mask_op
.zeroing
= 1;
7869 mask_op
.operand
= this_operand
;
7874 if (i
.mask
->zeroing
)
7877 as_bad (_("duplicated `%s'"), saved
);
7881 i
.mask
->zeroing
= 1;
7883 /* Only "{%k}" is allowed here. No need to check mask
7884 register explicitly. */
7885 if (i
.mask
->operand
!= this_operand
)
7887 as_bad (_("invalid zeroing-masking `%s'"),
7896 goto unknown_vec_op
;
7898 if (*op_string
!= '}')
7900 as_bad (_("missing `}' in `%s'"), saved
);
7907 /* We don't know this one. */
7908 as_bad (_("unknown vector operation: `%s'"), saved
);
7916 i386_immediate (char *imm_start
)
7918 char *save_input_line_pointer
;
7919 char *gotfree_input_line
;
7922 i386_operand_type types
;
7924 operand_type_set (&types
, ~0);
7926 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
7928 as_bad (_("at most %d immediate operands are allowed"),
7929 MAX_IMMEDIATE_OPERANDS
);
7933 exp
= &im_expressions
[i
.imm_operands
++];
7934 i
.op
[this_operand
].imms
= exp
;
7936 if (is_space_char (*imm_start
))
7939 save_input_line_pointer
= input_line_pointer
;
7940 input_line_pointer
= imm_start
;
7942 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
7943 (i
.bnd_prefix
!= NULL
7944 || add_bnd_prefix
));
7945 if (gotfree_input_line
)
7946 input_line_pointer
= gotfree_input_line
;
7948 exp_seg
= expression (exp
);
7952 /* Handle vector operations. */
7953 if (*input_line_pointer
== '{')
7955 input_line_pointer
= check_VecOperations (input_line_pointer
,
7957 if (input_line_pointer
== NULL
)
7961 if (*input_line_pointer
)
7962 as_bad (_("junk `%s' after expression"), input_line_pointer
);
7964 input_line_pointer
= save_input_line_pointer
;
7965 if (gotfree_input_line
)
7967 free (gotfree_input_line
);
7969 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
7970 exp
->X_op
= O_illegal
;
7973 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
7977 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
7978 i386_operand_type types
, const char *imm_start
)
7980 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
7983 as_bad (_("missing or invalid immediate expression `%s'"),
7987 else if (exp
->X_op
== O_constant
)
7989 /* Size it properly later. */
7990 i
.types
[this_operand
].bitfield
.imm64
= 1;
7991 /* If not 64bit, sign extend val. */
7992 if (flag_code
!= CODE_64BIT
7993 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
7995 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
7997 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7998 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
7999 && exp_seg
!= absolute_section
8000 && exp_seg
!= text_section
8001 && exp_seg
!= data_section
8002 && exp_seg
!= bss_section
8003 && exp_seg
!= undefined_section
8004 && !bfd_is_com_section (exp_seg
))
8006 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8010 else if (!intel_syntax
&& exp_seg
== reg_section
)
8013 as_bad (_("illegal immediate register operand %s"), imm_start
);
8018 /* This is an address. The size of the address will be
8019 determined later, depending on destination register,
8020 suffix, or the default for the section. */
8021 i
.types
[this_operand
].bitfield
.imm8
= 1;
8022 i
.types
[this_operand
].bitfield
.imm16
= 1;
8023 i
.types
[this_operand
].bitfield
.imm32
= 1;
8024 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8025 i
.types
[this_operand
].bitfield
.imm64
= 1;
8026 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8034 i386_scale (char *scale
)
8037 char *save
= input_line_pointer
;
8039 input_line_pointer
= scale
;
8040 val
= get_absolute_expression ();
8045 i
.log2_scale_factor
= 0;
8048 i
.log2_scale_factor
= 1;
8051 i
.log2_scale_factor
= 2;
8054 i
.log2_scale_factor
= 3;
8058 char sep
= *input_line_pointer
;
8060 *input_line_pointer
= '\0';
8061 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8063 *input_line_pointer
= sep
;
8064 input_line_pointer
= save
;
8068 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8070 as_warn (_("scale factor of %d without an index register"),
8071 1 << i
.log2_scale_factor
);
8072 i
.log2_scale_factor
= 0;
8074 scale
= input_line_pointer
;
8075 input_line_pointer
= save
;
8080 i386_displacement (char *disp_start
, char *disp_end
)
8084 char *save_input_line_pointer
;
8085 char *gotfree_input_line
;
8087 i386_operand_type bigdisp
, types
= anydisp
;
8090 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8092 as_bad (_("at most %d displacement operands are allowed"),
8093 MAX_MEMORY_OPERANDS
);
8097 operand_type_set (&bigdisp
, 0);
8098 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8099 || (!current_templates
->start
->opcode_modifier
.jump
8100 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8102 bigdisp
.bitfield
.disp32
= 1;
8103 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8104 if (flag_code
== CODE_64BIT
)
8108 bigdisp
.bitfield
.disp32s
= 1;
8109 bigdisp
.bitfield
.disp64
= 1;
8112 else if ((flag_code
== CODE_16BIT
) ^ override
)
8114 bigdisp
.bitfield
.disp32
= 0;
8115 bigdisp
.bitfield
.disp16
= 1;
8120 /* For PC-relative branches, the width of the displacement
8121 is dependent upon data size, not address size. */
8122 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8123 if (flag_code
== CODE_64BIT
)
8125 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8126 bigdisp
.bitfield
.disp16
= 1;
8129 bigdisp
.bitfield
.disp32
= 1;
8130 bigdisp
.bitfield
.disp32s
= 1;
8136 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8138 : LONG_MNEM_SUFFIX
));
8139 bigdisp
.bitfield
.disp32
= 1;
8140 if ((flag_code
== CODE_16BIT
) ^ override
)
8142 bigdisp
.bitfield
.disp32
= 0;
8143 bigdisp
.bitfield
.disp16
= 1;
8147 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8150 exp
= &disp_expressions
[i
.disp_operands
];
8151 i
.op
[this_operand
].disps
= exp
;
8153 save_input_line_pointer
= input_line_pointer
;
8154 input_line_pointer
= disp_start
;
8155 END_STRING_AND_SAVE (disp_end
);
8157 #ifndef GCC_ASM_O_HACK
8158 #define GCC_ASM_O_HACK 0
8161 END_STRING_AND_SAVE (disp_end
+ 1);
8162 if (i
.types
[this_operand
].bitfield
.baseIndex
8163 && displacement_string_end
[-1] == '+')
8165 /* This hack is to avoid a warning when using the "o"
8166 constraint within gcc asm statements.
8169 #define _set_tssldt_desc(n,addr,limit,type) \
8170 __asm__ __volatile__ ( \
8172 "movw %w1,2+%0\n\t" \
8174 "movb %b1,4+%0\n\t" \
8175 "movb %4,5+%0\n\t" \
8176 "movb $0,6+%0\n\t" \
8177 "movb %h1,7+%0\n\t" \
8179 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8181 This works great except that the output assembler ends
8182 up looking a bit weird if it turns out that there is
8183 no offset. You end up producing code that looks like:
8196 So here we provide the missing zero. */
8198 *displacement_string_end
= '0';
8201 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
,
8202 (i
.bnd_prefix
!= NULL
8203 || add_bnd_prefix
));
8204 if (gotfree_input_line
)
8205 input_line_pointer
= gotfree_input_line
;
8207 exp_seg
= expression (exp
);
8210 if (*input_line_pointer
)
8211 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8213 RESTORE_END_STRING (disp_end
+ 1);
8215 input_line_pointer
= save_input_line_pointer
;
8216 if (gotfree_input_line
)
8218 free (gotfree_input_line
);
8220 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8221 exp
->X_op
= O_illegal
;
8224 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8226 RESTORE_END_STRING (disp_end
);
8232 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8233 i386_operand_type types
, const char *disp_start
)
8235 i386_operand_type bigdisp
;
8238 /* We do this to make sure that the section symbol is in
8239 the symbol table. We will ultimately change the relocation
8240 to be relative to the beginning of the section. */
8241 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8242 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8243 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8245 if (exp
->X_op
!= O_symbol
)
8248 if (S_IS_LOCAL (exp
->X_add_symbol
)
8249 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8250 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8251 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8252 exp
->X_op
= O_subtract
;
8253 exp
->X_op_symbol
= GOT_symbol
;
8254 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8255 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8256 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8257 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8259 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8262 else if (exp
->X_op
== O_absent
8263 || exp
->X_op
== O_illegal
8264 || exp
->X_op
== O_big
)
8267 as_bad (_("missing or invalid displacement expression `%s'"),
8272 else if (flag_code
== CODE_64BIT
8273 && !i
.prefix
[ADDR_PREFIX
]
8274 && exp
->X_op
== O_constant
)
8276 /* Since displacement is signed extended to 64bit, don't allow
8277 disp32 and turn off disp32s if they are out of range. */
8278 i
.types
[this_operand
].bitfield
.disp32
= 0;
8279 if (!fits_in_signed_long (exp
->X_add_number
))
8281 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8282 if (i
.types
[this_operand
].bitfield
.baseindex
)
8284 as_bad (_("0x%lx out range of signed 32bit displacement"),
8285 (long) exp
->X_add_number
);
8291 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8292 else if (exp
->X_op
!= O_constant
8293 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8294 && exp_seg
!= absolute_section
8295 && exp_seg
!= text_section
8296 && exp_seg
!= data_section
8297 && exp_seg
!= bss_section
8298 && exp_seg
!= undefined_section
8299 && !bfd_is_com_section (exp_seg
))
8301 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8306 /* Check if this is a displacement only operand. */
8307 bigdisp
= i
.types
[this_operand
];
8308 bigdisp
.bitfield
.disp8
= 0;
8309 bigdisp
.bitfield
.disp16
= 0;
8310 bigdisp
.bitfield
.disp32
= 0;
8311 bigdisp
.bitfield
.disp32s
= 0;
8312 bigdisp
.bitfield
.disp64
= 0;
8313 if (operand_type_all_zero (&bigdisp
))
8314 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8320 /* Make sure the memory operand we've been dealt is valid.
8321 Return 1 on success, 0 on a failure. */
8324 i386_index_check (const char *operand_string
)
8326 const char *kind
= "base/index";
8327 enum flag_code addr_mode
;
8329 if (i
.prefix
[ADDR_PREFIX
])
8330 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8333 addr_mode
= flag_code
;
8335 #if INFER_ADDR_PREFIX
8336 if (i
.mem_operands
== 0)
8338 /* Infer address prefix from the first memory operand. */
8339 const reg_entry
*addr_reg
= i
.base_reg
;
8341 if (addr_reg
== NULL
)
8342 addr_reg
= i
.index_reg
;
8346 if (addr_reg
->reg_num
== RegEip
8347 || addr_reg
->reg_num
== RegEiz
8348 || addr_reg
->reg_type
.bitfield
.reg32
)
8349 addr_mode
= CODE_32BIT
;
8350 else if (flag_code
!= CODE_64BIT
8351 && addr_reg
->reg_type
.bitfield
.reg16
)
8352 addr_mode
= CODE_16BIT
;
8354 if (addr_mode
!= flag_code
)
8356 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8358 /* Change the size of any displacement too. At most one
8359 of Disp16 or Disp32 is set.
8360 FIXME. There doesn't seem to be any real need for
8361 separate Disp16 and Disp32 flags. The same goes for
8362 Imm16 and Imm32. Removing them would probably clean
8363 up the code quite a lot. */
8364 if (flag_code
!= CODE_64BIT
8365 && (i
.types
[this_operand
].bitfield
.disp16
8366 || i
.types
[this_operand
].bitfield
.disp32
))
8367 i
.types
[this_operand
]
8368 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8375 if (current_templates
->start
->opcode_modifier
.isstring
8376 && !current_templates
->start
->opcode_modifier
.immext
8377 && (current_templates
->end
[-1].opcode_modifier
.isstring
8380 /* Memory operands of string insns are special in that they only allow
8381 a single register (rDI, rSI, or rBX) as their memory address. */
8382 const reg_entry
*expected_reg
;
8383 static const char *di_si
[][2] =
8389 static const char *bx
[] = { "ebx", "bx", "rbx" };
8391 kind
= "string address";
8393 if (current_templates
->start
->opcode_modifier
.w
)
8395 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8397 if (!type
.bitfield
.baseindex
8398 || ((!i
.mem_operands
!= !intel_syntax
)
8399 && current_templates
->end
[-1].operand_types
[1]
8400 .bitfield
.baseindex
))
8401 type
= current_templates
->end
[-1].operand_types
[1];
8402 expected_reg
= hash_find (reg_hash
,
8403 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8407 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8409 if (i
.base_reg
!= expected_reg
8411 || operand_type_check (i
.types
[this_operand
], disp
))
8413 /* The second memory operand must have the same size as
8417 && !((addr_mode
== CODE_64BIT
8418 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8419 || (addr_mode
== CODE_32BIT
8420 ? i
.base_reg
->reg_type
.bitfield
.reg32
8421 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8424 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8426 intel_syntax
? '[' : '(',
8428 expected_reg
->reg_name
,
8429 intel_syntax
? ']' : ')');
8436 as_bad (_("`%s' is not a valid %s expression"),
8437 operand_string
, kind
);
8442 if (addr_mode
!= CODE_16BIT
)
8444 /* 32-bit/64-bit checks. */
8446 && (addr_mode
== CODE_64BIT
8447 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8448 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8450 || (i
.base_reg
->reg_num
8451 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8453 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8454 && !i
.index_reg
->reg_type
.bitfield
.regymm
8455 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8456 && ((addr_mode
== CODE_64BIT
8457 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8458 || i
.index_reg
->reg_num
== RegRiz
)
8459 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8460 || i
.index_reg
->reg_num
== RegEiz
))
8461 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8466 /* 16-bit checks. */
8468 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8469 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8471 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8472 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8474 && i
.base_reg
->reg_num
< 6
8475 && i
.index_reg
->reg_num
>= 6
8476 && i
.log2_scale_factor
== 0))))
8483 /* Handle vector immediates. */
8486 RC_SAE_immediate (const char *imm_start
)
8488 unsigned int match_found
, j
;
8489 const char *pstr
= imm_start
;
8497 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8499 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8503 rc_op
.type
= RC_NamesTable
[j
].type
;
8504 rc_op
.operand
= this_operand
;
8505 i
.rounding
= &rc_op
;
8509 as_bad (_("duplicated `%s'"), imm_start
);
8512 pstr
+= RC_NamesTable
[j
].len
;
8522 as_bad (_("Missing '}': '%s'"), imm_start
);
8525 /* RC/SAE immediate string should contain nothing more. */;
8528 as_bad (_("Junk after '}': '%s'"), imm_start
);
8532 exp
= &im_expressions
[i
.imm_operands
++];
8533 i
.op
[this_operand
].imms
= exp
;
8535 exp
->X_op
= O_constant
;
8536 exp
->X_add_number
= 0;
8537 exp
->X_add_symbol
= (symbolS
*) 0;
8538 exp
->X_op_symbol
= (symbolS
*) 0;
8540 i
.types
[this_operand
].bitfield
.imm8
= 1;
8544 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8548 i386_att_operand (char *operand_string
)
8552 char *op_string
= operand_string
;
8554 if (is_space_char (*op_string
))
8557 /* We check for an absolute prefix (differentiating,
8558 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8559 if (*op_string
== ABSOLUTE_PREFIX
)
8562 if (is_space_char (*op_string
))
8564 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8567 /* Check if operand is a register. */
8568 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8570 i386_operand_type temp
;
8572 /* Check for a segment override by searching for ':' after a
8573 segment register. */
8575 if (is_space_char (*op_string
))
8577 if (*op_string
== ':'
8578 && (r
->reg_type
.bitfield
.sreg2
8579 || r
->reg_type
.bitfield
.sreg3
))
8584 i
.seg
[i
.mem_operands
] = &es
;
8587 i
.seg
[i
.mem_operands
] = &cs
;
8590 i
.seg
[i
.mem_operands
] = &ss
;
8593 i
.seg
[i
.mem_operands
] = &ds
;
8596 i
.seg
[i
.mem_operands
] = &fs
;
8599 i
.seg
[i
.mem_operands
] = &gs
;
8603 /* Skip the ':' and whitespace. */
8605 if (is_space_char (*op_string
))
8608 if (!is_digit_char (*op_string
)
8609 && !is_identifier_char (*op_string
)
8610 && *op_string
!= '('
8611 && *op_string
!= ABSOLUTE_PREFIX
)
8613 as_bad (_("bad memory operand `%s'"), op_string
);
8616 /* Handle case of %es:*foo. */
8617 if (*op_string
== ABSOLUTE_PREFIX
)
8620 if (is_space_char (*op_string
))
8622 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8624 goto do_memory_reference
;
8627 /* Handle vector operations. */
8628 if (*op_string
== '{')
8630 op_string
= check_VecOperations (op_string
, NULL
);
8631 if (op_string
== NULL
)
8637 as_bad (_("junk `%s' after register"), op_string
);
8641 temp
.bitfield
.baseindex
= 0;
8642 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8644 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8645 i
.op
[this_operand
].regs
= r
;
8648 else if (*op_string
== REGISTER_PREFIX
)
8650 as_bad (_("bad register name `%s'"), op_string
);
8653 else if (*op_string
== IMMEDIATE_PREFIX
)
8656 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8658 as_bad (_("immediate operand illegal with absolute jump"));
8661 if (!i386_immediate (op_string
))
8664 else if (RC_SAE_immediate (operand_string
))
8666 /* If it is a RC or SAE immediate, do nothing. */
8669 else if (is_digit_char (*op_string
)
8670 || is_identifier_char (*op_string
)
8671 || *op_string
== '(')
8673 /* This is a memory reference of some sort. */
8676 /* Start and end of displacement string expression (if found). */
8677 char *displacement_string_start
;
8678 char *displacement_string_end
;
8681 do_memory_reference
:
8682 if ((i
.mem_operands
== 1
8683 && !current_templates
->start
->opcode_modifier
.isstring
)
8684 || i
.mem_operands
== 2)
8686 as_bad (_("too many memory references for `%s'"),
8687 current_templates
->start
->name
);
8691 /* Check for base index form. We detect the base index form by
8692 looking for an ')' at the end of the operand, searching
8693 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8695 base_string
= op_string
+ strlen (op_string
);
8697 /* Handle vector operations. */
8698 vop_start
= strchr (op_string
, '{');
8699 if (vop_start
&& vop_start
< base_string
)
8701 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8703 base_string
= vop_start
;
8707 if (is_space_char (*base_string
))
8710 /* If we only have a displacement, set-up for it to be parsed later. */
8711 displacement_string_start
= op_string
;
8712 displacement_string_end
= base_string
+ 1;
8714 if (*base_string
== ')')
8717 unsigned int parens_balanced
= 1;
8718 /* We've already checked that the number of left & right ()'s are
8719 equal, so this loop will not be infinite. */
8723 if (*base_string
== ')')
8725 if (*base_string
== '(')
8728 while (parens_balanced
);
8730 temp_string
= base_string
;
8732 /* Skip past '(' and whitespace. */
8734 if (is_space_char (*base_string
))
8737 if (*base_string
== ','
8738 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8741 displacement_string_end
= temp_string
;
8743 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8747 base_string
= end_op
;
8748 if (is_space_char (*base_string
))
8752 /* There may be an index reg or scale factor here. */
8753 if (*base_string
== ',')
8756 if (is_space_char (*base_string
))
8759 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8762 base_string
= end_op
;
8763 if (is_space_char (*base_string
))
8765 if (*base_string
== ',')
8768 if (is_space_char (*base_string
))
8771 else if (*base_string
!= ')')
8773 as_bad (_("expecting `,' or `)' "
8774 "after index register in `%s'"),
8779 else if (*base_string
== REGISTER_PREFIX
)
8781 end_op
= strchr (base_string
, ',');
8784 as_bad (_("bad register name `%s'"), base_string
);
8788 /* Check for scale factor. */
8789 if (*base_string
!= ')')
8791 char *end_scale
= i386_scale (base_string
);
8796 base_string
= end_scale
;
8797 if (is_space_char (*base_string
))
8799 if (*base_string
!= ')')
8801 as_bad (_("expecting `)' "
8802 "after scale factor in `%s'"),
8807 else if (!i
.index_reg
)
8809 as_bad (_("expecting index register or scale factor "
8810 "after `,'; got '%c'"),
8815 else if (*base_string
!= ')')
8817 as_bad (_("expecting `,' or `)' "
8818 "after base register in `%s'"),
8823 else if (*base_string
== REGISTER_PREFIX
)
8825 end_op
= strchr (base_string
, ',');
8828 as_bad (_("bad register name `%s'"), base_string
);
8833 /* If there's an expression beginning the operand, parse it,
8834 assuming displacement_string_start and
8835 displacement_string_end are meaningful. */
8836 if (displacement_string_start
!= displacement_string_end
)
8838 if (!i386_displacement (displacement_string_start
,
8839 displacement_string_end
))
8843 /* Special case for (%dx) while doing input/output op. */
8845 && operand_type_equal (&i
.base_reg
->reg_type
,
8846 ®16_inoutportreg
)
8848 && i
.log2_scale_factor
== 0
8849 && i
.seg
[i
.mem_operands
] == 0
8850 && !operand_type_check (i
.types
[this_operand
], disp
))
8852 i
.types
[this_operand
] = inoutportreg
;
8856 if (i386_index_check (operand_string
) == 0)
8858 i
.types
[this_operand
].bitfield
.mem
= 1;
8863 /* It's not a memory operand; argh! */
8864 as_bad (_("invalid char %s beginning operand %d `%s'"),
8865 output_invalid (*op_string
),
8870 return 1; /* Normal return. */
8873 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8874 that an rs_machine_dependent frag may reach. */
8877 i386_frag_max_var (fragS
*frag
)
8879 /* The only relaxable frags are for jumps.
8880 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8881 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8882 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8885 /* md_estimate_size_before_relax()
8887 Called just before relax() for rs_machine_dependent frags. The x86
8888 assembler uses these frags to handle variable size jump
8891 Any symbol that is now undefined will not become defined.
8892 Return the correct fr_subtype in the frag.
8893 Return the initial "guess for variable size of frag" to caller.
8894 The guess is actually the growth beyond the fixed part. Whatever
8895 we do to grow the fixed or variable part contributes to our
8899 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
8901 /* We've already got fragP->fr_subtype right; all we have to do is
8902 check for un-relaxable symbols. On an ELF system, we can't relax
8903 an externally visible symbol, because it may be overridden by a
8905 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
8906 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8908 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
8909 || S_IS_WEAK (fragP
->fr_symbol
)
8910 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
8911 & BSF_GNU_INDIRECT_FUNCTION
))))
8913 #if defined (OBJ_COFF) && defined (TE_PE)
8914 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
8915 && S_IS_WEAK (fragP
->fr_symbol
))
8919 /* Symbol is undefined in this segment, or we need to keep a
8920 reloc so that weak symbols can be overridden. */
8921 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
8922 enum bfd_reloc_code_real reloc_type
;
8923 unsigned char *opcode
;
8926 if (fragP
->fr_var
!= NO_RELOC
)
8927 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
8929 reloc_type
= BFD_RELOC_16_PCREL
;
8931 reloc_type
= BFD_RELOC_32_PCREL
;
8933 old_fr_fix
= fragP
->fr_fix
;
8934 opcode
= (unsigned char *) fragP
->fr_opcode
;
8936 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
8939 /* Make jmp (0xeb) a (d)word displacement jump. */
8941 fragP
->fr_fix
+= size
;
8942 fix_new (fragP
, old_fr_fix
, size
,
8944 fragP
->fr_offset
, 1,
8950 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
8952 /* Negate the condition, and branch past an
8953 unconditional jump. */
8956 /* Insert an unconditional jump. */
8958 /* We added two extra opcode bytes, and have a two byte
8960 fragP
->fr_fix
+= 2 + 2;
8961 fix_new (fragP
, old_fr_fix
+ 2, 2,
8963 fragP
->fr_offset
, 1,
8970 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
8975 fixP
= fix_new (fragP
, old_fr_fix
, 1,
8977 fragP
->fr_offset
, 1,
8979 fixP
->fx_signed
= 1;
8983 /* This changes the byte-displacement jump 0x7N
8984 to the (d)word-displacement jump 0x0f,0x8N. */
8985 opcode
[1] = opcode
[0] + 0x10;
8986 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
8987 /* We've added an opcode byte. */
8988 fragP
->fr_fix
+= 1 + size
;
8989 fix_new (fragP
, old_fr_fix
+ 1, size
,
8991 fragP
->fr_offset
, 1,
8996 BAD_CASE (fragP
->fr_subtype
);
9000 return fragP
->fr_fix
- old_fr_fix
;
9003 /* Guess size depending on current relax state. Initially the relax
9004 state will correspond to a short jump and we return 1, because
9005 the variable part of the frag (the branch offset) is one byte
9006 long. However, we can relax a section more than once and in that
9007 case we must either set fr_subtype back to the unrelaxed state,
9008 or return the value for the appropriate branch. */
9009 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9012 /* Called after relax() is finished.
9014 In: Address of frag.
9015 fr_type == rs_machine_dependent.
9016 fr_subtype is what the address relaxed to.
9018 Out: Any fixSs and constants are set up.
9019 Caller will turn frag into a ".space 0". */
9022 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9025 unsigned char *opcode
;
9026 unsigned char *where_to_put_displacement
= NULL
;
9027 offsetT target_address
;
9028 offsetT opcode_address
;
9029 unsigned int extension
= 0;
9030 offsetT displacement_from_opcode_start
;
9032 opcode
= (unsigned char *) fragP
->fr_opcode
;
9034 /* Address we want to reach in file space. */
9035 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9037 /* Address opcode resides at in file space. */
9038 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9040 /* Displacement from opcode start to fill into instruction. */
9041 displacement_from_opcode_start
= target_address
- opcode_address
;
9043 if ((fragP
->fr_subtype
& BIG
) == 0)
9045 /* Don't have to change opcode. */
9046 extension
= 1; /* 1 opcode + 1 displacement */
9047 where_to_put_displacement
= &opcode
[1];
9051 if (no_cond_jump_promotion
9052 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9053 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9054 _("long jump required"));
9056 switch (fragP
->fr_subtype
)
9058 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9059 extension
= 4; /* 1 opcode + 4 displacement */
9061 where_to_put_displacement
= &opcode
[1];
9064 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9065 extension
= 2; /* 1 opcode + 2 displacement */
9067 where_to_put_displacement
= &opcode
[1];
9070 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9071 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9072 extension
= 5; /* 2 opcode + 4 displacement */
9073 opcode
[1] = opcode
[0] + 0x10;
9074 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9075 where_to_put_displacement
= &opcode
[2];
9078 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9079 extension
= 3; /* 2 opcode + 2 displacement */
9080 opcode
[1] = opcode
[0] + 0x10;
9081 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9082 where_to_put_displacement
= &opcode
[2];
9085 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9090 where_to_put_displacement
= &opcode
[3];
9094 BAD_CASE (fragP
->fr_subtype
);
9099 /* If size if less then four we are sure that the operand fits,
9100 but if it's 4, then it could be that the displacement is larger
9102 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9104 && ((addressT
) (displacement_from_opcode_start
- extension
9105 + ((addressT
) 1 << 31))
9106 > (((addressT
) 2 << 31) - 1)))
9108 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9109 _("jump target out of range"));
9110 /* Make us emit 0. */
9111 displacement_from_opcode_start
= extension
;
9113 /* Now put displacement after opcode. */
9114 md_number_to_chars ((char *) where_to_put_displacement
,
9115 (valueT
) (displacement_from_opcode_start
- extension
),
9116 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9117 fragP
->fr_fix
+= extension
;
9120 /* Apply a fixup (fixP) to segment data, once it has been determined
9121 by our caller that we have all the info we need to fix it up.
9123 Parameter valP is the pointer to the value of the bits.
9125 On the 386, immediates, displacements, and data pointers are all in
9126 the same (little-endian) format, so we don't need to care about which
9130 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9132 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9133 valueT value
= *valP
;
9135 #if !defined (TE_Mach)
9138 switch (fixP
->fx_r_type
)
9144 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9147 case BFD_RELOC_X86_64_32S
:
9148 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9151 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9154 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9159 if (fixP
->fx_addsy
!= NULL
9160 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9161 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9162 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9163 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
9164 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
)
9165 && !use_rela_relocations
)
9167 /* This is a hack. There should be a better way to handle this.
9168 This covers for the fact that bfd_install_relocation will
9169 subtract the current location (for partial_inplace, PC relative
9170 relocations); see more below. */
9174 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9177 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9182 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9185 || (symbol_section_p (fixP
->fx_addsy
)
9186 && sym_seg
!= absolute_section
))
9187 && !generic_force_reloc (fixP
))
9189 /* Yes, we add the values in twice. This is because
9190 bfd_install_relocation subtracts them out again. I think
9191 bfd_install_relocation is broken, but I don't dare change
9193 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9197 #if defined (OBJ_COFF) && defined (TE_PE)
9198 /* For some reason, the PE format does not store a
9199 section address offset for a PC relative symbol. */
9200 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9201 || S_IS_WEAK (fixP
->fx_addsy
))
9202 value
+= md_pcrel_from (fixP
);
9205 #if defined (OBJ_COFF) && defined (TE_PE)
9206 if (fixP
->fx_addsy
!= NULL
9207 && S_IS_WEAK (fixP
->fx_addsy
)
9208 /* PR 16858: Do not modify weak function references. */
9209 && ! fixP
->fx_pcrel
)
9211 #if !defined (TE_PEP)
9212 /* For x86 PE weak function symbols are neither PC-relative
9213 nor do they set S_IS_FUNCTION. So the only reliable way
9214 to detect them is to check the flags of their containing
9216 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9217 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9221 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9225 /* Fix a few things - the dynamic linker expects certain values here,
9226 and we must not disappoint it. */
9227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9228 if (IS_ELF
&& fixP
->fx_addsy
)
9229 switch (fixP
->fx_r_type
)
9231 case BFD_RELOC_386_PLT32
:
9232 case BFD_RELOC_X86_64_PLT32
:
9233 case BFD_RELOC_X86_64_PLT32_BND
:
9234 /* Make the jump instruction point to the address of the operand. At
9235 runtime we merely add the offset to the actual PLT entry. */
9239 case BFD_RELOC_386_TLS_GD
:
9240 case BFD_RELOC_386_TLS_LDM
:
9241 case BFD_RELOC_386_TLS_IE_32
:
9242 case BFD_RELOC_386_TLS_IE
:
9243 case BFD_RELOC_386_TLS_GOTIE
:
9244 case BFD_RELOC_386_TLS_GOTDESC
:
9245 case BFD_RELOC_X86_64_TLSGD
:
9246 case BFD_RELOC_X86_64_TLSLD
:
9247 case BFD_RELOC_X86_64_GOTTPOFF
:
9248 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9249 value
= 0; /* Fully resolved at runtime. No addend. */
9251 case BFD_RELOC_386_TLS_LE
:
9252 case BFD_RELOC_386_TLS_LDO_32
:
9253 case BFD_RELOC_386_TLS_LE_32
:
9254 case BFD_RELOC_X86_64_DTPOFF32
:
9255 case BFD_RELOC_X86_64_DTPOFF64
:
9256 case BFD_RELOC_X86_64_TPOFF32
:
9257 case BFD_RELOC_X86_64_TPOFF64
:
9258 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9261 case BFD_RELOC_386_TLS_DESC_CALL
:
9262 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9263 value
= 0; /* Fully resolved at runtime. No addend. */
9264 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9268 case BFD_RELOC_386_GOT32
:
9269 case BFD_RELOC_X86_64_GOT32
:
9270 value
= 0; /* Fully resolved at runtime. No addend. */
9273 case BFD_RELOC_VTABLE_INHERIT
:
9274 case BFD_RELOC_VTABLE_ENTRY
:
9281 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9283 #endif /* !defined (TE_Mach) */
9285 /* Are we finished with this relocation now? */
9286 if (fixP
->fx_addsy
== NULL
)
9288 #if defined (OBJ_COFF) && defined (TE_PE)
9289 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9292 /* Remember value for tc_gen_reloc. */
9293 fixP
->fx_addnumber
= value
;
9294 /* Clear out the frag for now. */
9298 else if (use_rela_relocations
)
9300 fixP
->fx_no_overflow
= 1;
9301 /* Remember value for tc_gen_reloc. */
9302 fixP
->fx_addnumber
= value
;
9306 md_number_to_chars (p
, value
, fixP
->fx_size
);
9310 md_atof (int type
, char *litP
, int *sizeP
)
9312 /* This outputs the LITTLENUMs in REVERSE order;
9313 in accord with the bigendian 386. */
9314 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9317 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9320 output_invalid (int c
)
9323 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9326 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9327 "(0x%x)", (unsigned char) c
);
9328 return output_invalid_buf
;
9331 /* REG_STRING starts *before* REGISTER_PREFIX. */
9333 static const reg_entry
*
9334 parse_real_register (char *reg_string
, char **end_op
)
9336 char *s
= reg_string
;
9338 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9341 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9342 if (*s
== REGISTER_PREFIX
)
9345 if (is_space_char (*s
))
9349 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9351 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9352 return (const reg_entry
*) NULL
;
9356 /* For naked regs, make sure that we are not dealing with an identifier.
9357 This prevents confusing an identifier like `eax_var' with register
9359 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9360 return (const reg_entry
*) NULL
;
9364 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9366 /* Handle floating point regs, allowing spaces in the (i) part. */
9367 if (r
== i386_regtab
/* %st is first entry of table */)
9369 if (is_space_char (*s
))
9374 if (is_space_char (*s
))
9376 if (*s
>= '0' && *s
<= '7')
9380 if (is_space_char (*s
))
9385 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9390 /* We have "%st(" then garbage. */
9391 return (const reg_entry
*) NULL
;
9395 if (r
== NULL
|| allow_pseudo_reg
)
9398 if (operand_type_all_zero (&r
->reg_type
))
9399 return (const reg_entry
*) NULL
;
9401 if ((r
->reg_type
.bitfield
.reg32
9402 || r
->reg_type
.bitfield
.sreg3
9403 || r
->reg_type
.bitfield
.control
9404 || r
->reg_type
.bitfield
.debug
9405 || r
->reg_type
.bitfield
.test
)
9406 && !cpu_arch_flags
.bitfield
.cpui386
)
9407 return (const reg_entry
*) NULL
;
9409 if (r
->reg_type
.bitfield
.floatreg
9410 && !cpu_arch_flags
.bitfield
.cpu8087
9411 && !cpu_arch_flags
.bitfield
.cpu287
9412 && !cpu_arch_flags
.bitfield
.cpu387
)
9413 return (const reg_entry
*) NULL
;
9415 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9416 return (const reg_entry
*) NULL
;
9418 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9419 return (const reg_entry
*) NULL
;
9421 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9422 return (const reg_entry
*) NULL
;
9424 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9425 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9426 return (const reg_entry
*) NULL
;
9428 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9429 if (!allow_index_reg
9430 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9431 return (const reg_entry
*) NULL
;
9433 /* Upper 16 vector register is only available with VREX in 64bit
9435 if ((r
->reg_flags
& RegVRex
))
9437 if (!cpu_arch_flags
.bitfield
.cpuvrex
9438 || flag_code
!= CODE_64BIT
)
9439 return (const reg_entry
*) NULL
;
9444 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9445 || r
->reg_type
.bitfield
.reg64
)
9446 && (!cpu_arch_flags
.bitfield
.cpulm
9447 || !operand_type_equal (&r
->reg_type
, &control
))
9448 && flag_code
!= CODE_64BIT
)
9449 return (const reg_entry
*) NULL
;
9451 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9452 return (const reg_entry
*) NULL
;
9457 /* REG_STRING starts *before* REGISTER_PREFIX. */
9459 static const reg_entry
*
9460 parse_register (char *reg_string
, char **end_op
)
9464 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9465 r
= parse_real_register (reg_string
, end_op
);
9470 char *save
= input_line_pointer
;
9474 input_line_pointer
= reg_string
;
9475 c
= get_symbol_end ();
9476 symbolP
= symbol_find (reg_string
);
9477 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9479 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9481 know (e
->X_op
== O_register
);
9482 know (e
->X_add_number
>= 0
9483 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9484 r
= i386_regtab
+ e
->X_add_number
;
9485 if ((r
->reg_flags
& RegVRex
))
9487 *end_op
= input_line_pointer
;
9489 *input_line_pointer
= c
;
9490 input_line_pointer
= save
;
9496 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9499 char *end
= input_line_pointer
;
9502 r
= parse_register (name
, &input_line_pointer
);
9503 if (r
&& end
<= input_line_pointer
)
9505 *nextcharP
= *input_line_pointer
;
9506 *input_line_pointer
= 0;
9507 e
->X_op
= O_register
;
9508 e
->X_add_number
= r
- i386_regtab
;
9511 input_line_pointer
= end
;
9513 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9517 md_operand (expressionS
*e
)
9522 switch (*input_line_pointer
)
9524 case REGISTER_PREFIX
:
9525 r
= parse_real_register (input_line_pointer
, &end
);
9528 e
->X_op
= O_register
;
9529 e
->X_add_number
= r
- i386_regtab
;
9530 input_line_pointer
= end
;
9535 gas_assert (intel_syntax
);
9536 end
= input_line_pointer
++;
9538 if (*input_line_pointer
== ']')
9540 ++input_line_pointer
;
9541 e
->X_op_symbol
= make_expr_symbol (e
);
9542 e
->X_add_symbol
= NULL
;
9543 e
->X_add_number
= 0;
9549 input_line_pointer
= end
;
9556 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9557 const char *md_shortopts
= "kVQ:sqn";
9559 const char *md_shortopts
= "qn";
9562 #define OPTION_32 (OPTION_MD_BASE + 0)
9563 #define OPTION_64 (OPTION_MD_BASE + 1)
9564 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9565 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9566 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9567 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9568 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9569 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9570 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9571 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9572 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9573 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9574 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9575 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9576 #define OPTION_X32 (OPTION_MD_BASE + 14)
9577 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9578 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9579 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9580 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9581 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9582 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9584 struct option md_longopts
[] =
9586 {"32", no_argument
, NULL
, OPTION_32
},
9587 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9588 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9589 {"64", no_argument
, NULL
, OPTION_64
},
9591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9592 {"x32", no_argument
, NULL
, OPTION_X32
},
9594 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9595 {"march", required_argument
, NULL
, OPTION_MARCH
},
9596 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9597 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9598 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9599 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9600 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9601 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9602 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9603 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9604 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9605 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9606 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9607 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9608 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9609 # if defined (TE_PE) || defined (TE_PEP)
9610 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9612 {"momit-lock-prefix", required_argument
, NULL
, OPTION_OMIT_LOCK_PREFIX
},
9613 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9614 {NULL
, no_argument
, NULL
, 0}
9616 size_t md_longopts_size
= sizeof (md_longopts
);
9619 md_parse_option (int c
, char *arg
)
9627 optimize_align_code
= 0;
9634 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9635 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9636 should be emitted or not. FIXME: Not implemented. */
9640 /* -V: SVR4 argument to print version ID. */
9642 print_version_id ();
9645 /* -k: Ignore for FreeBSD compatibility. */
9650 /* -s: On i386 Solaris, this tells the native assembler to use
9651 .stab instead of .stab.excl. We always use .stab anyhow. */
9654 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9655 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9658 const char **list
, **l
;
9660 list
= bfd_target_list ();
9661 for (l
= list
; *l
!= NULL
; l
++)
9662 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9663 || strcmp (*l
, "coff-x86-64") == 0
9664 || strcmp (*l
, "pe-x86-64") == 0
9665 || strcmp (*l
, "pei-x86-64") == 0
9666 || strcmp (*l
, "mach-o-x86-64") == 0)
9668 default_arch
= "x86_64";
9672 as_fatal (_("no compiled in support for x86_64"));
9678 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9682 const char **list
, **l
;
9684 list
= bfd_target_list ();
9685 for (l
= list
; *l
!= NULL
; l
++)
9686 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9688 default_arch
= "x86_64:32";
9692 as_fatal (_("no compiled in support for 32bit x86_64"));
9696 as_fatal (_("32bit x86_64 is only supported for ELF"));
9701 default_arch
= "i386";
9705 #ifdef SVR4_COMMENT_CHARS
9710 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
9712 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9716 i386_comment_chars
= n
;
9722 arch
= xstrdup (arg
);
9726 as_fatal (_("invalid -march= option: `%s'"), arg
);
9727 next
= strchr (arch
, '+');
9730 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9732 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9735 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9738 cpu_arch_name
= cpu_arch
[j
].name
;
9739 cpu_sub_arch_name
= NULL
;
9740 cpu_arch_flags
= cpu_arch
[j
].flags
;
9741 cpu_arch_isa
= cpu_arch
[j
].type
;
9742 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9743 if (!cpu_arch_tune_set
)
9745 cpu_arch_tune
= cpu_arch_isa
;
9746 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9750 else if (*cpu_arch
[j
].name
== '.'
9751 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9753 /* ISA entension. */
9754 i386_cpu_flags flags
;
9756 if (!cpu_arch
[j
].negated
)
9757 flags
= cpu_flags_or (cpu_arch_flags
,
9760 flags
= cpu_flags_and_not (cpu_arch_flags
,
9762 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9764 if (cpu_sub_arch_name
)
9766 char *name
= cpu_sub_arch_name
;
9767 cpu_sub_arch_name
= concat (name
,
9769 (const char *) NULL
);
9773 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9774 cpu_arch_flags
= flags
;
9775 cpu_arch_isa_flags
= flags
;
9781 if (j
>= ARRAY_SIZE (cpu_arch
))
9782 as_fatal (_("invalid -march= option: `%s'"), arg
);
9786 while (next
!= NULL
);
9791 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9792 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9794 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9796 cpu_arch_tune_set
= 1;
9797 cpu_arch_tune
= cpu_arch
[j
].type
;
9798 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9802 if (j
>= ARRAY_SIZE (cpu_arch
))
9803 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9806 case OPTION_MMNEMONIC
:
9807 if (strcasecmp (arg
, "att") == 0)
9809 else if (strcasecmp (arg
, "intel") == 0)
9812 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9815 case OPTION_MSYNTAX
:
9816 if (strcasecmp (arg
, "att") == 0)
9818 else if (strcasecmp (arg
, "intel") == 0)
9821 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
9824 case OPTION_MINDEX_REG
:
9825 allow_index_reg
= 1;
9828 case OPTION_MNAKED_REG
:
9829 allow_naked_reg
= 1;
9832 case OPTION_MOLD_GCC
:
9836 case OPTION_MSSE2AVX
:
9840 case OPTION_MSSE_CHECK
:
9841 if (strcasecmp (arg
, "error") == 0)
9842 sse_check
= check_error
;
9843 else if (strcasecmp (arg
, "warning") == 0)
9844 sse_check
= check_warning
;
9845 else if (strcasecmp (arg
, "none") == 0)
9846 sse_check
= check_none
;
9848 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
9851 case OPTION_MOPERAND_CHECK
:
9852 if (strcasecmp (arg
, "error") == 0)
9853 operand_check
= check_error
;
9854 else if (strcasecmp (arg
, "warning") == 0)
9855 operand_check
= check_warning
;
9856 else if (strcasecmp (arg
, "none") == 0)
9857 operand_check
= check_none
;
9859 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
9862 case OPTION_MAVXSCALAR
:
9863 if (strcasecmp (arg
, "128") == 0)
9865 else if (strcasecmp (arg
, "256") == 0)
9868 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
9871 case OPTION_MADD_BND_PREFIX
:
9875 case OPTION_MEVEXLIG
:
9876 if (strcmp (arg
, "128") == 0)
9878 else if (strcmp (arg
, "256") == 0)
9880 else if (strcmp (arg
, "512") == 0)
9883 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
9886 case OPTION_MEVEXRCIG
:
9887 if (strcmp (arg
, "rne") == 0)
9889 else if (strcmp (arg
, "rd") == 0)
9891 else if (strcmp (arg
, "ru") == 0)
9893 else if (strcmp (arg
, "rz") == 0)
9896 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
9899 case OPTION_MEVEXWIG
:
9900 if (strcmp (arg
, "0") == 0)
9902 else if (strcmp (arg
, "1") == 0)
9905 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
9908 # if defined (TE_PE) || defined (TE_PEP)
9909 case OPTION_MBIG_OBJ
:
9914 case OPTION_OMIT_LOCK_PREFIX
:
9915 if (strcasecmp (arg
, "yes") == 0)
9916 omit_lock_prefix
= 1;
9917 else if (strcasecmp (arg
, "no") == 0)
9918 omit_lock_prefix
= 0;
9920 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
9929 #define MESSAGE_TEMPLATE \
9933 show_arch (FILE *stream
, int ext
, int check
)
9935 static char message
[] = MESSAGE_TEMPLATE
;
9936 char *start
= message
+ 27;
9938 int size
= sizeof (MESSAGE_TEMPLATE
);
9945 left
= size
- (start
- message
);
9946 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9948 /* Should it be skipped? */
9949 if (cpu_arch
[j
].skip
)
9952 name
= cpu_arch
[j
].name
;
9953 len
= cpu_arch
[j
].len
;
9956 /* It is an extension. Skip if we aren't asked to show it. */
9967 /* It is an processor. Skip if we show only extension. */
9970 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9972 /* It is an impossible processor - skip. */
9976 /* Reserve 2 spaces for ", " or ",\0" */
9979 /* Check if there is any room. */
9987 p
= mempcpy (p
, name
, len
);
9991 /* Output the current message now and start a new one. */
9994 fprintf (stream
, "%s\n", message
);
9996 left
= size
- (start
- message
) - len
- 2;
9998 gas_assert (left
>= 0);
10000 p
= mempcpy (p
, name
, len
);
10005 fprintf (stream
, "%s\n", message
);
10009 md_show_usage (FILE *stream
)
10011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10012 fprintf (stream
, _("\
10014 -V print assembler version number\n\
10017 fprintf (stream
, _("\
10018 -n Do not optimize code alignment\n\
10019 -q quieten some warnings\n"));
10020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10021 fprintf (stream
, _("\
10024 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10025 || defined (TE_PE) || defined (TE_PEP))
10026 fprintf (stream
, _("\
10027 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10029 #ifdef SVR4_COMMENT_CHARS
10030 fprintf (stream
, _("\
10031 --divide do not treat `/' as a comment character\n"));
10033 fprintf (stream
, _("\
10034 --divide ignored\n"));
10036 fprintf (stream
, _("\
10037 -march=CPU[,+EXTENSION...]\n\
10038 generate code for CPU and EXTENSION, CPU is one of:\n"));
10039 show_arch (stream
, 0, 1);
10040 fprintf (stream
, _("\
10041 EXTENSION is combination of:\n"));
10042 show_arch (stream
, 1, 0);
10043 fprintf (stream
, _("\
10044 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10045 show_arch (stream
, 0, 0);
10046 fprintf (stream
, _("\
10047 -msse2avx encode SSE instructions with VEX prefix\n"));
10048 fprintf (stream
, _("\
10049 -msse-check=[none|error|warning]\n\
10050 check SSE instructions\n"));
10051 fprintf (stream
, _("\
10052 -moperand-check=[none|error|warning]\n\
10053 check operand combinations for validity\n"));
10054 fprintf (stream
, _("\
10055 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10057 fprintf (stream
, _("\
10058 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10060 fprintf (stream
, _("\
10061 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10062 for EVEX.W bit ignored instructions\n"));
10063 fprintf (stream
, _("\
10064 -mevexrcig=[rne|rd|ru|rz]\n\
10065 encode EVEX instructions with specific EVEX.RC value\n\
10066 for SAE-only ignored instructions\n"));
10067 fprintf (stream
, _("\
10068 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10069 fprintf (stream
, _("\
10070 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10071 fprintf (stream
, _("\
10072 -mindex-reg support pseudo index registers\n"));
10073 fprintf (stream
, _("\
10074 -mnaked-reg don't require `%%' prefix for registers\n"));
10075 fprintf (stream
, _("\
10076 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10077 fprintf (stream
, _("\
10078 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10079 # if defined (TE_PE) || defined (TE_PEP)
10080 fprintf (stream
, _("\
10081 -mbig-obj generate big object files\n"));
10083 fprintf (stream
, _("\
10084 -momit-lock-prefix=[no|yes]\n\
10085 strip all lock prefixes\n"));
10088 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10089 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10090 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10092 /* Pick the target format to use. */
10095 i386_target_format (void)
10097 if (!strncmp (default_arch
, "x86_64", 6))
10099 update_code_flag (CODE_64BIT
, 1);
10100 if (default_arch
[6] == '\0')
10101 x86_elf_abi
= X86_64_ABI
;
10103 x86_elf_abi
= X86_64_X32_ABI
;
10105 else if (!strcmp (default_arch
, "i386"))
10106 update_code_flag (CODE_32BIT
, 1);
10108 as_fatal (_("unknown architecture"));
10110 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10111 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10112 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10113 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10115 switch (OUTPUT_FLAVOR
)
10117 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10118 case bfd_target_aout_flavour
:
10119 return AOUT_TARGET_FORMAT
;
10121 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10122 # if defined (TE_PE) || defined (TE_PEP)
10123 case bfd_target_coff_flavour
:
10124 if (flag_code
== CODE_64BIT
)
10125 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10128 # elif defined (TE_GO32)
10129 case bfd_target_coff_flavour
:
10130 return "coff-go32";
10132 case bfd_target_coff_flavour
:
10133 return "coff-i386";
10136 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10137 case bfd_target_elf_flavour
:
10139 const char *format
;
10141 switch (x86_elf_abi
)
10144 format
= ELF_TARGET_FORMAT
;
10147 use_rela_relocations
= 1;
10149 format
= ELF_TARGET_FORMAT64
;
10151 case X86_64_X32_ABI
:
10152 use_rela_relocations
= 1;
10154 disallow_64bit_reloc
= 1;
10155 format
= ELF_TARGET_FORMAT32
;
10158 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10160 if (x86_elf_abi
!= X86_64_ABI
)
10161 as_fatal (_("Intel L1OM is 64bit only"));
10162 return ELF_TARGET_L1OM_FORMAT
;
10164 if (cpu_arch_isa
== PROCESSOR_K1OM
)
10166 if (x86_elf_abi
!= X86_64_ABI
)
10167 as_fatal (_("Intel K1OM is 64bit only"));
10168 return ELF_TARGET_K1OM_FORMAT
;
10174 #if defined (OBJ_MACH_O)
10175 case bfd_target_mach_o_flavour
:
10176 if (flag_code
== CODE_64BIT
)
10178 use_rela_relocations
= 1;
10180 return "mach-o-x86-64";
10183 return "mach-o-i386";
10191 #endif /* OBJ_MAYBE_ more than one */
10193 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10195 i386_elf_emit_arch_note (void)
10197 if (IS_ELF
&& cpu_arch_name
!= NULL
)
10200 asection
*seg
= now_seg
;
10201 subsegT subseg
= now_subseg
;
10202 Elf_Internal_Note i_note
;
10203 Elf_External_Note e_note
;
10204 asection
*note_secp
;
10207 /* Create the .note section. */
10208 note_secp
= subseg_new (".note", 0);
10209 bfd_set_section_flags (stdoutput
,
10211 SEC_HAS_CONTENTS
| SEC_READONLY
);
10213 /* Process the arch string. */
10214 len
= strlen (cpu_arch_name
);
10216 i_note
.namesz
= len
+ 1;
10218 i_note
.type
= NT_ARCH
;
10219 p
= frag_more (sizeof (e_note
.namesz
));
10220 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
10221 p
= frag_more (sizeof (e_note
.descsz
));
10222 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
10223 p
= frag_more (sizeof (e_note
.type
));
10224 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
10225 p
= frag_more (len
+ 1);
10226 strcpy (p
, cpu_arch_name
);
10228 frag_align (2, 0, 0);
10230 subseg_set (seg
, subseg
);
10236 md_undefined_symbol (char *name
)
10238 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10239 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10240 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10241 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10245 if (symbol_find (name
))
10246 as_bad (_("GOT already in symbol table"));
10247 GOT_symbol
= symbol_new (name
, undefined_section
,
10248 (valueT
) 0, &zero_address_frag
);
10255 /* Round up a section size to the appropriate boundary. */
10258 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10260 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10261 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10263 /* For a.out, force the section size to be aligned. If we don't do
10264 this, BFD will align it for us, but it will not write out the
10265 final bytes of the section. This may be a bug in BFD, but it is
10266 easier to fix it here since that is how the other a.out targets
10270 align
= bfd_get_section_alignment (stdoutput
, segment
);
10271 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
10278 /* On the i386, PC-relative offsets are relative to the start of the
10279 next instruction. That is, the address of the offset, plus its
10280 size, since the offset is always the last part of the insn. */
10283 md_pcrel_from (fixS
*fixP
)
10285 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10291 s_bss (int ignore ATTRIBUTE_UNUSED
)
10295 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10297 obj_elf_section_change_hook ();
10299 temp
= get_absolute_expression ();
10300 subseg_set (bss_section
, (subsegT
) temp
);
10301 demand_empty_rest_of_line ();
10307 i386_validate_fix (fixS
*fixp
)
10309 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
10311 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10315 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10320 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10322 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10324 fixp
->fx_subsy
= 0;
10329 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10332 bfd_reloc_code_real_type code
;
10334 switch (fixp
->fx_r_type
)
10336 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10337 case BFD_RELOC_SIZE32
:
10338 case BFD_RELOC_SIZE64
:
10339 if (S_IS_DEFINED (fixp
->fx_addsy
)
10340 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10342 /* Resolve size relocation against local symbol to size of
10343 the symbol plus addend. */
10344 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10345 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10346 && !fits_in_unsigned_long (value
))
10347 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10348 _("symbol size computation overflow"));
10349 fixp
->fx_addsy
= NULL
;
10350 fixp
->fx_subsy
= NULL
;
10351 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10356 case BFD_RELOC_X86_64_PLT32
:
10357 case BFD_RELOC_X86_64_PLT32_BND
:
10358 case BFD_RELOC_X86_64_GOT32
:
10359 case BFD_RELOC_X86_64_GOTPCREL
:
10360 case BFD_RELOC_386_PLT32
:
10361 case BFD_RELOC_386_GOT32
:
10362 case BFD_RELOC_386_GOTOFF
:
10363 case BFD_RELOC_386_GOTPC
:
10364 case BFD_RELOC_386_TLS_GD
:
10365 case BFD_RELOC_386_TLS_LDM
:
10366 case BFD_RELOC_386_TLS_LDO_32
:
10367 case BFD_RELOC_386_TLS_IE_32
:
10368 case BFD_RELOC_386_TLS_IE
:
10369 case BFD_RELOC_386_TLS_GOTIE
:
10370 case BFD_RELOC_386_TLS_LE_32
:
10371 case BFD_RELOC_386_TLS_LE
:
10372 case BFD_RELOC_386_TLS_GOTDESC
:
10373 case BFD_RELOC_386_TLS_DESC_CALL
:
10374 case BFD_RELOC_X86_64_TLSGD
:
10375 case BFD_RELOC_X86_64_TLSLD
:
10376 case BFD_RELOC_X86_64_DTPOFF32
:
10377 case BFD_RELOC_X86_64_DTPOFF64
:
10378 case BFD_RELOC_X86_64_GOTTPOFF
:
10379 case BFD_RELOC_X86_64_TPOFF32
:
10380 case BFD_RELOC_X86_64_TPOFF64
:
10381 case BFD_RELOC_X86_64_GOTOFF64
:
10382 case BFD_RELOC_X86_64_GOTPC32
:
10383 case BFD_RELOC_X86_64_GOT64
:
10384 case BFD_RELOC_X86_64_GOTPCREL64
:
10385 case BFD_RELOC_X86_64_GOTPC64
:
10386 case BFD_RELOC_X86_64_GOTPLT64
:
10387 case BFD_RELOC_X86_64_PLTOFF64
:
10388 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10389 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10390 case BFD_RELOC_RVA
:
10391 case BFD_RELOC_VTABLE_ENTRY
:
10392 case BFD_RELOC_VTABLE_INHERIT
:
10394 case BFD_RELOC_32_SECREL
:
10396 code
= fixp
->fx_r_type
;
10398 case BFD_RELOC_X86_64_32S
:
10399 if (!fixp
->fx_pcrel
)
10401 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10402 code
= fixp
->fx_r_type
;
10406 if (fixp
->fx_pcrel
)
10408 switch (fixp
->fx_size
)
10411 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10412 _("can not do %d byte pc-relative relocation"),
10414 code
= BFD_RELOC_32_PCREL
;
10416 case 1: code
= BFD_RELOC_8_PCREL
; break;
10417 case 2: code
= BFD_RELOC_16_PCREL
; break;
10419 code
= (fixp
->fx_r_type
== BFD_RELOC_X86_64_PC32_BND
10420 ? fixp
-> fx_r_type
: BFD_RELOC_32_PCREL
);
10423 case 8: code
= BFD_RELOC_64_PCREL
; break;
10429 switch (fixp
->fx_size
)
10432 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10433 _("can not do %d byte relocation"),
10435 code
= BFD_RELOC_32
;
10437 case 1: code
= BFD_RELOC_8
; break;
10438 case 2: code
= BFD_RELOC_16
; break;
10439 case 4: code
= BFD_RELOC_32
; break;
10441 case 8: code
= BFD_RELOC_64
; break;
10448 if ((code
== BFD_RELOC_32
10449 || code
== BFD_RELOC_32_PCREL
10450 || code
== BFD_RELOC_X86_64_32S
)
10452 && fixp
->fx_addsy
== GOT_symbol
)
10455 code
= BFD_RELOC_386_GOTPC
;
10457 code
= BFD_RELOC_X86_64_GOTPC32
;
10459 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10461 && fixp
->fx_addsy
== GOT_symbol
)
10463 code
= BFD_RELOC_X86_64_GOTPC64
;
10466 rel
= (arelent
*) xmalloc (sizeof (arelent
));
10467 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10468 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10470 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10472 if (!use_rela_relocations
)
10474 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10475 vtable entry to be used in the relocation's section offset. */
10476 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10477 rel
->address
= fixp
->fx_offset
;
10478 #if defined (OBJ_COFF) && defined (TE_PE)
10479 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10480 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10485 /* Use the rela in 64bit mode. */
10488 if (disallow_64bit_reloc
)
10491 case BFD_RELOC_X86_64_DTPOFF64
:
10492 case BFD_RELOC_X86_64_TPOFF64
:
10493 case BFD_RELOC_64_PCREL
:
10494 case BFD_RELOC_X86_64_GOTOFF64
:
10495 case BFD_RELOC_X86_64_GOT64
:
10496 case BFD_RELOC_X86_64_GOTPCREL64
:
10497 case BFD_RELOC_X86_64_GOTPC64
:
10498 case BFD_RELOC_X86_64_GOTPLT64
:
10499 case BFD_RELOC_X86_64_PLTOFF64
:
10500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10501 _("cannot represent relocation type %s in x32 mode"),
10502 bfd_get_reloc_code_name (code
));
10508 if (!fixp
->fx_pcrel
)
10509 rel
->addend
= fixp
->fx_offset
;
10513 case BFD_RELOC_X86_64_PLT32
:
10514 case BFD_RELOC_X86_64_PLT32_BND
:
10515 case BFD_RELOC_X86_64_GOT32
:
10516 case BFD_RELOC_X86_64_GOTPCREL
:
10517 case BFD_RELOC_X86_64_TLSGD
:
10518 case BFD_RELOC_X86_64_TLSLD
:
10519 case BFD_RELOC_X86_64_GOTTPOFF
:
10520 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10521 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10522 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10525 rel
->addend
= (section
->vma
10527 + fixp
->fx_addnumber
10528 + md_pcrel_from (fixp
));
10533 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10534 if (rel
->howto
== NULL
)
10536 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10537 _("cannot represent relocation type %s"),
10538 bfd_get_reloc_code_name (code
));
10539 /* Set howto to a garbage value so that we can keep going. */
10540 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10541 gas_assert (rel
->howto
!= NULL
);
10547 #include "tc-i386-intel.c"
10550 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10552 int saved_naked_reg
;
10553 char saved_register_dot
;
10555 saved_naked_reg
= allow_naked_reg
;
10556 allow_naked_reg
= 1;
10557 saved_register_dot
= register_chars
['.'];
10558 register_chars
['.'] = '.';
10559 allow_pseudo_reg
= 1;
10560 expression_and_evaluate (exp
);
10561 allow_pseudo_reg
= 0;
10562 register_chars
['.'] = saved_register_dot
;
10563 allow_naked_reg
= saved_naked_reg
;
10565 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10567 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10569 exp
->X_op
= O_constant
;
10570 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10571 .dw2_regnum
[flag_code
>> 1];
10574 exp
->X_op
= O_illegal
;
10579 tc_x86_frame_initial_instructions (void)
10581 static unsigned int sp_regno
[2];
10583 if (!sp_regno
[flag_code
>> 1])
10585 char *saved_input
= input_line_pointer
;
10586 char sp
[][4] = {"esp", "rsp"};
10589 input_line_pointer
= sp
[flag_code
>> 1];
10590 tc_x86_parse_to_dw2regnum (&exp
);
10591 gas_assert (exp
.X_op
== O_constant
);
10592 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10593 input_line_pointer
= saved_input
;
10596 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10597 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10601 x86_dwarf2_addr_size (void)
10603 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10604 if (x86_elf_abi
== X86_64_X32_ABI
)
10607 return bfd_arch_bits_per_address (stdoutput
) / 8;
10611 i386_elf_section_type (const char *str
, size_t len
)
10613 if (flag_code
== CODE_64BIT
10614 && len
== sizeof ("unwind") - 1
10615 && strncmp (str
, "unwind", 6) == 0)
10616 return SHT_X86_64_UNWIND
;
10623 i386_solaris_fix_up_eh_frame (segT sec
)
10625 if (flag_code
== CODE_64BIT
)
10626 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10632 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10636 exp
.X_op
= O_secrel
;
10637 exp
.X_add_symbol
= symbol
;
10638 exp
.X_add_number
= 0;
10639 emit_expr (&exp
, size
);
10643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10644 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10647 x86_64_section_letter (int letter
, char **ptr_msg
)
10649 if (flag_code
== CODE_64BIT
)
10652 return SHF_X86_64_LARGE
;
10654 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10657 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10662 x86_64_section_word (char *str
, size_t len
)
10664 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10665 return SHF_X86_64_LARGE
;
10671 handle_large_common (int small ATTRIBUTE_UNUSED
)
10673 if (flag_code
!= CODE_64BIT
)
10675 s_comm_internal (0, elf_common_parse
);
10676 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10680 static segT lbss_section
;
10681 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10682 asection
*saved_bss_section
= bss_section
;
10684 if (lbss_section
== NULL
)
10686 flagword applicable
;
10687 segT seg
= now_seg
;
10688 subsegT subseg
= now_subseg
;
10690 /* The .lbss section is for local .largecomm symbols. */
10691 lbss_section
= subseg_new (".lbss", 0);
10692 applicable
= bfd_applicable_section_flags (stdoutput
);
10693 bfd_set_section_flags (stdoutput
, lbss_section
,
10694 applicable
& SEC_ALLOC
);
10695 seg_info (lbss_section
)->bss
= 1;
10697 subseg_set (seg
, subseg
);
10700 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10701 bss_section
= lbss_section
;
10703 s_comm_internal (0, elf_common_parse
);
10705 elf_com_section_ptr
= saved_com_section_ptr
;
10706 bss_section
= saved_bss_section
;
10709 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */