1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c
);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry
*parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry
*build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS
*, offsetT
);
95 static void output_disp (fragS
*, offsetT
);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
103 static const char *default_arch
= DEFAULT_ARCH
;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry
*regs
;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands
;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types
[MAX_OPERANDS
];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op
[MAX_OPERANDS
];
140 /* Flags for operands. */
141 unsigned int flags
[MAX_OPERANDS
];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry
*base_reg
;
150 const reg_entry
*index_reg
;
151 unsigned int log2_scale_factor
;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry
*seg
[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes
;
160 unsigned char prefix
[MAX_PREFIXES
];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn
;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars
[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars
= "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars
= "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "#/";
212 const char line_separator_chars
[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS
[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS
[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars
[256];
225 static char register_chars
[256];
226 static char operand_chars
[256];
227 static char identifier_chars
[256];
228 static char digit_chars
[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack
[32];
246 static char *save_stack_p
;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates
*current_templates
;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
260 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
262 /* Current operand we are working on. */
263 static int this_operand
;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code
;
275 static unsigned int object_64bit
;
276 static int use_rela_relocations
= 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names
[] =
286 /* 1 for intel syntax,
288 static int intel_syntax
= 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg
= 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix
= "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size
= '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code
= 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings
= 0;
308 static const char *cpu_arch_name
= NULL
;
309 static const char *cpu_sub_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set
= 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags
= 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags
= 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion
= 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS
*GOT_symbol
;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column
;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment
;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table
[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch
[] =
423 {"generic32", PROCESSOR_GENERIC32
,
424 Cpu186
|Cpu286
|Cpu386
},
425 {"generic64", PROCESSOR_GENERIC64
,
426 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
427 |CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"i8086", PROCESSOR_UNKNOWN
,
430 {"i186", PROCESSOR_UNKNOWN
,
432 {"i286", PROCESSOR_UNKNOWN
,
434 {"i386", PROCESSOR_I386
,
435 Cpu186
|Cpu286
|Cpu386
},
436 {"i486", PROCESSOR_I486
,
437 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
438 {"i586", PROCESSOR_PENTIUM
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
440 {"i686", PROCESSOR_PENTIUMPRO
,
441 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
442 {"pentium", PROCESSOR_PENTIUM
,
443 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
445 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
446 {"pentiumii", PROCESSOR_PENTIUMPRO
,
447 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
449 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
450 {"pentium4", PROCESSOR_PENTIUM4
,
451 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
452 |CpuMMX2
|CpuSSE
|CpuSSE2
},
453 {"prescott", PROCESSOR_NOCONA
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
455 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
456 {"nocona", PROCESSOR_NOCONA
,
457 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
458 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
459 {"yonah", PROCESSOR_CORE
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
461 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
462 {"core", PROCESSOR_CORE
,
463 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
464 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
465 {"merom", PROCESSOR_CORE2
,
466 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
467 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
468 {"core2", PROCESSOR_CORE2
,
469 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
470 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
472 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
473 {"k6_2", PROCESSOR_K6
,
474 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
475 {"athlon", PROCESSOR_ATHLON
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
477 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
478 {"sledgehammer", PROCESSOR_K8
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
480 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
481 {"opteron", PROCESSOR_K8
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
483 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
486 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
487 {"amdfam10", PROCESSOR_AMDFAM10
,
488 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
489 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN
,
493 {".sse", PROCESSOR_UNKNOWN
,
494 CpuMMX
|CpuMMX2
|CpuSSE
},
495 {".sse2", PROCESSOR_UNKNOWN
,
496 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
497 {".sse3", PROCESSOR_UNKNOWN
,
498 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
499 {".ssse3", PROCESSOR_UNKNOWN
,
500 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
501 {".sse4.1", PROCESSOR_UNKNOWN
,
502 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4_1
},
503 {".sse4.2", PROCESSOR_UNKNOWN
,
504 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
505 {".sse4", PROCESSOR_UNKNOWN
,
506 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
507 {".3dnow", PROCESSOR_UNKNOWN
,
509 {".3dnowa", PROCESSOR_UNKNOWN
,
510 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
511 {".padlock", PROCESSOR_UNKNOWN
,
513 {".pacifica", PROCESSOR_UNKNOWN
,
515 {".svme", PROCESSOR_UNKNOWN
,
517 {".sse4a", PROCESSOR_UNKNOWN
,
518 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
519 {".abm", PROCESSOR_UNKNOWN
,
523 const pseudo_typeS md_pseudo_table
[] =
525 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes
, 0},
528 {"align", s_align_ptwo
, 0},
530 {"arch", set_cpu_arch
, 0},
534 {"ffloat", float_cons
, 'f'},
535 {"dfloat", float_cons
, 'd'},
536 {"tfloat", float_cons
, 'x'},
538 {"slong", signed_cons
, 4},
539 {"noopt", s_ignore
, 0},
540 {"optim", s_ignore
, 0},
541 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
542 {"code16", set_code_flag
, CODE_16BIT
},
543 {"code32", set_code_flag
, CODE_32BIT
},
544 {"code64", set_code_flag
, CODE_64BIT
},
545 {"intel_syntax", set_intel_syntax
, 1},
546 {"att_syntax", set_intel_syntax
, 0},
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common
, 0},
550 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
551 {"loc", dwarf2_directive_loc
, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
555 {"secrel32", pe_directive_secrel
, 0},
560 /* For interface with expression (). */
561 extern char *input_line_pointer
;
563 /* Hash table for instruction mnemonic lookup. */
564 static struct hash_control
*op_hash
;
566 /* Hash table for register lookup. */
567 static struct hash_control
*reg_hash
;
570 i386_align_code (fragS
*fragP
, int count
)
572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
575 static const char f32_1
[] =
577 static const char f32_2
[] =
578 {0x66,0x90}; /* xchg %ax,%ax */
579 static const char f32_3
[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4
[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5
[] =
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6
[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7
[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8
[] =
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9
[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10
[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11
[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12
[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13
[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14
[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f16_3
[] =
612 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
613 static const char f16_4
[] =
614 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_5
[] =
617 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_6
[] =
619 {0x89,0xf6, /* mov %si,%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_7
[] =
622 {0x8d,0x74,0x00, /* lea 0(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_8
[] =
625 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char jump_31
[] =
628 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
632 static const char *const f32_patt
[] = {
633 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
634 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
636 static const char *const f16_patt
[] = {
637 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
640 static const char alt_3
[] =
642 /* nopl 0(%[re]ax) */
643 static const char alt_4
[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5
[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6
[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7
[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8
[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9
[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10
[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11
[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12
[] =
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13
[] =
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14
[] =
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15
[] =
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11
[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12
[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
720 static const char alt_short_13
[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
725 static const char alt_short_14
[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15
[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt
[] = {
734 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
735 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
736 alt_short_14
, alt_short_15
738 static const char *const alt_long_patt
[] = {
739 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
740 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
741 alt_long_14
, alt_long_15
744 /* Only align for at least a positive non-zero boundary. */
745 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
748 /* We need to decide which NOP sequence to use for 32bit and
749 64bit. When -mtune= is used:
751 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
752 PROCESSOR_GENERIC32, f32_patt will be used.
753 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
754 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
755 alt_long_patt will be used.
756 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
757 PROCESSOR_AMDFAM10, alt_short_patt will be used.
759 When -mtune= isn't used, alt_long_patt will be used if
760 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
763 When -march= or .arch is used, we can't use anything beyond
764 cpu_arch_isa_flags. */
766 if (flag_code
== CODE_16BIT
)
770 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
772 /* Adjust jump offset. */
773 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
776 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
777 f16_patt
[count
- 1], count
);
781 const char *const *patt
= NULL
;
783 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
785 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
786 switch (cpu_arch_tune
)
788 case PROCESSOR_UNKNOWN
:
789 /* We use cpu_arch_isa_flags to check if we SHOULD
790 optimize for Cpu686. */
791 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
792 patt
= alt_long_patt
;
796 case PROCESSOR_PENTIUMPRO
:
797 case PROCESSOR_PENTIUM4
:
798 case PROCESSOR_NOCONA
:
800 case PROCESSOR_CORE2
:
801 case PROCESSOR_GENERIC64
:
802 patt
= alt_long_patt
;
805 case PROCESSOR_ATHLON
:
807 case PROCESSOR_AMDFAM10
:
808 patt
= alt_short_patt
;
812 case PROCESSOR_PENTIUM
:
813 case PROCESSOR_GENERIC32
:
820 switch (cpu_arch_tune
)
822 case PROCESSOR_UNKNOWN
:
823 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
824 PROCESSOR_UNKNOWN. */
830 case PROCESSOR_PENTIUM
:
832 case PROCESSOR_ATHLON
:
834 case PROCESSOR_AMDFAM10
:
835 case PROCESSOR_GENERIC32
:
836 /* We use cpu_arch_isa_flags to check if we CAN optimize
838 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
839 patt
= alt_short_patt
;
843 case PROCESSOR_PENTIUMPRO
:
844 case PROCESSOR_PENTIUM4
:
845 case PROCESSOR_NOCONA
:
847 case PROCESSOR_CORE2
:
848 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
849 patt
= alt_long_patt
;
853 case PROCESSOR_GENERIC64
:
854 patt
= alt_long_patt
;
859 if (patt
== f32_patt
)
861 /* If the padding is less than 15 bytes, we use the normal
862 ones. Otherwise, we use a jump instruction and adjust
865 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
866 patt
[count
- 1], count
);
869 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
871 /* Adjust jump offset. */
872 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
877 /* Maximum length of an instruction is 15 byte. If the
878 padding is greater than 15 bytes and we don't use jump,
879 we have to break it into smaller pieces. */
884 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
889 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
890 patt
[padding
- 1], padding
);
893 fragP
->fr_var
= count
;
896 static INLINE
unsigned int
897 mode_from_disp_size (unsigned int t
)
899 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
903 fits_in_signed_byte (offsetT num
)
905 return (num
>= -128) && (num
<= 127);
909 fits_in_unsigned_byte (offsetT num
)
911 return (num
& 0xff) == num
;
915 fits_in_unsigned_word (offsetT num
)
917 return (num
& 0xffff) == num
;
921 fits_in_signed_word (offsetT num
)
923 return (-32768 <= num
) && (num
<= 32767);
927 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
932 return (!(((offsetT
) -1 << 31) & num
)
933 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
935 } /* fits_in_signed_long() */
938 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
943 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
945 } /* fits_in_unsigned_long() */
948 smallest_imm_type (offsetT num
)
950 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
958 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
960 return (fits_in_signed_byte (num
)
961 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
962 : fits_in_unsigned_byte (num
)
963 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
964 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
965 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
966 : fits_in_signed_long (num
)
967 ? (Imm32
| Imm32S
| Imm64
)
968 : fits_in_unsigned_long (num
)
974 offset_in_range (offsetT val
, int size
)
980 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
981 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
982 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
984 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
989 /* If BFD64, sign extend val. */
990 if (!use_rela_relocations
)
991 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
992 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
994 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
996 char buf1
[40], buf2
[40];
998 sprint_value (buf1
, val
);
999 sprint_value (buf2
, val
& mask
);
1000 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1005 /* Returns 0 if attempting to add a prefix where one from the same
1006 class already exists, 1 if non rep/repne added, 2 if rep/repne
1009 add_prefix (unsigned int prefix
)
1014 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1015 && flag_code
== CODE_64BIT
)
1017 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1018 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1019 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1030 case CS_PREFIX_OPCODE
:
1031 case DS_PREFIX_OPCODE
:
1032 case ES_PREFIX_OPCODE
:
1033 case FS_PREFIX_OPCODE
:
1034 case GS_PREFIX_OPCODE
:
1035 case SS_PREFIX_OPCODE
:
1039 case REPNE_PREFIX_OPCODE
:
1040 case REPE_PREFIX_OPCODE
:
1043 case LOCK_PREFIX_OPCODE
:
1051 case ADDR_PREFIX_OPCODE
:
1055 case DATA_PREFIX_OPCODE
:
1059 if (i
.prefix
[q
] != 0)
1067 i
.prefix
[q
] |= prefix
;
1070 as_bad (_("same type of prefix used twice"));
1076 set_code_flag (int value
)
1079 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1080 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1081 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1083 as_bad (_("64bit mode not supported on this CPU."));
1085 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1087 as_bad (_("32bit mode not supported on this CPU."));
1089 stackop_size
= '\0';
1093 set_16bit_gcc_code_flag (int new_code_flag
)
1095 flag_code
= new_code_flag
;
1096 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1097 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1098 stackop_size
= LONG_MNEM_SUFFIX
;
1102 set_intel_syntax (int syntax_flag
)
1104 /* Find out if register prefixing is specified. */
1105 int ask_naked_reg
= 0;
1108 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1110 char *string
= input_line_pointer
;
1111 int e
= get_symbol_end ();
1113 if (strcmp (string
, "prefix") == 0)
1115 else if (strcmp (string
, "noprefix") == 0)
1118 as_bad (_("bad argument to syntax directive."));
1119 *input_line_pointer
= e
;
1121 demand_empty_rest_of_line ();
1123 intel_syntax
= syntax_flag
;
1125 if (ask_naked_reg
== 0)
1126 allow_naked_reg
= (intel_syntax
1127 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1129 allow_naked_reg
= (ask_naked_reg
< 0);
1131 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1132 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1133 register_prefix
= allow_naked_reg
? "" : "%";
1137 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1141 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1143 char *string
= input_line_pointer
;
1144 int e
= get_symbol_end ();
1147 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1149 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1153 cpu_arch_name
= cpu_arch
[i
].name
;
1154 cpu_sub_arch_name
= NULL
;
1155 cpu_arch_flags
= (cpu_arch
[i
].flags
1156 | (flag_code
== CODE_64BIT
1157 ? Cpu64
: CpuNo64
));
1158 cpu_arch_isa
= cpu_arch
[i
].type
;
1159 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1160 if (!cpu_arch_tune_set
)
1162 cpu_arch_tune
= cpu_arch_isa
;
1163 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1167 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1169 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1170 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1172 *input_line_pointer
= e
;
1173 demand_empty_rest_of_line ();
1177 if (i
>= ARRAY_SIZE (cpu_arch
))
1178 as_bad (_("no such architecture: `%s'"), string
);
1180 *input_line_pointer
= e
;
1183 as_bad (_("missing cpu architecture"));
1185 no_cond_jump_promotion
= 0;
1186 if (*input_line_pointer
== ','
1187 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1189 char *string
= ++input_line_pointer
;
1190 int e
= get_symbol_end ();
1192 if (strcmp (string
, "nojumps") == 0)
1193 no_cond_jump_promotion
= 1;
1194 else if (strcmp (string
, "jumps") == 0)
1197 as_bad (_("no such architecture modifier: `%s'"), string
);
1199 *input_line_pointer
= e
;
1202 demand_empty_rest_of_line ();
1208 if (!strcmp (default_arch
, "x86_64"))
1209 return bfd_mach_x86_64
;
1210 else if (!strcmp (default_arch
, "i386"))
1211 return bfd_mach_i386_i386
;
1213 as_fatal (_("Unknown architecture"));
1219 const char *hash_err
;
1221 /* Initialize op_hash hash table. */
1222 op_hash
= hash_new ();
1225 const template *optab
;
1226 templates
*core_optab
;
1228 /* Setup for loop. */
1230 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1231 core_optab
->start
= optab
;
1236 if (optab
->name
== NULL
1237 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1239 /* different name --> ship out current template list;
1240 add to hash table; & begin anew. */
1241 core_optab
->end
= optab
;
1242 hash_err
= hash_insert (op_hash
,
1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1251 if (optab
->name
== NULL
)
1253 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1254 core_optab
->start
= optab
;
1259 /* Initialize reg_hash hash table. */
1260 reg_hash
= hash_new ();
1262 const reg_entry
*regtab
;
1263 unsigned int regtab_size
= i386_regtab_size
;
1265 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1267 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1269 as_fatal (_("Internal Error: Can't hash %s: %s"),
1275 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1280 for (c
= 0; c
< 256; c
++)
1285 mnemonic_chars
[c
] = c
;
1286 register_chars
[c
] = c
;
1287 operand_chars
[c
] = c
;
1289 else if (ISLOWER (c
))
1291 mnemonic_chars
[c
] = c
;
1292 register_chars
[c
] = c
;
1293 operand_chars
[c
] = c
;
1295 else if (ISUPPER (c
))
1297 mnemonic_chars
[c
] = TOLOWER (c
);
1298 register_chars
[c
] = mnemonic_chars
[c
];
1299 operand_chars
[c
] = c
;
1302 if (ISALPHA (c
) || ISDIGIT (c
))
1303 identifier_chars
[c
] = c
;
1306 identifier_chars
[c
] = c
;
1307 operand_chars
[c
] = c
;
1312 identifier_chars
['@'] = '@';
1315 identifier_chars
['?'] = '?';
1316 operand_chars
['?'] = '?';
1318 digit_chars
['-'] = '-';
1319 mnemonic_chars
['-'] = '-';
1320 mnemonic_chars
['.'] = '.';
1321 identifier_chars
['_'] = '_';
1322 identifier_chars
['.'] = '.';
1324 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1325 operand_chars
[(unsigned char) *p
] = *p
;
1328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1331 record_alignment (text_section
, 2);
1332 record_alignment (data_section
, 2);
1333 record_alignment (bss_section
, 2);
1337 if (flag_code
== CODE_64BIT
)
1339 x86_dwarf2_return_column
= 16;
1340 x86_cie_data_alignment
= -8;
1344 x86_dwarf2_return_column
= 8;
1345 x86_cie_data_alignment
= -4;
1350 i386_print_statistics (FILE *file
)
1352 hash_print_statistics (file
, "i386 opcode", op_hash
);
1353 hash_print_statistics (file
, "i386 register", reg_hash
);
1358 /* Debugging routines for md_assemble. */
1359 static void pte (template *);
1360 static void pt (unsigned int);
1361 static void pe (expressionS
*);
1362 static void ps (symbolS
*);
1365 pi (char *line
, i386_insn
*x
)
1369 fprintf (stdout
, "%s: template ", line
);
1371 fprintf (stdout
, " address: base %s index %s scale %x\n",
1372 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1373 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1374 x
->log2_scale_factor
);
1375 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1376 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1377 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1378 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1379 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1380 (x
->rex
& REX_W
) != 0,
1381 (x
->rex
& REX_R
) != 0,
1382 (x
->rex
& REX_X
) != 0,
1383 (x
->rex
& REX_B
) != 0);
1384 for (i
= 0; i
< x
->operands
; i
++)
1386 fprintf (stdout
, " #%d: ", i
+ 1);
1388 fprintf (stdout
, "\n");
1390 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1391 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1392 if (x
->types
[i
] & Imm
)
1394 if (x
->types
[i
] & Disp
)
1395 pe (x
->op
[i
].disps
);
1403 fprintf (stdout
, " %d operands ", t
->operands
);
1404 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1405 if (t
->extension_opcode
!= None
)
1406 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1407 if (t
->opcode_modifier
& D
)
1408 fprintf (stdout
, "D");
1409 if (t
->opcode_modifier
& W
)
1410 fprintf (stdout
, "W");
1411 fprintf (stdout
, "\n");
1412 for (i
= 0; i
< t
->operands
; i
++)
1414 fprintf (stdout
, " #%d type ", i
+ 1);
1415 pt (t
->operand_types
[i
]);
1416 fprintf (stdout
, "\n");
1423 fprintf (stdout
, " operation %d\n", e
->X_op
);
1424 fprintf (stdout
, " add_number %ld (%lx)\n",
1425 (long) e
->X_add_number
, (long) e
->X_add_number
);
1426 if (e
->X_add_symbol
)
1428 fprintf (stdout
, " add_symbol ");
1429 ps (e
->X_add_symbol
);
1430 fprintf (stdout
, "\n");
1434 fprintf (stdout
, " op_symbol ");
1435 ps (e
->X_op_symbol
);
1436 fprintf (stdout
, "\n");
1443 fprintf (stdout
, "%s type %s%s",
1445 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1446 segment_name (S_GET_SEGMENT (s
)));
1449 static struct type_name
1454 const type_names
[] =
1467 { BaseIndex
, "BaseIndex" },
1471 { Disp32S
, "d32s" },
1473 { InOutPortReg
, "InOutPortReg" },
1474 { ShiftCount
, "ShiftCount" },
1475 { Control
, "control reg" },
1476 { Test
, "test reg" },
1477 { Debug
, "debug reg" },
1478 { FloatReg
, "FReg" },
1479 { FloatAcc
, "FAcc" },
1483 { JumpAbsolute
, "Jump Absolute" },
1494 const struct type_name
*ty
;
1496 for (ty
= type_names
; ty
->mask
; ty
++)
1498 fprintf (stdout
, "%s, ", ty
->tname
);
1502 #endif /* DEBUG386 */
1504 static bfd_reloc_code_real_type
1505 reloc (unsigned int size
,
1508 bfd_reloc_code_real_type other
)
1510 if (other
!= NO_RELOC
)
1512 reloc_howto_type
*reloc
;
1517 case BFD_RELOC_X86_64_GOT32
:
1518 return BFD_RELOC_X86_64_GOT64
;
1520 case BFD_RELOC_X86_64_PLTOFF64
:
1521 return BFD_RELOC_X86_64_PLTOFF64
;
1523 case BFD_RELOC_X86_64_GOTPC32
:
1524 other
= BFD_RELOC_X86_64_GOTPC64
;
1526 case BFD_RELOC_X86_64_GOTPCREL
:
1527 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1529 case BFD_RELOC_X86_64_TPOFF32
:
1530 other
= BFD_RELOC_X86_64_TPOFF64
;
1532 case BFD_RELOC_X86_64_DTPOFF32
:
1533 other
= BFD_RELOC_X86_64_DTPOFF64
;
1539 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1540 if (size
== 4 && flag_code
!= CODE_64BIT
)
1543 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1545 as_bad (_("unknown relocation (%u)"), other
);
1546 else if (size
!= bfd_get_reloc_size (reloc
))
1547 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1548 bfd_get_reloc_size (reloc
),
1550 else if (pcrel
&& !reloc
->pc_relative
)
1551 as_bad (_("non-pc-relative relocation for pc-relative field"));
1552 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1554 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1556 as_bad (_("relocated field and relocation type differ in signedness"));
1565 as_bad (_("there are no unsigned pc-relative relocations"));
1568 case 1: return BFD_RELOC_8_PCREL
;
1569 case 2: return BFD_RELOC_16_PCREL
;
1570 case 4: return BFD_RELOC_32_PCREL
;
1571 case 8: return BFD_RELOC_64_PCREL
;
1573 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1580 case 4: return BFD_RELOC_X86_64_32S
;
1585 case 1: return BFD_RELOC_8
;
1586 case 2: return BFD_RELOC_16
;
1587 case 4: return BFD_RELOC_32
;
1588 case 8: return BFD_RELOC_64
;
1590 as_bad (_("cannot do %s %u byte relocation"),
1591 sign
> 0 ? "signed" : "unsigned", size
);
1595 return BFD_RELOC_NONE
;
1598 /* Here we decide which fixups can be adjusted to make them relative to
1599 the beginning of the section instead of the symbol. Basically we need
1600 to make sure that the dynamic relocations are done correctly, so in
1601 some cases we force the original symbol to be used. */
1604 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1606 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1610 /* Don't adjust pc-relative references to merge sections in 64-bit
1612 if (use_rela_relocations
1613 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1617 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1618 and changed later by validate_fix. */
1619 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1620 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1623 /* adjust_reloc_syms doesn't know about the GOT. */
1624 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1625 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1626 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1627 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1628 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1629 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1630 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1631 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1632 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1633 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1634 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1635 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1636 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1637 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1638 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1639 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1640 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1641 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1642 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1643 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1644 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1645 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1646 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1647 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1648 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1649 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1650 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1651 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1658 intel_float_operand (const char *mnemonic
)
1660 /* Note that the value returned is meaningful only for opcodes with (memory)
1661 operands, hence the code here is free to improperly handle opcodes that
1662 have no operands (for better performance and smaller code). */
1664 if (mnemonic
[0] != 'f')
1665 return 0; /* non-math */
1667 switch (mnemonic
[1])
1669 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1670 the fs segment override prefix not currently handled because no
1671 call path can make opcodes without operands get here */
1673 return 2 /* integer op */;
1675 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1676 return 3; /* fldcw/fldenv */
1679 if (mnemonic
[2] != 'o' /* fnop */)
1680 return 3; /* non-waiting control op */
1683 if (mnemonic
[2] == 's')
1684 return 3; /* frstor/frstpm */
1687 if (mnemonic
[2] == 'a')
1688 return 3; /* fsave */
1689 if (mnemonic
[2] == 't')
1691 switch (mnemonic
[3])
1693 case 'c': /* fstcw */
1694 case 'd': /* fstdw */
1695 case 'e': /* fstenv */
1696 case 's': /* fsts[gw] */
1702 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1703 return 0; /* fxsave/fxrstor are not really math ops */
1710 /* This is the guts of the machine-dependent assembler. LINE points to a
1711 machine dependent instruction. This function is supposed to emit
1712 the frags/bytes it assembles to. */
1719 char mnemonic
[MAX_MNEM_SIZE
];
1721 /* Initialize globals. */
1722 memset (&i
, '\0', sizeof (i
));
1723 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1724 i
.reloc
[j
] = NO_RELOC
;
1725 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1726 memset (im_expressions
, '\0', sizeof (im_expressions
));
1727 save_stack_p
= save_stack
;
1729 /* First parse an instruction mnemonic & call i386_operand for the operands.
1730 We assume that the scrubber has arranged it so that line[0] is the valid
1731 start of a (possibly prefixed) mnemonic. */
1733 line
= parse_insn (line
, mnemonic
);
1737 line
= parse_operands (line
, mnemonic
);
1741 /* The order of the immediates should be reversed
1742 for 2 immediates extrq and insertq instructions */
1743 if ((i
.imm_operands
== 2)
1744 && ((strcmp (mnemonic
, "extrq") == 0)
1745 || (strcmp (mnemonic
, "insertq") == 0)))
1747 swap_2_operands (0, 1);
1748 /* "extrq" and insertq" are the only two instructions whose operands
1749 have to be reversed even though they have two immediate operands.
1755 /* Now we've parsed the mnemonic into a set of templates, and have the
1756 operands at hand. */
1758 /* All intel opcodes have reversed operands except for "bound" and
1759 "enter". We also don't reverse intersegment "jmp" and "call"
1760 instructions with 2 immediate operands so that the immediate segment
1761 precedes the offset, as it does when in AT&T mode. */
1764 && (strcmp (mnemonic
, "bound") != 0)
1765 && (strcmp (mnemonic
, "invlpga") != 0)
1766 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1772 /* Don't optimize displacement for movabs since it only takes 64bit
1775 && (flag_code
!= CODE_64BIT
1776 || strcmp (mnemonic
, "movabs") != 0))
1779 /* Next, we find a template that matches the given insn,
1780 making sure the overlap of the given operands types is consistent
1781 with the template operand types. */
1783 if (!match_template ())
1788 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1790 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1791 i
.tm
.base_opcode
^= Opcode_FloatR
;
1793 /* Zap movzx and movsx suffix. The suffix may have been set from
1794 "word ptr" or "byte ptr" on the source operand, but we'll use
1795 the suffix later to choose the destination register. */
1796 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1798 if (i
.reg_operands
< 2
1800 && (~i
.tm
.opcode_modifier
1807 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1813 if (i
.tm
.opcode_modifier
& FWait
)
1814 if (!add_prefix (FWAIT_OPCODE
))
1817 /* Check string instruction segment overrides. */
1818 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1820 if (!check_string ())
1824 if (!process_suffix ())
1827 /* Make still unresolved immediate matches conform to size of immediate
1828 given in i.suffix. */
1829 if (!finalize_imm ())
1832 if (i
.types
[0] & Imm1
)
1833 i
.imm_operands
= 0; /* kludge for shift insns. */
1834 if (i
.types
[0] & ImplicitRegister
)
1836 if (i
.types
[1] & ImplicitRegister
)
1838 if (i
.types
[2] & ImplicitRegister
)
1841 if (i
.tm
.opcode_modifier
& ImmExt
)
1845 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1847 /* Streaming SIMD extensions 3 Instructions have the fixed
1848 operands with an opcode suffix which is coded in the same
1849 place as an 8-bit immediate field would be. Here we check
1850 those operands and remove them afterwards. */
1853 for (x
= 0; x
< i
.operands
; x
++)
1854 if (i
.op
[x
].regs
->reg_num
!= x
)
1855 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1857 i
.op
[x
].regs
->reg_name
,
1863 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1864 opcode suffix which is coded in the same place as an 8-bit
1865 immediate field would be. Here we fake an 8-bit immediate
1866 operand from the opcode suffix stored in tm.extension_opcode. */
1868 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1870 exp
= &im_expressions
[i
.imm_operands
++];
1871 i
.op
[i
.operands
].imms
= exp
;
1872 i
.types
[i
.operands
++] = Imm8
;
1873 exp
->X_op
= O_constant
;
1874 exp
->X_add_number
= i
.tm
.extension_opcode
;
1875 i
.tm
.extension_opcode
= None
;
1878 /* For insns with operands there are more diddles to do to the opcode. */
1881 if (!process_operands ())
1884 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1886 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1887 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1890 /* Handle conversion of 'int $3' --> special int3 insn. */
1891 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1893 i
.tm
.base_opcode
= INT3_OPCODE
;
1897 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1898 && i
.op
[0].disps
->X_op
== O_constant
)
1900 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1901 the absolute address given by the constant. Since ix86 jumps and
1902 calls are pc relative, we need to generate a reloc. */
1903 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1904 i
.op
[0].disps
->X_op
= O_symbol
;
1907 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1910 /* For 8 bit registers we need an empty rex prefix. Also if the
1911 instruction already has a prefix, we need to convert old
1912 registers to new ones. */
1914 if (((i
.types
[0] & Reg8
) != 0
1915 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1916 || ((i
.types
[1] & Reg8
) != 0
1917 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1918 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1923 i
.rex
|= REX_OPCODE
;
1924 for (x
= 0; x
< 2; x
++)
1926 /* Look for 8 bit operand that uses old registers. */
1927 if ((i
.types
[x
] & Reg8
) != 0
1928 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1930 /* In case it is "hi" register, give up. */
1931 if (i
.op
[x
].regs
->reg_num
> 3)
1932 as_bad (_("can't encode register '%s%s' in an "
1933 "instruction requiring REX prefix."),
1934 register_prefix
, i
.op
[x
].regs
->reg_name
);
1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1940 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1946 add_prefix (REX_OPCODE
| i
.rex
);
1948 /* We are ready to output the insn. */
1953 parse_insn (char *line
, char *mnemonic
)
1956 char *token_start
= l
;
1961 /* Non-zero if we found a prefix only acceptable with string insns. */
1962 const char *expecting_string_instruction
= NULL
;
1967 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1970 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1972 as_bad (_("no such instruction: `%s'"), token_start
);
1977 if (!is_space_char (*l
)
1978 && *l
!= END_OF_INSN
1980 || (*l
!= PREFIX_SEPARATOR
1983 as_bad (_("invalid character %s in mnemonic"),
1984 output_invalid (*l
));
1987 if (token_start
== l
)
1989 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1990 as_bad (_("expecting prefix; got nothing"));
1992 as_bad (_("expecting mnemonic; got nothing"));
1996 /* Look up instruction (or prefix) via hash table. */
1997 current_templates
= hash_find (op_hash
, mnemonic
);
1999 if (*l
!= END_OF_INSN
2000 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2001 && current_templates
2002 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
2004 if (current_templates
->start
->cpu_flags
2005 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
2007 as_bad ((flag_code
!= CODE_64BIT
2008 ? _("`%s' is only supported in 64-bit mode")
2009 : _("`%s' is not supported in 64-bit mode")),
2010 current_templates
->start
->name
);
2013 /* If we are in 16-bit mode, do not allow addr16 or data16.
2014 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2015 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
2016 && flag_code
!= CODE_64BIT
2017 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
2018 ^ (flag_code
== CODE_16BIT
)))
2020 as_bad (_("redundant %s prefix"),
2021 current_templates
->start
->name
);
2024 /* Add prefix, checking for repeated prefixes. */
2025 switch (add_prefix (current_templates
->start
->base_opcode
))
2030 expecting_string_instruction
= current_templates
->start
->name
;
2033 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2040 if (!current_templates
)
2042 /* See if we can get a match by trimming off a suffix. */
2045 case WORD_MNEM_SUFFIX
:
2046 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2047 i
.suffix
= SHORT_MNEM_SUFFIX
;
2049 case BYTE_MNEM_SUFFIX
:
2050 case QWORD_MNEM_SUFFIX
:
2051 i
.suffix
= mnem_p
[-1];
2053 current_templates
= hash_find (op_hash
, mnemonic
);
2055 case SHORT_MNEM_SUFFIX
:
2056 case LONG_MNEM_SUFFIX
:
2059 i
.suffix
= mnem_p
[-1];
2061 current_templates
= hash_find (op_hash
, mnemonic
);
2069 if (intel_float_operand (mnemonic
) == 1)
2070 i
.suffix
= SHORT_MNEM_SUFFIX
;
2072 i
.suffix
= LONG_MNEM_SUFFIX
;
2074 current_templates
= hash_find (op_hash
, mnemonic
);
2078 if (!current_templates
)
2080 as_bad (_("no such instruction: `%s'"), token_start
);
2085 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2087 /* Check for a branch hint. We allow ",pt" and ",pn" for
2088 predict taken and predict not taken respectively.
2089 I'm not sure that branch hints actually do anything on loop
2090 and jcxz insns (JumpByte) for current Pentium4 chips. They
2091 may work in the future and it doesn't hurt to accept them
2093 if (l
[0] == ',' && l
[1] == 'p')
2097 if (!add_prefix (DS_PREFIX_OPCODE
))
2101 else if (l
[2] == 'n')
2103 if (!add_prefix (CS_PREFIX_OPCODE
))
2109 /* Any other comma loses. */
2112 as_bad (_("invalid character %s in mnemonic"),
2113 output_invalid (*l
));
2117 /* Check if instruction is supported on specified architecture. */
2119 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2121 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2122 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2124 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2127 if (!(supported
& 2))
2129 as_bad (flag_code
== CODE_64BIT
2130 ? _("`%s' is not supported in 64-bit mode")
2131 : _("`%s' is only supported in 64-bit mode"),
2132 current_templates
->start
->name
);
2135 if (!(supported
& 1))
2137 as_warn (_("`%s' is not supported on `%s%s'"),
2138 current_templates
->start
->name
,
2140 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2142 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2144 as_warn (_("use .code16 to ensure correct addressing mode"));
2147 /* Check for rep/repne without a string instruction. */
2148 if (expecting_string_instruction
)
2150 static templates override
;
2152 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2153 if (t
->opcode_modifier
& IsString
)
2155 if (t
>= current_templates
->end
)
2157 as_bad (_("expecting string instruction after `%s'"),
2158 expecting_string_instruction
);
2161 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2162 if (!(t
->opcode_modifier
& IsString
))
2165 current_templates
= &override
;
2172 parse_operands (char *l
, const char *mnemonic
)
2176 /* 1 if operand is pending after ','. */
2177 unsigned int expecting_operand
= 0;
2179 /* Non-zero if operand parens not balanced. */
2180 unsigned int paren_not_balanced
;
2182 while (*l
!= END_OF_INSN
)
2184 /* Skip optional white space before operand. */
2185 if (is_space_char (*l
))
2187 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2189 as_bad (_("invalid character %s before operand %d"),
2190 output_invalid (*l
),
2194 token_start
= l
; /* after white space */
2195 paren_not_balanced
= 0;
2196 while (paren_not_balanced
|| *l
!= ',')
2198 if (*l
== END_OF_INSN
)
2200 if (paren_not_balanced
)
2203 as_bad (_("unbalanced parenthesis in operand %d."),
2206 as_bad (_("unbalanced brackets in operand %d."),
2211 break; /* we are done */
2213 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2215 as_bad (_("invalid character %s in operand %d"),
2216 output_invalid (*l
),
2223 ++paren_not_balanced
;
2225 --paren_not_balanced
;
2230 ++paren_not_balanced
;
2232 --paren_not_balanced
;
2236 if (l
!= token_start
)
2237 { /* Yes, we've read in another operand. */
2238 unsigned int operand_ok
;
2239 this_operand
= i
.operands
++;
2240 if (i
.operands
> MAX_OPERANDS
)
2242 as_bad (_("spurious operands; (%d operands/instruction max)"),
2246 /* Now parse operand adding info to 'i' as we go along. */
2247 END_STRING_AND_SAVE (l
);
2251 i386_intel_operand (token_start
,
2252 intel_float_operand (mnemonic
));
2254 operand_ok
= i386_operand (token_start
);
2256 RESTORE_END_STRING (l
);
2262 if (expecting_operand
)
2264 expecting_operand_after_comma
:
2265 as_bad (_("expecting operand after ','; got nothing"));
2270 as_bad (_("expecting operand before ','; got nothing"));
2275 /* Now *l must be either ',' or END_OF_INSN. */
2278 if (*++l
== END_OF_INSN
)
2280 /* Just skip it, if it's \n complain. */
2281 goto expecting_operand_after_comma
;
2283 expecting_operand
= 1;
2290 swap_2_operands (int xchg1
, int xchg2
)
2292 union i386_op temp_op
;
2293 unsigned int temp_type
;
2294 enum bfd_reloc_code_real temp_reloc
;
2296 temp_type
= i
.types
[xchg2
];
2297 i
.types
[xchg2
] = i
.types
[xchg1
];
2298 i
.types
[xchg1
] = temp_type
;
2299 temp_op
= i
.op
[xchg2
];
2300 i
.op
[xchg2
] = i
.op
[xchg1
];
2301 i
.op
[xchg1
] = temp_op
;
2302 temp_reloc
= i
.reloc
[xchg2
];
2303 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2304 i
.reloc
[xchg1
] = temp_reloc
;
2308 swap_operands (void)
2313 swap_2_operands (1, i
.operands
- 2);
2316 swap_2_operands (0, i
.operands
- 1);
2322 if (i
.mem_operands
== 2)
2324 const seg_entry
*temp_seg
;
2325 temp_seg
= i
.seg
[0];
2326 i
.seg
[0] = i
.seg
[1];
2327 i
.seg
[1] = temp_seg
;
2331 /* Try to ensure constant immediates are represented in the smallest
2336 char guess_suffix
= 0;
2340 guess_suffix
= i
.suffix
;
2341 else if (i
.reg_operands
)
2343 /* Figure out a suffix from the last register operand specified.
2344 We can't do this properly yet, ie. excluding InOutPortReg,
2345 but the following works for instructions with immediates.
2346 In any case, we can't set i.suffix yet. */
2347 for (op
= i
.operands
; --op
>= 0;)
2348 if (i
.types
[op
] & Reg
)
2350 if (i
.types
[op
] & Reg8
)
2351 guess_suffix
= BYTE_MNEM_SUFFIX
;
2352 else if (i
.types
[op
] & Reg16
)
2353 guess_suffix
= WORD_MNEM_SUFFIX
;
2354 else if (i
.types
[op
] & Reg32
)
2355 guess_suffix
= LONG_MNEM_SUFFIX
;
2356 else if (i
.types
[op
] & Reg64
)
2357 guess_suffix
= QWORD_MNEM_SUFFIX
;
2361 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2362 guess_suffix
= WORD_MNEM_SUFFIX
;
2364 for (op
= i
.operands
; --op
>= 0;)
2365 if (i
.types
[op
] & Imm
)
2367 switch (i
.op
[op
].imms
->X_op
)
2370 /* If a suffix is given, this operand may be shortened. */
2371 switch (guess_suffix
)
2373 case LONG_MNEM_SUFFIX
:
2374 i
.types
[op
] |= Imm32
| Imm64
;
2376 case WORD_MNEM_SUFFIX
:
2377 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2379 case BYTE_MNEM_SUFFIX
:
2380 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2384 /* If this operand is at most 16 bits, convert it
2385 to a signed 16 bit number before trying to see
2386 whether it will fit in an even smaller size.
2387 This allows a 16-bit operand such as $0xffe0 to
2388 be recognised as within Imm8S range. */
2389 if ((i
.types
[op
] & Imm16
)
2390 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2392 i
.op
[op
].imms
->X_add_number
=
2393 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2395 if ((i
.types
[op
] & Imm32
)
2396 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2399 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2400 ^ ((offsetT
) 1 << 31))
2401 - ((offsetT
) 1 << 31));
2403 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2405 /* We must avoid matching of Imm32 templates when 64bit
2406 only immediate is available. */
2407 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2408 i
.types
[op
] &= ~Imm32
;
2415 /* Symbols and expressions. */
2417 /* Convert symbolic operand to proper sizes for matching, but don't
2418 prevent matching a set of insns that only supports sizes other
2419 than those matching the insn suffix. */
2421 unsigned int mask
, allowed
= 0;
2424 for (t
= current_templates
->start
;
2425 t
< current_templates
->end
;
2427 allowed
|= t
->operand_types
[op
];
2428 switch (guess_suffix
)
2430 case QWORD_MNEM_SUFFIX
:
2431 mask
= Imm64
| Imm32S
;
2433 case LONG_MNEM_SUFFIX
:
2436 case WORD_MNEM_SUFFIX
:
2439 case BYTE_MNEM_SUFFIX
:
2447 i
.types
[op
] &= mask
;
2454 /* Try to use the smallest displacement type too. */
2456 optimize_disp (void)
2460 for (op
= i
.operands
; --op
>= 0;)
2461 if (i
.types
[op
] & Disp
)
2463 if (i
.op
[op
].disps
->X_op
== O_constant
)
2465 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2467 if ((i
.types
[op
] & Disp16
)
2468 && (disp
& ~(offsetT
) 0xffff) == 0)
2470 /* If this operand is at most 16 bits, convert
2471 to a signed 16 bit number and don't use 64bit
2473 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2474 i
.types
[op
] &= ~Disp64
;
2476 if ((i
.types
[op
] & Disp32
)
2477 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2479 /* If this operand is at most 32 bits, convert
2480 to a signed 32 bit number and don't use 64bit
2482 disp
&= (((offsetT
) 2 << 31) - 1);
2483 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2484 i
.types
[op
] &= ~Disp64
;
2486 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2488 i
.types
[op
] &= ~Disp
;
2492 else if (flag_code
== CODE_64BIT
)
2494 if (fits_in_signed_long (disp
))
2496 i
.types
[op
] &= ~Disp64
;
2497 i
.types
[op
] |= Disp32S
;
2499 if (fits_in_unsigned_long (disp
))
2500 i
.types
[op
] |= Disp32
;
2502 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2503 && fits_in_signed_byte (disp
))
2504 i
.types
[op
] |= Disp8
;
2506 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2507 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2509 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2510 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2511 i
.types
[op
] &= ~Disp
;
2514 /* We only support 64bit displacement on constants. */
2515 i
.types
[op
] &= ~Disp64
;
2520 match_template (void)
2522 /* Points to template once we've found it. */
2524 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2525 unsigned int found_reverse_match
;
2527 unsigned int operand_types
[MAX_OPERANDS
];
2528 int addr_prefix_disp
;
2531 #if MAX_OPERANDS != 4
2532 # error "MAX_OPERANDS must be 4."
2535 #define MATCH(overlap, given, template) \
2536 ((overlap & ~JumpAbsolute) \
2537 && (((given) & (BaseIndex | JumpAbsolute)) \
2538 == ((overlap) & (BaseIndex | JumpAbsolute))))
2540 /* If given types r0 and r1 are registers they must be of the same type
2541 unless the expected operand type register overlap is null.
2542 Note that Acc in a template matches every size of reg. */
2543 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2544 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2545 || ((g0) & Reg) == ((g1) & Reg) \
2546 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2552 found_reverse_match
= 0;
2553 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2554 operand_types
[j
] = 0;
2555 addr_prefix_disp
= -1;
2556 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2558 : (i
.suffix
== WORD_MNEM_SUFFIX
2560 : (i
.suffix
== SHORT_MNEM_SUFFIX
2562 : (i
.suffix
== LONG_MNEM_SUFFIX
2564 : (i
.suffix
== QWORD_MNEM_SUFFIX
2566 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2567 ? No_xSuf
: 0))))));
2569 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2571 addr_prefix_disp
= -1;
2573 /* Must have right number of operands. */
2574 if (i
.operands
!= t
->operands
)
2577 /* Check the suffix, except for some instructions in intel mode. */
2578 if ((t
->opcode_modifier
& suffix_check
)
2580 && (t
->opcode_modifier
& IgnoreSize
)))
2583 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2584 operand_types
[j
] = t
->operand_types
[j
];
2586 /* In general, don't allow 64-bit operands in 32-bit mode. */
2587 if (i
.suffix
== QWORD_MNEM_SUFFIX
2588 && flag_code
!= CODE_64BIT
2590 ? (!(t
->opcode_modifier
& IgnoreSize
)
2591 && !intel_float_operand (t
->name
))
2592 : intel_float_operand (t
->name
) != 2)
2593 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2594 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2595 && (t
->base_opcode
!= 0x0fc7
2596 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2599 /* Do not verify operands when there are none. */
2600 else if (!t
->operands
)
2602 if (t
->cpu_flags
& ~cpu_arch_flags
)
2604 /* We've found a match; break out of loop. */
2608 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2609 into Disp32/Disp16/Disp32 operand. */
2610 if (i
.prefix
[ADDR_PREFIX
] != 0)
2612 unsigned int DispOn
= 0, DispOff
= 0;
2630 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2632 /* There should be only one Disp operand. */
2633 if ((operand_types
[j
] & DispOff
))
2635 addr_prefix_disp
= j
;
2636 operand_types
[j
] |= DispOn
;
2637 operand_types
[j
] &= ~DispOff
;
2643 overlap0
= i
.types
[0] & operand_types
[0];
2644 switch (t
->operands
)
2647 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2651 /* xchg %eax, %eax is a special case. It is an aliase for nop
2652 only in 32bit mode and we can use opcode 0x90. In 64bit
2653 mode, we can't use 0x90 for xchg %eax, %eax since it should
2654 zero-extend %eax to %rax. */
2655 if (flag_code
== CODE_64BIT
2656 && t
->base_opcode
== 0x90
2657 && i
.types
[0] == (Acc
| Reg32
)
2658 && i
.types
[1] == (Acc
| Reg32
))
2662 overlap1
= i
.types
[1] & operand_types
[1];
2663 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2664 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2665 /* monitor in SSE3 is a very special case. The first
2666 register and the second register may have different
2667 sizes. The same applies to crc32 in SSE4.2. */
2668 || !((t
->base_opcode
== 0x0f01
2669 && t
->extension_opcode
== 0xc8)
2670 || t
->base_opcode
== 0xf20f38f1
2671 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2673 overlap1
, i
.types
[1],
2676 /* Check if other direction is valid ... */
2677 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2680 /* Try reversing direction of operands. */
2681 overlap0
= i
.types
[0] & operand_types
[1];
2682 overlap1
= i
.types
[1] & operand_types
[0];
2683 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2684 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2685 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2687 overlap1
, i
.types
[1],
2690 /* Does not match either direction. */
2693 /* found_reverse_match holds which of D or FloatDR
2695 if ((t
->opcode_modifier
& D
))
2696 found_reverse_match
= Opcode_D
;
2697 else if ((t
->opcode_modifier
& FloatD
))
2698 found_reverse_match
= Opcode_FloatD
;
2700 found_reverse_match
= 0;
2701 if ((t
->opcode_modifier
& FloatR
))
2702 found_reverse_match
|= Opcode_FloatR
;
2706 /* Found a forward 2 operand match here. */
2707 switch (t
->operands
)
2710 overlap3
= i
.types
[3] & operand_types
[3];
2712 overlap2
= i
.types
[2] & operand_types
[2];
2716 switch (t
->operands
)
2719 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2720 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2728 /* Here we make use of the fact that there are no
2729 reverse match 3 operand instructions, and all 3
2730 operand instructions only need to be checked for
2731 register consistency between operands 2 and 3. */
2732 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2733 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2743 /* Found either forward/reverse 2, 3 or 4 operand match here:
2744 slip through to break. */
2746 if (t
->cpu_flags
& ~cpu_arch_flags
)
2748 found_reverse_match
= 0;
2751 /* We've found a match; break out of loop. */
2755 if (t
== current_templates
->end
)
2757 /* We found no match. */
2758 as_bad (_("suffix or operands invalid for `%s'"),
2759 current_templates
->start
->name
);
2763 if (!quiet_warnings
)
2766 && ((i
.types
[0] & JumpAbsolute
)
2767 != (operand_types
[0] & JumpAbsolute
)))
2769 as_warn (_("indirect %s without `*'"), t
->name
);
2772 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2773 == (IsPrefix
| IgnoreSize
))
2775 /* Warn them that a data or address size prefix doesn't
2776 affect assembly of the next line of code. */
2777 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2781 /* Copy the template we found. */
2784 if (addr_prefix_disp
!= -1)
2785 i
.tm
.operand_types
[addr_prefix_disp
]
2786 = operand_types
[addr_prefix_disp
];
2788 if (found_reverse_match
)
2790 /* If we found a reverse match we must alter the opcode
2791 direction bit. found_reverse_match holds bits to change
2792 (different for int & float insns). */
2794 i
.tm
.base_opcode
^= found_reverse_match
;
2796 i
.tm
.operand_types
[0] = operand_types
[1];
2797 i
.tm
.operand_types
[1] = operand_types
[0];
2806 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2807 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2809 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2811 as_bad (_("`%s' operand %d must use `%%es' segment"),
2816 /* There's only ever one segment override allowed per instruction.
2817 This instruction possibly has a legal segment override on the
2818 second operand, so copy the segment to where non-string
2819 instructions store it, allowing common code. */
2820 i
.seg
[0] = i
.seg
[1];
2822 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2824 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2826 as_bad (_("`%s' operand %d must use `%%es' segment"),
2836 process_suffix (void)
2838 /* If matched instruction specifies an explicit instruction mnemonic
2840 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2842 if (i
.tm
.opcode_modifier
& Size16
)
2843 i
.suffix
= WORD_MNEM_SUFFIX
;
2844 else if (i
.tm
.opcode_modifier
& Size64
)
2845 i
.suffix
= QWORD_MNEM_SUFFIX
;
2847 i
.suffix
= LONG_MNEM_SUFFIX
;
2849 else if (i
.reg_operands
)
2851 /* If there's no instruction mnemonic suffix we try to invent one
2852 based on register operands. */
2855 /* We take i.suffix from the last register operand specified,
2856 Destination register type is more significant than source
2857 register type. crc32 in SSE4.2 prefers source register
2859 if (i
.tm
.base_opcode
== 0xf20f38f1)
2861 if ((i
.types
[0] & Reg
))
2862 i
.suffix
= ((i
.types
[0] & Reg16
) ? WORD_MNEM_SUFFIX
:
2865 else if (i
.tm
.base_opcode
== 0xf20f38f0)
2867 if ((i
.types
[0] & Reg8
))
2868 i
.suffix
= BYTE_MNEM_SUFFIX
;
2875 if (i
.tm
.base_opcode
== 0xf20f38f1
2876 || i
.tm
.base_opcode
== 0xf20f38f0)
2878 /* We have to know the operand size for crc32. */
2879 as_bad (_("ambiguous memory operand size for `%s`"),
2884 for (op
= i
.operands
; --op
>= 0;)
2885 if ((i
.types
[op
] & Reg
)
2886 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2888 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2889 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2890 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2896 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2898 if (!check_byte_reg ())
2901 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2903 if (!check_long_reg ())
2906 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2908 if (!check_qword_reg ())
2911 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2913 if (!check_word_reg ())
2916 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2917 /* Do nothing if the instruction is going to ignore the prefix. */
2922 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2924 /* exclude fldenv/frstor/fsave/fstenv */
2925 && (i
.tm
.opcode_modifier
& No_sSuf
))
2927 i
.suffix
= stackop_size
;
2929 else if (intel_syntax
2931 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2932 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2933 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2934 && i
.tm
.extension_opcode
<= 3)))
2939 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2941 i
.suffix
= QWORD_MNEM_SUFFIX
;
2945 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2946 i
.suffix
= LONG_MNEM_SUFFIX
;
2949 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2950 i
.suffix
= WORD_MNEM_SUFFIX
;
2959 if (i
.tm
.opcode_modifier
& W
)
2961 as_bad (_("no instruction mnemonic suffix given and "
2962 "no register operands; can't size instruction"));
2968 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2976 if ((i
.tm
.opcode_modifier
& W
)
2977 || ((suffixes
& (suffixes
- 1))
2978 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2980 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2986 /* Change the opcode based on the operand size given by i.suffix;
2987 We don't need to change things for byte insns. */
2989 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2991 /* It's not a byte, select word/dword operation. */
2992 if (i
.tm
.opcode_modifier
& W
)
2994 if (i
.tm
.opcode_modifier
& ShortForm
)
2995 i
.tm
.base_opcode
|= 8;
2997 i
.tm
.base_opcode
|= 1;
3000 /* Now select between word & dword operations via the operand
3001 size prefix, except for instructions that will ignore this
3003 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
3005 /* monitor in SSE3 is a very special case. The default size
3006 of AX is the size of mode. The address size override
3007 prefix will change the size of AX. */
3008 if (i
.op
->regs
[0].reg_type
&
3009 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
3010 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3013 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3014 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3015 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
3016 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3017 || (flag_code
== CODE_64BIT
3018 && (i
.tm
.opcode_modifier
& JumpByte
))))
3020 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3022 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
3023 prefix
= ADDR_PREFIX_OPCODE
;
3025 if (!add_prefix (prefix
))
3029 /* Set mode64 for an operand. */
3030 if (i
.suffix
== QWORD_MNEM_SUFFIX
3031 && flag_code
== CODE_64BIT
3032 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
3034 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3035 need rex64. cmpxchg8b is also a special case. */
3036 if (! (i
.operands
== 2
3037 && i
.tm
.base_opcode
== 0x90
3038 && i
.tm
.extension_opcode
== None
3039 && i
.types
[0] == (Acc
| Reg64
)
3040 && i
.types
[1] == (Acc
| Reg64
))
3041 && ! (i
.operands
== 1
3042 && i
.tm
.base_opcode
== 0xfc7
3043 && i
.tm
.extension_opcode
== 1
3044 && (i
.types
[0] & Reg
) == 0
3045 && (i
.types
[0] & AnyMem
) != 0))
3049 /* Size floating point instruction. */
3050 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3051 if (i
.tm
.opcode_modifier
& FloatMF
)
3052 i
.tm
.base_opcode
^= 4;
3059 check_byte_reg (void)
3063 for (op
= i
.operands
; --op
>= 0;)
3065 /* If this is an eight bit register, it's OK. If it's the 16 or
3066 32 bit version of an eight bit register, we will just use the
3067 low portion, and that's OK too. */
3068 if (i
.types
[op
] & Reg8
)
3071 /* movzx, movsx, pextrb and pinsrb should not generate this
3074 && (i
.tm
.base_opcode
== 0xfb7
3075 || i
.tm
.base_opcode
== 0xfb6
3076 || i
.tm
.base_opcode
== 0x63
3077 || i
.tm
.base_opcode
== 0xfbe
3078 || i
.tm
.base_opcode
== 0xfbf
3079 || i
.tm
.base_opcode
== 0x660f3a14
3080 || i
.tm
.base_opcode
== 0x660f3a20))
3083 /* crc32 doesn't generate this warning. */
3084 if (i
.tm
.base_opcode
== 0xf20f38f0)
3087 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3089 /* Prohibit these changes in the 64bit mode, since the
3090 lowering is more complicated. */
3091 if (flag_code
== CODE_64BIT
3092 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3094 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3095 register_prefix
, i
.op
[op
].regs
->reg_name
,
3099 #if REGISTER_WARNINGS
3101 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3102 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3104 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3105 ? REGNAM_AL
- REGNAM_AX
3106 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3108 i
.op
[op
].regs
->reg_name
,
3113 /* Any other register is bad. */
3114 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3116 | Control
| Debug
| Test
3117 | FloatReg
| FloatAcc
))
3119 as_bad (_("`%s%s' not allowed with `%s%c'"),
3121 i
.op
[op
].regs
->reg_name
,
3131 check_long_reg (void)
3135 for (op
= i
.operands
; --op
>= 0;)
3136 /* Reject eight bit registers, except where the template requires
3137 them. (eg. movzb) */
3138 if ((i
.types
[op
] & Reg8
) != 0
3139 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3141 as_bad (_("`%s%s' not allowed with `%s%c'"),
3143 i
.op
[op
].regs
->reg_name
,
3148 /* Warn if the e prefix on a general reg is missing. */
3149 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3150 && (i
.types
[op
] & Reg16
) != 0
3151 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3153 /* Prohibit these changes in the 64bit mode, since the
3154 lowering is more complicated. */
3155 if (flag_code
== CODE_64BIT
)
3157 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3158 register_prefix
, i
.op
[op
].regs
->reg_name
,
3162 #if REGISTER_WARNINGS
3164 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3166 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3168 i
.op
[op
].regs
->reg_name
,
3172 /* Warn if the r prefix on a general reg is missing. */
3173 else if ((i
.types
[op
] & Reg64
) != 0
3174 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3177 && i
.tm
.base_opcode
== 0xf30f2d
3178 && (i
.types
[0] & RegXMM
) == 0)
3180 /* cvtss2si converts DWORD memory to Reg64. We want
3182 i
.suffix
= QWORD_MNEM_SUFFIX
;
3186 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3187 register_prefix
, i
.op
[op
].regs
->reg_name
,
3196 check_qword_reg (void)
3200 for (op
= i
.operands
; --op
>= 0; )
3201 /* Reject eight bit registers, except where the template requires
3202 them. (eg. movzb) */
3203 if ((i
.types
[op
] & Reg8
) != 0
3204 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3206 as_bad (_("`%s%s' not allowed with `%s%c'"),
3208 i
.op
[op
].regs
->reg_name
,
3213 /* Warn if the e prefix on a general reg is missing. */
3214 else if ((i
.types
[op
] & (Reg16
| Reg32
)) != 0
3215 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3217 /* Prohibit these changes in the 64bit mode, since the
3218 lowering is more complicated. */
3220 && i
.tm
.base_opcode
== 0xf20f2d
3221 && (i
.types
[0] & RegXMM
) == 0)
3223 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3225 i
.suffix
= LONG_MNEM_SUFFIX
;
3229 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3230 register_prefix
, i
.op
[op
].regs
->reg_name
,
3239 check_word_reg (void)
3242 for (op
= i
.operands
; --op
>= 0;)
3243 /* Reject eight bit registers, except where the template requires
3244 them. (eg. movzb) */
3245 if ((i
.types
[op
] & Reg8
) != 0
3246 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3248 as_bad (_("`%s%s' not allowed with `%s%c'"),
3250 i
.op
[op
].regs
->reg_name
,
3255 /* Warn if the e prefix on a general reg is present. */
3256 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3257 && (i
.types
[op
] & Reg32
) != 0
3258 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3260 /* Prohibit these changes in the 64bit mode, since the
3261 lowering is more complicated. */
3262 if (flag_code
== CODE_64BIT
)
3264 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3265 register_prefix
, i
.op
[op
].regs
->reg_name
,
3270 #if REGISTER_WARNINGS
3271 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3273 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3275 i
.op
[op
].regs
->reg_name
,
3285 unsigned int overlap0
, overlap1
, overlap2
;
3287 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3288 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3289 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3290 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3291 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3295 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3297 : (i
.suffix
== WORD_MNEM_SUFFIX
3299 : (i
.suffix
== QWORD_MNEM_SUFFIX
3303 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3304 || overlap0
== (Imm16
| Imm32
)
3305 || overlap0
== (Imm16
| Imm32S
))
3307 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3310 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3311 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3312 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3314 as_bad (_("no instruction mnemonic suffix given; "
3315 "can't determine immediate size"));
3319 i
.types
[0] = overlap0
;
3321 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3322 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3323 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3324 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3325 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3329 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3331 : (i
.suffix
== WORD_MNEM_SUFFIX
3333 : (i
.suffix
== QWORD_MNEM_SUFFIX
3337 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3338 || overlap1
== (Imm16
| Imm32
)
3339 || overlap1
== (Imm16
| Imm32S
))
3341 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3344 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3345 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3346 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3348 as_bad (_("no instruction mnemonic suffix given; "
3349 "can't determine immediate size %x %c"),
3350 overlap1
, i
.suffix
);
3354 i
.types
[1] = overlap1
;
3356 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3357 assert ((overlap2
& Imm
) == 0);
3358 i
.types
[2] = overlap2
;
3364 process_operands (void)
3366 /* Default segment register this instruction will use for memory
3367 accesses. 0 means unknown. This is only for optimizing out
3368 unnecessary segment overrides. */
3369 const seg_entry
*default_seg
= 0;
3371 /* The imul $imm, %reg instruction is converted into
3372 imul $imm, %reg, %reg, and the clr %reg instruction
3373 is converted into xor %reg, %reg. */
3374 if (i
.tm
.opcode_modifier
& RegKludge
)
3376 if ((i
.tm
.cpu_flags
& CpuSSE4_1
))
3378 /* The first operand in instruction blendvpd, blendvps and
3379 pblendvb in SSE4.1 is implicit and must be xmm0. */
3380 assert (i
.operands
== 3
3381 && i
.reg_operands
>= 2
3382 && i
.types
[0] == RegXMM
);
3383 if (i
.op
[0].regs
->reg_num
!= 0)
3386 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3387 i
.tm
.name
, register_prefix
);
3389 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3390 i
.tm
.name
, register_prefix
);
3395 i
.types
[0] = i
.types
[1];
3396 i
.types
[1] = i
.types
[2];
3400 /* We need to adjust fields in i.tm since they are used by
3401 build_modrm_byte. */
3402 i
.tm
.operand_types
[0] = i
.tm
.operand_types
[1];
3403 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[2];
3408 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3409 /* Pretend we saw the extra register operand. */
3410 assert (i
.reg_operands
== 1
3411 && i
.op
[first_reg_op
+ 1].regs
== 0);
3412 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3413 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3419 if (i
.tm
.opcode_modifier
& ShortForm
)
3421 if (i
.types
[0] & (SReg2
| SReg3
))
3423 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3424 && i
.op
[0].regs
->reg_num
== 1)
3426 as_bad (_("you can't `pop %%cs'"));
3429 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3430 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3435 /* The register or float register operand is in operand 0 or 1. */
3436 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3437 /* Register goes in low 3 bits of opcode. */
3438 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3439 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3441 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3443 /* Warn about some common errors, but press on regardless.
3444 The first case can be generated by gcc (<= 2.8.1). */
3445 if (i
.operands
== 2)
3447 /* Reversed arguments on faddp, fsubp, etc. */
3448 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
3449 register_prefix
, i
.op
[1].regs
->reg_name
,
3450 register_prefix
, i
.op
[0].regs
->reg_name
);
3454 /* Extraneous `l' suffix on fp insn. */
3455 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
3456 register_prefix
, i
.op
[0].regs
->reg_name
);
3461 else if (i
.tm
.opcode_modifier
& Modrm
)
3463 /* The opcode is completed (modulo i.tm.extension_opcode which
3464 must be put into the modrm byte). Now, we make the modrm and
3465 index base bytes based on all the info we've collected. */
3467 default_seg
= build_modrm_byte ();
3469 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3473 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3475 /* For the string instructions that allow a segment override
3476 on one of their operands, the default segment is ds. */
3480 if (i
.tm
.base_opcode
== 0x8d /* lea */
3483 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3485 /* If a segment was explicitly specified, and the specified segment
3486 is not the default, use an opcode prefix to select it. If we
3487 never figured out what the default segment is, then default_seg
3488 will be zero at this point, and the specified segment prefix will
3490 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3492 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3498 static const seg_entry
*
3499 build_modrm_byte (void)
3501 const seg_entry
*default_seg
= 0;
3503 /* i.reg_operands MUST be the number of real register operands;
3504 implicit registers do not count. */
3505 if (i
.reg_operands
== 2)
3507 unsigned int source
, dest
;
3515 /* When there are 3 operands, one of them may be immediate,
3516 which may be the first or the last operand. Otherwise,
3517 the first operand must be shift count register (cl). */
3518 assert (i
.imm_operands
== 1
3519 || (i
.imm_operands
== 0
3520 && (i
.types
[0] & ShiftCount
)));
3521 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3524 /* When there are 4 operands, the first two must be immediate
3525 operands. The source operand will be the 3rd one. */
3526 assert (i
.imm_operands
== 2
3527 && (i
.types
[0] & Imm
)
3528 && (i
.types
[1] & Imm
));
3538 /* One of the register operands will be encoded in the i.tm.reg
3539 field, the other in the combined i.tm.mode and i.tm.regmem
3540 fields. If no form of this instruction supports a memory
3541 destination operand, then we assume the source operand may
3542 sometimes be a memory operand and so we need to store the
3543 destination in the i.rm.reg field. */
3544 if ((i
.tm
.operand_types
[dest
] & (AnyMem
| RegMem
)) == 0)
3546 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3547 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3548 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3550 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3555 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3556 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3557 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3559 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3562 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
3564 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3566 i
.rex
&= ~(REX_R
| REX_B
);
3567 add_prefix (LOCK_PREFIX_OPCODE
);
3571 { /* If it's not 2 reg operands... */
3574 unsigned int fake_zero_displacement
= 0;
3577 for (op
= 0; op
< i
.operands
; op
++)
3578 if ((i
.types
[op
] & AnyMem
))
3580 assert (op
< i
.operands
);
3584 if (i
.base_reg
== 0)
3587 if (!i
.disp_operands
)
3588 fake_zero_displacement
= 1;
3589 if (i
.index_reg
== 0)
3591 /* Operand is just <disp> */
3592 if (flag_code
== CODE_64BIT
)
3594 /* 64bit mode overwrites the 32bit absolute
3595 addressing by RIP relative addressing and
3596 absolute addressing is encoded by one of the
3597 redundant SIB forms. */
3598 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3599 i
.sib
.base
= NO_BASE_REGISTER
;
3600 i
.sib
.index
= NO_INDEX_REGISTER
;
3601 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3602 ? Disp32S
: Disp32
);
3604 else if ((flag_code
== CODE_16BIT
)
3605 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3607 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3608 i
.types
[op
] = Disp16
;
3612 i
.rm
.regmem
= NO_BASE_REGISTER
;
3613 i
.types
[op
] = Disp32
;
3616 else /* !i.base_reg && i.index_reg */
3618 i
.sib
.index
= i
.index_reg
->reg_num
;
3619 i
.sib
.base
= NO_BASE_REGISTER
;
3620 i
.sib
.scale
= i
.log2_scale_factor
;
3621 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3622 i
.types
[op
] &= ~Disp
;
3623 if (flag_code
!= CODE_64BIT
)
3624 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3626 i
.types
[op
] |= Disp32S
;
3627 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3631 /* RIP addressing for 64bit mode. */
3632 else if (i
.base_reg
->reg_type
== BaseIndex
)
3634 i
.rm
.regmem
= NO_BASE_REGISTER
;
3635 i
.types
[op
] &= ~ Disp
;
3636 i
.types
[op
] |= Disp32S
;
3637 i
.flags
[op
] |= Operand_PCrel
;
3638 if (! i
.disp_operands
)
3639 fake_zero_displacement
= 1;
3641 else if (i
.base_reg
->reg_type
& Reg16
)
3643 switch (i
.base_reg
->reg_num
)
3646 if (i
.index_reg
== 0)
3648 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3649 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3653 if (i
.index_reg
== 0)
3656 if ((i
.types
[op
] & Disp
) == 0)
3658 /* fake (%bp) into 0(%bp) */
3659 i
.types
[op
] |= Disp8
;
3660 fake_zero_displacement
= 1;
3663 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3664 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3666 default: /* (%si) -> 4 or (%di) -> 5 */
3667 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3669 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3671 else /* i.base_reg and 32/64 bit mode */
3673 if (flag_code
== CODE_64BIT
3674 && (i
.types
[op
] & Disp
))
3675 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3676 | (i
.prefix
[ADDR_PREFIX
] == 0
3677 ? Disp32S
: Disp32
));
3679 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3680 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3682 i
.sib
.base
= i
.base_reg
->reg_num
;
3683 /* x86-64 ignores REX prefix bit here to avoid decoder
3685 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3688 if (i
.disp_operands
== 0)
3690 fake_zero_displacement
= 1;
3691 i
.types
[op
] |= Disp8
;
3694 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3698 i
.sib
.scale
= i
.log2_scale_factor
;
3699 if (i
.index_reg
== 0)
3701 /* <disp>(%esp) becomes two byte modrm with no index
3702 register. We've already stored the code for esp
3703 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3704 Any base register besides %esp will not use the
3705 extra modrm byte. */
3706 i
.sib
.index
= NO_INDEX_REGISTER
;
3707 #if !SCALE1_WHEN_NO_INDEX
3708 /* Another case where we force the second modrm byte. */
3709 if (i
.log2_scale_factor
)
3710 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3715 i
.sib
.index
= i
.index_reg
->reg_num
;
3716 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3717 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3722 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3723 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3726 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3729 if (fake_zero_displacement
)
3731 /* Fakes a zero displacement assuming that i.types[op]
3732 holds the correct displacement size. */
3735 assert (i
.op
[op
].disps
== 0);
3736 exp
= &disp_expressions
[i
.disp_operands
++];
3737 i
.op
[op
].disps
= exp
;
3738 exp
->X_op
= O_constant
;
3739 exp
->X_add_number
= 0;
3740 exp
->X_add_symbol
= (symbolS
*) 0;
3741 exp
->X_op_symbol
= (symbolS
*) 0;
3745 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3746 (if any) based on i.tm.extension_opcode. Again, we must be
3747 careful to make sure that segment/control/debug/test/MMX
3748 registers are coded into the i.rm.reg field. */
3753 for (op
= 0; op
< i
.operands
; op
++)
3754 if ((i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3756 | Control
| Debug
| Test
)))
3758 assert (op
< i
.operands
);
3760 /* If there is an extension opcode to put here, the register
3761 number must be put into the regmem field. */
3762 if (i
.tm
.extension_opcode
!= None
)
3764 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3765 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3770 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3771 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3775 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3776 must set it to 3 to indicate this is a register operand
3777 in the regmem field. */
3778 if (!i
.mem_operands
)
3782 /* Fill in i.rm.reg field with extension opcode (if any). */
3783 if (i
.tm
.extension_opcode
!= None
)
3784 i
.rm
.reg
= i
.tm
.extension_opcode
;
3790 output_branch (void)
3795 relax_substateT subtype
;
3800 if (flag_code
== CODE_16BIT
)
3804 if (i
.prefix
[DATA_PREFIX
] != 0)
3810 /* Pentium4 branch hints. */
3811 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3812 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3817 if (i
.prefix
[REX_PREFIX
] != 0)
3823 if (i
.prefixes
!= 0 && !intel_syntax
)
3824 as_warn (_("skipping prefixes on this instruction"));
3826 /* It's always a symbol; End frag & setup for relax.
3827 Make sure there is enough room in this frag for the largest
3828 instruction we may generate in md_convert_frag. This is 2
3829 bytes for the opcode and room for the prefix and largest
3831 frag_grow (prefix
+ 2 + 4);
3832 /* Prefix and 1 opcode byte go in fr_fix. */
3833 p
= frag_more (prefix
+ 1);
3834 if (i
.prefix
[DATA_PREFIX
] != 0)
3835 *p
++ = DATA_PREFIX_OPCODE
;
3836 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3837 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3838 *p
++ = i
.prefix
[SEG_PREFIX
];
3839 if (i
.prefix
[REX_PREFIX
] != 0)
3840 *p
++ = i
.prefix
[REX_PREFIX
];
3841 *p
= i
.tm
.base_opcode
;
3843 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3844 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3845 else if ((cpu_arch_flags
& Cpu386
) != 0)
3846 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3848 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3851 sym
= i
.op
[0].disps
->X_add_symbol
;
3852 off
= i
.op
[0].disps
->X_add_number
;
3854 if (i
.op
[0].disps
->X_op
!= O_constant
3855 && i
.op
[0].disps
->X_op
!= O_symbol
)
3857 /* Handle complex expressions. */
3858 sym
= make_expr_symbol (i
.op
[0].disps
);
3862 /* 1 possible extra opcode + 4 byte displacement go in var part.
3863 Pass reloc in fr_var. */
3864 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3874 if (i
.tm
.opcode_modifier
& JumpByte
)
3876 /* This is a loop or jecxz type instruction. */
3878 if (i
.prefix
[ADDR_PREFIX
] != 0)
3880 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3883 /* Pentium4 branch hints. */
3884 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3885 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3887 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3896 if (flag_code
== CODE_16BIT
)
3899 if (i
.prefix
[DATA_PREFIX
] != 0)
3901 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3911 if (i
.prefix
[REX_PREFIX
] != 0)
3913 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3917 if (i
.prefixes
!= 0 && !intel_syntax
)
3918 as_warn (_("skipping prefixes on this instruction"));
3920 p
= frag_more (1 + size
);
3921 *p
++ = i
.tm
.base_opcode
;
3923 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3924 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3926 /* All jumps handled here are signed, but don't use a signed limit
3927 check for 32 and 16 bit jumps as we want to allow wrap around at
3928 4G and 64k respectively. */
3930 fixP
->fx_signed
= 1;
3934 output_interseg_jump (void)
3942 if (flag_code
== CODE_16BIT
)
3946 if (i
.prefix
[DATA_PREFIX
] != 0)
3952 if (i
.prefix
[REX_PREFIX
] != 0)
3962 if (i
.prefixes
!= 0 && !intel_syntax
)
3963 as_warn (_("skipping prefixes on this instruction"));
3965 /* 1 opcode; 2 segment; offset */
3966 p
= frag_more (prefix
+ 1 + 2 + size
);
3968 if (i
.prefix
[DATA_PREFIX
] != 0)
3969 *p
++ = DATA_PREFIX_OPCODE
;
3971 if (i
.prefix
[REX_PREFIX
] != 0)
3972 *p
++ = i
.prefix
[REX_PREFIX
];
3974 *p
++ = i
.tm
.base_opcode
;
3975 if (i
.op
[1].imms
->X_op
== O_constant
)
3977 offsetT n
= i
.op
[1].imms
->X_add_number
;
3980 && !fits_in_unsigned_word (n
)
3981 && !fits_in_signed_word (n
))
3983 as_bad (_("16-bit jump out of range"));
3986 md_number_to_chars (p
, n
, size
);
3989 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3990 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3991 if (i
.op
[0].imms
->X_op
!= O_constant
)
3992 as_bad (_("can't handle non absolute segment in `%s'"),
3994 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4000 fragS
*insn_start_frag
;
4001 offsetT insn_start_off
;
4003 /* Tie dwarf2 debug info to the address at the start of the insn.
4004 We can't do this after the insn has been output as the current
4005 frag may have been closed off. eg. by frag_var. */
4006 dwarf2_emit_insn (0);
4008 insn_start_frag
= frag_now
;
4009 insn_start_off
= frag_now_fix ();
4012 if (i
.tm
.opcode_modifier
& Jump
)
4014 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
4016 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
4017 output_interseg_jump ();
4020 /* Output normal instructions here. */
4023 unsigned int prefix
;
4025 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
4026 SSE4 instructions have 3 bytes. We may use one more higher
4027 byte to specify a prefix the instruction requires. Exclude
4028 instructions which are in both SSE4 and ABM. */
4029 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
4030 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
4032 if (i
.tm
.base_opcode
& 0xff000000)
4034 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
4038 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
4040 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
4041 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
4044 if (prefix
!= REPE_PREFIX_OPCODE
4045 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
4046 add_prefix (prefix
);
4049 add_prefix (prefix
);
4052 /* The prefix bytes. */
4054 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
4060 md_number_to_chars (p
, (valueT
) *q
, 1);
4064 /* Now the opcode; be careful about word order here! */
4065 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
4067 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
4071 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
4072 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
4075 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
4080 /* Put out high byte first: can't use md_number_to_chars! */
4081 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
4082 *p
= i
.tm
.base_opcode
& 0xff;
4085 /* Now the modrm byte and sib byte (if present). */
4086 if (i
.tm
.opcode_modifier
& Modrm
)
4089 md_number_to_chars (p
,
4090 (valueT
) (i
.rm
.regmem
<< 0
4094 /* If i.rm.regmem == ESP (4)
4095 && i.rm.mode != (Register mode)
4097 ==> need second modrm byte. */
4098 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
4100 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
4103 md_number_to_chars (p
,
4104 (valueT
) (i
.sib
.base
<< 0
4106 | i
.sib
.scale
<< 6),
4111 if (i
.disp_operands
)
4112 output_disp (insn_start_frag
, insn_start_off
);
4115 output_imm (insn_start_frag
, insn_start_off
);
4121 pi ("" /*line*/, &i
);
4123 #endif /* DEBUG386 */
4126 /* Return the size of the displacement operand N. */
4129 disp_size (unsigned int n
)
4132 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4135 if (i
.types
[n
] & Disp8
)
4137 if (i
.types
[n
] & Disp64
)
4143 /* Return the size of the immediate operand N. */
4146 imm_size (unsigned int n
)
4149 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4152 if (i
.types
[n
] & (Imm8
| Imm8S
))
4154 if (i
.types
[n
] & Imm64
)
4161 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4166 for (n
= 0; n
< i
.operands
; n
++)
4168 if (i
.types
[n
] & Disp
)
4170 if (i
.op
[n
].disps
->X_op
== O_constant
)
4172 int size
= disp_size (n
);
4175 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4177 p
= frag_more (size
);
4178 md_number_to_chars (p
, val
, size
);
4182 enum bfd_reloc_code_real reloc_type
;
4183 int size
= disp_size (n
);
4184 int sign
= (i
.types
[n
] & Disp32S
) != 0;
4185 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4187 /* We can't have 8 bit displacement here. */
4188 assert ((i
.types
[n
] & Disp8
) == 0);
4190 /* The PC relative address is computed relative
4191 to the instruction boundary, so in case immediate
4192 fields follows, we need to adjust the value. */
4193 if (pcrel
&& i
.imm_operands
)
4198 for (n1
= 0; n1
< i
.operands
; n1
++)
4199 if (i
.types
[n1
] & Imm
)
4201 /* Only one immediate is allowed for PC
4202 relative address. */
4205 i
.op
[n
].disps
->X_add_number
-= sz
;
4207 /* We should find the immediate. */
4211 p
= frag_more (size
);
4212 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4214 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4215 && (((reloc_type
== BFD_RELOC_32
4216 || reloc_type
== BFD_RELOC_X86_64_32S
4217 || (reloc_type
== BFD_RELOC_64
4219 && (i
.op
[n
].disps
->X_op
== O_symbol
4220 || (i
.op
[n
].disps
->X_op
== O_add
4221 && ((symbol_get_value_expression
4222 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4224 || reloc_type
== BFD_RELOC_32_PCREL
))
4228 if (insn_start_frag
== frag_now
)
4229 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4234 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4235 for (fr
= insn_start_frag
->fr_next
;
4236 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4238 add
+= p
- frag_now
->fr_literal
;
4243 reloc_type
= BFD_RELOC_386_GOTPC
;
4244 i
.op
[n
].imms
->X_add_number
+= add
;
4246 else if (reloc_type
== BFD_RELOC_64
)
4247 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4249 /* Don't do the adjustment for x86-64, as there
4250 the pcrel addressing is relative to the _next_
4251 insn, and that is taken care of in other code. */
4252 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4254 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4255 i
.op
[n
].disps
, pcrel
, reloc_type
);
4262 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4267 for (n
= 0; n
< i
.operands
; n
++)
4269 if (i
.types
[n
] & Imm
)
4271 if (i
.op
[n
].imms
->X_op
== O_constant
)
4273 int size
= imm_size (n
);
4276 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4278 p
= frag_more (size
);
4279 md_number_to_chars (p
, val
, size
);
4283 /* Not absolute_section.
4284 Need a 32-bit fixup (don't support 8bit
4285 non-absolute imms). Try to support other
4287 enum bfd_reloc_code_real reloc_type
;
4288 int size
= imm_size (n
);
4291 if ((i
.types
[n
] & (Imm32S
))
4292 && (i
.suffix
== QWORD_MNEM_SUFFIX
4293 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4298 p
= frag_more (size
);
4299 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4301 /* This is tough to explain. We end up with this one if we
4302 * have operands that look like
4303 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4304 * obtain the absolute address of the GOT, and it is strongly
4305 * preferable from a performance point of view to avoid using
4306 * a runtime relocation for this. The actual sequence of
4307 * instructions often look something like:
4312 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4314 * The call and pop essentially return the absolute address
4315 * of the label .L66 and store it in %ebx. The linker itself
4316 * will ultimately change the first operand of the addl so
4317 * that %ebx points to the GOT, but to keep things simple, the
4318 * .o file must have this operand set so that it generates not
4319 * the absolute address of .L66, but the absolute address of
4320 * itself. This allows the linker itself simply treat a GOTPC
4321 * relocation as asking for a pcrel offset to the GOT to be
4322 * added in, and the addend of the relocation is stored in the
4323 * operand field for the instruction itself.
4325 * Our job here is to fix the operand so that it would add
4326 * the correct offset so that %ebx would point to itself. The
4327 * thing that is tricky is that .-.L66 will point to the
4328 * beginning of the instruction, so we need to further modify
4329 * the operand so that it will point to itself. There are
4330 * other cases where you have something like:
4332 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4334 * and here no correction would be required. Internally in
4335 * the assembler we treat operands of this form as not being
4336 * pcrel since the '.' is explicitly mentioned, and I wonder
4337 * whether it would simplify matters to do it this way. Who
4338 * knows. In earlier versions of the PIC patches, the
4339 * pcrel_adjust field was used to store the correction, but
4340 * since the expression is not pcrel, I felt it would be
4341 * confusing to do it this way. */
4343 if ((reloc_type
== BFD_RELOC_32
4344 || reloc_type
== BFD_RELOC_X86_64_32S
4345 || reloc_type
== BFD_RELOC_64
)
4347 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4348 && (i
.op
[n
].imms
->X_op
== O_symbol
4349 || (i
.op
[n
].imms
->X_op
== O_add
4350 && ((symbol_get_value_expression
4351 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4356 if (insn_start_frag
== frag_now
)
4357 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4362 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4363 for (fr
= insn_start_frag
->fr_next
;
4364 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4366 add
+= p
- frag_now
->fr_literal
;
4370 reloc_type
= BFD_RELOC_386_GOTPC
;
4372 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4374 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4375 i
.op
[n
].imms
->X_add_number
+= add
;
4377 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4378 i
.op
[n
].imms
, 0, reloc_type
);
4384 /* x86_cons_fix_new is called via the expression parsing code when a
4385 reloc is needed. We use this hook to get the correct .got reloc. */
4386 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4387 static int cons_sign
= -1;
4390 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4393 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4395 got_reloc
= NO_RELOC
;
4398 if (exp
->X_op
== O_secrel
)
4400 exp
->X_op
= O_symbol
;
4401 r
= BFD_RELOC_32_SECREL
;
4405 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4408 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4409 # define lex_got(reloc, adjust, types) NULL
4411 /* Parse operands of the form
4412 <symbol>@GOTOFF+<nnn>
4413 and similar .plt or .got references.
4415 If we find one, set up the correct relocation in RELOC and copy the
4416 input string, minus the `@GOTOFF' into a malloc'd buffer for
4417 parsing by the calling routine. Return this buffer, and if ADJUST
4418 is non-null set it to the length of the string we removed from the
4419 input line. Otherwise return NULL. */
4421 lex_got (enum bfd_reloc_code_real
*reloc
,
4423 unsigned int *types
)
4425 /* Some of the relocations depend on the size of what field is to
4426 be relocated. But in our callers i386_immediate and i386_displacement
4427 we don't yet know the operand size (this will be set by insn
4428 matching). Hence we record the word32 relocation here,
4429 and adjust the reloc according to the real size in reloc(). */
4430 static const struct {
4432 const enum bfd_reloc_code_real rel
[2];
4433 const unsigned int types64
;
4436 BFD_RELOC_X86_64_PLTOFF64
},
4438 { "PLT", { BFD_RELOC_386_PLT32
,
4439 BFD_RELOC_X86_64_PLT32
},
4440 Imm32
| Imm32S
| Disp32
},
4442 BFD_RELOC_X86_64_GOTPLT64
},
4444 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4445 BFD_RELOC_X86_64_GOTOFF64
},
4448 BFD_RELOC_X86_64_GOTPCREL
},
4449 Imm32
| Imm32S
| Disp32
},
4450 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4451 BFD_RELOC_X86_64_TLSGD
},
4452 Imm32
| Imm32S
| Disp32
},
4453 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4457 BFD_RELOC_X86_64_TLSLD
},
4458 Imm32
| Imm32S
| Disp32
},
4459 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
4460 BFD_RELOC_X86_64_GOTTPOFF
},
4461 Imm32
| Imm32S
| Disp32
},
4462 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
4463 BFD_RELOC_X86_64_TPOFF32
},
4464 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4465 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
4468 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
4469 BFD_RELOC_X86_64_DTPOFF32
},
4470 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4471 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
4474 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
4477 { "GOT", { BFD_RELOC_386_GOT32
,
4478 BFD_RELOC_X86_64_GOT32
},
4479 Imm32
| Imm32S
| Disp32
| Imm64
},
4480 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
4481 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
4482 Imm32
| Imm32S
| Disp32
},
4483 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
4484 BFD_RELOC_X86_64_TLSDESC_CALL
},
4485 Imm32
| Imm32S
| Disp32
}
4493 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4494 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
4497 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4501 len
= strlen (gotrel
[j
].str
);
4502 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4504 if (gotrel
[j
].rel
[object_64bit
] != 0)
4507 char *tmpbuf
, *past_reloc
;
4509 *reloc
= gotrel
[j
].rel
[object_64bit
];
4515 if (flag_code
!= CODE_64BIT
)
4516 *types
= Imm32
| Disp32
;
4518 *types
= gotrel
[j
].types64
;
4521 if (GOT_symbol
== NULL
)
4522 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4524 /* The length of the first part of our input line. */
4525 first
= cp
- input_line_pointer
;
4527 /* The second part goes from after the reloc token until
4528 (and including) an end_of_line char or comma. */
4529 past_reloc
= cp
+ 1 + len
;
4531 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
4533 second
= cp
+ 1 - past_reloc
;
4535 /* Allocate and copy string. The trailing NUL shouldn't
4536 be necessary, but be safe. */
4537 tmpbuf
= xmalloc (first
+ second
+ 2);
4538 memcpy (tmpbuf
, input_line_pointer
, first
);
4539 if (second
!= 0 && *past_reloc
!= ' ')
4540 /* Replace the relocation token with ' ', so that
4541 errors like foo@GOTOFF1 will be detected. */
4542 tmpbuf
[first
++] = ' ';
4543 memcpy (tmpbuf
+ first
, past_reloc
, second
);
4544 tmpbuf
[first
+ second
] = '\0';
4548 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4549 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4554 /* Might be a symbol version string. Don't as_bad here. */
4559 x86_cons (expressionS
*exp
, int size
)
4561 if (size
== 4 || (object_64bit
&& size
== 8))
4563 /* Handle @GOTOFF and the like in an expression. */
4565 char *gotfree_input_line
;
4568 save
= input_line_pointer
;
4569 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4570 if (gotfree_input_line
)
4571 input_line_pointer
= gotfree_input_line
;
4575 if (gotfree_input_line
)
4577 /* expression () has merrily parsed up to the end of line,
4578 or a comma - in the wrong buffer. Transfer how far
4579 input_line_pointer has moved to the right buffer. */
4580 input_line_pointer
= (save
4581 + (input_line_pointer
- gotfree_input_line
)
4583 free (gotfree_input_line
);
4584 if (exp
->X_op
== O_constant
4585 || exp
->X_op
== O_absent
4586 || exp
->X_op
== O_illegal
4587 || exp
->X_op
== O_register
4588 || exp
->X_op
== O_big
)
4590 char c
= *input_line_pointer
;
4591 *input_line_pointer
= 0;
4592 as_bad (_("missing or invalid expression `%s'"), save
);
4593 *input_line_pointer
= c
;
4602 static void signed_cons (int size
)
4604 if (flag_code
== CODE_64BIT
)
4612 pe_directive_secrel (dummy
)
4613 int dummy ATTRIBUTE_UNUSED
;
4620 if (exp
.X_op
== O_symbol
)
4621 exp
.X_op
= O_secrel
;
4623 emit_expr (&exp
, 4);
4625 while (*input_line_pointer
++ == ',');
4627 input_line_pointer
--;
4628 demand_empty_rest_of_line ();
4633 i386_immediate (char *imm_start
)
4635 char *save_input_line_pointer
;
4636 char *gotfree_input_line
;
4639 unsigned int types
= ~0U;
4641 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4643 as_bad (_("at most %d immediate operands are allowed"),
4644 MAX_IMMEDIATE_OPERANDS
);
4648 exp
= &im_expressions
[i
.imm_operands
++];
4649 i
.op
[this_operand
].imms
= exp
;
4651 if (is_space_char (*imm_start
))
4654 save_input_line_pointer
= input_line_pointer
;
4655 input_line_pointer
= imm_start
;
4657 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4658 if (gotfree_input_line
)
4659 input_line_pointer
= gotfree_input_line
;
4661 exp_seg
= expression (exp
);
4664 if (*input_line_pointer
)
4665 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4667 input_line_pointer
= save_input_line_pointer
;
4668 if (gotfree_input_line
)
4669 free (gotfree_input_line
);
4671 if (exp
->X_op
== O_absent
4672 || exp
->X_op
== O_illegal
4673 || exp
->X_op
== O_big
4674 || (gotfree_input_line
4675 && (exp
->X_op
== O_constant
4676 || exp
->X_op
== O_register
)))
4678 as_bad (_("missing or invalid immediate expression `%s'"),
4682 else if (exp
->X_op
== O_constant
)
4684 /* Size it properly later. */
4685 i
.types
[this_operand
] |= Imm64
;
4686 /* If BFD64, sign extend val. */
4687 if (!use_rela_relocations
4688 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4690 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4692 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4693 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4694 && exp_seg
!= absolute_section
4695 && exp_seg
!= text_section
4696 && exp_seg
!= data_section
4697 && exp_seg
!= bss_section
4698 && exp_seg
!= undefined_section
4699 && !bfd_is_com_section (exp_seg
))
4701 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4705 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4707 as_bad (_("illegal immediate register operand %s"), imm_start
);
4712 /* This is an address. The size of the address will be
4713 determined later, depending on destination register,
4714 suffix, or the default for the section. */
4715 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4716 i
.types
[this_operand
] &= types
;
4723 i386_scale (char *scale
)
4726 char *save
= input_line_pointer
;
4728 input_line_pointer
= scale
;
4729 val
= get_absolute_expression ();
4734 i
.log2_scale_factor
= 0;
4737 i
.log2_scale_factor
= 1;
4740 i
.log2_scale_factor
= 2;
4743 i
.log2_scale_factor
= 3;
4747 char sep
= *input_line_pointer
;
4749 *input_line_pointer
= '\0';
4750 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4752 *input_line_pointer
= sep
;
4753 input_line_pointer
= save
;
4757 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4759 as_warn (_("scale factor of %d without an index register"),
4760 1 << i
.log2_scale_factor
);
4761 #if SCALE1_WHEN_NO_INDEX
4762 i
.log2_scale_factor
= 0;
4765 scale
= input_line_pointer
;
4766 input_line_pointer
= save
;
4771 i386_displacement (char *disp_start
, char *disp_end
)
4775 char *save_input_line_pointer
;
4776 char *gotfree_input_line
;
4777 int bigdisp
, override
;
4778 unsigned int types
= Disp
;
4781 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4783 as_bad (_("at most %d displacement operands are allowed"),
4784 MAX_MEMORY_OPERANDS
);
4788 if ((i
.types
[this_operand
] & JumpAbsolute
)
4789 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4792 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4796 /* For PC-relative branches, the width of the displacement
4797 is dependent upon data size, not address size. */
4799 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4801 if (flag_code
== CODE_64BIT
)
4804 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4806 : Disp32S
| Disp32
);
4808 bigdisp
= Disp64
| Disp32S
| Disp32
;
4815 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4817 : LONG_MNEM_SUFFIX
));
4820 if ((flag_code
== CODE_16BIT
) ^ override
)
4823 i
.types
[this_operand
] |= bigdisp
;
4825 exp
= &disp_expressions
[i
.disp_operands
];
4826 i
.op
[this_operand
].disps
= exp
;
4828 save_input_line_pointer
= input_line_pointer
;
4829 input_line_pointer
= disp_start
;
4830 END_STRING_AND_SAVE (disp_end
);
4832 #ifndef GCC_ASM_O_HACK
4833 #define GCC_ASM_O_HACK 0
4836 END_STRING_AND_SAVE (disp_end
+ 1);
4837 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4838 && displacement_string_end
[-1] == '+')
4840 /* This hack is to avoid a warning when using the "o"
4841 constraint within gcc asm statements.
4844 #define _set_tssldt_desc(n,addr,limit,type) \
4845 __asm__ __volatile__ ( \
4847 "movw %w1,2+%0\n\t" \
4849 "movb %b1,4+%0\n\t" \
4850 "movb %4,5+%0\n\t" \
4851 "movb $0,6+%0\n\t" \
4852 "movb %h1,7+%0\n\t" \
4854 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4856 This works great except that the output assembler ends
4857 up looking a bit weird if it turns out that there is
4858 no offset. You end up producing code that looks like:
4871 So here we provide the missing zero. */
4873 *displacement_string_end
= '0';
4876 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4877 if (gotfree_input_line
)
4878 input_line_pointer
= gotfree_input_line
;
4880 exp_seg
= expression (exp
);
4883 if (*input_line_pointer
)
4884 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4886 RESTORE_END_STRING (disp_end
+ 1);
4888 input_line_pointer
= save_input_line_pointer
;
4889 if (gotfree_input_line
)
4890 free (gotfree_input_line
);
4893 /* We do this to make sure that the section symbol is in
4894 the symbol table. We will ultimately change the relocation
4895 to be relative to the beginning of the section. */
4896 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4897 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4898 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4900 if (exp
->X_op
!= O_symbol
)
4903 if (S_IS_LOCAL (exp
->X_add_symbol
)
4904 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4905 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4906 exp
->X_op
= O_subtract
;
4907 exp
->X_op_symbol
= GOT_symbol
;
4908 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4909 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4910 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4911 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4913 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4916 else if (exp
->X_op
== O_absent
4917 || exp
->X_op
== O_illegal
4918 || exp
->X_op
== O_big
4919 || (gotfree_input_line
4920 && (exp
->X_op
== O_constant
4921 || exp
->X_op
== O_register
)))
4924 as_bad (_("missing or invalid displacement expression `%s'"),
4929 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4930 else if (exp
->X_op
!= O_constant
4931 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4932 && exp_seg
!= absolute_section
4933 && exp_seg
!= text_section
4934 && exp_seg
!= data_section
4935 && exp_seg
!= bss_section
4936 && exp_seg
!= undefined_section
4937 && !bfd_is_com_section (exp_seg
))
4939 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4944 RESTORE_END_STRING (disp_end
);
4946 if (!(i
.types
[this_operand
] & ~Disp
))
4947 i
.types
[this_operand
] &= types
;
4952 /* Make sure the memory operand we've been dealt is valid.
4953 Return 1 on success, 0 on a failure. */
4956 i386_index_check (const char *operand_string
)
4959 #if INFER_ADDR_PREFIX
4965 if (flag_code
== CODE_64BIT
)
4967 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4970 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4971 && (i
.base_reg
->reg_type
!= BaseIndex
4974 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4975 != (RegXX
| BaseIndex
))))
4980 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4984 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4985 != (Reg16
| BaseIndex
)))
4987 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4988 != (Reg16
| BaseIndex
))
4990 && i
.base_reg
->reg_num
< 6
4991 && i
.index_reg
->reg_num
>= 6
4992 && i
.log2_scale_factor
== 0))))
4999 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
5001 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
5002 != (Reg32
| BaseIndex
))))
5008 #if INFER_ADDR_PREFIX
5009 if (i
.prefix
[ADDR_PREFIX
] == 0)
5011 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
5013 /* Change the size of any displacement too. At most one of
5014 Disp16 or Disp32 is set.
5015 FIXME. There doesn't seem to be any real need for separate
5016 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
5017 Removing them would probably clean up the code quite a lot. */
5018 if (flag_code
!= CODE_64BIT
5019 && (i
.types
[this_operand
] & (Disp16
| Disp32
)))
5020 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
5025 as_bad (_("`%s' is not a valid base/index expression"),
5029 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5031 flag_code_names
[flag_code
]);
5036 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
5040 i386_operand (char *operand_string
)
5044 char *op_string
= operand_string
;
5046 if (is_space_char (*op_string
))
5049 /* We check for an absolute prefix (differentiating,
5050 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
5051 if (*op_string
== ABSOLUTE_PREFIX
)
5054 if (is_space_char (*op_string
))
5056 i
.types
[this_operand
] |= JumpAbsolute
;
5059 /* Check if operand is a register. */
5060 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
5062 /* Check for a segment override by searching for ':' after a
5063 segment register. */
5065 if (is_space_char (*op_string
))
5067 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
5072 i
.seg
[i
.mem_operands
] = &es
;
5075 i
.seg
[i
.mem_operands
] = &cs
;
5078 i
.seg
[i
.mem_operands
] = &ss
;
5081 i
.seg
[i
.mem_operands
] = &ds
;
5084 i
.seg
[i
.mem_operands
] = &fs
;
5087 i
.seg
[i
.mem_operands
] = &gs
;
5091 /* Skip the ':' and whitespace. */
5093 if (is_space_char (*op_string
))
5096 if (!is_digit_char (*op_string
)
5097 && !is_identifier_char (*op_string
)
5098 && *op_string
!= '('
5099 && *op_string
!= ABSOLUTE_PREFIX
)
5101 as_bad (_("bad memory operand `%s'"), op_string
);
5104 /* Handle case of %es:*foo. */
5105 if (*op_string
== ABSOLUTE_PREFIX
)
5108 if (is_space_char (*op_string
))
5110 i
.types
[this_operand
] |= JumpAbsolute
;
5112 goto do_memory_reference
;
5116 as_bad (_("junk `%s' after register"), op_string
);
5119 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5120 i
.op
[this_operand
].regs
= r
;
5123 else if (*op_string
== REGISTER_PREFIX
)
5125 as_bad (_("bad register name `%s'"), op_string
);
5128 else if (*op_string
== IMMEDIATE_PREFIX
)
5131 if (i
.types
[this_operand
] & JumpAbsolute
)
5133 as_bad (_("immediate operand illegal with absolute jump"));
5136 if (!i386_immediate (op_string
))
5139 else if (is_digit_char (*op_string
)
5140 || is_identifier_char (*op_string
)
5141 || *op_string
== '(')
5143 /* This is a memory reference of some sort. */
5146 /* Start and end of displacement string expression (if found). */
5147 char *displacement_string_start
;
5148 char *displacement_string_end
;
5150 do_memory_reference
:
5151 if ((i
.mem_operands
== 1
5152 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5153 || i
.mem_operands
== 2)
5155 as_bad (_("too many memory references for `%s'"),
5156 current_templates
->start
->name
);
5160 /* Check for base index form. We detect the base index form by
5161 looking for an ')' at the end of the operand, searching
5162 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5164 base_string
= op_string
+ strlen (op_string
);
5167 if (is_space_char (*base_string
))
5170 /* If we only have a displacement, set-up for it to be parsed later. */
5171 displacement_string_start
= op_string
;
5172 displacement_string_end
= base_string
+ 1;
5174 if (*base_string
== ')')
5177 unsigned int parens_balanced
= 1;
5178 /* We've already checked that the number of left & right ()'s are
5179 equal, so this loop will not be infinite. */
5183 if (*base_string
== ')')
5185 if (*base_string
== '(')
5188 while (parens_balanced
);
5190 temp_string
= base_string
;
5192 /* Skip past '(' and whitespace. */
5194 if (is_space_char (*base_string
))
5197 if (*base_string
== ','
5198 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5201 displacement_string_end
= temp_string
;
5203 i
.types
[this_operand
] |= BaseIndex
;
5207 base_string
= end_op
;
5208 if (is_space_char (*base_string
))
5212 /* There may be an index reg or scale factor here. */
5213 if (*base_string
== ',')
5216 if (is_space_char (*base_string
))
5219 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5222 base_string
= end_op
;
5223 if (is_space_char (*base_string
))
5225 if (*base_string
== ',')
5228 if (is_space_char (*base_string
))
5231 else if (*base_string
!= ')')
5233 as_bad (_("expecting `,' or `)' "
5234 "after index register in `%s'"),
5239 else if (*base_string
== REGISTER_PREFIX
)
5241 as_bad (_("bad register name `%s'"), base_string
);
5245 /* Check for scale factor. */
5246 if (*base_string
!= ')')
5248 char *end_scale
= i386_scale (base_string
);
5253 base_string
= end_scale
;
5254 if (is_space_char (*base_string
))
5256 if (*base_string
!= ')')
5258 as_bad (_("expecting `)' "
5259 "after scale factor in `%s'"),
5264 else if (!i
.index_reg
)
5266 as_bad (_("expecting index register or scale factor "
5267 "after `,'; got '%c'"),
5272 else if (*base_string
!= ')')
5274 as_bad (_("expecting `,' or `)' "
5275 "after base register in `%s'"),
5280 else if (*base_string
== REGISTER_PREFIX
)
5282 as_bad (_("bad register name `%s'"), base_string
);
5287 /* If there's an expression beginning the operand, parse it,
5288 assuming displacement_string_start and
5289 displacement_string_end are meaningful. */
5290 if (displacement_string_start
!= displacement_string_end
)
5292 if (!i386_displacement (displacement_string_start
,
5293 displacement_string_end
))
5297 /* Special case for (%dx) while doing input/output op. */
5299 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5301 && i
.log2_scale_factor
== 0
5302 && i
.seg
[i
.mem_operands
] == 0
5303 && (i
.types
[this_operand
] & Disp
) == 0)
5305 i
.types
[this_operand
] = InOutPortReg
;
5309 if (i386_index_check (operand_string
) == 0)
5315 /* It's not a memory operand; argh! */
5316 as_bad (_("invalid char %s beginning operand %d `%s'"),
5317 output_invalid (*op_string
),
5322 return 1; /* Normal return. */
5325 /* md_estimate_size_before_relax()
5327 Called just before relax() for rs_machine_dependent frags. The x86
5328 assembler uses these frags to handle variable size jump
5331 Any symbol that is now undefined will not become defined.
5332 Return the correct fr_subtype in the frag.
5333 Return the initial "guess for variable size of frag" to caller.
5334 The guess is actually the growth beyond the fixed part. Whatever
5335 we do to grow the fixed or variable part contributes to our
5339 md_estimate_size_before_relax (fragP
, segment
)
5343 /* We've already got fragP->fr_subtype right; all we have to do is
5344 check for un-relaxable symbols. On an ELF system, we can't relax
5345 an externally visible symbol, because it may be overridden by a
5347 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5348 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5350 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5351 || S_IS_WEAK (fragP
->fr_symbol
)))
5355 /* Symbol is undefined in this segment, or we need to keep a
5356 reloc so that weak symbols can be overridden. */
5357 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5358 enum bfd_reloc_code_real reloc_type
;
5359 unsigned char *opcode
;
5362 if (fragP
->fr_var
!= NO_RELOC
)
5363 reloc_type
= fragP
->fr_var
;
5365 reloc_type
= BFD_RELOC_16_PCREL
;
5367 reloc_type
= BFD_RELOC_32_PCREL
;
5369 old_fr_fix
= fragP
->fr_fix
;
5370 opcode
= (unsigned char *) fragP
->fr_opcode
;
5372 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5375 /* Make jmp (0xeb) a (d)word displacement jump. */
5377 fragP
->fr_fix
+= size
;
5378 fix_new (fragP
, old_fr_fix
, size
,
5380 fragP
->fr_offset
, 1,
5386 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5388 /* Negate the condition, and branch past an
5389 unconditional jump. */
5392 /* Insert an unconditional jump. */
5394 /* We added two extra opcode bytes, and have a two byte
5396 fragP
->fr_fix
+= 2 + 2;
5397 fix_new (fragP
, old_fr_fix
+ 2, 2,
5399 fragP
->fr_offset
, 1,
5406 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5411 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5413 fragP
->fr_offset
, 1,
5415 fixP
->fx_signed
= 1;
5419 /* This changes the byte-displacement jump 0x7N
5420 to the (d)word-displacement jump 0x0f,0x8N. */
5421 opcode
[1] = opcode
[0] + 0x10;
5422 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5423 /* We've added an opcode byte. */
5424 fragP
->fr_fix
+= 1 + size
;
5425 fix_new (fragP
, old_fr_fix
+ 1, size
,
5427 fragP
->fr_offset
, 1,
5432 BAD_CASE (fragP
->fr_subtype
);
5436 return fragP
->fr_fix
- old_fr_fix
;
5439 /* Guess size depending on current relax state. Initially the relax
5440 state will correspond to a short jump and we return 1, because
5441 the variable part of the frag (the branch offset) is one byte
5442 long. However, we can relax a section more than once and in that
5443 case we must either set fr_subtype back to the unrelaxed state,
5444 or return the value for the appropriate branch. */
5445 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5448 /* Called after relax() is finished.
5450 In: Address of frag.
5451 fr_type == rs_machine_dependent.
5452 fr_subtype is what the address relaxed to.
5454 Out: Any fixSs and constants are set up.
5455 Caller will turn frag into a ".space 0". */
5458 md_convert_frag (abfd
, sec
, fragP
)
5459 bfd
*abfd ATTRIBUTE_UNUSED
;
5460 segT sec ATTRIBUTE_UNUSED
;
5463 unsigned char *opcode
;
5464 unsigned char *where_to_put_displacement
= NULL
;
5465 offsetT target_address
;
5466 offsetT opcode_address
;
5467 unsigned int extension
= 0;
5468 offsetT displacement_from_opcode_start
;
5470 opcode
= (unsigned char *) fragP
->fr_opcode
;
5472 /* Address we want to reach in file space. */
5473 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5475 /* Address opcode resides at in file space. */
5476 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5478 /* Displacement from opcode start to fill into instruction. */
5479 displacement_from_opcode_start
= target_address
- opcode_address
;
5481 if ((fragP
->fr_subtype
& BIG
) == 0)
5483 /* Don't have to change opcode. */
5484 extension
= 1; /* 1 opcode + 1 displacement */
5485 where_to_put_displacement
= &opcode
[1];
5489 if (no_cond_jump_promotion
5490 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5491 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5492 _("long jump required"));
5494 switch (fragP
->fr_subtype
)
5496 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5497 extension
= 4; /* 1 opcode + 4 displacement */
5499 where_to_put_displacement
= &opcode
[1];
5502 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5503 extension
= 2; /* 1 opcode + 2 displacement */
5505 where_to_put_displacement
= &opcode
[1];
5508 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5509 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5510 extension
= 5; /* 2 opcode + 4 displacement */
5511 opcode
[1] = opcode
[0] + 0x10;
5512 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5513 where_to_put_displacement
= &opcode
[2];
5516 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5517 extension
= 3; /* 2 opcode + 2 displacement */
5518 opcode
[1] = opcode
[0] + 0x10;
5519 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5520 where_to_put_displacement
= &opcode
[2];
5523 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5528 where_to_put_displacement
= &opcode
[3];
5532 BAD_CASE (fragP
->fr_subtype
);
5537 /* If size if less then four we are sure that the operand fits,
5538 but if it's 4, then it could be that the displacement is larger
5540 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5542 && ((addressT
) (displacement_from_opcode_start
- extension
5543 + ((addressT
) 1 << 31))
5544 > (((addressT
) 2 << 31) - 1)))
5546 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5547 _("jump target out of range"));
5548 /* Make us emit 0. */
5549 displacement_from_opcode_start
= extension
;
5551 /* Now put displacement after opcode. */
5552 md_number_to_chars ((char *) where_to_put_displacement
,
5553 (valueT
) (displacement_from_opcode_start
- extension
),
5554 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5555 fragP
->fr_fix
+= extension
;
5558 /* Size of byte displacement jmp. */
5559 int md_short_jump_size
= 2;
5561 /* Size of dword displacement jmp. */
5562 int md_long_jump_size
= 5;
5565 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5567 addressT from_addr
, to_addr
;
5568 fragS
*frag ATTRIBUTE_UNUSED
;
5569 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5573 offset
= to_addr
- (from_addr
+ 2);
5574 /* Opcode for byte-disp jump. */
5575 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5576 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5580 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5582 addressT from_addr
, to_addr
;
5583 fragS
*frag ATTRIBUTE_UNUSED
;
5584 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5588 offset
= to_addr
- (from_addr
+ 5);
5589 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5590 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5593 /* Apply a fixup (fixS) to segment data, once it has been determined
5594 by our caller that we have all the info we need to fix it up.
5596 On the 386, immediates, displacements, and data pointers are all in
5597 the same (little-endian) format, so we don't need to care about which
5601 md_apply_fix (fixP
, valP
, seg
)
5602 /* The fix we're to put in. */
5604 /* Pointer to the value of the bits. */
5606 /* Segment fix is from. */
5607 segT seg ATTRIBUTE_UNUSED
;
5609 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5610 valueT value
= *valP
;
5612 #if !defined (TE_Mach)
5615 switch (fixP
->fx_r_type
)
5621 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5624 case BFD_RELOC_X86_64_32S
:
5625 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5628 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5631 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5636 if (fixP
->fx_addsy
!= NULL
5637 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5638 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5639 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5640 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5641 && !use_rela_relocations
)
5643 /* This is a hack. There should be a better way to handle this.
5644 This covers for the fact that bfd_install_relocation will
5645 subtract the current location (for partial_inplace, PC relative
5646 relocations); see more below. */
5650 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5653 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5655 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5658 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5661 || (symbol_section_p (fixP
->fx_addsy
)
5662 && sym_seg
!= absolute_section
))
5663 && !generic_force_reloc (fixP
))
5665 /* Yes, we add the values in twice. This is because
5666 bfd_install_relocation subtracts them out again. I think
5667 bfd_install_relocation is broken, but I don't dare change
5669 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5673 #if defined (OBJ_COFF) && defined (TE_PE)
5674 /* For some reason, the PE format does not store a
5675 section address offset for a PC relative symbol. */
5676 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5677 || S_IS_WEAK (fixP
->fx_addsy
))
5678 value
+= md_pcrel_from (fixP
);
5682 /* Fix a few things - the dynamic linker expects certain values here,
5683 and we must not disappoint it. */
5684 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5685 if (IS_ELF
&& fixP
->fx_addsy
)
5686 switch (fixP
->fx_r_type
)
5688 case BFD_RELOC_386_PLT32
:
5689 case BFD_RELOC_X86_64_PLT32
:
5690 /* Make the jump instruction point to the address of the operand. At
5691 runtime we merely add the offset to the actual PLT entry. */
5695 case BFD_RELOC_386_TLS_GD
:
5696 case BFD_RELOC_386_TLS_LDM
:
5697 case BFD_RELOC_386_TLS_IE_32
:
5698 case BFD_RELOC_386_TLS_IE
:
5699 case BFD_RELOC_386_TLS_GOTIE
:
5700 case BFD_RELOC_386_TLS_GOTDESC
:
5701 case BFD_RELOC_X86_64_TLSGD
:
5702 case BFD_RELOC_X86_64_TLSLD
:
5703 case BFD_RELOC_X86_64_GOTTPOFF
:
5704 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5705 value
= 0; /* Fully resolved at runtime. No addend. */
5707 case BFD_RELOC_386_TLS_LE
:
5708 case BFD_RELOC_386_TLS_LDO_32
:
5709 case BFD_RELOC_386_TLS_LE_32
:
5710 case BFD_RELOC_X86_64_DTPOFF32
:
5711 case BFD_RELOC_X86_64_DTPOFF64
:
5712 case BFD_RELOC_X86_64_TPOFF32
:
5713 case BFD_RELOC_X86_64_TPOFF64
:
5714 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5717 case BFD_RELOC_386_TLS_DESC_CALL
:
5718 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5719 value
= 0; /* Fully resolved at runtime. No addend. */
5720 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5724 case BFD_RELOC_386_GOT32
:
5725 case BFD_RELOC_X86_64_GOT32
:
5726 value
= 0; /* Fully resolved at runtime. No addend. */
5729 case BFD_RELOC_VTABLE_INHERIT
:
5730 case BFD_RELOC_VTABLE_ENTRY
:
5737 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5739 #endif /* !defined (TE_Mach) */
5741 /* Are we finished with this relocation now? */
5742 if (fixP
->fx_addsy
== NULL
)
5744 else if (use_rela_relocations
)
5746 fixP
->fx_no_overflow
= 1;
5747 /* Remember value for tc_gen_reloc. */
5748 fixP
->fx_addnumber
= value
;
5752 md_number_to_chars (p
, value
, fixP
->fx_size
);
5755 #define MAX_LITTLENUMS 6
5757 /* Turn the string pointed to by litP into a floating point constant
5758 of type TYPE, and emit the appropriate bytes. The number of
5759 LITTLENUMS emitted is stored in *SIZEP. An error message is
5760 returned, or NULL on OK. */
5763 md_atof (type
, litP
, sizeP
)
5769 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5770 LITTLENUM_TYPE
*wordP
;
5792 return _("Bad call to md_atof ()");
5794 t
= atof_ieee (input_line_pointer
, type
, words
);
5796 input_line_pointer
= t
;
5798 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5799 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5800 the bigendian 386. */
5801 for (wordP
= words
+ prec
- 1; prec
--;)
5803 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5804 litP
+= sizeof (LITTLENUM_TYPE
);
5809 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5812 output_invalid (int c
)
5815 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5818 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5819 "(0x%x)", (unsigned char) c
);
5820 return output_invalid_buf
;
5823 /* REG_STRING starts *before* REGISTER_PREFIX. */
5825 static const reg_entry
*
5826 parse_real_register (char *reg_string
, char **end_op
)
5828 char *s
= reg_string
;
5830 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5833 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5834 if (*s
== REGISTER_PREFIX
)
5837 if (is_space_char (*s
))
5841 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5843 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5844 return (const reg_entry
*) NULL
;
5848 /* For naked regs, make sure that we are not dealing with an identifier.
5849 This prevents confusing an identifier like `eax_var' with register
5851 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5852 return (const reg_entry
*) NULL
;
5856 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5858 /* Handle floating point regs, allowing spaces in the (i) part. */
5859 if (r
== i386_regtab
/* %st is first entry of table */)
5861 if (is_space_char (*s
))
5866 if (is_space_char (*s
))
5868 if (*s
>= '0' && *s
<= '7')
5872 if (is_space_char (*s
))
5877 r
= hash_find (reg_hash
, "st(0)");
5882 /* We have "%st(" then garbage. */
5883 return (const reg_entry
*) NULL
;
5888 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5889 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5890 && flag_code
!= CODE_64BIT
)
5891 return (const reg_entry
*) NULL
;
5896 /* REG_STRING starts *before* REGISTER_PREFIX. */
5898 static const reg_entry
*
5899 parse_register (char *reg_string
, char **end_op
)
5903 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5904 r
= parse_real_register (reg_string
, end_op
);
5909 char *save
= input_line_pointer
;
5913 input_line_pointer
= reg_string
;
5914 c
= get_symbol_end ();
5915 symbolP
= symbol_find (reg_string
);
5916 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5918 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5920 know (e
->X_op
== O_register
);
5921 know (e
->X_add_number
>= 0
5922 && (valueT
) e
->X_add_number
< i386_regtab_size
);
5923 r
= i386_regtab
+ e
->X_add_number
;
5924 *end_op
= input_line_pointer
;
5926 *input_line_pointer
= c
;
5927 input_line_pointer
= save
;
5933 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5936 char *end
= input_line_pointer
;
5939 r
= parse_register (name
, &input_line_pointer
);
5940 if (r
&& end
<= input_line_pointer
)
5942 *nextcharP
= *input_line_pointer
;
5943 *input_line_pointer
= 0;
5944 e
->X_op
= O_register
;
5945 e
->X_add_number
= r
- i386_regtab
;
5948 input_line_pointer
= end
;
5954 md_operand (expressionS
*e
)
5956 if (*input_line_pointer
== REGISTER_PREFIX
)
5959 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5963 e
->X_op
= O_register
;
5964 e
->X_add_number
= r
- i386_regtab
;
5965 input_line_pointer
= end
;
5971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5972 const char *md_shortopts
= "kVQ:sqn";
5974 const char *md_shortopts
= "qn";
5977 #define OPTION_32 (OPTION_MD_BASE + 0)
5978 #define OPTION_64 (OPTION_MD_BASE + 1)
5979 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5980 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5981 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5983 struct option md_longopts
[] =
5985 {"32", no_argument
, NULL
, OPTION_32
},
5986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5987 {"64", no_argument
, NULL
, OPTION_64
},
5989 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5990 {"march", required_argument
, NULL
, OPTION_MARCH
},
5991 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5992 {NULL
, no_argument
, NULL
, 0}
5994 size_t md_longopts_size
= sizeof (md_longopts
);
5997 md_parse_option (int c
, char *arg
)
6004 optimize_align_code
= 0;
6011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6012 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6013 should be emitted or not. FIXME: Not implemented. */
6017 /* -V: SVR4 argument to print version ID. */
6019 print_version_id ();
6022 /* -k: Ignore for FreeBSD compatibility. */
6027 /* -s: On i386 Solaris, this tells the native assembler to use
6028 .stab instead of .stab.excl. We always use .stab anyhow. */
6031 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6034 const char **list
, **l
;
6036 list
= bfd_target_list ();
6037 for (l
= list
; *l
!= NULL
; l
++)
6038 if (CONST_STRNEQ (*l
, "elf64-x86-64")
6039 || strcmp (*l
, "coff-x86-64") == 0
6040 || strcmp (*l
, "pe-x86-64") == 0
6041 || strcmp (*l
, "pei-x86-64") == 0)
6043 default_arch
= "x86_64";
6047 as_fatal (_("No compiled in support for x86_64"));
6054 default_arch
= "i386";
6058 #ifdef SVR4_COMMENT_CHARS
6063 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
6065 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
6069 i386_comment_chars
= n
;
6076 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6077 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6079 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6081 cpu_arch_isa
= cpu_arch
[i
].type
;
6082 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
6083 if (!cpu_arch_tune_set
)
6085 cpu_arch_tune
= cpu_arch_isa
;
6086 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
6091 if (i
>= ARRAY_SIZE (cpu_arch
))
6092 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6097 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6098 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6100 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6102 cpu_arch_tune_set
= 1;
6103 cpu_arch_tune
= cpu_arch
[i
].type
;
6104 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
6108 if (i
>= ARRAY_SIZE (cpu_arch
))
6109 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6119 md_show_usage (stream
)
6122 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6123 fprintf (stream
, _("\
6125 -V print assembler version number\n\
6128 fprintf (stream
, _("\
6129 -n Do not optimize code alignment\n\
6130 -q quieten some warnings\n"));
6131 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6132 fprintf (stream
, _("\
6135 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6136 fprintf (stream
, _("\
6137 --32/--64 generate 32bit/64bit code\n"));
6139 #ifdef SVR4_COMMENT_CHARS
6140 fprintf (stream
, _("\
6141 --divide do not treat `/' as a comment character\n"));
6143 fprintf (stream
, _("\
6144 --divide ignored\n"));
6146 fprintf (stream
, _("\
6147 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6148 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6149 core, core2, k6, athlon, k8, generic32, generic64\n"));
6153 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6154 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
6156 /* Pick the target format to use. */
6159 i386_target_format (void)
6161 if (!strcmp (default_arch
, "x86_64"))
6163 set_code_flag (CODE_64BIT
);
6164 if (cpu_arch_isa_flags
== 0)
6165 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6166 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6168 if (cpu_arch_tune_flags
== 0)
6169 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6170 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6173 else if (!strcmp (default_arch
, "i386"))
6175 set_code_flag (CODE_32BIT
);
6176 if (cpu_arch_isa_flags
== 0)
6177 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6178 if (cpu_arch_tune_flags
== 0)
6179 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6182 as_fatal (_("Unknown architecture"));
6183 switch (OUTPUT_FLAVOR
)
6186 case bfd_target_coff_flavour
:
6187 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
6190 #ifdef OBJ_MAYBE_AOUT
6191 case bfd_target_aout_flavour
:
6192 return AOUT_TARGET_FORMAT
;
6194 #ifdef OBJ_MAYBE_COFF
6195 case bfd_target_coff_flavour
:
6198 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6199 case bfd_target_elf_flavour
:
6201 if (flag_code
== CODE_64BIT
)
6204 use_rela_relocations
= 1;
6206 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6215 #endif /* OBJ_MAYBE_ more than one */
6217 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6219 i386_elf_emit_arch_note (void)
6221 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6224 asection
*seg
= now_seg
;
6225 subsegT subseg
= now_subseg
;
6226 Elf_Internal_Note i_note
;
6227 Elf_External_Note e_note
;
6228 asection
*note_secp
;
6231 /* Create the .note section. */
6232 note_secp
= subseg_new (".note", 0);
6233 bfd_set_section_flags (stdoutput
,
6235 SEC_HAS_CONTENTS
| SEC_READONLY
);
6237 /* Process the arch string. */
6238 len
= strlen (cpu_arch_name
);
6240 i_note
.namesz
= len
+ 1;
6242 i_note
.type
= NT_ARCH
;
6243 p
= frag_more (sizeof (e_note
.namesz
));
6244 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6245 p
= frag_more (sizeof (e_note
.descsz
));
6246 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6247 p
= frag_more (sizeof (e_note
.type
));
6248 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6249 p
= frag_more (len
+ 1);
6250 strcpy (p
, cpu_arch_name
);
6252 frag_align (2, 0, 0);
6254 subseg_set (seg
, subseg
);
6260 md_undefined_symbol (name
)
6263 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6264 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6265 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6266 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6270 if (symbol_find (name
))
6271 as_bad (_("GOT already in symbol table"));
6272 GOT_symbol
= symbol_new (name
, undefined_section
,
6273 (valueT
) 0, &zero_address_frag
);
6280 /* Round up a section size to the appropriate boundary. */
6283 md_section_align (segment
, size
)
6284 segT segment ATTRIBUTE_UNUSED
;
6287 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6288 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6290 /* For a.out, force the section size to be aligned. If we don't do
6291 this, BFD will align it for us, but it will not write out the
6292 final bytes of the section. This may be a bug in BFD, but it is
6293 easier to fix it here since that is how the other a.out targets
6297 align
= bfd_get_section_alignment (stdoutput
, segment
);
6298 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6305 /* On the i386, PC-relative offsets are relative to the start of the
6306 next instruction. That is, the address of the offset, plus its
6307 size, since the offset is always the last part of the insn. */
6310 md_pcrel_from (fixS
*fixP
)
6312 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6318 s_bss (int ignore ATTRIBUTE_UNUSED
)
6322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6324 obj_elf_section_change_hook ();
6326 temp
= get_absolute_expression ();
6327 subseg_set (bss_section
, (subsegT
) temp
);
6328 demand_empty_rest_of_line ();
6334 i386_validate_fix (fixS
*fixp
)
6336 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6338 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6342 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6347 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6349 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6356 tc_gen_reloc (section
, fixp
)
6357 asection
*section ATTRIBUTE_UNUSED
;
6361 bfd_reloc_code_real_type code
;
6363 switch (fixp
->fx_r_type
)
6365 case BFD_RELOC_X86_64_PLT32
:
6366 case BFD_RELOC_X86_64_GOT32
:
6367 case BFD_RELOC_X86_64_GOTPCREL
:
6368 case BFD_RELOC_386_PLT32
:
6369 case BFD_RELOC_386_GOT32
:
6370 case BFD_RELOC_386_GOTOFF
:
6371 case BFD_RELOC_386_GOTPC
:
6372 case BFD_RELOC_386_TLS_GD
:
6373 case BFD_RELOC_386_TLS_LDM
:
6374 case BFD_RELOC_386_TLS_LDO_32
:
6375 case BFD_RELOC_386_TLS_IE_32
:
6376 case BFD_RELOC_386_TLS_IE
:
6377 case BFD_RELOC_386_TLS_GOTIE
:
6378 case BFD_RELOC_386_TLS_LE_32
:
6379 case BFD_RELOC_386_TLS_LE
:
6380 case BFD_RELOC_386_TLS_GOTDESC
:
6381 case BFD_RELOC_386_TLS_DESC_CALL
:
6382 case BFD_RELOC_X86_64_TLSGD
:
6383 case BFD_RELOC_X86_64_TLSLD
:
6384 case BFD_RELOC_X86_64_DTPOFF32
:
6385 case BFD_RELOC_X86_64_DTPOFF64
:
6386 case BFD_RELOC_X86_64_GOTTPOFF
:
6387 case BFD_RELOC_X86_64_TPOFF32
:
6388 case BFD_RELOC_X86_64_TPOFF64
:
6389 case BFD_RELOC_X86_64_GOTOFF64
:
6390 case BFD_RELOC_X86_64_GOTPC32
:
6391 case BFD_RELOC_X86_64_GOT64
:
6392 case BFD_RELOC_X86_64_GOTPCREL64
:
6393 case BFD_RELOC_X86_64_GOTPC64
:
6394 case BFD_RELOC_X86_64_GOTPLT64
:
6395 case BFD_RELOC_X86_64_PLTOFF64
:
6396 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6397 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6399 case BFD_RELOC_VTABLE_ENTRY
:
6400 case BFD_RELOC_VTABLE_INHERIT
:
6402 case BFD_RELOC_32_SECREL
:
6404 code
= fixp
->fx_r_type
;
6406 case BFD_RELOC_X86_64_32S
:
6407 if (!fixp
->fx_pcrel
)
6409 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6410 code
= fixp
->fx_r_type
;
6416 switch (fixp
->fx_size
)
6419 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6420 _("can not do %d byte pc-relative relocation"),
6422 code
= BFD_RELOC_32_PCREL
;
6424 case 1: code
= BFD_RELOC_8_PCREL
; break;
6425 case 2: code
= BFD_RELOC_16_PCREL
; break;
6426 case 4: code
= BFD_RELOC_32_PCREL
; break;
6428 case 8: code
= BFD_RELOC_64_PCREL
; break;
6434 switch (fixp
->fx_size
)
6437 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6438 _("can not do %d byte relocation"),
6440 code
= BFD_RELOC_32
;
6442 case 1: code
= BFD_RELOC_8
; break;
6443 case 2: code
= BFD_RELOC_16
; break;
6444 case 4: code
= BFD_RELOC_32
; break;
6446 case 8: code
= BFD_RELOC_64
; break;
6453 if ((code
== BFD_RELOC_32
6454 || code
== BFD_RELOC_32_PCREL
6455 || code
== BFD_RELOC_X86_64_32S
)
6457 && fixp
->fx_addsy
== GOT_symbol
)
6460 code
= BFD_RELOC_386_GOTPC
;
6462 code
= BFD_RELOC_X86_64_GOTPC32
;
6464 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6466 && fixp
->fx_addsy
== GOT_symbol
)
6468 code
= BFD_RELOC_X86_64_GOTPC64
;
6471 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6472 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6473 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6475 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6477 if (!use_rela_relocations
)
6479 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6480 vtable entry to be used in the relocation's section offset. */
6481 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6482 rel
->address
= fixp
->fx_offset
;
6486 /* Use the rela in 64bit mode. */
6489 if (!fixp
->fx_pcrel
)
6490 rel
->addend
= fixp
->fx_offset
;
6494 case BFD_RELOC_X86_64_PLT32
:
6495 case BFD_RELOC_X86_64_GOT32
:
6496 case BFD_RELOC_X86_64_GOTPCREL
:
6497 case BFD_RELOC_X86_64_TLSGD
:
6498 case BFD_RELOC_X86_64_TLSLD
:
6499 case BFD_RELOC_X86_64_GOTTPOFF
:
6500 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6501 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6502 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6505 rel
->addend
= (section
->vma
6507 + fixp
->fx_addnumber
6508 + md_pcrel_from (fixp
));
6513 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6514 if (rel
->howto
== NULL
)
6516 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6517 _("cannot represent relocation type %s"),
6518 bfd_get_reloc_code_name (code
));
6519 /* Set howto to a garbage value so that we can keep going. */
6520 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6521 assert (rel
->howto
!= NULL
);
6528 /* Parse operands using Intel syntax. This implements a recursive descent
6529 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6532 FIXME: We do not recognize the full operand grammar defined in the MASM
6533 documentation. In particular, all the structure/union and
6534 high-level macro operands are missing.
6536 Uppercase words are terminals, lower case words are non-terminals.
6537 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6538 bars '|' denote choices. Most grammar productions are implemented in
6539 functions called 'intel_<production>'.
6541 Initial production is 'expr'.
6547 binOp & | AND | \| | OR | ^ | XOR
6549 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6551 constant digits [[ radixOverride ]]
6553 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6591 => expr expr cmpOp e04
6594 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6595 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6597 hexdigit a | b | c | d | e | f
6598 | A | B | C | D | E | F
6604 mulOp * | / | % | MOD | << | SHL | >> | SHR
6608 register specialRegister
6612 segmentRegister CS | DS | ES | FS | GS | SS
6614 specialRegister CR0 | CR2 | CR3 | CR4
6615 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6616 | TR3 | TR4 | TR5 | TR6 | TR7
6618 We simplify the grammar in obvious places (e.g., register parsing is
6619 done by calling parse_register) and eliminate immediate left recursion
6620 to implement a recursive-descent parser.
6624 expr' cmpOp e04 expr'
6675 /* Parsing structure for the intel syntax parser. Used to implement the
6676 semantic actions for the operand grammar. */
6677 struct intel_parser_s
6679 char *op_string
; /* The string being parsed. */
6680 int got_a_float
; /* Whether the operand is a float. */
6681 int op_modifier
; /* Operand modifier. */
6682 int is_mem
; /* 1 if operand is memory reference. */
6683 int in_offset
; /* >=1 if parsing operand of offset. */
6684 int in_bracket
; /* >=1 if parsing operand in brackets. */
6685 const reg_entry
*reg
; /* Last register reference found. */
6686 char *disp
; /* Displacement string being built. */
6687 char *next_operand
; /* Resume point when splitting operands. */
6690 static struct intel_parser_s intel_parser
;
6692 /* Token structure for parsing intel syntax. */
6695 int code
; /* Token code. */
6696 const reg_entry
*reg
; /* Register entry for register tokens. */
6697 char *str
; /* String representation. */
6700 static struct intel_token cur_token
, prev_token
;
6702 /* Token codes for the intel parser. Since T_SHORT is already used
6703 by COFF, undefine it first to prevent a warning. */
6722 /* Prototypes for intel parser functions. */
6723 static int intel_match_token (int);
6724 static void intel_putback_token (void);
6725 static void intel_get_token (void);
6726 static int intel_expr (void);
6727 static int intel_e04 (void);
6728 static int intel_e05 (void);
6729 static int intel_e06 (void);
6730 static int intel_e09 (void);
6731 static int intel_e10 (void);
6732 static int intel_e11 (void);
6735 i386_intel_operand (char *operand_string
, int got_a_float
)
6740 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6741 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6745 /* Initialize token holders. */
6746 cur_token
.code
= prev_token
.code
= T_NIL
;
6747 cur_token
.reg
= prev_token
.reg
= NULL
;
6748 cur_token
.str
= prev_token
.str
= NULL
;
6750 /* Initialize parser structure. */
6751 intel_parser
.got_a_float
= got_a_float
;
6752 intel_parser
.op_modifier
= 0;
6753 intel_parser
.is_mem
= 0;
6754 intel_parser
.in_offset
= 0;
6755 intel_parser
.in_bracket
= 0;
6756 intel_parser
.reg
= NULL
;
6757 intel_parser
.disp
[0] = '\0';
6758 intel_parser
.next_operand
= NULL
;
6760 /* Read the first token and start the parser. */
6762 ret
= intel_expr ();
6767 if (cur_token
.code
!= T_NIL
)
6769 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6770 current_templates
->start
->name
, cur_token
.str
);
6773 /* If we found a memory reference, hand it over to i386_displacement
6774 to fill in the rest of the operand fields. */
6775 else if (intel_parser
.is_mem
)
6777 if ((i
.mem_operands
== 1
6778 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6779 || i
.mem_operands
== 2)
6781 as_bad (_("too many memory references for '%s'"),
6782 current_templates
->start
->name
);
6787 char *s
= intel_parser
.disp
;
6790 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6791 /* See the comments in intel_bracket_expr. */
6792 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6794 /* Add the displacement expression. */
6796 ret
= i386_displacement (s
, s
+ strlen (s
));
6799 /* Swap base and index in 16-bit memory operands like
6800 [si+bx]. Since i386_index_check is also used in AT&T
6801 mode we have to do that here. */
6804 && (i
.base_reg
->reg_type
& Reg16
)
6805 && (i
.index_reg
->reg_type
& Reg16
)
6806 && i
.base_reg
->reg_num
>= 6
6807 && i
.index_reg
->reg_num
< 6)
6809 const reg_entry
*base
= i
.index_reg
;
6811 i
.index_reg
= i
.base_reg
;
6814 ret
= i386_index_check (operand_string
);
6819 /* Constant and OFFSET expressions are handled by i386_immediate. */
6820 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6821 || intel_parser
.reg
== NULL
)
6822 ret
= i386_immediate (intel_parser
.disp
);
6824 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6826 if (!ret
|| !intel_parser
.next_operand
)
6828 intel_parser
.op_string
= intel_parser
.next_operand
;
6829 this_operand
= i
.operands
++;
6833 free (intel_parser
.disp
);
6838 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6842 expr' cmpOp e04 expr'
6847 /* XXX Implement the comparison operators. */
6848 return intel_e04 ();
6865 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6866 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6868 if (cur_token
.code
== '+')
6870 else if (cur_token
.code
== '-')
6871 nregs
= NUM_ADDRESS_REGS
;
6875 strcat (intel_parser
.disp
, cur_token
.str
);
6876 intel_match_token (cur_token
.code
);
6887 int nregs
= ~NUM_ADDRESS_REGS
;
6894 if (cur_token
.code
== '&'
6895 || cur_token
.code
== '|'
6896 || cur_token
.code
== '^')
6900 str
[0] = cur_token
.code
;
6902 strcat (intel_parser
.disp
, str
);
6907 intel_match_token (cur_token
.code
);
6912 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6913 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6924 int nregs
= ~NUM_ADDRESS_REGS
;
6931 if (cur_token
.code
== '*'
6932 || cur_token
.code
== '/'
6933 || cur_token
.code
== '%')
6937 str
[0] = cur_token
.code
;
6939 strcat (intel_parser
.disp
, str
);
6941 else if (cur_token
.code
== T_SHL
)
6942 strcat (intel_parser
.disp
, "<<");
6943 else if (cur_token
.code
== T_SHR
)
6944 strcat (intel_parser
.disp
, ">>");
6948 intel_match_token (cur_token
.code
);
6953 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6954 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6972 int nregs
= ~NUM_ADDRESS_REGS
;
6977 /* Don't consume constants here. */
6978 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6980 /* Need to look one token ahead - if the next token
6981 is a constant, the current token is its sign. */
6984 intel_match_token (cur_token
.code
);
6985 next_code
= cur_token
.code
;
6986 intel_putback_token ();
6987 if (next_code
== T_CONST
)
6991 /* e09 OFFSET e09 */
6992 if (cur_token
.code
== T_OFFSET
)
6995 ++intel_parser
.in_offset
;
6999 else if (cur_token
.code
== T_SHORT
)
7000 intel_parser
.op_modifier
|= 1 << T_SHORT
;
7003 else if (cur_token
.code
== '+')
7004 strcat (intel_parser
.disp
, "+");
7009 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
7015 str
[0] = cur_token
.code
;
7017 strcat (intel_parser
.disp
, str
);
7024 intel_match_token (cur_token
.code
);
7032 /* e09' PTR e10 e09' */
7033 if (cur_token
.code
== T_PTR
)
7037 if (prev_token
.code
== T_BYTE
)
7038 suffix
= BYTE_MNEM_SUFFIX
;
7040 else if (prev_token
.code
== T_WORD
)
7042 if (current_templates
->start
->name
[0] == 'l'
7043 && current_templates
->start
->name
[2] == 's'
7044 && current_templates
->start
->name
[3] == 0)
7045 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7046 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
7047 suffix
= SHORT_MNEM_SUFFIX
;
7049 suffix
= WORD_MNEM_SUFFIX
;
7052 else if (prev_token
.code
== T_DWORD
)
7054 if (current_templates
->start
->name
[0] == 'l'
7055 && current_templates
->start
->name
[2] == 's'
7056 && current_templates
->start
->name
[3] == 0)
7057 suffix
= WORD_MNEM_SUFFIX
;
7058 else if (flag_code
== CODE_16BIT
7059 && (current_templates
->start
->opcode_modifier
7060 & (Jump
| JumpDword
)))
7061 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7062 else if (intel_parser
.got_a_float
== 1) /* "f..." */
7063 suffix
= SHORT_MNEM_SUFFIX
;
7065 suffix
= LONG_MNEM_SUFFIX
;
7068 else if (prev_token
.code
== T_FWORD
)
7070 if (current_templates
->start
->name
[0] == 'l'
7071 && current_templates
->start
->name
[2] == 's'
7072 && current_templates
->start
->name
[3] == 0)
7073 suffix
= LONG_MNEM_SUFFIX
;
7074 else if (!intel_parser
.got_a_float
)
7076 if (flag_code
== CODE_16BIT
)
7077 add_prefix (DATA_PREFIX_OPCODE
);
7078 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7081 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7084 else if (prev_token
.code
== T_QWORD
)
7086 if (intel_parser
.got_a_float
== 1) /* "f..." */
7087 suffix
= LONG_MNEM_SUFFIX
;
7089 suffix
= QWORD_MNEM_SUFFIX
;
7092 else if (prev_token
.code
== T_TBYTE
)
7094 if (intel_parser
.got_a_float
== 1)
7095 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7097 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7100 else if (prev_token
.code
== T_XMMWORD
)
7102 /* XXX ignored for now, but accepted since gcc uses it */
7108 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7112 /* Operands for jump/call using 'ptr' notation denote absolute
7114 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7115 i
.types
[this_operand
] |= JumpAbsolute
;
7117 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7121 else if (i
.suffix
!= suffix
)
7123 as_bad (_("Conflicting operand modifiers"));
7129 /* e09' : e10 e09' */
7130 else if (cur_token
.code
== ':')
7132 if (prev_token
.code
!= T_REG
)
7134 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7135 segment/group identifier (which we don't have), using comma
7136 as the operand separator there is even less consistent, since
7137 there all branches only have a single operand. */
7138 if (this_operand
!= 0
7139 || intel_parser
.in_offset
7140 || intel_parser
.in_bracket
7141 || (!(current_templates
->start
->opcode_modifier
7142 & (Jump
|JumpDword
|JumpInterSegment
))
7143 && !(current_templates
->start
->operand_types
[0]
7145 return intel_match_token (T_NIL
);
7146 /* Remember the start of the 2nd operand and terminate 1st
7148 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7149 another expression), but it gets at least the simplest case
7150 (a plain number or symbol on the left side) right. */
7151 intel_parser
.next_operand
= intel_parser
.op_string
;
7152 *--intel_parser
.op_string
= '\0';
7153 return intel_match_token (':');
7161 intel_match_token (cur_token
.code
);
7167 --intel_parser
.in_offset
;
7170 if (NUM_ADDRESS_REGS
> nregs
)
7172 as_bad (_("Invalid operand to `OFFSET'"));
7175 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7178 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7179 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7184 intel_bracket_expr (void)
7186 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7187 const char *start
= intel_parser
.op_string
;
7190 if (i
.op
[this_operand
].regs
)
7191 return intel_match_token (T_NIL
);
7193 intel_match_token ('[');
7195 /* Mark as a memory operand only if it's not already known to be an
7196 offset expression. If it's an offset expression, we need to keep
7198 if (!intel_parser
.in_offset
)
7200 ++intel_parser
.in_bracket
;
7202 /* Operands for jump/call inside brackets denote absolute addresses. */
7203 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7204 i
.types
[this_operand
] |= JumpAbsolute
;
7206 /* Unfortunately gas always diverged from MASM in a respect that can't
7207 be easily fixed without risking to break code sequences likely to be
7208 encountered (the testsuite even check for this): MASM doesn't consider
7209 an expression inside brackets unconditionally as a memory reference.
7210 When that is e.g. a constant, an offset expression, or the sum of the
7211 two, this is still taken as a constant load. gas, however, always
7212 treated these as memory references. As a compromise, we'll try to make
7213 offset expressions inside brackets work the MASM way (since that's
7214 less likely to be found in real world code), but make constants alone
7215 continue to work the traditional gas way. In either case, issue a
7217 intel_parser
.op_modifier
&= ~was_offset
;
7220 strcat (intel_parser
.disp
, "[");
7222 /* Add a '+' to the displacement string if necessary. */
7223 if (*intel_parser
.disp
!= '\0'
7224 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7225 strcat (intel_parser
.disp
, "+");
7228 && (len
= intel_parser
.op_string
- start
- 1,
7229 intel_match_token (']')))
7231 /* Preserve brackets when the operand is an offset expression. */
7232 if (intel_parser
.in_offset
)
7233 strcat (intel_parser
.disp
, "]");
7236 --intel_parser
.in_bracket
;
7237 if (i
.base_reg
|| i
.index_reg
)
7238 intel_parser
.is_mem
= 1;
7239 if (!intel_parser
.is_mem
)
7241 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7242 /* Defer the warning until all of the operand was parsed. */
7243 intel_parser
.is_mem
= -1;
7244 else if (!quiet_warnings
)
7245 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7246 len
, start
, len
, start
);
7249 intel_parser
.op_modifier
|= was_offset
;
7266 while (cur_token
.code
== '[')
7268 if (!intel_bracket_expr ())
7293 switch (cur_token
.code
)
7297 intel_match_token ('(');
7298 strcat (intel_parser
.disp
, "(");
7300 if (intel_expr () && intel_match_token (')'))
7302 strcat (intel_parser
.disp
, ")");
7309 return intel_bracket_expr ();
7314 strcat (intel_parser
.disp
, cur_token
.str
);
7315 intel_match_token (cur_token
.code
);
7317 /* Mark as a memory operand only if it's not already known to be an
7318 offset expression. */
7319 if (!intel_parser
.in_offset
)
7320 intel_parser
.is_mem
= 1;
7327 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7329 intel_match_token (T_REG
);
7331 /* Check for segment change. */
7332 if (cur_token
.code
== ':')
7334 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7336 as_bad (_("`%s' is not a valid segment register"),
7340 else if (i
.seg
[i
.mem_operands
])
7341 as_warn (_("Extra segment override ignored"));
7344 if (!intel_parser
.in_offset
)
7345 intel_parser
.is_mem
= 1;
7346 switch (reg
->reg_num
)
7349 i
.seg
[i
.mem_operands
] = &es
;
7352 i
.seg
[i
.mem_operands
] = &cs
;
7355 i
.seg
[i
.mem_operands
] = &ss
;
7358 i
.seg
[i
.mem_operands
] = &ds
;
7361 i
.seg
[i
.mem_operands
] = &fs
;
7364 i
.seg
[i
.mem_operands
] = &gs
;
7370 /* Not a segment register. Check for register scaling. */
7371 else if (cur_token
.code
== '*')
7373 if (!intel_parser
.in_bracket
)
7375 as_bad (_("Register scaling only allowed in memory operands"));
7379 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7380 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7381 else if (i
.index_reg
)
7382 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7384 /* What follows must be a valid scale. */
7385 intel_match_token ('*');
7387 i
.types
[this_operand
] |= BaseIndex
;
7389 /* Set the scale after setting the register (otherwise,
7390 i386_scale will complain) */
7391 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7393 char *str
, sign
= cur_token
.code
;
7394 intel_match_token (cur_token
.code
);
7395 if (cur_token
.code
!= T_CONST
)
7397 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7401 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7402 strcpy (str
+ 1, cur_token
.str
);
7404 if (!i386_scale (str
))
7408 else if (!i386_scale (cur_token
.str
))
7410 intel_match_token (cur_token
.code
);
7413 /* No scaling. If this is a memory operand, the register is either a
7414 base register (first occurrence) or an index register (second
7416 else if (intel_parser
.in_bracket
)
7421 else if (!i
.index_reg
)
7425 as_bad (_("Too many register references in memory operand"));
7429 i
.types
[this_operand
] |= BaseIndex
;
7432 /* It's neither base nor index. */
7433 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7435 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7436 i
.op
[this_operand
].regs
= reg
;
7441 as_bad (_("Invalid use of register"));
7445 /* Since registers are not part of the displacement string (except
7446 when we're parsing offset operands), we may need to remove any
7447 preceding '+' from the displacement string. */
7448 if (*intel_parser
.disp
!= '\0'
7449 && !intel_parser
.in_offset
)
7451 char *s
= intel_parser
.disp
;
7452 s
+= strlen (s
) - 1;
7475 intel_match_token (cur_token
.code
);
7477 if (cur_token
.code
== T_PTR
)
7480 /* It must have been an identifier. */
7481 intel_putback_token ();
7482 cur_token
.code
= T_ID
;
7488 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7492 /* The identifier represents a memory reference only if it's not
7493 preceded by an offset modifier and if it's not an equate. */
7494 symbolP
= symbol_find(cur_token
.str
);
7495 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7496 intel_parser
.is_mem
= 1;
7504 char *save_str
, sign
= 0;
7506 /* Allow constants that start with `+' or `-'. */
7507 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7509 sign
= cur_token
.code
;
7510 intel_match_token (cur_token
.code
);
7511 if (cur_token
.code
!= T_CONST
)
7513 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7519 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7520 strcpy (save_str
+ !!sign
, cur_token
.str
);
7524 /* Get the next token to check for register scaling. */
7525 intel_match_token (cur_token
.code
);
7527 /* Check if this constant is a scaling factor for an
7529 if (cur_token
.code
== '*')
7531 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7533 const reg_entry
*reg
= cur_token
.reg
;
7535 if (!intel_parser
.in_bracket
)
7537 as_bad (_("Register scaling only allowed "
7538 "in memory operands"));
7542 /* Disallow things like [1*si].
7543 sp and esp are invalid as index. */
7544 if (reg
->reg_type
& Reg16
)
7545 reg
= i386_regtab
+ REGNAM_AX
+ 4;
7546 else if (i
.index_reg
)
7547 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
7549 /* The constant is followed by `* reg', so it must be
7552 i
.types
[this_operand
] |= BaseIndex
;
7554 /* Set the scale after setting the register (otherwise,
7555 i386_scale will complain) */
7556 if (!i386_scale (save_str
))
7558 intel_match_token (T_REG
);
7560 /* Since registers are not part of the displacement
7561 string, we may need to remove any preceding '+' from
7562 the displacement string. */
7563 if (*intel_parser
.disp
!= '\0')
7565 char *s
= intel_parser
.disp
;
7566 s
+= strlen (s
) - 1;
7576 /* The constant was not used for register scaling. Since we have
7577 already consumed the token following `*' we now need to put it
7578 back in the stream. */
7579 intel_putback_token ();
7582 /* Add the constant to the displacement string. */
7583 strcat (intel_parser
.disp
, save_str
);
7590 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7594 /* Match the given token against cur_token. If they match, read the next
7595 token from the operand string. */
7597 intel_match_token (int code
)
7599 if (cur_token
.code
== code
)
7606 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7611 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7613 intel_get_token (void)
7616 const reg_entry
*reg
;
7617 struct intel_token new_token
;
7619 new_token
.code
= T_NIL
;
7620 new_token
.reg
= NULL
;
7621 new_token
.str
= NULL
;
7623 /* Free the memory allocated to the previous token and move
7624 cur_token to prev_token. */
7626 free (prev_token
.str
);
7628 prev_token
= cur_token
;
7630 /* Skip whitespace. */
7631 while (is_space_char (*intel_parser
.op_string
))
7632 intel_parser
.op_string
++;
7634 /* Return an empty token if we find nothing else on the line. */
7635 if (*intel_parser
.op_string
== '\0')
7637 cur_token
= new_token
;
7641 /* The new token cannot be larger than the remainder of the operand
7643 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7644 new_token
.str
[0] = '\0';
7646 if (strchr ("0123456789", *intel_parser
.op_string
))
7648 char *p
= new_token
.str
;
7649 char *q
= intel_parser
.op_string
;
7650 new_token
.code
= T_CONST
;
7652 /* Allow any kind of identifier char to encompass floating point and
7653 hexadecimal numbers. */
7654 while (is_identifier_char (*q
))
7658 /* Recognize special symbol names [0-9][bf]. */
7659 if (strlen (intel_parser
.op_string
) == 2
7660 && (intel_parser
.op_string
[1] == 'b'
7661 || intel_parser
.op_string
[1] == 'f'))
7662 new_token
.code
= T_ID
;
7665 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7667 size_t len
= end_op
- intel_parser
.op_string
;
7669 new_token
.code
= T_REG
;
7670 new_token
.reg
= reg
;
7672 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7673 new_token
.str
[len
] = '\0';
7676 else if (is_identifier_char (*intel_parser
.op_string
))
7678 char *p
= new_token
.str
;
7679 char *q
= intel_parser
.op_string
;
7681 /* A '.' or '$' followed by an identifier char is an identifier.
7682 Otherwise, it's operator '.' followed by an expression. */
7683 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7685 new_token
.code
= '.';
7686 new_token
.str
[0] = '.';
7687 new_token
.str
[1] = '\0';
7691 while (is_identifier_char (*q
) || *q
== '@')
7695 if (strcasecmp (new_token
.str
, "NOT") == 0)
7696 new_token
.code
= '~';
7698 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7699 new_token
.code
= '%';
7701 else if (strcasecmp (new_token
.str
, "AND") == 0)
7702 new_token
.code
= '&';
7704 else if (strcasecmp (new_token
.str
, "OR") == 0)
7705 new_token
.code
= '|';
7707 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7708 new_token
.code
= '^';
7710 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7711 new_token
.code
= T_SHL
;
7713 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7714 new_token
.code
= T_SHR
;
7716 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7717 new_token
.code
= T_BYTE
;
7719 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7720 new_token
.code
= T_WORD
;
7722 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7723 new_token
.code
= T_DWORD
;
7725 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7726 new_token
.code
= T_FWORD
;
7728 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7729 new_token
.code
= T_QWORD
;
7731 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7732 /* XXX remove (gcc still uses it) */
7733 || strcasecmp (new_token
.str
, "XWORD") == 0)
7734 new_token
.code
= T_TBYTE
;
7736 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7737 || strcasecmp (new_token
.str
, "OWORD") == 0)
7738 new_token
.code
= T_XMMWORD
;
7740 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7741 new_token
.code
= T_PTR
;
7743 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7744 new_token
.code
= T_SHORT
;
7746 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7748 new_token
.code
= T_OFFSET
;
7750 /* ??? This is not mentioned in the MASM grammar but gcc
7751 makes use of it with -mintel-syntax. OFFSET may be
7752 followed by FLAT: */
7753 if (strncasecmp (q
, " FLAT:", 6) == 0)
7754 strcat (new_token
.str
, " FLAT:");
7757 /* ??? This is not mentioned in the MASM grammar. */
7758 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7760 new_token
.code
= T_OFFSET
;
7762 strcat (new_token
.str
, ":");
7764 as_bad (_("`:' expected"));
7768 new_token
.code
= T_ID
;
7772 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7774 new_token
.code
= *intel_parser
.op_string
;
7775 new_token
.str
[0] = *intel_parser
.op_string
;
7776 new_token
.str
[1] = '\0';
7779 else if (strchr ("<>", *intel_parser
.op_string
)
7780 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7782 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7783 new_token
.str
[0] = *intel_parser
.op_string
;
7784 new_token
.str
[1] = *intel_parser
.op_string
;
7785 new_token
.str
[2] = '\0';
7789 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7791 intel_parser
.op_string
+= strlen (new_token
.str
);
7792 cur_token
= new_token
;
7795 /* Put cur_token back into the token stream and make cur_token point to
7798 intel_putback_token (void)
7800 if (cur_token
.code
!= T_NIL
)
7802 intel_parser
.op_string
-= strlen (cur_token
.str
);
7803 free (cur_token
.str
);
7805 cur_token
= prev_token
;
7807 /* Forget prev_token. */
7808 prev_token
.code
= T_NIL
;
7809 prev_token
.reg
= NULL
;
7810 prev_token
.str
= NULL
;
7814 tc_x86_regname_to_dw2regnum (char *regname
)
7816 unsigned int regnum
;
7817 unsigned int regnames_count
;
7818 static const char *const regnames_32
[] =
7820 "eax", "ecx", "edx", "ebx",
7821 "esp", "ebp", "esi", "edi",
7822 "eip", "eflags", NULL
,
7823 "st0", "st1", "st2", "st3",
7824 "st4", "st5", "st6", "st7",
7826 "xmm0", "xmm1", "xmm2", "xmm3",
7827 "xmm4", "xmm5", "xmm6", "xmm7",
7828 "mm0", "mm1", "mm2", "mm3",
7829 "mm4", "mm5", "mm6", "mm7",
7830 "fcw", "fsw", "mxcsr",
7831 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7834 static const char *const regnames_64
[] =
7836 "rax", "rdx", "rcx", "rbx",
7837 "rsi", "rdi", "rbp", "rsp",
7838 "r8", "r9", "r10", "r11",
7839 "r12", "r13", "r14", "r15",
7841 "xmm0", "xmm1", "xmm2", "xmm3",
7842 "xmm4", "xmm5", "xmm6", "xmm7",
7843 "xmm8", "xmm9", "xmm10", "xmm11",
7844 "xmm12", "xmm13", "xmm14", "xmm15",
7845 "st0", "st1", "st2", "st3",
7846 "st4", "st5", "st6", "st7",
7847 "mm0", "mm1", "mm2", "mm3",
7848 "mm4", "mm5", "mm6", "mm7",
7850 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7851 "fs.base", "gs.base", NULL
, NULL
,
7853 "mxcsr", "fcw", "fsw"
7855 const char *const *regnames
;
7857 if (flag_code
== CODE_64BIT
)
7859 regnames
= regnames_64
;
7860 regnames_count
= ARRAY_SIZE (regnames_64
);
7864 regnames
= regnames_32
;
7865 regnames_count
= ARRAY_SIZE (regnames_32
);
7868 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7869 if (regnames
[regnum
] != NULL
7870 && strcmp (regname
, regnames
[regnum
]) == 0)
7877 tc_x86_frame_initial_instructions (void)
7879 static unsigned int sp_regno
;
7882 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7885 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7886 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7890 i386_elf_section_type (const char *str
, size_t len
)
7892 if (flag_code
== CODE_64BIT
7893 && len
== sizeof ("unwind") - 1
7894 && strncmp (str
, "unwind", 6) == 0)
7895 return SHT_X86_64_UNWIND
;
7902 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7906 expr
.X_op
= O_secrel
;
7907 expr
.X_add_symbol
= symbol
;
7908 expr
.X_add_number
= 0;
7909 emit_expr (&expr
, size
);
7913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7914 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7917 x86_64_section_letter (int letter
, char **ptr_msg
)
7919 if (flag_code
== CODE_64BIT
)
7922 return SHF_X86_64_LARGE
;
7924 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7927 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7932 x86_64_section_word (char *str
, size_t len
)
7934 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7935 return SHF_X86_64_LARGE
;
7941 handle_large_common (int small ATTRIBUTE_UNUSED
)
7943 if (flag_code
!= CODE_64BIT
)
7945 s_comm_internal (0, elf_common_parse
);
7946 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7950 static segT lbss_section
;
7951 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7952 asection
*saved_bss_section
= bss_section
;
7954 if (lbss_section
== NULL
)
7956 flagword applicable
;
7958 subsegT subseg
= now_subseg
;
7960 /* The .lbss section is for local .largecomm symbols. */
7961 lbss_section
= subseg_new (".lbss", 0);
7962 applicable
= bfd_applicable_section_flags (stdoutput
);
7963 bfd_set_section_flags (stdoutput
, lbss_section
,
7964 applicable
& SEC_ALLOC
);
7965 seg_info (lbss_section
)->bss
= 1;
7967 subseg_set (seg
, subseg
);
7970 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7971 bss_section
= lbss_section
;
7973 s_comm_internal (0, elf_common_parse
);
7975 elf_com_section_ptr
= saved_com_section_ptr
;
7976 bss_section
= saved_bss_section
;
7979 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */