1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
53 #define RELOC_ENUM enum bfd_reloc_code_real
55 #define RELOC_ENUM int
59 #define DEFAULT_ARCH "i386"
64 #define INLINE __inline__
70 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
71 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
72 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
73 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
74 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
75 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
76 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
77 static int smallest_imm_type
PARAMS ((offsetT
));
78 static offsetT offset_in_range
PARAMS ((offsetT
, int));
79 static int add_prefix
PARAMS ((unsigned int));
80 static void set_code_flag
PARAMS ((int));
81 static void set_16bit_gcc_code_flag
PARAMS ((int));
82 static void set_intel_syntax
PARAMS ((int));
83 static void set_cpu_arch
PARAMS ((int));
84 static char *output_invalid
PARAMS ((int c
));
85 static int i386_operand
PARAMS ((char *operand_string
));
86 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
87 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
89 static char *parse_insn
PARAMS ((char *, char *));
90 static char *parse_operands
PARAMS ((char *, const char *));
91 static void swap_operands
PARAMS ((void));
92 static void optimize_imm
PARAMS ((void));
93 static void optimize_disp
PARAMS ((void));
94 static int match_template
PARAMS ((void));
95 static int check_string
PARAMS ((void));
96 static int process_suffix
PARAMS ((void));
97 static int check_byte_reg
PARAMS ((void));
98 static int check_long_reg
PARAMS ((void));
99 static int check_qword_reg
PARAMS ((void));
100 static int check_word_reg
PARAMS ((void));
101 static int finalize_imm
PARAMS ((void));
102 static int process_operands
PARAMS ((void));
103 static const seg_entry
*build_modrm_byte
PARAMS ((void));
104 static void output_insn
PARAMS ((void));
105 static void output_branch
PARAMS ((void));
106 static void output_jump
PARAMS ((void));
107 static void output_interseg_jump
PARAMS ((void));
108 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
109 offsetT insn_start_off
));
110 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
111 offsetT insn_start_off
));
113 static void s_bss
PARAMS ((int));
116 static const char *default_arch
= DEFAULT_ARCH
;
118 /* 'md_assemble ()' gathers together information and puts it into a
125 const reg_entry
*regs
;
130 /* TM holds the template for the insn were currently assembling. */
133 /* SUFFIX holds the instruction mnemonic suffix if given.
134 (e.g. 'l' for 'movl') */
137 /* OPERANDS gives the number of given operands. */
138 unsigned int operands
;
140 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
141 of given register, displacement, memory operands and immediate
143 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
145 /* TYPES [i] is the type (see above #defines) which tells us how to
146 use OP[i] for the corresponding operand. */
147 unsigned int types
[MAX_OPERANDS
];
149 /* Displacement expression, immediate expression, or register for each
151 union i386_op op
[MAX_OPERANDS
];
153 /* Flags for operands. */
154 unsigned int flags
[MAX_OPERANDS
];
155 #define Operand_PCrel 1
157 /* Relocation type for operand */
158 RELOC_ENUM reloc
[MAX_OPERANDS
];
160 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
161 the base index byte below. */
162 const reg_entry
*base_reg
;
163 const reg_entry
*index_reg
;
164 unsigned int log2_scale_factor
;
166 /* SEG gives the seg_entries of this insn. They are zero unless
167 explicit segment overrides are given. */
168 const seg_entry
*seg
[2];
170 /* PREFIX holds all the given prefix opcodes (usually null).
171 PREFIXES is the number of prefix opcodes. */
172 unsigned int prefixes
;
173 unsigned char prefix
[MAX_PREFIXES
];
175 /* RM and SIB are the modrm byte and the sib byte where the
176 addressing modes of this insn are encoded. */
183 typedef struct _i386_insn i386_insn
;
185 /* List of chars besides those in app.c:symbol_chars that can start an
186 operand. Used to prevent the scrubber eating vital white-space. */
188 const char extra_symbol_chars
[] = "*%-(@[";
190 const char extra_symbol_chars
[] = "*%-([";
193 #if (defined (TE_I386AIX) \
194 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
195 && !defined (TE_LINUX) \
196 && !defined (TE_FreeBSD) \
197 && !defined (TE_NetBSD)))
198 /* This array holds the chars that always start a comment. If the
199 pre-processor is disabled, these aren't very useful. */
200 const char comment_chars
[] = "#/";
201 #define PREFIX_SEPARATOR '\\'
203 /* This array holds the chars that only start a comment at the beginning of
204 a line. If the line seems to have the form '# 123 filename'
205 .line and .file directives will appear in the pre-processed output.
206 Note that input_file.c hand checks for '#' at the beginning of the
207 first line of the input file. This is because the compiler outputs
208 #NO_APP at the beginning of its output.
209 Also note that comments started like this one will always work if
210 '/' isn't otherwise defined. */
211 const char line_comment_chars
[] = "#";
214 /* Putting '/' here makes it impossible to use the divide operator.
215 However, we need it for compatibility with SVR4 systems. */
216 const char comment_chars
[] = "#";
217 #define PREFIX_SEPARATOR '/'
219 const char line_comment_chars
[] = "/#";
222 const char line_separator_chars
[] = ";";
224 /* Chars that can be used to separate mant from exp in floating point
226 const char EXP_CHARS
[] = "eE";
228 /* Chars that mean this number is a floating point constant
231 const char FLT_CHARS
[] = "fFdDxX";
233 /* Tables for lexical analysis. */
234 static char mnemonic_chars
[256];
235 static char register_chars
[256];
236 static char operand_chars
[256];
237 static char identifier_chars
[256];
238 static char digit_chars
[256];
240 /* Lexical macros. */
241 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
242 #define is_operand_char(x) (operand_chars[(unsigned char) x])
243 #define is_register_char(x) (register_chars[(unsigned char) x])
244 #define is_space_char(x) ((x) == ' ')
245 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
246 #define is_digit_char(x) (digit_chars[(unsigned char) x])
248 /* All non-digit non-letter charcters that may occur in an operand. */
249 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
251 /* md_assemble() always leaves the strings it's passed unaltered. To
252 effect this we maintain a stack of saved characters that we've smashed
253 with '\0's (indicating end of strings for various sub-fields of the
254 assembler instruction). */
255 static char save_stack
[32];
256 static char *save_stack_p
;
257 #define END_STRING_AND_SAVE(s) \
258 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
259 #define RESTORE_END_STRING(s) \
260 do { *(s) = *--save_stack_p; } while (0)
262 /* The instruction we're assembling. */
265 /* Possible templates for current insn. */
266 static const templates
*current_templates
;
268 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
269 static expressionS disp_expressions
[2], im_expressions
[2];
271 /* Current operand we are working on. */
272 static int this_operand
;
274 /* We support four different modes. FLAG_CODE variable is used to distinguish
281 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
283 static enum flag_code flag_code
;
284 static int use_rela_relocations
= 0;
286 /* The names used to print error messages. */
287 static const char *flag_code_names
[] =
294 /* 1 for intel syntax,
296 static int intel_syntax
= 0;
298 /* 1 if register prefix % not required. */
299 static int allow_naked_reg
= 0;
301 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
302 leave, push, and pop instructions so that gcc has the same stack
303 frame as in 32 bit mode. */
304 static char stackop_size
= '\0';
306 /* Non-zero to quieten some warnings. */
307 static int quiet_warnings
= 0;
310 static const char *cpu_arch_name
= NULL
;
312 /* CPU feature flags. */
313 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
315 /* If set, conditional jumps are not automatically promoted to handle
316 larger than a byte offset. */
317 static unsigned int no_cond_jump_promotion
= 0;
319 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
322 /* Interface to relax_segment.
323 There are 3 major relax states for 386 jump insns because the
324 different types of jumps add different sizes to frags when we're
325 figuring out what sort of jump to choose to reach a given label. */
328 #define UNCOND_JUMP 0
330 #define COND_JUMP86 2
335 #define SMALL16 (SMALL | CODE16)
337 #define BIG16 (BIG | CODE16)
341 #define INLINE __inline__
347 #define ENCODE_RELAX_STATE(type, size) \
348 ((relax_substateT) (((type) << 2) | (size)))
349 #define TYPE_FROM_RELAX_STATE(s) \
351 #define DISP_SIZE_FROM_RELAX_STATE(s) \
352 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
354 /* This table is used by relax_frag to promote short jumps to long
355 ones where necessary. SMALL (short) jumps may be promoted to BIG
356 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
357 don't allow a short jump in a 32 bit code segment to be promoted to
358 a 16 bit offset jump because it's slower (requires data size
359 prefix), and doesn't work, unless the destination is in the bottom
360 64k of the code segment (The top 16 bits of eip are zeroed). */
362 const relax_typeS md_relax_table
[] =
365 1) most positive reach of this state,
366 2) most negative reach of this state,
367 3) how many bytes this mode will have in the variable part of the frag
368 4) which index into the table to try if we can't fit into this one. */
370 /* UNCOND_JUMP states. */
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
372 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
373 /* dword jmp adds 4 bytes to frag:
374 0 extra opcode bytes, 4 displacement bytes. */
376 /* word jmp adds 2 byte2 to frag:
377 0 extra opcode bytes, 2 displacement bytes. */
380 /* COND_JUMP states. */
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
382 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
383 /* dword conditionals adds 5 bytes to frag:
384 1 extra opcode byte, 4 displacement bytes. */
386 /* word conditionals add 3 bytes to frag:
387 1 extra opcode byte, 2 displacement bytes. */
390 /* COND_JUMP86 states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
393 /* dword conditionals adds 5 bytes to frag:
394 1 extra opcode byte, 4 displacement bytes. */
396 /* word conditionals add 4 bytes to frag:
397 1 displacement byte and a 3 byte long branch insn. */
401 static const arch_entry cpu_arch
[] = {
403 {"i186", Cpu086
|Cpu186
},
404 {"i286", Cpu086
|Cpu186
|Cpu286
},
405 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
406 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
407 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
408 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
409 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
410 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
411 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
412 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
413 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
414 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
418 const pseudo_typeS md_pseudo_table
[] =
420 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
421 {"align", s_align_bytes
, 0},
423 {"align", s_align_ptwo
, 0},
425 {"arch", set_cpu_arch
, 0},
429 {"ffloat", float_cons
, 'f'},
430 {"dfloat", float_cons
, 'd'},
431 {"tfloat", float_cons
, 'x'},
433 {"noopt", s_ignore
, 0},
434 {"optim", s_ignore
, 0},
435 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
436 {"code16", set_code_flag
, CODE_16BIT
},
437 {"code32", set_code_flag
, CODE_32BIT
},
438 {"code64", set_code_flag
, CODE_64BIT
},
439 {"intel_syntax", set_intel_syntax
, 1},
440 {"att_syntax", set_intel_syntax
, 0},
441 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
442 {"loc", dwarf2_directive_loc
, 0},
446 /* For interface with expression (). */
447 extern char *input_line_pointer
;
449 /* Hash table for instruction mnemonic lookup. */
450 static struct hash_control
*op_hash
;
452 /* Hash table for register lookup. */
453 static struct hash_control
*reg_hash
;
456 i386_align_code (fragP
, count
)
460 /* Various efficient no-op patterns for aligning code labels.
461 Note: Don't try to assemble the instructions in the comments.
462 0L and 0w are not legal. */
463 static const char f32_1
[] =
465 static const char f32_2
[] =
466 {0x89,0xf6}; /* movl %esi,%esi */
467 static const char f32_3
[] =
468 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
469 static const char f32_4
[] =
470 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_5
[] =
473 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
474 static const char f32_6
[] =
475 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
476 static const char f32_7
[] =
477 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_8
[] =
480 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
481 static const char f32_9
[] =
482 {0x89,0xf6, /* movl %esi,%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_10
[] =
485 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_11
[] =
488 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
489 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
490 static const char f32_12
[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
493 static const char f32_13
[] =
494 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_14
[] =
497 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
498 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
499 static const char f32_15
[] =
500 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
501 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
502 static const char f16_3
[] =
503 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
504 static const char f16_4
[] =
505 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_5
[] =
508 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
509 static const char f16_6
[] =
510 {0x89,0xf6, /* mov %si,%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_7
[] =
513 {0x8d,0x74,0x00, /* lea 0(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char f16_8
[] =
516 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
517 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
518 static const char *const f32_patt
[] = {
519 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
520 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
522 static const char *const f16_patt
[] = {
523 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
524 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
527 if (count
<= 0 || count
> 15)
530 /* The recommended way to pad 64bit code is to use NOPs preceded by
531 maximally four 0x66 prefixes. Balance the size of nops. */
532 if (flag_code
== CODE_64BIT
)
535 int nnops
= (count
+ 3) / 4;
536 int len
= count
/ nnops
;
537 int remains
= count
- nnops
* len
;
540 for (i
= 0; i
< remains
; i
++)
542 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
543 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
546 for (; i
< nnops
; i
++)
548 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
549 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
554 if (flag_code
== CODE_16BIT
)
556 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
557 f16_patt
[count
- 1], count
);
559 /* Adjust jump offset. */
560 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
563 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
564 f32_patt
[count
- 1], count
);
565 fragP
->fr_var
= count
;
568 static INLINE
unsigned int
569 mode_from_disp_size (t
)
572 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
576 fits_in_signed_byte (num
)
579 return (num
>= -128) && (num
<= 127);
583 fits_in_unsigned_byte (num
)
586 return (num
& 0xff) == num
;
590 fits_in_unsigned_word (num
)
593 return (num
& 0xffff) == num
;
597 fits_in_signed_word (num
)
600 return (-32768 <= num
) && (num
<= 32767);
603 fits_in_signed_long (num
)
604 offsetT num ATTRIBUTE_UNUSED
;
609 return (!(((offsetT
) -1 << 31) & num
)
610 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
612 } /* fits_in_signed_long() */
614 fits_in_unsigned_long (num
)
615 offsetT num ATTRIBUTE_UNUSED
;
620 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
622 } /* fits_in_unsigned_long() */
625 smallest_imm_type (num
)
628 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
630 /* This code is disabled on the 486 because all the Imm1 forms
631 in the opcode table are slower on the i486. They're the
632 versions with the implicitly specified single-position
633 displacement, which has another syntax if you really want to
636 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
638 return (fits_in_signed_byte (num
)
639 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
640 : fits_in_unsigned_byte (num
)
641 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
642 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
643 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
644 : fits_in_signed_long (num
)
645 ? (Imm32
| Imm32S
| Imm64
)
646 : fits_in_unsigned_long (num
)
652 offset_in_range (val
, size
)
660 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
661 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
662 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
664 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
669 /* If BFD64, sign extend val. */
670 if (!use_rela_relocations
)
671 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
672 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
674 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
676 char buf1
[40], buf2
[40];
678 sprint_value (buf1
, val
);
679 sprint_value (buf2
, val
& mask
);
680 as_warn (_("%s shortened to %s"), buf1
, buf2
);
685 /* Returns 0 if attempting to add a prefix where one from the same
686 class already exists, 1 if non rep/repne added, 2 if rep/repne
695 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
696 && flag_code
== CODE_64BIT
)
704 case CS_PREFIX_OPCODE
:
705 case DS_PREFIX_OPCODE
:
706 case ES_PREFIX_OPCODE
:
707 case FS_PREFIX_OPCODE
:
708 case GS_PREFIX_OPCODE
:
709 case SS_PREFIX_OPCODE
:
713 case REPNE_PREFIX_OPCODE
:
714 case REPE_PREFIX_OPCODE
:
717 case LOCK_PREFIX_OPCODE
:
725 case ADDR_PREFIX_OPCODE
:
729 case DATA_PREFIX_OPCODE
:
734 if (i
.prefix
[q
] != 0)
736 as_bad (_("same type of prefix used twice"));
741 i
.prefix
[q
] = prefix
;
746 set_code_flag (value
)
750 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
751 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
752 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
754 as_bad (_("64bit mode not supported on this CPU."));
756 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
758 as_bad (_("32bit mode not supported on this CPU."));
764 set_16bit_gcc_code_flag (new_code_flag
)
767 flag_code
= new_code_flag
;
768 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
769 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
774 set_intel_syntax (syntax_flag
)
777 /* Find out if register prefixing is specified. */
778 int ask_naked_reg
= 0;
781 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
783 char *string
= input_line_pointer
;
784 int e
= get_symbol_end ();
786 if (strcmp (string
, "prefix") == 0)
788 else if (strcmp (string
, "noprefix") == 0)
791 as_bad (_("bad argument to syntax directive."));
792 *input_line_pointer
= e
;
794 demand_empty_rest_of_line ();
796 intel_syntax
= syntax_flag
;
798 if (ask_naked_reg
== 0)
801 allow_naked_reg
= (intel_syntax
802 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
804 /* Conservative default. */
809 allow_naked_reg
= (ask_naked_reg
< 0);
814 int dummy ATTRIBUTE_UNUSED
;
818 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
820 char *string
= input_line_pointer
;
821 int e
= get_symbol_end ();
824 for (i
= 0; cpu_arch
[i
].name
; i
++)
826 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
828 cpu_arch_name
= cpu_arch
[i
].name
;
829 cpu_arch_flags
= (cpu_arch
[i
].flags
830 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
834 if (!cpu_arch
[i
].name
)
835 as_bad (_("no such architecture: `%s'"), string
);
837 *input_line_pointer
= e
;
840 as_bad (_("missing cpu architecture"));
842 no_cond_jump_promotion
= 0;
843 if (*input_line_pointer
== ','
844 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
846 char *string
= ++input_line_pointer
;
847 int e
= get_symbol_end ();
849 if (strcmp (string
, "nojumps") == 0)
850 no_cond_jump_promotion
= 1;
851 else if (strcmp (string
, "jumps") == 0)
854 as_bad (_("no such architecture modifier: `%s'"), string
);
856 *input_line_pointer
= e
;
859 demand_empty_rest_of_line ();
866 if (!strcmp (default_arch
, "x86_64"))
867 return bfd_mach_x86_64
;
868 else if (!strcmp (default_arch
, "i386"))
869 return bfd_mach_i386_i386
;
871 as_fatal (_("Unknown architecture"));
878 const char *hash_err
;
880 /* Initialize op_hash hash table. */
881 op_hash
= hash_new ();
884 const template *optab
;
885 templates
*core_optab
;
887 /* Setup for loop. */
889 core_optab
= (templates
*) xmalloc (sizeof (templates
));
890 core_optab
->start
= optab
;
895 if (optab
->name
== NULL
896 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
898 /* different name --> ship out current template list;
899 add to hash table; & begin anew. */
900 core_optab
->end
= optab
;
901 hash_err
= hash_insert (op_hash
,
906 as_fatal (_("Internal Error: Can't hash %s: %s"),
910 if (optab
->name
== NULL
)
912 core_optab
= (templates
*) xmalloc (sizeof (templates
));
913 core_optab
->start
= optab
;
918 /* Initialize reg_hash hash table. */
919 reg_hash
= hash_new ();
921 const reg_entry
*regtab
;
923 for (regtab
= i386_regtab
;
924 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
927 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
929 as_fatal (_("Internal Error: Can't hash %s: %s"),
935 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
940 for (c
= 0; c
< 256; c
++)
945 mnemonic_chars
[c
] = c
;
946 register_chars
[c
] = c
;
947 operand_chars
[c
] = c
;
949 else if (ISLOWER (c
))
951 mnemonic_chars
[c
] = c
;
952 register_chars
[c
] = c
;
953 operand_chars
[c
] = c
;
955 else if (ISUPPER (c
))
957 mnemonic_chars
[c
] = TOLOWER (c
);
958 register_chars
[c
] = mnemonic_chars
[c
];
959 operand_chars
[c
] = c
;
962 if (ISALPHA (c
) || ISDIGIT (c
))
963 identifier_chars
[c
] = c
;
966 identifier_chars
[c
] = c
;
967 operand_chars
[c
] = c
;
972 identifier_chars
['@'] = '@';
974 digit_chars
['-'] = '-';
975 identifier_chars
['_'] = '_';
976 identifier_chars
['.'] = '.';
978 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
979 operand_chars
[(unsigned char) *p
] = *p
;
982 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
983 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
985 record_alignment (text_section
, 2);
986 record_alignment (data_section
, 2);
987 record_alignment (bss_section
, 2);
993 i386_print_statistics (file
)
996 hash_print_statistics (file
, "i386 opcode", op_hash
);
997 hash_print_statistics (file
, "i386 register", reg_hash
);
1002 /* Debugging routines for md_assemble. */
1003 static void pi
PARAMS ((char *, i386_insn
*));
1004 static void pte
PARAMS ((template *));
1005 static void pt
PARAMS ((unsigned int));
1006 static void pe
PARAMS ((expressionS
*));
1007 static void ps
PARAMS ((symbolS
*));
1016 fprintf (stdout
, "%s: template ", line
);
1018 fprintf (stdout
, " address: base %s index %s scale %x\n",
1019 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1020 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1021 x
->log2_scale_factor
);
1022 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1023 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1024 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1025 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1026 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1027 (x
->rex
& REX_MODE64
) != 0,
1028 (x
->rex
& REX_EXTX
) != 0,
1029 (x
->rex
& REX_EXTY
) != 0,
1030 (x
->rex
& REX_EXTZ
) != 0);
1031 for (i
= 0; i
< x
->operands
; i
++)
1033 fprintf (stdout
, " #%d: ", i
+ 1);
1035 fprintf (stdout
, "\n");
1037 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1038 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1039 if (x
->types
[i
] & Imm
)
1041 if (x
->types
[i
] & Disp
)
1042 pe (x
->op
[i
].disps
);
1051 fprintf (stdout
, " %d operands ", t
->operands
);
1052 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1053 if (t
->extension_opcode
!= None
)
1054 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1055 if (t
->opcode_modifier
& D
)
1056 fprintf (stdout
, "D");
1057 if (t
->opcode_modifier
& W
)
1058 fprintf (stdout
, "W");
1059 fprintf (stdout
, "\n");
1060 for (i
= 0; i
< t
->operands
; i
++)
1062 fprintf (stdout
, " #%d type ", i
+ 1);
1063 pt (t
->operand_types
[i
]);
1064 fprintf (stdout
, "\n");
1072 fprintf (stdout
, " operation %d\n", e
->X_op
);
1073 fprintf (stdout
, " add_number %ld (%lx)\n",
1074 (long) e
->X_add_number
, (long) e
->X_add_number
);
1075 if (e
->X_add_symbol
)
1077 fprintf (stdout
, " add_symbol ");
1078 ps (e
->X_add_symbol
);
1079 fprintf (stdout
, "\n");
1083 fprintf (stdout
, " op_symbol ");
1084 ps (e
->X_op_symbol
);
1085 fprintf (stdout
, "\n");
1093 fprintf (stdout
, "%s type %s%s",
1095 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1096 segment_name (S_GET_SEGMENT (s
)));
1105 static const type_names
[] =
1118 { BaseIndex
, "BaseIndex" },
1122 { Disp32S
, "d32s" },
1124 { InOutPortReg
, "InOutPortReg" },
1125 { ShiftCount
, "ShiftCount" },
1126 { Control
, "control reg" },
1127 { Test
, "test reg" },
1128 { Debug
, "debug reg" },
1129 { FloatReg
, "FReg" },
1130 { FloatAcc
, "FAcc" },
1134 { JumpAbsolute
, "Jump Absolute" },
1145 const struct type_name
*ty
;
1147 for (ty
= type_names
; ty
->mask
; ty
++)
1149 fprintf (stdout
, "%s, ", ty
->tname
);
1153 #endif /* DEBUG386 */
1155 #ifdef BFD_ASSEMBLER
1156 static bfd_reloc_code_real_type reloc
1157 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1159 static bfd_reloc_code_real_type
1160 reloc (size
, pcrel
, sign
, other
)
1164 bfd_reloc_code_real_type other
;
1166 if (other
!= NO_RELOC
)
1172 as_bad (_("There are no unsigned pc-relative relocations"));
1175 case 1: return BFD_RELOC_8_PCREL
;
1176 case 2: return BFD_RELOC_16_PCREL
;
1177 case 4: return BFD_RELOC_32_PCREL
;
1179 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1186 case 4: return BFD_RELOC_X86_64_32S
;
1191 case 1: return BFD_RELOC_8
;
1192 case 2: return BFD_RELOC_16
;
1193 case 4: return BFD_RELOC_32
;
1194 case 8: return BFD_RELOC_64
;
1196 as_bad (_("can not do %s %d byte relocation"),
1197 sign
? "signed" : "unsigned", size
);
1201 return BFD_RELOC_NONE
;
1204 /* Here we decide which fixups can be adjusted to make them relative to
1205 the beginning of the section instead of the symbol. Basically we need
1206 to make sure that the dynamic relocations are done correctly, so in
1207 some cases we force the original symbol to be used. */
1210 tc_i386_fix_adjustable (fixP
)
1211 fixS
*fixP ATTRIBUTE_UNUSED
;
1213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1214 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1217 /* Don't adjust pc-relative references to merge sections in 64-bit
1219 if (use_rela_relocations
1220 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1224 /* adjust_reloc_syms doesn't know about the GOT. */
1225 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1226 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1227 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1228 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1229 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1230 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1231 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1232 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1233 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1234 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1235 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1236 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1237 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1238 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1239 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1240 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1241 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1242 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1243 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1244 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1245 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1251 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1252 #define BFD_RELOC_8 0
1253 #define BFD_RELOC_16 0
1254 #define BFD_RELOC_32 0
1255 #define BFD_RELOC_8_PCREL 0
1256 #define BFD_RELOC_16_PCREL 0
1257 #define BFD_RELOC_32_PCREL 0
1258 #define BFD_RELOC_386_PLT32 0
1259 #define BFD_RELOC_386_GOT32 0
1260 #define BFD_RELOC_386_GOTOFF 0
1261 #define BFD_RELOC_386_TLS_GD 0
1262 #define BFD_RELOC_386_TLS_LDM 0
1263 #define BFD_RELOC_386_TLS_LDO_32 0
1264 #define BFD_RELOC_386_TLS_IE_32 0
1265 #define BFD_RELOC_386_TLS_IE 0
1266 #define BFD_RELOC_386_TLS_GOTIE 0
1267 #define BFD_RELOC_386_TLS_LE_32 0
1268 #define BFD_RELOC_386_TLS_LE 0
1269 #define BFD_RELOC_X86_64_PLT32 0
1270 #define BFD_RELOC_X86_64_GOT32 0
1271 #define BFD_RELOC_X86_64_GOTPCREL 0
1272 #define BFD_RELOC_X86_64_TLSGD 0
1273 #define BFD_RELOC_X86_64_TLSLD 0
1274 #define BFD_RELOC_X86_64_DTPOFF32 0
1275 #define BFD_RELOC_X86_64_GOTTPOFF 0
1276 #define BFD_RELOC_X86_64_TPOFF32 0
1279 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1282 intel_float_operand (mnemonic
)
1283 const char *mnemonic
;
1285 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1288 if (mnemonic
[0] == 'f')
1294 /* This is the guts of the machine-dependent assembler. LINE points to a
1295 machine dependent instruction. This function is supposed to emit
1296 the frags/bytes it assembles to. */
1303 char mnemonic
[MAX_MNEM_SIZE
];
1305 /* Initialize globals. */
1306 memset (&i
, '\0', sizeof (i
));
1307 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1308 i
.reloc
[j
] = NO_RELOC
;
1309 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1310 memset (im_expressions
, '\0', sizeof (im_expressions
));
1311 save_stack_p
= save_stack
;
1313 /* First parse an instruction mnemonic & call i386_operand for the operands.
1314 We assume that the scrubber has arranged it so that line[0] is the valid
1315 start of a (possibly prefixed) mnemonic. */
1317 line
= parse_insn (line
, mnemonic
);
1321 line
= parse_operands (line
, mnemonic
);
1325 /* Now we've parsed the mnemonic into a set of templates, and have the
1326 operands at hand. */
1328 /* All intel opcodes have reversed operands except for "bound" and
1329 "enter". We also don't reverse intersegment "jmp" and "call"
1330 instructions with 2 immediate operands so that the immediate segment
1331 precedes the offset, as it does when in AT&T mode. "enter" and the
1332 intersegment "jmp" and "call" instructions are the only ones that
1333 have two immediate operands. */
1334 if (intel_syntax
&& i
.operands
> 1
1335 && (strcmp (mnemonic
, "bound") != 0)
1336 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1342 if (i
.disp_operands
)
1345 /* Next, we find a template that matches the given insn,
1346 making sure the overlap of the given operands types is consistent
1347 with the template operand types. */
1349 if (!match_template ())
1354 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1356 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1357 i
.tm
.base_opcode
^= FloatR
;
1359 /* Zap movzx and movsx suffix. The suffix may have been set from
1360 "word ptr" or "byte ptr" on the source operand, but we'll use
1361 the suffix later to choose the destination register. */
1362 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1366 if (i
.tm
.opcode_modifier
& FWait
)
1367 if (!add_prefix (FWAIT_OPCODE
))
1370 /* Check string instruction segment overrides. */
1371 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1373 if (!check_string ())
1377 if (!process_suffix ())
1380 /* Make still unresolved immediate matches conform to size of immediate
1381 given in i.suffix. */
1382 if (!finalize_imm ())
1385 if (i
.types
[0] & Imm1
)
1386 i
.imm_operands
= 0; /* kludge for shift insns. */
1387 if (i
.types
[0] & ImplicitRegister
)
1389 if (i
.types
[1] & ImplicitRegister
)
1391 if (i
.types
[2] & ImplicitRegister
)
1394 if (i
.tm
.opcode_modifier
& ImmExt
)
1396 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1397 opcode suffix which is coded in the same place as an 8-bit
1398 immediate field would be. Here we fake an 8-bit immediate
1399 operand from the opcode suffix stored in tm.extension_opcode. */
1403 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1405 exp
= &im_expressions
[i
.imm_operands
++];
1406 i
.op
[i
.operands
].imms
= exp
;
1407 i
.types
[i
.operands
++] = Imm8
;
1408 exp
->X_op
= O_constant
;
1409 exp
->X_add_number
= i
.tm
.extension_opcode
;
1410 i
.tm
.extension_opcode
= None
;
1413 /* For insns with operands there are more diddles to do to the opcode. */
1416 if (!process_operands ())
1419 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1421 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1422 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1425 /* Handle conversion of 'int $3' --> special int3 insn. */
1426 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1428 i
.tm
.base_opcode
= INT3_OPCODE
;
1432 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1433 && i
.op
[0].disps
->X_op
== O_constant
)
1435 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1436 the absolute address given by the constant. Since ix86 jumps and
1437 calls are pc relative, we need to generate a reloc. */
1438 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1439 i
.op
[0].disps
->X_op
= O_symbol
;
1442 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1443 i
.rex
|= REX_MODE64
;
1445 /* For 8 bit registers we need an empty rex prefix. Also if the
1446 instruction already has a prefix, we need to convert old
1447 registers to new ones. */
1449 if (((i
.types
[0] & Reg8
) != 0
1450 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1451 || ((i
.types
[1] & Reg8
) != 0
1452 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1453 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1458 i
.rex
|= REX_OPCODE
;
1459 for (x
= 0; x
< 2; x
++)
1461 /* Look for 8 bit operand that uses old registers. */
1462 if ((i
.types
[x
] & Reg8
) != 0
1463 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1465 /* In case it is "hi" register, give up. */
1466 if (i
.op
[x
].regs
->reg_num
> 3)
1467 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1468 i
.op
[x
].regs
->reg_name
);
1470 /* Otherwise it is equivalent to the extended register.
1471 Since the encoding doesn't change this is merely
1472 cosmetic cleanup for debug output. */
1474 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1480 add_prefix (REX_OPCODE
| i
.rex
);
1482 /* We are ready to output the insn. */
1487 parse_insn (line
, mnemonic
)
1492 char *token_start
= l
;
1495 /* Non-zero if we found a prefix only acceptable with string insns. */
1496 const char *expecting_string_instruction
= NULL
;
1501 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1504 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1506 as_bad (_("no such instruction: `%s'"), token_start
);
1511 if (!is_space_char (*l
)
1512 && *l
!= END_OF_INSN
1513 && *l
!= PREFIX_SEPARATOR
1516 as_bad (_("invalid character %s in mnemonic"),
1517 output_invalid (*l
));
1520 if (token_start
== l
)
1522 if (*l
== PREFIX_SEPARATOR
)
1523 as_bad (_("expecting prefix; got nothing"));
1525 as_bad (_("expecting mnemonic; got nothing"));
1529 /* Look up instruction (or prefix) via hash table. */
1530 current_templates
= hash_find (op_hash
, mnemonic
);
1532 if (*l
!= END_OF_INSN
1533 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1534 && current_templates
1535 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1537 /* If we are in 16-bit mode, do not allow addr16 or data16.
1538 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1539 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1540 && flag_code
!= CODE_64BIT
1541 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1542 ^ (flag_code
== CODE_16BIT
)))
1544 as_bad (_("redundant %s prefix"),
1545 current_templates
->start
->name
);
1548 /* Add prefix, checking for repeated prefixes. */
1549 switch (add_prefix (current_templates
->start
->base_opcode
))
1554 expecting_string_instruction
= current_templates
->start
->name
;
1557 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1564 if (!current_templates
)
1566 /* See if we can get a match by trimming off a suffix. */
1569 case WORD_MNEM_SUFFIX
:
1570 case BYTE_MNEM_SUFFIX
:
1571 case QWORD_MNEM_SUFFIX
:
1572 i
.suffix
= mnem_p
[-1];
1574 current_templates
= hash_find (op_hash
, mnemonic
);
1576 case SHORT_MNEM_SUFFIX
:
1577 case LONG_MNEM_SUFFIX
:
1580 i
.suffix
= mnem_p
[-1];
1582 current_templates
= hash_find (op_hash
, mnemonic
);
1590 if (intel_float_operand (mnemonic
))
1591 i
.suffix
= SHORT_MNEM_SUFFIX
;
1593 i
.suffix
= LONG_MNEM_SUFFIX
;
1595 current_templates
= hash_find (op_hash
, mnemonic
);
1599 if (!current_templates
)
1601 as_bad (_("no such instruction: `%s'"), token_start
);
1606 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1608 /* Check for a branch hint. We allow ",pt" and ",pn" for
1609 predict taken and predict not taken respectively.
1610 I'm not sure that branch hints actually do anything on loop
1611 and jcxz insns (JumpByte) for current Pentium4 chips. They
1612 may work in the future and it doesn't hurt to accept them
1614 if (l
[0] == ',' && l
[1] == 'p')
1618 if (!add_prefix (DS_PREFIX_OPCODE
))
1622 else if (l
[2] == 'n')
1624 if (!add_prefix (CS_PREFIX_OPCODE
))
1630 /* Any other comma loses. */
1633 as_bad (_("invalid character %s in mnemonic"),
1634 output_invalid (*l
));
1638 /* Check if instruction is supported on specified architecture. */
1639 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1640 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1642 as_warn (_("`%s' is not supported on `%s'"),
1643 current_templates
->start
->name
, cpu_arch_name
);
1645 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1647 as_warn (_("use .code16 to ensure correct addressing mode"));
1650 /* Check for rep/repne without a string instruction. */
1651 if (expecting_string_instruction
1652 && !(current_templates
->start
->opcode_modifier
& IsString
))
1654 as_bad (_("expecting string instruction after `%s'"),
1655 expecting_string_instruction
);
1663 parse_operands (l
, mnemonic
)
1665 const char *mnemonic
;
1669 /* 1 if operand is pending after ','. */
1670 unsigned int expecting_operand
= 0;
1672 /* Non-zero if operand parens not balanced. */
1673 unsigned int paren_not_balanced
;
1675 while (*l
!= END_OF_INSN
)
1677 /* Skip optional white space before operand. */
1678 if (is_space_char (*l
))
1680 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1682 as_bad (_("invalid character %s before operand %d"),
1683 output_invalid (*l
),
1687 token_start
= l
; /* after white space */
1688 paren_not_balanced
= 0;
1689 while (paren_not_balanced
|| *l
!= ',')
1691 if (*l
== END_OF_INSN
)
1693 if (paren_not_balanced
)
1696 as_bad (_("unbalanced parenthesis in operand %d."),
1699 as_bad (_("unbalanced brackets in operand %d."),
1704 break; /* we are done */
1706 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1708 as_bad (_("invalid character %s in operand %d"),
1709 output_invalid (*l
),
1716 ++paren_not_balanced
;
1718 --paren_not_balanced
;
1723 ++paren_not_balanced
;
1725 --paren_not_balanced
;
1729 if (l
!= token_start
)
1730 { /* Yes, we've read in another operand. */
1731 unsigned int operand_ok
;
1732 this_operand
= i
.operands
++;
1733 if (i
.operands
> MAX_OPERANDS
)
1735 as_bad (_("spurious operands; (%d operands/instruction max)"),
1739 /* Now parse operand adding info to 'i' as we go along. */
1740 END_STRING_AND_SAVE (l
);
1744 i386_intel_operand (token_start
,
1745 intel_float_operand (mnemonic
));
1747 operand_ok
= i386_operand (token_start
);
1749 RESTORE_END_STRING (l
);
1755 if (expecting_operand
)
1757 expecting_operand_after_comma
:
1758 as_bad (_("expecting operand after ','; got nothing"));
1763 as_bad (_("expecting operand before ','; got nothing"));
1768 /* Now *l must be either ',' or END_OF_INSN. */
1771 if (*++l
== END_OF_INSN
)
1773 /* Just skip it, if it's \n complain. */
1774 goto expecting_operand_after_comma
;
1776 expecting_operand
= 1;
1785 union i386_op temp_op
;
1786 unsigned int temp_type
;
1787 RELOC_ENUM temp_reloc
;
1791 if (i
.operands
== 2)
1796 else if (i
.operands
== 3)
1801 temp_type
= i
.types
[xchg2
];
1802 i
.types
[xchg2
] = i
.types
[xchg1
];
1803 i
.types
[xchg1
] = temp_type
;
1804 temp_op
= i
.op
[xchg2
];
1805 i
.op
[xchg2
] = i
.op
[xchg1
];
1806 i
.op
[xchg1
] = temp_op
;
1807 temp_reloc
= i
.reloc
[xchg2
];
1808 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1809 i
.reloc
[xchg1
] = temp_reloc
;
1811 if (i
.mem_operands
== 2)
1813 const seg_entry
*temp_seg
;
1814 temp_seg
= i
.seg
[0];
1815 i
.seg
[0] = i
.seg
[1];
1816 i
.seg
[1] = temp_seg
;
1820 /* Try to ensure constant immediates are represented in the smallest
1825 char guess_suffix
= 0;
1829 guess_suffix
= i
.suffix
;
1830 else if (i
.reg_operands
)
1832 /* Figure out a suffix from the last register operand specified.
1833 We can't do this properly yet, ie. excluding InOutPortReg,
1834 but the following works for instructions with immediates.
1835 In any case, we can't set i.suffix yet. */
1836 for (op
= i
.operands
; --op
>= 0;)
1837 if (i
.types
[op
] & Reg
)
1839 if (i
.types
[op
] & Reg8
)
1840 guess_suffix
= BYTE_MNEM_SUFFIX
;
1841 else if (i
.types
[op
] & Reg16
)
1842 guess_suffix
= WORD_MNEM_SUFFIX
;
1843 else if (i
.types
[op
] & Reg32
)
1844 guess_suffix
= LONG_MNEM_SUFFIX
;
1845 else if (i
.types
[op
] & Reg64
)
1846 guess_suffix
= QWORD_MNEM_SUFFIX
;
1850 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1851 guess_suffix
= WORD_MNEM_SUFFIX
;
1853 for (op
= i
.operands
; --op
>= 0;)
1854 if (i
.types
[op
] & Imm
)
1856 switch (i
.op
[op
].imms
->X_op
)
1859 /* If a suffix is given, this operand may be shortened. */
1860 switch (guess_suffix
)
1862 case LONG_MNEM_SUFFIX
:
1863 i
.types
[op
] |= Imm32
| Imm64
;
1865 case WORD_MNEM_SUFFIX
:
1866 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1868 case BYTE_MNEM_SUFFIX
:
1869 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1873 /* If this operand is at most 16 bits, convert it
1874 to a signed 16 bit number before trying to see
1875 whether it will fit in an even smaller size.
1876 This allows a 16-bit operand such as $0xffe0 to
1877 be recognised as within Imm8S range. */
1878 if ((i
.types
[op
] & Imm16
)
1879 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1881 i
.op
[op
].imms
->X_add_number
=
1882 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1884 if ((i
.types
[op
] & Imm32
)
1885 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1888 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1889 ^ ((offsetT
) 1 << 31))
1890 - ((offsetT
) 1 << 31));
1892 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1894 /* We must avoid matching of Imm32 templates when 64bit
1895 only immediate is available. */
1896 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1897 i
.types
[op
] &= ~Imm32
;
1904 /* Symbols and expressions. */
1906 /* Convert symbolic operand to proper sizes for matching. */
1907 switch (guess_suffix
)
1909 case QWORD_MNEM_SUFFIX
:
1910 i
.types
[op
] = Imm64
| Imm32S
;
1912 case LONG_MNEM_SUFFIX
:
1913 i
.types
[op
] = Imm32
| Imm64
;
1915 case WORD_MNEM_SUFFIX
:
1916 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1919 case BYTE_MNEM_SUFFIX
:
1920 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1929 /* Try to use the smallest displacement type too. */
1935 for (op
= i
.operands
; --op
>= 0;)
1936 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1938 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1940 if (i
.types
[op
] & Disp16
)
1942 /* We know this operand is at most 16 bits, so
1943 convert to a signed 16 bit number before trying
1944 to see whether it will fit in an even smaller
1947 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1949 else if (i
.types
[op
] & Disp32
)
1951 /* We know this operand is at most 32 bits, so convert to a
1952 signed 32 bit number before trying to see whether it will
1953 fit in an even smaller size. */
1954 disp
&= (((offsetT
) 2 << 31) - 1);
1955 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1957 if (flag_code
== CODE_64BIT
)
1959 if (fits_in_signed_long (disp
))
1960 i
.types
[op
] |= Disp32S
;
1961 if (fits_in_unsigned_long (disp
))
1962 i
.types
[op
] |= Disp32
;
1964 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1965 && fits_in_signed_byte (disp
))
1966 i
.types
[op
] |= Disp8
;
1973 /* Points to template once we've found it. */
1975 unsigned int overlap0
, overlap1
, overlap2
;
1976 unsigned int found_reverse_match
;
1979 #define MATCH(overlap, given, template) \
1980 ((overlap & ~JumpAbsolute) \
1981 && (((given) & (BaseIndex | JumpAbsolute)) \
1982 == ((overlap) & (BaseIndex | JumpAbsolute))))
1984 /* If given types r0 and r1 are registers they must be of the same type
1985 unless the expected operand type register overlap is null.
1986 Note that Acc in a template matches every size of reg. */
1987 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1988 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1989 || ((g0) & Reg) == ((g1) & Reg) \
1990 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1995 found_reverse_match
= 0;
1996 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1998 : (i
.suffix
== WORD_MNEM_SUFFIX
2000 : (i
.suffix
== SHORT_MNEM_SUFFIX
2002 : (i
.suffix
== LONG_MNEM_SUFFIX
2004 : (i
.suffix
== QWORD_MNEM_SUFFIX
2006 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2007 ? No_xSuf
: 0))))));
2009 for (t
= current_templates
->start
;
2010 t
< current_templates
->end
;
2013 /* Must have right number of operands. */
2014 if (i
.operands
!= t
->operands
)
2017 /* Check the suffix, except for some instructions in intel mode. */
2018 if ((t
->opcode_modifier
& suffix_check
)
2020 && (t
->opcode_modifier
& IgnoreSize
))
2022 && t
->base_opcode
== 0xd9
2023 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2024 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2027 /* Do not verify operands when there are none. */
2028 else if (!t
->operands
)
2030 if (t
->cpu_flags
& ~cpu_arch_flags
)
2032 /* We've found a match; break out of loop. */
2036 overlap0
= i
.types
[0] & t
->operand_types
[0];
2037 switch (t
->operands
)
2040 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2045 overlap1
= i
.types
[1] & t
->operand_types
[1];
2046 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2047 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2048 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2049 t
->operand_types
[0],
2050 overlap1
, i
.types
[1],
2051 t
->operand_types
[1]))
2053 /* Check if other direction is valid ... */
2054 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2057 /* Try reversing direction of operands. */
2058 overlap0
= i
.types
[0] & t
->operand_types
[1];
2059 overlap1
= i
.types
[1] & t
->operand_types
[0];
2060 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2061 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2062 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2063 t
->operand_types
[1],
2064 overlap1
, i
.types
[1],
2065 t
->operand_types
[0]))
2067 /* Does not match either direction. */
2070 /* found_reverse_match holds which of D or FloatDR
2072 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2074 /* Found a forward 2 operand match here. */
2075 else if (t
->operands
== 3)
2077 /* Here we make use of the fact that there are no
2078 reverse match 3 operand instructions, and all 3
2079 operand instructions only need to be checked for
2080 register consistency between operands 2 and 3. */
2081 overlap2
= i
.types
[2] & t
->operand_types
[2];
2082 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2083 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2084 t
->operand_types
[1],
2085 overlap2
, i
.types
[2],
2086 t
->operand_types
[2]))
2090 /* Found either forward/reverse 2 or 3 operand match here:
2091 slip through to break. */
2093 if (t
->cpu_flags
& ~cpu_arch_flags
)
2095 found_reverse_match
= 0;
2098 /* We've found a match; break out of loop. */
2102 if (t
== current_templates
->end
)
2104 /* We found no match. */
2105 as_bad (_("suffix or operands invalid for `%s'"),
2106 current_templates
->start
->name
);
2110 if (!quiet_warnings
)
2113 && ((i
.types
[0] & JumpAbsolute
)
2114 != (t
->operand_types
[0] & JumpAbsolute
)))
2116 as_warn (_("indirect %s without `*'"), t
->name
);
2119 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2120 == (IsPrefix
| IgnoreSize
))
2122 /* Warn them that a data or address size prefix doesn't
2123 affect assembly of the next line of code. */
2124 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2128 /* Copy the template we found. */
2130 if (found_reverse_match
)
2132 /* If we found a reverse match we must alter the opcode
2133 direction bit. found_reverse_match holds bits to change
2134 (different for int & float insns). */
2136 i
.tm
.base_opcode
^= found_reverse_match
;
2138 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2139 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2148 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2149 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2151 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2153 as_bad (_("`%s' operand %d must use `%%es' segment"),
2158 /* There's only ever one segment override allowed per instruction.
2159 This instruction possibly has a legal segment override on the
2160 second operand, so copy the segment to where non-string
2161 instructions store it, allowing common code. */
2162 i
.seg
[0] = i
.seg
[1];
2164 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2166 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2168 as_bad (_("`%s' operand %d must use `%%es' segment"),
2180 /* If matched instruction specifies an explicit instruction mnemonic
2182 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2184 if (i
.tm
.opcode_modifier
& Size16
)
2185 i
.suffix
= WORD_MNEM_SUFFIX
;
2186 else if (i
.tm
.opcode_modifier
& Size64
)
2187 i
.suffix
= QWORD_MNEM_SUFFIX
;
2189 i
.suffix
= LONG_MNEM_SUFFIX
;
2191 else if (i
.reg_operands
)
2193 /* If there's no instruction mnemonic suffix we try to invent one
2194 based on register operands. */
2197 /* We take i.suffix from the last register operand specified,
2198 Destination register type is more significant than source
2201 for (op
= i
.operands
; --op
>= 0;)
2202 if ((i
.types
[op
] & Reg
)
2203 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2205 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2206 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2207 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2212 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2214 if (!check_byte_reg ())
2217 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2219 if (!check_long_reg ())
2222 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2224 if (!check_qword_reg ())
2227 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2229 if (!check_word_reg ())
2232 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2233 /* Do nothing if the instruction is going to ignore the prefix. */
2238 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2240 i
.suffix
= stackop_size
;
2243 /* Change the opcode based on the operand size given by i.suffix;
2244 We need not change things for byte insns. */
2246 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2248 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2252 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2254 /* It's not a byte, select word/dword operation. */
2255 if (i
.tm
.opcode_modifier
& W
)
2257 if (i
.tm
.opcode_modifier
& ShortForm
)
2258 i
.tm
.base_opcode
|= 8;
2260 i
.tm
.base_opcode
|= 1;
2263 /* Now select between word & dword operations via the operand
2264 size prefix, except for instructions that will ignore this
2266 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2267 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2268 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2269 || (flag_code
== CODE_64BIT
2270 && (i
.tm
.opcode_modifier
& JumpByte
))))
2272 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2273 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2274 prefix
= ADDR_PREFIX_OPCODE
;
2276 if (!add_prefix (prefix
))
2280 /* Set mode64 for an operand. */
2281 if (i
.suffix
== QWORD_MNEM_SUFFIX
2282 && flag_code
== CODE_64BIT
2283 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2284 i
.rex
|= REX_MODE64
;
2286 /* Size floating point instruction. */
2287 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2289 if (i
.tm
.opcode_modifier
& FloatMF
)
2290 i
.tm
.base_opcode
^= 4;
2301 for (op
= i
.operands
; --op
>= 0;)
2303 /* If this is an eight bit register, it's OK. If it's the 16 or
2304 32 bit version of an eight bit register, we will just use the
2305 low portion, and that's OK too. */
2306 if (i
.types
[op
] & Reg8
)
2309 /* movzx and movsx should not generate this warning. */
2311 && (i
.tm
.base_opcode
== 0xfb7
2312 || i
.tm
.base_opcode
== 0xfb6
2313 || i
.tm
.base_opcode
== 0x63
2314 || i
.tm
.base_opcode
== 0xfbe
2315 || i
.tm
.base_opcode
== 0xfbf))
2318 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2320 /* Check that the template allows eight bit regs. This
2321 kills insns such as `orb $1,%edx', which maybe should be
2323 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2327 /* Prohibit these changes in the 64bit mode, since the
2328 lowering is more complicated. */
2329 if (flag_code
== CODE_64BIT
2330 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2332 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2333 i
.op
[op
].regs
->reg_name
,
2337 #if REGISTER_WARNINGS
2339 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2340 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2341 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2342 ? REGNAM_AL
- REGNAM_AX
2343 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2344 i
.op
[op
].regs
->reg_name
,
2349 /* Any other register is bad. */
2350 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2352 | Control
| Debug
| Test
2353 | FloatReg
| FloatAcc
))
2355 as_bad (_("`%%%s' not allowed with `%s%c'"),
2356 i
.op
[op
].regs
->reg_name
,
2370 for (op
= i
.operands
; --op
>= 0;)
2371 /* Reject eight bit registers, except where the template requires
2372 them. (eg. movzb) */
2373 if ((i
.types
[op
] & Reg8
) != 0
2374 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2376 as_bad (_("`%%%s' not allowed with `%s%c'"),
2377 i
.op
[op
].regs
->reg_name
,
2382 /* Warn if the e prefix on a general reg is missing. */
2383 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2384 && (i
.types
[op
] & Reg16
) != 0
2385 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2387 /* Prohibit these changes in the 64bit mode, since the
2388 lowering is more complicated. */
2389 if (flag_code
== CODE_64BIT
)
2391 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2392 i
.op
[op
].regs
->reg_name
,
2396 #if REGISTER_WARNINGS
2398 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2399 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2400 i
.op
[op
].regs
->reg_name
,
2404 /* Warn if the r prefix on a general reg is missing. */
2405 else if ((i
.types
[op
] & Reg64
) != 0
2406 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2408 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2409 i
.op
[op
].regs
->reg_name
,
2421 for (op
= i
.operands
; --op
>= 0; )
2422 /* Reject eight bit registers, except where the template requires
2423 them. (eg. movzb) */
2424 if ((i
.types
[op
] & Reg8
) != 0
2425 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2427 as_bad (_("`%%%s' not allowed with `%s%c'"),
2428 i
.op
[op
].regs
->reg_name
,
2433 /* Warn if the e prefix on a general reg is missing. */
2434 else if (((i
.types
[op
] & Reg16
) != 0
2435 || (i
.types
[op
] & Reg32
) != 0)
2436 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2438 /* Prohibit these changes in the 64bit mode, since the
2439 lowering is more complicated. */
2440 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2441 i
.op
[op
].regs
->reg_name
,
2452 for (op
= i
.operands
; --op
>= 0;)
2453 /* Reject eight bit registers, except where the template requires
2454 them. (eg. movzb) */
2455 if ((i
.types
[op
] & Reg8
) != 0
2456 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2458 as_bad (_("`%%%s' not allowed with `%s%c'"),
2459 i
.op
[op
].regs
->reg_name
,
2464 /* Warn if the e prefix on a general reg is present. */
2465 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2466 && (i
.types
[op
] & Reg32
) != 0
2467 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2469 /* Prohibit these changes in the 64bit mode, since the
2470 lowering is more complicated. */
2471 if (flag_code
== CODE_64BIT
)
2473 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2474 i
.op
[op
].regs
->reg_name
,
2479 #if REGISTER_WARNINGS
2480 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2481 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2482 i
.op
[op
].regs
->reg_name
,
2492 unsigned int overlap0
, overlap1
, overlap2
;
2494 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2495 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2496 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2497 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2498 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2502 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2504 : (i
.suffix
== WORD_MNEM_SUFFIX
2506 : (i
.suffix
== QWORD_MNEM_SUFFIX
2510 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2511 || overlap0
== (Imm16
| Imm32
)
2512 || overlap0
== (Imm16
| Imm32S
))
2514 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2517 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2518 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2519 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2521 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2525 i
.types
[0] = overlap0
;
2527 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2528 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2529 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2530 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2531 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2535 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2537 : (i
.suffix
== WORD_MNEM_SUFFIX
2539 : (i
.suffix
== QWORD_MNEM_SUFFIX
2543 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2544 || overlap1
== (Imm16
| Imm32
)
2545 || overlap1
== (Imm16
| Imm32S
))
2547 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2550 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2551 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2552 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2554 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2558 i
.types
[1] = overlap1
;
2560 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2561 assert ((overlap2
& Imm
) == 0);
2562 i
.types
[2] = overlap2
;
2570 /* Default segment register this instruction will use for memory
2571 accesses. 0 means unknown. This is only for optimizing out
2572 unnecessary segment overrides. */
2573 const seg_entry
*default_seg
= 0;
2575 /* The imul $imm, %reg instruction is converted into
2576 imul $imm, %reg, %reg, and the clr %reg instruction
2577 is converted into xor %reg, %reg. */
2578 if (i
.tm
.opcode_modifier
& regKludge
)
2580 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2581 /* Pretend we saw the extra register operand. */
2582 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2583 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2584 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2588 if (i
.tm
.opcode_modifier
& ShortForm
)
2590 /* The register or float register operand is in operand 0 or 1. */
2591 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2592 /* Register goes in low 3 bits of opcode. */
2593 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2594 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2596 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2598 /* Warn about some common errors, but press on regardless.
2599 The first case can be generated by gcc (<= 2.8.1). */
2600 if (i
.operands
== 2)
2602 /* Reversed arguments on faddp, fsubp, etc. */
2603 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2604 i
.op
[1].regs
->reg_name
,
2605 i
.op
[0].regs
->reg_name
);
2609 /* Extraneous `l' suffix on fp insn. */
2610 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2611 i
.op
[0].regs
->reg_name
);
2615 else if (i
.tm
.opcode_modifier
& Modrm
)
2617 /* The opcode is completed (modulo i.tm.extension_opcode which
2618 must be put into the modrm byte). Now, we make the modrm and
2619 index base bytes based on all the info we've collected. */
2621 default_seg
= build_modrm_byte ();
2623 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2625 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2626 && i
.op
[0].regs
->reg_num
== 1)
2628 as_bad (_("you can't `pop %%cs'"));
2631 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2632 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2635 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2639 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2641 /* For the string instructions that allow a segment override
2642 on one of their operands, the default segment is ds. */
2646 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2647 as_warn (_("segment override on `lea' is ineffectual"));
2649 /* If a segment was explicitly specified, and the specified segment
2650 is not the default, use an opcode prefix to select it. If we
2651 never figured out what the default segment is, then default_seg
2652 will be zero at this point, and the specified segment prefix will
2654 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2656 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2662 static const seg_entry
*
2665 const seg_entry
*default_seg
= 0;
2667 /* i.reg_operands MUST be the number of real register operands;
2668 implicit registers do not count. */
2669 if (i
.reg_operands
== 2)
2671 unsigned int source
, dest
;
2672 source
= ((i
.types
[0]
2673 & (Reg
| RegMMX
| RegXMM
2675 | Control
| Debug
| Test
))
2680 /* One of the register operands will be encoded in the i.tm.reg
2681 field, the other in the combined i.tm.mode and i.tm.regmem
2682 fields. If no form of this instruction supports a memory
2683 destination operand, then we assume the source operand may
2684 sometimes be a memory operand and so we need to store the
2685 destination in the i.rm.reg field. */
2686 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2688 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2689 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2690 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2692 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2697 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2698 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2699 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2701 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2706 { /* If it's not 2 reg operands... */
2709 unsigned int fake_zero_displacement
= 0;
2710 unsigned int op
= ((i
.types
[0] & AnyMem
)
2712 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2716 if (i
.base_reg
== 0)
2719 if (!i
.disp_operands
)
2720 fake_zero_displacement
= 1;
2721 if (i
.index_reg
== 0)
2723 /* Operand is just <disp> */
2724 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
2725 && (flag_code
!= CODE_64BIT
))
2727 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2728 i
.types
[op
] &= ~Disp
;
2729 i
.types
[op
] |= Disp16
;
2731 else if (flag_code
!= CODE_64BIT
2732 || (i
.prefix
[ADDR_PREFIX
] != 0))
2734 i
.rm
.regmem
= NO_BASE_REGISTER
;
2735 i
.types
[op
] &= ~Disp
;
2736 i
.types
[op
] |= Disp32
;
2740 /* 64bit mode overwrites the 32bit absolute
2741 addressing by RIP relative addressing and
2742 absolute addressing is encoded by one of the
2743 redundant SIB forms. */
2744 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2745 i
.sib
.base
= NO_BASE_REGISTER
;
2746 i
.sib
.index
= NO_INDEX_REGISTER
;
2747 i
.types
[op
] &= ~Disp
;
2748 i
.types
[op
] |= Disp32S
;
2751 else /* !i.base_reg && i.index_reg */
2753 i
.sib
.index
= i
.index_reg
->reg_num
;
2754 i
.sib
.base
= NO_BASE_REGISTER
;
2755 i
.sib
.scale
= i
.log2_scale_factor
;
2756 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2757 i
.types
[op
] &= ~Disp
;
2758 if (flag_code
!= CODE_64BIT
)
2759 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2761 i
.types
[op
] |= Disp32S
;
2762 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2766 /* RIP addressing for 64bit mode. */
2767 else if (i
.base_reg
->reg_type
== BaseIndex
)
2769 i
.rm
.regmem
= NO_BASE_REGISTER
;
2770 i
.types
[op
] &= ~Disp
;
2771 i
.types
[op
] |= Disp32S
;
2772 i
.flags
[op
] = Operand_PCrel
;
2774 else if (i
.base_reg
->reg_type
& Reg16
)
2776 switch (i
.base_reg
->reg_num
)
2779 if (i
.index_reg
== 0)
2781 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2782 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2786 if (i
.index_reg
== 0)
2789 if ((i
.types
[op
] & Disp
) == 0)
2791 /* fake (%bp) into 0(%bp) */
2792 i
.types
[op
] |= Disp8
;
2793 fake_zero_displacement
= 1;
2796 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2797 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2799 default: /* (%si) -> 4 or (%di) -> 5 */
2800 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2802 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2804 else /* i.base_reg and 32/64 bit mode */
2806 if (flag_code
== CODE_64BIT
2807 && (i
.types
[op
] & Disp
))
2809 if (i
.types
[op
] & Disp8
)
2810 i
.types
[op
] = Disp8
| Disp32S
;
2812 i
.types
[op
] = Disp32S
;
2814 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2815 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2817 i
.sib
.base
= i
.base_reg
->reg_num
;
2818 /* x86-64 ignores REX prefix bit here to avoid decoder
2820 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2823 if (i
.disp_operands
== 0)
2825 fake_zero_displacement
= 1;
2826 i
.types
[op
] |= Disp8
;
2829 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2833 i
.sib
.scale
= i
.log2_scale_factor
;
2834 if (i
.index_reg
== 0)
2836 /* <disp>(%esp) becomes two byte modrm with no index
2837 register. We've already stored the code for esp
2838 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2839 Any base register besides %esp will not use the
2840 extra modrm byte. */
2841 i
.sib
.index
= NO_INDEX_REGISTER
;
2842 #if !SCALE1_WHEN_NO_INDEX
2843 /* Another case where we force the second modrm byte. */
2844 if (i
.log2_scale_factor
)
2845 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2850 i
.sib
.index
= i
.index_reg
->reg_num
;
2851 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2852 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2855 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2858 if (fake_zero_displacement
)
2860 /* Fakes a zero displacement assuming that i.types[op]
2861 holds the correct displacement size. */
2864 assert (i
.op
[op
].disps
== 0);
2865 exp
= &disp_expressions
[i
.disp_operands
++];
2866 i
.op
[op
].disps
= exp
;
2867 exp
->X_op
= O_constant
;
2868 exp
->X_add_number
= 0;
2869 exp
->X_add_symbol
= (symbolS
*) 0;
2870 exp
->X_op_symbol
= (symbolS
*) 0;
2874 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2875 (if any) based on i.tm.extension_opcode. Again, we must be
2876 careful to make sure that segment/control/debug/test/MMX
2877 registers are coded into the i.rm.reg field. */
2882 & (Reg
| RegMMX
| RegXMM
2884 | Control
| Debug
| Test
))
2887 & (Reg
| RegMMX
| RegXMM
2889 | Control
| Debug
| Test
))
2892 /* If there is an extension opcode to put here, the register
2893 number must be put into the regmem field. */
2894 if (i
.tm
.extension_opcode
!= None
)
2896 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2897 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2902 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2903 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2907 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2908 must set it to 3 to indicate this is a register operand
2909 in the regmem field. */
2910 if (!i
.mem_operands
)
2914 /* Fill in i.rm.reg field with extension opcode (if any). */
2915 if (i
.tm
.extension_opcode
!= None
)
2916 i
.rm
.reg
= i
.tm
.extension_opcode
;
2927 relax_substateT subtype
;
2932 if (flag_code
== CODE_16BIT
)
2936 if (i
.prefix
[DATA_PREFIX
] != 0)
2942 /* Pentium4 branch hints. */
2943 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2944 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2949 if (i
.prefix
[REX_PREFIX
] != 0)
2955 if (i
.prefixes
!= 0 && !intel_syntax
)
2956 as_warn (_("skipping prefixes on this instruction"));
2958 /* It's always a symbol; End frag & setup for relax.
2959 Make sure there is enough room in this frag for the largest
2960 instruction we may generate in md_convert_frag. This is 2
2961 bytes for the opcode and room for the prefix and largest
2963 frag_grow (prefix
+ 2 + 4);
2964 /* Prefix and 1 opcode byte go in fr_fix. */
2965 p
= frag_more (prefix
+ 1);
2966 if (i
.prefix
[DATA_PREFIX
] != 0)
2967 *p
++ = DATA_PREFIX_OPCODE
;
2968 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2969 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2970 *p
++ = i
.prefix
[SEG_PREFIX
];
2971 if (i
.prefix
[REX_PREFIX
] != 0)
2972 *p
++ = i
.prefix
[REX_PREFIX
];
2973 *p
= i
.tm
.base_opcode
;
2975 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2976 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2977 else if ((cpu_arch_flags
& Cpu386
) != 0)
2978 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2980 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2983 sym
= i
.op
[0].disps
->X_add_symbol
;
2984 off
= i
.op
[0].disps
->X_add_number
;
2986 if (i
.op
[0].disps
->X_op
!= O_constant
2987 && i
.op
[0].disps
->X_op
!= O_symbol
)
2989 /* Handle complex expressions. */
2990 sym
= make_expr_symbol (i
.op
[0].disps
);
2994 /* 1 possible extra opcode + 4 byte displacement go in var part.
2995 Pass reloc in fr_var. */
2996 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3006 if (i
.tm
.opcode_modifier
& JumpByte
)
3008 /* This is a loop or jecxz type instruction. */
3010 if (i
.prefix
[ADDR_PREFIX
] != 0)
3012 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3015 /* Pentium4 branch hints. */
3016 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3017 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3019 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3028 if (flag_code
== CODE_16BIT
)
3031 if (i
.prefix
[DATA_PREFIX
] != 0)
3033 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3043 if (i
.prefix
[REX_PREFIX
] != 0)
3045 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3049 if (i
.prefixes
!= 0 && !intel_syntax
)
3050 as_warn (_("skipping prefixes on this instruction"));
3052 p
= frag_more (1 + size
);
3053 *p
++ = i
.tm
.base_opcode
;
3055 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3056 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3058 /* All jumps handled here are signed, but don't use a signed limit
3059 check for 32 and 16 bit jumps as we want to allow wrap around at
3060 4G and 64k respectively. */
3062 fixP
->fx_signed
= 1;
3066 output_interseg_jump ()
3074 if (flag_code
== CODE_16BIT
)
3078 if (i
.prefix
[DATA_PREFIX
] != 0)
3084 if (i
.prefix
[REX_PREFIX
] != 0)
3094 if (i
.prefixes
!= 0 && !intel_syntax
)
3095 as_warn (_("skipping prefixes on this instruction"));
3097 /* 1 opcode; 2 segment; offset */
3098 p
= frag_more (prefix
+ 1 + 2 + size
);
3100 if (i
.prefix
[DATA_PREFIX
] != 0)
3101 *p
++ = DATA_PREFIX_OPCODE
;
3103 if (i
.prefix
[REX_PREFIX
] != 0)
3104 *p
++ = i
.prefix
[REX_PREFIX
];
3106 *p
++ = i
.tm
.base_opcode
;
3107 if (i
.op
[1].imms
->X_op
== O_constant
)
3109 offsetT n
= i
.op
[1].imms
->X_add_number
;
3112 && !fits_in_unsigned_word (n
)
3113 && !fits_in_signed_word (n
))
3115 as_bad (_("16-bit jump out of range"));
3118 md_number_to_chars (p
, n
, size
);
3121 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3122 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3123 if (i
.op
[0].imms
->X_op
!= O_constant
)
3124 as_bad (_("can't handle non absolute segment in `%s'"),
3126 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3133 fragS
*insn_start_frag
;
3134 offsetT insn_start_off
;
3136 /* Tie dwarf2 debug info to the address at the start of the insn.
3137 We can't do this after the insn has been output as the current
3138 frag may have been closed off. eg. by frag_var. */
3139 dwarf2_emit_insn (0);
3141 insn_start_frag
= frag_now
;
3142 insn_start_off
= frag_now_fix ();
3145 if (i
.tm
.opcode_modifier
& Jump
)
3147 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3149 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3150 output_interseg_jump ();
3153 /* Output normal instructions here. */
3157 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3158 byte for the SSE instructions to specify a prefix they require. */
3159 if (i
.tm
.base_opcode
& 0xff0000)
3160 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3162 /* The prefix bytes. */
3164 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3170 md_number_to_chars (p
, (valueT
) *q
, 1);
3174 /* Now the opcode; be careful about word order here! */
3175 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3177 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3182 /* Put out high byte first: can't use md_number_to_chars! */
3183 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3184 *p
= i
.tm
.base_opcode
& 0xff;
3187 /* Now the modrm byte and sib byte (if present). */
3188 if (i
.tm
.opcode_modifier
& Modrm
)
3191 md_number_to_chars (p
,
3192 (valueT
) (i
.rm
.regmem
<< 0
3196 /* If i.rm.regmem == ESP (4)
3197 && i.rm.mode != (Register mode)
3199 ==> need second modrm byte. */
3200 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3202 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3205 md_number_to_chars (p
,
3206 (valueT
) (i
.sib
.base
<< 0
3208 | i
.sib
.scale
<< 6),
3213 if (i
.disp_operands
)
3214 output_disp (insn_start_frag
, insn_start_off
);
3217 output_imm (insn_start_frag
, insn_start_off
);
3225 #endif /* DEBUG386 */
3229 output_disp (insn_start_frag
, insn_start_off
)
3230 fragS
*insn_start_frag
;
3231 offsetT insn_start_off
;
3236 for (n
= 0; n
< i
.operands
; n
++)
3238 if (i
.types
[n
] & Disp
)
3240 if (i
.op
[n
].disps
->X_op
== O_constant
)
3246 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3249 if (i
.types
[n
] & Disp8
)
3251 if (i
.types
[n
] & Disp64
)
3254 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3256 p
= frag_more (size
);
3257 md_number_to_chars (p
, val
, size
);
3261 RELOC_ENUM reloc_type
;
3264 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3266 /* The PC relative address is computed relative
3267 to the instruction boundary, so in case immediate
3268 fields follows, we need to adjust the value. */
3269 if (pcrel
&& i
.imm_operands
)
3274 for (n1
= 0; n1
< i
.operands
; n1
++)
3275 if (i
.types
[n1
] & Imm
)
3277 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3280 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3282 if (i
.types
[n1
] & Imm64
)
3287 /* We should find the immediate. */
3288 if (n1
== i
.operands
)
3290 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3293 if (i
.types
[n
] & Disp32S
)
3296 if (i
.types
[n
] & (Disp16
| Disp64
))
3299 if (i
.types
[n
] & Disp64
)
3303 p
= frag_more (size
);
3304 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3305 #ifdef BFD_ASSEMBLER
3306 if (reloc_type
== BFD_RELOC_32
3308 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3309 && (i
.op
[n
].disps
->X_op
== O_symbol
3310 || (i
.op
[n
].disps
->X_op
== O_add
3311 && ((symbol_get_value_expression
3312 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3317 if (insn_start_frag
== frag_now
)
3318 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3323 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3324 for (fr
= insn_start_frag
->fr_next
;
3325 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3327 add
+= p
- frag_now
->fr_literal
;
3330 /* We don't support dynamic linking on x86-64 yet. */
3331 if (flag_code
== CODE_64BIT
)
3333 reloc_type
= BFD_RELOC_386_GOTPC
;
3334 i
.op
[n
].disps
->X_add_number
+= add
;
3337 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3338 i
.op
[n
].disps
, pcrel
, reloc_type
);
3345 output_imm (insn_start_frag
, insn_start_off
)
3346 fragS
*insn_start_frag
;
3347 offsetT insn_start_off
;
3352 for (n
= 0; n
< i
.operands
; n
++)
3354 if (i
.types
[n
] & Imm
)
3356 if (i
.op
[n
].imms
->X_op
== O_constant
)
3362 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3365 if (i
.types
[n
] & (Imm8
| Imm8S
))
3367 else if (i
.types
[n
] & Imm64
)
3370 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3372 p
= frag_more (size
);
3373 md_number_to_chars (p
, val
, size
);
3377 /* Not absolute_section.
3378 Need a 32-bit fixup (don't support 8bit
3379 non-absolute imms). Try to support other
3381 RELOC_ENUM reloc_type
;
3385 if ((i
.types
[n
] & (Imm32S
))
3386 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3388 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3391 if (i
.types
[n
] & (Imm8
| Imm8S
))
3393 if (i
.types
[n
] & Imm64
)
3397 p
= frag_more (size
);
3398 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3399 #ifdef BFD_ASSEMBLER
3400 /* This is tough to explain. We end up with this one if we
3401 * have operands that look like
3402 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3403 * obtain the absolute address of the GOT, and it is strongly
3404 * preferable from a performance point of view to avoid using
3405 * a runtime relocation for this. The actual sequence of
3406 * instructions often look something like:
3411 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3413 * The call and pop essentially return the absolute address
3414 * of the label .L66 and store it in %ebx. The linker itself
3415 * will ultimately change the first operand of the addl so
3416 * that %ebx points to the GOT, but to keep things simple, the
3417 * .o file must have this operand set so that it generates not
3418 * the absolute address of .L66, but the absolute address of
3419 * itself. This allows the linker itself simply treat a GOTPC
3420 * relocation as asking for a pcrel offset to the GOT to be
3421 * added in, and the addend of the relocation is stored in the
3422 * operand field for the instruction itself.
3424 * Our job here is to fix the operand so that it would add
3425 * the correct offset so that %ebx would point to itself. The
3426 * thing that is tricky is that .-.L66 will point to the
3427 * beginning of the instruction, so we need to further modify
3428 * the operand so that it will point to itself. There are
3429 * other cases where you have something like:
3431 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3433 * and here no correction would be required. Internally in
3434 * the assembler we treat operands of this form as not being
3435 * pcrel since the '.' is explicitly mentioned, and I wonder
3436 * whether it would simplify matters to do it this way. Who
3437 * knows. In earlier versions of the PIC patches, the
3438 * pcrel_adjust field was used to store the correction, but
3439 * since the expression is not pcrel, I felt it would be
3440 * confusing to do it this way. */
3442 if (reloc_type
== BFD_RELOC_32
3444 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3445 && (i
.op
[n
].imms
->X_op
== O_symbol
3446 || (i
.op
[n
].imms
->X_op
== O_add
3447 && ((symbol_get_value_expression
3448 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3453 if (insn_start_frag
== frag_now
)
3454 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3459 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3460 for (fr
= insn_start_frag
->fr_next
;
3461 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3463 add
+= p
- frag_now
->fr_literal
;
3466 /* We don't support dynamic linking on x86-64 yet. */
3467 if (flag_code
== CODE_64BIT
)
3469 reloc_type
= BFD_RELOC_386_GOTPC
;
3470 i
.op
[n
].imms
->X_add_number
+= add
;
3473 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3474 i
.op
[n
].imms
, 0, reloc_type
);
3481 static char *lex_got
PARAMS ((RELOC_ENUM
*, int *));
3483 /* Parse operands of the form
3484 <symbol>@GOTOFF+<nnn>
3485 and similar .plt or .got references.
3487 If we find one, set up the correct relocation in RELOC and copy the
3488 input string, minus the `@GOTOFF' into a malloc'd buffer for
3489 parsing by the calling routine. Return this buffer, and if ADJUST
3490 is non-null set it to the length of the string we removed from the
3491 input line. Otherwise return NULL. */
3493 lex_got (reloc
, adjust
)
3497 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3498 static const struct {
3500 const RELOC_ENUM rel
[NUM_FLAG_CODE
];
3502 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3503 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3504 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3505 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3506 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3507 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3508 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3509 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3510 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3511 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3512 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3513 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3514 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3519 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3520 if (is_end_of_line
[(unsigned char) *cp
])
3523 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3527 len
= strlen (gotrel
[j
].str
);
3528 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3530 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3533 char *tmpbuf
, *past_reloc
;
3535 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3539 if (GOT_symbol
== NULL
)
3540 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3542 /* Replace the relocation token with ' ', so that
3543 errors like foo@GOTOFF1 will be detected. */
3545 /* The length of the first part of our input line. */
3546 first
= cp
- input_line_pointer
;
3548 /* The second part goes from after the reloc token until
3549 (and including) an end_of_line char. Don't use strlen
3550 here as the end_of_line char may not be a NUL. */
3551 past_reloc
= cp
+ 1 + len
;
3552 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3554 second
= cp
- past_reloc
;
3556 /* Allocate and copy string. The trailing NUL shouldn't
3557 be necessary, but be safe. */
3558 tmpbuf
= xmalloc (first
+ second
+ 2);
3559 memcpy (tmpbuf
, input_line_pointer
, first
);
3560 tmpbuf
[first
] = ' ';
3561 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3562 tmpbuf
[first
+ second
+ 1] = '\0';
3566 as_bad (_("@%s reloc is not supported in %s bit mode"),
3567 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3572 /* Might be a symbol version string. Don't as_bad here. */
3576 /* x86_cons_fix_new is called via the expression parsing code when a
3577 reloc is needed. We use this hook to get the correct .got reloc. */
3578 static RELOC_ENUM got_reloc
= NO_RELOC
;
3581 x86_cons_fix_new (frag
, off
, len
, exp
)
3587 RELOC_ENUM r
= reloc (len
, 0, 0, got_reloc
);
3588 got_reloc
= NO_RELOC
;
3589 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3593 x86_cons (exp
, size
)
3599 /* Handle @GOTOFF and the like in an expression. */
3601 char *gotfree_input_line
;
3604 save
= input_line_pointer
;
3605 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3606 if (gotfree_input_line
)
3607 input_line_pointer
= gotfree_input_line
;
3611 if (gotfree_input_line
)
3613 /* expression () has merrily parsed up to the end of line,
3614 or a comma - in the wrong buffer. Transfer how far
3615 input_line_pointer has moved to the right buffer. */
3616 input_line_pointer
= (save
3617 + (input_line_pointer
- gotfree_input_line
)
3619 free (gotfree_input_line
);
3627 static int i386_immediate
PARAMS ((char *));
3630 i386_immediate (imm_start
)
3633 char *save_input_line_pointer
;
3635 char *gotfree_input_line
;
3640 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3642 as_bad (_("only 1 or 2 immediate operands are allowed"));
3646 exp
= &im_expressions
[i
.imm_operands
++];
3647 i
.op
[this_operand
].imms
= exp
;
3649 if (is_space_char (*imm_start
))
3652 save_input_line_pointer
= input_line_pointer
;
3653 input_line_pointer
= imm_start
;
3656 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3657 if (gotfree_input_line
)
3658 input_line_pointer
= gotfree_input_line
;
3661 exp_seg
= expression (exp
);
3664 if (*input_line_pointer
)
3665 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3667 input_line_pointer
= save_input_line_pointer
;
3669 if (gotfree_input_line
)
3670 free (gotfree_input_line
);
3673 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3675 /* Missing or bad expr becomes absolute 0. */
3676 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3678 exp
->X_op
= O_constant
;
3679 exp
->X_add_number
= 0;
3680 exp
->X_add_symbol
= (symbolS
*) 0;
3681 exp
->X_op_symbol
= (symbolS
*) 0;
3683 else if (exp
->X_op
== O_constant
)
3685 /* Size it properly later. */
3686 i
.types
[this_operand
] |= Imm64
;
3687 /* If BFD64, sign extend val. */
3688 if (!use_rela_relocations
)
3689 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3690 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3692 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3694 #ifdef BFD_ASSEMBLER
3695 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3697 && exp_seg
!= absolute_section
3698 && exp_seg
!= text_section
3699 && exp_seg
!= data_section
3700 && exp_seg
!= bss_section
3701 && exp_seg
!= undefined_section
3702 #ifdef BFD_ASSEMBLER
3703 && !bfd_is_com_section (exp_seg
)
3707 #ifdef BFD_ASSEMBLER
3708 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3710 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3717 /* This is an address. The size of the address will be
3718 determined later, depending on destination register,
3719 suffix, or the default for the section. */
3720 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3726 static char *i386_scale
PARAMS ((char *));
3733 char *save
= input_line_pointer
;
3735 input_line_pointer
= scale
;
3736 val
= get_absolute_expression ();
3742 i
.log2_scale_factor
= 0;
3745 i
.log2_scale_factor
= 1;
3748 i
.log2_scale_factor
= 2;
3751 i
.log2_scale_factor
= 3;
3754 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3756 input_line_pointer
= save
;
3759 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3761 as_warn (_("scale factor of %d without an index register"),
3762 1 << i
.log2_scale_factor
);
3763 #if SCALE1_WHEN_NO_INDEX
3764 i
.log2_scale_factor
= 0;
3767 scale
= input_line_pointer
;
3768 input_line_pointer
= save
;
3772 static int i386_displacement
PARAMS ((char *, char *));
3775 i386_displacement (disp_start
, disp_end
)
3781 char *save_input_line_pointer
;
3783 char *gotfree_input_line
;
3785 int bigdisp
= Disp32
;
3787 if (flag_code
== CODE_64BIT
)
3789 if (i
.prefix
[ADDR_PREFIX
] == 0)
3792 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3794 i
.types
[this_operand
] |= bigdisp
;
3796 exp
= &disp_expressions
[i
.disp_operands
];
3797 i
.op
[this_operand
].disps
= exp
;
3799 save_input_line_pointer
= input_line_pointer
;
3800 input_line_pointer
= disp_start
;
3801 END_STRING_AND_SAVE (disp_end
);
3803 #ifndef GCC_ASM_O_HACK
3804 #define GCC_ASM_O_HACK 0
3807 END_STRING_AND_SAVE (disp_end
+ 1);
3808 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3809 && displacement_string_end
[-1] == '+')
3811 /* This hack is to avoid a warning when using the "o"
3812 constraint within gcc asm statements.
3815 #define _set_tssldt_desc(n,addr,limit,type) \
3816 __asm__ __volatile__ ( \
3818 "movw %w1,2+%0\n\t" \
3820 "movb %b1,4+%0\n\t" \
3821 "movb %4,5+%0\n\t" \
3822 "movb $0,6+%0\n\t" \
3823 "movb %h1,7+%0\n\t" \
3825 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3827 This works great except that the output assembler ends
3828 up looking a bit weird if it turns out that there is
3829 no offset. You end up producing code that looks like:
3842 So here we provide the missing zero. */
3844 *displacement_string_end
= '0';
3848 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3849 if (gotfree_input_line
)
3850 input_line_pointer
= gotfree_input_line
;
3853 exp_seg
= expression (exp
);
3856 if (*input_line_pointer
)
3857 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3859 RESTORE_END_STRING (disp_end
+ 1);
3861 RESTORE_END_STRING (disp_end
);
3862 input_line_pointer
= save_input_line_pointer
;
3864 if (gotfree_input_line
)
3865 free (gotfree_input_line
);
3868 #ifdef BFD_ASSEMBLER
3869 /* We do this to make sure that the section symbol is in
3870 the symbol table. We will ultimately change the relocation
3871 to be relative to the beginning of the section. */
3872 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3873 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3875 if (exp
->X_op
!= O_symbol
)
3877 as_bad (_("bad expression used with @%s"),
3878 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3884 if (S_IS_LOCAL (exp
->X_add_symbol
)
3885 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3886 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3887 exp
->X_op
= O_subtract
;
3888 exp
->X_op_symbol
= GOT_symbol
;
3889 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3890 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3892 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3896 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3898 /* Missing or bad expr becomes absolute 0. */
3899 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3901 exp
->X_op
= O_constant
;
3902 exp
->X_add_number
= 0;
3903 exp
->X_add_symbol
= (symbolS
*) 0;
3904 exp
->X_op_symbol
= (symbolS
*) 0;
3907 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3908 if (exp
->X_op
!= O_constant
3909 #ifdef BFD_ASSEMBLER
3910 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3912 && exp_seg
!= absolute_section
3913 && exp_seg
!= text_section
3914 && exp_seg
!= data_section
3915 && exp_seg
!= bss_section
3916 && exp_seg
!= undefined_section
3917 #ifdef BFD_ASSEMBLER
3918 && !bfd_is_com_section (exp_seg
)
3922 #ifdef BFD_ASSEMBLER
3923 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3925 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3930 else if (flag_code
== CODE_64BIT
)
3931 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3935 static int i386_index_check
PARAMS ((const char *));
3937 /* Make sure the memory operand we've been dealt is valid.
3938 Return 1 on success, 0 on a failure. */
3941 i386_index_check (operand_string
)
3942 const char *operand_string
;
3945 #if INFER_ADDR_PREFIX
3951 if (flag_code
== CODE_64BIT
)
3953 if (i
.prefix
[ADDR_PREFIX
] == 0)
3957 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3958 && (i
.base_reg
->reg_type
!= BaseIndex
3961 && ((i
.index_reg
->reg_type
& (Reg64
| BaseIndex
))
3962 != (Reg64
| BaseIndex
))))
3969 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3971 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
3972 != (Reg32
| BaseIndex
))))
3978 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3982 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
3983 != (Reg16
| BaseIndex
)))
3985 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
3986 != (Reg16
| BaseIndex
))
3988 && i
.base_reg
->reg_num
< 6
3989 && i
.index_reg
->reg_num
>= 6
3990 && i
.log2_scale_factor
== 0))))
3997 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3999 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4000 != (Reg32
| BaseIndex
))))
4006 #if INFER_ADDR_PREFIX
4007 if (flag_code
!= CODE_64BIT
4008 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
4010 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4012 /* Change the size of any displacement too. At most one of
4013 Disp16 or Disp32 is set.
4014 FIXME. There doesn't seem to be any real need for separate
4015 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4016 Removing them would probably clean up the code quite a lot. */
4017 if (i
.types
[this_operand
] & (Disp16
| Disp32
))
4018 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4023 as_bad (_("`%s' is not a valid base/index expression"),
4027 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4029 flag_code_names
[flag_code
]);
4035 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4039 i386_operand (operand_string
)
4040 char *operand_string
;
4044 char *op_string
= operand_string
;
4046 if (is_space_char (*op_string
))
4049 /* We check for an absolute prefix (differentiating,
4050 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4051 if (*op_string
== ABSOLUTE_PREFIX
)
4054 if (is_space_char (*op_string
))
4056 i
.types
[this_operand
] |= JumpAbsolute
;
4059 /* Check if operand is a register. */
4060 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4061 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4063 /* Check for a segment override by searching for ':' after a
4064 segment register. */
4066 if (is_space_char (*op_string
))
4068 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4073 i
.seg
[i
.mem_operands
] = &es
;
4076 i
.seg
[i
.mem_operands
] = &cs
;
4079 i
.seg
[i
.mem_operands
] = &ss
;
4082 i
.seg
[i
.mem_operands
] = &ds
;
4085 i
.seg
[i
.mem_operands
] = &fs
;
4088 i
.seg
[i
.mem_operands
] = &gs
;
4092 /* Skip the ':' and whitespace. */
4094 if (is_space_char (*op_string
))
4097 if (!is_digit_char (*op_string
)
4098 && !is_identifier_char (*op_string
)
4099 && *op_string
!= '('
4100 && *op_string
!= ABSOLUTE_PREFIX
)
4102 as_bad (_("bad memory operand `%s'"), op_string
);
4105 /* Handle case of %es:*foo. */
4106 if (*op_string
== ABSOLUTE_PREFIX
)
4109 if (is_space_char (*op_string
))
4111 i
.types
[this_operand
] |= JumpAbsolute
;
4113 goto do_memory_reference
;
4117 as_bad (_("junk `%s' after register"), op_string
);
4120 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4121 i
.op
[this_operand
].regs
= r
;
4124 else if (*op_string
== REGISTER_PREFIX
)
4126 as_bad (_("bad register name `%s'"), op_string
);
4129 else if (*op_string
== IMMEDIATE_PREFIX
)
4132 if (i
.types
[this_operand
] & JumpAbsolute
)
4134 as_bad (_("immediate operand illegal with absolute jump"));
4137 if (!i386_immediate (op_string
))
4140 else if (is_digit_char (*op_string
)
4141 || is_identifier_char (*op_string
)
4142 || *op_string
== '(')
4144 /* This is a memory reference of some sort. */
4147 /* Start and end of displacement string expression (if found). */
4148 char *displacement_string_start
;
4149 char *displacement_string_end
;
4151 do_memory_reference
:
4152 if ((i
.mem_operands
== 1
4153 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4154 || i
.mem_operands
== 2)
4156 as_bad (_("too many memory references for `%s'"),
4157 current_templates
->start
->name
);
4161 /* Check for base index form. We detect the base index form by
4162 looking for an ')' at the end of the operand, searching
4163 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4165 base_string
= op_string
+ strlen (op_string
);
4168 if (is_space_char (*base_string
))
4171 /* If we only have a displacement, set-up for it to be parsed later. */
4172 displacement_string_start
= op_string
;
4173 displacement_string_end
= base_string
+ 1;
4175 if (*base_string
== ')')
4178 unsigned int parens_balanced
= 1;
4179 /* We've already checked that the number of left & right ()'s are
4180 equal, so this loop will not be infinite. */
4184 if (*base_string
== ')')
4186 if (*base_string
== '(')
4189 while (parens_balanced
);
4191 temp_string
= base_string
;
4193 /* Skip past '(' and whitespace. */
4195 if (is_space_char (*base_string
))
4198 if (*base_string
== ','
4199 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4200 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4202 displacement_string_end
= temp_string
;
4204 i
.types
[this_operand
] |= BaseIndex
;
4208 base_string
= end_op
;
4209 if (is_space_char (*base_string
))
4213 /* There may be an index reg or scale factor here. */
4214 if (*base_string
== ',')
4217 if (is_space_char (*base_string
))
4220 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4221 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4223 base_string
= end_op
;
4224 if (is_space_char (*base_string
))
4226 if (*base_string
== ',')
4229 if (is_space_char (*base_string
))
4232 else if (*base_string
!= ')')
4234 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4239 else if (*base_string
== REGISTER_PREFIX
)
4241 as_bad (_("bad register name `%s'"), base_string
);
4245 /* Check for scale factor. */
4246 if (*base_string
!= ')')
4248 char *end_scale
= i386_scale (base_string
);
4253 base_string
= end_scale
;
4254 if (is_space_char (*base_string
))
4256 if (*base_string
!= ')')
4258 as_bad (_("expecting `)' after scale factor in `%s'"),
4263 else if (!i
.index_reg
)
4265 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4270 else if (*base_string
!= ')')
4272 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4277 else if (*base_string
== REGISTER_PREFIX
)
4279 as_bad (_("bad register name `%s'"), base_string
);
4284 /* If there's an expression beginning the operand, parse it,
4285 assuming displacement_string_start and
4286 displacement_string_end are meaningful. */
4287 if (displacement_string_start
!= displacement_string_end
)
4289 if (!i386_displacement (displacement_string_start
,
4290 displacement_string_end
))
4294 /* Special case for (%dx) while doing input/output op. */
4296 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4298 && i
.log2_scale_factor
== 0
4299 && i
.seg
[i
.mem_operands
] == 0
4300 && (i
.types
[this_operand
] & Disp
) == 0)
4302 i
.types
[this_operand
] = InOutPortReg
;
4306 if (i386_index_check (operand_string
) == 0)
4312 /* It's not a memory operand; argh! */
4313 as_bad (_("invalid char %s beginning operand %d `%s'"),
4314 output_invalid (*op_string
),
4319 return 1; /* Normal return. */
4322 /* md_estimate_size_before_relax()
4324 Called just before relax() for rs_machine_dependent frags. The x86
4325 assembler uses these frags to handle variable size jump
4328 Any symbol that is now undefined will not become defined.
4329 Return the correct fr_subtype in the frag.
4330 Return the initial "guess for variable size of frag" to caller.
4331 The guess is actually the growth beyond the fixed part. Whatever
4332 we do to grow the fixed or variable part contributes to our
4336 md_estimate_size_before_relax (fragP
, segment
)
4340 /* We've already got fragP->fr_subtype right; all we have to do is
4341 check for un-relaxable symbols. On an ELF system, we can't relax
4342 an externally visible symbol, because it may be overridden by a
4344 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4346 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4347 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4348 || S_IS_WEAK (fragP
->fr_symbol
)))
4352 /* Symbol is undefined in this segment, or we need to keep a
4353 reloc so that weak symbols can be overridden. */
4354 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4355 RELOC_ENUM reloc_type
;
4356 unsigned char *opcode
;
4359 if (fragP
->fr_var
!= NO_RELOC
)
4360 reloc_type
= fragP
->fr_var
;
4362 reloc_type
= BFD_RELOC_16_PCREL
;
4364 reloc_type
= BFD_RELOC_32_PCREL
;
4366 old_fr_fix
= fragP
->fr_fix
;
4367 opcode
= (unsigned char *) fragP
->fr_opcode
;
4369 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4372 /* Make jmp (0xeb) a (d)word displacement jump. */
4374 fragP
->fr_fix
+= size
;
4375 fix_new (fragP
, old_fr_fix
, size
,
4377 fragP
->fr_offset
, 1,
4383 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4385 /* Negate the condition, and branch past an
4386 unconditional jump. */
4389 /* Insert an unconditional jump. */
4391 /* We added two extra opcode bytes, and have a two byte
4393 fragP
->fr_fix
+= 2 + 2;
4394 fix_new (fragP
, old_fr_fix
+ 2, 2,
4396 fragP
->fr_offset
, 1,
4403 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4408 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4410 fragP
->fr_offset
, 1,
4412 fixP
->fx_signed
= 1;
4416 /* This changes the byte-displacement jump 0x7N
4417 to the (d)word-displacement jump 0x0f,0x8N. */
4418 opcode
[1] = opcode
[0] + 0x10;
4419 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4420 /* We've added an opcode byte. */
4421 fragP
->fr_fix
+= 1 + size
;
4422 fix_new (fragP
, old_fr_fix
+ 1, size
,
4424 fragP
->fr_offset
, 1,
4429 BAD_CASE (fragP
->fr_subtype
);
4433 return fragP
->fr_fix
- old_fr_fix
;
4436 /* Guess size depending on current relax state. Initially the relax
4437 state will correspond to a short jump and we return 1, because
4438 the variable part of the frag (the branch offset) is one byte
4439 long. However, we can relax a section more than once and in that
4440 case we must either set fr_subtype back to the unrelaxed state,
4441 or return the value for the appropriate branch. */
4442 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4445 /* Called after relax() is finished.
4447 In: Address of frag.
4448 fr_type == rs_machine_dependent.
4449 fr_subtype is what the address relaxed to.
4451 Out: Any fixSs and constants are set up.
4452 Caller will turn frag into a ".space 0". */
4454 #ifndef BFD_ASSEMBLER
4456 md_convert_frag (headers
, sec
, fragP
)
4457 object_headers
*headers ATTRIBUTE_UNUSED
;
4458 segT sec ATTRIBUTE_UNUSED
;
4462 md_convert_frag (abfd
, sec
, fragP
)
4463 bfd
*abfd ATTRIBUTE_UNUSED
;
4464 segT sec ATTRIBUTE_UNUSED
;
4468 unsigned char *opcode
;
4469 unsigned char *where_to_put_displacement
= NULL
;
4470 offsetT target_address
;
4471 offsetT opcode_address
;
4472 unsigned int extension
= 0;
4473 offsetT displacement_from_opcode_start
;
4475 opcode
= (unsigned char *) fragP
->fr_opcode
;
4477 /* Address we want to reach in file space. */
4478 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4480 /* Address opcode resides at in file space. */
4481 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4483 /* Displacement from opcode start to fill into instruction. */
4484 displacement_from_opcode_start
= target_address
- opcode_address
;
4486 if ((fragP
->fr_subtype
& BIG
) == 0)
4488 /* Don't have to change opcode. */
4489 extension
= 1; /* 1 opcode + 1 displacement */
4490 where_to_put_displacement
= &opcode
[1];
4494 if (no_cond_jump_promotion
4495 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4496 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4498 switch (fragP
->fr_subtype
)
4500 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4501 extension
= 4; /* 1 opcode + 4 displacement */
4503 where_to_put_displacement
= &opcode
[1];
4506 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4507 extension
= 2; /* 1 opcode + 2 displacement */
4509 where_to_put_displacement
= &opcode
[1];
4512 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4513 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4514 extension
= 5; /* 2 opcode + 4 displacement */
4515 opcode
[1] = opcode
[0] + 0x10;
4516 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4517 where_to_put_displacement
= &opcode
[2];
4520 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4521 extension
= 3; /* 2 opcode + 2 displacement */
4522 opcode
[1] = opcode
[0] + 0x10;
4523 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4524 where_to_put_displacement
= &opcode
[2];
4527 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4532 where_to_put_displacement
= &opcode
[3];
4536 BAD_CASE (fragP
->fr_subtype
);
4541 /* Now put displacement after opcode. */
4542 md_number_to_chars ((char *) where_to_put_displacement
,
4543 (valueT
) (displacement_from_opcode_start
- extension
),
4544 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4545 fragP
->fr_fix
+= extension
;
4548 /* Size of byte displacement jmp. */
4549 int md_short_jump_size
= 2;
4551 /* Size of dword displacement jmp. */
4552 int md_long_jump_size
= 5;
4554 /* Size of relocation record. */
4555 const int md_reloc_size
= 8;
4558 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4560 addressT from_addr
, to_addr
;
4561 fragS
*frag ATTRIBUTE_UNUSED
;
4562 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4566 offset
= to_addr
- (from_addr
+ 2);
4567 /* Opcode for byte-disp jump. */
4568 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4569 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4573 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4575 addressT from_addr
, to_addr
;
4576 fragS
*frag ATTRIBUTE_UNUSED
;
4577 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4581 offset
= to_addr
- (from_addr
+ 5);
4582 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4583 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4586 /* Apply a fixup (fixS) to segment data, once it has been determined
4587 by our caller that we have all the info we need to fix it up.
4589 On the 386, immediates, displacements, and data pointers are all in
4590 the same (little-endian) format, so we don't need to care about which
4594 md_apply_fix3 (fixP
, valP
, seg
)
4595 /* The fix we're to put in. */
4597 /* Pointer to the value of the bits. */
4599 /* Segment fix is from. */
4600 segT seg ATTRIBUTE_UNUSED
;
4602 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4603 valueT value
= *valP
;
4605 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4608 switch (fixP
->fx_r_type
)
4614 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4617 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4620 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4625 if (fixP
->fx_addsy
!= NULL
4626 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4627 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4628 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4629 && !use_rela_relocations
)
4631 /* This is a hack. There should be a better way to handle this.
4632 This covers for the fact that bfd_install_relocation will
4633 subtract the current location (for partial_inplace, PC relative
4634 relocations); see more below. */
4636 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4638 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4641 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4644 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4646 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4649 || (symbol_section_p (fixP
->fx_addsy
)
4650 && sym_seg
!= absolute_section
))
4651 && !generic_force_reloc (fixP
))
4653 /* Yes, we add the values in twice. This is because
4654 bfd_install_relocation subtracts them out again. I think
4655 bfd_install_relocation is broken, but I don't dare change
4657 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4661 #if defined (OBJ_COFF) && defined (TE_PE)
4662 /* For some reason, the PE format does not store a section
4663 address offset for a PC relative symbol. */
4664 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4665 value
+= md_pcrel_from (fixP
);
4669 /* Fix a few things - the dynamic linker expects certain values here,
4670 and we must not dissappoint it. */
4671 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4672 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4674 switch (fixP
->fx_r_type
)
4676 case BFD_RELOC_386_PLT32
:
4677 case BFD_RELOC_X86_64_PLT32
:
4678 /* Make the jump instruction point to the address of the operand. At
4679 runtime we merely add the offset to the actual PLT entry. */
4683 case BFD_RELOC_386_TLS_GD
:
4684 case BFD_RELOC_386_TLS_LDM
:
4685 case BFD_RELOC_386_TLS_IE_32
:
4686 case BFD_RELOC_386_TLS_IE
:
4687 case BFD_RELOC_386_TLS_GOTIE
:
4688 case BFD_RELOC_X86_64_TLSGD
:
4689 case BFD_RELOC_X86_64_TLSLD
:
4690 case BFD_RELOC_X86_64_GOTTPOFF
:
4691 value
= 0; /* Fully resolved at runtime. No addend. */
4693 case BFD_RELOC_386_TLS_LE
:
4694 case BFD_RELOC_386_TLS_LDO_32
:
4695 case BFD_RELOC_386_TLS_LE_32
:
4696 case BFD_RELOC_X86_64_DTPOFF32
:
4697 case BFD_RELOC_X86_64_TPOFF32
:
4698 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4701 case BFD_RELOC_386_GOT32
:
4702 case BFD_RELOC_X86_64_GOT32
:
4703 value
= 0; /* Fully resolved at runtime. No addend. */
4706 case BFD_RELOC_VTABLE_INHERIT
:
4707 case BFD_RELOC_VTABLE_ENTRY
:
4714 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4716 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4718 /* Are we finished with this relocation now? */
4719 if (fixP
->fx_addsy
== NULL
)
4721 #ifdef BFD_ASSEMBLER
4722 else if (use_rela_relocations
)
4724 fixP
->fx_no_overflow
= 1;
4725 /* Remember value for tc_gen_reloc. */
4726 fixP
->fx_addnumber
= value
;
4730 md_number_to_chars (p
, value
, fixP
->fx_size
);
4733 #define MAX_LITTLENUMS 6
4735 /* Turn the string pointed to by litP into a floating point constant
4736 of type TYPE, and emit the appropriate bytes. The number of
4737 LITTLENUMS emitted is stored in *SIZEP. An error message is
4738 returned, or NULL on OK. */
4741 md_atof (type
, litP
, sizeP
)
4747 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4748 LITTLENUM_TYPE
*wordP
;
4770 return _("Bad call to md_atof ()");
4772 t
= atof_ieee (input_line_pointer
, type
, words
);
4774 input_line_pointer
= t
;
4776 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4777 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4778 the bigendian 386. */
4779 for (wordP
= words
+ prec
- 1; prec
--;)
4781 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4782 litP
+= sizeof (LITTLENUM_TYPE
);
4787 char output_invalid_buf
[8];
4794 sprintf (output_invalid_buf
, "'%c'", c
);
4796 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4797 return output_invalid_buf
;
4800 /* REG_STRING starts *before* REGISTER_PREFIX. */
4802 static const reg_entry
*
4803 parse_register (reg_string
, end_op
)
4807 char *s
= reg_string
;
4809 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4812 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4813 if (*s
== REGISTER_PREFIX
)
4816 if (is_space_char (*s
))
4820 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4822 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4823 return (const reg_entry
*) NULL
;
4827 /* For naked regs, make sure that we are not dealing with an identifier.
4828 This prevents confusing an identifier like `eax_var' with register
4830 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4831 return (const reg_entry
*) NULL
;
4835 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4837 /* Handle floating point regs, allowing spaces in the (i) part. */
4838 if (r
== i386_regtab
/* %st is first entry of table */)
4840 if (is_space_char (*s
))
4845 if (is_space_char (*s
))
4847 if (*s
>= '0' && *s
<= '7')
4849 r
= &i386_float_regtab
[*s
- '0'];
4851 if (is_space_char (*s
))
4859 /* We have "%st(" then garbage. */
4860 return (const reg_entry
*) NULL
;
4865 && (r
->reg_flags
& (RegRex64
| RegRex
)) != 0
4866 && flag_code
!= CODE_64BIT
)
4868 return (const reg_entry
*) NULL
;
4874 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4875 const char *md_shortopts
= "kVQ:sq";
4877 const char *md_shortopts
= "q";
4880 struct option md_longopts
[] = {
4881 #define OPTION_32 (OPTION_MD_BASE + 0)
4882 {"32", no_argument
, NULL
, OPTION_32
},
4883 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4884 #define OPTION_64 (OPTION_MD_BASE + 1)
4885 {"64", no_argument
, NULL
, OPTION_64
},
4887 {NULL
, no_argument
, NULL
, 0}
4889 size_t md_longopts_size
= sizeof (md_longopts
);
4892 md_parse_option (c
, arg
)
4894 char *arg ATTRIBUTE_UNUSED
;
4902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4903 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4904 should be emitted or not. FIXME: Not implemented. */
4908 /* -V: SVR4 argument to print version ID. */
4910 print_version_id ();
4913 /* -k: Ignore for FreeBSD compatibility. */
4918 /* -s: On i386 Solaris, this tells the native assembler to use
4919 .stab instead of .stab.excl. We always use .stab anyhow. */
4924 const char **list
, **l
;
4926 list
= bfd_target_list ();
4927 for (l
= list
; *l
!= NULL
; l
++)
4928 if (strcmp (*l
, "elf64-x86-64") == 0)
4930 default_arch
= "x86_64";
4934 as_fatal (_("No compiled in support for x86_64"));
4941 default_arch
= "i386";
4951 md_show_usage (stream
)
4954 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4955 fprintf (stream
, _("\
4957 -V print assembler version number\n\
4959 -q quieten some warnings\n\
4962 fprintf (stream
, _("\
4963 -q quieten some warnings\n"));
4967 #ifdef BFD_ASSEMBLER
4968 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4969 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4971 /* Pick the target format to use. */
4974 i386_target_format ()
4976 if (!strcmp (default_arch
, "x86_64"))
4977 set_code_flag (CODE_64BIT
);
4978 else if (!strcmp (default_arch
, "i386"))
4979 set_code_flag (CODE_32BIT
);
4981 as_fatal (_("Unknown architecture"));
4982 switch (OUTPUT_FLAVOR
)
4984 #ifdef OBJ_MAYBE_AOUT
4985 case bfd_target_aout_flavour
:
4986 return AOUT_TARGET_FORMAT
;
4988 #ifdef OBJ_MAYBE_COFF
4989 case bfd_target_coff_flavour
:
4992 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4993 case bfd_target_elf_flavour
:
4995 if (flag_code
== CODE_64BIT
)
4996 use_rela_relocations
= 1;
4997 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5006 #endif /* OBJ_MAYBE_ more than one */
5008 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5009 void i386_elf_emit_arch_note ()
5011 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5012 && cpu_arch_name
!= NULL
)
5015 asection
*seg
= now_seg
;
5016 subsegT subseg
= now_subseg
;
5017 Elf_Internal_Note i_note
;
5018 Elf_External_Note e_note
;
5019 asection
*note_secp
;
5022 /* Create the .note section. */
5023 note_secp
= subseg_new (".note", 0);
5024 bfd_set_section_flags (stdoutput
,
5026 SEC_HAS_CONTENTS
| SEC_READONLY
);
5028 /* Process the arch string. */
5029 len
= strlen (cpu_arch_name
);
5031 i_note
.namesz
= len
+ 1;
5033 i_note
.type
= NT_ARCH
;
5034 p
= frag_more (sizeof (e_note
.namesz
));
5035 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5036 p
= frag_more (sizeof (e_note
.descsz
));
5037 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5038 p
= frag_more (sizeof (e_note
.type
));
5039 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5040 p
= frag_more (len
+ 1);
5041 strcpy (p
, cpu_arch_name
);
5043 frag_align (2, 0, 0);
5045 subseg_set (seg
, subseg
);
5049 #endif /* BFD_ASSEMBLER */
5052 md_undefined_symbol (name
)
5055 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5056 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5057 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5058 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5062 if (symbol_find (name
))
5063 as_bad (_("GOT already in symbol table"));
5064 GOT_symbol
= symbol_new (name
, undefined_section
,
5065 (valueT
) 0, &zero_address_frag
);
5072 /* Round up a section size to the appropriate boundary. */
5075 md_section_align (segment
, size
)
5076 segT segment ATTRIBUTE_UNUSED
;
5079 #ifdef BFD_ASSEMBLER
5080 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5081 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5083 /* For a.out, force the section size to be aligned. If we don't do
5084 this, BFD will align it for us, but it will not write out the
5085 final bytes of the section. This may be a bug in BFD, but it is
5086 easier to fix it here since that is how the other a.out targets
5090 align
= bfd_get_section_alignment (stdoutput
, segment
);
5091 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5099 /* On the i386, PC-relative offsets are relative to the start of the
5100 next instruction. That is, the address of the offset, plus its
5101 size, since the offset is always the last part of the insn. */
5104 md_pcrel_from (fixP
)
5107 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5114 int ignore ATTRIBUTE_UNUSED
;
5118 temp
= get_absolute_expression ();
5119 subseg_set (bss_section
, (subsegT
) temp
);
5120 demand_empty_rest_of_line ();
5125 #ifdef BFD_ASSEMBLER
5128 i386_validate_fix (fixp
)
5131 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5133 /* GOTOFF relocation are nonsense in 64bit mode. */
5134 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5136 if (flag_code
!= CODE_64BIT
)
5138 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5142 if (flag_code
== CODE_64BIT
)
5144 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5151 tc_gen_reloc (section
, fixp
)
5152 asection
*section ATTRIBUTE_UNUSED
;
5156 bfd_reloc_code_real_type code
;
5158 switch (fixp
->fx_r_type
)
5160 case BFD_RELOC_X86_64_PLT32
:
5161 case BFD_RELOC_X86_64_GOT32
:
5162 case BFD_RELOC_X86_64_GOTPCREL
:
5163 case BFD_RELOC_386_PLT32
:
5164 case BFD_RELOC_386_GOT32
:
5165 case BFD_RELOC_386_GOTOFF
:
5166 case BFD_RELOC_386_GOTPC
:
5167 case BFD_RELOC_386_TLS_GD
:
5168 case BFD_RELOC_386_TLS_LDM
:
5169 case BFD_RELOC_386_TLS_LDO_32
:
5170 case BFD_RELOC_386_TLS_IE_32
:
5171 case BFD_RELOC_386_TLS_IE
:
5172 case BFD_RELOC_386_TLS_GOTIE
:
5173 case BFD_RELOC_386_TLS_LE_32
:
5174 case BFD_RELOC_386_TLS_LE
:
5175 case BFD_RELOC_X86_64_32S
:
5176 case BFD_RELOC_X86_64_TLSGD
:
5177 case BFD_RELOC_X86_64_TLSLD
:
5178 case BFD_RELOC_X86_64_DTPOFF32
:
5179 case BFD_RELOC_X86_64_GOTTPOFF
:
5180 case BFD_RELOC_X86_64_TPOFF32
:
5182 case BFD_RELOC_VTABLE_ENTRY
:
5183 case BFD_RELOC_VTABLE_INHERIT
:
5184 code
= fixp
->fx_r_type
;
5189 switch (fixp
->fx_size
)
5192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5193 _("can not do %d byte pc-relative relocation"),
5195 code
= BFD_RELOC_32_PCREL
;
5197 case 1: code
= BFD_RELOC_8_PCREL
; break;
5198 case 2: code
= BFD_RELOC_16_PCREL
; break;
5199 case 4: code
= BFD_RELOC_32_PCREL
; break;
5204 switch (fixp
->fx_size
)
5207 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5208 _("can not do %d byte relocation"),
5210 code
= BFD_RELOC_32
;
5212 case 1: code
= BFD_RELOC_8
; break;
5213 case 2: code
= BFD_RELOC_16
; break;
5214 case 4: code
= BFD_RELOC_32
; break;
5216 case 8: code
= BFD_RELOC_64
; break;
5223 if (code
== BFD_RELOC_32
5225 && fixp
->fx_addsy
== GOT_symbol
)
5227 /* We don't support GOTPC on 64bit targets. */
5228 if (flag_code
== CODE_64BIT
)
5230 code
= BFD_RELOC_386_GOTPC
;
5233 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5234 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5235 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5237 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5238 if (!use_rela_relocations
)
5240 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5241 vtable entry to be used in the relocation's section offset. */
5242 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5243 rel
->address
= fixp
->fx_offset
;
5247 /* Use the rela in 64bit mode. */
5250 if (!fixp
->fx_pcrel
)
5251 rel
->addend
= fixp
->fx_offset
;
5255 case BFD_RELOC_X86_64_PLT32
:
5256 case BFD_RELOC_X86_64_GOT32
:
5257 case BFD_RELOC_X86_64_GOTPCREL
:
5258 case BFD_RELOC_X86_64_TLSGD
:
5259 case BFD_RELOC_X86_64_TLSLD
:
5260 case BFD_RELOC_X86_64_GOTTPOFF
:
5261 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5264 rel
->addend
= (section
->vma
5266 + fixp
->fx_addnumber
5267 + md_pcrel_from (fixp
));
5272 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5273 if (rel
->howto
== NULL
)
5275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5276 _("cannot represent relocation type %s"),
5277 bfd_get_reloc_code_name (code
));
5278 /* Set howto to a garbage value so that we can keep going. */
5279 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5280 assert (rel
->howto
!= NULL
);
5286 #else /* !BFD_ASSEMBLER */
5288 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5290 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
5293 relax_addressT segment_address_in_file
;
5295 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5296 Out: GNU LD relocation length code: 0, 1, or 2. */
5298 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
5301 know (fixP
->fx_addsy
!= NULL
);
5303 md_number_to_chars (where
,
5304 (valueT
) (fixP
->fx_frag
->fr_address
5305 + fixP
->fx_where
- segment_address_in_file
),
5308 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
5309 ? S_GET_TYPE (fixP
->fx_addsy
)
5310 : fixP
->fx_addsy
->sy_number
);
5312 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
5313 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
5314 where
[4] = r_symbolnum
& 0x0ff;
5315 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
5316 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
5317 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
5320 #endif /* OBJ_AOUT or OBJ_BOUT. */
5322 #if defined (I386COFF)
5325 tc_coff_fix2rtype (fixP
)
5328 if (fixP
->fx_r_type
== R_IMAGEBASE
)
5331 return (fixP
->fx_pcrel
?
5332 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
5333 fixP
->fx_size
== 2 ? R_PCRWORD
:
5335 (fixP
->fx_size
== 1 ? R_RELBYTE
:
5336 fixP
->fx_size
== 2 ? R_RELWORD
:
5341 tc_coff_sizemachdep (frag
)
5345 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
5350 #endif /* I386COFF */
5352 #endif /* !BFD_ASSEMBLER */
5354 /* Parse operands using Intel syntax. This implements a recursive descent
5355 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5358 FIXME: We do not recognize the full operand grammar defined in the MASM
5359 documentation. In particular, all the structure/union and
5360 high-level macro operands are missing.
5362 Uppercase words are terminals, lower case words are non-terminals.
5363 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5364 bars '|' denote choices. Most grammar productions are implemented in
5365 functions called 'intel_<production>'.
5367 Initial production is 'expr'.
5373 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5375 constant digits [[ radixOverride ]]
5377 dataType BYTE | WORD | DWORD | QWORD | XWORD
5410 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5411 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5413 hexdigit a | b | c | d | e | f
5414 | A | B | C | D | E | F
5424 register specialRegister
5428 segmentRegister CS | DS | ES | FS | GS | SS
5430 specialRegister CR0 | CR2 | CR3
5431 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5432 | TR3 | TR4 | TR5 | TR6 | TR7
5434 We simplify the grammar in obvious places (e.g., register parsing is
5435 done by calling parse_register) and eliminate immediate left recursion
5436 to implement a recursive-descent parser.
5476 /* Parsing structure for the intel syntax parser. Used to implement the
5477 semantic actions for the operand grammar. */
5478 struct intel_parser_s
5480 char *op_string
; /* The string being parsed. */
5481 int got_a_float
; /* Whether the operand is a float. */
5482 int op_modifier
; /* Operand modifier. */
5483 int is_mem
; /* 1 if operand is memory reference. */
5484 const reg_entry
*reg
; /* Last register reference found. */
5485 char *disp
; /* Displacement string being built. */
5488 static struct intel_parser_s intel_parser
;
5490 /* Token structure for parsing intel syntax. */
5493 int code
; /* Token code. */
5494 const reg_entry
*reg
; /* Register entry for register tokens. */
5495 char *str
; /* String representation. */
5498 static struct intel_token cur_token
, prev_token
;
5500 /* Token codes for the intel parser. Since T_SHORT is already used
5501 by COFF, undefine it first to prevent a warning. */
5516 /* Prototypes for intel parser functions. */
5517 static int intel_match_token
PARAMS ((int code
));
5518 static void intel_get_token
PARAMS ((void));
5519 static void intel_putback_token
PARAMS ((void));
5520 static int intel_expr
PARAMS ((void));
5521 static int intel_e05
PARAMS ((void));
5522 static int intel_e05_1
PARAMS ((void));
5523 static int intel_e06
PARAMS ((void));
5524 static int intel_e06_1
PARAMS ((void));
5525 static int intel_e09
PARAMS ((void));
5526 static int intel_e09_1
PARAMS ((void));
5527 static int intel_e10
PARAMS ((void));
5528 static int intel_e10_1
PARAMS ((void));
5529 static int intel_e11
PARAMS ((void));
5532 i386_intel_operand (operand_string
, got_a_float
)
5533 char *operand_string
;
5539 /* Initialize token holders. */
5540 cur_token
.code
= prev_token
.code
= T_NIL
;
5541 cur_token
.reg
= prev_token
.reg
= NULL
;
5542 cur_token
.str
= prev_token
.str
= NULL
;
5544 /* Initialize parser structure. */
5545 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5548 strcpy (intel_parser
.op_string
, operand_string
);
5549 intel_parser
.got_a_float
= got_a_float
;
5550 intel_parser
.op_modifier
= -1;
5551 intel_parser
.is_mem
= 0;
5552 intel_parser
.reg
= NULL
;
5553 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5554 if (intel_parser
.disp
== NULL
)
5556 intel_parser
.disp
[0] = '\0';
5558 /* Read the first token and start the parser. */
5560 ret
= intel_expr ();
5564 /* If we found a memory reference, hand it over to i386_displacement
5565 to fill in the rest of the operand fields. */
5566 if (intel_parser
.is_mem
)
5568 if ((i
.mem_operands
== 1
5569 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5570 || i
.mem_operands
== 2)
5572 as_bad (_("too many memory references for '%s'"),
5573 current_templates
->start
->name
);
5578 char *s
= intel_parser
.disp
;
5581 /* Add the displacement expression. */
5583 ret
= i386_displacement (s
, s
+ strlen (s
))
5584 && i386_index_check (s
);
5588 /* Constant and OFFSET expressions are handled by i386_immediate. */
5589 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5590 || intel_parser
.reg
== NULL
)
5591 ret
= i386_immediate (intel_parser
.disp
);
5595 free (intel_parser
.disp
);
5605 /* expr SHORT e05 */
5606 if (cur_token
.code
== T_SHORT
)
5608 intel_parser
.op_modifier
= SHORT
;
5609 intel_match_token (T_SHORT
);
5611 return (intel_e05 ());
5616 return intel_e05 ();
5626 return (intel_e06 () && intel_e05_1 ());
5632 /* e05' addOp e06 e05' */
5633 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5635 strcat (intel_parser
.disp
, cur_token
.str
);
5636 intel_match_token (cur_token
.code
);
5638 return (intel_e06 () && intel_e05_1 ());
5653 return (intel_e09 () && intel_e06_1 ());
5659 /* e06' mulOp e09 e06' */
5660 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5662 strcat (intel_parser
.disp
, cur_token
.str
);
5663 intel_match_token (cur_token
.code
);
5665 return (intel_e09 () && intel_e06_1 ());
5673 /* e09 OFFSET e10 e09'
5682 /* e09 OFFSET e10 e09' */
5683 if (cur_token
.code
== T_OFFSET
)
5685 intel_parser
.is_mem
= 0;
5686 intel_parser
.op_modifier
= OFFSET_FLAT
;
5687 intel_match_token (T_OFFSET
);
5689 return (intel_e10 () && intel_e09_1 ());
5694 return (intel_e10 () && intel_e09_1 ());
5700 /* e09' PTR e10 e09' */
5701 if (cur_token
.code
== T_PTR
)
5703 if (prev_token
.code
== T_BYTE
)
5704 i
.suffix
= BYTE_MNEM_SUFFIX
;
5706 else if (prev_token
.code
== T_WORD
)
5708 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5709 i
.suffix
= SHORT_MNEM_SUFFIX
;
5711 i
.suffix
= WORD_MNEM_SUFFIX
;
5714 else if (prev_token
.code
== T_DWORD
)
5716 if (intel_parser
.got_a_float
== 1) /* "f..." */
5717 i
.suffix
= SHORT_MNEM_SUFFIX
;
5719 i
.suffix
= LONG_MNEM_SUFFIX
;
5722 else if (prev_token
.code
== T_QWORD
)
5724 if (intel_parser
.got_a_float
== 1) /* "f..." */
5725 i
.suffix
= LONG_MNEM_SUFFIX
;
5727 i
.suffix
= QWORD_MNEM_SUFFIX
;
5730 else if (prev_token
.code
== T_XWORD
)
5731 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5735 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5739 intel_match_token (T_PTR
);
5741 return (intel_e10 () && intel_e09_1 ());
5744 /* e09 : e10 e09' */
5745 else if (cur_token
.code
== ':')
5747 /* Mark as a memory operand only if it's not already known to be an
5748 offset expression. */
5749 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5750 intel_parser
.is_mem
= 1;
5752 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5767 return (intel_e11 () && intel_e10_1 ());
5773 /* e10' [ expr ] e10' */
5774 if (cur_token
.code
== '[')
5776 intel_match_token ('[');
5778 /* Mark as a memory operand only if it's not already known to be an
5779 offset expression. If it's an offset expression, we need to keep
5781 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5782 intel_parser
.is_mem
= 1;
5784 strcat (intel_parser
.disp
, "[");
5786 /* Add a '+' to the displacement string if necessary. */
5787 if (*intel_parser
.disp
!= '\0'
5788 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5789 strcat (intel_parser
.disp
, "+");
5791 if (intel_expr () && intel_match_token (']'))
5793 /* Preserve brackets when the operand is an offset expression. */
5794 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5795 strcat (intel_parser
.disp
, "]");
5797 return intel_e10_1 ();
5824 if (cur_token
.code
== '(')
5826 intel_match_token ('(');
5827 strcat (intel_parser
.disp
, "(");
5829 if (intel_expr () && intel_match_token (')'))
5831 strcat (intel_parser
.disp
, ")");
5839 else if (cur_token
.code
== '[')
5841 intel_match_token ('[');
5843 /* Mark as a memory operand only if it's not already known to be an
5844 offset expression. If it's an offset expression, we need to keep
5846 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5847 intel_parser
.is_mem
= 1;
5849 strcat (intel_parser
.disp
, "[");
5851 /* Operands for jump/call inside brackets denote absolute addresses. */
5852 if (current_templates
->start
->opcode_modifier
& Jump
5853 || current_templates
->start
->opcode_modifier
& JumpDword
5854 || current_templates
->start
->opcode_modifier
& JumpByte
5855 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5856 i
.types
[this_operand
] |= JumpAbsolute
;
5858 /* Add a '+' to the displacement string if necessary. */
5859 if (*intel_parser
.disp
!= '\0'
5860 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5861 strcat (intel_parser
.disp
, "+");
5863 if (intel_expr () && intel_match_token (']'))
5865 /* Preserve brackets when the operand is an offset expression. */
5866 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5867 strcat (intel_parser
.disp
, "]");
5880 else if (cur_token
.code
== T_BYTE
5881 || cur_token
.code
== T_WORD
5882 || cur_token
.code
== T_DWORD
5883 || cur_token
.code
== T_QWORD
5884 || cur_token
.code
== T_XWORD
)
5886 intel_match_token (cur_token
.code
);
5893 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5895 strcat (intel_parser
.disp
, cur_token
.str
);
5896 intel_match_token (cur_token
.code
);
5898 /* Mark as a memory operand only if it's not already known to be an
5899 offset expression. */
5900 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5901 intel_parser
.is_mem
= 1;
5907 else if (cur_token
.code
== T_REG
)
5909 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5911 intel_match_token (T_REG
);
5913 /* Check for segment change. */
5914 if (cur_token
.code
== ':')
5916 if (reg
->reg_type
& (SReg2
| SReg3
))
5918 switch (reg
->reg_num
)
5921 i
.seg
[i
.mem_operands
] = &es
;
5924 i
.seg
[i
.mem_operands
] = &cs
;
5927 i
.seg
[i
.mem_operands
] = &ss
;
5930 i
.seg
[i
.mem_operands
] = &ds
;
5933 i
.seg
[i
.mem_operands
] = &fs
;
5936 i
.seg
[i
.mem_operands
] = &gs
;
5942 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5947 /* Not a segment register. Check for register scaling. */
5948 else if (cur_token
.code
== '*')
5950 if (!intel_parser
.is_mem
)
5952 as_bad (_("Register scaling only allowed in memory operands."));
5956 /* What follows must be a valid scale. */
5957 if (intel_match_token ('*')
5958 && strchr ("01248", *cur_token
.str
))
5961 i
.types
[this_operand
] |= BaseIndex
;
5963 /* Set the scale after setting the register (otherwise,
5964 i386_scale will complain) */
5965 i386_scale (cur_token
.str
);
5966 intel_match_token (T_CONST
);
5970 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5976 /* No scaling. If this is a memory operand, the register is either a
5977 base register (first occurrence) or an index register (second
5979 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5981 if (i
.base_reg
&& i
.index_reg
)
5983 as_bad (_("Too many register references in memory operand.\n"));
5987 if (i
.base_reg
== NULL
)
5992 i
.types
[this_operand
] |= BaseIndex
;
5995 /* Offset modifier. Add the register to the displacement string to be
5996 parsed as an immediate expression after we're done. */
5997 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5998 strcat (intel_parser
.disp
, reg
->reg_name
);
6000 /* It's neither base nor index nor offset. */
6003 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
6004 i
.op
[this_operand
].regs
= reg
;
6008 /* Since registers are not part of the displacement string (except
6009 when we're parsing offset operands), we may need to remove any
6010 preceding '+' from the displacement string. */
6011 if (*intel_parser
.disp
!= '\0'
6012 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
6014 char *s
= intel_parser
.disp
;
6015 s
+= strlen (s
) - 1;
6024 else if (cur_token
.code
== T_ID
)
6026 /* Add the identifier to the displacement string. */
6027 strcat (intel_parser
.disp
, cur_token
.str
);
6028 intel_match_token (T_ID
);
6030 /* The identifier represents a memory reference only if it's not
6031 preceded by an offset modifier. */
6032 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
6033 intel_parser
.is_mem
= 1;
6039 else if (cur_token
.code
== T_CONST
6040 || cur_token
.code
== '-'
6041 || cur_token
.code
== '+')
6045 /* Allow constants that start with `+' or `-'. */
6046 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6048 strcat (intel_parser
.disp
, cur_token
.str
);
6049 intel_match_token (cur_token
.code
);
6050 if (cur_token
.code
!= T_CONST
)
6052 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6058 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6059 if (save_str
== NULL
)
6061 strcpy (save_str
, cur_token
.str
);
6063 /* Get the next token to check for register scaling. */
6064 intel_match_token (cur_token
.code
);
6066 /* Check if this constant is a scaling factor for an index register. */
6067 if (cur_token
.code
== '*')
6069 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6071 if (!intel_parser
.is_mem
)
6073 as_bad (_("Register scaling only allowed in memory operands."));
6077 /* The constant is followed by `* reg', so it must be
6079 if (strchr ("01248", *save_str
))
6081 i
.index_reg
= cur_token
.reg
;
6082 i
.types
[this_operand
] |= BaseIndex
;
6084 /* Set the scale after setting the register (otherwise,
6085 i386_scale will complain) */
6086 i386_scale (save_str
);
6087 intel_match_token (T_REG
);
6089 /* Since registers are not part of the displacement
6090 string, we may need to remove any preceding '+' from
6091 the displacement string. */
6092 if (*intel_parser
.disp
!= '\0')
6094 char *s
= intel_parser
.disp
;
6095 s
+= strlen (s
) - 1;
6108 /* The constant was not used for register scaling. Since we have
6109 already consumed the token following `*' we now need to put it
6110 back in the stream. */
6112 intel_putback_token ();
6115 /* Add the constant to the displacement string. */
6116 strcat (intel_parser
.disp
, save_str
);
6122 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6126 /* Match the given token against cur_token. If they match, read the next
6127 token from the operand string. */
6129 intel_match_token (code
)
6132 if (cur_token
.code
== code
)
6139 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
6144 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6149 const reg_entry
*reg
;
6150 struct intel_token new_token
;
6152 new_token
.code
= T_NIL
;
6153 new_token
.reg
= NULL
;
6154 new_token
.str
= NULL
;
6156 /* Free the memory allocated to the previous token and move
6157 cur_token to prev_token. */
6159 free (prev_token
.str
);
6161 prev_token
= cur_token
;
6163 /* Skip whitespace. */
6164 while (is_space_char (*intel_parser
.op_string
))
6165 intel_parser
.op_string
++;
6167 /* Return an empty token if we find nothing else on the line. */
6168 if (*intel_parser
.op_string
== '\0')
6170 cur_token
= new_token
;
6174 /* The new token cannot be larger than the remainder of the operand
6176 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6177 if (new_token
.str
== NULL
)
6179 new_token
.str
[0] = '\0';
6181 if (strchr ("0123456789", *intel_parser
.op_string
))
6183 char *p
= new_token
.str
;
6184 char *q
= intel_parser
.op_string
;
6185 new_token
.code
= T_CONST
;
6187 /* Allow any kind of identifier char to encompass floating point and
6188 hexadecimal numbers. */
6189 while (is_identifier_char (*q
))
6193 /* Recognize special symbol names [0-9][bf]. */
6194 if (strlen (intel_parser
.op_string
) == 2
6195 && (intel_parser
.op_string
[1] == 'b'
6196 || intel_parser
.op_string
[1] == 'f'))
6197 new_token
.code
= T_ID
;
6200 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
6202 new_token
.code
= *intel_parser
.op_string
;
6203 new_token
.str
[0] = *intel_parser
.op_string
;
6204 new_token
.str
[1] = '\0';
6207 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6208 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6210 new_token
.code
= T_REG
;
6211 new_token
.reg
= reg
;
6213 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6215 new_token
.str
[0] = REGISTER_PREFIX
;
6216 new_token
.str
[1] = '\0';
6219 strcat (new_token
.str
, reg
->reg_name
);
6222 else if (is_identifier_char (*intel_parser
.op_string
))
6224 char *p
= new_token
.str
;
6225 char *q
= intel_parser
.op_string
;
6227 /* A '.' or '$' followed by an identifier char is an identifier.
6228 Otherwise, it's operator '.' followed by an expression. */
6229 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6231 new_token
.code
= *q
;
6232 new_token
.str
[0] = *q
;
6233 new_token
.str
[1] = '\0';
6237 while (is_identifier_char (*q
) || *q
== '@')
6241 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6242 new_token
.code
= T_BYTE
;
6244 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6245 new_token
.code
= T_WORD
;
6247 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6248 new_token
.code
= T_DWORD
;
6250 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6251 new_token
.code
= T_QWORD
;
6253 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6254 new_token
.code
= T_XWORD
;
6256 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6257 new_token
.code
= T_PTR
;
6259 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6260 new_token
.code
= T_SHORT
;
6262 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6264 new_token
.code
= T_OFFSET
;
6266 /* ??? This is not mentioned in the MASM grammar but gcc
6267 makes use of it with -mintel-syntax. OFFSET may be
6268 followed by FLAT: */
6269 if (strncasecmp (q
, " FLAT:", 6) == 0)
6270 strcat (new_token
.str
, " FLAT:");
6273 /* ??? This is not mentioned in the MASM grammar. */
6274 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6275 new_token
.code
= T_OFFSET
;
6278 new_token
.code
= T_ID
;
6283 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
6285 intel_parser
.op_string
+= strlen (new_token
.str
);
6286 cur_token
= new_token
;
6289 /* Put cur_token back into the token stream and make cur_token point to
6292 intel_putback_token ()
6294 intel_parser
.op_string
-= strlen (cur_token
.str
);
6295 free (cur_token
.str
);
6296 cur_token
= prev_token
;
6298 /* Forget prev_token. */
6299 prev_token
.code
= T_NIL
;
6300 prev_token
.reg
= NULL
;
6301 prev_token
.str
= NULL
;
6305 tc_x86_cfi_init (void)
6307 struct cfi_config cfi_config
;
6309 if (flag_code
== CODE_64BIT
)
6311 cfi_config
.addr_length
= 8;
6312 cfi_config
.eh_align
= 8;
6313 cfi_config
.code_align
= 1;
6314 cfi_config
.data_align
= -8;
6315 cfi_config
.ra_column
= 0x10;
6316 cfi_config
.reloc_type
= BFD_RELOC_64
;
6320 cfi_config
.addr_length
= 4;
6321 cfi_config
.eh_align
= 4;
6322 cfi_config
.code_align
= 1;
6323 cfi_config
.data_align
= -4;
6324 cfi_config
.ra_column
= 0x08;
6325 cfi_config
.reloc_type
= BFD_RELOC_32
;
6328 cfi_set_config (&cfi_config
);
6332 tc_x86_regname_to_dw2regnum (const char *regname
)
6334 unsigned int regnum
;
6335 unsigned int regnames_count
;
6336 char *regnames_32
[] =
6338 "eax", "ebx", "ecx", "edx",
6339 "edi", "esi", "ebp", "esp",
6342 char *regnames_64
[] =
6344 "rax", "rbx", "rcx", "rdx",
6345 "rdi", "rsi", "rbp", "rsp",
6346 "r8", "r9", "r10", "r11",
6347 "r12", "r13", "r14", "r15",
6352 if (flag_code
== CODE_64BIT
)
6354 regnames
= regnames_64
;
6355 regnames_count
= sizeof (regnames_64
);
6359 regnames
= regnames_32
;
6360 regnames_count
= sizeof (regnames_32
);
6363 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6364 if (strcmp (regname
, regnames
[regnum
]) == 0)
6367 as_bad (_("unknown register name '%s'"), regname
);
6372 tc_x86_frame_initial_instructions (void)
6374 if (flag_code
== CODE_64BIT
)
6376 cfi_add_insn (CFA_def_cfa
, tc_x86_regname_to_dw2regnum ("rsp"), 8);
6377 cfi_add_insn (CFA_offset
, tc_x86_regname_to_dw2regnum ("rip"), -8);
6381 cfi_add_insn (CFA_def_cfa
, tc_x86_regname_to_dw2regnum ("esp"), 4);
6382 cfi_add_insn (CFA_offset
, tc_x86_regname_to_dw2regnum ("eip"), -4);