1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE
unsigned int mode_from_disp_size
PARAMS ((unsigned int));
67 static INLINE
int fits_in_signed_byte
PARAMS ((offsetT
));
68 static INLINE
int fits_in_unsigned_byte
PARAMS ((offsetT
));
69 static INLINE
int fits_in_unsigned_word
PARAMS ((offsetT
));
70 static INLINE
int fits_in_signed_word
PARAMS ((offsetT
));
71 static INLINE
int fits_in_unsigned_long
PARAMS ((offsetT
));
72 static INLINE
int fits_in_signed_long
PARAMS ((offsetT
));
73 static int smallest_imm_type
PARAMS ((offsetT
));
74 static offsetT offset_in_range
PARAMS ((offsetT
, int));
75 static int add_prefix
PARAMS ((unsigned int));
76 static void set_code_flag
PARAMS ((int));
77 static void set_16bit_gcc_code_flag
PARAMS ((int));
78 static void set_intel_syntax
PARAMS ((int));
79 static void set_cpu_arch
PARAMS ((int));
81 static void pe_directive_secrel
PARAMS ((int));
83 static char *output_invalid
PARAMS ((int c
));
84 static int i386_operand
PARAMS ((char *operand_string
));
85 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
86 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
88 static char *parse_insn
PARAMS ((char *, char *));
89 static char *parse_operands
PARAMS ((char *, const char *));
90 static void swap_operands
PARAMS ((void));
91 static void optimize_imm
PARAMS ((void));
92 static void optimize_disp
PARAMS ((void));
93 static int match_template
PARAMS ((void));
94 static int check_string
PARAMS ((void));
95 static int process_suffix
PARAMS ((void));
96 static int check_byte_reg
PARAMS ((void));
97 static int check_long_reg
PARAMS ((void));
98 static int check_qword_reg
PARAMS ((void));
99 static int check_word_reg
PARAMS ((void));
100 static int finalize_imm
PARAMS ((void));
101 static int process_operands
PARAMS ((void));
102 static const seg_entry
*build_modrm_byte
PARAMS ((void));
103 static void output_insn
PARAMS ((void));
104 static void output_branch
PARAMS ((void));
105 static void output_jump
PARAMS ((void));
106 static void output_interseg_jump
PARAMS ((void));
107 static void output_imm
PARAMS ((fragS
*insn_start_frag
,
108 offsetT insn_start_off
));
109 static void output_disp
PARAMS ((fragS
*insn_start_frag
,
110 offsetT insn_start_off
));
112 static void s_bss
PARAMS ((int));
115 static const char *default_arch
= DEFAULT_ARCH
;
117 /* 'md_assemble ()' gathers together information and puts it into a
124 const reg_entry
*regs
;
129 /* TM holds the template for the insn were currently assembling. */
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
136 /* OPERANDS gives the number of given operands. */
137 unsigned int operands
;
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
142 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
144 /* TYPES [i] is the type (see above #defines) which tells us how to
145 use OP[i] for the corresponding operand. */
146 unsigned int types
[MAX_OPERANDS
];
148 /* Displacement expression, immediate expression, or register for each
150 union i386_op op
[MAX_OPERANDS
];
152 /* Flags for operands. */
153 unsigned int flags
[MAX_OPERANDS
];
154 #define Operand_PCrel 1
156 /* Relocation type for operand */
157 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry
*base_reg
;
162 const reg_entry
*index_reg
;
163 unsigned int log2_scale_factor
;
165 /* SEG gives the seg_entries of this insn. They are zero unless
166 explicit segment overrides are given. */
167 const seg_entry
*seg
[2];
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes
;
172 unsigned char prefix
[MAX_PREFIXES
];
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
182 typedef struct _i386_insn i386_insn
;
184 /* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186 const char extra_symbol_chars
[] = "*%-(["
195 #if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
198 && !defined (TE_NETWARE) \
199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
201 /* This array holds the chars that always start a comment. If the
202 pre-processor is disabled, these aren't very useful. */
203 const char comment_chars
[] = "#/";
204 #define PREFIX_SEPARATOR '\\'
206 /* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
210 first line of the input file. This is because the compiler outputs
211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
213 '/' isn't otherwise defined. */
214 const char line_comment_chars
[] = "#";
217 /* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219 const char comment_chars
[] = "#";
220 #define PREFIX_SEPARATOR '/'
222 const char line_comment_chars
[] = "/#";
225 const char line_separator_chars
[] = ";";
227 /* Chars that can be used to separate mant from exp in floating point
229 const char EXP_CHARS
[] = "eE";
231 /* Chars that mean this number is a floating point constant
234 const char FLT_CHARS
[] = "fFdDxX";
236 /* Tables for lexical analysis. */
237 static char mnemonic_chars
[256];
238 static char register_chars
[256];
239 static char operand_chars
[256];
240 static char identifier_chars
[256];
241 static char digit_chars
[256];
243 /* Lexical macros. */
244 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245 #define is_operand_char(x) (operand_chars[(unsigned char) x])
246 #define is_register_char(x) (register_chars[(unsigned char) x])
247 #define is_space_char(x) ((x) == ' ')
248 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249 #define is_digit_char(x) (digit_chars[(unsigned char) x])
251 /* All non-digit non-letter characters that may occur in an operand. */
252 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
254 /* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
257 assembler instruction). */
258 static char save_stack
[32];
259 static char *save_stack_p
;
260 #define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262 #define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
265 /* The instruction we're assembling. */
268 /* Possible templates for current insn. */
269 static const templates
*current_templates
;
271 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
272 static expressionS disp_expressions
[2], im_expressions
[2];
274 /* Current operand we are working on. */
275 static int this_operand
;
277 /* We support four different modes. FLAG_CODE variable is used to distinguish
284 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
286 static enum flag_code flag_code
;
287 static int use_rela_relocations
= 0;
289 /* The names used to print error messages. */
290 static const char *flag_code_names
[] =
297 /* 1 for intel syntax,
299 static int intel_syntax
= 0;
301 /* 1 if register prefix % not required. */
302 static int allow_naked_reg
= 0;
304 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307 static char stackop_size
= '\0';
309 /* Non-zero to optimize code alignment. */
310 int optimize_align_code
= 1;
312 /* Non-zero to quieten some warnings. */
313 static int quiet_warnings
= 0;
316 static const char *cpu_arch_name
= NULL
;
318 /* CPU feature flags. */
319 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
321 /* If set, conditional jumps are not automatically promoted to handle
322 larger than a byte offset. */
323 static unsigned int no_cond_jump_promotion
= 0;
325 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
328 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
329 unsigned int x86_dwarf2_return_column
;
331 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
332 int x86_cie_data_alignment
;
334 /* Interface to relax_segment.
335 There are 3 major relax states for 386 jump insns because the
336 different types of jumps add different sizes to frags when we're
337 figuring out what sort of jump to choose to reach a given label. */
340 #define UNCOND_JUMP 0
342 #define COND_JUMP86 2
347 #define SMALL16 (SMALL | CODE16)
349 #define BIG16 (BIG | CODE16)
353 #define INLINE __inline__
359 #define ENCODE_RELAX_STATE(type, size) \
360 ((relax_substateT) (((type) << 2) | (size)))
361 #define TYPE_FROM_RELAX_STATE(s) \
363 #define DISP_SIZE_FROM_RELAX_STATE(s) \
364 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
366 /* This table is used by relax_frag to promote short jumps to long
367 ones where necessary. SMALL (short) jumps may be promoted to BIG
368 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
369 don't allow a short jump in a 32 bit code segment to be promoted to
370 a 16 bit offset jump because it's slower (requires data size
371 prefix), and doesn't work, unless the destination is in the bottom
372 64k of the code segment (The top 16 bits of eip are zeroed). */
374 const relax_typeS md_relax_table
[] =
377 1) most positive reach of this state,
378 2) most negative reach of this state,
379 3) how many bytes this mode will have in the variable part of the frag
380 4) which index into the table to try if we can't fit into this one. */
382 /* UNCOND_JUMP states. */
383 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
385 /* dword jmp adds 4 bytes to frag:
386 0 extra opcode bytes, 4 displacement bytes. */
388 /* word jmp adds 2 byte2 to frag:
389 0 extra opcode bytes, 2 displacement bytes. */
392 /* COND_JUMP states. */
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
395 /* dword conditionals adds 5 bytes to frag:
396 1 extra opcode byte, 4 displacement bytes. */
398 /* word conditionals add 3 bytes to frag:
399 1 extra opcode byte, 2 displacement bytes. */
402 /* COND_JUMP86 states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
405 /* dword conditionals adds 5 bytes to frag:
406 1 extra opcode byte, 4 displacement bytes. */
408 /* word conditionals add 4 bytes to frag:
409 1 displacement byte and a 3 byte long branch insn. */
413 static const arch_entry cpu_arch
[] = {
415 {"i186", Cpu086
|Cpu186
},
416 {"i286", Cpu086
|Cpu186
|Cpu286
},
417 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
418 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
419 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
420 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
421 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
422 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
423 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
424 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
425 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
426 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
430 const pseudo_typeS md_pseudo_table
[] =
432 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
433 {"align", s_align_bytes
, 0},
435 {"align", s_align_ptwo
, 0},
437 {"arch", set_cpu_arch
, 0},
441 {"ffloat", float_cons
, 'f'},
442 {"dfloat", float_cons
, 'd'},
443 {"tfloat", float_cons
, 'x'},
445 {"noopt", s_ignore
, 0},
446 {"optim", s_ignore
, 0},
447 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
448 {"code16", set_code_flag
, CODE_16BIT
},
449 {"code32", set_code_flag
, CODE_32BIT
},
450 {"code64", set_code_flag
, CODE_64BIT
},
451 {"intel_syntax", set_intel_syntax
, 1},
452 {"att_syntax", set_intel_syntax
, 0},
453 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
454 {"loc", dwarf2_directive_loc
, 0},
456 {"secrel32", pe_directive_secrel
, 0},
461 /* For interface with expression (). */
462 extern char *input_line_pointer
;
464 /* Hash table for instruction mnemonic lookup. */
465 static struct hash_control
*op_hash
;
467 /* Hash table for register lookup. */
468 static struct hash_control
*reg_hash
;
471 i386_align_code (fragP
, count
)
475 /* Various efficient no-op patterns for aligning code labels.
476 Note: Don't try to assemble the instructions in the comments.
477 0L and 0w are not legal. */
478 static const char f32_1
[] =
480 static const char f32_2
[] =
481 {0x89,0xf6}; /* movl %esi,%esi */
482 static const char f32_3
[] =
483 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
484 static const char f32_4
[] =
485 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
486 static const char f32_5
[] =
488 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
489 static const char f32_6
[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
491 static const char f32_7
[] =
492 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
493 static const char f32_8
[] =
495 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
496 static const char f32_9
[] =
497 {0x89,0xf6, /* movl %esi,%esi */
498 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
499 static const char f32_10
[] =
500 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
501 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
502 static const char f32_11
[] =
503 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
504 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
505 static const char f32_12
[] =
506 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
507 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
508 static const char f32_13
[] =
509 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
510 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
511 static const char f32_14
[] =
512 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
513 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
514 static const char f32_15
[] =
515 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
516 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
517 static const char f16_3
[] =
518 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
519 static const char f16_4
[] =
520 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
521 static const char f16_5
[] =
523 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
524 static const char f16_6
[] =
525 {0x89,0xf6, /* mov %si,%si */
526 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
527 static const char f16_7
[] =
528 {0x8d,0x74,0x00, /* lea 0(%si),%si */
529 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
530 static const char f16_8
[] =
531 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
532 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
533 static const char *const f32_patt
[] = {
534 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
535 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
537 static const char *const f16_patt
[] = {
538 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
539 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
542 if (count
<= 0 || count
> 15)
545 /* The recommended way to pad 64bit code is to use NOPs preceded by
546 maximally four 0x66 prefixes. Balance the size of nops. */
547 if (flag_code
== CODE_64BIT
)
550 int nnops
= (count
+ 3) / 4;
551 int len
= count
/ nnops
;
552 int remains
= count
- nnops
* len
;
555 for (i
= 0; i
< remains
; i
++)
557 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
558 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
561 for (; i
< nnops
; i
++)
563 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
564 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
569 if (flag_code
== CODE_16BIT
)
571 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
572 f16_patt
[count
- 1], count
);
574 /* Adjust jump offset. */
575 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
578 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
579 f32_patt
[count
- 1], count
);
580 fragP
->fr_var
= count
;
583 static INLINE
unsigned int
584 mode_from_disp_size (t
)
587 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
591 fits_in_signed_byte (num
)
594 return (num
>= -128) && (num
<= 127);
598 fits_in_unsigned_byte (num
)
601 return (num
& 0xff) == num
;
605 fits_in_unsigned_word (num
)
608 return (num
& 0xffff) == num
;
612 fits_in_signed_word (num
)
615 return (-32768 <= num
) && (num
<= 32767);
618 fits_in_signed_long (num
)
619 offsetT num ATTRIBUTE_UNUSED
;
624 return (!(((offsetT
) -1 << 31) & num
)
625 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
627 } /* fits_in_signed_long() */
629 fits_in_unsigned_long (num
)
630 offsetT num ATTRIBUTE_UNUSED
;
635 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
637 } /* fits_in_unsigned_long() */
640 smallest_imm_type (num
)
643 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
645 /* This code is disabled on the 486 because all the Imm1 forms
646 in the opcode table are slower on the i486. They're the
647 versions with the implicitly specified single-position
648 displacement, which has another syntax if you really want to
651 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
653 return (fits_in_signed_byte (num
)
654 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
655 : fits_in_unsigned_byte (num
)
656 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
657 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
658 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
659 : fits_in_signed_long (num
)
660 ? (Imm32
| Imm32S
| Imm64
)
661 : fits_in_unsigned_long (num
)
667 offset_in_range (val
, size
)
675 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
676 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
677 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
679 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
684 /* If BFD64, sign extend val. */
685 if (!use_rela_relocations
)
686 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
687 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
689 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
691 char buf1
[40], buf2
[40];
693 sprint_value (buf1
, val
);
694 sprint_value (buf2
, val
& mask
);
695 as_warn (_("%s shortened to %s"), buf1
, buf2
);
700 /* Returns 0 if attempting to add a prefix where one from the same
701 class already exists, 1 if non rep/repne added, 2 if rep/repne
710 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
711 && flag_code
== CODE_64BIT
)
719 case CS_PREFIX_OPCODE
:
720 case DS_PREFIX_OPCODE
:
721 case ES_PREFIX_OPCODE
:
722 case FS_PREFIX_OPCODE
:
723 case GS_PREFIX_OPCODE
:
724 case SS_PREFIX_OPCODE
:
728 case REPNE_PREFIX_OPCODE
:
729 case REPE_PREFIX_OPCODE
:
732 case LOCK_PREFIX_OPCODE
:
740 case ADDR_PREFIX_OPCODE
:
744 case DATA_PREFIX_OPCODE
:
749 if (i
.prefix
[q
] != 0)
751 as_bad (_("same type of prefix used twice"));
756 i
.prefix
[q
] = prefix
;
761 set_code_flag (value
)
765 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
766 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
767 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
769 as_bad (_("64bit mode not supported on this CPU."));
771 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
773 as_bad (_("32bit mode not supported on this CPU."));
779 set_16bit_gcc_code_flag (new_code_flag
)
782 flag_code
= new_code_flag
;
783 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
784 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
789 set_intel_syntax (syntax_flag
)
792 /* Find out if register prefixing is specified. */
793 int ask_naked_reg
= 0;
796 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
798 char *string
= input_line_pointer
;
799 int e
= get_symbol_end ();
801 if (strcmp (string
, "prefix") == 0)
803 else if (strcmp (string
, "noprefix") == 0)
806 as_bad (_("bad argument to syntax directive."));
807 *input_line_pointer
= e
;
809 demand_empty_rest_of_line ();
811 intel_syntax
= syntax_flag
;
813 if (ask_naked_reg
== 0)
814 allow_naked_reg
= (intel_syntax
815 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
817 allow_naked_reg
= (ask_naked_reg
< 0);
822 int dummy ATTRIBUTE_UNUSED
;
826 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
828 char *string
= input_line_pointer
;
829 int e
= get_symbol_end ();
832 for (i
= 0; cpu_arch
[i
].name
; i
++)
834 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
836 cpu_arch_name
= cpu_arch
[i
].name
;
837 cpu_arch_flags
= (cpu_arch
[i
].flags
838 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
842 if (!cpu_arch
[i
].name
)
843 as_bad (_("no such architecture: `%s'"), string
);
845 *input_line_pointer
= e
;
848 as_bad (_("missing cpu architecture"));
850 no_cond_jump_promotion
= 0;
851 if (*input_line_pointer
== ','
852 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
854 char *string
= ++input_line_pointer
;
855 int e
= get_symbol_end ();
857 if (strcmp (string
, "nojumps") == 0)
858 no_cond_jump_promotion
= 1;
859 else if (strcmp (string
, "jumps") == 0)
862 as_bad (_("no such architecture modifier: `%s'"), string
);
864 *input_line_pointer
= e
;
867 demand_empty_rest_of_line ();
873 if (!strcmp (default_arch
, "x86_64"))
874 return bfd_mach_x86_64
;
875 else if (!strcmp (default_arch
, "i386"))
876 return bfd_mach_i386_i386
;
878 as_fatal (_("Unknown architecture"));
884 const char *hash_err
;
886 /* Initialize op_hash hash table. */
887 op_hash
= hash_new ();
890 const template *optab
;
891 templates
*core_optab
;
893 /* Setup for loop. */
895 core_optab
= (templates
*) xmalloc (sizeof (templates
));
896 core_optab
->start
= optab
;
901 if (optab
->name
== NULL
902 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
904 /* different name --> ship out current template list;
905 add to hash table; & begin anew. */
906 core_optab
->end
= optab
;
907 hash_err
= hash_insert (op_hash
,
912 as_fatal (_("Internal Error: Can't hash %s: %s"),
916 if (optab
->name
== NULL
)
918 core_optab
= (templates
*) xmalloc (sizeof (templates
));
919 core_optab
->start
= optab
;
924 /* Initialize reg_hash hash table. */
925 reg_hash
= hash_new ();
927 const reg_entry
*regtab
;
929 for (regtab
= i386_regtab
;
930 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
933 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
935 as_fatal (_("Internal Error: Can't hash %s: %s"),
941 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
946 for (c
= 0; c
< 256; c
++)
951 mnemonic_chars
[c
] = c
;
952 register_chars
[c
] = c
;
953 operand_chars
[c
] = c
;
955 else if (ISLOWER (c
))
957 mnemonic_chars
[c
] = c
;
958 register_chars
[c
] = c
;
959 operand_chars
[c
] = c
;
961 else if (ISUPPER (c
))
963 mnemonic_chars
[c
] = TOLOWER (c
);
964 register_chars
[c
] = mnemonic_chars
[c
];
965 operand_chars
[c
] = c
;
968 if (ISALPHA (c
) || ISDIGIT (c
))
969 identifier_chars
[c
] = c
;
972 identifier_chars
[c
] = c
;
973 operand_chars
[c
] = c
;
978 identifier_chars
['@'] = '@';
981 identifier_chars
['?'] = '?';
982 operand_chars
['?'] = '?';
984 digit_chars
['-'] = '-';
985 identifier_chars
['_'] = '_';
986 identifier_chars
['.'] = '.';
988 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
989 operand_chars
[(unsigned char) *p
] = *p
;
992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
993 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
995 record_alignment (text_section
, 2);
996 record_alignment (data_section
, 2);
997 record_alignment (bss_section
, 2);
1001 if (flag_code
== CODE_64BIT
)
1003 x86_dwarf2_return_column
= 16;
1004 x86_cie_data_alignment
= -8;
1008 x86_dwarf2_return_column
= 8;
1009 x86_cie_data_alignment
= -4;
1014 i386_print_statistics (file
)
1017 hash_print_statistics (file
, "i386 opcode", op_hash
);
1018 hash_print_statistics (file
, "i386 register", reg_hash
);
1023 /* Debugging routines for md_assemble. */
1024 static void pi
PARAMS ((char *, i386_insn
*));
1025 static void pte
PARAMS ((template *));
1026 static void pt
PARAMS ((unsigned int));
1027 static void pe
PARAMS ((expressionS
*));
1028 static void ps
PARAMS ((symbolS
*));
1037 fprintf (stdout
, "%s: template ", line
);
1039 fprintf (stdout
, " address: base %s index %s scale %x\n",
1040 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1041 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1042 x
->log2_scale_factor
);
1043 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1044 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1045 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1046 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1047 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1048 (x
->rex
& REX_MODE64
) != 0,
1049 (x
->rex
& REX_EXTX
) != 0,
1050 (x
->rex
& REX_EXTY
) != 0,
1051 (x
->rex
& REX_EXTZ
) != 0);
1052 for (i
= 0; i
< x
->operands
; i
++)
1054 fprintf (stdout
, " #%d: ", i
+ 1);
1056 fprintf (stdout
, "\n");
1058 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1059 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1060 if (x
->types
[i
] & Imm
)
1062 if (x
->types
[i
] & Disp
)
1063 pe (x
->op
[i
].disps
);
1072 fprintf (stdout
, " %d operands ", t
->operands
);
1073 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1074 if (t
->extension_opcode
!= None
)
1075 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1076 if (t
->opcode_modifier
& D
)
1077 fprintf (stdout
, "D");
1078 if (t
->opcode_modifier
& W
)
1079 fprintf (stdout
, "W");
1080 fprintf (stdout
, "\n");
1081 for (i
= 0; i
< t
->operands
; i
++)
1083 fprintf (stdout
, " #%d type ", i
+ 1);
1084 pt (t
->operand_types
[i
]);
1085 fprintf (stdout
, "\n");
1093 fprintf (stdout
, " operation %d\n", e
->X_op
);
1094 fprintf (stdout
, " add_number %ld (%lx)\n",
1095 (long) e
->X_add_number
, (long) e
->X_add_number
);
1096 if (e
->X_add_symbol
)
1098 fprintf (stdout
, " add_symbol ");
1099 ps (e
->X_add_symbol
);
1100 fprintf (stdout
, "\n");
1104 fprintf (stdout
, " op_symbol ");
1105 ps (e
->X_op_symbol
);
1106 fprintf (stdout
, "\n");
1114 fprintf (stdout
, "%s type %s%s",
1116 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1117 segment_name (S_GET_SEGMENT (s
)));
1126 static const type_names
[] =
1139 { BaseIndex
, "BaseIndex" },
1143 { Disp32S
, "d32s" },
1145 { InOutPortReg
, "InOutPortReg" },
1146 { ShiftCount
, "ShiftCount" },
1147 { Control
, "control reg" },
1148 { Test
, "test reg" },
1149 { Debug
, "debug reg" },
1150 { FloatReg
, "FReg" },
1151 { FloatAcc
, "FAcc" },
1155 { JumpAbsolute
, "Jump Absolute" },
1166 const struct type_name
*ty
;
1168 for (ty
= type_names
; ty
->mask
; ty
++)
1170 fprintf (stdout
, "%s, ", ty
->tname
);
1174 #endif /* DEBUG386 */
1176 static bfd_reloc_code_real_type reloc
1177 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
1179 static bfd_reloc_code_real_type
1180 reloc (size
, pcrel
, sign
, other
)
1184 bfd_reloc_code_real_type other
;
1186 if (other
!= NO_RELOC
)
1192 as_bad (_("There are no unsigned pc-relative relocations"));
1195 case 1: return BFD_RELOC_8_PCREL
;
1196 case 2: return BFD_RELOC_16_PCREL
;
1197 case 4: return BFD_RELOC_32_PCREL
;
1199 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1206 case 4: return BFD_RELOC_X86_64_32S
;
1211 case 1: return BFD_RELOC_8
;
1212 case 2: return BFD_RELOC_16
;
1213 case 4: return BFD_RELOC_32
;
1214 case 8: return BFD_RELOC_64
;
1216 as_bad (_("can not do %s %d byte relocation"),
1217 sign
? "signed" : "unsigned", size
);
1221 return BFD_RELOC_NONE
;
1224 /* Here we decide which fixups can be adjusted to make them relative to
1225 the beginning of the section instead of the symbol. Basically we need
1226 to make sure that the dynamic relocations are done correctly, so in
1227 some cases we force the original symbol to be used. */
1230 tc_i386_fix_adjustable (fixP
)
1231 fixS
*fixP ATTRIBUTE_UNUSED
;
1233 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1234 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
1237 /* Don't adjust pc-relative references to merge sections in 64-bit
1239 if (use_rela_relocations
1240 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1244 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1245 and changed later by validate_fix. */
1246 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1247 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1250 /* adjust_reloc_syms doesn't know about the GOT. */
1251 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1252 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1253 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1254 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1255 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1256 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1257 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1258 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1259 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1260 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1261 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1262 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1263 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1264 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1265 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1266 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1267 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1268 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1269 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1270 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1271 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1277 static int intel_float_operand
PARAMS ((const char *mnemonic
));
1280 intel_float_operand (mnemonic
)
1281 const char *mnemonic
;
1283 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1286 if (mnemonic
[0] == 'f')
1292 /* This is the guts of the machine-dependent assembler. LINE points to a
1293 machine dependent instruction. This function is supposed to emit
1294 the frags/bytes it assembles to. */
1301 char mnemonic
[MAX_MNEM_SIZE
];
1303 /* Initialize globals. */
1304 memset (&i
, '\0', sizeof (i
));
1305 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1306 i
.reloc
[j
] = NO_RELOC
;
1307 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1308 memset (im_expressions
, '\0', sizeof (im_expressions
));
1309 save_stack_p
= save_stack
;
1311 /* First parse an instruction mnemonic & call i386_operand for the operands.
1312 We assume that the scrubber has arranged it so that line[0] is the valid
1313 start of a (possibly prefixed) mnemonic. */
1315 line
= parse_insn (line
, mnemonic
);
1319 line
= parse_operands (line
, mnemonic
);
1323 /* Now we've parsed the mnemonic into a set of templates, and have the
1324 operands at hand. */
1326 /* All intel opcodes have reversed operands except for "bound" and
1327 "enter". We also don't reverse intersegment "jmp" and "call"
1328 instructions with 2 immediate operands so that the immediate segment
1329 precedes the offset, as it does when in AT&T mode. "enter" and the
1330 intersegment "jmp" and "call" instructions are the only ones that
1331 have two immediate operands. */
1332 if (intel_syntax
&& i
.operands
> 1
1333 && (strcmp (mnemonic
, "bound") != 0)
1334 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1340 if (i
.disp_operands
)
1343 /* Next, we find a template that matches the given insn,
1344 making sure the overlap of the given operands types is consistent
1345 with the template operand types. */
1347 if (!match_template ())
1352 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1354 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1355 i
.tm
.base_opcode
^= FloatR
;
1357 /* Zap movzx and movsx suffix. The suffix may have been set from
1358 "word ptr" or "byte ptr" on the source operand, but we'll use
1359 the suffix later to choose the destination register. */
1360 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1364 if (i
.tm
.opcode_modifier
& FWait
)
1365 if (!add_prefix (FWAIT_OPCODE
))
1368 /* Check string instruction segment overrides. */
1369 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1371 if (!check_string ())
1375 if (!process_suffix ())
1378 /* Make still unresolved immediate matches conform to size of immediate
1379 given in i.suffix. */
1380 if (!finalize_imm ())
1383 if (i
.types
[0] & Imm1
)
1384 i
.imm_operands
= 0; /* kludge for shift insns. */
1385 if (i
.types
[0] & ImplicitRegister
)
1387 if (i
.types
[1] & ImplicitRegister
)
1389 if (i
.types
[2] & ImplicitRegister
)
1392 if (i
.tm
.opcode_modifier
& ImmExt
)
1396 if ((i
.tm
.cpu_flags
& CpuPNI
) && i
.operands
> 0)
1398 /* These Intel Prescott New Instructions have the fixed
1399 operands with an opcode suffix which is coded in the same
1400 place as an 8-bit immediate field would be. Here we check
1401 those operands and remove them afterwards. */
1404 for (x
= 0; x
< i
.operands
; x
++)
1405 if (i
.op
[x
].regs
->reg_num
!= x
)
1406 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1407 i
.op
[x
].regs
->reg_name
, x
+ 1, i
.tm
.name
);
1411 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1412 opcode suffix which is coded in the same place as an 8-bit
1413 immediate field would be. Here we fake an 8-bit immediate
1414 operand from the opcode suffix stored in tm.extension_opcode. */
1416 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1418 exp
= &im_expressions
[i
.imm_operands
++];
1419 i
.op
[i
.operands
].imms
= exp
;
1420 i
.types
[i
.operands
++] = Imm8
;
1421 exp
->X_op
= O_constant
;
1422 exp
->X_add_number
= i
.tm
.extension_opcode
;
1423 i
.tm
.extension_opcode
= None
;
1426 /* For insns with operands there are more diddles to do to the opcode. */
1429 if (!process_operands ())
1432 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1434 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1435 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1438 /* Handle conversion of 'int $3' --> special int3 insn. */
1439 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1441 i
.tm
.base_opcode
= INT3_OPCODE
;
1445 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1446 && i
.op
[0].disps
->X_op
== O_constant
)
1448 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1449 the absolute address given by the constant. Since ix86 jumps and
1450 calls are pc relative, we need to generate a reloc. */
1451 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1452 i
.op
[0].disps
->X_op
= O_symbol
;
1455 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1456 i
.rex
|= REX_MODE64
;
1458 /* For 8 bit registers we need an empty rex prefix. Also if the
1459 instruction already has a prefix, we need to convert old
1460 registers to new ones. */
1462 if (((i
.types
[0] & Reg8
) != 0
1463 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1464 || ((i
.types
[1] & Reg8
) != 0
1465 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1466 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1471 i
.rex
|= REX_OPCODE
;
1472 for (x
= 0; x
< 2; x
++)
1474 /* Look for 8 bit operand that uses old registers. */
1475 if ((i
.types
[x
] & Reg8
) != 0
1476 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1478 /* In case it is "hi" register, give up. */
1479 if (i
.op
[x
].regs
->reg_num
> 3)
1480 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1481 i
.op
[x
].regs
->reg_name
);
1483 /* Otherwise it is equivalent to the extended register.
1484 Since the encoding doesn't change this is merely
1485 cosmetic cleanup for debug output. */
1487 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1493 add_prefix (REX_OPCODE
| i
.rex
);
1495 /* We are ready to output the insn. */
1500 parse_insn (line
, mnemonic
)
1505 char *token_start
= l
;
1508 /* Non-zero if we found a prefix only acceptable with string insns. */
1509 const char *expecting_string_instruction
= NULL
;
1514 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1517 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1519 as_bad (_("no such instruction: `%s'"), token_start
);
1524 if (!is_space_char (*l
)
1525 && *l
!= END_OF_INSN
1526 && *l
!= PREFIX_SEPARATOR
1529 as_bad (_("invalid character %s in mnemonic"),
1530 output_invalid (*l
));
1533 if (token_start
== l
)
1535 if (*l
== PREFIX_SEPARATOR
)
1536 as_bad (_("expecting prefix; got nothing"));
1538 as_bad (_("expecting mnemonic; got nothing"));
1542 /* Look up instruction (or prefix) via hash table. */
1543 current_templates
= hash_find (op_hash
, mnemonic
);
1545 if (*l
!= END_OF_INSN
1546 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1547 && current_templates
1548 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1550 /* If we are in 16-bit mode, do not allow addr16 or data16.
1551 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1552 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1553 && flag_code
!= CODE_64BIT
1554 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1555 ^ (flag_code
== CODE_16BIT
)))
1557 as_bad (_("redundant %s prefix"),
1558 current_templates
->start
->name
);
1561 /* Add prefix, checking for repeated prefixes. */
1562 switch (add_prefix (current_templates
->start
->base_opcode
))
1567 expecting_string_instruction
= current_templates
->start
->name
;
1570 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1577 if (!current_templates
)
1579 /* See if we can get a match by trimming off a suffix. */
1582 case WORD_MNEM_SUFFIX
:
1583 case BYTE_MNEM_SUFFIX
:
1584 case QWORD_MNEM_SUFFIX
:
1585 i
.suffix
= mnem_p
[-1];
1587 current_templates
= hash_find (op_hash
, mnemonic
);
1589 case SHORT_MNEM_SUFFIX
:
1590 case LONG_MNEM_SUFFIX
:
1593 i
.suffix
= mnem_p
[-1];
1595 current_templates
= hash_find (op_hash
, mnemonic
);
1603 if (intel_float_operand (mnemonic
))
1604 i
.suffix
= SHORT_MNEM_SUFFIX
;
1606 i
.suffix
= LONG_MNEM_SUFFIX
;
1608 current_templates
= hash_find (op_hash
, mnemonic
);
1612 if (!current_templates
)
1614 as_bad (_("no such instruction: `%s'"), token_start
);
1619 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
1621 /* Check for a branch hint. We allow ",pt" and ",pn" for
1622 predict taken and predict not taken respectively.
1623 I'm not sure that branch hints actually do anything on loop
1624 and jcxz insns (JumpByte) for current Pentium4 chips. They
1625 may work in the future and it doesn't hurt to accept them
1627 if (l
[0] == ',' && l
[1] == 'p')
1631 if (!add_prefix (DS_PREFIX_OPCODE
))
1635 else if (l
[2] == 'n')
1637 if (!add_prefix (CS_PREFIX_OPCODE
))
1643 /* Any other comma loses. */
1646 as_bad (_("invalid character %s in mnemonic"),
1647 output_invalid (*l
));
1651 /* Check if instruction is supported on specified architecture. */
1652 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1653 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1655 as_warn (_("`%s' is not supported on `%s'"),
1656 current_templates
->start
->name
, cpu_arch_name
);
1658 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1660 as_warn (_("use .code16 to ensure correct addressing mode"));
1663 /* Check for rep/repne without a string instruction. */
1664 if (expecting_string_instruction
1665 && !(current_templates
->start
->opcode_modifier
& IsString
))
1667 as_bad (_("expecting string instruction after `%s'"),
1668 expecting_string_instruction
);
1676 parse_operands (l
, mnemonic
)
1678 const char *mnemonic
;
1682 /* 1 if operand is pending after ','. */
1683 unsigned int expecting_operand
= 0;
1685 /* Non-zero if operand parens not balanced. */
1686 unsigned int paren_not_balanced
;
1688 while (*l
!= END_OF_INSN
)
1690 /* Skip optional white space before operand. */
1691 if (is_space_char (*l
))
1693 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1695 as_bad (_("invalid character %s before operand %d"),
1696 output_invalid (*l
),
1700 token_start
= l
; /* after white space */
1701 paren_not_balanced
= 0;
1702 while (paren_not_balanced
|| *l
!= ',')
1704 if (*l
== END_OF_INSN
)
1706 if (paren_not_balanced
)
1709 as_bad (_("unbalanced parenthesis in operand %d."),
1712 as_bad (_("unbalanced brackets in operand %d."),
1717 break; /* we are done */
1719 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1721 as_bad (_("invalid character %s in operand %d"),
1722 output_invalid (*l
),
1729 ++paren_not_balanced
;
1731 --paren_not_balanced
;
1736 ++paren_not_balanced
;
1738 --paren_not_balanced
;
1742 if (l
!= token_start
)
1743 { /* Yes, we've read in another operand. */
1744 unsigned int operand_ok
;
1745 this_operand
= i
.operands
++;
1746 if (i
.operands
> MAX_OPERANDS
)
1748 as_bad (_("spurious operands; (%d operands/instruction max)"),
1752 /* Now parse operand adding info to 'i' as we go along. */
1753 END_STRING_AND_SAVE (l
);
1757 i386_intel_operand (token_start
,
1758 intel_float_operand (mnemonic
));
1760 operand_ok
= i386_operand (token_start
);
1762 RESTORE_END_STRING (l
);
1768 if (expecting_operand
)
1770 expecting_operand_after_comma
:
1771 as_bad (_("expecting operand after ','; got nothing"));
1776 as_bad (_("expecting operand before ','; got nothing"));
1781 /* Now *l must be either ',' or END_OF_INSN. */
1784 if (*++l
== END_OF_INSN
)
1786 /* Just skip it, if it's \n complain. */
1787 goto expecting_operand_after_comma
;
1789 expecting_operand
= 1;
1798 union i386_op temp_op
;
1799 unsigned int temp_type
;
1800 enum bfd_reloc_code_real temp_reloc
;
1804 if (i
.operands
== 2)
1809 else if (i
.operands
== 3)
1814 temp_type
= i
.types
[xchg2
];
1815 i
.types
[xchg2
] = i
.types
[xchg1
];
1816 i
.types
[xchg1
] = temp_type
;
1817 temp_op
= i
.op
[xchg2
];
1818 i
.op
[xchg2
] = i
.op
[xchg1
];
1819 i
.op
[xchg1
] = temp_op
;
1820 temp_reloc
= i
.reloc
[xchg2
];
1821 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
1822 i
.reloc
[xchg1
] = temp_reloc
;
1824 if (i
.mem_operands
== 2)
1826 const seg_entry
*temp_seg
;
1827 temp_seg
= i
.seg
[0];
1828 i
.seg
[0] = i
.seg
[1];
1829 i
.seg
[1] = temp_seg
;
1833 /* Try to ensure constant immediates are represented in the smallest
1838 char guess_suffix
= 0;
1842 guess_suffix
= i
.suffix
;
1843 else if (i
.reg_operands
)
1845 /* Figure out a suffix from the last register operand specified.
1846 We can't do this properly yet, ie. excluding InOutPortReg,
1847 but the following works for instructions with immediates.
1848 In any case, we can't set i.suffix yet. */
1849 for (op
= i
.operands
; --op
>= 0;)
1850 if (i
.types
[op
] & Reg
)
1852 if (i
.types
[op
] & Reg8
)
1853 guess_suffix
= BYTE_MNEM_SUFFIX
;
1854 else if (i
.types
[op
] & Reg16
)
1855 guess_suffix
= WORD_MNEM_SUFFIX
;
1856 else if (i
.types
[op
] & Reg32
)
1857 guess_suffix
= LONG_MNEM_SUFFIX
;
1858 else if (i
.types
[op
] & Reg64
)
1859 guess_suffix
= QWORD_MNEM_SUFFIX
;
1863 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1864 guess_suffix
= WORD_MNEM_SUFFIX
;
1866 for (op
= i
.operands
; --op
>= 0;)
1867 if (i
.types
[op
] & Imm
)
1869 switch (i
.op
[op
].imms
->X_op
)
1872 /* If a suffix is given, this operand may be shortened. */
1873 switch (guess_suffix
)
1875 case LONG_MNEM_SUFFIX
:
1876 i
.types
[op
] |= Imm32
| Imm64
;
1878 case WORD_MNEM_SUFFIX
:
1879 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1881 case BYTE_MNEM_SUFFIX
:
1882 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1886 /* If this operand is at most 16 bits, convert it
1887 to a signed 16 bit number before trying to see
1888 whether it will fit in an even smaller size.
1889 This allows a 16-bit operand such as $0xffe0 to
1890 be recognised as within Imm8S range. */
1891 if ((i
.types
[op
] & Imm16
)
1892 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1894 i
.op
[op
].imms
->X_add_number
=
1895 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1897 if ((i
.types
[op
] & Imm32
)
1898 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
1901 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
1902 ^ ((offsetT
) 1 << 31))
1903 - ((offsetT
) 1 << 31));
1905 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1907 /* We must avoid matching of Imm32 templates when 64bit
1908 only immediate is available. */
1909 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1910 i
.types
[op
] &= ~Imm32
;
1917 /* Symbols and expressions. */
1919 /* Convert symbolic operand to proper sizes for matching. */
1920 switch (guess_suffix
)
1922 case QWORD_MNEM_SUFFIX
:
1923 i
.types
[op
] = Imm64
| Imm32S
;
1925 case LONG_MNEM_SUFFIX
:
1926 i
.types
[op
] = Imm32
;
1928 case WORD_MNEM_SUFFIX
:
1929 i
.types
[op
] = Imm16
;
1931 case BYTE_MNEM_SUFFIX
:
1932 i
.types
[op
] = Imm8
| Imm8S
;
1940 /* Try to use the smallest displacement type too. */
1946 for (op
= i
.operands
; --op
>= 0;)
1947 if ((i
.types
[op
] & Disp
) && i
.op
[op
].disps
->X_op
== O_constant
)
1949 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1951 if (i
.types
[op
] & Disp16
)
1953 /* We know this operand is at most 16 bits, so
1954 convert to a signed 16 bit number before trying
1955 to see whether it will fit in an even smaller
1958 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1960 else if (i
.types
[op
] & Disp32
)
1962 /* We know this operand is at most 32 bits, so convert to a
1963 signed 32 bit number before trying to see whether it will
1964 fit in an even smaller size. */
1965 disp
&= (((offsetT
) 2 << 31) - 1);
1966 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1968 if (flag_code
== CODE_64BIT
)
1970 if (fits_in_signed_long (disp
))
1971 i
.types
[op
] |= Disp32S
;
1972 if (fits_in_unsigned_long (disp
))
1973 i
.types
[op
] |= Disp32
;
1975 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1976 && fits_in_signed_byte (disp
))
1977 i
.types
[op
] |= Disp8
;
1984 /* Points to template once we've found it. */
1986 unsigned int overlap0
, overlap1
, overlap2
;
1987 unsigned int found_reverse_match
;
1990 #define MATCH(overlap, given, template) \
1991 ((overlap & ~JumpAbsolute) \
1992 && (((given) & (BaseIndex | JumpAbsolute)) \
1993 == ((overlap) & (BaseIndex | JumpAbsolute))))
1995 /* If given types r0 and r1 are registers they must be of the same type
1996 unless the expected operand type register overlap is null.
1997 Note that Acc in a template matches every size of reg. */
1998 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1999 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2000 || ((g0) & Reg) == ((g1) & Reg) \
2001 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2006 found_reverse_match
= 0;
2007 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2009 : (i
.suffix
== WORD_MNEM_SUFFIX
2011 : (i
.suffix
== SHORT_MNEM_SUFFIX
2013 : (i
.suffix
== LONG_MNEM_SUFFIX
2015 : (i
.suffix
== QWORD_MNEM_SUFFIX
2017 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2018 ? No_xSuf
: 0))))));
2020 t
= current_templates
->start
;
2021 if (i
.suffix
== QWORD_MNEM_SUFFIX
2022 && flag_code
!= CODE_64BIT
2024 || (!(t
->opcode_modifier
& IgnoreSize
)
2025 && ! intel_float_operand (t
->name
)))
2026 && (!(t
->operand_types
[0] & (RegMMX
| RegXMM
))
2027 || !(t
->operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2028 && (t
->base_opcode
!= 0x0fc7
2029 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2030 t
= current_templates
->end
;
2031 for (; t
< current_templates
->end
; t
++)
2033 /* Must have right number of operands. */
2034 if (i
.operands
!= t
->operands
)
2037 /* Check the suffix, except for some instructions in intel mode. */
2038 if ((t
->opcode_modifier
& suffix_check
)
2040 && (t
->opcode_modifier
& IgnoreSize
))
2042 && t
->base_opcode
== 0xd9
2043 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
2044 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
2047 /* Do not verify operands when there are none. */
2048 else if (!t
->operands
)
2050 if (t
->cpu_flags
& ~cpu_arch_flags
)
2052 /* We've found a match; break out of loop. */
2056 overlap0
= i
.types
[0] & t
->operand_types
[0];
2057 switch (t
->operands
)
2060 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
2065 overlap1
= i
.types
[1] & t
->operand_types
[1];
2066 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
2067 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
2068 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2069 t
->operand_types
[0],
2070 overlap1
, i
.types
[1],
2071 t
->operand_types
[1]))
2073 /* Check if other direction is valid ... */
2074 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2077 /* Try reversing direction of operands. */
2078 overlap0
= i
.types
[0] & t
->operand_types
[1];
2079 overlap1
= i
.types
[1] & t
->operand_types
[0];
2080 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
2081 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
2082 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2083 t
->operand_types
[1],
2084 overlap1
, i
.types
[1],
2085 t
->operand_types
[0]))
2087 /* Does not match either direction. */
2090 /* found_reverse_match holds which of D or FloatDR
2092 found_reverse_match
= t
->opcode_modifier
& (D
| FloatDR
);
2094 /* Found a forward 2 operand match here. */
2095 else if (t
->operands
== 3)
2097 /* Here we make use of the fact that there are no
2098 reverse match 3 operand instructions, and all 3
2099 operand instructions only need to be checked for
2100 register consistency between operands 2 and 3. */
2101 overlap2
= i
.types
[2] & t
->operand_types
[2];
2102 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
2103 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
2104 t
->operand_types
[1],
2105 overlap2
, i
.types
[2],
2106 t
->operand_types
[2]))
2110 /* Found either forward/reverse 2 or 3 operand match here:
2111 slip through to break. */
2113 if (t
->cpu_flags
& ~cpu_arch_flags
)
2115 found_reverse_match
= 0;
2118 /* We've found a match; break out of loop. */
2122 if (t
== current_templates
->end
)
2124 /* We found no match. */
2125 as_bad (_("suffix or operands invalid for `%s'"),
2126 current_templates
->start
->name
);
2130 if (!quiet_warnings
)
2133 && ((i
.types
[0] & JumpAbsolute
)
2134 != (t
->operand_types
[0] & JumpAbsolute
)))
2136 as_warn (_("indirect %s without `*'"), t
->name
);
2139 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2140 == (IsPrefix
| IgnoreSize
))
2142 /* Warn them that a data or address size prefix doesn't
2143 affect assembly of the next line of code. */
2144 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2148 /* Copy the template we found. */
2150 if (found_reverse_match
)
2152 /* If we found a reverse match we must alter the opcode
2153 direction bit. found_reverse_match holds bits to change
2154 (different for int & float insns). */
2156 i
.tm
.base_opcode
^= found_reverse_match
;
2158 i
.tm
.operand_types
[0] = t
->operand_types
[1];
2159 i
.tm
.operand_types
[1] = t
->operand_types
[0];
2168 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2169 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2171 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2173 as_bad (_("`%s' operand %d must use `%%es' segment"),
2178 /* There's only ever one segment override allowed per instruction.
2179 This instruction possibly has a legal segment override on the
2180 second operand, so copy the segment to where non-string
2181 instructions store it, allowing common code. */
2182 i
.seg
[0] = i
.seg
[1];
2184 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2186 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2188 as_bad (_("`%s' operand %d must use `%%es' segment"),
2198 process_suffix (void)
2200 /* If matched instruction specifies an explicit instruction mnemonic
2202 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2204 if (i
.tm
.opcode_modifier
& Size16
)
2205 i
.suffix
= WORD_MNEM_SUFFIX
;
2206 else if (i
.tm
.opcode_modifier
& Size64
)
2207 i
.suffix
= QWORD_MNEM_SUFFIX
;
2209 i
.suffix
= LONG_MNEM_SUFFIX
;
2211 else if (i
.reg_operands
)
2213 /* If there's no instruction mnemonic suffix we try to invent one
2214 based on register operands. */
2217 /* We take i.suffix from the last register operand specified,
2218 Destination register type is more significant than source
2222 for (op
= i
.operands
; --op
>= 0;)
2223 if ((i
.types
[op
] & Reg
)
2224 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2226 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2227 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2228 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2233 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2235 if (!check_byte_reg ())
2238 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2240 if (!check_long_reg ())
2243 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2245 if (!check_qword_reg ())
2248 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2250 if (!check_word_reg ())
2253 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2254 /* Do nothing if the instruction is going to ignore the prefix. */
2259 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2261 i
.suffix
= stackop_size
;
2262 if (i
.suffix
== QWORD_MNEM_SUFFIX
2263 && (i
.tm
.opcode_modifier
& No_qSuf
))
2264 i
.suffix
= LONG_MNEM_SUFFIX
;
2267 /* Change the opcode based on the operand size given by i.suffix;
2268 We need not change things for byte insns. */
2269 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2271 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2275 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2277 /* It's not a byte, select word/dword operation. */
2278 if (i
.tm
.opcode_modifier
& W
)
2280 if (i
.tm
.opcode_modifier
& ShortForm
)
2281 i
.tm
.base_opcode
|= 8;
2283 i
.tm
.base_opcode
|= 1;
2286 /* Now select between word & dword operations via the operand
2287 size prefix, except for instructions that will ignore this
2289 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2290 && !(i
.tm
.opcode_modifier
& IgnoreSize
)
2291 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2292 || (flag_code
== CODE_64BIT
2293 && (i
.tm
.opcode_modifier
& JumpByte
))))
2295 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2297 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2298 prefix
= ADDR_PREFIX_OPCODE
;
2300 if (!add_prefix (prefix
))
2304 /* Set mode64 for an operand. */
2305 if (i
.suffix
== QWORD_MNEM_SUFFIX
2306 && flag_code
== CODE_64BIT
2307 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
2308 i
.rex
|= REX_MODE64
;
2310 /* Size floating point instruction. */
2311 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2312 if (i
.tm
.opcode_modifier
& FloatMF
)
2313 i
.tm
.base_opcode
^= 4;
2320 check_byte_reg (void)
2324 for (op
= i
.operands
; --op
>= 0;)
2326 /* If this is an eight bit register, it's OK. If it's the 16 or
2327 32 bit version of an eight bit register, we will just use the
2328 low portion, and that's OK too. */
2329 if (i
.types
[op
] & Reg8
)
2332 /* movzx and movsx should not generate this warning. */
2334 && (i
.tm
.base_opcode
== 0xfb7
2335 || i
.tm
.base_opcode
== 0xfb6
2336 || i
.tm
.base_opcode
== 0x63
2337 || i
.tm
.base_opcode
== 0xfbe
2338 || i
.tm
.base_opcode
== 0xfbf))
2341 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
2343 /* Check that the template allows eight bit regs. This
2344 kills insns such as `orb $1,%edx', which maybe should be
2346 && (i
.tm
.operand_types
[op
] & (Reg8
| InOutPortReg
))
2350 /* Prohibit these changes in the 64bit mode, since the
2351 lowering is more complicated. */
2352 if (flag_code
== CODE_64BIT
2353 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2355 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2356 i
.op
[op
].regs
->reg_name
,
2360 #if REGISTER_WARNINGS
2362 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2363 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2364 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
2365 ? REGNAM_AL
- REGNAM_AX
2366 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
2367 i
.op
[op
].regs
->reg_name
,
2372 /* Any other register is bad. */
2373 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2375 | Control
| Debug
| Test
2376 | FloatReg
| FloatAcc
))
2378 as_bad (_("`%%%s' not allowed with `%s%c'"),
2379 i
.op
[op
].regs
->reg_name
,
2393 for (op
= i
.operands
; --op
>= 0;)
2394 /* Reject eight bit registers, except where the template requires
2395 them. (eg. movzb) */
2396 if ((i
.types
[op
] & Reg8
) != 0
2397 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2399 as_bad (_("`%%%s' not allowed with `%s%c'"),
2400 i
.op
[op
].regs
->reg_name
,
2405 /* Warn if the e prefix on a general reg is missing. */
2406 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2407 && (i
.types
[op
] & Reg16
) != 0
2408 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2410 /* Prohibit these changes in the 64bit mode, since the
2411 lowering is more complicated. */
2412 if (flag_code
== CODE_64BIT
)
2414 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2415 i
.op
[op
].regs
->reg_name
,
2419 #if REGISTER_WARNINGS
2421 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2422 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
2423 i
.op
[op
].regs
->reg_name
,
2427 /* Warn if the r prefix on a general reg is missing. */
2428 else if ((i
.types
[op
] & Reg64
) != 0
2429 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2431 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2432 i
.op
[op
].regs
->reg_name
,
2444 for (op
= i
.operands
; --op
>= 0; )
2445 /* Reject eight bit registers, except where the template requires
2446 them. (eg. movzb) */
2447 if ((i
.types
[op
] & Reg8
) != 0
2448 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2450 as_bad (_("`%%%s' not allowed with `%s%c'"),
2451 i
.op
[op
].regs
->reg_name
,
2456 /* Warn if the e prefix on a general reg is missing. */
2457 else if (((i
.types
[op
] & Reg16
) != 0
2458 || (i
.types
[op
] & Reg32
) != 0)
2459 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
2461 /* Prohibit these changes in the 64bit mode, since the
2462 lowering is more complicated. */
2463 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2464 i
.op
[op
].regs
->reg_name
,
2475 for (op
= i
.operands
; --op
>= 0;)
2476 /* Reject eight bit registers, except where the template requires
2477 them. (eg. movzb) */
2478 if ((i
.types
[op
] & Reg8
) != 0
2479 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2481 as_bad (_("`%%%s' not allowed with `%s%c'"),
2482 i
.op
[op
].regs
->reg_name
,
2487 /* Warn if the e prefix on a general reg is present. */
2488 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2489 && (i
.types
[op
] & Reg32
) != 0
2490 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
2492 /* Prohibit these changes in the 64bit mode, since the
2493 lowering is more complicated. */
2494 if (flag_code
== CODE_64BIT
)
2496 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2497 i
.op
[op
].regs
->reg_name
,
2502 #if REGISTER_WARNINGS
2503 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2504 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
2505 i
.op
[op
].regs
->reg_name
,
2515 unsigned int overlap0
, overlap1
, overlap2
;
2517 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
2518 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
2519 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2520 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2521 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2525 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2527 : (i
.suffix
== WORD_MNEM_SUFFIX
2529 : (i
.suffix
== QWORD_MNEM_SUFFIX
2533 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2534 || overlap0
== (Imm16
| Imm32
)
2535 || overlap0
== (Imm16
| Imm32S
))
2537 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2540 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2541 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2542 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2544 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2548 i
.types
[0] = overlap0
;
2550 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
2551 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2552 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2553 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2554 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2558 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
2560 : (i
.suffix
== WORD_MNEM_SUFFIX
2562 : (i
.suffix
== QWORD_MNEM_SUFFIX
2566 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2567 || overlap1
== (Imm16
| Imm32
)
2568 || overlap1
== (Imm16
| Imm32S
))
2570 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
2573 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2574 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2575 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2577 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2581 i
.types
[1] = overlap1
;
2583 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
2584 assert ((overlap2
& Imm
) == 0);
2585 i
.types
[2] = overlap2
;
2593 /* Default segment register this instruction will use for memory
2594 accesses. 0 means unknown. This is only for optimizing out
2595 unnecessary segment overrides. */
2596 const seg_entry
*default_seg
= 0;
2598 /* The imul $imm, %reg instruction is converted into
2599 imul $imm, %reg, %reg, and the clr %reg instruction
2600 is converted into xor %reg, %reg. */
2601 if (i
.tm
.opcode_modifier
& regKludge
)
2603 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2604 /* Pretend we saw the extra register operand. */
2605 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2606 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2607 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2611 if (i
.tm
.opcode_modifier
& ShortForm
)
2613 /* The register or float register operand is in operand 0 or 1. */
2614 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2615 /* Register goes in low 3 bits of opcode. */
2616 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2617 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2619 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2621 /* Warn about some common errors, but press on regardless.
2622 The first case can be generated by gcc (<= 2.8.1). */
2623 if (i
.operands
== 2)
2625 /* Reversed arguments on faddp, fsubp, etc. */
2626 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2627 i
.op
[1].regs
->reg_name
,
2628 i
.op
[0].regs
->reg_name
);
2632 /* Extraneous `l' suffix on fp insn. */
2633 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2634 i
.op
[0].regs
->reg_name
);
2638 else if (i
.tm
.opcode_modifier
& Modrm
)
2640 /* The opcode is completed (modulo i.tm.extension_opcode which
2641 must be put into the modrm byte). Now, we make the modrm and
2642 index base bytes based on all the info we've collected. */
2644 default_seg
= build_modrm_byte ();
2646 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2648 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2649 && i
.op
[0].regs
->reg_num
== 1)
2651 as_bad (_("you can't `pop %%cs'"));
2654 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2655 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
2658 else if ((i
.tm
.base_opcode
& ~(D
| W
)) == MOV_AX_DISP32
)
2662 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2664 /* For the string instructions that allow a segment override
2665 on one of their operands, the default segment is ds. */
2669 if (i
.tm
.base_opcode
== 0x8d /* lea */ && i
.seg
[0] && !quiet_warnings
)
2670 as_warn (_("segment override on `lea' is ineffectual"));
2672 /* If a segment was explicitly specified, and the specified segment
2673 is not the default, use an opcode prefix to select it. If we
2674 never figured out what the default segment is, then default_seg
2675 will be zero at this point, and the specified segment prefix will
2677 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2679 if (!add_prefix (i
.seg
[0]->seg_prefix
))
2685 static const seg_entry
*
2688 const seg_entry
*default_seg
= 0;
2690 /* i.reg_operands MUST be the number of real register operands;
2691 implicit registers do not count. */
2692 if (i
.reg_operands
== 2)
2694 unsigned int source
, dest
;
2695 source
= ((i
.types
[0]
2696 & (Reg
| RegMMX
| RegXMM
2698 | Control
| Debug
| Test
))
2703 /* One of the register operands will be encoded in the i.tm.reg
2704 field, the other in the combined i.tm.mode and i.tm.regmem
2705 fields. If no form of this instruction supports a memory
2706 destination operand, then we assume the source operand may
2707 sometimes be a memory operand and so we need to store the
2708 destination in the i.rm.reg field. */
2709 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2711 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2712 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2713 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2715 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2720 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2721 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2722 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
2724 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
2729 { /* If it's not 2 reg operands... */
2732 unsigned int fake_zero_displacement
= 0;
2733 unsigned int op
= ((i
.types
[0] & AnyMem
)
2735 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2739 if (i
.base_reg
== 0)
2742 if (!i
.disp_operands
)
2743 fake_zero_displacement
= 1;
2744 if (i
.index_reg
== 0)
2746 /* Operand is just <disp> */
2747 if (flag_code
== CODE_64BIT
)
2749 /* 64bit mode overwrites the 32bit absolute
2750 addressing by RIP relative addressing and
2751 absolute addressing is encoded by one of the
2752 redundant SIB forms. */
2753 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2754 i
.sib
.base
= NO_BASE_REGISTER
;
2755 i
.sib
.index
= NO_INDEX_REGISTER
;
2756 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0) ? Disp32S
: Disp32
);
2758 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2760 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2761 i
.types
[op
] = Disp16
;
2765 i
.rm
.regmem
= NO_BASE_REGISTER
;
2766 i
.types
[op
] = Disp32
;
2769 else /* !i.base_reg && i.index_reg */
2771 i
.sib
.index
= i
.index_reg
->reg_num
;
2772 i
.sib
.base
= NO_BASE_REGISTER
;
2773 i
.sib
.scale
= i
.log2_scale_factor
;
2774 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2775 i
.types
[op
] &= ~Disp
;
2776 if (flag_code
!= CODE_64BIT
)
2777 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2779 i
.types
[op
] |= Disp32S
;
2780 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2784 /* RIP addressing for 64bit mode. */
2785 else if (i
.base_reg
->reg_type
== BaseIndex
)
2787 i
.rm
.regmem
= NO_BASE_REGISTER
;
2788 i
.types
[op
] &= ~ Disp
;
2789 i
.types
[op
] |= Disp32S
;
2790 i
.flags
[op
] = Operand_PCrel
;
2791 if (! i
.disp_operands
)
2792 fake_zero_displacement
= 1;
2794 else if (i
.base_reg
->reg_type
& Reg16
)
2796 switch (i
.base_reg
->reg_num
)
2799 if (i
.index_reg
== 0)
2801 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2802 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2806 if (i
.index_reg
== 0)
2809 if ((i
.types
[op
] & Disp
) == 0)
2811 /* fake (%bp) into 0(%bp) */
2812 i
.types
[op
] |= Disp8
;
2813 fake_zero_displacement
= 1;
2816 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2817 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2819 default: /* (%si) -> 4 or (%di) -> 5 */
2820 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2822 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2824 else /* i.base_reg and 32/64 bit mode */
2826 if (flag_code
== CODE_64BIT
2827 && (i
.types
[op
] & Disp
))
2828 i
.types
[op
] = (i
.types
[op
] & Disp8
) | (i
.prefix
[ADDR_PREFIX
] == 0 ? Disp32S
: Disp32
);
2830 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2831 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
2833 i
.sib
.base
= i
.base_reg
->reg_num
;
2834 /* x86-64 ignores REX prefix bit here to avoid decoder
2836 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2839 if (i
.disp_operands
== 0)
2841 fake_zero_displacement
= 1;
2842 i
.types
[op
] |= Disp8
;
2845 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2849 i
.sib
.scale
= i
.log2_scale_factor
;
2850 if (i
.index_reg
== 0)
2852 /* <disp>(%esp) becomes two byte modrm with no index
2853 register. We've already stored the code for esp
2854 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2855 Any base register besides %esp will not use the
2856 extra modrm byte. */
2857 i
.sib
.index
= NO_INDEX_REGISTER
;
2858 #if !SCALE1_WHEN_NO_INDEX
2859 /* Another case where we force the second modrm byte. */
2860 if (i
.log2_scale_factor
)
2861 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2866 i
.sib
.index
= i
.index_reg
->reg_num
;
2867 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2868 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
2871 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2874 if (fake_zero_displacement
)
2876 /* Fakes a zero displacement assuming that i.types[op]
2877 holds the correct displacement size. */
2880 assert (i
.op
[op
].disps
== 0);
2881 exp
= &disp_expressions
[i
.disp_operands
++];
2882 i
.op
[op
].disps
= exp
;
2883 exp
->X_op
= O_constant
;
2884 exp
->X_add_number
= 0;
2885 exp
->X_add_symbol
= (symbolS
*) 0;
2886 exp
->X_op_symbol
= (symbolS
*) 0;
2890 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2891 (if any) based on i.tm.extension_opcode. Again, we must be
2892 careful to make sure that segment/control/debug/test/MMX
2893 registers are coded into the i.rm.reg field. */
2898 & (Reg
| RegMMX
| RegXMM
2900 | Control
| Debug
| Test
))
2903 & (Reg
| RegMMX
| RegXMM
2905 | Control
| Debug
| Test
))
2908 /* If there is an extension opcode to put here, the register
2909 number must be put into the regmem field. */
2910 if (i
.tm
.extension_opcode
!= None
)
2912 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2913 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2918 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2919 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
2923 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2924 must set it to 3 to indicate this is a register operand
2925 in the regmem field. */
2926 if (!i
.mem_operands
)
2930 /* Fill in i.rm.reg field with extension opcode (if any). */
2931 if (i
.tm
.extension_opcode
!= None
)
2932 i
.rm
.reg
= i
.tm
.extension_opcode
;
2943 relax_substateT subtype
;
2948 if (flag_code
== CODE_16BIT
)
2952 if (i
.prefix
[DATA_PREFIX
] != 0)
2958 /* Pentium4 branch hints. */
2959 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
2960 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
2965 if (i
.prefix
[REX_PREFIX
] != 0)
2971 if (i
.prefixes
!= 0 && !intel_syntax
)
2972 as_warn (_("skipping prefixes on this instruction"));
2974 /* It's always a symbol; End frag & setup for relax.
2975 Make sure there is enough room in this frag for the largest
2976 instruction we may generate in md_convert_frag. This is 2
2977 bytes for the opcode and room for the prefix and largest
2979 frag_grow (prefix
+ 2 + 4);
2980 /* Prefix and 1 opcode byte go in fr_fix. */
2981 p
= frag_more (prefix
+ 1);
2982 if (i
.prefix
[DATA_PREFIX
] != 0)
2983 *p
++ = DATA_PREFIX_OPCODE
;
2984 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
2985 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
2986 *p
++ = i
.prefix
[SEG_PREFIX
];
2987 if (i
.prefix
[REX_PREFIX
] != 0)
2988 *p
++ = i
.prefix
[REX_PREFIX
];
2989 *p
= i
.tm
.base_opcode
;
2991 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
2992 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
2993 else if ((cpu_arch_flags
& Cpu386
) != 0)
2994 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
2996 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
2999 sym
= i
.op
[0].disps
->X_add_symbol
;
3000 off
= i
.op
[0].disps
->X_add_number
;
3002 if (i
.op
[0].disps
->X_op
!= O_constant
3003 && i
.op
[0].disps
->X_op
!= O_symbol
)
3005 /* Handle complex expressions. */
3006 sym
= make_expr_symbol (i
.op
[0].disps
);
3010 /* 1 possible extra opcode + 4 byte displacement go in var part.
3011 Pass reloc in fr_var. */
3012 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3022 if (i
.tm
.opcode_modifier
& JumpByte
)
3024 /* This is a loop or jecxz type instruction. */
3026 if (i
.prefix
[ADDR_PREFIX
] != 0)
3028 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3031 /* Pentium4 branch hints. */
3032 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3033 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3035 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3044 if (flag_code
== CODE_16BIT
)
3047 if (i
.prefix
[DATA_PREFIX
] != 0)
3049 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3059 if (i
.prefix
[REX_PREFIX
] != 0)
3061 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3065 if (i
.prefixes
!= 0 && !intel_syntax
)
3066 as_warn (_("skipping prefixes on this instruction"));
3068 p
= frag_more (1 + size
);
3069 *p
++ = i
.tm
.base_opcode
;
3071 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3072 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3074 /* All jumps handled here are signed, but don't use a signed limit
3075 check for 32 and 16 bit jumps as we want to allow wrap around at
3076 4G and 64k respectively. */
3078 fixP
->fx_signed
= 1;
3082 output_interseg_jump ()
3090 if (flag_code
== CODE_16BIT
)
3094 if (i
.prefix
[DATA_PREFIX
] != 0)
3100 if (i
.prefix
[REX_PREFIX
] != 0)
3110 if (i
.prefixes
!= 0 && !intel_syntax
)
3111 as_warn (_("skipping prefixes on this instruction"));
3113 /* 1 opcode; 2 segment; offset */
3114 p
= frag_more (prefix
+ 1 + 2 + size
);
3116 if (i
.prefix
[DATA_PREFIX
] != 0)
3117 *p
++ = DATA_PREFIX_OPCODE
;
3119 if (i
.prefix
[REX_PREFIX
] != 0)
3120 *p
++ = i
.prefix
[REX_PREFIX
];
3122 *p
++ = i
.tm
.base_opcode
;
3123 if (i
.op
[1].imms
->X_op
== O_constant
)
3125 offsetT n
= i
.op
[1].imms
->X_add_number
;
3128 && !fits_in_unsigned_word (n
)
3129 && !fits_in_signed_word (n
))
3131 as_bad (_("16-bit jump out of range"));
3134 md_number_to_chars (p
, n
, size
);
3137 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3138 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3139 if (i
.op
[0].imms
->X_op
!= O_constant
)
3140 as_bad (_("can't handle non absolute segment in `%s'"),
3142 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3148 fragS
*insn_start_frag
;
3149 offsetT insn_start_off
;
3151 /* Tie dwarf2 debug info to the address at the start of the insn.
3152 We can't do this after the insn has been output as the current
3153 frag may have been closed off. eg. by frag_var. */
3154 dwarf2_emit_insn (0);
3156 insn_start_frag
= frag_now
;
3157 insn_start_off
= frag_now_fix ();
3160 if (i
.tm
.opcode_modifier
& Jump
)
3162 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3164 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3165 output_interseg_jump ();
3168 /* Output normal instructions here. */
3172 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3173 have 3 bytes. We may use one more higher byte to specify a prefix
3174 the instruction requires. */
3175 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0
3176 && (i
.tm
.base_opcode
& 0xff000000) != 0)
3178 unsigned int prefix
;
3179 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3181 if (prefix
!= REPE_PREFIX_OPCODE
3182 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3183 add_prefix (prefix
);
3186 if ((i
.tm
.cpu_flags
& CpuPadLock
) == 0
3187 && (i
.tm
.base_opcode
& 0xff0000) != 0)
3188 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
3190 /* The prefix bytes. */
3192 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3198 md_number_to_chars (p
, (valueT
) *q
, 1);
3202 /* Now the opcode; be careful about word order here! */
3203 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
3205 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
3209 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3212 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
3217 /* Put out high byte first: can't use md_number_to_chars! */
3218 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
3219 *p
= i
.tm
.base_opcode
& 0xff;
3222 /* Now the modrm byte and sib byte (if present). */
3223 if (i
.tm
.opcode_modifier
& Modrm
)
3226 md_number_to_chars (p
,
3227 (valueT
) (i
.rm
.regmem
<< 0
3231 /* If i.rm.regmem == ESP (4)
3232 && i.rm.mode != (Register mode)
3234 ==> need second modrm byte. */
3235 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
3237 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
3240 md_number_to_chars (p
,
3241 (valueT
) (i
.sib
.base
<< 0
3243 | i
.sib
.scale
<< 6),
3248 if (i
.disp_operands
)
3249 output_disp (insn_start_frag
, insn_start_off
);
3252 output_imm (insn_start_frag
, insn_start_off
);
3260 #endif /* DEBUG386 */
3264 output_disp (insn_start_frag
, insn_start_off
)
3265 fragS
*insn_start_frag
;
3266 offsetT insn_start_off
;
3271 for (n
= 0; n
< i
.operands
; n
++)
3273 if (i
.types
[n
] & Disp
)
3275 if (i
.op
[n
].disps
->X_op
== O_constant
)
3281 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
3284 if (i
.types
[n
] & Disp8
)
3286 if (i
.types
[n
] & Disp64
)
3289 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
3291 p
= frag_more (size
);
3292 md_number_to_chars (p
, val
, size
);
3296 enum bfd_reloc_code_real reloc_type
;
3299 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
3301 /* The PC relative address is computed relative
3302 to the instruction boundary, so in case immediate
3303 fields follows, we need to adjust the value. */
3304 if (pcrel
&& i
.imm_operands
)
3309 for (n1
= 0; n1
< i
.operands
; n1
++)
3310 if (i
.types
[n1
] & Imm
)
3312 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3315 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3317 if (i
.types
[n1
] & Imm64
)
3322 /* We should find the immediate. */
3323 if (n1
== i
.operands
)
3325 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3328 if (i
.types
[n
] & Disp32S
)
3331 if (i
.types
[n
] & (Disp16
| Disp64
))
3334 if (i
.types
[n
] & Disp64
)
3338 p
= frag_more (size
);
3339 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
3340 if (reloc_type
== BFD_RELOC_32
3342 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
3343 && (i
.op
[n
].disps
->X_op
== O_symbol
3344 || (i
.op
[n
].disps
->X_op
== O_add
3345 && ((symbol_get_value_expression
3346 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
3351 if (insn_start_frag
== frag_now
)
3352 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3357 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3358 for (fr
= insn_start_frag
->fr_next
;
3359 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3361 add
+= p
- frag_now
->fr_literal
;
3364 /* We don't support dynamic linking on x86-64 yet. */
3365 if (flag_code
== CODE_64BIT
)
3367 reloc_type
= BFD_RELOC_386_GOTPC
;
3368 i
.op
[n
].disps
->X_add_number
+= add
;
3370 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3371 i
.op
[n
].disps
, pcrel
, reloc_type
);
3378 output_imm (insn_start_frag
, insn_start_off
)
3379 fragS
*insn_start_frag
;
3380 offsetT insn_start_off
;
3385 for (n
= 0; n
< i
.operands
; n
++)
3387 if (i
.types
[n
] & Imm
)
3389 if (i
.op
[n
].imms
->X_op
== O_constant
)
3395 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3398 if (i
.types
[n
] & (Imm8
| Imm8S
))
3400 else if (i
.types
[n
] & Imm64
)
3403 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3405 p
= frag_more (size
);
3406 md_number_to_chars (p
, val
, size
);
3410 /* Not absolute_section.
3411 Need a 32-bit fixup (don't support 8bit
3412 non-absolute imms). Try to support other
3414 enum bfd_reloc_code_real reloc_type
;
3418 if ((i
.types
[n
] & (Imm32S
))
3419 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3421 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3424 if (i
.types
[n
] & (Imm8
| Imm8S
))
3426 if (i
.types
[n
] & Imm64
)
3430 p
= frag_more (size
);
3431 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
3433 /* This is tough to explain. We end up with this one if we
3434 * have operands that look like
3435 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3436 * obtain the absolute address of the GOT, and it is strongly
3437 * preferable from a performance point of view to avoid using
3438 * a runtime relocation for this. The actual sequence of
3439 * instructions often look something like:
3444 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3446 * The call and pop essentially return the absolute address
3447 * of the label .L66 and store it in %ebx. The linker itself
3448 * will ultimately change the first operand of the addl so
3449 * that %ebx points to the GOT, but to keep things simple, the
3450 * .o file must have this operand set so that it generates not
3451 * the absolute address of .L66, but the absolute address of
3452 * itself. This allows the linker itself simply treat a GOTPC
3453 * relocation as asking for a pcrel offset to the GOT to be
3454 * added in, and the addend of the relocation is stored in the
3455 * operand field for the instruction itself.
3457 * Our job here is to fix the operand so that it would add
3458 * the correct offset so that %ebx would point to itself. The
3459 * thing that is tricky is that .-.L66 will point to the
3460 * beginning of the instruction, so we need to further modify
3461 * the operand so that it will point to itself. There are
3462 * other cases where you have something like:
3464 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3466 * and here no correction would be required. Internally in
3467 * the assembler we treat operands of this form as not being
3468 * pcrel since the '.' is explicitly mentioned, and I wonder
3469 * whether it would simplify matters to do it this way. Who
3470 * knows. In earlier versions of the PIC patches, the
3471 * pcrel_adjust field was used to store the correction, but
3472 * since the expression is not pcrel, I felt it would be
3473 * confusing to do it this way. */
3475 if (reloc_type
== BFD_RELOC_32
3477 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3478 && (i
.op
[n
].imms
->X_op
== O_symbol
3479 || (i
.op
[n
].imms
->X_op
== O_add
3480 && ((symbol_get_value_expression
3481 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3486 if (insn_start_frag
== frag_now
)
3487 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
3492 add
= insn_start_frag
->fr_fix
- insn_start_off
;
3493 for (fr
= insn_start_frag
->fr_next
;
3494 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
3496 add
+= p
- frag_now
->fr_literal
;
3499 /* We don't support dynamic linking on x86-64 yet. */
3500 if (flag_code
== CODE_64BIT
)
3502 reloc_type
= BFD_RELOC_386_GOTPC
;
3503 i
.op
[n
].imms
->X_add_number
+= add
;
3505 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3506 i
.op
[n
].imms
, 0, reloc_type
);
3513 static char *lex_got
PARAMS ((enum bfd_reloc_code_real
*, int *));
3515 /* Parse operands of the form
3516 <symbol>@GOTOFF+<nnn>
3517 and similar .plt or .got references.
3519 If we find one, set up the correct relocation in RELOC and copy the
3520 input string, minus the `@GOTOFF' into a malloc'd buffer for
3521 parsing by the calling routine. Return this buffer, and if ADJUST
3522 is non-null set it to the length of the string we removed from the
3523 input line. Otherwise return NULL. */
3525 lex_got (reloc
, adjust
)
3526 enum bfd_reloc_code_real
*reloc
;
3529 static const char * const mode_name
[NUM_FLAG_CODE
] = { "32", "16", "64" };
3530 static const struct {
3532 const enum bfd_reloc_code_real rel
[NUM_FLAG_CODE
];
3534 { "PLT", { BFD_RELOC_386_PLT32
, 0, BFD_RELOC_X86_64_PLT32
} },
3535 { "GOTOFF", { BFD_RELOC_386_GOTOFF
, 0, 0 } },
3536 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL
} },
3537 { "TLSGD", { BFD_RELOC_386_TLS_GD
, 0, BFD_RELOC_X86_64_TLSGD
} },
3538 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
, 0, 0 } },
3539 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD
} },
3540 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
, 0, BFD_RELOC_X86_64_GOTTPOFF
} },
3541 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
, 0, BFD_RELOC_X86_64_TPOFF32
} },
3542 { "NTPOFF", { BFD_RELOC_386_TLS_LE
, 0, 0 } },
3543 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
, 0, BFD_RELOC_X86_64_DTPOFF32
} },
3544 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
, 0, 0 } },
3545 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
, 0, 0 } },
3546 { "GOT", { BFD_RELOC_386_GOT32
, 0, BFD_RELOC_X86_64_GOT32
} }
3551 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
3552 if (is_end_of_line
[(unsigned char) *cp
])
3555 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
3559 len
= strlen (gotrel
[j
].str
);
3560 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
3562 if (gotrel
[j
].rel
[(unsigned int) flag_code
] != 0)
3565 char *tmpbuf
, *past_reloc
;
3567 *reloc
= gotrel
[j
].rel
[(unsigned int) flag_code
];
3571 if (GOT_symbol
== NULL
)
3572 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3574 /* Replace the relocation token with ' ', so that
3575 errors like foo@GOTOFF1 will be detected. */
3577 /* The length of the first part of our input line. */
3578 first
= cp
- input_line_pointer
;
3580 /* The second part goes from after the reloc token until
3581 (and including) an end_of_line char. Don't use strlen
3582 here as the end_of_line char may not be a NUL. */
3583 past_reloc
= cp
+ 1 + len
;
3584 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
3586 second
= cp
- past_reloc
;
3588 /* Allocate and copy string. The trailing NUL shouldn't
3589 be necessary, but be safe. */
3590 tmpbuf
= xmalloc (first
+ second
+ 2);
3591 memcpy (tmpbuf
, input_line_pointer
, first
);
3592 tmpbuf
[first
] = ' ';
3593 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
3594 tmpbuf
[first
+ second
+ 1] = '\0';
3598 as_bad (_("@%s reloc is not supported in %s bit mode"),
3599 gotrel
[j
].str
, mode_name
[(unsigned int) flag_code
]);
3604 /* Might be a symbol version string. Don't as_bad here. */
3608 /* x86_cons_fix_new is called via the expression parsing code when a
3609 reloc is needed. We use this hook to get the correct .got reloc. */
3610 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
3613 x86_cons_fix_new (frag
, off
, len
, exp
)
3619 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, got_reloc
);
3620 got_reloc
= NO_RELOC
;
3621 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3625 x86_cons (exp
, size
)
3631 /* Handle @GOTOFF and the like in an expression. */
3633 char *gotfree_input_line
;
3636 save
= input_line_pointer
;
3637 gotfree_input_line
= lex_got (&got_reloc
, &adjust
);
3638 if (gotfree_input_line
)
3639 input_line_pointer
= gotfree_input_line
;
3643 if (gotfree_input_line
)
3645 /* expression () has merrily parsed up to the end of line,
3646 or a comma - in the wrong buffer. Transfer how far
3647 input_line_pointer has moved to the right buffer. */
3648 input_line_pointer
= (save
3649 + (input_line_pointer
- gotfree_input_line
)
3651 free (gotfree_input_line
);
3661 #define O_secrel (O_max + 1)
3664 x86_pe_cons_fix_new (frag
, off
, len
, exp
)
3670 enum bfd_reloc_code_real r
= reloc (len
, 0, 0, NO_RELOC
);
3672 if (exp
->X_op
== O_secrel
)
3674 exp
->X_op
= O_symbol
;
3675 r
= BFD_RELOC_32_SECREL
;
3678 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
3682 pe_directive_secrel (dummy
)
3683 int dummy ATTRIBUTE_UNUSED
;
3690 if (exp
.X_op
== O_symbol
)
3691 exp
.X_op
= O_secrel
;
3693 emit_expr (&exp
, 4);
3695 while (*input_line_pointer
++ == ',');
3697 input_line_pointer
--;
3698 demand_empty_rest_of_line ();
3703 static int i386_immediate
PARAMS ((char *));
3706 i386_immediate (imm_start
)
3709 char *save_input_line_pointer
;
3711 char *gotfree_input_line
;
3716 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3718 as_bad (_("only 1 or 2 immediate operands are allowed"));
3722 exp
= &im_expressions
[i
.imm_operands
++];
3723 i
.op
[this_operand
].imms
= exp
;
3725 if (is_space_char (*imm_start
))
3728 save_input_line_pointer
= input_line_pointer
;
3729 input_line_pointer
= imm_start
;
3732 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3733 if (gotfree_input_line
)
3734 input_line_pointer
= gotfree_input_line
;
3737 exp_seg
= expression (exp
);
3740 if (*input_line_pointer
)
3741 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3743 input_line_pointer
= save_input_line_pointer
;
3745 if (gotfree_input_line
)
3746 free (gotfree_input_line
);
3749 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3751 /* Missing or bad expr becomes absolute 0. */
3752 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3754 exp
->X_op
= O_constant
;
3755 exp
->X_add_number
= 0;
3756 exp
->X_add_symbol
= (symbolS
*) 0;
3757 exp
->X_op_symbol
= (symbolS
*) 0;
3759 else if (exp
->X_op
== O_constant
)
3761 /* Size it properly later. */
3762 i
.types
[this_operand
] |= Imm64
;
3763 /* If BFD64, sign extend val. */
3764 if (!use_rela_relocations
)
3765 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3766 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3768 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3769 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
3770 && exp_seg
!= absolute_section
3771 && exp_seg
!= text_section
3772 && exp_seg
!= data_section
3773 && exp_seg
!= bss_section
3774 && exp_seg
!= undefined_section
3775 && !bfd_is_com_section (exp_seg
))
3777 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3783 /* This is an address. The size of the address will be
3784 determined later, depending on destination register,
3785 suffix, or the default for the section. */
3786 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3792 static char *i386_scale
PARAMS ((char *));
3799 char *save
= input_line_pointer
;
3801 input_line_pointer
= scale
;
3802 val
= get_absolute_expression ();
3808 i
.log2_scale_factor
= 0;
3811 i
.log2_scale_factor
= 1;
3814 i
.log2_scale_factor
= 2;
3817 i
.log2_scale_factor
= 3;
3820 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3822 input_line_pointer
= save
;
3825 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
3827 as_warn (_("scale factor of %d without an index register"),
3828 1 << i
.log2_scale_factor
);
3829 #if SCALE1_WHEN_NO_INDEX
3830 i
.log2_scale_factor
= 0;
3833 scale
= input_line_pointer
;
3834 input_line_pointer
= save
;
3838 static int i386_displacement
PARAMS ((char *, char *));
3841 i386_displacement (disp_start
, disp_end
)
3847 char *save_input_line_pointer
;
3849 char *gotfree_input_line
;
3851 int bigdisp
= Disp32
;
3853 if (flag_code
== CODE_64BIT
)
3855 if (i
.prefix
[ADDR_PREFIX
] == 0)
3858 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3860 i
.types
[this_operand
] |= bigdisp
;
3862 exp
= &disp_expressions
[i
.disp_operands
];
3863 i
.op
[this_operand
].disps
= exp
;
3865 save_input_line_pointer
= input_line_pointer
;
3866 input_line_pointer
= disp_start
;
3867 END_STRING_AND_SAVE (disp_end
);
3869 #ifndef GCC_ASM_O_HACK
3870 #define GCC_ASM_O_HACK 0
3873 END_STRING_AND_SAVE (disp_end
+ 1);
3874 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3875 && displacement_string_end
[-1] == '+')
3877 /* This hack is to avoid a warning when using the "o"
3878 constraint within gcc asm statements.
3881 #define _set_tssldt_desc(n,addr,limit,type) \
3882 __asm__ __volatile__ ( \
3884 "movw %w1,2+%0\n\t" \
3886 "movb %b1,4+%0\n\t" \
3887 "movb %4,5+%0\n\t" \
3888 "movb $0,6+%0\n\t" \
3889 "movb %h1,7+%0\n\t" \
3891 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3893 This works great except that the output assembler ends
3894 up looking a bit weird if it turns out that there is
3895 no offset. You end up producing code that looks like:
3908 So here we provide the missing zero. */
3910 *displacement_string_end
= '0';
3914 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
);
3915 if (gotfree_input_line
)
3916 input_line_pointer
= gotfree_input_line
;
3919 exp_seg
= expression (exp
);
3922 if (*input_line_pointer
)
3923 as_bad (_("junk `%s' after expression"), input_line_pointer
);
3925 RESTORE_END_STRING (disp_end
+ 1);
3927 RESTORE_END_STRING (disp_end
);
3928 input_line_pointer
= save_input_line_pointer
;
3930 if (gotfree_input_line
)
3931 free (gotfree_input_line
);
3934 /* We do this to make sure that the section symbol is in
3935 the symbol table. We will ultimately change the relocation
3936 to be relative to the beginning of the section. */
3937 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3938 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3940 if (exp
->X_op
!= O_symbol
)
3942 as_bad (_("bad expression used with @%s"),
3943 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
3949 if (S_IS_LOCAL (exp
->X_add_symbol
)
3950 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3951 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3952 exp
->X_op
= O_subtract
;
3953 exp
->X_op_symbol
= GOT_symbol
;
3954 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3955 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3957 i
.reloc
[this_operand
] = BFD_RELOC_32
;
3960 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3962 /* Missing or bad expr becomes absolute 0. */
3963 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3965 exp
->X_op
= O_constant
;
3966 exp
->X_add_number
= 0;
3967 exp
->X_add_symbol
= (symbolS
*) 0;
3968 exp
->X_op_symbol
= (symbolS
*) 0;
3971 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3972 if (exp
->X_op
!= O_constant
3973 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3974 && exp_seg
!= absolute_section
3975 && exp_seg
!= text_section
3976 && exp_seg
!= data_section
3977 && exp_seg
!= bss_section
3978 && exp_seg
!= undefined_section
3979 && !bfd_is_com_section (exp_seg
))
3981 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3985 else if (flag_code
== CODE_64BIT
)
3986 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3990 static int i386_index_check
PARAMS ((const char *));
3992 /* Make sure the memory operand we've been dealt is valid.
3993 Return 1 on success, 0 on a failure. */
3996 i386_index_check (operand_string
)
3997 const char *operand_string
;
4000 #if INFER_ADDR_PREFIX
4006 if (flag_code
== CODE_64BIT
)
4008 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4011 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4012 && (i
.base_reg
->reg_type
!= BaseIndex
4015 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4016 != (RegXX
| BaseIndex
))))
4021 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4025 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4026 != (Reg16
| BaseIndex
)))
4028 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4029 != (Reg16
| BaseIndex
))
4031 && i
.base_reg
->reg_num
< 6
4032 && i
.index_reg
->reg_num
>= 6
4033 && i
.log2_scale_factor
== 0))))
4040 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4042 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4043 != (Reg32
| BaseIndex
))))
4049 #if INFER_ADDR_PREFIX
4050 if (i
.prefix
[ADDR_PREFIX
] == 0)
4052 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4054 /* Change the size of any displacement too. At most one of
4055 Disp16 or Disp32 is set.
4056 FIXME. There doesn't seem to be any real need for separate
4057 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4058 Removing them would probably clean up the code quite a lot. */
4059 if (flag_code
!= CODE_64BIT
&& (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4060 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4065 as_bad (_("`%s' is not a valid base/index expression"),
4069 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4071 flag_code_names
[flag_code
]);
4076 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4080 i386_operand (operand_string
)
4081 char *operand_string
;
4085 char *op_string
= operand_string
;
4087 if (is_space_char (*op_string
))
4090 /* We check for an absolute prefix (differentiating,
4091 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4092 if (*op_string
== ABSOLUTE_PREFIX
)
4095 if (is_space_char (*op_string
))
4097 i
.types
[this_operand
] |= JumpAbsolute
;
4100 /* Check if operand is a register. */
4101 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4102 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
4104 /* Check for a segment override by searching for ':' after a
4105 segment register. */
4107 if (is_space_char (*op_string
))
4109 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
4114 i
.seg
[i
.mem_operands
] = &es
;
4117 i
.seg
[i
.mem_operands
] = &cs
;
4120 i
.seg
[i
.mem_operands
] = &ss
;
4123 i
.seg
[i
.mem_operands
] = &ds
;
4126 i
.seg
[i
.mem_operands
] = &fs
;
4129 i
.seg
[i
.mem_operands
] = &gs
;
4133 /* Skip the ':' and whitespace. */
4135 if (is_space_char (*op_string
))
4138 if (!is_digit_char (*op_string
)
4139 && !is_identifier_char (*op_string
)
4140 && *op_string
!= '('
4141 && *op_string
!= ABSOLUTE_PREFIX
)
4143 as_bad (_("bad memory operand `%s'"), op_string
);
4146 /* Handle case of %es:*foo. */
4147 if (*op_string
== ABSOLUTE_PREFIX
)
4150 if (is_space_char (*op_string
))
4152 i
.types
[this_operand
] |= JumpAbsolute
;
4154 goto do_memory_reference
;
4158 as_bad (_("junk `%s' after register"), op_string
);
4161 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
4162 i
.op
[this_operand
].regs
= r
;
4165 else if (*op_string
== REGISTER_PREFIX
)
4167 as_bad (_("bad register name `%s'"), op_string
);
4170 else if (*op_string
== IMMEDIATE_PREFIX
)
4173 if (i
.types
[this_operand
] & JumpAbsolute
)
4175 as_bad (_("immediate operand illegal with absolute jump"));
4178 if (!i386_immediate (op_string
))
4181 else if (is_digit_char (*op_string
)
4182 || is_identifier_char (*op_string
)
4183 || *op_string
== '(')
4185 /* This is a memory reference of some sort. */
4188 /* Start and end of displacement string expression (if found). */
4189 char *displacement_string_start
;
4190 char *displacement_string_end
;
4192 do_memory_reference
:
4193 if ((i
.mem_operands
== 1
4194 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4195 || i
.mem_operands
== 2)
4197 as_bad (_("too many memory references for `%s'"),
4198 current_templates
->start
->name
);
4202 /* Check for base index form. We detect the base index form by
4203 looking for an ')' at the end of the operand, searching
4204 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4206 base_string
= op_string
+ strlen (op_string
);
4209 if (is_space_char (*base_string
))
4212 /* If we only have a displacement, set-up for it to be parsed later. */
4213 displacement_string_start
= op_string
;
4214 displacement_string_end
= base_string
+ 1;
4216 if (*base_string
== ')')
4219 unsigned int parens_balanced
= 1;
4220 /* We've already checked that the number of left & right ()'s are
4221 equal, so this loop will not be infinite. */
4225 if (*base_string
== ')')
4227 if (*base_string
== '(')
4230 while (parens_balanced
);
4232 temp_string
= base_string
;
4234 /* Skip past '(' and whitespace. */
4236 if (is_space_char (*base_string
))
4239 if (*base_string
== ','
4240 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4241 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
4243 displacement_string_end
= temp_string
;
4245 i
.types
[this_operand
] |= BaseIndex
;
4249 base_string
= end_op
;
4250 if (is_space_char (*base_string
))
4254 /* There may be an index reg or scale factor here. */
4255 if (*base_string
== ',')
4258 if (is_space_char (*base_string
))
4261 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
4262 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
4264 base_string
= end_op
;
4265 if (is_space_char (*base_string
))
4267 if (*base_string
== ',')
4270 if (is_space_char (*base_string
))
4273 else if (*base_string
!= ')')
4275 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4280 else if (*base_string
== REGISTER_PREFIX
)
4282 as_bad (_("bad register name `%s'"), base_string
);
4286 /* Check for scale factor. */
4287 if (*base_string
!= ')')
4289 char *end_scale
= i386_scale (base_string
);
4294 base_string
= end_scale
;
4295 if (is_space_char (*base_string
))
4297 if (*base_string
!= ')')
4299 as_bad (_("expecting `)' after scale factor in `%s'"),
4304 else if (!i
.index_reg
)
4306 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4311 else if (*base_string
!= ')')
4313 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4318 else if (*base_string
== REGISTER_PREFIX
)
4320 as_bad (_("bad register name `%s'"), base_string
);
4325 /* If there's an expression beginning the operand, parse it,
4326 assuming displacement_string_start and
4327 displacement_string_end are meaningful. */
4328 if (displacement_string_start
!= displacement_string_end
)
4330 if (!i386_displacement (displacement_string_start
,
4331 displacement_string_end
))
4335 /* Special case for (%dx) while doing input/output op. */
4337 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
4339 && i
.log2_scale_factor
== 0
4340 && i
.seg
[i
.mem_operands
] == 0
4341 && (i
.types
[this_operand
] & Disp
) == 0)
4343 i
.types
[this_operand
] = InOutPortReg
;
4347 if (i386_index_check (operand_string
) == 0)
4353 /* It's not a memory operand; argh! */
4354 as_bad (_("invalid char %s beginning operand %d `%s'"),
4355 output_invalid (*op_string
),
4360 return 1; /* Normal return. */
4363 /* md_estimate_size_before_relax()
4365 Called just before relax() for rs_machine_dependent frags. The x86
4366 assembler uses these frags to handle variable size jump
4369 Any symbol that is now undefined will not become defined.
4370 Return the correct fr_subtype in the frag.
4371 Return the initial "guess for variable size of frag" to caller.
4372 The guess is actually the growth beyond the fixed part. Whatever
4373 we do to grow the fixed or variable part contributes to our
4377 md_estimate_size_before_relax (fragP
, segment
)
4381 /* We've already got fragP->fr_subtype right; all we have to do is
4382 check for un-relaxable symbols. On an ELF system, we can't relax
4383 an externally visible symbol, because it may be overridden by a
4385 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4386 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4387 || (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4388 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
4389 || S_IS_WEAK (fragP
->fr_symbol
)))
4393 /* Symbol is undefined in this segment, or we need to keep a
4394 reloc so that weak symbols can be overridden. */
4395 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
4396 enum bfd_reloc_code_real reloc_type
;
4397 unsigned char *opcode
;
4400 if (fragP
->fr_var
!= NO_RELOC
)
4401 reloc_type
= fragP
->fr_var
;
4403 reloc_type
= BFD_RELOC_16_PCREL
;
4405 reloc_type
= BFD_RELOC_32_PCREL
;
4407 old_fr_fix
= fragP
->fr_fix
;
4408 opcode
= (unsigned char *) fragP
->fr_opcode
;
4410 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
4413 /* Make jmp (0xeb) a (d)word displacement jump. */
4415 fragP
->fr_fix
+= size
;
4416 fix_new (fragP
, old_fr_fix
, size
,
4418 fragP
->fr_offset
, 1,
4424 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
4426 /* Negate the condition, and branch past an
4427 unconditional jump. */
4430 /* Insert an unconditional jump. */
4432 /* We added two extra opcode bytes, and have a two byte
4434 fragP
->fr_fix
+= 2 + 2;
4435 fix_new (fragP
, old_fr_fix
+ 2, 2,
4437 fragP
->fr_offset
, 1,
4444 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
4449 fixP
= fix_new (fragP
, old_fr_fix
, 1,
4451 fragP
->fr_offset
, 1,
4453 fixP
->fx_signed
= 1;
4457 /* This changes the byte-displacement jump 0x7N
4458 to the (d)word-displacement jump 0x0f,0x8N. */
4459 opcode
[1] = opcode
[0] + 0x10;
4460 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4461 /* We've added an opcode byte. */
4462 fragP
->fr_fix
+= 1 + size
;
4463 fix_new (fragP
, old_fr_fix
+ 1, size
,
4465 fragP
->fr_offset
, 1,
4470 BAD_CASE (fragP
->fr_subtype
);
4474 return fragP
->fr_fix
- old_fr_fix
;
4477 /* Guess size depending on current relax state. Initially the relax
4478 state will correspond to a short jump and we return 1, because
4479 the variable part of the frag (the branch offset) is one byte
4480 long. However, we can relax a section more than once and in that
4481 case we must either set fr_subtype back to the unrelaxed state,
4482 or return the value for the appropriate branch. */
4483 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4486 /* Called after relax() is finished.
4488 In: Address of frag.
4489 fr_type == rs_machine_dependent.
4490 fr_subtype is what the address relaxed to.
4492 Out: Any fixSs and constants are set up.
4493 Caller will turn frag into a ".space 0". */
4496 md_convert_frag (abfd
, sec
, fragP
)
4497 bfd
*abfd ATTRIBUTE_UNUSED
;
4498 segT sec ATTRIBUTE_UNUSED
;
4501 unsigned char *opcode
;
4502 unsigned char *where_to_put_displacement
= NULL
;
4503 offsetT target_address
;
4504 offsetT opcode_address
;
4505 unsigned int extension
= 0;
4506 offsetT displacement_from_opcode_start
;
4508 opcode
= (unsigned char *) fragP
->fr_opcode
;
4510 /* Address we want to reach in file space. */
4511 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4513 /* Address opcode resides at in file space. */
4514 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4516 /* Displacement from opcode start to fill into instruction. */
4517 displacement_from_opcode_start
= target_address
- opcode_address
;
4519 if ((fragP
->fr_subtype
& BIG
) == 0)
4521 /* Don't have to change opcode. */
4522 extension
= 1; /* 1 opcode + 1 displacement */
4523 where_to_put_displacement
= &opcode
[1];
4527 if (no_cond_jump_promotion
4528 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4529 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4531 switch (fragP
->fr_subtype
)
4533 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4534 extension
= 4; /* 1 opcode + 4 displacement */
4536 where_to_put_displacement
= &opcode
[1];
4539 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4540 extension
= 2; /* 1 opcode + 2 displacement */
4542 where_to_put_displacement
= &opcode
[1];
4545 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4546 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4547 extension
= 5; /* 2 opcode + 4 displacement */
4548 opcode
[1] = opcode
[0] + 0x10;
4549 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4550 where_to_put_displacement
= &opcode
[2];
4553 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4554 extension
= 3; /* 2 opcode + 2 displacement */
4555 opcode
[1] = opcode
[0] + 0x10;
4556 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4557 where_to_put_displacement
= &opcode
[2];
4560 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4565 where_to_put_displacement
= &opcode
[3];
4569 BAD_CASE (fragP
->fr_subtype
);
4574 /* Now put displacement after opcode. */
4575 md_number_to_chars ((char *) where_to_put_displacement
,
4576 (valueT
) (displacement_from_opcode_start
- extension
),
4577 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4578 fragP
->fr_fix
+= extension
;
4581 /* Size of byte displacement jmp. */
4582 int md_short_jump_size
= 2;
4584 /* Size of dword displacement jmp. */
4585 int md_long_jump_size
= 5;
4587 /* Size of relocation record. */
4588 const int md_reloc_size
= 8;
4591 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4593 addressT from_addr
, to_addr
;
4594 fragS
*frag ATTRIBUTE_UNUSED
;
4595 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4599 offset
= to_addr
- (from_addr
+ 2);
4600 /* Opcode for byte-disp jump. */
4601 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4602 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4606 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4608 addressT from_addr
, to_addr
;
4609 fragS
*frag ATTRIBUTE_UNUSED
;
4610 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4614 offset
= to_addr
- (from_addr
+ 5);
4615 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4616 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4619 /* Apply a fixup (fixS) to segment data, once it has been determined
4620 by our caller that we have all the info we need to fix it up.
4622 On the 386, immediates, displacements, and data pointers are all in
4623 the same (little-endian) format, so we don't need to care about which
4627 md_apply_fix3 (fixP
, valP
, seg
)
4628 /* The fix we're to put in. */
4630 /* Pointer to the value of the bits. */
4632 /* Segment fix is from. */
4633 segT seg ATTRIBUTE_UNUSED
;
4635 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4636 valueT value
= *valP
;
4638 #if !defined (TE_Mach)
4641 switch (fixP
->fx_r_type
)
4647 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4650 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4653 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4658 if (fixP
->fx_addsy
!= NULL
4659 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4660 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4661 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4662 && !use_rela_relocations
)
4664 /* This is a hack. There should be a better way to handle this.
4665 This covers for the fact that bfd_install_relocation will
4666 subtract the current location (for partial_inplace, PC relative
4667 relocations); see more below. */
4669 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4671 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4674 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4676 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4677 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4679 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4682 || (symbol_section_p (fixP
->fx_addsy
)
4683 && sym_seg
!= absolute_section
))
4684 && !generic_force_reloc (fixP
))
4686 /* Yes, we add the values in twice. This is because
4687 bfd_install_relocation subtracts them out again. I think
4688 bfd_install_relocation is broken, but I don't dare change
4690 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4694 #if defined (OBJ_COFF) && defined (TE_PE)
4695 /* For some reason, the PE format does not store a section
4696 address offset for a PC relative symbol. */
4697 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4698 value
+= md_pcrel_from (fixP
);
4702 /* Fix a few things - the dynamic linker expects certain values here,
4703 and we must not disappoint it. */
4704 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4705 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4707 switch (fixP
->fx_r_type
)
4709 case BFD_RELOC_386_PLT32
:
4710 case BFD_RELOC_X86_64_PLT32
:
4711 /* Make the jump instruction point to the address of the operand. At
4712 runtime we merely add the offset to the actual PLT entry. */
4716 case BFD_RELOC_386_TLS_GD
:
4717 case BFD_RELOC_386_TLS_LDM
:
4718 case BFD_RELOC_386_TLS_IE_32
:
4719 case BFD_RELOC_386_TLS_IE
:
4720 case BFD_RELOC_386_TLS_GOTIE
:
4721 case BFD_RELOC_X86_64_TLSGD
:
4722 case BFD_RELOC_X86_64_TLSLD
:
4723 case BFD_RELOC_X86_64_GOTTPOFF
:
4724 value
= 0; /* Fully resolved at runtime. No addend. */
4726 case BFD_RELOC_386_TLS_LE
:
4727 case BFD_RELOC_386_TLS_LDO_32
:
4728 case BFD_RELOC_386_TLS_LE_32
:
4729 case BFD_RELOC_X86_64_DTPOFF32
:
4730 case BFD_RELOC_X86_64_TPOFF32
:
4731 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4734 case BFD_RELOC_386_GOT32
:
4735 case BFD_RELOC_X86_64_GOT32
:
4736 value
= 0; /* Fully resolved at runtime. No addend. */
4739 case BFD_RELOC_VTABLE_INHERIT
:
4740 case BFD_RELOC_VTABLE_ENTRY
:
4747 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4749 #endif /* !defined (TE_Mach) */
4751 /* Are we finished with this relocation now? */
4752 if (fixP
->fx_addsy
== NULL
)
4754 else if (use_rela_relocations
)
4756 fixP
->fx_no_overflow
= 1;
4757 /* Remember value for tc_gen_reloc. */
4758 fixP
->fx_addnumber
= value
;
4762 md_number_to_chars (p
, value
, fixP
->fx_size
);
4765 #define MAX_LITTLENUMS 6
4767 /* Turn the string pointed to by litP into a floating point constant
4768 of type TYPE, and emit the appropriate bytes. The number of
4769 LITTLENUMS emitted is stored in *SIZEP. An error message is
4770 returned, or NULL on OK. */
4773 md_atof (type
, litP
, sizeP
)
4779 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4780 LITTLENUM_TYPE
*wordP
;
4802 return _("Bad call to md_atof ()");
4804 t
= atof_ieee (input_line_pointer
, type
, words
);
4806 input_line_pointer
= t
;
4808 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4809 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4810 the bigendian 386. */
4811 for (wordP
= words
+ prec
- 1; prec
--;)
4813 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4814 litP
+= sizeof (LITTLENUM_TYPE
);
4819 char output_invalid_buf
[8];
4826 sprintf (output_invalid_buf
, "'%c'", c
);
4828 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4829 return output_invalid_buf
;
4832 /* REG_STRING starts *before* REGISTER_PREFIX. */
4834 static const reg_entry
*
4835 parse_register (reg_string
, end_op
)
4839 char *s
= reg_string
;
4841 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4844 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4845 if (*s
== REGISTER_PREFIX
)
4848 if (is_space_char (*s
))
4852 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4854 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4855 return (const reg_entry
*) NULL
;
4859 /* For naked regs, make sure that we are not dealing with an identifier.
4860 This prevents confusing an identifier like `eax_var' with register
4862 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4863 return (const reg_entry
*) NULL
;
4867 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4869 /* Handle floating point regs, allowing spaces in the (i) part. */
4870 if (r
== i386_regtab
/* %st is first entry of table */)
4872 if (is_space_char (*s
))
4877 if (is_space_char (*s
))
4879 if (*s
>= '0' && *s
<= '7')
4881 r
= &i386_float_regtab
[*s
- '0'];
4883 if (is_space_char (*s
))
4891 /* We have "%st(" then garbage. */
4892 return (const reg_entry
*) NULL
;
4897 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
4898 && flag_code
!= CODE_64BIT
)
4899 return (const reg_entry
*) NULL
;
4904 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4905 const char *md_shortopts
= "kVQ:sqn";
4907 const char *md_shortopts
= "qn";
4910 struct option md_longopts
[] = {
4911 #define OPTION_32 (OPTION_MD_BASE + 0)
4912 {"32", no_argument
, NULL
, OPTION_32
},
4913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4914 #define OPTION_64 (OPTION_MD_BASE + 1)
4915 {"64", no_argument
, NULL
, OPTION_64
},
4917 {NULL
, no_argument
, NULL
, 0}
4919 size_t md_longopts_size
= sizeof (md_longopts
);
4922 md_parse_option (c
, arg
)
4924 char *arg ATTRIBUTE_UNUSED
;
4929 optimize_align_code
= 0;
4936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4937 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4938 should be emitted or not. FIXME: Not implemented. */
4942 /* -V: SVR4 argument to print version ID. */
4944 print_version_id ();
4947 /* -k: Ignore for FreeBSD compatibility. */
4952 /* -s: On i386 Solaris, this tells the native assembler to use
4953 .stab instead of .stab.excl. We always use .stab anyhow. */
4958 const char **list
, **l
;
4960 list
= bfd_target_list ();
4961 for (l
= list
; *l
!= NULL
; l
++)
4962 if (strcmp (*l
, "elf64-x86-64") == 0)
4964 default_arch
= "x86_64";
4968 as_fatal (_("No compiled in support for x86_64"));
4975 default_arch
= "i386";
4985 md_show_usage (stream
)
4988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4989 fprintf (stream
, _("\
4991 -V print assembler version number\n\
4993 -n Do not optimize code alignment\n\
4994 -q quieten some warnings\n\
4997 fprintf (stream
, _("\
4998 -n Do not optimize code alignment\n\
4999 -q quieten some warnings\n"));
5003 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5004 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5006 /* Pick the target format to use. */
5009 i386_target_format ()
5011 if (!strcmp (default_arch
, "x86_64"))
5012 set_code_flag (CODE_64BIT
);
5013 else if (!strcmp (default_arch
, "i386"))
5014 set_code_flag (CODE_32BIT
);
5016 as_fatal (_("Unknown architecture"));
5017 switch (OUTPUT_FLAVOR
)
5019 #ifdef OBJ_MAYBE_AOUT
5020 case bfd_target_aout_flavour
:
5021 return AOUT_TARGET_FORMAT
;
5023 #ifdef OBJ_MAYBE_COFF
5024 case bfd_target_coff_flavour
:
5027 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5028 case bfd_target_elf_flavour
:
5030 if (flag_code
== CODE_64BIT
)
5031 use_rela_relocations
= 1;
5032 return flag_code
== CODE_64BIT
? "elf64-x86-64" : ELF_TARGET_FORMAT
;
5041 #endif /* OBJ_MAYBE_ more than one */
5043 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5044 void i386_elf_emit_arch_note ()
5046 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
5047 && cpu_arch_name
!= NULL
)
5050 asection
*seg
= now_seg
;
5051 subsegT subseg
= now_subseg
;
5052 Elf_Internal_Note i_note
;
5053 Elf_External_Note e_note
;
5054 asection
*note_secp
;
5057 /* Create the .note section. */
5058 note_secp
= subseg_new (".note", 0);
5059 bfd_set_section_flags (stdoutput
,
5061 SEC_HAS_CONTENTS
| SEC_READONLY
);
5063 /* Process the arch string. */
5064 len
= strlen (cpu_arch_name
);
5066 i_note
.namesz
= len
+ 1;
5068 i_note
.type
= NT_ARCH
;
5069 p
= frag_more (sizeof (e_note
.namesz
));
5070 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
5071 p
= frag_more (sizeof (e_note
.descsz
));
5072 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
5073 p
= frag_more (sizeof (e_note
.type
));
5074 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
5075 p
= frag_more (len
+ 1);
5076 strcpy (p
, cpu_arch_name
);
5078 frag_align (2, 0, 0);
5080 subseg_set (seg
, subseg
);
5086 md_undefined_symbol (name
)
5089 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
5090 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
5091 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
5092 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
5096 if (symbol_find (name
))
5097 as_bad (_("GOT already in symbol table"));
5098 GOT_symbol
= symbol_new (name
, undefined_section
,
5099 (valueT
) 0, &zero_address_frag
);
5106 /* Round up a section size to the appropriate boundary. */
5109 md_section_align (segment
, size
)
5110 segT segment ATTRIBUTE_UNUSED
;
5113 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5114 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
5116 /* For a.out, force the section size to be aligned. If we don't do
5117 this, BFD will align it for us, but it will not write out the
5118 final bytes of the section. This may be a bug in BFD, but it is
5119 easier to fix it here since that is how the other a.out targets
5123 align
= bfd_get_section_alignment (stdoutput
, segment
);
5124 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
5131 /* On the i386, PC-relative offsets are relative to the start of the
5132 next instruction. That is, the address of the offset, plus its
5133 size, since the offset is always the last part of the insn. */
5136 md_pcrel_from (fixP
)
5139 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5146 int ignore ATTRIBUTE_UNUSED
;
5150 temp
= get_absolute_expression ();
5151 subseg_set (bss_section
, (subsegT
) temp
);
5152 demand_empty_rest_of_line ();
5158 i386_validate_fix (fixp
)
5161 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
5163 /* GOTOFF relocation are nonsense in 64bit mode. */
5164 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
5166 if (flag_code
!= CODE_64BIT
)
5168 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
5172 if (flag_code
== CODE_64BIT
)
5174 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
5181 tc_gen_reloc (section
, fixp
)
5182 asection
*section ATTRIBUTE_UNUSED
;
5186 bfd_reloc_code_real_type code
;
5188 switch (fixp
->fx_r_type
)
5190 case BFD_RELOC_X86_64_PLT32
:
5191 case BFD_RELOC_X86_64_GOT32
:
5192 case BFD_RELOC_X86_64_GOTPCREL
:
5193 case BFD_RELOC_386_PLT32
:
5194 case BFD_RELOC_386_GOT32
:
5195 case BFD_RELOC_386_GOTOFF
:
5196 case BFD_RELOC_386_GOTPC
:
5197 case BFD_RELOC_386_TLS_GD
:
5198 case BFD_RELOC_386_TLS_LDM
:
5199 case BFD_RELOC_386_TLS_LDO_32
:
5200 case BFD_RELOC_386_TLS_IE_32
:
5201 case BFD_RELOC_386_TLS_IE
:
5202 case BFD_RELOC_386_TLS_GOTIE
:
5203 case BFD_RELOC_386_TLS_LE_32
:
5204 case BFD_RELOC_386_TLS_LE
:
5205 case BFD_RELOC_X86_64_32S
:
5206 case BFD_RELOC_X86_64_TLSGD
:
5207 case BFD_RELOC_X86_64_TLSLD
:
5208 case BFD_RELOC_X86_64_DTPOFF32
:
5209 case BFD_RELOC_X86_64_GOTTPOFF
:
5210 case BFD_RELOC_X86_64_TPOFF32
:
5212 case BFD_RELOC_VTABLE_ENTRY
:
5213 case BFD_RELOC_VTABLE_INHERIT
:
5215 case BFD_RELOC_32_SECREL
:
5217 code
= fixp
->fx_r_type
;
5222 switch (fixp
->fx_size
)
5225 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5226 _("can not do %d byte pc-relative relocation"),
5228 code
= BFD_RELOC_32_PCREL
;
5230 case 1: code
= BFD_RELOC_8_PCREL
; break;
5231 case 2: code
= BFD_RELOC_16_PCREL
; break;
5232 case 4: code
= BFD_RELOC_32_PCREL
; break;
5237 switch (fixp
->fx_size
)
5240 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5241 _("can not do %d byte relocation"),
5243 code
= BFD_RELOC_32
;
5245 case 1: code
= BFD_RELOC_8
; break;
5246 case 2: code
= BFD_RELOC_16
; break;
5247 case 4: code
= BFD_RELOC_32
; break;
5249 case 8: code
= BFD_RELOC_64
; break;
5256 if (code
== BFD_RELOC_32
5258 && fixp
->fx_addsy
== GOT_symbol
)
5260 /* We don't support GOTPC on 64bit targets. */
5261 if (flag_code
== CODE_64BIT
)
5263 code
= BFD_RELOC_386_GOTPC
;
5266 rel
= (arelent
*) xmalloc (sizeof (arelent
));
5267 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5268 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5270 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5273 if (S_IS_WEAK (fixp
->fx_addsy
))
5274 rel
->addend
= rel
->address
- (*rel
->sym_ptr_ptr
)->value
+ 4;
5277 if (!use_rela_relocations
)
5279 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5280 vtable entry to be used in the relocation's section offset. */
5281 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5282 rel
->address
= fixp
->fx_offset
;
5286 /* Use the rela in 64bit mode. */
5289 if (!fixp
->fx_pcrel
)
5290 rel
->addend
= fixp
->fx_offset
;
5294 case BFD_RELOC_X86_64_PLT32
:
5295 case BFD_RELOC_X86_64_GOT32
:
5296 case BFD_RELOC_X86_64_GOTPCREL
:
5297 case BFD_RELOC_X86_64_TLSGD
:
5298 case BFD_RELOC_X86_64_TLSLD
:
5299 case BFD_RELOC_X86_64_GOTTPOFF
:
5300 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
5303 rel
->addend
= (section
->vma
5305 + fixp
->fx_addnumber
5306 + md_pcrel_from (fixp
));
5311 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
5312 if (rel
->howto
== NULL
)
5314 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5315 _("cannot represent relocation type %s"),
5316 bfd_get_reloc_code_name (code
));
5317 /* Set howto to a garbage value so that we can keep going. */
5318 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
5319 assert (rel
->howto
!= NULL
);
5326 /* Parse operands using Intel syntax. This implements a recursive descent
5327 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5330 FIXME: We do not recognize the full operand grammar defined in the MASM
5331 documentation. In particular, all the structure/union and
5332 high-level macro operands are missing.
5334 Uppercase words are terminals, lower case words are non-terminals.
5335 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5336 bars '|' denote choices. Most grammar productions are implemented in
5337 functions called 'intel_<production>'.
5339 Initial production is 'expr'.
5341 addOp + | - | & | \| | << | >>
5345 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5347 constant digits [[ radixOverride ]]
5349 dataType BYTE | WORD | DWORD | QWORD | XWORD
5383 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5384 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5386 hexdigit a | b | c | d | e | f
5387 | A | B | C | D | E | F
5397 register specialRegister
5401 segmentRegister CS | DS | ES | FS | GS | SS
5403 specialRegister CR0 | CR2 | CR3
5404 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5405 | TR3 | TR4 | TR5 | TR6 | TR7
5407 We simplify the grammar in obvious places (e.g., register parsing is
5408 done by calling parse_register) and eliminate immediate left recursion
5409 to implement a recursive-descent parser.
5450 /* Parsing structure for the intel syntax parser. Used to implement the
5451 semantic actions for the operand grammar. */
5452 struct intel_parser_s
5454 char *op_string
; /* The string being parsed. */
5455 int got_a_float
; /* Whether the operand is a float. */
5456 int op_modifier
; /* Operand modifier. */
5457 int is_mem
; /* 1 if operand is memory reference. */
5458 const reg_entry
*reg
; /* Last register reference found. */
5459 char *disp
; /* Displacement string being built. */
5462 static struct intel_parser_s intel_parser
;
5464 /* Token structure for parsing intel syntax. */
5467 int code
; /* Token code. */
5468 const reg_entry
*reg
; /* Register entry for register tokens. */
5469 char *str
; /* String representation. */
5472 static struct intel_token cur_token
, prev_token
;
5474 /* Token codes for the intel parser. Since T_SHORT is already used
5475 by COFF, undefine it first to prevent a warning. */
5489 #define T_SHIFTOP 12
5491 /* Prototypes for intel parser functions. */
5492 static int intel_match_token
PARAMS ((int code
));
5493 static void intel_get_token
PARAMS ((void));
5494 static void intel_putback_token
PARAMS ((void));
5495 static int intel_expr
PARAMS ((void));
5496 static int intel_e05
PARAMS ((void));
5497 static int intel_e05_1
PARAMS ((void));
5498 static int intel_e06
PARAMS ((void));
5499 static int intel_e06_1
PARAMS ((void));
5500 static int intel_e09
PARAMS ((void));
5501 static int intel_e09_1
PARAMS ((void));
5502 static int intel_e10
PARAMS ((void));
5503 static int intel_e10_1
PARAMS ((void));
5504 static int intel_e11
PARAMS ((void));
5507 i386_intel_operand (operand_string
, got_a_float
)
5508 char *operand_string
;
5514 /* Initialize token holders. */
5515 cur_token
.code
= prev_token
.code
= T_NIL
;
5516 cur_token
.reg
= prev_token
.reg
= NULL
;
5517 cur_token
.str
= prev_token
.str
= NULL
;
5519 /* Initialize parser structure. */
5520 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5523 strcpy (intel_parser
.op_string
, operand_string
);
5524 intel_parser
.got_a_float
= got_a_float
;
5525 intel_parser
.op_modifier
= -1;
5526 intel_parser
.is_mem
= 0;
5527 intel_parser
.reg
= NULL
;
5528 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5529 if (intel_parser
.disp
== NULL
)
5531 intel_parser
.disp
[0] = '\0';
5533 /* Read the first token and start the parser. */
5535 ret
= intel_expr ();
5539 /* If we found a memory reference, hand it over to i386_displacement
5540 to fill in the rest of the operand fields. */
5541 if (intel_parser
.is_mem
)
5543 if ((i
.mem_operands
== 1
5544 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5545 || i
.mem_operands
== 2)
5547 as_bad (_("too many memory references for '%s'"),
5548 current_templates
->start
->name
);
5553 char *s
= intel_parser
.disp
;
5556 /* Add the displacement expression. */
5558 ret
= i386_displacement (s
, s
+ strlen (s
));
5560 ret
= i386_index_check (operand_string
);
5564 /* Constant and OFFSET expressions are handled by i386_immediate. */
5565 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5566 || intel_parser
.reg
== NULL
)
5567 ret
= i386_immediate (intel_parser
.disp
);
5571 free (intel_parser
.disp
);
5581 /* expr SHORT e05 */
5582 if (cur_token
.code
== T_SHORT
)
5584 intel_parser
.op_modifier
= SHORT
;
5585 intel_match_token (T_SHORT
);
5587 return (intel_e05 ());
5592 return intel_e05 ();
5602 return (intel_e06 () && intel_e05_1 ());
5608 /* e05' addOp e06 e05' */
5609 if (cur_token
.code
== '+' || cur_token
.code
== '-'
5610 || cur_token
.code
== '&' || cur_token
.code
== '|'
5611 || cur_token
.code
== T_SHIFTOP
)
5613 strcat (intel_parser
.disp
, cur_token
.str
);
5614 intel_match_token (cur_token
.code
);
5616 return (intel_e06 () && intel_e05_1 ());
5631 return (intel_e09 () && intel_e06_1 ());
5637 /* e06' mulOp e09 e06' */
5638 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5640 strcat (intel_parser
.disp
, cur_token
.str
);
5641 intel_match_token (cur_token
.code
);
5643 return (intel_e09 () && intel_e06_1 ());
5651 /* e09 OFFSET e10 e09'
5660 /* e09 OFFSET e10 e09' */
5661 if (cur_token
.code
== T_OFFSET
)
5663 intel_parser
.is_mem
= 0;
5664 intel_parser
.op_modifier
= OFFSET_FLAT
;
5665 intel_match_token (T_OFFSET
);
5667 return (intel_e10 () && intel_e09_1 ());
5672 return (intel_e10 () && intel_e09_1 ());
5678 /* e09' PTR e10 e09' */
5679 if (cur_token
.code
== T_PTR
)
5681 if (prev_token
.code
== T_BYTE
)
5682 i
.suffix
= BYTE_MNEM_SUFFIX
;
5684 else if (prev_token
.code
== T_WORD
)
5686 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5687 i
.suffix
= SHORT_MNEM_SUFFIX
;
5689 i
.suffix
= WORD_MNEM_SUFFIX
;
5692 else if (prev_token
.code
== T_DWORD
)
5694 if (intel_parser
.got_a_float
== 1) /* "f..." */
5695 i
.suffix
= SHORT_MNEM_SUFFIX
;
5697 i
.suffix
= LONG_MNEM_SUFFIX
;
5700 else if (prev_token
.code
== T_QWORD
)
5702 if (intel_parser
.got_a_float
== 1) /* "f..." */
5703 i
.suffix
= LONG_MNEM_SUFFIX
;
5705 i
.suffix
= QWORD_MNEM_SUFFIX
;
5708 else if (prev_token
.code
== T_XWORD
)
5709 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5713 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
5717 intel_match_token (T_PTR
);
5719 return (intel_e10 () && intel_e09_1 ());
5722 /* e09 : e10 e09' */
5723 else if (cur_token
.code
== ':')
5725 /* Mark as a memory operand only if it's not already known to be an
5726 offset expression. */
5727 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5728 intel_parser
.is_mem
= 1;
5730 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5745 return (intel_e11 () && intel_e10_1 ());
5751 /* e10' [ expr ] e10' */
5752 if (cur_token
.code
== '[')
5754 intel_match_token ('[');
5756 /* Mark as a memory operand only if it's not already known to be an
5757 offset expression. If it's an offset expression, we need to keep
5759 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5760 intel_parser
.is_mem
= 1;
5762 strcat (intel_parser
.disp
, "[");
5764 /* Add a '+' to the displacement string if necessary. */
5765 if (*intel_parser
.disp
!= '\0'
5766 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5767 strcat (intel_parser
.disp
, "+");
5769 if (intel_expr () && intel_match_token (']'))
5771 /* Preserve brackets when the operand is an offset expression. */
5772 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5773 strcat (intel_parser
.disp
, "]");
5775 return intel_e10_1 ();
5803 if (cur_token
.code
== '(')
5805 intel_match_token ('(');
5806 strcat (intel_parser
.disp
, "(");
5808 if (intel_expr () && intel_match_token (')'))
5810 strcat (intel_parser
.disp
, ")");
5818 else if (cur_token
.code
== '~')
5820 strcat (intel_parser
.disp
, "~");
5821 intel_match_token ('~');
5823 return (intel_e11 ());
5827 else if (cur_token
.code
== '[')
5829 intel_match_token ('[');
5831 /* Mark as a memory operand only if it's not already known to be an
5832 offset expression. If it's an offset expression, we need to keep
5834 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5835 intel_parser
.is_mem
= 1;
5837 strcat (intel_parser
.disp
, "[");
5839 /* Operands for jump/call inside brackets denote absolute addresses. */
5840 if (current_templates
->start
->opcode_modifier
& Jump
5841 || current_templates
->start
->opcode_modifier
& JumpDword
5842 || current_templates
->start
->opcode_modifier
& JumpByte
5843 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5844 i
.types
[this_operand
] |= JumpAbsolute
;
5846 /* Add a '+' to the displacement string if necessary. */
5847 if (*intel_parser
.disp
!= '\0'
5848 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5849 strcat (intel_parser
.disp
, "+");
5851 if (intel_expr () && intel_match_token (']'))
5853 /* Preserve brackets when the operand is an offset expression. */
5854 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5855 strcat (intel_parser
.disp
, "]");
5868 else if (cur_token
.code
== T_BYTE
5869 || cur_token
.code
== T_WORD
5870 || cur_token
.code
== T_DWORD
5871 || cur_token
.code
== T_QWORD
5872 || cur_token
.code
== T_XWORD
)
5874 intel_match_token (cur_token
.code
);
5881 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5883 strcat (intel_parser
.disp
, cur_token
.str
);
5884 intel_match_token (cur_token
.code
);
5886 /* Mark as a memory operand only if it's not already known to be an
5887 offset expression. */
5888 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5889 intel_parser
.is_mem
= 1;
5895 else if (cur_token
.code
== T_REG
)
5897 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5899 intel_match_token (T_REG
);
5901 /* Check for segment change. */
5902 if (cur_token
.code
== ':')
5904 if (reg
->reg_type
& (SReg2
| SReg3
))
5906 switch (reg
->reg_num
)
5909 i
.seg
[i
.mem_operands
] = &es
;
5912 i
.seg
[i
.mem_operands
] = &cs
;
5915 i
.seg
[i
.mem_operands
] = &ss
;
5918 i
.seg
[i
.mem_operands
] = &ds
;
5921 i
.seg
[i
.mem_operands
] = &fs
;
5924 i
.seg
[i
.mem_operands
] = &gs
;
5930 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5935 /* Not a segment register. Check for register scaling. */
5936 else if (cur_token
.code
== '*')
5938 if (!intel_parser
.is_mem
)
5940 as_bad (_("Register scaling only allowed in memory operands."));
5944 /* What follows must be a valid scale. */
5945 if (intel_match_token ('*')
5946 && strchr ("01248", *cur_token
.str
))
5949 i
.types
[this_operand
] |= BaseIndex
;
5951 /* Set the scale after setting the register (otherwise,
5952 i386_scale will complain) */
5953 i386_scale (cur_token
.str
);
5954 intel_match_token (T_CONST
);
5958 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5964 /* No scaling. If this is a memory operand, the register is either a
5965 base register (first occurrence) or an index register (second
5967 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5969 if (i
.base_reg
&& i
.index_reg
)
5971 as_bad (_("Too many register references in memory operand."));
5975 if (i
.base_reg
== NULL
)
5980 i
.types
[this_operand
] |= BaseIndex
;
5983 /* Offset modifier. Add the register to the displacement string to be
5984 parsed as an immediate expression after we're done. */
5985 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5986 strcat (intel_parser
.disp
, reg
->reg_name
);
5988 /* It's neither base nor index nor offset. */
5991 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5992 i
.op
[this_operand
].regs
= reg
;
5996 /* Since registers are not part of the displacement string (except
5997 when we're parsing offset operands), we may need to remove any
5998 preceding '+' from the displacement string. */
5999 if (*intel_parser
.disp
!= '\0'
6000 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
6002 char *s
= intel_parser
.disp
;
6003 s
+= strlen (s
) - 1;
6012 else if (cur_token
.code
== T_ID
)
6014 /* Add the identifier to the displacement string. */
6015 strcat (intel_parser
.disp
, cur_token
.str
);
6016 intel_match_token (T_ID
);
6018 /* The identifier represents a memory reference only if it's not
6019 preceded by an offset modifier. */
6020 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
6021 intel_parser
.is_mem
= 1;
6027 else if (cur_token
.code
== T_CONST
6028 || cur_token
.code
== '-'
6029 || cur_token
.code
== '+')
6033 /* Allow constants that start with `+' or `-'. */
6034 if (cur_token
.code
== '-' || cur_token
.code
== '+')
6036 strcat (intel_parser
.disp
, cur_token
.str
);
6037 intel_match_token (cur_token
.code
);
6038 if (cur_token
.code
!= T_CONST
)
6040 as_bad (_("Syntax error. Expecting a constant. Got `%s'."),
6046 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
6047 if (save_str
== NULL
)
6049 strcpy (save_str
, cur_token
.str
);
6051 /* Get the next token to check for register scaling. */
6052 intel_match_token (cur_token
.code
);
6054 /* Check if this constant is a scaling factor for an index register. */
6055 if (cur_token
.code
== '*')
6057 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
6059 if (!intel_parser
.is_mem
)
6061 as_bad (_("Register scaling only allowed in memory operands."));
6065 /* The constant is followed by `* reg', so it must be
6067 if (strchr ("01248", *save_str
))
6069 i
.index_reg
= cur_token
.reg
;
6070 i
.types
[this_operand
] |= BaseIndex
;
6072 /* Set the scale after setting the register (otherwise,
6073 i386_scale will complain) */
6074 i386_scale (save_str
);
6075 intel_match_token (T_REG
);
6077 /* Since registers are not part of the displacement
6078 string, we may need to remove any preceding '+' from
6079 the displacement string. */
6080 if (*intel_parser
.disp
!= '\0')
6082 char *s
= intel_parser
.disp
;
6083 s
+= strlen (s
) - 1;
6096 /* The constant was not used for register scaling. Since we have
6097 already consumed the token following `*' we now need to put it
6098 back in the stream. */
6100 intel_putback_token ();
6103 /* Add the constant to the displacement string. */
6104 strcat (intel_parser
.disp
, save_str
);
6110 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
6114 /* Match the given token against cur_token. If they match, read the next
6115 token from the operand string. */
6117 intel_match_token (code
)
6120 if (cur_token
.code
== code
)
6127 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
6132 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6137 const reg_entry
*reg
;
6138 struct intel_token new_token
;
6140 new_token
.code
= T_NIL
;
6141 new_token
.reg
= NULL
;
6142 new_token
.str
= NULL
;
6144 /* Free the memory allocated to the previous token and move
6145 cur_token to prev_token. */
6147 free (prev_token
.str
);
6149 prev_token
= cur_token
;
6151 /* Skip whitespace. */
6152 while (is_space_char (*intel_parser
.op_string
))
6153 intel_parser
.op_string
++;
6155 /* Return an empty token if we find nothing else on the line. */
6156 if (*intel_parser
.op_string
== '\0')
6158 cur_token
= new_token
;
6162 /* The new token cannot be larger than the remainder of the operand
6164 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
6165 if (new_token
.str
== NULL
)
6167 new_token
.str
[0] = '\0';
6169 if (strchr ("0123456789", *intel_parser
.op_string
))
6171 char *p
= new_token
.str
;
6172 char *q
= intel_parser
.op_string
;
6173 new_token
.code
= T_CONST
;
6175 /* Allow any kind of identifier char to encompass floating point and
6176 hexadecimal numbers. */
6177 while (is_identifier_char (*q
))
6181 /* Recognize special symbol names [0-9][bf]. */
6182 if (strlen (intel_parser
.op_string
) == 2
6183 && (intel_parser
.op_string
[1] == 'b'
6184 || intel_parser
.op_string
[1] == 'f'))
6185 new_token
.code
= T_ID
;
6188 else if (strchr ("<>", *intel_parser
.op_string
)
6189 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
6191 new_token
.code
= T_SHIFTOP
;
6192 new_token
.str
[0] = *intel_parser
.op_string
;
6193 new_token
.str
[1] = *intel_parser
.op_string
;
6194 new_token
.str
[2] = '\0';
6197 else if (strchr ("+-/*&|:[]()~", *intel_parser
.op_string
))
6199 new_token
.code
= *intel_parser
.op_string
;
6200 new_token
.str
[0] = *intel_parser
.op_string
;
6201 new_token
.str
[1] = '\0';
6204 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
6205 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
6207 new_token
.code
= T_REG
;
6208 new_token
.reg
= reg
;
6210 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
6212 new_token
.str
[0] = REGISTER_PREFIX
;
6213 new_token
.str
[1] = '\0';
6216 strcat (new_token
.str
, reg
->reg_name
);
6219 else if (is_identifier_char (*intel_parser
.op_string
))
6221 char *p
= new_token
.str
;
6222 char *q
= intel_parser
.op_string
;
6224 /* A '.' or '$' followed by an identifier char is an identifier.
6225 Otherwise, it's operator '.' followed by an expression. */
6226 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
6228 new_token
.code
= *q
;
6229 new_token
.str
[0] = *q
;
6230 new_token
.str
[1] = '\0';
6234 while (is_identifier_char (*q
) || *q
== '@')
6238 if (strcasecmp (new_token
.str
, "BYTE") == 0)
6239 new_token
.code
= T_BYTE
;
6241 else if (strcasecmp (new_token
.str
, "WORD") == 0)
6242 new_token
.code
= T_WORD
;
6244 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
6245 new_token
.code
= T_DWORD
;
6247 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
6248 new_token
.code
= T_QWORD
;
6250 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
6251 new_token
.code
= T_XWORD
;
6253 else if (strcasecmp (new_token
.str
, "PTR") == 0)
6254 new_token
.code
= T_PTR
;
6256 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
6257 new_token
.code
= T_SHORT
;
6259 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
6261 new_token
.code
= T_OFFSET
;
6263 /* ??? This is not mentioned in the MASM grammar but gcc
6264 makes use of it with -mintel-syntax. OFFSET may be
6265 followed by FLAT: */
6266 if (strncasecmp (q
, " FLAT:", 6) == 0)
6267 strcat (new_token
.str
, " FLAT:");
6270 /* ??? This is not mentioned in the MASM grammar. */
6271 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
6272 new_token
.code
= T_OFFSET
;
6275 new_token
.code
= T_ID
;
6280 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
6282 intel_parser
.op_string
+= strlen (new_token
.str
);
6283 cur_token
= new_token
;
6286 /* Put cur_token back into the token stream and make cur_token point to
6289 intel_putback_token ()
6291 intel_parser
.op_string
-= strlen (cur_token
.str
);
6292 free (cur_token
.str
);
6293 cur_token
= prev_token
;
6295 /* Forget prev_token. */
6296 prev_token
.code
= T_NIL
;
6297 prev_token
.reg
= NULL
;
6298 prev_token
.str
= NULL
;
6302 tc_x86_regname_to_dw2regnum (const char *regname
)
6304 unsigned int regnum
;
6305 unsigned int regnames_count
;
6306 char *regnames_32
[] =
6308 "eax", "ecx", "edx", "ebx",
6309 "esp", "ebp", "esi", "edi",
6312 char *regnames_64
[] =
6314 "rax", "rbx", "rcx", "rdx",
6315 "rdi", "rsi", "rbp", "rsp",
6316 "r8", "r9", "r10", "r11",
6317 "r12", "r13", "r14", "r15",
6322 if (flag_code
== CODE_64BIT
)
6324 regnames
= regnames_64
;
6325 regnames_count
= ARRAY_SIZE (regnames_64
);
6329 regnames
= regnames_32
;
6330 regnames_count
= ARRAY_SIZE (regnames_32
);
6333 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
6334 if (strcmp (regname
, regnames
[regnum
]) == 0)
6341 tc_x86_frame_initial_instructions (void)
6343 static unsigned int sp_regno
;
6346 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
6349 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
6350 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
6354 i386_elf_section_type (const char *str
, size_t len
)
6356 if (flag_code
== CODE_64BIT
6357 && len
== sizeof ("unwind") - 1
6358 && strncmp (str
, "unwind", 6) == 0)
6359 return SHT_X86_64_UNWIND
;