1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c
);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry
*parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry
*build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS
*, offsetT
);
95 static void output_disp (fragS
*, offsetT
);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
103 static const char *default_arch
= DEFAULT_ARCH
;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry
*regs
;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands
;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types
[MAX_OPERANDS
];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op
[MAX_OPERANDS
];
140 /* Flags for operands. */
141 unsigned int flags
[MAX_OPERANDS
];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry
*base_reg
;
150 const reg_entry
*index_reg
;
151 unsigned int log2_scale_factor
;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry
*seg
[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes
;
160 unsigned char prefix
[MAX_PREFIXES
];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn
;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars
[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars
= "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars
= "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "#/";
212 const char line_separator_chars
[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS
[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS
[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars
[256];
225 static char register_chars
[256];
226 static char operand_chars
[256];
227 static char identifier_chars
[256];
228 static char digit_chars
[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack
[32];
246 static char *save_stack_p
;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates
*current_templates
;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
260 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
262 /* Current operand we are working on. */
263 static int this_operand
;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code
;
275 static unsigned int object_64bit
;
276 static int use_rela_relocations
= 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names
[] =
286 /* 1 for intel syntax,
288 static int intel_syntax
= 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg
= 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix
= "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size
= '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code
= 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings
= 0;
308 static const char *cpu_arch_name
= NULL
;
309 static const char *cpu_sub_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set
= 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags
= 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags
= 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion
= 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS
*GOT_symbol
;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column
;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment
;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table
[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch
[] =
423 {"generic32", PROCESSOR_GENERIC32
,
424 Cpu186
|Cpu286
|Cpu386
},
425 {"generic64", PROCESSOR_GENERIC64
,
426 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
427 |CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"i8086", PROCESSOR_UNKNOWN
,
430 {"i186", PROCESSOR_UNKNOWN
,
432 {"i286", PROCESSOR_UNKNOWN
,
434 {"i386", PROCESSOR_GENERIC32
,
435 Cpu186
|Cpu286
|Cpu386
},
436 {"i486", PROCESSOR_I486
,
437 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
438 {"i586", PROCESSOR_PENTIUM
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
440 {"i686", PROCESSOR_PENTIUMPRO
,
441 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
442 {"pentium", PROCESSOR_PENTIUM
,
443 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
445 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
446 {"pentiumii", PROCESSOR_PENTIUMPRO
,
447 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
449 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
450 {"pentium4", PROCESSOR_PENTIUM4
,
451 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
452 |CpuMMX2
|CpuSSE
|CpuSSE2
},
453 {"prescott", PROCESSOR_NOCONA
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
455 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
456 {"nocona", PROCESSOR_NOCONA
,
457 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
458 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
459 {"yonah", PROCESSOR_CORE
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
461 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
462 {"core", PROCESSOR_CORE
,
463 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
464 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
465 {"merom", PROCESSOR_CORE2
,
466 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
467 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
468 {"core2", PROCESSOR_CORE2
,
469 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
470 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
472 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
473 {"k6_2", PROCESSOR_K6
,
474 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
475 {"athlon", PROCESSOR_ATHLON
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
477 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
478 {"sledgehammer", PROCESSOR_K8
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
480 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
481 {"opteron", PROCESSOR_K8
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
483 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
486 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
487 {"amdfam10", PROCESSOR_AMDFAM10
,
488 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
489 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN
,
493 {".sse", PROCESSOR_UNKNOWN
,
494 CpuMMX
|CpuMMX2
|CpuSSE
},
495 {".sse2", PROCESSOR_UNKNOWN
,
496 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
497 {".sse3", PROCESSOR_UNKNOWN
,
498 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
499 {".ssse3", PROCESSOR_UNKNOWN
,
500 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
501 {".sse4.1", PROCESSOR_UNKNOWN
,
502 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4_1
},
503 {".sse4.2", PROCESSOR_UNKNOWN
,
504 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
505 {".sse4", PROCESSOR_UNKNOWN
,
506 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
507 {".3dnow", PROCESSOR_UNKNOWN
,
509 {".3dnowa", PROCESSOR_UNKNOWN
,
510 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
511 {".padlock", PROCESSOR_UNKNOWN
,
513 {".pacifica", PROCESSOR_UNKNOWN
,
515 {".svme", PROCESSOR_UNKNOWN
,
517 {".sse4a", PROCESSOR_UNKNOWN
,
518 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
519 {".abm", PROCESSOR_UNKNOWN
,
523 const pseudo_typeS md_pseudo_table
[] =
525 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes
, 0},
528 {"align", s_align_ptwo
, 0},
530 {"arch", set_cpu_arch
, 0},
534 {"ffloat", float_cons
, 'f'},
535 {"dfloat", float_cons
, 'd'},
536 {"tfloat", float_cons
, 'x'},
538 {"slong", signed_cons
, 4},
539 {"noopt", s_ignore
, 0},
540 {"optim", s_ignore
, 0},
541 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
542 {"code16", set_code_flag
, CODE_16BIT
},
543 {"code32", set_code_flag
, CODE_32BIT
},
544 {"code64", set_code_flag
, CODE_64BIT
},
545 {"intel_syntax", set_intel_syntax
, 1},
546 {"att_syntax", set_intel_syntax
, 0},
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common
, 0},
550 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
551 {"loc", dwarf2_directive_loc
, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
555 {"secrel32", pe_directive_secrel
, 0},
560 /* For interface with expression (). */
561 extern char *input_line_pointer
;
563 /* Hash table for instruction mnemonic lookup. */
564 static struct hash_control
*op_hash
;
566 /* Hash table for register lookup. */
567 static struct hash_control
*reg_hash
;
570 i386_align_code (fragS
*fragP
, int count
)
572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
575 static const char f32_1
[] =
577 static const char f32_2
[] =
578 {0x66,0x90}; /* xchg %ax,%ax */
579 static const char f32_3
[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4
[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5
[] =
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6
[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7
[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8
[] =
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9
[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10
[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11
[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12
[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13
[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14
[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_15
[] =
612 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
613 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
614 static const char f16_3
[] =
615 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
616 static const char f16_4
[] =
617 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_5
[] =
620 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
621 static const char f16_6
[] =
622 {0x89,0xf6, /* mov %si,%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_7
[] =
625 {0x8d,0x74,0x00, /* lea 0(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char f16_8
[] =
628 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
629 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
630 static const char *const f32_patt
[] = {
631 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
632 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
634 static const char *const f16_patt
[] = {
635 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
636 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
639 static const char alt_3
[] =
641 /* nopl 0(%[re]ax) */
642 static const char alt_4
[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5
[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6
[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7
[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8
[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9
[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10
[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11
[] =
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12
[] =
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13
[] =
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14
[] =
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15
[] =
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11
[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12
[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
719 static const char alt_short_13
[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
724 static const char alt_short_14
[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15
[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt
[] = {
733 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
734 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
735 alt_short_14
, alt_short_15
737 static const char *const alt_long_patt
[] = {
738 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
739 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
740 alt_long_14
, alt_long_15
743 if (count
<= 0 || count
> 15)
746 /* We need to decide which NOP sequence to use for 32bit and
747 64bit. When -mtune= is used:
749 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
750 f32_patt will be used.
751 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
752 0x66 prefix will be used.
753 3. For PROCESSOR_CORE2, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
764 if (flag_code
== CODE_16BIT
)
766 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
767 f16_patt
[count
- 1], count
);
769 /* Adjust jump offset. */
770 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
772 else if (flag_code
== CODE_64BIT
&& cpu_arch_tune
== PROCESSOR_K8
)
775 int nnops
= (count
+ 3) / 4;
776 int len
= count
/ nnops
;
777 int remains
= count
- nnops
* len
;
780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
782 for (i
= 0; i
< remains
; i
++)
784 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
);
785 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
] = 0x90;
788 for (; i
< nnops
; i
++)
790 memset (fragP
->fr_literal
+ fragP
->fr_fix
+ pos
, 0x66, len
- 1);
791 fragP
->fr_literal
[fragP
->fr_fix
+ pos
+ len
- 1] = 0x90;
797 const char *const *patt
= NULL
;
799 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune
)
804 case PROCESSOR_UNKNOWN
:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
808 patt
= alt_short_patt
;
812 case PROCESSOR_CORE2
:
813 patt
= alt_long_patt
;
815 case PROCESSOR_PENTIUMPRO
:
816 case PROCESSOR_PENTIUM4
:
817 case PROCESSOR_NOCONA
:
820 case PROCESSOR_ATHLON
:
822 case PROCESSOR_GENERIC64
:
823 case PROCESSOR_AMDFAM10
:
824 patt
= alt_short_patt
;
827 case PROCESSOR_PENTIUM
:
828 case PROCESSOR_GENERIC32
:
835 switch (cpu_arch_tune
)
837 case PROCESSOR_UNKNOWN
:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
844 case PROCESSOR_PENTIUM
:
845 case PROCESSOR_PENTIUMPRO
:
846 case PROCESSOR_PENTIUM4
:
847 case PROCESSOR_NOCONA
:
850 case PROCESSOR_ATHLON
:
852 case PROCESSOR_AMDFAM10
:
853 case PROCESSOR_GENERIC32
:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
856 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
857 patt
= alt_short_patt
;
861 case PROCESSOR_CORE2
:
862 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
863 patt
= alt_long_patt
;
867 case PROCESSOR_GENERIC64
:
868 patt
= alt_short_patt
;
873 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
874 patt
[count
- 1], count
);
876 fragP
->fr_var
= count
;
879 static INLINE
unsigned int
880 mode_from_disp_size (unsigned int t
)
882 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
886 fits_in_signed_byte (offsetT num
)
888 return (num
>= -128) && (num
<= 127);
892 fits_in_unsigned_byte (offsetT num
)
894 return (num
& 0xff) == num
;
898 fits_in_unsigned_word (offsetT num
)
900 return (num
& 0xffff) == num
;
904 fits_in_signed_word (offsetT num
)
906 return (-32768 <= num
) && (num
<= 32767);
910 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
915 return (!(((offsetT
) -1 << 31) & num
)
916 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
918 } /* fits_in_signed_long() */
921 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
926 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
928 } /* fits_in_unsigned_long() */
931 smallest_imm_type (offsetT num
)
933 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
935 /* This code is disabled on the 486 because all the Imm1 forms
936 in the opcode table are slower on the i486. They're the
937 versions with the implicitly specified single-position
938 displacement, which has another syntax if you really want to
941 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
943 return (fits_in_signed_byte (num
)
944 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
945 : fits_in_unsigned_byte (num
)
946 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
947 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
948 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
949 : fits_in_signed_long (num
)
950 ? (Imm32
| Imm32S
| Imm64
)
951 : fits_in_unsigned_long (num
)
957 offset_in_range (offsetT val
, int size
)
963 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
964 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
965 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
967 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
972 /* If BFD64, sign extend val. */
973 if (!use_rela_relocations
)
974 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
975 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
977 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
979 char buf1
[40], buf2
[40];
981 sprint_value (buf1
, val
);
982 sprint_value (buf2
, val
& mask
);
983 as_warn (_("%s shortened to %s"), buf1
, buf2
);
988 /* Returns 0 if attempting to add a prefix where one from the same
989 class already exists, 1 if non rep/repne added, 2 if rep/repne
992 add_prefix (unsigned int prefix
)
997 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
998 && flag_code
== CODE_64BIT
)
1000 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1001 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1002 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1013 case CS_PREFIX_OPCODE
:
1014 case DS_PREFIX_OPCODE
:
1015 case ES_PREFIX_OPCODE
:
1016 case FS_PREFIX_OPCODE
:
1017 case GS_PREFIX_OPCODE
:
1018 case SS_PREFIX_OPCODE
:
1022 case REPNE_PREFIX_OPCODE
:
1023 case REPE_PREFIX_OPCODE
:
1026 case LOCK_PREFIX_OPCODE
:
1034 case ADDR_PREFIX_OPCODE
:
1038 case DATA_PREFIX_OPCODE
:
1042 if (i
.prefix
[q
] != 0)
1050 i
.prefix
[q
] |= prefix
;
1053 as_bad (_("same type of prefix used twice"));
1059 set_code_flag (int value
)
1062 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1063 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1064 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1066 as_bad (_("64bit mode not supported on this CPU."));
1068 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1070 as_bad (_("32bit mode not supported on this CPU."));
1072 stackop_size
= '\0';
1076 set_16bit_gcc_code_flag (int new_code_flag
)
1078 flag_code
= new_code_flag
;
1079 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1080 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1081 stackop_size
= LONG_MNEM_SUFFIX
;
1085 set_intel_syntax (int syntax_flag
)
1087 /* Find out if register prefixing is specified. */
1088 int ask_naked_reg
= 0;
1091 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1093 char *string
= input_line_pointer
;
1094 int e
= get_symbol_end ();
1096 if (strcmp (string
, "prefix") == 0)
1098 else if (strcmp (string
, "noprefix") == 0)
1101 as_bad (_("bad argument to syntax directive."));
1102 *input_line_pointer
= e
;
1104 demand_empty_rest_of_line ();
1106 intel_syntax
= syntax_flag
;
1108 if (ask_naked_reg
== 0)
1109 allow_naked_reg
= (intel_syntax
1110 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1112 allow_naked_reg
= (ask_naked_reg
< 0);
1114 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1115 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1116 register_prefix
= allow_naked_reg
? "" : "%";
1120 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1124 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1126 char *string
= input_line_pointer
;
1127 int e
= get_symbol_end ();
1130 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1132 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1136 cpu_arch_name
= cpu_arch
[i
].name
;
1137 cpu_sub_arch_name
= NULL
;
1138 cpu_arch_flags
= (cpu_arch
[i
].flags
1139 | (flag_code
== CODE_64BIT
1140 ? Cpu64
: CpuNo64
));
1141 cpu_arch_isa
= cpu_arch
[i
].type
;
1142 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1143 if (!cpu_arch_tune_set
)
1145 cpu_arch_tune
= cpu_arch_isa
;
1146 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1150 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1152 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1153 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1155 *input_line_pointer
= e
;
1156 demand_empty_rest_of_line ();
1160 if (i
>= ARRAY_SIZE (cpu_arch
))
1161 as_bad (_("no such architecture: `%s'"), string
);
1163 *input_line_pointer
= e
;
1166 as_bad (_("missing cpu architecture"));
1168 no_cond_jump_promotion
= 0;
1169 if (*input_line_pointer
== ','
1170 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1172 char *string
= ++input_line_pointer
;
1173 int e
= get_symbol_end ();
1175 if (strcmp (string
, "nojumps") == 0)
1176 no_cond_jump_promotion
= 1;
1177 else if (strcmp (string
, "jumps") == 0)
1180 as_bad (_("no such architecture modifier: `%s'"), string
);
1182 *input_line_pointer
= e
;
1185 demand_empty_rest_of_line ();
1191 if (!strcmp (default_arch
, "x86_64"))
1192 return bfd_mach_x86_64
;
1193 else if (!strcmp (default_arch
, "i386"))
1194 return bfd_mach_i386_i386
;
1196 as_fatal (_("Unknown architecture"));
1202 const char *hash_err
;
1204 /* Initialize op_hash hash table. */
1205 op_hash
= hash_new ();
1208 const template *optab
;
1209 templates
*core_optab
;
1211 /* Setup for loop. */
1213 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1214 core_optab
->start
= optab
;
1219 if (optab
->name
== NULL
1220 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1222 /* different name --> ship out current template list;
1223 add to hash table; & begin anew. */
1224 core_optab
->end
= optab
;
1225 hash_err
= hash_insert (op_hash
,
1230 as_fatal (_("Internal Error: Can't hash %s: %s"),
1234 if (optab
->name
== NULL
)
1236 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1237 core_optab
->start
= optab
;
1242 /* Initialize reg_hash hash table. */
1243 reg_hash
= hash_new ();
1245 const reg_entry
*regtab
;
1246 unsigned int regtab_size
= i386_regtab_size
;
1248 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1250 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1258 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1263 for (c
= 0; c
< 256; c
++)
1268 mnemonic_chars
[c
] = c
;
1269 register_chars
[c
] = c
;
1270 operand_chars
[c
] = c
;
1272 else if (ISLOWER (c
))
1274 mnemonic_chars
[c
] = c
;
1275 register_chars
[c
] = c
;
1276 operand_chars
[c
] = c
;
1278 else if (ISUPPER (c
))
1280 mnemonic_chars
[c
] = TOLOWER (c
);
1281 register_chars
[c
] = mnemonic_chars
[c
];
1282 operand_chars
[c
] = c
;
1285 if (ISALPHA (c
) || ISDIGIT (c
))
1286 identifier_chars
[c
] = c
;
1289 identifier_chars
[c
] = c
;
1290 operand_chars
[c
] = c
;
1295 identifier_chars
['@'] = '@';
1298 identifier_chars
['?'] = '?';
1299 operand_chars
['?'] = '?';
1301 digit_chars
['-'] = '-';
1302 mnemonic_chars
['-'] = '-';
1303 mnemonic_chars
['.'] = '.';
1304 identifier_chars
['_'] = '_';
1305 identifier_chars
['.'] = '.';
1307 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1308 operand_chars
[(unsigned char) *p
] = *p
;
1311 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1314 record_alignment (text_section
, 2);
1315 record_alignment (data_section
, 2);
1316 record_alignment (bss_section
, 2);
1320 if (flag_code
== CODE_64BIT
)
1322 x86_dwarf2_return_column
= 16;
1323 x86_cie_data_alignment
= -8;
1327 x86_dwarf2_return_column
= 8;
1328 x86_cie_data_alignment
= -4;
1333 i386_print_statistics (FILE *file
)
1335 hash_print_statistics (file
, "i386 opcode", op_hash
);
1336 hash_print_statistics (file
, "i386 register", reg_hash
);
1341 /* Debugging routines for md_assemble. */
1342 static void pte (template *);
1343 static void pt (unsigned int);
1344 static void pe (expressionS
*);
1345 static void ps (symbolS
*);
1348 pi (char *line
, i386_insn
*x
)
1352 fprintf (stdout
, "%s: template ", line
);
1354 fprintf (stdout
, " address: base %s index %s scale %x\n",
1355 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1356 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1357 x
->log2_scale_factor
);
1358 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1359 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1360 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1361 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1362 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1363 (x
->rex
& REX_W
) != 0,
1364 (x
->rex
& REX_R
) != 0,
1365 (x
->rex
& REX_X
) != 0,
1366 (x
->rex
& REX_B
) != 0);
1367 for (i
= 0; i
< x
->operands
; i
++)
1369 fprintf (stdout
, " #%d: ", i
+ 1);
1371 fprintf (stdout
, "\n");
1373 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1374 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1375 if (x
->types
[i
] & Imm
)
1377 if (x
->types
[i
] & Disp
)
1378 pe (x
->op
[i
].disps
);
1386 fprintf (stdout
, " %d operands ", t
->operands
);
1387 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1388 if (t
->extension_opcode
!= None
)
1389 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1390 if (t
->opcode_modifier
& D
)
1391 fprintf (stdout
, "D");
1392 if (t
->opcode_modifier
& W
)
1393 fprintf (stdout
, "W");
1394 fprintf (stdout
, "\n");
1395 for (i
= 0; i
< t
->operands
; i
++)
1397 fprintf (stdout
, " #%d type ", i
+ 1);
1398 pt (t
->operand_types
[i
]);
1399 fprintf (stdout
, "\n");
1406 fprintf (stdout
, " operation %d\n", e
->X_op
);
1407 fprintf (stdout
, " add_number %ld (%lx)\n",
1408 (long) e
->X_add_number
, (long) e
->X_add_number
);
1409 if (e
->X_add_symbol
)
1411 fprintf (stdout
, " add_symbol ");
1412 ps (e
->X_add_symbol
);
1413 fprintf (stdout
, "\n");
1417 fprintf (stdout
, " op_symbol ");
1418 ps (e
->X_op_symbol
);
1419 fprintf (stdout
, "\n");
1426 fprintf (stdout
, "%s type %s%s",
1428 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1429 segment_name (S_GET_SEGMENT (s
)));
1432 static struct type_name
1437 const type_names
[] =
1450 { BaseIndex
, "BaseIndex" },
1454 { Disp32S
, "d32s" },
1456 { InOutPortReg
, "InOutPortReg" },
1457 { ShiftCount
, "ShiftCount" },
1458 { Control
, "control reg" },
1459 { Test
, "test reg" },
1460 { Debug
, "debug reg" },
1461 { FloatReg
, "FReg" },
1462 { FloatAcc
, "FAcc" },
1466 { JumpAbsolute
, "Jump Absolute" },
1477 const struct type_name
*ty
;
1479 for (ty
= type_names
; ty
->mask
; ty
++)
1481 fprintf (stdout
, "%s, ", ty
->tname
);
1485 #endif /* DEBUG386 */
1487 static bfd_reloc_code_real_type
1488 reloc (unsigned int size
,
1491 bfd_reloc_code_real_type other
)
1493 if (other
!= NO_RELOC
)
1495 reloc_howto_type
*reloc
;
1500 case BFD_RELOC_X86_64_GOT32
:
1501 return BFD_RELOC_X86_64_GOT64
;
1503 case BFD_RELOC_X86_64_PLTOFF64
:
1504 return BFD_RELOC_X86_64_PLTOFF64
;
1506 case BFD_RELOC_X86_64_GOTPC32
:
1507 other
= BFD_RELOC_X86_64_GOTPC64
;
1509 case BFD_RELOC_X86_64_GOTPCREL
:
1510 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1512 case BFD_RELOC_X86_64_TPOFF32
:
1513 other
= BFD_RELOC_X86_64_TPOFF64
;
1515 case BFD_RELOC_X86_64_DTPOFF32
:
1516 other
= BFD_RELOC_X86_64_DTPOFF64
;
1522 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1523 if (size
== 4 && flag_code
!= CODE_64BIT
)
1526 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1528 as_bad (_("unknown relocation (%u)"), other
);
1529 else if (size
!= bfd_get_reloc_size (reloc
))
1530 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1531 bfd_get_reloc_size (reloc
),
1533 else if (pcrel
&& !reloc
->pc_relative
)
1534 as_bad (_("non-pc-relative relocation for pc-relative field"));
1535 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1537 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1539 as_bad (_("relocated field and relocation type differ in signedness"));
1548 as_bad (_("there are no unsigned pc-relative relocations"));
1551 case 1: return BFD_RELOC_8_PCREL
;
1552 case 2: return BFD_RELOC_16_PCREL
;
1553 case 4: return BFD_RELOC_32_PCREL
;
1554 case 8: return BFD_RELOC_64_PCREL
;
1556 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1563 case 4: return BFD_RELOC_X86_64_32S
;
1568 case 1: return BFD_RELOC_8
;
1569 case 2: return BFD_RELOC_16
;
1570 case 4: return BFD_RELOC_32
;
1571 case 8: return BFD_RELOC_64
;
1573 as_bad (_("cannot do %s %u byte relocation"),
1574 sign
> 0 ? "signed" : "unsigned", size
);
1578 return BFD_RELOC_NONE
;
1581 /* Here we decide which fixups can be adjusted to make them relative to
1582 the beginning of the section instead of the symbol. Basically we need
1583 to make sure that the dynamic relocations are done correctly, so in
1584 some cases we force the original symbol to be used. */
1587 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1593 /* Don't adjust pc-relative references to merge sections in 64-bit
1595 if (use_rela_relocations
1596 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1600 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1601 and changed later by validate_fix. */
1602 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1603 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1606 /* adjust_reloc_syms doesn't know about the GOT. */
1607 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1608 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1609 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1610 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1611 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1612 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1613 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1614 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1615 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1616 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1617 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1618 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1619 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1622 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1623 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1624 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1625 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1626 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1627 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1628 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1629 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1630 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1631 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1632 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1633 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1634 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1641 intel_float_operand (const char *mnemonic
)
1643 /* Note that the value returned is meaningful only for opcodes with (memory)
1644 operands, hence the code here is free to improperly handle opcodes that
1645 have no operands (for better performance and smaller code). */
1647 if (mnemonic
[0] != 'f')
1648 return 0; /* non-math */
1650 switch (mnemonic
[1])
1652 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1653 the fs segment override prefix not currently handled because no
1654 call path can make opcodes without operands get here */
1656 return 2 /* integer op */;
1658 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1659 return 3; /* fldcw/fldenv */
1662 if (mnemonic
[2] != 'o' /* fnop */)
1663 return 3; /* non-waiting control op */
1666 if (mnemonic
[2] == 's')
1667 return 3; /* frstor/frstpm */
1670 if (mnemonic
[2] == 'a')
1671 return 3; /* fsave */
1672 if (mnemonic
[2] == 't')
1674 switch (mnemonic
[3])
1676 case 'c': /* fstcw */
1677 case 'd': /* fstdw */
1678 case 'e': /* fstenv */
1679 case 's': /* fsts[gw] */
1685 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1686 return 0; /* fxsave/fxrstor are not really math ops */
1693 /* This is the guts of the machine-dependent assembler. LINE points to a
1694 machine dependent instruction. This function is supposed to emit
1695 the frags/bytes it assembles to. */
1702 char mnemonic
[MAX_MNEM_SIZE
];
1704 /* Initialize globals. */
1705 memset (&i
, '\0', sizeof (i
));
1706 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1707 i
.reloc
[j
] = NO_RELOC
;
1708 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1709 memset (im_expressions
, '\0', sizeof (im_expressions
));
1710 save_stack_p
= save_stack
;
1712 /* First parse an instruction mnemonic & call i386_operand for the operands.
1713 We assume that the scrubber has arranged it so that line[0] is the valid
1714 start of a (possibly prefixed) mnemonic. */
1716 line
= parse_insn (line
, mnemonic
);
1720 line
= parse_operands (line
, mnemonic
);
1724 /* The order of the immediates should be reversed
1725 for 2 immediates extrq and insertq instructions */
1726 if ((i
.imm_operands
== 2)
1727 && ((strcmp (mnemonic
, "extrq") == 0)
1728 || (strcmp (mnemonic
, "insertq") == 0)))
1730 swap_2_operands (0, 1);
1731 /* "extrq" and insertq" are the only two instructions whose operands
1732 have to be reversed even though they have two immediate operands.
1738 /* Now we've parsed the mnemonic into a set of templates, and have the
1739 operands at hand. */
1741 /* All intel opcodes have reversed operands except for "bound" and
1742 "enter". We also don't reverse intersegment "jmp" and "call"
1743 instructions with 2 immediate operands so that the immediate segment
1744 precedes the offset, as it does when in AT&T mode. */
1747 && (strcmp (mnemonic
, "bound") != 0)
1748 && (strcmp (mnemonic
, "invlpga") != 0)
1749 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1755 /* Don't optimize displacement for movabs since it only takes 64bit
1758 && (flag_code
!= CODE_64BIT
1759 || strcmp (mnemonic
, "movabs") != 0))
1762 /* Next, we find a template that matches the given insn,
1763 making sure the overlap of the given operands types is consistent
1764 with the template operand types. */
1766 if (!match_template ())
1771 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1773 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1774 i
.tm
.base_opcode
^= Opcode_FloatR
;
1776 /* Zap movzx and movsx suffix. The suffix may have been set from
1777 "word ptr" or "byte ptr" on the source operand, but we'll use
1778 the suffix later to choose the destination register. */
1779 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1781 if (i
.reg_operands
< 2
1783 && (~i
.tm
.opcode_modifier
1790 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1796 if (i
.tm
.opcode_modifier
& FWait
)
1797 if (!add_prefix (FWAIT_OPCODE
))
1800 /* Check string instruction segment overrides. */
1801 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1803 if (!check_string ())
1807 if (!process_suffix ())
1810 /* Make still unresolved immediate matches conform to size of immediate
1811 given in i.suffix. */
1812 if (!finalize_imm ())
1815 if (i
.types
[0] & Imm1
)
1816 i
.imm_operands
= 0; /* kludge for shift insns. */
1817 if (i
.types
[0] & ImplicitRegister
)
1819 if (i
.types
[1] & ImplicitRegister
)
1821 if (i
.types
[2] & ImplicitRegister
)
1824 if (i
.tm
.opcode_modifier
& ImmExt
)
1828 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1830 /* Streaming SIMD extensions 3 Instructions have the fixed
1831 operands with an opcode suffix which is coded in the same
1832 place as an 8-bit immediate field would be. Here we check
1833 those operands and remove them afterwards. */
1836 for (x
= 0; x
< i
.operands
; x
++)
1837 if (i
.op
[x
].regs
->reg_num
!= x
)
1838 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1840 i
.op
[x
].regs
->reg_name
,
1846 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1847 opcode suffix which is coded in the same place as an 8-bit
1848 immediate field would be. Here we fake an 8-bit immediate
1849 operand from the opcode suffix stored in tm.extension_opcode. */
1851 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1853 exp
= &im_expressions
[i
.imm_operands
++];
1854 i
.op
[i
.operands
].imms
= exp
;
1855 i
.types
[i
.operands
++] = Imm8
;
1856 exp
->X_op
= O_constant
;
1857 exp
->X_add_number
= i
.tm
.extension_opcode
;
1858 i
.tm
.extension_opcode
= None
;
1861 /* For insns with operands there are more diddles to do to the opcode. */
1864 if (!process_operands ())
1867 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1869 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1870 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1873 /* Handle conversion of 'int $3' --> special int3 insn. */
1874 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1876 i
.tm
.base_opcode
= INT3_OPCODE
;
1880 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1881 && i
.op
[0].disps
->X_op
== O_constant
)
1883 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1884 the absolute address given by the constant. Since ix86 jumps and
1885 calls are pc relative, we need to generate a reloc. */
1886 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1887 i
.op
[0].disps
->X_op
= O_symbol
;
1890 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1893 /* For 8 bit registers we need an empty rex prefix. Also if the
1894 instruction already has a prefix, we need to convert old
1895 registers to new ones. */
1897 if (((i
.types
[0] & Reg8
) != 0
1898 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1899 || ((i
.types
[1] & Reg8
) != 0
1900 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1901 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1906 i
.rex
|= REX_OPCODE
;
1907 for (x
= 0; x
< 2; x
++)
1909 /* Look for 8 bit operand that uses old registers. */
1910 if ((i
.types
[x
] & Reg8
) != 0
1911 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1913 /* In case it is "hi" register, give up. */
1914 if (i
.op
[x
].regs
->reg_num
> 3)
1915 as_bad (_("can't encode register '%s%s' in an "
1916 "instruction requiring REX prefix."),
1917 register_prefix
, i
.op
[x
].regs
->reg_name
);
1919 /* Otherwise it is equivalent to the extended register.
1920 Since the encoding doesn't change this is merely
1921 cosmetic cleanup for debug output. */
1923 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1929 add_prefix (REX_OPCODE
| i
.rex
);
1931 /* We are ready to output the insn. */
1936 parse_insn (char *line
, char *mnemonic
)
1939 char *token_start
= l
;
1944 /* Non-zero if we found a prefix only acceptable with string insns. */
1945 const char *expecting_string_instruction
= NULL
;
1950 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1953 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1955 as_bad (_("no such instruction: `%s'"), token_start
);
1960 if (!is_space_char (*l
)
1961 && *l
!= END_OF_INSN
1963 || (*l
!= PREFIX_SEPARATOR
1966 as_bad (_("invalid character %s in mnemonic"),
1967 output_invalid (*l
));
1970 if (token_start
== l
)
1972 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1973 as_bad (_("expecting prefix; got nothing"));
1975 as_bad (_("expecting mnemonic; got nothing"));
1979 /* Look up instruction (or prefix) via hash table. */
1980 current_templates
= hash_find (op_hash
, mnemonic
);
1982 if (*l
!= END_OF_INSN
1983 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
1984 && current_templates
1985 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1987 if (current_templates
->start
->cpu_flags
1988 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
1990 as_bad ((flag_code
!= CODE_64BIT
1991 ? _("`%s' is only supported in 64-bit mode")
1992 : _("`%s' is not supported in 64-bit mode")),
1993 current_templates
->start
->name
);
1996 /* If we are in 16-bit mode, do not allow addr16 or data16.
1997 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1998 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1999 && flag_code
!= CODE_64BIT
2000 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
2001 ^ (flag_code
== CODE_16BIT
)))
2003 as_bad (_("redundant %s prefix"),
2004 current_templates
->start
->name
);
2007 /* Add prefix, checking for repeated prefixes. */
2008 switch (add_prefix (current_templates
->start
->base_opcode
))
2013 expecting_string_instruction
= current_templates
->start
->name
;
2016 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2023 if (!current_templates
)
2025 /* See if we can get a match by trimming off a suffix. */
2028 case WORD_MNEM_SUFFIX
:
2029 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2030 i
.suffix
= SHORT_MNEM_SUFFIX
;
2032 case BYTE_MNEM_SUFFIX
:
2033 case QWORD_MNEM_SUFFIX
:
2034 i
.suffix
= mnem_p
[-1];
2036 current_templates
= hash_find (op_hash
, mnemonic
);
2038 case SHORT_MNEM_SUFFIX
:
2039 case LONG_MNEM_SUFFIX
:
2042 i
.suffix
= mnem_p
[-1];
2044 current_templates
= hash_find (op_hash
, mnemonic
);
2052 if (intel_float_operand (mnemonic
) == 1)
2053 i
.suffix
= SHORT_MNEM_SUFFIX
;
2055 i
.suffix
= LONG_MNEM_SUFFIX
;
2057 current_templates
= hash_find (op_hash
, mnemonic
);
2061 if (!current_templates
)
2063 as_bad (_("no such instruction: `%s'"), token_start
);
2068 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2070 /* Check for a branch hint. We allow ",pt" and ",pn" for
2071 predict taken and predict not taken respectively.
2072 I'm not sure that branch hints actually do anything on loop
2073 and jcxz insns (JumpByte) for current Pentium4 chips. They
2074 may work in the future and it doesn't hurt to accept them
2076 if (l
[0] == ',' && l
[1] == 'p')
2080 if (!add_prefix (DS_PREFIX_OPCODE
))
2084 else if (l
[2] == 'n')
2086 if (!add_prefix (CS_PREFIX_OPCODE
))
2092 /* Any other comma loses. */
2095 as_bad (_("invalid character %s in mnemonic"),
2096 output_invalid (*l
));
2100 /* Check if instruction is supported on specified architecture. */
2102 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2104 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2105 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2107 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2110 if (!(supported
& 2))
2112 as_bad (flag_code
== CODE_64BIT
2113 ? _("`%s' is not supported in 64-bit mode")
2114 : _("`%s' is only supported in 64-bit mode"),
2115 current_templates
->start
->name
);
2118 if (!(supported
& 1))
2120 as_warn (_("`%s' is not supported on `%s%s'"),
2121 current_templates
->start
->name
,
2123 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2125 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2127 as_warn (_("use .code16 to ensure correct addressing mode"));
2130 /* Check for rep/repne without a string instruction. */
2131 if (expecting_string_instruction
)
2133 static templates override
;
2135 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2136 if (t
->opcode_modifier
& IsString
)
2138 if (t
>= current_templates
->end
)
2140 as_bad (_("expecting string instruction after `%s'"),
2141 expecting_string_instruction
);
2144 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2145 if (!(t
->opcode_modifier
& IsString
))
2148 current_templates
= &override
;
2155 parse_operands (char *l
, const char *mnemonic
)
2159 /* 1 if operand is pending after ','. */
2160 unsigned int expecting_operand
= 0;
2162 /* Non-zero if operand parens not balanced. */
2163 unsigned int paren_not_balanced
;
2165 while (*l
!= END_OF_INSN
)
2167 /* Skip optional white space before operand. */
2168 if (is_space_char (*l
))
2170 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2172 as_bad (_("invalid character %s before operand %d"),
2173 output_invalid (*l
),
2177 token_start
= l
; /* after white space */
2178 paren_not_balanced
= 0;
2179 while (paren_not_balanced
|| *l
!= ',')
2181 if (*l
== END_OF_INSN
)
2183 if (paren_not_balanced
)
2186 as_bad (_("unbalanced parenthesis in operand %d."),
2189 as_bad (_("unbalanced brackets in operand %d."),
2194 break; /* we are done */
2196 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2198 as_bad (_("invalid character %s in operand %d"),
2199 output_invalid (*l
),
2206 ++paren_not_balanced
;
2208 --paren_not_balanced
;
2213 ++paren_not_balanced
;
2215 --paren_not_balanced
;
2219 if (l
!= token_start
)
2220 { /* Yes, we've read in another operand. */
2221 unsigned int operand_ok
;
2222 this_operand
= i
.operands
++;
2223 if (i
.operands
> MAX_OPERANDS
)
2225 as_bad (_("spurious operands; (%d operands/instruction max)"),
2229 /* Now parse operand adding info to 'i' as we go along. */
2230 END_STRING_AND_SAVE (l
);
2234 i386_intel_operand (token_start
,
2235 intel_float_operand (mnemonic
));
2237 operand_ok
= i386_operand (token_start
);
2239 RESTORE_END_STRING (l
);
2245 if (expecting_operand
)
2247 expecting_operand_after_comma
:
2248 as_bad (_("expecting operand after ','; got nothing"));
2253 as_bad (_("expecting operand before ','; got nothing"));
2258 /* Now *l must be either ',' or END_OF_INSN. */
2261 if (*++l
== END_OF_INSN
)
2263 /* Just skip it, if it's \n complain. */
2264 goto expecting_operand_after_comma
;
2266 expecting_operand
= 1;
2273 swap_2_operands (int xchg1
, int xchg2
)
2275 union i386_op temp_op
;
2276 unsigned int temp_type
;
2277 enum bfd_reloc_code_real temp_reloc
;
2279 temp_type
= i
.types
[xchg2
];
2280 i
.types
[xchg2
] = i
.types
[xchg1
];
2281 i
.types
[xchg1
] = temp_type
;
2282 temp_op
= i
.op
[xchg2
];
2283 i
.op
[xchg2
] = i
.op
[xchg1
];
2284 i
.op
[xchg1
] = temp_op
;
2285 temp_reloc
= i
.reloc
[xchg2
];
2286 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2287 i
.reloc
[xchg1
] = temp_reloc
;
2291 swap_operands (void)
2296 swap_2_operands (1, i
.operands
- 2);
2299 swap_2_operands (0, i
.operands
- 1);
2305 if (i
.mem_operands
== 2)
2307 const seg_entry
*temp_seg
;
2308 temp_seg
= i
.seg
[0];
2309 i
.seg
[0] = i
.seg
[1];
2310 i
.seg
[1] = temp_seg
;
2314 /* Try to ensure constant immediates are represented in the smallest
2319 char guess_suffix
= 0;
2323 guess_suffix
= i
.suffix
;
2324 else if (i
.reg_operands
)
2326 /* Figure out a suffix from the last register operand specified.
2327 We can't do this properly yet, ie. excluding InOutPortReg,
2328 but the following works for instructions with immediates.
2329 In any case, we can't set i.suffix yet. */
2330 for (op
= i
.operands
; --op
>= 0;)
2331 if (i
.types
[op
] & Reg
)
2333 if (i
.types
[op
] & Reg8
)
2334 guess_suffix
= BYTE_MNEM_SUFFIX
;
2335 else if (i
.types
[op
] & Reg16
)
2336 guess_suffix
= WORD_MNEM_SUFFIX
;
2337 else if (i
.types
[op
] & Reg32
)
2338 guess_suffix
= LONG_MNEM_SUFFIX
;
2339 else if (i
.types
[op
] & Reg64
)
2340 guess_suffix
= QWORD_MNEM_SUFFIX
;
2344 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2345 guess_suffix
= WORD_MNEM_SUFFIX
;
2347 for (op
= i
.operands
; --op
>= 0;)
2348 if (i
.types
[op
] & Imm
)
2350 switch (i
.op
[op
].imms
->X_op
)
2353 /* If a suffix is given, this operand may be shortened. */
2354 switch (guess_suffix
)
2356 case LONG_MNEM_SUFFIX
:
2357 i
.types
[op
] |= Imm32
| Imm64
;
2359 case WORD_MNEM_SUFFIX
:
2360 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2362 case BYTE_MNEM_SUFFIX
:
2363 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2367 /* If this operand is at most 16 bits, convert it
2368 to a signed 16 bit number before trying to see
2369 whether it will fit in an even smaller size.
2370 This allows a 16-bit operand such as $0xffe0 to
2371 be recognised as within Imm8S range. */
2372 if ((i
.types
[op
] & Imm16
)
2373 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2375 i
.op
[op
].imms
->X_add_number
=
2376 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2378 if ((i
.types
[op
] & Imm32
)
2379 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2382 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2383 ^ ((offsetT
) 1 << 31))
2384 - ((offsetT
) 1 << 31));
2386 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2388 /* We must avoid matching of Imm32 templates when 64bit
2389 only immediate is available. */
2390 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2391 i
.types
[op
] &= ~Imm32
;
2398 /* Symbols and expressions. */
2400 /* Convert symbolic operand to proper sizes for matching, but don't
2401 prevent matching a set of insns that only supports sizes other
2402 than those matching the insn suffix. */
2404 unsigned int mask
, allowed
= 0;
2407 for (t
= current_templates
->start
;
2408 t
< current_templates
->end
;
2410 allowed
|= t
->operand_types
[op
];
2411 switch (guess_suffix
)
2413 case QWORD_MNEM_SUFFIX
:
2414 mask
= Imm64
| Imm32S
;
2416 case LONG_MNEM_SUFFIX
:
2419 case WORD_MNEM_SUFFIX
:
2422 case BYTE_MNEM_SUFFIX
:
2430 i
.types
[op
] &= mask
;
2437 /* Try to use the smallest displacement type too. */
2439 optimize_disp (void)
2443 for (op
= i
.operands
; --op
>= 0;)
2444 if (i
.types
[op
] & Disp
)
2446 if (i
.op
[op
].disps
->X_op
== O_constant
)
2448 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2450 if ((i
.types
[op
] & Disp16
)
2451 && (disp
& ~(offsetT
) 0xffff) == 0)
2453 /* If this operand is at most 16 bits, convert
2454 to a signed 16 bit number and don't use 64bit
2456 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2457 i
.types
[op
] &= ~Disp64
;
2459 if ((i
.types
[op
] & Disp32
)
2460 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2462 /* If this operand is at most 32 bits, convert
2463 to a signed 32 bit number and don't use 64bit
2465 disp
&= (((offsetT
) 2 << 31) - 1);
2466 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2467 i
.types
[op
] &= ~Disp64
;
2469 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2471 i
.types
[op
] &= ~Disp
;
2475 else if (flag_code
== CODE_64BIT
)
2477 if (fits_in_signed_long (disp
))
2479 i
.types
[op
] &= ~Disp64
;
2480 i
.types
[op
] |= Disp32S
;
2482 if (fits_in_unsigned_long (disp
))
2483 i
.types
[op
] |= Disp32
;
2485 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2486 && fits_in_signed_byte (disp
))
2487 i
.types
[op
] |= Disp8
;
2489 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2490 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2492 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2493 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2494 i
.types
[op
] &= ~Disp
;
2497 /* We only support 64bit displacement on constants. */
2498 i
.types
[op
] &= ~Disp64
;
2503 match_template (void)
2505 /* Points to template once we've found it. */
2507 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2508 unsigned int found_reverse_match
;
2510 unsigned int operand_types
[MAX_OPERANDS
];
2511 int addr_prefix_disp
;
2514 #if MAX_OPERANDS != 4
2515 # error "MAX_OPERANDS must be 4."
2518 #define MATCH(overlap, given, template) \
2519 ((overlap & ~JumpAbsolute) \
2520 && (((given) & (BaseIndex | JumpAbsolute)) \
2521 == ((overlap) & (BaseIndex | JumpAbsolute))))
2523 /* If given types r0 and r1 are registers they must be of the same type
2524 unless the expected operand type register overlap is null.
2525 Note that Acc in a template matches every size of reg. */
2526 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2527 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2528 || ((g0) & Reg) == ((g1) & Reg) \
2529 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2535 found_reverse_match
= 0;
2536 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2537 operand_types
[j
] = 0;
2538 addr_prefix_disp
= -1;
2539 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2541 : (i
.suffix
== WORD_MNEM_SUFFIX
2543 : (i
.suffix
== SHORT_MNEM_SUFFIX
2545 : (i
.suffix
== LONG_MNEM_SUFFIX
2547 : (i
.suffix
== QWORD_MNEM_SUFFIX
2549 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2550 ? No_xSuf
: 0))))));
2552 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2554 addr_prefix_disp
= -1;
2556 /* Must have right number of operands. */
2557 if (i
.operands
!= t
->operands
)
2560 /* Check the suffix, except for some instructions in intel mode. */
2561 if ((t
->opcode_modifier
& suffix_check
)
2563 && (t
->opcode_modifier
& IgnoreSize
)))
2566 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2567 operand_types
[j
] = t
->operand_types
[j
];
2569 /* In general, don't allow 64-bit operands in 32-bit mode. */
2570 if (i
.suffix
== QWORD_MNEM_SUFFIX
2571 && flag_code
!= CODE_64BIT
2573 ? (!(t
->opcode_modifier
& IgnoreSize
)
2574 && !intel_float_operand (t
->name
))
2575 : intel_float_operand (t
->name
) != 2)
2576 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2577 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2578 && (t
->base_opcode
!= 0x0fc7
2579 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2582 /* Do not verify operands when there are none. */
2583 else if (!t
->operands
)
2585 if (t
->cpu_flags
& ~cpu_arch_flags
)
2587 /* We've found a match; break out of loop. */
2591 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2592 into Disp32/Disp16/Disp32 operand. */
2593 if (i
.prefix
[ADDR_PREFIX
] != 0)
2595 unsigned int DispOn
= 0, DispOff
= 0;
2613 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2615 /* There should be only one Disp operand. */
2616 if ((operand_types
[j
] & DispOff
))
2618 addr_prefix_disp
= j
;
2619 operand_types
[j
] |= DispOn
;
2620 operand_types
[j
] &= ~DispOff
;
2626 overlap0
= i
.types
[0] & operand_types
[0];
2627 switch (t
->operands
)
2630 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2634 /* xchg %eax, %eax is a special case. It is an aliase for nop
2635 only in 32bit mode and we can use opcode 0x90. In 64bit
2636 mode, we can't use 0x90 for xchg %eax, %eax since it should
2637 zero-extend %eax to %rax. */
2638 if (flag_code
== CODE_64BIT
2639 && t
->base_opcode
== 0x90
2640 && i
.types
[0] == (Acc
| Reg32
)
2641 && i
.types
[1] == (Acc
| Reg32
))
2645 overlap1
= i
.types
[1] & operand_types
[1];
2646 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2647 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2648 /* monitor in SSE3 is a very special case. The first
2649 register and the second register may have different
2650 sizes. The same applies to crc32 in SSE4.2. */
2651 || !((t
->base_opcode
== 0x0f01
2652 && t
->extension_opcode
== 0xc8)
2653 || t
->base_opcode
== 0xf20f38f1
2654 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2656 overlap1
, i
.types
[1],
2659 /* Check if other direction is valid ... */
2660 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2663 /* Try reversing direction of operands. */
2664 overlap0
= i
.types
[0] & operand_types
[1];
2665 overlap1
= i
.types
[1] & operand_types
[0];
2666 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2667 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2668 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2670 overlap1
, i
.types
[1],
2673 /* Does not match either direction. */
2676 /* found_reverse_match holds which of D or FloatDR
2678 if ((t
->opcode_modifier
& D
))
2679 found_reverse_match
= Opcode_D
;
2680 else if ((t
->opcode_modifier
& FloatD
))
2681 found_reverse_match
= Opcode_FloatD
;
2683 found_reverse_match
= 0;
2684 if ((t
->opcode_modifier
& FloatR
))
2685 found_reverse_match
|= Opcode_FloatR
;
2689 /* Found a forward 2 operand match here. */
2690 switch (t
->operands
)
2693 overlap3
= i
.types
[3] & operand_types
[3];
2695 overlap2
= i
.types
[2] & operand_types
[2];
2699 switch (t
->operands
)
2702 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2703 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2711 /* Here we make use of the fact that there are no
2712 reverse match 3 operand instructions, and all 3
2713 operand instructions only need to be checked for
2714 register consistency between operands 2 and 3. */
2715 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2716 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2726 /* Found either forward/reverse 2, 3 or 4 operand match here:
2727 slip through to break. */
2729 if (t
->cpu_flags
& ~cpu_arch_flags
)
2731 found_reverse_match
= 0;
2734 /* We've found a match; break out of loop. */
2738 if (t
== current_templates
->end
)
2740 /* We found no match. */
2741 as_bad (_("suffix or operands invalid for `%s'"),
2742 current_templates
->start
->name
);
2746 if (!quiet_warnings
)
2749 && ((i
.types
[0] & JumpAbsolute
)
2750 != (operand_types
[0] & JumpAbsolute
)))
2752 as_warn (_("indirect %s without `*'"), t
->name
);
2755 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2756 == (IsPrefix
| IgnoreSize
))
2758 /* Warn them that a data or address size prefix doesn't
2759 affect assembly of the next line of code. */
2760 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2764 /* Copy the template we found. */
2767 if (addr_prefix_disp
!= -1)
2768 i
.tm
.operand_types
[addr_prefix_disp
]
2769 = operand_types
[addr_prefix_disp
];
2771 if (found_reverse_match
)
2773 /* If we found a reverse match we must alter the opcode
2774 direction bit. found_reverse_match holds bits to change
2775 (different for int & float insns). */
2777 i
.tm
.base_opcode
^= found_reverse_match
;
2779 i
.tm
.operand_types
[0] = operand_types
[1];
2780 i
.tm
.operand_types
[1] = operand_types
[0];
2789 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2790 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2792 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2794 as_bad (_("`%s' operand %d must use `%%es' segment"),
2799 /* There's only ever one segment override allowed per instruction.
2800 This instruction possibly has a legal segment override on the
2801 second operand, so copy the segment to where non-string
2802 instructions store it, allowing common code. */
2803 i
.seg
[0] = i
.seg
[1];
2805 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2807 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2809 as_bad (_("`%s' operand %d must use `%%es' segment"),
2819 process_suffix (void)
2821 /* If matched instruction specifies an explicit instruction mnemonic
2823 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2825 if (i
.tm
.opcode_modifier
& Size16
)
2826 i
.suffix
= WORD_MNEM_SUFFIX
;
2827 else if (i
.tm
.opcode_modifier
& Size64
)
2828 i
.suffix
= QWORD_MNEM_SUFFIX
;
2830 i
.suffix
= LONG_MNEM_SUFFIX
;
2832 else if (i
.reg_operands
)
2834 /* If there's no instruction mnemonic suffix we try to invent one
2835 based on register operands. */
2838 /* We take i.suffix from the last register operand specified,
2839 Destination register type is more significant than source
2840 register type. crc32 in SSE4.2 prefers source register
2842 if (i
.tm
.base_opcode
== 0xf20f38f1)
2844 if ((i
.types
[0] & Reg
))
2845 i
.suffix
= ((i
.types
[0] & Reg16
) ? WORD_MNEM_SUFFIX
:
2853 for (op
= i
.operands
; --op
>= 0;)
2854 if ((i
.types
[op
] & Reg
)
2855 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2857 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2858 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2859 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2865 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2867 if (!check_byte_reg ())
2870 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2872 if (!check_long_reg ())
2875 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2877 if (!check_qword_reg ())
2880 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2882 if (!check_word_reg ())
2885 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2886 /* Do nothing if the instruction is going to ignore the prefix. */
2891 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2893 /* exclude fldenv/frstor/fsave/fstenv */
2894 && (i
.tm
.opcode_modifier
& No_sSuf
))
2896 i
.suffix
= stackop_size
;
2898 else if (intel_syntax
2900 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2901 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2902 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2903 && i
.tm
.extension_opcode
<= 3)))
2908 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2910 i
.suffix
= QWORD_MNEM_SUFFIX
;
2914 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2915 i
.suffix
= LONG_MNEM_SUFFIX
;
2918 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2919 i
.suffix
= WORD_MNEM_SUFFIX
;
2928 if (i
.tm
.opcode_modifier
& W
)
2930 as_bad (_("no instruction mnemonic suffix given and "
2931 "no register operands; can't size instruction"));
2937 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2945 if ((i
.tm
.opcode_modifier
& W
)
2946 || ((suffixes
& (suffixes
- 1))
2947 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2949 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2955 /* Change the opcode based on the operand size given by i.suffix;
2956 We don't need to change things for byte insns. */
2958 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2960 /* It's not a byte, select word/dword operation. */
2961 if (i
.tm
.opcode_modifier
& W
)
2963 if (i
.tm
.opcode_modifier
& ShortForm
)
2964 i
.tm
.base_opcode
|= 8;
2966 i
.tm
.base_opcode
|= 1;
2969 /* Now select between word & dword operations via the operand
2970 size prefix, except for instructions that will ignore this
2972 if (i
.tm
.base_opcode
== 0x0f01 && i
.tm
.extension_opcode
== 0xc8)
2974 /* monitor in SSE3 is a very special case. The default size
2975 of AX is the size of mode. The address size override
2976 prefix will change the size of AX. */
2977 if (i
.op
->regs
[0].reg_type
&
2978 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
2979 if (!add_prefix (ADDR_PREFIX_OPCODE
))
2982 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
2983 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
2984 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
2985 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2986 || (flag_code
== CODE_64BIT
2987 && (i
.tm
.opcode_modifier
& JumpByte
))))
2989 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2991 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2992 prefix
= ADDR_PREFIX_OPCODE
;
2994 if (!add_prefix (prefix
))
2998 /* Set mode64 for an operand. */
2999 if (i
.suffix
== QWORD_MNEM_SUFFIX
3000 && flag_code
== CODE_64BIT
3001 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
3003 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3006 || i
.types
[0] != (Acc
| Reg64
)
3007 || i
.types
[1] != (Acc
| Reg64
)
3008 || i
.tm
.base_opcode
!= 0x90)
3012 /* Size floating point instruction. */
3013 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3014 if (i
.tm
.opcode_modifier
& FloatMF
)
3015 i
.tm
.base_opcode
^= 4;
3022 check_byte_reg (void)
3026 for (op
= i
.operands
; --op
>= 0;)
3028 /* If this is an eight bit register, it's OK. If it's the 16 or
3029 32 bit version of an eight bit register, we will just use the
3030 low portion, and that's OK too. */
3031 if (i
.types
[op
] & Reg8
)
3034 /* movzx and movsx should not generate this warning. */
3036 && (i
.tm
.base_opcode
== 0xfb7
3037 || i
.tm
.base_opcode
== 0xfb6
3038 || i
.tm
.base_opcode
== 0x63
3039 || i
.tm
.base_opcode
== 0xfbe
3040 || i
.tm
.base_opcode
== 0xfbf))
3043 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3045 /* Prohibit these changes in the 64bit mode, since the
3046 lowering is more complicated. */
3047 if (flag_code
== CODE_64BIT
3048 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3050 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3051 register_prefix
, i
.op
[op
].regs
->reg_name
,
3055 #if REGISTER_WARNINGS
3057 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3058 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3060 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3061 ? REGNAM_AL
- REGNAM_AX
3062 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3064 i
.op
[op
].regs
->reg_name
,
3069 /* Any other register is bad. */
3070 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3072 | Control
| Debug
| Test
3073 | FloatReg
| FloatAcc
))
3075 as_bad (_("`%s%s' not allowed with `%s%c'"),
3077 i
.op
[op
].regs
->reg_name
,
3087 check_long_reg (void)
3091 for (op
= i
.operands
; --op
>= 0;)
3092 /* Reject eight bit registers, except where the template requires
3093 them. (eg. movzb) */
3094 if ((i
.types
[op
] & Reg8
) != 0
3095 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3097 as_bad (_("`%s%s' not allowed with `%s%c'"),
3099 i
.op
[op
].regs
->reg_name
,
3104 /* Warn if the e prefix on a general reg is missing. */
3105 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3106 && (i
.types
[op
] & Reg16
) != 0
3107 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3109 /* Prohibit these changes in the 64bit mode, since the
3110 lowering is more complicated. */
3111 if (flag_code
== CODE_64BIT
)
3113 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3114 register_prefix
, i
.op
[op
].regs
->reg_name
,
3118 #if REGISTER_WARNINGS
3120 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3122 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3124 i
.op
[op
].regs
->reg_name
,
3128 /* Warn if the r prefix on a general reg is missing. */
3129 else if ((i
.types
[op
] & Reg64
) != 0
3130 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3132 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3133 register_prefix
, i
.op
[op
].regs
->reg_name
,
3141 check_qword_reg (void)
3145 for (op
= i
.operands
; --op
>= 0; )
3146 /* Reject eight bit registers, except where the template requires
3147 them. (eg. movzb) */
3148 if ((i
.types
[op
] & Reg8
) != 0
3149 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3151 as_bad (_("`%s%s' not allowed with `%s%c'"),
3153 i
.op
[op
].regs
->reg_name
,
3158 /* Warn if the e prefix on a general reg is missing. */
3159 else if (((i
.types
[op
] & Reg16
) != 0
3160 || (i
.types
[op
] & Reg32
) != 0)
3161 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3163 /* Prohibit these changes in the 64bit mode, since the
3164 lowering is more complicated. */
3165 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3166 register_prefix
, i
.op
[op
].regs
->reg_name
,
3174 check_word_reg (void)
3177 for (op
= i
.operands
; --op
>= 0;)
3178 /* Reject eight bit registers, except where the template requires
3179 them. (eg. movzb) */
3180 if ((i
.types
[op
] & Reg8
) != 0
3181 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3183 as_bad (_("`%s%s' not allowed with `%s%c'"),
3185 i
.op
[op
].regs
->reg_name
,
3190 /* Warn if the e prefix on a general reg is present. */
3191 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3192 && (i
.types
[op
] & Reg32
) != 0
3193 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3195 /* Prohibit these changes in the 64bit mode, since the
3196 lowering is more complicated. */
3197 if (flag_code
== CODE_64BIT
)
3199 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3200 register_prefix
, i
.op
[op
].regs
->reg_name
,
3205 #if REGISTER_WARNINGS
3206 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3208 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3210 i
.op
[op
].regs
->reg_name
,
3220 unsigned int overlap0
, overlap1
, overlap2
;
3222 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3223 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3224 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3225 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3226 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3230 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3232 : (i
.suffix
== WORD_MNEM_SUFFIX
3234 : (i
.suffix
== QWORD_MNEM_SUFFIX
3238 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3239 || overlap0
== (Imm16
| Imm32
)
3240 || overlap0
== (Imm16
| Imm32S
))
3242 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3245 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3246 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3247 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3249 as_bad (_("no instruction mnemonic suffix given; "
3250 "can't determine immediate size"));
3254 i
.types
[0] = overlap0
;
3256 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3257 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3258 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3259 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3260 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3264 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3266 : (i
.suffix
== WORD_MNEM_SUFFIX
3268 : (i
.suffix
== QWORD_MNEM_SUFFIX
3272 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3273 || overlap1
== (Imm16
| Imm32
)
3274 || overlap1
== (Imm16
| Imm32S
))
3276 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3279 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3280 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3281 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3283 as_bad (_("no instruction mnemonic suffix given; "
3284 "can't determine immediate size %x %c"),
3285 overlap1
, i
.suffix
);
3289 i
.types
[1] = overlap1
;
3291 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3292 assert ((overlap2
& Imm
) == 0);
3293 i
.types
[2] = overlap2
;
3299 process_operands (void)
3301 /* Default segment register this instruction will use for memory
3302 accesses. 0 means unknown. This is only for optimizing out
3303 unnecessary segment overrides. */
3304 const seg_entry
*default_seg
= 0;
3306 /* The imul $imm, %reg instruction is converted into
3307 imul $imm, %reg, %reg, and the clr %reg instruction
3308 is converted into xor %reg, %reg. */
3309 if (i
.tm
.opcode_modifier
& regKludge
)
3311 if ((i
.tm
.cpu_flags
& CpuSSE4_1
))
3313 /* The first operand in instruction blendvpd, blendvps and
3314 pblendvb in SSE4.1 is implicit and must be xmm0. */
3315 assert (i
.operands
== 3
3316 && i
.reg_operands
>= 2
3317 && i
.types
[0] == RegXMM
);
3318 if (i
.op
[0].regs
->reg_num
!= 0)
3321 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3322 i
.tm
.name
, register_prefix
);
3324 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3325 i
.tm
.name
, register_prefix
);
3330 i
.types
[0] = i
.types
[1];
3331 i
.types
[1] = i
.types
[2];
3335 /* We need to adjust fields in i.tm since they are used by
3336 build_modrm_byte. */
3337 i
.tm
.operand_types
[0] = i
.tm
.operand_types
[1];
3338 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[2];
3343 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3344 /* Pretend we saw the extra register operand. */
3345 assert (i
.reg_operands
== 1
3346 && i
.op
[first_reg_op
+ 1].regs
== 0);
3347 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3348 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3354 if (i
.tm
.opcode_modifier
& ShortForm
)
3356 if (i
.types
[0] & (SReg2
| SReg3
))
3358 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3359 && i
.op
[0].regs
->reg_num
== 1)
3361 as_bad (_("you can't `pop %%cs'"));
3364 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3365 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3370 /* The register or float register operand is in operand 0 or 1. */
3371 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3372 /* Register goes in low 3 bits of opcode. */
3373 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3374 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3376 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3378 /* Warn about some common errors, but press on regardless.
3379 The first case can be generated by gcc (<= 2.8.1). */
3380 if (i
.operands
== 2)
3382 /* Reversed arguments on faddp, fsubp, etc. */
3383 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
3384 register_prefix
, i
.op
[1].regs
->reg_name
,
3385 register_prefix
, i
.op
[0].regs
->reg_name
);
3389 /* Extraneous `l' suffix on fp insn. */
3390 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
3391 register_prefix
, i
.op
[0].regs
->reg_name
);
3396 else if (i
.tm
.opcode_modifier
& Modrm
)
3398 /* The opcode is completed (modulo i.tm.extension_opcode which
3399 must be put into the modrm byte). Now, we make the modrm and
3400 index base bytes based on all the info we've collected. */
3402 default_seg
= build_modrm_byte ();
3404 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3408 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3410 /* For the string instructions that allow a segment override
3411 on one of their operands, the default segment is ds. */
3415 if ((i
.tm
.base_opcode
== 0x8d /* lea */
3416 || (i
.tm
.cpu_flags
& CpuSVME
))
3417 && i
.seg
[0] && !quiet_warnings
)
3418 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3420 /* If a segment was explicitly specified, and the specified segment
3421 is not the default, use an opcode prefix to select it. If we
3422 never figured out what the default segment is, then default_seg
3423 will be zero at this point, and the specified segment prefix will
3425 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3427 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3433 static const seg_entry
*
3434 build_modrm_byte (void)
3436 const seg_entry
*default_seg
= 0;
3438 /* i.reg_operands MUST be the number of real register operands;
3439 implicit registers do not count. */
3440 if (i
.reg_operands
== 2)
3442 unsigned int source
, dest
;
3450 /* When there are 3 operands, one of them may be immediate,
3451 which may be the first or the last operand. Otherwise,
3452 the first operand must be shift count register (cl). */
3453 assert (i
.imm_operands
== 1
3454 || (i
.imm_operands
== 0
3455 && (i
.types
[0] & ShiftCount
)));
3456 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3459 /* When there are 4 operands, the first two must be immediate
3460 operands. The source operand will be the 3rd one. */
3461 assert (i
.imm_operands
== 2
3462 && (i
.types
[0] & Imm
)
3463 && (i
.types
[1] & Imm
));
3473 /* One of the register operands will be encoded in the i.tm.reg
3474 field, the other in the combined i.tm.mode and i.tm.regmem
3475 fields. If no form of this instruction supports a memory
3476 destination operand, then we assume the source operand may
3477 sometimes be a memory operand and so we need to store the
3478 destination in the i.rm.reg field. */
3479 if ((i
.tm
.operand_types
[dest
] & (AnyMem
| RegMem
)) == 0)
3481 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3482 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3483 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3485 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3490 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3491 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3492 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3494 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3497 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
3499 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3501 i
.rex
&= ~(REX_R
| REX_B
);
3502 add_prefix (LOCK_PREFIX_OPCODE
);
3506 { /* If it's not 2 reg operands... */
3509 unsigned int fake_zero_displacement
= 0;
3512 for (op
= 0; op
< i
.operands
; op
++)
3513 if ((i
.types
[op
] & AnyMem
))
3515 assert (op
< i
.operands
);
3519 if (i
.base_reg
== 0)
3522 if (!i
.disp_operands
)
3523 fake_zero_displacement
= 1;
3524 if (i
.index_reg
== 0)
3526 /* Operand is just <disp> */
3527 if (flag_code
== CODE_64BIT
)
3529 /* 64bit mode overwrites the 32bit absolute
3530 addressing by RIP relative addressing and
3531 absolute addressing is encoded by one of the
3532 redundant SIB forms. */
3533 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3534 i
.sib
.base
= NO_BASE_REGISTER
;
3535 i
.sib
.index
= NO_INDEX_REGISTER
;
3536 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3537 ? Disp32S
: Disp32
);
3539 else if ((flag_code
== CODE_16BIT
)
3540 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3542 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3543 i
.types
[op
] = Disp16
;
3547 i
.rm
.regmem
= NO_BASE_REGISTER
;
3548 i
.types
[op
] = Disp32
;
3551 else /* !i.base_reg && i.index_reg */
3553 i
.sib
.index
= i
.index_reg
->reg_num
;
3554 i
.sib
.base
= NO_BASE_REGISTER
;
3555 i
.sib
.scale
= i
.log2_scale_factor
;
3556 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3557 i
.types
[op
] &= ~Disp
;
3558 if (flag_code
!= CODE_64BIT
)
3559 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3561 i
.types
[op
] |= Disp32S
;
3562 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3566 /* RIP addressing for 64bit mode. */
3567 else if (i
.base_reg
->reg_type
== BaseIndex
)
3569 i
.rm
.regmem
= NO_BASE_REGISTER
;
3570 i
.types
[op
] &= ~ Disp
;
3571 i
.types
[op
] |= Disp32S
;
3572 i
.flags
[op
] |= Operand_PCrel
;
3573 if (! i
.disp_operands
)
3574 fake_zero_displacement
= 1;
3576 else if (i
.base_reg
->reg_type
& Reg16
)
3578 switch (i
.base_reg
->reg_num
)
3581 if (i
.index_reg
== 0)
3583 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3584 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3588 if (i
.index_reg
== 0)
3591 if ((i
.types
[op
] & Disp
) == 0)
3593 /* fake (%bp) into 0(%bp) */
3594 i
.types
[op
] |= Disp8
;
3595 fake_zero_displacement
= 1;
3598 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3599 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3601 default: /* (%si) -> 4 or (%di) -> 5 */
3602 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3604 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3606 else /* i.base_reg and 32/64 bit mode */
3608 if (flag_code
== CODE_64BIT
3609 && (i
.types
[op
] & Disp
))
3610 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3611 | (i
.prefix
[ADDR_PREFIX
] == 0
3612 ? Disp32S
: Disp32
));
3614 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3615 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3617 i
.sib
.base
= i
.base_reg
->reg_num
;
3618 /* x86-64 ignores REX prefix bit here to avoid decoder
3620 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3623 if (i
.disp_operands
== 0)
3625 fake_zero_displacement
= 1;
3626 i
.types
[op
] |= Disp8
;
3629 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3633 i
.sib
.scale
= i
.log2_scale_factor
;
3634 if (i
.index_reg
== 0)
3636 /* <disp>(%esp) becomes two byte modrm with no index
3637 register. We've already stored the code for esp
3638 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3639 Any base register besides %esp will not use the
3640 extra modrm byte. */
3641 i
.sib
.index
= NO_INDEX_REGISTER
;
3642 #if !SCALE1_WHEN_NO_INDEX
3643 /* Another case where we force the second modrm byte. */
3644 if (i
.log2_scale_factor
)
3645 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3650 i
.sib
.index
= i
.index_reg
->reg_num
;
3651 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3652 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3657 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3658 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3661 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3664 if (fake_zero_displacement
)
3666 /* Fakes a zero displacement assuming that i.types[op]
3667 holds the correct displacement size. */
3670 assert (i
.op
[op
].disps
== 0);
3671 exp
= &disp_expressions
[i
.disp_operands
++];
3672 i
.op
[op
].disps
= exp
;
3673 exp
->X_op
= O_constant
;
3674 exp
->X_add_number
= 0;
3675 exp
->X_add_symbol
= (symbolS
*) 0;
3676 exp
->X_op_symbol
= (symbolS
*) 0;
3680 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3681 (if any) based on i.tm.extension_opcode. Again, we must be
3682 careful to make sure that segment/control/debug/test/MMX
3683 registers are coded into the i.rm.reg field. */
3688 for (op
= 0; op
< i
.operands
; op
++)
3689 if ((i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3691 | Control
| Debug
| Test
)))
3693 assert (op
< i
.operands
);
3695 /* If there is an extension opcode to put here, the register
3696 number must be put into the regmem field. */
3697 if (i
.tm
.extension_opcode
!= None
)
3699 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3700 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3705 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3706 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3710 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3711 must set it to 3 to indicate this is a register operand
3712 in the regmem field. */
3713 if (!i
.mem_operands
)
3717 /* Fill in i.rm.reg field with extension opcode (if any). */
3718 if (i
.tm
.extension_opcode
!= None
)
3719 i
.rm
.reg
= i
.tm
.extension_opcode
;
3725 output_branch (void)
3730 relax_substateT subtype
;
3735 if (flag_code
== CODE_16BIT
)
3739 if (i
.prefix
[DATA_PREFIX
] != 0)
3745 /* Pentium4 branch hints. */
3746 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3747 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3752 if (i
.prefix
[REX_PREFIX
] != 0)
3758 if (i
.prefixes
!= 0 && !intel_syntax
)
3759 as_warn (_("skipping prefixes on this instruction"));
3761 /* It's always a symbol; End frag & setup for relax.
3762 Make sure there is enough room in this frag for the largest
3763 instruction we may generate in md_convert_frag. This is 2
3764 bytes for the opcode and room for the prefix and largest
3766 frag_grow (prefix
+ 2 + 4);
3767 /* Prefix and 1 opcode byte go in fr_fix. */
3768 p
= frag_more (prefix
+ 1);
3769 if (i
.prefix
[DATA_PREFIX
] != 0)
3770 *p
++ = DATA_PREFIX_OPCODE
;
3771 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3772 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3773 *p
++ = i
.prefix
[SEG_PREFIX
];
3774 if (i
.prefix
[REX_PREFIX
] != 0)
3775 *p
++ = i
.prefix
[REX_PREFIX
];
3776 *p
= i
.tm
.base_opcode
;
3778 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3779 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3780 else if ((cpu_arch_flags
& Cpu386
) != 0)
3781 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3783 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3786 sym
= i
.op
[0].disps
->X_add_symbol
;
3787 off
= i
.op
[0].disps
->X_add_number
;
3789 if (i
.op
[0].disps
->X_op
!= O_constant
3790 && i
.op
[0].disps
->X_op
!= O_symbol
)
3792 /* Handle complex expressions. */
3793 sym
= make_expr_symbol (i
.op
[0].disps
);
3797 /* 1 possible extra opcode + 4 byte displacement go in var part.
3798 Pass reloc in fr_var. */
3799 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3809 if (i
.tm
.opcode_modifier
& JumpByte
)
3811 /* This is a loop or jecxz type instruction. */
3813 if (i
.prefix
[ADDR_PREFIX
] != 0)
3815 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3818 /* Pentium4 branch hints. */
3819 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3820 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3822 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3831 if (flag_code
== CODE_16BIT
)
3834 if (i
.prefix
[DATA_PREFIX
] != 0)
3836 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3846 if (i
.prefix
[REX_PREFIX
] != 0)
3848 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3852 if (i
.prefixes
!= 0 && !intel_syntax
)
3853 as_warn (_("skipping prefixes on this instruction"));
3855 p
= frag_more (1 + size
);
3856 *p
++ = i
.tm
.base_opcode
;
3858 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3859 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3861 /* All jumps handled here are signed, but don't use a signed limit
3862 check for 32 and 16 bit jumps as we want to allow wrap around at
3863 4G and 64k respectively. */
3865 fixP
->fx_signed
= 1;
3869 output_interseg_jump (void)
3877 if (flag_code
== CODE_16BIT
)
3881 if (i
.prefix
[DATA_PREFIX
] != 0)
3887 if (i
.prefix
[REX_PREFIX
] != 0)
3897 if (i
.prefixes
!= 0 && !intel_syntax
)
3898 as_warn (_("skipping prefixes on this instruction"));
3900 /* 1 opcode; 2 segment; offset */
3901 p
= frag_more (prefix
+ 1 + 2 + size
);
3903 if (i
.prefix
[DATA_PREFIX
] != 0)
3904 *p
++ = DATA_PREFIX_OPCODE
;
3906 if (i
.prefix
[REX_PREFIX
] != 0)
3907 *p
++ = i
.prefix
[REX_PREFIX
];
3909 *p
++ = i
.tm
.base_opcode
;
3910 if (i
.op
[1].imms
->X_op
== O_constant
)
3912 offsetT n
= i
.op
[1].imms
->X_add_number
;
3915 && !fits_in_unsigned_word (n
)
3916 && !fits_in_signed_word (n
))
3918 as_bad (_("16-bit jump out of range"));
3921 md_number_to_chars (p
, n
, size
);
3924 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3925 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
3926 if (i
.op
[0].imms
->X_op
!= O_constant
)
3927 as_bad (_("can't handle non absolute segment in `%s'"),
3929 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
3935 fragS
*insn_start_frag
;
3936 offsetT insn_start_off
;
3938 /* Tie dwarf2 debug info to the address at the start of the insn.
3939 We can't do this after the insn has been output as the current
3940 frag may have been closed off. eg. by frag_var. */
3941 dwarf2_emit_insn (0);
3943 insn_start_frag
= frag_now
;
3944 insn_start_off
= frag_now_fix ();
3947 if (i
.tm
.opcode_modifier
& Jump
)
3949 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
3951 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
3952 output_interseg_jump ();
3955 /* Output normal instructions here. */
3958 unsigned int prefix
;
3960 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
3961 SSE4 instructions have 3 bytes. We may use one more higher
3962 byte to specify a prefix the instruction requires. Exclude
3963 instructions which are in both SSE4 and ABM. */
3964 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
3965 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
3967 if (i
.tm
.base_opcode
& 0xff000000)
3969 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
3973 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
3975 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
3976 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
3979 if (prefix
!= REPE_PREFIX_OPCODE
3980 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
3981 add_prefix (prefix
);
3984 add_prefix (prefix
);
3987 /* The prefix bytes. */
3989 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
3995 md_number_to_chars (p
, (valueT
) *q
, 1);
3999 /* Now the opcode; be careful about word order here! */
4000 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
4002 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
4006 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
4007 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
4010 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
4015 /* Put out high byte first: can't use md_number_to_chars! */
4016 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
4017 *p
= i
.tm
.base_opcode
& 0xff;
4020 /* Now the modrm byte and sib byte (if present). */
4021 if (i
.tm
.opcode_modifier
& Modrm
)
4024 md_number_to_chars (p
,
4025 (valueT
) (i
.rm
.regmem
<< 0
4029 /* If i.rm.regmem == ESP (4)
4030 && i.rm.mode != (Register mode)
4032 ==> need second modrm byte. */
4033 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
4035 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
4038 md_number_to_chars (p
,
4039 (valueT
) (i
.sib
.base
<< 0
4041 | i
.sib
.scale
<< 6),
4046 if (i
.disp_operands
)
4047 output_disp (insn_start_frag
, insn_start_off
);
4050 output_imm (insn_start_frag
, insn_start_off
);
4056 pi ("" /*line*/, &i
);
4058 #endif /* DEBUG386 */
4062 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4067 for (n
= 0; n
< i
.operands
; n
++)
4069 if (i
.types
[n
] & Disp
)
4071 if (i
.op
[n
].disps
->X_op
== O_constant
)
4077 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4080 if (i
.types
[n
] & Disp8
)
4082 if (i
.types
[n
] & Disp64
)
4085 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4087 p
= frag_more (size
);
4088 md_number_to_chars (p
, val
, size
);
4092 enum bfd_reloc_code_real reloc_type
;
4095 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4097 /* The PC relative address is computed relative
4098 to the instruction boundary, so in case immediate
4099 fields follows, we need to adjust the value. */
4100 if (pcrel
&& i
.imm_operands
)
4105 for (n1
= 0; n1
< i
.operands
; n1
++)
4106 if (i
.types
[n1
] & Imm
)
4108 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4111 if (i
.types
[n1
] & (Imm8
| Imm8S
))
4113 if (i
.types
[n1
] & Imm64
)
4118 /* We should find the immediate. */
4119 if (n1
== i
.operands
)
4121 i
.op
[n
].disps
->X_add_number
-= imm_size
;
4124 if (i
.types
[n
] & Disp32S
)
4127 if (i
.types
[n
] & (Disp16
| Disp64
))
4130 if (i
.types
[n
] & Disp64
)
4134 p
= frag_more (size
);
4135 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4137 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4138 && (((reloc_type
== BFD_RELOC_32
4139 || reloc_type
== BFD_RELOC_X86_64_32S
4140 || (reloc_type
== BFD_RELOC_64
4142 && (i
.op
[n
].disps
->X_op
== O_symbol
4143 || (i
.op
[n
].disps
->X_op
== O_add
4144 && ((symbol_get_value_expression
4145 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4147 || reloc_type
== BFD_RELOC_32_PCREL
))
4151 if (insn_start_frag
== frag_now
)
4152 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4157 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4158 for (fr
= insn_start_frag
->fr_next
;
4159 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4161 add
+= p
- frag_now
->fr_literal
;
4166 reloc_type
= BFD_RELOC_386_GOTPC
;
4167 i
.op
[n
].imms
->X_add_number
+= add
;
4169 else if (reloc_type
== BFD_RELOC_64
)
4170 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4172 /* Don't do the adjustment for x86-64, as there
4173 the pcrel addressing is relative to the _next_
4174 insn, and that is taken care of in other code. */
4175 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4177 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4178 i
.op
[n
].disps
, pcrel
, reloc_type
);
4185 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4190 for (n
= 0; n
< i
.operands
; n
++)
4192 if (i
.types
[n
] & Imm
)
4194 if (i
.op
[n
].imms
->X_op
== O_constant
)
4200 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4203 if (i
.types
[n
] & (Imm8
| Imm8S
))
4205 else if (i
.types
[n
] & Imm64
)
4208 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4210 p
= frag_more (size
);
4211 md_number_to_chars (p
, val
, size
);
4215 /* Not absolute_section.
4216 Need a 32-bit fixup (don't support 8bit
4217 non-absolute imms). Try to support other
4219 enum bfd_reloc_code_real reloc_type
;
4223 if ((i
.types
[n
] & (Imm32S
))
4224 && (i
.suffix
== QWORD_MNEM_SUFFIX
4225 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4227 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4230 if (i
.types
[n
] & (Imm8
| Imm8S
))
4232 if (i
.types
[n
] & Imm64
)
4236 p
= frag_more (size
);
4237 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4239 /* This is tough to explain. We end up with this one if we
4240 * have operands that look like
4241 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4242 * obtain the absolute address of the GOT, and it is strongly
4243 * preferable from a performance point of view to avoid using
4244 * a runtime relocation for this. The actual sequence of
4245 * instructions often look something like:
4250 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4252 * The call and pop essentially return the absolute address
4253 * of the label .L66 and store it in %ebx. The linker itself
4254 * will ultimately change the first operand of the addl so
4255 * that %ebx points to the GOT, but to keep things simple, the
4256 * .o file must have this operand set so that it generates not
4257 * the absolute address of .L66, but the absolute address of
4258 * itself. This allows the linker itself simply treat a GOTPC
4259 * relocation as asking for a pcrel offset to the GOT to be
4260 * added in, and the addend of the relocation is stored in the
4261 * operand field for the instruction itself.
4263 * Our job here is to fix the operand so that it would add
4264 * the correct offset so that %ebx would point to itself. The
4265 * thing that is tricky is that .-.L66 will point to the
4266 * beginning of the instruction, so we need to further modify
4267 * the operand so that it will point to itself. There are
4268 * other cases where you have something like:
4270 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4272 * and here no correction would be required. Internally in
4273 * the assembler we treat operands of this form as not being
4274 * pcrel since the '.' is explicitly mentioned, and I wonder
4275 * whether it would simplify matters to do it this way. Who
4276 * knows. In earlier versions of the PIC patches, the
4277 * pcrel_adjust field was used to store the correction, but
4278 * since the expression is not pcrel, I felt it would be
4279 * confusing to do it this way. */
4281 if ((reloc_type
== BFD_RELOC_32
4282 || reloc_type
== BFD_RELOC_X86_64_32S
4283 || reloc_type
== BFD_RELOC_64
)
4285 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4286 && (i
.op
[n
].imms
->X_op
== O_symbol
4287 || (i
.op
[n
].imms
->X_op
== O_add
4288 && ((symbol_get_value_expression
4289 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4294 if (insn_start_frag
== frag_now
)
4295 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4300 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4301 for (fr
= insn_start_frag
->fr_next
;
4302 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4304 add
+= p
- frag_now
->fr_literal
;
4308 reloc_type
= BFD_RELOC_386_GOTPC
;
4310 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4312 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4313 i
.op
[n
].imms
->X_add_number
+= add
;
4315 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4316 i
.op
[n
].imms
, 0, reloc_type
);
4322 /* x86_cons_fix_new is called via the expression parsing code when a
4323 reloc is needed. We use this hook to get the correct .got reloc. */
4324 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4325 static int cons_sign
= -1;
4328 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4331 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4333 got_reloc
= NO_RELOC
;
4336 if (exp
->X_op
== O_secrel
)
4338 exp
->X_op
= O_symbol
;
4339 r
= BFD_RELOC_32_SECREL
;
4343 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4346 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4347 # define lex_got(reloc, adjust, types) NULL
4349 /* Parse operands of the form
4350 <symbol>@GOTOFF+<nnn>
4351 and similar .plt or .got references.
4353 If we find one, set up the correct relocation in RELOC and copy the
4354 input string, minus the `@GOTOFF' into a malloc'd buffer for
4355 parsing by the calling routine. Return this buffer, and if ADJUST
4356 is non-null set it to the length of the string we removed from the
4357 input line. Otherwise return NULL. */
4359 lex_got (enum bfd_reloc_code_real
*reloc
,
4361 unsigned int *types
)
4363 /* Some of the relocations depend on the size of what field is to
4364 be relocated. But in our callers i386_immediate and i386_displacement
4365 we don't yet know the operand size (this will be set by insn
4366 matching). Hence we record the word32 relocation here,
4367 and adjust the reloc according to the real size in reloc(). */
4368 static const struct {
4370 const enum bfd_reloc_code_real rel
[2];
4371 const unsigned int types64
;
4374 BFD_RELOC_X86_64_PLTOFF64
},
4376 { "PLT", { BFD_RELOC_386_PLT32
,
4377 BFD_RELOC_X86_64_PLT32
},
4378 Imm32
| Imm32S
| Disp32
},
4380 BFD_RELOC_X86_64_GOTPLT64
},
4382 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4383 BFD_RELOC_X86_64_GOTOFF64
},
4386 BFD_RELOC_X86_64_GOTPCREL
},
4387 Imm32
| Imm32S
| Disp32
},
4388 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4389 BFD_RELOC_X86_64_TLSGD
},
4390 Imm32
| Imm32S
| Disp32
},
4391 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4395 BFD_RELOC_X86_64_TLSLD
},
4396 Imm32
| Imm32S
| Disp32
},
4397 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
4398 BFD_RELOC_X86_64_GOTTPOFF
},
4399 Imm32
| Imm32S
| Disp32
},
4400 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
4401 BFD_RELOC_X86_64_TPOFF32
},
4402 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4403 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
4406 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
4407 BFD_RELOC_X86_64_DTPOFF32
},
4408 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4409 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
4412 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
4415 { "GOT", { BFD_RELOC_386_GOT32
,
4416 BFD_RELOC_X86_64_GOT32
},
4417 Imm32
| Imm32S
| Disp32
| Imm64
},
4418 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
4419 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
4420 Imm32
| Imm32S
| Disp32
},
4421 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
4422 BFD_RELOC_X86_64_TLSDESC_CALL
},
4423 Imm32
| Imm32S
| Disp32
}
4431 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4432 if (is_end_of_line
[(unsigned char) *cp
])
4435 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4439 len
= strlen (gotrel
[j
].str
);
4440 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4442 if (gotrel
[j
].rel
[object_64bit
] != 0)
4445 char *tmpbuf
, *past_reloc
;
4447 *reloc
= gotrel
[j
].rel
[object_64bit
];
4453 if (flag_code
!= CODE_64BIT
)
4454 *types
= Imm32
| Disp32
;
4456 *types
= gotrel
[j
].types64
;
4459 if (GOT_symbol
== NULL
)
4460 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4462 /* Replace the relocation token with ' ', so that
4463 errors like foo@GOTOFF1 will be detected. */
4465 /* The length of the first part of our input line. */
4466 first
= cp
- input_line_pointer
;
4468 /* The second part goes from after the reloc token until
4469 (and including) an end_of_line char. Don't use strlen
4470 here as the end_of_line char may not be a NUL. */
4471 past_reloc
= cp
+ 1 + len
;
4472 for (cp
= past_reloc
; !is_end_of_line
[(unsigned char) *cp
++]; )
4474 second
= cp
- past_reloc
;
4476 /* Allocate and copy string. The trailing NUL shouldn't
4477 be necessary, but be safe. */
4478 tmpbuf
= xmalloc (first
+ second
+ 2);
4479 memcpy (tmpbuf
, input_line_pointer
, first
);
4480 tmpbuf
[first
] = ' ';
4481 memcpy (tmpbuf
+ first
+ 1, past_reloc
, second
);
4482 tmpbuf
[first
+ second
+ 1] = '\0';
4486 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4487 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4492 /* Might be a symbol version string. Don't as_bad here. */
4497 x86_cons (expressionS
*exp
, int size
)
4499 if (size
== 4 || (object_64bit
&& size
== 8))
4501 /* Handle @GOTOFF and the like in an expression. */
4503 char *gotfree_input_line
;
4506 save
= input_line_pointer
;
4507 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4508 if (gotfree_input_line
)
4509 input_line_pointer
= gotfree_input_line
;
4513 if (gotfree_input_line
)
4515 /* expression () has merrily parsed up to the end of line,
4516 or a comma - in the wrong buffer. Transfer how far
4517 input_line_pointer has moved to the right buffer. */
4518 input_line_pointer
= (save
4519 + (input_line_pointer
- gotfree_input_line
)
4521 free (gotfree_input_line
);
4529 static void signed_cons (int size
)
4531 if (flag_code
== CODE_64BIT
)
4539 pe_directive_secrel (dummy
)
4540 int dummy ATTRIBUTE_UNUSED
;
4547 if (exp
.X_op
== O_symbol
)
4548 exp
.X_op
= O_secrel
;
4550 emit_expr (&exp
, 4);
4552 while (*input_line_pointer
++ == ',');
4554 input_line_pointer
--;
4555 demand_empty_rest_of_line ();
4560 i386_immediate (char *imm_start
)
4562 char *save_input_line_pointer
;
4563 char *gotfree_input_line
;
4566 unsigned int types
= ~0U;
4568 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4570 as_bad (_("at most %d immediate operands are allowed"),
4571 MAX_IMMEDIATE_OPERANDS
);
4575 exp
= &im_expressions
[i
.imm_operands
++];
4576 i
.op
[this_operand
].imms
= exp
;
4578 if (is_space_char (*imm_start
))
4581 save_input_line_pointer
= input_line_pointer
;
4582 input_line_pointer
= imm_start
;
4584 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4585 if (gotfree_input_line
)
4586 input_line_pointer
= gotfree_input_line
;
4588 exp_seg
= expression (exp
);
4591 if (*input_line_pointer
)
4592 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4594 input_line_pointer
= save_input_line_pointer
;
4595 if (gotfree_input_line
)
4596 free (gotfree_input_line
);
4598 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4600 /* Missing or bad expr becomes absolute 0. */
4601 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4603 exp
->X_op
= O_constant
;
4604 exp
->X_add_number
= 0;
4605 exp
->X_add_symbol
= (symbolS
*) 0;
4606 exp
->X_op_symbol
= (symbolS
*) 0;
4608 else if (exp
->X_op
== O_constant
)
4610 /* Size it properly later. */
4611 i
.types
[this_operand
] |= Imm64
;
4612 /* If BFD64, sign extend val. */
4613 if (!use_rela_relocations
4614 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4616 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4618 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4619 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4620 && exp_seg
!= absolute_section
4621 && exp_seg
!= text_section
4622 && exp_seg
!= data_section
4623 && exp_seg
!= bss_section
4624 && exp_seg
!= undefined_section
4625 && !bfd_is_com_section (exp_seg
))
4627 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4631 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4633 as_bad (_("illegal immediate register operand %s"), imm_start
);
4638 /* This is an address. The size of the address will be
4639 determined later, depending on destination register,
4640 suffix, or the default for the section. */
4641 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4642 i
.types
[this_operand
] &= types
;
4649 i386_scale (char *scale
)
4652 char *save
= input_line_pointer
;
4654 input_line_pointer
= scale
;
4655 val
= get_absolute_expression ();
4660 i
.log2_scale_factor
= 0;
4663 i
.log2_scale_factor
= 1;
4666 i
.log2_scale_factor
= 2;
4669 i
.log2_scale_factor
= 3;
4673 char sep
= *input_line_pointer
;
4675 *input_line_pointer
= '\0';
4676 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4678 *input_line_pointer
= sep
;
4679 input_line_pointer
= save
;
4683 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4685 as_warn (_("scale factor of %d without an index register"),
4686 1 << i
.log2_scale_factor
);
4687 #if SCALE1_WHEN_NO_INDEX
4688 i
.log2_scale_factor
= 0;
4691 scale
= input_line_pointer
;
4692 input_line_pointer
= save
;
4697 i386_displacement (char *disp_start
, char *disp_end
)
4701 char *save_input_line_pointer
;
4702 char *gotfree_input_line
;
4703 int bigdisp
, override
;
4704 unsigned int types
= Disp
;
4706 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4708 as_bad (_("at most %d displacement operands are allowed"),
4709 MAX_MEMORY_OPERANDS
);
4713 if ((i
.types
[this_operand
] & JumpAbsolute
)
4714 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4717 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4721 /* For PC-relative branches, the width of the displacement
4722 is dependent upon data size, not address size. */
4724 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4726 if (flag_code
== CODE_64BIT
)
4729 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4731 : Disp32S
| Disp32
);
4733 bigdisp
= Disp64
| Disp32S
| Disp32
;
4740 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4742 : LONG_MNEM_SUFFIX
));
4745 if ((flag_code
== CODE_16BIT
) ^ override
)
4748 i
.types
[this_operand
] |= bigdisp
;
4750 exp
= &disp_expressions
[i
.disp_operands
];
4751 i
.op
[this_operand
].disps
= exp
;
4753 save_input_line_pointer
= input_line_pointer
;
4754 input_line_pointer
= disp_start
;
4755 END_STRING_AND_SAVE (disp_end
);
4757 #ifndef GCC_ASM_O_HACK
4758 #define GCC_ASM_O_HACK 0
4761 END_STRING_AND_SAVE (disp_end
+ 1);
4762 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4763 && displacement_string_end
[-1] == '+')
4765 /* This hack is to avoid a warning when using the "o"
4766 constraint within gcc asm statements.
4769 #define _set_tssldt_desc(n,addr,limit,type) \
4770 __asm__ __volatile__ ( \
4772 "movw %w1,2+%0\n\t" \
4774 "movb %b1,4+%0\n\t" \
4775 "movb %4,5+%0\n\t" \
4776 "movb $0,6+%0\n\t" \
4777 "movb %h1,7+%0\n\t" \
4779 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4781 This works great except that the output assembler ends
4782 up looking a bit weird if it turns out that there is
4783 no offset. You end up producing code that looks like:
4796 So here we provide the missing zero. */
4798 *displacement_string_end
= '0';
4801 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4802 if (gotfree_input_line
)
4803 input_line_pointer
= gotfree_input_line
;
4805 exp_seg
= expression (exp
);
4808 if (*input_line_pointer
)
4809 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4811 RESTORE_END_STRING (disp_end
+ 1);
4813 RESTORE_END_STRING (disp_end
);
4814 input_line_pointer
= save_input_line_pointer
;
4815 if (gotfree_input_line
)
4816 free (gotfree_input_line
);
4818 /* We do this to make sure that the section symbol is in
4819 the symbol table. We will ultimately change the relocation
4820 to be relative to the beginning of the section. */
4821 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4822 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4823 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4825 if (exp
->X_op
!= O_symbol
)
4827 as_bad (_("bad expression used with @%s"),
4828 (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4834 if (S_IS_LOCAL (exp
->X_add_symbol
)
4835 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4836 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4837 exp
->X_op
= O_subtract
;
4838 exp
->X_op_symbol
= GOT_symbol
;
4839 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4840 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4841 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4842 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4844 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4847 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
4849 /* Missing or bad expr becomes absolute 0. */
4850 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4852 exp
->X_op
= O_constant
;
4853 exp
->X_add_number
= 0;
4854 exp
->X_add_symbol
= (symbolS
*) 0;
4855 exp
->X_op_symbol
= (symbolS
*) 0;
4858 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4859 if (exp
->X_op
!= O_constant
4860 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4861 && exp_seg
!= absolute_section
4862 && exp_seg
!= text_section
4863 && exp_seg
!= data_section
4864 && exp_seg
!= bss_section
4865 && exp_seg
!= undefined_section
4866 && !bfd_is_com_section (exp_seg
))
4868 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4873 if (!(i
.types
[this_operand
] & ~Disp
))
4874 i
.types
[this_operand
] &= types
;
4879 /* Make sure the memory operand we've been dealt is valid.
4880 Return 1 on success, 0 on a failure. */
4883 i386_index_check (const char *operand_string
)
4886 #if INFER_ADDR_PREFIX
4892 if ((current_templates
->start
->cpu_flags
& CpuSVME
)
4893 && current_templates
->end
[-1].operand_types
[0] == AnyMem
)
4895 /* Memory operands of SVME insns are special in that they only allow
4896 rAX as their memory address and ignore any segment override. */
4899 /* SKINIT is even more restrictive: it always requires EAX. */
4900 if (strcmp (current_templates
->start
->name
, "skinit") == 0)
4902 else if (flag_code
== CODE_64BIT
)
4903 RegXX
= i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
;
4905 RegXX
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0)
4909 || !(i
.base_reg
->reg_type
& Acc
)
4910 || !(i
.base_reg
->reg_type
& RegXX
)
4912 || (i
.types
[0] & Disp
))
4915 else if (flag_code
== CODE_64BIT
)
4917 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4920 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4921 && (i
.base_reg
->reg_type
!= BaseIndex
4924 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4925 != (RegXX
| BaseIndex
))))
4930 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4934 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
| RegRex
))
4935 != (Reg16
| BaseIndex
)))
4937 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
4938 != (Reg16
| BaseIndex
))
4940 && i
.base_reg
->reg_num
< 6
4941 && i
.index_reg
->reg_num
>= 6
4942 && i
.log2_scale_factor
== 0))))
4949 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
4951 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
| RegRex
))
4952 != (Reg32
| BaseIndex
))))
4958 #if INFER_ADDR_PREFIX
4959 if (i
.prefix
[ADDR_PREFIX
] == 0)
4961 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
4963 /* Change the size of any displacement too. At most one of
4964 Disp16 or Disp32 is set.
4965 FIXME. There doesn't seem to be any real need for separate
4966 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4967 Removing them would probably clean up the code quite a lot. */
4968 if (flag_code
!= CODE_64BIT
4969 && (i
.types
[this_operand
] & (Disp16
| Disp32
)))
4970 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
4975 as_bad (_("`%s' is not a valid base/index expression"),
4979 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4981 flag_code_names
[flag_code
]);
4986 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4990 i386_operand (char *operand_string
)
4994 char *op_string
= operand_string
;
4996 if (is_space_char (*op_string
))
4999 /* We check for an absolute prefix (differentiating,
5000 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
5001 if (*op_string
== ABSOLUTE_PREFIX
)
5004 if (is_space_char (*op_string
))
5006 i
.types
[this_operand
] |= JumpAbsolute
;
5009 /* Check if operand is a register. */
5010 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
5012 /* Check for a segment override by searching for ':' after a
5013 segment register. */
5015 if (is_space_char (*op_string
))
5017 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
5022 i
.seg
[i
.mem_operands
] = &es
;
5025 i
.seg
[i
.mem_operands
] = &cs
;
5028 i
.seg
[i
.mem_operands
] = &ss
;
5031 i
.seg
[i
.mem_operands
] = &ds
;
5034 i
.seg
[i
.mem_operands
] = &fs
;
5037 i
.seg
[i
.mem_operands
] = &gs
;
5041 /* Skip the ':' and whitespace. */
5043 if (is_space_char (*op_string
))
5046 if (!is_digit_char (*op_string
)
5047 && !is_identifier_char (*op_string
)
5048 && *op_string
!= '('
5049 && *op_string
!= ABSOLUTE_PREFIX
)
5051 as_bad (_("bad memory operand `%s'"), op_string
);
5054 /* Handle case of %es:*foo. */
5055 if (*op_string
== ABSOLUTE_PREFIX
)
5058 if (is_space_char (*op_string
))
5060 i
.types
[this_operand
] |= JumpAbsolute
;
5062 goto do_memory_reference
;
5066 as_bad (_("junk `%s' after register"), op_string
);
5069 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5070 i
.op
[this_operand
].regs
= r
;
5073 else if (*op_string
== REGISTER_PREFIX
)
5075 as_bad (_("bad register name `%s'"), op_string
);
5078 else if (*op_string
== IMMEDIATE_PREFIX
)
5081 if (i
.types
[this_operand
] & JumpAbsolute
)
5083 as_bad (_("immediate operand illegal with absolute jump"));
5086 if (!i386_immediate (op_string
))
5089 else if (is_digit_char (*op_string
)
5090 || is_identifier_char (*op_string
)
5091 || *op_string
== '(')
5093 /* This is a memory reference of some sort. */
5096 /* Start and end of displacement string expression (if found). */
5097 char *displacement_string_start
;
5098 char *displacement_string_end
;
5100 do_memory_reference
:
5101 if ((i
.mem_operands
== 1
5102 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5103 || i
.mem_operands
== 2)
5105 as_bad (_("too many memory references for `%s'"),
5106 current_templates
->start
->name
);
5110 /* Check for base index form. We detect the base index form by
5111 looking for an ')' at the end of the operand, searching
5112 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5114 base_string
= op_string
+ strlen (op_string
);
5117 if (is_space_char (*base_string
))
5120 /* If we only have a displacement, set-up for it to be parsed later. */
5121 displacement_string_start
= op_string
;
5122 displacement_string_end
= base_string
+ 1;
5124 if (*base_string
== ')')
5127 unsigned int parens_balanced
= 1;
5128 /* We've already checked that the number of left & right ()'s are
5129 equal, so this loop will not be infinite. */
5133 if (*base_string
== ')')
5135 if (*base_string
== '(')
5138 while (parens_balanced
);
5140 temp_string
= base_string
;
5142 /* Skip past '(' and whitespace. */
5144 if (is_space_char (*base_string
))
5147 if (*base_string
== ','
5148 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5151 displacement_string_end
= temp_string
;
5153 i
.types
[this_operand
] |= BaseIndex
;
5157 base_string
= end_op
;
5158 if (is_space_char (*base_string
))
5162 /* There may be an index reg or scale factor here. */
5163 if (*base_string
== ',')
5166 if (is_space_char (*base_string
))
5169 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5172 base_string
= end_op
;
5173 if (is_space_char (*base_string
))
5175 if (*base_string
== ',')
5178 if (is_space_char (*base_string
))
5181 else if (*base_string
!= ')')
5183 as_bad (_("expecting `,' or `)' "
5184 "after index register in `%s'"),
5189 else if (*base_string
== REGISTER_PREFIX
)
5191 as_bad (_("bad register name `%s'"), base_string
);
5195 /* Check for scale factor. */
5196 if (*base_string
!= ')')
5198 char *end_scale
= i386_scale (base_string
);
5203 base_string
= end_scale
;
5204 if (is_space_char (*base_string
))
5206 if (*base_string
!= ')')
5208 as_bad (_("expecting `)' "
5209 "after scale factor in `%s'"),
5214 else if (!i
.index_reg
)
5216 as_bad (_("expecting index register or scale factor "
5217 "after `,'; got '%c'"),
5222 else if (*base_string
!= ')')
5224 as_bad (_("expecting `,' or `)' "
5225 "after base register in `%s'"),
5230 else if (*base_string
== REGISTER_PREFIX
)
5232 as_bad (_("bad register name `%s'"), base_string
);
5237 /* If there's an expression beginning the operand, parse it,
5238 assuming displacement_string_start and
5239 displacement_string_end are meaningful. */
5240 if (displacement_string_start
!= displacement_string_end
)
5242 if (!i386_displacement (displacement_string_start
,
5243 displacement_string_end
))
5247 /* Special case for (%dx) while doing input/output op. */
5249 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5251 && i
.log2_scale_factor
== 0
5252 && i
.seg
[i
.mem_operands
] == 0
5253 && (i
.types
[this_operand
] & Disp
) == 0)
5255 i
.types
[this_operand
] = InOutPortReg
;
5259 if (i386_index_check (operand_string
) == 0)
5265 /* It's not a memory operand; argh! */
5266 as_bad (_("invalid char %s beginning operand %d `%s'"),
5267 output_invalid (*op_string
),
5272 return 1; /* Normal return. */
5275 /* md_estimate_size_before_relax()
5277 Called just before relax() for rs_machine_dependent frags. The x86
5278 assembler uses these frags to handle variable size jump
5281 Any symbol that is now undefined will not become defined.
5282 Return the correct fr_subtype in the frag.
5283 Return the initial "guess for variable size of frag" to caller.
5284 The guess is actually the growth beyond the fixed part. Whatever
5285 we do to grow the fixed or variable part contributes to our
5289 md_estimate_size_before_relax (fragP
, segment
)
5293 /* We've already got fragP->fr_subtype right; all we have to do is
5294 check for un-relaxable symbols. On an ELF system, we can't relax
5295 an externally visible symbol, because it may be overridden by a
5297 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5300 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5301 || S_IS_WEAK (fragP
->fr_symbol
)))
5305 /* Symbol is undefined in this segment, or we need to keep a
5306 reloc so that weak symbols can be overridden. */
5307 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5308 enum bfd_reloc_code_real reloc_type
;
5309 unsigned char *opcode
;
5312 if (fragP
->fr_var
!= NO_RELOC
)
5313 reloc_type
= fragP
->fr_var
;
5315 reloc_type
= BFD_RELOC_16_PCREL
;
5317 reloc_type
= BFD_RELOC_32_PCREL
;
5319 old_fr_fix
= fragP
->fr_fix
;
5320 opcode
= (unsigned char *) fragP
->fr_opcode
;
5322 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5325 /* Make jmp (0xeb) a (d)word displacement jump. */
5327 fragP
->fr_fix
+= size
;
5328 fix_new (fragP
, old_fr_fix
, size
,
5330 fragP
->fr_offset
, 1,
5336 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5338 /* Negate the condition, and branch past an
5339 unconditional jump. */
5342 /* Insert an unconditional jump. */
5344 /* We added two extra opcode bytes, and have a two byte
5346 fragP
->fr_fix
+= 2 + 2;
5347 fix_new (fragP
, old_fr_fix
+ 2, 2,
5349 fragP
->fr_offset
, 1,
5356 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5361 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5363 fragP
->fr_offset
, 1,
5365 fixP
->fx_signed
= 1;
5369 /* This changes the byte-displacement jump 0x7N
5370 to the (d)word-displacement jump 0x0f,0x8N. */
5371 opcode
[1] = opcode
[0] + 0x10;
5372 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5373 /* We've added an opcode byte. */
5374 fragP
->fr_fix
+= 1 + size
;
5375 fix_new (fragP
, old_fr_fix
+ 1, size
,
5377 fragP
->fr_offset
, 1,
5382 BAD_CASE (fragP
->fr_subtype
);
5386 return fragP
->fr_fix
- old_fr_fix
;
5389 /* Guess size depending on current relax state. Initially the relax
5390 state will correspond to a short jump and we return 1, because
5391 the variable part of the frag (the branch offset) is one byte
5392 long. However, we can relax a section more than once and in that
5393 case we must either set fr_subtype back to the unrelaxed state,
5394 or return the value for the appropriate branch. */
5395 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5398 /* Called after relax() is finished.
5400 In: Address of frag.
5401 fr_type == rs_machine_dependent.
5402 fr_subtype is what the address relaxed to.
5404 Out: Any fixSs and constants are set up.
5405 Caller will turn frag into a ".space 0". */
5408 md_convert_frag (abfd
, sec
, fragP
)
5409 bfd
*abfd ATTRIBUTE_UNUSED
;
5410 segT sec ATTRIBUTE_UNUSED
;
5413 unsigned char *opcode
;
5414 unsigned char *where_to_put_displacement
= NULL
;
5415 offsetT target_address
;
5416 offsetT opcode_address
;
5417 unsigned int extension
= 0;
5418 offsetT displacement_from_opcode_start
;
5420 opcode
= (unsigned char *) fragP
->fr_opcode
;
5422 /* Address we want to reach in file space. */
5423 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5425 /* Address opcode resides at in file space. */
5426 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5428 /* Displacement from opcode start to fill into instruction. */
5429 displacement_from_opcode_start
= target_address
- opcode_address
;
5431 if ((fragP
->fr_subtype
& BIG
) == 0)
5433 /* Don't have to change opcode. */
5434 extension
= 1; /* 1 opcode + 1 displacement */
5435 where_to_put_displacement
= &opcode
[1];
5439 if (no_cond_jump_promotion
5440 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5441 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5442 _("long jump required"));
5444 switch (fragP
->fr_subtype
)
5446 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5447 extension
= 4; /* 1 opcode + 4 displacement */
5449 where_to_put_displacement
= &opcode
[1];
5452 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5453 extension
= 2; /* 1 opcode + 2 displacement */
5455 where_to_put_displacement
= &opcode
[1];
5458 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5459 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5460 extension
= 5; /* 2 opcode + 4 displacement */
5461 opcode
[1] = opcode
[0] + 0x10;
5462 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5463 where_to_put_displacement
= &opcode
[2];
5466 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5467 extension
= 3; /* 2 opcode + 2 displacement */
5468 opcode
[1] = opcode
[0] + 0x10;
5469 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5470 where_to_put_displacement
= &opcode
[2];
5473 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5478 where_to_put_displacement
= &opcode
[3];
5482 BAD_CASE (fragP
->fr_subtype
);
5487 /* If size if less then four we are sure that the operand fits,
5488 but if it's 4, then it could be that the displacement is larger
5490 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5492 && ((addressT
) (displacement_from_opcode_start
- extension
5493 + ((addressT
) 1 << 31))
5494 > (((addressT
) 2 << 31) - 1)))
5496 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5497 _("jump target out of range"));
5498 /* Make us emit 0. */
5499 displacement_from_opcode_start
= extension
;
5501 /* Now put displacement after opcode. */
5502 md_number_to_chars ((char *) where_to_put_displacement
,
5503 (valueT
) (displacement_from_opcode_start
- extension
),
5504 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5505 fragP
->fr_fix
+= extension
;
5508 /* Size of byte displacement jmp. */
5509 int md_short_jump_size
= 2;
5511 /* Size of dword displacement jmp. */
5512 int md_long_jump_size
= 5;
5515 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5517 addressT from_addr
, to_addr
;
5518 fragS
*frag ATTRIBUTE_UNUSED
;
5519 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5523 offset
= to_addr
- (from_addr
+ 2);
5524 /* Opcode for byte-disp jump. */
5525 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5526 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5530 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5532 addressT from_addr
, to_addr
;
5533 fragS
*frag ATTRIBUTE_UNUSED
;
5534 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5538 offset
= to_addr
- (from_addr
+ 5);
5539 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5540 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5543 /* Apply a fixup (fixS) to segment data, once it has been determined
5544 by our caller that we have all the info we need to fix it up.
5546 On the 386, immediates, displacements, and data pointers are all in
5547 the same (little-endian) format, so we don't need to care about which
5551 md_apply_fix (fixP
, valP
, seg
)
5552 /* The fix we're to put in. */
5554 /* Pointer to the value of the bits. */
5556 /* Segment fix is from. */
5557 segT seg ATTRIBUTE_UNUSED
;
5559 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5560 valueT value
= *valP
;
5562 #if !defined (TE_Mach)
5565 switch (fixP
->fx_r_type
)
5571 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5574 case BFD_RELOC_X86_64_32S
:
5575 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5578 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5581 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5586 if (fixP
->fx_addsy
!= NULL
5587 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5588 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5589 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5590 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5591 && !use_rela_relocations
)
5593 /* This is a hack. There should be a better way to handle this.
5594 This covers for the fact that bfd_install_relocation will
5595 subtract the current location (for partial_inplace, PC relative
5596 relocations); see more below. */
5600 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5603 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5608 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5611 || (symbol_section_p (fixP
->fx_addsy
)
5612 && sym_seg
!= absolute_section
))
5613 && !generic_force_reloc (fixP
))
5615 /* Yes, we add the values in twice. This is because
5616 bfd_install_relocation subtracts them out again. I think
5617 bfd_install_relocation is broken, but I don't dare change
5619 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5623 #if defined (OBJ_COFF) && defined (TE_PE)
5624 /* For some reason, the PE format does not store a
5625 section address offset for a PC relative symbol. */
5626 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5627 || S_IS_WEAK (fixP
->fx_addsy
))
5628 value
+= md_pcrel_from (fixP
);
5632 /* Fix a few things - the dynamic linker expects certain values here,
5633 and we must not disappoint it. */
5634 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5635 if (IS_ELF
&& fixP
->fx_addsy
)
5636 switch (fixP
->fx_r_type
)
5638 case BFD_RELOC_386_PLT32
:
5639 case BFD_RELOC_X86_64_PLT32
:
5640 /* Make the jump instruction point to the address of the operand. At
5641 runtime we merely add the offset to the actual PLT entry. */
5645 case BFD_RELOC_386_TLS_GD
:
5646 case BFD_RELOC_386_TLS_LDM
:
5647 case BFD_RELOC_386_TLS_IE_32
:
5648 case BFD_RELOC_386_TLS_IE
:
5649 case BFD_RELOC_386_TLS_GOTIE
:
5650 case BFD_RELOC_386_TLS_GOTDESC
:
5651 case BFD_RELOC_X86_64_TLSGD
:
5652 case BFD_RELOC_X86_64_TLSLD
:
5653 case BFD_RELOC_X86_64_GOTTPOFF
:
5654 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5655 value
= 0; /* Fully resolved at runtime. No addend. */
5657 case BFD_RELOC_386_TLS_LE
:
5658 case BFD_RELOC_386_TLS_LDO_32
:
5659 case BFD_RELOC_386_TLS_LE_32
:
5660 case BFD_RELOC_X86_64_DTPOFF32
:
5661 case BFD_RELOC_X86_64_DTPOFF64
:
5662 case BFD_RELOC_X86_64_TPOFF32
:
5663 case BFD_RELOC_X86_64_TPOFF64
:
5664 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5667 case BFD_RELOC_386_TLS_DESC_CALL
:
5668 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5669 value
= 0; /* Fully resolved at runtime. No addend. */
5670 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5674 case BFD_RELOC_386_GOT32
:
5675 case BFD_RELOC_X86_64_GOT32
:
5676 value
= 0; /* Fully resolved at runtime. No addend. */
5679 case BFD_RELOC_VTABLE_INHERIT
:
5680 case BFD_RELOC_VTABLE_ENTRY
:
5687 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5689 #endif /* !defined (TE_Mach) */
5691 /* Are we finished with this relocation now? */
5692 if (fixP
->fx_addsy
== NULL
)
5694 else if (use_rela_relocations
)
5696 fixP
->fx_no_overflow
= 1;
5697 /* Remember value for tc_gen_reloc. */
5698 fixP
->fx_addnumber
= value
;
5702 md_number_to_chars (p
, value
, fixP
->fx_size
);
5705 #define MAX_LITTLENUMS 6
5707 /* Turn the string pointed to by litP into a floating point constant
5708 of type TYPE, and emit the appropriate bytes. The number of
5709 LITTLENUMS emitted is stored in *SIZEP. An error message is
5710 returned, or NULL on OK. */
5713 md_atof (type
, litP
, sizeP
)
5719 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5720 LITTLENUM_TYPE
*wordP
;
5742 return _("Bad call to md_atof ()");
5744 t
= atof_ieee (input_line_pointer
, type
, words
);
5746 input_line_pointer
= t
;
5748 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5749 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5750 the bigendian 386. */
5751 for (wordP
= words
+ prec
- 1; prec
--;)
5753 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5754 litP
+= sizeof (LITTLENUM_TYPE
);
5759 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5762 output_invalid (int c
)
5765 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5768 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5769 "(0x%x)", (unsigned char) c
);
5770 return output_invalid_buf
;
5773 /* REG_STRING starts *before* REGISTER_PREFIX. */
5775 static const reg_entry
*
5776 parse_real_register (char *reg_string
, char **end_op
)
5778 char *s
= reg_string
;
5780 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5783 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5784 if (*s
== REGISTER_PREFIX
)
5787 if (is_space_char (*s
))
5791 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5793 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5794 return (const reg_entry
*) NULL
;
5798 /* For naked regs, make sure that we are not dealing with an identifier.
5799 This prevents confusing an identifier like `eax_var' with register
5801 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5802 return (const reg_entry
*) NULL
;
5806 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5808 /* Handle floating point regs, allowing spaces in the (i) part. */
5809 if (r
== i386_regtab
/* %st is first entry of table */)
5811 if (is_space_char (*s
))
5816 if (is_space_char (*s
))
5818 if (*s
>= '0' && *s
<= '7')
5822 if (is_space_char (*s
))
5827 r
= hash_find (reg_hash
, "st(0)");
5832 /* We have "%st(" then garbage. */
5833 return (const reg_entry
*) NULL
;
5838 && ((r
->reg_flags
& (RegRex64
| RegRex
)) | (r
->reg_type
& Reg64
)) != 0
5839 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5840 && flag_code
!= CODE_64BIT
)
5841 return (const reg_entry
*) NULL
;
5846 /* REG_STRING starts *before* REGISTER_PREFIX. */
5848 static const reg_entry
*
5849 parse_register (char *reg_string
, char **end_op
)
5853 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5854 r
= parse_real_register (reg_string
, end_op
);
5859 char *save
= input_line_pointer
;
5863 input_line_pointer
= reg_string
;
5864 c
= get_symbol_end ();
5865 symbolP
= symbol_find (reg_string
);
5866 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5868 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5870 know (e
->X_op
== O_register
);
5871 know (e
->X_add_number
>= 0
5872 && (valueT
) e
->X_add_number
< i386_regtab_size
);
5873 r
= i386_regtab
+ e
->X_add_number
;
5874 *end_op
= input_line_pointer
;
5876 *input_line_pointer
= c
;
5877 input_line_pointer
= save
;
5883 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5886 char *end
= input_line_pointer
;
5889 r
= parse_register (name
, &input_line_pointer
);
5890 if (r
&& end
<= input_line_pointer
)
5892 *nextcharP
= *input_line_pointer
;
5893 *input_line_pointer
= 0;
5894 e
->X_op
= O_register
;
5895 e
->X_add_number
= r
- i386_regtab
;
5898 input_line_pointer
= end
;
5904 md_operand (expressionS
*e
)
5906 if (*input_line_pointer
== REGISTER_PREFIX
)
5909 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5913 e
->X_op
= O_register
;
5914 e
->X_add_number
= r
- i386_regtab
;
5915 input_line_pointer
= end
;
5921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5922 const char *md_shortopts
= "kVQ:sqn";
5924 const char *md_shortopts
= "qn";
5927 #define OPTION_32 (OPTION_MD_BASE + 0)
5928 #define OPTION_64 (OPTION_MD_BASE + 1)
5929 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5930 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5931 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5933 struct option md_longopts
[] =
5935 {"32", no_argument
, NULL
, OPTION_32
},
5936 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5937 {"64", no_argument
, NULL
, OPTION_64
},
5939 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
5940 {"march", required_argument
, NULL
, OPTION_MARCH
},
5941 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
5942 {NULL
, no_argument
, NULL
, 0}
5944 size_t md_longopts_size
= sizeof (md_longopts
);
5947 md_parse_option (int c
, char *arg
)
5954 optimize_align_code
= 0;
5961 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5962 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5963 should be emitted or not. FIXME: Not implemented. */
5967 /* -V: SVR4 argument to print version ID. */
5969 print_version_id ();
5972 /* -k: Ignore for FreeBSD compatibility. */
5977 /* -s: On i386 Solaris, this tells the native assembler to use
5978 .stab instead of .stab.excl. We always use .stab anyhow. */
5981 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
5984 const char **list
, **l
;
5986 list
= bfd_target_list ();
5987 for (l
= list
; *l
!= NULL
; l
++)
5988 if (CONST_STRNEQ (*l
, "elf64-x86-64")
5989 || strcmp (*l
, "coff-x86-64") == 0
5990 || strcmp (*l
, "pe-x86-64") == 0
5991 || strcmp (*l
, "pei-x86-64") == 0)
5993 default_arch
= "x86_64";
5997 as_fatal (_("No compiled in support for x86_64"));
6004 default_arch
= "i386";
6008 #ifdef SVR4_COMMENT_CHARS
6013 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
6015 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
6019 i386_comment_chars
= n
;
6026 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6027 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6029 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6031 cpu_arch_isa
= cpu_arch
[i
].type
;
6032 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
6033 if (!cpu_arch_tune_set
)
6035 cpu_arch_tune
= cpu_arch_isa
;
6036 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
6041 if (i
>= ARRAY_SIZE (cpu_arch
))
6042 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6047 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6048 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6050 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6052 cpu_arch_tune_set
= 1;
6053 cpu_arch_tune
= cpu_arch
[i
].type
;
6054 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
6058 if (i
>= ARRAY_SIZE (cpu_arch
))
6059 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6069 md_show_usage (stream
)
6072 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6073 fprintf (stream
, _("\
6075 -V print assembler version number\n\
6078 fprintf (stream
, _("\
6079 -n Do not optimize code alignment\n\
6080 -q quieten some warnings\n"));
6081 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6082 fprintf (stream
, _("\
6085 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6086 fprintf (stream
, _("\
6087 --32/--64 generate 32bit/64bit code\n"));
6089 #ifdef SVR4_COMMENT_CHARS
6090 fprintf (stream
, _("\
6091 --divide do not treat `/' as a comment character\n"));
6093 fprintf (stream
, _("\
6094 --divide ignored\n"));
6096 fprintf (stream
, _("\
6097 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6098 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6099 core, core2, k6, athlon, k8, generic32, generic64\n"));
6105 x86_64_target_format (void)
6107 if (strcmp (default_arch
, "x86_64") == 0)
6109 set_code_flag (CODE_64BIT
);
6110 return COFF_TARGET_FORMAT
;
6112 else if (strcmp (default_arch
, "i386") == 0)
6114 set_code_flag (CODE_32BIT
);
6118 as_fatal (_("Unknown architecture"));
6123 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6124 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6126 /* Pick the target format to use. */
6129 i386_target_format (void)
6131 if (!strcmp (default_arch
, "x86_64"))
6133 set_code_flag (CODE_64BIT
);
6134 if (cpu_arch_isa_flags
== 0)
6135 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6136 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6138 if (cpu_arch_tune_flags
== 0)
6139 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6140 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6143 else if (!strcmp (default_arch
, "i386"))
6145 set_code_flag (CODE_32BIT
);
6146 if (cpu_arch_isa_flags
== 0)
6147 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6148 if (cpu_arch_tune_flags
== 0)
6149 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6152 as_fatal (_("Unknown architecture"));
6153 switch (OUTPUT_FLAVOR
)
6155 #ifdef OBJ_MAYBE_AOUT
6156 case bfd_target_aout_flavour
:
6157 return AOUT_TARGET_FORMAT
;
6159 #ifdef OBJ_MAYBE_COFF
6160 case bfd_target_coff_flavour
:
6163 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6164 case bfd_target_elf_flavour
:
6166 if (flag_code
== CODE_64BIT
)
6169 use_rela_relocations
= 1;
6171 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6180 #endif /* OBJ_MAYBE_ more than one */
6182 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6184 i386_elf_emit_arch_note (void)
6186 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6189 asection
*seg
= now_seg
;
6190 subsegT subseg
= now_subseg
;
6191 Elf_Internal_Note i_note
;
6192 Elf_External_Note e_note
;
6193 asection
*note_secp
;
6196 /* Create the .note section. */
6197 note_secp
= subseg_new (".note", 0);
6198 bfd_set_section_flags (stdoutput
,
6200 SEC_HAS_CONTENTS
| SEC_READONLY
);
6202 /* Process the arch string. */
6203 len
= strlen (cpu_arch_name
);
6205 i_note
.namesz
= len
+ 1;
6207 i_note
.type
= NT_ARCH
;
6208 p
= frag_more (sizeof (e_note
.namesz
));
6209 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6210 p
= frag_more (sizeof (e_note
.descsz
));
6211 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6212 p
= frag_more (sizeof (e_note
.type
));
6213 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6214 p
= frag_more (len
+ 1);
6215 strcpy (p
, cpu_arch_name
);
6217 frag_align (2, 0, 0);
6219 subseg_set (seg
, subseg
);
6225 md_undefined_symbol (name
)
6228 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6229 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6230 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6231 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6235 if (symbol_find (name
))
6236 as_bad (_("GOT already in symbol table"));
6237 GOT_symbol
= symbol_new (name
, undefined_section
,
6238 (valueT
) 0, &zero_address_frag
);
6245 /* Round up a section size to the appropriate boundary. */
6248 md_section_align (segment
, size
)
6249 segT segment ATTRIBUTE_UNUSED
;
6252 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6253 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6255 /* For a.out, force the section size to be aligned. If we don't do
6256 this, BFD will align it for us, but it will not write out the
6257 final bytes of the section. This may be a bug in BFD, but it is
6258 easier to fix it here since that is how the other a.out targets
6262 align
= bfd_get_section_alignment (stdoutput
, segment
);
6263 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6270 /* On the i386, PC-relative offsets are relative to the start of the
6271 next instruction. That is, the address of the offset, plus its
6272 size, since the offset is always the last part of the insn. */
6275 md_pcrel_from (fixS
*fixP
)
6277 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6283 s_bss (int ignore ATTRIBUTE_UNUSED
)
6287 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6289 obj_elf_section_change_hook ();
6291 temp
= get_absolute_expression ();
6292 subseg_set (bss_section
, (subsegT
) temp
);
6293 demand_empty_rest_of_line ();
6299 i386_validate_fix (fixS
*fixp
)
6301 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6303 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6307 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6312 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6314 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6321 tc_gen_reloc (section
, fixp
)
6322 asection
*section ATTRIBUTE_UNUSED
;
6326 bfd_reloc_code_real_type code
;
6328 switch (fixp
->fx_r_type
)
6330 case BFD_RELOC_X86_64_PLT32
:
6331 case BFD_RELOC_X86_64_GOT32
:
6332 case BFD_RELOC_X86_64_GOTPCREL
:
6333 case BFD_RELOC_386_PLT32
:
6334 case BFD_RELOC_386_GOT32
:
6335 case BFD_RELOC_386_GOTOFF
:
6336 case BFD_RELOC_386_GOTPC
:
6337 case BFD_RELOC_386_TLS_GD
:
6338 case BFD_RELOC_386_TLS_LDM
:
6339 case BFD_RELOC_386_TLS_LDO_32
:
6340 case BFD_RELOC_386_TLS_IE_32
:
6341 case BFD_RELOC_386_TLS_IE
:
6342 case BFD_RELOC_386_TLS_GOTIE
:
6343 case BFD_RELOC_386_TLS_LE_32
:
6344 case BFD_RELOC_386_TLS_LE
:
6345 case BFD_RELOC_386_TLS_GOTDESC
:
6346 case BFD_RELOC_386_TLS_DESC_CALL
:
6347 case BFD_RELOC_X86_64_TLSGD
:
6348 case BFD_RELOC_X86_64_TLSLD
:
6349 case BFD_RELOC_X86_64_DTPOFF32
:
6350 case BFD_RELOC_X86_64_DTPOFF64
:
6351 case BFD_RELOC_X86_64_GOTTPOFF
:
6352 case BFD_RELOC_X86_64_TPOFF32
:
6353 case BFD_RELOC_X86_64_TPOFF64
:
6354 case BFD_RELOC_X86_64_GOTOFF64
:
6355 case BFD_RELOC_X86_64_GOTPC32
:
6356 case BFD_RELOC_X86_64_GOT64
:
6357 case BFD_RELOC_X86_64_GOTPCREL64
:
6358 case BFD_RELOC_X86_64_GOTPC64
:
6359 case BFD_RELOC_X86_64_GOTPLT64
:
6360 case BFD_RELOC_X86_64_PLTOFF64
:
6361 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6362 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6364 case BFD_RELOC_VTABLE_ENTRY
:
6365 case BFD_RELOC_VTABLE_INHERIT
:
6367 case BFD_RELOC_32_SECREL
:
6369 code
= fixp
->fx_r_type
;
6371 case BFD_RELOC_X86_64_32S
:
6372 if (!fixp
->fx_pcrel
)
6374 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6375 code
= fixp
->fx_r_type
;
6381 switch (fixp
->fx_size
)
6384 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6385 _("can not do %d byte pc-relative relocation"),
6387 code
= BFD_RELOC_32_PCREL
;
6389 case 1: code
= BFD_RELOC_8_PCREL
; break;
6390 case 2: code
= BFD_RELOC_16_PCREL
; break;
6391 case 4: code
= BFD_RELOC_32_PCREL
; break;
6393 case 8: code
= BFD_RELOC_64_PCREL
; break;
6399 switch (fixp
->fx_size
)
6402 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6403 _("can not do %d byte relocation"),
6405 code
= BFD_RELOC_32
;
6407 case 1: code
= BFD_RELOC_8
; break;
6408 case 2: code
= BFD_RELOC_16
; break;
6409 case 4: code
= BFD_RELOC_32
; break;
6411 case 8: code
= BFD_RELOC_64
; break;
6418 if ((code
== BFD_RELOC_32
6419 || code
== BFD_RELOC_32_PCREL
6420 || code
== BFD_RELOC_X86_64_32S
)
6422 && fixp
->fx_addsy
== GOT_symbol
)
6425 code
= BFD_RELOC_386_GOTPC
;
6427 code
= BFD_RELOC_X86_64_GOTPC32
;
6429 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6431 && fixp
->fx_addsy
== GOT_symbol
)
6433 code
= BFD_RELOC_X86_64_GOTPC64
;
6436 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6437 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6438 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6440 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6442 if (!use_rela_relocations
)
6444 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6445 vtable entry to be used in the relocation's section offset. */
6446 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6447 rel
->address
= fixp
->fx_offset
;
6451 /* Use the rela in 64bit mode. */
6454 if (!fixp
->fx_pcrel
)
6455 rel
->addend
= fixp
->fx_offset
;
6459 case BFD_RELOC_X86_64_PLT32
:
6460 case BFD_RELOC_X86_64_GOT32
:
6461 case BFD_RELOC_X86_64_GOTPCREL
:
6462 case BFD_RELOC_X86_64_TLSGD
:
6463 case BFD_RELOC_X86_64_TLSLD
:
6464 case BFD_RELOC_X86_64_GOTTPOFF
:
6465 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6466 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6467 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6470 rel
->addend
= (section
->vma
6472 + fixp
->fx_addnumber
6473 + md_pcrel_from (fixp
));
6478 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6479 if (rel
->howto
== NULL
)
6481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6482 _("cannot represent relocation type %s"),
6483 bfd_get_reloc_code_name (code
));
6484 /* Set howto to a garbage value so that we can keep going. */
6485 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6486 assert (rel
->howto
!= NULL
);
6493 /* Parse operands using Intel syntax. This implements a recursive descent
6494 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6497 FIXME: We do not recognize the full operand grammar defined in the MASM
6498 documentation. In particular, all the structure/union and
6499 high-level macro operands are missing.
6501 Uppercase words are terminals, lower case words are non-terminals.
6502 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6503 bars '|' denote choices. Most grammar productions are implemented in
6504 functions called 'intel_<production>'.
6506 Initial production is 'expr'.
6512 binOp & | AND | \| | OR | ^ | XOR
6514 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6516 constant digits [[ radixOverride ]]
6518 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6556 => expr expr cmpOp e04
6559 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6560 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6562 hexdigit a | b | c | d | e | f
6563 | A | B | C | D | E | F
6569 mulOp * | / | % | MOD | << | SHL | >> | SHR
6573 register specialRegister
6577 segmentRegister CS | DS | ES | FS | GS | SS
6579 specialRegister CR0 | CR2 | CR3 | CR4
6580 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6581 | TR3 | TR4 | TR5 | TR6 | TR7
6583 We simplify the grammar in obvious places (e.g., register parsing is
6584 done by calling parse_register) and eliminate immediate left recursion
6585 to implement a recursive-descent parser.
6589 expr' cmpOp e04 expr'
6640 /* Parsing structure for the intel syntax parser. Used to implement the
6641 semantic actions for the operand grammar. */
6642 struct intel_parser_s
6644 char *op_string
; /* The string being parsed. */
6645 int got_a_float
; /* Whether the operand is a float. */
6646 int op_modifier
; /* Operand modifier. */
6647 int is_mem
; /* 1 if operand is memory reference. */
6648 int in_offset
; /* >=1 if parsing operand of offset. */
6649 int in_bracket
; /* >=1 if parsing operand in brackets. */
6650 const reg_entry
*reg
; /* Last register reference found. */
6651 char *disp
; /* Displacement string being built. */
6652 char *next_operand
; /* Resume point when splitting operands. */
6655 static struct intel_parser_s intel_parser
;
6657 /* Token structure for parsing intel syntax. */
6660 int code
; /* Token code. */
6661 const reg_entry
*reg
; /* Register entry for register tokens. */
6662 char *str
; /* String representation. */
6665 static struct intel_token cur_token
, prev_token
;
6667 /* Token codes for the intel parser. Since T_SHORT is already used
6668 by COFF, undefine it first to prevent a warning. */
6687 /* Prototypes for intel parser functions. */
6688 static int intel_match_token (int);
6689 static void intel_putback_token (void);
6690 static void intel_get_token (void);
6691 static int intel_expr (void);
6692 static int intel_e04 (void);
6693 static int intel_e05 (void);
6694 static int intel_e06 (void);
6695 static int intel_e09 (void);
6696 static int intel_e10 (void);
6697 static int intel_e11 (void);
6700 i386_intel_operand (char *operand_string
, int got_a_float
)
6705 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6706 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6710 /* Initialize token holders. */
6711 cur_token
.code
= prev_token
.code
= T_NIL
;
6712 cur_token
.reg
= prev_token
.reg
= NULL
;
6713 cur_token
.str
= prev_token
.str
= NULL
;
6715 /* Initialize parser structure. */
6716 intel_parser
.got_a_float
= got_a_float
;
6717 intel_parser
.op_modifier
= 0;
6718 intel_parser
.is_mem
= 0;
6719 intel_parser
.in_offset
= 0;
6720 intel_parser
.in_bracket
= 0;
6721 intel_parser
.reg
= NULL
;
6722 intel_parser
.disp
[0] = '\0';
6723 intel_parser
.next_operand
= NULL
;
6725 /* Read the first token and start the parser. */
6727 ret
= intel_expr ();
6732 if (cur_token
.code
!= T_NIL
)
6734 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6735 current_templates
->start
->name
, cur_token
.str
);
6738 /* If we found a memory reference, hand it over to i386_displacement
6739 to fill in the rest of the operand fields. */
6740 else if (intel_parser
.is_mem
)
6742 if ((i
.mem_operands
== 1
6743 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6744 || i
.mem_operands
== 2)
6746 as_bad (_("too many memory references for '%s'"),
6747 current_templates
->start
->name
);
6752 char *s
= intel_parser
.disp
;
6755 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6756 /* See the comments in intel_bracket_expr. */
6757 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6759 /* Add the displacement expression. */
6761 ret
= i386_displacement (s
, s
+ strlen (s
));
6764 /* Swap base and index in 16-bit memory operands like
6765 [si+bx]. Since i386_index_check is also used in AT&T
6766 mode we have to do that here. */
6769 && (i
.base_reg
->reg_type
& Reg16
)
6770 && (i
.index_reg
->reg_type
& Reg16
)
6771 && i
.base_reg
->reg_num
>= 6
6772 && i
.index_reg
->reg_num
< 6)
6774 const reg_entry
*base
= i
.index_reg
;
6776 i
.index_reg
= i
.base_reg
;
6779 ret
= i386_index_check (operand_string
);
6784 /* Constant and OFFSET expressions are handled by i386_immediate. */
6785 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6786 || intel_parser
.reg
== NULL
)
6787 ret
= i386_immediate (intel_parser
.disp
);
6789 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6791 if (!ret
|| !intel_parser
.next_operand
)
6793 intel_parser
.op_string
= intel_parser
.next_operand
;
6794 this_operand
= i
.operands
++;
6798 free (intel_parser
.disp
);
6803 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6807 expr' cmpOp e04 expr'
6812 /* XXX Implement the comparison operators. */
6813 return intel_e04 ();
6830 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6831 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6833 if (cur_token
.code
== '+')
6835 else if (cur_token
.code
== '-')
6836 nregs
= NUM_ADDRESS_REGS
;
6840 strcat (intel_parser
.disp
, cur_token
.str
);
6841 intel_match_token (cur_token
.code
);
6852 int nregs
= ~NUM_ADDRESS_REGS
;
6859 if (cur_token
.code
== '&'
6860 || cur_token
.code
== '|'
6861 || cur_token
.code
== '^')
6865 str
[0] = cur_token
.code
;
6867 strcat (intel_parser
.disp
, str
);
6872 intel_match_token (cur_token
.code
);
6877 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6878 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6889 int nregs
= ~NUM_ADDRESS_REGS
;
6896 if (cur_token
.code
== '*'
6897 || cur_token
.code
== '/'
6898 || cur_token
.code
== '%')
6902 str
[0] = cur_token
.code
;
6904 strcat (intel_parser
.disp
, str
);
6906 else if (cur_token
.code
== T_SHL
)
6907 strcat (intel_parser
.disp
, "<<");
6908 else if (cur_token
.code
== T_SHR
)
6909 strcat (intel_parser
.disp
, ">>");
6913 intel_match_token (cur_token
.code
);
6918 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6919 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6937 int nregs
= ~NUM_ADDRESS_REGS
;
6942 /* Don't consume constants here. */
6943 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6945 /* Need to look one token ahead - if the next token
6946 is a constant, the current token is its sign. */
6949 intel_match_token (cur_token
.code
);
6950 next_code
= cur_token
.code
;
6951 intel_putback_token ();
6952 if (next_code
== T_CONST
)
6956 /* e09 OFFSET e09 */
6957 if (cur_token
.code
== T_OFFSET
)
6960 ++intel_parser
.in_offset
;
6964 else if (cur_token
.code
== T_SHORT
)
6965 intel_parser
.op_modifier
|= 1 << T_SHORT
;
6968 else if (cur_token
.code
== '+')
6969 strcat (intel_parser
.disp
, "+");
6974 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
6980 str
[0] = cur_token
.code
;
6982 strcat (intel_parser
.disp
, str
);
6989 intel_match_token (cur_token
.code
);
6997 /* e09' PTR e10 e09' */
6998 if (cur_token
.code
== T_PTR
)
7002 if (prev_token
.code
== T_BYTE
)
7003 suffix
= BYTE_MNEM_SUFFIX
;
7005 else if (prev_token
.code
== T_WORD
)
7007 if (current_templates
->start
->name
[0] == 'l'
7008 && current_templates
->start
->name
[2] == 's'
7009 && current_templates
->start
->name
[3] == 0)
7010 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7011 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
7012 suffix
= SHORT_MNEM_SUFFIX
;
7014 suffix
= WORD_MNEM_SUFFIX
;
7017 else if (prev_token
.code
== T_DWORD
)
7019 if (current_templates
->start
->name
[0] == 'l'
7020 && current_templates
->start
->name
[2] == 's'
7021 && current_templates
->start
->name
[3] == 0)
7022 suffix
= WORD_MNEM_SUFFIX
;
7023 else if (flag_code
== CODE_16BIT
7024 && (current_templates
->start
->opcode_modifier
7025 & (Jump
| JumpDword
)))
7026 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7027 else if (intel_parser
.got_a_float
== 1) /* "f..." */
7028 suffix
= SHORT_MNEM_SUFFIX
;
7030 suffix
= LONG_MNEM_SUFFIX
;
7033 else if (prev_token
.code
== T_FWORD
)
7035 if (current_templates
->start
->name
[0] == 'l'
7036 && current_templates
->start
->name
[2] == 's'
7037 && current_templates
->start
->name
[3] == 0)
7038 suffix
= LONG_MNEM_SUFFIX
;
7039 else if (!intel_parser
.got_a_float
)
7041 if (flag_code
== CODE_16BIT
)
7042 add_prefix (DATA_PREFIX_OPCODE
);
7043 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7046 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7049 else if (prev_token
.code
== T_QWORD
)
7051 if (intel_parser
.got_a_float
== 1) /* "f..." */
7052 suffix
= LONG_MNEM_SUFFIX
;
7054 suffix
= QWORD_MNEM_SUFFIX
;
7057 else if (prev_token
.code
== T_TBYTE
)
7059 if (intel_parser
.got_a_float
== 1)
7060 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7062 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7065 else if (prev_token
.code
== T_XMMWORD
)
7067 /* XXX ignored for now, but accepted since gcc uses it */
7073 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7077 /* Operands for jump/call using 'ptr' notation denote absolute
7079 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7080 i
.types
[this_operand
] |= JumpAbsolute
;
7082 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7086 else if (i
.suffix
!= suffix
)
7088 as_bad (_("Conflicting operand modifiers"));
7094 /* e09' : e10 e09' */
7095 else if (cur_token
.code
== ':')
7097 if (prev_token
.code
!= T_REG
)
7099 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7100 segment/group identifier (which we don't have), using comma
7101 as the operand separator there is even less consistent, since
7102 there all branches only have a single operand. */
7103 if (this_operand
!= 0
7104 || intel_parser
.in_offset
7105 || intel_parser
.in_bracket
7106 || (!(current_templates
->start
->opcode_modifier
7107 & (Jump
|JumpDword
|JumpInterSegment
))
7108 && !(current_templates
->start
->operand_types
[0]
7110 return intel_match_token (T_NIL
);
7111 /* Remember the start of the 2nd operand and terminate 1st
7113 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7114 another expression), but it gets at least the simplest case
7115 (a plain number or symbol on the left side) right. */
7116 intel_parser
.next_operand
= intel_parser
.op_string
;
7117 *--intel_parser
.op_string
= '\0';
7118 return intel_match_token (':');
7126 intel_match_token (cur_token
.code
);
7132 --intel_parser
.in_offset
;
7135 if (NUM_ADDRESS_REGS
> nregs
)
7137 as_bad (_("Invalid operand to `OFFSET'"));
7140 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7143 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7144 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7149 intel_bracket_expr (void)
7151 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7152 const char *start
= intel_parser
.op_string
;
7155 if (i
.op
[this_operand
].regs
)
7156 return intel_match_token (T_NIL
);
7158 intel_match_token ('[');
7160 /* Mark as a memory operand only if it's not already known to be an
7161 offset expression. If it's an offset expression, we need to keep
7163 if (!intel_parser
.in_offset
)
7165 ++intel_parser
.in_bracket
;
7167 /* Operands for jump/call inside brackets denote absolute addresses. */
7168 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7169 i
.types
[this_operand
] |= JumpAbsolute
;
7171 /* Unfortunately gas always diverged from MASM in a respect that can't
7172 be easily fixed without risking to break code sequences likely to be
7173 encountered (the testsuite even check for this): MASM doesn't consider
7174 an expression inside brackets unconditionally as a memory reference.
7175 When that is e.g. a constant, an offset expression, or the sum of the
7176 two, this is still taken as a constant load. gas, however, always
7177 treated these as memory references. As a compromise, we'll try to make
7178 offset expressions inside brackets work the MASM way (since that's
7179 less likely to be found in real world code), but make constants alone
7180 continue to work the traditional gas way. In either case, issue a
7182 intel_parser
.op_modifier
&= ~was_offset
;
7185 strcat (intel_parser
.disp
, "[");
7187 /* Add a '+' to the displacement string if necessary. */
7188 if (*intel_parser
.disp
!= '\0'
7189 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7190 strcat (intel_parser
.disp
, "+");
7193 && (len
= intel_parser
.op_string
- start
- 1,
7194 intel_match_token (']')))
7196 /* Preserve brackets when the operand is an offset expression. */
7197 if (intel_parser
.in_offset
)
7198 strcat (intel_parser
.disp
, "]");
7201 --intel_parser
.in_bracket
;
7202 if (i
.base_reg
|| i
.index_reg
)
7203 intel_parser
.is_mem
= 1;
7204 if (!intel_parser
.is_mem
)
7206 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7207 /* Defer the warning until all of the operand was parsed. */
7208 intel_parser
.is_mem
= -1;
7209 else if (!quiet_warnings
)
7210 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7211 len
, start
, len
, start
);
7214 intel_parser
.op_modifier
|= was_offset
;
7231 while (cur_token
.code
== '[')
7233 if (!intel_bracket_expr ())
7258 switch (cur_token
.code
)
7262 intel_match_token ('(');
7263 strcat (intel_parser
.disp
, "(");
7265 if (intel_expr () && intel_match_token (')'))
7267 strcat (intel_parser
.disp
, ")");
7274 return intel_bracket_expr ();
7279 strcat (intel_parser
.disp
, cur_token
.str
);
7280 intel_match_token (cur_token
.code
);
7282 /* Mark as a memory operand only if it's not already known to be an
7283 offset expression. */
7284 if (!intel_parser
.in_offset
)
7285 intel_parser
.is_mem
= 1;
7292 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7294 intel_match_token (T_REG
);
7296 /* Check for segment change. */
7297 if (cur_token
.code
== ':')
7299 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7301 as_bad (_("`%s' is not a valid segment register"),
7305 else if (i
.seg
[i
.mem_operands
])
7306 as_warn (_("Extra segment override ignored"));
7309 if (!intel_parser
.in_offset
)
7310 intel_parser
.is_mem
= 1;
7311 switch (reg
->reg_num
)
7314 i
.seg
[i
.mem_operands
] = &es
;
7317 i
.seg
[i
.mem_operands
] = &cs
;
7320 i
.seg
[i
.mem_operands
] = &ss
;
7323 i
.seg
[i
.mem_operands
] = &ds
;
7326 i
.seg
[i
.mem_operands
] = &fs
;
7329 i
.seg
[i
.mem_operands
] = &gs
;
7335 /* Not a segment register. Check for register scaling. */
7336 else if (cur_token
.code
== '*')
7338 if (!intel_parser
.in_bracket
)
7340 as_bad (_("Register scaling only allowed in memory operands"));
7344 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7345 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7346 else if (i
.index_reg
)
7347 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7349 /* What follows must be a valid scale. */
7350 intel_match_token ('*');
7352 i
.types
[this_operand
] |= BaseIndex
;
7354 /* Set the scale after setting the register (otherwise,
7355 i386_scale will complain) */
7356 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7358 char *str
, sign
= cur_token
.code
;
7359 intel_match_token (cur_token
.code
);
7360 if (cur_token
.code
!= T_CONST
)
7362 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7366 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7367 strcpy (str
+ 1, cur_token
.str
);
7369 if (!i386_scale (str
))
7373 else if (!i386_scale (cur_token
.str
))
7375 intel_match_token (cur_token
.code
);
7378 /* No scaling. If this is a memory operand, the register is either a
7379 base register (first occurrence) or an index register (second
7381 else if (intel_parser
.in_bracket
)
7386 else if (!i
.index_reg
)
7390 as_bad (_("Too many register references in memory operand"));
7394 i
.types
[this_operand
] |= BaseIndex
;
7397 /* It's neither base nor index. */
7398 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7400 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7401 i
.op
[this_operand
].regs
= reg
;
7406 as_bad (_("Invalid use of register"));
7410 /* Since registers are not part of the displacement string (except
7411 when we're parsing offset operands), we may need to remove any
7412 preceding '+' from the displacement string. */
7413 if (*intel_parser
.disp
!= '\0'
7414 && !intel_parser
.in_offset
)
7416 char *s
= intel_parser
.disp
;
7417 s
+= strlen (s
) - 1;
7440 intel_match_token (cur_token
.code
);
7442 if (cur_token
.code
== T_PTR
)
7445 /* It must have been an identifier. */
7446 intel_putback_token ();
7447 cur_token
.code
= T_ID
;
7453 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7457 /* The identifier represents a memory reference only if it's not
7458 preceded by an offset modifier and if it's not an equate. */
7459 symbolP
= symbol_find(cur_token
.str
);
7460 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7461 intel_parser
.is_mem
= 1;
7469 char *save_str
, sign
= 0;
7471 /* Allow constants that start with `+' or `-'. */
7472 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7474 sign
= cur_token
.code
;
7475 intel_match_token (cur_token
.code
);
7476 if (cur_token
.code
!= T_CONST
)
7478 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7484 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7485 strcpy (save_str
+ !!sign
, cur_token
.str
);
7489 /* Get the next token to check for register scaling. */
7490 intel_match_token (cur_token
.code
);
7492 /* Check if this constant is a scaling factor for an
7494 if (cur_token
.code
== '*')
7496 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7498 const reg_entry
*reg
= cur_token
.reg
;
7500 if (!intel_parser
.in_bracket
)
7502 as_bad (_("Register scaling only allowed "
7503 "in memory operands"));
7507 /* Disallow things like [1*si].
7508 sp and esp are invalid as index. */
7509 if (reg
->reg_type
& Reg16
)
7510 reg
= i386_regtab
+ REGNAM_AX
+ 4;
7511 else if (i
.index_reg
)
7512 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
7514 /* The constant is followed by `* reg', so it must be
7517 i
.types
[this_operand
] |= BaseIndex
;
7519 /* Set the scale after setting the register (otherwise,
7520 i386_scale will complain) */
7521 if (!i386_scale (save_str
))
7523 intel_match_token (T_REG
);
7525 /* Since registers are not part of the displacement
7526 string, we may need to remove any preceding '+' from
7527 the displacement string. */
7528 if (*intel_parser
.disp
!= '\0')
7530 char *s
= intel_parser
.disp
;
7531 s
+= strlen (s
) - 1;
7541 /* The constant was not used for register scaling. Since we have
7542 already consumed the token following `*' we now need to put it
7543 back in the stream. */
7544 intel_putback_token ();
7547 /* Add the constant to the displacement string. */
7548 strcat (intel_parser
.disp
, save_str
);
7555 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7559 /* Match the given token against cur_token. If they match, read the next
7560 token from the operand string. */
7562 intel_match_token (int code
)
7564 if (cur_token
.code
== code
)
7571 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7576 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7578 intel_get_token (void)
7581 const reg_entry
*reg
;
7582 struct intel_token new_token
;
7584 new_token
.code
= T_NIL
;
7585 new_token
.reg
= NULL
;
7586 new_token
.str
= NULL
;
7588 /* Free the memory allocated to the previous token and move
7589 cur_token to prev_token. */
7591 free (prev_token
.str
);
7593 prev_token
= cur_token
;
7595 /* Skip whitespace. */
7596 while (is_space_char (*intel_parser
.op_string
))
7597 intel_parser
.op_string
++;
7599 /* Return an empty token if we find nothing else on the line. */
7600 if (*intel_parser
.op_string
== '\0')
7602 cur_token
= new_token
;
7606 /* The new token cannot be larger than the remainder of the operand
7608 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7609 new_token
.str
[0] = '\0';
7611 if (strchr ("0123456789", *intel_parser
.op_string
))
7613 char *p
= new_token
.str
;
7614 char *q
= intel_parser
.op_string
;
7615 new_token
.code
= T_CONST
;
7617 /* Allow any kind of identifier char to encompass floating point and
7618 hexadecimal numbers. */
7619 while (is_identifier_char (*q
))
7623 /* Recognize special symbol names [0-9][bf]. */
7624 if (strlen (intel_parser
.op_string
) == 2
7625 && (intel_parser
.op_string
[1] == 'b'
7626 || intel_parser
.op_string
[1] == 'f'))
7627 new_token
.code
= T_ID
;
7630 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7632 size_t len
= end_op
- intel_parser
.op_string
;
7634 new_token
.code
= T_REG
;
7635 new_token
.reg
= reg
;
7637 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7638 new_token
.str
[len
] = '\0';
7641 else if (is_identifier_char (*intel_parser
.op_string
))
7643 char *p
= new_token
.str
;
7644 char *q
= intel_parser
.op_string
;
7646 /* A '.' or '$' followed by an identifier char is an identifier.
7647 Otherwise, it's operator '.' followed by an expression. */
7648 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7650 new_token
.code
= '.';
7651 new_token
.str
[0] = '.';
7652 new_token
.str
[1] = '\0';
7656 while (is_identifier_char (*q
) || *q
== '@')
7660 if (strcasecmp (new_token
.str
, "NOT") == 0)
7661 new_token
.code
= '~';
7663 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7664 new_token
.code
= '%';
7666 else if (strcasecmp (new_token
.str
, "AND") == 0)
7667 new_token
.code
= '&';
7669 else if (strcasecmp (new_token
.str
, "OR") == 0)
7670 new_token
.code
= '|';
7672 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7673 new_token
.code
= '^';
7675 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7676 new_token
.code
= T_SHL
;
7678 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7679 new_token
.code
= T_SHR
;
7681 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7682 new_token
.code
= T_BYTE
;
7684 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7685 new_token
.code
= T_WORD
;
7687 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7688 new_token
.code
= T_DWORD
;
7690 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7691 new_token
.code
= T_FWORD
;
7693 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7694 new_token
.code
= T_QWORD
;
7696 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7697 /* XXX remove (gcc still uses it) */
7698 || strcasecmp (new_token
.str
, "XWORD") == 0)
7699 new_token
.code
= T_TBYTE
;
7701 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7702 || strcasecmp (new_token
.str
, "OWORD") == 0)
7703 new_token
.code
= T_XMMWORD
;
7705 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7706 new_token
.code
= T_PTR
;
7708 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7709 new_token
.code
= T_SHORT
;
7711 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7713 new_token
.code
= T_OFFSET
;
7715 /* ??? This is not mentioned in the MASM grammar but gcc
7716 makes use of it with -mintel-syntax. OFFSET may be
7717 followed by FLAT: */
7718 if (strncasecmp (q
, " FLAT:", 6) == 0)
7719 strcat (new_token
.str
, " FLAT:");
7722 /* ??? This is not mentioned in the MASM grammar. */
7723 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7725 new_token
.code
= T_OFFSET
;
7727 strcat (new_token
.str
, ":");
7729 as_bad (_("`:' expected"));
7733 new_token
.code
= T_ID
;
7737 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7739 new_token
.code
= *intel_parser
.op_string
;
7740 new_token
.str
[0] = *intel_parser
.op_string
;
7741 new_token
.str
[1] = '\0';
7744 else if (strchr ("<>", *intel_parser
.op_string
)
7745 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7747 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7748 new_token
.str
[0] = *intel_parser
.op_string
;
7749 new_token
.str
[1] = *intel_parser
.op_string
;
7750 new_token
.str
[2] = '\0';
7754 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7756 intel_parser
.op_string
+= strlen (new_token
.str
);
7757 cur_token
= new_token
;
7760 /* Put cur_token back into the token stream and make cur_token point to
7763 intel_putback_token (void)
7765 if (cur_token
.code
!= T_NIL
)
7767 intel_parser
.op_string
-= strlen (cur_token
.str
);
7768 free (cur_token
.str
);
7770 cur_token
= prev_token
;
7772 /* Forget prev_token. */
7773 prev_token
.code
= T_NIL
;
7774 prev_token
.reg
= NULL
;
7775 prev_token
.str
= NULL
;
7779 tc_x86_regname_to_dw2regnum (char *regname
)
7781 unsigned int regnum
;
7782 unsigned int regnames_count
;
7783 static const char *const regnames_32
[] =
7785 "eax", "ecx", "edx", "ebx",
7786 "esp", "ebp", "esi", "edi",
7787 "eip", "eflags", NULL
,
7788 "st0", "st1", "st2", "st3",
7789 "st4", "st5", "st6", "st7",
7791 "xmm0", "xmm1", "xmm2", "xmm3",
7792 "xmm4", "xmm5", "xmm6", "xmm7",
7793 "mm0", "mm1", "mm2", "mm3",
7794 "mm4", "mm5", "mm6", "mm7",
7795 "fcw", "fsw", "mxcsr",
7796 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7799 static const char *const regnames_64
[] =
7801 "rax", "rdx", "rcx", "rbx",
7802 "rsi", "rdi", "rbp", "rsp",
7803 "r8", "r9", "r10", "r11",
7804 "r12", "r13", "r14", "r15",
7806 "xmm0", "xmm1", "xmm2", "xmm3",
7807 "xmm4", "xmm5", "xmm6", "xmm7",
7808 "xmm8", "xmm9", "xmm10", "xmm11",
7809 "xmm12", "xmm13", "xmm14", "xmm15",
7810 "st0", "st1", "st2", "st3",
7811 "st4", "st5", "st6", "st7",
7812 "mm0", "mm1", "mm2", "mm3",
7813 "mm4", "mm5", "mm6", "mm7",
7815 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7816 "fs.base", "gs.base", NULL
, NULL
,
7818 "mxcsr", "fcw", "fsw"
7820 const char *const *regnames
;
7822 if (flag_code
== CODE_64BIT
)
7824 regnames
= regnames_64
;
7825 regnames_count
= ARRAY_SIZE (regnames_64
);
7829 regnames
= regnames_32
;
7830 regnames_count
= ARRAY_SIZE (regnames_32
);
7833 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7834 if (regnames
[regnum
] != NULL
7835 && strcmp (regname
, regnames
[regnum
]) == 0)
7842 tc_x86_frame_initial_instructions (void)
7844 static unsigned int sp_regno
;
7847 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7850 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7851 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7855 i386_elf_section_type (const char *str
, size_t len
)
7857 if (flag_code
== CODE_64BIT
7858 && len
== sizeof ("unwind") - 1
7859 && strncmp (str
, "unwind", 6) == 0)
7860 return SHT_X86_64_UNWIND
;
7867 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7871 expr
.X_op
= O_secrel
;
7872 expr
.X_add_symbol
= symbol
;
7873 expr
.X_add_number
= 0;
7874 emit_expr (&expr
, size
);
7878 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7879 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7882 x86_64_section_letter (int letter
, char **ptr_msg
)
7884 if (flag_code
== CODE_64BIT
)
7887 return SHF_X86_64_LARGE
;
7889 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7892 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7897 x86_64_section_word (char *str
, size_t len
)
7899 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7900 return SHF_X86_64_LARGE
;
7906 handle_large_common (int small ATTRIBUTE_UNUSED
)
7908 if (flag_code
!= CODE_64BIT
)
7910 s_comm_internal (0, elf_common_parse
);
7911 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7915 static segT lbss_section
;
7916 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7917 asection
*saved_bss_section
= bss_section
;
7919 if (lbss_section
== NULL
)
7921 flagword applicable
;
7923 subsegT subseg
= now_subseg
;
7925 /* The .lbss section is for local .largecomm symbols. */
7926 lbss_section
= subseg_new (".lbss", 0);
7927 applicable
= bfd_applicable_section_flags (stdoutput
);
7928 bfd_set_section_flags (stdoutput
, lbss_section
,
7929 applicable
& SEC_ALLOC
);
7930 seg_info (lbss_section
)->bss
= 1;
7932 subseg_set (seg
, subseg
);
7935 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7936 bss_section
= lbss_section
;
7938 s_comm_internal (0, elf_common_parse
);
7940 elf_com_section_ptr
= saved_com_section_ptr
;
7941 bss_section
= saved_bss_section
;
7944 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */